1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "dwarf2dbg.h"
49 #include "opcode/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
64 SPECIAL_SECTION_BSS
= 0,
66 SPECIAL_SECTION_SDATA
,
67 SPECIAL_SECTION_RODATA
,
68 SPECIAL_SECTION_COMMENT
,
69 SPECIAL_SECTION_UNWIND
,
70 SPECIAL_SECTION_UNWIND_INFO
83 FUNC_LT_FPTR_RELATIVE
,
89 REG_FR
= (REG_GR
+ 128),
90 REG_AR
= (REG_FR
+ 128),
91 REG_CR
= (REG_AR
+ 128),
92 REG_P
= (REG_CR
+ 128),
93 REG_BR
= (REG_P
+ 64),
94 REG_IP
= (REG_BR
+ 8),
101 /* The following are pseudo-registers for use by gas only. */
113 /* The following pseudo-registers are used for unwind directives only: */
121 DYNREG_GR
= 0, /* dynamic general purpose register */
122 DYNREG_FR
, /* dynamic floating point register */
123 DYNREG_PR
, /* dynamic predicate register */
127 enum operand_match_result
130 OPERAND_OUT_OF_RANGE
,
134 /* On the ia64, we can't know the address of a text label until the
135 instructions are packed into a bundle. To handle this, we keep
136 track of the list of labels that appear in front of each
140 struct label_fix
*next
;
144 extern int target_big_endian
;
146 /* Characters which always start a comment. */
147 const char comment_chars
[] = "";
149 /* Characters which start a comment at the beginning of a line. */
150 const char line_comment_chars
[] = "#";
152 /* Characters which may be used to separate multiple commands on a
154 const char line_separator_chars
[] = ";";
156 /* Characters which are used to indicate an exponent in a floating
158 const char EXP_CHARS
[] = "eE";
160 /* Characters which mean that a number is a floating point constant,
162 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
164 /* ia64-specific option processing: */
166 const char *md_shortopts
= "m:N:x::";
168 struct option md_longopts
[] =
170 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
171 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
172 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
173 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
176 size_t md_longopts_size
= sizeof (md_longopts
);
180 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
181 struct hash_control
*reg_hash
; /* register name hash table */
182 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
183 struct hash_control
*const_hash
; /* constant hash table */
184 struct hash_control
*entry_hash
; /* code entry hint hash table */
186 symbolS
*regsym
[REG_NUM
];
188 /* If X_op is != O_absent, the registername for the instruction's
189 qualifying predicate. If NULL, p0 is assumed for instructions
190 that are predicatable. */
197 explicit_mode
: 1, /* which mode we're in */
198 default_explicit_mode
: 1, /* which mode is the default */
199 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
202 /* Each bundle consists of up to three instructions. We keep
203 track of four most recent instructions so we can correctly set
204 the end_of_insn_group for the last instruction in a bundle. */
206 int num_slots_in_use
;
210 end_of_insn_group
: 1,
211 manual_bundling_on
: 1,
212 manual_bundling_off
: 1;
213 signed char user_template
; /* user-selected template, if any */
214 unsigned char qp_regno
; /* qualifying predicate */
215 /* This duplicates a good fraction of "struct fix" but we
216 can't use a "struct fix" instead since we can't call
217 fix_new_exp() until we know the address of the instruction. */
221 bfd_reloc_code_real_type code
;
222 enum ia64_opnd opnd
; /* type of operand in need of fix */
223 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
224 expressionS expr
; /* the value to be inserted */
226 fixup
[2]; /* at most two fixups per insn */
227 struct ia64_opcode
*idesc
;
228 struct label_fix
*label_fixups
;
229 struct label_fix
*tag_fixups
;
230 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
233 unsigned int src_line
;
234 struct dwarf2_line_info debug_line
;
242 struct dynreg
*next
; /* next dynamic register */
244 unsigned short base
; /* the base register number */
245 unsigned short num_regs
; /* # of registers in this set */
247 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
249 flagword flags
; /* ELF-header flags */
252 unsigned hint
:1; /* is this hint currently valid? */
253 bfd_vma offset
; /* mem.offset offset */
254 bfd_vma base
; /* mem.offset base */
257 int path
; /* number of alt. entry points seen */
258 const char **entry_labels
; /* labels of all alternate paths in
259 the current DV-checking block. */
260 int maxpaths
; /* size currently allocated for
262 /* Support for hardware errata workarounds. */
264 /* Record data about the last three insn groups. */
267 /* B-step workaround.
268 For each predicate register, this is set if the corresponding insn
269 group conditionally sets this register with one of the affected
272 /* B-step workaround.
273 For each general register, this is set if the corresponding insn
274 a) is conditional one one of the predicate registers for which
275 P_REG_SET is 1 in the corresponding entry of the previous group,
276 b) sets this general register with one of the affected
278 int g_reg_set_conditionally
[128];
284 /* application registers: */
290 #define AR_BSPSTORE 18
305 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
306 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
307 {"ar.rsc", 16}, {"ar.bsp", 17},
308 {"ar.bspstore", 18}, {"ar.rnat", 19},
309 {"ar.fcr", 21}, {"ar.eflag", 24},
310 {"ar.csd", 25}, {"ar.ssd", 26},
311 {"ar.cflg", 27}, {"ar.fsr", 28},
312 {"ar.fir", 29}, {"ar.fdr", 30},
313 {"ar.ccv", 32}, {"ar.unat", 36},
314 {"ar.fpsr", 40}, {"ar.itc", 44},
315 {"ar.pfs", 64}, {"ar.lc", 65},
336 /* control registers: */
378 static const struct const_desc
385 /* PSR constant masks: */
388 {"psr.be", ((valueT
) 1) << 1},
389 {"psr.up", ((valueT
) 1) << 2},
390 {"psr.ac", ((valueT
) 1) << 3},
391 {"psr.mfl", ((valueT
) 1) << 4},
392 {"psr.mfh", ((valueT
) 1) << 5},
394 {"psr.ic", ((valueT
) 1) << 13},
395 {"psr.i", ((valueT
) 1) << 14},
396 {"psr.pk", ((valueT
) 1) << 15},
398 {"psr.dt", ((valueT
) 1) << 17},
399 {"psr.dfl", ((valueT
) 1) << 18},
400 {"psr.dfh", ((valueT
) 1) << 19},
401 {"psr.sp", ((valueT
) 1) << 20},
402 {"psr.pp", ((valueT
) 1) << 21},
403 {"psr.di", ((valueT
) 1) << 22},
404 {"psr.si", ((valueT
) 1) << 23},
405 {"psr.db", ((valueT
) 1) << 24},
406 {"psr.lp", ((valueT
) 1) << 25},
407 {"psr.tb", ((valueT
) 1) << 26},
408 {"psr.rt", ((valueT
) 1) << 27},
409 /* 28-31: reserved */
410 /* 32-33: cpl (current privilege level) */
411 {"psr.is", ((valueT
) 1) << 34},
412 {"psr.mc", ((valueT
) 1) << 35},
413 {"psr.it", ((valueT
) 1) << 36},
414 {"psr.id", ((valueT
) 1) << 37},
415 {"psr.da", ((valueT
) 1) << 38},
416 {"psr.dd", ((valueT
) 1) << 39},
417 {"psr.ss", ((valueT
) 1) << 40},
418 /* 41-42: ri (restart instruction) */
419 {"psr.ed", ((valueT
) 1) << 43},
420 {"psr.bn", ((valueT
) 1) << 44},
423 /* indirect register-sets/memory: */
432 { "CPUID", IND_CPUID
},
433 { "cpuid", IND_CPUID
},
445 /* Pseudo functions used to indicate relocation types (these functions
446 start with an at sign (@). */
468 /* reloc pseudo functions (these must come first!): */
469 { "fptr", PSEUDO_FUNC_RELOC
, { 0 } },
470 { "gprel", PSEUDO_FUNC_RELOC
, { 0 } },
471 { "ltoff", PSEUDO_FUNC_RELOC
, { 0 } },
472 { "pcrel", PSEUDO_FUNC_RELOC
, { 0 } },
473 { "pltoff", PSEUDO_FUNC_RELOC
, { 0 } },
474 { "secrel", PSEUDO_FUNC_RELOC
, { 0 } },
475 { "segrel", PSEUDO_FUNC_RELOC
, { 0 } },
476 { "ltv", PSEUDO_FUNC_RELOC
, { 0 } },
477 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
479 /* mbtype4 constants: */
480 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
481 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
482 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
483 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
484 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
486 /* fclass constants: */
487 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
488 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
489 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
490 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
491 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
492 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
493 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
494 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
495 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
497 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
499 /* unwind-related constants: */
500 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
501 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
502 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
504 /* unwind-related registers: */
505 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
508 /* 41-bit nop opcodes (one per unit): */
509 static const bfd_vma nop
[IA64_NUM_UNITS
] =
511 0x0000000000LL
, /* NIL => break 0 */
512 0x0008000000LL
, /* I-unit nop */
513 0x0008000000LL
, /* M-unit nop */
514 0x4000000000LL
, /* B-unit nop */
515 0x0008000000LL
, /* F-unit nop */
516 0x0008000000LL
, /* L-"unit" nop */
517 0x0008000000LL
, /* X-unit nop */
520 /* Can't be `const' as it's passed to input routines (which have the
521 habit of setting temporary sentinels. */
522 static char special_section_name
[][20] =
524 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
525 {".IA_64.unwind"}, {".IA_64.unwind_info"}
528 /* The best template for a particular sequence of up to three
530 #define N IA64_NUM_TYPES
531 static unsigned char best_template
[N
][N
][N
];
534 /* Resource dependencies currently in effect */
536 int depind
; /* dependency index */
537 const struct ia64_dependency
*dependency
; /* actual dependency */
538 unsigned specific
:1, /* is this a specific bit/regno? */
539 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
540 int index
; /* specific regno/bit within dependency */
541 int note
; /* optional qualifying note (0 if none) */
545 int insn_srlz
; /* current insn serialization state */
546 int data_srlz
; /* current data serialization state */
547 int qp_regno
; /* qualifying predicate for this usage */
548 char *file
; /* what file marked this dependency */
549 unsigned int line
; /* what line marked this dependency */
550 struct mem_offset mem_offset
; /* optional memory offset hint */
551 enum { CMP_NONE
, CMP_OR
, CMP_AND
} cmp_type
; /* OR or AND compare? */
552 int path
; /* corresponding code entry index */
554 static int regdepslen
= 0;
555 static int regdepstotlen
= 0;
556 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
557 static const char *dv_sem
[] = { "none", "implied", "impliedf",
558 "data", "instr", "specific", "stop", "other" };
559 static const char *dv_cmp_type
[] = { "none", "OR", "AND" };
561 /* Current state of PR mutexation */
562 static struct qpmutex
{
565 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
566 static int qp_mutexeslen
= 0;
567 static int qp_mutexestotlen
= 0;
568 static valueT qp_safe_across_calls
= 0;
570 /* Current state of PR implications */
571 static struct qp_imply
{
574 unsigned p2_branched
:1;
576 } *qp_implies
= NULL
;
577 static int qp_implieslen
= 0;
578 static int qp_impliestotlen
= 0;
580 /* Keep track of static GR values so that indirect register usage can
581 sometimes be tracked. */
586 } gr_values
[128] = {{ 1, 0, 0 }};
588 /* These are the routines required to output the various types of
591 /* A slot_number is a frag address plus the slot index (0-2). We use the
592 frag address here so that if there is a section switch in the middle of
593 a function, then instructions emitted to a different section are not
594 counted. Since there may be more than one frag for a function, this
595 means we also need to keep track of which frag this address belongs to
596 so we can compute inter-frag distances. This also nicely solves the
597 problem with nops emitted for align directives, which can't easily be
598 counted, but can easily be derived from frag sizes. */
600 typedef struct unw_rec_list
{
602 unsigned long slot_number
;
604 struct unw_rec_list
*next
;
607 #define SLOT_NUM_NOT_SET (unsigned)-1
611 unsigned long next_slot_number
;
612 fragS
*next_slot_frag
;
614 /* Maintain a list of unwind entries for the current function. */
618 /* Any unwind entires that should be attached to the current slot
619 that an insn is being constructed for. */
620 unw_rec_list
*current_entry
;
622 /* These are used to create the unwind table entry for this function. */
625 symbolS
*info
; /* pointer to unwind info */
626 symbolS
*personality_routine
;
628 subsegT saved_text_subseg
;
629 unsigned int force_unwind_entry
: 1; /* force generation of unwind entry? */
631 /* TRUE if processing unwind directives in a prologue region. */
634 unsigned int prologue_count
; /* number of .prologues seen so far */
637 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
639 /* Forward delarations: */
640 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
641 static void set_section
PARAMS ((char *name
));
642 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
643 unsigned int, unsigned int));
644 static void dot_radix
PARAMS ((int));
645 static void dot_special_section
PARAMS ((int));
646 static void dot_proc
PARAMS ((int));
647 static void dot_fframe
PARAMS ((int));
648 static void dot_vframe
PARAMS ((int));
649 static void dot_vframesp
PARAMS ((int));
650 static void dot_vframepsp
PARAMS ((int));
651 static void dot_save
PARAMS ((int));
652 static void dot_restore
PARAMS ((int));
653 static void dot_restorereg
PARAMS ((int));
654 static void dot_restorereg_p
PARAMS ((int));
655 static void dot_handlerdata
PARAMS ((int));
656 static void dot_unwentry
PARAMS ((int));
657 static void dot_altrp
PARAMS ((int));
658 static void dot_savemem
PARAMS ((int));
659 static void dot_saveg
PARAMS ((int));
660 static void dot_savef
PARAMS ((int));
661 static void dot_saveb
PARAMS ((int));
662 static void dot_savegf
PARAMS ((int));
663 static void dot_spill
PARAMS ((int));
664 static void dot_spillreg
PARAMS ((int));
665 static void dot_spillmem
PARAMS ((int));
666 static void dot_spillreg_p
PARAMS ((int));
667 static void dot_spillmem_p
PARAMS ((int));
668 static void dot_label_state
PARAMS ((int));
669 static void dot_copy_state
PARAMS ((int));
670 static void dot_unwabi
PARAMS ((int));
671 static void dot_personality
PARAMS ((int));
672 static void dot_body
PARAMS ((int));
673 static void dot_prologue
PARAMS ((int));
674 static void dot_endp
PARAMS ((int));
675 static void dot_template
PARAMS ((int));
676 static void dot_regstk
PARAMS ((int));
677 static void dot_rot
PARAMS ((int));
678 static void dot_byteorder
PARAMS ((int));
679 static void dot_psr
PARAMS ((int));
680 static void dot_alias
PARAMS ((int));
681 static void dot_ln
PARAMS ((int));
682 static char *parse_section_name
PARAMS ((void));
683 static void dot_xdata
PARAMS ((int));
684 static void stmt_float_cons
PARAMS ((int));
685 static void stmt_cons_ua
PARAMS ((int));
686 static void dot_xfloat_cons
PARAMS ((int));
687 static void dot_xstringer
PARAMS ((int));
688 static void dot_xdata_ua
PARAMS ((int));
689 static void dot_xfloat_cons_ua
PARAMS ((int));
690 static void print_prmask
PARAMS ((valueT mask
));
691 static void dot_pred_rel
PARAMS ((int));
692 static void dot_reg_val
PARAMS ((int));
693 static void dot_dv_mode
PARAMS ((int));
694 static void dot_entry
PARAMS ((int));
695 static void dot_mem_offset
PARAMS ((int));
696 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
697 static symbolS
*declare_register
PARAMS ((const char *name
, int regnum
));
698 static void declare_register_set
PARAMS ((const char *, int, int));
699 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
700 static enum operand_match_result operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
703 static int parse_operand
PARAMS ((expressionS
*e
));
704 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
705 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
706 static void emit_one_bundle
PARAMS ((void));
707 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
708 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
709 bfd_reloc_code_real_type r_type
));
710 static void insn_group_break
PARAMS ((int, int, int));
711 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
712 struct rsrc
*, int depind
, int path
));
713 static void add_qp_mutex
PARAMS((valueT mask
));
714 static void add_qp_imply
PARAMS((int p1
, int p2
));
715 static void clear_qp_branch_flag
PARAMS((valueT mask
));
716 static void clear_qp_mutex
PARAMS((valueT mask
));
717 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
718 static void clear_register_values
PARAMS ((void));
719 static void print_dependency
PARAMS ((const char *action
, int depind
));
720 static void instruction_serialization
PARAMS ((void));
721 static void data_serialization
PARAMS ((void));
722 static void remove_marked_resource
PARAMS ((struct rsrc
*));
723 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
724 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
725 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
726 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
727 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
728 struct ia64_opcode
*, int, struct rsrc
[], int, int));
729 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
730 static void check_dependencies
PARAMS((struct ia64_opcode
*));
731 static void mark_resources
PARAMS((struct ia64_opcode
*));
732 static void update_dependencies
PARAMS((struct ia64_opcode
*));
733 static void note_register_values
PARAMS((struct ia64_opcode
*));
734 static int qp_mutex
PARAMS ((int, int, int));
735 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
736 static void output_vbyte_mem
PARAMS ((int, char *, char *));
737 static void count_output
PARAMS ((int, char *, char *));
738 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
739 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
740 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
741 static void output_P1_format
PARAMS ((vbyte_func
, int));
742 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
743 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
744 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
745 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
746 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
747 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
748 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
749 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
750 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
751 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
752 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
753 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
754 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
755 static char format_ab_reg
PARAMS ((int, int));
756 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
758 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
759 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
761 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
762 static void free_list_records
PARAMS ((unw_rec_list
*));
763 static unw_rec_list
*output_prologue
PARAMS ((void));
764 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
765 static unw_rec_list
*output_body
PARAMS ((void));
766 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
767 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
768 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
769 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
770 static unw_rec_list
*output_rp_when
PARAMS ((void));
771 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
772 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
773 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
774 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
775 static unw_rec_list
*output_pfs_when
PARAMS ((void));
776 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
777 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
778 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
779 static unw_rec_list
*output_preds_when
PARAMS ((void));
780 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
781 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
782 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
783 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
784 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
785 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
786 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
787 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
788 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
789 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
790 static unw_rec_list
*output_unat_when
PARAMS ((void));
791 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
792 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
793 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
794 static unw_rec_list
*output_lc_when
PARAMS ((void));
795 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
796 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
797 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
798 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
799 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
800 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
801 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
802 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
803 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
804 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
805 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
806 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
807 static unw_rec_list
*output_bsp_when
PARAMS ((void));
808 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
809 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
810 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
811 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
812 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
813 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
814 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
815 static unw_rec_list
*output_rnat_when
PARAMS ((void));
816 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
817 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
818 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
819 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
820 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
821 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
822 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
823 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
824 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
825 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
827 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
829 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
831 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
832 unsigned int, unsigned int));
833 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
834 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
835 static int calc_record_size
PARAMS ((unw_rec_list
*));
836 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
837 static int count_bits
PARAMS ((unsigned long));
838 static unsigned long slot_index
PARAMS ((unsigned long, fragS
*,
839 unsigned long, fragS
*));
840 static unw_rec_list
*optimize_unw_records
PARAMS ((unw_rec_list
*));
841 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
842 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
843 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
844 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
845 static int generate_unwind_image
PARAMS ((const char *));
847 /* Build the unwind section name by appending the (possibly stripped)
848 text section NAME to the unwind PREFIX. The resulting string
849 pointer is assigned to RESULT. The string is allocated on the
850 stack, so this must be a macro... */
851 #define make_unw_section_name(special, text_name, result) \
853 char *_prefix = special_section_name[special]; \
854 size_t _prefix_len = strlen (_prefix), _text_len = strlen (text_name); \
855 char *_result = alloca (_prefix_len + _text_len + 1); \
856 memcpy(_result, _prefix, _prefix_len); \
857 memcpy(_result + _prefix_len, text_name, _text_len); \
858 _result[_prefix_len + _text_len] = '\0'; \
863 /* Determine if application register REGNUM resides in the integer
864 unit (as opposed to the memory unit). */
866 ar_is_in_integer_unit (reg
)
871 return (reg
== 64 /* pfs */
872 || reg
== 65 /* lc */
873 || reg
== 66 /* ec */
874 /* ??? ias accepts and puts these in the integer unit. */
875 || (reg
>= 112 && reg
<= 127));
878 /* Switch to section NAME and create section if necessary. It's
879 rather ugly that we have to manipulate input_line_pointer but I
880 don't see any other way to accomplish the same thing without
881 changing obj-elf.c (which may be the Right Thing, in the end). */
886 char *saved_input_line_pointer
;
888 saved_input_line_pointer
= input_line_pointer
;
889 input_line_pointer
= name
;
891 input_line_pointer
= saved_input_line_pointer
;
894 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
897 ia64_elf_section_flags (flags
, attr
, type
)
899 int attr
, type ATTRIBUTE_UNUSED
;
901 if (attr
& SHF_IA_64_SHORT
)
902 flags
|= SEC_SMALL_DATA
;
907 ia64_elf_section_type (str
, len
)
911 len
= sizeof (ELF_STRING_ia64_unwind_info
) - 1;
912 if (strncmp (str
, ELF_STRING_ia64_unwind_info
, len
) == 0)
915 len
= sizeof (ELF_STRING_ia64_unwind
) - 1;
916 if (strncmp (str
, ELF_STRING_ia64_unwind
, len
) == 0)
917 return SHT_IA_64_UNWIND
;
923 set_regstack (ins
, locs
, outs
, rots
)
924 unsigned int ins
, locs
, outs
, rots
;
929 sof
= ins
+ locs
+ outs
;
932 as_bad ("Size of frame exceeds maximum of 96 registers");
937 as_warn ("Size of rotating registers exceeds frame size");
940 md
.in
.base
= REG_GR
+ 32;
941 md
.loc
.base
= md
.in
.base
+ ins
;
942 md
.out
.base
= md
.loc
.base
+ locs
;
944 md
.in
.num_regs
= ins
;
945 md
.loc
.num_regs
= locs
;
946 md
.out
.num_regs
= outs
;
947 md
.rot
.num_regs
= rots
;
954 struct label_fix
*lfix
;
956 subsegT saved_subseg
;
959 if (!md
.last_text_seg
)
963 saved_subseg
= now_subseg
;
965 subseg_set (md
.last_text_seg
, 0);
967 while (md
.num_slots_in_use
> 0)
968 emit_one_bundle (); /* force out queued instructions */
970 /* In case there are labels following the last instruction, resolve
972 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
974 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
975 symbol_set_frag (lfix
->sym
, frag_now
);
977 CURR_SLOT
.label_fixups
= 0;
978 for (lfix
= CURR_SLOT
.tag_fixups
; lfix
; lfix
= lfix
->next
)
980 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
981 symbol_set_frag (lfix
->sym
, frag_now
);
983 CURR_SLOT
.tag_fixups
= 0;
985 /* In case there are unwind directives following the last instruction,
986 resolve those now. We only handle body and prologue directives here.
987 Give an error for others. */
988 for (ptr
= unwind
.current_entry
; ptr
; ptr
= ptr
->next
)
990 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
991 || ptr
->r
.type
== body
)
993 ptr
->slot_number
= (unsigned long) frag_more (0);
994 ptr
->slot_frag
= frag_now
;
997 as_bad (_("Unwind directive not followed by an instruction."));
999 unwind
.current_entry
= NULL
;
1001 subseg_set (saved_seg
, saved_subseg
);
1003 if (md
.qp
.X_op
== O_register
)
1004 as_bad ("qualifying predicate not followed by instruction");
1008 ia64_do_align (nbytes
)
1011 char *saved_input_line_pointer
= input_line_pointer
;
1013 input_line_pointer
= "";
1014 s_align_bytes (nbytes
);
1015 input_line_pointer
= saved_input_line_pointer
;
1019 ia64_cons_align (nbytes
)
1024 char *saved_input_line_pointer
= input_line_pointer
;
1025 input_line_pointer
= "";
1026 s_align_bytes (nbytes
);
1027 input_line_pointer
= saved_input_line_pointer
;
1031 /* Output COUNT bytes to a memory location. */
1032 static unsigned char *vbyte_mem_ptr
= NULL
;
1035 output_vbyte_mem (count
, ptr
, comment
)
1038 char *comment ATTRIBUTE_UNUSED
;
1041 if (vbyte_mem_ptr
== NULL
)
1046 for (x
= 0; x
< count
; x
++)
1047 *(vbyte_mem_ptr
++) = ptr
[x
];
1050 /* Count the number of bytes required for records. */
1051 static int vbyte_count
= 0;
1053 count_output (count
, ptr
, comment
)
1055 char *ptr ATTRIBUTE_UNUSED
;
1056 char *comment ATTRIBUTE_UNUSED
;
1058 vbyte_count
+= count
;
1062 output_R1_format (f
, rtype
, rlen
)
1064 unw_record_type rtype
;
1071 output_R3_format (f
, rtype
, rlen
);
1077 else if (rtype
!= prologue
)
1078 as_bad ("record type is not valid");
1080 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
1081 (*f
) (1, &byte
, NULL
);
1085 output_R2_format (f
, mask
, grsave
, rlen
)
1092 mask
= (mask
& 0x0f);
1093 grsave
= (grsave
& 0x7f);
1095 bytes
[0] = (UNW_R2
| (mask
>> 1));
1096 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
1097 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
1098 (*f
) (count
, bytes
, NULL
);
1102 output_R3_format (f
, rtype
, rlen
)
1104 unw_record_type rtype
;
1111 output_R1_format (f
, rtype
, rlen
);
1117 else if (rtype
!= prologue
)
1118 as_bad ("record type is not valid");
1119 bytes
[0] = (UNW_R3
| r
);
1120 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1121 (*f
) (count
+ 1, bytes
, NULL
);
1125 output_P1_format (f
, brmask
)
1130 byte
= UNW_P1
| (brmask
& 0x1f);
1131 (*f
) (1, &byte
, NULL
);
1135 output_P2_format (f
, brmask
, gr
)
1141 brmask
= (brmask
& 0x1f);
1142 bytes
[0] = UNW_P2
| (brmask
>> 1);
1143 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1144 (*f
) (2, bytes
, NULL
);
1148 output_P3_format (f
, rtype
, reg
)
1150 unw_record_type rtype
;
1195 as_bad ("Invalid record type for P3 format.");
1197 bytes
[0] = (UNW_P3
| (r
>> 1));
1198 bytes
[1] = (((r
& 1) << 7) | reg
);
1199 (*f
) (2, bytes
, NULL
);
1203 output_P4_format (f
, imask
, imask_size
)
1205 unsigned char *imask
;
1206 unsigned long imask_size
;
1209 (*f
) (imask_size
, imask
, NULL
);
1213 output_P5_format (f
, grmask
, frmask
)
1216 unsigned long frmask
;
1219 grmask
= (grmask
& 0x0f);
1222 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1223 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1224 bytes
[3] = (frmask
& 0x000000ff);
1225 (*f
) (4, bytes
, NULL
);
1229 output_P6_format (f
, rtype
, rmask
)
1231 unw_record_type rtype
;
1237 if (rtype
== gr_mem
)
1239 else if (rtype
!= fr_mem
)
1240 as_bad ("Invalid record type for format P6");
1241 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1242 (*f
) (1, &byte
, NULL
);
1246 output_P7_format (f
, rtype
, w1
, w2
)
1248 unw_record_type rtype
;
1255 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1260 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1310 bytes
[0] = (UNW_P7
| r
);
1311 (*f
) (count
, bytes
, NULL
);
1315 output_P8_format (f
, rtype
, t
)
1317 unw_record_type rtype
;
1356 case bspstore_psprel
:
1359 case bspstore_sprel
:
1371 case priunat_when_gr
:
1374 case priunat_psprel
:
1380 case priunat_when_mem
:
1387 count
+= output_leb128 (bytes
+ 2, t
, 0);
1388 (*f
) (count
, bytes
, NULL
);
1392 output_P9_format (f
, grmask
, gr
)
1399 bytes
[1] = (grmask
& 0x0f);
1400 bytes
[2] = (gr
& 0x7f);
1401 (*f
) (3, bytes
, NULL
);
1405 output_P10_format (f
, abi
, context
)
1412 bytes
[1] = (abi
& 0xff);
1413 bytes
[2] = (context
& 0xff);
1414 (*f
) (3, bytes
, NULL
);
1418 output_B1_format (f
, rtype
, label
)
1420 unw_record_type rtype
;
1421 unsigned long label
;
1427 output_B4_format (f
, rtype
, label
);
1430 if (rtype
== copy_state
)
1432 else if (rtype
!= label_state
)
1433 as_bad ("Invalid record type for format B1");
1435 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1436 (*f
) (1, &byte
, NULL
);
1440 output_B2_format (f
, ecount
, t
)
1442 unsigned long ecount
;
1449 output_B3_format (f
, ecount
, t
);
1452 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1453 count
+= output_leb128 (bytes
+ 1, t
, 0);
1454 (*f
) (count
, bytes
, NULL
);
1458 output_B3_format (f
, ecount
, t
)
1460 unsigned long ecount
;
1467 output_B2_format (f
, ecount
, t
);
1471 count
+= output_leb128 (bytes
+ 1, t
, 0);
1472 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1473 (*f
) (count
, bytes
, NULL
);
1477 output_B4_format (f
, rtype
, label
)
1479 unw_record_type rtype
;
1480 unsigned long label
;
1487 output_B1_format (f
, rtype
, label
);
1491 if (rtype
== copy_state
)
1493 else if (rtype
!= label_state
)
1494 as_bad ("Invalid record type for format B1");
1496 bytes
[0] = (UNW_B4
| (r
<< 3));
1497 count
+= output_leb128 (bytes
+ 1, label
, 0);
1498 (*f
) (count
, bytes
, NULL
);
1502 format_ab_reg (ab
, reg
)
1509 ret
= (ab
<< 5) | reg
;
1514 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1516 unw_record_type rtype
;
1526 if (rtype
== spill_sprel
)
1528 else if (rtype
!= spill_psprel
)
1529 as_bad ("Invalid record type for format X1");
1530 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1531 count
+= output_leb128 (bytes
+ 2, t
, 0);
1532 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1533 (*f
) (count
, bytes
, NULL
);
1537 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1546 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1547 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1548 count
+= output_leb128 (bytes
+ 3, t
, 0);
1549 (*f
) (count
, bytes
, NULL
);
1553 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1555 unw_record_type rtype
;
1566 if (rtype
== spill_sprel_p
)
1568 else if (rtype
!= spill_psprel_p
)
1569 as_bad ("Invalid record type for format X3");
1570 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1571 bytes
[2] = format_ab_reg (ab
, reg
);
1572 count
+= output_leb128 (bytes
+ 3, t
, 0);
1573 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1574 (*f
) (count
, bytes
, NULL
);
1578 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1588 bytes
[1] = (qp
& 0x3f);
1589 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1590 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1591 count
+= output_leb128 (bytes
+ 4, t
, 0);
1592 (*f
) (count
, bytes
, NULL
);
1595 /* This function allocates a record list structure, and initializes fields. */
1597 static unw_rec_list
*
1598 alloc_record (unw_record_type t
)
1601 ptr
= xmalloc (sizeof (*ptr
));
1603 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1608 /* This function frees an entire list of record structures. */
1611 free_list_records (unw_rec_list
*first
)
1614 for (ptr
= first
; ptr
!= NULL
;)
1616 unw_rec_list
*tmp
= ptr
;
1618 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1619 && tmp
->r
.record
.r
.mask
.i
)
1620 free (tmp
->r
.record
.r
.mask
.i
);
1627 static unw_rec_list
*
1630 unw_rec_list
*ptr
= alloc_record (prologue
);
1631 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1635 static unw_rec_list
*
1636 output_prologue_gr (saved_mask
, reg
)
1637 unsigned int saved_mask
;
1640 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1641 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1642 ptr
->r
.record
.r
.grmask
= saved_mask
;
1643 ptr
->r
.record
.r
.grsave
= reg
;
1647 static unw_rec_list
*
1650 unw_rec_list
*ptr
= alloc_record (body
);
1654 static unw_rec_list
*
1655 output_mem_stack_f (size
)
1658 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1659 ptr
->r
.record
.p
.size
= size
;
1663 static unw_rec_list
*
1664 output_mem_stack_v ()
1666 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1670 static unw_rec_list
*
1674 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1675 ptr
->r
.record
.p
.gr
= gr
;
1679 static unw_rec_list
*
1680 output_psp_sprel (offset
)
1681 unsigned int offset
;
1683 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1684 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1688 static unw_rec_list
*
1691 unw_rec_list
*ptr
= alloc_record (rp_when
);
1695 static unw_rec_list
*
1699 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1700 ptr
->r
.record
.p
.gr
= gr
;
1704 static unw_rec_list
*
1708 unw_rec_list
*ptr
= alloc_record (rp_br
);
1709 ptr
->r
.record
.p
.br
= br
;
1713 static unw_rec_list
*
1714 output_rp_psprel (offset
)
1715 unsigned int offset
;
1717 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1718 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1722 static unw_rec_list
*
1723 output_rp_sprel (offset
)
1724 unsigned int offset
;
1726 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1727 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1731 static unw_rec_list
*
1734 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1738 static unw_rec_list
*
1742 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1743 ptr
->r
.record
.p
.gr
= gr
;
1747 static unw_rec_list
*
1748 output_pfs_psprel (offset
)
1749 unsigned int offset
;
1751 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1752 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1756 static unw_rec_list
*
1757 output_pfs_sprel (offset
)
1758 unsigned int offset
;
1760 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1761 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1765 static unw_rec_list
*
1766 output_preds_when ()
1768 unw_rec_list
*ptr
= alloc_record (preds_when
);
1772 static unw_rec_list
*
1773 output_preds_gr (gr
)
1776 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1777 ptr
->r
.record
.p
.gr
= gr
;
1781 static unw_rec_list
*
1782 output_preds_psprel (offset
)
1783 unsigned int offset
;
1785 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1786 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1790 static unw_rec_list
*
1791 output_preds_sprel (offset
)
1792 unsigned int offset
;
1794 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1795 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1799 static unw_rec_list
*
1800 output_fr_mem (mask
)
1803 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1804 ptr
->r
.record
.p
.rmask
= mask
;
1808 static unw_rec_list
*
1809 output_frgr_mem (gr_mask
, fr_mask
)
1810 unsigned int gr_mask
;
1811 unsigned int fr_mask
;
1813 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1814 ptr
->r
.record
.p
.grmask
= gr_mask
;
1815 ptr
->r
.record
.p
.frmask
= fr_mask
;
1819 static unw_rec_list
*
1820 output_gr_gr (mask
, reg
)
1824 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1825 ptr
->r
.record
.p
.grmask
= mask
;
1826 ptr
->r
.record
.p
.gr
= reg
;
1830 static unw_rec_list
*
1831 output_gr_mem (mask
)
1834 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1835 ptr
->r
.record
.p
.rmask
= mask
;
1839 static unw_rec_list
*
1840 output_br_mem (unsigned int mask
)
1842 unw_rec_list
*ptr
= alloc_record (br_mem
);
1843 ptr
->r
.record
.p
.brmask
= mask
;
1847 static unw_rec_list
*
1848 output_br_gr (save_mask
, reg
)
1849 unsigned int save_mask
;
1852 unw_rec_list
*ptr
= alloc_record (br_gr
);
1853 ptr
->r
.record
.p
.brmask
= save_mask
;
1854 ptr
->r
.record
.p
.gr
= reg
;
1858 static unw_rec_list
*
1859 output_spill_base (offset
)
1860 unsigned int offset
;
1862 unw_rec_list
*ptr
= alloc_record (spill_base
);
1863 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1867 static unw_rec_list
*
1870 unw_rec_list
*ptr
= alloc_record (unat_when
);
1874 static unw_rec_list
*
1878 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1879 ptr
->r
.record
.p
.gr
= gr
;
1883 static unw_rec_list
*
1884 output_unat_psprel (offset
)
1885 unsigned int offset
;
1887 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1888 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1892 static unw_rec_list
*
1893 output_unat_sprel (offset
)
1894 unsigned int offset
;
1896 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1897 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1901 static unw_rec_list
*
1904 unw_rec_list
*ptr
= alloc_record (lc_when
);
1908 static unw_rec_list
*
1912 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1913 ptr
->r
.record
.p
.gr
= gr
;
1917 static unw_rec_list
*
1918 output_lc_psprel (offset
)
1919 unsigned int offset
;
1921 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
1922 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1926 static unw_rec_list
*
1927 output_lc_sprel (offset
)
1928 unsigned int offset
;
1930 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
1931 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1935 static unw_rec_list
*
1938 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
1942 static unw_rec_list
*
1946 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
1947 ptr
->r
.record
.p
.gr
= gr
;
1951 static unw_rec_list
*
1952 output_fpsr_psprel (offset
)
1953 unsigned int offset
;
1955 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
1956 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1960 static unw_rec_list
*
1961 output_fpsr_sprel (offset
)
1962 unsigned int offset
;
1964 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
1965 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1969 static unw_rec_list
*
1970 output_priunat_when_gr ()
1972 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
1976 static unw_rec_list
*
1977 output_priunat_when_mem ()
1979 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
1983 static unw_rec_list
*
1984 output_priunat_gr (gr
)
1987 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
1988 ptr
->r
.record
.p
.gr
= gr
;
1992 static unw_rec_list
*
1993 output_priunat_psprel (offset
)
1994 unsigned int offset
;
1996 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
1997 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2001 static unw_rec_list
*
2002 output_priunat_sprel (offset
)
2003 unsigned int offset
;
2005 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
2006 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2010 static unw_rec_list
*
2013 unw_rec_list
*ptr
= alloc_record (bsp_when
);
2017 static unw_rec_list
*
2021 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
2022 ptr
->r
.record
.p
.gr
= gr
;
2026 static unw_rec_list
*
2027 output_bsp_psprel (offset
)
2028 unsigned int offset
;
2030 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
2031 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2035 static unw_rec_list
*
2036 output_bsp_sprel (offset
)
2037 unsigned int offset
;
2039 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
2040 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2044 static unw_rec_list
*
2045 output_bspstore_when ()
2047 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
2051 static unw_rec_list
*
2052 output_bspstore_gr (gr
)
2055 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
2056 ptr
->r
.record
.p
.gr
= gr
;
2060 static unw_rec_list
*
2061 output_bspstore_psprel (offset
)
2062 unsigned int offset
;
2064 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
2065 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2069 static unw_rec_list
*
2070 output_bspstore_sprel (offset
)
2071 unsigned int offset
;
2073 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
2074 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2078 static unw_rec_list
*
2081 unw_rec_list
*ptr
= alloc_record (rnat_when
);
2085 static unw_rec_list
*
2089 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
2090 ptr
->r
.record
.p
.gr
= gr
;
2094 static unw_rec_list
*
2095 output_rnat_psprel (offset
)
2096 unsigned int offset
;
2098 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
2099 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2103 static unw_rec_list
*
2104 output_rnat_sprel (offset
)
2105 unsigned int offset
;
2107 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2108 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2112 static unw_rec_list
*
2113 output_unwabi (abi
, context
)
2115 unsigned long context
;
2117 unw_rec_list
*ptr
= alloc_record (unwabi
);
2118 ptr
->r
.record
.p
.abi
= abi
;
2119 ptr
->r
.record
.p
.context
= context
;
2123 static unw_rec_list
*
2124 output_epilogue (unsigned long ecount
)
2126 unw_rec_list
*ptr
= alloc_record (epilogue
);
2127 ptr
->r
.record
.b
.ecount
= ecount
;
2131 static unw_rec_list
*
2132 output_label_state (unsigned long label
)
2134 unw_rec_list
*ptr
= alloc_record (label_state
);
2135 ptr
->r
.record
.b
.label
= label
;
2139 static unw_rec_list
*
2140 output_copy_state (unsigned long label
)
2142 unw_rec_list
*ptr
= alloc_record (copy_state
);
2143 ptr
->r
.record
.b
.label
= label
;
2147 static unw_rec_list
*
2148 output_spill_psprel (ab
, reg
, offset
)
2151 unsigned int offset
;
2153 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2154 ptr
->r
.record
.x
.ab
= ab
;
2155 ptr
->r
.record
.x
.reg
= reg
;
2156 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2160 static unw_rec_list
*
2161 output_spill_sprel (ab
, reg
, offset
)
2164 unsigned int offset
;
2166 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2167 ptr
->r
.record
.x
.ab
= ab
;
2168 ptr
->r
.record
.x
.reg
= reg
;
2169 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2173 static unw_rec_list
*
2174 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2177 unsigned int offset
;
2178 unsigned int predicate
;
2180 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2181 ptr
->r
.record
.x
.ab
= ab
;
2182 ptr
->r
.record
.x
.reg
= reg
;
2183 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2184 ptr
->r
.record
.x
.qp
= predicate
;
2188 static unw_rec_list
*
2189 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2192 unsigned int offset
;
2193 unsigned int predicate
;
2195 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2196 ptr
->r
.record
.x
.ab
= ab
;
2197 ptr
->r
.record
.x
.reg
= reg
;
2198 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2199 ptr
->r
.record
.x
.qp
= predicate
;
2203 static unw_rec_list
*
2204 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2207 unsigned int targ_reg
;
2210 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2211 ptr
->r
.record
.x
.ab
= ab
;
2212 ptr
->r
.record
.x
.reg
= reg
;
2213 ptr
->r
.record
.x
.treg
= targ_reg
;
2214 ptr
->r
.record
.x
.xy
= xy
;
2218 static unw_rec_list
*
2219 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2222 unsigned int targ_reg
;
2224 unsigned int predicate
;
2226 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2227 ptr
->r
.record
.x
.ab
= ab
;
2228 ptr
->r
.record
.x
.reg
= reg
;
2229 ptr
->r
.record
.x
.treg
= targ_reg
;
2230 ptr
->r
.record
.x
.xy
= xy
;
2231 ptr
->r
.record
.x
.qp
= predicate
;
2235 /* Given a unw_rec_list process the correct format with the
2236 specified function. */
2239 process_one_record (ptr
, f
)
2243 unsigned long fr_mask
, gr_mask
;
2245 switch (ptr
->r
.type
)
2251 /* These are taken care of by prologue/prologue_gr. */
2256 if (ptr
->r
.type
== prologue_gr
)
2257 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2258 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2260 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2262 /* Output descriptor(s) for union of register spills (if any). */
2263 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2264 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2267 if ((fr_mask
& ~0xfUL
) == 0)
2268 output_P6_format (f
, fr_mem
, fr_mask
);
2271 output_P5_format (f
, gr_mask
, fr_mask
);
2276 output_P6_format (f
, gr_mem
, gr_mask
);
2277 if (ptr
->r
.record
.r
.mask
.br_mem
)
2278 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2280 /* output imask descriptor if necessary: */
2281 if (ptr
->r
.record
.r
.mask
.i
)
2282 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2283 ptr
->r
.record
.r
.imask_size
);
2287 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2291 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2292 ptr
->r
.record
.p
.size
);
2305 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2308 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2311 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2319 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2328 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2338 case bspstore_sprel
:
2340 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2343 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2346 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2349 as_bad ("spill_mask record unimplemented.");
2351 case priunat_when_gr
:
2352 case priunat_when_mem
:
2356 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2358 case priunat_psprel
:
2360 case bspstore_psprel
:
2362 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2365 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2368 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2372 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2375 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2376 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2377 ptr
->r
.record
.x
.pspoff
);
2380 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2381 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2382 ptr
->r
.record
.x
.spoff
);
2385 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2386 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2387 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2389 case spill_psprel_p
:
2390 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2391 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2392 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2395 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2396 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2397 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2400 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2401 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2402 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2406 as_bad ("record_type_not_valid");
2411 /* Given a unw_rec_list list, process all the records with
2412 the specified function. */
2414 process_unw_records (list
, f
)
2419 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2420 process_one_record (ptr
, f
);
2423 /* Determine the size of a record list in bytes. */
2425 calc_record_size (list
)
2429 process_unw_records (list
, count_output
);
2433 /* Update IMASK bitmask to reflect the fact that one or more registers
2434 of type TYPE are saved starting at instruction with index T. If N
2435 bits are set in REGMASK, it is assumed that instructions T through
2436 T+N-1 save these registers.
2440 1: instruction saves next fp reg
2441 2: instruction saves next general reg
2442 3: instruction saves next branch reg */
2444 set_imask (region
, regmask
, t
, type
)
2445 unw_rec_list
*region
;
2446 unsigned long regmask
;
2450 unsigned char *imask
;
2451 unsigned long imask_size
;
2455 imask
= region
->r
.record
.r
.mask
.i
;
2456 imask_size
= region
->r
.record
.r
.imask_size
;
2459 imask_size
= (region
->r
.record
.r
.rlen
* 2 + 7) / 8 + 1;
2460 imask
= xmalloc (imask_size
);
2461 memset (imask
, 0, imask_size
);
2463 region
->r
.record
.r
.imask_size
= imask_size
;
2464 region
->r
.record
.r
.mask
.i
= imask
;
2468 pos
= 2 * (3 - t
% 4);
2471 if (i
>= imask_size
)
2473 as_bad ("Ignoring attempt to spill beyond end of region");
2477 imask
[i
] |= (type
& 0x3) << pos
;
2479 regmask
&= (regmask
- 1);
2490 count_bits (unsigned long mask
)
2502 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2503 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2504 containing FIRST_ADDR. */
2507 slot_index (slot_addr
, slot_frag
, first_addr
, first_frag
)
2508 unsigned long slot_addr
;
2510 unsigned long first_addr
;
2513 unsigned long index
= 0;
2515 /* First time we are called, the initial address and frag are invalid. */
2516 if (first_addr
== 0)
2519 /* If the two addresses are in different frags, then we need to add in
2520 the remaining size of this frag, and then the entire size of intermediate
2522 while (slot_frag
!= first_frag
)
2524 unsigned long start_addr
= (unsigned long) &first_frag
->fr_literal
;
2526 /* Add in the full size of the frag converted to instruction slots. */
2527 index
+= 3 * (first_frag
->fr_fix
>> 4);
2528 /* Subtract away the initial part before first_addr. */
2529 index
-= (3 * ((first_addr
>> 4) - (start_addr
>> 4))
2530 + ((first_addr
& 0x3) - (start_addr
& 0x3)));
2532 /* Move to the beginning of the next frag. */
2533 first_frag
= first_frag
->fr_next
;
2534 first_addr
= (unsigned long) &first_frag
->fr_literal
;
2537 /* Add in the used part of the last frag. */
2538 index
+= (3 * ((slot_addr
>> 4) - (first_addr
>> 4))
2539 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2543 /* Optimize unwind record directives. */
2545 static unw_rec_list
*
2546 optimize_unw_records (list
)
2552 /* If the only unwind record is ".prologue" or ".prologue" followed
2553 by ".body", then we can optimize the unwind directives away. */
2554 if (list
->r
.type
== prologue
2555 && (list
->next
== NULL
2556 || (list
->next
->r
.type
== body
&& list
->next
->next
== NULL
)))
2562 /* Given a complete record list, process any records which have
2563 unresolved fields, (ie length counts for a prologue). After
2564 this has been run, all neccessary information should be available
2565 within each record to generate an image. */
2568 fixup_unw_records (list
)
2571 unw_rec_list
*ptr
, *region
= 0;
2572 unsigned long first_addr
= 0, rlen
= 0, t
;
2573 fragS
*first_frag
= 0;
2575 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2577 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2578 as_bad (" Insn slot not set in unwind record.");
2579 t
= slot_index (ptr
->slot_number
, ptr
->slot_frag
,
2580 first_addr
, first_frag
);
2581 switch (ptr
->r
.type
)
2588 int size
, dir_len
= 0;
2589 unsigned long last_addr
;
2592 first_addr
= ptr
->slot_number
;
2593 first_frag
= ptr
->slot_frag
;
2594 ptr
->slot_number
= 0;
2595 /* Find either the next body/prologue start, or the end of
2596 the list, and determine the size of the region. */
2597 last_addr
= unwind
.next_slot_number
;
2598 last_frag
= unwind
.next_slot_frag
;
2599 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2600 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2601 || last
->r
.type
== body
)
2603 last_addr
= last
->slot_number
;
2604 last_frag
= last
->slot_frag
;
2607 else if (!last
->next
)
2609 /* In the absence of an explicit .body directive,
2610 the prologue ends after the last instruction
2611 covered by an unwind directive. */
2612 if (ptr
->r
.type
!= body
)
2614 last_addr
= last
->slot_number
;
2615 last_frag
= last
->slot_frag
;
2616 switch (last
->r
.type
)
2619 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2620 + count_bits (last
->r
.record
.p
.grmask
));
2624 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2628 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2631 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2640 size
= (slot_index (last_addr
, last_frag
, first_addr
, first_frag
)
2642 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2647 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2658 case priunat_when_gr
:
2659 case priunat_when_mem
:
2663 ptr
->r
.record
.p
.t
= t
;
2671 case spill_psprel_p
:
2672 ptr
->r
.record
.x
.t
= t
;
2678 as_bad ("frgr_mem record before region record!\n");
2681 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2682 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2683 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2684 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2689 as_bad ("fr_mem record before region record!\n");
2692 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2693 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2698 as_bad ("gr_mem record before region record!\n");
2701 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2702 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2707 as_bad ("br_mem record before region record!\n");
2710 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2711 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2717 as_bad ("gr_gr record before region record!\n");
2720 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2725 as_bad ("br_gr record before region record!\n");
2728 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2737 /* Generate an unwind image from a record list. Returns the number of
2738 bytes in the resulting image. The memory image itselof is returned
2739 in the 'ptr' parameter. */
2741 output_unw_records (list
, ptr
)
2745 int size
, x
, extra
= 0;
2750 list
= optimize_unw_records (list
);
2751 fixup_unw_records (list
);
2752 size
= calc_record_size (list
);
2754 /* pad to 8 byte boundry. */
2759 if (size
> 0 || unwind
.force_unwind_entry
)
2761 unwind
.force_unwind_entry
= 0;
2763 /* Add 8 for the header + 8 more bytes for the personality offset. */
2764 mem
= xmalloc (size
+ extra
+ 16);
2766 vbyte_mem_ptr
= mem
+ 8;
2767 /* Clear the padding area and personality. */
2768 memset (mem
+ 8 + size
, 0 , extra
+ 8);
2769 /* Initialize the header area. */
2770 md_number_to_chars (mem
,
2771 (((bfd_vma
) 1 << 48) /* version */
2772 | (unwind
.personality_routine
2773 ? ((bfd_vma
) 3 << 32) /* U & E handler flags */
2775 | ((size
+ extra
) / 8)), /* length (dwords) */
2778 process_unw_records (list
, output_vbyte_mem
);
2788 convert_expr_to_ab_reg (e
, ab
, regp
)
2795 if (e
->X_op
!= O_register
)
2798 reg
= e
->X_add_number
;
2799 if (reg
>= (REG_GR
+ 4) && reg
<= (REG_GR
+ 7))
2802 *regp
= reg
- REG_GR
;
2804 else if ((reg
>= (REG_FR
+ 2) && reg
<= (REG_FR
+ 5))
2805 || (reg
>= (REG_FR
+ 16) && reg
<= (REG_FR
+ 31)))
2808 *regp
= reg
- REG_FR
;
2810 else if (reg
>= (REG_BR
+ 1) && reg
<= (REG_BR
+ 5))
2813 *regp
= reg
- REG_BR
;
2820 case REG_PR
: *regp
= 0; break;
2821 case REG_PSP
: *regp
= 1; break;
2822 case REG_PRIUNAT
: *regp
= 2; break;
2823 case REG_BR
+ 0: *regp
= 3; break;
2824 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2825 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2826 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2827 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2828 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2829 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2830 case REG_AR
+ AR_LC
: *regp
= 10; break;
2840 convert_expr_to_xy_reg (e
, xy
, regp
)
2847 if (e
->X_op
!= O_register
)
2850 reg
= e
->X_add_number
;
2852 if (/* reg >= REG_GR && */ reg
<= (REG_GR
+ 127))
2855 *regp
= reg
- REG_GR
;
2857 else if (reg
>= REG_FR
&& reg
<= (REG_FR
+ 127))
2860 *regp
= reg
- REG_FR
;
2862 else if (reg
>= REG_BR
&& reg
<= (REG_BR
+ 7))
2865 *regp
= reg
- REG_BR
;
2874 int dummy ATTRIBUTE_UNUSED
;
2879 radix
= *input_line_pointer
++;
2881 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2883 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2884 ignore_rest_of_line ();
2889 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2891 dot_special_section (which
)
2894 set_section ((char *) special_section_name
[which
]);
2898 add_unwind_entry (ptr
)
2902 unwind
.tail
->next
= ptr
;
2907 /* The current entry can in fact be a chain of unwind entries. */
2908 if (unwind
.current_entry
== NULL
)
2909 unwind
.current_entry
= ptr
;
2914 int dummy ATTRIBUTE_UNUSED
;
2920 if (e
.X_op
!= O_constant
)
2921 as_bad ("Operand to .fframe must be a constant");
2923 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
2928 int dummy ATTRIBUTE_UNUSED
;
2934 reg
= e
.X_add_number
- REG_GR
;
2935 if (e
.X_op
== O_register
&& reg
< 128)
2937 add_unwind_entry (output_mem_stack_v ());
2938 if (! (unwind
.prologue_mask
& 2))
2939 add_unwind_entry (output_psp_gr (reg
));
2942 as_bad ("First operand to .vframe must be a general register");
2946 dot_vframesp (dummy
)
2947 int dummy ATTRIBUTE_UNUSED
;
2952 if (e
.X_op
== O_constant
)
2954 add_unwind_entry (output_mem_stack_v ());
2955 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2958 as_bad ("First operand to .vframesp must be a general register");
2962 dot_vframepsp (dummy
)
2963 int dummy ATTRIBUTE_UNUSED
;
2968 if (e
.X_op
== O_constant
)
2970 add_unwind_entry (output_mem_stack_v ());
2971 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2974 as_bad ("First operand to .vframepsp must be a general register");
2979 int dummy ATTRIBUTE_UNUSED
;
2985 sep
= parse_operand (&e1
);
2987 as_bad ("No second operand to .save");
2988 sep
= parse_operand (&e2
);
2990 reg1
= e1
.X_add_number
;
2991 reg2
= e2
.X_add_number
- REG_GR
;
2993 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2994 if (e1
.X_op
== O_register
)
2996 if (e2
.X_op
== O_register
&& reg2
>= 0 && reg2
< 128)
3000 case REG_AR
+ AR_BSP
:
3001 add_unwind_entry (output_bsp_when ());
3002 add_unwind_entry (output_bsp_gr (reg2
));
3004 case REG_AR
+ AR_BSPSTORE
:
3005 add_unwind_entry (output_bspstore_when ());
3006 add_unwind_entry (output_bspstore_gr (reg2
));
3008 case REG_AR
+ AR_RNAT
:
3009 add_unwind_entry (output_rnat_when ());
3010 add_unwind_entry (output_rnat_gr (reg2
));
3012 case REG_AR
+ AR_UNAT
:
3013 add_unwind_entry (output_unat_when ());
3014 add_unwind_entry (output_unat_gr (reg2
));
3016 case REG_AR
+ AR_FPSR
:
3017 add_unwind_entry (output_fpsr_when ());
3018 add_unwind_entry (output_fpsr_gr (reg2
));
3020 case REG_AR
+ AR_PFS
:
3021 add_unwind_entry (output_pfs_when ());
3022 if (! (unwind
.prologue_mask
& 4))
3023 add_unwind_entry (output_pfs_gr (reg2
));
3025 case REG_AR
+ AR_LC
:
3026 add_unwind_entry (output_lc_when ());
3027 add_unwind_entry (output_lc_gr (reg2
));
3030 add_unwind_entry (output_rp_when ());
3031 if (! (unwind
.prologue_mask
& 8))
3032 add_unwind_entry (output_rp_gr (reg2
));
3035 add_unwind_entry (output_preds_when ());
3036 if (! (unwind
.prologue_mask
& 1))
3037 add_unwind_entry (output_preds_gr (reg2
));
3040 add_unwind_entry (output_priunat_when_gr ());
3041 add_unwind_entry (output_priunat_gr (reg2
));
3044 as_bad ("First operand not a valid register");
3048 as_bad (" Second operand not a valid register");
3051 as_bad ("First operand not a register");
3056 int dummy ATTRIBUTE_UNUSED
;
3059 unsigned long ecount
; /* # of _additional_ regions to pop */
3062 sep
= parse_operand (&e1
);
3063 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
3065 as_bad ("First operand to .restore must be stack pointer (sp)");
3071 parse_operand (&e2
);
3072 if (e2
.X_op
!= O_constant
|| e2
.X_add_number
< 0)
3074 as_bad ("Second operand to .restore must be a constant >= 0");
3077 ecount
= e2
.X_add_number
;
3080 ecount
= unwind
.prologue_count
- 1;
3081 add_unwind_entry (output_epilogue (ecount
));
3083 if (ecount
< unwind
.prologue_count
)
3084 unwind
.prologue_count
-= ecount
+ 1;
3086 unwind
.prologue_count
= 0;
3090 dot_restorereg (dummy
)
3091 int dummy ATTRIBUTE_UNUSED
;
3093 unsigned int ab
, reg
;
3098 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
3100 as_bad ("First operand to .restorereg must be a preserved register");
3103 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
3107 dot_restorereg_p (dummy
)
3108 int dummy ATTRIBUTE_UNUSED
;
3110 unsigned int qp
, ab
, reg
;
3114 sep
= parse_operand (&e1
);
3117 as_bad ("No second operand to .restorereg.p");
3121 parse_operand (&e2
);
3123 qp
= e1
.X_add_number
- REG_P
;
3124 if (e1
.X_op
!= O_register
|| qp
> 63)
3126 as_bad ("First operand to .restorereg.p must be a predicate");
3130 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3132 as_bad ("Second operand to .restorereg.p must be a preserved register");
3135 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
3139 generate_unwind_image (text_name
)
3140 const char *text_name
;
3143 unsigned char *unw_rec
;
3145 /* Force out pending instructions, to make sure all unwind records have
3146 a valid slot_number field. */
3147 ia64_flush_insns ();
3149 /* Generate the unwind record. */
3150 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
3152 as_bad ("Unwind record is not a multiple of 8 bytes.");
3154 /* If there are unwind records, switch sections, and output the info. */
3157 unsigned char *where
;
3161 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO
, text_name
, sec_name
);
3162 set_section (sec_name
);
3163 bfd_set_section_flags (stdoutput
, now_seg
,
3164 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3166 /* Make sure the section has 8 byte alignment. */
3167 record_alignment (now_seg
, 3);
3169 /* Set expression which points to start of unwind descriptor area. */
3170 unwind
.info
= expr_build_dot ();
3172 where
= (unsigned char *) frag_more (size
);
3174 /* Issue a label for this address, and keep track of it to put it
3175 in the unwind section. */
3177 /* Copy the information from the unwind record into this section. The
3178 data is already in the correct byte order. */
3179 memcpy (where
, unw_rec
, size
);
3181 /* Add the personality address to the image. */
3182 if (unwind
.personality_routine
!= 0)
3184 exp
.X_op
= O_symbol
;
3185 exp
.X_add_symbol
= unwind
.personality_routine
;
3186 exp
.X_add_number
= 0;
3187 fix_new_exp (frag_now
, frag_now_fix () - 8, 8,
3188 &exp
, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB
);
3189 unwind
.personality_routine
= 0;
3193 free_list_records (unwind
.list
);
3194 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3200 dot_handlerdata (dummy
)
3201 int dummy ATTRIBUTE_UNUSED
;
3203 const char *text_name
= segment_name (now_seg
);
3205 /* If text section name starts with ".text" (which it should),
3206 strip this prefix off. */
3207 if (strcmp (text_name
, ".text") == 0)
3210 unwind
.force_unwind_entry
= 1;
3212 /* Remember which segment we're in so we can switch back after .endp */
3213 unwind
.saved_text_seg
= now_seg
;
3214 unwind
.saved_text_subseg
= now_subseg
;
3216 /* Generate unwind info into unwind-info section and then leave that
3217 section as the currently active one so dataXX directives go into
3218 the language specific data area of the unwind info block. */
3219 generate_unwind_image (text_name
);
3220 demand_empty_rest_of_line ();
3224 dot_unwentry (dummy
)
3225 int dummy ATTRIBUTE_UNUSED
;
3227 unwind
.force_unwind_entry
= 1;
3228 demand_empty_rest_of_line ();
3233 int dummy ATTRIBUTE_UNUSED
;
3239 reg
= e
.X_add_number
- REG_BR
;
3240 if (e
.X_op
== O_register
&& reg
< 8)
3241 add_unwind_entry (output_rp_br (reg
));
3243 as_bad ("First operand not a valid branch register");
3247 dot_savemem (psprel
)
3254 sep
= parse_operand (&e1
);
3256 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3257 sep
= parse_operand (&e2
);
3259 reg1
= e1
.X_add_number
;
3260 val
= e2
.X_add_number
;
3262 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3263 if (e1
.X_op
== O_register
)
3265 if (e2
.X_op
== O_constant
)
3269 case REG_AR
+ AR_BSP
:
3270 add_unwind_entry (output_bsp_when ());
3271 add_unwind_entry ((psprel
3273 : output_bsp_sprel
) (val
));
3275 case REG_AR
+ AR_BSPSTORE
:
3276 add_unwind_entry (output_bspstore_when ());
3277 add_unwind_entry ((psprel
3278 ? output_bspstore_psprel
3279 : output_bspstore_sprel
) (val
));
3281 case REG_AR
+ AR_RNAT
:
3282 add_unwind_entry (output_rnat_when ());
3283 add_unwind_entry ((psprel
3284 ? output_rnat_psprel
3285 : output_rnat_sprel
) (val
));
3287 case REG_AR
+ AR_UNAT
:
3288 add_unwind_entry (output_unat_when ());
3289 add_unwind_entry ((psprel
3290 ? output_unat_psprel
3291 : output_unat_sprel
) (val
));
3293 case REG_AR
+ AR_FPSR
:
3294 add_unwind_entry (output_fpsr_when ());
3295 add_unwind_entry ((psprel
3296 ? output_fpsr_psprel
3297 : output_fpsr_sprel
) (val
));
3299 case REG_AR
+ AR_PFS
:
3300 add_unwind_entry (output_pfs_when ());
3301 add_unwind_entry ((psprel
3303 : output_pfs_sprel
) (val
));
3305 case REG_AR
+ AR_LC
:
3306 add_unwind_entry (output_lc_when ());
3307 add_unwind_entry ((psprel
3309 : output_lc_sprel
) (val
));
3312 add_unwind_entry (output_rp_when ());
3313 add_unwind_entry ((psprel
3315 : output_rp_sprel
) (val
));
3318 add_unwind_entry (output_preds_when ());
3319 add_unwind_entry ((psprel
3320 ? output_preds_psprel
3321 : output_preds_sprel
) (val
));
3324 add_unwind_entry (output_priunat_when_mem ());
3325 add_unwind_entry ((psprel
3326 ? output_priunat_psprel
3327 : output_priunat_sprel
) (val
));
3330 as_bad ("First operand not a valid register");
3334 as_bad (" Second operand not a valid constant");
3337 as_bad ("First operand not a register");
3342 int dummy ATTRIBUTE_UNUSED
;
3346 sep
= parse_operand (&e1
);
3348 parse_operand (&e2
);
3350 if (e1
.X_op
!= O_constant
)
3351 as_bad ("First operand to .save.g must be a constant.");
3354 int grmask
= e1
.X_add_number
;
3356 add_unwind_entry (output_gr_mem (grmask
));
3359 int reg
= e2
.X_add_number
- REG_GR
;
3360 if (e2
.X_op
== O_register
&& reg
>= 0 && reg
< 128)
3361 add_unwind_entry (output_gr_gr (grmask
, reg
));
3363 as_bad ("Second operand is an invalid register.");
3370 int dummy ATTRIBUTE_UNUSED
;
3374 sep
= parse_operand (&e1
);
3376 if (e1
.X_op
!= O_constant
)
3377 as_bad ("Operand to .save.f must be a constant.");
3379 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3384 int dummy ATTRIBUTE_UNUSED
;
3391 sep
= parse_operand (&e1
);
3392 if (e1
.X_op
!= O_constant
)
3394 as_bad ("First operand to .save.b must be a constant.");
3397 brmask
= e1
.X_add_number
;
3401 sep
= parse_operand (&e2
);
3402 reg
= e2
.X_add_number
- REG_GR
;
3403 if (e2
.X_op
!= O_register
|| reg
> 127)
3405 as_bad ("Second operand to .save.b must be a general register.");
3408 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3411 add_unwind_entry (output_br_mem (brmask
));
3413 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3414 ignore_rest_of_line ();
3419 int dummy ATTRIBUTE_UNUSED
;
3423 sep
= parse_operand (&e1
);
3425 parse_operand (&e2
);
3427 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3428 as_bad ("Both operands of .save.gf must be constants.");
3431 int grmask
= e1
.X_add_number
;
3432 int frmask
= e2
.X_add_number
;
3433 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3439 int dummy ATTRIBUTE_UNUSED
;
3444 sep
= parse_operand (&e
);
3445 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3446 ignore_rest_of_line ();
3448 if (e
.X_op
!= O_constant
)
3449 as_bad ("Operand to .spill must be a constant");
3451 add_unwind_entry (output_spill_base (e
.X_add_number
));
3455 dot_spillreg (dummy
)
3456 int dummy ATTRIBUTE_UNUSED
;
3458 int sep
, ab
, xy
, reg
, treg
;
3461 sep
= parse_operand (&e1
);
3464 as_bad ("No second operand to .spillreg");
3468 parse_operand (&e2
);
3470 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3472 as_bad ("First operand to .spillreg must be a preserved register");
3476 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3478 as_bad ("Second operand to .spillreg must be a register");
3482 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3486 dot_spillmem (psprel
)
3492 sep
= parse_operand (&e1
);
3495 as_bad ("Second operand missing");
3499 parse_operand (&e2
);
3501 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3503 as_bad ("First operand to .spill%s must be a preserved register",
3504 psprel
? "psp" : "sp");
3508 if (e2
.X_op
!= O_constant
)
3510 as_bad ("Second operand to .spill%s must be a constant",
3511 psprel
? "psp" : "sp");
3516 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3518 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3522 dot_spillreg_p (dummy
)
3523 int dummy ATTRIBUTE_UNUSED
;
3525 int sep
, ab
, xy
, reg
, treg
;
3526 expressionS e1
, e2
, e3
;
3529 sep
= parse_operand (&e1
);
3532 as_bad ("No second and third operand to .spillreg.p");
3536 sep
= parse_operand (&e2
);
3539 as_bad ("No third operand to .spillreg.p");
3543 parse_operand (&e3
);
3545 qp
= e1
.X_add_number
- REG_P
;
3547 if (e1
.X_op
!= O_register
|| qp
> 63)
3549 as_bad ("First operand to .spillreg.p must be a predicate");
3553 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3555 as_bad ("Second operand to .spillreg.p must be a preserved register");
3559 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3561 as_bad ("Third operand to .spillreg.p must be a register");
3565 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3569 dot_spillmem_p (psprel
)
3572 expressionS e1
, e2
, e3
;
3576 sep
= parse_operand (&e1
);
3579 as_bad ("Second operand missing");
3583 parse_operand (&e2
);
3586 as_bad ("Second operand missing");
3590 parse_operand (&e3
);
3592 qp
= e1
.X_add_number
- REG_P
;
3593 if (e1
.X_op
!= O_register
|| qp
> 63)
3595 as_bad ("First operand to .spill%s_p must be a predicate",
3596 psprel
? "psp" : "sp");
3600 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3602 as_bad ("Second operand to .spill%s_p must be a preserved register",
3603 psprel
? "psp" : "sp");
3607 if (e3
.X_op
!= O_constant
)
3609 as_bad ("Third operand to .spill%s_p must be a constant",
3610 psprel
? "psp" : "sp");
3615 add_unwind_entry (output_spill_psprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3617 add_unwind_entry (output_spill_sprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3621 dot_label_state (dummy
)
3622 int dummy ATTRIBUTE_UNUSED
;
3627 if (e
.X_op
!= O_constant
)
3629 as_bad ("Operand to .label_state must be a constant");
3632 add_unwind_entry (output_label_state (e
.X_add_number
));
3636 dot_copy_state (dummy
)
3637 int dummy ATTRIBUTE_UNUSED
;
3642 if (e
.X_op
!= O_constant
)
3644 as_bad ("Operand to .copy_state must be a constant");
3647 add_unwind_entry (output_copy_state (e
.X_add_number
));
3652 int dummy ATTRIBUTE_UNUSED
;
3657 sep
= parse_operand (&e1
);
3660 as_bad ("Second operand to .unwabi missing");
3663 sep
= parse_operand (&e2
);
3664 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3665 ignore_rest_of_line ();
3667 if (e1
.X_op
!= O_constant
)
3669 as_bad ("First operand to .unwabi must be a constant");
3673 if (e2
.X_op
!= O_constant
)
3675 as_bad ("Second operand to .unwabi must be a constant");
3679 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3683 dot_personality (dummy
)
3684 int dummy ATTRIBUTE_UNUSED
;
3688 name
= input_line_pointer
;
3689 c
= get_symbol_end ();
3690 p
= input_line_pointer
;
3691 unwind
.personality_routine
= symbol_find_or_make (name
);
3692 unwind
.force_unwind_entry
= 1;
3695 demand_empty_rest_of_line ();
3700 int dummy ATTRIBUTE_UNUSED
;
3705 unwind
.proc_start
= expr_build_dot ();
3706 /* Parse names of main and alternate entry points and mark them as
3707 function symbols: */
3711 name
= input_line_pointer
;
3712 c
= get_symbol_end ();
3713 p
= input_line_pointer
;
3714 sym
= symbol_find_or_make (name
);
3715 if (unwind
.proc_start
== 0)
3717 unwind
.proc_start
= sym
;
3719 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3722 if (*input_line_pointer
!= ',')
3724 ++input_line_pointer
;
3726 demand_empty_rest_of_line ();
3729 unwind
.prologue_count
= 0;
3730 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3731 unwind
.personality_routine
= 0;
3736 int dummy ATTRIBUTE_UNUSED
;
3738 unwind
.prologue
= 0;
3739 unwind
.prologue_mask
= 0;
3741 add_unwind_entry (output_body ());
3742 demand_empty_rest_of_line ();
3746 dot_prologue (dummy
)
3747 int dummy ATTRIBUTE_UNUSED
;
3750 int mask
= 0, grsave
= 0;
3752 if (!is_it_end_of_statement ())
3755 sep
= parse_operand (&e1
);
3757 as_bad ("No second operand to .prologue");
3758 sep
= parse_operand (&e2
);
3759 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3760 ignore_rest_of_line ();
3762 if (e1
.X_op
== O_constant
)
3764 mask
= e1
.X_add_number
;
3766 if (e2
.X_op
== O_constant
)
3767 grsave
= e2
.X_add_number
;
3768 else if (e2
.X_op
== O_register
3769 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3772 as_bad ("Second operand not a constant or general register");
3774 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3777 as_bad ("First operand not a constant");
3780 add_unwind_entry (output_prologue ());
3782 unwind
.prologue
= 1;
3783 unwind
.prologue_mask
= mask
;
3784 ++unwind
.prologue_count
;
3789 int dummy ATTRIBUTE_UNUSED
;
3793 int bytes_per_address
;
3796 subsegT saved_subseg
;
3797 const char *sec_name
, *text_name
;
3799 if (unwind
.saved_text_seg
)
3801 saved_seg
= unwind
.saved_text_seg
;
3802 saved_subseg
= unwind
.saved_text_subseg
;
3803 unwind
.saved_text_seg
= NULL
;
3807 saved_seg
= now_seg
;
3808 saved_subseg
= now_subseg
;
3812 Use a slightly ugly scheme to derive the unwind section names from
3813 the text section name:
3815 text sect. unwind table sect.
3816 name: name: comments:
3817 ---------- ----------------- --------------------------------
3819 .text.foo .IA_64.unwind.text.foo
3820 .foo .IA_64.unwind.foo
3821 _info .IA_64.unwind_info gas issues error message (ditto)
3822 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
3824 This mapping is done so that:
3826 (a) An object file with unwind info only in .text will use
3827 unwind section names .IA_64.unwind and .IA_64.unwind_info.
3828 This follows the letter of the ABI and also ensures backwards
3829 compatibility with older toolchains.
3831 (b) An object file with unwind info in multiple text sections
3832 will use separate unwind sections for each text section.
3833 This allows us to properly set the "sh_info" and "sh_link"
3834 fields in SHT_IA_64_UNWIND as required by the ABI and also
3835 lets GNU ld support programs with multiple segments
3836 containing unwind info (as might be the case for certain
3837 embedded applications).
3839 (c) An error is issued if there would be a name clash.
3841 text_name
= segment_name (saved_seg
);
3842 if (strncmp (text_name
, "_info", 5) == 0)
3844 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
3846 ignore_rest_of_line ();
3849 if (strcmp (text_name
, ".text") == 0)
3853 demand_empty_rest_of_line ();
3855 insn_group_break (1, 0, 0);
3857 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
3859 generate_unwind_image (text_name
);
3861 if (unwind
.info
|| unwind
.force_unwind_entry
)
3863 subseg_set (md
.last_text_seg
, 0);
3864 unwind
.proc_end
= expr_build_dot ();
3866 make_unw_section_name (SPECIAL_SECTION_UNWIND
, text_name
, sec_name
);
3867 set_section ((char *) sec_name
);
3868 bfd_set_section_flags (stdoutput
, now_seg
,
3869 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3871 /* Make sure the section has 8 byte alignment. */
3872 record_alignment (now_seg
, 3);
3874 ptr
= frag_more (24);
3875 where
= frag_now_fix () - 24;
3876 bytes_per_address
= bfd_arch_bits_per_address (stdoutput
) / 8;
3878 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3879 e
.X_op
= O_pseudo_fixup
;
3880 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3882 e
.X_add_symbol
= unwind
.proc_start
;
3883 ia64_cons_fix_new (frag_now
, where
, bytes_per_address
, &e
);
3885 e
.X_op
= O_pseudo_fixup
;
3886 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3888 e
.X_add_symbol
= unwind
.proc_end
;
3889 ia64_cons_fix_new (frag_now
, where
+ bytes_per_address
,
3890 bytes_per_address
, &e
);
3894 e
.X_op
= O_pseudo_fixup
;
3895 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3897 e
.X_add_symbol
= unwind
.info
;
3898 ia64_cons_fix_new (frag_now
, where
+ (bytes_per_address
* 2),
3899 bytes_per_address
, &e
);
3902 md_number_to_chars (ptr
+ (bytes_per_address
* 2), 0,
3906 subseg_set (saved_seg
, saved_subseg
);
3907 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
3911 dot_template (template)
3914 CURR_SLOT
.user_template
= template;
3919 int dummy ATTRIBUTE_UNUSED
;
3921 int ins
, locs
, outs
, rots
;
3923 if (is_it_end_of_statement ())
3924 ins
= locs
= outs
= rots
= 0;
3927 ins
= get_absolute_expression ();
3928 if (*input_line_pointer
++ != ',')
3930 locs
= get_absolute_expression ();
3931 if (*input_line_pointer
++ != ',')
3933 outs
= get_absolute_expression ();
3934 if (*input_line_pointer
++ != ',')
3936 rots
= get_absolute_expression ();
3938 set_regstack (ins
, locs
, outs
, rots
);
3942 as_bad ("Comma expected");
3943 ignore_rest_of_line ();
3950 unsigned num_regs
, num_alloced
= 0;
3951 struct dynreg
**drpp
, *dr
;
3952 int ch
, base_reg
= 0;
3958 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
3959 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
3960 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
3964 /* First, remove existing names from hash table. */
3965 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
3967 hash_delete (md
.dynreg_hash
, dr
->name
);
3971 drpp
= &md
.dynreg
[type
];
3974 start
= input_line_pointer
;
3975 ch
= get_symbol_end ();
3976 *input_line_pointer
= ch
;
3977 len
= (input_line_pointer
- start
);
3980 if (*input_line_pointer
!= '[')
3982 as_bad ("Expected '['");
3985 ++input_line_pointer
; /* skip '[' */
3987 num_regs
= get_absolute_expression ();
3989 if (*input_line_pointer
++ != ']')
3991 as_bad ("Expected ']'");
3996 num_alloced
+= num_regs
;
4000 if (num_alloced
> md
.rot
.num_regs
)
4002 as_bad ("Used more than the declared %d rotating registers",
4008 if (num_alloced
> 96)
4010 as_bad ("Used more than the available 96 rotating registers");
4015 if (num_alloced
> 48)
4017 as_bad ("Used more than the available 48 rotating registers");
4026 name
= obstack_alloc (¬es
, len
+ 1);
4027 memcpy (name
, start
, len
);
4032 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
4033 memset (*drpp
, 0, sizeof (*dr
));
4038 dr
->num_regs
= num_regs
;
4039 dr
->base
= base_reg
;
4041 base_reg
+= num_regs
;
4043 if (hash_insert (md
.dynreg_hash
, name
, dr
))
4045 as_bad ("Attempt to redefine register set `%s'", name
);
4049 if (*input_line_pointer
!= ',')
4051 ++input_line_pointer
; /* skip comma */
4054 demand_empty_rest_of_line ();
4058 ignore_rest_of_line ();
4062 dot_byteorder (byteorder
)
4065 target_big_endian
= byteorder
;
4070 int dummy ATTRIBUTE_UNUSED
;
4077 option
= input_line_pointer
;
4078 ch
= get_symbol_end ();
4079 if (strcmp (option
, "lsb") == 0)
4080 md
.flags
&= ~EF_IA_64_BE
;
4081 else if (strcmp (option
, "msb") == 0)
4082 md
.flags
|= EF_IA_64_BE
;
4083 else if (strcmp (option
, "abi32") == 0)
4084 md
.flags
&= ~EF_IA_64_ABI64
;
4085 else if (strcmp (option
, "abi64") == 0)
4086 md
.flags
|= EF_IA_64_ABI64
;
4088 as_bad ("Unknown psr option `%s'", option
);
4089 *input_line_pointer
= ch
;
4092 if (*input_line_pointer
!= ',')
4095 ++input_line_pointer
;
4098 demand_empty_rest_of_line ();
4103 int dummy ATTRIBUTE_UNUSED
;
4105 as_bad (".alias not implemented yet");
4110 int dummy ATTRIBUTE_UNUSED
;
4112 new_logical_line (0, get_absolute_expression ());
4113 demand_empty_rest_of_line ();
4117 parse_section_name ()
4123 if (*input_line_pointer
!= '"')
4125 as_bad ("Missing section name");
4126 ignore_rest_of_line ();
4129 name
= demand_copy_C_string (&len
);
4132 ignore_rest_of_line ();
4136 if (*input_line_pointer
!= ',')
4138 as_bad ("Comma expected after section name");
4139 ignore_rest_of_line ();
4142 ++input_line_pointer
; /* skip comma */
4150 char *name
= parse_section_name ();
4156 obj_elf_previous (0);
4159 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
4162 stmt_float_cons (kind
)
4169 case 'd': size
= 8; break;
4170 case 'x': size
= 10; break;
4177 ia64_do_align (size
);
4185 int saved_auto_align
= md
.auto_align
;
4189 md
.auto_align
= saved_auto_align
;
4193 dot_xfloat_cons (kind
)
4196 char *name
= parse_section_name ();
4201 stmt_float_cons (kind
);
4202 obj_elf_previous (0);
4206 dot_xstringer (zero
)
4209 char *name
= parse_section_name ();
4215 obj_elf_previous (0);
4222 int saved_auto_align
= md
.auto_align
;
4223 char *name
= parse_section_name ();
4230 md
.auto_align
= saved_auto_align
;
4231 obj_elf_previous (0);
4235 dot_xfloat_cons_ua (kind
)
4238 int saved_auto_align
= md
.auto_align
;
4239 char *name
= parse_section_name ();
4245 stmt_float_cons (kind
);
4246 md
.auto_align
= saved_auto_align
;
4247 obj_elf_previous (0);
4250 /* .reg.val <regname>,value */
4254 int dummy ATTRIBUTE_UNUSED
;
4259 if (reg
.X_op
!= O_register
)
4261 as_bad (_("Register name expected"));
4262 ignore_rest_of_line ();
4264 else if (*input_line_pointer
++ != ',')
4266 as_bad (_("Comma expected"));
4267 ignore_rest_of_line ();
4271 valueT value
= get_absolute_expression ();
4272 int regno
= reg
.X_add_number
;
4273 if (regno
< REG_GR
|| regno
> REG_GR
+ 128)
4274 as_warn (_("Register value annotation ignored"));
4277 gr_values
[regno
- REG_GR
].known
= 1;
4278 gr_values
[regno
- REG_GR
].value
= value
;
4279 gr_values
[regno
- REG_GR
].path
= md
.path
;
4282 demand_empty_rest_of_line ();
4285 /* select dv checking mode
4290 A stop is inserted when changing modes
4297 if (md
.manual_bundling
)
4298 as_warn (_("Directive invalid within a bundle"));
4300 if (type
== 'E' || type
== 'A')
4301 md
.mode_explicitly_set
= 0;
4303 md
.mode_explicitly_set
= 1;
4310 if (md
.explicit_mode
)
4311 insn_group_break (1, 0, 0);
4312 md
.explicit_mode
= 0;
4316 if (!md
.explicit_mode
)
4317 insn_group_break (1, 0, 0);
4318 md
.explicit_mode
= 1;
4322 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4323 insn_group_break (1, 0, 0);
4324 md
.explicit_mode
= md
.default_explicit_mode
;
4325 md
.mode_explicitly_set
= 0;
4336 for (regno
= 0; regno
< 64; regno
++)
4338 if (mask
& ((valueT
) 1 << regno
))
4340 fprintf (stderr
, "%s p%d", comma
, regno
);
4347 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4348 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4349 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4350 .pred.safe_across_calls p1 [, p2 [,...]]
4359 int p1
= -1, p2
= -1;
4363 if (*input_line_pointer
!= '"')
4365 as_bad (_("Missing predicate relation type"));
4366 ignore_rest_of_line ();
4372 char *form
= demand_copy_C_string (&len
);
4373 if (strcmp (form
, "mutex") == 0)
4375 else if (strcmp (form
, "clear") == 0)
4377 else if (strcmp (form
, "imply") == 0)
4381 as_bad (_("Unrecognized predicate relation type"));
4382 ignore_rest_of_line ();
4386 if (*input_line_pointer
== ',')
4387 ++input_line_pointer
;
4397 if (toupper (*input_line_pointer
) != 'P'
4398 || (regno
= atoi (++input_line_pointer
)) < 0
4401 as_bad (_("Predicate register expected"));
4402 ignore_rest_of_line ();
4405 while (isdigit (*input_line_pointer
))
4406 ++input_line_pointer
;
4413 as_warn (_("Duplicate predicate register ignored"));
4416 /* See if it's a range. */
4417 if (*input_line_pointer
== '-')
4420 ++input_line_pointer
;
4422 if (toupper (*input_line_pointer
) != 'P'
4423 || (regno
= atoi (++input_line_pointer
)) < 0
4426 as_bad (_("Predicate register expected"));
4427 ignore_rest_of_line ();
4430 while (isdigit (*input_line_pointer
))
4431 ++input_line_pointer
;
4435 as_bad (_("Bad register range"));
4436 ignore_rest_of_line ();
4447 if (*input_line_pointer
!= ',')
4449 ++input_line_pointer
;
4458 clear_qp_mutex (mask
);
4459 clear_qp_implies (mask
, (valueT
) 0);
4462 if (count
!= 2 || p1
== -1 || p2
== -1)
4463 as_bad (_("Predicate source and target required"));
4464 else if (p1
== 0 || p2
== 0)
4465 as_bad (_("Use of p0 is not valid in this context"));
4467 add_qp_imply (p1
, p2
);
4472 as_bad (_("At least two PR arguments expected"));
4477 as_bad (_("Use of p0 is not valid in this context"));
4480 add_qp_mutex (mask
);
4483 /* note that we don't override any existing relations */
4486 as_bad (_("At least one PR argument expected"));
4491 fprintf (stderr
, "Safe across calls: ");
4492 print_prmask (mask
);
4493 fprintf (stderr
, "\n");
4495 qp_safe_across_calls
= mask
;
4498 demand_empty_rest_of_line ();
4501 /* .entry label [, label [, ...]]
4502 Hint to DV code that the given labels are to be considered entry points.
4503 Otherwise, only global labels are considered entry points. */
4507 int dummy ATTRIBUTE_UNUSED
;
4516 name
= input_line_pointer
;
4517 c
= get_symbol_end ();
4518 symbolP
= symbol_find_or_make (name
);
4520 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4522 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4525 *input_line_pointer
= c
;
4527 c
= *input_line_pointer
;
4530 input_line_pointer
++;
4532 if (*input_line_pointer
== '\n')
4538 demand_empty_rest_of_line ();
4541 /* .mem.offset offset, base
4542 "base" is used to distinguish between offsets from a different base. */
4545 dot_mem_offset (dummy
)
4546 int dummy ATTRIBUTE_UNUSED
;
4548 md
.mem_offset
.hint
= 1;
4549 md
.mem_offset
.offset
= get_absolute_expression ();
4550 if (*input_line_pointer
!= ',')
4552 as_bad (_("Comma expected"));
4553 ignore_rest_of_line ();
4556 ++input_line_pointer
;
4557 md
.mem_offset
.base
= get_absolute_expression ();
4558 demand_empty_rest_of_line ();
4561 /* ia64-specific pseudo-ops: */
4562 const pseudo_typeS md_pseudo_table
[] =
4564 { "radix", dot_radix
, 0 },
4565 { "lcomm", s_lcomm_bytes
, 1 },
4566 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4567 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4568 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4569 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4570 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4571 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4572 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4573 { "proc", dot_proc
, 0 },
4574 { "body", dot_body
, 0 },
4575 { "prologue", dot_prologue
, 0 },
4576 { "endp", dot_endp
, 0 },
4577 { "file", dwarf2_directive_file
, 0 },
4578 { "loc", dwarf2_directive_loc
, 0 },
4580 { "fframe", dot_fframe
, 0 },
4581 { "vframe", dot_vframe
, 0 },
4582 { "vframesp", dot_vframesp
, 0 },
4583 { "vframepsp", dot_vframepsp
, 0 },
4584 { "save", dot_save
, 0 },
4585 { "restore", dot_restore
, 0 },
4586 { "restorereg", dot_restorereg
, 0 },
4587 { "restorereg.p", dot_restorereg_p
, 0 },
4588 { "handlerdata", dot_handlerdata
, 0 },
4589 { "unwentry", dot_unwentry
, 0 },
4590 { "altrp", dot_altrp
, 0 },
4591 { "savesp", dot_savemem
, 0 },
4592 { "savepsp", dot_savemem
, 1 },
4593 { "save.g", dot_saveg
, 0 },
4594 { "save.f", dot_savef
, 0 },
4595 { "save.b", dot_saveb
, 0 },
4596 { "save.gf", dot_savegf
, 0 },
4597 { "spill", dot_spill
, 0 },
4598 { "spillreg", dot_spillreg
, 0 },
4599 { "spillsp", dot_spillmem
, 0 },
4600 { "spillpsp", dot_spillmem
, 1 },
4601 { "spillreg.p", dot_spillreg_p
, 0 },
4602 { "spillsp.p", dot_spillmem_p
, 0 },
4603 { "spillpsp.p", dot_spillmem_p
, 1 },
4604 { "label_state", dot_label_state
, 0 },
4605 { "copy_state", dot_copy_state
, 0 },
4606 { "unwabi", dot_unwabi
, 0 },
4607 { "personality", dot_personality
, 0 },
4609 { "estate", dot_estate
, 0 },
4611 { "mii", dot_template
, 0x0 },
4612 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4613 { "mlx", dot_template
, 0x2 },
4614 { "mmi", dot_template
, 0x4 },
4615 { "mfi", dot_template
, 0x6 },
4616 { "mmf", dot_template
, 0x7 },
4617 { "mib", dot_template
, 0x8 },
4618 { "mbb", dot_template
, 0x9 },
4619 { "bbb", dot_template
, 0xb },
4620 { "mmb", dot_template
, 0xc },
4621 { "mfb", dot_template
, 0xe },
4623 { "lb", dot_scope
, 0 },
4624 { "le", dot_scope
, 1 },
4626 { "align", s_align_bytes
, 0 },
4627 { "regstk", dot_regstk
, 0 },
4628 { "rotr", dot_rot
, DYNREG_GR
},
4629 { "rotf", dot_rot
, DYNREG_FR
},
4630 { "rotp", dot_rot
, DYNREG_PR
},
4631 { "lsb", dot_byteorder
, 0 },
4632 { "msb", dot_byteorder
, 1 },
4633 { "psr", dot_psr
, 0 },
4634 { "alias", dot_alias
, 0 },
4635 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4637 { "xdata1", dot_xdata
, 1 },
4638 { "xdata2", dot_xdata
, 2 },
4639 { "xdata4", dot_xdata
, 4 },
4640 { "xdata8", dot_xdata
, 8 },
4641 { "xreal4", dot_xfloat_cons
, 'f' },
4642 { "xreal8", dot_xfloat_cons
, 'd' },
4643 { "xreal10", dot_xfloat_cons
, 'x' },
4644 { "xstring", dot_xstringer
, 0 },
4645 { "xstringz", dot_xstringer
, 1 },
4647 /* unaligned versions: */
4648 { "xdata2.ua", dot_xdata_ua
, 2 },
4649 { "xdata4.ua", dot_xdata_ua
, 4 },
4650 { "xdata8.ua", dot_xdata_ua
, 8 },
4651 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4652 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4653 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4655 /* annotations/DV checking support */
4656 { "entry", dot_entry
, 0 },
4657 { "mem.offset", dot_mem_offset
, 0 },
4658 { "pred.rel", dot_pred_rel
, 0 },
4659 { "pred.rel.clear", dot_pred_rel
, 'c' },
4660 { "pred.rel.imply", dot_pred_rel
, 'i' },
4661 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4662 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4663 { "reg.val", dot_reg_val
, 0 },
4664 { "auto", dot_dv_mode
, 'a' },
4665 { "explicit", dot_dv_mode
, 'e' },
4666 { "default", dot_dv_mode
, 'd' },
4671 static const struct pseudo_opcode
4674 void (*handler
) (int);
4679 /* these are more like pseudo-ops, but don't start with a dot */
4680 { "data1", cons
, 1 },
4681 { "data2", cons
, 2 },
4682 { "data4", cons
, 4 },
4683 { "data8", cons
, 8 },
4684 { "real4", stmt_float_cons
, 'f' },
4685 { "real8", stmt_float_cons
, 'd' },
4686 { "real10", stmt_float_cons
, 'x' },
4687 { "string", stringer
, 0 },
4688 { "stringz", stringer
, 1 },
4690 /* unaligned versions: */
4691 { "data2.ua", stmt_cons_ua
, 2 },
4692 { "data4.ua", stmt_cons_ua
, 4 },
4693 { "data8.ua", stmt_cons_ua
, 8 },
4694 { "real4.ua", float_cons
, 'f' },
4695 { "real8.ua", float_cons
, 'd' },
4696 { "real10.ua", float_cons
, 'x' },
4699 /* Declare a register by creating a symbol for it and entering it in
4700 the symbol table. */
4703 declare_register (name
, regnum
)
4710 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4712 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4714 as_fatal ("Inserting \"%s\" into register table failed: %s",
4721 declare_register_set (prefix
, num_regs
, base_regnum
)
4729 for (i
= 0; i
< num_regs
; ++i
)
4731 sprintf (name
, "%s%u", prefix
, i
);
4732 declare_register (name
, base_regnum
+ i
);
4737 operand_width (opnd
)
4738 enum ia64_opnd opnd
;
4740 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
4741 unsigned int bits
= 0;
4745 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
4746 bits
+= odesc
->field
[i
].bits
;
4751 static enum operand_match_result
4752 operand_match (idesc
, index
, e
)
4753 const struct ia64_opcode
*idesc
;
4757 enum ia64_opnd opnd
= idesc
->operands
[index
];
4758 int bits
, relocatable
= 0;
4759 struct insn_fix
*fix
;
4766 case IA64_OPND_AR_CCV
:
4767 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
4768 return OPERAND_MATCH
;
4771 case IA64_OPND_AR_PFS
:
4772 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
4773 return OPERAND_MATCH
;
4777 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
4778 return OPERAND_MATCH
;
4782 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
4783 return OPERAND_MATCH
;
4787 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
4788 return OPERAND_MATCH
;
4791 case IA64_OPND_PR_ROT
:
4792 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
4793 return OPERAND_MATCH
;
4797 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
4798 return OPERAND_MATCH
;
4801 case IA64_OPND_PSR_L
:
4802 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
4803 return OPERAND_MATCH
;
4806 case IA64_OPND_PSR_UM
:
4807 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
4808 return OPERAND_MATCH
;
4812 if (e
->X_op
== O_constant
)
4814 if (e
->X_add_number
== 1)
4815 return OPERAND_MATCH
;
4817 return OPERAND_OUT_OF_RANGE
;
4822 if (e
->X_op
== O_constant
)
4824 if (e
->X_add_number
== 8)
4825 return OPERAND_MATCH
;
4827 return OPERAND_OUT_OF_RANGE
;
4832 if (e
->X_op
== O_constant
)
4834 if (e
->X_add_number
== 16)
4835 return OPERAND_MATCH
;
4837 return OPERAND_OUT_OF_RANGE
;
4841 /* register operands: */
4844 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
4845 && e
->X_add_number
< REG_AR
+ 128)
4846 return OPERAND_MATCH
;
4851 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
4852 && e
->X_add_number
< REG_BR
+ 8)
4853 return OPERAND_MATCH
;
4857 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
4858 && e
->X_add_number
< REG_CR
+ 128)
4859 return OPERAND_MATCH
;
4866 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
4867 && e
->X_add_number
< REG_FR
+ 128)
4868 return OPERAND_MATCH
;
4873 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
4874 && e
->X_add_number
< REG_P
+ 64)
4875 return OPERAND_MATCH
;
4881 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4882 && e
->X_add_number
< REG_GR
+ 128)
4883 return OPERAND_MATCH
;
4886 case IA64_OPND_R3_2
:
4887 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
)
4889 if (e
->X_add_number
< REG_GR
+ 4)
4890 return OPERAND_MATCH
;
4891 else if (e
->X_add_number
< REG_GR
+ 128)
4892 return OPERAND_OUT_OF_RANGE
;
4896 /* indirect operands: */
4897 case IA64_OPND_CPUID_R3
:
4898 case IA64_OPND_DBR_R3
:
4899 case IA64_OPND_DTR_R3
:
4900 case IA64_OPND_ITR_R3
:
4901 case IA64_OPND_IBR_R3
:
4902 case IA64_OPND_MSR_R3
:
4903 case IA64_OPND_PKR_R3
:
4904 case IA64_OPND_PMC_R3
:
4905 case IA64_OPND_PMD_R3
:
4906 case IA64_OPND_RR_R3
:
4907 if (e
->X_op
== O_index
&& e
->X_op_symbol
4908 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
4909 == opnd
- IA64_OPND_CPUID_R3
))
4910 return OPERAND_MATCH
;
4914 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
4915 return OPERAND_MATCH
;
4918 /* immediate operands: */
4919 case IA64_OPND_CNT2a
:
4920 case IA64_OPND_LEN4
:
4921 case IA64_OPND_LEN6
:
4922 bits
= operand_width (idesc
->operands
[index
]);
4923 if (e
->X_op
== O_constant
)
4925 if ((bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
4926 return OPERAND_MATCH
;
4928 return OPERAND_OUT_OF_RANGE
;
4932 case IA64_OPND_CNT2b
:
4933 if (e
->X_op
== O_constant
)
4935 if ((bfd_vma
) (e
->X_add_number
- 1) < 3)
4936 return OPERAND_MATCH
;
4938 return OPERAND_OUT_OF_RANGE
;
4942 case IA64_OPND_CNT2c
:
4943 val
= e
->X_add_number
;
4944 if (e
->X_op
== O_constant
)
4946 if ((val
== 0 || val
== 7 || val
== 15 || val
== 16))
4947 return OPERAND_MATCH
;
4949 return OPERAND_OUT_OF_RANGE
;
4954 /* SOR must be an integer multiple of 8 */
4955 if (e
->X_op
== O_constant
&& e
->X_add_number
& 0x7)
4956 return OPERAND_OUT_OF_RANGE
;
4959 if (e
->X_op
== O_constant
)
4961 if ((bfd_vma
) e
->X_add_number
<= 96)
4962 return OPERAND_MATCH
;
4964 return OPERAND_OUT_OF_RANGE
;
4968 case IA64_OPND_IMMU62
:
4969 if (e
->X_op
== O_constant
)
4971 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
4972 return OPERAND_MATCH
;
4974 return OPERAND_OUT_OF_RANGE
;
4978 /* FIXME -- need 62-bit relocation type */
4979 as_bad (_("62-bit relocation not yet implemented"));
4983 case IA64_OPND_IMMU64
:
4984 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
4985 || e
->X_op
== O_subtract
)
4987 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4988 fix
->code
= BFD_RELOC_IA64_IMM64
;
4989 if (e
->X_op
!= O_subtract
)
4991 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4992 if (e
->X_op
== O_pseudo_fixup
)
4996 fix
->opnd
= idesc
->operands
[index
];
4999 ++CURR_SLOT
.num_fixups
;
5000 return OPERAND_MATCH
;
5002 else if (e
->X_op
== O_constant
)
5003 return OPERAND_MATCH
;
5006 case IA64_OPND_CCNT5
:
5007 case IA64_OPND_CNT5
:
5008 case IA64_OPND_CNT6
:
5009 case IA64_OPND_CPOS6a
:
5010 case IA64_OPND_CPOS6b
:
5011 case IA64_OPND_CPOS6c
:
5012 case IA64_OPND_IMMU2
:
5013 case IA64_OPND_IMMU7a
:
5014 case IA64_OPND_IMMU7b
:
5015 case IA64_OPND_IMMU21
:
5016 case IA64_OPND_IMMU24
:
5017 case IA64_OPND_MBTYPE4
:
5018 case IA64_OPND_MHTYPE8
:
5019 case IA64_OPND_POS6
:
5020 bits
= operand_width (idesc
->operands
[index
]);
5021 if (e
->X_op
== O_constant
)
5023 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5024 return OPERAND_MATCH
;
5026 return OPERAND_OUT_OF_RANGE
;
5030 case IA64_OPND_IMMU9
:
5031 bits
= operand_width (idesc
->operands
[index
]);
5032 if (e
->X_op
== O_constant
)
5034 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5036 int lobits
= e
->X_add_number
& 0x3;
5037 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
5038 e
->X_add_number
|= (bfd_vma
) 0x3;
5039 return OPERAND_MATCH
;
5042 return OPERAND_OUT_OF_RANGE
;
5046 case IA64_OPND_IMM44
:
5047 /* least 16 bits must be zero */
5048 if ((e
->X_add_number
& 0xffff) != 0)
5049 /* XXX technically, this is wrong: we should not be issuing warning
5050 messages until we're sure this instruction pattern is going to
5052 as_warn (_("lower 16 bits of mask ignored"));
5054 if (e
->X_op
== O_constant
)
5056 if (((e
->X_add_number
>= 0
5057 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 44))
5058 || (e
->X_add_number
< 0
5059 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
5062 if (e
->X_add_number
>= 0
5063 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
5065 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
5067 return OPERAND_MATCH
;
5070 return OPERAND_OUT_OF_RANGE
;
5074 case IA64_OPND_IMM17
:
5075 /* bit 0 is a don't care (pr0 is hardwired to 1) */
5076 if (e
->X_op
== O_constant
)
5078 if (((e
->X_add_number
>= 0
5079 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 17))
5080 || (e
->X_add_number
< 0
5081 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
5084 if (e
->X_add_number
>= 0
5085 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
5087 e
->X_add_number
|= ~(((bfd_vma
) 1 << 17) - 1);
5089 return OPERAND_MATCH
;
5092 return OPERAND_OUT_OF_RANGE
;
5096 case IA64_OPND_IMM14
:
5097 case IA64_OPND_IMM22
:
5099 case IA64_OPND_IMM1
:
5100 case IA64_OPND_IMM8
:
5101 case IA64_OPND_IMM8U4
:
5102 case IA64_OPND_IMM8M1
:
5103 case IA64_OPND_IMM8M1U4
:
5104 case IA64_OPND_IMM8M1U8
:
5105 case IA64_OPND_IMM9a
:
5106 case IA64_OPND_IMM9b
:
5107 bits
= operand_width (idesc
->operands
[index
]);
5108 if (relocatable
&& (e
->X_op
== O_symbol
5109 || e
->X_op
== O_subtract
5110 || e
->X_op
== O_pseudo_fixup
))
5112 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5114 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
5115 fix
->code
= BFD_RELOC_IA64_IMM14
;
5117 fix
->code
= BFD_RELOC_IA64_IMM22
;
5119 if (e
->X_op
!= O_subtract
)
5121 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5122 if (e
->X_op
== O_pseudo_fixup
)
5126 fix
->opnd
= idesc
->operands
[index
];
5129 ++CURR_SLOT
.num_fixups
;
5130 return OPERAND_MATCH
;
5132 else if (e
->X_op
!= O_constant
5133 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
5134 return OPERAND_MISMATCH
;
5136 if (opnd
== IA64_OPND_IMM8M1U4
)
5138 /* Zero is not valid for unsigned compares that take an adjusted
5139 constant immediate range. */
5140 if (e
->X_add_number
== 0)
5141 return OPERAND_OUT_OF_RANGE
;
5143 /* Sign-extend 32-bit unsigned numbers, so that the following range
5144 checks will work. */
5145 val
= e
->X_add_number
;
5146 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5147 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5148 val
= ((val
<< 32) >> 32);
5150 /* Check for 0x100000000. This is valid because
5151 0x100000000-1 is the same as ((uint32_t) -1). */
5152 if (val
== ((bfd_signed_vma
) 1 << 32))
5153 return OPERAND_MATCH
;
5157 else if (opnd
== IA64_OPND_IMM8M1U8
)
5159 /* Zero is not valid for unsigned compares that take an adjusted
5160 constant immediate range. */
5161 if (e
->X_add_number
== 0)
5162 return OPERAND_OUT_OF_RANGE
;
5164 /* Check for 0x10000000000000000. */
5165 if (e
->X_op
== O_big
)
5167 if (generic_bignum
[0] == 0
5168 && generic_bignum
[1] == 0
5169 && generic_bignum
[2] == 0
5170 && generic_bignum
[3] == 0
5171 && generic_bignum
[4] == 1)
5172 return OPERAND_MATCH
;
5174 return OPERAND_OUT_OF_RANGE
;
5177 val
= e
->X_add_number
- 1;
5179 else if (opnd
== IA64_OPND_IMM8M1
)
5180 val
= e
->X_add_number
- 1;
5181 else if (opnd
== IA64_OPND_IMM8U4
)
5183 /* Sign-extend 32-bit unsigned numbers, so that the following range
5184 checks will work. */
5185 val
= e
->X_add_number
;
5186 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5187 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5188 val
= ((val
<< 32) >> 32);
5191 val
= e
->X_add_number
;
5193 if ((val
>= 0 && (bfd_vma
) val
< ((bfd_vma
) 1 << (bits
- 1)))
5194 || (val
< 0 && (bfd_vma
) -val
<= ((bfd_vma
) 1 << (bits
- 1))))
5195 return OPERAND_MATCH
;
5197 return OPERAND_OUT_OF_RANGE
;
5199 case IA64_OPND_INC3
:
5200 /* +/- 1, 4, 8, 16 */
5201 val
= e
->X_add_number
;
5204 if (e
->X_op
== O_constant
)
5206 if ((val
== 1 || val
== 4 || val
== 8 || val
== 16))
5207 return OPERAND_MATCH
;
5209 return OPERAND_OUT_OF_RANGE
;
5213 case IA64_OPND_TGT25
:
5214 case IA64_OPND_TGT25b
:
5215 case IA64_OPND_TGT25c
:
5216 case IA64_OPND_TGT64
:
5217 if (e
->X_op
== O_symbol
)
5219 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5220 if (opnd
== IA64_OPND_TGT25
)
5221 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
5222 else if (opnd
== IA64_OPND_TGT25b
)
5223 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
5224 else if (opnd
== IA64_OPND_TGT25c
)
5225 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
5226 else if (opnd
== IA64_OPND_TGT64
)
5227 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
5231 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5232 fix
->opnd
= idesc
->operands
[index
];
5235 ++CURR_SLOT
.num_fixups
;
5236 return OPERAND_MATCH
;
5238 case IA64_OPND_TAG13
:
5239 case IA64_OPND_TAG13b
:
5243 return OPERAND_MATCH
;
5246 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5247 /* There are no external relocs for TAG13/TAG13b fields, so we
5248 create a dummy reloc. This will not live past md_apply_fix3. */
5249 fix
->code
= BFD_RELOC_UNUSED
;
5250 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5251 fix
->opnd
= idesc
->operands
[index
];
5254 ++CURR_SLOT
.num_fixups
;
5255 return OPERAND_MATCH
;
5265 return OPERAND_MISMATCH
;
5274 memset (e
, 0, sizeof (*e
));
5277 if (*input_line_pointer
!= '}')
5279 sep
= *input_line_pointer
++;
5283 if (!md
.manual_bundling
)
5284 as_warn ("Found '}' when manual bundling is off");
5286 CURR_SLOT
.manual_bundling_off
= 1;
5287 md
.manual_bundling
= 0;
5293 /* Returns the next entry in the opcode table that matches the one in
5294 IDESC, and frees the entry in IDESC. If no matching entry is
5295 found, NULL is returned instead. */
5297 static struct ia64_opcode
*
5298 get_next_opcode (struct ia64_opcode
*idesc
)
5300 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
5301 ia64_free_opcode (idesc
);
5305 /* Parse the operands for the opcode and find the opcode variant that
5306 matches the specified operands, or NULL if no match is possible. */
5308 static struct ia64_opcode
*
5309 parse_operands (idesc
)
5310 struct ia64_opcode
*idesc
;
5312 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
5313 int error_pos
, out_of_range_pos
, curr_out_of_range_pos
, sep
= 0;
5314 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
5315 enum operand_match_result result
;
5317 char *first_arg
= 0, *end
, *saved_input_pointer
;
5320 assert (strlen (idesc
->name
) <= 128);
5322 strcpy (mnemonic
, idesc
->name
);
5323 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5325 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5326 can't parse the first operand until we have parsed the
5327 remaining operands of the "alloc" instruction. */
5329 first_arg
= input_line_pointer
;
5330 end
= strchr (input_line_pointer
, '=');
5333 as_bad ("Expected separator `='");
5336 input_line_pointer
= end
+ 1;
5341 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
5343 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
5344 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
5349 if (sep
!= '=' && sep
!= ',')
5354 if (num_outputs
> 0)
5355 as_bad ("Duplicate equal sign (=) in instruction");
5357 num_outputs
= i
+ 1;
5362 as_bad ("Illegal operand separator `%c'", sep
);
5366 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5368 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5369 know (strcmp (idesc
->name
, "alloc") == 0);
5370 if (num_operands
== 5 /* first_arg not included in this count! */
5371 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5372 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5373 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5374 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5376 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5377 CURR_SLOT
.opnd
[3].X_add_number
,
5378 CURR_SLOT
.opnd
[4].X_add_number
,
5379 CURR_SLOT
.opnd
[5].X_add_number
);
5381 /* now we can parse the first arg: */
5382 saved_input_pointer
= input_line_pointer
;
5383 input_line_pointer
= first_arg
;
5384 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5386 --num_outputs
; /* force error */
5387 input_line_pointer
= saved_input_pointer
;
5389 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5390 CURR_SLOT
.opnd
[3].X_add_number
5391 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5392 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5396 highest_unmatched_operand
= 0;
5397 curr_out_of_range_pos
= -1;
5399 expected_operand
= idesc
->operands
[0];
5400 for (; idesc
; idesc
= get_next_opcode (idesc
))
5402 if (num_outputs
!= idesc
->num_outputs
)
5403 continue; /* mismatch in # of outputs */
5405 CURR_SLOT
.num_fixups
= 0;
5407 /* Try to match all operands. If we see an out-of-range operand,
5408 then continue trying to match the rest of the operands, since if
5409 the rest match, then this idesc will give the best error message. */
5411 out_of_range_pos
= -1;
5412 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5414 result
= operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
);
5415 if (result
!= OPERAND_MATCH
)
5417 if (result
!= OPERAND_OUT_OF_RANGE
)
5419 if (out_of_range_pos
< 0)
5420 /* remember position of the first out-of-range operand: */
5421 out_of_range_pos
= i
;
5425 /* If we did not match all operands, or if at least one operand was
5426 out-of-range, then this idesc does not match. Keep track of which
5427 idesc matched the most operands before failing. If we have two
5428 idescs that failed at the same position, and one had an out-of-range
5429 operand, then prefer the out-of-range operand. Thus if we have
5430 "add r0=0x1000000,r1" we get an error saying the constant is out
5431 of range instead of an error saying that the constant should have been
5434 if (i
!= num_operands
|| out_of_range_pos
>= 0)
5436 if (i
> highest_unmatched_operand
5437 || (i
== highest_unmatched_operand
5438 && out_of_range_pos
> curr_out_of_range_pos
))
5440 highest_unmatched_operand
= i
;
5441 if (out_of_range_pos
>= 0)
5443 expected_operand
= idesc
->operands
[out_of_range_pos
];
5444 error_pos
= out_of_range_pos
;
5448 expected_operand
= idesc
->operands
[i
];
5451 curr_out_of_range_pos
= out_of_range_pos
;
5456 if (num_operands
< NELEMS (idesc
->operands
)
5457 && idesc
->operands
[num_operands
])
5458 continue; /* mismatch in number of arguments */
5464 if (expected_operand
)
5465 as_bad ("Operand %u of `%s' should be %s",
5466 error_pos
+ 1, mnemonic
,
5467 elf64_ia64_operands
[expected_operand
].desc
);
5469 as_bad ("Operand mismatch");
5475 /* Keep track of state necessary to determine whether a NOP is necessary
5476 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5477 detect a case where additional NOPs may be necessary. */
5479 errata_nop_necessary_p (slot
, insn_unit
)
5481 enum ia64_unit insn_unit
;
5484 struct group
*this_group
= md
.last_groups
+ md
.group_idx
;
5485 struct group
*prev_group
= md
.last_groups
+ (md
.group_idx
+ 2) % 3;
5486 struct ia64_opcode
*idesc
= slot
->idesc
;
5488 /* Test whether this could be the first insn in a problematic sequence. */
5489 if (insn_unit
== IA64_UNIT_F
)
5491 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5492 if (idesc
->operands
[i
] == IA64_OPND_P1
5493 || idesc
->operands
[i
] == IA64_OPND_P2
)
5495 int regno
= slot
->opnd
[i
].X_add_number
- REG_P
;
5496 /* Ignore invalid operands; they generate errors elsewhere. */
5499 this_group
->p_reg_set
[regno
] = 1;
5503 /* Test whether this could be the second insn in a problematic sequence. */
5504 if (insn_unit
== IA64_UNIT_M
&& slot
->qp_regno
> 0
5505 && prev_group
->p_reg_set
[slot
->qp_regno
])
5507 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5508 if (idesc
->operands
[i
] == IA64_OPND_R1
5509 || idesc
->operands
[i
] == IA64_OPND_R2
5510 || idesc
->operands
[i
] == IA64_OPND_R3
)
5512 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5513 /* Ignore invalid operands; they generate errors elsewhere. */
5516 if (strncmp (idesc
->name
, "add", 3) != 0
5517 && strncmp (idesc
->name
, "sub", 3) != 0
5518 && strncmp (idesc
->name
, "shladd", 6) != 0
5519 && (idesc
->flags
& IA64_OPCODE_POSTINC
) == 0)
5520 this_group
->g_reg_set_conditionally
[regno
] = 1;
5524 /* Test whether this could be the third insn in a problematic sequence. */
5525 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; i
++)
5527 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5528 idesc
->operands
[i
] == IA64_OPND_R3
5529 /* For mov indirect. */
5530 || idesc
->operands
[i
] == IA64_OPND_RR_R3
5531 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
5532 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
5533 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
5534 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
5535 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
5536 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
5537 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
5539 || idesc
->operands
[i
] == IA64_OPND_ITR_R3
5540 || idesc
->operands
[i
] == IA64_OPND_DTR_R3
5541 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5542 || idesc
->operands
[i
] == IA64_OPND_MR3
)
5544 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5545 /* Ignore invalid operands; they generate errors elsewhere. */
5548 if (idesc
->operands
[i
] == IA64_OPND_R3
)
5550 if (strcmp (idesc
->name
, "fc") != 0
5551 && strcmp (idesc
->name
, "tak") != 0
5552 && strcmp (idesc
->name
, "thash") != 0
5553 && strcmp (idesc
->name
, "tpa") != 0
5554 && strcmp (idesc
->name
, "ttag") != 0
5555 && strncmp (idesc
->name
, "ptr", 3) != 0
5556 && strncmp (idesc
->name
, "ptc", 3) != 0
5557 && strncmp (idesc
->name
, "probe", 5) != 0)
5560 if (prev_group
->g_reg_set_conditionally
[regno
])
5568 build_insn (slot
, insnp
)
5572 const struct ia64_operand
*odesc
, *o2desc
;
5573 struct ia64_opcode
*idesc
= slot
->idesc
;
5574 bfd_signed_vma insn
, val
;
5578 insn
= idesc
->opcode
| slot
->qp_regno
;
5580 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5582 if (slot
->opnd
[i
].X_op
== O_register
5583 || slot
->opnd
[i
].X_op
== O_constant
5584 || slot
->opnd
[i
].X_op
== O_index
)
5585 val
= slot
->opnd
[i
].X_add_number
;
5586 else if (slot
->opnd
[i
].X_op
== O_big
)
5588 /* This must be the value 0x10000000000000000. */
5589 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5595 switch (idesc
->operands
[i
])
5597 case IA64_OPND_IMMU64
:
5598 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5599 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5600 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5601 | (((val
>> 63) & 0x1) << 36));
5604 case IA64_OPND_IMMU62
:
5605 val
&= 0x3fffffffffffffffULL
;
5606 if (val
!= slot
->opnd
[i
].X_add_number
)
5607 as_warn (_("Value truncated to 62 bits"));
5608 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5609 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5612 case IA64_OPND_TGT64
:
5614 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5615 insn
|= ((((val
>> 59) & 0x1) << 36)
5616 | (((val
>> 0) & 0xfffff) << 13));
5647 case IA64_OPND_R3_2
:
5648 case IA64_OPND_CPUID_R3
:
5649 case IA64_OPND_DBR_R3
:
5650 case IA64_OPND_DTR_R3
:
5651 case IA64_OPND_ITR_R3
:
5652 case IA64_OPND_IBR_R3
:
5654 case IA64_OPND_MSR_R3
:
5655 case IA64_OPND_PKR_R3
:
5656 case IA64_OPND_PMC_R3
:
5657 case IA64_OPND_PMD_R3
:
5658 case IA64_OPND_RR_R3
:
5666 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5667 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5669 as_bad_where (slot
->src_file
, slot
->src_line
,
5670 "Bad operand value: %s", err
);
5671 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5673 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5674 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5676 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5677 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5679 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5680 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5681 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5683 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5684 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5694 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5695 unsigned int manual_bundling
= 0;
5696 enum ia64_unit required_unit
, insn_unit
= 0;
5697 enum ia64_insn_type type
[3], insn_type
;
5698 unsigned int template, orig_template
;
5699 bfd_vma insn
[3] = { -1, -1, -1 };
5700 struct ia64_opcode
*idesc
;
5701 int end_of_insn_group
= 0, user_template
= -1;
5702 int n
, i
, j
, first
, curr
;
5704 bfd_vma t0
= 0, t1
= 0;
5705 struct label_fix
*lfix
;
5706 struct insn_fix
*ifix
;
5711 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5712 know (first
>= 0 & first
< NUM_SLOTS
);
5713 n
= MIN (3, md
.num_slots_in_use
);
5715 /* Determine template: user user_template if specified, best match
5718 if (md
.slot
[first
].user_template
>= 0)
5719 user_template
= template = md
.slot
[first
].user_template
;
5722 /* Auto select appropriate template. */
5723 memset (type
, 0, sizeof (type
));
5725 for (i
= 0; i
< n
; ++i
)
5727 if (md
.slot
[curr
].label_fixups
&& i
!= 0)
5729 type
[i
] = md
.slot
[curr
].idesc
->type
;
5730 curr
= (curr
+ 1) % NUM_SLOTS
;
5732 template = best_template
[type
[0]][type
[1]][type
[2]];
5735 /* initialize instructions with appropriate nops: */
5736 for (i
= 0; i
< 3; ++i
)
5737 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
5741 /* now fill in slots with as many insns as possible: */
5743 idesc
= md
.slot
[curr
].idesc
;
5744 end_of_insn_group
= 0;
5745 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
5747 /* Set the slot number for prologue/body records now as those
5748 refer to the current point, not the point after the
5749 instruction has been issued: */
5750 /* Don't try to delete prologue/body records here, as that will cause
5751 them to also be deleted from the master list of unwind records. */
5752 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5753 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
5754 || ptr
->r
.type
== body
)
5756 ptr
->slot_number
= (unsigned long) f
+ i
;
5757 ptr
->slot_frag
= frag_now
;
5760 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
5762 if (manual_bundling
&& i
!= 2)
5763 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5764 "`%s' must be last in bundle", idesc
->name
);
5768 if (idesc
->flags
& IA64_OPCODE_LAST
)
5771 unsigned int required_template
;
5773 /* If we need a stop bit after an M slot, our only choice is
5774 template 5 (M;;MI). If we need a stop bit after a B
5775 slot, our only choice is to place it at the end of the
5776 bundle, because the only available templates are MIB,
5777 MBB, BBB, MMB, and MFB. We don't handle anything other
5778 than M and B slots because these are the only kind of
5779 instructions that can have the IA64_OPCODE_LAST bit set. */
5780 required_template
= template;
5781 switch (idesc
->type
)
5785 required_template
= 5;
5793 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5794 "Internal error: don't know how to force %s to end"
5795 "of instruction group", idesc
->name
);
5799 if (manual_bundling
&& i
!= required_slot
)
5800 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5801 "`%s' must be last in instruction group",
5803 if (required_slot
< i
)
5804 /* Can't fit this instruction. */
5808 if (required_template
!= template)
5810 /* If we switch the template, we need to reset the NOPs
5811 after slot i. The slot-types of the instructions ahead
5812 of i never change, so we don't need to worry about
5813 changing NOPs in front of this slot. */
5814 for (j
= i
; j
< 3; ++j
)
5815 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
5817 template = required_template
;
5819 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
5821 if (manual_bundling_on
)
5822 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5823 "Label must be first in a bundle");
5824 /* This insn must go into the first slot of a bundle. */
5828 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
5829 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
5831 if (manual_bundling_on
)
5834 manual_bundling
= 1;
5836 break; /* need to start a new bundle */
5839 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
5841 /* We need an instruction group boundary in the middle of a
5842 bundle. See if we can switch to an other template with
5843 an appropriate boundary. */
5845 orig_template
= template;
5846 if (i
== 1 && (user_template
== 4
5847 || (user_template
< 0
5848 && (ia64_templ_desc
[template].exec_unit
[0]
5852 end_of_insn_group
= 0;
5854 else if (i
== 2 && (user_template
== 0
5855 || (user_template
< 0
5856 && (ia64_templ_desc
[template].exec_unit
[1]
5858 /* This test makes sure we don't switch the template if
5859 the next instruction is one that needs to be first in
5860 an instruction group. Since all those instructions are
5861 in the M group, there is no way such an instruction can
5862 fit in this bundle even if we switch the template. The
5863 reason we have to check for this is that otherwise we
5864 may end up generating "MI;;I M.." which has the deadly
5865 effect that the second M instruction is no longer the
5866 first in the bundle! --davidm 99/12/16 */
5867 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
5870 end_of_insn_group
= 0;
5872 else if (curr
!= first
)
5873 /* can't fit this insn */
5876 if (template != orig_template
)
5877 /* if we switch the template, we need to reset the NOPs
5878 after slot i. The slot-types of the instructions ahead
5879 of i never change, so we don't need to worry about
5880 changing NOPs in front of this slot. */
5881 for (j
= i
; j
< 3; ++j
)
5882 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
5884 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
5886 /* resolve dynamic opcodes such as "break" and "nop": */
5887 if (idesc
->type
== IA64_TYPE_DYN
)
5889 if ((strcmp (idesc
->name
, "nop") == 0)
5890 || (strcmp (idesc
->name
, "break") == 0))
5891 insn_unit
= required_unit
;
5892 else if (strcmp (idesc
->name
, "chk.s") == 0)
5894 insn_unit
= IA64_UNIT_M
;
5895 if (required_unit
== IA64_UNIT_I
)
5896 insn_unit
= IA64_UNIT_I
;
5899 as_fatal ("emit_one_bundle: unexpected dynamic op");
5901 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
5902 ia64_free_opcode (idesc
);
5903 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
5905 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
5910 insn_type
= idesc
->type
;
5911 insn_unit
= IA64_UNIT_NIL
;
5915 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
5916 insn_unit
= required_unit
;
5918 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
5919 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
5920 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
5921 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
5922 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
5927 if (insn_unit
!= required_unit
)
5929 if (required_unit
== IA64_UNIT_L
5930 && insn_unit
== IA64_UNIT_I
5931 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
5933 /* we got ourselves an MLX template but the current
5934 instruction isn't an X-unit, or an I-unit instruction
5935 that can go into the X slot of an MLX template. Duh. */
5936 if (md
.num_slots_in_use
>= NUM_SLOTS
)
5938 as_bad_where (md
.slot
[curr
].src_file
,
5939 md
.slot
[curr
].src_line
,
5940 "`%s' can't go in X slot of "
5941 "MLX template", idesc
->name
);
5942 /* drop this insn so we don't livelock: */
5943 --md
.num_slots_in_use
;
5947 continue; /* try next slot */
5953 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + i
;
5954 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
5957 if (errata_nop_necessary_p (md
.slot
+ curr
, insn_unit
))
5958 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
5960 build_insn (md
.slot
+ curr
, insn
+ i
);
5962 /* Set slot counts for non prologue/body unwind records. */
5963 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5964 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
5965 && ptr
->r
.type
!= body
)
5967 ptr
->slot_number
= (unsigned long) f
+ i
;
5968 ptr
->slot_frag
= frag_now
;
5970 md
.slot
[curr
].unwind_record
= NULL
;
5972 if (required_unit
== IA64_UNIT_L
)
5975 /* skip one slot for long/X-unit instructions */
5978 --md
.num_slots_in_use
;
5980 /* now is a good time to fix up the labels for this insn: */
5981 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
5983 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
5984 symbol_set_frag (lfix
->sym
, frag_now
);
5986 /* and fix up the tags also. */
5987 for (lfix
= md
.slot
[curr
].tag_fixups
; lfix
; lfix
= lfix
->next
)
5989 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16 + i
);
5990 symbol_set_frag (lfix
->sym
, frag_now
);
5993 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
5995 ifix
= md
.slot
[curr
].fixup
+ j
;
5996 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 8,
5997 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
5998 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
5999 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
6000 fix
->fx_file
= md
.slot
[curr
].src_file
;
6001 fix
->fx_line
= md
.slot
[curr
].src_line
;
6004 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
6006 if (end_of_insn_group
)
6008 md
.group_idx
= (md
.group_idx
+ 1) % 3;
6009 memset (md
.last_groups
+ md
.group_idx
, 0, sizeof md
.last_groups
[0]);
6013 ia64_free_opcode (md
.slot
[curr
].idesc
);
6014 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
6015 md
.slot
[curr
].user_template
= -1;
6017 if (manual_bundling_off
)
6019 manual_bundling
= 0;
6022 curr
= (curr
+ 1) % NUM_SLOTS
;
6023 idesc
= md
.slot
[curr
].idesc
;
6025 if (manual_bundling
)
6027 if (md
.num_slots_in_use
> 0)
6028 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6029 "`%s' does not fit into %s template",
6030 idesc
->name
, ia64_templ_desc
[template].name
);
6032 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6033 "Missing '}' at end of file");
6035 know (md
.num_slots_in_use
< NUM_SLOTS
);
6037 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
6038 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
6040 number_to_chars_littleendian (f
+ 0, t0
, 8);
6041 number_to_chars_littleendian (f
+ 8, t1
, 8);
6043 unwind
.next_slot_number
= (unsigned long) f
+ 16;
6044 unwind
.next_slot_frag
= frag_now
;
6048 md_parse_option (c
, arg
)
6055 /* Switches from the Intel assembler. */
6057 if (strcmp (arg
, "ilp64") == 0
6058 || strcmp (arg
, "lp64") == 0
6059 || strcmp (arg
, "p64") == 0)
6061 md
.flags
|= EF_IA_64_ABI64
;
6063 else if (strcmp (arg
, "ilp32") == 0)
6065 md
.flags
&= ~EF_IA_64_ABI64
;
6067 else if (strcmp (arg
, "le") == 0)
6069 md
.flags
&= ~EF_IA_64_BE
;
6071 else if (strcmp (arg
, "be") == 0)
6073 md
.flags
|= EF_IA_64_BE
;
6080 if (strcmp (arg
, "so") == 0)
6082 /* Suppress signon message. */
6084 else if (strcmp (arg
, "pi") == 0)
6086 /* Reject privileged instructions. FIXME */
6088 else if (strcmp (arg
, "us") == 0)
6090 /* Allow union of signed and unsigned range. FIXME */
6092 else if (strcmp (arg
, "close_fcalls") == 0)
6094 /* Do not resolve global function calls. */
6101 /* temp[="prefix"] Insert temporary labels into the object file
6102 symbol table prefixed by "prefix".
6103 Default prefix is ":temp:".
6108 /* indirect=<tgt> Assume unannotated indirect branches behavior
6109 according to <tgt> --
6110 exit: branch out from the current context (default)
6111 labels: all labels in context may be branch targets
6113 if (strncmp (arg
, "indirect=", 9) != 0)
6118 /* -X conflicts with an ignored option, use -x instead */
6120 if (!arg
|| strcmp (arg
, "explicit") == 0)
6122 /* set default mode to explicit */
6123 md
.default_explicit_mode
= 1;
6126 else if (strcmp (arg
, "auto") == 0)
6128 md
.default_explicit_mode
= 0;
6130 else if (strcmp (arg
, "debug") == 0)
6134 else if (strcmp (arg
, "debugx") == 0)
6136 md
.default_explicit_mode
= 1;
6141 as_bad (_("Unrecognized option '-x%s'"), arg
);
6146 /* nops Print nops statistics. */
6149 /* GNU specific switches for gcc. */
6150 case OPTION_MCONSTANT_GP
:
6151 md
.flags
|= EF_IA_64_CONS_GP
;
6154 case OPTION_MAUTO_PIC
:
6155 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
6166 md_show_usage (stream
)
6171 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6172 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
6173 -x | -xexplicit turn on dependency violation checking (default)\n\
6174 -xauto automagically remove dependency violations\n\
6175 -xdebug debug dependency violation checker\n"),
6179 /* Return true if TYPE fits in TEMPL at SLOT. */
6182 match (int templ
, int type
, int slot
)
6184 enum ia64_unit unit
;
6187 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
6190 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
6192 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
6194 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
6195 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
6196 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
6197 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
6198 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
6199 default: result
= 0; break;
6204 /* Add a bit of extra goodness if a nop of type F or B would fit
6205 in TEMPL at SLOT. */
6208 extra_goodness (int templ
, int slot
)
6210 if (slot
== 1 && match (templ
, IA64_TYPE_F
, slot
))
6212 if (slot
== 2 && match (templ
, IA64_TYPE_B
, slot
))
6217 /* This function is called once, at assembler startup time. It sets
6218 up all the tables, etc. that the MD part of the assembler will need
6219 that can be determined before arguments are parsed. */
6223 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
, ok
;
6228 md
.explicit_mode
= md
.default_explicit_mode
;
6230 bfd_set_section_alignment (stdoutput
, text_section
, 4);
6232 target_big_endian
= TARGET_BYTES_BIG_ENDIAN
;
6233 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
6234 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
6235 &zero_address_frag
);
6237 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
6238 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
6239 &zero_address_frag
);
6241 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
6242 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
6243 &zero_address_frag
);
6245 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
6246 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
6247 &zero_address_frag
);
6249 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
6250 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
6251 &zero_address_frag
);
6253 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
6254 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
6255 &zero_address_frag
);
6257 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
6258 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
6259 &zero_address_frag
);
6261 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
6262 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
6263 &zero_address_frag
);
6265 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
6266 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
6267 &zero_address_frag
);
6269 /* Compute the table of best templates. We compute goodness as a
6270 base 4 value, in which each match counts for 3, each F counts
6271 for 2, each B counts for 1. This should maximize the number of
6272 F and B nops in the chosen bundles, which is good because these
6273 pipelines are least likely to be overcommitted. */
6274 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
6275 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
6276 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
6279 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
6282 if (match (t
, i
, 0))
6284 if (match (t
, j
, 1))
6286 if (match (t
, k
, 2))
6287 goodness
= 3 + 3 + 3;
6289 goodness
= 3 + 3 + extra_goodness (t
, 2);
6291 else if (match (t
, j
, 2))
6292 goodness
= 3 + 3 + extra_goodness (t
, 1);
6296 goodness
+= extra_goodness (t
, 1);
6297 goodness
+= extra_goodness (t
, 2);
6300 else if (match (t
, i
, 1))
6302 if (match (t
, j
, 2))
6305 goodness
= 3 + extra_goodness (t
, 2);
6307 else if (match (t
, i
, 2))
6308 goodness
= 3 + extra_goodness (t
, 1);
6310 if (goodness
> best
)
6313 best_template
[i
][j
][k
] = t
;
6318 for (i
= 0; i
< NUM_SLOTS
; ++i
)
6319 md
.slot
[i
].user_template
= -1;
6321 md
.pseudo_hash
= hash_new ();
6322 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
6324 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
6325 (void *) (pseudo_opcode
+ i
));
6327 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6328 pseudo_opcode
[i
].name
, err
);
6331 md
.reg_hash
= hash_new ();
6332 md
.dynreg_hash
= hash_new ();
6333 md
.const_hash
= hash_new ();
6334 md
.entry_hash
= hash_new ();
6336 /* general registers: */
6339 for (i
= 0; i
< total
; ++i
)
6341 sprintf (name
, "r%d", i
- REG_GR
);
6342 md
.regsym
[i
] = declare_register (name
, i
);
6345 /* floating point registers: */
6347 for (; i
< total
; ++i
)
6349 sprintf (name
, "f%d", i
- REG_FR
);
6350 md
.regsym
[i
] = declare_register (name
, i
);
6353 /* application registers: */
6356 for (; i
< total
; ++i
)
6358 sprintf (name
, "ar%d", i
- REG_AR
);
6359 md
.regsym
[i
] = declare_register (name
, i
);
6362 /* control registers: */
6365 for (; i
< total
; ++i
)
6367 sprintf (name
, "cr%d", i
- REG_CR
);
6368 md
.regsym
[i
] = declare_register (name
, i
);
6371 /* predicate registers: */
6373 for (; i
< total
; ++i
)
6375 sprintf (name
, "p%d", i
- REG_P
);
6376 md
.regsym
[i
] = declare_register (name
, i
);
6379 /* branch registers: */
6381 for (; i
< total
; ++i
)
6383 sprintf (name
, "b%d", i
- REG_BR
);
6384 md
.regsym
[i
] = declare_register (name
, i
);
6387 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
6388 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
6389 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
6390 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
6391 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
6392 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
6393 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
6395 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
6397 regnum
= indirect_reg
[i
].regnum
;
6398 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
6401 /* define synonyms for application registers: */
6402 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
6403 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
6404 REG_AR
+ ar
[i
- REG_AR
].regnum
);
6406 /* define synonyms for control registers: */
6407 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
6408 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
6409 REG_CR
+ cr
[i
- REG_CR
].regnum
);
6411 declare_register ("gp", REG_GR
+ 1);
6412 declare_register ("sp", REG_GR
+ 12);
6413 declare_register ("rp", REG_BR
+ 0);
6415 /* pseudo-registers used to specify unwind info: */
6416 declare_register ("psp", REG_PSP
);
6418 declare_register_set ("ret", 4, REG_GR
+ 8);
6419 declare_register_set ("farg", 8, REG_FR
+ 8);
6420 declare_register_set ("fret", 8, REG_FR
+ 8);
6422 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
6424 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
6425 (PTR
) (const_bits
+ i
));
6427 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6431 /* Set the architecture and machine depending on defaults and command line
6433 if (md
.flags
& EF_IA_64_ABI64
)
6434 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf64
);
6436 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf32
);
6439 as_warn (_("Could not set architecture and machine"));
6441 md
.mem_offset
.hint
= 0;
6444 md
.entry_labels
= NULL
;
6447 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6448 because that is called after md_parse_option which is where we do the
6449 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6450 default endianness. */
6453 ia64_init (argc
, argv
)
6454 int argc ATTRIBUTE_UNUSED
;
6455 char **argv ATTRIBUTE_UNUSED
;
6457 md
.flags
= EF_IA_64_ABI64
;
6458 if (TARGET_BYTES_BIG_ENDIAN
)
6459 md
.flags
|= EF_IA_64_BE
;
6462 /* Return a string for the target object file format. */
6465 ia64_target_format ()
6467 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6469 if (md
.flags
& EF_IA_64_BE
)
6471 if (md
.flags
& EF_IA_64_ABI64
)
6473 return "elf64-ia64-aix-big";
6475 return "elf64-ia64-big";
6479 return "elf32-ia64-aix-big";
6481 return "elf32-ia64-big";
6486 if (md
.flags
& EF_IA_64_ABI64
)
6488 return "elf64-ia64-aix-little";
6490 return "elf64-ia64-little";
6494 return "elf32-ia64-aix-little";
6496 return "elf32-ia64-little";
6501 return "unknown-format";
6505 ia64_end_of_source ()
6507 /* terminate insn group upon reaching end of file: */
6508 insn_group_break (1, 0, 0);
6510 /* emits slots we haven't written yet: */
6511 ia64_flush_insns ();
6513 bfd_set_private_flags (stdoutput
, md
.flags
);
6515 md
.mem_offset
.hint
= 0;
6521 if (md
.qp
.X_op
== O_register
)
6522 as_bad ("qualifying predicate not followed by instruction");
6523 md
.qp
.X_op
= O_absent
;
6525 if (ignore_input ())
6528 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
6530 if (md
.detect_dv
&& !md
.explicit_mode
)
6531 as_warn (_("Explicit stops are ignored in auto mode"));
6533 insn_group_break (1, 0, 0);
6537 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6539 static int defining_tag
= 0;
6542 ia64_unrecognized_line (ch
)
6548 expression (&md
.qp
);
6549 if (*input_line_pointer
++ != ')')
6551 as_bad ("Expected ')'");
6554 if (md
.qp
.X_op
!= O_register
)
6556 as_bad ("Qualifying predicate expected");
6559 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
6561 as_bad ("Predicate register expected");
6567 if (md
.manual_bundling
)
6568 as_warn ("Found '{' when manual bundling is already turned on");
6570 CURR_SLOT
.manual_bundling_on
= 1;
6571 md
.manual_bundling
= 1;
6573 /* Bundling is only acceptable in explicit mode
6574 or when in default automatic mode. */
6575 if (md
.detect_dv
&& !md
.explicit_mode
)
6577 if (!md
.mode_explicitly_set
6578 && !md
.default_explicit_mode
)
6581 as_warn (_("Found '{' after explicit switch to automatic mode"));
6586 if (!md
.manual_bundling
)
6587 as_warn ("Found '}' when manual bundling is off");
6589 PREV_SLOT
.manual_bundling_off
= 1;
6590 md
.manual_bundling
= 0;
6592 /* switch back to automatic mode, if applicable */
6595 && !md
.mode_explicitly_set
6596 && !md
.default_explicit_mode
)
6599 /* Allow '{' to follow on the same line. We also allow ";;", but that
6600 happens automatically because ';' is an end of line marker. */
6602 if (input_line_pointer
[0] == '{')
6604 input_line_pointer
++;
6605 return ia64_unrecognized_line ('{');
6608 demand_empty_rest_of_line ();
6617 if (md
.qp
.X_op
== O_register
)
6619 as_bad ("Tag must come before qualifying predicate.");
6622 s
= input_line_pointer
;
6623 c
= get_symbol_end ();
6626 /* Put ':' back for error messages' sake. */
6627 *input_line_pointer
++ = ':';
6628 as_bad ("Expected ':'");
6634 /* Put ':' back for error messages' sake. */
6635 *input_line_pointer
++ = ':';
6636 if (*input_line_pointer
++ != ']')
6638 as_bad ("Expected ']'");
6643 as_bad ("Tag name expected");
6653 /* Not a valid line. */
6658 ia64_frob_label (sym
)
6661 struct label_fix
*fix
;
6663 /* Tags need special handling since they are not bundle breaks like
6667 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6669 fix
->next
= CURR_SLOT
.tag_fixups
;
6670 CURR_SLOT
.tag_fixups
= fix
;
6675 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6677 md
.last_text_seg
= now_seg
;
6678 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6680 fix
->next
= CURR_SLOT
.label_fixups
;
6681 CURR_SLOT
.label_fixups
= fix
;
6683 /* Keep track of how many code entry points we've seen. */
6684 if (md
.path
== md
.maxpaths
)
6687 md
.entry_labels
= (const char **)
6688 xrealloc ((void *) md
.entry_labels
,
6689 md
.maxpaths
* sizeof (char *));
6691 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
6696 ia64_flush_pending_output ()
6698 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6700 /* ??? This causes many unnecessary stop bits to be emitted.
6701 Unfortunately, it isn't clear if it is safe to remove this. */
6702 insn_group_break (1, 0, 0);
6703 ia64_flush_insns ();
6707 /* Do ia64-specific expression optimization. All that's done here is
6708 to transform index expressions that are either due to the indexing
6709 of rotating registers or due to the indexing of indirect register
6712 ia64_optimize_expr (l
, op
, r
)
6721 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
6723 num_regs
= (l
->X_add_number
>> 16);
6724 if ((unsigned) r
->X_add_number
>= num_regs
)
6727 as_bad ("No current frame");
6729 as_bad ("Index out of range 0..%u", num_regs
- 1);
6730 r
->X_add_number
= 0;
6732 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
6735 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
6737 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
6738 || l
->X_add_number
== IND_MEM
)
6740 as_bad ("Indirect register set name expected");
6741 l
->X_add_number
= IND_CPUID
;
6744 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
6745 l
->X_add_number
= r
->X_add_number
;
6753 ia64_parse_name (name
, e
)
6757 struct const_desc
*cdesc
;
6758 struct dynreg
*dr
= 0;
6759 unsigned int regnum
;
6763 /* first see if NAME is a known register name: */
6764 sym
= hash_find (md
.reg_hash
, name
);
6767 e
->X_op
= O_register
;
6768 e
->X_add_number
= S_GET_VALUE (sym
);
6772 cdesc
= hash_find (md
.const_hash
, name
);
6775 e
->X_op
= O_constant
;
6776 e
->X_add_number
= cdesc
->value
;
6780 /* check for inN, locN, or outN: */
6784 if (name
[1] == 'n' && isdigit (name
[2]))
6792 if (name
[1] == 'o' && name
[2] == 'c' && isdigit (name
[3]))
6800 if (name
[1] == 'u' && name
[2] == 't' && isdigit (name
[3]))
6813 /* The name is inN, locN, or outN; parse the register number. */
6814 regnum
= strtoul (name
, &end
, 10);
6815 if (end
> name
&& *end
== '\0')
6817 if ((unsigned) regnum
>= dr
->num_regs
)
6820 as_bad ("No current frame");
6822 as_bad ("Register number out of range 0..%u",
6826 e
->X_op
= O_register
;
6827 e
->X_add_number
= dr
->base
+ regnum
;
6832 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
6834 /* We've got ourselves the name of a rotating register set.
6835 Store the base register number in the low 16 bits of
6836 X_add_number and the size of the register set in the top 16
6838 e
->X_op
= O_register
;
6839 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
6845 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6848 ia64_canonicalize_symbol_name (name
)
6851 size_t len
= strlen (name
);
6852 if (len
> 1 && name
[len
- 1] == '#')
6853 name
[len
- 1] = '\0';
6858 is_conditional_branch (idesc
)
6859 struct ia64_opcode
*idesc
;
6861 return (strncmp (idesc
->name
, "br", 2) == 0
6862 && (strcmp (idesc
->name
, "br") == 0
6863 || strncmp (idesc
->name
, "br.cond", 7) == 0
6864 || strncmp (idesc
->name
, "br.call", 7) == 0
6865 || strncmp (idesc
->name
, "br.ret", 6) == 0
6866 || strcmp (idesc
->name
, "brl") == 0
6867 || strncmp (idesc
->name
, "brl.cond", 7) == 0
6868 || strncmp (idesc
->name
, "brl.call", 7) == 0
6869 || strncmp (idesc
->name
, "brl.ret", 6) == 0));
6872 /* Return whether the given opcode is a taken branch. If there's any doubt,
6876 is_taken_branch (idesc
)
6877 struct ia64_opcode
*idesc
;
6879 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
6880 || strncmp (idesc
->name
, "br.ia", 5) == 0);
6883 /* Return whether the given opcode is an interruption or rfi. If there's any
6884 doubt, returns zero. */
6887 is_interruption_or_rfi (idesc
)
6888 struct ia64_opcode
*idesc
;
6890 if (strcmp (idesc
->name
, "rfi") == 0)
6895 /* Returns the index of the given dependency in the opcode's list of chks, or
6896 -1 if there is no dependency. */
6899 depends_on (depind
, idesc
)
6901 struct ia64_opcode
*idesc
;
6904 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
6905 for (i
= 0; i
< dep
->nchks
; i
++)
6907 if (depind
== DEP (dep
->chks
[i
]))
6913 /* Determine a set of specific resources used for a particular resource
6914 class. Returns the number of specific resources identified For those
6915 cases which are not determinable statically, the resource returned is
6918 Meanings of value in 'NOTE':
6919 1) only read/write when the register number is explicitly encoded in the
6921 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6922 accesses CFM when qualifying predicate is in the rotating region.
6923 3) general register value is used to specify an indirect register; not
6924 determinable statically.
6925 4) only read the given resource when bits 7:0 of the indirect index
6926 register value does not match the register number of the resource; not
6927 determinable statically.
6928 5) all rules are implementation specific.
6929 6) only when both the index specified by the reader and the index specified
6930 by the writer have the same value in bits 63:61; not determinable
6932 7) only access the specified resource when the corresponding mask bit is
6934 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6935 only read when these insns reference FR2-31
6936 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6937 written when these insns write FR32-127
6938 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6940 11) The target predicates are written independently of PR[qp], but source
6941 registers are only read if PR[qp] is true. Since the state of PR[qp]
6942 cannot statically be determined, all source registers are marked used.
6943 12) This insn only reads the specified predicate register when that
6944 register is the PR[qp].
6945 13) This reference to ld-c only applies to teh GR whose value is loaded
6946 with data returned from memory, not the post-incremented address register.
6947 14) The RSE resource includes the implementation-specific RSE internal
6948 state resources. At least one (and possibly more) of these resources are
6949 read by each instruction listed in IC:rse-readers. At least one (and
6950 possibly more) of these resources are written by each insn listed in
6952 15+16) Represents reserved instructions, which the assembler does not
6955 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6956 this code; there are no dependency violations based on memory access.
6959 #define MAX_SPECS 256
6964 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
6965 const struct ia64_dependency
*dep
;
6966 struct ia64_opcode
*idesc
;
6967 int type
; /* is this a DV chk or a DV reg? */
6968 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
6969 int note
; /* resource note for this insn's usage */
6970 int path
; /* which execution path to examine */
6977 if (dep
->mode
== IA64_DV_WAW
6978 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
6979 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
6982 /* template for any resources we identify */
6983 tmpl
.dependency
= dep
;
6985 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
6986 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
6987 tmpl
.link_to_qp_branch
= 1;
6988 tmpl
.mem_offset
.hint
= 0;
6991 tmpl
.cmp_type
= CMP_NONE
;
6994 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6995 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6996 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6998 /* we don't need to track these */
6999 if (dep
->semantics
== IA64_DVS_NONE
)
7002 switch (dep
->specifier
)
7007 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7009 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7010 if (regno
>= 0 && regno
<= 7)
7012 specs
[count
] = tmpl
;
7013 specs
[count
++].index
= regno
;
7019 for (i
= 0; i
< 8; i
++)
7021 specs
[count
] = tmpl
;
7022 specs
[count
++].index
= i
;
7031 case IA64_RS_AR_UNAT
:
7032 /* This is a mov =AR or mov AR= instruction. */
7033 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7035 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7036 if (regno
== AR_UNAT
)
7038 specs
[count
++] = tmpl
;
7043 /* This is a spill/fill, or other instruction that modifies the
7046 /* Unless we can determine the specific bits used, mark the whole
7047 thing; bits 8:3 of the memory address indicate the bit used in
7048 UNAT. The .mem.offset hint may be used to eliminate a small
7049 subset of conflicts. */
7050 specs
[count
] = tmpl
;
7051 if (md
.mem_offset
.hint
)
7054 fprintf (stderr
, " Using hint for spill/fill\n");
7055 /* The index isn't actually used, just set it to something
7056 approximating the bit index. */
7057 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
7058 specs
[count
].mem_offset
.hint
= 1;
7059 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
7060 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
7064 specs
[count
++].specific
= 0;
7072 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7074 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7075 if ((regno
>= 8 && regno
<= 15)
7076 || (regno
>= 20 && regno
<= 23)
7077 || (regno
>= 31 && regno
<= 39)
7078 || (regno
>= 41 && regno
<= 47)
7079 || (regno
>= 67 && regno
<= 111))
7081 specs
[count
] = tmpl
;
7082 specs
[count
++].index
= regno
;
7095 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7097 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7098 if ((regno
>= 48 && regno
<= 63)
7099 || (regno
>= 112 && regno
<= 127))
7101 specs
[count
] = tmpl
;
7102 specs
[count
++].index
= regno
;
7108 for (i
= 48; i
< 64; i
++)
7110 specs
[count
] = tmpl
;
7111 specs
[count
++].index
= i
;
7113 for (i
= 112; i
< 128; i
++)
7115 specs
[count
] = tmpl
;
7116 specs
[count
++].index
= i
;
7134 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7135 if (idesc
->operands
[i
] == IA64_OPND_B1
7136 || idesc
->operands
[i
] == IA64_OPND_B2
)
7138 specs
[count
] = tmpl
;
7139 specs
[count
++].index
=
7140 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7145 for (i
= idesc
->num_outputs
;i
< NELEMS (idesc
->operands
); i
++)
7146 if (idesc
->operands
[i
] == IA64_OPND_B1
7147 || idesc
->operands
[i
] == IA64_OPND_B2
)
7149 specs
[count
] = tmpl
;
7150 specs
[count
++].index
=
7151 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7157 case IA64_RS_CPUID
: /* four or more registers */
7160 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
7162 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7163 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7166 specs
[count
] = tmpl
;
7167 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7171 specs
[count
] = tmpl
;
7172 specs
[count
++].specific
= 0;
7182 case IA64_RS_DBR
: /* four or more registers */
7185 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
7187 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7188 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7191 specs
[count
] = tmpl
;
7192 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7196 specs
[count
] = tmpl
;
7197 specs
[count
++].specific
= 0;
7201 else if (note
== 0 && !rsrc_write
)
7203 specs
[count
] = tmpl
;
7204 specs
[count
++].specific
= 0;
7212 case IA64_RS_IBR
: /* four or more registers */
7215 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
7217 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7218 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7221 specs
[count
] = tmpl
;
7222 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7226 specs
[count
] = tmpl
;
7227 specs
[count
++].specific
= 0;
7240 /* These are implementation specific. Force all references to
7241 conflict with all other references. */
7242 specs
[count
] = tmpl
;
7243 specs
[count
++].specific
= 0;
7251 case IA64_RS_PKR
: /* 16 or more registers */
7252 if (note
== 3 || note
== 4)
7254 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
7256 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7257 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7262 specs
[count
] = tmpl
;
7263 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7266 for (i
= 0; i
< NELEMS (gr_values
); i
++)
7268 /* Uses all registers *except* the one in R3. */
7269 if ((unsigned)i
!= (gr_values
[regno
].value
& 0xFF))
7271 specs
[count
] = tmpl
;
7272 specs
[count
++].index
= i
;
7278 specs
[count
] = tmpl
;
7279 specs
[count
++].specific
= 0;
7286 specs
[count
] = tmpl
;
7287 specs
[count
++].specific
= 0;
7291 case IA64_RS_PMC
: /* four or more registers */
7294 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
7295 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
7298 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
7300 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
7301 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7304 specs
[count
] = tmpl
;
7305 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7309 specs
[count
] = tmpl
;
7310 specs
[count
++].specific
= 0;
7320 case IA64_RS_PMD
: /* four or more registers */
7323 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
7325 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7326 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7329 specs
[count
] = tmpl
;
7330 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7334 specs
[count
] = tmpl
;
7335 specs
[count
++].specific
= 0;
7345 case IA64_RS_RR
: /* eight registers */
7348 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
7350 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7351 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7354 specs
[count
] = tmpl
;
7355 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
7359 specs
[count
] = tmpl
;
7360 specs
[count
++].specific
= 0;
7364 else if (note
== 0 && !rsrc_write
)
7366 specs
[count
] = tmpl
;
7367 specs
[count
++].specific
= 0;
7375 case IA64_RS_CR_IRR
:
7378 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7379 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
7381 && idesc
->operands
[1] == IA64_OPND_CR3
7384 for (i
= 0; i
< 4; i
++)
7386 specs
[count
] = tmpl
;
7387 specs
[count
++].index
= CR_IRR0
+ i
;
7393 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7394 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7396 && regno
<= CR_IRR3
)
7398 specs
[count
] = tmpl
;
7399 specs
[count
++].index
= regno
;
7408 case IA64_RS_CR_LRR
:
7415 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7416 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7417 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
7419 specs
[count
] = tmpl
;
7420 specs
[count
++].index
= regno
;
7428 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7430 specs
[count
] = tmpl
;
7431 specs
[count
++].index
=
7432 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7447 else if (rsrc_write
)
7449 if (dep
->specifier
== IA64_RS_FRb
7450 && idesc
->operands
[0] == IA64_OPND_F1
)
7452 specs
[count
] = tmpl
;
7453 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
7458 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
7460 if (idesc
->operands
[i
] == IA64_OPND_F2
7461 || idesc
->operands
[i
] == IA64_OPND_F3
7462 || idesc
->operands
[i
] == IA64_OPND_F4
)
7464 specs
[count
] = tmpl
;
7465 specs
[count
++].index
=
7466 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7475 /* This reference applies only to the GR whose value is loaded with
7476 data returned from memory. */
7477 specs
[count
] = tmpl
;
7478 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7484 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7485 if (idesc
->operands
[i
] == IA64_OPND_R1
7486 || idesc
->operands
[i
] == IA64_OPND_R2
7487 || idesc
->operands
[i
] == IA64_OPND_R3
)
7489 specs
[count
] = tmpl
;
7490 specs
[count
++].index
=
7491 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7493 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
7494 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7495 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
7497 specs
[count
] = tmpl
;
7498 specs
[count
++].index
=
7499 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7504 /* Look for anything that reads a GR. */
7505 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7507 if (idesc
->operands
[i
] == IA64_OPND_MR3
7508 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
7509 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
7510 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
7511 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
7512 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
7513 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
7514 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
7515 || idesc
->operands
[i
] == IA64_OPND_RR_R3
7516 || ((i
>= idesc
->num_outputs
)
7517 && (idesc
->operands
[i
] == IA64_OPND_R1
7518 || idesc
->operands
[i
] == IA64_OPND_R2
7519 || idesc
->operands
[i
] == IA64_OPND_R3
7520 /* addl source register. */
7521 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
7523 specs
[count
] = tmpl
;
7524 specs
[count
++].index
=
7525 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7536 /* This is the same as IA64_RS_PRr, except that the register range is
7537 from 1 - 15, and there are no rotating register reads/writes here. */
7541 for (i
= 1; i
< 16; i
++)
7543 specs
[count
] = tmpl
;
7544 specs
[count
++].index
= i
;
7550 /* Mark only those registers indicated by the mask. */
7553 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7554 for (i
= 1; i
< 16; i
++)
7555 if (mask
& ((valueT
) 1 << i
))
7557 specs
[count
] = tmpl
;
7558 specs
[count
++].index
= i
;
7566 else if (note
== 11) /* note 11 implies note 1 as well */
7570 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7572 if (idesc
->operands
[i
] == IA64_OPND_P1
7573 || idesc
->operands
[i
] == IA64_OPND_P2
)
7575 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7576 if (regno
>= 1 && regno
< 16)
7578 specs
[count
] = tmpl
;
7579 specs
[count
++].index
= regno
;
7589 else if (note
== 12)
7591 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7593 specs
[count
] = tmpl
;
7594 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7601 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7602 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7603 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
7604 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
7606 if ((idesc
->operands
[0] == IA64_OPND_P1
7607 || idesc
->operands
[0] == IA64_OPND_P2
)
7608 && p1
>= 1 && p1
< 16)
7610 specs
[count
] = tmpl
;
7611 specs
[count
].cmp_type
=
7612 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7613 specs
[count
++].index
= p1
;
7615 if ((idesc
->operands
[1] == IA64_OPND_P1
7616 || idesc
->operands
[1] == IA64_OPND_P2
)
7617 && p2
>= 1 && p2
< 16)
7619 specs
[count
] = tmpl
;
7620 specs
[count
].cmp_type
=
7621 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7622 specs
[count
++].index
= p2
;
7627 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7629 specs
[count
] = tmpl
;
7630 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7632 if (idesc
->operands
[1] == IA64_OPND_PR
)
7634 for (i
= 1; i
< 16; i
++)
7636 specs
[count
] = tmpl
;
7637 specs
[count
++].index
= i
;
7648 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7649 simplified cases of this. */
7653 for (i
= 16; i
< 63; i
++)
7655 specs
[count
] = tmpl
;
7656 specs
[count
++].index
= i
;
7662 /* Mark only those registers indicated by the mask. */
7664 && idesc
->operands
[0] == IA64_OPND_PR
)
7666 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7667 if (mask
& ((valueT
) 1<<16))
7668 for (i
= 16; i
< 63; i
++)
7670 specs
[count
] = tmpl
;
7671 specs
[count
++].index
= i
;
7675 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
7677 for (i
= 16; i
< 63; i
++)
7679 specs
[count
] = tmpl
;
7680 specs
[count
++].index
= i
;
7688 else if (note
== 11) /* note 11 implies note 1 as well */
7692 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7694 if (idesc
->operands
[i
] == IA64_OPND_P1
7695 || idesc
->operands
[i
] == IA64_OPND_P2
)
7697 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7698 if (regno
>= 16 && regno
< 63)
7700 specs
[count
] = tmpl
;
7701 specs
[count
++].index
= regno
;
7711 else if (note
== 12)
7713 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7715 specs
[count
] = tmpl
;
7716 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7723 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7724 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7725 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
7726 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
7728 if ((idesc
->operands
[0] == IA64_OPND_P1
7729 || idesc
->operands
[0] == IA64_OPND_P2
)
7730 && p1
>= 16 && p1
< 63)
7732 specs
[count
] = tmpl
;
7733 specs
[count
].cmp_type
=
7734 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7735 specs
[count
++].index
= p1
;
7737 if ((idesc
->operands
[1] == IA64_OPND_P1
7738 || idesc
->operands
[1] == IA64_OPND_P2
)
7739 && p2
>= 16 && p2
< 63)
7741 specs
[count
] = tmpl
;
7742 specs
[count
].cmp_type
=
7743 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7744 specs
[count
++].index
= p2
;
7749 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7751 specs
[count
] = tmpl
;
7752 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7754 if (idesc
->operands
[1] == IA64_OPND_PR
)
7756 for (i
= 16; i
< 63; i
++)
7758 specs
[count
] = tmpl
;
7759 specs
[count
++].index
= i
;
7771 /* Verify that the instruction is using the PSR bit indicated in
7775 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
7777 if (dep
->regindex
< 6)
7779 specs
[count
++] = tmpl
;
7782 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
7784 if (dep
->regindex
< 32
7785 || dep
->regindex
== 35
7786 || dep
->regindex
== 36
7787 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
7789 specs
[count
++] = tmpl
;
7792 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
7794 if (dep
->regindex
< 32
7795 || dep
->regindex
== 35
7796 || dep
->regindex
== 36
7797 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
7799 specs
[count
++] = tmpl
;
7804 /* Several PSR bits have very specific dependencies. */
7805 switch (dep
->regindex
)
7808 specs
[count
++] = tmpl
;
7813 specs
[count
++] = tmpl
;
7817 /* Only certain CR accesses use PSR.ic */
7818 if (idesc
->operands
[0] == IA64_OPND_CR3
7819 || idesc
->operands
[1] == IA64_OPND_CR3
)
7822 ((idesc
->operands
[0] == IA64_OPND_CR3
)
7825 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
7840 specs
[count
++] = tmpl
;
7849 specs
[count
++] = tmpl
;
7853 /* Only some AR accesses use cpl */
7854 if (idesc
->operands
[0] == IA64_OPND_AR3
7855 || idesc
->operands
[1] == IA64_OPND_AR3
)
7858 ((idesc
->operands
[0] == IA64_OPND_AR3
)
7861 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
7868 && regno
<= AR_K7
))))
7870 specs
[count
++] = tmpl
;
7875 specs
[count
++] = tmpl
;
7885 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
7887 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
7893 if (mask
& ((valueT
) 1 << dep
->regindex
))
7895 specs
[count
++] = tmpl
;
7900 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
7901 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
7902 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7903 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7905 if (idesc
->operands
[i
] == IA64_OPND_F1
7906 || idesc
->operands
[i
] == IA64_OPND_F2
7907 || idesc
->operands
[i
] == IA64_OPND_F3
7908 || idesc
->operands
[i
] == IA64_OPND_F4
)
7910 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7911 if (reg
>= min
&& reg
<= max
)
7913 specs
[count
++] = tmpl
;
7920 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
7921 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
7922 /* mfh is read on writes to FR32-127; mfl is read on writes to
7924 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7926 if (idesc
->operands
[i
] == IA64_OPND_F1
)
7928 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7929 if (reg
>= min
&& reg
<= max
)
7931 specs
[count
++] = tmpl
;
7936 else if (note
== 10)
7938 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7940 if (idesc
->operands
[i
] == IA64_OPND_R1
7941 || idesc
->operands
[i
] == IA64_OPND_R2
7942 || idesc
->operands
[i
] == IA64_OPND_R3
)
7944 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7945 if (regno
>= 16 && regno
<= 31)
7947 specs
[count
++] = tmpl
;
7958 case IA64_RS_AR_FPSR
:
7959 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7961 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7962 if (regno
== AR_FPSR
)
7964 specs
[count
++] = tmpl
;
7969 specs
[count
++] = tmpl
;
7974 /* Handle all AR[REG] resources */
7975 if (note
== 0 || note
== 1)
7977 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7978 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
7979 && regno
== dep
->regindex
)
7981 specs
[count
++] = tmpl
;
7983 /* other AR[REG] resources may be affected by AR accesses */
7984 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
7987 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
7988 switch (dep
->regindex
)
7994 if (regno
== AR_BSPSTORE
)
7996 specs
[count
++] = tmpl
;
8000 (regno
== AR_BSPSTORE
8001 || regno
== AR_RNAT
))
8003 specs
[count
++] = tmpl
;
8008 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8011 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
8012 switch (dep
->regindex
)
8017 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
8019 specs
[count
++] = tmpl
;
8026 specs
[count
++] = tmpl
;
8036 /* Handle all CR[REG] resources */
8037 if (note
== 0 || note
== 1)
8039 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
8041 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
8042 if (regno
== dep
->regindex
)
8044 specs
[count
++] = tmpl
;
8046 else if (!rsrc_write
)
8048 /* Reads from CR[IVR] affect other resources. */
8049 if (regno
== CR_IVR
)
8051 if ((dep
->regindex
>= CR_IRR0
8052 && dep
->regindex
<= CR_IRR3
)
8053 || dep
->regindex
== CR_TPR
)
8055 specs
[count
++] = tmpl
;
8062 specs
[count
++] = tmpl
;
8071 case IA64_RS_INSERVICE
:
8072 /* look for write of EOI (67) or read of IVR (65) */
8073 if ((idesc
->operands
[0] == IA64_OPND_CR3
8074 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
8075 || (idesc
->operands
[1] == IA64_OPND_CR3
8076 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
8078 specs
[count
++] = tmpl
;
8085 specs
[count
++] = tmpl
;
8096 specs
[count
++] = tmpl
;
8100 /* Check if any of the registers accessed are in the rotating region.
8101 mov to/from pr accesses CFM only when qp_regno is in the rotating
8103 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8105 if (idesc
->operands
[i
] == IA64_OPND_R1
8106 || idesc
->operands
[i
] == IA64_OPND_R2
8107 || idesc
->operands
[i
] == IA64_OPND_R3
)
8109 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8110 /* Assumes that md.rot.num_regs is always valid */
8111 if (md
.rot
.num_regs
> 0
8113 && num
< 31 + md
.rot
.num_regs
)
8115 specs
[count
] = tmpl
;
8116 specs
[count
++].specific
= 0;
8119 else if (idesc
->operands
[i
] == IA64_OPND_F1
8120 || idesc
->operands
[i
] == IA64_OPND_F2
8121 || idesc
->operands
[i
] == IA64_OPND_F3
8122 || idesc
->operands
[i
] == IA64_OPND_F4
)
8124 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8127 specs
[count
] = tmpl
;
8128 specs
[count
++].specific
= 0;
8131 else if (idesc
->operands
[i
] == IA64_OPND_P1
8132 || idesc
->operands
[i
] == IA64_OPND_P2
)
8134 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8137 specs
[count
] = tmpl
;
8138 specs
[count
++].specific
= 0;
8142 if (CURR_SLOT
.qp_regno
> 15)
8144 specs
[count
] = tmpl
;
8145 specs
[count
++].specific
= 0;
8150 /* This is the same as IA64_RS_PRr, except simplified to account for
8151 the fact that there is only one register. */
8155 specs
[count
++] = tmpl
;
8160 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
8161 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
8162 if (mask
& ((valueT
) 1 << 63))
8163 specs
[count
++] = tmpl
;
8165 else if (note
== 11)
8167 if ((idesc
->operands
[0] == IA64_OPND_P1
8168 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
8169 || (idesc
->operands
[1] == IA64_OPND_P2
8170 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
8172 specs
[count
++] = tmpl
;
8175 else if (note
== 12)
8177 if (CURR_SLOT
.qp_regno
== 63)
8179 specs
[count
++] = tmpl
;
8186 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8187 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8188 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
8189 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
8192 && (idesc
->operands
[0] == IA64_OPND_P1
8193 || idesc
->operands
[0] == IA64_OPND_P2
))
8195 specs
[count
] = tmpl
;
8196 specs
[count
++].cmp_type
=
8197 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
8200 && (idesc
->operands
[1] == IA64_OPND_P1
8201 || idesc
->operands
[1] == IA64_OPND_P2
))
8203 specs
[count
] = tmpl
;
8204 specs
[count
++].cmp_type
=
8205 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
8210 if (CURR_SLOT
.qp_regno
== 63)
8212 specs
[count
++] = tmpl
;
8223 /* FIXME we can identify some individual RSE written resources, but RSE
8224 read resources have not yet been completely identified, so for now
8225 treat RSE as a single resource */
8226 if (strncmp (idesc
->name
, "mov", 3) == 0)
8230 if (idesc
->operands
[0] == IA64_OPND_AR3
8231 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
8233 specs
[count
] = tmpl
;
8234 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8239 if (idesc
->operands
[0] == IA64_OPND_AR3
)
8241 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
8242 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
8244 specs
[count
++] = tmpl
;
8247 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8249 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
8250 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
8251 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
8253 specs
[count
++] = tmpl
;
8260 specs
[count
++] = tmpl
;
8265 /* FIXME -- do any of these need to be non-specific? */
8266 specs
[count
++] = tmpl
;
8270 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
8277 /* Clear branch flags on marked resources. This breaks the link between the
8278 QP of the marking instruction and a subsequent branch on the same QP. */
8281 clear_qp_branch_flag (mask
)
8285 for (i
= 0; i
< regdepslen
; i
++)
8287 valueT bit
= ((valueT
) 1 << regdeps
[i
].qp_regno
);
8288 if ((bit
& mask
) != 0)
8290 regdeps
[i
].link_to_qp_branch
= 0;
8295 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8297 Any changes to a PR clears the mutex relations which include that PR. */
8300 clear_qp_mutex (mask
)
8306 while (i
< qp_mutexeslen
)
8308 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
8312 fprintf (stderr
, " Clearing mutex relation");
8313 print_prmask (qp_mutexes
[i
].prmask
);
8314 fprintf (stderr
, "\n");
8316 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
8323 /* Clear implies relations which contain PRs in the given masks.
8324 P1_MASK indicates the source of the implies relation, while P2_MASK
8325 indicates the implied PR. */
8328 clear_qp_implies (p1_mask
, p2_mask
)
8335 while (i
< qp_implieslen
)
8337 if ((((valueT
) 1 << qp_implies
[i
].p1
) & p1_mask
) != 0
8338 || (((valueT
) 1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
8341 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
8342 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
8343 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
8350 /* Add the PRs specified to the list of implied relations. */
8353 add_qp_imply (p1
, p2
)
8360 /* p0 is not meaningful here. */
8361 if (p1
== 0 || p2
== 0)
8367 /* If it exists already, ignore it. */
8368 for (i
= 0; i
< qp_implieslen
; i
++)
8370 if (qp_implies
[i
].p1
== p1
8371 && qp_implies
[i
].p2
== p2
8372 && qp_implies
[i
].path
== md
.path
8373 && !qp_implies
[i
].p2_branched
)
8377 if (qp_implieslen
== qp_impliestotlen
)
8379 qp_impliestotlen
+= 20;
8380 qp_implies
= (struct qp_imply
*)
8381 xrealloc ((void *) qp_implies
,
8382 qp_impliestotlen
* sizeof (struct qp_imply
));
8385 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
8386 qp_implies
[qp_implieslen
].p1
= p1
;
8387 qp_implies
[qp_implieslen
].p2
= p2
;
8388 qp_implies
[qp_implieslen
].path
= md
.path
;
8389 qp_implies
[qp_implieslen
++].p2_branched
= 0;
8391 /* Add in the implied transitive relations; for everything that p2 implies,
8392 make p1 imply that, too; for everything that implies p1, make it imply p2
8394 for (i
= 0; i
< qp_implieslen
; i
++)
8396 if (qp_implies
[i
].p1
== p2
)
8397 add_qp_imply (p1
, qp_implies
[i
].p2
);
8398 if (qp_implies
[i
].p2
== p1
)
8399 add_qp_imply (qp_implies
[i
].p1
, p2
);
8401 /* Add in mutex relations implied by this implies relation; for each mutex
8402 relation containing p2, duplicate it and replace p2 with p1. */
8403 bit
= (valueT
) 1 << p1
;
8404 mask
= (valueT
) 1 << p2
;
8405 for (i
= 0; i
< qp_mutexeslen
; i
++)
8407 if (qp_mutexes
[i
].prmask
& mask
)
8408 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
8412 /* Add the PRs specified in the mask to the mutex list; this means that only
8413 one of the PRs can be true at any time. PR0 should never be included in
8423 if (qp_mutexeslen
== qp_mutexestotlen
)
8425 qp_mutexestotlen
+= 20;
8426 qp_mutexes
= (struct qpmutex
*)
8427 xrealloc ((void *) qp_mutexes
,
8428 qp_mutexestotlen
* sizeof (struct qpmutex
));
8432 fprintf (stderr
, " Registering mutex on");
8433 print_prmask (mask
);
8434 fprintf (stderr
, "\n");
8436 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
8437 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
8441 clear_register_values ()
8445 fprintf (stderr
, " Clearing register values\n");
8446 for (i
= 1; i
< NELEMS (gr_values
); i
++)
8447 gr_values
[i
].known
= 0;
8450 /* Keep track of register values/changes which affect DV tracking.
8452 optimization note: should add a flag to classes of insns where otherwise we
8453 have to examine a group of strings to identify them. */
8456 note_register_values (idesc
)
8457 struct ia64_opcode
*idesc
;
8459 valueT qp_changemask
= 0;
8462 /* Invalidate values for registers being written to. */
8463 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8465 if (idesc
->operands
[i
] == IA64_OPND_R1
8466 || idesc
->operands
[i
] == IA64_OPND_R2
8467 || idesc
->operands
[i
] == IA64_OPND_R3
)
8469 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8470 if (regno
> 0 && regno
< NELEMS (gr_values
))
8471 gr_values
[regno
].known
= 0;
8473 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
8475 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8476 if (regno
> 0 && regno
< 4)
8477 gr_values
[regno
].known
= 0;
8479 else if (idesc
->operands
[i
] == IA64_OPND_P1
8480 || idesc
->operands
[i
] == IA64_OPND_P2
)
8482 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8483 qp_changemask
|= (valueT
) 1 << regno
;
8485 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
8487 if (idesc
->operands
[2] & (valueT
) 0x10000)
8488 qp_changemask
= ~(valueT
) 0x1FFFF | idesc
->operands
[2];
8490 qp_changemask
= idesc
->operands
[2];
8493 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
8495 if (idesc
->operands
[1] & ((valueT
) 1 << 43))
8496 qp_changemask
= ~(valueT
) 0xFFFFFFFFFFF | idesc
->operands
[1];
8498 qp_changemask
= idesc
->operands
[1];
8499 qp_changemask
&= ~(valueT
) 0xFFFF;
8504 /* Always clear qp branch flags on any PR change. */
8505 /* FIXME there may be exceptions for certain compares. */
8506 clear_qp_branch_flag (qp_changemask
);
8508 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8509 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
8511 qp_changemask
|= ~(valueT
) 0xFFFF;
8512 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
8514 for (i
= 32; i
< 32 + md
.rot
.num_regs
; i
++)
8515 gr_values
[i
].known
= 0;
8517 clear_qp_mutex (qp_changemask
);
8518 clear_qp_implies (qp_changemask
, qp_changemask
);
8520 /* After a call, all register values are undefined, except those marked
8522 else if (strncmp (idesc
->name
, "br.call", 6) == 0
8523 || strncmp (idesc
->name
, "brl.call", 7) == 0)
8525 /* FIXME keep GR values which are marked as "safe_across_calls" */
8526 clear_register_values ();
8527 clear_qp_mutex (~qp_safe_across_calls
);
8528 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
8529 clear_qp_branch_flag (~qp_safe_across_calls
);
8531 else if (is_interruption_or_rfi (idesc
)
8532 || is_taken_branch (idesc
))
8534 clear_register_values ();
8535 clear_qp_mutex (~(valueT
) 0);
8536 clear_qp_implies (~(valueT
) 0, ~(valueT
) 0);
8538 /* Look for mutex and implies relations. */
8539 else if ((idesc
->operands
[0] == IA64_OPND_P1
8540 || idesc
->operands
[0] == IA64_OPND_P2
)
8541 && (idesc
->operands
[1] == IA64_OPND_P1
8542 || idesc
->operands
[1] == IA64_OPND_P2
))
8544 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8545 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8546 valueT p1mask
= (valueT
) 1 << p1
;
8547 valueT p2mask
= (valueT
) 1 << p2
;
8549 /* If one of the PRs is PR0, we can't really do anything. */
8550 if (p1
== 0 || p2
== 0)
8553 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
8555 /* In general, clear mutexes and implies which include P1 or P2,
8556 with the following exceptions. */
8557 else if (strstr (idesc
->name
, ".or.andcm") != NULL
)
8559 add_qp_mutex (p1mask
| p2mask
);
8560 clear_qp_implies (p2mask
, p1mask
);
8562 else if (strstr (idesc
->name
, ".and.orcm") != NULL
)
8564 add_qp_mutex (p1mask
| p2mask
);
8565 clear_qp_implies (p1mask
, p2mask
);
8567 else if (strstr (idesc
->name
, ".and") != NULL
)
8569 clear_qp_implies (0, p1mask
| p2mask
);
8571 else if (strstr (idesc
->name
, ".or") != NULL
)
8573 clear_qp_mutex (p1mask
| p2mask
);
8574 clear_qp_implies (p1mask
| p2mask
, 0);
8578 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
8579 if (strstr (idesc
->name
, ".unc") != NULL
)
8581 add_qp_mutex (p1mask
| p2mask
);
8582 if (CURR_SLOT
.qp_regno
!= 0)
8584 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
8585 CURR_SLOT
.qp_regno
);
8586 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
8587 CURR_SLOT
.qp_regno
);
8590 else if (CURR_SLOT
.qp_regno
== 0)
8592 add_qp_mutex (p1mask
| p2mask
);
8596 clear_qp_mutex (p1mask
| p2mask
);
8600 /* Look for mov imm insns into GRs. */
8601 else if (idesc
->operands
[0] == IA64_OPND_R1
8602 && (idesc
->operands
[1] == IA64_OPND_IMM22
8603 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
8604 && (strcmp (idesc
->name
, "mov") == 0
8605 || strcmp (idesc
->name
, "movl") == 0))
8607 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
8608 if (regno
> 0 && regno
< NELEMS (gr_values
))
8610 gr_values
[regno
].known
= 1;
8611 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
8612 gr_values
[regno
].path
= md
.path
;
8615 fprintf (stderr
, " Know gr%d = ", regno
);
8616 fprintf_vma (stderr
, gr_values
[regno
].value
);
8617 fputs ("\n", stderr
);
8623 clear_qp_mutex (qp_changemask
);
8624 clear_qp_implies (qp_changemask
, qp_changemask
);
8628 /* Return whether the given predicate registers are currently mutex. */
8631 qp_mutex (p1
, p2
, path
)
8641 mask
= ((valueT
) 1 << p1
) | (valueT
) 1 << p2
;
8642 for (i
= 0; i
< qp_mutexeslen
; i
++)
8644 if (qp_mutexes
[i
].path
>= path
8645 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
8652 /* Return whether the given resource is in the given insn's list of chks
8653 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8657 resources_match (rs
, idesc
, note
, qp_regno
, path
)
8659 struct ia64_opcode
*idesc
;
8664 struct rsrc specs
[MAX_SPECS
];
8667 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8668 we don't need to check. One exception is note 11, which indicates that
8669 target predicates are written regardless of PR[qp]. */
8670 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
8674 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
8677 /* UNAT checking is a bit more specific than other resources */
8678 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
8679 && specs
[count
].mem_offset
.hint
8680 && rs
->mem_offset
.hint
)
8682 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
8684 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
8685 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
8692 /* Skip apparent PR write conflicts where both writes are an AND or both
8693 writes are an OR. */
8694 if (rs
->dependency
->specifier
== IA64_RS_PR
8695 || rs
->dependency
->specifier
== IA64_RS_PRr
8696 || rs
->dependency
->specifier
== IA64_RS_PR63
)
8698 if (specs
[count
].cmp_type
!= CMP_NONE
8699 && specs
[count
].cmp_type
== rs
->cmp_type
)
8702 fprintf (stderr
, " %s on parallel compare allowed (PR%d)\n",
8703 dv_mode
[rs
->dependency
->mode
],
8704 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8705 specs
[count
].index
: 63);
8710 " %s on parallel compare conflict %s vs %s on PR%d\n",
8711 dv_mode
[rs
->dependency
->mode
],
8712 dv_cmp_type
[rs
->cmp_type
],
8713 dv_cmp_type
[specs
[count
].cmp_type
],
8714 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8715 specs
[count
].index
: 63);
8719 /* If either resource is not specific, conservatively assume a conflict
8721 if (!specs
[count
].specific
|| !rs
->specific
)
8723 else if (specs
[count
].index
== rs
->index
)
8728 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
8734 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8735 insert a stop to create the break. Update all resource dependencies
8736 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8737 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8738 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
8742 insn_group_break (insert_stop
, qp_regno
, save_current
)
8749 if (insert_stop
&& md
.num_slots_in_use
> 0)
8750 PREV_SLOT
.end_of_insn_group
= 1;
8754 fprintf (stderr
, " Insn group break%s",
8755 (insert_stop
? " (w/stop)" : ""));
8757 fprintf (stderr
, " effective for QP=%d", qp_regno
);
8758 fprintf (stderr
, "\n");
8762 while (i
< regdepslen
)
8764 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
8767 && regdeps
[i
].qp_regno
!= qp_regno
)
8774 && CURR_SLOT
.src_file
== regdeps
[i
].file
8775 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
8781 /* clear dependencies which are automatically cleared by a stop, or
8782 those that have reached the appropriate state of insn serialization */
8783 if (dep
->semantics
== IA64_DVS_IMPLIED
8784 || dep
->semantics
== IA64_DVS_IMPLIEDF
8785 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
8787 print_dependency ("Removing", i
);
8788 regdeps
[i
] = regdeps
[--regdepslen
];
8792 if (dep
->semantics
== IA64_DVS_DATA
8793 || dep
->semantics
== IA64_DVS_INSTR
8794 || dep
->semantics
== IA64_DVS_SPECIFIC
)
8796 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
8797 regdeps
[i
].insn_srlz
= STATE_STOP
;
8798 if (regdeps
[i
].data_srlz
== STATE_NONE
)
8799 regdeps
[i
].data_srlz
= STATE_STOP
;
8806 /* Add the given resource usage spec to the list of active dependencies. */
8809 mark_resource (idesc
, dep
, spec
, depind
, path
)
8810 struct ia64_opcode
*idesc ATTRIBUTE_UNUSED
;
8811 const struct ia64_dependency
*dep ATTRIBUTE_UNUSED
;
8816 if (regdepslen
== regdepstotlen
)
8818 regdepstotlen
+= 20;
8819 regdeps
= (struct rsrc
*)
8820 xrealloc ((void *) regdeps
,
8821 regdepstotlen
* sizeof (struct rsrc
));
8824 regdeps
[regdepslen
] = *spec
;
8825 regdeps
[regdepslen
].depind
= depind
;
8826 regdeps
[regdepslen
].path
= path
;
8827 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
8828 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
8830 print_dependency ("Adding", regdepslen
);
8836 print_dependency (action
, depind
)
8842 fprintf (stderr
, " %s %s '%s'",
8843 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
8844 (regdeps
[depind
].dependency
)->name
);
8845 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
8846 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
8847 if (regdeps
[depind
].mem_offset
.hint
)
8849 fputs (" ", stderr
);
8850 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.base
);
8851 fputs ("+", stderr
);
8852 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.offset
);
8854 fprintf (stderr
, "\n");
8859 instruction_serialization ()
8863 fprintf (stderr
, " Instruction serialization\n");
8864 for (i
= 0; i
< regdepslen
; i
++)
8865 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
8866 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
8870 data_serialization ()
8874 fprintf (stderr
, " Data serialization\n");
8875 while (i
< regdepslen
)
8877 if (regdeps
[i
].data_srlz
== STATE_STOP
8878 /* Note: as of 991210, all "other" dependencies are cleared by a
8879 data serialization. This might change with new tables */
8880 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
8882 print_dependency ("Removing", i
);
8883 regdeps
[i
] = regdeps
[--regdepslen
];
8890 /* Insert stops and serializations as needed to avoid DVs. */
8893 remove_marked_resource (rs
)
8896 switch (rs
->dependency
->semantics
)
8898 case IA64_DVS_SPECIFIC
:
8900 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
8901 /* ...fall through... */
8902 case IA64_DVS_INSTR
:
8904 fprintf (stderr
, "Inserting instr serialization\n");
8905 if (rs
->insn_srlz
< STATE_STOP
)
8906 insn_group_break (1, 0, 0);
8907 if (rs
->insn_srlz
< STATE_SRLZ
)
8909 int oldqp
= CURR_SLOT
.qp_regno
;
8910 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8911 /* Manually jam a srlz.i insn into the stream */
8912 CURR_SLOT
.qp_regno
= 0;
8913 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
8914 instruction_serialization ();
8915 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8916 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8918 CURR_SLOT
.qp_regno
= oldqp
;
8919 CURR_SLOT
.idesc
= oldidesc
;
8921 insn_group_break (1, 0, 0);
8923 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
8924 "other" types of DV are eliminated
8925 by a data serialization */
8928 fprintf (stderr
, "Inserting data serialization\n");
8929 if (rs
->data_srlz
< STATE_STOP
)
8930 insn_group_break (1, 0, 0);
8932 int oldqp
= CURR_SLOT
.qp_regno
;
8933 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8934 /* Manually jam a srlz.d insn into the stream */
8935 CURR_SLOT
.qp_regno
= 0;
8936 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
8937 data_serialization ();
8938 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8939 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8941 CURR_SLOT
.qp_regno
= oldqp
;
8942 CURR_SLOT
.idesc
= oldidesc
;
8945 case IA64_DVS_IMPLIED
:
8946 case IA64_DVS_IMPLIEDF
:
8948 fprintf (stderr
, "Inserting stop\n");
8949 insn_group_break (1, 0, 0);
8956 /* Check the resources used by the given opcode against the current dependency
8959 The check is run once for each execution path encountered. In this case,
8960 a unique execution path is the sequence of instructions following a code
8961 entry point, e.g. the following has three execution paths, one starting
8962 at L0, one at L1, and one at L2.
8971 check_dependencies (idesc
)
8972 struct ia64_opcode
*idesc
;
8974 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8978 /* Note that the number of marked resources may change within the
8979 loop if in auto mode. */
8981 while (i
< regdepslen
)
8983 struct rsrc
*rs
= ®deps
[i
];
8984 const struct ia64_dependency
*dep
= rs
->dependency
;
8989 if (dep
->semantics
== IA64_DVS_NONE
8990 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
8996 note
= NOTE (opdeps
->chks
[chkind
]);
8998 /* Check this resource against each execution path seen thus far. */
8999 for (path
= 0; path
<= md
.path
; path
++)
9003 /* If the dependency wasn't on the path being checked, ignore it. */
9004 if (rs
->path
< path
)
9007 /* If the QP for this insn implies a QP which has branched, don't
9008 bother checking. Ed. NOTE: I don't think this check is terribly
9009 useful; what's the point of generating code which will only be
9010 reached if its QP is zero?
9011 This code was specifically inserted to handle the following code,
9012 based on notes from Intel's DV checking code, where p1 implies p2.
9018 if (CURR_SLOT
.qp_regno
!= 0)
9022 for (implies
= 0; implies
< qp_implieslen
; implies
++)
9024 if (qp_implies
[implies
].path
>= path
9025 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
9026 && qp_implies
[implies
].p2_branched
)
9036 if ((matchtype
= resources_match (rs
, idesc
, note
,
9037 CURR_SLOT
.qp_regno
, path
)) != 0)
9040 char pathmsg
[256] = "";
9041 char indexmsg
[256] = "";
9042 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
9045 sprintf (pathmsg
, " when entry is at label '%s'",
9046 md
.entry_labels
[path
- 1]);
9047 if (rs
->specific
&& rs
->index
!= 0)
9048 sprintf (indexmsg
, ", specific resource number is %d",
9050 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
9052 (certain
? "violates" : "may violate"),
9053 dv_mode
[dep
->mode
], dep
->name
,
9054 dv_sem
[dep
->semantics
],
9057 if (md
.explicit_mode
)
9059 as_warn ("%s", msg
);
9061 as_warn (_("Only the first path encountering the conflict "
9063 as_warn_where (rs
->file
, rs
->line
,
9064 _("This is the location of the "
9065 "conflicting usage"));
9066 /* Don't bother checking other paths, to avoid duplicating
9073 fprintf (stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
9075 remove_marked_resource (rs
);
9077 /* since the set of dependencies has changed, start over */
9078 /* FIXME -- since we're removing dvs as we go, we
9079 probably don't really need to start over... */
9092 /* Register new dependencies based on the given opcode. */
9095 mark_resources (idesc
)
9096 struct ia64_opcode
*idesc
;
9099 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9100 int add_only_qp_reads
= 0;
9102 /* A conditional branch only uses its resources if it is taken; if it is
9103 taken, we stop following that path. The other branch types effectively
9104 *always* write their resources. If it's not taken, register only QP
9106 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
9108 add_only_qp_reads
= 1;
9112 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
9114 for (i
= 0; i
< opdeps
->nregs
; i
++)
9116 const struct ia64_dependency
*dep
;
9117 struct rsrc specs
[MAX_SPECS
];
9122 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
9123 note
= NOTE (opdeps
->regs
[i
]);
9125 if (add_only_qp_reads
9126 && !(dep
->mode
== IA64_DV_WAR
9127 && (dep
->specifier
== IA64_RS_PR
9128 || dep
->specifier
== IA64_RS_PRr
9129 || dep
->specifier
== IA64_RS_PR63
)))
9132 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
9135 if (md
.debug_dv
&& !count
)
9136 fprintf (stderr
, " No %s %s usage found (path %d)\n",
9137 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
9142 mark_resource (idesc
, dep
, &specs
[count
],
9143 DEP (opdeps
->regs
[i
]), md
.path
);
9146 /* The execution path may affect register values, which may in turn
9147 affect which indirect-access resources are accessed. */
9148 switch (dep
->specifier
)
9160 for (path
= 0; path
< md
.path
; path
++)
9162 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
9164 mark_resource (idesc
, dep
, &specs
[count
],
9165 DEP (opdeps
->regs
[i
]), path
);
9172 /* Remove dependencies when they no longer apply. */
9175 update_dependencies (idesc
)
9176 struct ia64_opcode
*idesc
;
9180 if (strcmp (idesc
->name
, "srlz.i") == 0)
9182 instruction_serialization ();
9184 else if (strcmp (idesc
->name
, "srlz.d") == 0)
9186 data_serialization ();
9188 else if (is_interruption_or_rfi (idesc
)
9189 || is_taken_branch (idesc
))
9191 /* Although technically the taken branch doesn't clear dependencies
9192 which require a srlz.[id], we don't follow the branch; the next
9193 instruction is assumed to start with a clean slate. */
9197 else if (is_conditional_branch (idesc
)
9198 && CURR_SLOT
.qp_regno
!= 0)
9200 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
9202 for (i
= 0; i
< qp_implieslen
; i
++)
9204 /* If the conditional branch's predicate is implied by the predicate
9205 in an existing dependency, remove that dependency. */
9206 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
9209 /* Note that this implied predicate takes a branch so that if
9210 a later insn generates a DV but its predicate implies this
9211 one, we can avoid the false DV warning. */
9212 qp_implies
[i
].p2_branched
= 1;
9213 while (depind
< regdepslen
)
9215 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
9217 print_dependency ("Removing", depind
);
9218 regdeps
[depind
] = regdeps
[--regdepslen
];
9225 /* Any marked resources which have this same predicate should be
9226 cleared, provided that the QP hasn't been modified between the
9227 marking instruction and the branch. */
9230 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
9235 while (i
< regdepslen
)
9237 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
9238 && regdeps
[i
].link_to_qp_branch
9239 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
9240 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
9242 /* Treat like a taken branch */
9243 print_dependency ("Removing", i
);
9244 regdeps
[i
] = regdeps
[--regdepslen
];
9253 /* Examine the current instruction for dependency violations. */
9257 struct ia64_opcode
*idesc
;
9261 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
9262 idesc
->name
, CURR_SLOT
.src_line
,
9263 idesc
->dependencies
->nchks
,
9264 idesc
->dependencies
->nregs
);
9267 /* Look through the list of currently marked resources; if the current
9268 instruction has the dependency in its chks list which uses that resource,
9269 check against the specific resources used. */
9270 check_dependencies (idesc
);
9272 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9273 then add them to the list of marked resources. */
9274 mark_resources (idesc
);
9276 /* There are several types of dependency semantics, and each has its own
9277 requirements for being cleared
9279 Instruction serialization (insns separated by interruption, rfi, or
9280 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9282 Data serialization (instruction serialization, or writer + srlz.d +
9283 reader, where writer and srlz.d are in separate groups) clears
9284 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9285 always be the case).
9287 Instruction group break (groups separated by stop, taken branch,
9288 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9290 update_dependencies (idesc
);
9292 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9293 warning. Keep track of as many as possible that are useful. */
9294 note_register_values (idesc
);
9296 /* We don't need or want this anymore. */
9297 md
.mem_offset
.hint
= 0;
9302 /* Translate one line of assembly. Pseudo ops and labels do not show
9308 char *saved_input_line_pointer
, *mnemonic
;
9309 const struct pseudo_opcode
*pdesc
;
9310 struct ia64_opcode
*idesc
;
9311 unsigned char qp_regno
;
9315 saved_input_line_pointer
= input_line_pointer
;
9316 input_line_pointer
= str
;
9318 /* extract the opcode (mnemonic): */
9320 mnemonic
= input_line_pointer
;
9321 ch
= get_symbol_end ();
9322 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
9325 *input_line_pointer
= ch
;
9326 (*pdesc
->handler
) (pdesc
->arg
);
9330 /* Find the instruction descriptor matching the arguments. */
9332 idesc
= ia64_find_opcode (mnemonic
);
9333 *input_line_pointer
= ch
;
9336 as_bad ("Unknown opcode `%s'", mnemonic
);
9340 idesc
= parse_operands (idesc
);
9344 /* Handle the dynamic ops we can handle now: */
9345 if (idesc
->type
== IA64_TYPE_DYN
)
9347 if (strcmp (idesc
->name
, "add") == 0)
9349 if (CURR_SLOT
.opnd
[2].X_op
== O_register
9350 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
9354 ia64_free_opcode (idesc
);
9355 idesc
= ia64_find_opcode (mnemonic
);
9357 know (!idesc
->next
);
9360 else if (strcmp (idesc
->name
, "mov") == 0)
9362 enum ia64_opnd opnd1
, opnd2
;
9365 opnd1
= idesc
->operands
[0];
9366 opnd2
= idesc
->operands
[1];
9367 if (opnd1
== IA64_OPND_AR3
)
9369 else if (opnd2
== IA64_OPND_AR3
)
9373 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
9374 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
9378 ia64_free_opcode (idesc
);
9379 idesc
= ia64_find_opcode (mnemonic
);
9380 while (idesc
!= NULL
9381 && (idesc
->operands
[0] != opnd1
9382 || idesc
->operands
[1] != opnd2
))
9383 idesc
= get_next_opcode (idesc
);
9388 if (md
.qp
.X_op
== O_register
)
9390 qp_regno
= md
.qp
.X_add_number
- REG_P
;
9391 md
.qp
.X_op
= O_absent
;
9394 flags
= idesc
->flags
;
9396 if ((flags
& IA64_OPCODE_FIRST
) != 0)
9397 insn_group_break (1, 0, 0);
9399 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
9401 as_bad ("`%s' cannot be predicated", idesc
->name
);
9405 /* Build the instruction. */
9406 CURR_SLOT
.qp_regno
= qp_regno
;
9407 CURR_SLOT
.idesc
= idesc
;
9408 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
9409 dwarf2_where (&CURR_SLOT
.debug_line
);
9411 /* Add unwind entry, if there is one. */
9412 if (unwind
.current_entry
)
9414 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
9415 unwind
.current_entry
= NULL
;
9418 /* Check for dependency violations. */
9422 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9423 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9426 if ((flags
& IA64_OPCODE_LAST
) != 0)
9427 insn_group_break (1, 0, 0);
9429 md
.last_text_seg
= now_seg
;
9432 input_line_pointer
= saved_input_line_pointer
;
9435 /* Called when symbol NAME cannot be found in the symbol table.
9436 Should be used for dynamic valued symbols only. */
9439 md_undefined_symbol (name
)
9440 char *name ATTRIBUTE_UNUSED
;
9445 /* Called for any expression that can not be recognized. When the
9446 function is called, `input_line_pointer' will point to the start of
9453 enum pseudo_type pseudo_type
;
9458 switch (*input_line_pointer
)
9461 /* Find what relocation pseudo-function we're dealing with. */
9463 ch
= *++input_line_pointer
;
9464 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
9465 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
9467 len
= strlen (pseudo_func
[i
].name
);
9468 if (strncmp (pseudo_func
[i
].name
+ 1,
9469 input_line_pointer
+ 1, len
- 1) == 0
9470 && !is_part_of_name (input_line_pointer
[len
]))
9472 input_line_pointer
+= len
;
9473 pseudo_type
= pseudo_func
[i
].type
;
9477 switch (pseudo_type
)
9479 case PSEUDO_FUNC_RELOC
:
9481 if (*input_line_pointer
!= '(')
9483 as_bad ("Expected '('");
9487 ++input_line_pointer
;
9489 if (*input_line_pointer
++ != ')')
9491 as_bad ("Missing ')'");
9494 if (e
->X_op
!= O_symbol
)
9496 if (e
->X_op
!= O_pseudo_fixup
)
9498 as_bad ("Not a symbolic expression");
9501 if (S_GET_VALUE (e
->X_op_symbol
) == FUNC_FPTR_RELATIVE
9502 && i
== FUNC_LT_RELATIVE
)
9503 i
= FUNC_LT_FPTR_RELATIVE
;
9506 as_bad ("Illegal combination of relocation functions");
9510 /* Make sure gas doesn't get rid of local symbols that are used
9512 e
->X_op
= O_pseudo_fixup
;
9513 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
9516 case PSEUDO_FUNC_CONST
:
9517 e
->X_op
= O_constant
;
9518 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9521 case PSEUDO_FUNC_REG
:
9522 e
->X_op
= O_register
;
9523 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9527 name
= input_line_pointer
- 1;
9529 as_bad ("Unknown pseudo function `%s'", name
);
9535 ++input_line_pointer
;
9537 if (*input_line_pointer
!= ']')
9539 as_bad ("Closing bracket misssing");
9544 if (e
->X_op
!= O_register
)
9545 as_bad ("Register expected as index");
9547 ++input_line_pointer
;
9558 ignore_rest_of_line ();
9561 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9562 a section symbol plus some offset. For relocs involving @fptr(),
9563 directives we don't want such adjustments since we need to have the
9564 original symbol's name in the reloc. */
9566 ia64_fix_adjustable (fix
)
9569 /* Prevent all adjustments to global symbols */
9570 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
9573 switch (fix
->fx_r_type
)
9575 case BFD_RELOC_IA64_FPTR64I
:
9576 case BFD_RELOC_IA64_FPTR32MSB
:
9577 case BFD_RELOC_IA64_FPTR32LSB
:
9578 case BFD_RELOC_IA64_FPTR64MSB
:
9579 case BFD_RELOC_IA64_FPTR64LSB
:
9580 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9581 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9591 ia64_force_relocation (fix
)
9594 switch (fix
->fx_r_type
)
9596 case BFD_RELOC_IA64_FPTR64I
:
9597 case BFD_RELOC_IA64_FPTR32MSB
:
9598 case BFD_RELOC_IA64_FPTR32LSB
:
9599 case BFD_RELOC_IA64_FPTR64MSB
:
9600 case BFD_RELOC_IA64_FPTR64LSB
:
9602 case BFD_RELOC_IA64_LTOFF22
:
9603 case BFD_RELOC_IA64_LTOFF64I
:
9604 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9605 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9606 case BFD_RELOC_IA64_PLTOFF22
:
9607 case BFD_RELOC_IA64_PLTOFF64I
:
9608 case BFD_RELOC_IA64_PLTOFF64MSB
:
9609 case BFD_RELOC_IA64_PLTOFF64LSB
:
9618 /* Decide from what point a pc-relative relocation is relative to,
9619 relative to the pc-relative fixup. Er, relatively speaking. */
9621 ia64_pcrel_from_section (fix
, sec
)
9625 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
9627 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
9633 /* This is called whenever some data item (not an instruction) needs a
9634 fixup. We pick the right reloc code depending on the byteorder
9635 currently in effect. */
9637 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
9643 bfd_reloc_code_real_type code
;
9648 /* There are no reloc for 8 and 16 bit quantities, but we allow
9649 them here since they will work fine as long as the expression
9650 is fully defined at the end of the pass over the source file. */
9651 case 1: code
= BFD_RELOC_8
; break;
9652 case 2: code
= BFD_RELOC_16
; break;
9654 if (target_big_endian
)
9655 code
= BFD_RELOC_IA64_DIR32MSB
;
9657 code
= BFD_RELOC_IA64_DIR32LSB
;
9661 if (target_big_endian
)
9662 code
= BFD_RELOC_IA64_DIR64MSB
;
9664 code
= BFD_RELOC_IA64_DIR64LSB
;
9668 as_bad ("Unsupported fixup size %d", nbytes
);
9669 ignore_rest_of_line ();
9672 if (exp
->X_op
== O_pseudo_fixup
)
9675 exp
->X_op
= O_symbol
;
9676 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
9678 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
9679 /* We need to store the byte order in effect in case we're going
9680 to fix an 8 or 16 bit relocation (for which there no real
9681 relocs available). See md_apply_fix(). */
9682 fix
->tc_fix_data
.bigendian
= target_big_endian
;
9685 /* Return the actual relocation we wish to associate with the pseudo
9686 reloc described by SYM and R_TYPE. SYM should be one of the
9687 symbols in the pseudo_func array, or NULL. */
9689 static bfd_reloc_code_real_type
9690 ia64_gen_real_reloc_type (sym
, r_type
)
9692 bfd_reloc_code_real_type r_type
;
9694 bfd_reloc_code_real_type
new = 0;
9701 switch (S_GET_VALUE (sym
))
9703 case FUNC_FPTR_RELATIVE
:
9706 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
9707 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
9708 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
9709 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
9710 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
9715 case FUNC_GP_RELATIVE
:
9718 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
9719 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
9720 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
9721 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
9722 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
9723 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
9728 case FUNC_LT_RELATIVE
:
9731 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
9732 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
9737 case FUNC_PC_RELATIVE
:
9740 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
9741 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
9742 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
9743 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
9744 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
9745 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
9750 case FUNC_PLT_RELATIVE
:
9753 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
9754 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
9755 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
9756 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
9761 case FUNC_SEC_RELATIVE
:
9764 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
9765 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
9766 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
9767 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
9772 case FUNC_SEG_RELATIVE
:
9775 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
9776 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
9777 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
9778 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
9783 case FUNC_LTV_RELATIVE
:
9786 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
9787 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
9788 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
9789 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
9794 case FUNC_LT_FPTR_RELATIVE
:
9797 case BFD_RELOC_IA64_IMM22
:
9798 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
9799 case BFD_RELOC_IA64_IMM64
:
9800 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
9808 /* Hmmmm. Should this ever occur? */
9815 /* Here is where generate the appropriate reloc for pseudo relocation
9818 ia64_validate_fix (fix
)
9821 switch (fix
->fx_r_type
)
9823 case BFD_RELOC_IA64_FPTR64I
:
9824 case BFD_RELOC_IA64_FPTR32MSB
:
9825 case BFD_RELOC_IA64_FPTR64LSB
:
9826 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9827 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9828 if (fix
->fx_offset
!= 0)
9829 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9830 "No addend allowed in @fptr() relocation");
9840 fix_insn (fix
, odesc
, value
)
9842 const struct ia64_operand
*odesc
;
9845 bfd_vma insn
[3], t0
, t1
, control_bits
;
9850 slot
= fix
->fx_where
& 0x3;
9851 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
9853 /* Bundles are always in little-endian byte order */
9854 t0
= bfd_getl64 (fixpos
);
9855 t1
= bfd_getl64 (fixpos
+ 8);
9856 control_bits
= t0
& 0x1f;
9857 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
9858 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
9859 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
9862 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
9864 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
9865 insn
[2] |= (((value
& 0x7f) << 13)
9866 | (((value
>> 7) & 0x1ff) << 27)
9867 | (((value
>> 16) & 0x1f) << 22)
9868 | (((value
>> 21) & 0x1) << 21)
9869 | (((value
>> 63) & 0x1) << 36));
9871 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
9873 if (value
& ~0x3fffffffffffffffULL
)
9874 err
= "integer operand out of range";
9875 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
9876 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
9878 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
9881 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
9882 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
9883 | (((value
>> 0) & 0xfffff) << 13));
9886 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
9889 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
9891 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
9892 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
9893 number_to_chars_littleendian (fixpos
+ 0, t0
, 8);
9894 number_to_chars_littleendian (fixpos
+ 8, t1
, 8);
9897 /* Attempt to simplify or even eliminate a fixup. The return value is
9898 ignored; perhaps it was once meaningful, but now it is historical.
9899 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9901 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9904 md_apply_fix3 (fix
, valuep
, seg
)
9907 segT seg ATTRIBUTE_UNUSED
;
9910 valueT value
= *valuep
;
9913 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
9917 switch (fix
->fx_r_type
)
9919 case BFD_RELOC_IA64_DIR32MSB
:
9920 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
9924 case BFD_RELOC_IA64_DIR32LSB
:
9925 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
9929 case BFD_RELOC_IA64_DIR64MSB
:
9930 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
9934 case BFD_RELOC_IA64_DIR64LSB
:
9935 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
9945 if (fix
->fx_r_type
== (int) BFD_RELOC_UNUSED
)
9947 /* This must be a TAG13 or TAG13b operand. There are no external
9948 relocs defined for them, so we must give an error. */
9949 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9950 "%s must have a constant value",
9951 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
9956 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9957 work. There should be a better way to handle this. */
9959 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
9961 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
9963 if (fix
->tc_fix_data
.bigendian
)
9964 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
9966 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
9972 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
9979 /* Generate the BFD reloc to be stuck in the object file from the
9980 fixup used internally in the assembler. */
9983 tc_gen_reloc (sec
, fixp
)
9984 asection
*sec ATTRIBUTE_UNUSED
;
9989 reloc
= xmalloc (sizeof (*reloc
));
9990 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9991 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9992 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9993 reloc
->addend
= fixp
->fx_offset
;
9994 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
9998 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9999 "Cannot represent %s relocation in object file",
10000 bfd_get_reloc_code_name (fixp
->fx_r_type
));
10005 /* Turn a string in input_line_pointer into a floating point constant
10006 of type TYPE, and store the appropriate bytes in *LIT. The number
10007 of LITTLENUMS emitted is stored in *SIZE. An error message is
10008 returned, or NULL on OK. */
10010 #define MAX_LITTLENUMS 5
10013 md_atof (type
, lit
, size
)
10018 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
10019 LITTLENUM_TYPE
*word
;
10049 return "Bad call to MD_ATOF()";
10051 t
= atof_ieee (input_line_pointer
, type
, words
);
10053 input_line_pointer
= t
;
10054 *size
= prec
* sizeof (LITTLENUM_TYPE
);
10056 for (word
= words
+ prec
- 1; prec
--;)
10058 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
10059 lit
+= sizeof (LITTLENUM_TYPE
);
10064 /* Round up a section's size to the appropriate boundary. */
10066 md_section_align (seg
, size
)
10070 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10071 valueT mask
= ((valueT
) 1 << align
) - 1;
10073 return (size
+ mask
) & ~mask
;
10076 /* Handle ia64 specific semantics of the align directive. */
10079 ia64_md_do_align (n
, fill
, len
, max
)
10080 int n ATTRIBUTE_UNUSED
;
10081 const char *fill ATTRIBUTE_UNUSED
;
10082 int len ATTRIBUTE_UNUSED
;
10083 int max ATTRIBUTE_UNUSED
;
10085 if (subseg_text_p (now_seg
))
10086 ia64_flush_insns ();
10089 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10090 of an rs_align_code fragment. */
10093 ia64_handle_align (fragp
)
10096 /* Use mfi bundle of nops with no stop bits. */
10097 static const unsigned char be_nop
[]
10098 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
10099 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
10100 static const unsigned char le_nop
[]
10101 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
10102 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
10107 if (fragp
->fr_type
!= rs_align_code
)
10110 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
10111 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
10113 /* Make sure we are on a 16-byte boundary, in case someone has been
10114 putting data into a text section. */
10117 int fix
= bytes
& 15;
10118 memset (p
, 0, fix
);
10121 fragp
->fr_fix
+= fix
;
10124 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 16);
10125 fragp
->fr_var
= 16;