1 /* tc-m32c.c -- Assembler for the Renesas M32C.
2 Copyright (C) 2005, 2006 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
25 #include "opcodes/m32c-desc.h"
26 #include "opcodes/m32c-opc.h"
28 #include "elf/common.h"
31 #include "safe-ctype.h"
33 /* Structure to hold all of the different components
34 describing an individual instruction. */
37 const CGEN_INSN
* insn
;
38 const CGEN_INSN
* orig_insn
;
41 CGEN_INSN_INT buffer
[1];
42 #define INSN_VALUE(buf) (*(buf))
44 unsigned char buffer
[CGEN_MAX_INSN_SIZE
];
45 #define INSN_VALUE(buf) (buf)
50 fixS
* fixups
[GAS_CGEN_MAX_FIXUPS
];
51 int indices
[MAX_OPERAND_INSTANCES
];
55 #define rl_for(insn) (CGEN_ATTR_CGEN_INSN_RL_TYPE_VALUE (&(insn.insn->base->attrs)))
56 #define relaxable(insn) (CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE (&(insn.insn->base->attrs)))
58 const char comment_chars
[] = ";";
59 const char line_comment_chars
[] = "#";
60 const char line_separator_chars
[] = "|";
61 const char EXP_CHARS
[] = "eE";
62 const char FLT_CHARS
[] = "dD";
64 #define M32C_SHORTOPTS ""
65 const char * md_shortopts
= M32C_SHORTOPTS
;
67 /* assembler options */
68 #define OPTION_CPU_M16C (OPTION_MD_BASE)
69 #define OPTION_CPU_M32C (OPTION_MD_BASE + 1)
70 #define OPTION_LINKRELAX (OPTION_MD_BASE + 2)
72 struct option md_longopts
[] =
74 { "m16c", no_argument
, NULL
, OPTION_CPU_M16C
},
75 { "m32c", no_argument
, NULL
, OPTION_CPU_M32C
},
76 { "relax", no_argument
, NULL
, OPTION_LINKRELAX
},
77 {NULL
, no_argument
, NULL
, 0}
79 size_t md_longopts_size
= sizeof (md_longopts
);
83 #define DEFAULT_MACHINE bfd_mach_m16c
84 #define DEFAULT_FLAGS EF_M32C_CPU_M16C
86 static unsigned long m32c_mach
= bfd_mach_m16c
;
87 static int cpu_mach
= (1 << MACH_M16C
);
89 static int m32c_relax
= 0;
91 /* Flags to set in the elf header */
92 static flagword m32c_flags
= DEFAULT_FLAGS
;
94 static char default_isa
= 1 << (7 - ISA_M16C
);
95 static CGEN_BITSET m32c_isa
= {1, & default_isa
};
98 set_isa (enum isa_attr isa_num
)
100 cgen_bitset_set (& m32c_isa
, isa_num
);
103 static void s_bss (int);
106 md_parse_option (int c
, char * arg ATTRIBUTE_UNUSED
)
110 case OPTION_CPU_M16C
:
111 m32c_flags
= (m32c_flags
& ~EF_M32C_CPU_MASK
) | EF_M32C_CPU_M16C
;
112 m32c_mach
= bfd_mach_m16c
;
113 cpu_mach
= (1 << MACH_M16C
);
117 case OPTION_CPU_M32C
:
118 m32c_flags
= (m32c_flags
& ~EF_M32C_CPU_MASK
) | EF_M32C_CPU_M32C
;
119 m32c_mach
= bfd_mach_m32c
;
120 cpu_mach
= (1 << MACH_M32C
);
124 case OPTION_LINKRELAX
:
135 md_show_usage (FILE * stream
)
137 fprintf (stream
, _(" M32C specific command line options:\n"));
141 s_bss (int ignore ATTRIBUTE_UNUSED
)
145 temp
= get_absolute_expression ();
146 subseg_set (bss_section
, (subsegT
) temp
);
147 demand_empty_rest_of_line ();
150 /* The target specific pseudo-ops which we support. */
151 const pseudo_typeS md_pseudo_table
[] =
154 { "3byte", cons
, 3 },
163 /* Initialize the `cgen' interface. */
165 /* Set the machine number and endian. */
166 gas_cgen_cpu_desc
= m32c_cgen_cpu_open (CGEN_CPU_OPEN_MACHS
, cpu_mach
,
167 CGEN_CPU_OPEN_ENDIAN
,
169 CGEN_CPU_OPEN_ISAS
, & m32c_isa
,
172 m32c_cgen_init_asm (gas_cgen_cpu_desc
);
174 /* This is a callback from cgen to gas to parse operands. */
175 cgen_set_parse_operand_fn (gas_cgen_cpu_desc
, gas_cgen_parse_operand
);
177 /* Set the ELF flags if desired. */
179 bfd_set_private_flags (stdoutput
, m32c_flags
);
181 /* Set the machine type */
182 bfd_default_set_arch_mach (stdoutput
, bfd_arch_m32c
, m32c_mach
);
192 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
194 /* Pad with nops for objdump. */
195 n_nops
= (32 - ((insn_size
) % 32)) / 8;
196 for (i
= 1; i
<= n_nops
; i
++)
202 m32c_start_line_hook (void)
204 #if 0 /* not necessary....handled in the .cpu file */
205 char *s
= input_line_pointer
;
208 for (s
= input_line_pointer
; s
&& s
[0] != '\n'; s
++)
212 /* Remove :g suffix. Squeeze out blanks. */
215 for (sg
= s
- 1; sg
&& sg
>= input_line_pointer
; sg
--)
221 input_line_pointer
+= 2;
228 /* Process [[indirect-operands]] in instruction str. */
231 m32c_indirect_operand (char *str
)
238 enum indirect_type
{none
, relative
, absolute
} ;
239 enum indirect_type indirection
[3] = { none
, none
, none
};
240 int brace_n
[3] = { 0, 0, 0 };
245 for (s
= str
; *s
; s
++)
249 /* [abs] where abs is not a0 or a1 */
250 if (s
[1] == '[' && ! (s
[2] == 'a' && (s
[3] == '0' || s
[3] == '1'))
251 && (ISBLANK (s
[0]) || s
[0] == ','))
252 indirection
[operand
] = absolute
;
253 if (s
[0] == ']' && s
[1] == ']')
254 indirection
[operand
] = relative
;
255 if (s
[0] == '[' && s
[1] == '[')
256 indirection
[operand
] = relative
;
259 if (indirection
[1] == none
&& indirection
[2] == none
)
263 ns_len
= strlen (str
);
264 new_str
= (char*) xmalloc (ns_len
);
266 ns_end
= ns
+ ns_len
;
268 for (s
= str
; *s
; s
++)
273 if (s
[0] == '[' && ! brace_n
[operand
])
275 brace_n
[operand
] += 1;
276 /* Squeeze [[ to [ if this is an indirect operand. */
277 if (indirection
[operand
] != none
)
281 else if (s
[0] == '[' && brace_n
[operand
])
283 brace_n
[operand
] += 1;
285 else if (s
[0] == ']' && s
[1] == ']' && indirection
[operand
] == relative
)
287 s
+= 1; /* skip one ]. */
288 brace_n
[operand
] -= 2; /* allow for 2 [. */
290 else if (s
[0] == ']' && indirection
[operand
] == absolute
)
292 brace_n
[operand
] -= 1;
293 continue; /* skip closing ]. */
295 else if (s
[0] == ']')
297 brace_n
[operand
] -= 1;
307 for (operand
= 1; operand
<= 2; operand
++)
308 if (brace_n
[operand
])
310 fprintf (stderr
, "Unmatched [[operand-%d]] %d\n", operand
, brace_n
[operand
]);
313 if (indirection
[1] != none
&& indirection
[2] != none
)
314 md_assemble ("src-dest-indirect");
315 else if (indirection
[1] != none
)
316 md_assemble ("src-indirect");
317 else if (indirection
[2] != none
)
318 md_assemble ("dest-indirect");
320 md_assemble (new_str
);
326 md_assemble (char * str
)
328 static int last_insn_had_delay_slot
= 0;
331 finished_insnS results
;
334 if (m32c_mach
== bfd_mach_m32c
&& m32c_indirect_operand (str
))
337 /* Initialize GAS's cgen interface for a new instruction. */
338 gas_cgen_init_parse ();
340 insn
.insn
= m32c_cgen_assemble_insn
341 (gas_cgen_cpu_desc
, str
, & insn
.fields
, insn
.buffer
, & errmsg
);
345 as_bad ("%s", errmsg
);
349 results
.num_fixups
= 0;
350 /* Doesn't really matter what we pass for RELAX_P here. */
351 gas_cgen_finish_insn (insn
.insn
, insn
.buffer
,
352 CGEN_FIELDS_BITSIZE (& insn
.fields
), 1, &results
);
354 last_insn_had_delay_slot
355 = CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_DELAY_SLOT
);
356 insn_size
= CGEN_INSN_BITSIZE(insn
.insn
);
358 rl_type
= rl_for (insn
);
360 /* We have to mark all the jumps, because we need to adjust them
361 when we delete bytes, but we only need to mark the displacements
362 if they're symbolic - if they're not, we've already picked the
363 shortest opcode by now. The linker, however, will still have to
364 check any operands to see if they're the displacement type, since
365 we don't know (nor record) *which* operands are relaxable. */
367 && rl_type
!= RL_TYPE_NONE
368 && (rl_type
== RL_TYPE_JUMP
|| results
.num_fixups
)
369 && !relaxable (insn
))
372 int addend
= results
.num_fixups
+ 16 * insn_size
/8;
374 switch (rl_for (insn
))
376 case RL_TYPE_JUMP
: reloc
= BFD_RELOC_M32C_RL_JUMP
; break;
377 case RL_TYPE_1ADDR
: reloc
= BFD_RELOC_M32C_RL_1ADDR
; break;
378 case RL_TYPE_2ADDR
: reloc
= BFD_RELOC_M32C_RL_2ADDR
; break;
380 if (insn
.insn
->base
->num
== M32C_INSN_JMP16_S
381 || insn
.insn
->base
->num
== M32C_INSN_JMP32_S
)
384 fix_new (results
.frag
,
385 results
.addr
- results
.frag
->fr_literal
,
386 0, abs_section_sym
, addend
, 0,
391 /* The syntax in the manual says constants begin with '#'.
392 We just ignore it. */
395 md_operand (expressionS
* exp
)
397 /* In case of a syntax error, escape back to try next syntax combo. */
398 if (exp
->X_op
== O_absent
)
399 gas_cgen_md_operand (exp
);
403 md_section_align (segT segment
, valueT size
)
405 int align
= bfd_get_section_alignment (stdoutput
, segment
);
406 return ((size
+ (1 << align
) - 1) & (-1 << align
));
410 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
415 const relax_typeS md_relax_table
[] =
418 1) most positive reach of this state,
419 2) most negative reach of this state,
420 3) how many bytes this mode will have in the variable part of the frag
421 4) which index into the table to try if we can't fit into this one. */
423 /* 0 */ { 0, 0, 0, 0 }, /* unused */
424 /* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */
426 /* 2 */ { 127, -128, 2, 3 }, /* jcnd16_5.b */
427 /* 3 */ { 32767, -32768, 5, 4 }, /* jcnd16_5.w */
428 /* 4 */ { 0, 0, 6, 0 }, /* jcnd16_5.a */
430 /* 5 */ { 127, -128, 2, 6 }, /* jcnd16.b */
431 /* 6 */ { 32767, -32768, 5, 7 }, /* jcnd16.w */
432 /* 7 */ { 0, 0, 6, 0 }, /* jcnd16.a */
434 /* 8 */ { 8, 1, 1, 9 }, /* jmp16.s */
435 /* 9 */ { 127, -128, 2, 10 }, /* jmp16.b */
436 /* 10 */ { 32767, -32768, 3, 11 }, /* jmp16.w */
437 /* 11 */ { 0, 0, 4, 0 }, /* jmp16.a */
439 /* 12 */ { 127, -128, 2, 13 }, /* jcnd32.b */
440 /* 13 */ { 32767, -32768, 5, 14 }, /* jcnd32.w */
441 /* 14 */ { 0, 0, 6, 0 }, /* jcnd32.a */
443 /* 15 */ { 8, 1, 1, 16 }, /* jmp32.s */
444 /* 16 */ { 127, -128, 2, 17 }, /* jmp32.b */
445 /* 17 */ { 32767, -32768, 3, 18 }, /* jmp32.w */
446 /* 18 */ { 0, 0, 4, 0 }, /* jmp32.a */
448 /* 19 */ { 32767, -32768, 3, 20 }, /* jsr16.w */
449 /* 20 */ { 0, 0, 4, 0 }, /* jsr16.a */
450 /* 21 */ { 32767, -32768, 3, 11 }, /* jsr32.w */
451 /* 22 */ { 0, 0, 4, 0 } /* jsr32.a */
455 M32C_MACRO_JCND16_5_W
,
456 M32C_MACRO_JCND16_5_A
,
467 int pcrel_aim_offset
;
468 } subtype_mappings
[] = {
469 /* 0 */ { 0, 0, 0, 0 },
470 /* 1 */ { 0, 0, 0, 0 },
472 /* 2 */ { M32C_INSN_JCND16_5
, 2, -M32C_MACRO_JCND16_5_A
, 1 },
473 /* 3 */ { -M32C_MACRO_JCND16_5_W
, 5, -M32C_MACRO_JCND16_5_A
, 4 },
474 /* 4 */ { -M32C_MACRO_JCND16_5_A
, 6, -M32C_MACRO_JCND16_5_A
, 0 },
476 /* 5 */ { M32C_INSN_JCND16
, 3, -M32C_MACRO_JCND16_A
, 1 },
477 /* 6 */ { -M32C_MACRO_JCND16_W
, 6, -M32C_MACRO_JCND16_A
, 4 },
478 /* 7 */ { -M32C_MACRO_JCND16_A
, 7, -M32C_MACRO_JCND16_A
, 0 },
480 /* 8 */ { M32C_INSN_JMP16_S
, 1, M32C_INSN_JMP16_A
, 0 },
481 /* 9 */ { M32C_INSN_JMP16_B
, 2, M32C_INSN_JMP16_A
, 1 },
482 /* 10 */ { M32C_INSN_JMP16_W
, 3, M32C_INSN_JMP16_A
, 2 },
483 /* 11 */ { M32C_INSN_JMP16_A
, 4, M32C_INSN_JMP16_A
, 0 },
485 /* 12 */ { M32C_INSN_JCND32
, 2, -M32C_MACRO_JCND32_A
, 1 },
486 /* 13 */ { -M32C_MACRO_JCND32_W
, 5, -M32C_MACRO_JCND32_A
, 4 },
487 /* 14 */ { -M32C_MACRO_JCND32_A
, 6, -M32C_MACRO_JCND32_A
, 0 },
489 /* 15 */ { M32C_INSN_JMP32_S
, 1, M32C_INSN_JMP32_A
, 0 },
490 /* 16 */ { M32C_INSN_JMP32_B
, 2, M32C_INSN_JMP32_A
, 1 },
491 /* 17 */ { M32C_INSN_JMP32_W
, 3, M32C_INSN_JMP32_A
, 2 },
492 /* 18 */ { M32C_INSN_JMP32_A
, 4, M32C_INSN_JMP32_A
, 0 },
494 /* 19 */ { M32C_INSN_JSR16_W
, 3, M32C_INSN_JSR16_A
, 2 },
495 /* 20 */ { M32C_INSN_JSR16_A
, 4, M32C_INSN_JSR16_A
, 0 },
496 /* 21 */ { M32C_INSN_JSR32_W
, 3, M32C_INSN_JSR32_A
, 2 },
497 /* 22 */ { M32C_INSN_JSR32_A
, 4, M32C_INSN_JSR32_A
, 0 }
499 #define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
502 m32c_prepare_relax_scan (fragS
*fragP
, offsetT
*aim
, relax_substateT this_state
)
504 symbolS
*symbolP
= fragP
->fr_symbol
;
505 if (symbolP
&& !S_IS_DEFINED (symbolP
))
507 /* Adjust for m32c pcrel not being relative to the next opcode. */
508 *aim
+= subtype_mappings
[this_state
].pcrel_aim_offset
;
512 insn_to_subtype (int insn
)
515 for (i
=0; i
<NUM_MAPPINGS
; i
++)
516 if (insn
== subtype_mappings
[i
].insn
)
518 /*printf("mapping %d used\n", i);*/
524 /* Return an initial guess of the length by which a fragment must grow to
525 hold a branch to reach its destination.
526 Also updates fr_type/fr_subtype as necessary.
528 Called just before doing relaxation.
529 Any symbol that is now undefined will not become defined.
530 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
531 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
532 Although it may not be explicit in the frag, pretend fr_var starts with a
536 md_estimate_size_before_relax (fragS
* fragP
, segT segment ATTRIBUTE_UNUSED
)
538 int where
= fragP
->fr_opcode
- fragP
->fr_literal
;
540 if (fragP
->fr_subtype
== 1)
541 fragP
->fr_subtype
= insn_to_subtype (fragP
->fr_cgen
.insn
->base
->num
);
543 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
547 new_insn
= subtype_mappings
[fragP
->fr_subtype
].insn_for_extern
;
548 fragP
->fr_subtype
= insn_to_subtype (new_insn
);
551 if (fragP
->fr_cgen
.insn
->base
552 && fragP
->fr_cgen
.insn
->base
->num
553 != subtype_mappings
[fragP
->fr_subtype
].insn
554 && subtype_mappings
[fragP
->fr_subtype
].insn
> 0)
556 int new_insn
= subtype_mappings
[fragP
->fr_subtype
].insn
;
559 fragP
->fr_cgen
.insn
= (fragP
->fr_cgen
.insn
560 - fragP
->fr_cgen
.insn
->base
->num
565 return subtype_mappings
[fragP
->fr_subtype
].bytes
- (fragP
->fr_fix
- where
);
568 /* *fragP has been relaxed to its final size, and now needs to have
569 the bytes inside it modified to conform to the new size.
571 Called after relaxation is finished.
572 fragP->fr_type == rs_machine_dependent.
573 fragP->fr_subtype is the subtype of what the address relaxed to. */
576 target_address_for (fragS
*frag
)
578 int rv
= frag
->fr_offset
;
579 symbolS
*sym
= frag
->fr_symbol
;
582 rv
+= S_GET_VALUE (sym
);
584 /*printf("target_address_for returns %d\n", rv);*/
589 md_convert_frag (bfd
* abfd ATTRIBUTE_UNUSED
,
590 segT sec ATTRIBUTE_UNUSED
,
591 fragS
* fragP ATTRIBUTE_UNUSED
)
596 int where
= fragP
->fr_opcode
- fragP
->fr_literal
;
597 int rl_where
= fragP
->fr_opcode
- fragP
->fr_literal
;
598 unsigned char *op
= (unsigned char *)fragP
->fr_opcode
;
603 addend
= target_address_for (fragP
) - (fragP
->fr_address
+ where
);
604 new_insn
= subtype_mappings
[fragP
->fr_subtype
].insn
;
606 fragP
->fr_fix
= where
+ subtype_mappings
[fragP
->fr_subtype
].bytes
;
610 switch (subtype_mappings
[fragP
->fr_subtype
].insn
)
612 case M32C_INSN_JCND16_5
:
614 operand
= M32C_OPERAND_LAB_8_8
;
619 case -M32C_MACRO_JCND16_5_W
:
624 op
[4] = (addend
- 3) >> 8;
625 operand
= M32C_OPERAND_LAB_8_16
;
627 new_insn
= M32C_INSN_JMP16_W
;
633 case -M32C_MACRO_JCND16_5_A
:
637 operand
= M32C_OPERAND_LAB_8_24
;
639 new_insn
= M32C_INSN_JMP16_A
;
646 case M32C_INSN_JCND16
:
648 operand
= M32C_OPERAND_LAB_16_8
;
654 case -M32C_MACRO_JCND16_W
:
659 op
[5] = (addend
- 4) >> 8;
660 operand
= M32C_OPERAND_LAB_8_16
;
662 new_insn
= M32C_INSN_JMP16_W
;
668 case -M32C_MACRO_JCND16_A
:
672 operand
= M32C_OPERAND_LAB_8_24
;
674 new_insn
= M32C_INSN_JMP16_A
;
680 case M32C_INSN_JMP16_S
:
681 op
[0] = 0x60 | ((addend
-2) & 0x07);
682 operand
= M32C_OPERAND_LAB_5_3
;
688 case M32C_INSN_JMP16_B
:
691 operand
= M32C_OPERAND_LAB_8_8
;
697 case M32C_INSN_JMP16_W
:
700 op
[2] = (addend
- 1) >> 8;
701 operand
= M32C_OPERAND_LAB_8_16
;
707 case M32C_INSN_JMP16_A
:
712 operand
= M32C_OPERAND_LAB_8_24
;
718 case M32C_INSN_JCND32
:
720 operand
= M32C_OPERAND_LAB_8_8
;
726 case -M32C_MACRO_JCND32_W
:
731 op
[4] = (addend
- 3) >> 8;
732 operand
= M32C_OPERAND_LAB_8_16
;
734 new_insn
= M32C_INSN_JMP32_W
;
740 case -M32C_MACRO_JCND32_A
:
744 operand
= M32C_OPERAND_LAB_8_24
;
746 new_insn
= M32C_INSN_JMP32_A
;
754 case M32C_INSN_JMP32_S
:
755 addend
= ((addend
-2) & 0x07);
756 op
[0] = 0x4a | (addend
& 0x01) | ((addend
<< 3) & 0x30);
757 operand
= M32C_OPERAND_LAB32_JMP_S
;
763 case M32C_INSN_JMP32_B
:
766 operand
= M32C_OPERAND_LAB_8_8
;
772 case M32C_INSN_JMP32_W
:
775 op
[2] = (addend
- 1) >> 8;
776 operand
= M32C_OPERAND_LAB_8_16
;
782 case M32C_INSN_JMP32_A
:
787 operand
= M32C_OPERAND_LAB_8_24
;
794 case M32C_INSN_JSR16_W
:
797 op
[2] = (addend
- 1) >> 8;
798 operand
= M32C_OPERAND_LAB_8_16
;
804 case M32C_INSN_JSR16_A
:
809 operand
= M32C_OPERAND_LAB_8_24
;
815 case M32C_INSN_JSR32_W
:
818 op
[2] = (addend
- 1) >> 8;
819 operand
= M32C_OPERAND_LAB_8_16
;
825 case M32C_INSN_JSR32_A
:
830 operand
= M32C_OPERAND_LAB_8_24
;
839 printf("\nHey! Need more opcode converters! missing: %d %s\n\n",
841 fragP
->fr_cgen
.insn
->base
->name
);
847 if (operand
!= M32C_OPERAND_LAB_8_24
)
848 fragP
->fr_offset
= (fragP
->fr_address
+ where
);
852 0, abs_section_sym
, rl_addend
, 0,
853 BFD_RELOC_M32C_RL_JUMP
);
856 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
857 || operand
== M32C_OPERAND_LAB_8_24
858 || (m32c_relax
&& (operand
!= M32C_OPERAND_LAB_5_3
859 && operand
!= M32C_OPERAND_LAB32_JMP_S
)))
861 assert (fragP
->fr_cgen
.insn
!= 0);
862 gas_cgen_record_fixup (fragP
,
865 (fragP
->fr_fix
- where
) * 8,
866 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
868 fragP
->fr_cgen
.opinfo
,
869 fragP
->fr_symbol
, fragP
->fr_offset
);
873 /* Functions concerning relocs. */
875 /* The location from which a PC relative jump should be calculated,
876 given a PC relative reloc. */
879 md_pcrel_from_section (fixS
* fixP
, segT sec
)
881 if (fixP
->fx_addsy
!= (symbolS
*) NULL
882 && (! S_IS_DEFINED (fixP
->fx_addsy
)
883 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
884 /* The symbol is undefined (or is defined but not in this section).
885 Let the linker figure it out. */
888 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
);
891 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
892 Returns BFD_RELOC_NONE if no reloc type can be found.
893 *FIXP may be modified if desired. */
895 bfd_reloc_code_real_type
896 md_cgen_lookup_reloc (const CGEN_INSN
* insn ATTRIBUTE_UNUSED
,
897 const CGEN_OPERAND
* operand
,
898 fixS
* fixP ATTRIBUTE_UNUSED
)
900 static const struct op_reloc
{
901 /* A CGEN operand type that can be a relocatable expression. */
902 CGEN_OPERAND_TYPE operand
;
904 /* The appropriate BFD reloc type to use for that. */
905 bfd_reloc_code_real_type reloc
;
907 /* The offset from the start of the instruction to the field to be
908 relocated, in bytes. */
910 } op_reloc_table
[] = {
912 /* PC-REL relocs for 8-bit fields. */
913 { M32C_OPERAND_LAB_8_8
, BFD_RELOC_8_PCREL
, 1 },
914 { M32C_OPERAND_LAB_16_8
, BFD_RELOC_8_PCREL
, 2 },
915 { M32C_OPERAND_LAB_24_8
, BFD_RELOC_8_PCREL
, 3 },
916 { M32C_OPERAND_LAB_32_8
, BFD_RELOC_8_PCREL
, 4 },
917 { M32C_OPERAND_LAB_40_8
, BFD_RELOC_8_PCREL
, 5 },
919 /* PC-REL relocs for 16-bit fields. */
920 { M32C_OPERAND_LAB_8_16
, BFD_RELOC_16_PCREL
, 1 },
922 /* Absolute relocs for 8-bit fields. */
923 { M32C_OPERAND_IMM_8_QI
, BFD_RELOC_8
, 1 },
924 { M32C_OPERAND_IMM_16_QI
, BFD_RELOC_8
, 2 },
925 { M32C_OPERAND_IMM_24_QI
, BFD_RELOC_8
, 3 },
926 { M32C_OPERAND_IMM_32_QI
, BFD_RELOC_8
, 4 },
927 { M32C_OPERAND_IMM_40_QI
, BFD_RELOC_8
, 5 },
928 { M32C_OPERAND_IMM_48_QI
, BFD_RELOC_8
, 6 },
929 { M32C_OPERAND_IMM_56_QI
, BFD_RELOC_8
, 7 },
930 { M32C_OPERAND_DSP_8_S8
, BFD_RELOC_8
, 1 },
931 { M32C_OPERAND_DSP_16_S8
, BFD_RELOC_8
, 2 },
932 { M32C_OPERAND_DSP_24_S8
, BFD_RELOC_8
, 3 },
933 { M32C_OPERAND_DSP_32_S8
, BFD_RELOC_8
, 4 },
934 { M32C_OPERAND_DSP_40_S8
, BFD_RELOC_8
, 5 },
935 { M32C_OPERAND_DSP_48_S8
, BFD_RELOC_8
, 6 },
936 { M32C_OPERAND_DSP_8_U8
, BFD_RELOC_8
, 1 },
937 { M32C_OPERAND_DSP_16_U8
, BFD_RELOC_8
, 2 },
938 { M32C_OPERAND_DSP_24_U8
, BFD_RELOC_8
, 3 },
939 { M32C_OPERAND_DSP_32_U8
, BFD_RELOC_8
, 4 },
940 { M32C_OPERAND_DSP_40_U8
, BFD_RELOC_8
, 5 },
941 { M32C_OPERAND_DSP_48_U8
, BFD_RELOC_8
, 6 },
942 { M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED
, BFD_RELOC_8
, 2 },
943 { M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED
, BFD_RELOC_8
, 2 },
944 { M32C_OPERAND_BITBASE32_24_S11_PREFIXED
, BFD_RELOC_8
, 3 },
945 { M32C_OPERAND_BITBASE32_24_U11_PREFIXED
, BFD_RELOC_8
, 3 },
947 /* Absolute relocs for 16-bit fields. */
948 { M32C_OPERAND_IMM_8_HI
, BFD_RELOC_16
, 1 },
949 { M32C_OPERAND_IMM_16_HI
, BFD_RELOC_16
, 2 },
950 { M32C_OPERAND_IMM_24_HI
, BFD_RELOC_16
, 3 },
951 { M32C_OPERAND_IMM_32_HI
, BFD_RELOC_16
, 4 },
952 { M32C_OPERAND_IMM_40_HI
, BFD_RELOC_16
, 5 },
953 { M32C_OPERAND_IMM_48_HI
, BFD_RELOC_16
, 6 },
954 { M32C_OPERAND_IMM_56_HI
, BFD_RELOC_16
, 7 },
955 { M32C_OPERAND_IMM_64_HI
, BFD_RELOC_16
, 8 },
956 { M32C_OPERAND_DSP_16_S16
, BFD_RELOC_16
, 2 },
957 { M32C_OPERAND_DSP_24_S16
, BFD_RELOC_16
, 3 },
958 { M32C_OPERAND_DSP_32_S16
, BFD_RELOC_16
, 4 },
959 { M32C_OPERAND_DSP_40_S16
, BFD_RELOC_16
, 5 },
960 { M32C_OPERAND_DSP_8_U16
, BFD_RELOC_16
, 1 },
961 { M32C_OPERAND_DSP_16_U16
, BFD_RELOC_16
, 2 },
962 { M32C_OPERAND_DSP_24_U16
, BFD_RELOC_16
, 3 },
963 { M32C_OPERAND_DSP_32_U16
, BFD_RELOC_16
, 4 },
964 { M32C_OPERAND_DSP_40_U16
, BFD_RELOC_16
, 5 },
965 { M32C_OPERAND_DSP_48_U16
, BFD_RELOC_16
, 6 },
966 { M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED
, BFD_RELOC_16
, 2 },
967 { M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED
, BFD_RELOC_16
, 2 },
968 { M32C_OPERAND_BITBASE32_24_S19_PREFIXED
, BFD_RELOC_16
, 3 },
969 { M32C_OPERAND_BITBASE32_24_U19_PREFIXED
, BFD_RELOC_16
, 3 },
971 /* Absolute relocs for 24-bit fields. */
972 { M32C_OPERAND_LAB_8_24
, BFD_RELOC_24
, 1 },
973 { M32C_OPERAND_DSP_8_S24
, BFD_RELOC_24
, 1 },
974 { M32C_OPERAND_DSP_8_U24
, BFD_RELOC_24
, 1 },
975 { M32C_OPERAND_DSP_16_U24
, BFD_RELOC_24
, 2 },
976 { M32C_OPERAND_DSP_24_U24
, BFD_RELOC_24
, 3 },
977 { M32C_OPERAND_DSP_32_U24
, BFD_RELOC_24
, 4 },
978 { M32C_OPERAND_DSP_40_U24
, BFD_RELOC_24
, 5 },
979 { M32C_OPERAND_DSP_48_U24
, BFD_RELOC_24
, 6 },
980 { M32C_OPERAND_DSP_16_U20
, BFD_RELOC_24
, 2 },
981 { M32C_OPERAND_DSP_24_U20
, BFD_RELOC_24
, 3 },
982 { M32C_OPERAND_DSP_32_U20
, BFD_RELOC_24
, 4 },
983 { M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED
, BFD_RELOC_24
, 2 },
984 { M32C_OPERAND_BITBASE32_24_U27_PREFIXED
, BFD_RELOC_24
, 3 },
986 /* Absolute relocs for 32-bit fields. */
987 { M32C_OPERAND_IMM_16_SI
, BFD_RELOC_32
, 2 },
988 { M32C_OPERAND_IMM_24_SI
, BFD_RELOC_32
, 3 },
989 { M32C_OPERAND_IMM_32_SI
, BFD_RELOC_32
, 4 },
990 { M32C_OPERAND_IMM_40_SI
, BFD_RELOC_32
, 5 },
996 for (i
= ARRAY_SIZE (op_reloc_table
); --i
>= 0; )
998 const struct op_reloc
*or = &op_reloc_table
[i
];
1000 if (or->operand
== operand
->type
)
1002 fixP
->fx_where
+= or->offset
;
1003 fixP
->fx_size
-= or->offset
;
1005 if (fixP
->fx_cgen
.opinfo
1006 && fixP
->fx_cgen
.opinfo
!= BFD_RELOC_NONE
)
1007 return fixP
->fx_cgen
.opinfo
;
1015 "Error: tc-m32c.c:md_cgen_lookup_reloc Unimplemented relocation for operand %s\n",
1018 return BFD_RELOC_NONE
;
1022 m32c_cons_fix_new (fragS
* frag
,
1027 bfd_reloc_code_real_type type
;
1035 type
= BFD_RELOC_16
;
1038 type
= BFD_RELOC_24
;
1042 type
= BFD_RELOC_32
;
1045 type
= BFD_RELOC_64
;
1049 fix_new_exp (frag
, where
, (int) size
, exp
, 0, type
);
1053 m32c_apply_fix (struct fix
*f
, valueT
*t
, segT s
)
1055 if (f
->fx_r_type
== BFD_RELOC_M32C_RL_JUMP
1056 || f
->fx_r_type
== BFD_RELOC_M32C_RL_1ADDR
1057 || f
->fx_r_type
== BFD_RELOC_M32C_RL_2ADDR
)
1059 gas_cgen_md_apply_fix (f
, t
, s
);
1063 tc_gen_reloc (asection
*sec
, fixS
*fx
)
1065 if (fx
->fx_r_type
== BFD_RELOC_M32C_RL_JUMP
1066 || fx
->fx_r_type
== BFD_RELOC_M32C_RL_1ADDR
1067 || fx
->fx_r_type
== BFD_RELOC_M32C_RL_2ADDR
)
1071 reloc
= xmalloc (sizeof (* reloc
));
1073 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
1074 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fx
->fx_addsy
);
1075 reloc
->address
= fx
->fx_frag
->fr_address
+ fx
->fx_where
;
1076 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fx
->fx_r_type
);
1077 reloc
->addend
= fx
->fx_offset
;
1081 return gas_cgen_tc_gen_reloc (sec
, fx
);
1084 /* See whether we need to force a relocation into the output file.
1085 This is used to force out switch and PC relative relocations when
1089 m32c_force_relocation (fixS
* fixp
)
1091 int reloc
= fixp
->fx_r_type
;
1093 if (reloc
> (int)BFD_RELOC_UNUSED
)
1095 reloc
-= (int)BFD_RELOC_UNUSED
;
1098 case M32C_OPERAND_DSP_32_S16
:
1099 case M32C_OPERAND_DSP_32_U16
:
1100 case M32C_OPERAND_IMM_32_HI
:
1101 case M32C_OPERAND_DSP_16_S16
:
1102 case M32C_OPERAND_DSP_16_U16
:
1103 case M32C_OPERAND_IMM_16_HI
:
1104 case M32C_OPERAND_DSP_24_S16
:
1105 case M32C_OPERAND_DSP_24_U16
:
1106 case M32C_OPERAND_IMM_24_HI
:
1109 /* If we're doing linker relaxing, we need to keep all the
1110 pc-relative jumps in case we need to fix them due to
1111 deleted bytes between the jump and its destination. */
1112 case M32C_OPERAND_LAB_8_8
:
1113 case M32C_OPERAND_LAB_8_16
:
1114 case M32C_OPERAND_LAB_8_24
:
1115 case M32C_OPERAND_LAB_16_8
:
1116 case M32C_OPERAND_LAB_24_8
:
1117 case M32C_OPERAND_LAB_32_8
:
1118 case M32C_OPERAND_LAB_40_8
:
1127 switch (fixp
->fx_r_type
)
1132 case BFD_RELOC_M32C_RL_JUMP
:
1133 case BFD_RELOC_M32C_RL_1ADDR
:
1134 case BFD_RELOC_M32C_RL_2ADDR
:
1135 case BFD_RELOC_8_PCREL
:
1136 case BFD_RELOC_16_PCREL
:
1144 return generic_force_reloc (fixp
);
1147 /* Write a value out to the object file, using the appropriate endianness. */
1150 md_number_to_chars (char * buf
, valueT val
, int n
)
1152 number_to_chars_littleendian (buf
, val
, n
);
1155 /* Turn a string in input_line_pointer into a floating point constant of type
1156 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1157 emitted is stored in *sizeP . An error message is returned, or NULL on OK. */
1159 /* Equal to MAX_PRECISION in atof-ieee.c. */
1160 #define MAX_LITTLENUMS 6
1163 md_atof (int type
, char * litP
, int * sizeP
)
1167 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1186 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1190 return _("Bad call to md_atof()");
1193 t
= atof_ieee (input_line_pointer
, type
, words
);
1195 input_line_pointer
= t
;
1196 * sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1198 for (i
= 0; i
< prec
; i
++)
1200 md_number_to_chars (litP
, (valueT
) words
[i
],
1201 sizeof (LITTLENUM_TYPE
));
1202 litP
+= sizeof (LITTLENUM_TYPE
);
1209 m32c_fix_adjustable (fixS
* fixP
)
1212 if (fixP
->fx_addsy
== NULL
)
1215 /* We need the symbol name for the VTABLE entries. */
1216 reloc
= fixP
->fx_r_type
;
1217 if (reloc
> (int)BFD_RELOC_UNUSED
)
1219 reloc
-= (int)BFD_RELOC_UNUSED
;
1222 case M32C_OPERAND_DSP_32_S16
:
1223 case M32C_OPERAND_DSP_32_U16
:
1224 case M32C_OPERAND_IMM_32_HI
:
1225 case M32C_OPERAND_DSP_16_S16
:
1226 case M32C_OPERAND_DSP_16_U16
:
1227 case M32C_OPERAND_IMM_16_HI
:
1228 case M32C_OPERAND_DSP_24_S16
:
1229 case M32C_OPERAND_DSP_24_U16
:
1230 case M32C_OPERAND_IMM_24_HI
:
1236 if (fixP
->fx_r_type
== BFD_RELOC_16
)
1240 /* Do not adjust relocations involving symbols in merged sections.
1242 A reloc patching in the value of some symbol S plus some addend A
1243 can be produced in different ways:
1245 1) It might simply be a reference to the data at S + A. Clearly,
1246 if linker merging shift that data around, the value patched in
1247 by the reloc needs to be adjusted accordingly.
1249 2) Or, it might be a reference to S, with A added in as a constant
1250 bias. For example, given code like this:
1256 it would be reasonable for the compiler to rearrange the array
1257 reference to something like:
1261 and emit assembly code that refers to S - (8 * sizeof (int)),
1262 so the subtraction is done entirely at compile-time. In this
1263 case, the reloc's addend A would be -(8 * sizeof (int)), and
1264 shifting around code or data at S + A should not affect the
1265 reloc: the reloc isn't referring to that code or data at all.
1267 The linker has no way of knowing which case it has in hand. So,
1268 to disambiguate, we have the linker always treat reloc addends as
1269 in case 2): they're constants that should be simply added to the
1270 symbol value, just like the reloc says. And we express case 1)
1271 in different way: we have the compiler place a label at the real
1272 target, and reference that label with an addend of zero. (The
1273 compiler is unlikely to reference code using a label plus an
1274 offset anyway, since it doesn't know the sizes of the
1277 The simplification being done by gas/write.c:adjust_reloc_syms,
1278 however, turns the explicit-label usage into the label-plus-
1279 offset usage, re-introducing the ambiguity the compiler avoided.
1280 So we need to disable that simplification for symbols referring
1283 This only affects object size a little bit. */
1284 if (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
)
1293 /* Worker function for m32c_is_colon_insn(). */
1294 static char restore_colon
PARAMS ((int));
1297 restore_colon (int advance_i_l_p_by
)
1301 /* Restore the colon, and advance input_line_pointer to
1302 the end of the new symbol. */
1303 * input_line_pointer
= ':';
1304 input_line_pointer
+= advance_i_l_p_by
;
1305 c
= * input_line_pointer
;
1306 * input_line_pointer
= 0;
1311 /* Determines if the symbol starting at START and ending in
1312 a colon that was at the location pointed to by INPUT_LINE_POINTER
1313 (but which has now been replaced bu a NUL) is in fact an
1314 :Z, :S, :Q, or :G suffix.
1315 If it is, then it restores the colon, advances INPUT_LINE_POINTER
1316 to the real end of the instruction/symbol, and returns the character
1317 that really terminated the symbol. Otherwise it returns 0. */
1319 m32c_is_colon_insn (char *start ATTRIBUTE_UNUSED
)
1321 char * i_l_p
= input_line_pointer
;
1323 /* Check to see if the text following the colon is 'G' */
1324 if (TOLOWER (i_l_p
[1]) == 'g' && (i_l_p
[2] == ' ' || i_l_p
[2] == '\t'))
1325 return restore_colon (2);
1327 /* Check to see if the text following the colon is 'Q' */
1328 if (TOLOWER (i_l_p
[1]) == 'q' && (i_l_p
[2] == ' ' || i_l_p
[2] == '\t'))
1329 return restore_colon (2);
1331 /* Check to see if the text following the colon is 'S' */
1332 if (TOLOWER (i_l_p
[1]) == 's' && (i_l_p
[2] == ' ' || i_l_p
[2] == '\t'))
1333 return restore_colon (2);
1335 /* Check to see if the text following the colon is 'Z' */
1336 if (TOLOWER (i_l_p
[1]) == 'z' && (i_l_p
[2] == ' ' || i_l_p
[2] == '\t'))
1337 return restore_colon (2);