projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
*** empty log message ***
[deliverable/binutils-gdb.git] / gas / config / tc-m32c.c
1 /* tc-m32c.c -- Assembler for the Renesas M32C.
2 Copyright (C) 2005, 2006 Free Software Foundation.
3 Contributed by RedHat.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "as.h"
23 #include "subsegs.h"
24 #include "symcat.h"
25 #include "opcodes/m32c-desc.h"
26 #include "opcodes/m32c-opc.h"
27 #include "cgen.h"
28 #include "elf/common.h"
29 #include "elf/m32c.h"
30 #include "libbfd.h"
31 #include "safe-ctype.h"
32
33 /* Structure to hold all of the different components
34 describing an individual instruction. */
35 typedef struct
36 {
37 const CGEN_INSN * insn;
38 const CGEN_INSN * orig_insn;
39 CGEN_FIELDS fields;
40 #if CGEN_INT_INSN_P
41 CGEN_INSN_INT buffer [1];
42 #define INSN_VALUE(buf) (*(buf))
43 #else
44 unsigned char buffer [CGEN_MAX_INSN_SIZE];
45 #define INSN_VALUE(buf) (buf)
46 #endif
47 char * addr;
48 fragS * frag;
49 int num_fixups;
50 fixS * fixups [GAS_CGEN_MAX_FIXUPS];
51 int indices [MAX_OPERAND_INSTANCES];
52 }
53 m32c_insn;
54
55 #define rl_for(insn) (CGEN_ATTR_CGEN_INSN_RL_TYPE_VALUE (&(insn.insn->base->attrs)))
56 #define relaxable(insn) (CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE (&(insn.insn->base->attrs)))
57
58 const char comment_chars[] = ";";
59 const char line_comment_chars[] = "#";
60 const char line_separator_chars[] = "|";
61 const char EXP_CHARS[] = "eE";
62 const char FLT_CHARS[] = "dD";
63 \f
64 #define M32C_SHORTOPTS ""
65 const char * md_shortopts = M32C_SHORTOPTS;
66
67 /* assembler options */
68 #define OPTION_CPU_M16C (OPTION_MD_BASE)
69 #define OPTION_CPU_M32C (OPTION_MD_BASE + 1)
70 #define OPTION_LINKRELAX (OPTION_MD_BASE + 2)
71
72 struct option md_longopts[] =
73 {
74 { "m16c", no_argument, NULL, OPTION_CPU_M16C },
75 { "m32c", no_argument, NULL, OPTION_CPU_M32C },
76 { "relax", no_argument, NULL, OPTION_LINKRELAX },
77 {NULL, no_argument, NULL, 0}
78 };
79 size_t md_longopts_size = sizeof (md_longopts);
80
81 /* Default machine */
82
83 #define DEFAULT_MACHINE bfd_mach_m16c
84 #define DEFAULT_FLAGS EF_M32C_CPU_M16C
85
86 static unsigned long m32c_mach = bfd_mach_m16c;
87 static int cpu_mach = (1 << MACH_M16C);
88 static int insn_size;
89 static int m32c_relax = 0;
90
91 /* Flags to set in the elf header */
92 static flagword m32c_flags = DEFAULT_FLAGS;
93
94 static char default_isa = 1 << (7 - ISA_M16C);
95 static CGEN_BITSET m32c_isa = {1, & default_isa};
96
97 static void
98 set_isa (enum isa_attr isa_num)
99 {
100 cgen_bitset_set (& m32c_isa, isa_num);
101 }
102
103 static void s_bss (int);
104
105 int
106 md_parse_option (int c, char * arg ATTRIBUTE_UNUSED)
107 {
108 switch (c)
109 {
110 case OPTION_CPU_M16C:
111 m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M16C;
112 m32c_mach = bfd_mach_m16c;
113 cpu_mach = (1 << MACH_M16C);
114 set_isa (ISA_M16C);
115 break;
116
117 case OPTION_CPU_M32C:
118 m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M32C;
119 m32c_mach = bfd_mach_m32c;
120 cpu_mach = (1 << MACH_M32C);
121 set_isa (ISA_M32C);
122 break;
123
124 case OPTION_LINKRELAX:
125 m32c_relax = 1;
126 break;
127
128 default:
129 return 0;
130 }
131 return 1;
132 }
133
134 void
135 md_show_usage (FILE * stream)
136 {
137 fprintf (stream, _(" M32C specific command line options:\n"));
138 }
139
140 static void
141 s_bss (int ignore ATTRIBUTE_UNUSED)
142 {
143 int temp;
144
145 temp = get_absolute_expression ();
146 subseg_set (bss_section, (subsegT) temp);
147 demand_empty_rest_of_line ();
148 }
149
150 /* The target specific pseudo-ops which we support. */
151 const pseudo_typeS md_pseudo_table[] =
152 {
153 { "bss", s_bss, 0},
154 { "3byte", cons, 3 },
155 { "word", cons, 4 },
156 { NULL, NULL, 0 }
157 };
158
159 \f
160 void
161 md_begin (void)
162 {
163 /* Initialize the `cgen' interface. */
164
165 /* Set the machine number and endian. */
166 gas_cgen_cpu_desc = m32c_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach,
167 CGEN_CPU_OPEN_ENDIAN,
168 CGEN_ENDIAN_BIG,
169 CGEN_CPU_OPEN_ISAS, & m32c_isa,
170 CGEN_CPU_OPEN_END);
171
172 m32c_cgen_init_asm (gas_cgen_cpu_desc);
173
174 /* This is a callback from cgen to gas to parse operands. */
175 cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
176
177 /* Set the ELF flags if desired. */
178 if (m32c_flags)
179 bfd_set_private_flags (stdoutput, m32c_flags);
180
181 /* Set the machine type */
182 bfd_default_set_arch_mach (stdoutput, bfd_arch_m32c, m32c_mach);
183
184 insn_size = 0;
185 }
186
187 void
188 m32c_md_end (void)
189 {
190 int i, n_nops;
191
192 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
193 {
194 /* Pad with nops for objdump. */
195 n_nops = (32 - ((insn_size) % 32)) / 8;
196 for (i = 1; i <= n_nops; i++)
197 md_assemble ("nop");
198 }
199 }
200
201 void
202 m32c_start_line_hook (void)
203 {
204 #if 0 /* not necessary....handled in the .cpu file */
205 char *s = input_line_pointer;
206 char *sg;
207
208 for (s = input_line_pointer ; s && s[0] != '\n'; s++)
209 {
210 if (s[0] == ':')
211 {
212 /* Remove :g suffix. Squeeze out blanks. */
213 if (s[1] == 'g')
214 {
215 for (sg = s - 1; sg && sg >= input_line_pointer; sg--)
216 {
217 sg[2] = sg[0];
218 }
219 sg[1] = ' ';
220 sg[2] = ' ';
221 input_line_pointer += 2;
222 }
223 }
224 }
225 #endif
226 }
227
228 /* Process [[indirect-operands]] in instruction str. */
229
230 static bfd_boolean
231 m32c_indirect_operand (char *str)
232 {
233 char *new_str;
234 char *s;
235 char *ns;
236 int ns_len;
237 char *ns_end;
238 enum indirect_type {none, relative, absolute} ;
239 enum indirect_type indirection [3] = { none, none, none };
240 int brace_n [3] = { 0, 0, 0 };
241 int operand;
242
243 s = str;
244 operand = 1;
245 for (s = str; *s; s++)
246 {
247 if (s[0] == ',')
248 operand = 2;
249 /* [abs] where abs is not a0 or a1 */
250 if (s[1] == '[' && ! (s[2] == 'a' && (s[3] == '0' || s[3] == '1'))
251 && (ISBLANK (s[0]) || s[0] == ','))
252 indirection[operand] = absolute;
253 if (s[0] == ']' && s[1] == ']')
254 indirection[operand] = relative;
255 if (s[0] == '[' && s[1] == '[')
256 indirection[operand] = relative;
257 }
258
259 if (indirection[1] == none && indirection[2] == none)
260 return FALSE;
261
262 operand = 1;
263 ns_len = strlen (str);
264 new_str = (char*) xmalloc (ns_len);
265 ns = new_str;
266 ns_end = ns + ns_len;
267
268 for (s = str; *s; s++)
269 {
270 if (s[0] == ',')
271 operand = 2;
272
273 if (s[0] == '[' && ! brace_n[operand])
274 {
275 brace_n[operand] += 1;
276 /* Squeeze [[ to [ if this is an indirect operand. */
277 if (indirection[operand] != none)
278 continue;
279 }
280
281 else if (s[0] == '[' && brace_n[operand])
282 {
283 brace_n[operand] += 1;
284 }
285 else if (s[0] == ']' && s[1] == ']' && indirection[operand] == relative)
286 {
287 s += 1; /* skip one ]. */
288 brace_n[operand] -= 2; /* allow for 2 [. */
289 }
290 else if (s[0] == ']' && indirection[operand] == absolute)
291 {
292 brace_n[operand] -= 1;
293 continue; /* skip closing ]. */
294 }
295 else if (s[0] == ']')
296 {
297 brace_n[operand] -= 1;
298 }
299 *ns = s[0];
300 ns += 1;
301 if (ns >= ns_end)
302 return FALSE;
303 if (s[0] == 0)
304 break;
305 }
306 *ns = '\0';
307 for (operand = 1; operand <= 2; operand++)
308 if (brace_n[operand])
309 {
310 fprintf (stderr, "Unmatched [[operand-%d]] %d\n", operand, brace_n[operand]);
311 }
312
313 if (indirection[1] != none && indirection[2] != none)
314 md_assemble ("src-dest-indirect");
315 else if (indirection[1] != none)
316 md_assemble ("src-indirect");
317 else if (indirection[2] != none)
318 md_assemble ("dest-indirect");
319
320 md_assemble (new_str);
321 free (new_str);
322 return TRUE;
323 }
324
325 void
326 md_assemble (char * str)
327 {
328 static int last_insn_had_delay_slot = 0;
329 m32c_insn insn;
330 char * errmsg;
331 finished_insnS results;
332 int rl_type;
333
334 if (m32c_mach == bfd_mach_m32c && m32c_indirect_operand (str))
335 return;
336
337 /* Initialize GAS's cgen interface for a new instruction. */
338 gas_cgen_init_parse ();
339
340 insn.insn = m32c_cgen_assemble_insn
341 (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
342
343 if (!insn.insn)
344 {
345 as_bad ("%s", errmsg);
346 return;
347 }
348
349 results.num_fixups = 0;
350 /* Doesn't really matter what we pass for RELAX_P here. */
351 gas_cgen_finish_insn (insn.insn, insn.buffer,
352 CGEN_FIELDS_BITSIZE (& insn.fields), 1, &results);
353
354 last_insn_had_delay_slot
355 = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
356 insn_size = CGEN_INSN_BITSIZE(insn.insn);
357
358 rl_type = rl_for (insn);
359
360 /* We have to mark all the jumps, because we need to adjust them
361 when we delete bytes, but we only need to mark the displacements
362 if they're symbolic - if they're not, we've already picked the
363 shortest opcode by now. The linker, however, will still have to
364 check any operands to see if they're the displacement type, since
365 we don't know (nor record) *which* operands are relaxable. */
366 if (m32c_relax
367 && rl_type != RL_TYPE_NONE
368 && (rl_type == RL_TYPE_JUMP || results.num_fixups)
369 && !relaxable (insn))
370 {
371 int reloc = 0;
372 int addend = results.num_fixups + 16 * insn_size/8;
373
374 switch (rl_for (insn))
375 {
376 case RL_TYPE_JUMP: reloc = BFD_RELOC_M32C_RL_JUMP; break;
377 case RL_TYPE_1ADDR: reloc = BFD_RELOC_M32C_RL_1ADDR; break;
378 case RL_TYPE_2ADDR: reloc = BFD_RELOC_M32C_RL_2ADDR; break;
379 }
380 if (insn.insn->base->num == M32C_INSN_JMP16_S
381 || insn.insn->base->num == M32C_INSN_JMP32_S)
382 addend = 0x10;
383
384 fix_new (results.frag,
385 results.addr - results.frag->fr_literal,
386 0, abs_section_sym, addend, 0,
387 reloc);
388 }
389 }
390
391 /* The syntax in the manual says constants begin with '#'.
392 We just ignore it. */
393
394 void
395 md_operand (expressionS * exp)
396 {
397 /* In case of a syntax error, escape back to try next syntax combo. */
398 if (exp->X_op == O_absent)
399 gas_cgen_md_operand (exp);
400 }
401
402 valueT
403 md_section_align (segT segment, valueT size)
404 {
405 int align = bfd_get_section_alignment (stdoutput, segment);
406 return ((size + (1 << align) - 1) & (-1 << align));
407 }
408
409 symbolS *
410 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
411 {
412 return 0;
413 }
414 \f
415 const relax_typeS md_relax_table[] =
416 {
417 /* The fields are:
418 1) most positive reach of this state,
419 2) most negative reach of this state,
420 3) how many bytes this mode will have in the variable part of the frag
421 4) which index into the table to try if we can't fit into this one. */
422
423 /* 0 */ { 0, 0, 0, 0 }, /* unused */
424 /* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */
425
426 /* 2 */ { 127, -128, 2, 3 }, /* jcnd16_5.b */
427 /* 3 */ { 32767, -32768, 5, 4 }, /* jcnd16_5.w */
428 /* 4 */ { 0, 0, 6, 0 }, /* jcnd16_5.a */
429
430 /* 5 */ { 127, -128, 2, 6 }, /* jcnd16.b */
431 /* 6 */ { 32767, -32768, 5, 7 }, /* jcnd16.w */
432 /* 7 */ { 0, 0, 6, 0 }, /* jcnd16.a */
433
434 /* 8 */ { 8, 1, 1, 9 }, /* jmp16.s */
435 /* 9 */ { 127, -128, 2, 10 }, /* jmp16.b */
436 /* 10 */ { 32767, -32768, 3, 11 }, /* jmp16.w */
437 /* 11 */ { 0, 0, 4, 0 }, /* jmp16.a */
438
439 /* 12 */ { 127, -128, 2, 13 }, /* jcnd32.b */
440 /* 13 */ { 32767, -32768, 5, 14 }, /* jcnd32.w */
441 /* 14 */ { 0, 0, 6, 0 }, /* jcnd32.a */
442
443 /* 15 */ { 8, 1, 1, 16 }, /* jmp32.s */
444 /* 16 */ { 127, -128, 2, 17 }, /* jmp32.b */
445 /* 17 */ { 32767, -32768, 3, 18 }, /* jmp32.w */
446 /* 18 */ { 0, 0, 4, 0 }, /* jmp32.a */
447
448 /* 19 */ { 32767, -32768, 3, 20 }, /* jsr16.w */
449 /* 20 */ { 0, 0, 4, 0 }, /* jsr16.a */
450 /* 21 */ { 32767, -32768, 3, 11 }, /* jsr32.w */
451 /* 22 */ { 0, 0, 4, 0 } /* jsr32.a */
452 };
453
454 enum {
455 M32C_MACRO_JCND16_5_W,
456 M32C_MACRO_JCND16_5_A,
457 M32C_MACRO_JCND16_W,
458 M32C_MACRO_JCND16_A,
459 M32C_MACRO_JCND32_W,
460 M32C_MACRO_JCND32_A,
461 } M32C_Macros;
462
463 static struct {
464 int insn;
465 int bytes;
466 int insn_for_extern;
467 int pcrel_aim_offset;
468 } subtype_mappings[] = {
469 /* 0 */ { 0, 0, 0, 0 },
470 /* 1 */ { 0, 0, 0, 0 },
471
472 /* 2 */ { M32C_INSN_JCND16_5, 2, -M32C_MACRO_JCND16_5_A, 1 },
473 /* 3 */ { -M32C_MACRO_JCND16_5_W, 5, -M32C_MACRO_JCND16_5_A, 4 },
474 /* 4 */ { -M32C_MACRO_JCND16_5_A, 6, -M32C_MACRO_JCND16_5_A, 0 },
475
476 /* 5 */ { M32C_INSN_JCND16, 3, -M32C_MACRO_JCND16_A, 1 },
477 /* 6 */ { -M32C_MACRO_JCND16_W, 6, -M32C_MACRO_JCND16_A, 4 },
478 /* 7 */ { -M32C_MACRO_JCND16_A, 7, -M32C_MACRO_JCND16_A, 0 },
479
480 /* 8 */ { M32C_INSN_JMP16_S, 1, M32C_INSN_JMP16_A, 0 },
481 /* 9 */ { M32C_INSN_JMP16_B, 2, M32C_INSN_JMP16_A, 1 },
482 /* 10 */ { M32C_INSN_JMP16_W, 3, M32C_INSN_JMP16_A, 2 },
483 /* 11 */ { M32C_INSN_JMP16_A, 4, M32C_INSN_JMP16_A, 0 },
484
485 /* 12 */ { M32C_INSN_JCND32, 2, -M32C_MACRO_JCND32_A, 1 },
486 /* 13 */ { -M32C_MACRO_JCND32_W, 5, -M32C_MACRO_JCND32_A, 4 },
487 /* 14 */ { -M32C_MACRO_JCND32_A, 6, -M32C_MACRO_JCND32_A, 0 },
488
489 /* 15 */ { M32C_INSN_JMP32_S, 1, M32C_INSN_JMP32_A, 0 },
490 /* 16 */ { M32C_INSN_JMP32_B, 2, M32C_INSN_JMP32_A, 1 },
491 /* 17 */ { M32C_INSN_JMP32_W, 3, M32C_INSN_JMP32_A, 2 },
492 /* 18 */ { M32C_INSN_JMP32_A, 4, M32C_INSN_JMP32_A, 0 },
493
494 /* 19 */ { M32C_INSN_JSR16_W, 3, M32C_INSN_JSR16_A, 2 },
495 /* 20 */ { M32C_INSN_JSR16_A, 4, M32C_INSN_JSR16_A, 0 },
496 /* 21 */ { M32C_INSN_JSR32_W, 3, M32C_INSN_JSR32_A, 2 },
497 /* 22 */ { M32C_INSN_JSR32_A, 4, M32C_INSN_JSR32_A, 0 }
498 };
499 #define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
500
501 void
502 m32c_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state)
503 {
504 symbolS *symbolP = fragP->fr_symbol;
505 if (symbolP && !S_IS_DEFINED (symbolP))
506 *aim = 0;
507 /* Adjust for m32c pcrel not being relative to the next opcode. */
508 *aim += subtype_mappings[this_state].pcrel_aim_offset;
509 }
510
511 static int
512 insn_to_subtype (int insn)
513 {
514 unsigned int i;
515 for (i=0; i<NUM_MAPPINGS; i++)
516 if (insn == subtype_mappings[i].insn)
517 {
518 /*printf("mapping %d used\n", i);*/
519 return i;
520 }
521 abort ();
522 }
523
524 /* Return an initial guess of the length by which a fragment must grow to
525 hold a branch to reach its destination.
526 Also updates fr_type/fr_subtype as necessary.
527
528 Called just before doing relaxation.
529 Any symbol that is now undefined will not become defined.
530 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
531 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
532 Although it may not be explicit in the frag, pretend fr_var starts with a
533 0 value. */
534
535 int
536 md_estimate_size_before_relax (fragS * fragP, segT segment ATTRIBUTE_UNUSED)
537 {
538 int where = fragP->fr_opcode - fragP->fr_literal;
539
540 if (fragP->fr_subtype == 1)
541 fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num);
542
543 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
544 {
545 int new_insn;
546
547 new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern;
548 fragP->fr_subtype = insn_to_subtype (new_insn);
549 }
550
551 if (fragP->fr_cgen.insn->base
552 && fragP->fr_cgen.insn->base->num
553 != subtype_mappings[fragP->fr_subtype].insn
554 && subtype_mappings[fragP->fr_subtype].insn > 0)
555 {
556 int new_insn= subtype_mappings[fragP->fr_subtype].insn;
557 if (new_insn >= 0)
558 {
559 fragP->fr_cgen.insn = (fragP->fr_cgen.insn
560 - fragP->fr_cgen.insn->base->num
561 + new_insn);
562 }
563 }
564
565 return subtype_mappings[fragP->fr_subtype].bytes - (fragP->fr_fix - where);
566 }
567
568 /* *fragP has been relaxed to its final size, and now needs to have
569 the bytes inside it modified to conform to the new size.
570
571 Called after relaxation is finished.
572 fragP->fr_type == rs_machine_dependent.
573 fragP->fr_subtype is the subtype of what the address relaxed to. */
574
575 static int
576 target_address_for (fragS *frag)
577 {
578 int rv = frag->fr_offset;
579 symbolS *sym = frag->fr_symbol;
580
581 if (sym)
582 rv += S_GET_VALUE (sym);
583
584 /*printf("target_address_for returns %d\n", rv);*/
585 return rv;
586 }
587
588 void
589 md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
590 segT sec ATTRIBUTE_UNUSED,
591 fragS * fragP ATTRIBUTE_UNUSED)
592 {
593 int addend;
594 int operand;
595 int new_insn;
596 int where = fragP->fr_opcode - fragP->fr_literal;
597 int rl_where = fragP->fr_opcode - fragP->fr_literal;
598 unsigned char *op = (unsigned char *)fragP->fr_opcode;
599 int op_base = 0;
600 int op_op = 0;
601 int rl_addend = 0;
602
603 addend = target_address_for (fragP) - (fragP->fr_address + where);
604 new_insn = subtype_mappings[fragP->fr_subtype].insn;
605
606 fragP->fr_fix = where + subtype_mappings[fragP->fr_subtype].bytes;
607
608 op_base = 0;
609
610 switch (subtype_mappings[fragP->fr_subtype].insn)
611 {
612 case M32C_INSN_JCND16_5:
613 op[1] = addend - 1;
614 operand = M32C_OPERAND_LAB_8_8;
615 op_op = 1;
616 rl_addend = 0x21;
617 break;
618
619 case -M32C_MACRO_JCND16_5_W:
620 op[0] ^= 0x04;
621 op[1] = 4;
622 op[2] = 0xf4;
623 op[3] = addend - 3;
624 op[4] = (addend - 3) >> 8;
625 operand = M32C_OPERAND_LAB_8_16;
626 where += 2;
627 new_insn = M32C_INSN_JMP16_W;
628 op_base = 2;
629 op_op = 3;
630 rl_addend = 0x51;
631 break;
632
633 case -M32C_MACRO_JCND16_5_A:
634 op[0] ^= 0x04;
635 op[1] = 5;
636 op[2] = 0xfc;
637 operand = M32C_OPERAND_LAB_8_24;
638 where += 2;
639 new_insn = M32C_INSN_JMP16_A;
640 op_base = 2;
641 op_op = 3;
642 rl_addend = 0x61;
643 break;
644
645
646 case M32C_INSN_JCND16:
647 op[2] = addend - 2;
648 operand = M32C_OPERAND_LAB_16_8;
649 op_base = 0;
650 op_op = 2;
651 rl_addend = 0x31;
652 break;
653
654 case -M32C_MACRO_JCND16_W:
655 op[1] ^= 0x04;
656 op[2] = 4;
657 op[3] = 0xf4;
658 op[4] = addend - 4;
659 op[5] = (addend - 4) >> 8;
660 operand = M32C_OPERAND_LAB_8_16;
661 where += 3;
662 new_insn = M32C_INSN_JMP16_W;
663 op_base = 3;
664 op_op = 4;
665 rl_addend = 0x61;
666 break;
667
668 case -M32C_MACRO_JCND16_A:
669 op[1] ^= 0x04;
670 op[2] = 5;
671 op[3] = 0xfc;
672 operand = M32C_OPERAND_LAB_8_24;
673 where += 3;
674 new_insn = M32C_INSN_JMP16_A;
675 op_base = 3;
676 op_op = 4;
677 rl_addend = 0x71;
678 break;
679
680 case M32C_INSN_JMP16_S:
681 op[0] = 0x60 | ((addend-2) & 0x07);
682 operand = M32C_OPERAND_LAB_5_3;
683 op_base = 0;
684 op_op = 0;
685 rl_addend = 0x10;
686 break;
687
688 case M32C_INSN_JMP16_B:
689 op[0] = 0xfe;
690 op[1] = addend - 1;
691 operand = M32C_OPERAND_LAB_8_8;
692 op_base = 0;
693 op_op = 1;
694 rl_addend = 0x21;
695 break;
696
697 case M32C_INSN_JMP16_W:
698 op[0] = 0xf4;
699 op[1] = addend - 1;
700 op[2] = (addend - 1) >> 8;
701 operand = M32C_OPERAND_LAB_8_16;
702 op_base = 0;
703 op_op = 1;
704 rl_addend = 0x31;
705 break;
706
707 case M32C_INSN_JMP16_A:
708 op[0] = 0xfc;
709 op[1] = 0;
710 op[2] = 0;
711 op[3] = 0;
712 operand = M32C_OPERAND_LAB_8_24;
713 op_base = 0;
714 op_op = 1;
715 rl_addend = 0x41;
716 break;
717
718 case M32C_INSN_JCND32:
719 op[1] = addend - 1;
720 operand = M32C_OPERAND_LAB_8_8;
721 op_base = 0;
722 op_op = 1;
723 rl_addend = 0x21;
724 break;
725
726 case -M32C_MACRO_JCND32_W:
727 op[0] ^= 0x40;
728 op[1] = 4;
729 op[2] = 0xce;
730 op[3] = addend - 3;
731 op[4] = (addend - 3) >> 8;
732 operand = M32C_OPERAND_LAB_8_16;
733 where += 2;
734 new_insn = M32C_INSN_JMP32_W;
735 op_base = 2;
736 op_op = 3;
737 rl_addend = 0x51;
738 break;
739
740 case -M32C_MACRO_JCND32_A:
741 op[0] ^= 0x40;
742 op[1] = 5;
743 op[2] = 0xcc;
744 operand = M32C_OPERAND_LAB_8_24;
745 where += 2;
746 new_insn = M32C_INSN_JMP32_A;
747 op_base = 2;
748 op_op = 3;
749 rl_addend = 0x61;
750 break;
751
752
753
754 case M32C_INSN_JMP32_S:
755 addend = ((addend-2) & 0x07);
756 op[0] = 0x4a | (addend & 0x01) | ((addend << 3) & 0x30);
757 operand = M32C_OPERAND_LAB32_JMP_S;
758 op_base = 0;
759 op_op = 0;
760 rl_addend = 0x10;
761 break;
762
763 case M32C_INSN_JMP32_B:
764 op[0] = 0xbb;
765 op[1] = addend - 1;
766 operand = M32C_OPERAND_LAB_8_8;
767 op_base = 0;
768 op_op = 1;
769 rl_addend = 0x21;
770 break;
771
772 case M32C_INSN_JMP32_W:
773 op[0] = 0xce;
774 op[1] = addend - 1;
775 op[2] = (addend - 1) >> 8;
776 operand = M32C_OPERAND_LAB_8_16;
777 op_base = 0;
778 op_op = 1;
779 rl_addend = 0x31;
780 break;
781
782 case M32C_INSN_JMP32_A:
783 op[0] = 0xcc;
784 op[1] = 0;
785 op[2] = 0;
786 op[3] = 0;
787 operand = M32C_OPERAND_LAB_8_24;
788 op_base = 0;
789 op_op = 1;
790 rl_addend = 0x41;
791 break;
792
793
794 case M32C_INSN_JSR16_W:
795 op[0] = 0xf5;
796 op[1] = addend - 1;
797 op[2] = (addend - 1) >> 8;
798 operand = M32C_OPERAND_LAB_8_16;
799 op_base = 0;
800 op_op = 1;
801 rl_addend = 0x31;
802 break;
803
804 case M32C_INSN_JSR16_A:
805 op[0] = 0xfd;
806 op[1] = 0;
807 op[2] = 0;
808 op[3] = 0;
809 operand = M32C_OPERAND_LAB_8_24;
810 op_base = 0;
811 op_op = 1;
812 rl_addend = 0x41;
813 break;
814
815 case M32C_INSN_JSR32_W:
816 op[0] = 0xcf;
817 op[1] = addend - 1;
818 op[2] = (addend - 1) >> 8;
819 operand = M32C_OPERAND_LAB_8_16;
820 op_base = 0;
821 op_op = 1;
822 rl_addend = 0x31;
823 break;
824
825 case M32C_INSN_JSR32_A:
826 op[0] = 0xcd;
827 op[1] = 0;
828 op[2] = 0;
829 op[3] = 0;
830 operand = M32C_OPERAND_LAB_8_24;
831 op_base = 0;
832 op_op = 1;
833 rl_addend = 0x41;
834 break;
835
836
837
838 default:
839 printf("\nHey! Need more opcode converters! missing: %d %s\n\n",
840 fragP->fr_subtype,
841 fragP->fr_cgen.insn->base->name);
842 abort();
843 }
844
845 if (m32c_relax)
846 {
847 if (operand != M32C_OPERAND_LAB_8_24)
848 fragP->fr_offset = (fragP->fr_address + where);
849
850 fix_new (fragP,
851 rl_where,
852 0, abs_section_sym, rl_addend, 0,
853 BFD_RELOC_M32C_RL_JUMP);
854 }
855
856 if (S_GET_SEGMENT (fragP->fr_symbol) != sec
857 || operand == M32C_OPERAND_LAB_8_24
858 || (m32c_relax && (operand != M32C_OPERAND_LAB_5_3
859 && operand != M32C_OPERAND_LAB32_JMP_S)))
860 {
861 assert (fragP->fr_cgen.insn != 0);
862 gas_cgen_record_fixup (fragP,
863 where,
864 fragP->fr_cgen.insn,
865 (fragP->fr_fix - where) * 8,
866 cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
867 operand),
868 fragP->fr_cgen.opinfo,
869 fragP->fr_symbol, fragP->fr_offset);
870 }
871 }
872 \f
873 /* Functions concerning relocs. */
874
875 /* The location from which a PC relative jump should be calculated,
876 given a PC relative reloc. */
877
878 long
879 md_pcrel_from_section (fixS * fixP, segT sec)
880 {
881 if (fixP->fx_addsy != (symbolS *) NULL
882 && (! S_IS_DEFINED (fixP->fx_addsy)
883 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
884 /* The symbol is undefined (or is defined but not in this section).
885 Let the linker figure it out. */
886 return 0;
887
888 return (fixP->fx_frag->fr_address + fixP->fx_where);
889 }
890
891 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
892 Returns BFD_RELOC_NONE if no reloc type can be found.
893 *FIXP may be modified if desired. */
894
895 bfd_reloc_code_real_type
896 md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED,
897 const CGEN_OPERAND * operand,
898 fixS * fixP ATTRIBUTE_UNUSED)
899 {
900 static const struct op_reloc {
901 /* A CGEN operand type that can be a relocatable expression. */
902 CGEN_OPERAND_TYPE operand;
903
904 /* The appropriate BFD reloc type to use for that. */
905 bfd_reloc_code_real_type reloc;
906
907 /* The offset from the start of the instruction to the field to be
908 relocated, in bytes. */
909 int offset;
910 } op_reloc_table[] = {
911
912 /* PC-REL relocs for 8-bit fields. */
913 { M32C_OPERAND_LAB_8_8, BFD_RELOC_8_PCREL, 1 },
914 { M32C_OPERAND_LAB_16_8, BFD_RELOC_8_PCREL, 2 },
915 { M32C_OPERAND_LAB_24_8, BFD_RELOC_8_PCREL, 3 },
916 { M32C_OPERAND_LAB_32_8, BFD_RELOC_8_PCREL, 4 },
917 { M32C_OPERAND_LAB_40_8, BFD_RELOC_8_PCREL, 5 },
918
919 /* PC-REL relocs for 16-bit fields. */
920 { M32C_OPERAND_LAB_8_16, BFD_RELOC_16_PCREL, 1 },
921
922 /* Absolute relocs for 8-bit fields. */
923 { M32C_OPERAND_IMM_8_QI, BFD_RELOC_8, 1 },
924 { M32C_OPERAND_IMM_16_QI, BFD_RELOC_8, 2 },
925 { M32C_OPERAND_IMM_24_QI, BFD_RELOC_8, 3 },
926 { M32C_OPERAND_IMM_32_QI, BFD_RELOC_8, 4 },
927 { M32C_OPERAND_IMM_40_QI, BFD_RELOC_8, 5 },
928 { M32C_OPERAND_IMM_48_QI, BFD_RELOC_8, 6 },
929 { M32C_OPERAND_IMM_56_QI, BFD_RELOC_8, 7 },
930 { M32C_OPERAND_DSP_8_S8, BFD_RELOC_8, 1 },
931 { M32C_OPERAND_DSP_16_S8, BFD_RELOC_8, 2 },
932 { M32C_OPERAND_DSP_24_S8, BFD_RELOC_8, 3 },
933 { M32C_OPERAND_DSP_32_S8, BFD_RELOC_8, 4 },
934 { M32C_OPERAND_DSP_40_S8, BFD_RELOC_8, 5 },
935 { M32C_OPERAND_DSP_48_S8, BFD_RELOC_8, 6 },
936 { M32C_OPERAND_DSP_8_U8, BFD_RELOC_8, 1 },
937 { M32C_OPERAND_DSP_16_U8, BFD_RELOC_8, 2 },
938 { M32C_OPERAND_DSP_24_U8, BFD_RELOC_8, 3 },
939 { M32C_OPERAND_DSP_32_U8, BFD_RELOC_8, 4 },
940 { M32C_OPERAND_DSP_40_U8, BFD_RELOC_8, 5 },
941 { M32C_OPERAND_DSP_48_U8, BFD_RELOC_8, 6 },
942 { M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, BFD_RELOC_8, 2 },
943 { M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, BFD_RELOC_8, 2 },
944 { M32C_OPERAND_BITBASE32_24_S11_PREFIXED, BFD_RELOC_8, 3 },
945 { M32C_OPERAND_BITBASE32_24_U11_PREFIXED, BFD_RELOC_8, 3 },
946
947 /* Absolute relocs for 16-bit fields. */
948 { M32C_OPERAND_IMM_8_HI, BFD_RELOC_16, 1 },
949 { M32C_OPERAND_IMM_16_HI, BFD_RELOC_16, 2 },
950 { M32C_OPERAND_IMM_24_HI, BFD_RELOC_16, 3 },
951 { M32C_OPERAND_IMM_32_HI, BFD_RELOC_16, 4 },
952 { M32C_OPERAND_IMM_40_HI, BFD_RELOC_16, 5 },
953 { M32C_OPERAND_IMM_48_HI, BFD_RELOC_16, 6 },
954 { M32C_OPERAND_IMM_56_HI, BFD_RELOC_16, 7 },
955 { M32C_OPERAND_IMM_64_HI, BFD_RELOC_16, 8 },
956 { M32C_OPERAND_DSP_16_S16, BFD_RELOC_16, 2 },
957 { M32C_OPERAND_DSP_24_S16, BFD_RELOC_16, 3 },
958 { M32C_OPERAND_DSP_32_S16, BFD_RELOC_16, 4 },
959 { M32C_OPERAND_DSP_40_S16, BFD_RELOC_16, 5 },
960 { M32C_OPERAND_DSP_8_U16, BFD_RELOC_16, 1 },
961 { M32C_OPERAND_DSP_16_U16, BFD_RELOC_16, 2 },
962 { M32C_OPERAND_DSP_24_U16, BFD_RELOC_16, 3 },
963 { M32C_OPERAND_DSP_32_U16, BFD_RELOC_16, 4 },
964 { M32C_OPERAND_DSP_40_U16, BFD_RELOC_16, 5 },
965 { M32C_OPERAND_DSP_48_U16, BFD_RELOC_16, 6 },
966 { M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, BFD_RELOC_16, 2 },
967 { M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, BFD_RELOC_16, 2 },
968 { M32C_OPERAND_BITBASE32_24_S19_PREFIXED, BFD_RELOC_16, 3 },
969 { M32C_OPERAND_BITBASE32_24_U19_PREFIXED, BFD_RELOC_16, 3 },
970
971 /* Absolute relocs for 24-bit fields. */
972 { M32C_OPERAND_LAB_8_24, BFD_RELOC_24, 1 },
973 { M32C_OPERAND_DSP_8_S24, BFD_RELOC_24, 1 },
974 { M32C_OPERAND_DSP_8_U24, BFD_RELOC_24, 1 },
975 { M32C_OPERAND_DSP_16_U24, BFD_RELOC_24, 2 },
976 { M32C_OPERAND_DSP_24_U24, BFD_RELOC_24, 3 },
977 { M32C_OPERAND_DSP_32_U24, BFD_RELOC_24, 4 },
978 { M32C_OPERAND_DSP_40_U24, BFD_RELOC_24, 5 },
979 { M32C_OPERAND_DSP_48_U24, BFD_RELOC_24, 6 },
980 { M32C_OPERAND_DSP_16_U20, BFD_RELOC_24, 2 },
981 { M32C_OPERAND_DSP_24_U20, BFD_RELOC_24, 3 },
982 { M32C_OPERAND_DSP_32_U20, BFD_RELOC_24, 4 },
983 { M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, BFD_RELOC_24, 2 },
984 { M32C_OPERAND_BITBASE32_24_U27_PREFIXED, BFD_RELOC_24, 3 },
985
986 /* Absolute relocs for 32-bit fields. */
987 { M32C_OPERAND_IMM_16_SI, BFD_RELOC_32, 2 },
988 { M32C_OPERAND_IMM_24_SI, BFD_RELOC_32, 3 },
989 { M32C_OPERAND_IMM_32_SI, BFD_RELOC_32, 4 },
990 { M32C_OPERAND_IMM_40_SI, BFD_RELOC_32, 5 },
991
992 };
993
994 int i;
995
996 for (i = ARRAY_SIZE (op_reloc_table); --i >= 0; )
997 {
998 const struct op_reloc *or = &op_reloc_table[i];
999
1000 if (or->operand == operand->type)
1001 {
1002 fixP->fx_where += or->offset;
1003 fixP->fx_size -= or->offset;
1004
1005 if (fixP->fx_cgen.opinfo
1006 && fixP->fx_cgen.opinfo != BFD_RELOC_NONE)
1007 return fixP->fx_cgen.opinfo;
1008
1009 return or->reloc;
1010 }
1011 }
1012
1013 fprintf
1014 (stderr,
1015 "Error: tc-m32c.c:md_cgen_lookup_reloc Unimplemented relocation for operand %s\n",
1016 operand->name);
1017
1018 return BFD_RELOC_NONE;
1019 }
1020
1021 void
1022 m32c_apply_fix (struct fix *f, valueT *t, segT s)
1023 {
1024 if (f->fx_r_type == BFD_RELOC_M32C_RL_JUMP
1025 || f->fx_r_type == BFD_RELOC_M32C_RL_1ADDR
1026 || f->fx_r_type == BFD_RELOC_M32C_RL_2ADDR)
1027 return;
1028 gas_cgen_md_apply_fix (f, t, s);
1029 }
1030
1031 arelent *
1032 tc_gen_reloc (asection *sec, fixS *fx)
1033 {
1034 if (fx->fx_r_type == BFD_RELOC_M32C_RL_JUMP
1035 || fx->fx_r_type == BFD_RELOC_M32C_RL_1ADDR
1036 || fx->fx_r_type == BFD_RELOC_M32C_RL_2ADDR)
1037 {
1038 arelent * reloc;
1039
1040 reloc = xmalloc (sizeof (* reloc));
1041
1042 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
1043 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fx->fx_addsy);
1044 reloc->address = fx->fx_frag->fr_address + fx->fx_where;
1045 reloc->howto = bfd_reloc_type_lookup (stdoutput, fx->fx_r_type);
1046 reloc->addend = fx->fx_offset;
1047 return reloc;
1048
1049 }
1050 return gas_cgen_tc_gen_reloc (sec, fx);
1051 }
1052
1053 /* See whether we need to force a relocation into the output file.
1054 This is used to force out switch and PC relative relocations when
1055 relaxing. */
1056
1057 int
1058 m32c_force_relocation (fixS * fixp)
1059 {
1060 int reloc = fixp->fx_r_type;
1061
1062 if (reloc > (int)BFD_RELOC_UNUSED)
1063 {
1064 reloc -= (int)BFD_RELOC_UNUSED;
1065 switch (reloc)
1066 {
1067 case M32C_OPERAND_DSP_32_S16:
1068 case M32C_OPERAND_DSP_32_U16:
1069 case M32C_OPERAND_IMM_32_HI:
1070 case M32C_OPERAND_DSP_16_S16:
1071 case M32C_OPERAND_DSP_16_U16:
1072 case M32C_OPERAND_IMM_16_HI:
1073 case M32C_OPERAND_DSP_24_S16:
1074 case M32C_OPERAND_DSP_24_U16:
1075 case M32C_OPERAND_IMM_24_HI:
1076 return 1;
1077
1078 /* If we're doing linker relaxing, we need to keep all the
1079 pc-relative jumps in case we need to fix them due to
1080 deleted bytes between the jump and its destination. */
1081 case M32C_OPERAND_LAB_8_8:
1082 case M32C_OPERAND_LAB_8_16:
1083 case M32C_OPERAND_LAB_8_24:
1084 case M32C_OPERAND_LAB_16_8:
1085 case M32C_OPERAND_LAB_24_8:
1086 case M32C_OPERAND_LAB_32_8:
1087 case M32C_OPERAND_LAB_40_8:
1088 if (m32c_relax)
1089 return 1;
1090 default:
1091 break;
1092 }
1093 }
1094 else
1095 {
1096 switch (fixp->fx_r_type)
1097 {
1098 case BFD_RELOC_16:
1099 return 1;
1100
1101 case BFD_RELOC_M32C_RL_JUMP:
1102 case BFD_RELOC_M32C_RL_1ADDR:
1103 case BFD_RELOC_M32C_RL_2ADDR:
1104 case BFD_RELOC_8_PCREL:
1105 case BFD_RELOC_16_PCREL:
1106 if (m32c_relax)
1107 return 1;
1108 default:
1109 break;
1110 }
1111 }
1112
1113 return generic_force_reloc (fixp);
1114 }
1115 \f
1116 /* Write a value out to the object file, using the appropriate endianness. */
1117
1118 void
1119 md_number_to_chars (char * buf, valueT val, int n)
1120 {
1121 number_to_chars_littleendian (buf, val, n);
1122 }
1123
1124 /* Turn a string in input_line_pointer into a floating point constant of type
1125 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1126 emitted is stored in *sizeP . An error message is returned, or NULL on OK. */
1127
1128 /* Equal to MAX_PRECISION in atof-ieee.c. */
1129 #define MAX_LITTLENUMS 6
1130
1131 char *
1132 md_atof (int type, char * litP, int * sizeP)
1133 {
1134 int i;
1135 int prec;
1136 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1137 char * t;
1138
1139 switch (type)
1140 {
1141 case 'f':
1142 case 'F':
1143 case 's':
1144 case 'S':
1145 prec = 2;
1146 break;
1147
1148 case 'd':
1149 case 'D':
1150 case 'r':
1151 case 'R':
1152 prec = 4;
1153 break;
1154
1155 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1156
1157 default:
1158 * sizeP = 0;
1159 return _("Bad call to md_atof()");
1160 }
1161
1162 t = atof_ieee (input_line_pointer, type, words);
1163 if (t)
1164 input_line_pointer = t;
1165 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1166
1167 for (i = 0; i < prec; i++)
1168 {
1169 md_number_to_chars (litP, (valueT) words[i],
1170 sizeof (LITTLENUM_TYPE));
1171 litP += sizeof (LITTLENUM_TYPE);
1172 }
1173
1174 return 0;
1175 }
1176
1177 bfd_boolean
1178 m32c_fix_adjustable (fixS * fixP)
1179 {
1180 int reloc;
1181 if (fixP->fx_addsy == NULL)
1182 return 1;
1183
1184 /* We need the symbol name for the VTABLE entries. */
1185 reloc = fixP->fx_r_type;
1186 if (reloc > (int)BFD_RELOC_UNUSED)
1187 {
1188 reloc -= (int)BFD_RELOC_UNUSED;
1189 switch (reloc)
1190 {
1191 case M32C_OPERAND_DSP_32_S16:
1192 case M32C_OPERAND_DSP_32_U16:
1193 case M32C_OPERAND_IMM_32_HI:
1194 case M32C_OPERAND_DSP_16_S16:
1195 case M32C_OPERAND_DSP_16_U16:
1196 case M32C_OPERAND_IMM_16_HI:
1197 case M32C_OPERAND_DSP_24_S16:
1198 case M32C_OPERAND_DSP_24_U16:
1199 case M32C_OPERAND_IMM_24_HI:
1200 return 0;
1201 }
1202 }
1203 else
1204 {
1205 if (fixP->fx_r_type == BFD_RELOC_16)
1206 return 0;
1207 }
1208
1209 /* Do not adjust relocations involving symbols in merged sections.
1210
1211 A reloc patching in the value of some symbol S plus some addend A
1212 can be produced in different ways:
1213
1214 1) It might simply be a reference to the data at S + A. Clearly,
1215 if linker merging shift that data around, the value patched in
1216 by the reloc needs to be adjusted accordingly.
1217
1218 2) Or, it might be a reference to S, with A added in as a constant
1219 bias. For example, given code like this:
1220
1221 static int S[100];
1222
1223 ... S[i - 8] ...
1224
1225 it would be reasonable for the compiler to rearrange the array
1226 reference to something like:
1227
1228 ... (S-8)[i] ...
1229
1230 and emit assembly code that refers to S - (8 * sizeof (int)),
1231 so the subtraction is done entirely at compile-time. In this
1232 case, the reloc's addend A would be -(8 * sizeof (int)), and
1233 shifting around code or data at S + A should not affect the
1234 reloc: the reloc isn't referring to that code or data at all.
1235
1236 The linker has no way of knowing which case it has in hand. So,
1237 to disambiguate, we have the linker always treat reloc addends as
1238 in case 2): they're constants that should be simply added to the
1239 symbol value, just like the reloc says. And we express case 1)
1240 in different way: we have the compiler place a label at the real
1241 target, and reference that label with an addend of zero. (The
1242 compiler is unlikely to reference code using a label plus an
1243 offset anyway, since it doesn't know the sizes of the
1244 instructions.)
1245
1246 The simplification being done by gas/write.c:adjust_reloc_syms,
1247 however, turns the explicit-label usage into the label-plus-
1248 offset usage, re-introducing the ambiguity the compiler avoided.
1249 So we need to disable that simplification for symbols referring
1250 to merged data.
1251
1252 This only affects object size a little bit. */
1253 if (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE)
1254 return 0;
1255
1256 if (m32c_relax)
1257 return 0;
1258
1259 return 1;
1260 }
1261
1262 /* Worker function for m32c_is_colon_insn(). */
1263 static char restore_colon PARAMS ((int));
1264
1265 static char
1266 restore_colon (int advance_i_l_p_by)
1267 {
1268 char c;
1269
1270 /* Restore the colon, and advance input_line_pointer to
1271 the end of the new symbol. */
1272 * input_line_pointer = ':';
1273 input_line_pointer += advance_i_l_p_by;
1274 c = * input_line_pointer;
1275 * input_line_pointer = 0;
1276
1277 return c;
1278 }
1279
1280 /* Determines if the symbol starting at START and ending in
1281 a colon that was at the location pointed to by INPUT_LINE_POINTER
1282 (but which has now been replaced bu a NUL) is in fact an
1283 :Z, :S, :Q, or :G suffix.
1284 If it is, then it restores the colon, advances INPUT_LINE_POINTER
1285 to the real end of the instruction/symbol, and returns the character
1286 that really terminated the symbol. Otherwise it returns 0. */
1287 char
1288 m32c_is_colon_insn (char *start ATTRIBUTE_UNUSED)
1289 {
1290 char * i_l_p = input_line_pointer;
1291
1292 /* Check to see if the text following the colon is 'G' */
1293 if (TOLOWER (i_l_p[1]) == 'g' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1294 return restore_colon (2);
1295
1296 /* Check to see if the text following the colon is 'Q' */
1297 if (TOLOWER (i_l_p[1]) == 'q' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1298 return restore_colon (2);
1299
1300 /* Check to see if the text following the colon is 'S' */
1301 if (TOLOWER (i_l_p[1]) == 's' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1302 return restore_colon (2);
1303
1304 /* Check to see if the text following the colon is 'Z' */
1305 if (TOLOWER (i_l_p[1]) == 'z' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1306 return restore_colon (2);
1307
1308 return 0;
1309 }
GDB Binutils - Deliverables
This page took 0.062886 seconds and 5 git commands to generate.