1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 /* Linked list of symbols that are debugging symbols to be defined as the
30 beginning of the current instruction. */
31 typedef struct sym_link
33 struct sym_link
*next
;
37 static sym_linkS
*debug_sym_link
= (sym_linkS
*)0;
39 /* Structure to hold all of the different components describing
40 an individual instruction. */
43 const CGEN_INSN
* insn
;
44 const CGEN_INSN
* orig_insn
;
47 CGEN_INSN_INT buffer
[1];
48 #define INSN_VALUE(buf) (*(buf))
50 unsigned char buffer
[CGEN_MAX_INSN_SIZE
];
51 #define INSN_VALUE(buf) (buf)
56 fixS
* fixups
[GAS_CGEN_MAX_FIXUPS
];
57 int indices
[MAX_OPERAND_INSTANCES
];
58 sym_linkS
*debug_sym_link
;
62 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
63 boundary (i.e. was the first of two 16 bit insns). */
64 static m32r_insn prev_insn
;
66 /* Non-zero if we've seen a relaxable insn since the last 32 bit
68 static int seen_relaxable_p
= 0;
70 /* Non-zero if -relax specified, in which case sufficient relocs are output
71 for the linker to do relaxing.
72 We do simple forms of relaxing internally, but they are always done.
73 This flag does not apply to them. */
74 static int m32r_relax
;
76 #if 0 /* not supported yet */
77 /* If non-NULL, pointer to cpu description file to read.
78 This allows runtime additions to the assembler. */
79 static const char * m32r_cpu_desc
;
82 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
83 Each high/shigh reloc must be paired with it's low cousin in order to
84 properly calculate the addend in a relocatable link (since there is a
85 potential carry from the low to the high/shigh).
86 This option is off by default though for user-written assembler code it
87 might make sense to make the default be on (i.e. have gcc pass a flag
88 to turn it off). This warning must not be on for GCC created code as
89 optimization may delete the low but not the high/shigh (at least we
90 shouldn't assume or require it to). */
91 static int warn_unmatched_high
= 0;
93 /* start-sanitize-m32rx */
94 /* Non-zero if -m32rx has been specified, in which case support for the
95 extended M32RX instruction set should be enabled. */
96 static int enable_m32rx
= 0;
98 /* Non-zero if -m32rx -hidden has been specified, in which case support for
99 the special M32RX instruction set should be enabled. */
100 static int enable_special
= 0;
102 /* Non-zero if the programmer should be warned when an explicit parallel
103 instruction might have constraint violations. */
104 static int warn_explicit_parallel_conflicts
= 1;
106 /* Non-zero if insns can be made parallel. */
108 /* end-sanitize-m32rx */
110 /* stuff for .scomm symbols. */
111 static segT sbss_section
;
112 static asection scom_section
;
113 static asymbol scom_symbol
;
115 const char comment_chars
[] = ";";
116 const char line_comment_chars
[] = "#";
117 const char line_separator_chars
[] = "";
118 const char EXP_CHARS
[] = "eE";
119 const char FLT_CHARS
[] = "dD";
121 /* Relocations against symbols are done in two
122 parts, with a HI relocation and a LO relocation. Each relocation
123 has only 16 bits of space to store an addend. This means that in
124 order for the linker to handle carries correctly, it must be able
125 to locate both the HI and the LO relocation. This means that the
126 relocations must appear in order in the relocation table.
128 In order to implement this, we keep track of each unmatched HI
129 relocation. We then sort them so that they immediately precede the
130 corresponding LO relocation. */
134 struct m32r_hi_fixup
* next
; /* Next HI fixup. */
135 fixS
* fixp
; /* This fixup. */
136 segT seg
; /* The section this fixup is in. */
140 /* The list of unmatched HI relocs. */
142 static struct m32r_hi_fixup
* m32r_hi_fixup_list
;
145 /* start-sanitize-m32rx */
152 if (stdoutput
!= NULL
)
153 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
154 enable_m32rx
? bfd_mach_m32rx
: bfd_mach_m32r
);
156 /* end-sanitize-m32rx */
158 #define M32R_SHORTOPTS ""
159 /* start-sanitize-m32rx */
160 #undef M32R_SHORTOPTS
161 #define M32R_SHORTOPTS "O"
162 /* end-sanitize-m32rx */
163 const char * md_shortopts
= M32R_SHORTOPTS
;
165 struct option md_longopts
[] =
167 /* start-sanitize-m32rx */
168 #define OPTION_M32RX (OPTION_MD_BASE)
169 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
170 #define OPTION_WARN_PARALLEL (OPTION_MD_BASE + 1)
171 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
172 {"Wp", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
173 #define OPTION_NO_WARN_PARALLEL (OPTION_MD_BASE + 2)
174 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
175 {"Wnp", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
176 #define OPTION_SPECIAL (OPTION_MD_BASE + 3)
177 {"hidden", no_argument
, NULL
, OPTION_SPECIAL
},
178 /* end-sanitize-m32rx */
180 /* Sigh. I guess all warnings must now have both variants. */
181 #define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4)
182 {"warn-unmatched-high", OPTION_WARN_UNMATCHED
},
183 {"Wuh", OPTION_WARN_UNMATCHED
},
184 #define OPTION_NO_WARN_UNMATCHED (OPTION_MD_BASE + 5)
185 {"no-warn-unmatched-high", OPTION_WARN_UNMATCHED
},
186 {"Wnuh", OPTION_WARN_UNMATCHED
},
188 #if 0 /* not supported yet */
189 #define OPTION_RELAX (OPTION_MD_BASE + 6)
190 {"relax", no_argument
, NULL
, OPTION_RELAX
},
191 #define OPTION_CPU_DESC (OPTION_MD_BASE + 7)
192 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
195 {NULL
, no_argument
, NULL
, 0}
197 size_t md_longopts_size
= sizeof (md_longopts
);
200 md_parse_option (c
, arg
)
206 /* start-sanitize-m32rx */
215 case OPTION_WARN_PARALLEL
:
216 warn_explicit_parallel_conflicts
= 1;
219 case OPTION_NO_WARN_PARALLEL
:
220 warn_explicit_parallel_conflicts
= 0;
228 extern char * myname
;
230 /* Pretend that we do not recognise this option. */
231 fprintf (stderr
, _("%s: unrecognised option: -hidden\n"), myname
);
235 /* end-sanitize-m32rx */
237 case OPTION_WARN_UNMATCHED
:
238 warn_unmatched_high
= 1;
241 case OPTION_NO_WARN_UNMATCHED
:
242 warn_unmatched_high
= 0;
245 #if 0 /* not supported yet */
249 case OPTION_CPU_DESC
:
261 md_show_usage (stream
)
264 fprintf (stream
, _(" M32R specific command line options:\n"));
266 /* start-sanitize-m32rx */
267 fprintf (stream
, _("\
268 -m32rx support the extended m32rx instruction set\n"));
269 fprintf (stream
, _("\
270 -O try to combine instructions in parallel\n"));
272 fprintf (stream
, _("\
273 -warn-explicit-parallel-conflicts warn when parallel instructions\n"));
274 fprintf (stream
, _("\
275 violate contraints\n"));
276 fprintf (stream
, _("\
277 -no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
278 fprintf (stream
, _("\
279 instructions violate contraints\n"));
280 fprintf (stream
, _("\
281 -Wp synonym for -warn-explicit-parallel-conflicts\n"));
282 fprintf (stream
, _("\
283 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
284 /* end-sanitize-m32rx */
286 fprintf (stream
, _("\
287 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
288 fprintf (stream
, _("\
289 -no-warn-unmatched-high do not warn about missing low relocs\n"));
290 fprintf (stream
, _("\
291 -Wuh synonym for -warn-unmatched-high\n"));
292 fprintf (stream
, _("\
293 -Wnuh synonym for -no-warn-unmatched-high\n"));
296 fprintf (stream
, _("\
297 -relax create linker relaxable code\n"));
298 fprintf (stream
, _("\
299 -cpu-desc provide runtime cpu description file\n"));
303 static void fill_insn
PARAMS ((int));
304 static void m32r_scomm
PARAMS ((int));
305 static void debug_sym
PARAMS ((int));
306 static void expand_debug_syms
PARAMS ((sym_linkS
*, int));
308 /* Set by md_assemble for use by m32r_fill_insn. */
309 static subsegT prev_subseg
;
310 static segT prev_seg
;
312 /* The target specific pseudo-ops which we support. */
313 const pseudo_typeS md_pseudo_table
[] =
316 { "fillinsn", fill_insn
, 0 },
317 { "scomm", m32r_scomm
, 0 },
318 { "debugsym", debug_sym
, 0 },
319 /* start-sanitize-m32rx */
320 /* Not documented as so far there is no need for them.... */
321 { "m32r", allow_m32rx
, 0 },
322 { "m32rx", allow_m32rx
, 1 },
323 /* end-sanitize-m32rx */
327 /* FIXME: Should be machine generated. */
328 #define NOP_INSN 0x7000
329 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
331 /* When we align the .text section, insert the correct NOP pattern.
332 N is the power of 2 alignment. LEN is the length of pattern FILL.
333 MAX is the maximum number of characters to skip when doing the alignment,
334 or 0 if there is no maximum. */
337 m32r_do_align (n
, fill
, len
, max
)
343 /* Only do this if the fill pattern wasn't specified. */
345 && (now_seg
->flags
& SEC_CODE
) != 0
346 /* Only do this special handling if aligning to at least a
349 /* Only do this special handling if we're allowed to emit at
351 && (max
== 0 || max
> 1))
353 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
356 /* First align to a 2 byte boundary, in case there is an odd .byte. */
357 /* FIXME: How much memory will cause gas to use when assembling a big
358 program? Perhaps we can avoid the frag_align call? */
359 frag_align (1, 0, 0);
361 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
363 frag_align_pattern (2, nop_pattern
, sizeof nop_pattern
, 0);
364 /* If doing larger alignments use a repeating sequence of appropriate
368 static const unsigned char multi_nop_pattern
[] =
369 { 0x70, 0x00, 0xf0, 0x00 };
370 frag_align_pattern (n
, multi_nop_pattern
, sizeof multi_nop_pattern
,
374 prev_insn
.insn
= NULL
;
381 /* If the last instruction was the first of 2 16 bit insns,
382 output a nop to move the PC to a 32 bit boundary.
384 This is done via an alignment specification since branch relaxing
385 may make it unnecessary.
387 Internally, we need to output one of these each time a 32 bit insn is
388 seen after an insn that is relaxable. */
394 (void) m32r_do_align (2, NULL
, 0, 0);
395 prev_insn
.insn
= NULL
;
396 seen_relaxable_p
= 0;
399 /* Record the symbol so that when we output the insn, we can create
400 a symbol that is at the start of the instruction. This is used
401 to emit the label for the start of a breakpoint without causing
402 the assembler to emit a NOP if the previous instruction was a
403 16 bit instruction. */
411 register char *end_name
;
412 register symbolS
*symbolP
;
413 register sym_linkS
*link
;
415 name
= input_line_pointer
;
416 delim
= get_symbol_end ();
417 end_name
= input_line_pointer
;
419 if ((symbolP
= symbol_find (name
)) == NULL
420 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
422 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
425 symbol_table_insert (symbolP
);
426 if (S_IS_DEFINED (symbolP
) && S_GET_SEGMENT (symbolP
) != reg_section
)
427 /* xgettext:c-format */
428 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
432 link
= (sym_linkS
*) xmalloc (sizeof (sym_linkS
));
433 link
->symbol
= symbolP
;
434 link
->next
= debug_sym_link
;
435 debug_sym_link
= link
;
440 demand_empty_rest_of_line ();
443 /* Second pass to expanding the debug symbols, go through linked
444 list of symbols and reassign the address. */
447 expand_debug_syms (syms
, align
)
451 char *save_input_line
= input_line_pointer
;
452 sym_linkS
*next_syms
;
457 (void) m32r_do_align (align
, NULL
, 0, 0);
458 for (; syms
!= (sym_linkS
*)0; syms
= next_syms
)
460 symbolS
*symbolP
= syms
->symbol
;
461 next_syms
= syms
->next
;
462 input_line_pointer
= ".\n";
463 pseudo_set (symbolP
);
467 input_line_pointer
= save_input_line
;
470 /* Cover function to fill_insn called after a label and at end of assembly.
471 The result is always 1: we're called in a conditional to see if the
472 current line is a label. */
475 m32r_fill_insn (done
)
478 if (prev_seg
!= NULL
)
481 subsegT subseg
= now_subseg
;
483 subseg_set (prev_seg
, prev_subseg
);
487 subseg_set (seg
, subseg
);
490 if (done
&& debug_sym_link
)
492 expand_debug_syms (debug_sym_link
, 1);
493 debug_sym_link
= (sym_linkS
*)0;
506 /* Initialize the `cgen' interface. */
508 /* Set the machine number and endian. */
509 gas_cgen_opcode_desc
= m32r_cgen_opcode_open (0 /* mach number */,
512 : CGEN_ENDIAN_LITTLE
);
513 m32r_cgen_init_asm (gas_cgen_opcode_desc
);
515 /* This is a callback from cgen to gas to parse operands. */
516 cgen_set_parse_operand_fn (gas_cgen_opcode_desc
, gas_cgen_parse_operand
);
518 #if 0 /* not supported yet */
519 /* If a runtime cpu description file was provided, parse it. */
520 if (m32r_cpu_desc
!= NULL
)
524 errmsg
= cgen_read_cpu_file (gas_cgen_opcode_desc
, m32r_cpu_desc
);
526 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
530 /* Save the current subseg so we can restore it [it's the default one and
531 we don't want the initial section to be .sbss]. */
535 /* The sbss section is for local .scomm symbols. */
536 sbss_section
= subseg_new (".sbss", 0);
538 /* This is copied from perform_an_assembly_pass. */
539 applicable
= bfd_applicable_section_flags (stdoutput
);
540 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
542 #if 0 /* What does this do? [see perform_an_assembly_pass] */
543 seg_info (bss_section
)->bss
= 1;
546 subseg_set (seg
, subseg
);
548 /* We must construct a fake section similar to bfd_com_section
549 but with the name .scommon. */
550 scom_section
= bfd_com_section
;
551 scom_section
.name
= ".scommon";
552 scom_section
.output_section
= & scom_section
;
553 scom_section
.symbol
= & scom_symbol
;
554 scom_section
.symbol_ptr_ptr
= & scom_section
.symbol
;
555 scom_symbol
= * bfd_com_section
.symbol
;
556 scom_symbol
.name
= ".scommon";
557 scom_symbol
.section
= & scom_section
;
559 /* start-sanitize-m32rx */
560 allow_m32rx (enable_m32rx
);
561 /* end-sanitize-m32rx */
564 /* start-sanitize-m32rx */
566 #define OPERAND_IS_COND_BIT(operand, indices, index) \
567 (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \
568 || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \
569 && (indices [index] == 0 || indices [index] == 1)))
571 /* Returns true if an output of instruction 'a' is referenced by an operand
572 of instruction 'b'. If 'check_outputs' is true then b's outputs are
573 checked, otherwise its inputs are examined. */
576 first_writes_to_seconds_operands (a
, b
, check_outputs
)
579 const int check_outputs
;
581 const CGEN_OPERAND_INSTANCE
* a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
582 const CGEN_OPERAND_INSTANCE
* b_ops
= CGEN_INSN_OPERANDS (b
->insn
);
585 /* If at least one of the instructions takes no operands, then there is
586 nothing to check. There really are instructions without operands,
588 if (a_operands
== NULL
|| b_ops
== NULL
)
591 /* Scan the operand list of 'a' looking for an output operand. */
593 CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
;
594 a_index
++, a_operands
++)
596 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) == CGEN_OPERAND_INSTANCE_OUTPUT
)
599 const CGEN_OPERAND_INSTANCE
* b_operands
= b_ops
;
602 The Condition bit 'C' is a shadow of the CBR register (control
603 register 1) and also a shadow of bit 31 of the program status
604 word (control register 0). For now this is handled here, rather
607 if (OPERAND_IS_COND_BIT (a_operands
, a
->indices
, a_index
))
609 /* Scan operand list of 'b' looking for another reference to the
610 condition bit, which goes in the right direction. */
612 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
613 b_index
++, b_operands
++)
615 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
616 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
617 && OPERAND_IS_COND_BIT (b_operands
, b
->indices
, b_index
))
623 /* Scan operand list of 'b' looking for an operand that
624 references the same hardware element, and which goes in the
627 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
628 b_index
++, b_operands
++)
630 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
631 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
632 && (CGEN_OPERAND_INSTANCE_HW (b_operands
) == CGEN_OPERAND_INSTANCE_HW (a_operands
))
633 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
643 /* Returns true if the insn can (potentially) alter the program counter. */
649 #if 0 /* Once PC operands are working.... */
650 const CGEN_OPERAND_INSTANCE
* a_operands
== CGEN_INSN_OPERANDS (a
->insn
);
652 if (a_operands
== NULL
)
655 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
)
657 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
) != NULL
658 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
)) == M32R_OPERAND_PC
)
664 if (CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_UNCOND_CTI
)
665 || CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_COND_CTI
))
671 /* Returns NULL if the two 16 bit insns can be executed in parallel,
672 otherwise it returns a pointer to an error message explaining why not. */
675 can_make_parallel (a
, b
)
682 /* Make sure the instructions are the right length. */
683 if ( CGEN_FIELDS_BITSIZE (& a
->fields
) != 16
684 || CGEN_FIELDS_BITSIZE (& b
->fields
) != 16)
687 if (first_writes_to_seconds_operands (a
, b
, true))
688 return _("Instructions write to the same destination register.");
690 a_pipe
= CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_PIPE
);
691 b_pipe
= CGEN_INSN_ATTR (b
->insn
, CGEN_INSN_PIPE
);
693 /* Make sure that the instructions use the correct execution pipelines. */
694 if ( a_pipe
== PIPE_NONE
695 || b_pipe
== PIPE_NONE
)
696 return _("Instructions do not use parallel execution pipelines.");
698 /* Leave this test for last, since it is the only test that can
699 go away if the instructions are swapped, and we want to make
700 sure that any other errors are detected before this happens. */
701 if ( a_pipe
== PIPE_S
703 return _("Instructions share the same execution pipeline");
708 /* Force the top bit of the second 16-bit insn to be set. */
711 make_parallel (buffer
)
712 CGEN_INSN_BYTES_PTR buffer
;
717 buffer
[CGEN_OPCODE_ENDIAN (gas_cgen_opcode_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
722 /* Same as make_parallel except buffer contains the bytes in target order. */
725 target_make_parallel (buffer
)
728 buffer
[CGEN_OPCODE_ENDIAN (gas_cgen_opcode_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
732 /* Assemble two instructions with an explicit parallel operation (||) or
733 sequential operation (->). */
736 assemble_two_insns (str
, str2
, parallel_p
)
745 char save_str2
= *str2
;
747 * str2
= 0; /* Seperate the two instructions. */
749 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
750 so that the parallel instruction will start on a 32 bit boundary. */
754 first
.debug_sym_link
= debug_sym_link
;
755 debug_sym_link
= (sym_linkS
*)0;
757 /* Parse the first instruction. */
758 if (! (first
.insn
= m32r_cgen_assemble_insn
759 (gas_cgen_opcode_desc
, str
, & first
.fields
, first
.buffer
, & errmsg
)))
766 if (CGEN_FIELDS_BITSIZE (&first
.fields
) != 16)
768 /* xgettext:c-format */
769 as_bad (_("not a 16 bit instruction '%s'"), str
);
772 else if (! enable_special
773 && CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_SPECIAL
))
775 /* xgettext:c-format */
776 as_bad (_("unknown instruction '%s'"), str
);
779 else if (! enable_m32rx
780 /* FIXME: Need standard macro to perform this test. */
781 && CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
783 /* xgettext:c-format */
784 as_bad (_("instruction '%s' is for the M32RX only"), str
);
788 /* Check to see if this is an allowable parallel insn. */
789 if (parallel_p
&& CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
791 /* xgettext:c-format */
792 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
796 *str2
= save_str2
; /* Restore the original assembly text, just in case it is needed. */
797 str3
= str
; /* Save the original string pointer. */
798 str
= str2
+ 2; /* Advanced past the parsed string. */
799 str2
= str3
; /* Remember the entire string in case it is needed for error messages. */
801 /* Convert the opcode to lower case. */
805 while (isspace (*s2
++))
810 while (isalnum (*s2
))
812 if (isupper ((unsigned char) *s2
))
818 /* Preserve any fixups that have been generated and reset the list to empty. */
819 gas_cgen_save_fixups ();
821 /* Get the indices of the operands of the instruction. */
822 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
823 doesn't seem right. Perhaps allow passing fields like we do insn. */
824 /* FIXME: ALIAS insns do not have operands, so we use this function
825 to find the equivalent insn and overwrite the value stored in our
826 structure. We still need the original insn, however, since this
827 may have certain attributes that are not present in the unaliased
828 version (eg relaxability). When aliases behave differently this
829 may have to change. */
830 first
.orig_insn
= first
.insn
;
831 first
.insn
= m32r_cgen_lookup_get_insn_operands
832 (gas_cgen_opcode_desc
, NULL
, INSN_VALUE (first
.buffer
), 16,
835 if (first
.insn
== NULL
)
836 as_fatal (_("internal error: lookup/get operands failed"));
838 second
.debug_sym_link
= NULL
;
840 /* Parse the second instruction. */
841 if (! (second
.insn
= m32r_cgen_assemble_insn
842 (gas_cgen_opcode_desc
, str
, & second
.fields
, second
.buffer
, & errmsg
)))
849 if (CGEN_FIELDS_BITSIZE (&second
.fields
) != 16)
851 /* xgettext:c-format */
852 as_bad (_("not a 16 bit instruction '%s'"), str
);
855 else if (! enable_special
856 && CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_SPECIAL
))
858 /* xgettext:c-format */
859 as_bad (_("unknown instruction '%s'"), str
);
862 else if (! enable_m32rx
863 && CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
865 /* xgettext:c-format */
866 as_bad (_("instruction '%s' is for the M32RX only"), str
);
870 /* Check to see if this is an allowable parallel insn. */
871 if (parallel_p
&& CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
873 /* xgettext:c-format */
874 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
878 if (parallel_p
&& ! enable_m32rx
)
880 if (CGEN_INSN_NUM (first
.insn
) != M32R_INSN_NOP
881 && CGEN_INSN_NUM (second
.insn
) != M32R_INSN_NOP
)
883 /* xgettext:c-format */
884 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2
);
889 /* Get the indices of the operands of the instruction. */
890 second
.orig_insn
= second
.insn
;
891 second
.insn
= m32r_cgen_lookup_get_insn_operands
892 (gas_cgen_opcode_desc
, NULL
, INSN_VALUE (second
.buffer
), 16,
895 if (second
.insn
== NULL
)
896 as_fatal (_("internal error: lookup/get operands failed"));
898 /* We assume that if the first instruction writes to a register that is
899 read by the second instruction it is because the programmer intended
900 this to happen, (after all they have explicitly requested that these
901 two instructions be executed in parallel). Although if the global
902 variable warn_explicit_parallel_conflicts is true then we do generate
903 a warning message. Similarly we assume that parallel branch and jump
904 instructions are deliberate and should not produce errors. */
906 if (parallel_p
&& warn_explicit_parallel_conflicts
)
908 if (first_writes_to_seconds_operands (& first
, & second
, false))
909 /* xgettext:c-format */
910 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2
);
912 if (first_writes_to_seconds_operands (& second
, & first
, false))
913 /* xgettext:c-format */
914 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2
);
917 if (!parallel_p
|| (errmsg
= (char *) can_make_parallel (& first
, & second
)) == NULL
)
919 /* Get the fixups for the first instruction. */
920 gas_cgen_swap_fixups ();
923 expand_debug_syms (first
.debug_sym_link
, 1);
924 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
925 CGEN_FIELDS_BITSIZE (& first
.fields
), 0, NULL
);
927 /* Force the top bit of the second insn to be set. */
929 make_parallel (second
.buffer
);
931 /* Get its fixups. */
932 gas_cgen_restore_fixups ();
935 expand_debug_syms (second
.debug_sym_link
, 1);
936 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
937 CGEN_FIELDS_BITSIZE (& second
.fields
), 0, NULL
);
939 /* Try swapping the instructions to see if they work that way. */
940 else if (can_make_parallel (& second
, & first
) == NULL
)
942 /* Write out the second instruction first. */
943 expand_debug_syms (second
.debug_sym_link
, 1);
944 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
945 CGEN_FIELDS_BITSIZE (& second
.fields
), 0, NULL
);
947 /* Force the top bit of the first instruction to be set. */
948 make_parallel (first
.buffer
);
950 /* Get the fixups for the first instruction. */
951 gas_cgen_restore_fixups ();
953 /* Write out the first instruction. */
954 expand_debug_syms (first
.debug_sym_link
, 1);
955 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
956 CGEN_FIELDS_BITSIZE (& first
.fields
), 0, NULL
);
960 as_bad ("'%s': %s", str2
, errmsg
);
964 /* Set these so m32r_fill_insn can use them. */
966 prev_subseg
= now_subseg
;
969 /* end-sanitize-m32rx */
980 /* Initialize GAS's cgen interface for a new instruction. */
981 gas_cgen_init_parse ();
983 /* start-sanitize-m32rx */
984 /* Look for a parallel instruction seperator. */
985 if ((str2
= strstr (str
, "||")) != NULL
)
987 assemble_two_insns (str
, str2
, 1);
991 /* Also look for a sequential instruction seperator. */
992 if ((str2
= strstr (str
, "->")) != NULL
)
994 assemble_two_insns (str
, str2
, 0);
997 /* end-sanitize-m32rx */
999 insn
.debug_sym_link
= debug_sym_link
;
1000 debug_sym_link
= (sym_linkS
*)0;
1002 insn
.insn
= m32r_cgen_assemble_insn
1003 (gas_cgen_opcode_desc
, str
, & insn
.fields
, insn
.buffer
, & errmsg
);
1011 /* start-sanitize-m32rx */
1012 if (! enable_special
1013 && CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_SPECIAL
))
1015 /* xgettext:c-format */
1016 as_bad (_("unknown instruction '%s'"), str
);
1019 else if (! enable_m32rx
1020 && CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
1022 /* xgettext:c-format */
1023 as_bad (_("instruction '%s' is for the M32RX only"), str
);
1026 /* end-sanitize-m32rx */
1028 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
1030 /* 32 bit insns must live on 32 bit boundaries. */
1031 if (prev_insn
.insn
|| seen_relaxable_p
)
1033 /* ??? If calling fill_insn too many times turns us into a memory
1034 pig, can we call a fn to assemble a nop instead of
1035 !seen_relaxable_p? */
1039 expand_debug_syms (insn
.debug_sym_link
, 2);
1041 /* Doesn't really matter what we pass for RELAX_P here. */
1042 gas_cgen_finish_insn (insn
.insn
, insn
.buffer
,
1043 CGEN_FIELDS_BITSIZE (& insn
.fields
), 1, NULL
);
1047 int on_32bit_boundary_p
;
1048 /* start-sanitize-m32rx */
1050 /* end-sanitize-m32rx */
1052 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
1055 insn
.orig_insn
= insn
.insn
;
1056 /* start-sanitize-m32rx */
1057 /* If the previous insn was relaxable, then it may be expanded
1058 to fill the current 16 bit slot. Emit a NOP here to occupy
1059 this slot, so that we can start at optimizing at a 32 bit
1061 if (prev_insn
.insn
&& seen_relaxable_p
&& optimize
)
1066 /* Get the indices of the operands of the instruction.
1067 FIXME: See assemble_parallel for notes on orig_insn. */
1068 insn
.insn
= m32r_cgen_lookup_get_insn_operands
1069 (gas_cgen_opcode_desc
, NULL
, INSN_VALUE (insn
.buffer
),
1072 if (insn
.insn
== NULL
)
1073 as_fatal (_("internal error: lookup/get operands failed"));
1075 /* end-sanitize-m32rx */
1077 /* Compute whether we're on a 32 bit boundary or not.
1078 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1079 on_32bit_boundary_p
= prev_insn
.insn
== NULL
;
1081 /* start-sanitize-m32rx */
1082 /* Look to see if this instruction can be combined with the
1083 previous instruction to make one, parallel, 32 bit instruction.
1084 If the previous instruction (potentially) changed the flow of
1085 program control, then it cannot be combined with the current
1086 instruction. If the current instruction is relaxable, then it
1087 might be replaced with a longer version, so we cannot combine it.
1088 Also if the output of the previous instruction is used as an
1089 input to the current instruction then it cannot be combined.
1090 Otherwise call can_make_parallel() with both orderings of the
1091 instructions to see if they can be combined. */
1092 if ( ! on_32bit_boundary_p
1095 && CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) == 0
1096 && ! writes_to_pc (& prev_insn
)
1097 && ! first_writes_to_seconds_operands (& prev_insn
, &insn
, false)
1100 if (can_make_parallel (& prev_insn
, & insn
) == NULL
)
1101 make_parallel (insn
.buffer
);
1102 else if (can_make_parallel (& insn
, & prev_insn
) == NULL
)
1105 /* end-sanitize-m32rx */
1107 expand_debug_syms (insn
.debug_sym_link
, 1);
1113 /* Ensure each pair of 16 bit insns is in the same frag. */
1116 gas_cgen_finish_insn (insn
.orig_insn
, insn
.buffer
,
1117 CGEN_FIELDS_BITSIZE (& insn
.fields
),
1118 1 /*relax_p*/, &fi
);
1119 insn
.addr
= fi
.addr
;
1120 insn
.frag
= fi
.frag
;
1121 insn
.num_fixups
= fi
.num_fixups
;
1122 for (i
= 0; i
< fi
.num_fixups
; ++i
)
1123 insn
.fixups
[i
] = fi
.fixups
[i
];
1126 /* start-sanitize-m32rx */
1131 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1133 /* Swap the two insns */
1134 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
1135 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
1137 target_make_parallel (insn
.addr
);
1139 /* Swap any relaxable frags recorded for the two insns. */
1140 /* FIXME: Clarify. relaxation precludes parallel insns */
1141 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
1142 prev_insn
.frag
->fr_opcode
= insn
.addr
;
1143 else if (insn
.frag
->fr_opcode
== insn
.addr
)
1144 insn
.frag
->fr_opcode
= prev_insn
.addr
;
1146 /* Update the addresses in any fixups.
1147 Note that we don't have to handle the case where each insn is in
1148 a different frag as we ensure they're in the same frag above. */
1149 for (i
= 0; i
< prev_insn
.num_fixups
; ++i
)
1150 prev_insn
.fixups
[i
]->fx_where
+= 2;
1151 for (i
= 0; i
< insn
.num_fixups
; ++i
)
1152 insn
.fixups
[i
]->fx_where
-= 2;
1154 /* end-sanitize-m32rx */
1156 /* Keep track of whether we've seen a pair of 16 bit insns.
1157 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1158 if (on_32bit_boundary_p
)
1161 prev_insn
.insn
= NULL
;
1163 /* If the insn needs the following one to be on a 32 bit boundary
1164 (e.g. subroutine calls), fill this insn's slot. */
1165 if (on_32bit_boundary_p
1166 && CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_FILL_SLOT
) != 0)
1169 /* If this is a relaxable insn (can be replaced with a larger version)
1170 mark the fact so that we can emit an alignment directive for a
1171 following 32 bit insn if we see one. */
1172 if (CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) != 0)
1173 seen_relaxable_p
= 1;
1176 /* Set these so m32r_fill_insn can use them. */
1178 prev_subseg
= now_subseg
;
1181 /* The syntax in the manual says constants begin with '#'.
1182 We just ignore it. */
1185 md_operand (expressionP
)
1186 expressionS
* expressionP
;
1188 if (* input_line_pointer
== '#')
1190 input_line_pointer
++;
1191 expression (expressionP
);
1196 md_section_align (segment
, size
)
1200 int align
= bfd_get_section_alignment (stdoutput
, segment
);
1201 return ((size
+ (1 << align
) - 1) & (-1 << align
));
1205 md_undefined_symbol (name
)
1211 /* .scomm pseudo-op handler.
1213 This is a new pseudo-op to handle putting objects in .scommon.
1214 By doing this the linker won't need to do any work and more importantly
1215 it removes the implicit -G arg necessary to correctly link the object file.
1222 register char * name
;
1226 register symbolS
* symbolP
;
1230 name
= input_line_pointer
;
1231 c
= get_symbol_end ();
1233 /* just after name is now '\0' */
1234 p
= input_line_pointer
;
1237 if (* input_line_pointer
!= ',')
1239 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1240 ignore_rest_of_line ();
1244 input_line_pointer
++; /* skip ',' */
1245 if ((size
= get_absolute_expression ()) < 0)
1247 /* xgettext:c-format */
1248 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size
);
1249 ignore_rest_of_line ();
1253 /* The third argument to .scomm is the alignment. */
1254 if (* input_line_pointer
!= ',')
1258 ++ input_line_pointer
;
1259 align
= get_absolute_expression ();
1262 as_warn (_("ignoring bad alignment"));
1266 /* Convert to a power of 2 alignment. */
1269 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++ align2
)
1273 as_bad (_("Common alignment not a power of 2"));
1274 ignore_rest_of_line ();
1282 symbolP
= symbol_find_or_make (name
);
1285 if (S_IS_DEFINED (symbolP
))
1287 /* xgettext:c-format */
1288 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1289 S_GET_NAME (symbolP
));
1290 ignore_rest_of_line ();
1294 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
1296 /* xgettext:c-format */
1297 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1298 S_GET_NAME (symbolP
),
1299 (long) S_GET_VALUE (symbolP
),
1302 ignore_rest_of_line ();
1308 segT old_sec
= now_seg
;
1309 int old_subsec
= now_subseg
;
1312 record_alignment (sbss_section
, align2
);
1313 subseg_set (sbss_section
, 0);
1316 frag_align (align2
, 0, 0);
1318 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1319 symbolP
->sy_frag
->fr_symbol
= 0;
1321 symbolP
->sy_frag
= frag_now
;
1323 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1326 S_SET_SIZE (symbolP
, size
);
1327 S_SET_SEGMENT (symbolP
, sbss_section
);
1328 S_CLEAR_EXTERNAL (symbolP
);
1329 subseg_set (old_sec
, old_subsec
);
1333 S_SET_VALUE (symbolP
, (valueT
) size
);
1334 S_SET_ALIGN (symbolP
, align2
);
1335 S_SET_EXTERNAL (symbolP
);
1336 S_SET_SEGMENT (symbolP
, & scom_section
);
1339 demand_empty_rest_of_line ();
1342 /* Interface to relax_segment. */
1344 /* FIXME: Build table by hand, get it working, then machine generate. */
1346 const relax_typeS md_relax_table
[] =
1349 1) most positive reach of this state,
1350 2) most negative reach of this state,
1351 3) how many bytes this mode will add to the size of the current frag
1352 4) which index into the table to try if we can't fit into this one. */
1354 /* The first entry must be unused because an `rlx_more' value of zero ends
1358 /* The displacement used by GAS is from the end of the 2 byte insn,
1359 so we subtract 2 from the following. */
1360 /* 16 bit insn, 8 bit disp -> 10 bit range.
1361 This doesn't handle a branch in the right slot at the border:
1362 the "& -4" isn't taken into account. It's not important enough to
1363 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1365 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1366 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1367 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1368 /* Same thing, but with leading nop for alignment. */
1369 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1373 m32r_relax_frag (fragP
, stretch
)
1377 /* Address of branch insn. */
1378 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1381 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1382 if (fragP
->fr_subtype
== 2)
1384 if ((address
& 3) != 0)
1386 fragP
->fr_subtype
= 3;
1390 else if (fragP
->fr_subtype
== 3)
1392 if ((address
& 3) == 0)
1394 fragP
->fr_subtype
= 2;
1400 growth
= relax_frag (fragP
, stretch
);
1402 /* Long jump on odd halfword boundary? */
1403 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1405 fragP
->fr_subtype
= 3;
1413 /* Return an initial guess of the length by which a fragment must grow to
1414 hold a branch to reach its destination.
1415 Also updates fr_type/fr_subtype as necessary.
1417 Called just before doing relaxation.
1418 Any symbol that is now undefined will not become defined.
1419 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1420 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1421 Although it may not be explicit in the frag, pretend fr_var starts with a
1425 md_estimate_size_before_relax (fragP
, segment
)
1429 int old_fr_fix
= fragP
->fr_fix
;
1431 /* The only thing we have to handle here are symbols outside of the
1432 current segment. They may be undefined or in a different segment in
1433 which case linker scripts may place them anywhere.
1434 However, we can't finish the fragment here and emit the reloc as insn
1435 alignment requirements may move the insn about. */
1437 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1439 /* The symbol is undefined in this segment.
1440 Change the relaxation subtype to the max allowable and leave
1441 all further handling to md_convert_frag. */
1442 fragP
->fr_subtype
= 2;
1444 #if 0 /* Can't use this, but leave in for illustration. */
1445 /* Change 16 bit insn to 32 bit insn. */
1446 fragP
->fr_opcode
[0] |= 0x80;
1448 /* Increase known (fixed) size of fragment. */
1451 /* Create a relocation for it. */
1452 fix_new (fragP
, old_fr_fix
, 4,
1454 fragP
->fr_offset
, 1 /* pcrel */,
1455 /* FIXME: Can't use a real BFD reloc here.
1456 gas_cgen_md_apply_fix3 can't handle it. */
1457 BFD_RELOC_M32R_26_PCREL
);
1459 /* Mark this fragment as finished. */
1463 const CGEN_INSN
* insn
;
1466 /* Update the recorded insn.
1467 Fortunately we don't have to look very far.
1468 FIXME: Change this to record in the instruction the next higher
1469 relaxable insn to use. */
1470 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1472 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1473 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1475 && CGEN_INSN_ATTR (insn
, CGEN_INSN_RELAX
))
1481 fragP
->fr_cgen
.insn
= insn
;
1487 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
1490 /* *fragP has been relaxed to its final size, and now needs to have
1491 the bytes inside it modified to conform to the new size.
1493 Called after relaxation is finished.
1494 fragP->fr_type == rs_machine_dependent.
1495 fragP->fr_subtype is the subtype of what the address relaxed to. */
1498 md_convert_frag (abfd
, sec
, fragP
)
1504 char * displacement
;
1510 opcode
= fragP
->fr_opcode
;
1512 /* Address opcode resides at in file space. */
1513 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1515 switch (fragP
->fr_subtype
)
1519 displacement
= & opcode
[1];
1524 displacement
= & opcode
[1];
1527 opcode
[2] = opcode
[0] | 0x80;
1528 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1529 opcode_address
+= 2;
1531 displacement
= & opcode
[3];
1537 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1539 /* symbol must be resolved by linker */
1540 if (fragP
->fr_offset
& 3)
1541 as_warn (_("Addend to unresolved symbol not on word boundary."));
1542 addend
= fragP
->fr_offset
>> 2;
1546 /* Address we want to reach in file space. */
1547 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1548 target_address
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
1549 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1552 /* Create a relocation for symbols that must be resolved by the linker.
1553 Otherwise output the completed insn. */
1555 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1557 assert (fragP
->fr_subtype
!= 1);
1558 assert (fragP
->fr_cgen
.insn
!= 0);
1559 gas_cgen_record_fixup (fragP
,
1560 /* Offset of branch insn in frag. */
1561 fragP
->fr_fix
+ extension
- 4,
1562 fragP
->fr_cgen
.insn
,
1564 /* FIXME: quick hack */
1566 CGEN_OPERAND_ENTRY (fragP
->fr_cgen
.opindex
),
1568 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24
),
1570 fragP
->fr_cgen
.opinfo
,
1571 fragP
->fr_symbol
, fragP
->fr_offset
);
1574 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1576 md_number_to_chars (displacement
, (valueT
) addend
,
1577 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1579 fragP
->fr_fix
+= extension
;
1582 /* Functions concerning relocs. */
1584 /* The location from which a PC relative jump should be calculated,
1585 given a PC relative reloc. */
1588 md_pcrel_from_section (fixP
, sec
)
1592 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1593 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1594 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1596 /* The symbol is undefined (or is defined but not in this section).
1597 Let the linker figure it out. */
1601 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1604 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1605 Returns BFD_RELOC_NONE if no reloc type can be found.
1606 *FIXP may be modified if desired. */
1608 bfd_reloc_code_real_type
1609 md_cgen_lookup_reloc (insn
, operand
, fixP
)
1610 const CGEN_INSN
* insn
;
1611 const CGEN_OPERAND
* operand
;
1614 switch (CGEN_OPERAND_TYPE (operand
))
1616 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1617 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1618 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1619 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1620 case M32R_OPERAND_HI16
:
1621 case M32R_OPERAND_SLO16
:
1622 case M32R_OPERAND_ULO16
:
1623 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1624 if (fixP
->tc_fix_data
.opinfo
!= 0)
1625 return fixP
->tc_fix_data
.opinfo
;
1627 default : /* avoid -Wall warning */
1630 return BFD_RELOC_NONE
;
1633 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1636 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1641 struct m32r_hi_fixup
* hi_fixup
;
1643 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1644 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1646 hi_fixup
= ((struct m32r_hi_fixup
*)
1647 xmalloc (sizeof (struct m32r_hi_fixup
)));
1648 hi_fixup
->fixp
= fixP
;
1649 hi_fixup
->seg
= now_seg
;
1650 hi_fixup
->next
= m32r_hi_fixup_list
;
1652 m32r_hi_fixup_list
= hi_fixup
;
1655 /* Called while parsing an instruction to create a fixup.
1656 We need to check for HI16 relocs and queue them up for later sorting. */
1659 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1662 const CGEN_INSN
* insn
;
1664 const CGEN_OPERAND
* operand
;
1668 fixS
* fixP
= gas_cgen_record_fixup_exp (frag
, where
, insn
, length
,
1669 operand
, opinfo
, exp
);
1671 switch (CGEN_OPERAND_TYPE (operand
))
1673 case M32R_OPERAND_HI16
:
1674 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1675 if (fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1676 || fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1677 m32r_record_hi16 (fixP
->tc_fix_data
.opinfo
, fixP
, now_seg
);
1679 default : /* avoid -Wall warning */
1686 /* Return BFD reloc type from opinfo field in a fixS.
1687 It's tricky using fx_r_type in m32r_frob_file because the values
1688 are BFD_RELOC_UNUSED + operand number. */
1689 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1691 /* Sort any unmatched HI16 relocs so that they immediately precede
1692 the corresponding LO16 reloc. This is called before md_apply_fix and
1698 struct m32r_hi_fixup
* l
;
1700 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1702 segment_info_type
* seginfo
;
1705 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1706 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1708 /* Check quickly whether the next fixup happens to be a matching low. */
1709 if (l
->fixp
->fx_next
!= NULL
1710 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1711 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1712 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1715 /* Look through the fixups for this segment for a matching `low'.
1716 When we find one, move the high/shigh just in front of it. We do
1717 this in two passes. In the first pass, we try to find a
1718 unique `low'. In the second pass, we permit multiple high's
1719 relocs for a single `low'. */
1720 seginfo
= seg_info (l
->seg
);
1721 for (pass
= 0; pass
< 2; pass
++)
1727 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1729 /* Check whether this is a `low' fixup which matches l->fixp. */
1730 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
1731 && f
->fx_addsy
== l
->fixp
->fx_addsy
1732 && f
->fx_offset
== l
->fixp
->fx_offset
1735 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
1736 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
1737 || prev
->fx_addsy
!= f
->fx_addsy
1738 || prev
->fx_offset
!= f
->fx_offset
))
1742 /* Move l->fixp before f. */
1743 for (pf
= &seginfo
->fix_root
;
1745 pf
= & (* pf
)->fx_next
)
1746 assert (* pf
!= NULL
);
1748 * pf
= l
->fixp
->fx_next
;
1750 l
->fixp
->fx_next
= f
;
1752 seginfo
->fix_root
= l
->fixp
;
1754 prev
->fx_next
= l
->fixp
;
1766 && warn_unmatched_high
)
1767 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1768 _("Unmatched high/shigh reloc"));
1773 /* See whether we need to force a relocation into the output file.
1774 This is used to force out switch and PC relative relocations when
1778 m32r_force_relocation (fix
)
1781 if (fix
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1782 || fix
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1788 return (fix
->fx_pcrel
1792 /* Write a value out to the object file, using the appropriate endianness. */
1795 md_number_to_chars (buf
, val
, n
)
1800 if (target_big_endian
)
1801 number_to_chars_bigendian (buf
, val
, n
);
1803 number_to_chars_littleendian (buf
, val
, n
);
1806 /* Turn a string in input_line_pointer into a floating point constant of type
1807 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1808 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1811 /* Equal to MAX_PRECISION in atof-ieee.c */
1812 #define MAX_LITTLENUMS 6
1815 md_atof (type
, litP
, sizeP
)
1822 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1824 char * atof_ieee ();
1842 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1846 return _("Bad call to md_atof()");
1849 t
= atof_ieee (input_line_pointer
, type
, words
);
1851 input_line_pointer
= t
;
1852 * sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1854 if (target_big_endian
)
1856 for (i
= 0; i
< prec
; i
++)
1858 md_number_to_chars (litP
, (valueT
) words
[i
],
1859 sizeof (LITTLENUM_TYPE
));
1860 litP
+= sizeof (LITTLENUM_TYPE
);
1865 for (i
= prec
- 1; i
>= 0; i
--)
1867 md_number_to_chars (litP
, (valueT
) words
[i
],
1868 sizeof (LITTLENUM_TYPE
));
1869 litP
+= sizeof (LITTLENUM_TYPE
);
1877 m32r_elf_section_change_hook ()
1879 /* If we have reached the end of a section and we have just emitted a
1880 16 bit insn, then emit a nop to make sure that the section ends on
1881 a 32 bit boundary. */
1883 if (prev_insn
.insn
|| seen_relaxable_p
)
1884 (void) m32r_fill_insn (0);
1888 m32r_fix_adjustable (fixP
)
1892 if (fixP
->fx_addsy
== NULL
)
1895 /* Prevent all adjustments to global symbols. */
1896 if (S_IS_EXTERN (fixP
->fx_addsy
))
1898 if (S_IS_WEAK (fixP
->fx_addsy
))
1901 /* We need the symbol name for the VTABLE entries */
1902 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1903 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)