1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "opcodes/m32r-desc.h"
27 #include "opcodes/m32r-opc.h"
30 /* Linked list of symbols that are debugging symbols to be defined as the
31 beginning of the current instruction. */
32 typedef struct sym_link
34 struct sym_link
*next
;
38 static sym_linkS
*debug_sym_link
= (sym_linkS
*)0;
40 /* Structure to hold all of the different components describing
41 an individual instruction. */
44 const CGEN_INSN
* insn
;
45 const CGEN_INSN
* orig_insn
;
48 CGEN_INSN_INT buffer
[1];
49 #define INSN_VALUE(buf) (*(buf))
51 unsigned char buffer
[CGEN_MAX_INSN_SIZE
];
52 #define INSN_VALUE(buf) (buf)
57 fixS
* fixups
[GAS_CGEN_MAX_FIXUPS
];
58 int indices
[MAX_OPERAND_INSTANCES
];
59 sym_linkS
*debug_sym_link
;
63 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
64 boundary (i.e. was the first of two 16 bit insns). */
65 static m32r_insn prev_insn
;
67 /* Non-zero if we've seen a relaxable insn since the last 32 bit
69 static int seen_relaxable_p
= 0;
71 /* Non-zero if -relax specified, in which case sufficient relocs are output
72 for the linker to do relaxing.
73 We do simple forms of relaxing internally, but they are always done.
74 This flag does not apply to them. */
75 static int m32r_relax
;
77 #if 0 /* not supported yet */
78 /* If non-NULL, pointer to cpu description file to read.
79 This allows runtime additions to the assembler. */
80 static const char * m32r_cpu_desc
;
83 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
84 Each high/shigh reloc must be paired with it's low cousin in order to
85 properly calculate the addend in a relocatable link (since there is a
86 potential carry from the low to the high/shigh).
87 This option is off by default though for user-written assembler code it
88 might make sense to make the default be on (i.e. have gcc pass a flag
89 to turn it off). This warning must not be on for GCC created code as
90 optimization may delete the low but not the high/shigh (at least we
91 shouldn't assume or require it to). */
92 static int warn_unmatched_high
= 0;
94 /* Non-zero if -m32rx has been specified, in which case support for the
95 extended M32RX instruction set should be enabled. */
96 static int enable_m32rx
= 0;
98 /* Non-zero if -m32rx -hidden has been specified, in which case support for
99 the special M32RX instruction set should be enabled. */
100 static int enable_special
= 0;
102 /* Non-zero if the programmer should be warned when an explicit parallel
103 instruction might have constraint violations. */
104 static int warn_explicit_parallel_conflicts
= 1;
106 /* Non-zero if insns can be made parallel. */
109 /* stuff for .scomm symbols. */
110 static segT sbss_section
;
111 static asection scom_section
;
112 static asymbol scom_symbol
;
114 const char comment_chars
[] = ";";
115 const char line_comment_chars
[] = "#";
116 const char line_separator_chars
[] = "";
117 const char EXP_CHARS
[] = "eE";
118 const char FLT_CHARS
[] = "dD";
120 /* Relocations against symbols are done in two
121 parts, with a HI relocation and a LO relocation. Each relocation
122 has only 16 bits of space to store an addend. This means that in
123 order for the linker to handle carries correctly, it must be able
124 to locate both the HI and the LO relocation. This means that the
125 relocations must appear in order in the relocation table.
127 In order to implement this, we keep track of each unmatched HI
128 relocation. We then sort them so that they immediately precede the
129 corresponding LO relocation. */
133 struct m32r_hi_fixup
* next
; /* Next HI fixup. */
134 fixS
* fixp
; /* This fixup. */
135 segT seg
; /* The section this fixup is in. */
139 /* The list of unmatched HI relocs. */
141 static struct m32r_hi_fixup
* m32r_hi_fixup_list
;
150 if (stdoutput
!= NULL
)
151 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
152 enable_m32rx
? bfd_mach_m32rx
: bfd_mach_m32r
);
155 #define M32R_SHORTOPTS "O"
156 const char * md_shortopts
= M32R_SHORTOPTS
;
158 struct option md_longopts
[] =
160 #define OPTION_M32R (OPTION_MD_BASE)
161 #define OPTION_M32RX (OPTION_M32R + 1)
162 #define OPTION_WARN_PARALLEL (OPTION_M32RX + 1)
163 #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1)
164 #define OPTION_SPECIAL (OPTION_NO_WARN_PARALLEL + 1)
165 #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL + 1)
166 #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1)
167 {"m32r", no_argument
, NULL
, OPTION_M32R
},
168 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
169 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
170 {"Wp", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
171 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
172 {"Wnp", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
173 {"hidden", no_argument
, NULL
, OPTION_SPECIAL
},
174 /* Sigh. I guess all warnings must now have both variants. */
175 {"warn-unmatched-high", no_argument
, NULL
, OPTION_WARN_UNMATCHED
},
176 {"Wuh", no_argument
, NULL
, OPTION_WARN_UNMATCHED
},
177 {"no-warn-unmatched-high", no_argument
, NULL
, OPTION_NO_WARN_UNMATCHED
},
178 {"Wnuh", no_argument
, NULL
, OPTION_NO_WARN_UNMATCHED
},
180 #if 0 /* not supported yet */
181 #define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1)
182 #define OPTION_CPU_DESC (OPTION_RELAX + 1)
183 {"relax", no_argument
, NULL
, OPTION_RELAX
},
184 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
186 {NULL
, no_argument
, NULL
, 0}
188 size_t md_longopts_size
= sizeof (md_longopts
);
191 md_parse_option (c
, arg
)
209 case OPTION_WARN_PARALLEL
:
210 warn_explicit_parallel_conflicts
= 1;
213 case OPTION_NO_WARN_PARALLEL
:
214 warn_explicit_parallel_conflicts
= 0;
222 /* Pretend that we do not recognise this option. */
223 as_bad (_("Unrecognised option: -hidden"));
228 case OPTION_WARN_UNMATCHED
:
229 warn_unmatched_high
= 1;
232 case OPTION_NO_WARN_UNMATCHED
:
233 warn_unmatched_high
= 0;
236 #if 0 /* not supported yet */
240 case OPTION_CPU_DESC
:
253 md_show_usage (stream
)
256 fprintf (stream
, _(" M32R specific command line options:\n"));
258 fprintf (stream
, _("\
259 -m32rx support the extended m32rx instruction set\n"));
260 fprintf (stream
, _("\
261 -O try to combine instructions in parallel\n"));
263 fprintf (stream
, _("\
264 -warn-explicit-parallel-conflicts warn when parallel instructions\n"));
265 fprintf (stream
, _("\
266 violate contraints\n"));
267 fprintf (stream
, _("\
268 -no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
269 fprintf (stream
, _("\
270 instructions violate contraints\n"));
271 fprintf (stream
, _("\
272 -Wp synonym for -warn-explicit-parallel-conflicts\n"));
273 fprintf (stream
, _("\
274 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
276 fprintf (stream
, _("\
277 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
278 fprintf (stream
, _("\
279 -no-warn-unmatched-high do not warn about missing low relocs\n"));
280 fprintf (stream
, _("\
281 -Wuh synonym for -warn-unmatched-high\n"));
282 fprintf (stream
, _("\
283 -Wnuh synonym for -no-warn-unmatched-high\n"));
286 fprintf (stream
, _("\
287 -relax create linker relaxable code\n"));
288 fprintf (stream
, _("\
289 -cpu-desc provide runtime cpu description file\n"));
293 static void fill_insn
PARAMS ((int));
294 static void m32r_scomm
PARAMS ((int));
295 static void debug_sym
PARAMS ((int));
296 static void expand_debug_syms
PARAMS ((sym_linkS
*, int));
298 /* Set by md_assemble for use by m32r_fill_insn. */
299 static subsegT prev_subseg
;
300 static segT prev_seg
;
302 /* The target specific pseudo-ops which we support. */
303 const pseudo_typeS md_pseudo_table
[] =
306 { "fillinsn", fill_insn
, 0 },
307 { "scomm", m32r_scomm
, 0 },
308 { "debugsym", debug_sym
, 0 },
309 /* Not documented as so far there is no need for them.... */
310 { "m32r", allow_m32rx
, 0 },
311 { "m32rx", allow_m32rx
, 1 },
315 /* FIXME: Should be machine generated. */
316 #define NOP_INSN 0x7000
317 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
319 /* When we align the .text section, insert the correct NOP pattern.
320 N is the power of 2 alignment. LEN is the length of pattern FILL.
321 MAX is the maximum number of characters to skip when doing the alignment,
322 or 0 if there is no maximum. */
325 m32r_do_align (n
, fill
, len
, max
)
331 /* Only do this if the fill pattern wasn't specified. */
333 && subseg_text_p (now_seg
)
334 /* Only do this special handling if aligning to at least a
337 /* Only do this special handling if we're allowed to emit at
339 && (max
== 0 || max
> 1))
341 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
344 /* First align to a 2 byte boundary, in case there is an odd .byte. */
345 /* FIXME: How much memory will cause gas to use when assembling a big
346 program? Perhaps we can avoid the frag_align call? */
347 frag_align (1, 0, 0);
349 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
351 frag_align_pattern (2, nop_pattern
, sizeof nop_pattern
, 0);
352 /* If doing larger alignments use a repeating sequence of appropriate
356 static const unsigned char multi_nop_pattern
[] =
357 { 0x70, 0x00, 0xf0, 0x00 };
358 frag_align_pattern (n
, multi_nop_pattern
, sizeof multi_nop_pattern
,
362 prev_insn
.insn
= NULL
;
369 /* If the last instruction was the first of 2 16 bit insns,
370 output a nop to move the PC to a 32 bit boundary.
372 This is done via an alignment specification since branch relaxing
373 may make it unnecessary.
375 Internally, we need to output one of these each time a 32 bit insn is
376 seen after an insn that is relaxable. */
382 (void) m32r_do_align (2, NULL
, 0, 0);
383 prev_insn
.insn
= NULL
;
384 seen_relaxable_p
= 0;
387 /* Record the symbol so that when we output the insn, we can create
388 a symbol that is at the start of the instruction. This is used
389 to emit the label for the start of a breakpoint without causing
390 the assembler to emit a NOP if the previous instruction was a
391 16 bit instruction. */
399 register char *end_name
;
400 register symbolS
*symbolP
;
401 register sym_linkS
*link
;
403 name
= input_line_pointer
;
404 delim
= get_symbol_end ();
405 end_name
= input_line_pointer
;
407 if ((symbolP
= symbol_find (name
)) == NULL
408 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
410 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
413 symbol_table_insert (symbolP
);
414 if (S_IS_DEFINED (symbolP
) && S_GET_SEGMENT (symbolP
) != reg_section
)
415 /* xgettext:c-format */
416 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
420 link
= (sym_linkS
*) xmalloc (sizeof (sym_linkS
));
421 link
->symbol
= symbolP
;
422 link
->next
= debug_sym_link
;
423 debug_sym_link
= link
;
424 symbol_get_obj (symbolP
)->local
= 1;
428 demand_empty_rest_of_line ();
431 /* Second pass to expanding the debug symbols, go through linked
432 list of symbols and reassign the address. */
435 expand_debug_syms (syms
, align
)
439 char *save_input_line
= input_line_pointer
;
440 sym_linkS
*next_syms
;
445 (void) m32r_do_align (align
, NULL
, 0, 0);
446 for (; syms
!= (sym_linkS
*)0; syms
= next_syms
)
448 symbolS
*symbolP
= syms
->symbol
;
449 next_syms
= syms
->next
;
450 input_line_pointer
= ".\n";
451 pseudo_set (symbolP
);
455 input_line_pointer
= save_input_line
;
458 /* Cover function to fill_insn called after a label and at end of assembly.
459 The result is always 1: we're called in a conditional to see if the
460 current line is a label. */
463 m32r_fill_insn (done
)
466 if (prev_seg
!= NULL
)
469 subsegT subseg
= now_subseg
;
471 subseg_set (prev_seg
, prev_subseg
);
475 subseg_set (seg
, subseg
);
478 if (done
&& debug_sym_link
)
480 expand_debug_syms (debug_sym_link
, 1);
481 debug_sym_link
= (sym_linkS
*)0;
494 /* Initialize the `cgen' interface. */
496 /* Set the machine number and endian. */
497 gas_cgen_cpu_desc
= m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS
, 0,
498 CGEN_CPU_OPEN_ENDIAN
,
501 m32r_cgen_init_asm (gas_cgen_cpu_desc
);
503 /* The operand instance table is used during optimization to determine
504 which insns can be executed in parallel. It is also used to give
505 warnings regarding operand interference in parallel insns. */
506 m32r_cgen_init_opinst_table (gas_cgen_cpu_desc
);
508 /* This is a callback from cgen to gas to parse operands. */
509 cgen_set_parse_operand_fn (gas_cgen_cpu_desc
, gas_cgen_parse_operand
);
511 #if 0 /* not supported yet */
512 /* If a runtime cpu description file was provided, parse it. */
513 if (m32r_cpu_desc
!= NULL
)
517 errmsg
= cgen_read_cpu_file (gas_cgen_cpu_desc
, m32r_cpu_desc
);
519 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
523 /* Save the current subseg so we can restore it [it's the default one and
524 we don't want the initial section to be .sbss]. */
528 /* The sbss section is for local .scomm symbols. */
529 sbss_section
= subseg_new (".sbss", 0);
531 /* This is copied from perform_an_assembly_pass. */
532 applicable
= bfd_applicable_section_flags (stdoutput
);
533 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
535 #if 0 /* What does this do? [see perform_an_assembly_pass] */
536 seg_info (bss_section
)->bss
= 1;
539 subseg_set (seg
, subseg
);
541 /* We must construct a fake section similar to bfd_com_section
542 but with the name .scommon. */
543 scom_section
= bfd_com_section
;
544 scom_section
.name
= ".scommon";
545 scom_section
.output_section
= & scom_section
;
546 scom_section
.symbol
= & scom_symbol
;
547 scom_section
.symbol_ptr_ptr
= & scom_section
.symbol
;
548 scom_symbol
= * bfd_com_section
.symbol
;
549 scom_symbol
.name
= ".scommon";
550 scom_symbol
.section
= & scom_section
;
552 allow_m32rx (enable_m32rx
);
555 #define OPERAND_IS_COND_BIT(operand, indices, index) \
556 ((operand)->hw_type == HW_H_COND \
557 || ((operand)->hw_type == HW_H_PSW) \
558 || ((operand)->hw_type == HW_H_CR \
559 && (indices [index] == 0 || indices [index] == 1)))
561 /* Returns true if an output of instruction 'a' is referenced by an operand
562 of instruction 'b'. If 'check_outputs' is true then b's outputs are
563 checked, otherwise its inputs are examined. */
566 first_writes_to_seconds_operands (a
, b
, check_outputs
)
569 const int check_outputs
;
571 const CGEN_OPINST
* a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
572 const CGEN_OPINST
* b_ops
= CGEN_INSN_OPERANDS (b
->insn
);
575 /* If at least one of the instructions takes no operands, then there is
576 nothing to check. There really are instructions without operands,
578 if (a_operands
== NULL
|| b_ops
== NULL
)
581 /* Scan the operand list of 'a' looking for an output operand. */
583 a_operands
->type
!= CGEN_OPINST_END
;
584 a_index
++, a_operands
++)
586 if (a_operands
->type
== CGEN_OPINST_OUTPUT
)
589 const CGEN_OPINST
* b_operands
= b_ops
;
592 The Condition bit 'C' is a shadow of the CBR register (control
593 register 1) and also a shadow of bit 31 of the program status
594 word (control register 0). For now this is handled here, rather
597 if (OPERAND_IS_COND_BIT (a_operands
, a
->indices
, a_index
))
599 /* Scan operand list of 'b' looking for another reference to the
600 condition bit, which goes in the right direction. */
602 b_operands
->type
!= CGEN_OPINST_END
;
603 b_index
++, b_operands
++)
605 if ((b_operands
->type
608 : CGEN_OPINST_INPUT
))
609 && OPERAND_IS_COND_BIT (b_operands
, b
->indices
, b_index
))
615 /* Scan operand list of 'b' looking for an operand that
616 references the same hardware element, and which goes in the
619 b_operands
->type
!= CGEN_OPINST_END
;
620 b_index
++, b_operands
++)
622 if ((b_operands
->type
625 : CGEN_OPINST_INPUT
))
626 && (b_operands
->hw_type
== a_operands
->hw_type
)
627 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
637 /* Returns true if the insn can (potentially) alter the program counter. */
643 #if 0 /* Once PC operands are working.... */
644 const CGEN_OPINST
* a_operands
== CGEN_INSN_OPERANDS (gas_cgen_cpu_desc
,
647 if (a_operands
== NULL
)
650 while (a_operands
->type
!= CGEN_OPINST_END
)
652 if (a_operands
->operand
!= NULL
653 && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc
, a_operands
->operand
) == M32R_OPERAND_PC
)
659 if (CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_UNCOND_CTI
)
660 || CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_COND_CTI
))
666 /* Returns NULL if the two 16 bit insns can be executed in parallel,
667 otherwise it returns a pointer to an error message explaining why not. */
670 can_make_parallel (a
, b
)
677 /* Make sure the instructions are the right length. */
678 if ( CGEN_FIELDS_BITSIZE (& a
->fields
) != 16
679 || CGEN_FIELDS_BITSIZE (& b
->fields
) != 16)
682 if (first_writes_to_seconds_operands (a
, b
, true))
683 return _("Instructions write to the same destination register.");
685 a_pipe
= CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_PIPE
);
686 b_pipe
= CGEN_INSN_ATTR_VALUE (b
->insn
, CGEN_INSN_PIPE
);
688 /* Make sure that the instructions use the correct execution pipelines. */
689 if ( a_pipe
== PIPE_NONE
690 || b_pipe
== PIPE_NONE
)
691 return _("Instructions do not use parallel execution pipelines.");
693 /* Leave this test for last, since it is the only test that can
694 go away if the instructions are swapped, and we want to make
695 sure that any other errors are detected before this happens. */
696 if ( a_pipe
== PIPE_S
698 return _("Instructions share the same execution pipeline");
703 /* Force the top bit of the second 16-bit insn to be set. */
706 make_parallel (buffer
)
707 CGEN_INSN_BYTES_PTR buffer
;
712 buffer
[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
717 /* Same as make_parallel except buffer contains the bytes in target order. */
720 target_make_parallel (buffer
)
723 buffer
[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
727 /* Assemble two instructions with an explicit parallel operation (||) or
728 sequential operation (->). */
731 assemble_two_insns (str
, str2
, parallel_p
)
740 char save_str2
= *str2
;
742 * str2
= 0; /* Seperate the two instructions. */
744 /* Make sure the two insns begin on a 32 bit boundary.
745 This is also done for the serial case (foo -> bar), relaxing doesn't
746 affect insns written like this.
747 Note that we must always do this as we can't assume anything about
748 whether we're currently on a 32 bit boundary or not. Relaxing may
752 first
.debug_sym_link
= debug_sym_link
;
753 debug_sym_link
= (sym_linkS
*)0;
755 /* Parse the first instruction. */
756 if (! (first
.insn
= m32r_cgen_assemble_insn
757 (gas_cgen_cpu_desc
, str
, & first
.fields
, first
.buffer
, & errmsg
)))
764 if (CGEN_FIELDS_BITSIZE (&first
.fields
) != 16)
766 /* xgettext:c-format */
767 as_bad (_("not a 16 bit instruction '%s'"), str
);
770 else if (! enable_special
771 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL
))
773 /* xgettext:c-format */
774 as_bad (_("unknown instruction '%s'"), str
);
777 else if (! enable_m32rx
778 /* FIXME: Need standard macro to perform this test. */
779 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
781 /* xgettext:c-format */
782 as_bad (_("instruction '%s' is for the M32RX only"), str
);
786 /* Check to see if this is an allowable parallel insn. */
787 if (parallel_p
&& CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
789 /* xgettext:c-format */
790 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
794 *str2
= save_str2
; /* Restore the original assembly text, just in case it is needed. */
795 str3
= str
; /* Save the original string pointer. */
796 str
= str2
+ 2; /* Advanced past the parsed string. */
797 str2
= str3
; /* Remember the entire string in case it is needed for error messages. */
799 /* Convert the opcode to lower case. */
803 while (isspace (*s2
++))
808 while (isalnum (*s2
))
810 if (isupper ((unsigned char) *s2
))
816 /* Preserve any fixups that have been generated and reset the list to empty. */
817 gas_cgen_save_fixups ();
819 /* Get the indices of the operands of the instruction. */
820 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
821 doesn't seem right. Perhaps allow passing fields like we do insn. */
822 /* FIXME: ALIAS insns do not have operands, so we use this function
823 to find the equivalent insn and overwrite the value stored in our
824 structure. We still need the original insn, however, since this
825 may have certain attributes that are not present in the unaliased
826 version (eg relaxability). When aliases behave differently this
827 may have to change. */
828 first
.orig_insn
= first
.insn
;
830 CGEN_FIELDS tmp_fields
;
831 first
.insn
= cgen_lookup_get_insn_operands
832 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (first
.buffer
), NULL
, 16,
833 first
.indices
, &tmp_fields
);
836 if (first
.insn
== NULL
)
837 as_fatal (_("internal error: lookup/get operands failed"));
839 second
.debug_sym_link
= NULL
;
841 /* Parse the second instruction. */
842 if (! (second
.insn
= m32r_cgen_assemble_insn
843 (gas_cgen_cpu_desc
, str
, & second
.fields
, second
.buffer
, & errmsg
)))
850 if (CGEN_FIELDS_BITSIZE (&second
.fields
) != 16)
852 /* xgettext:c-format */
853 as_bad (_("not a 16 bit instruction '%s'"), str
);
856 else if (! enable_special
857 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL
))
859 /* xgettext:c-format */
860 as_bad (_("unknown instruction '%s'"), str
);
863 else if (! enable_m32rx
864 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
866 /* xgettext:c-format */
867 as_bad (_("instruction '%s' is for the M32RX only"), str
);
871 /* Check to see if this is an allowable parallel insn. */
872 if (parallel_p
&& CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
874 /* xgettext:c-format */
875 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
879 if (parallel_p
&& ! enable_m32rx
)
881 if (CGEN_INSN_NUM (first
.insn
) != M32R_INSN_NOP
882 && CGEN_INSN_NUM (second
.insn
) != M32R_INSN_NOP
)
884 /* xgettext:c-format */
885 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2
);
890 /* Get the indices of the operands of the instruction. */
891 second
.orig_insn
= second
.insn
;
893 CGEN_FIELDS tmp_fields
;
894 second
.insn
= cgen_lookup_get_insn_operands
895 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (second
.buffer
), NULL
, 16,
896 second
.indices
, &tmp_fields
);
899 if (second
.insn
== NULL
)
900 as_fatal (_("internal error: lookup/get operands failed"));
902 /* We assume that if the first instruction writes to a register that is
903 read by the second instruction it is because the programmer intended
904 this to happen, (after all they have explicitly requested that these
905 two instructions be executed in parallel). Although if the global
906 variable warn_explicit_parallel_conflicts is true then we do generate
907 a warning message. Similarly we assume that parallel branch and jump
908 instructions are deliberate and should not produce errors. */
910 if (parallel_p
&& warn_explicit_parallel_conflicts
)
912 if (first_writes_to_seconds_operands (& first
, & second
, false))
913 /* xgettext:c-format */
914 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2
);
916 if (first_writes_to_seconds_operands (& second
, & first
, false))
917 /* xgettext:c-format */
918 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2
);
922 || (errmsg
= (char *) can_make_parallel (& first
, & second
)) == NULL
)
924 /* Get the fixups for the first instruction. */
925 gas_cgen_swap_fixups ();
928 expand_debug_syms (first
.debug_sym_link
, 1);
929 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
930 CGEN_FIELDS_BITSIZE (& first
.fields
), 0, NULL
);
932 /* Force the top bit of the second insn to be set. */
934 make_parallel (second
.buffer
);
936 /* Get its fixups. */
937 gas_cgen_restore_fixups ();
940 expand_debug_syms (second
.debug_sym_link
, 1);
941 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
942 CGEN_FIELDS_BITSIZE (& second
.fields
), 0, NULL
);
944 /* Try swapping the instructions to see if they work that way. */
945 else if (can_make_parallel (& second
, & first
) == NULL
)
947 /* Write out the second instruction first. */
948 expand_debug_syms (second
.debug_sym_link
, 1);
949 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
950 CGEN_FIELDS_BITSIZE (& second
.fields
), 0, NULL
);
952 /* Force the top bit of the first instruction to be set. */
953 make_parallel (first
.buffer
);
955 /* Get the fixups for the first instruction. */
956 gas_cgen_restore_fixups ();
958 /* Write out the first instruction. */
959 expand_debug_syms (first
.debug_sym_link
, 1);
960 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
961 CGEN_FIELDS_BITSIZE (& first
.fields
), 0, NULL
);
965 as_bad ("'%s': %s", str2
, errmsg
);
969 /* Set these so m32r_fill_insn can use them. */
971 prev_subseg
= now_subseg
;
982 /* Initialize GAS's cgen interface for a new instruction. */
983 gas_cgen_init_parse ();
985 /* Look for a parallel instruction seperator. */
986 if ((str2
= strstr (str
, "||")) != NULL
)
988 assemble_two_insns (str
, str2
, 1);
992 /* Also look for a sequential instruction seperator. */
993 if ((str2
= strstr (str
, "->")) != NULL
)
995 assemble_two_insns (str
, str2
, 0);
999 insn
.debug_sym_link
= debug_sym_link
;
1000 debug_sym_link
= (sym_linkS
*)0;
1002 insn
.insn
= m32r_cgen_assemble_insn
1003 (gas_cgen_cpu_desc
, str
, & insn
.fields
, insn
.buffer
, & errmsg
);
1011 if (! enable_special
1012 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL
))
1014 /* xgettext:c-format */
1015 as_bad (_("unknown instruction '%s'"), str
);
1018 else if (! enable_m32rx
1019 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
1021 /* xgettext:c-format */
1022 as_bad (_("instruction '%s' is for the M32RX only"), str
);
1026 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
1028 /* 32 bit insns must live on 32 bit boundaries. */
1029 if (prev_insn
.insn
|| seen_relaxable_p
)
1031 /* ??? If calling fill_insn too many times turns us into a memory
1032 pig, can we call a fn to assemble a nop instead of
1033 !seen_relaxable_p? */
1037 expand_debug_syms (insn
.debug_sym_link
, 2);
1039 /* Doesn't really matter what we pass for RELAX_P here. */
1040 gas_cgen_finish_insn (insn
.insn
, insn
.buffer
,
1041 CGEN_FIELDS_BITSIZE (& insn
.fields
), 1, NULL
);
1045 int on_32bit_boundary_p
;
1048 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
1051 insn
.orig_insn
= insn
.insn
;
1053 /* If the previous insn was relaxable, then it may be expanded
1054 to fill the current 16 bit slot. Emit a NOP here to occupy
1055 this slot, so that we can start at optimizing at a 32 bit
1057 if (prev_insn
.insn
&& seen_relaxable_p
&& optimize
)
1062 /* Get the indices of the operands of the instruction.
1063 FIXME: See assemble_parallel for notes on orig_insn. */
1065 CGEN_FIELDS tmp_fields
;
1066 insn
.insn
= cgen_lookup_get_insn_operands
1067 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (insn
.buffer
), NULL
,
1068 16, insn
.indices
, &tmp_fields
);
1071 if (insn
.insn
== NULL
)
1072 as_fatal (_("internal error: lookup/get operands failed"));
1075 /* Compute whether we're on a 32 bit boundary or not.
1076 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1077 on_32bit_boundary_p
= prev_insn
.insn
== NULL
;
1079 /* Look to see if this instruction can be combined with the
1080 previous instruction to make one, parallel, 32 bit instruction.
1081 If the previous instruction (potentially) changed the flow of
1082 program control, then it cannot be combined with the current
1083 instruction. If the current instruction is relaxable, then it
1084 might be replaced with a longer version, so we cannot combine it.
1085 Also if the output of the previous instruction is used as an
1086 input to the current instruction then it cannot be combined.
1087 Otherwise call can_make_parallel() with both orderings of the
1088 instructions to see if they can be combined. */
1089 if ( ! on_32bit_boundary_p
1092 && CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) == 0
1093 && ! writes_to_pc (& prev_insn
)
1094 && ! first_writes_to_seconds_operands (& prev_insn
, &insn
, false)
1097 if (can_make_parallel (& prev_insn
, & insn
) == NULL
)
1098 make_parallel (insn
.buffer
);
1099 else if (can_make_parallel (& insn
, & prev_insn
) == NULL
)
1103 expand_debug_syms (insn
.debug_sym_link
, 1);
1109 /* Ensure each pair of 16 bit insns is in the same frag. */
1112 gas_cgen_finish_insn (insn
.orig_insn
, insn
.buffer
,
1113 CGEN_FIELDS_BITSIZE (& insn
.fields
),
1114 1 /*relax_p*/, &fi
);
1115 insn
.addr
= fi
.addr
;
1116 insn
.frag
= fi
.frag
;
1117 insn
.num_fixups
= fi
.num_fixups
;
1118 for (i
= 0; i
< fi
.num_fixups
; ++i
)
1119 insn
.fixups
[i
] = fi
.fixups
[i
];
1126 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1128 /* Swap the two insns */
1129 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
1130 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
1132 target_make_parallel (insn
.addr
);
1134 /* Swap any relaxable frags recorded for the two insns. */
1135 /* FIXME: Clarify. relaxation precludes parallel insns */
1136 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
1137 prev_insn
.frag
->fr_opcode
= insn
.addr
;
1138 else if (insn
.frag
->fr_opcode
== insn
.addr
)
1139 insn
.frag
->fr_opcode
= prev_insn
.addr
;
1141 /* Update the addresses in any fixups.
1142 Note that we don't have to handle the case where each insn is in
1143 a different frag as we ensure they're in the same frag above. */
1144 for (i
= 0; i
< prev_insn
.num_fixups
; ++i
)
1145 prev_insn
.fixups
[i
]->fx_where
+= 2;
1146 for (i
= 0; i
< insn
.num_fixups
; ++i
)
1147 insn
.fixups
[i
]->fx_where
-= 2;
1150 /* Keep track of whether we've seen a pair of 16 bit insns.
1151 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1152 if (on_32bit_boundary_p
)
1155 prev_insn
.insn
= NULL
;
1157 /* If the insn needs the following one to be on a 32 bit boundary
1158 (e.g. subroutine calls), fill this insn's slot. */
1159 if (on_32bit_boundary_p
1160 && CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_FILL_SLOT
) != 0)
1163 /* If this is a relaxable insn (can be replaced with a larger version)
1164 mark the fact so that we can emit an alignment directive for a
1165 following 32 bit insn if we see one. */
1166 if (CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) != 0)
1167 seen_relaxable_p
= 1;
1170 /* Set these so m32r_fill_insn can use them. */
1172 prev_subseg
= now_subseg
;
1175 /* The syntax in the manual says constants begin with '#'.
1176 We just ignore it. */
1179 md_operand (expressionP
)
1180 expressionS
* expressionP
;
1182 if (* input_line_pointer
== '#')
1184 input_line_pointer
++;
1185 expression (expressionP
);
1190 md_section_align (segment
, size
)
1194 int align
= bfd_get_section_alignment (stdoutput
, segment
);
1195 return ((size
+ (1 << align
) - 1) & (-1 << align
));
1199 md_undefined_symbol (name
)
1205 /* .scomm pseudo-op handler.
1207 This is a new pseudo-op to handle putting objects in .scommon.
1208 By doing this the linker won't need to do any work and more importantly
1209 it removes the implicit -G arg necessary to correctly link the object file.
1216 register char * name
;
1220 register symbolS
* symbolP
;
1224 name
= input_line_pointer
;
1225 c
= get_symbol_end ();
1227 /* just after name is now '\0' */
1228 p
= input_line_pointer
;
1231 if (* input_line_pointer
!= ',')
1233 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1234 ignore_rest_of_line ();
1238 input_line_pointer
++; /* skip ',' */
1239 if ((size
= get_absolute_expression ()) < 0)
1241 /* xgettext:c-format */
1242 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size
);
1243 ignore_rest_of_line ();
1247 /* The third argument to .scomm is the alignment. */
1248 if (* input_line_pointer
!= ',')
1252 ++ input_line_pointer
;
1253 align
= get_absolute_expression ();
1256 as_warn (_("ignoring bad alignment"));
1260 /* Convert to a power of 2 alignment. */
1263 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++ align2
)
1267 as_bad (_("Common alignment not a power of 2"));
1268 ignore_rest_of_line ();
1276 symbolP
= symbol_find_or_make (name
);
1279 if (S_IS_DEFINED (symbolP
))
1281 /* xgettext:c-format */
1282 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1283 S_GET_NAME (symbolP
));
1284 ignore_rest_of_line ();
1288 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
1290 /* xgettext:c-format */
1291 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1292 S_GET_NAME (symbolP
),
1293 (long) S_GET_VALUE (symbolP
),
1296 ignore_rest_of_line ();
1300 if (symbol_get_obj (symbolP
)->local
)
1302 segT old_sec
= now_seg
;
1303 int old_subsec
= now_subseg
;
1306 record_alignment (sbss_section
, align2
);
1307 subseg_set (sbss_section
, 0);
1310 frag_align (align2
, 0, 0);
1312 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1313 symbol_get_frag (symbolP
)->fr_symbol
= 0;
1315 symbol_set_frag (symbolP
, frag_now
);
1317 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1320 S_SET_SIZE (symbolP
, size
);
1321 S_SET_SEGMENT (symbolP
, sbss_section
);
1322 S_CLEAR_EXTERNAL (symbolP
);
1323 subseg_set (old_sec
, old_subsec
);
1327 S_SET_VALUE (symbolP
, (valueT
) size
);
1328 S_SET_ALIGN (symbolP
, align2
);
1329 S_SET_EXTERNAL (symbolP
);
1330 S_SET_SEGMENT (symbolP
, & scom_section
);
1333 demand_empty_rest_of_line ();
1336 /* Interface to relax_segment. */
1338 /* FIXME: Build table by hand, get it working, then machine generate. */
1340 const relax_typeS md_relax_table
[] =
1343 1) most positive reach of this state,
1344 2) most negative reach of this state,
1345 3) how many bytes this mode will add to the size of the current frag
1346 4) which index into the table to try if we can't fit into this one. */
1348 /* The first entry must be unused because an `rlx_more' value of zero ends
1352 /* The displacement used by GAS is from the end of the 2 byte insn,
1353 so we subtract 2 from the following. */
1354 /* 16 bit insn, 8 bit disp -> 10 bit range.
1355 This doesn't handle a branch in the right slot at the border:
1356 the "& -4" isn't taken into account. It's not important enough to
1357 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1359 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1360 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1361 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1362 /* Same thing, but with leading nop for alignment. */
1363 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1367 m32r_relax_frag (fragP
, stretch
)
1371 /* Address of branch insn. */
1372 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1375 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1376 if (fragP
->fr_subtype
== 2)
1378 if ((address
& 3) != 0)
1380 fragP
->fr_subtype
= 3;
1384 else if (fragP
->fr_subtype
== 3)
1386 if ((address
& 3) == 0)
1388 fragP
->fr_subtype
= 2;
1394 growth
= relax_frag (fragP
, stretch
);
1396 /* Long jump on odd halfword boundary? */
1397 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1399 fragP
->fr_subtype
= 3;
1407 /* Return an initial guess of the length by which a fragment must grow to
1408 hold a branch to reach its destination.
1409 Also updates fr_type/fr_subtype as necessary.
1411 Called just before doing relaxation.
1412 Any symbol that is now undefined will not become defined.
1413 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1414 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1415 Although it may not be explicit in the frag, pretend fr_var starts with a
1419 md_estimate_size_before_relax (fragP
, segment
)
1423 int old_fr_fix
= fragP
->fr_fix
;
1425 /* The only thing we have to handle here are symbols outside of the
1426 current segment. They may be undefined or in a different segment in
1427 which case linker scripts may place them anywhere.
1428 However, we can't finish the fragment here and emit the reloc as insn
1429 alignment requirements may move the insn about. */
1431 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1433 /* The symbol is undefined in this segment.
1434 Change the relaxation subtype to the max allowable and leave
1435 all further handling to md_convert_frag. */
1436 fragP
->fr_subtype
= 2;
1438 #if 0 /* Can't use this, but leave in for illustration. */
1439 /* Change 16 bit insn to 32 bit insn. */
1440 fragP
->fr_opcode
[0] |= 0x80;
1442 /* Increase known (fixed) size of fragment. */
1445 /* Create a relocation for it. */
1446 fix_new (fragP
, old_fr_fix
, 4,
1448 fragP
->fr_offset
, 1 /* pcrel */,
1449 /* FIXME: Can't use a real BFD reloc here.
1450 gas_cgen_md_apply_fix3 can't handle it. */
1451 BFD_RELOC_M32R_26_PCREL
);
1453 /* Mark this fragment as finished. */
1457 const CGEN_INSN
* insn
;
1460 /* Update the recorded insn.
1461 Fortunately we don't have to look very far.
1462 FIXME: Change this to record in the instruction the next higher
1463 relaxable insn to use. */
1464 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1466 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1467 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1469 && CGEN_INSN_ATTR_VALUE (insn
, CGEN_INSN_RELAX
))
1475 fragP
->fr_cgen
.insn
= insn
;
1481 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
1484 /* *fragP has been relaxed to its final size, and now needs to have
1485 the bytes inside it modified to conform to the new size.
1487 Called after relaxation is finished.
1488 fragP->fr_type == rs_machine_dependent.
1489 fragP->fr_subtype is the subtype of what the address relaxed to. */
1492 md_convert_frag (abfd
, sec
, fragP
)
1498 char * displacement
;
1504 opcode
= fragP
->fr_opcode
;
1506 /* Address opcode resides at in file space. */
1507 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1509 switch (fragP
->fr_subtype
)
1513 displacement
= & opcode
[1];
1518 displacement
= & opcode
[1];
1521 opcode
[2] = opcode
[0] | 0x80;
1522 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1523 opcode_address
+= 2;
1525 displacement
= & opcode
[3];
1531 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1533 /* symbol must be resolved by linker */
1534 if (fragP
->fr_offset
& 3)
1535 as_warn (_("Addend to unresolved symbol not on word boundary."));
1536 addend
= fragP
->fr_offset
>> 2;
1540 /* Address we want to reach in file space. */
1541 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1542 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
1543 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1546 /* Create a relocation for symbols that must be resolved by the linker.
1547 Otherwise output the completed insn. */
1549 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1551 assert (fragP
->fr_subtype
!= 1);
1552 assert (fragP
->fr_cgen
.insn
!= 0);
1553 gas_cgen_record_fixup (fragP
,
1554 /* Offset of branch insn in frag. */
1555 fragP
->fr_fix
+ extension
- 4,
1556 fragP
->fr_cgen
.insn
,
1558 /* FIXME: quick hack */
1560 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1561 fragP
->fr_cgen
.opindex
),
1563 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1564 M32R_OPERAND_DISP24
),
1566 fragP
->fr_cgen
.opinfo
,
1567 fragP
->fr_symbol
, fragP
->fr_offset
);
1570 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1572 md_number_to_chars (displacement
, (valueT
) addend
,
1573 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1575 fragP
->fr_fix
+= extension
;
1578 /* Functions concerning relocs. */
1580 /* The location from which a PC relative jump should be calculated,
1581 given a PC relative reloc. */
1584 md_pcrel_from_section (fixP
, sec
)
1588 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1589 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1590 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1592 /* The symbol is undefined (or is defined but not in this section).
1593 Let the linker figure it out. */
1597 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1600 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1601 Returns BFD_RELOC_NONE if no reloc type can be found.
1602 *FIXP may be modified if desired. */
1604 bfd_reloc_code_real_type
1605 md_cgen_lookup_reloc (insn
, operand
, fixP
)
1606 const CGEN_INSN
* insn
;
1607 const CGEN_OPERAND
* operand
;
1610 switch (operand
->type
)
1612 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1613 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1614 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1615 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1616 case M32R_OPERAND_HI16
:
1617 case M32R_OPERAND_SLO16
:
1618 case M32R_OPERAND_ULO16
:
1619 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1620 if (fixP
->fx_cgen
.opinfo
!= 0)
1621 return fixP
->fx_cgen
.opinfo
;
1623 default : /* avoid -Wall warning */
1626 return BFD_RELOC_NONE
;
1629 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1632 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1637 struct m32r_hi_fixup
* hi_fixup
;
1639 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1640 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1642 hi_fixup
= ((struct m32r_hi_fixup
*)
1643 xmalloc (sizeof (struct m32r_hi_fixup
)));
1644 hi_fixup
->fixp
= fixP
;
1645 hi_fixup
->seg
= now_seg
;
1646 hi_fixup
->next
= m32r_hi_fixup_list
;
1648 m32r_hi_fixup_list
= hi_fixup
;
1651 /* Called while parsing an instruction to create a fixup.
1652 We need to check for HI16 relocs and queue them up for later sorting. */
1655 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1658 const CGEN_INSN
* insn
;
1660 const CGEN_OPERAND
* operand
;
1664 fixS
* fixP
= gas_cgen_record_fixup_exp (frag
, where
, insn
, length
,
1665 operand
, opinfo
, exp
);
1667 switch (operand
->type
)
1669 case M32R_OPERAND_HI16
:
1670 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1671 if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1672 || fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1673 m32r_record_hi16 (fixP
->fx_cgen
.opinfo
, fixP
, now_seg
);
1675 default : /* avoid -Wall warning */
1682 /* Return BFD reloc type from opinfo field in a fixS.
1683 It's tricky using fx_r_type in m32r_frob_file because the values
1684 are BFD_RELOC_UNUSED + operand number. */
1685 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
1687 /* Sort any unmatched HI16 relocs so that they immediately precede
1688 the corresponding LO16 reloc. This is called before md_apply_fix and
1694 struct m32r_hi_fixup
* l
;
1696 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1698 segment_info_type
* seginfo
;
1701 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1702 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1704 /* Check quickly whether the next fixup happens to be a matching low. */
1705 if (l
->fixp
->fx_next
!= NULL
1706 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1707 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1708 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1711 /* Look through the fixups for this segment for a matching `low'.
1712 When we find one, move the high/shigh just in front of it. We do
1713 this in two passes. In the first pass, we try to find a
1714 unique `low'. In the second pass, we permit multiple high's
1715 relocs for a single `low'. */
1716 seginfo
= seg_info (l
->seg
);
1717 for (pass
= 0; pass
< 2; pass
++)
1723 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1725 /* Check whether this is a `low' fixup which matches l->fixp. */
1726 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
1727 && f
->fx_addsy
== l
->fixp
->fx_addsy
1728 && f
->fx_offset
== l
->fixp
->fx_offset
1731 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
1732 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
1733 || prev
->fx_addsy
!= f
->fx_addsy
1734 || prev
->fx_offset
!= f
->fx_offset
))
1738 /* Move l->fixp before f. */
1739 for (pf
= &seginfo
->fix_root
;
1741 pf
= & (* pf
)->fx_next
)
1742 assert (* pf
!= NULL
);
1744 * pf
= l
->fixp
->fx_next
;
1746 l
->fixp
->fx_next
= f
;
1748 seginfo
->fix_root
= l
->fixp
;
1750 prev
->fx_next
= l
->fixp
;
1762 && warn_unmatched_high
)
1763 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1764 _("Unmatched high/shigh reloc"));
1769 /* See whether we need to force a relocation into the output file.
1770 This is used to force out switch and PC relative relocations when
1774 m32r_force_relocation (fix
)
1777 if (fix
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1778 || fix
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1784 return (fix
->fx_pcrel
1788 /* Write a value out to the object file, using the appropriate endianness. */
1791 md_number_to_chars (buf
, val
, n
)
1796 if (target_big_endian
)
1797 number_to_chars_bigendian (buf
, val
, n
);
1799 number_to_chars_littleendian (buf
, val
, n
);
1802 /* Turn a string in input_line_pointer into a floating point constant of type
1803 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1804 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1807 /* Equal to MAX_PRECISION in atof-ieee.c */
1808 #define MAX_LITTLENUMS 6
1811 md_atof (type
, litP
, sizeP
)
1818 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1820 char * atof_ieee ();
1838 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1842 return _("Bad call to md_atof()");
1845 t
= atof_ieee (input_line_pointer
, type
, words
);
1847 input_line_pointer
= t
;
1848 * sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1850 if (target_big_endian
)
1852 for (i
= 0; i
< prec
; i
++)
1854 md_number_to_chars (litP
, (valueT
) words
[i
],
1855 sizeof (LITTLENUM_TYPE
));
1856 litP
+= sizeof (LITTLENUM_TYPE
);
1861 for (i
= prec
- 1; i
>= 0; i
--)
1863 md_number_to_chars (litP
, (valueT
) words
[i
],
1864 sizeof (LITTLENUM_TYPE
));
1865 litP
+= sizeof (LITTLENUM_TYPE
);
1873 m32r_elf_section_change_hook ()
1875 /* If we have reached the end of a section and we have just emitted a
1876 16 bit insn, then emit a nop to make sure that the section ends on
1877 a 32 bit boundary. */
1879 if (prev_insn
.insn
|| seen_relaxable_p
)
1880 (void) m32r_fill_insn (0);
1884 m32r_fix_adjustable (fixP
)
1888 if (fixP
->fx_addsy
== NULL
)
1891 /* Prevent all adjustments to global symbols. */
1892 if (S_IS_EXTERN (fixP
->fx_addsy
))
1894 if (S_IS_WEAK (fixP
->fx_addsy
))
1897 /* We need the symbol name for the VTABLE entries */
1898 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1899 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)