1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 /* Linked list of symbols that are debugging symbols to be defined as the
30 beginning of the current instruction. */
31 typedef struct sym_link
33 struct sym_link
*next
;
37 static sym_linkS
*debug_sym_link
= (sym_linkS
*)0;
39 /* Structure to hold all of the different components describing
40 an individual instruction. */
43 const CGEN_INSN
* insn
;
44 const CGEN_INSN
* orig_insn
;
47 cgen_insn_t buffer
[CGEN_MAX_INSN_SIZE
/ sizeof (cgen_insn_t
)];
49 char buffer
[CGEN_MAX_INSN_SIZE
];
54 fixS
* fixups
[GAS_CGEN_MAX_FIXUPS
];
55 int indices
[MAX_OPERAND_INSTANCES
];
56 sym_linkS
*debug_sym_link
;
60 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
61 boundary (i.e. was the first of two 16 bit insns). */
62 static m32r_insn prev_insn
;
64 /* Non-zero if we've seen a relaxable insn since the last 32 bit
66 static int seen_relaxable_p
= 0;
68 /* Non-zero if -relax specified, in which case sufficient relocs are output
69 for the linker to do relaxing.
70 We do simple forms of relaxing internally, but they are always done.
71 This flag does not apply to them. */
72 static int m32r_relax
;
74 #if 0 /* not supported yet */
75 /* If non-NULL, pointer to cpu description file to read.
76 This allows runtime additions to the assembler. */
77 static const char * m32r_cpu_desc
;
80 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
81 Each high/shigh reloc must be paired with it's low cousin in order to
82 properly calculate the addend in a relocatable link (since there is a
83 potential carry from the low to the high/shigh).
84 This option is off by default though for user-written assembler code it
85 might make sense to make the default be on (i.e. have gcc pass a flag
86 to turn it off). This warning must not be on for GCC created code as
87 optimization may delete the low but not the high/shigh (at least we
88 shouldn't assume or require it to). */
89 static int warn_unmatched_high
= 0;
91 /* start-sanitize-m32rx */
92 /* Non-zero if -m32rx has been specified, in which case support for the
93 extended M32RX instruction set should be enabled. */
94 static int enable_m32rx
= 0;
96 /* Non-zero if -m32rx -hidden has been specified, in which case support for
97 the special M32RX instruction set should be enabled. */
98 static int enable_special
= 0;
100 /* Non-zero if the programmer should be warned when an explicit parallel
101 instruction might have constraint violations. */
102 static int warn_explicit_parallel_conflicts
= 1;
104 /* Non-zero if insns can be made parallel. */
106 /* end-sanitize-m32rx */
108 /* stuff for .scomm symbols. */
109 static segT sbss_section
;
110 static asection scom_section
;
111 static asymbol scom_symbol
;
113 const char comment_chars
[] = ";";
114 const char line_comment_chars
[] = "#";
115 const char line_separator_chars
[] = "";
116 const char EXP_CHARS
[] = "eE";
117 const char FLT_CHARS
[] = "dD";
119 /* Relocations against symbols are done in two
120 parts, with a HI relocation and a LO relocation. Each relocation
121 has only 16 bits of space to store an addend. This means that in
122 order for the linker to handle carries correctly, it must be able
123 to locate both the HI and the LO relocation. This means that the
124 relocations must appear in order in the relocation table.
126 In order to implement this, we keep track of each unmatched HI
127 relocation. We then sort them so that they immediately precede the
128 corresponding LO relocation. */
132 struct m32r_hi_fixup
* next
; /* Next HI fixup. */
133 fixS
* fixp
; /* This fixup. */
134 segT seg
; /* The section this fixup is in. */
138 /* The list of unmatched HI relocs. */
140 static struct m32r_hi_fixup
* m32r_hi_fixup_list
;
143 /* start-sanitize-m32rx */
150 if (stdoutput
!= NULL
)
151 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
152 enable_m32rx
? bfd_mach_m32rx
: bfd_mach_m32r
);
154 /* end-sanitize-m32rx */
156 #define M32R_SHORTOPTS ""
157 /* start-sanitize-m32rx */
158 #undef M32R_SHORTOPTS
159 #define M32R_SHORTOPTS "O"
160 /* end-sanitize-m32rx */
161 const char * md_shortopts
= M32R_SHORTOPTS
;
163 struct option md_longopts
[] =
165 /* start-sanitize-m32rx */
166 #define OPTION_M32RX (OPTION_MD_BASE)
167 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
168 #define OPTION_WARN_PARALLEL (OPTION_MD_BASE + 1)
169 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
170 {"Wp", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
171 #define OPTION_NO_WARN_PARALLEL (OPTION_MD_BASE + 2)
172 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
173 {"Wnp", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
174 #define OPTION_SPECIAL (OPTION_MD_BASE + 3)
175 {"hidden", no_argument
, NULL
, OPTION_SPECIAL
},
176 /* end-sanitize-m32rx */
178 /* Sigh. I guess all warnings must now have both variants. */
179 #define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4)
180 {"warn-unmatched-high", OPTION_WARN_UNMATCHED
},
181 {"Wuh", OPTION_WARN_UNMATCHED
},
182 #define OPTION_NO_WARN_UNMATCHED (OPTION_MD_BASE + 5)
183 {"no-warn-unmatched-high", OPTION_WARN_UNMATCHED
},
184 {"Wnuh", OPTION_WARN_UNMATCHED
},
186 #if 0 /* not supported yet */
187 #define OPTION_RELAX (OPTION_MD_BASE + 6)
188 {"relax", no_argument
, NULL
, OPTION_RELAX
},
189 #define OPTION_CPU_DESC (OPTION_MD_BASE + 7)
190 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
193 {NULL
, no_argument
, NULL
, 0}
195 size_t md_longopts_size
= sizeof (md_longopts
);
198 md_parse_option (c
, arg
)
204 /* start-sanitize-m32rx */
213 case OPTION_WARN_PARALLEL
:
214 warn_explicit_parallel_conflicts
= 1;
217 case OPTION_NO_WARN_PARALLEL
:
218 warn_explicit_parallel_conflicts
= 0;
226 extern char * myname
;
228 /* Pretend that we do not recognise this option. */
229 fprintf (stderr
, _("%s: unrecognised option: -hidden\n"), myname
);
233 /* end-sanitize-m32rx */
235 case OPTION_WARN_UNMATCHED
:
236 warn_unmatched_high
= 1;
239 case OPTION_NO_WARN_UNMATCHED
:
240 warn_unmatched_high
= 0;
243 #if 0 /* not supported yet */
247 case OPTION_CPU_DESC
:
259 md_show_usage (stream
)
262 fprintf (stream
, _(" M32R specific command line options:\n"));
264 /* start-sanitize-m32rx */
265 fprintf (stream
, _("\
266 -m32rx support the extended m32rx instruction set\n"));
267 fprintf (stream
, _("\
268 -O try to combine instructions in parallel\n"));
270 fprintf (stream
, _("\
271 -warn-explicit-parallel-conflicts warn when parallel instructions\n"));
272 fprintf (stream
, _("\
273 violate contraints\n"));
274 fprintf (stream
, _("\
275 -no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
276 fprintf (stream
, _("\
277 instructions violate contraints\n"));
278 fprintf (stream
, _("\
279 -Wp synonym for -warn-explicit-parallel-conflicts\n"));
280 fprintf (stream
, _("\
281 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
282 /* end-sanitize-m32rx */
284 fprintf (stream
, _("\
285 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
286 fprintf (stream
, _("\
287 -no-warn-unmatched-high do not warn about missing low relocs\n"));
288 fprintf (stream
, _("\
289 -Wuh synonym for -warn-unmatched-high\n"));
290 fprintf (stream
, _("\
291 -Wnuh synonym for -no-warn-unmatched-high\n"));
294 fprintf (stream
, _("\
295 -relax create linker relaxable code\n"));
296 fprintf (stream
, _("\
297 -cpu-desc provide runtime cpu description file\n"));
301 static void fill_insn
PARAMS ((int));
302 static void m32r_scomm
PARAMS ((int));
303 static void debug_sym
PARAMS ((int));
304 static void expand_debug_syms
PARAMS ((sym_linkS
*, int));
306 /* Set by md_assemble for use by m32r_fill_insn. */
307 static subsegT prev_subseg
;
308 static segT prev_seg
;
310 /* The target specific pseudo-ops which we support. */
311 const pseudo_typeS md_pseudo_table
[] =
314 { "fillinsn", fill_insn
, 0 },
315 { "scomm", m32r_scomm
, 0 },
316 { "debugsym", debug_sym
, 0 },
317 /* start-sanitize-m32rx */
318 /* Not documented as so far there is no need for them.... */
319 { "m32r", allow_m32rx
, 0 },
320 { "m32rx", allow_m32rx
, 1 },
321 /* end-sanitize-m32rx */
325 /* FIXME: Should be machine generated. */
326 #define NOP_INSN 0x7000
327 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
329 /* When we align the .text section, insert the correct NOP pattern.
330 N is the power of 2 alignment. LEN is the length of pattern FILL.
331 MAX is the maximum number of characters to skip when doing the alignment,
332 or 0 if there is no maximum. */
335 m32r_do_align (n
, fill
, len
, max
)
341 /* Only do this if the fill pattern wasn't specified. */
343 && (now_seg
->flags
& SEC_CODE
) != 0
344 /* Only do this special handling if aligning to at least a
347 /* Only do this special handling if we're allowed to emit at
349 && (max
== 0 || max
> 1))
351 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
354 /* First align to a 2 byte boundary, in case there is an odd .byte. */
355 /* FIXME: How much memory will cause gas to use when assembling a big
356 program? Perhaps we can avoid the frag_align call? */
357 frag_align (1, 0, 0);
359 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
361 frag_align_pattern (2, nop_pattern
, sizeof nop_pattern
, 0);
362 /* If doing larger alignments use a repeating sequence of appropriate
366 static const unsigned char multi_nop_pattern
[] =
367 { 0x70, 0x00, 0xf0, 0x00 };
368 frag_align_pattern (n
, multi_nop_pattern
, sizeof multi_nop_pattern
,
372 prev_insn
.insn
= NULL
;
379 /* If the last instruction was the first of 2 16 bit insns,
380 output a nop to move the PC to a 32 bit boundary.
382 This is done via an alignment specification since branch relaxing
383 may make it unnecessary.
385 Internally, we need to output one of these each time a 32 bit insn is
386 seen after an insn that is relaxable. */
392 (void) m32r_do_align (2, NULL
, 0, 0);
393 prev_insn
.insn
= NULL
;
394 seen_relaxable_p
= 0;
397 /* Record the symbol so that when we output the insn, we can create
398 a symbol that is at the start of the instruction. This is used
399 to emit the label for the start of a breakpoint without causing
400 the assembler to emit a NOP if the previous instruction was a
401 16 bit instruction. */
409 register char *end_name
;
410 register symbolS
*symbolP
;
411 register sym_linkS
*link
;
413 name
= input_line_pointer
;
414 delim
= get_symbol_end ();
415 end_name
= input_line_pointer
;
417 if ((symbolP
= symbol_find (name
)) == NULL
418 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
420 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
423 symbol_table_insert (symbolP
);
424 if (S_IS_DEFINED (symbolP
) && S_GET_SEGMENT (symbolP
) != reg_section
)
425 /* xgettext:c-format */
426 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
430 link
= (sym_linkS
*) xmalloc (sizeof (sym_linkS
));
431 link
->symbol
= symbolP
;
432 link
->next
= debug_sym_link
;
433 debug_sym_link
= link
;
438 demand_empty_rest_of_line ();
441 /* Second pass to expanding the debug symbols, go through linked
442 list of symbols and reassign the address. */
445 expand_debug_syms (syms
, align
)
449 char *save_input_line
= input_line_pointer
;
450 sym_linkS
*next_syms
;
455 (void) m32r_do_align (align
, NULL
, 0, 0);
456 for (; syms
!= (sym_linkS
*)0; syms
= next_syms
)
458 symbolS
*symbolP
= syms
->symbol
;
459 next_syms
= syms
->next
;
460 input_line_pointer
= ".\n";
461 pseudo_set (symbolP
);
465 input_line_pointer
= save_input_line
;
468 /* Cover function to fill_insn called after a label and at end of assembly.
469 The result is always 1: we're called in a conditional to see if the
470 current line is a label. */
473 m32r_fill_insn (done
)
476 if (prev_seg
!= NULL
)
479 subsegT subseg
= now_subseg
;
481 subseg_set (prev_seg
, prev_subseg
);
485 subseg_set (seg
, subseg
);
488 if (done
&& debug_sym_link
)
490 expand_debug_syms (debug_sym_link
, 1);
491 debug_sym_link
= (sym_linkS
*)0;
504 /* Initialize the `cgen' interface. */
506 /* Set the machine number and endian. */
507 gas_cgen_opcode_desc
= m32r_cgen_opcode_open (0 /* mach number */,
510 : CGEN_ENDIAN_LITTLE
);
511 m32r_cgen_init_asm (gas_cgen_opcode_desc
);
513 /* This is a callback from cgen to gas to parse operands. */
514 cgen_set_parse_operand_fn (gas_cgen_opcode_desc
, gas_cgen_parse_operand
);
516 #if 0 /* not supported yet */
517 /* If a runtime cpu description file was provided, parse it. */
518 if (m32r_cpu_desc
!= NULL
)
522 errmsg
= cgen_read_cpu_file (gas_cgen_opcode_desc
, m32r_cpu_desc
);
524 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
528 /* Save the current subseg so we can restore it [it's the default one and
529 we don't want the initial section to be .sbss]. */
533 /* The sbss section is for local .scomm symbols. */
534 sbss_section
= subseg_new (".sbss", 0);
536 /* This is copied from perform_an_assembly_pass. */
537 applicable
= bfd_applicable_section_flags (stdoutput
);
538 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
540 #if 0 /* What does this do? [see perform_an_assembly_pass] */
541 seg_info (bss_section
)->bss
= 1;
544 subseg_set (seg
, subseg
);
546 /* We must construct a fake section similar to bfd_com_section
547 but with the name .scommon. */
548 scom_section
= bfd_com_section
;
549 scom_section
.name
= ".scommon";
550 scom_section
.output_section
= & scom_section
;
551 scom_section
.symbol
= & scom_symbol
;
552 scom_section
.symbol_ptr_ptr
= & scom_section
.symbol
;
553 scom_symbol
= * bfd_com_section
.symbol
;
554 scom_symbol
.name
= ".scommon";
555 scom_symbol
.section
= & scom_section
;
557 /* start-sanitize-m32rx */
558 allow_m32rx (enable_m32rx
);
559 /* end-sanitize-m32rx */
562 /* start-sanitize-m32rx */
564 #define OPERAND_IS_COND_BIT(operand, indices, index) \
565 (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \
566 || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \
567 && (indices [index] == 0 || indices [index] == 1)))
569 /* Returns true if an output of instruction 'a' is referenced by an operand
570 of instruction 'b'. If 'check_outputs' is true then b's outputs are
571 checked, otherwise its inputs are examined. */
574 first_writes_to_seconds_operands (a
, b
, check_outputs
)
577 const int check_outputs
;
579 const CGEN_OPERAND_INSTANCE
* a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
580 const CGEN_OPERAND_INSTANCE
* b_ops
= CGEN_INSN_OPERANDS (b
->insn
);
583 /* If at least one of the instructions takes no operands, then there is
584 nothing to check. There really are instructions without operands,
586 if (a_operands
== NULL
|| b_ops
== NULL
)
589 /* Scan the operand list of 'a' looking for an output operand. */
591 CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
;
592 a_index
++, a_operands
++)
594 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) == CGEN_OPERAND_INSTANCE_OUTPUT
)
597 const CGEN_OPERAND_INSTANCE
* b_operands
= b_ops
;
600 The Condition bit 'C' is a shadow of the CBR register (control
601 register 1) and also a shadow of bit 31 of the program status
602 word (control register 0). For now this is handled here, rather
605 if (OPERAND_IS_COND_BIT (a_operands
, a
->indices
, a_index
))
607 /* Scan operand list of 'b' looking for another reference to the
608 condition bit, which goes in the right direction. */
610 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
611 b_index
++, b_operands
++)
613 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
614 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
615 && OPERAND_IS_COND_BIT (b_operands
, b
->indices
, b_index
))
621 /* Scan operand list of 'b' looking for an operand that
622 references the same hardware element, and which goes in the
625 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
626 b_index
++, b_operands
++)
628 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
629 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
630 && (CGEN_OPERAND_INSTANCE_HW (b_operands
) == CGEN_OPERAND_INSTANCE_HW (a_operands
))
631 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
641 /* Returns true if the insn can (potentially) alter the program counter. */
647 #if 0 /* Once PC operands are working.... */
648 const CGEN_OPERAND_INSTANCE
* a_operands
== CGEN_INSN_OPERANDS (a
->insn
);
650 if (a_operands
== NULL
)
653 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
)
655 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
) != NULL
656 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
)) == M32R_OPERAND_PC
)
662 if (CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_UNCOND_CTI
)
663 || CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_COND_CTI
))
669 /* Returns NULL if the two 16 bit insns can be executed in parallel,
670 otherwise it returns a pointer to an error message explaining why not. */
673 can_make_parallel (a
, b
)
680 /* Make sure the instructions are the right length. */
681 if ( CGEN_FIELDS_BITSIZE (& a
->fields
) != 16
682 || CGEN_FIELDS_BITSIZE (& b
->fields
) != 16)
685 if (first_writes_to_seconds_operands (a
, b
, true))
686 return _("Instructions write to the same destination register.");
688 a_pipe
= CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_PIPE
);
689 b_pipe
= CGEN_INSN_ATTR (b
->insn
, CGEN_INSN_PIPE
);
691 /* Make sure that the instructions use the correct execution pipelines. */
692 if ( a_pipe
== PIPE_NONE
693 || b_pipe
== PIPE_NONE
)
694 return _("Instructions do not use parallel execution pipelines.");
696 /* Leave this test for last, since it is the only test that can
697 go away if the instructions are swapped, and we want to make
698 sure that any other errors are detected before this happens. */
699 if ( a_pipe
== PIPE_S
701 return _("Instructions share the same execution pipeline");
709 make_parallel (buffer
)
710 cgen_insn_t
* buffer
;
712 /* Force the top bit of the second insn to be set. */
716 if (CGEN_OPCODE_ENDIAN (gas_cgen_opcode_desc
) == CGEN_ENDIAN_BIG
)
718 value
= bfd_getb16 ((bfd_byte
*) buffer
);
720 bfd_putb16 (value
, (char *) buffer
);
724 value
= bfd_getl16 ((bfd_byte
*) buffer
);
726 bfd_putl16 (value
, (char *) buffer
);
733 make_parallel (buffer
)
736 /* Force the top bit of the second insn to be set. */
738 buffer
[CGEN_OPCODE_ENDIAN (gas_cgen_opcode_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
742 #endif /* ! CGEN_INT_INSN */
745 assemble_parallel_insn (str
, str2
)
754 * str2
= 0; /* Seperate the two instructions. */
756 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
757 so that the parallel instruction will start on a 32 bit boundary. */
761 first
.debug_sym_link
= debug_sym_link
;
762 debug_sym_link
= (sym_linkS
*)0;
764 /* Parse the first instruction. */
765 if (! (first
.insn
= m32r_cgen_assemble_insn
766 (gas_cgen_opcode_desc
, str
, & first
.fields
, first
.buffer
, & errmsg
)))
773 && CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_SPECIAL
))
775 /* xgettext:c-format */
776 as_bad (_("unknown instruction '%s'"), str
);
779 else if (! enable_m32rx
780 /* FIXME: Need standard macro to perform this test. */
781 && CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
783 /* xgettext:c-format */
784 as_bad (_("instruction '%s' is for the M32RX only"), str
);
788 /* Check to see if this is an allowable parallel insn. */
789 if (CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
791 /* xgettext:c-format */
792 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
796 *str2
= '|'; /* Restore the original assembly text, just in case it is needed. */
797 str3
= str
; /* Save the original string pointer. */
798 str
= str2
+ 2; /* Advanced past the parsed string. */
799 str2
= str3
; /* Remember the entire string in case it is needed for error messages. */
801 /* Preserve any fixups that have been generated and reset the list to empty. */
802 gas_cgen_save_fixups();
804 /* Get the indices of the operands of the instruction. */
805 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
806 doesn't seem right. Perhaps allow passing fields like we do insn. */
807 /* FIXME: ALIAS insns do not have operands, so we use this function
808 to find the equivalent insn and overwrite the value stored in our
809 structure. We still need the original insn, however, since this
810 may have certain attributes that are not present in the unaliased
811 version (eg relaxability). When aliases behave differently this
812 may have to change. */
813 first
.orig_insn
= first
.insn
;
814 first
.insn
= m32r_cgen_lookup_get_insn_operands
815 (gas_cgen_opcode_desc
, NULL
, bfd_getb16 ((char *) first
.buffer
), 16,
818 if (first
.insn
== NULL
)
819 as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for first insn"));
821 second
.debug_sym_link
= NULL
;
823 /* Parse the second instruction. */
824 if (! (second
.insn
= m32r_cgen_assemble_insn
825 (gas_cgen_opcode_desc
, str
, & second
.fields
, second
.buffer
, & errmsg
)))
833 && CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_SPECIAL
))
835 /* xgettext:c-format */
836 as_bad (_("unknown instruction '%s'"), str
);
839 else if (! enable_m32rx
840 && CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
842 /* xgettext:c-format */
843 as_bad (_("instruction '%s' is for the M32RX only"), str
);
847 /* Check to see if this is an allowable parallel insn. */
848 if (CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
850 /* xgettext:c-format */
851 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
857 if (CGEN_INSN_NUM (first
.insn
) != M32R_INSN_NOP
858 && CGEN_INSN_NUM (second
.insn
) != M32R_INSN_NOP
)
860 /* xgettext:c-format */
861 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2
);
866 /* Get the indices of the operands of the instruction. */
867 second
.orig_insn
= second
.insn
;
868 second
.insn
= m32r_cgen_lookup_get_insn_operands
869 (gas_cgen_opcode_desc
, NULL
, bfd_getb16 ((char *) second
.buffer
), 16,
872 if (second
.insn
== NULL
)
873 as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for second insn"));
875 /* We assume that if the first instruction writes to a register that is
876 read by the second instruction it is because the programmer intended
877 this to happen, (after all they have explicitly requested that these
878 two instructions be executed in parallel). Although if the global
879 variable warn_explicit_parallel_conflicts is true then we do generate
880 a warning message. Similarly we assume that parallel branch and jump
881 instructions are deliberate and should not produce errors. */
883 if (warn_explicit_parallel_conflicts
)
885 if (first_writes_to_seconds_operands (& first
, & second
, false))
886 /* xgettext:c-format */
887 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2
);
889 if (first_writes_to_seconds_operands (& second
, & first
, false))
890 /* xgettext:c-format */
891 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2
);
894 if ((errmsg
= (char *) can_make_parallel (& first
, & second
)) == NULL
)
896 /* Get the fixups for the first instruction. */
897 gas_cgen_swap_fixups ();
900 expand_debug_syms (first
.debug_sym_link
, 1);
901 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
902 CGEN_FIELDS_BITSIZE (& first
.fields
), 0, NULL
);
904 /* Force the top bit of the second insn to be set. */
905 make_parallel (second
.buffer
);
907 /* Get its fixups. */
908 gas_cgen_restore_fixups ();
911 expand_debug_syms (second
.debug_sym_link
, 1);
912 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
913 CGEN_FIELDS_BITSIZE (& second
.fields
), 0, NULL
);
915 /* Try swapping the instructions to see if they work that way. */
916 else if (can_make_parallel (& second
, & first
) == NULL
)
918 /* Write out the second instruction first. */
919 expand_debug_syms (second
.debug_sym_link
, 1);
920 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
921 CGEN_FIELDS_BITSIZE (& second
.fields
), 0, NULL
);
923 /* Force the top bit of the first instruction to be set. */
924 make_parallel (first
.buffer
);
926 /* Get the fixups for the first instruction. */
927 gas_cgen_restore_fixups ();
929 /* Write out the first instruction. */
930 expand_debug_syms (first
.debug_sym_link
, 1);
931 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
932 CGEN_FIELDS_BITSIZE (& first
.fields
), 0, NULL
);
936 as_bad ("'%s': %s", str2
, errmsg
);
940 /* Set these so m32r_fill_insn can use them. */
942 prev_subseg
= now_subseg
;
945 /* end-sanitize-m32rx */
956 /* Initialize GAS's cgen interface for a new instruction. */
957 gas_cgen_init_parse ();
959 /* start-sanitize-m32rx */
960 /* Look for a parallel instruction seperator. */
961 if ((str2
= strstr (str
, "||")) != NULL
)
963 assemble_parallel_insn (str
, str2
);
966 /* end-sanitize-m32rx */
968 insn
.debug_sym_link
= debug_sym_link
;
969 debug_sym_link
= (sym_linkS
*)0;
971 insn
.insn
= m32r_cgen_assemble_insn
972 (gas_cgen_opcode_desc
, str
, & insn
.fields
, insn
.buffer
, & errmsg
);
980 /* start-sanitize-m32rx */
982 && CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_SPECIAL
))
984 /* xgettext:c-format */
985 as_bad (_("unknown instruction '%s'"), str
);
988 else if (! enable_m32rx
989 && CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
991 /* xgettext:c-format */
992 as_bad (_("instruction '%s' is for the M32RX only"), str
);
995 /* end-sanitize-m32rx */
997 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
999 /* 32 bit insns must live on 32 bit boundaries. */
1000 if (prev_insn
.insn
|| seen_relaxable_p
)
1002 /* ??? If calling fill_insn too many times turns us into a memory
1003 pig, can we call a fn to assemble a nop instead of
1004 !seen_relaxable_p? */
1008 expand_debug_syms (insn
.debug_sym_link
, 2);
1010 /* Doesn't really matter what we pass for RELAX_P here. */
1011 gas_cgen_finish_insn (insn
.insn
, insn
.buffer
,
1012 CGEN_FIELDS_BITSIZE (& insn
.fields
), 1, NULL
);
1016 int on_32bit_boundary_p
;
1017 /* start-sanitize-m32rx */
1019 /* end-sanitize-m32rx */
1021 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
1024 insn
.orig_insn
= insn
.insn
;
1025 /* start-sanitize-m32rx */
1028 /* Get the indices of the operands of the instruction.
1029 FIXME: See assemble_parallel for notes on orig_insn. */
1030 insn
.insn
= m32r_cgen_lookup_get_insn_operands
1031 (gas_cgen_opcode_desc
, NULL
, bfd_getb16 ((char *) insn
.buffer
),
1034 if (insn
.insn
== NULL
)
1035 as_fatal (_("internal error: m32r_cgen_get_insn_operands failed"));
1037 /* end-sanitize-m32rx */
1039 /* Compute whether we're on a 32 bit boundary or not.
1040 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1041 on_32bit_boundary_p
= prev_insn
.insn
== NULL
;
1043 /* start-sanitize-m32rx */
1044 /* Look to see if this instruction can be combined with the
1045 previous instruction to make one, parallel, 32 bit instruction.
1046 If the previous instruction (potentially) changed the flow of
1047 program control, then it cannot be combined with the current
1048 instruction. If the current instruction is relaxable, then it
1049 might be replaced with a longer version, so we cannot combine it.
1050 Also if the output of the previous instruction is used as an
1051 input to the current instruction then it cannot be combined.
1052 Otherwise call can_make_parallel() with both orderings of the
1053 instructions to see if they can be combined. */
1054 if ( ! on_32bit_boundary_p
1057 && CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) == 0
1058 && ! writes_to_pc (& prev_insn
)
1059 && ! first_writes_to_seconds_operands (& prev_insn
, &insn
, false)
1062 if (can_make_parallel (& prev_insn
, & insn
) == NULL
)
1063 make_parallel (insn
.buffer
);
1064 else if (can_make_parallel (& insn
, & prev_insn
) == NULL
)
1067 /* end-sanitize-m32rx */
1069 expand_debug_syms (insn
.debug_sym_link
, 1);
1075 /* Ensure each pair of 16 bit insns is in the same frag. */
1078 gas_cgen_finish_insn (insn
.orig_insn
, insn
.buffer
,
1079 CGEN_FIELDS_BITSIZE (& insn
.fields
),
1080 1 /*relax_p*/, &fi
);
1081 insn
.addr
= fi
.addr
;
1082 insn
.frag
= fi
.frag
;
1083 insn
.num_fixups
= fi
.num_fixups
;
1084 for (i
= 0; i
< fi
.num_fixups
; ++i
)
1085 insn
.fixups
[i
] = fi
.fixups
[i
];
1088 /* start-sanitize-m32rx */
1093 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1095 /* Swap the two insns */
1096 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
1097 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
1099 make_parallel (insn
.addr
);
1101 /* Swap any relaxable frags recorded for the two insns. */
1102 /* FIXME: Clarify. relaxation precludes parallel insns */
1103 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
1104 prev_insn
.frag
->fr_opcode
= insn
.addr
;
1105 else if (insn
.frag
->fr_opcode
== insn
.addr
)
1106 insn
.frag
->fr_opcode
= prev_insn
.addr
;
1108 /* Update the addresses in any fixups.
1109 Note that we don't have to handle the case where each insn is in
1110 a different frag as we ensure they're in the same frag above. */
1111 for (i
= 0; i
< prev_insn
.num_fixups
; ++i
)
1112 prev_insn
.fixups
[i
]->fx_where
+= 2;
1113 for (i
= 0; i
< insn
.num_fixups
; ++i
)
1114 insn
.fixups
[i
]->fx_where
-= 2;
1116 /* end-sanitize-m32rx */
1118 /* Keep track of whether we've seen a pair of 16 bit insns.
1119 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1120 if (on_32bit_boundary_p
)
1123 prev_insn
.insn
= NULL
;
1125 /* If the insn needs the following one to be on a 32 bit boundary
1126 (e.g. subroutine calls), fill this insn's slot. */
1127 if (on_32bit_boundary_p
1128 && CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_FILL_SLOT
) != 0)
1131 /* If this is a relaxable insn (can be replaced with a larger version)
1132 mark the fact so that we can emit an alignment directive for a
1133 following 32 bit insn if we see one. */
1134 if (CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) != 0)
1135 seen_relaxable_p
= 1;
1138 /* Set these so m32r_fill_insn can use them. */
1140 prev_subseg
= now_subseg
;
1143 /* The syntax in the manual says constants begin with '#'.
1144 We just ignore it. */
1147 md_operand (expressionP
)
1148 expressionS
* expressionP
;
1150 if (* input_line_pointer
== '#')
1152 input_line_pointer
++;
1153 expression (expressionP
);
1158 md_section_align (segment
, size
)
1162 int align
= bfd_get_section_alignment (stdoutput
, segment
);
1163 return ((size
+ (1 << align
) - 1) & (-1 << align
));
1167 md_undefined_symbol (name
)
1173 /* .scomm pseudo-op handler.
1175 This is a new pseudo-op to handle putting objects in .scommon.
1176 By doing this the linker won't need to do any work and more importantly
1177 it removes the implicit -G arg necessary to correctly link the object file.
1184 register char * name
;
1188 register symbolS
* symbolP
;
1192 name
= input_line_pointer
;
1193 c
= get_symbol_end ();
1195 /* just after name is now '\0' */
1196 p
= input_line_pointer
;
1199 if (* input_line_pointer
!= ',')
1201 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1202 ignore_rest_of_line ();
1206 input_line_pointer
++; /* skip ',' */
1207 if ((size
= get_absolute_expression ()) < 0)
1209 /* xgettext:c-format */
1210 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size
);
1211 ignore_rest_of_line ();
1215 /* The third argument to .scomm is the alignment. */
1216 if (* input_line_pointer
!= ',')
1220 ++ input_line_pointer
;
1221 align
= get_absolute_expression ();
1224 as_warn (_("ignoring bad alignment"));
1228 /* Convert to a power of 2 alignment. */
1231 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++ align2
)
1235 as_bad (_("Common alignment not a power of 2"));
1236 ignore_rest_of_line ();
1244 symbolP
= symbol_find_or_make (name
);
1247 if (S_IS_DEFINED (symbolP
))
1249 /* xgettext:c-format */
1250 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1251 S_GET_NAME (symbolP
));
1252 ignore_rest_of_line ();
1256 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
1258 /* xgettext:c-format */
1259 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1260 S_GET_NAME (symbolP
),
1261 (long) S_GET_VALUE (symbolP
),
1264 ignore_rest_of_line ();
1270 segT old_sec
= now_seg
;
1271 int old_subsec
= now_subseg
;
1274 record_alignment (sbss_section
, align2
);
1275 subseg_set (sbss_section
, 0);
1278 frag_align (align2
, 0, 0);
1280 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1281 symbolP
->sy_frag
->fr_symbol
= 0;
1283 symbolP
->sy_frag
= frag_now
;
1285 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1288 S_SET_SIZE (symbolP
, size
);
1289 S_SET_SEGMENT (symbolP
, sbss_section
);
1290 S_CLEAR_EXTERNAL (symbolP
);
1291 subseg_set (old_sec
, old_subsec
);
1295 S_SET_VALUE (symbolP
, (valueT
) size
);
1296 S_SET_ALIGN (symbolP
, align2
);
1297 S_SET_EXTERNAL (symbolP
);
1298 S_SET_SEGMENT (symbolP
, & scom_section
);
1301 demand_empty_rest_of_line ();
1304 /* Interface to relax_segment. */
1306 /* FIXME: Build table by hand, get it working, then machine generate. */
1308 const relax_typeS md_relax_table
[] =
1311 1) most positive reach of this state,
1312 2) most negative reach of this state,
1313 3) how many bytes this mode will add to the size of the current frag
1314 4) which index into the table to try if we can't fit into this one. */
1316 /* The first entry must be unused because an `rlx_more' value of zero ends
1320 /* The displacement used by GAS is from the end of the 2 byte insn,
1321 so we subtract 2 from the following. */
1322 /* 16 bit insn, 8 bit disp -> 10 bit range.
1323 This doesn't handle a branch in the right slot at the border:
1324 the "& -4" isn't taken into account. It's not important enough to
1325 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1327 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1328 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1329 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1330 /* Same thing, but with leading nop for alignment. */
1331 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1335 m32r_relax_frag (fragP
, stretch
)
1339 /* Address of branch insn. */
1340 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1343 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1344 if (fragP
->fr_subtype
== 2)
1346 if ((address
& 3) != 0)
1348 fragP
->fr_subtype
= 3;
1352 else if (fragP
->fr_subtype
== 3)
1354 if ((address
& 3) == 0)
1356 fragP
->fr_subtype
= 2;
1362 growth
= relax_frag (fragP
, stretch
);
1364 /* Long jump on odd halfword boundary? */
1365 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1367 fragP
->fr_subtype
= 3;
1375 /* Return an initial guess of the length by which a fragment must grow to
1376 hold a branch to reach its destination.
1377 Also updates fr_type/fr_subtype as necessary.
1379 Called just before doing relaxation.
1380 Any symbol that is now undefined will not become defined.
1381 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1382 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1383 Although it may not be explicit in the frag, pretend fr_var starts with a
1387 md_estimate_size_before_relax (fragP
, segment
)
1391 int old_fr_fix
= fragP
->fr_fix
;
1393 /* The only thing we have to handle here are symbols outside of the
1394 current segment. They may be undefined or in a different segment in
1395 which case linker scripts may place them anywhere.
1396 However, we can't finish the fragment here and emit the reloc as insn
1397 alignment requirements may move the insn about. */
1399 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1401 /* The symbol is undefined in this segment.
1402 Change the relaxation subtype to the max allowable and leave
1403 all further handling to md_convert_frag. */
1404 fragP
->fr_subtype
= 2;
1406 #if 0 /* Can't use this, but leave in for illustration. */
1407 /* Change 16 bit insn to 32 bit insn. */
1408 fragP
->fr_opcode
[0] |= 0x80;
1410 /* Increase known (fixed) size of fragment. */
1413 /* Create a relocation for it. */
1414 fix_new (fragP
, old_fr_fix
, 4,
1416 fragP
->fr_offset
, 1 /* pcrel */,
1417 /* FIXME: Can't use a real BFD reloc here.
1418 gas_cgen_md_apply_fix3 can't handle it. */
1419 BFD_RELOC_M32R_26_PCREL
);
1421 /* Mark this fragment as finished. */
1425 const CGEN_INSN
* insn
;
1428 /* Update the recorded insn.
1429 Fortunately we don't have to look very far.
1430 FIXME: Change this to record in the instruction the next higher
1431 relaxable insn to use. */
1432 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1434 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1435 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1437 && CGEN_INSN_ATTR (insn
, CGEN_INSN_RELAX
))
1443 fragP
->fr_cgen
.insn
= insn
;
1449 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
1452 /* *fragP has been relaxed to its final size, and now needs to have
1453 the bytes inside it modified to conform to the new size.
1455 Called after relaxation is finished.
1456 fragP->fr_type == rs_machine_dependent.
1457 fragP->fr_subtype is the subtype of what the address relaxed to. */
1460 md_convert_frag (abfd
, sec
, fragP
)
1466 char * displacement
;
1472 opcode
= fragP
->fr_opcode
;
1474 /* Address opcode resides at in file space. */
1475 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1477 switch (fragP
->fr_subtype
)
1481 displacement
= & opcode
[1];
1486 displacement
= & opcode
[1];
1489 opcode
[2] = opcode
[0] | 0x80;
1490 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1491 opcode_address
+= 2;
1493 displacement
= & opcode
[3];
1499 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1501 /* symbol must be resolved by linker */
1502 if (fragP
->fr_offset
& 3)
1503 as_warn (_("Addend to unresolved symbol not on word boundary."));
1504 addend
= fragP
->fr_offset
>> 2;
1508 /* Address we want to reach in file space. */
1509 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1510 target_address
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
1511 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1514 /* Create a relocation for symbols that must be resolved by the linker.
1515 Otherwise output the completed insn. */
1517 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1519 assert (fragP
->fr_subtype
!= 1);
1520 assert (fragP
->fr_cgen
.insn
!= 0);
1521 gas_cgen_record_fixup (fragP
,
1522 /* Offset of branch insn in frag. */
1523 fragP
->fr_fix
+ extension
- 4,
1524 fragP
->fr_cgen
.insn
,
1526 /* FIXME: quick hack */
1528 CGEN_OPERAND_ENTRY (fragP
->fr_cgen
.opindex
),
1530 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24
),
1532 fragP
->fr_cgen
.opinfo
,
1533 fragP
->fr_symbol
, fragP
->fr_offset
);
1536 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1538 md_number_to_chars (displacement
, (valueT
) addend
,
1539 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1541 fragP
->fr_fix
+= extension
;
1544 /* Functions concerning relocs. */
1546 /* The location from which a PC relative jump should be calculated,
1547 given a PC relative reloc. */
1550 md_pcrel_from_section (fixP
, sec
)
1554 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1555 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1556 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1558 /* The symbol is undefined (or is defined but not in this section).
1559 Let the linker figure it out. */
1563 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1566 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1567 Returns BFD_RELOC_NONE if no reloc type can be found.
1568 *FIXP may be modified if desired. */
1570 bfd_reloc_code_real_type
1571 md_cgen_lookup_reloc (insn
, operand
, fixP
)
1572 const CGEN_INSN
* insn
;
1573 const CGEN_OPERAND
* operand
;
1576 switch (CGEN_OPERAND_TYPE (operand
))
1578 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1579 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1580 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1581 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1582 case M32R_OPERAND_HI16
:
1583 case M32R_OPERAND_SLO16
:
1584 case M32R_OPERAND_ULO16
:
1585 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1586 if (fixP
->tc_fix_data
.opinfo
!= 0)
1587 return fixP
->tc_fix_data
.opinfo
;
1589 default : /* avoid -Wall warning */
1592 return BFD_RELOC_NONE
;
1595 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1598 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1603 struct m32r_hi_fixup
* hi_fixup
;
1605 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1606 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1608 hi_fixup
= ((struct m32r_hi_fixup
*)
1609 xmalloc (sizeof (struct m32r_hi_fixup
)));
1610 hi_fixup
->fixp
= fixP
;
1611 hi_fixup
->seg
= now_seg
;
1612 hi_fixup
->next
= m32r_hi_fixup_list
;
1614 m32r_hi_fixup_list
= hi_fixup
;
1617 /* Called while parsing an instruction to create a fixup.
1618 We need to check for HI16 relocs and queue them up for later sorting. */
1621 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1624 const CGEN_INSN
* insn
;
1626 const CGEN_OPERAND
* operand
;
1630 fixS
* fixP
= gas_cgen_record_fixup_exp (frag
, where
, insn
, length
,
1631 operand
, opinfo
, exp
);
1633 switch (CGEN_OPERAND_TYPE (operand
))
1635 case M32R_OPERAND_HI16
:
1636 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1637 if (fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1638 || fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1639 m32r_record_hi16 (fixP
->tc_fix_data
.opinfo
, fixP
, now_seg
);
1641 default : /* avoid -Wall warning */
1648 /* Return BFD reloc type from opinfo field in a fixS.
1649 It's tricky using fx_r_type in m32r_frob_file because the values
1650 are BFD_RELOC_UNUSED + operand number. */
1651 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1653 /* Sort any unmatched HI16 relocs so that they immediately precede
1654 the corresponding LO16 reloc. This is called before md_apply_fix and
1660 struct m32r_hi_fixup
* l
;
1662 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1664 segment_info_type
* seginfo
;
1667 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1668 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1670 /* Check quickly whether the next fixup happens to be a matching low. */
1671 if (l
->fixp
->fx_next
!= NULL
1672 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1673 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1674 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1677 /* Look through the fixups for this segment for a matching `low'.
1678 When we find one, move the high/shigh just in front of it. We do
1679 this in two passes. In the first pass, we try to find a
1680 unique `low'. In the second pass, we permit multiple high's
1681 relocs for a single `low'. */
1682 seginfo
= seg_info (l
->seg
);
1683 for (pass
= 0; pass
< 2; pass
++)
1689 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1691 /* Check whether this is a `low' fixup which matches l->fixp. */
1692 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
1693 && f
->fx_addsy
== l
->fixp
->fx_addsy
1694 && f
->fx_offset
== l
->fixp
->fx_offset
1697 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
1698 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
1699 || prev
->fx_addsy
!= f
->fx_addsy
1700 || prev
->fx_offset
!= f
->fx_offset
))
1704 /* Move l->fixp before f. */
1705 for (pf
= &seginfo
->fix_root
;
1707 pf
= & (* pf
)->fx_next
)
1708 assert (* pf
!= NULL
);
1710 * pf
= l
->fixp
->fx_next
;
1712 l
->fixp
->fx_next
= f
;
1714 seginfo
->fix_root
= l
->fixp
;
1716 prev
->fx_next
= l
->fixp
;
1728 && warn_unmatched_high
)
1729 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1730 _("Unmatched high/shigh reloc"));
1735 /* See whether we need to force a relocation into the output file.
1736 This is used to force out switch and PC relative relocations when
1740 m32r_force_relocation (fix
)
1746 return (fix
->fx_pcrel
1750 /* Write a value out to the object file, using the appropriate endianness. */
1753 md_number_to_chars (buf
, val
, n
)
1758 if (target_big_endian
)
1759 number_to_chars_bigendian (buf
, val
, n
);
1761 number_to_chars_littleendian (buf
, val
, n
);
1764 /* Turn a string in input_line_pointer into a floating point constant of type
1765 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1766 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1769 /* Equal to MAX_PRECISION in atof-ieee.c */
1770 #define MAX_LITTLENUMS 6
1773 md_atof (type
, litP
, sizeP
)
1780 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1782 char * atof_ieee ();
1800 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1804 return _("Bad call to md_atof()");
1807 t
= atof_ieee (input_line_pointer
, type
, words
);
1809 input_line_pointer
= t
;
1810 * sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1812 if (target_big_endian
)
1814 for (i
= 0; i
< prec
; i
++)
1816 md_number_to_chars (litP
, (valueT
) words
[i
],
1817 sizeof (LITTLENUM_TYPE
));
1818 litP
+= sizeof (LITTLENUM_TYPE
);
1823 for (i
= prec
- 1; i
>= 0; i
--)
1825 md_number_to_chars (litP
, (valueT
) words
[i
],
1826 sizeof (LITTLENUM_TYPE
));
1827 litP
+= sizeof (LITTLENUM_TYPE
);
1835 m32r_elf_section_change_hook ()
1837 /* If we have reached the end of a section and we have just emitted a
1838 16 bit insn, then emit a nop to make sure that the section ends on
1839 a 32 bit boundary. */
1841 if (prev_insn
.insn
|| seen_relaxable_p
)
1842 (void) m32r_fill_insn (0);