1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 const CGEN_INSN
* insn
;
32 cgen_insn_t buffer
[CGEN_MAX_INSN_SIZE
/ sizeof (cgen_insn_t
)];
34 char buffer
[CGEN_MAX_INSN_SIZE
];
41 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
42 boundary (i.e. was the first of two 16 bit insns). */
43 static m32r_insn prev_insn
;
45 /* Non-zero if we've seen a relaxable insn since the last 32 bit
47 static int seen_relaxable_p
= 0;
49 /* Non-zero if -relax specified, in which case sufficient relocs are output
50 for the linker to do relaxing.
51 We do simple forms of relaxing internally, but they are always done.
52 This flag does not apply to them. */
53 static int m32r_relax
;
55 /* If non-NULL, pointer to cpu description file to read.
56 This allows runtime additions to the assembler. */
57 static char * m32r_cpu_desc
;
59 /* start-sanitize-m32rx */
60 /* Non-zero if -m32rx has been specified, in which case support for the
61 extended M32RX instruction set should be enabled. */
62 static int enable_m32rx
= 0;
64 /* Non-zero if the programmer should be warned when an explicit parallel
65 instruction might have constraint violations. */
66 static int warn_explicit_parallel_conflicts
= 1;
67 /* end-sanitize-m32rx */
69 /* stuff for .scomm symbols. */
70 static segT sbss_section
;
71 static asection scom_section
;
72 static asymbol scom_symbol
;
74 const char comment_chars
[] = ";";
75 const char line_comment_chars
[] = "#";
76 const char line_separator_chars
[] = "";
77 const char EXP_CHARS
[] = "eE";
78 const char FLT_CHARS
[] = "dD";
80 /* Relocations against symbols are done in two
81 parts, with a HI relocation and a LO relocation. Each relocation
82 has only 16 bits of space to store an addend. This means that in
83 order for the linker to handle carries correctly, it must be able
84 to locate both the HI and the LO relocation. This means that the
85 relocations must appear in order in the relocation table.
87 In order to implement this, we keep track of each unmatched HI
88 relocation. We then sort them so that they immediately precede the
89 corresponding LO relocation. */
93 struct m32r_hi_fixup
* next
; /* Next HI fixup. */
94 fixS
* fixp
; /* This fixup. */
95 segT seg
; /* The section this fixup is in. */
99 /* The list of unmatched HI relocs. */
101 static struct m32r_hi_fixup
* m32r_hi_fixup_list
;
104 /* start-sanitize-m32rx */
111 if (stdoutput
!= NULL
)
112 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
113 enable_m32rx
? bfd_mach_m32rx
: bfd_mach_m32r
);
115 /* end-sanitize-m32rx */
117 const char * md_shortopts
= "";
119 struct option md_longopts
[] =
121 /* start-sanitize-m32rx */
122 #define OPTION_M32RX (OPTION_MD_BASE)
123 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
124 #define OPTION_WARN (OPTION_MD_BASE + 1)
125 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN
},
126 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
127 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN
},
128 /* end-sanitize-m32rx */
130 #if 0 /* not supported yet */
131 #define OPTION_RELAX (OPTION_MD_BASE + 3)
132 {"relax", no_argument
, NULL
, OPTION_RELAX
},
133 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
134 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
137 {NULL
, no_argument
, NULL
, 0}
139 size_t md_longopts_size
= sizeof (md_longopts
);
142 md_parse_option (c
, arg
)
148 /* start-sanitize-m32rx */
154 warn_explicit_parallel_conflicts
= 1;
158 warn_explicit_parallel_conflicts
= 0;
160 /* end-sanitize-m32rx */
162 #if 0 /* not supported yet */
166 case OPTION_CPU_DESC
:
177 md_show_usage (stream
)
180 fprintf (stream
, "M32R/X options:\n");
181 /* start-sanitize-m32rx */
183 --m32rx support the extended m32rx instruction set\n");
186 --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\
187 --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n");
188 /* end-sanitize-m32rx */
192 --relax create linker relaxable code\n");
194 --cpu-desc provide runtime cpu description file\n");
198 static void fill_insn
PARAMS ((int));
199 static void m32r_scomm
PARAMS ((int));
201 /* Set by md_assemble for use by m32r_fill_insn. */
202 static subsegT prev_subseg
;
203 static segT prev_seg
;
205 /* The target specific pseudo-ops which we support. */
206 const pseudo_typeS md_pseudo_table
[] =
209 { "fillinsn", fill_insn
, 0 },
210 { "scomm", m32r_scomm
, 0 },
211 /* start-sanitize-m32rx */
212 { "m32r", allow_m32rx
, 0},
213 { "m32rx", allow_m32rx
, 1},
214 /* end-sanitize-m32rx */
218 /* FIXME: Should be machine generated. */
219 #define NOP_INSN 0x7000
220 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
222 /* When we align the .text section, insert the correct NOP pattern.
223 N is the power of 2 alignment. LEN is the length of pattern FILL.
224 MAX is the maximum number of characters to skip when doing the alignment,
225 or 0 if there is no maximum. */
228 m32r_do_align (n
, fill
, len
, max
)
234 if ((fill
== NULL
|| (* fill
== 0 && len
== 1))
235 && (now_seg
->flags
& SEC_CODE
) != 0
236 /* Only do this special handling if aligning to at least a
239 /* Only do this special handling if we're allowed to emit at
241 && (max
== 0 || max
> 1))
243 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
246 /* First align to a 2 byte boundary, in case there is an odd .byte. */
247 /* FIXME: How much memory will cause gas to use when assembling a big
248 program? Perhaps we can avoid the frag_align call? */
249 frag_align (1, 0, 0);
251 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
253 frag_align_pattern (2, nop_pattern
, sizeof nop_pattern
, 0);
254 /* If doing larger alignments use a repeating sequence of appropriate
258 static const unsigned char multi_nop_pattern
[] =
259 { 0x70, 0x00, 0xf0, 0x00 };
260 frag_align_pattern (n
, multi_nop_pattern
, sizeof multi_nop_pattern
,
270 assemble_nop (opcode
)
273 char * f
= frag_more (2);
274 md_number_to_chars (f
, opcode
, 2);
277 /* If the last instruction was the first of 2 16 bit insns,
278 output a nop to move the PC to a 32 bit boundary.
280 This is done via an alignment specification since branch relaxing
281 may make it unnecessary.
283 Internally, we need to output one of these each time a 32 bit insn is
284 seen after an insn that is relaxable. */
290 (void) m32r_do_align (2, NULL
, 0, 0);
291 prev_insn
.insn
= NULL
;
292 seen_relaxable_p
= 0;
295 /* Cover function to fill_insn called after a label and at end of assembly.
297 The result is always 1: we're called in a conditional to see if the
298 current line is a label. */
301 m32r_fill_insn (done
)
307 if (prev_seg
!= NULL
)
312 subseg_set (prev_seg
, prev_subseg
);
316 subseg_set (seg
, subseg
);
329 /* Initialize the `cgen' interface. */
331 /* This is a callback from cgen to gas to parse operands. */
332 cgen_parse_operand_fn
= cgen_parse_operand
;
334 /* Set the machine number and endian. */
335 CGEN_SYM (init_asm
) (0 /* mach number */,
337 CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE
);
339 #if 0 /* not supported yet */
340 /* If a runtime cpu description file was provided, parse it. */
341 if (m32r_cpu_desc
!= NULL
)
345 errmsg
= cgen_read_cpu_file (m32r_cpu_desc
);
347 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
351 /* Save the current subseg so we can restore it [it's the default one and
352 we don't want the initial section to be .sbss]. */
356 /* The sbss section is for local .scomm symbols. */
357 sbss_section
= subseg_new (".sbss", 0);
359 /* This is copied from perform_an_assembly_pass. */
360 applicable
= bfd_applicable_section_flags (stdoutput
);
361 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
363 #if 0 /* What does this do? [see perform_an_assembly_pass] */
364 seg_info (bss_section
)->bss
= 1;
367 subseg_set (seg
, subseg
);
369 /* We must construct a fake section similar to bfd_com_section
370 but with the name .scommon. */
371 scom_section
= bfd_com_section
;
372 scom_section
.name
= ".scommon";
373 scom_section
.output_section
= & scom_section
;
374 scom_section
.symbol
= & scom_symbol
;
375 scom_section
.symbol_ptr_ptr
= & scom_section
.symbol
;
376 scom_symbol
= * bfd_com_section
.symbol
;
377 scom_symbol
.name
= ".scommon";
378 scom_symbol
.section
= & scom_section
;
380 /* start-sanitize-m32rx */
381 allow_m32rx (enable_m32rx
);
382 /* end-sanitize-m32rx */
385 /* start-sanitize-m32rx */
386 #ifdef HAVE_CPU_M32RX
388 /* Returns non zero if the given instruction writes to a destination register. */
390 writes_to_dest_reg (insn
)
391 const CGEN_INSN
* insn
;
393 unsigned char * syntax
= CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn
));
396 /* Scan the syntax string looking for a destination register. */
397 while ((c
= (* syntax
++)) != 0)
398 if (c
== 128 + M32R_OPERAND_DR
)
404 /* Returns non zero if the given instruction reads from a source register.
405 Ignores the first 'num_ignore' macthes in the syntax string. */
407 reads_from_src_reg (insn
, num_ignore
)
408 const CGEN_INSN
* insn
;
411 unsigned char * syntax
= CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn
));
414 /* Scan the syntax string looking for a source register. */
415 while ((c
= (* syntax
++)) != 0)
417 if ( c
== 128 + M32R_OPERAND_SR
418 || c
== 128 + M32R_OPERAND_SRC1
419 || c
== 128 + M32R_OPERAND_SRC2
)
421 if (num_ignore
-- > 0)
431 /* Returns the integer value of the destination register held in the fields. */
432 #define get_dest_reg(fields) (fields).f_r1
434 /* Returns an integer representing the source register of the given type. */
436 get_src_reg (syntax_field
, fields
)
437 unsigned char syntax_field
;
438 CGEN_FIELDS
* fields
;
440 switch (syntax_field
)
442 case 128 + M32R_OPERAND_SR
: return fields
->f_r2
;
443 /* Relies upon the fact that no instruction with a $src1 operand
444 also has a $dr operand. */
445 case 128 + M32R_OPERAND_SRC1
: return fields
->f_r1
;
446 case 128 + M32R_OPERAND_SRC2
: return fields
->f_r2
;
447 default: abort(); return -1;
451 /* Returns zero iff the output register of instruction 'a'
452 is an input register to instruction 'b'. */
454 check_parallel_io_clash (a
, b
)
458 if (writes_to_dest_reg (a
->insn
))
460 unsigned char syntax_field
;
463 while (syntax_field
= reads_from_src_reg (b
->insn
, skip
++))
465 if (get_src_reg (syntax_field
, & b
->fields
) == get_dest_reg (a
->fields
))
473 /* Returns non zero iff instruction 'a' has a side effect
474 that affects the destination of instruction 'b'. */
476 check_for_side_effects (a
, b
)
480 unsigned char syntax_field
;
482 if (CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_WRITE_SRC
) != WRITE_SRC_YES
)
485 if (! writes_to_dest_reg (b
->insn
))
488 /* Find the source register. */
489 syntax_field
= reads_from_src_reg (a
->insn
, 0);
491 /* The st-plus and st-minus instructions have two sources,
492 only the second one has a side effect. */
493 if (syntax_field
== 128 + M32R_OPERAND_SRC1
)
494 syntax_field
= reads_from_src_reg (a
->insn
, 1); /* We know that this will be src2 */
496 return get_dest_reg (b
->fields
) == get_src_reg (syntax_field
, & a
->fields
);
499 /* Returns NULL if the two 16 bit insns can be executed in parallel,
500 otherwise it returns a pointer to an error message explaining why not. */
502 can_make_parallel (a
, b
)
509 /* Make sure the instructions are the right length. */
510 if ( CGEN_FIELDS_BITSIZE (& a
->fields
) != 16
511 || CGEN_FIELDS_BITSIZE (& b
->fields
) != 16)
514 /* Make sure that the destinations are different. */
515 if ( writes_to_dest_reg (a
->insn
)
516 && writes_to_dest_reg (b
->insn
)
517 && (get_dest_reg (a
->fields
) == get_dest_reg (b
->fields
)))
518 return "Instructions write to the same destination register.";
520 /* Special case: Some instructions also modify their source register. */
521 if (check_for_side_effects (a
, b
))
522 return "Destination of second instruction written to by side effect of first instruction.";
524 if (check_for_side_effects (b
, a
))
525 return "Destination of first instruction written to by side effect of second instruction.";
527 /* Special case: The branch-and-link type instructions also write to r14. */
528 if (writes_to_dest_reg (b
->insn
)
529 && get_dest_reg (b
->fields
) == 14
530 && CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_WRITE_LR
) == WRITE_LR_YES
)
531 return "Both instructions write to the link register";
533 a_pipe
= CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_PIPE
);
534 b_pipe
= CGEN_INSN_ATTR (b
->insn
, CGEN_INSN_PIPE
);
536 /* Make sure that the instructions use the correct execution pipelines. */
537 if ( a_pipe
== PIPE_NONE
538 || b_pipe
== PIPE_NONE
)
539 return "Instructions do not use parallel execution pipelines.";
541 /* Leave this test for last, since it is the only test that can
542 go away if the instructions are swapped, and we want to make
543 sure that any other errors are detected before this happens. */
544 if ( a_pipe
== PIPE_S
546 return "Instructions share the same execution pipeline";
553 make_parallel (buffer
)
554 cgen_insn_t
* buffer
;
556 /* Force the top bit of the second insn to be set. */
560 if (CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
)
562 value
= bfd_getb16 ((bfd_byte
*) buffer
);
564 bfd_putb16 (value
, (char *) buffer
);
568 value
= bfd_getl16 ((bfd_byte
*) buffer
);
570 bfd_putl16 (value
, (char *) buffer
);
575 make_parallel (buffer
)
578 /* Force the top bit of the second insn to be set. */
580 buffer
[CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
? 0 : 1] |= 0x80;
586 assemble_parallel_insn (str
, str2
)
595 * str2
= 0; /* Seperate the two instructions. */
597 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
598 so that the parallel instruction will start on a 32 bit boundary. */
602 /* Parse the first instruction. */
603 if (! (first
.insn
= CGEN_SYM (assemble_insn
)
604 (str
, & first
.fields
, first
.buffer
, & errmsg
)))
610 /* Check to see if this is an allowable parallel insn. */
611 if (CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
613 as_bad ("instruction '%s' cannot be executed in parallel.", str
);
618 && CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
620 as_bad ("instruction '%s' is for the M32RX only", str
);
624 *str2
= '|'; /* Restore the original assembly text, just in case it is needed. */
625 str3
= str
; /* Save the original string pointer. */
626 str
= str2
+ 2; /* Advanced past the parsed string. */
627 str2
= str3
; /* Remember the entire string in case it is needed for error messages. */
629 /* Preserve any fixups that have been generated and reset the list to empty. */
632 /* Parse the second instruction. */
633 if (! (second
.insn
= CGEN_SYM (assemble_insn
)
634 (str
, & second
.fields
, second
.buffer
, & errmsg
)))
642 && CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
644 as_bad ("instruction '%s' is for the M32RX only", str
);
650 if ( strcmp (first
.insn
->name
, "nop") != 0
651 && strcmp (second
.insn
->name
, "nop") != 0)
653 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2
);
658 /* We assume that if the first instruction writes to a register that is
659 read by the second instruction it is because the programmer intended
660 this to happen, (after all they have explicitly requested that these
661 two instructions be executed in parallel). Although if the global
662 variable warn_explicit_parallel_conflicts is true then we do generate
663 a warning message. Similarly we assume that parallel branch and jump
664 instructions are deliberate and should not produce errors. */
666 if ((errmsg
= (char *) can_make_parallel (& first
, & second
)) == NULL
)
668 if (warn_explicit_parallel_conflicts
669 && (! check_parallel_io_clash (& first
, & second
)))
670 as_warn ("%s: output of first instruction is the same as the input of second instruction - is this intentional ?", str2
);
672 /* Get the fixups for the first instruction. */
676 (void) cgen_asm_finish_insn (first
.insn
, first
.buffer
,
677 CGEN_FIELDS_BITSIZE (& first
.fields
));
679 /* Force the top bit of the second insn to be set. */
680 make_parallel (second
.buffer
);
682 /* Get its fixups. */
683 cgen_restore_fixups ();
686 (void) cgen_asm_finish_insn (second
.insn
, second
.buffer
,
687 CGEN_FIELDS_BITSIZE (& second
.fields
));
689 /* Try swapping the instructions to see if they work that way. */
690 else if (can_make_parallel (& second
, & first
, false, false) == NULL
)
692 if (warn_explicit_parallel_conflicts
693 && (! check_parallel_io_clash (& second
, & first
)))
694 as_warn ("%s: had to swap instructions to make them parallel, but the output of the second instruction is the same as the input of first instruction - is this intentional ?", str2
);
696 /* Write out the second instruction first. */
697 (void) cgen_asm_finish_insn (second
.insn
, second
.buffer
,
698 CGEN_FIELDS_BITSIZE (& second
.fields
));
700 /* Force the top bit of the first instruction to be set. */
701 make_parallel (first
.buffer
);
703 /* Get the fixups for the first instruction. */
704 cgen_restore_fixups ();
706 /* Write out the first instruction. */
707 (void) cgen_asm_finish_insn (first
.insn
, first
.buffer
,
708 CGEN_FIELDS_BITSIZE (& first
.fields
));
712 as_bad ("'%s': %s", str2
, errmsg
);
716 /* Set these so m32r_fill_insn can use them. */
718 prev_subseg
= now_subseg
;
723 #endif /* HAVE_CPU_M32RX */
725 /* end-sanitize-m32rx */
736 /* Initialize GAS's cgen interface for a new instruction. */
737 cgen_asm_init_parse ();
739 /* start-sanitize-m32rx */
740 #ifdef HAVE_CPU_M32RX
741 /* Look for a parallel instruction seperator. */
742 if ((str2
= strstr (str
, "||")) != NULL
)
744 assemble_parallel_insn (str
, str2
);
748 /* end-sanitize-m32rx */
750 insn
.insn
= CGEN_SYM (assemble_insn
) (str
, & insn
.fields
, insn
.buffer
, & errmsg
);
757 /* start-sanitize-m32rx */
758 #ifdef HAVE_CPU_M32RX
759 if (! enable_m32rx
&& CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
761 as_bad ("instruction '%s' is for the M32RX only", str
);
765 /* end-sanitize-m32rx */
767 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
769 /* 32 bit insns must live on 32 bit boundaries. */
770 if (prev_insn
.insn
|| seen_relaxable_p
)
772 /* FIXME: If calling fill_insn too many times turns us into a memory
773 pig, can we call assemble_nop instead of !seen_relaxable_p? */
777 (void) cgen_asm_finish_insn (insn
.insn
, insn
.buffer
,
778 CGEN_FIELDS_BITSIZE (& insn
.fields
));
782 /* start-sanitize-m32rx */
783 /* start-sanitize-phase2-m32rx */
785 /* end-sanitize-phase2-m32rx */
786 /* end-sanitize-m32rx */
788 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
791 /* Keep track of whether we've seen a pair of 16 bit insns.
792 prev_insn.insn is NULL when we're on a 32 bit boundary. */
795 /* start-sanitize-m32rx */
796 /* start-sanitize-phase2-m32rx */
797 #ifdef HAVE_CPU_M32RX
798 /* Look to see if this instruction can be combined with the
799 previous instruction to make one, parallel, 32 bit instruction.
800 If the previous instruction (potentially) changed the flow of
801 program control, then it cannot be combined with the current
802 instruction. Also if the output of the previous instruction
803 is used as an input to the current instruction then it cannot
804 be combined. Otherwise call can_make_parallel() with both
805 orderings of the instructions to see if they can be combined. */
806 if ( ! CGEN_INSN_ATTR (prev_insn
.insn
, CGEN_INSN_COND_CTI
)
807 && ! CGEN_INSN_ATTR (prev_insn
.insn
, CGEN_INSN_UNCOND_CTI
)
808 && check_parallel_io_clash (& prev_insn
, &insn
)
811 if (can_make_parallel (& prev_insn
, & insn
) == NULL
)
812 make_parallel (insn
.buffer
);
813 else if (can_make_parallel (& insn
, & prev_insn
.insn
) == NULL
)
817 /* end-sanitize-phase2-m32rx */
818 /* end-sanitize-m32rx */
820 prev_insn
.insn
= NULL
;
827 /* Record the frag that might be used by this insn. */
828 insn
.frag
= frag_now
;
829 insn
.addr
= cgen_asm_finish_insn (insn
.insn
, insn
.buffer
,
830 CGEN_FIELDS_BITSIZE (& insn
.fields
));
832 /* start-sanitize-m32rx */
833 /* start-sanitize-phase2-m32rx */
834 #ifdef HAVE_CPU_M32RX
839 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
841 /* Swap the two insns */
842 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
843 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
845 make_parallel (insn
.addr
);
847 /* Swap any relaxable frags recorded for the two insns. */
848 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
850 prev_insn
.frag
->fr_opcode
= insn
.addr
;
852 else if (insn
.frag
->fr_opcode
== insn
.addr
)
854 insn
.frag
->fr_opcode
= prev_insn
.addr
;
857 /* end-sanitize-phase2-m32rx */
859 /* Record where this instruction was assembled. */
860 prev_insn
.addr
= insn
.addr
;
861 prev_insn
.frag
= insn
.frag
;
863 /* end-sanitize-m32rx */
865 /* If the insn needs the following one to be on a 32 bit boundary
866 (e.g. subroutine calls), fill this insn's slot. */
868 && CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_FILL_SLOT
) != 0)
871 /* If this is a relaxable insn (can be replaced with a larger version)
872 mark the fact so that we can emit an alignment directive for a
873 following 32 bit insn if we see one. */
874 if (CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_RELAXABLE
) != 0)
875 seen_relaxable_p
= 1;
878 /* Set these so m32r_fill_insn can use them. */
880 prev_subseg
= now_subseg
;
883 /* The syntax in the manual says constants begin with '#'.
884 We just ignore it. */
887 md_operand (expressionP
)
888 expressionS
* expressionP
;
890 if (* input_line_pointer
== '#')
892 input_line_pointer
++;
893 expression (expressionP
);
898 md_section_align (segment
, size
)
902 int align
= bfd_get_section_alignment (stdoutput
, segment
);
903 return ((size
+ (1 << align
) - 1) & (-1 << align
));
907 md_undefined_symbol (name
)
913 /* .scomm pseudo-op handler.
915 This is a new pseudo-op to handle putting objects in .scommon.
916 By doing this the linker won't need to do any work and more importantly
917 it removes the implicit -G arg necessary to correctly link the object file.
924 register char * name
;
928 register symbolS
* symbolP
;
932 name
= input_line_pointer
;
933 c
= get_symbol_end ();
935 /* just after name is now '\0' */
936 p
= input_line_pointer
;
939 if (* input_line_pointer
!= ',')
941 as_bad ("Expected comma after symbol-name: rest of line ignored.");
942 ignore_rest_of_line ();
946 input_line_pointer
++; /* skip ',' */
947 if ((size
= get_absolute_expression ()) < 0)
949 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size
);
950 ignore_rest_of_line ();
954 /* The third argument to .scomm is the alignment. */
955 if (* input_line_pointer
!= ',')
959 ++ input_line_pointer
;
960 align
= get_absolute_expression ();
963 as_warn ("ignoring bad alignment");
967 /* Convert to a power of 2 alignment. */
970 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++ align2
)
974 as_bad ("Common alignment not a power of 2");
975 ignore_rest_of_line ();
983 symbolP
= symbol_find_or_make (name
);
986 if (S_IS_DEFINED (symbolP
))
988 as_bad ("Ignoring attempt to re-define symbol `%s'.",
989 S_GET_NAME (symbolP
));
990 ignore_rest_of_line ();
994 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
996 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
997 S_GET_NAME (symbolP
),
998 (long) S_GET_VALUE (symbolP
),
1001 ignore_rest_of_line ();
1007 segT old_sec
= now_seg
;
1008 int old_subsec
= now_subseg
;
1011 record_alignment (sbss_section
, align2
);
1012 subseg_set (sbss_section
, 0);
1015 frag_align (align2
, 0, 0);
1017 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1018 symbolP
->sy_frag
->fr_symbol
= 0;
1020 symbolP
->sy_frag
= frag_now
;
1022 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1025 S_SET_SIZE (symbolP
, size
);
1026 S_SET_SEGMENT (symbolP
, sbss_section
);
1027 S_CLEAR_EXTERNAL (symbolP
);
1028 subseg_set (old_sec
, old_subsec
);
1032 S_SET_VALUE (symbolP
, (valueT
) size
);
1033 S_SET_ALIGN (symbolP
, align2
);
1034 S_SET_EXTERNAL (symbolP
);
1035 S_SET_SEGMENT (symbolP
, & scom_section
);
1038 demand_empty_rest_of_line ();
1041 /* Interface to relax_segment. */
1043 /* FIXME: Build table by hand, get it working, then machine generate. */
1045 const relax_typeS md_relax_table
[] =
1048 1) most positive reach of this state,
1049 2) most negative reach of this state,
1050 3) how many bytes this mode will add to the size of the current frag
1051 4) which index into the table to try if we can't fit into this one. */
1053 /* The first entry must be unused because an `rlx_more' value of zero ends
1057 /* The displacement used by GAS is from the end of the 2 byte insn,
1058 so we subtract 2 from the following. */
1059 /* 16 bit insn, 8 bit disp -> 10 bit range.
1060 This doesn't handle a branch in the right slot at the border:
1061 the "& -4" isn't taken into account. It's not important enough to
1062 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1064 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1065 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1066 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1067 /* Same thing, but with leading nop for alignment. */
1068 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1072 m32r_relax_frag (fragP
, stretch
)
1076 /* Address of branch insn. */
1077 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1080 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1081 if (fragP
->fr_subtype
== 2)
1083 if ((address
& 3) != 0)
1085 fragP
->fr_subtype
= 3;
1089 else if (fragP
->fr_subtype
== 3)
1091 if ((address
& 3) == 0)
1093 fragP
->fr_subtype
= 2;
1099 growth
= relax_frag (fragP
, stretch
);
1101 /* Long jump on odd halfword boundary? */
1102 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1104 fragP
->fr_subtype
= 3;
1112 /* Return an initial guess of the length by which a fragment must grow to
1113 hold a branch to reach its destination.
1114 Also updates fr_type/fr_subtype as necessary.
1116 Called just before doing relaxation.
1117 Any symbol that is now undefined will not become defined.
1118 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1119 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1120 Although it may not be explicit in the frag, pretend fr_var starts with a
1124 md_estimate_size_before_relax (fragP
, segment
)
1128 int old_fr_fix
= fragP
->fr_fix
;
1129 char * opcode
= fragP
->fr_opcode
;
1131 /* The only thing we have to handle here are symbols outside of the
1132 current segment. They may be undefined or in a different segment in
1133 which case linker scripts may place them anywhere.
1134 However, we can't finish the fragment here and emit the reloc as insn
1135 alignment requirements may move the insn about. */
1137 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1139 /* The symbol is undefined in this segment.
1140 Change the relaxation subtype to the max allowable and leave
1141 all further handling to md_convert_frag. */
1142 fragP
->fr_subtype
= 2;
1144 #if 0 /* Can't use this, but leave in for illustration. */
1145 /* Change 16 bit insn to 32 bit insn. */
1148 /* Increase known (fixed) size of fragment. */
1151 /* Create a relocation for it. */
1152 fix_new (fragP
, old_fr_fix
, 4,
1154 fragP
->fr_offset
, 1 /* pcrel */,
1155 /* FIXME: Can't use a real BFD reloc here.
1156 cgen_md_apply_fix3 can't handle it. */
1157 BFD_RELOC_M32R_26_PCREL
);
1159 /* Mark this fragment as finished. */
1163 const CGEN_INSN
* insn
;
1166 /* Update the recorded insn.
1167 Fortunately we don't have to look very far.
1168 FIXME: Change this to record in the instruction the next higher
1169 relaxable insn to use. */
1170 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1172 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1173 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1175 && CGEN_INSN_ATTR (insn
, CGEN_INSN_RELAX
))
1181 fragP
->fr_cgen
.insn
= insn
;
1187 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
1190 /* *fragP has been relaxed to its final size, and now needs to have
1191 the bytes inside it modified to conform to the new size.
1193 Called after relaxation is finished.
1194 fragP->fr_type == rs_machine_dependent.
1195 fragP->fr_subtype is the subtype of what the address relaxed to. */
1198 md_convert_frag (abfd
, sec
, fragP
)
1204 char * displacement
;
1210 opcode
= fragP
->fr_opcode
;
1212 /* Address opcode resides at in file space. */
1213 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1215 switch (fragP
->fr_subtype
)
1219 displacement
= & opcode
[1];
1224 displacement
= & opcode
[1];
1227 opcode
[2] = opcode
[0] | 0x80;
1228 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1229 opcode_address
+= 2;
1231 displacement
= & opcode
[3];
1237 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1239 /* symbol must be resolved by linker */
1240 if (fragP
->fr_offset
& 3)
1241 as_warn ("Addend to unresolved symbol not on word boundary.");
1242 addend
= fragP
->fr_offset
>> 2;
1246 /* Address we want to reach in file space. */
1247 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1248 target_address
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
1249 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1252 /* Create a relocation for symbols that must be resolved by the linker.
1253 Otherwise output the completed insn. */
1255 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1257 assert (fragP
->fr_subtype
!= 1);
1258 assert (fragP
->fr_cgen
.insn
!= 0);
1259 cgen_record_fixup (fragP
,
1260 /* Offset of branch insn in frag. */
1261 fragP
->fr_fix
+ extension
- 4,
1262 fragP
->fr_cgen
.insn
,
1264 /* FIXME: quick hack */
1266 CGEN_OPERAND_ENTRY (fragP
->fr_cgen
.opindex
),
1268 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24
),
1270 fragP
->fr_cgen
.opinfo
,
1271 fragP
->fr_symbol
, fragP
->fr_offset
);
1274 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1276 md_number_to_chars (displacement
, (valueT
) addend
,
1277 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1279 fragP
->fr_fix
+= extension
;
1282 /* Functions concerning relocs. */
1284 /* The location from which a PC relative jump should be calculated,
1285 given a PC relative reloc. */
1288 md_pcrel_from_section (fixP
, sec
)
1292 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1293 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1294 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1296 /* The symbol is undefined (or is defined but not in this section).
1297 Let the linker figure it out. */
1301 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1304 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1305 Returns BFD_RELOC_NONE if no reloc type can be found.
1306 *FIXP may be modified if desired. */
1308 bfd_reloc_code_real_type
1309 CGEN_SYM (lookup_reloc
) (insn
, operand
, fixP
)
1310 const CGEN_INSN
* insn
;
1311 const CGEN_OPERAND
* operand
;
1314 switch (CGEN_OPERAND_TYPE (operand
))
1316 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1317 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1318 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1319 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1320 case M32R_OPERAND_HI16
:
1321 case M32R_OPERAND_SLO16
:
1322 case M32R_OPERAND_ULO16
:
1323 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1324 if (fixP
->tc_fix_data
.opinfo
!= 0)
1325 return fixP
->tc_fix_data
.opinfo
;
1328 return BFD_RELOC_NONE
;
1331 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1334 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1339 struct m32r_hi_fixup
* hi_fixup
;
1341 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1342 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1344 hi_fixup
= ((struct m32r_hi_fixup
*)
1345 xmalloc (sizeof (struct m32r_hi_fixup
)));
1346 hi_fixup
->fixp
= fixP
;
1347 hi_fixup
->seg
= now_seg
;
1348 hi_fixup
->next
= m32r_hi_fixup_list
;
1350 m32r_hi_fixup_list
= hi_fixup
;
1353 /* Called while parsing an instruction to create a fixup.
1354 We need to check for HI16 relocs and queue them up for later sorting. */
1357 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1360 const CGEN_INSN
* insn
;
1362 const CGEN_OPERAND
* operand
;
1366 fixS
* fixP
= cgen_record_fixup_exp (frag
, where
, insn
, length
,
1367 operand
, opinfo
, exp
);
1369 switch (CGEN_OPERAND_TYPE (operand
))
1371 case M32R_OPERAND_HI16
:
1372 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1373 if (fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1374 || fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1375 m32r_record_hi16 (fixP
->tc_fix_data
.opinfo
, fixP
, now_seg
);
1382 /* Return BFD reloc type from opinfo field in a fixS.
1383 It's tricky using fx_r_type in m32r_frob_file because the values
1384 are BFD_RELOC_UNUSED + operand number. */
1385 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1387 /* Sort any unmatched HI16 relocs so that they immediately precede
1388 the corresponding LO16 reloc. This is called before md_apply_fix and
1394 struct m32r_hi_fixup
* l
;
1396 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1398 segment_info_type
* seginfo
;
1401 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1402 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1404 /* Check quickly whether the next fixup happens to be a matching low. */
1405 if (l
->fixp
->fx_next
!= NULL
1406 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1407 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1408 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1411 /* Look through the fixups for this segment for a matching `low'.
1412 When we find one, move the high/shigh just in front of it. We do
1413 this in two passes. In the first pass, we try to find a
1414 unique `low'. In the second pass, we permit multiple high's
1415 relocs for a single `low'. */
1416 seginfo
= seg_info (l
->seg
);
1417 for (pass
= 0; pass
< 2; pass
++)
1423 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1425 /* Check whether this is a `low' fixup which matches l->fixp. */
1426 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
1427 && f
->fx_addsy
== l
->fixp
->fx_addsy
1428 && f
->fx_offset
== l
->fixp
->fx_offset
1431 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
1432 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
1433 || prev
->fx_addsy
!= f
->fx_addsy
1434 || prev
->fx_offset
!= f
->fx_offset
))
1438 /* Move l->fixp before f. */
1439 for (pf
= &seginfo
->fix_root
;
1441 pf
= & (* pf
)->fx_next
)
1442 assert (* pf
!= NULL
);
1444 * pf
= l
->fixp
->fx_next
;
1446 l
->fixp
->fx_next
= f
;
1448 seginfo
->fix_root
= l
->fixp
;
1450 prev
->fx_next
= l
->fixp
;
1462 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1463 "Unmatched high/shigh reloc");
1468 /* See whether we need to force a relocation into the output file.
1469 This is used to force out switch and PC relative relocations when
1473 m32r_force_relocation (fix
)
1479 return (fix
->fx_pcrel
1483 /* Write a value out to the object file, using the appropriate endianness. */
1486 md_number_to_chars (buf
, val
, n
)
1491 if (target_big_endian
)
1492 number_to_chars_bigendian (buf
, val
, n
);
1494 number_to_chars_littleendian (buf
, val
, n
);
1497 /* Turn a string in input_line_pointer into a floating point constant of type
1498 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1499 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1502 /* Equal to MAX_PRECISION in atof-ieee.c */
1503 #define MAX_LITTLENUMS 6
1506 md_atof (type
, litP
, sizeP
)
1513 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1514 LITTLENUM_TYPE
* wordP
;
1516 char * atof_ieee ();
1534 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1538 return "Bad call to md_atof()";
1541 t
= atof_ieee (input_line_pointer
, type
, words
);
1543 input_line_pointer
= t
;
1544 * sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1546 if (target_big_endian
)
1548 for (i
= 0; i
< prec
; i
++)
1550 md_number_to_chars (litP
, (valueT
) words
[i
],
1551 sizeof (LITTLENUM_TYPE
));
1552 litP
+= sizeof (LITTLENUM_TYPE
);
1557 for (i
= prec
- 1; i
>= 0; i
--)
1559 md_number_to_chars (litP
, (valueT
) words
[i
],
1560 sizeof (LITTLENUM_TYPE
));
1561 litP
+= sizeof (LITTLENUM_TYPE
);