1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 /* Linked list of symbols that are debugging symbols to be defined as the
30 beginning of the current instruction. */
31 typedef struct sym_link
33 struct sym_link
*next
;
37 static sym_linkS
*debug_sym_link
= (sym_linkS
*)0;
39 /* Structure to hold all of the different components describing
40 an individual instruction. */
43 const CGEN_INSN
* insn
;
44 const CGEN_INSN
* orig_insn
;
47 cgen_insn_t buffer
[CGEN_MAX_INSN_SIZE
/ sizeof (cgen_insn_t
)];
49 char buffer
[CGEN_MAX_INSN_SIZE
];
54 fixS
* fixups
[CGEN_MAX_FIXUPS
];
55 int indices
[MAX_OPERAND_INSTANCES
];
56 sym_linkS
*debug_sym_link
;
60 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
61 boundary (i.e. was the first of two 16 bit insns). */
62 static m32r_insn prev_insn
;
64 /* Non-zero if we've seen a relaxable insn since the last 32 bit
66 static int seen_relaxable_p
= 0;
68 /* Non-zero if -relax specified, in which case sufficient relocs are output
69 for the linker to do relaxing.
70 We do simple forms of relaxing internally, but they are always done.
71 This flag does not apply to them. */
72 static int m32r_relax
;
74 /* If non-NULL, pointer to cpu description file to read.
75 This allows runtime additions to the assembler. */
76 static char * m32r_cpu_desc
;
78 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
79 Each high/shigh reloc must be paired with it's low cousin in order to
80 properly calculate the addend in a relocatable link (since there is a
81 potential carry from the low to the high/shigh).
82 This option is off by default though for user-written assembler code it
83 might make sense to make the default be on (i.e. have gcc pass a flag
84 to turn it off). This warning must not be on for GCC created code as
85 optimization may delete the low but not the high/shigh (at least we
86 shouldn't assume or require it to). */
87 static int warn_unmatched_high
= 0;
89 /* start-sanitize-m32rx */
90 /* Non-zero if --m32rx has been specified, in which case support for the
91 extended M32RX instruction set should be enabled. */
92 static int enable_m32rx
= 0;
94 /* Non-zero if --m32rx --hidden has been specified, in which case support for
95 the special M32RX instruction set should be enabled. */
96 static int enable_special
= 0;
98 /* Non-zero if the programmer should be warned when an explicit parallel
99 instruction might have constraint violations. */
100 static int warn_explicit_parallel_conflicts
= 1;
102 /* Non-zero if insns can be made parallel. */
104 /* end-sanitize-m32rx */
106 /* stuff for .scomm symbols. */
107 static segT sbss_section
;
108 static asection scom_section
;
109 static asymbol scom_symbol
;
111 const char comment_chars
[] = ";";
112 const char line_comment_chars
[] = "#";
113 const char line_separator_chars
[] = "";
114 const char EXP_CHARS
[] = "eE";
115 const char FLT_CHARS
[] = "dD";
117 /* Relocations against symbols are done in two
118 parts, with a HI relocation and a LO relocation. Each relocation
119 has only 16 bits of space to store an addend. This means that in
120 order for the linker to handle carries correctly, it must be able
121 to locate both the HI and the LO relocation. This means that the
122 relocations must appear in order in the relocation table.
124 In order to implement this, we keep track of each unmatched HI
125 relocation. We then sort them so that they immediately precede the
126 corresponding LO relocation. */
130 struct m32r_hi_fixup
* next
; /* Next HI fixup. */
131 fixS
* fixp
; /* This fixup. */
132 segT seg
; /* The section this fixup is in. */
136 /* The list of unmatched HI relocs. */
138 static struct m32r_hi_fixup
* m32r_hi_fixup_list
;
141 /* start-sanitize-m32rx */
148 if (stdoutput
!= NULL
)
149 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
150 enable_m32rx
? bfd_mach_m32rx
: bfd_mach_m32r
);
152 /* end-sanitize-m32rx */
154 #define M32R_SHORTOPTS ""
155 /* start-sanitize-m32rx */
156 #undef M32R_SHORTOPTS
157 #define M32R_SHORTOPTS "O"
158 /* end-sanitize-m32rx */
159 const char * md_shortopts
= M32R_SHORTOPTS
;
161 struct option md_longopts
[] =
163 /* start-sanitize-m32rx */
164 #define OPTION_M32RX (OPTION_MD_BASE)
165 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
166 #define OPTION_WARN_PARALLEL (OPTION_MD_BASE + 1)
167 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
168 {"Wp", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
169 #define OPTION_NO_WARN_PARALLEL (OPTION_MD_BASE + 2)
170 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
171 {"Wnp", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
172 #define OPTION_SPECIAL (OPTION_MD_BASE + 3)
173 {"hidden", no_argument
, NULL
, OPTION_SPECIAL
},
174 /* end-sanitize-m32rx */
176 /* Sigh. I guess all warnings must now have both variants. */
177 #define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4)
178 {"warn-unmatched-high", OPTION_WARN_UNMATCHED
},
179 {"Wuh", OPTION_WARN_UNMATCHED
},
180 #define OPTION_NO_WARN_UNMATCHED (OPTION_MD_BASE + 5)
181 {"no-warn-unmatched-high", OPTION_WARN_UNMATCHED
},
182 {"Wnuh", OPTION_WARN_UNMATCHED
},
184 #if 0 /* not supported yet */
185 #define OPTION_RELAX (OPTION_MD_BASE + 6)
186 {"relax", no_argument
, NULL
, OPTION_RELAX
},
187 #define OPTION_CPU_DESC (OPTION_MD_BASE + 7)
188 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
191 {NULL
, no_argument
, NULL
, 0}
193 size_t md_longopts_size
= sizeof (md_longopts
);
196 md_parse_option (c
, arg
)
202 /* start-sanitize-m32rx */
211 case OPTION_WARN_PARALLEL
:
212 warn_explicit_parallel_conflicts
= 1;
215 case OPTION_NO_WARN_PARALLEL
:
216 warn_explicit_parallel_conflicts
= 0;
224 extern char * myname
;
226 /* Pretend that we do not recognise this option. */
227 fprintf (stderr
, _("%s: unrecognised option: --hidden\n"), myname
);
231 /* end-sanitize-m32rx */
233 case OPTION_WARN_UNMATCHED
:
234 warn_unmatched_high
= 1;
237 case OPTION_NO_WARN_UNMATCHED
:
238 warn_unmatched_high
= 0;
241 #if 0 /* not supported yet */
245 case OPTION_CPU_DESC
:
257 md_show_usage (stream
)
260 fprintf (stream
, _("M32R specific command line options:\n"));
262 /* start-sanitize-m32rx */
263 fprintf (stream
, _("\
264 --m32rx support the extended m32rx instruction set\n"));
265 fprintf (stream
, _("\
266 -O try to combine instructions in parallel\n"));
268 fprintf (stream
, _("\
269 --warn-explicit-parallel-conflicts warn when parallel instrucitons violate contraints\n"));
270 fprintf (stream
, _("\
271 --no-warn-explicit-parallel-conflicts do not warn when parallel instrucitons violate contraints\n"));
272 fprintf (stream
, _("\
273 --Wp synonym for --warn-explicit-parallel-conflicts\n"));
274 fprintf (stream
, _("\
275 --Wnp synonym for --no-warn-explicit-parallel-conflicts\n"));
276 /* end-sanitize-m32rx */
278 fprintf (stream
, _("\
279 --warn-unmatched-high warn when a high or shigh reloc has no matching low reloc\n"));
280 fprintf (stream
, _("\
281 --no-warn-unmatched-high do not warn when a high or shigh reloc has no matching low reloc\n"));
282 fprintf (stream
, _("\
283 --Wuh synonym for --warn-unmatched-high\n"));
284 fprintf (stream
, _("\
285 --Wnuh synonym for --no-warn-unmatched-high\n"));
288 fprintf (stream
, _("\
289 --relax create linker relaxable code\n"));
290 fprintf (stream
, _("\
291 --cpu-desc provide runtime cpu description file\n"));
295 static void fill_insn
PARAMS ((int));
296 static void m32r_scomm
PARAMS ((int));
297 static void debug_sym
PARAMS ((int));
298 static void expand_debug_syms
PARAMS ((sym_linkS
*, int));
300 /* Set by md_assemble for use by m32r_fill_insn. */
301 static subsegT prev_subseg
;
302 static segT prev_seg
;
304 /* The target specific pseudo-ops which we support. */
305 const pseudo_typeS md_pseudo_table
[] =
308 { "fillinsn", fill_insn
, 0 },
309 { "scomm", m32r_scomm
, 0 },
310 { "debugsym", debug_sym
, 0 },
311 /* start-sanitize-m32rx */
312 { "m32r", allow_m32rx
, 0 },
313 { "m32rx", allow_m32rx
, 1 },
314 /* end-sanitize-m32rx */
318 /* FIXME: Should be machine generated. */
319 #define NOP_INSN 0x7000
320 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
322 /* When we align the .text section, insert the correct NOP pattern.
323 N is the power of 2 alignment. LEN is the length of pattern FILL.
324 MAX is the maximum number of characters to skip when doing the alignment,
325 or 0 if there is no maximum. */
328 m32r_do_align (n
, fill
, len
, max
)
334 /* Only do this if the fill pattern wasn't specified. */
336 && (now_seg
->flags
& SEC_CODE
) != 0
337 /* Only do this special handling if aligning to at least a
340 /* Only do this special handling if we're allowed to emit at
342 && (max
== 0 || max
> 1))
344 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
347 /* First align to a 2 byte boundary, in case there is an odd .byte. */
348 /* FIXME: How much memory will cause gas to use when assembling a big
349 program? Perhaps we can avoid the frag_align call? */
350 frag_align (1, 0, 0);
352 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
354 frag_align_pattern (2, nop_pattern
, sizeof nop_pattern
, 0);
355 /* If doing larger alignments use a repeating sequence of appropriate
359 static const unsigned char multi_nop_pattern
[] =
360 { 0x70, 0x00, 0xf0, 0x00 };
361 frag_align_pattern (n
, multi_nop_pattern
, sizeof multi_nop_pattern
,
371 assemble_nop (opcode
)
374 char * f
= frag_more (2);
375 md_number_to_chars (f
, opcode
, 2);
378 /* If the last instruction was the first of 2 16 bit insns,
379 output a nop to move the PC to a 32 bit boundary.
381 This is done via an alignment specification since branch relaxing
382 may make it unnecessary.
384 Internally, we need to output one of these each time a 32 bit insn is
385 seen after an insn that is relaxable. */
391 (void) m32r_do_align (2, NULL
, 0, 0);
392 prev_insn
.insn
= NULL
;
393 seen_relaxable_p
= 0;
396 /* Record the symbol so that when we output the insn, we can create
397 a symbol that is at the start of the instruction. This is used
398 to emit the label for the start of a breakpoint without causing
399 the assembler to emit a NOP if the previous instruction was a
400 16 bit instruction. */
408 register char *end_name
;
409 register symbolS
*symbolP
;
410 register sym_linkS
*link
;
412 name
= input_line_pointer
;
413 delim
= get_symbol_end ();
414 end_name
= input_line_pointer
;
416 if ((symbolP
= symbol_find (name
)) == NULL
417 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
419 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
422 symbol_table_insert (symbolP
);
423 if (S_IS_DEFINED (symbolP
) && S_GET_SEGMENT (symbolP
) != reg_section
)
424 /* xgettext:c-format */
425 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
429 link
= (sym_linkS
*) xmalloc (sizeof (sym_linkS
));
430 link
->symbol
= symbolP
;
431 link
->next
= debug_sym_link
;
432 debug_sym_link
= link
;
437 demand_empty_rest_of_line ();
440 /* Second pass to expanding the debug symbols, go through linked
441 list of symbols and reassign the address. */
444 expand_debug_syms (syms
, align
)
448 char *save_input_line
= input_line_pointer
;
449 sym_linkS
*next_syms
;
455 (void) m32r_do_align (align
, NULL
, 0, 0);
456 for (; syms
!= (sym_linkS
*)0; syms
= next_syms
)
458 symbolS
*symbolP
= syms
->symbol
;
459 next_syms
= syms
->next
;
460 input_line_pointer
= ".\n";
461 pseudo_set (symbolP
);
465 input_line_pointer
= save_input_line
;
468 /* Cover function to fill_insn called after a label and at end of assembly.
469 The result is always 1: we're called in a conditional to see if the
470 current line is a label. */
473 m32r_fill_insn (done
)
476 if (prev_seg
!= NULL
)
479 subsegT subseg
= now_subseg
;
481 subseg_set (prev_seg
, prev_subseg
);
485 subseg_set (seg
, subseg
);
488 if (done
&& debug_sym_link
)
490 expand_debug_syms (debug_sym_link
, 1);
491 debug_sym_link
= (sym_linkS
*)0;
504 /* Initialize the `cgen' interface. */
506 /* This is a callback from cgen to gas to parse operands. */
507 cgen_parse_operand_fn
= cgen_parse_operand
;
509 /* Set the machine number and endian. */
510 CGEN_SYM (init_asm
) (0 /* mach number */,
512 CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE
);
514 #if 0 /* not supported yet */
515 /* If a runtime cpu description file was provided, parse it. */
516 if (m32r_cpu_desc
!= NULL
)
520 errmsg
= cgen_read_cpu_file (m32r_cpu_desc
);
522 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
526 /* Save the current subseg so we can restore it [it's the default one and
527 we don't want the initial section to be .sbss]. */
531 /* The sbss section is for local .scomm symbols. */
532 sbss_section
= subseg_new (".sbss", 0);
534 /* This is copied from perform_an_assembly_pass. */
535 applicable
= bfd_applicable_section_flags (stdoutput
);
536 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
538 #if 0 /* What does this do? [see perform_an_assembly_pass] */
539 seg_info (bss_section
)->bss
= 1;
542 subseg_set (seg
, subseg
);
544 /* We must construct a fake section similar to bfd_com_section
545 but with the name .scommon. */
546 scom_section
= bfd_com_section
;
547 scom_section
.name
= ".scommon";
548 scom_section
.output_section
= & scom_section
;
549 scom_section
.symbol
= & scom_symbol
;
550 scom_section
.symbol_ptr_ptr
= & scom_section
.symbol
;
551 scom_symbol
= * bfd_com_section
.symbol
;
552 scom_symbol
.name
= ".scommon";
553 scom_symbol
.section
= & scom_section
;
555 /* start-sanitize-m32rx */
556 allow_m32rx (enable_m32rx
);
557 /* end-sanitize-m32rx */
560 /* start-sanitize-m32rx */
562 #define OPERAND_IS_COND_BIT(operand, indices, index) \
563 (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \
564 || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \
565 && (indices [index] == 0 || indices [index] == 1)))
567 /* Returns true if an output of instruction 'a' is referenced by an operand
568 of instruction 'b'. If 'check_outputs' is true then b's outputs are
569 checked, otherwise its inputs are examined. */
572 first_writes_to_seconds_operands (a
, b
, check_outputs
)
575 const int check_outputs
;
577 const CGEN_OPERAND_INSTANCE
* a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
578 const CGEN_OPERAND_INSTANCE
* b_ops
= CGEN_INSN_OPERANDS (b
->insn
);
581 /* If at least one of the instructions takes no operands, then there is
582 nothing to check. There really are instructions without operands,
584 if (a_operands
== NULL
|| b_ops
== NULL
)
587 /* Scan the operand list of 'a' looking for an output operand. */
589 CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
;
590 a_index
++, a_operands
++)
592 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) == CGEN_OPERAND_INSTANCE_OUTPUT
)
595 const CGEN_OPERAND_INSTANCE
* b_operands
= b_ops
;
598 The Condition bit 'C' is a shadow of the CBR register (control
599 register 1) and also a shadow of bit 31 of the program status
600 word (control register 0). For now this is handled here, rather
603 if (OPERAND_IS_COND_BIT (a_operands
, a
->indices
, a_index
))
605 /* Scan operand list of 'b' looking for another reference to the
606 condition bit, which goes in the right direction. */
608 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
609 b_index
++, b_operands
++)
611 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
612 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
613 && OPERAND_IS_COND_BIT (b_operands
, b
->indices
, b_index
))
619 /* Scan operand list of 'b' looking for an operand that
620 references the same hardware element, and which goes in the
623 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
624 b_index
++, b_operands
++)
626 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
627 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
628 && (CGEN_OPERAND_INSTANCE_HW (b_operands
) == CGEN_OPERAND_INSTANCE_HW (a_operands
))
629 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
639 /* Returns true if the insn can (potentially) alter the program counter. */
645 #if 0 /* Once PC operands are working.... */
646 const CGEN_OPERAND_INSTANCE
* a_operands
== CGEN_INSN_OPERANDS (a
->insn
);
648 if (a_operands
== NULL
)
651 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
)
653 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
) != NULL
654 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
)) == M32R_OPERAND_PC
)
660 if (CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_UNCOND_CTI
)
661 || CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_COND_CTI
))
667 /* Returns NULL if the two 16 bit insns can be executed in parallel,
668 otherwise it returns a pointer to an error message explaining why not. */
671 can_make_parallel (a
, b
)
678 /* Make sure the instructions are the right length. */
679 if ( CGEN_FIELDS_BITSIZE (& a
->fields
) != 16
680 || CGEN_FIELDS_BITSIZE (& b
->fields
) != 16)
683 if (first_writes_to_seconds_operands (a
, b
, true))
684 return _("Instructions write to the same destination register.");
686 a_pipe
= CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_PIPE
);
687 b_pipe
= CGEN_INSN_ATTR (b
->insn
, CGEN_INSN_PIPE
);
689 /* Make sure that the instructions use the correct execution pipelines. */
690 if ( a_pipe
== PIPE_NONE
691 || b_pipe
== PIPE_NONE
)
692 return _("Instructions do not use parallel execution pipelines.");
694 /* Leave this test for last, since it is the only test that can
695 go away if the instructions are swapped, and we want to make
696 sure that any other errors are detected before this happens. */
697 if ( a_pipe
== PIPE_S
699 return _("Instructions share the same execution pipeline");
707 make_parallel (buffer
)
708 cgen_insn_t
* buffer
;
710 /* Force the top bit of the second insn to be set. */
714 if (CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
)
716 value
= bfd_getb16 ((bfd_byte
*) buffer
);
718 bfd_putb16 (value
, (char *) buffer
);
722 value
= bfd_getl16 ((bfd_byte
*) buffer
);
724 bfd_putl16 (value
, (char *) buffer
);
731 make_parallel (buffer
)
734 /* Force the top bit of the second insn to be set. */
736 buffer
[CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
? 0 : 1] |= 0x80;
739 #endif /* ! CGEN_INT_INSN */
742 assemble_parallel_insn (str
, str2
)
751 * str2
= 0; /* Seperate the two instructions. */
753 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
754 so that the parallel instruction will start on a 32 bit boundary. */
758 first
.debug_sym_link
= debug_sym_link
;
759 debug_sym_link
= (sym_linkS
*)0;
761 /* Parse the first instruction. */
762 if (! (first
.insn
= CGEN_SYM (assemble_insn
)
763 (str
, & first
.fields
, first
.buffer
, & errmsg
)))
770 && CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_SPECIAL
))
772 /* xgettext:c-format */
773 as_bad (_("unknown instruction '%s'"), str
);
776 else if (! enable_m32rx
777 /* FIXME: Need standard macro to perform this test. */
778 && CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
780 /* xgettext:c-format */
781 as_bad (_("instruction '%s' is for the M32RX only"), str
);
785 /* Check to see if this is an allowable parallel insn. */
786 if (CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
788 /* xgettext:c-format */
789 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
793 *str2
= '|'; /* Restore the original assembly text, just in case it is needed. */
794 str3
= str
; /* Save the original string pointer. */
795 str
= str2
+ 2; /* Advanced past the parsed string. */
796 str2
= str3
; /* Remember the entire string in case it is needed for error messages. */
798 /* Preserve any fixups that have been generated and reset the list to empty. */
801 /* Get the indices of the operands of the instruction. */
802 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
803 doesn't seem right. Perhaps allow passing fields like we do insn. */
804 /* FIXME: ALIAS insns do not have operands, so we use this function
805 to find the equivalent insn and overwrite the value stored in our
806 structure. We still need the original insn, however, since this
807 may have certain attributes that are not present in the unaliased
808 version (eg relaxability). When aliases behave differently this
809 may have to change. */
810 first
.orig_insn
= first
.insn
;
811 first
.insn
= m32r_cgen_lookup_get_insn_operands
812 (NULL
, bfd_getb16 ((char *) first
.buffer
), 16, first
.indices
);
814 if (first
.insn
== NULL
)
815 as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for first insn"));
817 second
.debug_sym_link
= NULL
;
819 /* Parse the second instruction. */
820 if (! (second
.insn
= CGEN_SYM (assemble_insn
)
821 (str
, & second
.fields
, second
.buffer
, & errmsg
)))
829 && CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_SPECIAL
))
831 /* xgettext:c-format */
832 as_bad (_("unknown instruction '%s'"), str
);
835 else if (! enable_m32rx
836 && CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
838 /* xgettext:c-format */
839 as_bad (_("instruction '%s' is for the M32RX only"), str
);
843 /* Check to see if this is an allowable parallel insn. */
844 if (CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
846 /* xgettext:c-format */
847 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
853 if (CGEN_INSN_NUM (first
.insn
) != M32R_INSN_NOP
854 && CGEN_INSN_NUM (second
.insn
) != M32R_INSN_NOP
)
856 /* xgettext:c-format */
857 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2
);
862 /* Get the indices of the operands of the instruction. */
863 second
.orig_insn
= second
.insn
;
864 second
.insn
= m32r_cgen_lookup_get_insn_operands
865 (NULL
, bfd_getb16 ((char *) second
.buffer
), 16, second
.indices
);
867 if (second
.insn
== NULL
)
868 as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for second insn"));
870 /* We assume that if the first instruction writes to a register that is
871 read by the second instruction it is because the programmer intended
872 this to happen, (after all they have explicitly requested that these
873 two instructions be executed in parallel). Although if the global
874 variable warn_explicit_parallel_conflicts is true then we do generate
875 a warning message. Similarly we assume that parallel branch and jump
876 instructions are deliberate and should not produce errors. */
878 if (warn_explicit_parallel_conflicts
)
880 if (first_writes_to_seconds_operands (& first
, & second
, false))
881 /* xgettext:c-format */
882 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2
);
884 if (first_writes_to_seconds_operands (& second
, & first
, false))
885 /* xgettext:c-format */
886 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2
);
889 if ((errmsg
= (char *) can_make_parallel (& first
, & second
)) == NULL
)
891 /* Get the fixups for the first instruction. */
895 expand_debug_syms (first
.debug_sym_link
, 1);
896 cgen_asm_finish_insn (first
.orig_insn
, first
.buffer
,
897 CGEN_FIELDS_BITSIZE (& first
.fields
), 0, NULL
);
899 /* Force the top bit of the second insn to be set. */
900 make_parallel (second
.buffer
);
902 /* Get its fixups. */
903 cgen_restore_fixups ();
906 expand_debug_syms (second
.debug_sym_link
, 1);
907 cgen_asm_finish_insn (second
.orig_insn
, second
.buffer
,
908 CGEN_FIELDS_BITSIZE (& second
.fields
), 0, NULL
);
910 /* Try swapping the instructions to see if they work that way. */
911 else if (can_make_parallel (& second
, & first
) == NULL
)
913 /* Write out the second instruction first. */
914 expand_debug_syms (second
.debug_sym_link
, 1);
915 cgen_asm_finish_insn (second
.orig_insn
, second
.buffer
,
916 CGEN_FIELDS_BITSIZE (& second
.fields
), 0, NULL
);
918 /* Force the top bit of the first instruction to be set. */
919 make_parallel (first
.buffer
);
921 /* Get the fixups for the first instruction. */
922 cgen_restore_fixups ();
924 /* Write out the first instruction. */
925 expand_debug_syms (first
.debug_sym_link
, 1);
926 cgen_asm_finish_insn (first
.orig_insn
, first
.buffer
,
927 CGEN_FIELDS_BITSIZE (& first
.fields
), 0, NULL
);
931 as_bad ("'%s': %s", str2
, errmsg
);
935 /* Set these so m32r_fill_insn can use them. */
937 prev_subseg
= now_subseg
;
940 /* end-sanitize-m32rx */
951 /* Initialize GAS's cgen interface for a new instruction. */
952 cgen_asm_init_parse ();
954 /* start-sanitize-m32rx */
955 /* Look for a parallel instruction seperator. */
956 if ((str2
= strstr (str
, "||")) != NULL
)
958 assemble_parallel_insn (str
, str2
);
961 /* end-sanitize-m32rx */
963 insn
.debug_sym_link
= debug_sym_link
;
964 debug_sym_link
= (sym_linkS
*)0;
966 insn
.insn
= CGEN_SYM (assemble_insn
)
967 (str
, & insn
.fields
, insn
.buffer
, & errmsg
);
975 /* start-sanitize-m32rx */
977 && CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_SPECIAL
))
979 /* xgettext:c-format */
980 as_bad (_("unknown instruction '%s'"), str
);
983 else if (! enable_m32rx
984 && CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
986 /* xgettext:c-format */
987 as_bad (_("instruction '%s' is for the M32RX only"), str
);
990 /* end-sanitize-m32rx */
992 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
994 /* 32 bit insns must live on 32 bit boundaries. */
995 if (prev_insn
.insn
|| seen_relaxable_p
)
997 /* ??? If calling fill_insn too many times turns us into a memory
998 pig, can we call assemble_nop instead of !seen_relaxable_p? */
1002 expand_debug_syms (insn
.debug_sym_link
, 2);
1004 /* Doesn't really matter what we pass for RELAX_P here. */
1005 cgen_asm_finish_insn (insn
.insn
, insn
.buffer
,
1006 CGEN_FIELDS_BITSIZE (& insn
.fields
), 1, NULL
);
1010 int on_32bit_boundary_p
;
1011 /* start-sanitize-m32rx */
1013 /* end-sanitize-m32rx */
1015 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
1018 insn
.orig_insn
= insn
.insn
;
1019 /* start-sanitize-m32rx */
1022 /* Get the indices of the operands of the instruction.
1023 FIXME: See assemble_parallel for notes on orig_insn. */
1024 insn
.insn
= m32r_cgen_lookup_get_insn_operands
1025 (NULL
, bfd_getb16 ((char *) insn
.buffer
), 16, insn
.indices
);
1027 if (insn
.insn
== NULL
)
1028 as_fatal (_("internal error: m32r_cgen_get_insn_operands failed"));
1030 /* end-sanitize-m32rx */
1032 /* Compute whether we're on a 32 bit boundary or not.
1033 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1034 on_32bit_boundary_p
= prev_insn
.insn
== NULL
;
1036 /* start-sanitize-m32rx */
1037 /* Look to see if this instruction can be combined with the
1038 previous instruction to make one, parallel, 32 bit instruction.
1039 If the previous instruction (potentially) changed the flow of
1040 program control, then it cannot be combined with the current
1041 instruction. If the current instruction is relaxable, then it
1042 might be replaced with a longer version, so we cannot combine it.
1043 Also if the output of the previous instruction is used as an
1044 input to the current instruction then it cannot be combined.
1045 Otherwise call can_make_parallel() with both orderings of the
1046 instructions to see if they can be combined. */
1047 if ( ! on_32bit_boundary_p
1050 && CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) == 0
1051 && ! writes_to_pc (& prev_insn
)
1052 && ! first_writes_to_seconds_operands (& prev_insn
, &insn
, false)
1055 if (can_make_parallel (& prev_insn
, & insn
) == NULL
)
1056 make_parallel (insn
.buffer
);
1057 else if (can_make_parallel (& insn
, & prev_insn
) == NULL
)
1060 /* end-sanitize-m32rx */
1062 expand_debug_syms (insn
.debug_sym_link
, 1);
1068 /* Ensure each pair of 16 bit insns is in the same frag. */
1071 cgen_asm_finish_insn (insn
.orig_insn
, insn
.buffer
,
1072 CGEN_FIELDS_BITSIZE (& insn
.fields
),
1073 1 /*relax_p*/, &fi
);
1074 insn
.addr
= fi
.addr
;
1075 insn
.frag
= fi
.frag
;
1076 insn
.num_fixups
= fi
.num_fixups
;
1077 for (i
= 0; i
< fi
.num_fixups
; ++i
)
1078 insn
.fixups
[i
] = fi
.fixups
[i
];
1081 /* start-sanitize-m32rx */
1086 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1088 /* Swap the two insns */
1089 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
1090 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
1092 make_parallel (insn
.addr
);
1094 /* Swap any relaxable frags recorded for the two insns. */
1095 /* FIXME: Clarify. relaxation precludes parallel insns */
1096 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
1097 prev_insn
.frag
->fr_opcode
= insn
.addr
;
1098 else if (insn
.frag
->fr_opcode
== insn
.addr
)
1099 insn
.frag
->fr_opcode
= prev_insn
.addr
;
1101 /* Update the addresses in any fixups.
1102 Note that we don't have to handle the case where each insn is in
1103 a different frag as we ensure they're in the same frag above. */
1104 for (i
= 0; i
< prev_insn
.num_fixups
; ++i
)
1105 prev_insn
.fixups
[i
]->fx_where
+= 2;
1106 for (i
= 0; i
< insn
.num_fixups
; ++i
)
1107 insn
.fixups
[i
]->fx_where
-= 2;
1109 /* end-sanitize-m32rx */
1111 /* Keep track of whether we've seen a pair of 16 bit insns.
1112 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1113 if (on_32bit_boundary_p
)
1116 prev_insn
.insn
= NULL
;
1118 /* If the insn needs the following one to be on a 32 bit boundary
1119 (e.g. subroutine calls), fill this insn's slot. */
1120 if (on_32bit_boundary_p
1121 && CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_FILL_SLOT
) != 0)
1124 /* If this is a relaxable insn (can be replaced with a larger version)
1125 mark the fact so that we can emit an alignment directive for a
1126 following 32 bit insn if we see one. */
1127 if (CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) != 0)
1128 seen_relaxable_p
= 1;
1131 /* Set these so m32r_fill_insn can use them. */
1133 prev_subseg
= now_subseg
;
1136 /* The syntax in the manual says constants begin with '#'.
1137 We just ignore it. */
1140 md_operand (expressionP
)
1141 expressionS
* expressionP
;
1143 if (* input_line_pointer
== '#')
1145 input_line_pointer
++;
1146 expression (expressionP
);
1151 md_section_align (segment
, size
)
1155 int align
= bfd_get_section_alignment (stdoutput
, segment
);
1156 return ((size
+ (1 << align
) - 1) & (-1 << align
));
1160 md_undefined_symbol (name
)
1166 /* .scomm pseudo-op handler.
1168 This is a new pseudo-op to handle putting objects in .scommon.
1169 By doing this the linker won't need to do any work and more importantly
1170 it removes the implicit -G arg necessary to correctly link the object file.
1177 register char * name
;
1181 register symbolS
* symbolP
;
1185 name
= input_line_pointer
;
1186 c
= get_symbol_end ();
1188 /* just after name is now '\0' */
1189 p
= input_line_pointer
;
1192 if (* input_line_pointer
!= ',')
1194 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1195 ignore_rest_of_line ();
1199 input_line_pointer
++; /* skip ',' */
1200 if ((size
= get_absolute_expression ()) < 0)
1202 /* xgettext:c-format */
1203 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size
);
1204 ignore_rest_of_line ();
1208 /* The third argument to .scomm is the alignment. */
1209 if (* input_line_pointer
!= ',')
1213 ++ input_line_pointer
;
1214 align
= get_absolute_expression ();
1217 as_warn (_("ignoring bad alignment"));
1221 /* Convert to a power of 2 alignment. */
1224 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++ align2
)
1228 as_bad (_("Common alignment not a power of 2"));
1229 ignore_rest_of_line ();
1237 symbolP
= symbol_find_or_make (name
);
1240 if (S_IS_DEFINED (symbolP
))
1242 /* xgettext:c-format */
1243 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1244 S_GET_NAME (symbolP
));
1245 ignore_rest_of_line ();
1249 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
1251 /* xgettext:c-format */
1252 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1253 S_GET_NAME (symbolP
),
1254 (long) S_GET_VALUE (symbolP
),
1257 ignore_rest_of_line ();
1263 segT old_sec
= now_seg
;
1264 int old_subsec
= now_subseg
;
1267 record_alignment (sbss_section
, align2
);
1268 subseg_set (sbss_section
, 0);
1271 frag_align (align2
, 0, 0);
1273 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1274 symbolP
->sy_frag
->fr_symbol
= 0;
1276 symbolP
->sy_frag
= frag_now
;
1278 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1281 S_SET_SIZE (symbolP
, size
);
1282 S_SET_SEGMENT (symbolP
, sbss_section
);
1283 S_CLEAR_EXTERNAL (symbolP
);
1284 subseg_set (old_sec
, old_subsec
);
1288 S_SET_VALUE (symbolP
, (valueT
) size
);
1289 S_SET_ALIGN (symbolP
, align2
);
1290 S_SET_EXTERNAL (symbolP
);
1291 S_SET_SEGMENT (symbolP
, & scom_section
);
1294 demand_empty_rest_of_line ();
1297 /* Interface to relax_segment. */
1299 /* FIXME: Build table by hand, get it working, then machine generate. */
1301 const relax_typeS md_relax_table
[] =
1304 1) most positive reach of this state,
1305 2) most negative reach of this state,
1306 3) how many bytes this mode will add to the size of the current frag
1307 4) which index into the table to try if we can't fit into this one. */
1309 /* The first entry must be unused because an `rlx_more' value of zero ends
1313 /* The displacement used by GAS is from the end of the 2 byte insn,
1314 so we subtract 2 from the following. */
1315 /* 16 bit insn, 8 bit disp -> 10 bit range.
1316 This doesn't handle a branch in the right slot at the border:
1317 the "& -4" isn't taken into account. It's not important enough to
1318 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1320 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1321 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1322 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1323 /* Same thing, but with leading nop for alignment. */
1324 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1328 m32r_relax_frag (fragP
, stretch
)
1332 /* Address of branch insn. */
1333 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1336 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1337 if (fragP
->fr_subtype
== 2)
1339 if ((address
& 3) != 0)
1341 fragP
->fr_subtype
= 3;
1345 else if (fragP
->fr_subtype
== 3)
1347 if ((address
& 3) == 0)
1349 fragP
->fr_subtype
= 2;
1355 growth
= relax_frag (fragP
, stretch
);
1357 /* Long jump on odd halfword boundary? */
1358 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1360 fragP
->fr_subtype
= 3;
1368 /* Return an initial guess of the length by which a fragment must grow to
1369 hold a branch to reach its destination.
1370 Also updates fr_type/fr_subtype as necessary.
1372 Called just before doing relaxation.
1373 Any symbol that is now undefined will not become defined.
1374 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1375 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1376 Although it may not be explicit in the frag, pretend fr_var starts with a
1380 md_estimate_size_before_relax (fragP
, segment
)
1384 int old_fr_fix
= fragP
->fr_fix
;
1385 char * opcode
= fragP
->fr_opcode
;
1387 /* The only thing we have to handle here are symbols outside of the
1388 current segment. They may be undefined or in a different segment in
1389 which case linker scripts may place them anywhere.
1390 However, we can't finish the fragment here and emit the reloc as insn
1391 alignment requirements may move the insn about. */
1393 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1395 /* The symbol is undefined in this segment.
1396 Change the relaxation subtype to the max allowable and leave
1397 all further handling to md_convert_frag. */
1398 fragP
->fr_subtype
= 2;
1400 #if 0 /* Can't use this, but leave in for illustration. */
1401 /* Change 16 bit insn to 32 bit insn. */
1404 /* Increase known (fixed) size of fragment. */
1407 /* Create a relocation for it. */
1408 fix_new (fragP
, old_fr_fix
, 4,
1410 fragP
->fr_offset
, 1 /* pcrel */,
1411 /* FIXME: Can't use a real BFD reloc here.
1412 cgen_md_apply_fix3 can't handle it. */
1413 BFD_RELOC_M32R_26_PCREL
);
1415 /* Mark this fragment as finished. */
1419 const CGEN_INSN
* insn
;
1422 /* Update the recorded insn.
1423 Fortunately we don't have to look very far.
1424 FIXME: Change this to record in the instruction the next higher
1425 relaxable insn to use. */
1426 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1428 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1429 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1431 && CGEN_INSN_ATTR (insn
, CGEN_INSN_RELAX
))
1437 fragP
->fr_cgen
.insn
= insn
;
1443 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
1446 /* *fragP has been relaxed to its final size, and now needs to have
1447 the bytes inside it modified to conform to the new size.
1449 Called after relaxation is finished.
1450 fragP->fr_type == rs_machine_dependent.
1451 fragP->fr_subtype is the subtype of what the address relaxed to. */
1454 md_convert_frag (abfd
, sec
, fragP
)
1460 char * displacement
;
1466 opcode
= fragP
->fr_opcode
;
1468 /* Address opcode resides at in file space. */
1469 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1471 switch (fragP
->fr_subtype
)
1475 displacement
= & opcode
[1];
1480 displacement
= & opcode
[1];
1483 opcode
[2] = opcode
[0] | 0x80;
1484 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1485 opcode_address
+= 2;
1487 displacement
= & opcode
[3];
1493 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1495 /* symbol must be resolved by linker */
1496 if (fragP
->fr_offset
& 3)
1497 as_warn (_("Addend to unresolved symbol not on word boundary."));
1498 addend
= fragP
->fr_offset
>> 2;
1502 /* Address we want to reach in file space. */
1503 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1504 target_address
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
1505 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1508 /* Create a relocation for symbols that must be resolved by the linker.
1509 Otherwise output the completed insn. */
1511 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1513 assert (fragP
->fr_subtype
!= 1);
1514 assert (fragP
->fr_cgen
.insn
!= 0);
1515 cgen_record_fixup (fragP
,
1516 /* Offset of branch insn in frag. */
1517 fragP
->fr_fix
+ extension
- 4,
1518 fragP
->fr_cgen
.insn
,
1520 /* FIXME: quick hack */
1522 CGEN_OPERAND_ENTRY (fragP
->fr_cgen
.opindex
),
1524 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24
),
1526 fragP
->fr_cgen
.opinfo
,
1527 fragP
->fr_symbol
, fragP
->fr_offset
);
1530 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1532 md_number_to_chars (displacement
, (valueT
) addend
,
1533 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1535 fragP
->fr_fix
+= extension
;
1538 /* Functions concerning relocs. */
1540 /* The location from which a PC relative jump should be calculated,
1541 given a PC relative reloc. */
1544 md_pcrel_from_section (fixP
, sec
)
1548 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1549 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1550 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1552 /* The symbol is undefined (or is defined but not in this section).
1553 Let the linker figure it out. */
1557 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1560 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1561 Returns BFD_RELOC_NONE if no reloc type can be found.
1562 *FIXP may be modified if desired. */
1564 bfd_reloc_code_real_type
1565 CGEN_SYM (lookup_reloc
) (insn
, operand
, fixP
)
1566 const CGEN_INSN
* insn
;
1567 const CGEN_OPERAND
* operand
;
1570 switch (CGEN_OPERAND_TYPE (operand
))
1572 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1573 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1574 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1575 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1576 case M32R_OPERAND_HI16
:
1577 case M32R_OPERAND_SLO16
:
1578 case M32R_OPERAND_ULO16
:
1579 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1580 if (fixP
->tc_fix_data
.opinfo
!= 0)
1581 return fixP
->tc_fix_data
.opinfo
;
1584 return BFD_RELOC_NONE
;
1587 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1590 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1595 struct m32r_hi_fixup
* hi_fixup
;
1597 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1598 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1600 hi_fixup
= ((struct m32r_hi_fixup
*)
1601 xmalloc (sizeof (struct m32r_hi_fixup
)));
1602 hi_fixup
->fixp
= fixP
;
1603 hi_fixup
->seg
= now_seg
;
1604 hi_fixup
->next
= m32r_hi_fixup_list
;
1606 m32r_hi_fixup_list
= hi_fixup
;
1609 /* Called while parsing an instruction to create a fixup.
1610 We need to check for HI16 relocs and queue them up for later sorting. */
1613 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1616 const CGEN_INSN
* insn
;
1618 const CGEN_OPERAND
* operand
;
1622 fixS
* fixP
= cgen_record_fixup_exp (frag
, where
, insn
, length
,
1623 operand
, opinfo
, exp
);
1625 switch (CGEN_OPERAND_TYPE (operand
))
1627 case M32R_OPERAND_HI16
:
1628 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1629 if (fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1630 || fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1631 m32r_record_hi16 (fixP
->tc_fix_data
.opinfo
, fixP
, now_seg
);
1638 /* Return BFD reloc type from opinfo field in a fixS.
1639 It's tricky using fx_r_type in m32r_frob_file because the values
1640 are BFD_RELOC_UNUSED + operand number. */
1641 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1643 /* Sort any unmatched HI16 relocs so that they immediately precede
1644 the corresponding LO16 reloc. This is called before md_apply_fix and
1650 struct m32r_hi_fixup
* l
;
1652 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1654 segment_info_type
* seginfo
;
1657 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1658 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1660 /* Check quickly whether the next fixup happens to be a matching low. */
1661 if (l
->fixp
->fx_next
!= NULL
1662 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1663 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1664 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1667 /* Look through the fixups for this segment for a matching `low'.
1668 When we find one, move the high/shigh just in front of it. We do
1669 this in two passes. In the first pass, we try to find a
1670 unique `low'. In the second pass, we permit multiple high's
1671 relocs for a single `low'. */
1672 seginfo
= seg_info (l
->seg
);
1673 for (pass
= 0; pass
< 2; pass
++)
1679 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1681 /* Check whether this is a `low' fixup which matches l->fixp. */
1682 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
1683 && f
->fx_addsy
== l
->fixp
->fx_addsy
1684 && f
->fx_offset
== l
->fixp
->fx_offset
1687 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
1688 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
1689 || prev
->fx_addsy
!= f
->fx_addsy
1690 || prev
->fx_offset
!= f
->fx_offset
))
1694 /* Move l->fixp before f. */
1695 for (pf
= &seginfo
->fix_root
;
1697 pf
= & (* pf
)->fx_next
)
1698 assert (* pf
!= NULL
);
1700 * pf
= l
->fixp
->fx_next
;
1702 l
->fixp
->fx_next
= f
;
1704 seginfo
->fix_root
= l
->fixp
;
1706 prev
->fx_next
= l
->fixp
;
1718 && warn_unmatched_high
)
1719 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1720 _("Unmatched high/shigh reloc"));
1725 /* See whether we need to force a relocation into the output file.
1726 This is used to force out switch and PC relative relocations when
1730 m32r_force_relocation (fix
)
1736 return (fix
->fx_pcrel
1740 /* Write a value out to the object file, using the appropriate endianness. */
1743 md_number_to_chars (buf
, val
, n
)
1748 if (target_big_endian
)
1749 number_to_chars_bigendian (buf
, val
, n
);
1751 number_to_chars_littleendian (buf
, val
, n
);
1754 /* Turn a string in input_line_pointer into a floating point constant of type
1755 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1756 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1759 /* Equal to MAX_PRECISION in atof-ieee.c */
1760 #define MAX_LITTLENUMS 6
1763 md_atof (type
, litP
, sizeP
)
1770 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1771 LITTLENUM_TYPE
* wordP
;
1773 char * atof_ieee ();
1791 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1795 return _("Bad call to md_atof()");
1798 t
= atof_ieee (input_line_pointer
, type
, words
);
1800 input_line_pointer
= t
;
1801 * sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1803 if (target_big_endian
)
1805 for (i
= 0; i
< prec
; i
++)
1807 md_number_to_chars (litP
, (valueT
) words
[i
],
1808 sizeof (LITTLENUM_TYPE
));
1809 litP
+= sizeof (LITTLENUM_TYPE
);
1814 for (i
= prec
- 1; i
>= 0; i
--)
1816 md_number_to_chars (litP
, (valueT
) words
[i
],
1817 sizeof (LITTLENUM_TYPE
));
1818 litP
+= sizeof (LITTLENUM_TYPE
);
1826 m32r_elf_section_change_hook ()
1828 /* If we have reached the end of a section and we have just emitted a
1829 16 bit insn, then emit a nop to make sure that the section ends on
1830 a 32 bit boundary. */
1832 if (prev_insn
.insn
|| seen_relaxable_p
)
1833 (void) m32r_fill_insn (0);