1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 const CGEN_INSN
* insn
;
32 cgen_insn_t buffer
[CGEN_MAX_INSN_SIZE
/ sizeof (cgen_insn_t
)];
34 char buffer
[CGEN_MAX_INSN_SIZE
];
38 int indices
[MAX_OPERAND_INSTANCES
];
42 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
43 boundary (i.e. was the first of two 16 bit insns). */
44 static m32r_insn prev_insn
;
46 /* Non-zero if we've seen a relaxable insn since the last 32 bit
48 static int seen_relaxable_p
= 0;
50 /* Non-zero if -relax specified, in which case sufficient relocs are output
51 for the linker to do relaxing.
52 We do simple forms of relaxing internally, but they are always done.
53 This flag does not apply to them. */
54 static int m32r_relax
;
56 /* If non-NULL, pointer to cpu description file to read.
57 This allows runtime additions to the assembler. */
58 static char * m32r_cpu_desc
;
60 /* start-sanitize-m32rx */
61 /* Non-zero if -m32rx has been specified, in which case support for the
62 extended M32RX instruction set should be enabled. */
63 static int enable_m32rx
= 0;
65 /* Non-zero if the programmer should be warned when an explicit parallel
66 instruction might have constraint violations. */
67 static int warn_explicit_parallel_conflicts
= 1;
68 /* end-sanitize-m32rx */
70 /* stuff for .scomm symbols. */
71 static segT sbss_section
;
72 static asection scom_section
;
73 static asymbol scom_symbol
;
75 const char comment_chars
[] = ";";
76 const char line_comment_chars
[] = "#";
77 const char line_separator_chars
[] = "";
78 const char EXP_CHARS
[] = "eE";
79 const char FLT_CHARS
[] = "dD";
81 /* Relocations against symbols are done in two
82 parts, with a HI relocation and a LO relocation. Each relocation
83 has only 16 bits of space to store an addend. This means that in
84 order for the linker to handle carries correctly, it must be able
85 to locate both the HI and the LO relocation. This means that the
86 relocations must appear in order in the relocation table.
88 In order to implement this, we keep track of each unmatched HI
89 relocation. We then sort them so that they immediately precede the
90 corresponding LO relocation. */
94 struct m32r_hi_fixup
* next
; /* Next HI fixup. */
95 fixS
* fixp
; /* This fixup. */
96 segT seg
; /* The section this fixup is in. */
100 /* The list of unmatched HI relocs. */
102 static struct m32r_hi_fixup
* m32r_hi_fixup_list
;
105 /* start-sanitize-m32rx */
112 if (stdoutput
!= NULL
)
113 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
114 enable_m32rx
? bfd_mach_m32rx
: bfd_mach_m32r
);
116 /* end-sanitize-m32rx */
118 const char * md_shortopts
= "";
120 struct option md_longopts
[] =
122 /* start-sanitize-m32rx */
123 #define OPTION_M32RX (OPTION_MD_BASE)
124 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
125 #define OPTION_WARN (OPTION_MD_BASE + 1)
126 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN
},
127 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
128 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN
},
129 /* end-sanitize-m32rx */
131 #if 0 /* not supported yet */
132 #define OPTION_RELAX (OPTION_MD_BASE + 3)
133 {"relax", no_argument
, NULL
, OPTION_RELAX
},
134 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
135 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
138 {NULL
, no_argument
, NULL
, 0}
140 size_t md_longopts_size
= sizeof (md_longopts
);
143 md_parse_option (c
, arg
)
149 /* start-sanitize-m32rx */
155 warn_explicit_parallel_conflicts
= 1;
159 warn_explicit_parallel_conflicts
= 0;
161 /* end-sanitize-m32rx */
163 #if 0 /* not supported yet */
167 case OPTION_CPU_DESC
:
178 md_show_usage (stream
)
181 fprintf (stream
, "M32R/X options:\n");
182 /* start-sanitize-m32rx */
184 --m32rx support the extended m32rx instruction set\n");
187 --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\n");
189 --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n");
190 /* end-sanitize-m32rx */
194 --relax create linker relaxable code\n");
196 --cpu-desc provide runtime cpu description file\n");
200 static void fill_insn
PARAMS ((int));
201 static void m32r_scomm
PARAMS ((int));
203 /* Set by md_assemble for use by m32r_fill_insn. */
204 static subsegT prev_subseg
;
205 static segT prev_seg
;
207 /* The target specific pseudo-ops which we support. */
208 const pseudo_typeS md_pseudo_table
[] =
211 { "fillinsn", fill_insn
, 0 },
212 { "scomm", m32r_scomm
, 0 },
213 /* start-sanitize-m32rx */
214 { "m32r", allow_m32rx
, 0},
215 { "m32rx", allow_m32rx
, 1},
216 /* end-sanitize-m32rx */
220 /* FIXME: Should be machine generated. */
221 #define NOP_INSN 0x7000
222 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
224 /* When we align the .text section, insert the correct NOP pattern.
225 N is the power of 2 alignment. LEN is the length of pattern FILL.
226 MAX is the maximum number of characters to skip when doing the alignment,
227 or 0 if there is no maximum. */
230 m32r_do_align (n
, fill
, len
, max
)
236 if ((fill
== NULL
|| (* fill
== 0 && len
== 1))
237 && (now_seg
->flags
& SEC_CODE
) != 0
238 /* Only do this special handling if aligning to at least a
241 /* Only do this special handling if we're allowed to emit at
243 && (max
== 0 || max
> 1))
245 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
248 /* First align to a 2 byte boundary, in case there is an odd .byte. */
249 /* FIXME: How much memory will cause gas to use when assembling a big
250 program? Perhaps we can avoid the frag_align call? */
251 frag_align (1, 0, 0);
253 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
255 frag_align_pattern (2, nop_pattern
, sizeof nop_pattern
, 0);
256 /* If doing larger alignments use a repeating sequence of appropriate
260 static const unsigned char multi_nop_pattern
[] =
261 { 0x70, 0x00, 0xf0, 0x00 };
262 frag_align_pattern (n
, multi_nop_pattern
, sizeof multi_nop_pattern
,
272 assemble_nop (opcode
)
275 char * f
= frag_more (2);
276 md_number_to_chars (f
, opcode
, 2);
279 /* If the last instruction was the first of 2 16 bit insns,
280 output a nop to move the PC to a 32 bit boundary.
282 This is done via an alignment specification since branch relaxing
283 may make it unnecessary.
285 Internally, we need to output one of these each time a 32 bit insn is
286 seen after an insn that is relaxable. */
292 (void) m32r_do_align (2, NULL
, 0, 0);
293 prev_insn
.insn
= NULL
;
294 seen_relaxable_p
= 0;
297 /* Cover function to fill_insn called after a label and at end of assembly.
299 The result is always 1: we're called in a conditional to see if the
300 current line is a label. */
303 m32r_fill_insn (done
)
309 if (prev_seg
!= NULL
)
314 subseg_set (prev_seg
, prev_subseg
);
318 subseg_set (seg
, subseg
);
331 /* Initialize the `cgen' interface. */
333 /* This is a callback from cgen to gas to parse operands. */
334 cgen_parse_operand_fn
= cgen_parse_operand
;
336 /* Set the machine number and endian. */
337 CGEN_SYM (init_asm
) (0 /* mach number */,
339 CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE
);
341 #if 0 /* not supported yet */
342 /* If a runtime cpu description file was provided, parse it. */
343 if (m32r_cpu_desc
!= NULL
)
347 errmsg
= cgen_read_cpu_file (m32r_cpu_desc
);
349 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
353 /* Save the current subseg so we can restore it [it's the default one and
354 we don't want the initial section to be .sbss]. */
358 /* The sbss section is for local .scomm symbols. */
359 sbss_section
= subseg_new (".sbss", 0);
361 /* This is copied from perform_an_assembly_pass. */
362 applicable
= bfd_applicable_section_flags (stdoutput
);
363 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
365 #if 0 /* What does this do? [see perform_an_assembly_pass] */
366 seg_info (bss_section
)->bss
= 1;
369 subseg_set (seg
, subseg
);
371 /* We must construct a fake section similar to bfd_com_section
372 but with the name .scommon. */
373 scom_section
= bfd_com_section
;
374 scom_section
.name
= ".scommon";
375 scom_section
.output_section
= & scom_section
;
376 scom_section
.symbol
= & scom_symbol
;
377 scom_section
.symbol_ptr_ptr
= & scom_section
.symbol
;
378 scom_symbol
= * bfd_com_section
.symbol
;
379 scom_symbol
.name
= ".scommon";
380 scom_symbol
.section
= & scom_section
;
382 /* start-sanitize-m32rx */
383 allow_m32rx (enable_m32rx
);
384 /* end-sanitize-m32rx */
387 /* start-sanitize-m32rx */
388 #ifdef HAVE_CPU_M32RX
390 /* Returns true if an output of instruction 'a' is referenced by an operand
391 of instruction 'b'. If 'check_outputs' is true then b's outputs are
392 checked, otherwise its inputs are examined. */
394 first_writes_to_seconds_operands (a
, b
, check_outputs
)
397 const int check_outputs
;
399 const CGEN_OPERAND_INSTANCE
* a_operands
;
402 /* Scan the operand list of 'a' looking for an output operand. */
403 for (a_index
= 0, a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
404 CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
;
405 a_index
++, a_operands
++)
407 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) == CGEN_OPERAND_INSTANCE_OUTPUT
)
409 const CGEN_OPERAND_INSTANCE
* b_operands
;
412 /* Scan operand list of 'b' looking for an operand that references
413 the same hardware element, and which goes in the right direction. */
414 for (b_index
= 0, b_operands
= CGEN_INSN_OPERANDS (b
->insn
);
415 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
416 b_index
++, b_operands
++)
418 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
419 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
420 && (CGEN_OPERAND_INSTANCE_HW (b_operands
) == CGEN_OPERAND_INSTANCE_HW (a_operands
))
421 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
430 /* Returns true if the insn can (potentially) alter the program counter. */
436 const CGEN_OPERAND_INSTANCE
* a_operands
;
438 for (a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
439 CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
;
442 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
) != NULL
443 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
)) == M32R_OPERAND_PC
)
447 if (CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_UNCOND_CTI
)
448 || CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_COND_CTI
))
454 /* Returns NULL if the two 16 bit insns can be executed in parallel,
455 otherwise it returns a pointer to an error message explaining why not. */
457 can_make_parallel (a
, b
)
464 /* Make sure the instructions are the right length. */
465 if ( CGEN_FIELDS_BITSIZE (& a
->fields
) != 16
466 || CGEN_FIELDS_BITSIZE (& b
->fields
) != 16)
469 if (first_writes_to_seconds_operands (a
, b
, true))
470 return "Instructions write to the same destination register.";
472 a_pipe
= CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_PIPE
);
473 b_pipe
= CGEN_INSN_ATTR (b
->insn
, CGEN_INSN_PIPE
);
475 /* Make sure that the instructions use the correct execution pipelines. */
476 if ( a_pipe
== PIPE_NONE
477 || b_pipe
== PIPE_NONE
)
478 return "Instructions do not use parallel execution pipelines.";
480 /* Leave this test for last, since it is the only test that can
481 go away if the instructions are swapped, and we want to make
482 sure that any other errors are detected before this happens. */
483 if ( a_pipe
== PIPE_S
485 return "Instructions share the same execution pipeline";
492 make_parallel (buffer
)
493 cgen_insn_t
* buffer
;
495 /* Force the top bit of the second insn to be set. */
499 if (CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
)
501 value
= bfd_getb16 ((bfd_byte
*) buffer
);
503 bfd_putb16 (value
, (char *) buffer
);
507 value
= bfd_getl16 ((bfd_byte
*) buffer
);
509 bfd_putl16 (value
, (char *) buffer
);
514 make_parallel (buffer
)
517 /* Force the top bit of the second insn to be set. */
519 buffer
[CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
? 0 : 1] |= 0x80;
525 assemble_parallel_insn (str
, str2
)
534 * str2
= 0; /* Seperate the two instructions. */
536 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
537 so that the parallel instruction will start on a 32 bit boundary. */
541 /* Parse the first instruction. */
542 if (! (first
.insn
= CGEN_SYM (assemble_insn
)
543 (str
, & first
.fields
, first
.buffer
, & errmsg
)))
549 /* Check to see if this is an allowable parallel insn. */
550 if (CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
552 as_bad ("instruction '%s' cannot be executed in parallel.", str
);
557 && CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
559 as_bad ("instruction '%s' is for the M32RX only", str
);
563 *str2
= '|'; /* Restore the original assembly text, just in case it is needed. */
564 str3
= str
; /* Save the original string pointer. */
565 str
= str2
+ 2; /* Advanced past the parsed string. */
566 str2
= str3
; /* Remember the entire string in case it is needed for error messages. */
568 /* Preserve any fixups that have been generated and reset the list to empty. */
571 /* Get the indicies of the operands of the instruction. */
572 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
573 doesn't seem right. Perhaps allow passing fields like we do insn. */
574 if (m32r_cgen_get_insn_operands (first
.insn
, bfd_getb16 ((char *) first
.buffer
), 16,
575 first
.indices
) == NULL
)
576 as_fatal ("internal error: m32r_cgen_get_insn_operands failed for first insn");
578 /* Parse the second instruction. */
579 if (! (second
.insn
= CGEN_SYM (assemble_insn
)
580 (str
, & second
.fields
, second
.buffer
, & errmsg
)))
588 && CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
590 as_bad ("instruction '%s' is for the M32RX only", str
);
596 if ( strcmp (first
.insn
->name
, "nop") != 0
597 && strcmp (second
.insn
->name
, "nop") != 0)
599 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2
);
604 /* Get the indicies of the operands of the instruction. */
605 if (m32r_cgen_get_insn_operands (second
.insn
, bfd_getb16 ((char *) second
.buffer
), 16,
606 second
.indices
) == NULL
)
607 as_fatal ("internal error: m32r_cgen_get_insn_operands failed for second insn");
609 /* We assume that if the first instruction writes to a register that is
610 read by the second instruction it is because the programmer intended
611 this to happen, (after all they have explicitly requested that these
612 two instructions be executed in parallel). Although if the global
613 variable warn_explicit_parallel_conflicts is true then we do generate
614 a warning message. Similarly we assume that parallel branch and jump
615 instructions are deliberate and should not produce errors. */
617 if (warn_explicit_parallel_conflicts
)
619 if (first_writes_to_seconds_operands (& first
, & second
, false))
620 as_warn ("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?", str2
);
622 if (first_writes_to_seconds_operands (& second
, & first
, false))
623 as_warn ("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?", str2
);
626 if ((errmsg
= (char *) can_make_parallel (& first
, & second
)) == NULL
)
628 /* Get the fixups for the first instruction. */
632 (void) cgen_asm_finish_insn (first
.insn
, first
.buffer
,
633 CGEN_FIELDS_BITSIZE (& first
.fields
));
635 /* Force the top bit of the second insn to be set. */
636 make_parallel (second
.buffer
);
638 /* Get its fixups. */
639 cgen_restore_fixups ();
642 (void) cgen_asm_finish_insn (second
.insn
, second
.buffer
,
643 CGEN_FIELDS_BITSIZE (& second
.fields
));
645 /* Try swapping the instructions to see if they work that way. */
646 else if (can_make_parallel (& second
, & first
) == NULL
)
648 /* Write out the second instruction first. */
649 (void) cgen_asm_finish_insn (second
.insn
, second
.buffer
,
650 CGEN_FIELDS_BITSIZE (& second
.fields
));
652 /* Force the top bit of the first instruction to be set. */
653 make_parallel (first
.buffer
);
655 /* Get the fixups for the first instruction. */
656 cgen_restore_fixups ();
658 /* Write out the first instruction. */
659 (void) cgen_asm_finish_insn (first
.insn
, first
.buffer
,
660 CGEN_FIELDS_BITSIZE (& first
.fields
));
664 as_bad ("'%s': %s", str2
, errmsg
);
668 /* Set these so m32r_fill_insn can use them. */
670 prev_subseg
= now_subseg
;
675 #endif /* HAVE_CPU_M32RX */
677 /* end-sanitize-m32rx */
688 /* Initialize GAS's cgen interface for a new instruction. */
689 cgen_asm_init_parse ();
691 /* start-sanitize-m32rx */
692 #ifdef HAVE_CPU_M32RX
693 /* Look for a parallel instruction seperator. */
694 if ((str2
= strstr (str
, "||")) != NULL
)
696 assemble_parallel_insn (str
, str2
);
700 /* end-sanitize-m32rx */
702 insn
.insn
= CGEN_SYM (assemble_insn
) (str
, & insn
.fields
, insn
.buffer
, & errmsg
);
709 /* start-sanitize-m32rx */
710 #ifdef HAVE_CPU_M32RX
711 if (! enable_m32rx
&& CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
713 as_bad ("instruction '%s' is for the M32RX only", str
);
717 /* end-sanitize-m32rx */
719 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
721 /* 32 bit insns must live on 32 bit boundaries. */
722 if (prev_insn
.insn
|| seen_relaxable_p
)
724 /* FIXME: If calling fill_insn too many times turns us into a memory
725 pig, can we call assemble_nop instead of !seen_relaxable_p? */
729 (void) cgen_asm_finish_insn (insn
.insn
, insn
.buffer
,
730 CGEN_FIELDS_BITSIZE (& insn
.fields
));
734 /* start-sanitize-m32rx */
735 /* start-sanitize-phase2-m32rx */
737 /* end-sanitize-phase2-m32rx */
738 /* end-sanitize-m32rx */
740 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
743 /* Get the indicies of the operands of the instruction. */
744 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
745 doesn't seem right. Perhaps allow passing fields like we do insn. */
746 if (m32r_cgen_get_insn_operands (insn
.insn
, bfd_getb16 ((char *) insn
.buffer
), 16,
747 insn
.indices
) == NULL
)
748 as_fatal ("internal error: m32r_cgen_get_insn_operands failed");
750 /* Keep track of whether we've seen a pair of 16 bit insns.
751 prev_insn.insn is NULL when we're on a 32 bit boundary. */
754 /* start-sanitize-m32rx */
755 /* start-sanitize-phase2-m32rx */
756 #ifdef HAVE_CPU_M32RX
757 /* Look to see if this instruction can be combined with the
758 previous instruction to make one, parallel, 32 bit instruction.
759 If the previous instruction (potentially) changed the flow of
760 program control, then it cannot be combined with the current
761 instruction. Also if the output of the previous instruction
762 is used as an input to the current instruction then it cannot
763 be combined. Otherwise call can_make_parallel() with both
764 orderings of the instructions to see if they can be combined. */
765 if (! writes_to_pc (& prev_insn
)
766 && ! first_writes_to_seconds_operands (& prev_insn
, &insn
, false)
769 if (can_make_parallel (& prev_insn
, & insn
) == NULL
)
770 make_parallel (insn
.buffer
);
771 else if (can_make_parallel (& insn
, & prev_insn
.insn
) == NULL
)
775 /* end-sanitize-phase2-m32rx */
776 /* end-sanitize-m32rx */
778 prev_insn
.insn
= NULL
;
785 /* Record the frag that might be used by this insn. */
786 insn
.frag
= frag_now
;
787 insn
.addr
= cgen_asm_finish_insn (insn
.insn
, insn
.buffer
,
788 CGEN_FIELDS_BITSIZE (& insn
.fields
));
790 /* start-sanitize-m32rx */
791 /* start-sanitize-phase2-m32rx */
792 #ifdef HAVE_CPU_M32RX
797 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
799 /* Swap the two insns */
800 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
801 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
803 make_parallel (insn
.addr
);
805 /* Swap any relaxable frags recorded for the two insns. */
806 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
808 prev_insn
.frag
->fr_opcode
= insn
.addr
;
810 else if (insn
.frag
->fr_opcode
== insn
.addr
)
812 insn
.frag
->fr_opcode
= prev_insn
.addr
;
815 /* end-sanitize-phase2-m32rx */
817 /* Record where this instruction was assembled. */
818 prev_insn
.addr
= insn
.addr
;
819 prev_insn
.frag
= insn
.frag
;
821 /* end-sanitize-m32rx */
823 /* If the insn needs the following one to be on a 32 bit boundary
824 (e.g. subroutine calls), fill this insn's slot. */
826 && CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_FILL_SLOT
) != 0)
829 /* If this is a relaxable insn (can be replaced with a larger version)
830 mark the fact so that we can emit an alignment directive for a
831 following 32 bit insn if we see one. */
832 if (CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_RELAXABLE
) != 0)
833 seen_relaxable_p
= 1;
836 /* Set these so m32r_fill_insn can use them. */
838 prev_subseg
= now_subseg
;
841 /* The syntax in the manual says constants begin with '#'.
842 We just ignore it. */
845 md_operand (expressionP
)
846 expressionS
* expressionP
;
848 if (* input_line_pointer
== '#')
850 input_line_pointer
++;
851 expression (expressionP
);
856 md_section_align (segment
, size
)
860 int align
= bfd_get_section_alignment (stdoutput
, segment
);
861 return ((size
+ (1 << align
) - 1) & (-1 << align
));
865 md_undefined_symbol (name
)
871 /* .scomm pseudo-op handler.
873 This is a new pseudo-op to handle putting objects in .scommon.
874 By doing this the linker won't need to do any work and more importantly
875 it removes the implicit -G arg necessary to correctly link the object file.
882 register char * name
;
886 register symbolS
* symbolP
;
890 name
= input_line_pointer
;
891 c
= get_symbol_end ();
893 /* just after name is now '\0' */
894 p
= input_line_pointer
;
897 if (* input_line_pointer
!= ',')
899 as_bad ("Expected comma after symbol-name: rest of line ignored.");
900 ignore_rest_of_line ();
904 input_line_pointer
++; /* skip ',' */
905 if ((size
= get_absolute_expression ()) < 0)
907 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size
);
908 ignore_rest_of_line ();
912 /* The third argument to .scomm is the alignment. */
913 if (* input_line_pointer
!= ',')
917 ++ input_line_pointer
;
918 align
= get_absolute_expression ();
921 as_warn ("ignoring bad alignment");
925 /* Convert to a power of 2 alignment. */
928 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++ align2
)
932 as_bad ("Common alignment not a power of 2");
933 ignore_rest_of_line ();
941 symbolP
= symbol_find_or_make (name
);
944 if (S_IS_DEFINED (symbolP
))
946 as_bad ("Ignoring attempt to re-define symbol `%s'.",
947 S_GET_NAME (symbolP
));
948 ignore_rest_of_line ();
952 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
954 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
955 S_GET_NAME (symbolP
),
956 (long) S_GET_VALUE (symbolP
),
959 ignore_rest_of_line ();
965 segT old_sec
= now_seg
;
966 int old_subsec
= now_subseg
;
969 record_alignment (sbss_section
, align2
);
970 subseg_set (sbss_section
, 0);
973 frag_align (align2
, 0, 0);
975 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
976 symbolP
->sy_frag
->fr_symbol
= 0;
978 symbolP
->sy_frag
= frag_now
;
980 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
983 S_SET_SIZE (symbolP
, size
);
984 S_SET_SEGMENT (symbolP
, sbss_section
);
985 S_CLEAR_EXTERNAL (symbolP
);
986 subseg_set (old_sec
, old_subsec
);
990 S_SET_VALUE (symbolP
, (valueT
) size
);
991 S_SET_ALIGN (symbolP
, align2
);
992 S_SET_EXTERNAL (symbolP
);
993 S_SET_SEGMENT (symbolP
, & scom_section
);
996 demand_empty_rest_of_line ();
999 /* Interface to relax_segment. */
1001 /* FIXME: Build table by hand, get it working, then machine generate. */
1003 const relax_typeS md_relax_table
[] =
1006 1) most positive reach of this state,
1007 2) most negative reach of this state,
1008 3) how many bytes this mode will add to the size of the current frag
1009 4) which index into the table to try if we can't fit into this one. */
1011 /* The first entry must be unused because an `rlx_more' value of zero ends
1015 /* The displacement used by GAS is from the end of the 2 byte insn,
1016 so we subtract 2 from the following. */
1017 /* 16 bit insn, 8 bit disp -> 10 bit range.
1018 This doesn't handle a branch in the right slot at the border:
1019 the "& -4" isn't taken into account. It's not important enough to
1020 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1022 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1023 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1024 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1025 /* Same thing, but with leading nop for alignment. */
1026 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1030 m32r_relax_frag (fragP
, stretch
)
1034 /* Address of branch insn. */
1035 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1038 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1039 if (fragP
->fr_subtype
== 2)
1041 if ((address
& 3) != 0)
1043 fragP
->fr_subtype
= 3;
1047 else if (fragP
->fr_subtype
== 3)
1049 if ((address
& 3) == 0)
1051 fragP
->fr_subtype
= 2;
1057 growth
= relax_frag (fragP
, stretch
);
1059 /* Long jump on odd halfword boundary? */
1060 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1062 fragP
->fr_subtype
= 3;
1070 /* Return an initial guess of the length by which a fragment must grow to
1071 hold a branch to reach its destination.
1072 Also updates fr_type/fr_subtype as necessary.
1074 Called just before doing relaxation.
1075 Any symbol that is now undefined will not become defined.
1076 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1077 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1078 Although it may not be explicit in the frag, pretend fr_var starts with a
1082 md_estimate_size_before_relax (fragP
, segment
)
1086 int old_fr_fix
= fragP
->fr_fix
;
1087 char * opcode
= fragP
->fr_opcode
;
1089 /* The only thing we have to handle here are symbols outside of the
1090 current segment. They may be undefined or in a different segment in
1091 which case linker scripts may place them anywhere.
1092 However, we can't finish the fragment here and emit the reloc as insn
1093 alignment requirements may move the insn about. */
1095 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1097 /* The symbol is undefined in this segment.
1098 Change the relaxation subtype to the max allowable and leave
1099 all further handling to md_convert_frag. */
1100 fragP
->fr_subtype
= 2;
1102 #if 0 /* Can't use this, but leave in for illustration. */
1103 /* Change 16 bit insn to 32 bit insn. */
1106 /* Increase known (fixed) size of fragment. */
1109 /* Create a relocation for it. */
1110 fix_new (fragP
, old_fr_fix
, 4,
1112 fragP
->fr_offset
, 1 /* pcrel */,
1113 /* FIXME: Can't use a real BFD reloc here.
1114 cgen_md_apply_fix3 can't handle it. */
1115 BFD_RELOC_M32R_26_PCREL
);
1117 /* Mark this fragment as finished. */
1121 const CGEN_INSN
* insn
;
1124 /* Update the recorded insn.
1125 Fortunately we don't have to look very far.
1126 FIXME: Change this to record in the instruction the next higher
1127 relaxable insn to use. */
1128 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1130 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1131 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1133 && CGEN_INSN_ATTR (insn
, CGEN_INSN_RELAX
))
1139 fragP
->fr_cgen
.insn
= insn
;
1145 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
1148 /* *fragP has been relaxed to its final size, and now needs to have
1149 the bytes inside it modified to conform to the new size.
1151 Called after relaxation is finished.
1152 fragP->fr_type == rs_machine_dependent.
1153 fragP->fr_subtype is the subtype of what the address relaxed to. */
1156 md_convert_frag (abfd
, sec
, fragP
)
1162 char * displacement
;
1168 opcode
= fragP
->fr_opcode
;
1170 /* Address opcode resides at in file space. */
1171 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1173 switch (fragP
->fr_subtype
)
1177 displacement
= & opcode
[1];
1182 displacement
= & opcode
[1];
1185 opcode
[2] = opcode
[0] | 0x80;
1186 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1187 opcode_address
+= 2;
1189 displacement
= & opcode
[3];
1195 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1197 /* symbol must be resolved by linker */
1198 if (fragP
->fr_offset
& 3)
1199 as_warn ("Addend to unresolved symbol not on word boundary.");
1200 addend
= fragP
->fr_offset
>> 2;
1204 /* Address we want to reach in file space. */
1205 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1206 target_address
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
1207 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1210 /* Create a relocation for symbols that must be resolved by the linker.
1211 Otherwise output the completed insn. */
1213 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1215 assert (fragP
->fr_subtype
!= 1);
1216 assert (fragP
->fr_cgen
.insn
!= 0);
1217 cgen_record_fixup (fragP
,
1218 /* Offset of branch insn in frag. */
1219 fragP
->fr_fix
+ extension
- 4,
1220 fragP
->fr_cgen
.insn
,
1222 /* FIXME: quick hack */
1224 CGEN_OPERAND_ENTRY (fragP
->fr_cgen
.opindex
),
1226 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24
),
1228 fragP
->fr_cgen
.opinfo
,
1229 fragP
->fr_symbol
, fragP
->fr_offset
);
1232 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1234 md_number_to_chars (displacement
, (valueT
) addend
,
1235 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1237 fragP
->fr_fix
+= extension
;
1240 /* Functions concerning relocs. */
1242 /* The location from which a PC relative jump should be calculated,
1243 given a PC relative reloc. */
1246 md_pcrel_from_section (fixP
, sec
)
1250 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1251 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1252 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1254 /* The symbol is undefined (or is defined but not in this section).
1255 Let the linker figure it out. */
1259 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1262 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1263 Returns BFD_RELOC_NONE if no reloc type can be found.
1264 *FIXP may be modified if desired. */
1266 bfd_reloc_code_real_type
1267 CGEN_SYM (lookup_reloc
) (insn
, operand
, fixP
)
1268 const CGEN_INSN
* insn
;
1269 const CGEN_OPERAND
* operand
;
1272 switch (CGEN_OPERAND_TYPE (operand
))
1274 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1275 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1276 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1277 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1278 case M32R_OPERAND_HI16
:
1279 case M32R_OPERAND_SLO16
:
1280 case M32R_OPERAND_ULO16
:
1281 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1282 if (fixP
->tc_fix_data
.opinfo
!= 0)
1283 return fixP
->tc_fix_data
.opinfo
;
1286 return BFD_RELOC_NONE
;
1289 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1292 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1297 struct m32r_hi_fixup
* hi_fixup
;
1299 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1300 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1302 hi_fixup
= ((struct m32r_hi_fixup
*)
1303 xmalloc (sizeof (struct m32r_hi_fixup
)));
1304 hi_fixup
->fixp
= fixP
;
1305 hi_fixup
->seg
= now_seg
;
1306 hi_fixup
->next
= m32r_hi_fixup_list
;
1308 m32r_hi_fixup_list
= hi_fixup
;
1311 /* Called while parsing an instruction to create a fixup.
1312 We need to check for HI16 relocs and queue them up for later sorting. */
1315 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1318 const CGEN_INSN
* insn
;
1320 const CGEN_OPERAND
* operand
;
1324 fixS
* fixP
= cgen_record_fixup_exp (frag
, where
, insn
, length
,
1325 operand
, opinfo
, exp
);
1327 switch (CGEN_OPERAND_TYPE (operand
))
1329 case M32R_OPERAND_HI16
:
1330 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1331 if (fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1332 || fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1333 m32r_record_hi16 (fixP
->tc_fix_data
.opinfo
, fixP
, now_seg
);
1340 /* Return BFD reloc type from opinfo field in a fixS.
1341 It's tricky using fx_r_type in m32r_frob_file because the values
1342 are BFD_RELOC_UNUSED + operand number. */
1343 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1345 /* Sort any unmatched HI16 relocs so that they immediately precede
1346 the corresponding LO16 reloc. This is called before md_apply_fix and
1352 struct m32r_hi_fixup
* l
;
1354 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1356 segment_info_type
* seginfo
;
1359 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1360 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1362 /* Check quickly whether the next fixup happens to be a matching low. */
1363 if (l
->fixp
->fx_next
!= NULL
1364 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1365 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1366 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1369 /* Look through the fixups for this segment for a matching `low'.
1370 When we find one, move the high/shigh just in front of it. We do
1371 this in two passes. In the first pass, we try to find a
1372 unique `low'. In the second pass, we permit multiple high's
1373 relocs for a single `low'. */
1374 seginfo
= seg_info (l
->seg
);
1375 for (pass
= 0; pass
< 2; pass
++)
1381 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1383 /* Check whether this is a `low' fixup which matches l->fixp. */
1384 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
1385 && f
->fx_addsy
== l
->fixp
->fx_addsy
1386 && f
->fx_offset
== l
->fixp
->fx_offset
1389 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
1390 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
1391 || prev
->fx_addsy
!= f
->fx_addsy
1392 || prev
->fx_offset
!= f
->fx_offset
))
1396 /* Move l->fixp before f. */
1397 for (pf
= &seginfo
->fix_root
;
1399 pf
= & (* pf
)->fx_next
)
1400 assert (* pf
!= NULL
);
1402 * pf
= l
->fixp
->fx_next
;
1404 l
->fixp
->fx_next
= f
;
1406 seginfo
->fix_root
= l
->fixp
;
1408 prev
->fx_next
= l
->fixp
;
1420 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1421 "Unmatched high/shigh reloc");
1426 /* See whether we need to force a relocation into the output file.
1427 This is used to force out switch and PC relative relocations when
1431 m32r_force_relocation (fix
)
1437 return (fix
->fx_pcrel
1441 /* Write a value out to the object file, using the appropriate endianness. */
1444 md_number_to_chars (buf
, val
, n
)
1449 if (target_big_endian
)
1450 number_to_chars_bigendian (buf
, val
, n
);
1452 number_to_chars_littleendian (buf
, val
, n
);
1455 /* Turn a string in input_line_pointer into a floating point constant of type
1456 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1457 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1460 /* Equal to MAX_PRECISION in atof-ieee.c */
1461 #define MAX_LITTLENUMS 6
1464 md_atof (type
, litP
, sizeP
)
1471 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1472 LITTLENUM_TYPE
* wordP
;
1474 char * atof_ieee ();
1492 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1496 return "Bad call to md_atof()";
1499 t
= atof_ieee (input_line_pointer
, type
, words
);
1501 input_line_pointer
= t
;
1502 * sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1504 if (target_big_endian
)
1506 for (i
= 0; i
< prec
; i
++)
1508 md_number_to_chars (litP
, (valueT
) words
[i
],
1509 sizeof (LITTLENUM_TYPE
));
1510 litP
+= sizeof (LITTLENUM_TYPE
);
1515 for (i
= prec
- 1; i
>= 0; i
--)
1517 md_number_to_chars (litP
, (valueT
) words
[i
],
1518 sizeof (LITTLENUM_TYPE
));
1519 litP
+= sizeof (LITTLENUM_TYPE
);