1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 /* Linked list of symbols that are debugging symbols to be defined as the
30 beginning of the current instruction. */
31 typedef struct sym_link
33 struct sym_link
*next
;
37 static sym_linkS
*debug_sym_link
= (sym_linkS
*)0;
39 /* Structure to hold all of the different components describing
40 an individual instruction. */
43 const CGEN_INSN
* insn
;
44 const CGEN_INSN
* orig_insn
;
47 cgen_insn_t buffer
[CGEN_MAX_INSN_SIZE
/ sizeof (cgen_insn_t
)];
49 char buffer
[CGEN_MAX_INSN_SIZE
];
54 fixS
* fixups
[CGEN_MAX_FIXUPS
];
55 int indices
[MAX_OPERAND_INSTANCES
];
56 sym_linkS
*debug_sym_link
;
60 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
61 boundary (i.e. was the first of two 16 bit insns). */
62 static m32r_insn prev_insn
;
64 /* Non-zero if we've seen a relaxable insn since the last 32 bit
66 static int seen_relaxable_p
= 0;
68 /* Non-zero if -relax specified, in which case sufficient relocs are output
69 for the linker to do relaxing.
70 We do simple forms of relaxing internally, but they are always done.
71 This flag does not apply to them. */
72 static int m32r_relax
;
74 /* If non-NULL, pointer to cpu description file to read.
75 This allows runtime additions to the assembler. */
76 static char * m32r_cpu_desc
;
78 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
79 Each high/shigh reloc must be paired with it's low cousin in order to
80 properly calculate the addend in a relocatable link (since there is a
81 potential carry from the low to the high/shigh).
82 This option is off by default though for user-written assembler code it
83 might make sense to make the default be on (i.e. have gcc pass a flag
84 to turn it off). This warning must not be on for GCC created code as
85 optimization may delete the low but not the high/shigh (at least we
86 shouldn't assume or require it to). */
87 static int warn_unmatched_high
= 0;
89 /* start-sanitize-m32rx */
90 /* Non-zero if --m32rx has been specified, in which case support for the
91 extended M32RX instruction set should be enabled. */
92 static int enable_m32rx
= 0;
94 /* Non-zero if --m32rx --hidden has been specified, in which case support for
95 the special M32RX instruction set should be enabled. */
96 static int enable_special
= 0;
98 /* Non-zero if the programmer should be warned when an explicit parallel
99 instruction might have constraint violations. */
100 static int warn_explicit_parallel_conflicts
= 1;
102 /* Non-zero if insns can be made parallel. */
104 /* end-sanitize-m32rx */
106 /* stuff for .scomm symbols. */
107 static segT sbss_section
;
108 static asection scom_section
;
109 static asymbol scom_symbol
;
111 const char comment_chars
[] = ";";
112 const char line_comment_chars
[] = "#";
113 const char line_separator_chars
[] = "";
114 const char EXP_CHARS
[] = "eE";
115 const char FLT_CHARS
[] = "dD";
117 /* Relocations against symbols are done in two
118 parts, with a HI relocation and a LO relocation. Each relocation
119 has only 16 bits of space to store an addend. This means that in
120 order for the linker to handle carries correctly, it must be able
121 to locate both the HI and the LO relocation. This means that the
122 relocations must appear in order in the relocation table.
124 In order to implement this, we keep track of each unmatched HI
125 relocation. We then sort them so that they immediately precede the
126 corresponding LO relocation. */
130 struct m32r_hi_fixup
* next
; /* Next HI fixup. */
131 fixS
* fixp
; /* This fixup. */
132 segT seg
; /* The section this fixup is in. */
136 /* The list of unmatched HI relocs. */
138 static struct m32r_hi_fixup
* m32r_hi_fixup_list
;
141 /* start-sanitize-m32rx */
148 if (stdoutput
!= NULL
)
149 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
150 enable_m32rx
? bfd_mach_m32rx
: bfd_mach_m32r
);
152 /* end-sanitize-m32rx */
154 #define M32R_SHORTOPTS ""
155 /* start-sanitize-m32rx */
156 #undef M32R_SHORTOPTS
157 #define M32R_SHORTOPTS "O"
158 /* end-sanitize-m32rx */
159 const char * md_shortopts
= M32R_SHORTOPTS
;
161 struct option md_longopts
[] =
163 /* start-sanitize-m32rx */
164 #define OPTION_M32RX (OPTION_MD_BASE)
165 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
166 #define OPTION_WARN_PARALLEL (OPTION_MD_BASE + 1)
167 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
168 {"Wp", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
169 #define OPTION_NO_WARN_PARALLEL (OPTION_MD_BASE + 2)
170 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
171 {"Wnp", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
172 #define OPTION_SPECIAL (OPTION_MD_BASE + 3)
173 {"hidden", no_argument
, NULL
, OPTION_SPECIAL
},
174 /* end-sanitize-m32rx */
176 /* Sigh. I guess all warnings must now have both variants. */
177 #define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4)
178 {"warn-unmatched-high", OPTION_WARN_UNMATCHED
},
179 {"Wuh", OPTION_WARN_UNMATCHED
},
180 #define OPTION_NO_WARN_UNMATCHED (OPTION_MD_BASE + 5)
181 {"no-warn-unmatched-high", OPTION_WARN_UNMATCHED
},
182 {"Wnuh", OPTION_WARN_UNMATCHED
},
184 #if 0 /* not supported yet */
185 #define OPTION_RELAX (OPTION_MD_BASE + 6)
186 {"relax", no_argument
, NULL
, OPTION_RELAX
},
187 #define OPTION_CPU_DESC (OPTION_MD_BASE + 7)
188 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
191 {NULL
, no_argument
, NULL
, 0}
193 size_t md_longopts_size
= sizeof (md_longopts
);
196 md_parse_option (c
, arg
)
202 /* start-sanitize-m32rx */
211 case OPTION_WARN_PARALLEL
:
212 warn_explicit_parallel_conflicts
= 1;
215 case OPTION_NO_WARN_PARALLEL
:
216 warn_explicit_parallel_conflicts
= 0;
224 extern char * myname
;
226 /* Pretend that we do not recognise this option. */
227 fprintf (stderr
, _("%s: unrecognised option: --hidden\n"), myname
);
231 /* end-sanitize-m32rx */
233 case OPTION_WARN_UNMATCHED
:
234 warn_unmatched_high
= 1;
237 case OPTION_NO_WARN_UNMATCHED
:
238 warn_unmatched_high
= 0;
241 #if 0 /* not supported yet */
245 case OPTION_CPU_DESC
:
257 md_show_usage (stream
)
260 fprintf (stream
, _("M32R specific command line options:\n"));
262 /* start-sanitize-m32rx */
263 fprintf (stream
, _("\
264 --m32rx support the extended m32rx instruction set\n"));
265 fprintf (stream
, _("\
266 -O try to combine instructions in parallel\n"));
268 fprintf (stream
, _("\
269 --warn-explicit-parallel-conflicts warn when parallel instrucitons violate contraints\n"));
270 fprintf (stream
, _("\
271 --no-warn-explicit-parallel-conflicts do not warn when parallel instrucitons violate contraints\n"));
272 fprintf (stream
, _("\
273 --Wp synonym for --warn-explicit-parallel-conflicts\n"));
274 fprintf (stream
, _("\
275 --Wnp synonym for --no-warn-explicit-parallel-conflicts\n"));
276 /* end-sanitize-m32rx */
278 fprintf (stream
, _("\
279 --warn-unmatched-high warn when a high or shigh reloc has no matching low reloc\n"));
280 fprintf (stream
, _("\
281 --no-warn-unmatched-high do not warn when a high or shigh reloc has no matching low reloc\n"));
282 fprintf (stream
, _("\
283 --Wuh synonym for --warn-unmatched-high\n"));
284 fprintf (stream
, _("\
285 --Wnuh synonym for --no-warn-unmatched-high\n"));
288 fprintf (stream
, _("\
289 --relax create linker relaxable code\n"));
290 fprintf (stream
, _("\
291 --cpu-desc provide runtime cpu description file\n"));
295 static void fill_insn
PARAMS ((int));
296 static void m32r_scomm
PARAMS ((int));
297 static void debug_sym
PARAMS ((int));
298 static void expand_debug_syms
PARAMS ((sym_linkS
*, int));
300 /* Set by md_assemble for use by m32r_fill_insn. */
301 static subsegT prev_subseg
;
302 static segT prev_seg
;
304 /* The target specific pseudo-ops which we support. */
305 const pseudo_typeS md_pseudo_table
[] =
308 { "fillinsn", fill_insn
, 0 },
309 { "scomm", m32r_scomm
, 0 },
310 { "debugsym", debug_sym
, 0 },
311 /* start-sanitize-m32rx */
312 { "m32r", allow_m32rx
, 0 },
313 { "m32rx", allow_m32rx
, 1 },
314 /* end-sanitize-m32rx */
318 /* FIXME: Should be machine generated. */
319 #define NOP_INSN 0x7000
320 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
322 /* When we align the .text section, insert the correct NOP pattern.
323 N is the power of 2 alignment. LEN is the length of pattern FILL.
324 MAX is the maximum number of characters to skip when doing the alignment,
325 or 0 if there is no maximum. */
328 m32r_do_align (n
, fill
, len
, max
)
334 if ((fill
== NULL
|| (* fill
== 0 && len
== 1))
335 && (now_seg
->flags
& SEC_CODE
) != 0
336 /* Only do this special handling if aligning to at least a
339 /* Only do this special handling if we're allowed to emit at
341 && (max
== 0 || max
> 1))
343 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
346 /* First align to a 2 byte boundary, in case there is an odd .byte. */
347 /* FIXME: How much memory will cause gas to use when assembling a big
348 program? Perhaps we can avoid the frag_align call? */
349 frag_align (1, 0, 0);
351 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
353 frag_align_pattern (2, nop_pattern
, sizeof nop_pattern
, 0);
354 /* If doing larger alignments use a repeating sequence of appropriate
358 static const unsigned char multi_nop_pattern
[] =
359 { 0x70, 0x00, 0xf0, 0x00 };
360 frag_align_pattern (n
, multi_nop_pattern
, sizeof multi_nop_pattern
,
370 assemble_nop (opcode
)
373 char * f
= frag_more (2);
374 md_number_to_chars (f
, opcode
, 2);
377 /* If the last instruction was the first of 2 16 bit insns,
378 output a nop to move the PC to a 32 bit boundary.
380 This is done via an alignment specification since branch relaxing
381 may make it unnecessary.
383 Internally, we need to output one of these each time a 32 bit insn is
384 seen after an insn that is relaxable. */
390 (void) m32r_do_align (2, NULL
, 0, 0);
391 prev_insn
.insn
= NULL
;
392 seen_relaxable_p
= 0;
395 /* Record the symbol so that when we output the insn, we can create
396 a symbol that is at the start of the instruction. This is used
397 to emit the label for the start of a breakpoint without causing
398 the assembler to emit a NOP if the previous instruction was a
399 16 bit instruction. */
407 register char *end_name
;
408 register symbolS
*symbolP
;
409 register sym_linkS
*link
;
411 name
= input_line_pointer
;
412 delim
= get_symbol_end ();
413 end_name
= input_line_pointer
;
415 if ((symbolP
= symbol_find (name
)) == NULL
416 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
418 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
421 symbol_table_insert (symbolP
);
422 if (S_IS_DEFINED (symbolP
) && S_GET_SEGMENT (symbolP
) != reg_section
)
423 /* xgettext:c-format */
424 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
428 link
= (sym_linkS
*) xmalloc (sizeof (sym_linkS
));
429 link
->symbol
= symbolP
;
430 link
->next
= debug_sym_link
;
431 debug_sym_link
= link
;
436 demand_empty_rest_of_line ();
439 /* Second pass to expanding the debug symbols, go through linked
440 list of symbols and reassign the address. */
443 expand_debug_syms (syms
, align
)
447 char *save_input_line
= input_line_pointer
;
448 sym_linkS
*next_syms
;
454 (void) m32r_do_align (align
, NULL
, 0, 0);
455 for (; syms
!= (sym_linkS
*)0; syms
= next_syms
)
457 symbolS
*symbolP
= syms
->symbol
;
458 next_syms
= syms
->next
;
459 input_line_pointer
= ".\n";
460 pseudo_set (symbolP
);
464 input_line_pointer
= save_input_line
;
467 /* Cover function to fill_insn called after a label and at end of assembly.
468 The result is always 1: we're called in a conditional to see if the
469 current line is a label. */
472 m32r_fill_insn (done
)
475 if (prev_seg
!= NULL
)
478 subsegT subseg
= now_subseg
;
480 subseg_set (prev_seg
, prev_subseg
);
484 subseg_set (seg
, subseg
);
497 /* Initialize the `cgen' interface. */
499 /* This is a callback from cgen to gas to parse operands. */
500 cgen_parse_operand_fn
= cgen_parse_operand
;
502 /* Set the machine number and endian. */
503 CGEN_SYM (init_asm
) (0 /* mach number */,
505 CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE
);
507 #if 0 /* not supported yet */
508 /* If a runtime cpu description file was provided, parse it. */
509 if (m32r_cpu_desc
!= NULL
)
513 errmsg
= cgen_read_cpu_file (m32r_cpu_desc
);
515 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
519 /* Save the current subseg so we can restore it [it's the default one and
520 we don't want the initial section to be .sbss]. */
524 /* The sbss section is for local .scomm symbols. */
525 sbss_section
= subseg_new (".sbss", 0);
527 /* This is copied from perform_an_assembly_pass. */
528 applicable
= bfd_applicable_section_flags (stdoutput
);
529 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
531 #if 0 /* What does this do? [see perform_an_assembly_pass] */
532 seg_info (bss_section
)->bss
= 1;
535 subseg_set (seg
, subseg
);
537 /* We must construct a fake section similar to bfd_com_section
538 but with the name .scommon. */
539 scom_section
= bfd_com_section
;
540 scom_section
.name
= ".scommon";
541 scom_section
.output_section
= & scom_section
;
542 scom_section
.symbol
= & scom_symbol
;
543 scom_section
.symbol_ptr_ptr
= & scom_section
.symbol
;
544 scom_symbol
= * bfd_com_section
.symbol
;
545 scom_symbol
.name
= ".scommon";
546 scom_symbol
.section
= & scom_section
;
548 /* start-sanitize-m32rx */
549 allow_m32rx (enable_m32rx
);
550 /* end-sanitize-m32rx */
553 /* start-sanitize-m32rx */
555 #define OPERAND_IS_COND_BIT(operand, indices, index) \
556 (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \
557 || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \
558 && (indices [index] == 0 || indices [index] == 1)))
560 /* Returns true if an output of instruction 'a' is referenced by an operand
561 of instruction 'b'. If 'check_outputs' is true then b's outputs are
562 checked, otherwise its inputs are examined. */
565 first_writes_to_seconds_operands (a
, b
, check_outputs
)
568 const int check_outputs
;
570 const CGEN_OPERAND_INSTANCE
* a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
571 const CGEN_OPERAND_INSTANCE
* b_ops
= CGEN_INSN_OPERANDS (b
->insn
);
574 /* If at least one of the instructions takes no operands, then there is
575 nothing to check. There really are instructions without operands,
577 if (a_operands
== NULL
|| b_ops
== NULL
)
580 /* Scan the operand list of 'a' looking for an output operand. */
582 CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
;
583 a_index
++, a_operands
++)
585 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) == CGEN_OPERAND_INSTANCE_OUTPUT
)
588 const CGEN_OPERAND_INSTANCE
* b_operands
= b_ops
;
591 The Condition bit 'C' is a shadow of the CBR register (control
592 register 1) and also a shadow of bit 31 of the program status
593 word (control register 0). For now this is handled here, rather
596 if (OPERAND_IS_COND_BIT (a_operands
, a
->indices
, a_index
))
598 /* Scan operand list of 'b' looking for another reference to the
599 condition bit, which goes in the right direction. */
601 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
602 b_index
++, b_operands
++)
604 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
605 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
606 && OPERAND_IS_COND_BIT (b_operands
, b
->indices
, b_index
))
612 /* Scan operand list of 'b' looking for an operand that
613 references the same hardware element, and which goes in the
616 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
617 b_index
++, b_operands
++)
619 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
620 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
621 && (CGEN_OPERAND_INSTANCE_HW (b_operands
) == CGEN_OPERAND_INSTANCE_HW (a_operands
))
622 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
632 /* Returns true if the insn can (potentially) alter the program counter. */
638 #if 0 /* Once PC operands are working.... */
639 const CGEN_OPERAND_INSTANCE
* a_operands
== CGEN_INSN_OPERANDS (a
->insn
);
641 if (a_operands
== NULL
)
644 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
)
646 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
) != NULL
647 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
)) == M32R_OPERAND_PC
)
653 if (CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_UNCOND_CTI
)
654 || CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_COND_CTI
))
660 /* Returns NULL if the two 16 bit insns can be executed in parallel,
661 otherwise it returns a pointer to an error message explaining why not. */
664 can_make_parallel (a
, b
)
671 /* Make sure the instructions are the right length. */
672 if ( CGEN_FIELDS_BITSIZE (& a
->fields
) != 16
673 || CGEN_FIELDS_BITSIZE (& b
->fields
) != 16)
676 if (first_writes_to_seconds_operands (a
, b
, true))
677 return _("Instructions write to the same destination register.");
679 a_pipe
= CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_PIPE
);
680 b_pipe
= CGEN_INSN_ATTR (b
->insn
, CGEN_INSN_PIPE
);
682 /* Make sure that the instructions use the correct execution pipelines. */
683 if ( a_pipe
== PIPE_NONE
684 || b_pipe
== PIPE_NONE
)
685 return _("Instructions do not use parallel execution pipelines.");
687 /* Leave this test for last, since it is the only test that can
688 go away if the instructions are swapped, and we want to make
689 sure that any other errors are detected before this happens. */
690 if ( a_pipe
== PIPE_S
692 return _("Instructions share the same execution pipeline");
700 make_parallel (buffer
)
701 cgen_insn_t
* buffer
;
703 /* Force the top bit of the second insn to be set. */
707 if (CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
)
709 value
= bfd_getb16 ((bfd_byte
*) buffer
);
711 bfd_putb16 (value
, (char *) buffer
);
715 value
= bfd_getl16 ((bfd_byte
*) buffer
);
717 bfd_putl16 (value
, (char *) buffer
);
724 make_parallel (buffer
)
727 /* Force the top bit of the second insn to be set. */
729 buffer
[CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
? 0 : 1] |= 0x80;
732 #endif /* ! CGEN_INT_INSN */
735 assemble_parallel_insn (str
, str2
)
744 * str2
= 0; /* Seperate the two instructions. */
746 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
747 so that the parallel instruction will start on a 32 bit boundary. */
751 first
.debug_sym_link
= debug_sym_link
;
752 debug_sym_link
= (sym_linkS
*)0;
754 /* Parse the first instruction. */
755 if (! (first
.insn
= CGEN_SYM (assemble_insn
)
756 (str
, & first
.fields
, first
.buffer
, & errmsg
)))
763 && CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_SPECIAL
))
765 /* xgettext:c-format */
766 as_bad (_("unknown instruction '%s'"), str
);
769 else if (! enable_m32rx
770 /* FIXME: Need standard macro to perform this test. */
771 && CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
773 /* xgettext:c-format */
774 as_bad (_("instruction '%s' is for the M32RX only"), str
);
778 /* Check to see if this is an allowable parallel insn. */
779 if (CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
781 /* xgettext:c-format */
782 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
786 *str2
= '|'; /* Restore the original assembly text, just in case it is needed. */
787 str3
= str
; /* Save the original string pointer. */
788 str
= str2
+ 2; /* Advanced past the parsed string. */
789 str2
= str3
; /* Remember the entire string in case it is needed for error messages. */
791 /* Preserve any fixups that have been generated and reset the list to empty. */
794 /* Get the indices of the operands of the instruction. */
795 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
796 doesn't seem right. Perhaps allow passing fields like we do insn. */
797 /* FIXME: ALIAS insns do not have operands, so we use this function
798 to find the equivalent insn and overwrite the value stored in our
799 structure. We still need the original insn, however, since this
800 may have certain attributes that are not present in the unaliased
801 version (eg relaxability). When aliases behave differently this
802 may have to change. */
803 first
.orig_insn
= first
.insn
;
804 first
.insn
= m32r_cgen_lookup_get_insn_operands
805 (NULL
, bfd_getb16 ((char *) first
.buffer
), 16, first
.indices
);
807 if (first
.insn
== NULL
)
808 as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for first insn"));
810 second
.debug_sym_link
= NULL
;
812 /* Parse the second instruction. */
813 if (! (second
.insn
= CGEN_SYM (assemble_insn
)
814 (str
, & second
.fields
, second
.buffer
, & errmsg
)))
822 && CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_SPECIAL
))
824 /* xgettext:c-format */
825 as_bad (_("unknown instruction '%s'"), str
);
828 else if (! enable_m32rx
829 && CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
831 /* xgettext:c-format */
832 as_bad (_("instruction '%s' is for the M32RX only"), str
);
836 /* Check to see if this is an allowable parallel insn. */
837 if (CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
839 /* xgettext:c-format */
840 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
846 if (CGEN_INSN_NUM (first
.insn
) != M32R_INSN_NOP
847 && CGEN_INSN_NUM (second
.insn
) != M32R_INSN_NOP
)
849 /* xgettext:c-format */
850 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2
);
855 /* Get the indices of the operands of the instruction. */
856 second
.orig_insn
= second
.insn
;
857 second
.insn
= m32r_cgen_lookup_get_insn_operands
858 (NULL
, bfd_getb16 ((char *) second
.buffer
), 16, second
.indices
);
860 if (second
.insn
== NULL
)
861 as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for second insn"));
863 /* We assume that if the first instruction writes to a register that is
864 read by the second instruction it is because the programmer intended
865 this to happen, (after all they have explicitly requested that these
866 two instructions be executed in parallel). Although if the global
867 variable warn_explicit_parallel_conflicts is true then we do generate
868 a warning message. Similarly we assume that parallel branch and jump
869 instructions are deliberate and should not produce errors. */
871 if (warn_explicit_parallel_conflicts
)
873 if (first_writes_to_seconds_operands (& first
, & second
, false))
874 /* xgettext:c-format */
875 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2
);
877 if (first_writes_to_seconds_operands (& second
, & first
, false))
878 /* xgettext:c-format */
879 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2
);
882 if ((errmsg
= (char *) can_make_parallel (& first
, & second
)) == NULL
)
884 /* Get the fixups for the first instruction. */
888 expand_debug_syms (first
.debug_sym_link
, 1);
889 cgen_asm_finish_insn (first
.orig_insn
, first
.buffer
,
890 CGEN_FIELDS_BITSIZE (& first
.fields
), 0, NULL
);
892 /* Force the top bit of the second insn to be set. */
893 make_parallel (second
.buffer
);
895 /* Get its fixups. */
896 cgen_restore_fixups ();
899 expand_debug_syms (second
.debug_sym_link
, 1);
900 cgen_asm_finish_insn (second
.orig_insn
, second
.buffer
,
901 CGEN_FIELDS_BITSIZE (& second
.fields
), 0, NULL
);
903 /* Try swapping the instructions to see if they work that way. */
904 else if (can_make_parallel (& second
, & first
) == NULL
)
906 /* Write out the second instruction first. */
907 expand_debug_syms (second
.debug_sym_link
, 1);
908 cgen_asm_finish_insn (second
.orig_insn
, second
.buffer
,
909 CGEN_FIELDS_BITSIZE (& second
.fields
), 0, NULL
);
911 /* Force the top bit of the first instruction to be set. */
912 make_parallel (first
.buffer
);
914 /* Get the fixups for the first instruction. */
915 cgen_restore_fixups ();
917 /* Write out the first instruction. */
918 expand_debug_syms (first
.debug_sym_link
, 1);
919 cgen_asm_finish_insn (first
.orig_insn
, first
.buffer
,
920 CGEN_FIELDS_BITSIZE (& first
.fields
), 0, NULL
);
924 as_bad ("'%s': %s", str2
, errmsg
);
928 /* Set these so m32r_fill_insn can use them. */
930 prev_subseg
= now_subseg
;
933 /* end-sanitize-m32rx */
944 /* Initialize GAS's cgen interface for a new instruction. */
945 cgen_asm_init_parse ();
947 /* start-sanitize-m32rx */
948 /* Look for a parallel instruction seperator. */
949 if ((str2
= strstr (str
, "||")) != NULL
)
951 assemble_parallel_insn (str
, str2
);
954 /* end-sanitize-m32rx */
956 insn
.debug_sym_link
= debug_sym_link
;
957 debug_sym_link
= (sym_linkS
*)0;
959 insn
.insn
= CGEN_SYM (assemble_insn
)
960 (str
, & insn
.fields
, insn
.buffer
, & errmsg
);
968 /* start-sanitize-m32rx */
970 && CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_SPECIAL
))
972 /* xgettext:c-format */
973 as_bad (_("unknown instruction '%s'"), str
);
976 else if (! enable_m32rx
977 && CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
979 /* xgettext:c-format */
980 as_bad (_("instruction '%s' is for the M32RX only"), str
);
983 /* end-sanitize-m32rx */
985 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
987 /* 32 bit insns must live on 32 bit boundaries. */
988 if (prev_insn
.insn
|| seen_relaxable_p
)
990 /* ??? If calling fill_insn too many times turns us into a memory
991 pig, can we call assemble_nop instead of !seen_relaxable_p? */
995 expand_debug_syms (insn
.debug_sym_link
, 2);
997 /* Doesn't really matter what we pass for RELAX_P here. */
998 cgen_asm_finish_insn (insn
.insn
, insn
.buffer
,
999 CGEN_FIELDS_BITSIZE (& insn
.fields
), 1, NULL
);
1003 int on_32bit_boundary_p
;
1004 /* start-sanitize-m32rx */
1006 /* end-sanitize-m32rx */
1008 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
1011 insn
.orig_insn
= insn
.insn
;
1012 /* start-sanitize-m32rx */
1015 /* Get the indices of the operands of the instruction.
1016 FIXME: See assemble_parallel for notes on orig_insn. */
1017 insn
.insn
= m32r_cgen_lookup_get_insn_operands
1018 (NULL
, bfd_getb16 ((char *) insn
.buffer
), 16, insn
.indices
);
1020 if (insn
.insn
== NULL
)
1021 as_fatal (_("internal error: m32r_cgen_get_insn_operands failed"));
1023 /* end-sanitize-m32rx */
1025 /* Compute whether we're on a 32 bit boundary or not.
1026 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1027 on_32bit_boundary_p
= prev_insn
.insn
== NULL
;
1029 /* start-sanitize-m32rx */
1030 /* Look to see if this instruction can be combined with the
1031 previous instruction to make one, parallel, 32 bit instruction.
1032 If the previous instruction (potentially) changed the flow of
1033 program control, then it cannot be combined with the current
1034 instruction. If the current instruction is relaxable, then it
1035 might be replaced with a longer version, so we cannot combine it.
1036 Also if the output of the previous instruction is used as an
1037 input to the current instruction then it cannot be combined.
1038 Otherwise call can_make_parallel() with both orderings of the
1039 instructions to see if they can be combined. */
1040 if ( ! on_32bit_boundary_p
1043 && CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) == 0
1044 && ! writes_to_pc (& prev_insn
)
1045 && ! first_writes_to_seconds_operands (& prev_insn
, &insn
, false)
1048 if (can_make_parallel (& prev_insn
, & insn
) == NULL
)
1049 make_parallel (insn
.buffer
);
1050 else if (can_make_parallel (& insn
, & prev_insn
) == NULL
)
1053 /* end-sanitize-m32rx */
1055 expand_debug_syms (insn
.debug_sym_link
, 1);
1061 /* Ensure each pair of 16 bit insns is in the same frag. */
1064 cgen_asm_finish_insn (insn
.orig_insn
, insn
.buffer
,
1065 CGEN_FIELDS_BITSIZE (& insn
.fields
),
1066 1 /*relax_p*/, &fi
);
1067 insn
.addr
= fi
.addr
;
1068 insn
.frag
= fi
.frag
;
1069 insn
.num_fixups
= fi
.num_fixups
;
1070 for (i
= 0; i
< fi
.num_fixups
; ++i
)
1071 insn
.fixups
[i
] = fi
.fixups
[i
];
1074 /* start-sanitize-m32rx */
1079 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1081 /* Swap the two insns */
1082 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
1083 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
1085 make_parallel (insn
.addr
);
1087 /* Swap any relaxable frags recorded for the two insns. */
1088 /* FIXME: Clarify. relaxation precludes parallel insns */
1089 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
1090 prev_insn
.frag
->fr_opcode
= insn
.addr
;
1091 else if (insn
.frag
->fr_opcode
== insn
.addr
)
1092 insn
.frag
->fr_opcode
= prev_insn
.addr
;
1094 /* Update the addresses in any fixups.
1095 Note that we don't have to handle the case where each insn is in
1096 a different frag as we ensure they're in the same frag above. */
1097 for (i
= 0; i
< prev_insn
.num_fixups
; ++i
)
1098 prev_insn
.fixups
[i
]->fx_where
+= 2;
1099 for (i
= 0; i
< insn
.num_fixups
; ++i
)
1100 insn
.fixups
[i
]->fx_where
-= 2;
1102 /* end-sanitize-m32rx */
1104 /* Keep track of whether we've seen a pair of 16 bit insns.
1105 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1106 if (on_32bit_boundary_p
)
1109 prev_insn
.insn
= NULL
;
1111 /* If the insn needs the following one to be on a 32 bit boundary
1112 (e.g. subroutine calls), fill this insn's slot. */
1113 if (on_32bit_boundary_p
1114 && CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_FILL_SLOT
) != 0)
1117 /* If this is a relaxable insn (can be replaced with a larger version)
1118 mark the fact so that we can emit an alignment directive for a
1119 following 32 bit insn if we see one. */
1120 if (CGEN_INSN_ATTR (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) != 0)
1121 seen_relaxable_p
= 1;
1124 /* Set these so m32r_fill_insn can use them. */
1126 prev_subseg
= now_subseg
;
1129 /* The syntax in the manual says constants begin with '#'.
1130 We just ignore it. */
1133 md_operand (expressionP
)
1134 expressionS
* expressionP
;
1136 if (* input_line_pointer
== '#')
1138 input_line_pointer
++;
1139 expression (expressionP
);
1144 md_section_align (segment
, size
)
1148 int align
= bfd_get_section_alignment (stdoutput
, segment
);
1149 return ((size
+ (1 << align
) - 1) & (-1 << align
));
1153 md_undefined_symbol (name
)
1159 /* .scomm pseudo-op handler.
1161 This is a new pseudo-op to handle putting objects in .scommon.
1162 By doing this the linker won't need to do any work and more importantly
1163 it removes the implicit -G arg necessary to correctly link the object file.
1170 register char * name
;
1174 register symbolS
* symbolP
;
1178 name
= input_line_pointer
;
1179 c
= get_symbol_end ();
1181 /* just after name is now '\0' */
1182 p
= input_line_pointer
;
1185 if (* input_line_pointer
!= ',')
1187 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1188 ignore_rest_of_line ();
1192 input_line_pointer
++; /* skip ',' */
1193 if ((size
= get_absolute_expression ()) < 0)
1195 /* xgettext:c-format */
1196 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size
);
1197 ignore_rest_of_line ();
1201 /* The third argument to .scomm is the alignment. */
1202 if (* input_line_pointer
!= ',')
1206 ++ input_line_pointer
;
1207 align
= get_absolute_expression ();
1210 as_warn (_("ignoring bad alignment"));
1214 /* Convert to a power of 2 alignment. */
1217 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++ align2
)
1221 as_bad (_("Common alignment not a power of 2"));
1222 ignore_rest_of_line ();
1230 symbolP
= symbol_find_or_make (name
);
1233 if (S_IS_DEFINED (symbolP
))
1235 /* xgettext:c-format */
1236 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1237 S_GET_NAME (symbolP
));
1238 ignore_rest_of_line ();
1242 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
1244 /* xgettext:c-format */
1245 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1246 S_GET_NAME (symbolP
),
1247 (long) S_GET_VALUE (symbolP
),
1250 ignore_rest_of_line ();
1256 segT old_sec
= now_seg
;
1257 int old_subsec
= now_subseg
;
1260 record_alignment (sbss_section
, align2
);
1261 subseg_set (sbss_section
, 0);
1264 frag_align (align2
, 0, 0);
1266 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1267 symbolP
->sy_frag
->fr_symbol
= 0;
1269 symbolP
->sy_frag
= frag_now
;
1271 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1274 S_SET_SIZE (symbolP
, size
);
1275 S_SET_SEGMENT (symbolP
, sbss_section
);
1276 S_CLEAR_EXTERNAL (symbolP
);
1277 subseg_set (old_sec
, old_subsec
);
1281 S_SET_VALUE (symbolP
, (valueT
) size
);
1282 S_SET_ALIGN (symbolP
, align2
);
1283 S_SET_EXTERNAL (symbolP
);
1284 S_SET_SEGMENT (symbolP
, & scom_section
);
1287 demand_empty_rest_of_line ();
1290 /* Interface to relax_segment. */
1292 /* FIXME: Build table by hand, get it working, then machine generate. */
1294 const relax_typeS md_relax_table
[] =
1297 1) most positive reach of this state,
1298 2) most negative reach of this state,
1299 3) how many bytes this mode will add to the size of the current frag
1300 4) which index into the table to try if we can't fit into this one. */
1302 /* The first entry must be unused because an `rlx_more' value of zero ends
1306 /* The displacement used by GAS is from the end of the 2 byte insn,
1307 so we subtract 2 from the following. */
1308 /* 16 bit insn, 8 bit disp -> 10 bit range.
1309 This doesn't handle a branch in the right slot at the border:
1310 the "& -4" isn't taken into account. It's not important enough to
1311 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1313 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1314 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1315 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1316 /* Same thing, but with leading nop for alignment. */
1317 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1321 m32r_relax_frag (fragP
, stretch
)
1325 /* Address of branch insn. */
1326 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1329 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1330 if (fragP
->fr_subtype
== 2)
1332 if ((address
& 3) != 0)
1334 fragP
->fr_subtype
= 3;
1338 else if (fragP
->fr_subtype
== 3)
1340 if ((address
& 3) == 0)
1342 fragP
->fr_subtype
= 2;
1348 growth
= relax_frag (fragP
, stretch
);
1350 /* Long jump on odd halfword boundary? */
1351 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1353 fragP
->fr_subtype
= 3;
1361 /* Return an initial guess of the length by which a fragment must grow to
1362 hold a branch to reach its destination.
1363 Also updates fr_type/fr_subtype as necessary.
1365 Called just before doing relaxation.
1366 Any symbol that is now undefined will not become defined.
1367 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1368 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1369 Although it may not be explicit in the frag, pretend fr_var starts with a
1373 md_estimate_size_before_relax (fragP
, segment
)
1377 int old_fr_fix
= fragP
->fr_fix
;
1378 char * opcode
= fragP
->fr_opcode
;
1380 /* The only thing we have to handle here are symbols outside of the
1381 current segment. They may be undefined or in a different segment in
1382 which case linker scripts may place them anywhere.
1383 However, we can't finish the fragment here and emit the reloc as insn
1384 alignment requirements may move the insn about. */
1386 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1388 /* The symbol is undefined in this segment.
1389 Change the relaxation subtype to the max allowable and leave
1390 all further handling to md_convert_frag. */
1391 fragP
->fr_subtype
= 2;
1393 #if 0 /* Can't use this, but leave in for illustration. */
1394 /* Change 16 bit insn to 32 bit insn. */
1397 /* Increase known (fixed) size of fragment. */
1400 /* Create a relocation for it. */
1401 fix_new (fragP
, old_fr_fix
, 4,
1403 fragP
->fr_offset
, 1 /* pcrel */,
1404 /* FIXME: Can't use a real BFD reloc here.
1405 cgen_md_apply_fix3 can't handle it. */
1406 BFD_RELOC_M32R_26_PCREL
);
1408 /* Mark this fragment as finished. */
1412 const CGEN_INSN
* insn
;
1415 /* Update the recorded insn.
1416 Fortunately we don't have to look very far.
1417 FIXME: Change this to record in the instruction the next higher
1418 relaxable insn to use. */
1419 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1421 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1422 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1424 && CGEN_INSN_ATTR (insn
, CGEN_INSN_RELAX
))
1430 fragP
->fr_cgen
.insn
= insn
;
1436 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
1439 /* *fragP has been relaxed to its final size, and now needs to have
1440 the bytes inside it modified to conform to the new size.
1442 Called after relaxation is finished.
1443 fragP->fr_type == rs_machine_dependent.
1444 fragP->fr_subtype is the subtype of what the address relaxed to. */
1447 md_convert_frag (abfd
, sec
, fragP
)
1453 char * displacement
;
1459 opcode
= fragP
->fr_opcode
;
1461 /* Address opcode resides at in file space. */
1462 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1464 switch (fragP
->fr_subtype
)
1468 displacement
= & opcode
[1];
1473 displacement
= & opcode
[1];
1476 opcode
[2] = opcode
[0] | 0x80;
1477 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1478 opcode_address
+= 2;
1480 displacement
= & opcode
[3];
1486 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1488 /* symbol must be resolved by linker */
1489 if (fragP
->fr_offset
& 3)
1490 as_warn (_("Addend to unresolved symbol not on word boundary."));
1491 addend
= fragP
->fr_offset
>> 2;
1495 /* Address we want to reach in file space. */
1496 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1497 target_address
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
1498 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1501 /* Create a relocation for symbols that must be resolved by the linker.
1502 Otherwise output the completed insn. */
1504 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1506 assert (fragP
->fr_subtype
!= 1);
1507 assert (fragP
->fr_cgen
.insn
!= 0);
1508 cgen_record_fixup (fragP
,
1509 /* Offset of branch insn in frag. */
1510 fragP
->fr_fix
+ extension
- 4,
1511 fragP
->fr_cgen
.insn
,
1513 /* FIXME: quick hack */
1515 CGEN_OPERAND_ENTRY (fragP
->fr_cgen
.opindex
),
1517 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24
),
1519 fragP
->fr_cgen
.opinfo
,
1520 fragP
->fr_symbol
, fragP
->fr_offset
);
1523 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1525 md_number_to_chars (displacement
, (valueT
) addend
,
1526 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1528 fragP
->fr_fix
+= extension
;
1531 /* Functions concerning relocs. */
1533 /* The location from which a PC relative jump should be calculated,
1534 given a PC relative reloc. */
1537 md_pcrel_from_section (fixP
, sec
)
1541 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1542 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1543 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1545 /* The symbol is undefined (or is defined but not in this section).
1546 Let the linker figure it out. */
1550 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1553 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1554 Returns BFD_RELOC_NONE if no reloc type can be found.
1555 *FIXP may be modified if desired. */
1557 bfd_reloc_code_real_type
1558 CGEN_SYM (lookup_reloc
) (insn
, operand
, fixP
)
1559 const CGEN_INSN
* insn
;
1560 const CGEN_OPERAND
* operand
;
1563 switch (CGEN_OPERAND_TYPE (operand
))
1565 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1566 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1567 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1568 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1569 case M32R_OPERAND_HI16
:
1570 case M32R_OPERAND_SLO16
:
1571 case M32R_OPERAND_ULO16
:
1572 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1573 if (fixP
->tc_fix_data
.opinfo
!= 0)
1574 return fixP
->tc_fix_data
.opinfo
;
1577 return BFD_RELOC_NONE
;
1580 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1583 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1588 struct m32r_hi_fixup
* hi_fixup
;
1590 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1591 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1593 hi_fixup
= ((struct m32r_hi_fixup
*)
1594 xmalloc (sizeof (struct m32r_hi_fixup
)));
1595 hi_fixup
->fixp
= fixP
;
1596 hi_fixup
->seg
= now_seg
;
1597 hi_fixup
->next
= m32r_hi_fixup_list
;
1599 m32r_hi_fixup_list
= hi_fixup
;
1602 /* Called while parsing an instruction to create a fixup.
1603 We need to check for HI16 relocs and queue them up for later sorting. */
1606 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1609 const CGEN_INSN
* insn
;
1611 const CGEN_OPERAND
* operand
;
1615 fixS
* fixP
= cgen_record_fixup_exp (frag
, where
, insn
, length
,
1616 operand
, opinfo
, exp
);
1618 switch (CGEN_OPERAND_TYPE (operand
))
1620 case M32R_OPERAND_HI16
:
1621 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1622 if (fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1623 || fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1624 m32r_record_hi16 (fixP
->tc_fix_data
.opinfo
, fixP
, now_seg
);
1631 /* Return BFD reloc type from opinfo field in a fixS.
1632 It's tricky using fx_r_type in m32r_frob_file because the values
1633 are BFD_RELOC_UNUSED + operand number. */
1634 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1636 /* Sort any unmatched HI16 relocs so that they immediately precede
1637 the corresponding LO16 reloc. This is called before md_apply_fix and
1643 struct m32r_hi_fixup
* l
;
1645 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1647 segment_info_type
* seginfo
;
1650 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1651 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1653 /* Check quickly whether the next fixup happens to be a matching low. */
1654 if (l
->fixp
->fx_next
!= NULL
1655 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1656 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1657 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1660 /* Look through the fixups for this segment for a matching `low'.
1661 When we find one, move the high/shigh just in front of it. We do
1662 this in two passes. In the first pass, we try to find a
1663 unique `low'. In the second pass, we permit multiple high's
1664 relocs for a single `low'. */
1665 seginfo
= seg_info (l
->seg
);
1666 for (pass
= 0; pass
< 2; pass
++)
1672 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1674 /* Check whether this is a `low' fixup which matches l->fixp. */
1675 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
1676 && f
->fx_addsy
== l
->fixp
->fx_addsy
1677 && f
->fx_offset
== l
->fixp
->fx_offset
1680 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
1681 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
1682 || prev
->fx_addsy
!= f
->fx_addsy
1683 || prev
->fx_offset
!= f
->fx_offset
))
1687 /* Move l->fixp before f. */
1688 for (pf
= &seginfo
->fix_root
;
1690 pf
= & (* pf
)->fx_next
)
1691 assert (* pf
!= NULL
);
1693 * pf
= l
->fixp
->fx_next
;
1695 l
->fixp
->fx_next
= f
;
1697 seginfo
->fix_root
= l
->fixp
;
1699 prev
->fx_next
= l
->fixp
;
1711 && warn_unmatched_high
)
1712 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1713 _("Unmatched high/shigh reloc"));
1718 /* See whether we need to force a relocation into the output file.
1719 This is used to force out switch and PC relative relocations when
1723 m32r_force_relocation (fix
)
1729 return (fix
->fx_pcrel
1733 /* Write a value out to the object file, using the appropriate endianness. */
1736 md_number_to_chars (buf
, val
, n
)
1741 if (target_big_endian
)
1742 number_to_chars_bigendian (buf
, val
, n
);
1744 number_to_chars_littleendian (buf
, val
, n
);
1747 /* Turn a string in input_line_pointer into a floating point constant of type
1748 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1749 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1752 /* Equal to MAX_PRECISION in atof-ieee.c */
1753 #define MAX_LITTLENUMS 6
1756 md_atof (type
, litP
, sizeP
)
1763 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1764 LITTLENUM_TYPE
* wordP
;
1766 char * atof_ieee ();
1784 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1788 return _("Bad call to md_atof()");
1791 t
= atof_ieee (input_line_pointer
, type
, words
);
1793 input_line_pointer
= t
;
1794 * sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1796 if (target_big_endian
)
1798 for (i
= 0; i
< prec
; i
++)
1800 md_number_to_chars (litP
, (valueT
) words
[i
],
1801 sizeof (LITTLENUM_TYPE
));
1802 litP
+= sizeof (LITTLENUM_TYPE
);
1807 for (i
= prec
- 1; i
>= 0; i
--)
1809 md_number_to_chars (litP
, (valueT
) words
[i
],
1810 sizeof (LITTLENUM_TYPE
));
1811 litP
+= sizeof (LITTLENUM_TYPE
);
1819 m32r_elf_section_change_hook ()
1821 /* If we have reached the end of a section and we have just emitted a
1822 16 bit insn, then emit a nop to make sure that the section ends on
1823 a 32 bit boundary. */
1825 if (prev_insn
.insn
|| seen_relaxable_p
)
1826 (void) m32r_fill_insn (0);