1 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12.
2 Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@nerim.fr)
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "safe-ctype.h"
26 #include "opcode/m68hc11.h"
27 #include "dwarf2dbg.h"
28 #include "elf/m68hc11.h"
30 const char comment_chars
[] = ";!";
31 const char line_comment_chars
[] = "#*";
32 const char line_separator_chars
[] = "";
34 const char EXP_CHARS
[] = "eE";
35 const char FLT_CHARS
[] = "dD";
37 #define STATE_CONDITIONAL_BRANCH (1)
38 #define STATE_PC_RELATIVE (2)
39 #define STATE_INDEXED_OFFSET (3)
40 #define STATE_INDEXED_PCREL (4)
41 #define STATE_XBCC_BRANCH (5)
42 #define STATE_CONDITIONAL_BRANCH_6812 (6)
44 #define STATE_BYTE (0)
45 #define STATE_BITS5 (0)
46 #define STATE_WORD (1)
47 #define STATE_BITS9 (1)
48 #define STATE_LONG (2)
49 #define STATE_BITS16 (2)
50 #define STATE_UNDF (3) /* Symbol undefined in pass1 */
52 /* This macro has no side-effects. */
53 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
54 #define RELAX_STATE(s) ((s) >> 2)
55 #define RELAX_LENGTH(s) ((s) & 3)
57 #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF))
59 /* This table describes how you change sizes for the various types of variable
60 size expressions. This version only supports two kinds. */
63 How far Forward this mode will reach.
64 How far Backward this mode will reach.
65 How many bytes this mode will add to the size of the frag.
66 Which mode to go to if the offset won't fit in this one. */
68 relax_typeS md_relax_table
[] = {
69 {1, 1, 0, 0}, /* First entries aren't used. */
70 {1, 1, 0, 0}, /* For no good reason except. */
71 {1, 1, 0, 0}, /* that the VAX doesn't either. */
75 These insns are translated into b!cc +3 jmp L. */
76 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_WORD
)},
81 /* Relax for bsr <L> and bra <L>.
82 These insns are translated into jsr and jmp. */
83 {(127), (-128), 0, ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_WORD
)},
88 /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */
89 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
)},
90 {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
)},
94 /* Relax for PC relative offset: 5-bits, 9-bits, 16-bits.
95 For the 9-bit case, there will be a -1 correction to take into
96 account the new byte that's why the range is -255..256. */
97 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
)},
98 {(256), (-255), 1, ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
)},
102 /* Relax for dbeq/ibeq/tbeq r,<L>:
103 These insns are translated into db!cc +3 jmp L. */
104 {(255), (-256), 0, ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_WORD
)},
109 /* Relax for bcc <L> on 68HC12.
110 These insns are translated into lbcc <L>. */
111 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_WORD
)},
118 /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */
119 typedef enum register_id
{
131 typedef struct operand
{
138 struct m68hc11_opcode_def
{
144 struct m68hc11_opcode
*opcode
;
147 static struct m68hc11_opcode_def
*m68hc11_opcode_defs
= 0;
148 static int m68hc11_nb_opcode_defs
= 0;
150 typedef struct alias
{
155 static alias alias_opcodes
[] = {
162 /* Local functions. */
163 static register_id reg_name_search
PARAMS ((char *));
164 static register_id register_name
PARAMS ((void));
165 static int cmp_opcode
PARAMS ((struct m68hc11_opcode
*,
166 struct m68hc11_opcode
*));
167 static char *print_opcode_format
PARAMS ((struct m68hc11_opcode
*, int));
168 static char *skip_whites
PARAMS ((char *));
169 static int check_range
PARAMS ((long, int));
170 static void print_opcode_list
PARAMS ((void));
171 static void get_default_target
PARAMS ((void));
172 static void print_insn_format
PARAMS ((char *));
173 static int get_operand
PARAMS ((operand
*, int, long));
174 static void fixup8
PARAMS ((expressionS
*, int, int));
175 static void fixup16
PARAMS ((expressionS
*, int, int));
176 static void fixup24
PARAMS ((expressionS
*, int, int));
177 static unsigned char convert_branch
PARAMS ((unsigned char));
178 static char *m68hc11_new_insn
PARAMS ((int));
179 static void build_dbranch_insn
PARAMS ((struct m68hc11_opcode
*,
180 operand
*, int, int));
181 static int build_indexed_byte
PARAMS ((operand
*, int, int));
182 static int build_reg_mode
PARAMS ((operand
*, int));
184 static struct m68hc11_opcode
*find
185 PARAMS ((struct m68hc11_opcode_def
*, operand
*, int));
186 static struct m68hc11_opcode
*find_opcode
187 PARAMS ((struct m68hc11_opcode_def
*, operand
*, int *));
188 static void build_jump_insn
189 PARAMS ((struct m68hc11_opcode
*, operand
*, int, int));
190 static void build_insn
191 PARAMS ((struct m68hc11_opcode
*, operand
*, int));
192 static int relaxable_symbol
PARAMS ((symbolS
*));
194 /* Pseudo op to indicate a relax group. */
195 static void s_m68hc11_relax
PARAMS((int));
197 /* Pseudo op to control the ELF flags. */
198 static void s_m68hc11_mode
PARAMS ((int));
200 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions
201 are using 'rtc' for returning. It is necessary to use 'call'
202 to invoke them. This is also used by the debugger to correctly
203 find the stack frame. */
204 static void s_m68hc11_mark_symbol
PARAMS ((int));
206 /* Controls whether relative branches can be turned into long branches.
207 When the relative offset is too large, the insn are changed:
215 Setting the flag forbidds this. */
216 static short flag_fixed_branchs
= 0;
218 /* Force to use long jumps (absolute) instead of relative branches. */
219 static short flag_force_long_jumps
= 0;
221 /* Change the direct addressing mode into an absolute addressing mode
222 when the insn does not support direct addressing.
223 For example, "clr *ZD0" is normally not possible and is changed
225 static short flag_strict_direct_addressing
= 1;
227 /* When an opcode has invalid operand, print out the syntax of the opcode
229 static short flag_print_insn_syntax
= 0;
231 /* Dumps the list of instructions with syntax and then exit:
232 1 -> Only dumps the list (sorted by name)
233 2 -> Generate an example (or test) that can be compiled. */
234 static short flag_print_opcodes
= 0;
236 /* Opcode hash table. */
237 static struct hash_control
*m68hc11_hash
;
239 /* Current cpu (either cpu6811 or cpu6812). This is determined automagically
240 by 'get_default_target' by looking at default BFD vector. This is overriden
241 with the -m<cpu> option. */
242 static int current_architecture
= 0;
244 /* Default cpu determined by 'get_default_target'. */
245 static const char *default_cpu
;
247 /* Number of opcodes in the sorted table (filtered by current cpu). */
248 static int num_opcodes
;
250 /* The opcodes sorted by name and filtered by current cpu. */
251 static struct m68hc11_opcode
*m68hc11_sorted_opcodes
;
253 /* ELF flags to set in the output file header. */
254 static int elf_flags
= E_M68HC11_F64
;
256 /* These are the machine dependent pseudo-ops. These are included so
257 the assembler can work on the output from the SUN C compiler, which
260 /* This table describes all the machine specific pseudo-ops the assembler
261 has to support. The fields are:
262 pseudo-op name without dot
263 function to call to execute this pseudo-op
264 Integer arg to pass to the function. */
265 const pseudo_typeS md_pseudo_table
[] = {
266 /* The following pseudo-ops are supported for MRI compatibility. */
269 {"fcc", stringer
, 1},
272 /* Dwarf2 support for Gcc. */
273 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
274 {"loc", dwarf2_directive_loc
, 0},
277 {"xrefb", s_ignore
, 0}, /* Same as xref */
279 /* Gcc driven relaxation. */
280 {"relax", s_m68hc11_relax
, 0},
282 /* .mode instruction (ala SH). */
283 {"mode", s_m68hc11_mode
, 0},
285 /* .far instruction. */
286 {"far", s_m68hc11_mark_symbol
, STO_M68HC12_FAR
},
288 /* .interrupt instruction. */
289 {"interrupt", s_m68hc11_mark_symbol
, STO_M68HC12_INTERRUPT
},
294 /* Options and initialization. */
296 const char *md_shortopts
= "Sm:";
298 struct option md_longopts
[] = {
299 #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
300 {"force-long-branchs", no_argument
, NULL
, OPTION_FORCE_LONG_BRANCH
},
302 #define OPTION_SHORT_BRANCHS (OPTION_MD_BASE + 1)
303 {"short-branchs", no_argument
, NULL
, OPTION_SHORT_BRANCHS
},
305 #define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2)
306 {"strict-direct-mode", no_argument
, NULL
, OPTION_STRICT_DIRECT_MODE
},
308 #define OPTION_PRINT_INSN_SYNTAX (OPTION_MD_BASE + 3)
309 {"print-insn-syntax", no_argument
, NULL
, OPTION_PRINT_INSN_SYNTAX
},
311 #define OPTION_PRINT_OPCODES (OPTION_MD_BASE + 4)
312 {"print-opcodes", no_argument
, NULL
, OPTION_PRINT_OPCODES
},
314 #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5)
315 {"generate-example", no_argument
, NULL
, OPTION_GENERATE_EXAMPLE
},
317 #define OPTION_MSHORT (OPTION_MD_BASE + 6)
318 {"mshort", no_argument
, NULL
, OPTION_MSHORT
},
320 #define OPTION_MLONG (OPTION_MD_BASE + 7)
321 {"mlong", no_argument
, NULL
, OPTION_MLONG
},
323 #define OPTION_MSHORT_DOUBLE (OPTION_MD_BASE + 8)
324 {"mshort-double", no_argument
, NULL
, OPTION_MSHORT_DOUBLE
},
326 #define OPTION_MLONG_DOUBLE (OPTION_MD_BASE + 9)
327 {"mlong-double", no_argument
, NULL
, OPTION_MLONG_DOUBLE
},
329 {NULL
, no_argument
, NULL
, 0}
331 size_t md_longopts_size
= sizeof (md_longopts
);
333 /* Get the target cpu for the assembler. This is based on the configure
334 options and on the -m68hc11/-m68hc12 option. If no option is specified,
335 we must get the default. */
337 m68hc11_arch_format ()
339 get_default_target ();
340 if (current_architecture
& cpu6811
)
341 return "elf32-m68hc11";
343 return "elf32-m68hc12";
346 enum bfd_architecture
349 get_default_target ();
350 if (current_architecture
& cpu6811
)
351 return bfd_arch_m68hc11
;
353 return bfd_arch_m68hc12
;
362 /* Listing header selected according to cpu. */
364 m68hc11_listing_header ()
366 if (current_architecture
& cpu6811
)
367 return "M68HC11 GAS ";
369 return "M68HC12 GAS ";
373 md_show_usage (stream
)
376 get_default_target ();
377 fprintf (stream
, _("\
378 Motorola 68HC11/68HC12/68HCS12 options:\n\
379 -m68hc11 | -m68hc12 |
380 -m68hcs12 specify the processor [default %s]\n\
381 -mshort use 16-bit int ABI (default)\n\
382 -mlong use 32-bit int ABI\n\
383 -mshort-double use 32-bit double ABI\n\
384 -mlong-double use 64-bit double ABI (default)\n\
385 --force-long-branchs always turn relative branchs into absolute ones\n\
386 -S,--short-branchs do not turn relative branchs into absolute ones\n\
387 when the offset is out of range\n\
388 --strict-direct-mode do not turn the direct mode into extended mode\n\
389 when the instruction does not support direct mode\n\
390 --print-insn-syntax print the syntax of instruction in case of error\n\
391 --print-opcodes print the list of instructions with syntax\n\
392 --generate-example generate an example of each instruction\n\
393 (used for testing)\n"), default_cpu
);
397 /* Try to identify the default target based on the BFD library. */
399 get_default_target ()
401 const bfd_target
*target
;
404 if (current_architecture
!= 0)
407 default_cpu
= "unknown";
408 target
= bfd_find_target (0, &abfd
);
409 if (target
&& target
->name
)
411 if (strcmp (target
->name
, "elf32-m68hc12") == 0)
413 current_architecture
= cpu6812
;
414 default_cpu
= "m68hc12";
416 else if (strcmp (target
->name
, "elf32-m68hc11") == 0)
418 current_architecture
= cpu6811
;
419 default_cpu
= "m68hc11";
423 as_bad (_("Default target `%s' is not supported."), target
->name
);
429 m68hc11_print_statistics (file
)
433 struct m68hc11_opcode_def
*opc
;
435 hash_print_statistics (file
, "opcode table", m68hc11_hash
);
437 opc
= m68hc11_opcode_defs
;
438 if (opc
== 0 || m68hc11_nb_opcode_defs
== 0)
441 /* Dump the opcode statistics table. */
442 fprintf (file
, _("Name # Modes Min ops Max ops Modes mask # Used\n"));
443 for (i
= 0; i
< m68hc11_nb_opcode_defs
; i
++, opc
++)
445 fprintf (file
, "%-7.7s %5d %7d %7d 0x%08lx %7d\n",
448 opc
->min_operands
, opc
->max_operands
, opc
->format
, opc
->used
);
453 md_parse_option (c
, arg
)
457 get_default_target ();
460 /* -S means keep external to 2 bit offset rather than 16 bit one. */
461 case OPTION_SHORT_BRANCHS
:
463 flag_fixed_branchs
= 1;
466 case OPTION_FORCE_LONG_BRANCH
:
467 flag_force_long_jumps
= 1;
470 case OPTION_PRINT_INSN_SYNTAX
:
471 flag_print_insn_syntax
= 1;
474 case OPTION_PRINT_OPCODES
:
475 flag_print_opcodes
= 1;
478 case OPTION_STRICT_DIRECT_MODE
:
479 flag_strict_direct_addressing
= 0;
482 case OPTION_GENERATE_EXAMPLE
:
483 flag_print_opcodes
= 2;
487 elf_flags
&= ~E_M68HC11_I32
;
491 elf_flags
|= E_M68HC11_I32
;
494 case OPTION_MSHORT_DOUBLE
:
495 elf_flags
&= ~E_M68HC11_F64
;
498 case OPTION_MLONG_DOUBLE
:
499 elf_flags
|= E_M68HC11_F64
;
503 if (strcasecmp (arg
, "68hc11") == 0)
504 current_architecture
= cpu6811
;
505 else if (strcasecmp (arg
, "68hc12") == 0)
506 current_architecture
= cpu6812
;
507 else if (strcasecmp (arg
, "68hcs12") == 0)
508 current_architecture
= cpu6812
| cpu6812s
;
510 as_bad (_("Option `%s' is not recognized."), arg
);
521 md_undefined_symbol (name
)
522 char *name ATTRIBUTE_UNUSED
;
527 /* Equal to MAX_PRECISION in atof-ieee.c. */
528 #define MAX_LITTLENUMS 6
530 /* Turn a string in input_line_pointer into a floating point constant
531 of type TYPE, and store the appropriate bytes in *LITP. The number
532 of LITTLENUMS emitted is stored in *SIZEP. An error message is
533 returned, or NULL on OK. */
535 md_atof (type
, litP
, sizeP
)
541 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
542 LITTLENUM_TYPE
*wordP
;
573 return _("Bad call to MD_ATOF()");
575 t
= atof_ieee (input_line_pointer
, type
, words
);
577 input_line_pointer
= t
;
579 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
580 for (wordP
= words
; prec
--;)
582 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
583 litP
+= sizeof (LITTLENUM_TYPE
);
589 md_section_align (seg
, addr
)
593 int align
= bfd_get_section_alignment (stdoutput
, seg
);
594 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
598 cmp_opcode (op1
, op2
)
599 struct m68hc11_opcode
*op1
;
600 struct m68hc11_opcode
*op2
;
602 return strcmp (op1
->name
, op2
->name
);
605 #define IS_CALL_SYMBOL(MODE) \
606 (((MODE) & (M6812_OP_PAGE|M6811_OP_IND16)) \
607 == ((M6812_OP_PAGE|M6811_OP_IND16)))
609 /* Initialize the assembler. Create the opcode hash table
610 (sorted on the names) with the M6811 opcode table
611 (from opcode library). */
615 char *prev_name
= "";
616 struct m68hc11_opcode
*opcodes
;
617 struct m68hc11_opcode_def
*opc
= 0;
620 get_default_target ();
622 m68hc11_hash
= hash_new ();
624 /* Get a writable copy of the opcode table and sort it on the names. */
625 opcodes
= (struct m68hc11_opcode
*) xmalloc (m68hc11_num_opcodes
*
628 m68hc11_sorted_opcodes
= opcodes
;
630 for (i
= 0; i
< m68hc11_num_opcodes
; i
++)
632 if (m68hc11_opcodes
[i
].arch
& current_architecture
)
634 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
635 if (opcodes
[num_opcodes
].name
[0] == 'b'
636 && opcodes
[num_opcodes
].format
& M6811_OP_JUMP_REL
637 && !(opcodes
[num_opcodes
].format
& M6811_OP_BITMASK
))
640 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
643 for (j
= 0; alias_opcodes
[j
].name
!= 0; j
++)
644 if (strcmp (m68hc11_opcodes
[i
].name
, alias_opcodes
[j
].name
) == 0)
646 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
647 opcodes
[num_opcodes
].name
= alias_opcodes
[j
].alias
;
653 qsort (opcodes
, num_opcodes
, sizeof (struct m68hc11_opcode
),
654 (int (*) PARAMS ((const PTR
, const PTR
))) cmp_opcode
);
656 opc
= (struct m68hc11_opcode_def
*)
657 xmalloc (num_opcodes
* sizeof (struct m68hc11_opcode_def
));
658 m68hc11_opcode_defs
= opc
--;
660 /* Insert unique names into hash table. The M6811 instruction set
661 has several identical opcode names that have different opcodes based
662 on the operands. This hash table then provides a quick index to
663 the first opcode with a particular name in the opcode table. */
664 for (i
= 0; i
< num_opcodes
; i
++, opcodes
++)
668 if (strcmp (prev_name
, opcodes
->name
))
670 prev_name
= (char *) opcodes
->name
;
674 opc
->min_operands
= 100;
675 opc
->max_operands
= 0;
677 opc
->opcode
= opcodes
;
679 hash_insert (m68hc11_hash
, opcodes
->name
, (char *) opc
);
682 opc
->format
|= opcodes
->format
;
684 /* See how many operands this opcode needs. */
686 if (opcodes
->format
& M6811_OP_MASK
)
688 if (opcodes
->format
& M6811_OP_BITMASK
)
690 if (opcodes
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
692 if (opcodes
->format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
694 /* Special case for call instruction. */
695 if ((opcodes
->format
& M6812_OP_PAGE
)
696 && !(opcodes
->format
& M6811_OP_IND16
))
699 if (expect
< opc
->min_operands
)
700 opc
->min_operands
= expect
;
701 if (IS_CALL_SYMBOL (opcodes
->format
))
703 if (expect
> opc
->max_operands
)
704 opc
->max_operands
= expect
;
707 m68hc11_nb_opcode_defs
= opc
- m68hc11_opcode_defs
;
709 if (flag_print_opcodes
)
711 print_opcode_list ();
717 m68hc11_init_after_args ()
723 /* Return a string that represents the operand format for the instruction.
724 When example is true, this generates an example of operand. This is used
725 to give an example and also to generate a test. */
727 print_opcode_format (opcode
, example
)
728 struct m68hc11_opcode
*opcode
;
731 static char buf
[128];
732 int format
= opcode
->format
;
737 if (format
& M6811_OP_IMM8
)
740 sprintf (p
, "#%d", rand () & 0x0FF);
742 strcpy (p
, _("#<imm8>"));
746 if (format
& M6811_OP_IMM16
)
749 sprintf (p
, "#%d", rand () & 0x0FFFF);
751 strcpy (p
, _("#<imm16>"));
755 if (format
& M6811_OP_IX
)
758 sprintf (p
, "%d,X", rand () & 0x0FF);
760 strcpy (p
, _("<imm8>,X"));
764 if (format
& M6811_OP_IY
)
767 sprintf (p
, "%d,X", rand () & 0x0FF);
769 strcpy (p
, _("<imm8>,X"));
773 if (format
& M6812_OP_IDX
)
776 sprintf (p
, "%d,X", rand () & 0x0FF);
782 if (format
& M6812_OP_PAGE
)
785 sprintf (p
, ", %d", rand () & 0x0FF);
787 strcpy (p
, ", <page>");
791 if (format
& M6811_OP_DIRECT
)
794 sprintf (p
, "*Z%d", rand () & 0x0FF);
796 strcpy (p
, _("*<abs8>"));
800 if (format
& M6811_OP_BITMASK
)
806 sprintf (p
, "#$%02x", rand () & 0x0FF);
808 strcpy (p
, _("#<mask>"));
811 if (format
& M6811_OP_JUMP_REL
)
815 if (format
& M6811_OP_IND16
)
818 sprintf (p
, _("symbol%d"), rand () & 0x0FF);
820 strcpy (p
, _("<abs>"));
825 if (format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
829 if (format
& M6811_OP_BITMASK
)
831 sprintf (p
, ".+%d", rand () & 0x7F);
835 sprintf (p
, "L%d", rand () & 0x0FF);
839 strcpy (p
, _("<label>"));
845 /* Prints the list of instructions with the possible operands. */
850 char *prev_name
= "";
851 struct m68hc11_opcode
*opcodes
;
852 int example
= flag_print_opcodes
== 2;
855 printf (_("# Example of `%s' instructions\n\t.sect .text\n_start:\n"),
858 opcodes
= m68hc11_sorted_opcodes
;
860 /* Walk the list sorted on names (by md_begin). We only report
861 one instruction per line, and we collect the different operand
863 for (i
= 0; i
< num_opcodes
; i
++, opcodes
++)
865 char *fmt
= print_opcode_format (opcodes
, example
);
869 printf ("L%d:\t", i
);
870 printf ("%s %s\n", opcodes
->name
, fmt
);
874 if (strcmp (prev_name
, opcodes
->name
))
879 printf ("%-5.5s ", opcodes
->name
);
880 prev_name
= (char *) opcodes
->name
;
883 printf (" [%s]", fmt
);
889 /* Print the instruction format. This operation is called when some
890 instruction is not correct. Instruction format is printed as an
893 print_insn_format (name
)
896 struct m68hc11_opcode_def
*opc
;
897 struct m68hc11_opcode
*opcode
;
900 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, name
);
903 as_bad (_("Instruction `%s' is not recognized."), name
);
906 opcode
= opc
->opcode
;
908 as_bad (_("Instruction formats for `%s':"), name
);
913 fmt
= print_opcode_format (opcode
, 0);
914 sprintf (buf
, "\t%-5.5s %s", opcode
->name
, fmt
);
919 while (strcmp (opcode
->name
, name
) == 0);
922 /* Analysis of 68HC11 and 68HC12 operands. */
924 /* reg_name_search() finds the register number given its name.
925 Returns the register number or REG_NONE on failure. */
927 reg_name_search (name
)
930 if (strcasecmp (name
, "x") == 0 || strcasecmp (name
, "ix") == 0)
932 if (strcasecmp (name
, "y") == 0 || strcasecmp (name
, "iy") == 0)
934 if (strcasecmp (name
, "a") == 0)
936 if (strcasecmp (name
, "b") == 0)
938 if (strcasecmp (name
, "d") == 0)
940 if (strcasecmp (name
, "sp") == 0)
942 if (strcasecmp (name
, "pc") == 0)
944 if (strcasecmp (name
, "ccr") == 0)
954 while (*p
== ' ' || *p
== '\t')
960 /* Check the string at input_line_pointer
961 to see if it is a valid register name. */
965 register_id reg_number
;
966 char c
, *p
= input_line_pointer
;
968 if (!is_name_beginner (*p
++))
971 while (is_part_of_name (*p
++))
978 /* Look to see if it's in the register table. */
979 reg_number
= reg_name_search (input_line_pointer
);
980 if (reg_number
!= REG_NONE
)
985 input_line_pointer
= p
;
994 /* Parse a string of operands and return an array of expressions.
996 Operand mode[0] mode[1] exp[0] exp[1]
997 #n M6811_OP_IMM16 - O_*
998 *<exp> M6811_OP_DIRECT - O_*
999 .{+-}<exp> M6811_OP_JUMP_REL - O_*
1000 <exp> M6811_OP_IND16 - O_*
1001 ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register
1002 n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register
1003 n,+r M6812_PRE_INC " "
1004 n,r- M6812_POST_DEC " "
1005 n,r+ M6812_POST_INC " "
1006 A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register
1007 [D,r] M6811_OP_D_IDX M6812_OP_REG O_register O_register
1008 [n,r] M6811_OP_D_IDX_2 M6812_OP_REG O_constant O_register */
1010 get_operand (oper
, which
, opmode
)
1015 char *p
= input_line_pointer
;
1019 oper
->exp
.X_op
= O_absent
;
1020 oper
->reg1
= REG_NONE
;
1021 oper
->reg2
= REG_NONE
;
1022 mode
= M6811_OP_NONE
;
1024 p
= skip_whites (p
);
1026 if (*p
== 0 || *p
== '\n' || *p
== '\r')
1028 input_line_pointer
= p
;
1032 if (*p
== '*' && (opmode
& (M6811_OP_DIRECT
| M6811_OP_IND16
)))
1034 mode
= M6811_OP_DIRECT
;
1039 if (!(opmode
& (M6811_OP_IMM8
| M6811_OP_IMM16
| M6811_OP_BITMASK
)))
1041 as_bad (_("Immediate operand is not allowed for operand %d."),
1046 mode
= M6811_OP_IMM16
;
1048 if (strncmp (p
, "%hi", 3) == 0)
1051 mode
|= M6811_OP_HIGH_ADDR
;
1053 else if (strncmp (p
, "%lo", 3) == 0)
1056 mode
|= M6811_OP_LOW_ADDR
;
1059 else if (*p
== '.' && (p
[1] == '+' || p
[1] == '-'))
1062 mode
= M6811_OP_JUMP_REL
;
1066 if (current_architecture
& cpu6811
)
1067 as_bad (_("Indirect indexed addressing is not valid for 68HC11."));
1070 mode
= M6812_OP_D_IDX
;
1071 p
= skip_whites (p
);
1073 else if (*p
== ',') /* Special handling of ,x and ,y. */
1076 input_line_pointer
= p
;
1078 reg
= register_name ();
1079 if (reg
!= REG_NONE
)
1082 oper
->exp
.X_op
= O_constant
;
1083 oper
->exp
.X_add_number
= 0;
1084 oper
->mode
= M6812_OP_IDX
;
1087 as_bad (_("Spurious `,' or bad indirect register addressing mode."));
1090 input_line_pointer
= p
;
1092 if (mode
== M6811_OP_NONE
|| mode
== M6812_OP_D_IDX
)
1093 reg
= register_name ();
1097 if (reg
!= REG_NONE
)
1099 p
= skip_whites (input_line_pointer
);
1100 if (*p
== ']' && mode
== M6812_OP_D_IDX
)
1103 (_("Missing second register or offset for indexed-indirect mode."));
1108 oper
->mode
= mode
| M6812_OP_REG
;
1111 if (mode
== M6812_OP_D_IDX
)
1113 as_bad (_("Missing second register for indexed-indirect mode."));
1120 input_line_pointer
= p
;
1121 reg
= register_name ();
1122 if (reg
!= REG_NONE
)
1124 p
= skip_whites (input_line_pointer
);
1125 if (mode
== M6812_OP_D_IDX
)
1129 as_bad (_("Missing `]' to close indexed-indirect mode."));
1133 oper
->mode
= M6812_OP_D_IDX
;
1135 input_line_pointer
= p
;
1143 /* In MRI mode, isolate the operand because we can't distinguish
1144 operands from comments. */
1149 p
= skip_whites (p
);
1150 while (*p
&& *p
!= ' ' && *p
!= '\t')
1159 /* Parse as an expression. */
1160 expression (&oper
->exp
);
1169 expression (&oper
->exp
);
1172 if (oper
->exp
.X_op
== O_illegal
)
1174 as_bad (_("Illegal operand."));
1177 else if (oper
->exp
.X_op
== O_absent
)
1179 as_bad (_("Missing operand."));
1183 p
= input_line_pointer
;
1185 if (mode
== M6811_OP_NONE
|| mode
== M6811_OP_DIRECT
1186 || mode
== M6812_OP_D_IDX
)
1188 p
= skip_whites (input_line_pointer
);
1192 int possible_mode
= M6811_OP_NONE
;
1193 char *old_input_line
;
1198 /* 68HC12 pre increment or decrement. */
1199 if (mode
== M6811_OP_NONE
)
1203 possible_mode
= M6812_PRE_DEC
;
1208 possible_mode
= M6812_PRE_INC
;
1211 p
= skip_whites (p
);
1213 input_line_pointer
= p
;
1214 reg
= register_name ();
1216 /* Backtrack if we have a valid constant expression and
1217 it does not correspond to the offset of the 68HC12 indexed
1218 addressing mode (as in N,x). */
1219 if (reg
== REG_NONE
&& mode
== M6811_OP_NONE
1220 && possible_mode
!= M6811_OP_NONE
)
1222 oper
->mode
= M6811_OP_IND16
| M6811_OP_JUMP_REL
;
1223 input_line_pointer
= skip_whites (old_input_line
);
1227 if (possible_mode
!= M6811_OP_NONE
)
1228 mode
= possible_mode
;
1230 if ((current_architecture
& cpu6811
)
1231 && possible_mode
!= M6811_OP_NONE
)
1232 as_bad (_("Pre-increment mode is not valid for 68HC11"));
1234 if (which
== 0 && opmode
& M6812_OP_IDX_P2
1235 && reg
!= REG_X
&& reg
!= REG_Y
1236 && reg
!= REG_PC
&& reg
!= REG_SP
)
1239 input_line_pointer
= p
;
1242 if (reg
== REG_NONE
&& mode
!= M6811_OP_DIRECT
1243 && !(mode
== M6811_OP_NONE
&& opmode
& M6811_OP_IND16
))
1245 as_bad (_("Wrong register in register indirect mode."));
1248 if (mode
== M6812_OP_D_IDX
)
1250 p
= skip_whites (input_line_pointer
);
1253 as_bad (_("Missing `]' to close register indirect operand."));
1256 input_line_pointer
= p
;
1258 oper
->mode
= M6812_OP_D_IDX_2
;
1261 if (reg
!= REG_NONE
)
1264 if (mode
== M6811_OP_NONE
)
1266 p
= input_line_pointer
;
1269 mode
= M6812_POST_DEC
;
1271 if (current_architecture
& cpu6811
)
1273 (_("Post-decrement mode is not valid for 68HC11."));
1277 mode
= M6812_POST_INC
;
1279 if (current_architecture
& cpu6811
)
1281 (_("Post-increment mode is not valid for 68HC11."));
1284 mode
= M6812_OP_IDX
;
1286 input_line_pointer
= p
;
1289 mode
|= M6812_OP_IDX
;
1294 input_line_pointer
= old_input_line
;
1297 if (mode
== M6812_OP_D_IDX_2
)
1299 as_bad (_("Invalid indexed indirect mode."));
1304 /* If the mode is not known until now, this is either a label
1305 or an indirect address. */
1306 if (mode
== M6811_OP_NONE
)
1307 mode
= M6811_OP_IND16
| M6811_OP_JUMP_REL
;
1309 p
= input_line_pointer
;
1310 while (*p
== ' ' || *p
== '\t')
1312 input_line_pointer
= p
;
1318 #define M6812_AUTO_INC_DEC (M6812_PRE_INC | M6812_PRE_DEC \
1319 | M6812_POST_INC | M6812_POST_DEC)
1321 /* Checks that the number 'num' fits for a given mode. */
1323 check_range (num
, mode
)
1327 /* Auto increment and decrement are ok for [-8..8] without 0. */
1328 if (mode
& M6812_AUTO_INC_DEC
)
1329 return (num
!= 0 && num
<= 8 && num
>= -8);
1331 /* The 68HC12 supports 5, 9 and 16-bit offsets. */
1332 if (mode
& (M6812_INDEXED_IND
| M6812_INDEXED
| M6812_OP_IDX
))
1333 mode
= M6811_OP_IND16
;
1335 if (mode
& M6812_OP_JUMP_REL16
)
1336 mode
= M6811_OP_IND16
;
1338 mode
&= ~M6811_OP_BRANCH
;
1343 case M6811_OP_DIRECT
:
1344 return (num
>= 0 && num
<= 255) ? 1 : 0;
1346 case M6811_OP_BITMASK
:
1349 return (((num
& 0xFFFFFF00) == 0) || ((num
& 0xFFFFFF00) == 0xFFFFFF00))
1352 case M6811_OP_JUMP_REL
:
1353 return (num
>= -128 && num
<= 127) ? 1 : 0;
1355 case M6811_OP_IND16
:
1356 case M6811_OP_IND16
| M6812_OP_PAGE
:
1357 case M6811_OP_IMM16
:
1358 return (((num
& 0xFFFF0000) == 0) || ((num
& 0xFFFF0000) == 0xFFFF0000))
1361 case M6812_OP_IBCC_MARKER
:
1362 case M6812_OP_TBCC_MARKER
:
1363 case M6812_OP_DBCC_MARKER
:
1364 return (num
>= -256 && num
<= 255) ? 1 : 0;
1366 case M6812_OP_TRAP_ID
:
1367 return ((num
>= 0x30 && num
<= 0x39)
1368 || (num
>= 0x40 && num
<= 0x0ff)) ? 1 : 0;
1375 /* Gas fixup generation. */
1377 /* Put a 1 byte expression described by 'oper'. If this expression contains
1378 unresolved symbols, generate an 8-bit fixup. */
1380 fixup8 (oper
, mode
, opmode
)
1389 if (oper
->X_op
== O_constant
)
1391 if (mode
& M6812_OP_TRAP_ID
1392 && !check_range (oper
->X_add_number
, M6812_OP_TRAP_ID
))
1394 static char trap_id_warn_once
= 0;
1396 as_bad (_("Trap id `%ld' is out of range."), oper
->X_add_number
);
1397 if (trap_id_warn_once
== 0)
1399 trap_id_warn_once
= 1;
1400 as_bad (_("Trap id must be within [0x30..0x39] or [0x40..0xff]."));
1404 if (!(mode
& M6812_OP_TRAP_ID
)
1405 && !check_range (oper
->X_add_number
, mode
))
1407 as_bad (_("Operand out of 8-bit range: `%ld'."), oper
->X_add_number
);
1409 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FF, 1);
1411 else if (oper
->X_op
!= O_register
)
1413 if (mode
& M6812_OP_TRAP_ID
)
1414 as_bad (_("The trap id must be a constant."));
1416 if (mode
== M6811_OP_JUMP_REL
)
1420 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1421 oper
, TRUE
, BFD_RELOC_8_PCREL
);
1422 fixp
->fx_pcrel_adjust
= 1;
1426 /* Now create an 8-bit fixup. If there was some %hi or %lo
1427 modifier, generate the reloc accordingly. */
1428 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1430 ((opmode
& M6811_OP_HIGH_ADDR
)
1431 ? BFD_RELOC_M68HC11_HI8
1432 : ((opmode
& M6811_OP_LOW_ADDR
)
1433 ? BFD_RELOC_M68HC11_LO8
1434 : ((mode
& M6812_OP_PAGE
)
1435 ? BFD_RELOC_M68HC11_PAGE
: BFD_RELOC_8
))));
1437 number_to_chars_bigendian (f
, 0, 1);
1441 as_fatal (_("Operand `%x' not recognized in fixup8."), oper
->X_op
);
1445 /* Put a 2 byte expression described by 'oper'. If this expression contains
1446 unresolved symbols, generate a 16-bit fixup. */
1448 fixup16 (oper
, mode
, opmode
)
1451 int opmode ATTRIBUTE_UNUSED
;
1457 if (oper
->X_op
== O_constant
)
1459 if (!check_range (oper
->X_add_number
, mode
))
1461 as_bad (_("Operand out of 16-bit range: `%ld'."),
1462 oper
->X_add_number
);
1464 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FFFF, 2);
1466 else if (oper
->X_op
!= O_register
)
1470 /* Now create a 16-bit fixup. */
1471 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 2,
1473 (mode
& M6812_OP_JUMP_REL16
? TRUE
: FALSE
),
1474 (mode
& M6812_OP_JUMP_REL16
1475 ? BFD_RELOC_16_PCREL
1476 : (mode
& M6812_OP_PAGE
)
1477 ? BFD_RELOC_M68HC11_LO16
: BFD_RELOC_16
));
1478 number_to_chars_bigendian (f
, 0, 2);
1479 if (mode
& M6812_OP_JUMP_REL16
)
1480 fixp
->fx_pcrel_adjust
= 2;
1484 as_fatal (_("Operand `%x' not recognized in fixup16."), oper
->X_op
);
1488 /* Put a 3 byte expression described by 'oper'. If this expression contains
1489 unresolved symbols, generate a 24-bit fixup. */
1491 fixup24 (oper
, mode
, opmode
)
1494 int opmode ATTRIBUTE_UNUSED
;
1500 if (oper
->X_op
== O_constant
)
1502 if (!check_range (oper
->X_add_number
, mode
))
1504 as_bad (_("Operand out of 16-bit range: `%ld'."),
1505 oper
->X_add_number
);
1507 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FFFFFF, 3);
1509 else if (oper
->X_op
!= O_register
)
1513 /* Now create a 24-bit fixup. */
1514 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 2,
1515 oper
, FALSE
, BFD_RELOC_M68HC11_24
);
1516 number_to_chars_bigendian (f
, 0, 3);
1520 as_fatal (_("Operand `%x' not recognized in fixup16."), oper
->X_op
);
1524 /* 68HC11 and 68HC12 code generation. */
1526 /* Translate the short branch/bsr instruction into a long branch. */
1527 static unsigned char
1528 convert_branch (code
)
1531 if (IS_OPCODE (code
, M6812_BSR
))
1533 else if (IS_OPCODE (code
, M6811_BSR
))
1535 else if (IS_OPCODE (code
, M6811_BRA
))
1536 return (current_architecture
& cpu6812
) ? M6812_JMP
: M6811_JMP
;
1538 as_fatal (_("Unexpected branch conversion with `%x'"), code
);
1540 /* Keep gcc happy. */
1544 /* Start a new insn that contains at least 'size' bytes. Record the
1545 line information of that insn in the dwarf2 debug sections. */
1547 m68hc11_new_insn (size
)
1552 f
= frag_more (size
);
1554 dwarf2_emit_insn (size
);
1559 /* Builds a jump instruction (bra, bcc, bsr). */
1561 build_jump_insn (opcode
, operands
, nb_operands
, jmp_mode
)
1562 struct m68hc11_opcode
*opcode
;
1573 /* The relative branch convertion is not supported for
1575 assert ((opcode
->format
& M6811_OP_BITMASK
) == 0);
1576 assert (nb_operands
== 1);
1577 assert (operands
[0].reg1
== REG_NONE
&& operands
[0].reg2
== REG_NONE
);
1579 code
= opcode
->opcode
;
1581 n
= operands
[0].exp
.X_add_number
;
1583 /* Turn into a long branch:
1584 - when force long branch option (and not for jbcc pseudos),
1585 - when jbcc and the constant is out of -128..127 range,
1586 - when branch optimization is allowed and branch out of range. */
1587 if ((jmp_mode
== 0 && flag_force_long_jumps
)
1588 || (operands
[0].exp
.X_op
== O_constant
1589 && (!check_range (n
, opcode
->format
) &&
1590 (jmp_mode
== 1 || flag_fixed_branchs
== 0))))
1593 where
= frag_now_fix ();
1595 fix_new (frag_now
, frag_now_fix (), 1,
1596 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1598 if (code
== M6811_BSR
|| code
== M6811_BRA
|| code
== M6812_BSR
)
1600 code
= convert_branch (code
);
1602 f
= m68hc11_new_insn (1);
1603 number_to_chars_bigendian (f
, code
, 1);
1605 else if (current_architecture
& cpu6812
)
1607 /* 68HC12: translate the bcc into a lbcc. */
1608 f
= m68hc11_new_insn (2);
1609 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1610 number_to_chars_bigendian (f
+ 1, code
, 1);
1611 fixup16 (&operands
[0].exp
, M6812_OP_JUMP_REL16
,
1612 M6812_OP_JUMP_REL16
);
1617 /* 68HC11: translate the bcc into b!cc +3; jmp <L>. */
1618 f
= m68hc11_new_insn (3);
1620 number_to_chars_bigendian (f
, code
, 1);
1621 number_to_chars_bigendian (f
+ 1, 3, 1);
1622 number_to_chars_bigendian (f
+ 2, M6811_JMP
, 1);
1624 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, M6811_OP_IND16
);
1628 /* Branch with a constant that must fit in 8-bits. */
1629 if (operands
[0].exp
.X_op
== O_constant
)
1631 if (!check_range (n
, opcode
->format
))
1633 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1636 else if (opcode
->format
& M6812_OP_JUMP_REL16
)
1638 f
= m68hc11_new_insn (4);
1639 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1640 number_to_chars_bigendian (f
+ 1, code
, 1);
1641 number_to_chars_bigendian (f
+ 2, n
& 0x0ffff, 2);
1645 f
= m68hc11_new_insn (2);
1646 number_to_chars_bigendian (f
, code
, 1);
1647 number_to_chars_bigendian (f
+ 1, n
& 0x0FF, 1);
1650 else if (opcode
->format
& M6812_OP_JUMP_REL16
)
1653 where
= frag_now_fix ();
1655 fix_new (frag_now
, frag_now_fix (), 1,
1656 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1658 f
= m68hc11_new_insn (2);
1659 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1660 number_to_chars_bigendian (f
+ 1, code
, 1);
1661 fixup16 (&operands
[0].exp
, M6812_OP_JUMP_REL16
, M6812_OP_JUMP_REL16
);
1668 where
= frag_now_fix ();
1670 fix_new (frag_now
, frag_now_fix (), 1,
1671 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1673 /* Branch offset must fit in 8-bits, don't do some relax. */
1674 if (jmp_mode
== 0 && flag_fixed_branchs
)
1676 opcode
= m68hc11_new_insn (1);
1677 number_to_chars_bigendian (opcode
, code
, 1);
1678 fixup8 (&operands
[0].exp
, M6811_OP_JUMP_REL
, M6811_OP_JUMP_REL
);
1681 /* bra/bsr made be changed into jmp/jsr. */
1682 else if (code
== M6811_BSR
|| code
== M6811_BRA
|| code
== M6812_BSR
)
1684 /* Allocate worst case storage. */
1685 opcode
= m68hc11_new_insn (3);
1686 number_to_chars_bigendian (opcode
, code
, 1);
1687 number_to_chars_bigendian (opcode
+ 1, 0, 1);
1688 frag_variant (rs_machine_dependent
, 1, 1,
1689 ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_UNDF
),
1690 operands
[0].exp
.X_add_symbol
, (offsetT
) n
,
1693 else if (current_architecture
& cpu6812
)
1695 opcode
= m68hc11_new_insn (2);
1696 number_to_chars_bigendian (opcode
, code
, 1);
1697 number_to_chars_bigendian (opcode
+ 1, 0, 1);
1698 frag_var (rs_machine_dependent
, 2, 2,
1699 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_UNDF
),
1700 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, opcode
);
1704 opcode
= m68hc11_new_insn (2);
1705 number_to_chars_bigendian (opcode
, code
, 1);
1706 number_to_chars_bigendian (opcode
+ 1, 0, 1);
1707 frag_var (rs_machine_dependent
, 3, 3,
1708 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_UNDF
),
1709 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, opcode
);
1714 /* Builds a dbne/dbeq/tbne/tbeq instruction. */
1716 build_dbranch_insn (opcode
, operands
, nb_operands
, jmp_mode
)
1717 struct m68hc11_opcode
*opcode
;
1726 /* The relative branch convertion is not supported for
1728 assert ((opcode
->format
& M6811_OP_BITMASK
) == 0);
1729 assert (nb_operands
== 2);
1730 assert (operands
[0].reg1
!= REG_NONE
);
1732 code
= opcode
->opcode
& 0x0FF;
1734 f
= m68hc11_new_insn (1);
1735 number_to_chars_bigendian (f
, code
, 1);
1737 n
= operands
[1].exp
.X_add_number
;
1738 code
= operands
[0].reg1
;
1740 if (operands
[0].reg1
== REG_NONE
|| operands
[0].reg1
== REG_CCR
1741 || operands
[0].reg1
== REG_PC
)
1742 as_bad (_("Invalid register for dbcc/tbcc instruction."));
1744 if (opcode
->format
& M6812_OP_IBCC_MARKER
)
1746 else if (opcode
->format
& M6812_OP_TBCC_MARKER
)
1749 if (!(opcode
->format
& M6812_OP_EQ_MARKER
))
1752 /* Turn into a long branch:
1753 - when force long branch option (and not for jbcc pseudos),
1754 - when jdbcc and the constant is out of -256..255 range,
1755 - when branch optimization is allowed and branch out of range. */
1756 if ((jmp_mode
== 0 && flag_force_long_jumps
)
1757 || (operands
[1].exp
.X_op
== O_constant
1758 && (!check_range (n
, M6812_OP_IBCC_MARKER
) &&
1759 (jmp_mode
== 1 || flag_fixed_branchs
== 0))))
1763 number_to_chars_bigendian (f
, code
, 1);
1764 number_to_chars_bigendian (f
+ 1, M6812_JMP
, 1);
1765 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, M6811_OP_IND16
);
1769 /* Branch with a constant that must fit in 9-bits. */
1770 if (operands
[1].exp
.X_op
== O_constant
)
1772 if (!check_range (n
, M6812_OP_IBCC_MARKER
))
1774 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1783 number_to_chars_bigendian (f
, code
, 1);
1784 number_to_chars_bigendian (f
+ 1, n
& 0x0FF, 1);
1789 /* Branch offset must fit in 8-bits, don't do some relax. */
1790 if (jmp_mode
== 0 && flag_fixed_branchs
)
1792 fixup8 (&operands
[0].exp
, M6811_OP_JUMP_REL
, M6811_OP_JUMP_REL
);
1798 number_to_chars_bigendian (f
, code
, 1);
1799 number_to_chars_bigendian (f
+ 1, 0, 1);
1800 frag_var (rs_machine_dependent
, 3, 3,
1801 ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_UNDF
),
1802 operands
[1].exp
.X_add_symbol
, (offsetT
) n
, f
);
1807 #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4)
1809 /* Assemble the post index byte for 68HC12 extended addressing modes. */
1811 build_indexed_byte (op
, format
, move_insn
)
1813 int format ATTRIBUTE_UNUSED
;
1816 unsigned char byte
= 0;
1821 val
= op
->exp
.X_add_number
;
1823 if (mode
& M6812_AUTO_INC_DEC
)
1826 if (mode
& (M6812_POST_INC
| M6812_POST_DEC
))
1829 if (op
->exp
.X_op
== O_constant
)
1831 if (!check_range (val
, mode
))
1833 as_bad (_("Increment/decrement value is out of range: `%ld'."),
1836 if (mode
& (M6812_POST_INC
| M6812_PRE_INC
))
1837 byte
|= (val
- 1) & 0x07;
1839 byte
|= (8 - ((val
) & 7)) | 0x8;
1844 as_fatal (_("Expecting a register."));
1859 as_bad (_("Invalid register for post/pre increment."));
1864 number_to_chars_bigendian (f
, byte
, 1);
1868 if (mode
& (M6812_OP_IDX
| M6812_OP_D_IDX_2
))
1889 as_bad (_("Invalid register."));
1892 if (op
->exp
.X_op
== O_constant
)
1894 if (!check_range (val
, M6812_OP_IDX
))
1896 as_bad (_("Offset out of 16-bit range: %ld."), val
);
1899 if (move_insn
&& !(val
>= -16 && val
<= 15))
1901 as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."),
1906 if (val
>= -16 && val
<= 15 && !(mode
& M6812_OP_D_IDX_2
))
1911 number_to_chars_bigendian (f
, byte
, 1);
1914 else if (val
>= -256 && val
<= 255 && !(mode
& M6812_OP_D_IDX_2
))
1921 number_to_chars_bigendian (f
, byte
, 1);
1922 number_to_chars_bigendian (f
+ 1, val
& 0x0FF, 1);
1928 if (mode
& M6812_OP_D_IDX_2
)
1934 number_to_chars_bigendian (f
, byte
, 1);
1935 number_to_chars_bigendian (f
+ 1, val
& 0x0FFFF, 2);
1939 if (mode
& M6812_OP_D_IDX_2
)
1941 byte
= (byte
<< 3) | 0xe3;
1943 number_to_chars_bigendian (f
, byte
, 1);
1945 fixup16 (&op
->exp
, 0, 0);
1947 else if (op
->reg1
!= REG_PC
)
1953 number_to_chars_bigendian (f
, byte
, 1);
1954 sym
= op
->exp
.X_add_symbol
;
1955 off
= op
->exp
.X_add_number
;
1956 if (op
->exp
.X_op
!= O_symbol
)
1958 sym
= make_expr_symbol (&op
->exp
);
1961 frag_var (rs_machine_dependent
, 2, 2,
1962 ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_UNDF
),
1968 number_to_chars_bigendian (f
, byte
, 1);
1969 frag_var (rs_machine_dependent
, 2, 2,
1970 ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_UNDF
),
1971 op
->exp
.X_add_symbol
,
1972 op
->exp
.X_add_number
, f
);
1977 if (mode
& (M6812_OP_REG
| M6812_OP_D_IDX
))
1979 if (mode
& M6812_OP_D_IDX
)
1981 if (op
->reg1
!= REG_D
)
1982 as_bad (_("Expecting register D for indexed indirect mode."));
1984 as_bad (_("Indexed indirect mode is not allowed for movb/movw."));
2001 as_bad (_("Invalid accumulator register."));
2026 as_bad (_("Invalid indexed register."));
2030 number_to_chars_bigendian (f
, byte
, 1);
2034 as_fatal (_("Addressing mode not implemented yet."));
2038 /* Assemble the 68HC12 register mode byte. */
2040 build_reg_mode (op
, format
)
2047 if (format
& M6812_OP_SEX_MARKER
2048 && op
->reg1
!= REG_A
&& op
->reg1
!= REG_B
&& op
->reg1
!= REG_CCR
)
2049 as_bad (_("Invalid source register for this instruction, use 'tfr'."));
2050 else if (op
->reg1
== REG_NONE
|| op
->reg1
== REG_PC
)
2051 as_bad (_("Invalid source register."));
2053 if (format
& M6812_OP_SEX_MARKER
2054 && op
->reg2
!= REG_D
2055 && op
->reg2
!= REG_X
&& op
->reg2
!= REG_Y
&& op
->reg2
!= REG_SP
)
2056 as_bad (_("Invalid destination register for this instruction, use 'tfr'."));
2057 else if (op
->reg2
== REG_NONE
|| op
->reg2
== REG_PC
)
2058 as_bad (_("Invalid destination register."));
2060 byte
= (op
->reg1
<< 4) | (op
->reg2
);
2061 if (format
& M6812_OP_EXG_MARKER
)
2065 number_to_chars_bigendian (f
, byte
, 1);
2069 /* build_insn takes a pointer to the opcode entry in the opcode table,
2070 the array of operand expressions and builds the correspding instruction.
2071 This operation only deals with non relative jumps insn (need special
2074 build_insn (opcode
, operands
, nb_operands
)
2075 struct m68hc11_opcode
*opcode
;
2077 int nb_operands ATTRIBUTE_UNUSED
;
2084 /* Put the page code instruction if there is one. */
2085 format
= opcode
->format
;
2087 if (format
& M6811_OP_BRANCH
)
2088 fix_new (frag_now
, frag_now_fix (), 1,
2089 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
2091 if (format
& OP_EXTENDED
)
2095 f
= m68hc11_new_insn (2);
2096 if (format
& M6811_OP_PAGE2
)
2097 page_code
= M6811_OPCODE_PAGE2
;
2098 else if (format
& M6811_OP_PAGE3
)
2099 page_code
= M6811_OPCODE_PAGE3
;
2101 page_code
= M6811_OPCODE_PAGE4
;
2103 number_to_chars_bigendian (f
, page_code
, 1);
2107 f
= m68hc11_new_insn (1);
2109 number_to_chars_bigendian (f
, opcode
->opcode
, 1);
2113 /* The 68HC12 movb and movw instructions are special. We have to handle
2114 them in a special way. */
2115 if (format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
2118 if (format
& M6812_OP_IDX
)
2120 build_indexed_byte (&operands
[0], format
, 1);
2122 format
&= ~M6812_OP_IDX
;
2124 if (format
& M6812_OP_IDX_P2
)
2126 build_indexed_byte (&operands
[1], format
, 1);
2128 format
&= ~M6812_OP_IDX_P2
;
2132 if (format
& (M6811_OP_DIRECT
| M6811_OP_IMM8
))
2134 fixup8 (&operands
[i
].exp
,
2135 format
& (M6811_OP_DIRECT
| M6811_OP_IMM8
| M6812_OP_TRAP_ID
),
2139 else if (IS_CALL_SYMBOL (format
) && nb_operands
== 1)
2141 format
&= ~M6812_OP_PAGE
;
2142 fixup24 (&operands
[i
].exp
, format
& M6811_OP_IND16
,
2146 else if (format
& (M6811_OP_IMM16
| M6811_OP_IND16
))
2148 fixup16 (&operands
[i
].exp
,
2149 format
& (M6811_OP_IMM16
| M6811_OP_IND16
| M6812_OP_PAGE
),
2153 else if (format
& (M6811_OP_IX
| M6811_OP_IY
))
2155 if ((format
& M6811_OP_IX
) && (operands
[0].reg1
!= REG_X
))
2156 as_bad (_("Invalid indexed register, expecting register X."));
2157 if ((format
& M6811_OP_IY
) && (operands
[0].reg1
!= REG_Y
))
2158 as_bad (_("Invalid indexed register, expecting register Y."));
2160 fixup8 (&operands
[0].exp
, M6811_OP_IX
, operands
[0].mode
);
2164 (M6812_OP_IDX
| M6812_OP_IDX_2
| M6812_OP_IDX_1
2165 | M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
2167 build_indexed_byte (&operands
[i
], format
, move_insn
);
2170 else if (format
& M6812_OP_REG
&& current_architecture
& cpu6812
)
2172 build_reg_mode (&operands
[i
], format
);
2175 if (format
& M6811_OP_BITMASK
)
2177 fixup8 (&operands
[i
].exp
, M6811_OP_BITMASK
, operands
[i
].mode
);
2180 if (format
& M6811_OP_JUMP_REL
)
2182 fixup8 (&operands
[i
].exp
, M6811_OP_JUMP_REL
, operands
[i
].mode
);
2184 else if (format
& M6812_OP_IND16_P2
)
2186 fixup16 (&operands
[1].exp
, M6811_OP_IND16
, operands
[1].mode
);
2188 if (format
& M6812_OP_PAGE
)
2190 fixup8 (&operands
[i
].exp
, M6812_OP_PAGE
, operands
[i
].mode
);
2194 /* Opcode identification and operand analysis. */
2196 /* find() gets a pointer to an entry in the opcode table. It must look at all
2197 opcodes with the same name and use the operands to choose the correct
2198 opcode. Returns the opcode pointer if there was a match and 0 if none. */
2199 static struct m68hc11_opcode
*
2200 find (opc
, operands
, nb_operands
)
2201 struct m68hc11_opcode_def
*opc
;
2206 struct m68hc11_opcode
*opcode
;
2207 struct m68hc11_opcode
*op_indirect
;
2210 opcode
= opc
->opcode
;
2212 /* Now search the opcode table table for one with operands
2213 that matches what we've got. We're only done if the operands matched so
2214 far AND there are no more to check. */
2215 for (pos
= match
= 0; match
== 0 && pos
< opc
->nb_modes
; pos
++, opcode
++)
2217 int poss_indirect
= 0;
2218 long format
= opcode
->format
;
2222 if (opcode
->format
& M6811_OP_MASK
)
2224 if (opcode
->format
& M6811_OP_BITMASK
)
2226 if (opcode
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2228 if (opcode
->format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
2230 if ((opcode
->format
& M6812_OP_PAGE
)
2231 && (!IS_CALL_SYMBOL (opcode
->format
) || nb_operands
== 2))
2234 for (i
= 0; expect
== nb_operands
&& i
< nb_operands
; i
++)
2236 int mode
= operands
[i
].mode
;
2238 if (mode
& M6811_OP_IMM16
)
2241 (M6811_OP_IMM8
| M6811_OP_IMM16
| M6811_OP_BITMASK
))
2245 if (mode
== M6811_OP_DIRECT
)
2247 if (format
& M6811_OP_DIRECT
)
2250 /* If the operand is a page 0 operand, remember a
2251 possible <abs-16> addressing mode. We mark
2252 this and continue to check other operands. */
2253 if (format
& M6811_OP_IND16
2254 && flag_strict_direct_addressing
&& op_indirect
== 0)
2261 if (mode
& M6811_OP_IND16
)
2263 if (i
== 0 && (format
& M6811_OP_IND16
) != 0)
2265 if (i
!= 0 && (format
& M6812_OP_PAGE
) != 0)
2267 if (i
!= 0 && (format
& M6812_OP_IND16_P2
) != 0)
2269 if (i
== 0 && (format
& M6811_OP_BITMASK
))
2272 if (mode
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2274 if (format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2277 if (mode
& M6812_OP_REG
)
2280 && (format
& M6812_OP_REG
)
2281 && (operands
[i
].reg2
== REG_NONE
))
2284 && (format
& M6812_OP_REG
)
2285 && (format
& M6812_OP_REG_2
)
2286 && (operands
[i
].reg2
!= REG_NONE
))
2289 && (format
& M6812_OP_IDX
)
2290 && (operands
[i
].reg2
!= REG_NONE
))
2293 && (format
& M6812_OP_IDX
)
2294 && (format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
)))
2297 && (format
& M6812_OP_IDX_P2
))
2301 if (mode
& M6812_OP_IDX
)
2303 if (format
& M6811_OP_IX
&& operands
[i
].reg1
== REG_X
)
2305 if (format
& M6811_OP_IY
&& operands
[i
].reg1
== REG_Y
)
2308 && format
& (M6812_OP_IDX
| M6812_OP_IDX_1
| M6812_OP_IDX_2
)
2309 && (operands
[i
].reg1
== REG_X
2310 || operands
[i
].reg1
== REG_Y
2311 || operands
[i
].reg1
== REG_SP
2312 || operands
[i
].reg1
== REG_PC
))
2314 if (i
== 1 && format
& M6812_OP_IDX_P2
)
2317 if (mode
& format
& (M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
2322 if (mode
& M6812_AUTO_INC_DEC
)
2325 && format
& (M6812_OP_IDX
| M6812_OP_IDX_1
|
2328 if (i
== 1 && format
& M6812_OP_IDX_P2
)
2333 match
= i
== nb_operands
;
2335 /* Operands are ok but an operand uses page 0 addressing mode
2336 while the insn supports abs-16 mode. Keep a reference to this
2337 insns in case there is no insn supporting page 0 addressing. */
2338 if (match
&& poss_indirect
)
2340 op_indirect
= opcode
;
2347 /* Page 0 addressing is used but not supported by any insn.
2348 If absolute addresses are supported, we use that insn. */
2349 if (match
== 0 && op_indirect
)
2351 opcode
= op_indirect
;
2363 /* Find the real opcode and its associated operands. We use a progressive
2364 approach here. On entry, 'opc' points to the first opcode in the
2365 table that matches the opcode name in the source line. We try to
2366 isolate an operand, find a possible match in the opcode table.
2367 We isolate another operand if no match were found. The table 'operands'
2368 is filled while operands are recognized.
2370 Returns the opcode pointer that matches the opcode name in the
2371 source line and the associated operands. */
2372 static struct m68hc11_opcode
*
2373 find_opcode (opc
, operands
, nb_operands
)
2374 struct m68hc11_opcode_def
*opc
;
2378 struct m68hc11_opcode
*opcode
;
2381 if (opc
->max_operands
== 0)
2387 for (i
= 0; i
< opc
->max_operands
;)
2391 result
= get_operand (&operands
[i
], i
, opc
->format
);
2395 /* Special case where the bitmask of the bclr/brclr
2396 instructions is not introduced by #.
2397 Example: bclr 3,x $80. */
2398 if (i
== 1 && (opc
->format
& M6811_OP_BITMASK
)
2399 && (operands
[i
].mode
& M6811_OP_IND16
))
2401 operands
[i
].mode
= M6811_OP_IMM16
;
2406 if (i
>= opc
->min_operands
)
2408 opcode
= find (opc
, operands
, i
);
2409 if (opcode
&& !(opcode
->format
& M6812_OP_PAGE
))
2412 if (opcode
&& *input_line_pointer
!= ',')
2416 if (*input_line_pointer
== ',')
2417 input_line_pointer
++;
2423 #define M6812_XBCC_MARKER (M6812_OP_TBCC_MARKER \
2424 | M6812_OP_DBCC_MARKER \
2425 | M6812_OP_IBCC_MARKER)
2427 /* Gas line assembler entry point. */
2429 /* This is the main entry point for the machine-dependent assembler. str
2430 points to a machine-dependent instruction. This function is supposed to
2431 emit the frags/bytes it assembles to. */
2436 struct m68hc11_opcode_def
*opc
;
2437 struct m68hc11_opcode
*opcode
;
2439 unsigned char *op_start
, *save
;
2440 unsigned char *op_end
;
2443 operand operands
[M6811_MAX_OPERANDS
];
2445 int branch_optimize
= 0;
2448 /* Drop leading whitespace. */
2452 /* Find the opcode end and get the opcode in 'name'. The opcode is forced
2453 lower case (the opcode table only has lower case op-codes). */
2454 for (op_start
= op_end
= (unsigned char *) (str
);
2455 *op_end
&& nlen
< 20 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
2458 name
[nlen
] = TOLOWER (op_start
[nlen
]);
2465 as_bad (_("No instruction or missing opcode."));
2469 /* Find the opcode definition given its name. */
2470 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, name
);
2472 /* If it's not recognized, look for 'jbsr' and 'jbxx'. These are
2473 pseudo insns for relative branch. For these branchs, we always
2474 optimize them (turned into absolute branchs) even if --short-branchs
2476 if (opc
== NULL
&& name
[0] == 'j' && name
[1] == 'b')
2478 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, &name
[1]);
2480 && (!(opc
->format
& M6811_OP_JUMP_REL
)
2481 || (opc
->format
& M6811_OP_BITMASK
)))
2484 branch_optimize
= 1;
2487 /* The following test should probably be removed. This is not conform
2488 to Motorola assembler specs. */
2489 if (opc
== NULL
&& flag_mri
)
2491 if (*op_end
== ' ' || *op_end
== '\t')
2493 while (*op_end
== ' ' || *op_end
== '\t')
2498 (is_end_of_line
[op_end
[1]]
2499 || op_end
[1] == ' ' || op_end
[1] == '\t'
2500 || !ISALNUM (op_end
[1])))
2501 && (*op_end
== 'a' || *op_end
== 'b'
2502 || *op_end
== 'A' || *op_end
== 'B'
2503 || *op_end
== 'd' || *op_end
== 'D'
2504 || *op_end
== 'x' || *op_end
== 'X'
2505 || *op_end
== 'y' || *op_end
== 'Y'))
2507 name
[nlen
++] = TOLOWER (*op_end
++);
2509 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
,
2515 /* Identify a possible instruction alias. There are some on the
2516 68HC12 to emulate a few 68HC11 instructions. */
2517 if (opc
== NULL
&& (current_architecture
& cpu6812
))
2521 for (i
= 0; i
< m68hc12_num_alias
; i
++)
2522 if (strcmp (m68hc12_alias
[i
].name
, name
) == 0)
2528 if (opc
== NULL
&& alias_id
< 0)
2530 as_bad (_("Opcode `%s' is not recognized."), name
);
2533 save
= input_line_pointer
;
2534 input_line_pointer
= op_end
;
2539 opcode
= find_opcode (opc
, operands
, &nb_operands
);
2544 if ((opcode
|| alias_id
>= 0) && !flag_mri
)
2546 char *p
= input_line_pointer
;
2548 while (*p
== ' ' || *p
== '\t' || *p
== '\n' || *p
== '\r')
2551 if (*p
!= '\n' && *p
)
2552 as_bad (_("Garbage at end of instruction: `%s'."), p
);
2555 input_line_pointer
= save
;
2559 char *f
= m68hc11_new_insn (m68hc12_alias
[alias_id
].size
);
2561 number_to_chars_bigendian (f
, m68hc12_alias
[alias_id
].code1
, 1);
2562 if (m68hc12_alias
[alias_id
].size
> 1)
2563 number_to_chars_bigendian (f
+ 1, m68hc12_alias
[alias_id
].code2
, 1);
2568 /* Opcode is known but does not have valid operands. Print out the
2569 syntax for this opcode. */
2572 if (flag_print_insn_syntax
)
2573 print_insn_format (name
);
2575 as_bad (_("Invalid operand for `%s'"), name
);
2579 /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is
2580 relative and must be in the range -256..255 (9-bits). */
2581 if ((opcode
->format
& M6812_XBCC_MARKER
)
2582 && (opcode
->format
& M6811_OP_JUMP_REL
))
2583 build_dbranch_insn (opcode
, operands
, nb_operands
, branch_optimize
);
2585 /* Relative jumps instructions are taken care of separately. We have to make
2586 sure that the relative branch is within the range -128..127. If it's out
2587 of range, the instructions are changed into absolute instructions.
2588 This is not supported for the brset and brclr instructions. */
2589 else if ((opcode
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2590 && !(opcode
->format
& M6811_OP_BITMASK
))
2591 build_jump_insn (opcode
, operands
, nb_operands
, branch_optimize
);
2593 build_insn (opcode
, operands
, nb_operands
);
2597 /* Pseudo op to control the ELF flags. */
2600 int x ATTRIBUTE_UNUSED
;
2602 char *name
= input_line_pointer
, ch
;
2604 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2605 input_line_pointer
++;
2606 ch
= *input_line_pointer
;
2607 *input_line_pointer
= '\0';
2609 if (strcmp (name
, "mshort") == 0)
2611 elf_flags
&= ~E_M68HC11_I32
;
2613 else if (strcmp (name
, "mlong") == 0)
2615 elf_flags
|= E_M68HC11_I32
;
2617 else if (strcmp (name
, "mshort-double") == 0)
2619 elf_flags
&= ~E_M68HC11_F64
;
2621 else if (strcmp (name
, "mlong-double") == 0)
2623 elf_flags
|= E_M68HC11_F64
;
2627 as_warn (_("Invalid mode: %s\n"), name
);
2629 *input_line_pointer
= ch
;
2630 demand_empty_rest_of_line ();
2633 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions
2634 are using 'rtc' for returning. It is necessary to use 'call'
2635 to invoke them. This is also used by the debugger to correctly
2636 find the stack frame. */
2638 s_m68hc11_mark_symbol (mark
)
2645 elf_symbol_type
*elfsym
;
2649 name
= input_line_pointer
;
2650 c
= get_symbol_end ();
2651 symbolP
= symbol_find_or_make (name
);
2652 *input_line_pointer
= c
;
2656 bfdsym
= symbol_get_bfdsym (symbolP
);
2657 elfsym
= elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
2661 /* Mark the symbol far (using rtc for function return). */
2662 elfsym
->internal_elf_sym
.st_other
|= mark
;
2666 input_line_pointer
++;
2670 if (*input_line_pointer
== '\n')
2676 demand_empty_rest_of_line ();
2680 s_m68hc11_relax (ignore
)
2681 int ignore ATTRIBUTE_UNUSED
;
2687 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
2689 as_bad (_("bad .relax format"));
2690 ignore_rest_of_line ();
2694 fix_new_exp (frag_now
, frag_now_fix (), 1, &ex
, 1,
2695 BFD_RELOC_M68HC11_RL_GROUP
);
2697 demand_empty_rest_of_line ();
2701 /* Relocation, relaxation and frag conversions. */
2703 /* PC-relative offsets are relative to the start of the
2704 next instruction. That is, the address of the offset, plus its
2705 size, since the offset is always the last part of the insn. */
2707 md_pcrel_from (fixP
)
2710 if (fixP
->fx_r_type
== BFD_RELOC_M68HC11_RL_JUMP
)
2713 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2716 /* If while processing a fixup, a reloc really needs to be created
2717 then it is done here. */
2719 tc_gen_reloc (section
, fixp
)
2720 asection
*section ATTRIBUTE_UNUSED
;
2725 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2726 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2727 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2728 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2729 if (fixp
->fx_r_type
== 0)
2730 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
2732 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2733 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
2735 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2736 _("Relocation %d is not supported by object file format."),
2737 (int) fixp
->fx_r_type
);
2741 /* Since we use Rel instead of Rela, encode the vtable entry to be
2742 used in the relocation's section offset. */
2743 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2744 reloc
->address
= fixp
->fx_offset
;
2750 /* We need a port-specific relaxation function to cope with sym2 - sym1
2751 relative expressions with both symbols in the same segment (but not
2752 necessarily in the same frag as this insn), for example:
2753 ldab sym2-(sym1-2),pc
2755 The offset can be 5, 9 or 16 bits long. */
2758 m68hc11_relax_frag (seg
, fragP
, stretch
)
2759 segT seg ATTRIBUTE_UNUSED
;
2761 long stretch ATTRIBUTE_UNUSED
;
2766 const relax_typeS
*this_type
;
2767 const relax_typeS
*start_type
;
2768 relax_substateT next_state
;
2769 relax_substateT this_state
;
2770 const relax_typeS
*table
= TC_GENERIC_RELAX_TABLE
;
2772 /* We only have to cope with frags as prepared by
2773 md_estimate_size_before_relax. The STATE_BITS16 case may geet here
2774 because of the different reasons that it's not relaxable. */
2775 switch (fragP
->fr_subtype
)
2777 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
):
2778 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
):
2779 /* When we get to this state, the frag won't grow any more. */
2782 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS5
):
2783 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS5
):
2784 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
):
2785 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
):
2786 if (fragP
->fr_symbol
== NULL
2787 || S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
2788 as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"),
2789 __FUNCTION__
, (long) fragP
->fr_symbol
);
2790 symbolP
= fragP
->fr_symbol
;
2791 if (symbol_resolved_p (symbolP
))
2792 as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
2794 aim
= S_GET_VALUE (symbolP
);
2798 as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"),
2799 __FUNCTION__
, fragP
->fr_subtype
);
2802 /* The rest is stolen from relax_frag. There's no obvious way to
2803 share the code, but fortunately no requirement to keep in sync as
2804 long as fragP->fr_symbol does not have its segment changed. */
2806 this_state
= fragP
->fr_subtype
;
2807 start_type
= this_type
= table
+ this_state
;
2811 /* Look backwards. */
2812 for (next_state
= this_type
->rlx_more
; next_state
;)
2813 if (aim
>= this_type
->rlx_backward
)
2817 /* Grow to next state. */
2818 this_state
= next_state
;
2819 this_type
= table
+ this_state
;
2820 next_state
= this_type
->rlx_more
;
2825 /* Look forwards. */
2826 for (next_state
= this_type
->rlx_more
; next_state
;)
2827 if (aim
<= this_type
->rlx_forward
)
2831 /* Grow to next state. */
2832 this_state
= next_state
;
2833 this_type
= table
+ this_state
;
2834 next_state
= this_type
->rlx_more
;
2838 growth
= this_type
->rlx_length
- start_type
->rlx_length
;
2840 fragP
->fr_subtype
= this_state
;
2845 md_convert_frag (abfd
, sec
, fragP
)
2846 bfd
*abfd ATTRIBUTE_UNUSED
;
2847 asection
*sec ATTRIBUTE_UNUSED
;
2853 char *buffer_address
= fragP
->fr_literal
;
2855 /* Address in object code of the displacement. */
2856 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
2858 buffer_address
+= fragP
->fr_fix
;
2860 /* The displacement of the address, from current location. */
2861 value
= S_GET_VALUE (fragP
->fr_symbol
);
2862 disp
= (value
+ fragP
->fr_offset
) - object_address
;
2864 switch (fragP
->fr_subtype
)
2866 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_BYTE
):
2867 fragP
->fr_opcode
[1] = disp
;
2870 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_WORD
):
2871 /* This relax is only for bsr and bra. */
2872 assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
2873 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
2874 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
2876 fragP
->fr_opcode
[0] = convert_branch (fragP
->fr_opcode
[0]);
2878 fix_new (fragP
, fragP
->fr_fix
- 1, 2,
2879 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2883 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_BYTE
):
2884 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_BYTE
):
2885 fragP
->fr_opcode
[1] = disp
;
2888 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_WORD
):
2889 /* Invert branch. */
2890 fragP
->fr_opcode
[0] ^= 1;
2891 fragP
->fr_opcode
[1] = 3; /* Branch offset. */
2892 buffer_address
[0] = M6811_JMP
;
2893 fix_new (fragP
, fragP
->fr_fix
+ 1, 2,
2894 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2898 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_WORD
):
2899 /* Translate branch into a long branch. */
2900 fragP
->fr_opcode
[1] = fragP
->fr_opcode
[0];
2901 fragP
->fr_opcode
[0] = M6811_OPCODE_PAGE2
;
2903 fixp
= fix_new (fragP
, fragP
->fr_fix
, 2,
2904 fragP
->fr_symbol
, fragP
->fr_offset
, 1,
2905 BFD_RELOC_16_PCREL
);
2906 fixp
->fx_pcrel_adjust
= 2;
2910 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS5
):
2911 if (fragP
->fr_symbol
!= 0
2912 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
2916 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS5
):
2917 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 6;
2918 fragP
->fr_opcode
[0] |= value
& 0x1f;
2921 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
):
2922 /* For a PC-relative offset, use the displacement with a -1 correction
2923 to take into account the additional byte of the insn. */
2924 if (fragP
->fr_symbol
!= 0
2925 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
2929 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
):
2930 fragP
->fr_opcode
[0] = (fragP
->fr_opcode
[0] << 3);
2931 fragP
->fr_opcode
[0] |= 0xE0;
2932 fragP
->fr_opcode
[0] |= (value
>> 8) & 1;
2933 fragP
->fr_opcode
[1] = value
;
2937 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
):
2938 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
):
2939 fragP
->fr_opcode
[0] = (fragP
->fr_opcode
[0] << 3);
2940 fragP
->fr_opcode
[0] |= 0xe2;
2941 if ((fragP
->fr_opcode
[0] & 0x0ff) == 0x0fa
2942 && fragP
->fr_symbol
!= 0
2943 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
2945 fixp
= fix_new (fragP
, fragP
->fr_fix
, 2,
2946 fragP
->fr_symbol
, fragP
->fr_offset
,
2947 1, BFD_RELOC_16_PCREL
);
2951 fix_new (fragP
, fragP
->fr_fix
, 2,
2952 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2957 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_BYTE
):
2959 fragP
->fr_opcode
[0] |= 0x10;
2961 fragP
->fr_opcode
[1] = disp
& 0x0FF;
2964 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_WORD
):
2965 /* Invert branch. */
2966 fragP
->fr_opcode
[0] ^= 0x20;
2967 fragP
->fr_opcode
[1] = 3; /* Branch offset. */
2968 buffer_address
[0] = M6812_JMP
;
2969 fix_new (fragP
, fragP
->fr_fix
+ 1, 2,
2970 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2979 /* On an ELF system, we can't relax a weak symbol. The weak symbol
2980 can be overridden at final link time by a non weak symbol. We can
2981 relax externally visible symbol because there is no shared library
2982 and such symbol can't be overridden (unless they are weak). */
2984 relaxable_symbol (symbol
)
2987 return ! S_IS_WEAK (symbol
);
2990 /* Force truly undefined symbols to their maximum size, and generally set up
2991 the frag list to be relaxed. */
2993 md_estimate_size_before_relax (fragP
, segment
)
2997 if (RELAX_LENGTH (fragP
->fr_subtype
) == STATE_UNDF
)
2999 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3000 || !relaxable_symbol (fragP
->fr_symbol
))
3002 /* Non-relaxable cases. */
3004 char *buffer_address
;
3006 old_fr_fix
= fragP
->fr_fix
;
3007 buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
3009 switch (RELAX_STATE (fragP
->fr_subtype
))
3011 case STATE_PC_RELATIVE
:
3013 /* This relax is only for bsr and bra. */
3014 assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
3015 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
3016 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
3018 if (flag_fixed_branchs
)
3019 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
3020 _("bra or bsr with undefined symbol."));
3022 /* The symbol is undefined or in a separate section.
3023 Turn bra into a jmp and bsr into a jsr. The insn
3024 becomes 3 bytes long (instead of 2). A fixup is
3025 necessary for the unresolved symbol address. */
3026 fragP
->fr_opcode
[0] = convert_branch (fragP
->fr_opcode
[0]);
3028 fix_new (fragP
, fragP
->fr_fix
- 1, 2, fragP
->fr_symbol
,
3029 fragP
->fr_offset
, 0, BFD_RELOC_16
);
3033 case STATE_CONDITIONAL_BRANCH
:
3034 assert (current_architecture
& cpu6811
);
3036 fragP
->fr_opcode
[0] ^= 1; /* Reverse sense of branch. */
3037 fragP
->fr_opcode
[1] = 3; /* Skip next jmp insn (3 bytes). */
3039 /* Don't use fr_opcode[2] because this may be
3040 in a different frag. */
3041 buffer_address
[0] = M6811_JMP
;
3044 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3045 fragP
->fr_offset
, 0, BFD_RELOC_16
);
3049 case STATE_INDEXED_OFFSET
:
3050 assert (current_architecture
& cpu6812
);
3052 if (fragP
->fr_symbol
3053 && S_GET_SEGMENT (fragP
->fr_symbol
) == absolute_section
)
3055 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_OFFSET
,
3057 /* Return the size of the variable part of the frag. */
3058 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3062 /* Switch the indexed operation to 16-bit mode. */
3063 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 3;
3064 fragP
->fr_opcode
[0] |= 0xe2;
3065 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3066 fragP
->fr_offset
, 0, BFD_RELOC_16
);
3071 case STATE_INDEXED_PCREL
:
3072 assert (current_architecture
& cpu6812
);
3074 if (fragP
->fr_symbol
3075 && S_GET_SEGMENT (fragP
->fr_symbol
) == absolute_section
)
3077 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_PCREL
,
3079 /* Return the size of the variable part of the frag. */
3080 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3086 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 3;
3087 fragP
->fr_opcode
[0] |= 0xe2;
3088 fixp
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3089 fragP
->fr_offset
, 1, BFD_RELOC_16_PCREL
);
3094 case STATE_XBCC_BRANCH
:
3095 assert (current_architecture
& cpu6812
);
3097 fragP
->fr_opcode
[0] ^= 0x20; /* Reverse sense of branch. */
3098 fragP
->fr_opcode
[1] = 3; /* Skip next jmp insn (3 bytes). */
3100 /* Don't use fr_opcode[2] because this may be
3101 in a different frag. */
3102 buffer_address
[0] = M6812_JMP
;
3105 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3106 fragP
->fr_offset
, 0, BFD_RELOC_16
);
3110 case STATE_CONDITIONAL_BRANCH_6812
:
3111 assert (current_architecture
& cpu6812
);
3113 /* Translate into a lbcc branch. */
3114 fragP
->fr_opcode
[1] = fragP
->fr_opcode
[0];
3115 fragP
->fr_opcode
[0] = M6811_OPCODE_PAGE2
;
3117 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3118 fragP
->fr_offset
, 1, BFD_RELOC_16_PCREL
);
3123 as_fatal (_("Subtype %d is not recognized."), fragP
->fr_subtype
);
3127 /* Return the growth in the fixed part of the frag. */
3128 return fragP
->fr_fix
- old_fr_fix
;
3131 /* Relaxable cases. */
3132 switch (RELAX_STATE (fragP
->fr_subtype
))
3134 case STATE_PC_RELATIVE
:
3135 /* This relax is only for bsr and bra. */
3136 assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
3137 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
3138 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
3140 fragP
->fr_subtype
= ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_BYTE
);
3143 case STATE_CONDITIONAL_BRANCH
:
3144 assert (current_architecture
& cpu6811
);
3146 fragP
->fr_subtype
= ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
,
3150 case STATE_INDEXED_OFFSET
:
3151 assert (current_architecture
& cpu6812
);
3153 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_OFFSET
,
3157 case STATE_INDEXED_PCREL
:
3158 assert (current_architecture
& cpu6812
);
3160 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_PCREL
,
3164 case STATE_XBCC_BRANCH
:
3165 assert (current_architecture
& cpu6812
);
3167 fragP
->fr_subtype
= ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_BYTE
);
3170 case STATE_CONDITIONAL_BRANCH_6812
:
3171 assert (current_architecture
& cpu6812
);
3173 fragP
->fr_subtype
= ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
,
3179 if (fragP
->fr_subtype
>= sizeof (md_relax_table
) / sizeof (md_relax_table
[0]))
3180 as_fatal (_("Subtype %d is not recognized."), fragP
->fr_subtype
);
3182 /* Return the size of the variable part of the frag. */
3183 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3186 /* See whether we need to force a relocation into the output file. */
3188 tc_m68hc11_force_relocation (fixP
)
3191 switch (fixP
->fx_r_type
)
3193 case BFD_RELOC_VTABLE_INHERIT
:
3194 case BFD_RELOC_VTABLE_ENTRY
:
3195 case BFD_RELOC_M68HC11_RL_GROUP
:
3202 return S_FORCE_RELOC (fixP
->fx_addsy
);
3205 /* Here we decide which fixups can be adjusted to make them relative
3206 to the beginning of the section instead of the symbol. Basically
3207 we need to make sure that the linker relaxation is done
3208 correctly, so in some cases we force the original symbol to be
3211 tc_m68hc11_fix_adjustable (fixP
)
3214 switch (fixP
->fx_r_type
)
3216 /* For the linker relaxation to work correctly, these relocs
3217 need to be on the symbol itself. */
3219 case BFD_RELOC_LO16
:
3220 case BFD_RELOC_M68HC11_RL_JUMP
:
3221 case BFD_RELOC_M68HC11_RL_GROUP
:
3222 case BFD_RELOC_VTABLE_INHERIT
:
3223 case BFD_RELOC_VTABLE_ENTRY
:
3233 md_apply_fix3 (fixP
, valP
, seg
)
3236 segT seg ATTRIBUTE_UNUSED
;
3239 long value
= * valP
;
3242 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
3245 /* We don't actually support subtracting a symbol. */
3246 if (fixP
->fx_subsy
!= (symbolS
*) NULL
)
3247 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("Expression too complex."));
3249 op_type
= fixP
->fx_r_type
;
3251 /* Patch the instruction with the resolved operand. Elf relocation
3252 info will also be generated to take care of linker/loader fixups.
3253 The 68HC11 addresses only 64Kb, we are only concerned by 8 and 16-bit
3254 relocs. BFD_RELOC_8 is basically used for .page0 access (the linker
3255 will warn for overflows). BFD_RELOC_8_PCREL should not be generated
3256 because it's either resolved or turned out into non-relative insns (see
3257 relax table, bcc, bra, bsr transformations)
3259 The BFD_RELOC_32 is necessary for the support of --gstabs. */
3260 where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
3262 switch (fixP
->fx_r_type
)
3265 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
3269 case BFD_RELOC_M68HC11_24
:
3270 bfd_putb16 ((bfd_vma
) (value
& 0x0ffff), (unsigned char *) where
);
3271 ((bfd_byte
*) where
)[2] = ((value
>> 16) & 0x0ff);
3275 case BFD_RELOC_16_PCREL
:
3276 case BFD_RELOC_M68HC11_LO16
:
3277 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
3278 if (value
< -65537 || value
> 65535)
3279 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3280 _("Value out of 16-bit range."));
3283 case BFD_RELOC_M68HC11_HI8
:
3287 case BFD_RELOC_M68HC11_LO8
:
3289 case BFD_RELOC_M68HC11_PAGE
:
3291 bfd_putb8 ((bfd_vma
) value
, (unsigned char *) where
);
3293 ((bfd_byte
*) where
)[0] = (bfd_byte
) value
;
3296 case BFD_RELOC_8_PCREL
:
3298 bfd_putb8 ((bfd_vma
) value
, (unsigned char *) where
);
3300 ((bfd_byte
*) where
)[0] = (bfd_byte
) value
;
3302 if (value
< -128 || value
> 127)
3303 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3304 _("Value %ld too large for 8-bit PC-relative branch."),
3308 case BFD_RELOC_M68HC11_3B
:
3309 if (value
<= 0 || value
> 8)
3310 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3311 _("Auto increment/decrement offset '%ld' is out of range."),
3318 where
[0] = where
[0] | (value
& 0x07);
3321 case BFD_RELOC_M68HC11_RL_JUMP
:
3322 case BFD_RELOC_M68HC11_RL_GROUP
:
3323 case BFD_RELOC_VTABLE_INHERIT
:
3324 case BFD_RELOC_VTABLE_ENTRY
:
3329 as_fatal (_("Line %d: unknown relocation type: 0x%x."),
3330 fixP
->fx_line
, fixP
->fx_r_type
);
3334 /* Set the ELF specific flags. */
3336 m68hc11_elf_final_processing ()
3338 if (current_architecture
& cpu6812s
)
3339 elf_flags
|= EF_M68HCS12_MACH
;
3340 elf_elfheader (stdoutput
)->e_flags
&= ~EF_M68HC11_ABI
;
3341 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;