1 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12.
2 Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010,
4 Free Software Foundation, Inc.
5 Written by Stephane Carrez (stcarrez@nerim.fr)
6 XGATE and S12X added by James Murray (jsm@jsm-net.demon.co.uk)
8 This file is part of GAS, the GNU Assembler.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
23 Boston, MA 02110-1301, USA. */
26 #include "safe-ctype.h"
28 #include "opcode/m68hc11.h"
29 #include "dwarf2dbg.h"
30 #include "elf/m68hc11.h"
32 const char comment_chars
[] = ";!";
33 const char line_comment_chars
[] = "#*";
34 const char line_separator_chars
[] = "";
36 const char EXP_CHARS
[] = "eE";
37 const char FLT_CHARS
[] = "dD";
39 #define STATE_CONDITIONAL_BRANCH (1)
40 #define STATE_PC_RELATIVE (2)
41 #define STATE_INDEXED_OFFSET (3)
42 #define STATE_INDEXED_PCREL (4)
43 #define STATE_XBCC_BRANCH (5)
44 #define STATE_CONDITIONAL_BRANCH_6812 (6)
46 #define STATE_BYTE (0)
47 #define STATE_BITS5 (0)
48 #define STATE_WORD (1)
49 #define STATE_BITS9 (1)
50 #define STATE_LONG (2)
51 #define STATE_BITS16 (2)
52 #define STATE_UNDF (3) /* Symbol undefined in pass1 */
54 /* This macro has no side-effects. */
55 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
56 #define RELAX_STATE(s) ((s) >> 2)
57 #define RELAX_LENGTH(s) ((s) & 3)
59 #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF))
61 /* This table describes how you change sizes for the various types of variable
62 size expressions. This version only supports two kinds. */
65 How far Forward this mode will reach.
66 How far Backward this mode will reach.
67 How many bytes this mode will add to the size of the frag.
68 Which mode to go to if the offset won't fit in this one. */
70 relax_typeS md_relax_table
[] =
72 {1, 1, 0, 0}, /* First entries aren't used. */
73 {1, 1, 0, 0}, /* For no good reason except. */
74 {1, 1, 0, 0}, /* that the VAX doesn't either. */
78 These insns are translated into b!cc +3 jmp L. */
79 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_WORD
)},
84 /* Relax for bsr <L> and bra <L>.
85 These insns are translated into jsr and jmp. */
86 {(127), (-128), 0, ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_WORD
)},
91 /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */
92 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
)},
93 {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
)},
97 /* Relax for PC relative offset: 5-bits, 9-bits, 16-bits.
98 For the 9-bit case, there will be a -1 correction to take into
99 account the new byte that's why the range is -255..256. */
100 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
)},
101 {(256), (-255), 1, ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
)},
105 /* Relax for dbeq/ibeq/tbeq r,<L>:
106 These insns are translated into db!cc +3 jmp L. */
107 {(255), (-256), 0, ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_WORD
)},
112 /* Relax for bcc <L> on 68HC12.
113 These insns are translated into lbcc <L>. */
114 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_WORD
)},
121 /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */
122 typedef enum register_id
146 typedef struct operand
154 struct m68hc11_opcode_def
161 struct m68hc11_opcode
*opcode
;
164 static struct m68hc11_opcode_def
*m68hc11_opcode_defs
= 0;
165 static int m68hc11_nb_opcode_defs
= 0;
173 static alias alias_opcodes
[] =
181 struct m9s12xg_opcode_def
188 struct m9s12xg_opcode
*opcode
;
191 /* Local functions. */
192 static register_id
reg_name_search (char *);
193 static register_id
register_name (void);
194 static int cmp_opcode (struct m68hc11_opcode
*, struct m68hc11_opcode
*);
195 static char *print_opcode_format (struct m68hc11_opcode
*, int);
196 static char *skip_whites (char *);
197 static int check_range (long, int);
198 static void print_opcode_list (void);
199 static void get_default_target (void);
200 static void print_insn_format (char *);
201 static int get_operand (operand
*, int, long);
202 static void fixup8 (expressionS
*, int, int);
203 static void fixup16 (expressionS
*, int, int);
204 static void fixup24 (expressionS
*, int, int);
205 static void fixup8_xg (expressionS
*, int, int);
206 static unsigned char convert_branch (unsigned char);
207 static char *m68hc11_new_insn (int);
208 static void build_dbranch_insn (struct m68hc11_opcode
*,
209 operand
*, int, int);
210 static int build_indexed_byte (operand
*, int, int);
211 static int build_reg_mode (operand
*, int);
213 static struct m68hc11_opcode
*find (struct m68hc11_opcode_def
*,
215 static struct m68hc11_opcode
*find_opcode (struct m68hc11_opcode_def
*,
217 static void build_jump_insn (struct m68hc11_opcode
*, operand
*, int, int);
218 static void build_insn_xg (struct m68hc11_opcode
*, operand
*, int);
219 static void build_insn (struct m68hc11_opcode
*, operand
*, int);
220 static int relaxable_symbol (symbolS
*);
222 /* Pseudo op to indicate a relax group. */
223 static void s_m68hc11_relax (int);
225 /* Pseudo op to control the ELF flags. */
226 static void s_m68hc11_mode (int);
228 /* Process directives specified via pseudo ops. */
229 static void s_m68hc11_parse_pseudo_instruction (int);
231 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions
232 are using 'rtc' for returning. It is necessary to use 'call'
233 to invoke them. This is also used by the debugger to correctly
234 find the stack frame. */
235 static void s_m68hc11_mark_symbol (int);
237 /* Controls whether relative branches can be turned into long branches.
238 When the relative offset is too large, the insn are changed:
246 Setting the flag forbidds this. */
247 static short flag_fixed_branches
= 0;
249 /* Force to use long jumps (absolute) instead of relative branches. */
250 static short flag_force_long_jumps
= 0;
252 /* Change the direct addressing mode into an absolute addressing mode
253 when the insn does not support direct addressing.
254 For example, "clr *ZD0" is normally not possible and is changed
256 static short flag_strict_direct_addressing
= 1;
258 /* When an opcode has invalid operand, print out the syntax of the opcode
260 static short flag_print_insn_syntax
= 0;
262 /* Dumps the list of instructions with syntax and then exit:
263 1 -> Only dumps the list (sorted by name)
264 2 -> Generate an example (or test) that can be compiled. */
265 static short flag_print_opcodes
= 0;
267 /* Opcode hash table. */
268 static struct hash_control
*m68hc11_hash
;
270 /* Current cpu (either cpu6811 or cpu6812). This is determined automagically
271 by 'get_default_target' by looking at default BFD vector. This is overridden
272 with the -m<cpu> option. */
273 static int current_architecture
= 0;
275 /* Default cpu determined by 'get_default_target'. */
276 static const char *default_cpu
;
278 /* Number of opcodes in the sorted table (filtered by current cpu). */
279 static int num_opcodes
;
281 /* The opcodes sorted by name and filtered by current cpu. */
282 static struct m68hc11_opcode
*m68hc11_sorted_opcodes
;
284 /* ELF flags to set in the output file header. */
285 static int elf_flags
= E_M68HC11_F64
;
287 /* These are the machine dependent pseudo-ops. These are included so
288 the assembler can work on the output from the SUN C compiler, which
291 /* This table describes all the machine specific pseudo-ops the assembler
292 has to support. The fields are:
293 pseudo-op name without dot
294 function to call to execute this pseudo-op
295 Integer arg to pass to the function. */
296 const pseudo_typeS md_pseudo_table
[] =
298 /* The following pseudo-ops are supported for MRI compatibility. */
302 {"fcc", stringer
, 8 + 1},
306 {"xrefb", s_ignore
, 0}, /* Same as xref */
308 /* Gcc driven relaxation. */
309 {"relax", s_m68hc11_relax
, 0},
311 /* .mode instruction (ala SH). */
312 {"mode", s_m68hc11_mode
, 0},
314 /* .far instruction. */
315 {"far", s_m68hc11_mark_symbol
, STO_M68HC12_FAR
},
317 /* .interrupt instruction. */
318 {"interrupt", s_m68hc11_mark_symbol
, STO_M68HC12_INTERRUPT
},
320 /* .nobankwarning instruction. */
321 {"nobankwarning", s_m68hc11_parse_pseudo_instruction
, E_M68HC11_NO_BANK_WARNING
},
326 /* Options and initialization. */
328 const char *md_shortopts
= "Sm:";
330 struct option md_longopts
[] =
332 #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
333 {"force-long-branches", no_argument
, NULL
, OPTION_FORCE_LONG_BRANCH
},
334 {"force-long-branchs", no_argument
, NULL
, OPTION_FORCE_LONG_BRANCH
}, /* Misspelt version kept for backwards compatibility. */
336 #define OPTION_SHORT_BRANCHES (OPTION_MD_BASE + 1)
337 {"short-branches", no_argument
, NULL
, OPTION_SHORT_BRANCHES
},
338 {"short-branchs", no_argument
, NULL
, OPTION_SHORT_BRANCHES
}, /* Misspelt version kept for backwards compatibility. */
340 #define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2)
341 {"strict-direct-mode", no_argument
, NULL
, OPTION_STRICT_DIRECT_MODE
},
343 #define OPTION_PRINT_INSN_SYNTAX (OPTION_MD_BASE + 3)
344 {"print-insn-syntax", no_argument
, NULL
, OPTION_PRINT_INSN_SYNTAX
},
346 #define OPTION_PRINT_OPCODES (OPTION_MD_BASE + 4)
347 {"print-opcodes", no_argument
, NULL
, OPTION_PRINT_OPCODES
},
349 #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5)
350 {"generate-example", no_argument
, NULL
, OPTION_GENERATE_EXAMPLE
},
352 #define OPTION_MSHORT (OPTION_MD_BASE + 6)
353 {"mshort", no_argument
, NULL
, OPTION_MSHORT
},
355 #define OPTION_MLONG (OPTION_MD_BASE + 7)
356 {"mlong", no_argument
, NULL
, OPTION_MLONG
},
358 #define OPTION_MSHORT_DOUBLE (OPTION_MD_BASE + 8)
359 {"mshort-double", no_argument
, NULL
, OPTION_MSHORT_DOUBLE
},
361 #define OPTION_MLONG_DOUBLE (OPTION_MD_BASE + 9)
362 {"mlong-double", no_argument
, NULL
, OPTION_MLONG_DOUBLE
},
364 #define OPTION_XGATE_RAMOFFSET (OPTION_MD_BASE + 10)
365 {"xgate-ramoffset", no_argument
, NULL
, OPTION_XGATE_RAMOFFSET
},
367 {NULL
, no_argument
, NULL
, 0}
369 size_t md_longopts_size
= sizeof (md_longopts
);
371 /* Get the target cpu for the assembler. This is based on the configure
372 options and on the -m68hc11/-m68hc12 option. If no option is specified,
373 we must get the default. */
375 m68hc11_arch_format (void)
377 get_default_target ();
378 if (current_architecture
& cpu6811
)
379 return "elf32-m68hc11";
381 return "elf32-m68hc12";
384 enum bfd_architecture
387 get_default_target ();
388 if (current_architecture
& cpu6811
)
389 return bfd_arch_m68hc11
;
391 return bfd_arch_m68hc12
;
400 /* Listing header selected according to cpu. */
402 m68hc11_listing_header (void)
404 if (current_architecture
& cpu6811
)
405 return "M68HC11 GAS ";
406 else if (current_architecture
& cpuxgate
)
408 else if (current_architecture
& cpu9s12x
)
411 return "M68HC12 GAS ";
415 md_show_usage (FILE *stream
)
417 get_default_target ();
418 fprintf (stream
, _("\
419 Motorola 68HC11/68HC12/68HCS12 options:\n\
420 -m68hc11 | -m68hc12 |\n\
421 -m68hcs12 | -mm9s12x |\n\
422 -mm9s12xg specify the processor [default %s]\n\
423 -mshort use 16-bit int ABI (default)\n\
424 -mlong use 32-bit int ABI\n\
425 -mshort-double use 32-bit double ABI\n\
426 -mlong-double use 64-bit double ABI (default)\n\
427 --force-long-branches always turn relative branches into absolute ones\n\
428 -S,--short-branches do not turn relative branches into absolute ones\n\
429 when the offset is out of range\n\
430 --strict-direct-mode do not turn the direct mode into extended mode\n\
431 when the instruction does not support direct mode\n\
432 --print-insn-syntax print the syntax of instruction in case of error\n\
433 --print-opcodes print the list of instructions with syntax\n\
434 --xgate-ramoffset offset ram addresses by 0xc000\n\
435 --generate-example generate an example of each instruction\n\
436 (used for testing)\n"), default_cpu
);
440 /* Try to identify the default target based on the BFD library. */
442 get_default_target (void)
444 const bfd_target
*target
;
447 if (current_architecture
!= 0)
450 default_cpu
= "unknown";
451 target
= bfd_find_target (0, &abfd
);
452 if (target
&& target
->name
)
454 if (strcmp (target
->name
, "elf32-m68hc12") == 0)
456 current_architecture
= cpu6812
;
457 default_cpu
= "m68hc12";
459 else if (strcmp (target
->name
, "elf32-m68hc11") == 0)
461 current_architecture
= cpu6811
;
462 default_cpu
= "m68hc11";
466 as_bad (_("Default target `%s' is not supported."), target
->name
);
472 m68hc11_print_statistics (FILE *file
)
475 struct m68hc11_opcode_def
*opc
;
477 hash_print_statistics (file
, "opcode table", m68hc11_hash
);
479 opc
= m68hc11_opcode_defs
;
480 if (opc
== 0 || m68hc11_nb_opcode_defs
== 0)
483 /* Dump the opcode statistics table. */
484 fprintf (file
, _("Name # Modes Min ops Max ops Modes mask # Used\n"));
485 for (i
= 0; i
< m68hc11_nb_opcode_defs
; i
++, opc
++)
487 fprintf (file
, "%-7.7s %5d %7d %7d 0x%08lx %7d\n",
490 opc
->min_operands
, opc
->max_operands
, opc
->format
, opc
->used
);
495 md_parse_option (int c
, char *arg
)
497 get_default_target ();
500 /* -S means keep external to 2 bit offset rather than 16 bit one. */
501 case OPTION_SHORT_BRANCHES
:
503 flag_fixed_branches
= 1;
506 case OPTION_FORCE_LONG_BRANCH
:
507 flag_force_long_jumps
= 1;
510 case OPTION_PRINT_INSN_SYNTAX
:
511 flag_print_insn_syntax
= 1;
514 case OPTION_PRINT_OPCODES
:
515 flag_print_opcodes
= 1;
518 case OPTION_STRICT_DIRECT_MODE
:
519 flag_strict_direct_addressing
= 0;
522 case OPTION_GENERATE_EXAMPLE
:
523 flag_print_opcodes
= 2;
527 elf_flags
&= ~E_M68HC11_I32
;
531 elf_flags
|= E_M68HC11_I32
;
534 case OPTION_MSHORT_DOUBLE
:
535 elf_flags
&= ~E_M68HC11_F64
;
538 case OPTION_MLONG_DOUBLE
:
539 elf_flags
|= E_M68HC11_F64
;
542 case OPTION_XGATE_RAMOFFSET
:
543 elf_flags
|= E_M68HC11_XGATE_RAMOFFSET
;
547 if ((strcasecmp (arg
, "68hc11") == 0)
548 || (strcasecmp (arg
, "m68hc11") == 0))
549 current_architecture
= cpu6811
;
550 else if ((strcasecmp (arg
, "68hc12") == 0)
551 || (strcasecmp (arg
, "m68hc12") == 0))
552 current_architecture
= cpu6812
;
553 else if ((strcasecmp (arg
, "68hcs12") == 0)
554 || (strcasecmp (arg
, "m68hcs12") == 0))
555 current_architecture
= cpu6812
| cpu6812s
;
556 else if (strcasecmp (arg
, "m9s12x") == 0)
557 current_architecture
= cpu6812
| cpu6812s
| cpu9s12x
;
558 else if ((strcasecmp (arg
, "m9s12xg") == 0)
559 || (strcasecmp (arg
, "xgate") == 0))
560 /* xgate for backwards compatability */
561 current_architecture
= cpuxgate
;
563 as_bad (_("Option `%s' is not recognized."), arg
);
574 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
580 md_atof (int type
, char *litP
, int *sizeP
)
582 return ieee_md_atof (type
, litP
, sizeP
, TRUE
);
586 md_section_align (asection
*seg
, valueT addr
)
588 int align
= bfd_get_section_alignment (stdoutput
, seg
);
589 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
593 cmp_opcode (struct m68hc11_opcode
*op1
, struct m68hc11_opcode
*op2
)
595 return strcmp (op1
->name
, op2
->name
);
598 #define IS_CALL_SYMBOL(MODE) \
599 (((MODE) & (M6812_OP_PAGE|M6811_OP_IND16)) \
600 == ((M6812_OP_PAGE|M6811_OP_IND16)))
602 /* Initialize the assembler. Create the opcode hash table
603 (sorted on the names) with the M6811 opcode table
604 (from opcode library). */
608 char *prev_name
= "";
609 struct m68hc11_opcode
*opcodes
;
610 struct m68hc11_opcode_def
*opc
= 0;
613 get_default_target ();
615 m68hc11_hash
= hash_new ();
617 /* Get a writable copy of the opcode table and sort it on the names. */
618 opcodes
= (struct m68hc11_opcode
*) xmalloc (m68hc11_num_opcodes
*
621 m68hc11_sorted_opcodes
= opcodes
;
623 for (i
= 0; i
< m68hc11_num_opcodes
; i
++)
625 if (m68hc11_opcodes
[i
].arch
& current_architecture
)
627 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
628 if (opcodes
[num_opcodes
].name
[0] == 'b'
629 && opcodes
[num_opcodes
].format
& M6811_OP_JUMP_REL
630 && !(opcodes
[num_opcodes
].format
& M6811_OP_BITMASK
))
633 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
636 for (j
= 0; alias_opcodes
[j
].name
!= 0; j
++)
637 if (strcmp (m68hc11_opcodes
[i
].name
, alias_opcodes
[j
].name
) == 0)
639 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
640 opcodes
[num_opcodes
].name
= alias_opcodes
[j
].alias
;
646 qsort (opcodes
, num_opcodes
, sizeof (struct m68hc11_opcode
),
647 (int (*) (const void*, const void*)) cmp_opcode
);
649 opc
= (struct m68hc11_opcode_def
*)
650 xmalloc (num_opcodes
* sizeof (struct m68hc11_opcode_def
));
651 m68hc11_opcode_defs
= opc
--;
653 /* Insert unique names into hash table. The M6811 instruction set
654 has several identical opcode names that have different opcodes based
655 on the operands. This hash table then provides a quick index to
656 the first opcode with a particular name in the opcode table. */
657 for (i
= 0; i
< num_opcodes
; i
++, opcodes
++)
661 if (strcmp (prev_name
, opcodes
->name
))
663 prev_name
= (char *) opcodes
->name
;
667 opc
->min_operands
= 100;
668 opc
->max_operands
= 0;
670 opc
->opcode
= opcodes
;
672 hash_insert (m68hc11_hash
, opcodes
->name
, opc
);
675 opc
->format
|= opcodes
->format
;
677 /* See how many operands this opcode needs. */
679 if (opcodes
->arch
== cpuxgate
)
681 if (opcodes
->format
& (M68XG_OP_IMM3
| M68XG_OP_R
| M68XG_OP_REL9
684 else if (opcodes
->format
& (M68XG_OP_R_R
| M68XG_OP_R_IMM4
685 | M68XG_OP_R_IMM8
| M68XG_OP_R_IMM8
))
687 else if (opcodes
->format
& (M68XG_OP_R_R_R
| M68XG_OP_R_R_OFFS5
688 | M68XG_OP_RD_RB_RI
| M68XG_OP_RD_RB_RIp
689 | M68XG_OP_RD_RB_mRI
))
694 if (opcodes
->format
& M6811_OP_MASK
)
696 if (opcodes
->format
& M6811_OP_BITMASK
)
698 if (opcodes
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
700 if (opcodes
->format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
702 /* Special case for call instruction. */
703 if ((opcodes
->format
& M6812_OP_PAGE
)
704 && !(opcodes
->format
& M6811_OP_IND16
))
708 if (expect
< opc
->min_operands
)
709 opc
->min_operands
= expect
;
710 if (IS_CALL_SYMBOL (opcodes
->format
))
712 if (expect
> opc
->max_operands
)
713 opc
->max_operands
= expect
;
716 m68hc11_nb_opcode_defs
= opc
- m68hc11_opcode_defs
;
718 if (flag_print_opcodes
)
720 print_opcode_list ();
726 m68hc11_init_after_args (void)
732 /* Return a string that represents the operand format for the instruction.
733 When example is true, this generates an example of operand. This is used
734 to give an example and also to generate a test. */
737 print_opcode_format (struct m68hc11_opcode
*opcode
, int example
)
739 static char buf
[128];
740 int format
= opcode
->format
;
746 if (current_architecture
== cpuxgate
)
748 if (format
& M68XG_OP_IMM3
)
751 sprintf (p
, "#%d", rand () & 0x007);
753 strcpy (p
, _("imm3"));
756 else if (format
& M68XG_OP_R
)
759 sprintf (p
, "R%d", rand () & 0x07);
764 else if (format
& M68XG_OP_R_R
)
767 sprintf (p
, "R%d,R%d", rand () & 0x07, rand () & 0x07);
769 strcpy (p
, _("RD,RS"));
772 else if (format
& M68XG_OP_R_IMM4
)
775 sprintf (p
, "R%d,#%d", rand () & 0x07, rand () & 0x0f);
777 strcpy (p
, _("RI, #imm4"));
780 else if (format
& M68XG_OP_R_R_R
)
783 sprintf (p
, "R%d,R%d,R%d", rand () & 0x07, rand () & 0x07, rand () & 0x07);
785 strcpy (p
, "RD,RS1,RS2");
788 else if (format
& M68XG_OP_REL9
)
791 sprintf (p
, "%d", rand () & 0x1FF);
793 strcpy (p
, "<rel9>");
796 else if (format
& M68XG_OP_REL10
)
799 sprintf (p
, "%d", rand () & 0x3FF);
801 strcpy (p
, "<rel10>");
804 else if (format
& M68XG_OP_R_R_OFFS5
)
807 sprintf (p
, "R%d, (R%d, #0x%x)", rand () & 0x07, rand () & 0x07, rand () & 0x1f);
809 strcpy (p
, _("RD, (RI,#offs5)"));
812 else if (format
& M68XG_OP_RD_RB_RI
)
815 sprintf (p
, "R%d, (R%d, R%d)", rand () & 0x07, rand () & 0x07, rand () & 0x07);
817 strcpy (p
, "RD, (RB, RI)");
820 else if (format
& M68XG_OP_RD_RB_RIp
)
823 sprintf (p
, "R%d, (R%d, R%d+)", rand () & 0x07, rand () & 0x07, rand () & 0x07);
825 strcpy (p
, "RD, (RB, RI+)");
828 else if (format
& M68XG_OP_RD_RB_mRI
)
831 sprintf (p
, "R%d, (R%d, -R%d)", rand () & 0x07, rand () & 0x07, rand () & 0x07);
833 strcpy (p
, "RD, (RB, -RI)");
836 else if (format
& M68XG_OP_R_IMM8
)
839 sprintf (p
, "R%d, #0x%x", rand () & 0x07, rand () & 0xff);
841 strcpy (p
, "RD, #imm8");
844 else if (format
& M68XG_OP_R_IMM16
)
847 sprintf (p
, "R%d, #0x%x", rand () & 0x07, rand () & 0xffff);
849 strcpy (p
, "RD, #imm16");
856 if (format
& M6811_OP_IMM8
)
859 sprintf (p
, "#%d", rand () & 0x0FF);
861 strcpy (p
, _("#<imm8>"));
865 if (format
& M6811_OP_IMM16
)
868 sprintf (p
, "#%d", rand () & 0x0FFFF);
870 strcpy (p
, _("#<imm16>"));
874 if (format
& M6811_OP_IX
)
877 sprintf (p
, "%d,X", rand () & 0x0FF);
879 strcpy (p
, _("<imm8>,X"));
883 if (format
& M6811_OP_IY
)
886 sprintf (p
, "%d,X", rand () & 0x0FF);
888 strcpy (p
, _("<imm8>,X"));
892 if (format
& M6812_OP_IDX
)
895 sprintf (p
, "%d,X", rand () & 0x0FF);
901 if (format
& M6812_OP_PAGE
)
904 sprintf (p
, ", %d", rand () & 0x0FF);
906 strcpy (p
, ", <page>");
910 if (format
& M6811_OP_DIRECT
)
913 sprintf (p
, "*Z%d", rand () & 0x0FF);
915 strcpy (p
, _("*<abs8>"));
919 if (format
& M6811_OP_BITMASK
)
925 sprintf (p
, "#$%02x", rand () & 0x0FF);
927 strcpy (p
, _("#<mask>"));
930 if (format
& M6811_OP_JUMP_REL
)
934 if (format
& M6811_OP_IND16
)
937 sprintf (p
, _("symbol%d"), rand () & 0x0FF);
939 strcpy (p
, _("<abs>"));
944 if (format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
948 if (format
& M6811_OP_BITMASK
)
950 sprintf (p
, ".+%d", rand () & 0x7F);
954 sprintf (p
, "L%d", rand () & 0x0FF);
958 strcpy (p
, _("<label>"));
964 /* Prints the list of instructions with the possible operands. */
966 print_opcode_list (void)
969 char *prev_name
= "";
970 struct m68hc11_opcode
*opcodes
;
971 int example
= flag_print_opcodes
== 2;
974 printf (_("# Example of `%s' instructions\n\t.sect .text\n_start:\n"),
977 opcodes
= m68hc11_sorted_opcodes
;
979 /* Walk the list sorted on names (by md_begin). We only report
980 one instruction per line, and we collect the different operand
982 for (i
= 0; i
< num_opcodes
; i
++, opcodes
++)
984 char *fmt
= print_opcode_format (opcodes
, example
);
988 printf ("L%d:\t", i
);
989 printf ("%s %s\n", opcodes
->name
, fmt
);
993 if (strcmp (prev_name
, opcodes
->name
))
998 printf ("%-5.5s ", opcodes
->name
);
999 prev_name
= (char *) opcodes
->name
;
1002 printf (" [%s]", fmt
);
1008 /* Print the instruction format. This operation is called when some
1009 instruction is not correct. Instruction format is printed as an
1012 print_insn_format (char *name
)
1014 struct m68hc11_opcode_def
*opc
;
1015 struct m68hc11_opcode
*opcode
;
1018 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, name
);
1021 as_bad (_("Instruction `%s' is not recognized."), name
);
1024 opcode
= opc
->opcode
;
1026 as_bad (_("Instruction formats for `%s':"), name
);
1031 fmt
= print_opcode_format (opcode
, 0);
1032 sprintf (buf
, "\t%-5.5s %s", opcode
->name
, fmt
);
1037 while (strcmp (opcode
->name
, name
) == 0);
1040 /* Analysis of 68HC11 and 68HC12 operands. */
1042 /* reg_name_search() finds the register number given its name.
1043 Returns the register number or REG_NONE on failure. */
1045 reg_name_search (char *name
)
1047 if (strcasecmp (name
, "x") == 0 || strcasecmp (name
, "ix") == 0)
1049 if (strcasecmp (name
, "y") == 0 || strcasecmp (name
, "iy") == 0)
1051 if (strcasecmp (name
, "a") == 0)
1053 if (strcasecmp (name
, "b") == 0)
1055 if (strcasecmp (name
, "d") == 0)
1057 if (strcasecmp (name
, "sp") == 0)
1059 if (strcasecmp (name
, "pc") == 0)
1061 if (strcasecmp (name
, "ccr") == 0)
1064 if (strcasecmp (name
, "r0") == 0)
1066 if (strcasecmp (name
, "r1") == 0)
1068 if (strcasecmp (name
, "r2") == 0)
1070 if (strcasecmp (name
, "r3") == 0)
1072 if (strcasecmp (name
, "r4") == 0)
1074 if (strcasecmp (name
, "r5") == 0)
1076 if (strcasecmp (name
, "r6") == 0)
1078 if (strcasecmp (name
, "r7") == 0)
1080 if (strcasecmp (name
, "sp") == 0)
1082 if (strcasecmp (name
, "pc") == 0)
1084 if (strcasecmp (name
, "ccr") == 0)
1090 skip_whites (char *p
)
1092 while (*p
== ' ' || *p
== '\t')
1098 /* Check the string at input_line_pointer
1099 to see if it is a valid register name. */
1101 register_name (void)
1103 register_id reg_number
;
1104 char c
, *p
= input_line_pointer
;
1106 if (!is_name_beginner (*p
++))
1109 while (is_part_of_name (*p
++))
1116 /* Look to see if it's in the register table. */
1117 reg_number
= reg_name_search (input_line_pointer
);
1118 if (reg_number
!= REG_NONE
)
1123 input_line_pointer
= p
;
1131 #define M6811_OP_CALL_ADDR 0x00800000
1132 #define M6811_OP_PAGE_ADDR 0x04000000
1134 /* Parse a string of operands and return an array of expressions.
1136 Operand mode[0] mode[1] exp[0] exp[1]
1137 #n M6811_OP_IMM16 - O_*
1138 *<exp> M6811_OP_DIRECT - O_*
1139 .{+-}<exp> M6811_OP_JUMP_REL - O_*
1140 <exp> M6811_OP_IND16 - O_*
1141 ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register
1142 n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register
1143 n,+r M6812_PRE_INC " "
1144 n,r- M6812_POST_DEC " "
1145 n,r+ M6812_POST_INC " "
1146 A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register
1147 [D,r] M6811_OP_D_IDX M6812_OP_REG O_register O_register
1148 [n,r] M6811_OP_D_IDX_2 M6812_OP_REG O_constant O_register */
1150 get_operand (operand
*oper
, int which
, long opmode
)
1152 char *p
= input_line_pointer
;
1156 oper
->exp
.X_op
= O_absent
;
1157 oper
->reg1
= REG_NONE
;
1158 oper
->reg2
= REG_NONE
;
1159 mode
= M6811_OP_NONE
;
1161 p
= skip_whites (p
);
1163 if (*p
== 0 || *p
== '\n' || *p
== '\r')
1165 input_line_pointer
= p
;
1169 if (*p
== '*' && (opmode
& (M6811_OP_DIRECT
| M6811_OP_IND16
)))
1171 mode
= M6811_OP_DIRECT
;
1176 if (!(opmode
& (M6811_OP_IMM8
| M6811_OP_IMM16
| M6811_OP_BITMASK
)))
1178 as_bad (_("Immediate operand is not allowed for operand %d."),
1183 mode
= M6811_OP_IMM16
;
1185 if (strncmp (p
, "%hi", 3) == 0)
1188 mode
|= M6811_OP_HIGH_ADDR
;
1190 else if (strncmp (p
, "%lo", 3) == 0)
1193 mode
|= M6811_OP_LOW_ADDR
;
1195 /* %page modifier is used to obtain only the page number
1196 of the address of a function. */
1197 else if (strncmp (p
, "%page", 5) == 0)
1200 mode
|= M6811_OP_PAGE_ADDR
;
1203 /* %addr modifier is used to obtain the physical address part
1204 of the function (16-bit). For 68HC12 the function will be
1205 mapped in the 16K window at 0x8000 and the value will be
1206 within that window (although the function address may not fit
1207 in 16-bit). See bfd/elf32-m68hc12.c for the translation. */
1208 else if (strncmp (p
, "%addr", 5) == 0)
1211 mode
|= M6811_OP_CALL_ADDR
;
1214 else if (*p
== '.' && (p
[1] == '+' || p
[1] == '-'))
1217 mode
= M6811_OP_JUMP_REL
;
1221 if (current_architecture
& cpu6811
)
1222 as_bad (_("Indirect indexed addressing is not valid for 68HC11."));
1225 mode
= M6812_OP_D_IDX
;
1226 p
= skip_whites (p
);
1228 else if (*p
== ',') /* Special handling of ,x and ,y. */
1231 input_line_pointer
= p
;
1233 reg
= register_name ();
1234 if (reg
!= REG_NONE
)
1237 oper
->exp
.X_op
= O_constant
;
1238 oper
->exp
.X_add_number
= 0;
1239 oper
->mode
= M6812_OP_IDX
;
1242 as_bad (_("Spurious `,' or bad indirect register addressing mode."));
1245 /* Handle 68HC12 page specification in 'call foo,%page(bar)'. */
1246 else if ((opmode
& M6812_OP_PAGE
) && strncmp (p
, "%page", 5) == 0)
1249 mode
= M6811_OP_PAGE_ADDR
| M6812_OP_PAGE
| M6811_OP_IND16
;
1251 input_line_pointer
= p
;
1253 if (mode
== M6811_OP_NONE
|| mode
== M6812_OP_D_IDX
)
1254 reg
= register_name ();
1258 if (reg
!= REG_NONE
)
1260 p
= skip_whites (input_line_pointer
);
1261 if (*p
== ']' && mode
== M6812_OP_D_IDX
)
1264 (_("Missing second register or offset for indexed-indirect mode."));
1269 oper
->mode
= mode
| M6812_OP_REG
;
1272 if (mode
== M6812_OP_D_IDX
)
1274 as_bad (_("Missing second register for indexed-indirect mode."));
1281 input_line_pointer
= p
;
1282 reg
= register_name ();
1283 if (reg
!= REG_NONE
)
1285 p
= skip_whites (input_line_pointer
);
1286 if (mode
== M6812_OP_D_IDX
)
1290 as_bad (_("Missing `]' to close indexed-indirect mode."));
1294 oper
->mode
= M6812_OP_D_IDX
;
1296 input_line_pointer
= p
;
1304 /* In MRI mode, isolate the operand because we can't distinguish
1305 operands from comments. */
1310 p
= skip_whites (p
);
1311 while (*p
&& *p
!= ' ' && *p
!= '\t')
1320 /* Parse as an expression. */
1321 expression (&oper
->exp
);
1330 expression (&oper
->exp
);
1333 if (oper
->exp
.X_op
== O_illegal
)
1335 as_bad (_("Illegal operand."));
1338 else if (oper
->exp
.X_op
== O_absent
)
1340 as_bad (_("Missing operand."));
1344 p
= input_line_pointer
;
1346 if (mode
== M6811_OP_NONE
|| mode
== M6811_OP_DIRECT
1347 || mode
== M6812_OP_D_IDX
)
1349 p
= skip_whites (input_line_pointer
);
1353 int possible_mode
= M6811_OP_NONE
;
1354 char *old_input_line
;
1359 /* 68HC12 pre increment or decrement. */
1360 if (mode
== M6811_OP_NONE
)
1364 possible_mode
= M6812_PRE_DEC
;
1369 possible_mode
= M6812_PRE_INC
;
1372 p
= skip_whites (p
);
1374 input_line_pointer
= p
;
1375 reg
= register_name ();
1377 /* Backtrack if we have a valid constant expression and
1378 it does not correspond to the offset of the 68HC12 indexed
1379 addressing mode (as in N,x). */
1380 if (reg
== REG_NONE
&& mode
== M6811_OP_NONE
1381 && possible_mode
!= M6811_OP_NONE
)
1383 oper
->mode
= M6811_OP_IND16
| M6811_OP_JUMP_REL
;
1384 input_line_pointer
= skip_whites (old_input_line
);
1388 if (possible_mode
!= M6811_OP_NONE
)
1389 mode
= possible_mode
;
1391 if ((current_architecture
& cpu6811
)
1392 && possible_mode
!= M6811_OP_NONE
)
1393 as_bad (_("Pre-increment mode is not valid for 68HC11"));
1395 if (which
== 0 && opmode
& M6812_OP_IDX_P2
1396 && reg
!= REG_X
&& reg
!= REG_Y
1397 && reg
!= REG_PC
&& reg
!= REG_SP
)
1400 input_line_pointer
= p
;
1403 if (reg
== REG_NONE
&& mode
!= M6811_OP_DIRECT
1404 && !(mode
== M6811_OP_NONE
&& opmode
& M6811_OP_IND16
))
1406 as_bad (_("Wrong register in register indirect mode."));
1409 if (mode
== M6812_OP_D_IDX
)
1411 p
= skip_whites (input_line_pointer
);
1414 as_bad (_("Missing `]' to close register indirect operand."));
1417 input_line_pointer
= p
;
1419 oper
->mode
= M6812_OP_D_IDX_2
;
1422 if (reg
!= REG_NONE
)
1425 if (mode
== M6811_OP_NONE
)
1427 p
= input_line_pointer
;
1430 mode
= M6812_POST_DEC
;
1432 if (current_architecture
& cpu6811
)
1434 (_("Post-decrement mode is not valid for 68HC11."));
1438 mode
= M6812_POST_INC
;
1440 if (current_architecture
& cpu6811
)
1442 (_("Post-increment mode is not valid for 68HC11."));
1445 mode
= M6812_OP_IDX
;
1447 input_line_pointer
= p
;
1450 mode
|= M6812_OP_IDX
;
1455 input_line_pointer
= old_input_line
;
1458 if (mode
== M6812_OP_D_IDX_2
)
1460 as_bad (_("Invalid indexed indirect mode."));
1465 /* If the mode is not known until now, this is either a label
1466 or an indirect address. */
1467 if (mode
== M6811_OP_NONE
)
1468 mode
= M6811_OP_IND16
| M6811_OP_JUMP_REL
;
1470 p
= input_line_pointer
;
1471 while (*p
== ' ' || *p
== '\t')
1473 input_line_pointer
= p
;
1479 #define M6812_AUTO_INC_DEC (M6812_PRE_INC | M6812_PRE_DEC \
1480 | M6812_POST_INC | M6812_POST_DEC)
1482 /* Checks that the number 'num' fits for a given mode. */
1484 check_range (long num
, int mode
)
1486 if (current_architecture
== cpuxgate
)
1491 return (num
>= 0 && num
<= 7) ? 1 : 0;
1493 case M68XG_OP_R_IMM4
:
1494 return (num
>= 0 && num
<= 15) ? 1 : 0;
1496 case M68XG_OP_R_R_OFFS5
:
1497 return (num
>= 0 && num
<= 31) ? 1 : 0;
1499 case M68XG_OP_R_IMM8
:
1500 return (num
>= 0 && num
<= 255) ? 1 : 0;
1502 case M68XG_OP_R_IMM16
:
1503 return (num
>= 0 && num
<= 65535) ? 1 : 0;
1505 case M68XG_OP_B_MARKER
:
1506 return (num
>= -512 && num
<= 511) ? 1 : 0;
1508 case M68XG_OP_BRA_MARKER
:
1509 return (num
>= -1024 && num
<= 1023) ? 1 : 0;
1517 /* Auto increment and decrement are ok for [-8..8] without 0. */
1518 if (mode
& M6812_AUTO_INC_DEC
)
1519 return (num
!= 0 && num
<= 8 && num
>= -8);
1521 /* The 68HC12 supports 5, 9 and 16-bit offsets. */
1522 if (mode
& (M6812_INDEXED_IND
| M6812_INDEXED
| M6812_OP_IDX
))
1523 mode
= M6811_OP_IND16
;
1525 if (mode
& M6812_OP_JUMP_REL16
)
1526 mode
= M6811_OP_IND16
;
1528 mode
&= ~M6811_OP_BRANCH
;
1533 case M6811_OP_DIRECT
:
1534 return (num
>= 0 && num
<= 255) ? 1 : 0;
1536 case M6811_OP_BITMASK
:
1539 return (((num
& 0xFFFFFF00) == 0) || ((num
& 0xFFFFFF00) == 0xFFFFFF00))
1542 case M6811_OP_JUMP_REL
:
1543 return (num
>= -128 && num
<= 127) ? 1 : 0;
1545 case M6811_OP_IND16
:
1546 case M6811_OP_IND16
| M6812_OP_PAGE
:
1547 case M6811_OP_IMM16
:
1548 return (((num
& 0xFFFF0000) == 0) || ((num
& 0xFFFF0000) == 0xFFFF0000))
1551 case M6812_OP_IBCC_MARKER
:
1552 case M6812_OP_TBCC_MARKER
:
1553 case M6812_OP_DBCC_MARKER
:
1554 return (num
>= -256 && num
<= 255) ? 1 : 0;
1556 case M6812_OP_TRAP_ID
:
1557 return ((num
>= 0x30 && num
<= 0x39)
1558 || (num
>= 0x40 && num
<= 0x0ff)) ? 1 : 0;
1566 /* Gas fixup generation. */
1568 /* Put a 1 byte expression described by 'oper'. If this expression contains
1569 unresolved symbols, generate an 8-bit fixup. */
1571 fixup8 (expressionS
*oper
, int mode
, int opmode
)
1577 if (oper
->X_op
== O_constant
)
1579 if (mode
& M6812_OP_TRAP_ID
1580 && !check_range (oper
->X_add_number
, M6812_OP_TRAP_ID
))
1582 static char trap_id_warn_once
= 0;
1584 as_bad (_("Trap id `%ld' is out of range."), oper
->X_add_number
);
1585 if (trap_id_warn_once
== 0)
1587 trap_id_warn_once
= 1;
1588 as_bad (_("Trap id must be within [0x30..0x39] or [0x40..0xff]."));
1592 if (!(mode
& M6812_OP_TRAP_ID
)
1593 && !check_range (oper
->X_add_number
, mode
))
1595 as_bad (_("Operand out of 8-bit range: `%ld'."), oper
->X_add_number
);
1597 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FF, 1);
1599 else if (oper
->X_op
!= O_register
)
1601 if (mode
& M6812_OP_TRAP_ID
)
1602 as_bad (_("The trap id must be a constant."));
1604 if (mode
== M6811_OP_JUMP_REL
)
1606 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1607 oper
, TRUE
, BFD_RELOC_8_PCREL
);
1614 /* Now create an 8-bit fixup. If there was some %hi, %lo
1615 or %page modifier, generate the reloc accordingly. */
1616 if (opmode
& M6811_OP_HIGH_ADDR
)
1617 reloc
= BFD_RELOC_M68HC11_HI8
;
1618 else if (opmode
& M6811_OP_LOW_ADDR
)
1619 reloc
= BFD_RELOC_M68HC11_LO8
;
1620 else if (opmode
& M6811_OP_PAGE_ADDR
)
1621 reloc
= BFD_RELOC_M68HC11_PAGE
;
1623 reloc
= BFD_RELOC_8
;
1625 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1626 oper
, FALSE
, reloc
);
1627 if (reloc
!= BFD_RELOC_8
)
1628 fixp
->fx_no_overflow
= 1;
1630 number_to_chars_bigendian (f
, 0, 1);
1634 as_fatal (_("Operand `%x' not recognized in fixup8."), oper
->X_op
);
1638 /* Put a 2 byte expression described by 'oper'. If this expression contains
1639 unresolved symbols, generate a 16-bit fixup. */
1641 fixup16 (expressionS
*oper
, int mode
, int opmode ATTRIBUTE_UNUSED
)
1647 if (oper
->X_op
== O_constant
)
1649 if (!check_range (oper
->X_add_number
, mode
))
1651 as_bad (_("Operand out of 16-bit range: `%ld'."),
1652 oper
->X_add_number
);
1654 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FFFF, 2);
1656 else if (oper
->X_op
!= O_register
)
1661 if ((opmode
& M6811_OP_CALL_ADDR
) && (mode
& M6811_OP_IMM16
))
1662 reloc
= BFD_RELOC_M68HC11_LO16
;
1663 else if (mode
& M6812_OP_JUMP_REL16
)
1664 reloc
= BFD_RELOC_16_PCREL
;
1665 else if (mode
& M6812_OP_PAGE
)
1666 reloc
= BFD_RELOC_M68HC11_LO16
;
1668 reloc
= BFD_RELOC_16
;
1670 /* Now create a 16-bit fixup. */
1671 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 2,
1673 reloc
== BFD_RELOC_16_PCREL
,
1675 number_to_chars_bigendian (f
, 0, 2);
1677 if (reloc
== BFD_RELOC_M68HC11_LO16
)
1678 fixp
->fx_no_overflow
= 1;
1682 as_fatal (_("Operand `%x' not recognized in fixup16."), oper
->X_op
);
1686 /* Put a 3 byte expression described by 'oper'. If this expression contains
1687 unresolved symbols, generate a 24-bit fixup. */
1689 fixup24 (expressionS
*oper
, int mode
, int opmode ATTRIBUTE_UNUSED
)
1695 if (oper
->X_op
== O_constant
)
1697 if (!check_range (oper
->X_add_number
, mode
))
1699 as_bad (_("Operand out of 16-bit range: `%ld'."),
1700 oper
->X_add_number
);
1702 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FFFFFF, 3);
1704 else if (oper
->X_op
!= O_register
)
1706 /* Now create a 24-bit fixup. */
1707 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 3,
1708 oper
, FALSE
, BFD_RELOC_M68HC11_24
);
1709 number_to_chars_bigendian (f
, 0, 3);
1713 as_fatal (_("Operand `%x' not recognized in fixup16."), oper
->X_op
);
1717 /* XGATE Put a 1 byte expression described by 'oper'. If this expression
1718 containts unresolved symbols, generate an 8-bit fixup. */
1720 fixup8_xg (expressionS
*oper
, int mode
, int opmode
)
1726 if (oper
->X_op
== O_constant
)
1731 if ((opmode
& M6811_OP_HIGH_ADDR
) || (opmode
& M6811_OP_LOW_ADDR
))
1733 if (opmode
& M6811_OP_HIGH_ADDR
)
1734 reloc
= BFD_RELOC_M68HC11_HI8
;
1736 reloc
= BFD_RELOC_M68HC11_LO8
;
1738 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1739 oper
, FALSE
, reloc
);
1740 fixp
->fx_no_overflow
= 1;
1741 number_to_chars_bigendian (f
, 0, 1);
1745 if (!(check_range (oper
->X_add_number
, mode
)))
1746 as_bad (_("Operand out of 8-bit range: `%ld'."),
1747 oper
->X_add_number
);
1748 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FF, 1);
1751 else if (oper
->X_op
!= O_register
)
1753 if (mode
== M68XG_OP_REL9
)
1755 /* Future improvement:
1756 This fixup/reloc isn't adding on constants to symbols. */
1757 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
-1, 2,
1758 oper
, TRUE
, BFD_RELOC_M68HC12_9_PCREL
);
1760 else if (mode
== M68XG_OP_REL10
)
1762 /* Future improvement:
1763 This fixup/reloc isn't adding on constants to symbols. */
1764 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
-1, 2,
1765 oper
, TRUE
, BFD_RELOC_M68HC12_10_PCREL
);
1772 /* Now create an 8-bit fixup. If there was some %hi, %lo
1773 modifier, generate the reloc accordingly. */
1774 if (opmode
& M6811_OP_HIGH_ADDR
)
1775 reloc
= BFD_RELOC_M68HC11_HI8
;
1776 else if (opmode
& M6811_OP_LOW_ADDR
)
1777 reloc
= BFD_RELOC_M68HC11_LO8
;
1779 reloc
= BFD_RELOC_8
;
1781 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1782 oper
, FALSE
, reloc
);
1783 if (reloc
!= BFD_RELOC_8
)
1784 fixp
->fx_no_overflow
= 1;
1786 number_to_chars_bigendian (f
, 0, 1);
1789 as_fatal (_("Operand `%x' not recognized in fixup8."), oper
->X_op
);
1792 /* 68HC11 and 68HC12 code generation. */
1794 /* Translate the short branch/bsr instruction into a long branch. */
1796 static unsigned char
1797 convert_branch (unsigned char code
)
1799 if (IS_OPCODE (code
, M6812_BSR
))
1801 else if (IS_OPCODE (code
, M6811_BSR
))
1803 else if (IS_OPCODE (code
, M6811_BRA
))
1804 return (current_architecture
& cpu6812
) ? M6812_JMP
: M6811_JMP
;
1806 as_fatal (_("Unexpected branch conversion with `%x'"), code
);
1808 /* Keep gcc happy. */
1812 /* Start a new insn that contains at least 'size' bytes. Record the
1813 line information of that insn in the dwarf2 debug sections. */
1815 m68hc11_new_insn (int size
)
1819 f
= frag_more (size
);
1821 dwarf2_emit_insn (size
);
1826 /* Builds a jump instruction (bra, bcc, bsr). */
1828 build_jump_insn (struct m68hc11_opcode
*opcode
, operand operands
[],
1829 int nb_operands
, int jmp_mode
)
1835 /* The relative branch conversion is not supported for
1837 gas_assert ((opcode
->format
& M6811_OP_BITMASK
) == 0);
1838 gas_assert (nb_operands
== 1);
1839 gas_assert (operands
[0].reg1
== REG_NONE
&& operands
[0].reg2
== REG_NONE
);
1841 code
= opcode
->opcode
;
1843 n
= operands
[0].exp
.X_add_number
;
1845 /* Turn into a long branch:
1846 - when force long branch option (and not for jbcc pseudos),
1847 - when jbcc and the constant is out of -128..127 range,
1848 - when branch optimization is allowed and branch out of range. */
1849 if ((jmp_mode
== 0 && flag_force_long_jumps
)
1850 || (operands
[0].exp
.X_op
== O_constant
1851 && (!check_range (n
, opcode
->format
) &&
1852 (jmp_mode
== 1 || flag_fixed_branches
== 0))))
1854 fix_new (frag_now
, frag_now_fix (), 0,
1855 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1857 if (code
== M6811_BSR
|| code
== M6811_BRA
|| code
== M6812_BSR
)
1859 code
= convert_branch (code
);
1861 f
= m68hc11_new_insn (1);
1862 number_to_chars_bigendian (f
, code
, 1);
1864 else if (current_architecture
& cpu6812
)
1866 /* 68HC12: translate the bcc into a lbcc. */
1867 f
= m68hc11_new_insn (2);
1868 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1869 number_to_chars_bigendian (f
+ 1, code
, 1);
1870 fixup16 (&operands
[0].exp
, M6812_OP_JUMP_REL16
,
1871 M6812_OP_JUMP_REL16
);
1876 /* 68HC11: translate the bcc into b!cc +3; jmp <L>. */
1877 f
= m68hc11_new_insn (3);
1879 number_to_chars_bigendian (f
, code
, 1);
1880 number_to_chars_bigendian (f
+ 1, 3, 1);
1881 number_to_chars_bigendian (f
+ 2, M6811_JMP
, 1);
1883 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, M6811_OP_IND16
);
1887 /* Branch with a constant that must fit in 8-bits. */
1888 if (operands
[0].exp
.X_op
== O_constant
)
1890 if (!check_range (n
, opcode
->format
))
1892 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1895 else if (opcode
->format
& M6812_OP_JUMP_REL16
)
1897 f
= m68hc11_new_insn (4);
1898 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1899 number_to_chars_bigendian (f
+ 1, code
, 1);
1900 number_to_chars_bigendian (f
+ 2, n
& 0x0ffff, 2);
1904 f
= m68hc11_new_insn (2);
1905 number_to_chars_bigendian (f
, code
, 1);
1906 number_to_chars_bigendian (f
+ 1, n
& 0x0FF, 1);
1909 else if (opcode
->format
& M6812_OP_JUMP_REL16
)
1911 fix_new (frag_now
, frag_now_fix (), 0,
1912 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1914 f
= m68hc11_new_insn (2);
1915 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1916 number_to_chars_bigendian (f
+ 1, code
, 1);
1917 fixup16 (&operands
[0].exp
, M6812_OP_JUMP_REL16
, M6812_OP_JUMP_REL16
);
1923 fix_new (frag_now
, frag_now_fix (), 0,
1924 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1926 /* Branch offset must fit in 8-bits, don't do some relax. */
1927 if (jmp_mode
== 0 && flag_fixed_branches
)
1929 op
= m68hc11_new_insn (1);
1930 number_to_chars_bigendian (op
, code
, 1);
1931 fixup8 (&operands
[0].exp
, M6811_OP_JUMP_REL
, M6811_OP_JUMP_REL
);
1934 /* bra/bsr made be changed into jmp/jsr. */
1935 else if (code
== M6811_BSR
|| code
== M6811_BRA
|| code
== M6812_BSR
)
1937 /* Allocate worst case storage. */
1938 op
= m68hc11_new_insn (3);
1939 number_to_chars_bigendian (op
, code
, 1);
1940 number_to_chars_bigendian (op
+ 1, 0, 1);
1941 frag_variant (rs_machine_dependent
, 1, 1,
1942 ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_UNDF
),
1943 operands
[0].exp
.X_add_symbol
, (offsetT
) n
,
1946 else if (current_architecture
& cpu6812
)
1948 op
= m68hc11_new_insn (2);
1949 number_to_chars_bigendian (op
, code
, 1);
1950 number_to_chars_bigendian (op
+ 1, 0, 1);
1951 frag_var (rs_machine_dependent
, 2, 2,
1952 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_UNDF
),
1953 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, op
);
1957 op
= m68hc11_new_insn (2);
1958 number_to_chars_bigendian (op
, code
, 1);
1959 number_to_chars_bigendian (op
+ 1, 0, 1);
1960 frag_var (rs_machine_dependent
, 3, 3,
1961 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_UNDF
),
1962 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, op
);
1967 /* Builds a dbne/dbeq/tbne/tbeq instruction. */
1969 build_dbranch_insn (struct m68hc11_opcode
*opcode
, operand operands
[],
1970 int nb_operands
, int jmp_mode
)
1976 /* The relative branch conversion is not supported for
1978 gas_assert ((opcode
->format
& M6811_OP_BITMASK
) == 0);
1979 gas_assert (nb_operands
== 2);
1980 gas_assert (operands
[0].reg1
!= REG_NONE
);
1982 code
= opcode
->opcode
& 0x0FF;
1984 f
= m68hc11_new_insn (1);
1985 number_to_chars_bigendian (f
, code
, 1);
1987 n
= operands
[1].exp
.X_add_number
;
1988 code
= operands
[0].reg1
;
1990 if (operands
[0].reg1
== REG_NONE
|| operands
[0].reg1
== REG_CCR
1991 || operands
[0].reg1
== REG_PC
)
1992 as_bad (_("Invalid register for dbcc/tbcc instruction."));
1994 if (opcode
->format
& M6812_OP_IBCC_MARKER
)
1996 else if (opcode
->format
& M6812_OP_TBCC_MARKER
)
1999 if (!(opcode
->format
& M6812_OP_EQ_MARKER
))
2002 /* Turn into a long branch:
2003 - when force long branch option (and not for jbcc pseudos),
2004 - when jdbcc and the constant is out of -256..255 range,
2005 - when branch optimization is allowed and branch out of range. */
2006 if ((jmp_mode
== 0 && flag_force_long_jumps
)
2007 || (operands
[1].exp
.X_op
== O_constant
2008 && (!check_range (n
, M6812_OP_IBCC_MARKER
) &&
2009 (jmp_mode
== 1 || flag_fixed_branches
== 0))))
2013 number_to_chars_bigendian (f
, code
, 1);
2014 number_to_chars_bigendian (f
+ 1, M6812_JMP
, 1);
2015 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, M6811_OP_IND16
);
2019 /* Branch with a constant that must fit in 9-bits. */
2020 if (operands
[1].exp
.X_op
== O_constant
)
2022 if (!check_range (n
, M6812_OP_IBCC_MARKER
))
2024 as_bad (_("Operand out of range for a relative branch: `%ld'"),
2033 number_to_chars_bigendian (f
, code
, 1);
2034 number_to_chars_bigendian (f
+ 1, n
& 0x0FF, 1);
2039 /* Branch offset must fit in 8-bits, don't do some relax. */
2040 if (jmp_mode
== 0 && flag_fixed_branches
)
2042 fixup8 (&operands
[0].exp
, M6811_OP_JUMP_REL
, M6811_OP_JUMP_REL
);
2048 number_to_chars_bigendian (f
, code
, 1);
2049 number_to_chars_bigendian (f
+ 1, 0, 1);
2050 frag_var (rs_machine_dependent
, 3, 3,
2051 ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_UNDF
),
2052 operands
[1].exp
.X_add_symbol
, (offsetT
) n
, f
);
2057 #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4)
2059 /* Assemble the post index byte for 68HC12 extended addressing modes. */
2062 build_indexed_byte (operand
*op
, int format ATTRIBUTE_UNUSED
, int move_insn
)
2064 unsigned char byte
= 0;
2069 val
= op
->exp
.X_add_number
;
2071 if (mode
& M6812_AUTO_INC_DEC
)
2074 if (mode
& (M6812_POST_INC
| M6812_POST_DEC
))
2077 if (op
->exp
.X_op
== O_constant
)
2079 if (!check_range (val
, mode
))
2080 as_bad (_("Increment/decrement value is out of range: `%ld'."),
2083 if (mode
& (M6812_POST_INC
| M6812_PRE_INC
))
2084 byte
|= (val
- 1) & 0x07;
2086 byte
|= (8 - ((val
) & 7)) | 0x8;
2092 as_fatal (_("Expecting a register."));
2107 as_bad (_("Invalid register for post/pre increment."));
2112 number_to_chars_bigendian (f
, byte
, 1);
2116 if (mode
& (M6812_OP_IDX
| M6812_OP_D_IDX_2
))
2137 as_bad (_("Invalid register."));
2141 if (op
->exp
.X_op
== O_constant
)
2143 if (!check_range (val
, M6812_OP_IDX
))
2144 as_bad (_("Offset out of 16-bit range: %ld."), val
);
2146 if (move_insn
&& !(val
>= -16 && val
<= 15)
2147 && ((!(mode
& M6812_OP_IDX
) && !(mode
& M6812_OP_D_IDX_2
))
2148 || !(current_architecture
& cpu9s12x
)))
2150 as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."),
2155 if (val
>= -16 && val
<= 15 && !(mode
& M6812_OP_D_IDX_2
))
2160 number_to_chars_bigendian (f
, byte
, 1);
2163 else if (val
>= -256 && val
<= 255 && !(mode
& M6812_OP_D_IDX_2
))
2170 number_to_chars_bigendian (f
, byte
, 1);
2171 number_to_chars_bigendian (f
+ 1, val
& 0x0FF, 1);
2177 if (mode
& M6812_OP_D_IDX_2
)
2183 number_to_chars_bigendian (f
, byte
, 1);
2184 number_to_chars_bigendian (f
+ 1, val
& 0x0FFFF, 2);
2189 if (mode
& M6812_OP_D_IDX_2
)
2191 byte
= (byte
<< 3) | 0xe3;
2193 number_to_chars_bigendian (f
, byte
, 1);
2195 fixup16 (&op
->exp
, 0, 0);
2197 else if (op
->reg1
!= REG_PC
)
2203 number_to_chars_bigendian (f
, byte
, 1);
2204 sym
= op
->exp
.X_add_symbol
;
2205 off
= op
->exp
.X_add_number
;
2206 if (op
->exp
.X_op
!= O_symbol
)
2208 sym
= make_expr_symbol (&op
->exp
);
2212 /* movb/movw cannot be relaxed. */
2215 if ((mode
& M6812_OP_IDX
) && (current_architecture
& cpu9s12x
))
2217 /* Must treat as a 16bit relocate as size of final result is unknown. */
2221 number_to_chars_bigendian (f
, byte
, 1);
2223 fix_new (frag_now
, f
- frag_now
->fr_literal
, 2,
2224 sym
, off
, 0, BFD_RELOC_M68HC12_16B
);
2229 /* Non-S12X will fail at relocate stage if offset out of range. */
2231 number_to_chars_bigendian (f
, byte
, 1);
2232 fix_new (frag_now
, f
- frag_now
->fr_literal
, 1,
2233 sym
, off
, 0, BFD_RELOC_M68HC12_5B
);
2239 number_to_chars_bigendian (f
, byte
, 1);
2240 frag_var (rs_machine_dependent
, 2, 2,
2241 ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_UNDF
),
2249 /* movb/movw cannot be relaxed. */
2253 number_to_chars_bigendian (f
, byte
, 1);
2254 fix_new (frag_now
, f
- frag_now
->fr_literal
, 1,
2255 op
->exp
.X_add_symbol
, op
->exp
.X_add_number
, 0, BFD_RELOC_M68HC12_5B
);
2260 number_to_chars_bigendian (f
, byte
, 1);
2261 frag_var (rs_machine_dependent
, 2, 2,
2262 ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_UNDF
),
2263 op
->exp
.X_add_symbol
,
2264 op
->exp
.X_add_number
, f
);
2270 if (mode
& (M6812_OP_REG
| M6812_OP_D_IDX
))
2272 if (mode
& M6812_OP_D_IDX
)
2274 if (op
->reg1
!= REG_D
)
2275 as_bad (_("Expecting register D for indexed indirect mode."));
2276 if ((move_insn
) && (!(current_architecture
& cpu9s12x
)))
2277 as_bad (_("Indexed indirect mode is not allowed for movb/movw."));
2294 as_bad (_("Invalid accumulator register."));
2319 as_bad (_("Invalid indexed register."));
2323 number_to_chars_bigendian (f
, byte
, 1);
2327 fprintf (stderr
, "mode = 0x%x\nop->reg1 = 0x%x\nop->reg2 = 0x%x\n",
2328 mode
, op
->reg1
, op
->reg2
);
2329 as_fatal (_("Addressing mode not implemented yet."));
2333 /* Assemble the 68HC12 register mode byte. */
2335 build_reg_mode (operand
*op
, int format
)
2340 if ((format
& M6812_OP_SEX_MARKER
)
2341 && (op
->reg1
!= REG_A
) && (op
->reg1
!= REG_B
) && (op
->reg1
!= REG_CCR
)
2342 && (!(current_architecture
& cpu9s12x
)))
2343 as_bad (_("Invalid source register for this instruction, use 'tfr'."));
2344 else if (op
->reg1
== REG_NONE
|| op
->reg1
== REG_PC
)
2345 as_bad (_("Invalid source register."));
2347 if (format
& M6812_OP_SEX_MARKER
2348 && op
->reg2
!= REG_D
2349 && op
->reg2
!= REG_X
&& op
->reg2
!= REG_Y
&& op
->reg2
!= REG_SP
)
2350 as_bad (_("Invalid destination register for this instruction, use 'tfr'."));
2351 else if (op
->reg2
== REG_NONE
|| op
->reg2
== REG_PC
)
2352 as_bad (_("Invalid destination register."));
2354 byte
= (op
->reg1
<< 4) | (op
->reg2
);
2355 if (format
& M6812_OP_EXG_MARKER
)
2358 if ((format
& M6812_OP_SEX_MARKER
)
2359 && (op
->reg1
== REG_D
) && (current_architecture
& cpu9s12x
))
2363 number_to_chars_bigendian (f
, byte
, 1);
2367 /* build_insn_xg takes a pointer to the opcode entry in the opcode table,
2368 the array of operand expressions and builds the corresponding instruction. */
2371 build_insn_xg (struct m68hc11_opcode
*opcode
,
2373 int nb_operands ATTRIBUTE_UNUSED
)
2378 /* Put the page code instruction if there is one. */
2379 format
= opcode
->format
;
2381 if (!(operands
[0].mode
& (M6811_OP_LOW_ADDR
| M6811_OP_HIGH_ADDR
)))
2382 /* Need to retain those two modes, but clear for others. */
2383 operands
[0].mode
= 0;
2385 if (format
& M68XG_OP_R_IMM8
)
2387 /* These opcodes are byte followed by imm8. */
2388 f
= m68hc11_new_insn (1);
2389 number_to_chars_bigendian (f
, opcode
->opcode
>> 8, 1);
2390 fixup8_xg (&operands
[0].exp
, format
, operands
[0].mode
);
2392 else if (format
& M68XG_OP_R_IMM16
)
2395 /* These opcodes expand into two imm8 instructions.
2396 Emit as low:high as per the Freescale datasheet.
2397 The linker requires them to be adjacent to handle the upper byte. */
2399 /* Build low byte. */
2400 f
= m68hc11_new_insn (1);
2401 number_to_chars_bigendian (f
, opcode
->opcode
>> 8, 1);
2402 operands
[0].mode
= M6811_OP_LOW_ADDR
;
2404 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
2405 &operands
[0].exp
, FALSE
, BFD_RELOC_M68HC12_LO8XG
);
2406 fixp
->fx_no_overflow
= 1;
2407 number_to_chars_bigendian (f
, 0, 1);
2409 /* Build high byte. */
2410 f
= m68hc11_new_insn (1);
2411 number_to_chars_bigendian (f
, (opcode
->opcode
>> 8) | 0x08, 1);
2412 operands
[0].mode
= M6811_OP_HIGH_ADDR
;
2414 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
2415 &operands
[0].exp
, FALSE
, BFD_RELOC_M68HC12_HI8XG
);
2416 fixp
->fx_no_overflow
= 1;
2417 number_to_chars_bigendian (f
, 0, 1);
2420 else if (format
& M68XG_OP_REL9
)
2422 f
= m68hc11_new_insn (1);
2423 number_to_chars_bigendian (f
, opcode
->opcode
>> 8, 1); /* High byte. */
2424 fixup8_xg (&operands
[0].exp
, format
, M68XG_OP_REL9
);
2426 else if (format
& M68XG_OP_REL10
)
2428 f
= m68hc11_new_insn (1);
2429 number_to_chars_bigendian (f
, opcode
->opcode
>> 8, 1); /* High byte. */
2430 fixup8_xg (&operands
[0].exp
, format
, M68XG_OP_REL10
);
2434 f
= m68hc11_new_insn (2);
2435 number_to_chars_bigendian (f
, opcode
->opcode
, 2);
2440 /* build_insn takes a pointer to the opcode entry in the opcode table,
2441 the array of operand expressions and builds the corresponding instruction.
2442 This operation only deals with non relative jumps insn (need special
2446 build_insn (struct m68hc11_opcode
*opcode
,
2448 int nb_operands ATTRIBUTE_UNUSED
)
2455 /* Put the page code instruction if there is one. */
2456 format
= opcode
->format
;
2458 if (format
& M6811_OP_BRANCH
)
2459 fix_new (frag_now
, frag_now_fix (), 0,
2460 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
2462 if (format
& OP_EXTENDED
)
2466 f
= m68hc11_new_insn (2);
2467 if (format
& M6811_OP_PAGE2
)
2468 page_code
= M6811_OPCODE_PAGE2
;
2469 else if (format
& M6811_OP_PAGE3
)
2470 page_code
= M6811_OPCODE_PAGE3
;
2472 page_code
= M6811_OPCODE_PAGE4
;
2474 number_to_chars_bigendian (f
, page_code
, 1);
2478 f
= m68hc11_new_insn (1);
2480 number_to_chars_bigendian (f
, opcode
->opcode
, 1);
2484 /* The 68HC12 movb and movw instructions are special. We have to handle
2485 them in a special way. */
2486 if (format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
2489 if (format
& M6812_OP_IDX
)
2491 build_indexed_byte (&operands
[0], format
, 1);
2493 format
&= ~M6812_OP_IDX
;
2495 if (format
& M6812_OP_IDX_P2
)
2497 build_indexed_byte (&operands
[1], format
, 1);
2499 format
&= ~M6812_OP_IDX_P2
;
2503 if (format
& (M6811_OP_DIRECT
| M6811_OP_IMM8
))
2505 fixup8 (&operands
[i
].exp
,
2506 format
& (M6811_OP_DIRECT
| M6811_OP_IMM8
| M6812_OP_TRAP_ID
),
2510 else if (IS_CALL_SYMBOL (format
) && nb_operands
== 1)
2512 format
&= ~M6812_OP_PAGE
;
2513 fixup24 (&operands
[i
].exp
, format
& M6811_OP_IND16
,
2517 else if (format
& (M6811_OP_IMM16
| M6811_OP_IND16
))
2519 fixup16 (&operands
[i
].exp
,
2520 format
& (M6811_OP_IMM16
| M6811_OP_IND16
| M6812_OP_PAGE
),
2524 else if (format
& (M6811_OP_IX
| M6811_OP_IY
))
2526 if ((format
& M6811_OP_IX
) && (operands
[0].reg1
!= REG_X
))
2527 as_bad (_("Invalid indexed register, expecting register X."));
2528 if ((format
& M6811_OP_IY
) && (operands
[0].reg1
!= REG_Y
))
2529 as_bad (_("Invalid indexed register, expecting register Y."));
2531 fixup8 (&operands
[0].exp
, M6811_OP_IX
, operands
[0].mode
);
2535 (M6812_OP_IDX
| M6812_OP_IDX_2
| M6812_OP_IDX_1
2536 | M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
2538 build_indexed_byte (&operands
[i
], format
, move_insn
);
2541 else if (format
& M6812_OP_REG
&& current_architecture
& cpu6812
)
2543 build_reg_mode (&operands
[i
], format
);
2546 if (format
& M6811_OP_BITMASK
)
2548 fixup8 (&operands
[i
].exp
, M6811_OP_BITMASK
, operands
[i
].mode
);
2551 if (format
& M6811_OP_JUMP_REL
)
2553 fixup8 (&operands
[i
].exp
, M6811_OP_JUMP_REL
, operands
[i
].mode
);
2555 else if (format
& M6812_OP_IND16_P2
)
2557 fixup16 (&operands
[1].exp
, M6811_OP_IND16
, operands
[1].mode
);
2559 if (format
& M6812_OP_PAGE
)
2561 fixup8 (&operands
[i
].exp
, M6812_OP_PAGE
, operands
[i
].mode
);
2565 /* Opcode identification and operand analysis. */
2567 /* find() gets a pointer to an entry in the opcode table. It must look at all
2568 opcodes with the same name and use the operands to choose the correct
2569 opcode. Returns the opcode pointer if there was a match and 0 if none. */
2570 static struct m68hc11_opcode
*
2571 find (struct m68hc11_opcode_def
*opc
, operand operands
[], int nb_operands
)
2574 struct m68hc11_opcode
*opcode
;
2575 struct m68hc11_opcode
*op_indirect
;
2578 opcode
= opc
->opcode
;
2580 /* Now search the opcode table table for one with operands
2581 that matches what we've got. */
2583 if (current_architecture
& cpuxgate
)
2585 /* Many XGATE insns are simple enough that we get an exact match. */
2586 for (pos
= match
= 0; match
== 0 && pos
< opc
->nb_modes
; pos
++, opcode
++)
2587 if (opcode
->format
== operands
[nb_operands
-1].mode
)
2595 /* Now search the opcode table table for one with operands
2596 that matches what we've got. We're only done if the operands matched so
2597 far AND there are no more to check. */
2598 for (pos
= match
= 0; match
== 0 && pos
< opc
->nb_modes
; pos
++, opcode
++)
2600 int poss_indirect
= 0;
2601 long format
= opcode
->format
;
2605 if (opcode
->format
& M6811_OP_MASK
)
2607 if (opcode
->format
& M6811_OP_BITMASK
)
2609 if (opcode
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2611 if (opcode
->format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
2613 if ((opcode
->format
& M6812_OP_PAGE
)
2614 && (!IS_CALL_SYMBOL (opcode
->format
) || nb_operands
== 2))
2617 for (i
= 0; expect
== nb_operands
&& i
< nb_operands
; i
++)
2619 int mode
= operands
[i
].mode
;
2621 if (mode
& M6811_OP_IMM16
)
2624 (M6811_OP_IMM8
| M6811_OP_IMM16
| M6811_OP_BITMASK
))
2628 if (mode
== M6811_OP_DIRECT
)
2630 if (format
& M6811_OP_DIRECT
)
2633 /* If the operand is a page 0 operand, remember a
2634 possible <abs-16> addressing mode. We mark
2635 this and continue to check other operands. */
2636 if (format
& M6811_OP_IND16
2637 && flag_strict_direct_addressing
&& op_indirect
== 0)
2644 if (mode
& M6811_OP_IND16
)
2646 if (i
== 0 && (format
& M6811_OP_IND16
) != 0)
2648 if (i
!= 0 && (format
& M6812_OP_PAGE
) != 0)
2650 if (i
!= 0 && (format
& M6812_OP_IND16_P2
) != 0)
2652 if (i
== 0 && (format
& M6811_OP_BITMASK
))
2655 if (mode
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2657 if (format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2660 if (mode
& M6812_OP_REG
)
2663 && (format
& M6812_OP_REG
)
2664 && (operands
[i
].reg2
== REG_NONE
))
2667 && (format
& M6812_OP_REG
)
2668 && (format
& M6812_OP_REG_2
)
2669 && (operands
[i
].reg2
!= REG_NONE
))
2672 && (format
& M6812_OP_IDX
)
2673 && (operands
[i
].reg2
!= REG_NONE
))
2676 && (format
& M6812_OP_IDX
)
2677 && (format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
)))
2680 && (format
& M6812_OP_IDX_P2
))
2684 if (mode
& M6812_OP_IDX
)
2686 if (format
& M6811_OP_IX
&& operands
[i
].reg1
== REG_X
)
2688 if (format
& M6811_OP_IY
&& operands
[i
].reg1
== REG_Y
)
2691 && format
& (M6812_OP_IDX
| M6812_OP_IDX_1
| M6812_OP_IDX_2
)
2692 && (operands
[i
].reg1
== REG_X
2693 || operands
[i
].reg1
== REG_Y
2694 || operands
[i
].reg1
== REG_SP
2695 || operands
[i
].reg1
== REG_PC
))
2697 if (i
== 1 && (format
& M6812_OP_IDX_P2
))
2700 if (mode
& format
& (M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
2705 if (mode
& M6812_AUTO_INC_DEC
)
2708 && format
& (M6812_OP_IDX
| M6812_OP_IDX_1
|
2711 if (i
== 1 && format
& M6812_OP_IDX_P2
)
2716 match
= i
== nb_operands
;
2718 /* Operands are ok but an operand uses page 0 addressing mode
2719 while the insn supports abs-16 mode. Keep a reference to this
2720 insns in case there is no insn supporting page 0 addressing. */
2721 if (match
&& poss_indirect
)
2723 op_indirect
= opcode
;
2730 /* Page 0 addressing is used but not supported by any insn.
2731 If absolute addresses are supported, we use that insn. */
2732 if (match
== 0 && op_indirect
)
2734 opcode
= op_indirect
;
2738 return match
? opcode
: 0;
2741 /* Find the real opcode and its associated operands. We use a progressive
2742 approach here. On entry, 'opc' points to the first opcode in the
2743 table that matches the opcode name in the source line. We try to
2744 isolate an operand, find a possible match in the opcode table.
2745 We isolate another operand if no match were found. The table 'operands'
2746 is filled while operands are recognized.
2748 Returns the opcode pointer that matches the opcode name in the
2749 source line and the associated operands. */
2750 static struct m68hc11_opcode
*
2751 find_opcode (struct m68hc11_opcode_def
*opc
, operand operands
[],
2754 struct m68hc11_opcode
*opcode
;
2757 if (opc
->max_operands
== 0)
2763 for (i
= 0; i
< opc
->max_operands
;)
2767 result
= get_operand (&operands
[i
], i
, opc
->format
);
2771 /* Special case where the bitmask of the bclr/brclr
2772 instructions is not introduced by #.
2773 Example: bclr 3,x $80. */
2774 if (i
== 1 && (opc
->format
& M6811_OP_BITMASK
)
2775 && (operands
[i
].mode
& M6811_OP_IND16
))
2777 operands
[i
].mode
= M6811_OP_IMM16
;
2782 if (i
>= opc
->min_operands
)
2784 opcode
= find (opc
, operands
, i
);
2786 /* Another special case for 'call foo,page' instructions.
2787 Since we support 'call foo' and 'call foo,page' we must look
2788 if the optional page specification is present otherwise we will
2789 assemble immediately and treat the page spec as garbage. */
2790 if (opcode
&& !(opcode
->format
& M6812_OP_PAGE
))
2793 if (opcode
&& *input_line_pointer
!= ',')
2797 if (*input_line_pointer
== ',')
2798 input_line_pointer
++;
2804 #define M6812_XBCC_MARKER (M6812_OP_TBCC_MARKER \
2805 | M6812_OP_DBCC_MARKER \
2806 | M6812_OP_IBCC_MARKER)
2808 /* Gas line assembler entry point. */
2810 /* This is the main entry point for the machine-dependent assembler. str
2811 points to a machine-dependent instruction. This function is supposed to
2812 emit the frags/bytes it assembles to. */
2814 md_assemble (char *str
)
2816 struct m68hc11_opcode_def
*opc
;
2817 struct m68hc11_opcode
*opcode
;
2819 struct m68hc11_opcode opcode_local
;
2820 unsigned char *op_start
, *op_end
;
2824 operand operands
[M6811_MAX_OPERANDS
];
2825 int nb_operands
= 0;
2826 int branch_optimize
= 0;
2829 /* Drop leading whitespace. */
2833 /* Find the opcode end and get the opcode in 'name'. The opcode is forced
2834 lower case (the opcode table only has lower case op-codes). */
2835 for (op_start
= op_end
= (unsigned char *) str
;
2836 *op_end
&& !is_end_of_line
[*op_end
] && *op_end
!= ' ';
2839 name
[nlen
] = TOLOWER (op_start
[nlen
]);
2841 if (nlen
== sizeof (name
) - 1)
2848 as_bad (_("No instruction or missing opcode."));
2852 if (current_architecture
== cpuxgate
)
2854 /* Find the opcode definition given its name. */
2855 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, name
);
2858 as_bad (_("Opcode `%s' is not recognized."), name
);
2862 /* Grab a local copy. */
2863 opcode_local
.name
= opc
->opcode
->name
;
2864 /* These will be incomplete where multiple variants exist. */
2865 opcode_local
.opcode
= opc
->opcode
->opcode
;
2866 opcode_local
.format
= opc
->opcode
->format
;
2868 save
= input_line_pointer
;
2869 input_line_pointer
= (char *) op_end
;
2871 if (opc
->format
== M68XG_OP_NONE
)
2873 /* No special handling required. */
2874 opcode_local
.format
= M68XG_OP_NONE
;
2875 build_insn_xg (opc
->opcode
, operands
, 0);
2879 /* Special handling of TFR. */
2880 if (strncmp (opc
->opcode
->name
, "tfr",3) == 0)
2882 /* There must be two operands with a comma. */
2883 input_line_pointer
= skip_whites (input_line_pointer
);
2884 operands
[0].reg1
= register_name ();
2885 if (operands
[0].reg1
== REG_NONE
)
2887 as_bad ("Invalid register\n");
2890 input_line_pointer
= skip_whites (input_line_pointer
);
2891 if (*input_line_pointer
!= ',')
2893 as_bad ("Missing comma.\n");
2896 input_line_pointer
++;
2897 input_line_pointer
= skip_whites (input_line_pointer
);
2898 operands
[1].reg1
= register_name ();
2899 if (operands
[1].reg1
== REG_NONE
)
2901 as_bad ("Invalid register\n");
2904 input_line_pointer
= skip_whites (input_line_pointer
);
2905 if (*input_line_pointer
!= '\n' && *input_line_pointer
)
2907 as_bad (_("Garbage at end of instruction: `%s'."),
2908 input_line_pointer
);
2911 if (operands
[1].reg1
== REG_CCR
) /* ,CCR */
2912 opc
->opcode
->opcode
= 0x00f8 | ( operands
[0].reg1
<< 8);
2913 else if (operands
[0].reg1
== REG_CCR
) /* CCR, */
2914 opc
->opcode
->opcode
= 0x00f9 | ( operands
[1].reg1
<< 8);
2915 else if (operands
[1].reg1
== REG_PC
) /* ,PC */
2916 opc
->opcode
->opcode
= 0x00fa | ( operands
[0].reg1
<< 8);
2919 as_bad ("Invalid operand to TFR\n");
2922 /* no special handling required */
2923 opcode_local
.format
= M68XG_OP_NONE
;
2924 opcode_local
.opcode
= opc
->opcode
->opcode
;
2925 build_insn_xg (&opcode_local
, operands
, 0);
2930 if (opc
->format
& M68XG_OP_IMM3
)
2932 /* Either IMM3 or R */
2933 input_line_pointer
= skip_whites (input_line_pointer
);
2934 if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
2936 operands
[0].reg1
= register_name ();
2937 if (operands
[0].reg1
== REG_NONE
)
2939 as_bad ("Invalid register\n");
2942 operands
[0].mode
= M68XG_OP_R
;
2943 /* One opcode has multiple modes, so find right one. */
2944 opcode
= find (opc
, operands
, 1);
2947 opcode_local
.opcode
= opcode
->opcode
2948 | (operands
[0].reg1
<< 8);
2949 opcode_local
.format
= M68XG_OP_NONE
;
2950 build_insn_xg (&opcode_local
, operands
, 1);
2953 as_bad ("No opcode found\n");
2959 if (*input_line_pointer
== '#')
2960 input_line_pointer
++;
2962 expression (&operands
[0].exp
);
2963 if (operands
[0].exp
.X_op
== O_illegal
)
2965 as_bad (_("Illegal operand."));
2968 else if (operands
[0].exp
.X_op
== O_absent
)
2970 as_bad (_("Missing operand."));
2974 if (check_range (operands
[0].exp
.X_add_number
,M68XG_OP_IMM3
))
2976 opcode_local
.opcode
|= (operands
[0].exp
.X_add_number
);
2977 operands
[0].mode
= M68XG_OP_IMM3
;
2979 opcode
= find (opc
, operands
, 1);
2982 opcode_local
.opcode
= opcode
->opcode
;
2984 |= (operands
[0].exp
.X_add_number
) << 8;
2985 opcode_local
.format
= M68XG_OP_NONE
;
2986 build_insn_xg (&opcode_local
, operands
, 1);
2989 as_bad ("No opcode found\n");
2995 as_bad ("Number out of range for IMM3\n");
3001 /* Special handling of SIF. */
3002 if (strncmp (opc
->opcode
->name
, "sif",3) == 0)
3004 /* Either OP_NONE or OP_RS. */
3005 if (*input_line_pointer
!= '\n')
3006 input_line_pointer
= skip_whites (input_line_pointer
);
3008 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3009 || (*input_line_pointer
== '\0'))
3010 opc
->opcode
->opcode
= 0x0300;
3013 operands
[0].reg1
= register_name ();
3014 if (operands
[0].reg1
== REG_NONE
)
3016 as_bad ("Invalid register\n");
3019 opcode_local
.opcode
= 0x00f7 | (operands
[0].reg1
<< 8);
3021 opcode_local
.format
= M68XG_OP_NONE
;
3022 build_insn_xg (&opcode_local
, operands
, 0);
3026 /* SEX, PAR, JAL plus aliases NEG, TST, COM */
3027 if (opc
->format
& M68XG_OP_R
)
3029 input_line_pointer
= skip_whites (input_line_pointer
);
3030 operands
[0].reg1
= register_name ();
3031 if (operands
[0].reg1
== REG_NONE
)
3033 as_bad ("Invalid register\n");
3036 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3037 || (*input_line_pointer
== '\0'))
3039 /* Likely to be OP R. */
3040 if (opc
->format
& M68XG_OP_R
)
3042 operands
[0].mode
= M68XG_OP_R
;
3044 opcode
= find (opc
, operands
, 1);
3047 if ((strncmp (opc
->opcode
->name
, "com",3) == 0)
3048 || (strncmp (opc
->opcode
->name
, "neg",3) == 0))
3049 /* Special case for com RD as alias for sub RD,R0,RS */
3050 /* Special case for neg RD as alias for sub RD,R0,RS */
3051 opcode_local
.opcode
= opcode
->opcode
3052 | (operands
[0].reg1
<< 8) | (operands
[0].reg1
<< 2);
3053 else if (strncmp (opc
->opcode
->name
, "tst",3) == 0)
3054 /* Special case for tst RS alias for sub R0, RS, R0 */
3055 opcode_local
.opcode
= opcode
->opcode
3056 | (operands
[0].reg1
<< 5);
3058 opcode_local
.opcode
|= (operands
[0].reg1
<< 8);
3060 opcode_local
.format
= M68XG_OP_NONE
;
3061 build_insn_xg (&opcode_local
, operands
, 0);
3064 as_bad ("No valid mode found\n");
3070 if (opc
->format
& (M68XG_OP_REL9
| M68XG_OP_REL10
))
3072 opcode_local
.format
= opc
->format
;
3073 input_line_pointer
= skip_whites (input_line_pointer
);
3074 expression (&operands
[0].exp
);
3075 if (operands
[0].exp
.X_op
== O_illegal
)
3077 as_bad (_("Illegal operand."));
3080 else if (operands
[0].exp
.X_op
== O_absent
)
3082 as_bad (_("Missing operand."));
3085 opcode_local
.opcode
= opc
->opcode
->opcode
;
3086 build_insn_xg (&opcode_local
, operands
, 1);
3091 /* For other command formats, parse input line and determine the mode
3092 we are using as we go. */
3094 input_line_pointer
= skip_whites (input_line_pointer
);
3095 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3096 || (*input_line_pointer
== '\0'))
3097 return; /* nothing left */
3099 if (*input_line_pointer
== '#')
3101 as_bad ("No register specified before hash\n");
3105 /* first operand is expected to be a register */
3106 if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
3108 operands
[0].reg1
= register_name ();
3109 if (operands
[0].reg1
== REG_NONE
)
3111 as_bad ("Invalid register\n");
3116 input_line_pointer
= skip_whites (input_line_pointer
);
3117 if (*input_line_pointer
!= ',')
3119 as_bad ("Missing operand\n");
3122 input_line_pointer
++;
3123 input_line_pointer
= skip_whites (input_line_pointer
);
3125 if (*input_line_pointer
== '#')
3127 /* Some kind of immediate mode, check if this is possible. */
3129 & (M68XG_OP_R_IMM8
| M68XG_OP_R_IMM16
| M68XG_OP_R_IMM4
)))
3130 as_bad ("Invalid immediate mode for `%s'", opc
->opcode
->name
);
3133 input_line_pointer
++;
3134 input_line_pointer
= skip_whites (input_line_pointer
);
3135 if (strncmp (input_line_pointer
, "%hi", 3) == 0)
3137 input_line_pointer
+= 3;
3138 operands
[0].mode
= M6811_OP_HIGH_ADDR
;
3140 else if (strncmp (input_line_pointer
, "%lo", 3) == 0)
3142 input_line_pointer
+= 3;
3143 operands
[0].mode
= M6811_OP_LOW_ADDR
;
3146 operands
[0].mode
= 0;
3148 expression (&operands
[0].exp
);
3149 if (operands
[0].exp
.X_op
== O_illegal
)
3151 as_bad (_("Illegal operand."));
3154 else if (operands
[0].exp
.X_op
== O_absent
)
3156 as_bad (_("Missing operand."));
3159 /* ok so far, can only be one mode */
3160 opcode_local
.format
= opc
->format
3161 & (M68XG_OP_R_IMM8
| M68XG_OP_R_IMM16
| M68XG_OP_R_IMM4
);
3162 if (opcode_local
.format
& M68XG_OP_R_IMM4
)
3164 operands
[0].mode
= M68XG_OP_R_IMM4
;
3165 /* same opcodes have multiple modes, so find right one */
3166 opcode
= find (opc
, operands
, 1);
3168 opcode_local
.opcode
= opcode
->opcode
3169 | (operands
[0].reg1
<< 8);
3171 if (operands
[0].exp
.X_op
!= O_constant
)
3172 as_bad ("Only constants supported at for IMM4 mode\n");
3176 (operands
[0].exp
.X_add_number
,M68XG_OP_R_IMM4
))
3178 |= (operands
[0].exp
.X_add_number
<< 4);
3180 as_bad ("Number out of range for IMM4\n");
3182 opcode_local
.format
= M68XG_OP_NONE
;
3184 else if (opcode_local
.format
& M68XG_OP_R_IMM16
)
3186 operands
[0].mode
= M68XG_OP_R_IMM16
;
3188 opcode
= find (opc
, operands
, 1);
3191 opcode_local
.opcode
= opcode
->opcode
3192 | (operands
[0].reg1
<< 8);
3197 opcode_local
.opcode
= opc
->opcode
->opcode
3198 | (operands
[0].reg1
<< 8);
3200 build_insn_xg (&opcode_local
, operands
, 1);
3203 else if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
3205 /* we've got as far as OP R, R */
3206 operands
[1].reg1
= register_name ();
3207 if (operands
[1].reg1
== REG_NONE
)
3209 as_bad ("Invalid register\n");
3212 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3213 || (*input_line_pointer
== '\0'))
3215 /* looks like OP_R_R */
3216 if (opc
->format
& M68XG_OP_R_R
)
3218 operands
[0].mode
= M68XG_OP_R_R
;
3219 /* same opcodes have multiple modes, so find right one */
3220 opcode
= find (opc
, operands
, 1);
3223 if ((strncmp (opc
->opcode
->name
, "com",3) == 0)
3224 || (strncmp (opc
->opcode
->name
, "mov",3) == 0)
3225 || (strncmp (opc
->opcode
->name
, "neg",3) == 0))
3227 /* Special cases for:
3228 com RD, RS alias for xnor RD,R0,RS
3229 mov RD, RS alias for or RD, R0, RS
3230 neg RD, RS alias for sub RD, R0, RS */
3231 opcode_local
.opcode
= opcode
->opcode
3232 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 2);
3234 else if ((strncmp (opc
->opcode
->name
, "cmp",3) == 0)
3235 || (strncmp (opc
->opcode
->name
, "cpc",3) == 0))
3237 /* special cases for:
3238 cmp RS1, RS2 alias for sub R0, RS1, RS2
3239 cpc RS1, RS2 alias for sbc R0, RS1, RS2 */
3240 opcode_local
.opcode
= opcode
->opcode
3241 | (operands
[0].reg1
<< 5) | (operands
[1].reg1
<< 2);
3245 opcode_local
.opcode
= opcode
->opcode
3246 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 5);
3248 opcode_local
.format
= M68XG_OP_NONE
;
3249 build_insn_xg (&opcode_local
, operands
, 1);
3254 as_bad ("No valid mode found\n");
3260 if (*input_line_pointer
!= ',')
3262 as_bad (_("Missing operand."));
3265 input_line_pointer
++;
3266 input_line_pointer
= skip_whites (input_line_pointer
);
3267 if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
3269 operands
[2].reg1
= register_name ();
3270 if (operands
[2].reg1
== REG_NONE
)
3272 as_bad ("Invalid register\n");
3275 if (opc
->format
& M68XG_OP_R_R_R
)
3277 operands
[0].mode
= M68XG_OP_R_R_R
;
3279 opcode
= find (opc
, operands
, 1);
3282 opcode_local
.opcode
= opcode
->opcode
3283 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 5)
3284 | (operands
[2].reg1
<< 2);
3285 opcode_local
.format
= M68XG_OP_NONE
;
3286 build_insn_xg (&opcode_local
, operands
, 1);
3291 as_bad ("No valid mode found\n");
3296 else if (*input_line_pointer
== '(') /* Indexed modes */
3298 input_line_pointer
++;
3299 input_line_pointer
= skip_whites (input_line_pointer
);
3300 if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
3302 /* we've got as far as OP R, (R */
3303 operands
[1].reg1
= register_name ();
3304 if (operands
[1].reg1
== REG_NONE
)
3306 as_bad ("Invalid register\n");
3310 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3311 || (*input_line_pointer
== '\0'))
3313 /* Looks like OP_R_R. */
3314 as_bad (_("Missing operand."));
3318 input_line_pointer
= skip_whites (input_line_pointer
);
3320 if (*input_line_pointer
!= ',')
3322 as_bad (_("Missing operand."));
3325 input_line_pointer
++;
3326 input_line_pointer
= skip_whites (input_line_pointer
);
3328 if (*input_line_pointer
== '#')
3330 input_line_pointer
++;
3331 input_line_pointer
= skip_whites (input_line_pointer
);
3332 expression (&operands
[0].exp
);
3333 if (operands
[0].exp
.X_op
== O_illegal
)
3335 as_bad (_("Illegal operand."));
3338 else if (operands
[0].exp
.X_op
== O_absent
)
3340 as_bad (_("Missing operand."));
3344 input_line_pointer
= skip_whites (input_line_pointer
);
3345 if (*input_line_pointer
!= ')')
3347 as_bad ("Missing `)' to close register indirect operand.");
3352 input_line_pointer
++;
3355 /* Ok so far, can only be one mode. */
3356 opcode_local
.format
= M68XG_OP_R_R_OFFS5
;
3357 operands
[0].mode
= M68XG_OP_R_R_OFFS5
;
3359 opcode
= find (opc
, operands
, 1);
3362 opcode_local
.opcode
= opcode
->opcode
3363 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 5);
3364 if (operands
[0].exp
.X_op
!= O_constant
)
3367 ("Only constants supported for indexed OFFS5 mode\n");
3371 if (check_range (operands
[0].exp
.X_add_number
,
3372 M68XG_OP_R_R_OFFS5
))
3375 |= (operands
[0].exp
.X_add_number
);
3376 opcode_local
.format
= M68XG_OP_NONE
;
3377 build_insn_xg (&opcode_local
, operands
, 1);
3381 as_bad ("Number out of range for OFFS5\n");
3388 operands
[0].mode
= M68XG_OP_RD_RB_RI
;
3390 if (*input_line_pointer
== '-')
3392 operands
[0].mode
= M68XG_OP_RD_RB_mRI
;
3393 input_line_pointer
++;
3395 operands
[2].reg1
= register_name ();
3396 if (operands
[2].reg1
== REG_NONE
)
3398 as_bad ("Invalid register\n");
3402 if (*input_line_pointer
== '+')
3404 if (opcode_local
.format
== M68XG_OP_RD_RB_mRI
)
3406 as_bad (_("Illegal operand."));
3409 operands
[0].mode
= M68XG_OP_RD_RB_RIp
;
3410 input_line_pointer
++;
3413 input_line_pointer
= skip_whites (input_line_pointer
);
3414 if (*input_line_pointer
!= ')')
3417 ("Missing `)' to close register indirect operand.");
3422 input_line_pointer
++;
3425 opcode
= find (opc
, operands
, 1);
3428 opcode_local
.opcode
= opcode
->opcode
3429 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 5)
3430 | (operands
[2].reg1
<< 2);
3431 opcode_local
.format
= M68XG_OP_NONE
;
3432 build_insn_xg (&opcode_local
, operands
, 1);
3436 as_bad ("Failed to find opcode for %s %s\n",
3437 opc
->opcode
->name
, (char *)op_end
);
3444 as_bad (_("Failed to find a valid mode for `%s'."),
3448 if (opc
->opcode
&& !flag_mri
)
3450 char *p
= input_line_pointer
;
3452 while (*p
== ' ' || *p
== '\t' || *p
== '\n' || *p
== '\r')
3455 if (*p
!= '\n' && *p
)
3456 as_bad (_("Garbage at end of instruction: `%s'."), p
);
3459 input_line_pointer
= save
;
3461 /* Opcode is known but does not have valid operands. Print out the
3462 syntax for this opcode. */
3463 if (opc
->opcode
== 0)
3465 if (flag_print_insn_syntax
)
3466 print_insn_format (name
);
3468 as_bad (_("Invalid operand for `%s'"), name
);
3475 /* Find the opcode definition given its name. */
3476 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, name
);
3478 /* If it's not recognized, look for 'jbsr' and 'jbxx'. These are
3479 pseudo insns for relative branch. For these branches, we always
3480 optimize them (turned into absolute branches) even if --short-branches
3482 if (opc
== NULL
&& name
[0] == 'j' && name
[1] == 'b')
3484 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, &name
[1]);
3486 && (!(opc
->format
& M6811_OP_JUMP_REL
)
3487 || (opc
->format
& M6811_OP_BITMASK
)))
3490 branch_optimize
= 1;
3493 /* The following test should probably be removed. This does not conform
3494 to Motorola assembler specs. */
3495 if (opc
== NULL
&& flag_mri
)
3497 if (*op_end
== ' ' || *op_end
== '\t')
3499 while (*op_end
== ' ' || *op_end
== '\t')
3504 (is_end_of_line
[op_end
[1]]
3505 || op_end
[1] == ' ' || op_end
[1] == '\t'
3506 || !ISALNUM (op_end
[1])))
3507 && (*op_end
== 'a' || *op_end
== 'b'
3508 || *op_end
== 'A' || *op_end
== 'B'
3509 || *op_end
== 'd' || *op_end
== 'D'
3510 || *op_end
== 'x' || *op_end
== 'X'
3511 || *op_end
== 'y' || *op_end
== 'Y'))
3513 name
[nlen
++] = TOLOWER (*op_end
++);
3515 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
,
3521 /* Identify a possible instruction alias. There are some on the
3522 68HC12 to emulate a few 68HC11 instructions. */
3523 if (opc
== NULL
&& (current_architecture
& cpu6812
))
3527 for (i
= 0; i
< m68hc12_num_alias
; i
++)
3528 if (strcmp (m68hc12_alias
[i
].name
, name
) == 0)
3534 if (opc
== NULL
&& alias_id
< 0)
3536 as_bad (_("Opcode `%s' is not recognized."), name
);
3539 save
= input_line_pointer
;
3540 input_line_pointer
= (char *) op_end
;
3545 opcode
= find_opcode (opc
, operands
, &nb_operands
);
3550 if ((opcode
|| alias_id
>= 0) && !flag_mri
)
3552 char *p
= input_line_pointer
;
3554 while (*p
== ' ' || *p
== '\t' || *p
== '\n' || *p
== '\r')
3557 if (*p
!= '\n' && *p
)
3558 as_bad (_("Garbage at end of instruction: `%s'."), p
);
3561 input_line_pointer
= save
;
3565 char *f
= m68hc11_new_insn (m68hc12_alias
[alias_id
].size
);
3567 number_to_chars_bigendian (f
, m68hc12_alias
[alias_id
].code1
, 1);
3568 if (m68hc12_alias
[alias_id
].size
> 1)
3569 number_to_chars_bigendian (f
+ 1, m68hc12_alias
[alias_id
].code2
, 1);
3574 /* Opcode is known but does not have valid operands. Print out the
3575 syntax for this opcode. */
3578 if (flag_print_insn_syntax
)
3579 print_insn_format (name
);
3581 if (((strcmp (name
, "movb") == 0) || (strcmp (name
, "movw") == 0))
3582 && (current_architecture
& cpu9s12x
))
3586 if (strcmp (name
, "movb") == 0)
3591 /* The existing operand extract code fell over if these additional modes
3592 were enabled in m68hc11-opc.c. So they are commented there and
3593 decoded here instead. */
3595 if (operands
[1].mode
& (M6812_OP_IDX
| M6812_OP_IDX_1
3596 | M6812_OP_IDX_2
| M6812_OP_D_IDX
| M6812_OP_D_IDX_2
| M6812_PRE_INC
3597 | M6812_PRE_DEC
| M6812_POST_INC
| M6812_POST_DEC
))
3599 /* first check if valid mode then start building it up */
3600 if (operands
[0].mode
& (M6811_OP_IMM8
| M6811_OP_IMM16
3601 | M6811_OP_IND16
| M6812_OP_IDX
| M6812_OP_IDX_1
3602 | M6812_OP_IDX_2
| M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
3605 if (operands
[1].mode
& (M6811_OP_IND16
))
3610 f
= m68hc11_new_insn (2);
3612 if (operands
[0].mode
& (M6811_OP_IMM8
| M6811_OP_IMM16
))
3614 number_to_chars_bigendian (f
, 0x1800 + movb
+ opr16a
, 2);
3615 build_indexed_byte (&operands
[1], operands
[1].mode
, 1);
3617 fixup8 (&operands
[0].exp
, M6811_OP_IMM8
,
3620 fixup16 (&operands
[0].exp
, M6811_OP_IMM16
,
3625 else if (operands
[0].mode
& M6811_OP_IND16
)
3627 number_to_chars_bigendian (f
, 0x1801 + movb
+ opr16a
, 2);
3628 build_indexed_byte (&operands
[1], operands
[1].mode
, 1);
3629 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, operands
[0].mode
);
3634 number_to_chars_bigendian (f
, 0x1802 + movb
+ opr16a
, 2);
3635 build_indexed_byte (&operands
[0], operands
[0].mode
, 1);
3636 build_indexed_byte (&operands
[1], operands
[1].mode
, 1);
3641 else if (operands
[1].mode
& M6811_OP_IND16
)
3643 /* First check if this is valid mode, then start building it up. */
3644 if (operands
[0].mode
& (M6811_OP_IMM8
| M6811_OP_IMM16
3645 | M6811_OP_IND16
| M6812_OP_IDX
| M6812_OP_IDX_1
3646 | M6812_OP_IDX_2
| M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
3649 if (operands
[1].mode
& (M6811_OP_IND16
))
3654 f
= m68hc11_new_insn (2);
3656 /* The first two cases here should actually be covered by the
3657 normal operand code. */
3658 if (operands
[0].mode
& (M6811_OP_IMM8
| M6811_OP_IMM16
))
3660 number_to_chars_bigendian (f
, 0x1800 + movb
+ opr16a
, 2);
3662 fixup8 (&operands
[0].exp
, M6811_OP_IMM8
, operands
[0].mode
);
3664 fixup16 (&operands
[0].exp
, M6811_OP_IMM16
, operands
[0].mode
);
3666 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, operands
[0].mode
);
3669 else if (operands
[0].mode
& M6811_OP_IND16
)
3671 number_to_chars_bigendian (f
, 0x1801 + movb
+ opr16a
, 2);
3672 build_indexed_byte (&operands
[1], operands
[1].mode
, 1);
3673 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, operands
[0].mode
);
3678 number_to_chars_bigendian (f
, 0x1802 + movb
+ opr16a
, 2);
3679 build_indexed_byte (&operands
[0], operands
[0].mode
, 1);
3680 fixup16 (&operands
[1].exp
, M6811_OP_IND16
, operands
[1].mode
);
3686 as_bad (_("Invalid operand for `%s'"), name
);
3692 as_bad (_("Invalid operand for `%s'"), name
);
3697 /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is
3698 relative and must be in the range -256..255 (9-bits). */
3699 if ((opcode
->format
& M6812_XBCC_MARKER
)
3700 && (opcode
->format
& M6811_OP_JUMP_REL
))
3701 build_dbranch_insn (opcode
, operands
, nb_operands
, branch_optimize
);
3703 /* Relative jumps instructions are taken care of separately. We have to make
3704 sure that the relative branch is within the range -128..127. If it's out
3705 of range, the instructions are changed into absolute instructions.
3706 This is not supported for the brset and brclr instructions. */
3707 else if ((opcode
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
3708 && !(opcode
->format
& M6811_OP_BITMASK
))
3709 build_jump_insn (opcode
, operands
, nb_operands
, branch_optimize
);
3711 build_insn (opcode
, operands
, nb_operands
);
3715 /* Pseudo op to control the ELF flags. */
3717 s_m68hc11_mode (int x ATTRIBUTE_UNUSED
)
3719 char *name
= input_line_pointer
, ch
;
3721 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3722 input_line_pointer
++;
3723 ch
= *input_line_pointer
;
3724 *input_line_pointer
= '\0';
3726 if (strcmp (name
, "mshort") == 0)
3728 elf_flags
&= ~E_M68HC11_I32
;
3730 else if (strcmp (name
, "mlong") == 0)
3732 elf_flags
|= E_M68HC11_I32
;
3734 else if (strcmp (name
, "mshort-double") == 0)
3736 elf_flags
&= ~E_M68HC11_F64
;
3738 else if (strcmp (name
, "mlong-double") == 0)
3740 elf_flags
|= E_M68HC11_F64
;
3744 as_warn (_("Invalid mode: %s\n"), name
);
3746 *input_line_pointer
= ch
;
3747 demand_empty_rest_of_line ();
3750 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions
3751 are using 'rtc' for returning. It is necessary to use 'call'
3752 to invoke them. This is also used by the debugger to correctly
3753 find the stack frame. */
3755 s_m68hc11_mark_symbol (int mark
)
3761 elf_symbol_type
*elfsym
;
3765 name
= input_line_pointer
;
3766 c
= get_symbol_end ();
3767 symbolP
= symbol_find_or_make (name
);
3768 *input_line_pointer
= c
;
3772 bfdsym
= symbol_get_bfdsym (symbolP
);
3773 elfsym
= elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
3775 gas_assert (elfsym
);
3777 /* Mark the symbol far (using rtc for function return). */
3778 elfsym
->internal_elf_sym
.st_other
|= mark
;
3782 input_line_pointer
++;
3786 if (*input_line_pointer
== '\n')
3792 demand_empty_rest_of_line ();
3796 s_m68hc11_relax (int ignore ATTRIBUTE_UNUSED
)
3802 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
3804 as_bad (_("bad .relax format"));
3805 ignore_rest_of_line ();
3809 fix_new_exp (frag_now
, frag_now_fix (), 0, &ex
, 1,
3810 BFD_RELOC_M68HC11_RL_GROUP
);
3812 demand_empty_rest_of_line ();
3816 /* Relocation, relaxation and frag conversions. */
3818 /* PC-relative offsets are relative to the start of the
3819 next instruction. That is, the address of the offset, plus its
3820 size, since the offset is always the last part of the insn. */
3822 md_pcrel_from (fixS
*fixP
)
3824 if (fixP
->fx_r_type
== BFD_RELOC_M68HC11_RL_JUMP
)
3827 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3830 /* If while processing a fixup, a reloc really needs to be created
3831 then it is done here. */
3833 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3837 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3838 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3839 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3840 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3841 if (fixp
->fx_r_type
== 0)
3842 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
3844 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3845 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
3847 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3848 _("Relocation %d is not supported by object file format."),
3849 (int) fixp
->fx_r_type
);
3853 /* Since we use Rel instead of Rela, encode the vtable entry to be
3854 used in the relocation's section offset. */
3855 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3856 reloc
->address
= fixp
->fx_offset
;
3862 /* We need a port-specific relaxation function to cope with sym2 - sym1
3863 relative expressions with both symbols in the same segment (but not
3864 necessarily in the same frag as this insn), for example:
3865 ldab sym2-(sym1-2),pc
3867 The offset can be 5, 9 or 16 bits long. */
3870 m68hc11_relax_frag (segT seg ATTRIBUTE_UNUSED
, fragS
*fragP
,
3871 long stretch ATTRIBUTE_UNUSED
)
3876 const relax_typeS
*this_type
;
3877 const relax_typeS
*start_type
;
3878 relax_substateT next_state
;
3879 relax_substateT this_state
;
3880 const relax_typeS
*table
= TC_GENERIC_RELAX_TABLE
;
3882 /* We only have to cope with frags as prepared by
3883 md_estimate_size_before_relax. The STATE_BITS16 case may geet here
3884 because of the different reasons that it's not relaxable. */
3885 switch (fragP
->fr_subtype
)
3887 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
):
3888 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
):
3889 /* When we get to this state, the frag won't grow any more. */
3892 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS5
):
3893 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS5
):
3894 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
):
3895 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
):
3896 if (fragP
->fr_symbol
== NULL
3897 || S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3898 as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"),
3899 __FUNCTION__
, (long) fragP
->fr_symbol
);
3900 symbolP
= fragP
->fr_symbol
;
3901 if (symbol_resolved_p (symbolP
))
3902 as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
3904 aim
= S_GET_VALUE (symbolP
);
3908 as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"),
3909 __FUNCTION__
, fragP
->fr_subtype
);
3912 /* The rest is stolen from relax_frag. There's no obvious way to
3913 share the code, but fortunately no requirement to keep in sync as
3914 long as fragP->fr_symbol does not have its segment changed. */
3916 this_state
= fragP
->fr_subtype
;
3917 start_type
= this_type
= table
+ this_state
;
3921 /* Look backwards. */
3922 for (next_state
= this_type
->rlx_more
; next_state
;)
3923 if (aim
>= this_type
->rlx_backward
)
3927 /* Grow to next state. */
3928 this_state
= next_state
;
3929 this_type
= table
+ this_state
;
3930 next_state
= this_type
->rlx_more
;
3935 /* Look forwards. */
3936 for (next_state
= this_type
->rlx_more
; next_state
;)
3937 if (aim
<= this_type
->rlx_forward
)
3941 /* Grow to next state. */
3942 this_state
= next_state
;
3943 this_type
= table
+ this_state
;
3944 next_state
= this_type
->rlx_more
;
3948 growth
= this_type
->rlx_length
- start_type
->rlx_length
;
3950 fragP
->fr_subtype
= this_state
;
3955 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec ATTRIBUTE_UNUSED
,
3960 char *buffer_address
= fragP
->fr_literal
;
3962 /* Address in object code of the displacement. */
3963 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
3965 buffer_address
+= fragP
->fr_fix
;
3967 /* The displacement of the address, from current location. */
3968 value
= S_GET_VALUE (fragP
->fr_symbol
);
3969 disp
= (value
+ fragP
->fr_offset
) - object_address
;
3971 switch (fragP
->fr_subtype
)
3973 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_BYTE
):
3974 fragP
->fr_opcode
[1] = disp
;
3977 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_WORD
):
3978 /* This relax is only for bsr and bra. */
3979 gas_assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
3980 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
3981 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
3983 fragP
->fr_opcode
[0] = convert_branch (fragP
->fr_opcode
[0]);
3985 fix_new (fragP
, fragP
->fr_fix
- 1, 2,
3986 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
3990 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_BYTE
):
3991 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_BYTE
):
3992 fragP
->fr_opcode
[1] = disp
;
3995 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_WORD
):
3996 /* Invert branch. */
3997 fragP
->fr_opcode
[0] ^= 1;
3998 fragP
->fr_opcode
[1] = 3; /* Branch offset. */
3999 buffer_address
[0] = M6811_JMP
;
4000 fix_new (fragP
, fragP
->fr_fix
+ 1, 2,
4001 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
4005 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_WORD
):
4006 /* Translate branch into a long branch. */
4007 fragP
->fr_opcode
[1] = fragP
->fr_opcode
[0];
4008 fragP
->fr_opcode
[0] = M6811_OPCODE_PAGE2
;
4010 fix_new (fragP
, fragP
->fr_fix
, 2,
4011 fragP
->fr_symbol
, fragP
->fr_offset
, 1,
4012 BFD_RELOC_16_PCREL
);
4016 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS5
):
4017 if (fragP
->fr_symbol
!= 0
4018 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
4022 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS5
):
4023 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 6;
4024 fragP
->fr_opcode
[0] |= value
& 0x1f;
4027 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
):
4028 /* For a PC-relative offset, use the displacement with a -1 correction
4029 to take into account the additional byte of the insn. */
4030 if (fragP
->fr_symbol
!= 0
4031 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
4035 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
):
4036 fragP
->fr_opcode
[0] = (fragP
->fr_opcode
[0] << 3);
4037 fragP
->fr_opcode
[0] |= 0xE0;
4038 fragP
->fr_opcode
[0] |= (value
>> 8) & 1;
4039 fragP
->fr_opcode
[1] = value
;
4043 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
):
4044 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
):
4045 fragP
->fr_opcode
[0] = (fragP
->fr_opcode
[0] << 3);
4046 fragP
->fr_opcode
[0] |= 0xe2;
4047 if ((fragP
->fr_opcode
[0] & 0x0ff) == 0x0fa
4048 && fragP
->fr_symbol
!= 0
4049 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
4051 fix_new (fragP
, fragP
->fr_fix
, 2,
4052 fragP
->fr_symbol
, fragP
->fr_offset
,
4053 1, BFD_RELOC_16_PCREL
);
4057 fix_new (fragP
, fragP
->fr_fix
, 2,
4058 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
4063 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_BYTE
):
4065 fragP
->fr_opcode
[0] |= 0x10;
4067 fragP
->fr_opcode
[1] = disp
& 0x0FF;
4070 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_WORD
):
4071 /* Invert branch. */
4072 fragP
->fr_opcode
[0] ^= 0x20;
4073 fragP
->fr_opcode
[1] = 3; /* Branch offset. */
4074 buffer_address
[0] = M6812_JMP
;
4075 fix_new (fragP
, fragP
->fr_fix
+ 1, 2,
4076 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
4085 /* On an ELF system, we can't relax a weak symbol. The weak symbol
4086 can be overridden at final link time by a non weak symbol. We can
4087 relax externally visible symbol because there is no shared library
4088 and such symbol can't be overridden (unless they are weak). */
4090 relaxable_symbol (symbolS
*symbol
)
4092 return ! S_IS_WEAK (symbol
);
4095 /* Force truly undefined symbols to their maximum size, and generally set up
4096 the frag list to be relaxed. */
4098 md_estimate_size_before_relax (fragS
*fragP
, asection
*segment
)
4100 if (RELAX_LENGTH (fragP
->fr_subtype
) == STATE_UNDF
)
4102 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4103 || !relaxable_symbol (fragP
->fr_symbol
)
4104 || (segment
!= absolute_section
4105 && RELAX_STATE (fragP
->fr_subtype
) == STATE_INDEXED_OFFSET
))
4107 /* Non-relaxable cases. */
4109 char *buffer_address
;
4111 old_fr_fix
= fragP
->fr_fix
;
4112 buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
4114 switch (RELAX_STATE (fragP
->fr_subtype
))
4116 case STATE_PC_RELATIVE
:
4118 /* This relax is only for bsr and bra. */
4119 gas_assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
4120 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
4121 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
4123 if (flag_fixed_branches
)
4124 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4125 _("bra or bsr with undefined symbol."));
4127 /* The symbol is undefined or in a separate section.
4128 Turn bra into a jmp and bsr into a jsr. The insn
4129 becomes 3 bytes long (instead of 2). A fixup is
4130 necessary for the unresolved symbol address. */
4131 fragP
->fr_opcode
[0] = convert_branch (fragP
->fr_opcode
[0]);
4133 fix_new (fragP
, fragP
->fr_fix
- 1, 2, fragP
->fr_symbol
,
4134 fragP
->fr_offset
, 0, BFD_RELOC_16
);
4138 case STATE_CONDITIONAL_BRANCH
:
4139 gas_assert (current_architecture
& cpu6811
);
4141 fragP
->fr_opcode
[0] ^= 1; /* Reverse sense of branch. */
4142 fragP
->fr_opcode
[1] = 3; /* Skip next jmp insn (3 bytes). */
4144 /* Don't use fr_opcode[2] because this may be
4145 in a different frag. */
4146 buffer_address
[0] = M6811_JMP
;
4149 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4150 fragP
->fr_offset
, 0, BFD_RELOC_16
);
4154 case STATE_INDEXED_OFFSET
:
4155 gas_assert (current_architecture
& cpu6812
);
4157 if (fragP
->fr_symbol
4158 && S_GET_SEGMENT (fragP
->fr_symbol
) == absolute_section
)
4160 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_OFFSET
,
4162 /* Return the size of the variable part of the frag. */
4163 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4167 /* Switch the indexed operation to 16-bit mode. */
4168 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 3;
4169 fragP
->fr_opcode
[0] |= 0xe2;
4170 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4171 fragP
->fr_offset
, 0, BFD_RELOC_16
);
4176 case STATE_INDEXED_PCREL
:
4177 gas_assert (current_architecture
& cpu6812
);
4179 if (fragP
->fr_symbol
4180 && S_GET_SEGMENT (fragP
->fr_symbol
) == absolute_section
)
4182 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_PCREL
,
4184 /* Return the size of the variable part of the frag. */
4185 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4189 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 3;
4190 fragP
->fr_opcode
[0] |= 0xe2;
4191 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4192 fragP
->fr_offset
, 1, BFD_RELOC_16_PCREL
);
4197 case STATE_XBCC_BRANCH
:
4198 gas_assert (current_architecture
& cpu6812
);
4200 fragP
->fr_opcode
[0] ^= 0x20; /* Reverse sense of branch. */
4201 fragP
->fr_opcode
[1] = 3; /* Skip next jmp insn (3 bytes). */
4203 /* Don't use fr_opcode[2] because this may be
4204 in a different frag. */
4205 buffer_address
[0] = M6812_JMP
;
4208 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4209 fragP
->fr_offset
, 0, BFD_RELOC_16
);
4213 case STATE_CONDITIONAL_BRANCH_6812
:
4214 gas_assert (current_architecture
& cpu6812
);
4216 /* Translate into a lbcc branch. */
4217 fragP
->fr_opcode
[1] = fragP
->fr_opcode
[0];
4218 fragP
->fr_opcode
[0] = M6811_OPCODE_PAGE2
;
4220 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4221 fragP
->fr_offset
, 1, BFD_RELOC_16_PCREL
);
4226 as_fatal (_("Subtype %d is not recognized."), fragP
->fr_subtype
);
4230 /* Return the growth in the fixed part of the frag. */
4231 return fragP
->fr_fix
- old_fr_fix
;
4234 /* Relaxable cases. */
4235 switch (RELAX_STATE (fragP
->fr_subtype
))
4237 case STATE_PC_RELATIVE
:
4238 /* This relax is only for bsr and bra. */
4239 gas_assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
4240 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
4241 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
4243 fragP
->fr_subtype
= ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_BYTE
);
4246 case STATE_CONDITIONAL_BRANCH
:
4247 gas_assert (current_architecture
& cpu6811
);
4249 fragP
->fr_subtype
= ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
,
4253 case STATE_INDEXED_OFFSET
:
4254 gas_assert (current_architecture
& cpu6812
);
4256 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_OFFSET
,
4260 case STATE_INDEXED_PCREL
:
4261 gas_assert (current_architecture
& cpu6812
);
4263 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_PCREL
,
4267 case STATE_XBCC_BRANCH
:
4268 gas_assert (current_architecture
& cpu6812
);
4270 fragP
->fr_subtype
= ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_BYTE
);
4273 case STATE_CONDITIONAL_BRANCH_6812
:
4274 gas_assert (current_architecture
& cpu6812
);
4276 fragP
->fr_subtype
= ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
,
4282 if (fragP
->fr_subtype
>= sizeof (md_relax_table
) / sizeof (md_relax_table
[0]))
4283 as_fatal (_("Subtype %d is not recognized."), fragP
->fr_subtype
);
4285 /* Return the size of the variable part of the frag. */
4286 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4289 /* See whether we need to force a relocation into the output file. */
4291 tc_m68hc11_force_relocation (fixS
*fixP
)
4293 if (fixP
->fx_r_type
== BFD_RELOC_M68HC11_RL_GROUP
)
4296 return generic_force_reloc (fixP
);
4299 /* Here we decide which fixups can be adjusted to make them relative
4300 to the beginning of the section instead of the symbol. Basically
4301 we need to make sure that the linker relaxation is done
4302 correctly, so in some cases we force the original symbol to be
4305 tc_m68hc11_fix_adjustable (fixS
*fixP
)
4307 switch (fixP
->fx_r_type
)
4309 /* For the linker relaxation to work correctly, these relocs
4310 need to be on the symbol itself. */
4312 case BFD_RELOC_M68HC11_RL_JUMP
:
4313 case BFD_RELOC_M68HC11_RL_GROUP
:
4314 case BFD_RELOC_VTABLE_INHERIT
:
4315 case BFD_RELOC_VTABLE_ENTRY
:
4318 /* The memory bank addressing translation also needs the original
4320 case BFD_RELOC_M68HC11_LO16
:
4321 case BFD_RELOC_M68HC11_PAGE
:
4322 case BFD_RELOC_M68HC11_24
:
4331 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4334 long value
= * valP
;
4336 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
4339 /* We don't actually support subtracting a symbol. */
4340 if (fixP
->fx_subsy
!= (symbolS
*) NULL
)
4341 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("Expression too complex."));
4343 /* Patch the instruction with the resolved operand. Elf relocation
4344 info will also be generated to take care of linker/loader fixups.
4345 The 68HC11 addresses only 64Kb, we are only concerned by 8 and 16-bit
4346 relocs. BFD_RELOC_8 is basically used for .page0 access (the linker
4347 will warn for overflows). BFD_RELOC_8_PCREL should not be generated
4348 because it's either resolved or turned out into non-relative insns (see
4349 relax table, bcc, bra, bsr transformations)
4351 The BFD_RELOC_32 is necessary for the support of --gstabs. */
4352 where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4354 switch (fixP
->fx_r_type
)
4357 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
4361 case BFD_RELOC_M68HC11_24
:
4362 bfd_putb16 ((bfd_vma
) (value
& 0x0ffff), (unsigned char *) where
);
4363 ((bfd_byte
*) where
)[2] = ((value
>> 16) & 0x0ff);
4367 case BFD_RELOC_16_PCREL
:
4368 case BFD_RELOC_M68HC11_LO16
:
4369 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
4370 if (value
< -65537 || value
> 65535)
4371 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4372 _("Value out of 16-bit range."));
4375 case BFD_RELOC_M68HC11_HI8
:
4376 /* Caution, %hi(<symbol>+%ld) will generate incorrect code if %lo
4378 case BFD_RELOC_M68HC12_HI8XG
:
4382 case BFD_RELOC_M68HC12_LO8XG
:
4383 case BFD_RELOC_M68HC11_LO8
:
4385 case BFD_RELOC_M68HC11_PAGE
:
4386 ((bfd_byte
*) where
)[0] = (bfd_byte
) value
;
4389 case BFD_RELOC_8_PCREL
:
4390 ((bfd_byte
*) where
)[0] = (bfd_byte
) value
;
4392 if (value
< -128 || value
> 127)
4393 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4394 _("Value %ld too large for 8-bit PC-relative branch."),
4398 /* These next two are for XGATE. */
4399 case BFD_RELOC_M68HC12_9_PCREL
:
4400 ((bfd_byte
*) where
)[0] |= (bfd_byte
) ((value
>>9) & 0x01);
4401 ((bfd_byte
*) where
)[1] = (bfd_byte
) ((value
>>1) & 0xff);
4402 if (value
< -512 || value
> 511)
4403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4404 _("Value %ld too large for 9-bit PC-relative branch."),
4408 case BFD_RELOC_M68HC12_10_PCREL
:
4409 ((bfd_byte
*) where
)[0] |= (bfd_byte
) ((value
>>9) & 0x03);
4410 ((bfd_byte
*) where
)[1] = (bfd_byte
) ((value
>>1) & 0xff);
4411 if (value
< -1024 || value
> 1023)
4412 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4413 _("Value %ld too large for 10-bit PC-relative branch."),
4418 case BFD_RELOC_M68HC11_3B
:
4419 if (value
<= 0 || value
> 8)
4420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4421 _("Auto increment/decrement offset '%ld' is out of range."),
4428 where
[0] = where
[0] | (value
& 0x07);
4431 case BFD_RELOC_M68HC12_5B
:
4432 if (value
< -16 || value
> 15)
4433 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4434 _("Offset out of 5-bit range for movw/movb insn: %ld"),
4439 where
[0] |= (0x10 | (16 + value
));
4442 case BFD_RELOC_M68HC12_9B
:
4443 if (value
< -256 || value
> 255)
4444 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4445 _("Offset out of 9-bit range for movw/movb insn: %ld"),
4447 /* sign bit already in xb postbyte */
4451 where
[1] = (256 + value
);
4454 case BFD_RELOC_M68HC12_16B
:
4455 if (value
< -32768 || value
> 32767)
4456 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4457 _("Offset out of 16-bit range for movw/movb insn: %ld"),
4462 where
[0] = (value
>> 8);
4463 where
[1] = (value
& 0xff);
4466 case BFD_RELOC_M68HC11_RL_JUMP
:
4467 case BFD_RELOC_M68HC11_RL_GROUP
:
4468 case BFD_RELOC_VTABLE_INHERIT
:
4469 case BFD_RELOC_VTABLE_ENTRY
:
4474 as_fatal (_("Line %d: unknown relocation type: 0x%x."),
4475 fixP
->fx_line
, fixP
->fx_r_type
);
4479 /* Set the ELF specific flags. */
4481 m68hc11_elf_final_processing (void)
4483 if (current_architecture
& cpu6812s
)
4484 elf_flags
|= EF_M68HCS12_MACH
;
4485 elf_elfheader (stdoutput
)->e_flags
&= ~EF_M68HC11_ABI
;
4486 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
4489 /* Process directives specified via pseudo ops */
4491 s_m68hc11_parse_pseudo_instruction (int pseudo_insn
)
4493 switch (pseudo_insn
)
4495 case E_M68HC11_NO_BANK_WARNING
:
4496 elf_flags
|= E_M68HC11_NO_BANK_WARNING
;
4499 as_bad (_("Invalid directive"));