1 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12.
2 Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010,
4 Free Software Foundation, Inc.
5 Written by Stephane Carrez (stcarrez@nerim.fr)
6 XGATE and S12X added by James Murray (jsm@jsm-net.demon.co.uk)
8 This file is part of GAS, the GNU Assembler.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
23 Boston, MA 02110-1301, USA. */
26 #include "safe-ctype.h"
28 #include "opcode/m68hc11.h"
29 #include "dwarf2dbg.h"
30 #include "elf/m68hc11.h"
32 const char comment_chars
[] = ";!";
33 const char line_comment_chars
[] = "#*";
34 const char line_separator_chars
[] = "";
36 const char EXP_CHARS
[] = "eE";
37 const char FLT_CHARS
[] = "dD";
39 #define STATE_CONDITIONAL_BRANCH (1)
40 #define STATE_PC_RELATIVE (2)
41 #define STATE_INDEXED_OFFSET (3)
42 #define STATE_INDEXED_PCREL (4)
43 #define STATE_XBCC_BRANCH (5)
44 #define STATE_CONDITIONAL_BRANCH_6812 (6)
46 #define STATE_BYTE (0)
47 #define STATE_BITS5 (0)
48 #define STATE_WORD (1)
49 #define STATE_BITS9 (1)
50 #define STATE_LONG (2)
51 #define STATE_BITS16 (2)
52 #define STATE_UNDF (3) /* Symbol undefined in pass1 */
54 /* This macro has no side-effects. */
55 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
56 #define RELAX_STATE(s) ((s) >> 2)
57 #define RELAX_LENGTH(s) ((s) & 3)
59 #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF))
61 /* This table describes how you change sizes for the various types of variable
62 size expressions. This version only supports two kinds. */
65 How far Forward this mode will reach.
66 How far Backward this mode will reach.
67 How many bytes this mode will add to the size of the frag.
68 Which mode to go to if the offset won't fit in this one. */
70 relax_typeS md_relax_table
[] =
72 {1, 1, 0, 0}, /* First entries aren't used. */
73 {1, 1, 0, 0}, /* For no good reason except. */
74 {1, 1, 0, 0}, /* that the VAX doesn't either. */
78 These insns are translated into b!cc +3 jmp L. */
79 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_WORD
)},
84 /* Relax for bsr <L> and bra <L>.
85 These insns are translated into jsr and jmp. */
86 {(127), (-128), 0, ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_WORD
)},
91 /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */
92 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
)},
93 {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
)},
97 /* Relax for PC relative offset: 5-bits, 9-bits, 16-bits.
98 For the 9-bit case, there will be a -1 correction to take into
99 account the new byte that's why the range is -255..256. */
100 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
)},
101 {(256), (-255), 1, ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
)},
105 /* Relax for dbeq/ibeq/tbeq r,<L>:
106 These insns are translated into db!cc +3 jmp L. */
107 {(255), (-256), 0, ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_WORD
)},
112 /* Relax for bcc <L> on 68HC12.
113 These insns are translated into lbcc <L>. */
114 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_WORD
)},
121 /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */
122 typedef enum register_id
146 typedef struct operand
154 struct m68hc11_opcode_def
161 struct m68hc11_opcode
*opcode
;
164 static struct m68hc11_opcode_def
*m68hc11_opcode_defs
= 0;
165 static int m68hc11_nb_opcode_defs
= 0;
173 static alias alias_opcodes
[] =
181 struct m9s12xg_opcode_def
188 struct m9s12xg_opcode
*opcode
;
191 /* Local functions. */
192 static register_id
reg_name_search (char *);
193 static register_id
register_name (void);
194 static int cmp_opcode (struct m68hc11_opcode
*, struct m68hc11_opcode
*);
195 static char *print_opcode_format (struct m68hc11_opcode
*, int);
196 static char *skip_whites (char *);
197 static int check_range (long, int);
198 static void print_opcode_list (void);
199 static void get_default_target (void);
200 static void print_insn_format (char *);
201 static int get_operand (operand
*, int, long);
202 static void fixup8 (expressionS
*, int, int);
203 static void fixup16 (expressionS
*, int, int);
204 static void fixup24 (expressionS
*, int, int);
205 static void fixup8_xg (expressionS
*, int, int);
206 static unsigned char convert_branch (unsigned char);
207 static char *m68hc11_new_insn (int);
208 static void build_dbranch_insn (struct m68hc11_opcode
*,
209 operand
*, int, int);
210 static int build_indexed_byte (operand
*, int, int);
211 static int build_reg_mode (operand
*, int);
213 static struct m68hc11_opcode
*find (struct m68hc11_opcode_def
*,
215 static struct m68hc11_opcode
*find_opcode (struct m68hc11_opcode_def
*,
217 static void build_jump_insn (struct m68hc11_opcode
*, operand
*, int, int);
218 static void build_insn_xg (struct m68hc11_opcode
*, operand
*, int);
219 static void build_insn (struct m68hc11_opcode
*, operand
*, int);
220 static int relaxable_symbol (symbolS
*);
222 /* Pseudo op to indicate a relax group. */
223 static void s_m68hc11_relax (int);
225 /* Pseudo op to control the ELF flags. */
226 static void s_m68hc11_mode (int);
228 /* Process directives specified via pseudo ops. */
229 static void s_m68hc11_parse_pseudo_instruction (int);
231 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions
232 are using 'rtc' for returning. It is necessary to use 'call'
233 to invoke them. This is also used by the debugger to correctly
234 find the stack frame. */
235 static void s_m68hc11_mark_symbol (int);
237 /* Controls whether relative branches can be turned into long branches.
238 When the relative offset is too large, the insn are changed:
246 Setting the flag forbidds this. */
247 static short flag_fixed_branches
= 0;
249 /* Force to use long jumps (absolute) instead of relative branches. */
250 static short flag_force_long_jumps
= 0;
252 /* Change the direct addressing mode into an absolute addressing mode
253 when the insn does not support direct addressing.
254 For example, "clr *ZD0" is normally not possible and is changed
256 static short flag_strict_direct_addressing
= 1;
258 /* When an opcode has invalid operand, print out the syntax of the opcode
260 static short flag_print_insn_syntax
= 0;
262 /* Dumps the list of instructions with syntax and then exit:
263 1 -> Only dumps the list (sorted by name)
264 2 -> Generate an example (or test) that can be compiled. */
265 static short flag_print_opcodes
= 0;
267 /* Opcode hash table. */
268 static struct hash_control
*m68hc11_hash
;
270 /* Current cpu (either cpu6811 or cpu6812). This is determined automagically
271 by 'get_default_target' by looking at default BFD vector. This is overridden
272 with the -m<cpu> option. */
273 static int current_architecture
= 0;
275 /* Default cpu determined by 'get_default_target'. */
276 static const char *default_cpu
;
278 /* Number of opcodes in the sorted table (filtered by current cpu). */
279 static int num_opcodes
;
281 /* The opcodes sorted by name and filtered by current cpu. */
282 static struct m68hc11_opcode
*m68hc11_sorted_opcodes
;
284 /* ELF flags to set in the output file header. */
285 static int elf_flags
= E_M68HC11_F64
;
287 /* These are the machine dependent pseudo-ops. These are included so
288 the assembler can work on the output from the SUN C compiler, which
291 /* This table describes all the machine specific pseudo-ops the assembler
292 has to support. The fields are:
293 pseudo-op name without dot
294 function to call to execute this pseudo-op
295 Integer arg to pass to the function. */
296 const pseudo_typeS md_pseudo_table
[] =
298 /* The following pseudo-ops are supported for MRI compatibility. */
302 {"fcc", stringer
, 8 + 1},
306 {"xrefb", s_ignore
, 0}, /* Same as xref */
308 /* Gcc driven relaxation. */
309 {"relax", s_m68hc11_relax
, 0},
311 /* .mode instruction (ala SH). */
312 {"mode", s_m68hc11_mode
, 0},
314 /* .far instruction. */
315 {"far", s_m68hc11_mark_symbol
, STO_M68HC12_FAR
},
317 /* .interrupt instruction. */
318 {"interrupt", s_m68hc11_mark_symbol
, STO_M68HC12_INTERRUPT
},
320 /* .nobankwarning instruction. */
321 {"nobankwarning", s_m68hc11_parse_pseudo_instruction
, E_M68HC11_NO_BANK_WARNING
},
326 /* Options and initialization. */
328 const char *md_shortopts
= "Sm:";
330 struct option md_longopts
[] =
332 #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
333 {"force-long-branches", no_argument
, NULL
, OPTION_FORCE_LONG_BRANCH
},
334 {"force-long-branchs", no_argument
, NULL
, OPTION_FORCE_LONG_BRANCH
}, /* Misspelt version kept for backwards compatibility. */
336 #define OPTION_SHORT_BRANCHES (OPTION_MD_BASE + 1)
337 {"short-branches", no_argument
, NULL
, OPTION_SHORT_BRANCHES
},
338 {"short-branchs", no_argument
, NULL
, OPTION_SHORT_BRANCHES
}, /* Misspelt version kept for backwards compatibility. */
340 #define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2)
341 {"strict-direct-mode", no_argument
, NULL
, OPTION_STRICT_DIRECT_MODE
},
343 #define OPTION_PRINT_INSN_SYNTAX (OPTION_MD_BASE + 3)
344 {"print-insn-syntax", no_argument
, NULL
, OPTION_PRINT_INSN_SYNTAX
},
346 #define OPTION_PRINT_OPCODES (OPTION_MD_BASE + 4)
347 {"print-opcodes", no_argument
, NULL
, OPTION_PRINT_OPCODES
},
349 #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5)
350 {"generate-example", no_argument
, NULL
, OPTION_GENERATE_EXAMPLE
},
352 #define OPTION_MSHORT (OPTION_MD_BASE + 6)
353 {"mshort", no_argument
, NULL
, OPTION_MSHORT
},
355 #define OPTION_MLONG (OPTION_MD_BASE + 7)
356 {"mlong", no_argument
, NULL
, OPTION_MLONG
},
358 #define OPTION_MSHORT_DOUBLE (OPTION_MD_BASE + 8)
359 {"mshort-double", no_argument
, NULL
, OPTION_MSHORT_DOUBLE
},
361 #define OPTION_MLONG_DOUBLE (OPTION_MD_BASE + 9)
362 {"mlong-double", no_argument
, NULL
, OPTION_MLONG_DOUBLE
},
364 #define OPTION_XGATE_RAMOFFSET (OPTION_MD_BASE + 10)
365 {"xgate-ramoffset", no_argument
, NULL
, OPTION_XGATE_RAMOFFSET
},
367 {NULL
, no_argument
, NULL
, 0}
369 size_t md_longopts_size
= sizeof (md_longopts
);
371 /* Get the target cpu for the assembler. This is based on the configure
372 options and on the -m68hc11/-m68hc12 option. If no option is specified,
373 we must get the default. */
375 m68hc11_arch_format (void)
377 get_default_target ();
378 if (current_architecture
& cpu6811
)
379 return "elf32-m68hc11";
381 return "elf32-m68hc12";
384 enum bfd_architecture
387 get_default_target ();
388 if (current_architecture
& cpu6811
)
389 return bfd_arch_m68hc11
;
391 return bfd_arch_m68hc12
;
400 /* Listing header selected according to cpu. */
402 m68hc11_listing_header (void)
404 if (current_architecture
& cpu6811
)
405 return "M68HC11 GAS ";
406 else if (current_architecture
& cpuxgate
)
408 else if (current_architecture
& cpu9s12x
)
411 return "M68HC12 GAS ";
415 md_show_usage (FILE *stream
)
417 get_default_target ();
418 fprintf (stream
, _("\
419 Motorola 68HC11/68HC12/68HCS12 options:\n\
420 -m68hc11 | -m68hc12 |\n\
421 -m68hcs12 | -mm9s12x |\n\
422 -mm9s12xg specify the processor [default %s]\n\
423 -mshort use 16-bit int ABI (default)\n\
424 -mlong use 32-bit int ABI\n\
425 -mshort-double use 32-bit double ABI\n\
426 -mlong-double use 64-bit double ABI (default)\n\
427 --force-long-branches always turn relative branches into absolute ones\n\
428 -S,--short-branches do not turn relative branches into absolute ones\n\
429 when the offset is out of range\n\
430 --strict-direct-mode do not turn the direct mode into extended mode\n\
431 when the instruction does not support direct mode\n\
432 --print-insn-syntax print the syntax of instruction in case of error\n\
433 --print-opcodes print the list of instructions with syntax\n\
434 --xgate-ramoffset offset ram addresses by 0xc000\n\
435 --generate-example generate an example of each instruction\n\
436 (used for testing)\n"), default_cpu
);
440 /* Try to identify the default target based on the BFD library. */
442 get_default_target (void)
444 const bfd_target
*target
;
447 if (current_architecture
!= 0)
450 default_cpu
= "unknown";
451 target
= bfd_find_target (0, &abfd
);
452 if (target
&& target
->name
)
454 if (strcmp (target
->name
, "elf32-m68hc12") == 0)
456 current_architecture
= cpu6812
;
457 default_cpu
= "m68hc12";
459 else if (strcmp (target
->name
, "elf32-m68hc11") == 0)
461 current_architecture
= cpu6811
;
462 default_cpu
= "m68hc11";
466 as_bad (_("Default target `%s' is not supported."), target
->name
);
472 m68hc11_print_statistics (FILE *file
)
475 struct m68hc11_opcode_def
*opc
;
477 hash_print_statistics (file
, "opcode table", m68hc11_hash
);
479 opc
= m68hc11_opcode_defs
;
480 if (opc
== 0 || m68hc11_nb_opcode_defs
== 0)
483 /* Dump the opcode statistics table. */
484 fprintf (file
, _("Name # Modes Min ops Max ops Modes mask # Used\n"));
485 for (i
= 0; i
< m68hc11_nb_opcode_defs
; i
++, opc
++)
487 fprintf (file
, "%-7.7s %5d %7d %7d 0x%08lx %7d\n",
490 opc
->min_operands
, opc
->max_operands
, opc
->format
, opc
->used
);
495 md_parse_option (int c
, char *arg
)
497 get_default_target ();
500 /* -S means keep external to 2 bit offset rather than 16 bit one. */
501 case OPTION_SHORT_BRANCHES
:
503 flag_fixed_branches
= 1;
506 case OPTION_FORCE_LONG_BRANCH
:
507 flag_force_long_jumps
= 1;
510 case OPTION_PRINT_INSN_SYNTAX
:
511 flag_print_insn_syntax
= 1;
514 case OPTION_PRINT_OPCODES
:
515 flag_print_opcodes
= 1;
518 case OPTION_STRICT_DIRECT_MODE
:
519 flag_strict_direct_addressing
= 0;
522 case OPTION_GENERATE_EXAMPLE
:
523 flag_print_opcodes
= 2;
527 elf_flags
&= ~E_M68HC11_I32
;
531 elf_flags
|= E_M68HC11_I32
;
534 case OPTION_MSHORT_DOUBLE
:
535 elf_flags
&= ~E_M68HC11_F64
;
538 case OPTION_MLONG_DOUBLE
:
539 elf_flags
|= E_M68HC11_F64
;
542 case OPTION_XGATE_RAMOFFSET
:
543 elf_flags
|= E_M68HC11_XGATE_RAMOFFSET
;
547 if ((strcasecmp (arg
, "68hc11") == 0)
548 || (strcasecmp (arg
, "m68hc11") == 0))
549 current_architecture
= cpu6811
;
550 else if ((strcasecmp (arg
, "68hc12") == 0)
551 || (strcasecmp (arg
, "m68hc12") == 0))
552 current_architecture
= cpu6812
;
553 else if ((strcasecmp (arg
, "68hcs12") == 0)
554 || (strcasecmp (arg
, "m68hcs12") == 0))
555 current_architecture
= cpu6812
| cpu6812s
;
556 else if (strcasecmp (arg
, "m9s12x") == 0)
557 current_architecture
= cpu6812
| cpu6812s
| cpu9s12x
;
558 else if ((strcasecmp (arg
, "m9s12xg") == 0)
559 || (strcasecmp (arg
, "xgate") == 0))
560 /* xgate for backwards compatability */
561 current_architecture
= cpuxgate
;
563 as_bad (_("Option `%s' is not recognized."), arg
);
574 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
580 md_atof (int type
, char *litP
, int *sizeP
)
582 return ieee_md_atof (type
, litP
, sizeP
, TRUE
);
586 md_section_align (asection
*seg
, valueT addr
)
588 int align
= bfd_get_section_alignment (stdoutput
, seg
);
589 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
593 cmp_opcode (struct m68hc11_opcode
*op1
, struct m68hc11_opcode
*op2
)
595 return strcmp (op1
->name
, op2
->name
);
598 #define IS_CALL_SYMBOL(MODE) \
599 (((MODE) & (M6812_OP_PAGE|M6811_OP_IND16)) \
600 == ((M6812_OP_PAGE|M6811_OP_IND16)))
602 /* Initialize the assembler. Create the opcode hash table
603 (sorted on the names) with the M6811 opcode table
604 (from opcode library). */
608 char *prev_name
= "";
609 struct m68hc11_opcode
*opcodes
;
610 struct m68hc11_opcode_def
*opc
= 0;
613 get_default_target ();
615 m68hc11_hash
= hash_new ();
617 /* Get a writable copy of the opcode table and sort it on the names. */
618 opcodes
= (struct m68hc11_opcode
*) xmalloc (m68hc11_num_opcodes
*
621 m68hc11_sorted_opcodes
= opcodes
;
623 for (i
= 0; i
< m68hc11_num_opcodes
; i
++)
625 if (m68hc11_opcodes
[i
].arch
& current_architecture
)
627 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
628 if (opcodes
[num_opcodes
].name
[0] == 'b'
629 && opcodes
[num_opcodes
].format
& M6811_OP_JUMP_REL
630 && !(opcodes
[num_opcodes
].format
& M6811_OP_BITMASK
))
633 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
636 for (j
= 0; alias_opcodes
[j
].name
!= 0; j
++)
637 if (strcmp (m68hc11_opcodes
[i
].name
, alias_opcodes
[j
].name
) == 0)
639 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
640 opcodes
[num_opcodes
].name
= alias_opcodes
[j
].alias
;
646 qsort (opcodes
, num_opcodes
, sizeof (struct m68hc11_opcode
),
647 (int (*) (const void*, const void*)) cmp_opcode
);
649 opc
= (struct m68hc11_opcode_def
*)
650 xmalloc (num_opcodes
* sizeof (struct m68hc11_opcode_def
));
651 m68hc11_opcode_defs
= opc
--;
653 /* Insert unique names into hash table. The M6811 instruction set
654 has several identical opcode names that have different opcodes based
655 on the operands. This hash table then provides a quick index to
656 the first opcode with a particular name in the opcode table. */
657 for (i
= 0; i
< num_opcodes
; i
++, opcodes
++)
661 if (strcmp (prev_name
, opcodes
->name
))
663 prev_name
= (char *) opcodes
->name
;
667 opc
->min_operands
= 100;
668 opc
->max_operands
= 0;
670 opc
->opcode
= opcodes
;
672 hash_insert (m68hc11_hash
, opcodes
->name
, opc
);
675 opc
->format
|= opcodes
->format
;
677 /* See how many operands this opcode needs. */
679 if (opcodes
->arch
== cpuxgate
)
681 if (opcodes
->format
& (M68XG_OP_IMM3
| M68XG_OP_R
| M68XG_OP_REL9
684 else if (opcodes
->format
& (M68XG_OP_R_R
| M68XG_OP_R_IMM4
685 | M68XG_OP_R_IMM8
| M68XG_OP_R_IMM8
))
687 else if (opcodes
->format
& (M68XG_OP_R_R_R
| M68XG_OP_R_R_OFFS5
688 | M68XG_OP_RD_RB_RI
| M68XG_OP_RD_RB_RIp
689 | M68XG_OP_RD_RB_mRI
))
694 if (opcodes
->format
& M6811_OP_MASK
)
696 if (opcodes
->format
& M6811_OP_BITMASK
)
698 if (opcodes
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
700 if (opcodes
->format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
702 /* Special case for call instruction. */
703 if ((opcodes
->format
& M6812_OP_PAGE
)
704 && !(opcodes
->format
& M6811_OP_IND16
))
708 if (expect
< opc
->min_operands
)
709 opc
->min_operands
= expect
;
710 if (IS_CALL_SYMBOL (opcodes
->format
))
712 if (expect
> opc
->max_operands
)
713 opc
->max_operands
= expect
;
716 m68hc11_nb_opcode_defs
= opc
- m68hc11_opcode_defs
;
718 if (flag_print_opcodes
)
720 print_opcode_list ();
726 m68hc11_init_after_args (void)
732 /* Return a string that represents the operand format for the instruction.
733 When example is true, this generates an example of operand. This is used
734 to give an example and also to generate a test. */
737 print_opcode_format (struct m68hc11_opcode
*opcode
, int example
)
739 static char buf
[128];
740 int format
= opcode
->format
;
746 if (current_architecture
== cpuxgate
)
748 if (format
& M68XG_OP_IMM3
)
751 sprintf (p
, "#%d", rand () & 0x007);
753 strcpy (p
, _("imm3"));
756 else if (format
& M68XG_OP_R
)
759 sprintf (p
, "R%d", rand () & 0x07);
764 else if (format
& M68XG_OP_R_R
)
767 sprintf (p
, "R%d,R%d", rand () & 0x07, rand () & 0x07);
769 strcpy (p
, _("RD,RS"));
772 else if (format
& M68XG_OP_R_IMM4
)
775 sprintf (p
, "R%d,#%d", rand () & 0x07, rand () & 0x0f);
777 strcpy (p
, _("RI, #imm4"));
780 else if (format
& M68XG_OP_R_R_R
)
783 sprintf (p
, "R%d,R%d,R%d", rand () & 0x07, rand () & 0x07, rand () & 0x07);
785 strcpy (p
, "RD,RS1,RS2");
788 else if (format
& M68XG_OP_REL9
)
791 sprintf (p
, "%d", rand () & 0x1FF);
793 strcpy (p
, "<rel9>");
796 else if (format
& M68XG_OP_REL10
)
799 sprintf (p
, "%d", rand () & 0x3FF);
801 strcpy (p
, "<rel10>");
804 else if (format
& M68XG_OP_R_R_OFFS5
)
807 sprintf (p
, "R%d, (R%d, #0x%x)", rand () & 0x07, rand () & 0x07, rand () & 0x1f);
809 strcpy (p
, _("RD, (RI,#offs5)"));
812 else if (format
& M68XG_OP_RD_RB_RI
)
815 sprintf (p
, "R%d, (R%d, R%d)", rand () & 0x07, rand () & 0x07, rand () & 0x07);
817 strcpy (p
, "RD, (RB, RI)");
820 else if (format
& M68XG_OP_RD_RB_RIp
)
823 sprintf (p
, "R%d, (R%d, R%d+)", rand () & 0x07, rand () & 0x07, rand () & 0x07);
825 strcpy (p
, "RD, (RB, RI+)");
828 else if (format
& M68XG_OP_RD_RB_mRI
)
831 sprintf (p
, "R%d, (R%d, -R%d)", rand () & 0x07, rand () & 0x07, rand () & 0x07);
833 strcpy (p
, "RD, (RB, -RI)");
836 else if (format
& M68XG_OP_R_IMM8
)
839 sprintf (p
, "R%d, #0x%x", rand () & 0x07, rand () & 0xff);
841 strcpy (p
, "RD, #imm8");
844 else if (format
& M68XG_OP_R_IMM16
)
847 sprintf (p
, "R%d, #0x%x", rand () & 0x07, rand () & 0xffff);
849 strcpy (p
, "RD, #imm16");
856 if (format
& M6811_OP_IMM8
)
859 sprintf (p
, "#%d", rand () & 0x0FF);
861 strcpy (p
, _("#<imm8>"));
865 if (format
& M6811_OP_IMM16
)
868 sprintf (p
, "#%d", rand () & 0x0FFFF);
870 strcpy (p
, _("#<imm16>"));
874 if (format
& M6811_OP_IX
)
877 sprintf (p
, "%d,X", rand () & 0x0FF);
879 strcpy (p
, _("<imm8>,X"));
883 if (format
& M6811_OP_IY
)
886 sprintf (p
, "%d,X", rand () & 0x0FF);
888 strcpy (p
, _("<imm8>,X"));
892 if (format
& M6812_OP_IDX
)
895 sprintf (p
, "%d,X", rand () & 0x0FF);
901 if (format
& M6812_OP_PAGE
)
904 sprintf (p
, ", %d", rand () & 0x0FF);
906 strcpy (p
, ", <page>");
910 if (format
& M6811_OP_DIRECT
)
913 sprintf (p
, "*Z%d", rand () & 0x0FF);
915 strcpy (p
, _("*<abs8>"));
919 if (format
& M6811_OP_BITMASK
)
925 sprintf (p
, "#$%02x", rand () & 0x0FF);
927 strcpy (p
, _("#<mask>"));
930 if (format
& M6811_OP_JUMP_REL
)
934 if (format
& M6811_OP_IND16
)
937 sprintf (p
, _("symbol%d"), rand () & 0x0FF);
939 strcpy (p
, _("<abs>"));
944 if (format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
948 if (format
& M6811_OP_BITMASK
)
950 sprintf (p
, ".+%d", rand () & 0x7F);
954 sprintf (p
, "L%d", rand () & 0x0FF);
958 strcpy (p
, _("<label>"));
964 /* Prints the list of instructions with the possible operands. */
966 print_opcode_list (void)
969 char *prev_name
= "";
970 struct m68hc11_opcode
*opcodes
;
971 int example
= flag_print_opcodes
== 2;
974 printf (_("# Example of `%s' instructions\n\t.sect .text\n_start:\n"),
977 opcodes
= m68hc11_sorted_opcodes
;
979 /* Walk the list sorted on names (by md_begin). We only report
980 one instruction per line, and we collect the different operand
982 for (i
= 0; i
< num_opcodes
; i
++, opcodes
++)
984 char *fmt
= print_opcode_format (opcodes
, example
);
988 printf ("L%d:\t", i
);
989 printf ("%s %s\n", opcodes
->name
, fmt
);
993 if (strcmp (prev_name
, opcodes
->name
))
998 printf ("%-5.5s ", opcodes
->name
);
999 prev_name
= (char *) opcodes
->name
;
1002 printf (" [%s]", fmt
);
1008 /* Print the instruction format. This operation is called when some
1009 instruction is not correct. Instruction format is printed as an
1012 print_insn_format (char *name
)
1014 struct m68hc11_opcode_def
*opc
;
1015 struct m68hc11_opcode
*opcode
;
1018 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, name
);
1021 as_bad (_("Instruction `%s' is not recognized."), name
);
1024 opcode
= opc
->opcode
;
1026 as_bad (_("Instruction formats for `%s':"), name
);
1031 fmt
= print_opcode_format (opcode
, 0);
1032 sprintf (buf
, "\t%-5.5s %s", opcode
->name
, fmt
);
1037 while (strcmp (opcode
->name
, name
) == 0);
1040 /* Analysis of 68HC11 and 68HC12 operands. */
1042 /* reg_name_search() finds the register number given its name.
1043 Returns the register number or REG_NONE on failure. */
1045 reg_name_search (char *name
)
1047 if (strcasecmp (name
, "x") == 0 || strcasecmp (name
, "ix") == 0)
1049 if (strcasecmp (name
, "y") == 0 || strcasecmp (name
, "iy") == 0)
1051 if (strcasecmp (name
, "a") == 0)
1053 if (strcasecmp (name
, "b") == 0)
1055 if (strcasecmp (name
, "d") == 0)
1057 if (strcasecmp (name
, "sp") == 0)
1059 if (strcasecmp (name
, "pc") == 0)
1061 if (strcasecmp (name
, "ccr") == 0)
1064 if (strcasecmp (name
, "r0") == 0)
1066 if (strcasecmp (name
, "r1") == 0)
1068 if (strcasecmp (name
, "r2") == 0)
1070 if (strcasecmp (name
, "r3") == 0)
1072 if (strcasecmp (name
, "r4") == 0)
1074 if (strcasecmp (name
, "r5") == 0)
1076 if (strcasecmp (name
, "r6") == 0)
1078 if (strcasecmp (name
, "r7") == 0)
1080 if (strcasecmp (name
, "sp") == 0)
1082 if (strcasecmp (name
, "pc") == 0)
1084 if (strcasecmp (name
, "ccr") == 0)
1090 skip_whites (char *p
)
1092 while (*p
== ' ' || *p
== '\t')
1098 /* Check the string at input_line_pointer
1099 to see if it is a valid register name. */
1101 register_name (void)
1103 register_id reg_number
;
1104 char c
, *p
= input_line_pointer
;
1106 if (!is_name_beginner (*p
++))
1109 while (is_part_of_name (*p
++))
1116 /* Look to see if it's in the register table. */
1117 reg_number
= reg_name_search (input_line_pointer
);
1118 if (reg_number
!= REG_NONE
)
1123 input_line_pointer
= p
;
1131 #define M6811_OP_CALL_ADDR 0x00800000
1132 #define M6811_OP_PAGE_ADDR 0x04000000
1134 /* Parse a string of operands and return an array of expressions.
1136 Operand mode[0] mode[1] exp[0] exp[1]
1137 #n M6811_OP_IMM16 - O_*
1138 *<exp> M6811_OP_DIRECT - O_*
1139 .{+-}<exp> M6811_OP_JUMP_REL - O_*
1140 <exp> M6811_OP_IND16 - O_*
1141 ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register
1142 n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register
1143 n,+r M6812_PRE_INC " "
1144 n,r- M6812_POST_DEC " "
1145 n,r+ M6812_POST_INC " "
1146 A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register
1147 [D,r] M6811_OP_D_IDX M6812_OP_REG O_register O_register
1148 [n,r] M6811_OP_D_IDX_2 M6812_OP_REG O_constant O_register */
1150 get_operand (operand
*oper
, int which
, long opmode
)
1152 char *p
= input_line_pointer
;
1156 oper
->exp
.X_op
= O_absent
;
1157 oper
->reg1
= REG_NONE
;
1158 oper
->reg2
= REG_NONE
;
1159 mode
= M6811_OP_NONE
;
1161 p
= skip_whites (p
);
1163 if (*p
== 0 || *p
== '\n' || *p
== '\r')
1165 input_line_pointer
= p
;
1169 if (*p
== '*' && (opmode
& (M6811_OP_DIRECT
| M6811_OP_IND16
)))
1171 mode
= M6811_OP_DIRECT
;
1176 if (!(opmode
& (M6811_OP_IMM8
| M6811_OP_IMM16
| M6811_OP_BITMASK
)))
1178 as_bad (_("Immediate operand is not allowed for operand %d."),
1183 mode
= M6811_OP_IMM16
;
1185 if (strncmp (p
, "%hi", 3) == 0)
1188 mode
|= M6811_OP_HIGH_ADDR
;
1190 else if (strncmp (p
, "%lo", 3) == 0)
1193 mode
|= M6811_OP_LOW_ADDR
;
1195 /* %page modifier is used to obtain only the page number
1196 of the address of a function. */
1197 else if (strncmp (p
, "%page", 5) == 0)
1200 mode
|= M6811_OP_PAGE_ADDR
;
1203 /* %addr modifier is used to obtain the physical address part
1204 of the function (16-bit). For 68HC12 the function will be
1205 mapped in the 16K window at 0x8000 and the value will be
1206 within that window (although the function address may not fit
1207 in 16-bit). See bfd/elf32-m68hc12.c for the translation. */
1208 else if (strncmp (p
, "%addr", 5) == 0)
1211 mode
|= M6811_OP_CALL_ADDR
;
1214 else if (*p
== '.' && (p
[1] == '+' || p
[1] == '-'))
1217 mode
= M6811_OP_JUMP_REL
;
1221 if (current_architecture
& cpu6811
)
1222 as_bad (_("Indirect indexed addressing is not valid for 68HC11."));
1225 mode
= M6812_OP_D_IDX
;
1226 p
= skip_whites (p
);
1228 else if (*p
== ',') /* Special handling of ,x and ,y. */
1231 input_line_pointer
= p
;
1233 reg
= register_name ();
1234 if (reg
!= REG_NONE
)
1237 oper
->exp
.X_op
= O_constant
;
1238 oper
->exp
.X_add_number
= 0;
1239 oper
->mode
= M6812_OP_IDX
;
1242 as_bad (_("Spurious `,' or bad indirect register addressing mode."));
1245 /* Handle 68HC12 page specification in 'call foo,%page(bar)'. */
1246 else if ((opmode
& M6812_OP_PAGE
) && strncmp (p
, "%page", 5) == 0)
1249 mode
= M6811_OP_PAGE_ADDR
| M6812_OP_PAGE
| M6811_OP_IND16
;
1251 input_line_pointer
= p
;
1253 if (mode
== M6811_OP_NONE
|| mode
== M6812_OP_D_IDX
)
1254 reg
= register_name ();
1258 if (reg
!= REG_NONE
)
1260 p
= skip_whites (input_line_pointer
);
1261 if (*p
== ']' && mode
== M6812_OP_D_IDX
)
1264 (_("Missing second register or offset for indexed-indirect mode."));
1269 oper
->mode
= mode
| M6812_OP_REG
;
1272 if (mode
== M6812_OP_D_IDX
)
1274 as_bad (_("Missing second register for indexed-indirect mode."));
1281 input_line_pointer
= p
;
1282 reg
= register_name ();
1283 if (reg
!= REG_NONE
)
1285 p
= skip_whites (input_line_pointer
);
1286 if (mode
== M6812_OP_D_IDX
)
1290 as_bad (_("Missing `]' to close indexed-indirect mode."));
1294 oper
->mode
= M6812_OP_D_IDX
;
1296 input_line_pointer
= p
;
1304 /* In MRI mode, isolate the operand because we can't distinguish
1305 operands from comments. */
1310 p
= skip_whites (p
);
1311 while (*p
&& *p
!= ' ' && *p
!= '\t')
1320 /* Parse as an expression. */
1321 expression (&oper
->exp
);
1330 expression (&oper
->exp
);
1333 if (oper
->exp
.X_op
== O_illegal
)
1335 as_bad (_("Illegal operand."));
1338 else if (oper
->exp
.X_op
== O_absent
)
1340 as_bad (_("Missing operand."));
1344 p
= input_line_pointer
;
1346 if (mode
== M6811_OP_NONE
|| mode
== M6811_OP_DIRECT
1347 || mode
== M6812_OP_D_IDX
)
1349 p
= skip_whites (input_line_pointer
);
1353 int possible_mode
= M6811_OP_NONE
;
1354 char *old_input_line
;
1359 /* 68HC12 pre increment or decrement. */
1360 if (mode
== M6811_OP_NONE
)
1364 possible_mode
= M6812_PRE_DEC
;
1369 possible_mode
= M6812_PRE_INC
;
1372 p
= skip_whites (p
);
1374 input_line_pointer
= p
;
1375 reg
= register_name ();
1377 /* Backtrack if we have a valid constant expression and
1378 it does not correspond to the offset of the 68HC12 indexed
1379 addressing mode (as in N,x). */
1380 if (reg
== REG_NONE
&& mode
== M6811_OP_NONE
1381 && possible_mode
!= M6811_OP_NONE
)
1383 oper
->mode
= M6811_OP_IND16
| M6811_OP_JUMP_REL
;
1384 input_line_pointer
= skip_whites (old_input_line
);
1388 if (possible_mode
!= M6811_OP_NONE
)
1389 mode
= possible_mode
;
1391 if ((current_architecture
& cpu6811
)
1392 && possible_mode
!= M6811_OP_NONE
)
1393 as_bad (_("Pre-increment mode is not valid for 68HC11"));
1395 if (which
== 0 && opmode
& M6812_OP_IDX_P2
1396 && reg
!= REG_X
&& reg
!= REG_Y
1397 && reg
!= REG_PC
&& reg
!= REG_SP
)
1400 input_line_pointer
= p
;
1403 if (reg
== REG_NONE
&& mode
!= M6811_OP_DIRECT
1404 && !(mode
== M6811_OP_NONE
&& opmode
& M6811_OP_IND16
))
1406 as_bad (_("Wrong register in register indirect mode."));
1409 if (mode
== M6812_OP_D_IDX
)
1411 p
= skip_whites (input_line_pointer
);
1414 as_bad (_("Missing `]' to close register indirect operand."));
1417 input_line_pointer
= p
;
1419 oper
->mode
= M6812_OP_D_IDX_2
;
1422 if (reg
!= REG_NONE
)
1425 if (mode
== M6811_OP_NONE
)
1427 p
= input_line_pointer
;
1430 mode
= M6812_POST_DEC
;
1432 if (current_architecture
& cpu6811
)
1434 (_("Post-decrement mode is not valid for 68HC11."));
1438 mode
= M6812_POST_INC
;
1440 if (current_architecture
& cpu6811
)
1442 (_("Post-increment mode is not valid for 68HC11."));
1445 mode
= M6812_OP_IDX
;
1447 input_line_pointer
= p
;
1450 mode
|= M6812_OP_IDX
;
1455 input_line_pointer
= old_input_line
;
1458 if (mode
== M6812_OP_D_IDX_2
)
1460 as_bad (_("Invalid indexed indirect mode."));
1465 /* If the mode is not known until now, this is either a label
1466 or an indirect address. */
1467 if (mode
== M6811_OP_NONE
)
1468 mode
= M6811_OP_IND16
| M6811_OP_JUMP_REL
;
1470 p
= input_line_pointer
;
1471 while (*p
== ' ' || *p
== '\t')
1473 input_line_pointer
= p
;
1479 #define M6812_AUTO_INC_DEC (M6812_PRE_INC | M6812_PRE_DEC \
1480 | M6812_POST_INC | M6812_POST_DEC)
1482 /* Checks that the number 'num' fits for a given mode. */
1484 check_range (long num
, int mode
)
1486 if (current_architecture
== cpuxgate
)
1491 return (num
>= 0 && num
<= 7) ? 1 : 0;
1493 case M68XG_OP_R_IMM4
:
1494 return (num
>= 0 && num
<= 15) ? 1 : 0;
1496 case M68XG_OP_R_R_OFFS5
:
1497 return (num
>= 0 && num
<= 31) ? 1 : 0;
1499 case M68XG_OP_R_IMM8
:
1500 return (num
>= 0 && num
<= 255) ? 1 : 0;
1502 case M68XG_OP_R_IMM16
:
1503 return (num
>= 0 && num
<= 65535) ? 1 : 0;
1505 case M68XG_OP_B_MARKER
:
1506 return (num
>= -512 && num
<= 511) ? 1 : 0;
1508 case M68XG_OP_BRA_MARKER
:
1509 return (num
>= -1024 && num
<= 1023) ? 1 : 0;
1517 /* Auto increment and decrement are ok for [-8..8] without 0. */
1518 if (mode
& M6812_AUTO_INC_DEC
)
1519 return (num
!= 0 && num
<= 8 && num
>= -8);
1521 /* The 68HC12 supports 5, 9 and 16-bit offsets. */
1522 if (mode
& (M6812_INDEXED_IND
| M6812_INDEXED
| M6812_OP_IDX
))
1523 mode
= M6811_OP_IND16
;
1525 if (mode
& M6812_OP_JUMP_REL16
)
1526 mode
= M6811_OP_IND16
;
1528 mode
&= ~M6811_OP_BRANCH
;
1533 case M6811_OP_DIRECT
:
1534 return (num
>= 0 && num
<= 255) ? 1 : 0;
1536 case M6811_OP_BITMASK
:
1539 return (((num
& 0xFFFFFF00) == 0) || ((num
& 0xFFFFFF00) == 0xFFFFFF00))
1542 case M6811_OP_JUMP_REL
:
1543 return (num
>= -128 && num
<= 127) ? 1 : 0;
1545 case M6811_OP_IND16
:
1546 case M6811_OP_IND16
| M6812_OP_PAGE
:
1547 case M6811_OP_IMM16
:
1548 return (((num
& 0xFFFF0000) == 0) || ((num
& 0xFFFF0000) == 0xFFFF0000))
1551 case M6812_OP_IBCC_MARKER
:
1552 case M6812_OP_TBCC_MARKER
:
1553 case M6812_OP_DBCC_MARKER
:
1554 return (num
>= -256 && num
<= 255) ? 1 : 0;
1556 case M6812_OP_TRAP_ID
:
1557 return ((num
>= 0x30 && num
<= 0x39)
1558 || (num
>= 0x40 && num
<= 0x0ff)) ? 1 : 0;
1566 /* Gas fixup generation. */
1568 /* Put a 1 byte expression described by 'oper'. If this expression contains
1569 unresolved symbols, generate an 8-bit fixup. */
1571 fixup8 (expressionS
*oper
, int mode
, int opmode
)
1577 if (oper
->X_op
== O_constant
)
1579 if (mode
& M6812_OP_TRAP_ID
1580 && !check_range (oper
->X_add_number
, M6812_OP_TRAP_ID
))
1582 static char trap_id_warn_once
= 0;
1584 as_bad (_("Trap id `%ld' is out of range."), oper
->X_add_number
);
1585 if (trap_id_warn_once
== 0)
1587 trap_id_warn_once
= 1;
1588 as_bad (_("Trap id must be within [0x30..0x39] or [0x40..0xff]."));
1592 if (!(mode
& M6812_OP_TRAP_ID
)
1593 && !check_range (oper
->X_add_number
, mode
))
1595 as_bad (_("Operand out of 8-bit range: `%ld'."), oper
->X_add_number
);
1597 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FF, 1);
1599 else if (oper
->X_op
!= O_register
)
1601 if (mode
& M6812_OP_TRAP_ID
)
1602 as_bad (_("The trap id must be a constant."));
1604 if (mode
== M6811_OP_JUMP_REL
)
1608 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1609 oper
, TRUE
, BFD_RELOC_8_PCREL
);
1610 fixp
->fx_pcrel_adjust
= 1;
1617 /* Now create an 8-bit fixup. If there was some %hi, %lo
1618 or %page modifier, generate the reloc accordingly. */
1619 if (opmode
& M6811_OP_HIGH_ADDR
)
1620 reloc
= BFD_RELOC_M68HC11_HI8
;
1621 else if (opmode
& M6811_OP_LOW_ADDR
)
1622 reloc
= BFD_RELOC_M68HC11_LO8
;
1623 else if (opmode
& M6811_OP_PAGE_ADDR
)
1624 reloc
= BFD_RELOC_M68HC11_PAGE
;
1626 reloc
= BFD_RELOC_8
;
1628 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1629 oper
, FALSE
, reloc
);
1630 if (reloc
!= BFD_RELOC_8
)
1631 fixp
->fx_no_overflow
= 1;
1633 number_to_chars_bigendian (f
, 0, 1);
1637 as_fatal (_("Operand `%x' not recognized in fixup8."), oper
->X_op
);
1641 /* Put a 2 byte expression described by 'oper'. If this expression contains
1642 unresolved symbols, generate a 16-bit fixup. */
1644 fixup16 (expressionS
*oper
, int mode
, int opmode ATTRIBUTE_UNUSED
)
1650 if (oper
->X_op
== O_constant
)
1652 if (!check_range (oper
->X_add_number
, mode
))
1654 as_bad (_("Operand out of 16-bit range: `%ld'."),
1655 oper
->X_add_number
);
1657 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FFFF, 2);
1659 else if (oper
->X_op
!= O_register
)
1664 if ((opmode
& M6811_OP_CALL_ADDR
) && (mode
& M6811_OP_IMM16
))
1665 reloc
= BFD_RELOC_M68HC11_LO16
;
1666 else if (mode
& M6812_OP_JUMP_REL16
)
1667 reloc
= BFD_RELOC_16_PCREL
;
1668 else if (mode
& M6812_OP_PAGE
)
1669 reloc
= BFD_RELOC_M68HC11_LO16
;
1671 reloc
= BFD_RELOC_16
;
1673 /* Now create a 16-bit fixup. */
1674 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 2,
1676 reloc
== BFD_RELOC_16_PCREL
,
1678 number_to_chars_bigendian (f
, 0, 2);
1679 if (reloc
== BFD_RELOC_16_PCREL
)
1680 fixp
->fx_pcrel_adjust
= 2;
1681 if (reloc
== BFD_RELOC_M68HC11_LO16
)
1682 fixp
->fx_no_overflow
= 1;
1686 as_fatal (_("Operand `%x' not recognized in fixup16."), oper
->X_op
);
1690 /* Put a 3 byte expression described by 'oper'. If this expression contains
1691 unresolved symbols, generate a 24-bit fixup. */
1693 fixup24 (expressionS
*oper
, int mode
, int opmode ATTRIBUTE_UNUSED
)
1699 if (oper
->X_op
== O_constant
)
1701 if (!check_range (oper
->X_add_number
, mode
))
1703 as_bad (_("Operand out of 16-bit range: `%ld'."),
1704 oper
->X_add_number
);
1706 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FFFFFF, 3);
1708 else if (oper
->X_op
!= O_register
)
1710 /* Now create a 24-bit fixup. */
1711 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 3,
1712 oper
, FALSE
, BFD_RELOC_M68HC11_24
);
1713 number_to_chars_bigendian (f
, 0, 3);
1717 as_fatal (_("Operand `%x' not recognized in fixup16."), oper
->X_op
);
1721 /* XGATE Put a 1 byte expression described by 'oper'. If this expression
1722 containts unresolved symbols, generate an 8-bit fixup. */
1724 fixup8_xg (expressionS
*oper
, int mode
, int opmode
)
1730 if (oper
->X_op
== O_constant
)
1735 if ((opmode
& M6811_OP_HIGH_ADDR
) || (opmode
& M6811_OP_LOW_ADDR
))
1737 if (opmode
& M6811_OP_HIGH_ADDR
)
1738 reloc
= BFD_RELOC_M68HC11_HI8
;
1740 reloc
= BFD_RELOC_M68HC11_LO8
;
1742 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1743 oper
, FALSE
, reloc
);
1744 fixp
->fx_no_overflow
= 1;
1745 number_to_chars_bigendian (f
, 0, 1);
1749 if (!(check_range (oper
->X_add_number
, mode
)))
1750 as_bad (_("Operand out of 8-bit range: `%ld'."),
1751 oper
->X_add_number
);
1752 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FF, 1);
1755 else if (oper
->X_op
!= O_register
)
1757 if (mode
== M68XG_OP_REL9
)
1761 /* Future improvement:
1762 This fixup/reloc isn't adding on constants to symbols. */
1763 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
-1, 2,
1764 oper
, TRUE
, BFD_RELOC_M68HC12_9_PCREL
);
1765 fixp
->fx_pcrel_adjust
= 1;
1767 else if (mode
== M68XG_OP_REL10
)
1771 /* Future improvement:
1772 This fixup/reloc isn't adding on constants to symbols. */
1773 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
-1, 2,
1774 oper
, TRUE
, BFD_RELOC_M68HC12_10_PCREL
);
1775 fixp
->fx_pcrel_adjust
= 1;
1782 /* Now create an 8-bit fixup. If there was some %hi, %lo
1783 modifier, generate the reloc accordingly. */
1784 if (opmode
& M6811_OP_HIGH_ADDR
)
1785 reloc
= BFD_RELOC_M68HC11_HI8
;
1786 else if (opmode
& M6811_OP_LOW_ADDR
)
1787 reloc
= BFD_RELOC_M68HC11_LO8
;
1789 reloc
= BFD_RELOC_8
;
1791 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1792 oper
, FALSE
, reloc
);
1793 if (reloc
!= BFD_RELOC_8
)
1794 fixp
->fx_no_overflow
= 1;
1796 number_to_chars_bigendian (f
, 0, 1);
1799 as_fatal (_("Operand `%x' not recognized in fixup8."), oper
->X_op
);
1802 /* 68HC11 and 68HC12 code generation. */
1804 /* Translate the short branch/bsr instruction into a long branch. */
1806 static unsigned char
1807 convert_branch (unsigned char code
)
1809 if (IS_OPCODE (code
, M6812_BSR
))
1811 else if (IS_OPCODE (code
, M6811_BSR
))
1813 else if (IS_OPCODE (code
, M6811_BRA
))
1814 return (current_architecture
& cpu6812
) ? M6812_JMP
: M6811_JMP
;
1816 as_fatal (_("Unexpected branch conversion with `%x'"), code
);
1818 /* Keep gcc happy. */
1822 /* Start a new insn that contains at least 'size' bytes. Record the
1823 line information of that insn in the dwarf2 debug sections. */
1825 m68hc11_new_insn (int size
)
1829 f
= frag_more (size
);
1831 dwarf2_emit_insn (size
);
1836 /* Builds a jump instruction (bra, bcc, bsr). */
1838 build_jump_insn (struct m68hc11_opcode
*opcode
, operand operands
[],
1839 int nb_operands
, int jmp_mode
)
1845 /* The relative branch conversion is not supported for
1847 gas_assert ((opcode
->format
& M6811_OP_BITMASK
) == 0);
1848 gas_assert (nb_operands
== 1);
1849 gas_assert (operands
[0].reg1
== REG_NONE
&& operands
[0].reg2
== REG_NONE
);
1851 code
= opcode
->opcode
;
1853 n
= operands
[0].exp
.X_add_number
;
1855 /* Turn into a long branch:
1856 - when force long branch option (and not for jbcc pseudos),
1857 - when jbcc and the constant is out of -128..127 range,
1858 - when branch optimization is allowed and branch out of range. */
1859 if ((jmp_mode
== 0 && flag_force_long_jumps
)
1860 || (operands
[0].exp
.X_op
== O_constant
1861 && (!check_range (n
, opcode
->format
) &&
1862 (jmp_mode
== 1 || flag_fixed_branches
== 0))))
1864 fix_new (frag_now
, frag_now_fix (), 0,
1865 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1867 if (code
== M6811_BSR
|| code
== M6811_BRA
|| code
== M6812_BSR
)
1869 code
= convert_branch (code
);
1871 f
= m68hc11_new_insn (1);
1872 number_to_chars_bigendian (f
, code
, 1);
1874 else if (current_architecture
& cpu6812
)
1876 /* 68HC12: translate the bcc into a lbcc. */
1877 f
= m68hc11_new_insn (2);
1878 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1879 number_to_chars_bigendian (f
+ 1, code
, 1);
1880 fixup16 (&operands
[0].exp
, M6812_OP_JUMP_REL16
,
1881 M6812_OP_JUMP_REL16
);
1886 /* 68HC11: translate the bcc into b!cc +3; jmp <L>. */
1887 f
= m68hc11_new_insn (3);
1889 number_to_chars_bigendian (f
, code
, 1);
1890 number_to_chars_bigendian (f
+ 1, 3, 1);
1891 number_to_chars_bigendian (f
+ 2, M6811_JMP
, 1);
1893 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, M6811_OP_IND16
);
1897 /* Branch with a constant that must fit in 8-bits. */
1898 if (operands
[0].exp
.X_op
== O_constant
)
1900 if (!check_range (n
, opcode
->format
))
1902 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1905 else if (opcode
->format
& M6812_OP_JUMP_REL16
)
1907 f
= m68hc11_new_insn (4);
1908 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1909 number_to_chars_bigendian (f
+ 1, code
, 1);
1910 number_to_chars_bigendian (f
+ 2, n
& 0x0ffff, 2);
1914 f
= m68hc11_new_insn (2);
1915 number_to_chars_bigendian (f
, code
, 1);
1916 number_to_chars_bigendian (f
+ 1, n
& 0x0FF, 1);
1919 else if (opcode
->format
& M6812_OP_JUMP_REL16
)
1921 fix_new (frag_now
, frag_now_fix (), 0,
1922 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1924 f
= m68hc11_new_insn (2);
1925 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1926 number_to_chars_bigendian (f
+ 1, code
, 1);
1927 fixup16 (&operands
[0].exp
, M6812_OP_JUMP_REL16
, M6812_OP_JUMP_REL16
);
1933 fix_new (frag_now
, frag_now_fix (), 0,
1934 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1936 /* Branch offset must fit in 8-bits, don't do some relax. */
1937 if (jmp_mode
== 0 && flag_fixed_branches
)
1939 op
= m68hc11_new_insn (1);
1940 number_to_chars_bigendian (op
, code
, 1);
1941 fixup8 (&operands
[0].exp
, M6811_OP_JUMP_REL
, M6811_OP_JUMP_REL
);
1944 /* bra/bsr made be changed into jmp/jsr. */
1945 else if (code
== M6811_BSR
|| code
== M6811_BRA
|| code
== M6812_BSR
)
1947 /* Allocate worst case storage. */
1948 op
= m68hc11_new_insn (3);
1949 number_to_chars_bigendian (op
, code
, 1);
1950 number_to_chars_bigendian (op
+ 1, 0, 1);
1951 frag_variant (rs_machine_dependent
, 1, 1,
1952 ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_UNDF
),
1953 operands
[0].exp
.X_add_symbol
, (offsetT
) n
,
1956 else if (current_architecture
& cpu6812
)
1958 op
= m68hc11_new_insn (2);
1959 number_to_chars_bigendian (op
, code
, 1);
1960 number_to_chars_bigendian (op
+ 1, 0, 1);
1961 frag_var (rs_machine_dependent
, 2, 2,
1962 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_UNDF
),
1963 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, op
);
1967 op
= m68hc11_new_insn (2);
1968 number_to_chars_bigendian (op
, code
, 1);
1969 number_to_chars_bigendian (op
+ 1, 0, 1);
1970 frag_var (rs_machine_dependent
, 3, 3,
1971 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_UNDF
),
1972 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, op
);
1977 /* Builds a dbne/dbeq/tbne/tbeq instruction. */
1979 build_dbranch_insn (struct m68hc11_opcode
*opcode
, operand operands
[],
1980 int nb_operands
, int jmp_mode
)
1986 /* The relative branch conversion is not supported for
1988 gas_assert ((opcode
->format
& M6811_OP_BITMASK
) == 0);
1989 gas_assert (nb_operands
== 2);
1990 gas_assert (operands
[0].reg1
!= REG_NONE
);
1992 code
= opcode
->opcode
& 0x0FF;
1994 f
= m68hc11_new_insn (1);
1995 number_to_chars_bigendian (f
, code
, 1);
1997 n
= operands
[1].exp
.X_add_number
;
1998 code
= operands
[0].reg1
;
2000 if (operands
[0].reg1
== REG_NONE
|| operands
[0].reg1
== REG_CCR
2001 || operands
[0].reg1
== REG_PC
)
2002 as_bad (_("Invalid register for dbcc/tbcc instruction."));
2004 if (opcode
->format
& M6812_OP_IBCC_MARKER
)
2006 else if (opcode
->format
& M6812_OP_TBCC_MARKER
)
2009 if (!(opcode
->format
& M6812_OP_EQ_MARKER
))
2012 /* Turn into a long branch:
2013 - when force long branch option (and not for jbcc pseudos),
2014 - when jdbcc and the constant is out of -256..255 range,
2015 - when branch optimization is allowed and branch out of range. */
2016 if ((jmp_mode
== 0 && flag_force_long_jumps
)
2017 || (operands
[1].exp
.X_op
== O_constant
2018 && (!check_range (n
, M6812_OP_IBCC_MARKER
) &&
2019 (jmp_mode
== 1 || flag_fixed_branches
== 0))))
2023 number_to_chars_bigendian (f
, code
, 1);
2024 number_to_chars_bigendian (f
+ 1, M6812_JMP
, 1);
2025 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, M6811_OP_IND16
);
2029 /* Branch with a constant that must fit in 9-bits. */
2030 if (operands
[1].exp
.X_op
== O_constant
)
2032 if (!check_range (n
, M6812_OP_IBCC_MARKER
))
2034 as_bad (_("Operand out of range for a relative branch: `%ld'"),
2043 number_to_chars_bigendian (f
, code
, 1);
2044 number_to_chars_bigendian (f
+ 1, n
& 0x0FF, 1);
2049 /* Branch offset must fit in 8-bits, don't do some relax. */
2050 if (jmp_mode
== 0 && flag_fixed_branches
)
2052 fixup8 (&operands
[0].exp
, M6811_OP_JUMP_REL
, M6811_OP_JUMP_REL
);
2058 number_to_chars_bigendian (f
, code
, 1);
2059 number_to_chars_bigendian (f
+ 1, 0, 1);
2060 frag_var (rs_machine_dependent
, 3, 3,
2061 ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_UNDF
),
2062 operands
[1].exp
.X_add_symbol
, (offsetT
) n
, f
);
2067 #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4)
2069 /* Assemble the post index byte for 68HC12 extended addressing modes. */
2072 build_indexed_byte (operand
*op
, int format ATTRIBUTE_UNUSED
, int move_insn
)
2074 unsigned char byte
= 0;
2079 val
= op
->exp
.X_add_number
;
2081 if (mode
& M6812_AUTO_INC_DEC
)
2084 if (mode
& (M6812_POST_INC
| M6812_POST_DEC
))
2087 if (op
->exp
.X_op
== O_constant
)
2089 if (!check_range (val
, mode
))
2090 as_bad (_("Increment/decrement value is out of range: `%ld'."),
2093 if (mode
& (M6812_POST_INC
| M6812_PRE_INC
))
2094 byte
|= (val
- 1) & 0x07;
2096 byte
|= (8 - ((val
) & 7)) | 0x8;
2102 as_fatal (_("Expecting a register."));
2117 as_bad (_("Invalid register for post/pre increment."));
2122 number_to_chars_bigendian (f
, byte
, 1);
2126 if (mode
& (M6812_OP_IDX
| M6812_OP_D_IDX_2
))
2147 as_bad (_("Invalid register."));
2151 if (op
->exp
.X_op
== O_constant
)
2153 if (!check_range (val
, M6812_OP_IDX
))
2154 as_bad (_("Offset out of 16-bit range: %ld."), val
);
2156 if (move_insn
&& !(val
>= -16 && val
<= 15)
2157 && ((!(mode
& M6812_OP_IDX
) && !(mode
& M6812_OP_D_IDX_2
))
2158 || !(current_architecture
& cpu9s12x
)))
2160 as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."),
2165 if (val
>= -16 && val
<= 15 && !(mode
& M6812_OP_D_IDX_2
))
2170 number_to_chars_bigendian (f
, byte
, 1);
2173 else if (val
>= -256 && val
<= 255 && !(mode
& M6812_OP_D_IDX_2
))
2180 number_to_chars_bigendian (f
, byte
, 1);
2181 number_to_chars_bigendian (f
+ 1, val
& 0x0FF, 1);
2187 if (mode
& M6812_OP_D_IDX_2
)
2193 number_to_chars_bigendian (f
, byte
, 1);
2194 number_to_chars_bigendian (f
+ 1, val
& 0x0FFFF, 2);
2199 if (mode
& M6812_OP_D_IDX_2
)
2201 byte
= (byte
<< 3) | 0xe3;
2203 number_to_chars_bigendian (f
, byte
, 1);
2205 fixup16 (&op
->exp
, 0, 0);
2207 else if (op
->reg1
!= REG_PC
)
2213 number_to_chars_bigendian (f
, byte
, 1);
2214 sym
= op
->exp
.X_add_symbol
;
2215 off
= op
->exp
.X_add_number
;
2216 if (op
->exp
.X_op
!= O_symbol
)
2218 sym
= make_expr_symbol (&op
->exp
);
2222 /* movb/movw cannot be relaxed. */
2225 if ((mode
& M6812_OP_IDX
) && (current_architecture
& cpu9s12x
))
2227 /* Must treat as a 16bit relocate as size of final result is unknown. */
2231 number_to_chars_bigendian (f
, byte
, 1);
2232 fix_new (frag_now
, f
- frag_now
->fr_literal
, 2,
2233 sym
, off
, 0, BFD_RELOC_M68HC12_16B
);
2239 /* Non-S12X will fail at relocate stage if offset out of range. */
2241 number_to_chars_bigendian (f
, byte
, 1);
2242 fix_new (frag_now
, f
- frag_now
->fr_literal
, 1,
2243 sym
, off
, 0, BFD_RELOC_M68HC12_5B
);
2249 number_to_chars_bigendian (f
, byte
, 1);
2250 frag_var (rs_machine_dependent
, 2, 2,
2251 ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_UNDF
),
2259 /* movb/movw cannot be relaxed. */
2263 number_to_chars_bigendian (f
, byte
, 1);
2264 fix_new (frag_now
, f
- frag_now
->fr_literal
, 1,
2265 op
->exp
.X_add_symbol
, op
->exp
.X_add_number
, 0, BFD_RELOC_M68HC12_5B
);
2270 number_to_chars_bigendian (f
, byte
, 1);
2271 frag_var (rs_machine_dependent
, 2, 2,
2272 ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_UNDF
),
2273 op
->exp
.X_add_symbol
,
2274 op
->exp
.X_add_number
, f
);
2280 if (mode
& (M6812_OP_REG
| M6812_OP_D_IDX
))
2282 if (mode
& M6812_OP_D_IDX
)
2284 if (op
->reg1
!= REG_D
)
2285 as_bad (_("Expecting register D for indexed indirect mode."));
2286 if ((move_insn
) && (!(current_architecture
& cpu9s12x
)))
2287 as_bad (_("Indexed indirect mode is not allowed for movb/movw."));
2304 as_bad (_("Invalid accumulator register."));
2329 as_bad (_("Invalid indexed register."));
2333 number_to_chars_bigendian (f
, byte
, 1);
2337 fprintf (stderr
, "mode = 0x%x\nop->reg1 = 0x%x\nop->reg2 = 0x%x\n",
2338 mode
, op
->reg1
, op
->reg2
);
2339 as_fatal (_("Addressing mode not implemented yet."));
2343 /* Assemble the 68HC12 register mode byte. */
2345 build_reg_mode (operand
*op
, int format
)
2350 if ((format
& M6812_OP_SEX_MARKER
)
2351 && (op
->reg1
!= REG_A
) && (op
->reg1
!= REG_B
) && (op
->reg1
!= REG_CCR
)
2352 && (!(current_architecture
& cpu9s12x
)))
2353 as_bad (_("Invalid source register for this instruction, use 'tfr'."));
2354 else if (op
->reg1
== REG_NONE
|| op
->reg1
== REG_PC
)
2355 as_bad (_("Invalid source register."));
2357 if (format
& M6812_OP_SEX_MARKER
2358 && op
->reg2
!= REG_D
2359 && op
->reg2
!= REG_X
&& op
->reg2
!= REG_Y
&& op
->reg2
!= REG_SP
)
2360 as_bad (_("Invalid destination register for this instruction, use 'tfr'."));
2361 else if (op
->reg2
== REG_NONE
|| op
->reg2
== REG_PC
)
2362 as_bad (_("Invalid destination register."));
2364 byte
= (op
->reg1
<< 4) | (op
->reg2
);
2365 if (format
& M6812_OP_EXG_MARKER
)
2368 if ((format
& M6812_OP_SEX_MARKER
)
2369 && (op
->reg1
== REG_D
) && (current_architecture
& cpu9s12x
))
2373 number_to_chars_bigendian (f
, byte
, 1);
2377 /* build_insn_xg takes a pointer to the opcode entry in the opcode table,
2378 the array of operand expressions and builds the corresponding instruction. */
2381 build_insn_xg (struct m68hc11_opcode
*opcode
,
2383 int nb_operands ATTRIBUTE_UNUSED
)
2388 /* Put the page code instruction if there is one. */
2389 format
= opcode
->format
;
2391 if (!(operands
[0].mode
& (M6811_OP_LOW_ADDR
| M6811_OP_HIGH_ADDR
)))
2392 /* Need to retain those two modes, but clear for others. */
2393 operands
[0].mode
= 0;
2395 if (format
& M68XG_OP_R_IMM8
)
2397 /* These opcodes are byte followed by imm8. */
2398 f
= m68hc11_new_insn (1);
2399 number_to_chars_bigendian (f
, opcode
->opcode
>> 8, 1);
2400 fixup8_xg (&operands
[0].exp
, format
, operands
[0].mode
);
2402 else if (format
& M68XG_OP_R_IMM16
)
2405 /* These opcodes expand into two imm8 instructions.
2406 Emit as low:high as per the Freescale datasheet.
2407 The linker requires them to be adjacent to handle the upper byte. */
2409 /* Build low byte. */
2410 f
= m68hc11_new_insn (1);
2411 number_to_chars_bigendian (f
, opcode
->opcode
>> 8, 1);
2412 operands
[0].mode
= M6811_OP_LOW_ADDR
;
2414 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
2415 &operands
[0].exp
, FALSE
, BFD_RELOC_M68HC12_LO8XG
);
2416 fixp
->fx_no_overflow
= 1;
2417 number_to_chars_bigendian (f
, 0, 1);
2419 /* Build high byte. */
2420 f
= m68hc11_new_insn (1);
2421 number_to_chars_bigendian (f
, (opcode
->opcode
>> 8) | 0x08, 1);
2422 operands
[0].mode
= M6811_OP_HIGH_ADDR
;
2424 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
2425 &operands
[0].exp
, FALSE
, BFD_RELOC_M68HC12_HI8XG
);
2426 fixp
->fx_no_overflow
= 1;
2427 number_to_chars_bigendian (f
, 0, 1);
2430 else if (format
& M68XG_OP_REL9
)
2432 f
= m68hc11_new_insn (1);
2433 number_to_chars_bigendian (f
, opcode
->opcode
>> 8, 1); /* High byte. */
2434 fixup8_xg (&operands
[0].exp
, format
, M68XG_OP_REL9
);
2436 else if (format
& M68XG_OP_REL10
)
2438 f
= m68hc11_new_insn (1);
2439 number_to_chars_bigendian (f
, opcode
->opcode
>> 8, 1); /* High byte. */
2440 fixup8_xg (&operands
[0].exp
, format
, M68XG_OP_REL10
);
2444 f
= m68hc11_new_insn (2);
2445 number_to_chars_bigendian (f
, opcode
->opcode
, 2);
2450 /* build_insn takes a pointer to the opcode entry in the opcode table,
2451 the array of operand expressions and builds the corresponding instruction.
2452 This operation only deals with non relative jumps insn (need special
2456 build_insn (struct m68hc11_opcode
*opcode
,
2458 int nb_operands ATTRIBUTE_UNUSED
)
2465 /* Put the page code instruction if there is one. */
2466 format
= opcode
->format
;
2468 if (format
& M6811_OP_BRANCH
)
2469 fix_new (frag_now
, frag_now_fix (), 0,
2470 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
2472 if (format
& OP_EXTENDED
)
2476 f
= m68hc11_new_insn (2);
2477 if (format
& M6811_OP_PAGE2
)
2478 page_code
= M6811_OPCODE_PAGE2
;
2479 else if (format
& M6811_OP_PAGE3
)
2480 page_code
= M6811_OPCODE_PAGE3
;
2482 page_code
= M6811_OPCODE_PAGE4
;
2484 number_to_chars_bigendian (f
, page_code
, 1);
2488 f
= m68hc11_new_insn (1);
2490 number_to_chars_bigendian (f
, opcode
->opcode
, 1);
2494 /* The 68HC12 movb and movw instructions are special. We have to handle
2495 them in a special way. */
2496 if (format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
2499 if (format
& M6812_OP_IDX
)
2501 build_indexed_byte (&operands
[0], format
, 1);
2503 format
&= ~M6812_OP_IDX
;
2505 if (format
& M6812_OP_IDX_P2
)
2507 build_indexed_byte (&operands
[1], format
, 1);
2509 format
&= ~M6812_OP_IDX_P2
;
2513 if (format
& (M6811_OP_DIRECT
| M6811_OP_IMM8
))
2515 fixup8 (&operands
[i
].exp
,
2516 format
& (M6811_OP_DIRECT
| M6811_OP_IMM8
| M6812_OP_TRAP_ID
),
2520 else if (IS_CALL_SYMBOL (format
) && nb_operands
== 1)
2522 format
&= ~M6812_OP_PAGE
;
2523 fixup24 (&operands
[i
].exp
, format
& M6811_OP_IND16
,
2527 else if (format
& (M6811_OP_IMM16
| M6811_OP_IND16
))
2529 fixup16 (&operands
[i
].exp
,
2530 format
& (M6811_OP_IMM16
| M6811_OP_IND16
| M6812_OP_PAGE
),
2534 else if (format
& (M6811_OP_IX
| M6811_OP_IY
))
2536 if ((format
& M6811_OP_IX
) && (operands
[0].reg1
!= REG_X
))
2537 as_bad (_("Invalid indexed register, expecting register X."));
2538 if ((format
& M6811_OP_IY
) && (operands
[0].reg1
!= REG_Y
))
2539 as_bad (_("Invalid indexed register, expecting register Y."));
2541 fixup8 (&operands
[0].exp
, M6811_OP_IX
, operands
[0].mode
);
2545 (M6812_OP_IDX
| M6812_OP_IDX_2
| M6812_OP_IDX_1
2546 | M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
2548 build_indexed_byte (&operands
[i
], format
, move_insn
);
2551 else if (format
& M6812_OP_REG
&& current_architecture
& cpu6812
)
2553 build_reg_mode (&operands
[i
], format
);
2556 if (format
& M6811_OP_BITMASK
)
2558 fixup8 (&operands
[i
].exp
, M6811_OP_BITMASK
, operands
[i
].mode
);
2561 if (format
& M6811_OP_JUMP_REL
)
2563 fixup8 (&operands
[i
].exp
, M6811_OP_JUMP_REL
, operands
[i
].mode
);
2565 else if (format
& M6812_OP_IND16_P2
)
2567 fixup16 (&operands
[1].exp
, M6811_OP_IND16
, operands
[1].mode
);
2569 if (format
& M6812_OP_PAGE
)
2571 fixup8 (&operands
[i
].exp
, M6812_OP_PAGE
, operands
[i
].mode
);
2575 /* Opcode identification and operand analysis. */
2577 /* find() gets a pointer to an entry in the opcode table. It must look at all
2578 opcodes with the same name and use the operands to choose the correct
2579 opcode. Returns the opcode pointer if there was a match and 0 if none. */
2580 static struct m68hc11_opcode
*
2581 find (struct m68hc11_opcode_def
*opc
, operand operands
[], int nb_operands
)
2584 struct m68hc11_opcode
*opcode
;
2585 struct m68hc11_opcode
*op_indirect
;
2588 opcode
= opc
->opcode
;
2590 /* Now search the opcode table table for one with operands
2591 that matches what we've got. */
2593 if (current_architecture
& cpuxgate
)
2595 /* Many XGATE insns are simple enough that we get an exact match. */
2596 for (pos
= match
= 0; match
== 0 && pos
< opc
->nb_modes
; pos
++, opcode
++)
2597 if (opcode
->format
== operands
[nb_operands
-1].mode
)
2605 /* Now search the opcode table table for one with operands
2606 that matches what we've got. We're only done if the operands matched so
2607 far AND there are no more to check. */
2608 for (pos
= match
= 0; match
== 0 && pos
< opc
->nb_modes
; pos
++, opcode
++)
2610 int poss_indirect
= 0;
2611 long format
= opcode
->format
;
2615 if (opcode
->format
& M6811_OP_MASK
)
2617 if (opcode
->format
& M6811_OP_BITMASK
)
2619 if (opcode
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2621 if (opcode
->format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
2623 if ((opcode
->format
& M6812_OP_PAGE
)
2624 && (!IS_CALL_SYMBOL (opcode
->format
) || nb_operands
== 2))
2627 for (i
= 0; expect
== nb_operands
&& i
< nb_operands
; i
++)
2629 int mode
= operands
[i
].mode
;
2631 if (mode
& M6811_OP_IMM16
)
2634 (M6811_OP_IMM8
| M6811_OP_IMM16
| M6811_OP_BITMASK
))
2638 if (mode
== M6811_OP_DIRECT
)
2640 if (format
& M6811_OP_DIRECT
)
2643 /* If the operand is a page 0 operand, remember a
2644 possible <abs-16> addressing mode. We mark
2645 this and continue to check other operands. */
2646 if (format
& M6811_OP_IND16
2647 && flag_strict_direct_addressing
&& op_indirect
== 0)
2654 if (mode
& M6811_OP_IND16
)
2656 if (i
== 0 && (format
& M6811_OP_IND16
) != 0)
2658 if (i
!= 0 && (format
& M6812_OP_PAGE
) != 0)
2660 if (i
!= 0 && (format
& M6812_OP_IND16_P2
) != 0)
2662 if (i
== 0 && (format
& M6811_OP_BITMASK
))
2665 if (mode
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2667 if (format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2670 if (mode
& M6812_OP_REG
)
2673 && (format
& M6812_OP_REG
)
2674 && (operands
[i
].reg2
== REG_NONE
))
2677 && (format
& M6812_OP_REG
)
2678 && (format
& M6812_OP_REG_2
)
2679 && (operands
[i
].reg2
!= REG_NONE
))
2682 && (format
& M6812_OP_IDX
)
2683 && (operands
[i
].reg2
!= REG_NONE
))
2686 && (format
& M6812_OP_IDX
)
2687 && (format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
)))
2690 && (format
& M6812_OP_IDX_P2
))
2694 if (mode
& M6812_OP_IDX
)
2696 if (format
& M6811_OP_IX
&& operands
[i
].reg1
== REG_X
)
2698 if (format
& M6811_OP_IY
&& operands
[i
].reg1
== REG_Y
)
2701 && format
& (M6812_OP_IDX
| M6812_OP_IDX_1
| M6812_OP_IDX_2
)
2702 && (operands
[i
].reg1
== REG_X
2703 || operands
[i
].reg1
== REG_Y
2704 || operands
[i
].reg1
== REG_SP
2705 || operands
[i
].reg1
== REG_PC
))
2707 if (i
== 1 && (format
& M6812_OP_IDX_P2
))
2710 if (mode
& format
& (M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
2715 if (mode
& M6812_AUTO_INC_DEC
)
2718 && format
& (M6812_OP_IDX
| M6812_OP_IDX_1
|
2721 if (i
== 1 && format
& M6812_OP_IDX_P2
)
2726 match
= i
== nb_operands
;
2728 /* Operands are ok but an operand uses page 0 addressing mode
2729 while the insn supports abs-16 mode. Keep a reference to this
2730 insns in case there is no insn supporting page 0 addressing. */
2731 if (match
&& poss_indirect
)
2733 op_indirect
= opcode
;
2740 /* Page 0 addressing is used but not supported by any insn.
2741 If absolute addresses are supported, we use that insn. */
2742 if (match
== 0 && op_indirect
)
2744 opcode
= op_indirect
;
2748 return match
? opcode
: 0;
2751 /* Find the real opcode and its associated operands. We use a progressive
2752 approach here. On entry, 'opc' points to the first opcode in the
2753 table that matches the opcode name in the source line. We try to
2754 isolate an operand, find a possible match in the opcode table.
2755 We isolate another operand if no match were found. The table 'operands'
2756 is filled while operands are recognized.
2758 Returns the opcode pointer that matches the opcode name in the
2759 source line and the associated operands. */
2760 static struct m68hc11_opcode
*
2761 find_opcode (struct m68hc11_opcode_def
*opc
, operand operands
[],
2764 struct m68hc11_opcode
*opcode
;
2767 if (opc
->max_operands
== 0)
2773 for (i
= 0; i
< opc
->max_operands
;)
2777 result
= get_operand (&operands
[i
], i
, opc
->format
);
2781 /* Special case where the bitmask of the bclr/brclr
2782 instructions is not introduced by #.
2783 Example: bclr 3,x $80. */
2784 if (i
== 1 && (opc
->format
& M6811_OP_BITMASK
)
2785 && (operands
[i
].mode
& M6811_OP_IND16
))
2787 operands
[i
].mode
= M6811_OP_IMM16
;
2792 if (i
>= opc
->min_operands
)
2794 opcode
= find (opc
, operands
, i
);
2796 /* Another special case for 'call foo,page' instructions.
2797 Since we support 'call foo' and 'call foo,page' we must look
2798 if the optional page specification is present otherwise we will
2799 assemble immediately and treat the page spec as garbage. */
2800 if (opcode
&& !(opcode
->format
& M6812_OP_PAGE
))
2803 if (opcode
&& *input_line_pointer
!= ',')
2807 if (*input_line_pointer
== ',')
2808 input_line_pointer
++;
2814 #define M6812_XBCC_MARKER (M6812_OP_TBCC_MARKER \
2815 | M6812_OP_DBCC_MARKER \
2816 | M6812_OP_IBCC_MARKER)
2818 /* Gas line assembler entry point. */
2820 /* This is the main entry point for the machine-dependent assembler. str
2821 points to a machine-dependent instruction. This function is supposed to
2822 emit the frags/bytes it assembles to. */
2824 md_assemble (char *str
)
2826 struct m68hc11_opcode_def
*opc
;
2827 struct m68hc11_opcode
*opcode
;
2829 struct m68hc11_opcode opcode_local
;
2830 unsigned char *op_start
, *op_end
;
2834 operand operands
[M6811_MAX_OPERANDS
];
2835 int nb_operands
= 0;
2836 int branch_optimize
= 0;
2839 /* Drop leading whitespace. */
2843 /* Find the opcode end and get the opcode in 'name'. The opcode is forced
2844 lower case (the opcode table only has lower case op-codes). */
2845 for (op_start
= op_end
= (unsigned char *) str
;
2846 *op_end
&& !is_end_of_line
[*op_end
] && *op_end
!= ' ';
2849 name
[nlen
] = TOLOWER (op_start
[nlen
]);
2851 if (nlen
== sizeof (name
) - 1)
2858 as_bad (_("No instruction or missing opcode."));
2862 if (current_architecture
== cpuxgate
)
2864 /* Find the opcode definition given its name. */
2865 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, name
);
2868 as_bad (_("Opcode `%s' is not recognized."), name
);
2872 /* Grab a local copy. */
2873 opcode_local
.name
= opc
->opcode
->name
;
2874 /* These will be incomplete where multiple variants exist. */
2875 opcode_local
.opcode
= opc
->opcode
->opcode
;
2876 opcode_local
.format
= opc
->opcode
->format
;
2878 save
= input_line_pointer
;
2879 input_line_pointer
= (char *) op_end
;
2881 if (opc
->format
== M68XG_OP_NONE
)
2883 /* No special handling required. */
2884 opcode_local
.format
= M68XG_OP_NONE
;
2885 build_insn_xg (opc
->opcode
, operands
, 0);
2889 /* Special handling of TFR. */
2890 if (strncmp (opc
->opcode
->name
, "tfr",3) == 0)
2892 /* There must be two operands with a comma. */
2893 input_line_pointer
= skip_whites (input_line_pointer
);
2894 operands
[0].reg1
= register_name ();
2895 if (operands
[0].reg1
== REG_NONE
)
2897 as_bad ("Invalid register\n");
2900 input_line_pointer
= skip_whites (input_line_pointer
);
2901 if (*input_line_pointer
!= ',')
2903 as_bad ("Missing comma.\n");
2906 input_line_pointer
++;
2907 input_line_pointer
= skip_whites (input_line_pointer
);
2908 operands
[1].reg1
= register_name ();
2909 if (operands
[1].reg1
== REG_NONE
)
2911 as_bad ("Invalid register\n");
2914 input_line_pointer
= skip_whites (input_line_pointer
);
2915 if (*input_line_pointer
!= '\n' && *input_line_pointer
)
2917 as_bad (_("Garbage at end of instruction: `%s'."),
2918 input_line_pointer
);
2921 if (operands
[1].reg1
== REG_CCR
) /* ,CCR */
2922 opc
->opcode
->opcode
= 0x00f8 | ( operands
[0].reg1
<< 8);
2923 else if (operands
[0].reg1
== REG_CCR
) /* CCR, */
2924 opc
->opcode
->opcode
= 0x00f9 | ( operands
[1].reg1
<< 8);
2925 else if (operands
[1].reg1
== REG_PC
) /* ,PC */
2926 opc
->opcode
->opcode
= 0x00fa | ( operands
[0].reg1
<< 8);
2929 as_bad ("Invalid operand to TFR\n");
2932 /* no special handling required */
2933 opcode_local
.format
= M68XG_OP_NONE
;
2934 opcode_local
.opcode
= opc
->opcode
->opcode
;
2935 build_insn_xg (&opcode_local
, operands
, 0);
2940 if (opc
->format
& M68XG_OP_IMM3
)
2942 /* Either IMM3 or R */
2943 input_line_pointer
= skip_whites (input_line_pointer
);
2944 if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
2946 operands
[0].reg1
= register_name ();
2947 if (operands
[0].reg1
== REG_NONE
)
2949 as_bad ("Invalid register\n");
2952 operands
[0].mode
= M68XG_OP_R
;
2953 /* One opcode has multiple modes, so find right one. */
2954 opcode
= find (opc
, operands
, 1);
2957 opcode_local
.opcode
= opcode
->opcode
2958 | (operands
[0].reg1
<< 8);
2959 opcode_local
.format
= M68XG_OP_NONE
;
2960 build_insn_xg (&opcode_local
, operands
, 1);
2963 as_bad ("No opcode found\n");
2969 if (*input_line_pointer
== '#')
2970 input_line_pointer
++;
2972 expression (&operands
[0].exp
);
2973 if (operands
[0].exp
.X_op
== O_illegal
)
2975 as_bad (_("Illegal operand."));
2978 else if (operands
[0].exp
.X_op
== O_absent
)
2980 as_bad (_("Missing operand."));
2984 if (check_range (operands
[0].exp
.X_add_number
,M68XG_OP_IMM3
))
2986 opcode_local
.opcode
|= (operands
[0].exp
.X_add_number
);
2987 operands
[0].mode
= M68XG_OP_IMM3
;
2989 opcode
= find (opc
, operands
, 1);
2992 opcode_local
.opcode
= opcode
->opcode
;
2994 |= (operands
[0].exp
.X_add_number
) << 8;
2995 opcode_local
.format
= M68XG_OP_NONE
;
2996 build_insn_xg (&opcode_local
, operands
, 1);
2999 as_bad ("No opcode found\n");
3005 as_bad ("Number out of range for IMM3\n");
3011 /* Special handling of SIF. */
3012 if (strncmp (opc
->opcode
->name
, "sif",3) == 0)
3014 /* Either OP_NONE or OP_RS. */
3015 if (*input_line_pointer
!= '\n')
3016 input_line_pointer
= skip_whites (input_line_pointer
);
3018 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3019 || (*input_line_pointer
== '\0'))
3020 opc
->opcode
->opcode
= 0x0300;
3023 operands
[0].reg1
= register_name ();
3024 if (operands
[0].reg1
== REG_NONE
)
3026 as_bad ("Invalid register\n");
3029 opcode_local
.opcode
= 0x00f7 | (operands
[0].reg1
<< 8);
3031 opcode_local
.format
= M68XG_OP_NONE
;
3032 build_insn_xg (&opcode_local
, operands
, 0);
3036 /* SEX, PAR, JAL plus aliases NEG, TST, COM */
3037 if (opc
->format
& M68XG_OP_R
)
3039 input_line_pointer
= skip_whites (input_line_pointer
);
3040 operands
[0].reg1
= register_name ();
3041 if (operands
[0].reg1
== REG_NONE
)
3043 as_bad ("Invalid register\n");
3046 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3047 || (*input_line_pointer
== '\0'))
3049 /* Likely to be OP R. */
3050 if (opc
->format
& M68XG_OP_R
)
3052 operands
[0].mode
= M68XG_OP_R
;
3054 opcode
= find (opc
, operands
, 1);
3057 if ((strncmp (opc
->opcode
->name
, "com",3) == 0)
3058 || (strncmp (opc
->opcode
->name
, "neg",3) == 0))
3059 /* Special case for com RD as alias for sub RD,R0,RS */
3060 /* Special case for neg RD as alias for sub RD,R0,RS */
3061 opcode_local
.opcode
= opcode
->opcode
3062 | (operands
[0].reg1
<< 8) | (operands
[0].reg1
<< 2);
3063 else if (strncmp (opc
->opcode
->name
, "tst",3) == 0)
3064 /* Special case for tst RS alias for sub R0, RS, R0 */
3065 opcode_local
.opcode
= opcode
->opcode
3066 | (operands
[0].reg1
<< 5);
3068 opcode_local
.opcode
|= (operands
[0].reg1
<< 8);
3070 opcode_local
.format
= M68XG_OP_NONE
;
3071 build_insn_xg (&opcode_local
, operands
, 0);
3074 as_bad ("No valid mode found\n");
3080 if (opc
->format
& (M68XG_OP_REL9
| M68XG_OP_REL10
))
3082 opcode_local
.format
= opc
->format
;
3083 input_line_pointer
= skip_whites (input_line_pointer
);
3084 expression (&operands
[0].exp
);
3085 if (operands
[0].exp
.X_op
== O_illegal
)
3087 as_bad (_("Illegal operand."));
3090 else if (operands
[0].exp
.X_op
== O_absent
)
3092 as_bad (_("Missing operand."));
3095 opcode_local
.opcode
= opc
->opcode
->opcode
;
3096 build_insn_xg (&opcode_local
, operands
, 1);
3101 /* For other command formats, parse input line and determine the mode
3102 we are using as we go. */
3104 input_line_pointer
= skip_whites (input_line_pointer
);
3105 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3106 || (*input_line_pointer
== '\0'))
3107 return; /* nothing left */
3109 if (*input_line_pointer
== '#')
3111 as_bad ("No register specified before hash\n");
3115 /* first operand is expected to be a register */
3116 if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
3118 operands
[0].reg1
= register_name ();
3119 if (operands
[0].reg1
== REG_NONE
)
3121 as_bad ("Invalid register\n");
3126 input_line_pointer
= skip_whites (input_line_pointer
);
3127 if (*input_line_pointer
!= ',')
3129 as_bad ("Missing operand\n");
3132 input_line_pointer
++;
3133 input_line_pointer
= skip_whites (input_line_pointer
);
3135 if (*input_line_pointer
== '#')
3137 /* Some kind of immediate mode, check if this is possible. */
3139 & (M68XG_OP_R_IMM8
| M68XG_OP_R_IMM16
| M68XG_OP_R_IMM4
)))
3140 as_bad ("Invalid immediate mode for `%s'", opc
->opcode
->name
);
3143 input_line_pointer
++;
3144 input_line_pointer
= skip_whites (input_line_pointer
);
3145 if (strncmp (input_line_pointer
, "%hi", 3) == 0)
3147 input_line_pointer
+= 3;
3148 operands
[0].mode
= M6811_OP_HIGH_ADDR
;
3150 else if (strncmp (input_line_pointer
, "%lo", 3) == 0)
3152 input_line_pointer
+= 3;
3153 operands
[0].mode
= M6811_OP_LOW_ADDR
;
3156 operands
[0].mode
= 0;
3158 expression (&operands
[0].exp
);
3159 if (operands
[0].exp
.X_op
== O_illegal
)
3161 as_bad (_("Illegal operand."));
3164 else if (operands
[0].exp
.X_op
== O_absent
)
3166 as_bad (_("Missing operand."));
3169 /* ok so far, can only be one mode */
3170 opcode_local
.format
= opc
->format
3171 & (M68XG_OP_R_IMM8
| M68XG_OP_R_IMM16
| M68XG_OP_R_IMM4
);
3172 if (opcode_local
.format
& M68XG_OP_R_IMM4
)
3174 operands
[0].mode
= M68XG_OP_R_IMM4
;
3175 /* same opcodes have multiple modes, so find right one */
3176 opcode
= find (opc
, operands
, 1);
3178 opcode_local
.opcode
= opcode
->opcode
3179 | (operands
[0].reg1
<< 8);
3181 if (operands
[0].exp
.X_op
!= O_constant
)
3182 as_bad ("Only constants supported at for IMM4 mode\n");
3186 (operands
[0].exp
.X_add_number
,M68XG_OP_R_IMM4
))
3188 |= (operands
[0].exp
.X_add_number
<< 4);
3190 as_bad ("Number out of range for IMM4\n");
3192 opcode_local
.format
= M68XG_OP_NONE
;
3194 else if (opcode_local
.format
& M68XG_OP_R_IMM16
)
3196 operands
[0].mode
= M68XG_OP_R_IMM16
;
3198 opcode
= find (opc
, operands
, 1);
3201 opcode_local
.opcode
= opcode
->opcode
3202 | (operands
[0].reg1
<< 8);
3207 opcode_local
.opcode
= opc
->opcode
->opcode
3208 | (operands
[0].reg1
<< 8);
3210 build_insn_xg (&opcode_local
, operands
, 1);
3213 else if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
3215 /* we've got as far as OP R, R */
3216 operands
[1].reg1
= register_name ();
3217 if (operands
[1].reg1
== REG_NONE
)
3219 as_bad ("Invalid register\n");
3222 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3223 || (*input_line_pointer
== '\0'))
3225 /* looks like OP_R_R */
3226 if (opc
->format
& M68XG_OP_R_R
)
3228 operands
[0].mode
= M68XG_OP_R_R
;
3229 /* same opcodes have multiple modes, so find right one */
3230 opcode
= find (opc
, operands
, 1);
3233 if ((strncmp (opc
->opcode
->name
, "com",3) == 0)
3234 || (strncmp (opc
->opcode
->name
, "mov",3) == 0)
3235 || (strncmp (opc
->opcode
->name
, "neg",3) == 0))
3237 /* Special cases for:
3238 com RD, RS alias for xnor RD,R0,RS
3239 mov RD, RS alias for or RD, R0, RS
3240 neg RD, RS alias for sub RD, R0, RS */
3241 opcode_local
.opcode
= opcode
->opcode
3242 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 2);
3244 else if ((strncmp (opc
->opcode
->name
, "cmp",3) == 0)
3245 || (strncmp (opc
->opcode
->name
, "cpc",3) == 0))
3247 /* special cases for:
3248 cmp RS1, RS2 alias for sub R0, RS1, RS2
3249 cpc RS1, RS2 alias for sbc R0, RS1, RS2 */
3250 opcode_local
.opcode
= opcode
->opcode
3251 | (operands
[0].reg1
<< 5) | (operands
[1].reg1
<< 2);
3255 opcode_local
.opcode
= opcode
->opcode
3256 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 5);
3258 opcode_local
.format
= M68XG_OP_NONE
;
3259 build_insn_xg (&opcode_local
, operands
, 1);
3264 as_bad ("No valid mode found\n");
3270 if (*input_line_pointer
!= ',')
3272 as_bad (_("Missing operand."));
3275 input_line_pointer
++;
3276 input_line_pointer
= skip_whites (input_line_pointer
);
3277 if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
3279 operands
[2].reg1
= register_name ();
3280 if (operands
[2].reg1
== REG_NONE
)
3282 as_bad ("Invalid register\n");
3285 if (opc
->format
& M68XG_OP_R_R_R
)
3287 operands
[0].mode
= M68XG_OP_R_R_R
;
3289 opcode
= find (opc
, operands
, 1);
3292 opcode_local
.opcode
= opcode
->opcode
3293 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 5)
3294 | (operands
[2].reg1
<< 2);
3295 opcode_local
.format
= M68XG_OP_NONE
;
3296 build_insn_xg (&opcode_local
, operands
, 1);
3301 as_bad ("No valid mode found\n");
3306 else if (*input_line_pointer
== '(') /* Indexed modes */
3308 input_line_pointer
++;
3309 input_line_pointer
= skip_whites (input_line_pointer
);
3310 if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
3312 /* we've got as far as OP R, (R */
3313 operands
[1].reg1
= register_name ();
3314 if (operands
[1].reg1
== REG_NONE
)
3316 as_bad ("Invalid register\n");
3320 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3321 || (*input_line_pointer
== '\0'))
3323 /* Looks like OP_R_R. */
3324 as_bad (_("Missing operand."));
3328 input_line_pointer
= skip_whites (input_line_pointer
);
3330 if (*input_line_pointer
!= ',')
3332 as_bad (_("Missing operand."));
3335 input_line_pointer
++;
3336 input_line_pointer
= skip_whites (input_line_pointer
);
3338 if (*input_line_pointer
== '#')
3340 input_line_pointer
++;
3341 input_line_pointer
= skip_whites (input_line_pointer
);
3342 expression (&operands
[0].exp
);
3343 if (operands
[0].exp
.X_op
== O_illegal
)
3345 as_bad (_("Illegal operand."));
3348 else if (operands
[0].exp
.X_op
== O_absent
)
3350 as_bad (_("Missing operand."));
3354 input_line_pointer
= skip_whites (input_line_pointer
);
3355 if (*input_line_pointer
!= ')')
3357 as_bad ("Missing `)' to close register indirect operand.");
3362 input_line_pointer
++;
3365 /* Ok so far, can only be one mode. */
3366 opcode_local
.format
= M68XG_OP_R_R_OFFS5
;
3367 operands
[0].mode
= M68XG_OP_R_R_OFFS5
;
3369 opcode
= find (opc
, operands
, 1);
3372 opcode_local
.opcode
= opcode
->opcode
3373 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 5);
3374 if (operands
[0].exp
.X_op
!= O_constant
)
3377 ("Only constants supported for indexed OFFS5 mode\n");
3381 if (check_range (operands
[0].exp
.X_add_number
,
3382 M68XG_OP_R_R_OFFS5
))
3385 |= (operands
[0].exp
.X_add_number
);
3386 opcode_local
.format
= M68XG_OP_NONE
;
3387 build_insn_xg (&opcode_local
, operands
, 1);
3391 as_bad ("Number out of range for OFFS5\n");
3398 operands
[0].mode
= M68XG_OP_RD_RB_RI
;
3400 if (*input_line_pointer
== '-')
3402 operands
[0].mode
= M68XG_OP_RD_RB_mRI
;
3403 input_line_pointer
++;
3405 operands
[2].reg1
= register_name ();
3406 if (operands
[2].reg1
== REG_NONE
)
3408 as_bad ("Invalid register\n");
3412 if (*input_line_pointer
== '+')
3414 if (opcode_local
.format
== M68XG_OP_RD_RB_mRI
)
3416 as_bad (_("Illegal operand."));
3419 operands
[0].mode
= M68XG_OP_RD_RB_RIp
;
3420 input_line_pointer
++;
3423 input_line_pointer
= skip_whites (input_line_pointer
);
3424 if (*input_line_pointer
!= ')')
3427 ("Missing `)' to close register indirect operand.");
3432 input_line_pointer
++;
3435 opcode
= find (opc
, operands
, 1);
3438 opcode_local
.opcode
= opcode
->opcode
3439 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 5)
3440 | (operands
[2].reg1
<< 2);
3441 opcode_local
.format
= M68XG_OP_NONE
;
3442 build_insn_xg (&opcode_local
, operands
, 1);
3446 as_bad ("Failed to find opcode for %s %s\n",
3447 opc
->opcode
->name
, (char *)op_end
);
3454 as_bad (_("Failed to find a valid mode for `%s'."),
3458 if (opc
->opcode
&& !flag_mri
)
3460 char *p
= input_line_pointer
;
3462 while (*p
== ' ' || *p
== '\t' || *p
== '\n' || *p
== '\r')
3465 if (*p
!= '\n' && *p
)
3466 as_bad (_("Garbage at end of instruction: `%s'."), p
);
3469 input_line_pointer
= save
;
3471 /* Opcode is known but does not have valid operands. Print out the
3472 syntax for this opcode. */
3473 if (opc
->opcode
== 0)
3475 if (flag_print_insn_syntax
)
3476 print_insn_format (name
);
3478 as_bad (_("Invalid operand for `%s'"), name
);
3485 /* Find the opcode definition given its name. */
3486 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, name
);
3488 /* If it's not recognized, look for 'jbsr' and 'jbxx'. These are
3489 pseudo insns for relative branch. For these branches, we always
3490 optimize them (turned into absolute branches) even if --short-branches
3492 if (opc
== NULL
&& name
[0] == 'j' && name
[1] == 'b')
3494 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, &name
[1]);
3496 && (!(opc
->format
& M6811_OP_JUMP_REL
)
3497 || (opc
->format
& M6811_OP_BITMASK
)))
3500 branch_optimize
= 1;
3503 /* The following test should probably be removed. This does not conform
3504 to Motorola assembler specs. */
3505 if (opc
== NULL
&& flag_mri
)
3507 if (*op_end
== ' ' || *op_end
== '\t')
3509 while (*op_end
== ' ' || *op_end
== '\t')
3514 (is_end_of_line
[op_end
[1]]
3515 || op_end
[1] == ' ' || op_end
[1] == '\t'
3516 || !ISALNUM (op_end
[1])))
3517 && (*op_end
== 'a' || *op_end
== 'b'
3518 || *op_end
== 'A' || *op_end
== 'B'
3519 || *op_end
== 'd' || *op_end
== 'D'
3520 || *op_end
== 'x' || *op_end
== 'X'
3521 || *op_end
== 'y' || *op_end
== 'Y'))
3523 name
[nlen
++] = TOLOWER (*op_end
++);
3525 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
,
3531 /* Identify a possible instruction alias. There are some on the
3532 68HC12 to emulate a few 68HC11 instructions. */
3533 if (opc
== NULL
&& (current_architecture
& cpu6812
))
3537 for (i
= 0; i
< m68hc12_num_alias
; i
++)
3538 if (strcmp (m68hc12_alias
[i
].name
, name
) == 0)
3544 if (opc
== NULL
&& alias_id
< 0)
3546 as_bad (_("Opcode `%s' is not recognized."), name
);
3549 save
= input_line_pointer
;
3550 input_line_pointer
= (char *) op_end
;
3555 opcode
= find_opcode (opc
, operands
, &nb_operands
);
3560 if ((opcode
|| alias_id
>= 0) && !flag_mri
)
3562 char *p
= input_line_pointer
;
3564 while (*p
== ' ' || *p
== '\t' || *p
== '\n' || *p
== '\r')
3567 if (*p
!= '\n' && *p
)
3568 as_bad (_("Garbage at end of instruction: `%s'."), p
);
3571 input_line_pointer
= save
;
3575 char *f
= m68hc11_new_insn (m68hc12_alias
[alias_id
].size
);
3577 number_to_chars_bigendian (f
, m68hc12_alias
[alias_id
].code1
, 1);
3578 if (m68hc12_alias
[alias_id
].size
> 1)
3579 number_to_chars_bigendian (f
+ 1, m68hc12_alias
[alias_id
].code2
, 1);
3584 /* Opcode is known but does not have valid operands. Print out the
3585 syntax for this opcode. */
3588 if (flag_print_insn_syntax
)
3589 print_insn_format (name
);
3591 if (((strcmp (name
, "movb") == 0) || (strcmp (name
, "movw") == 0))
3592 && (current_architecture
& cpu9s12x
))
3596 if (strcmp (name
, "movb") == 0)
3601 /* The existing operand extract code fell over if these additional modes
3602 were enabled in m68hc11-opc.c. So they are commented there and
3603 decoded here instead. */
3605 if (operands
[1].mode
& (M6812_OP_IDX
| M6812_OP_IDX_1
3606 | M6812_OP_IDX_2
| M6812_OP_D_IDX
| M6812_OP_D_IDX_2
| M6812_PRE_INC
3607 | M6812_PRE_DEC
| M6812_POST_INC
| M6812_POST_DEC
))
3609 /* first check if valid mode then start building it up */
3610 if (operands
[0].mode
& (M6811_OP_IMM8
| M6811_OP_IMM16
3611 | M6811_OP_IND16
| M6812_OP_IDX
| M6812_OP_IDX_1
3612 | M6812_OP_IDX_2
| M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
3615 if (operands
[1].mode
& (M6811_OP_IND16
))
3620 f
= m68hc11_new_insn (2);
3622 if (operands
[0].mode
& (M6811_OP_IMM8
| M6811_OP_IMM16
))
3624 number_to_chars_bigendian (f
, 0x1800 + movb
+ opr16a
, 2);
3625 build_indexed_byte (&operands
[1], operands
[1].mode
, 1);
3627 fixup8 (&operands
[0].exp
, M6811_OP_IMM8
,
3630 fixup16 (&operands
[0].exp
, M6811_OP_IMM16
,
3635 else if (operands
[0].mode
& M6811_OP_IND16
)
3637 number_to_chars_bigendian (f
, 0x1801 + movb
+ opr16a
, 2);
3638 build_indexed_byte (&operands
[1], operands
[1].mode
, 1);
3639 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, operands
[0].mode
);
3644 number_to_chars_bigendian (f
, 0x1802 + movb
+ opr16a
, 2);
3645 build_indexed_byte (&operands
[0], operands
[0].mode
, 1);
3646 build_indexed_byte (&operands
[1], operands
[1].mode
, 1);
3651 else if (operands
[1].mode
& M6811_OP_IND16
)
3653 /* First check if this is valid mode, then start building it up. */
3654 if (operands
[0].mode
& (M6811_OP_IMM8
| M6811_OP_IMM16
3655 | M6811_OP_IND16
| M6812_OP_IDX
| M6812_OP_IDX_1
3656 | M6812_OP_IDX_2
| M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
3659 if (operands
[1].mode
& (M6811_OP_IND16
))
3664 f
= m68hc11_new_insn (2);
3666 /* The first two cases here should actually be covered by the
3667 normal operand code. */
3668 if (operands
[0].mode
& (M6811_OP_IMM8
| M6811_OP_IMM16
))
3670 number_to_chars_bigendian (f
, 0x1800 + movb
+ opr16a
, 2);
3672 fixup8 (&operands
[0].exp
, M6811_OP_IMM8
, operands
[0].mode
);
3674 fixup16 (&operands
[0].exp
, M6811_OP_IMM16
, operands
[0].mode
);
3676 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, operands
[0].mode
);
3679 else if (operands
[0].mode
& M6811_OP_IND16
)
3681 number_to_chars_bigendian (f
, 0x1801 + movb
+ opr16a
, 2);
3682 build_indexed_byte (&operands
[1], operands
[1].mode
, 1);
3683 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, operands
[0].mode
);
3688 number_to_chars_bigendian (f
, 0x1802 + movb
+ opr16a
, 2);
3689 build_indexed_byte (&operands
[0], operands
[0].mode
, 1);
3690 fixup16 (&operands
[1].exp
, M6811_OP_IND16
, operands
[1].mode
);
3696 as_bad (_("Invalid operand for `%s'"), name
);
3702 as_bad (_("Invalid operand for `%s'"), name
);
3707 /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is
3708 relative and must be in the range -256..255 (9-bits). */
3709 if ((opcode
->format
& M6812_XBCC_MARKER
)
3710 && (opcode
->format
& M6811_OP_JUMP_REL
))
3711 build_dbranch_insn (opcode
, operands
, nb_operands
, branch_optimize
);
3713 /* Relative jumps instructions are taken care of separately. We have to make
3714 sure that the relative branch is within the range -128..127. If it's out
3715 of range, the instructions are changed into absolute instructions.
3716 This is not supported for the brset and brclr instructions. */
3717 else if ((opcode
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
3718 && !(opcode
->format
& M6811_OP_BITMASK
))
3719 build_jump_insn (opcode
, operands
, nb_operands
, branch_optimize
);
3721 build_insn (opcode
, operands
, nb_operands
);
3725 /* Pseudo op to control the ELF flags. */
3727 s_m68hc11_mode (int x ATTRIBUTE_UNUSED
)
3729 char *name
= input_line_pointer
, ch
;
3731 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3732 input_line_pointer
++;
3733 ch
= *input_line_pointer
;
3734 *input_line_pointer
= '\0';
3736 if (strcmp (name
, "mshort") == 0)
3738 elf_flags
&= ~E_M68HC11_I32
;
3740 else if (strcmp (name
, "mlong") == 0)
3742 elf_flags
|= E_M68HC11_I32
;
3744 else if (strcmp (name
, "mshort-double") == 0)
3746 elf_flags
&= ~E_M68HC11_F64
;
3748 else if (strcmp (name
, "mlong-double") == 0)
3750 elf_flags
|= E_M68HC11_F64
;
3754 as_warn (_("Invalid mode: %s\n"), name
);
3756 *input_line_pointer
= ch
;
3757 demand_empty_rest_of_line ();
3760 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions
3761 are using 'rtc' for returning. It is necessary to use 'call'
3762 to invoke them. This is also used by the debugger to correctly
3763 find the stack frame. */
3765 s_m68hc11_mark_symbol (int mark
)
3771 elf_symbol_type
*elfsym
;
3775 name
= input_line_pointer
;
3776 c
= get_symbol_end ();
3777 symbolP
= symbol_find_or_make (name
);
3778 *input_line_pointer
= c
;
3782 bfdsym
= symbol_get_bfdsym (symbolP
);
3783 elfsym
= elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
3785 gas_assert (elfsym
);
3787 /* Mark the symbol far (using rtc for function return). */
3788 elfsym
->internal_elf_sym
.st_other
|= mark
;
3792 input_line_pointer
++;
3796 if (*input_line_pointer
== '\n')
3802 demand_empty_rest_of_line ();
3806 s_m68hc11_relax (int ignore ATTRIBUTE_UNUSED
)
3812 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
3814 as_bad (_("bad .relax format"));
3815 ignore_rest_of_line ();
3819 fix_new_exp (frag_now
, frag_now_fix (), 0, &ex
, 1,
3820 BFD_RELOC_M68HC11_RL_GROUP
);
3822 demand_empty_rest_of_line ();
3826 /* Relocation, relaxation and frag conversions. */
3828 /* PC-relative offsets are relative to the start of the
3829 next instruction. That is, the address of the offset, plus its
3830 size, since the offset is always the last part of the insn. */
3832 md_pcrel_from (fixS
*fixP
)
3834 if (fixP
->fx_r_type
== BFD_RELOC_M68HC11_RL_JUMP
)
3837 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3840 /* If while processing a fixup, a reloc really needs to be created
3841 then it is done here. */
3843 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3847 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3848 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3849 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3850 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3851 if (fixp
->fx_r_type
== 0)
3852 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
3854 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3855 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
3857 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3858 _("Relocation %d is not supported by object file format."),
3859 (int) fixp
->fx_r_type
);
3863 /* Since we use Rel instead of Rela, encode the vtable entry to be
3864 used in the relocation's section offset. */
3865 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3866 reloc
->address
= fixp
->fx_offset
;
3872 /* We need a port-specific relaxation function to cope with sym2 - sym1
3873 relative expressions with both symbols in the same segment (but not
3874 necessarily in the same frag as this insn), for example:
3875 ldab sym2-(sym1-2),pc
3877 The offset can be 5, 9 or 16 bits long. */
3880 m68hc11_relax_frag (segT seg ATTRIBUTE_UNUSED
, fragS
*fragP
,
3881 long stretch ATTRIBUTE_UNUSED
)
3886 const relax_typeS
*this_type
;
3887 const relax_typeS
*start_type
;
3888 relax_substateT next_state
;
3889 relax_substateT this_state
;
3890 const relax_typeS
*table
= TC_GENERIC_RELAX_TABLE
;
3892 /* We only have to cope with frags as prepared by
3893 md_estimate_size_before_relax. The STATE_BITS16 case may geet here
3894 because of the different reasons that it's not relaxable. */
3895 switch (fragP
->fr_subtype
)
3897 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
):
3898 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
):
3899 /* When we get to this state, the frag won't grow any more. */
3902 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS5
):
3903 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS5
):
3904 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
):
3905 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
):
3906 if (fragP
->fr_symbol
== NULL
3907 || S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3908 as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"),
3909 __FUNCTION__
, (long) fragP
->fr_symbol
);
3910 symbolP
= fragP
->fr_symbol
;
3911 if (symbol_resolved_p (symbolP
))
3912 as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
3914 aim
= S_GET_VALUE (symbolP
);
3918 as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"),
3919 __FUNCTION__
, fragP
->fr_subtype
);
3922 /* The rest is stolen from relax_frag. There's no obvious way to
3923 share the code, but fortunately no requirement to keep in sync as
3924 long as fragP->fr_symbol does not have its segment changed. */
3926 this_state
= fragP
->fr_subtype
;
3927 start_type
= this_type
= table
+ this_state
;
3931 /* Look backwards. */
3932 for (next_state
= this_type
->rlx_more
; next_state
;)
3933 if (aim
>= this_type
->rlx_backward
)
3937 /* Grow to next state. */
3938 this_state
= next_state
;
3939 this_type
= table
+ this_state
;
3940 next_state
= this_type
->rlx_more
;
3945 /* Look forwards. */
3946 for (next_state
= this_type
->rlx_more
; next_state
;)
3947 if (aim
<= this_type
->rlx_forward
)
3951 /* Grow to next state. */
3952 this_state
= next_state
;
3953 this_type
= table
+ this_state
;
3954 next_state
= this_type
->rlx_more
;
3958 growth
= this_type
->rlx_length
- start_type
->rlx_length
;
3960 fragP
->fr_subtype
= this_state
;
3965 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec ATTRIBUTE_UNUSED
,
3971 char *buffer_address
= fragP
->fr_literal
;
3973 /* Address in object code of the displacement. */
3974 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
3976 buffer_address
+= fragP
->fr_fix
;
3978 /* The displacement of the address, from current location. */
3979 value
= S_GET_VALUE (fragP
->fr_symbol
);
3980 disp
= (value
+ fragP
->fr_offset
) - object_address
;
3982 switch (fragP
->fr_subtype
)
3984 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_BYTE
):
3985 fragP
->fr_opcode
[1] = disp
;
3988 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_WORD
):
3989 /* This relax is only for bsr and bra. */
3990 gas_assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
3991 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
3992 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
3994 fragP
->fr_opcode
[0] = convert_branch (fragP
->fr_opcode
[0]);
3996 fix_new (fragP
, fragP
->fr_fix
- 1, 2,
3997 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
4001 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_BYTE
):
4002 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_BYTE
):
4003 fragP
->fr_opcode
[1] = disp
;
4006 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_WORD
):
4007 /* Invert branch. */
4008 fragP
->fr_opcode
[0] ^= 1;
4009 fragP
->fr_opcode
[1] = 3; /* Branch offset. */
4010 buffer_address
[0] = M6811_JMP
;
4011 fix_new (fragP
, fragP
->fr_fix
+ 1, 2,
4012 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
4016 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_WORD
):
4017 /* Translate branch into a long branch. */
4018 fragP
->fr_opcode
[1] = fragP
->fr_opcode
[0];
4019 fragP
->fr_opcode
[0] = M6811_OPCODE_PAGE2
;
4021 fixp
= fix_new (fragP
, fragP
->fr_fix
, 2,
4022 fragP
->fr_symbol
, fragP
->fr_offset
, 1,
4023 BFD_RELOC_16_PCREL
);
4024 fixp
->fx_pcrel_adjust
= 2;
4028 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS5
):
4029 if (fragP
->fr_symbol
!= 0
4030 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
4034 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS5
):
4035 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 6;
4036 fragP
->fr_opcode
[0] |= value
& 0x1f;
4039 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
):
4040 /* For a PC-relative offset, use the displacement with a -1 correction
4041 to take into account the additional byte of the insn. */
4042 if (fragP
->fr_symbol
!= 0
4043 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
4047 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
):
4048 fragP
->fr_opcode
[0] = (fragP
->fr_opcode
[0] << 3);
4049 fragP
->fr_opcode
[0] |= 0xE0;
4050 fragP
->fr_opcode
[0] |= (value
>> 8) & 1;
4051 fragP
->fr_opcode
[1] = value
;
4055 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
):
4056 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
):
4057 fragP
->fr_opcode
[0] = (fragP
->fr_opcode
[0] << 3);
4058 fragP
->fr_opcode
[0] |= 0xe2;
4059 if ((fragP
->fr_opcode
[0] & 0x0ff) == 0x0fa
4060 && fragP
->fr_symbol
!= 0
4061 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
4063 fixp
= fix_new (fragP
, fragP
->fr_fix
, 2,
4064 fragP
->fr_symbol
, fragP
->fr_offset
,
4065 1, BFD_RELOC_16_PCREL
);
4069 fix_new (fragP
, fragP
->fr_fix
, 2,
4070 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
4075 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_BYTE
):
4077 fragP
->fr_opcode
[0] |= 0x10;
4079 fragP
->fr_opcode
[1] = disp
& 0x0FF;
4082 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_WORD
):
4083 /* Invert branch. */
4084 fragP
->fr_opcode
[0] ^= 0x20;
4085 fragP
->fr_opcode
[1] = 3; /* Branch offset. */
4086 buffer_address
[0] = M6812_JMP
;
4087 fix_new (fragP
, fragP
->fr_fix
+ 1, 2,
4088 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
4097 /* On an ELF system, we can't relax a weak symbol. The weak symbol
4098 can be overridden at final link time by a non weak symbol. We can
4099 relax externally visible symbol because there is no shared library
4100 and such symbol can't be overridden (unless they are weak). */
4102 relaxable_symbol (symbolS
*symbol
)
4104 return ! S_IS_WEAK (symbol
);
4107 /* Force truly undefined symbols to their maximum size, and generally set up
4108 the frag list to be relaxed. */
4110 md_estimate_size_before_relax (fragS
*fragP
, asection
*segment
)
4112 if (RELAX_LENGTH (fragP
->fr_subtype
) == STATE_UNDF
)
4114 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4115 || !relaxable_symbol (fragP
->fr_symbol
)
4116 || (segment
!= absolute_section
4117 && RELAX_STATE (fragP
->fr_subtype
) == STATE_INDEXED_OFFSET
))
4119 /* Non-relaxable cases. */
4121 char *buffer_address
;
4123 old_fr_fix
= fragP
->fr_fix
;
4124 buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
4126 switch (RELAX_STATE (fragP
->fr_subtype
))
4128 case STATE_PC_RELATIVE
:
4130 /* This relax is only for bsr and bra. */
4131 gas_assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
4132 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
4133 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
4135 if (flag_fixed_branches
)
4136 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4137 _("bra or bsr with undefined symbol."));
4139 /* The symbol is undefined or in a separate section.
4140 Turn bra into a jmp and bsr into a jsr. The insn
4141 becomes 3 bytes long (instead of 2). A fixup is
4142 necessary for the unresolved symbol address. */
4143 fragP
->fr_opcode
[0] = convert_branch (fragP
->fr_opcode
[0]);
4145 fix_new (fragP
, fragP
->fr_fix
- 1, 2, fragP
->fr_symbol
,
4146 fragP
->fr_offset
, 0, BFD_RELOC_16
);
4150 case STATE_CONDITIONAL_BRANCH
:
4151 gas_assert (current_architecture
& cpu6811
);
4153 fragP
->fr_opcode
[0] ^= 1; /* Reverse sense of branch. */
4154 fragP
->fr_opcode
[1] = 3; /* Skip next jmp insn (3 bytes). */
4156 /* Don't use fr_opcode[2] because this may be
4157 in a different frag. */
4158 buffer_address
[0] = M6811_JMP
;
4161 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4162 fragP
->fr_offset
, 0, BFD_RELOC_16
);
4166 case STATE_INDEXED_OFFSET
:
4167 gas_assert (current_architecture
& cpu6812
);
4169 if (fragP
->fr_symbol
4170 && S_GET_SEGMENT (fragP
->fr_symbol
) == absolute_section
)
4172 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_OFFSET
,
4174 /* Return the size of the variable part of the frag. */
4175 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4179 /* Switch the indexed operation to 16-bit mode. */
4180 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 3;
4181 fragP
->fr_opcode
[0] |= 0xe2;
4182 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4183 fragP
->fr_offset
, 0, BFD_RELOC_16
);
4188 case STATE_INDEXED_PCREL
:
4189 gas_assert (current_architecture
& cpu6812
);
4191 if (fragP
->fr_symbol
4192 && S_GET_SEGMENT (fragP
->fr_symbol
) == absolute_section
)
4194 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_PCREL
,
4196 /* Return the size of the variable part of the frag. */
4197 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4201 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 3;
4202 fragP
->fr_opcode
[0] |= 0xe2;
4203 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4204 fragP
->fr_offset
, 1, BFD_RELOC_16_PCREL
);
4209 case STATE_XBCC_BRANCH
:
4210 gas_assert (current_architecture
& cpu6812
);
4212 fragP
->fr_opcode
[0] ^= 0x20; /* Reverse sense of branch. */
4213 fragP
->fr_opcode
[1] = 3; /* Skip next jmp insn (3 bytes). */
4215 /* Don't use fr_opcode[2] because this may be
4216 in a different frag. */
4217 buffer_address
[0] = M6812_JMP
;
4220 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4221 fragP
->fr_offset
, 0, BFD_RELOC_16
);
4225 case STATE_CONDITIONAL_BRANCH_6812
:
4226 gas_assert (current_architecture
& cpu6812
);
4228 /* Translate into a lbcc branch. */
4229 fragP
->fr_opcode
[1] = fragP
->fr_opcode
[0];
4230 fragP
->fr_opcode
[0] = M6811_OPCODE_PAGE2
;
4232 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4233 fragP
->fr_offset
, 1, BFD_RELOC_16_PCREL
);
4238 as_fatal (_("Subtype %d is not recognized."), fragP
->fr_subtype
);
4242 /* Return the growth in the fixed part of the frag. */
4243 return fragP
->fr_fix
- old_fr_fix
;
4246 /* Relaxable cases. */
4247 switch (RELAX_STATE (fragP
->fr_subtype
))
4249 case STATE_PC_RELATIVE
:
4250 /* This relax is only for bsr and bra. */
4251 gas_assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
4252 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
4253 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
4255 fragP
->fr_subtype
= ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_BYTE
);
4258 case STATE_CONDITIONAL_BRANCH
:
4259 gas_assert (current_architecture
& cpu6811
);
4261 fragP
->fr_subtype
= ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
,
4265 case STATE_INDEXED_OFFSET
:
4266 gas_assert (current_architecture
& cpu6812
);
4268 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_OFFSET
,
4272 case STATE_INDEXED_PCREL
:
4273 gas_assert (current_architecture
& cpu6812
);
4275 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_PCREL
,
4279 case STATE_XBCC_BRANCH
:
4280 gas_assert (current_architecture
& cpu6812
);
4282 fragP
->fr_subtype
= ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_BYTE
);
4285 case STATE_CONDITIONAL_BRANCH_6812
:
4286 gas_assert (current_architecture
& cpu6812
);
4288 fragP
->fr_subtype
= ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
,
4294 if (fragP
->fr_subtype
>= sizeof (md_relax_table
) / sizeof (md_relax_table
[0]))
4295 as_fatal (_("Subtype %d is not recognized."), fragP
->fr_subtype
);
4297 /* Return the size of the variable part of the frag. */
4298 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4301 /* See whether we need to force a relocation into the output file. */
4303 tc_m68hc11_force_relocation (fixS
*fixP
)
4305 if (fixP
->fx_r_type
== BFD_RELOC_M68HC11_RL_GROUP
)
4308 return generic_force_reloc (fixP
);
4311 /* Here we decide which fixups can be adjusted to make them relative
4312 to the beginning of the section instead of the symbol. Basically
4313 we need to make sure that the linker relaxation is done
4314 correctly, so in some cases we force the original symbol to be
4317 tc_m68hc11_fix_adjustable (fixS
*fixP
)
4319 switch (fixP
->fx_r_type
)
4321 /* For the linker relaxation to work correctly, these relocs
4322 need to be on the symbol itself. */
4324 case BFD_RELOC_M68HC11_RL_JUMP
:
4325 case BFD_RELOC_M68HC11_RL_GROUP
:
4326 case BFD_RELOC_VTABLE_INHERIT
:
4327 case BFD_RELOC_VTABLE_ENTRY
:
4330 /* The memory bank addressing translation also needs the original
4332 case BFD_RELOC_M68HC11_LO16
:
4333 case BFD_RELOC_M68HC11_PAGE
:
4334 case BFD_RELOC_M68HC11_24
:
4343 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4346 long value
= * valP
;
4348 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
4351 /* We don't actually support subtracting a symbol. */
4352 if (fixP
->fx_subsy
!= (symbolS
*) NULL
)
4353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("Expression too complex."));
4355 /* Patch the instruction with the resolved operand. Elf relocation
4356 info will also be generated to take care of linker/loader fixups.
4357 The 68HC11 addresses only 64Kb, we are only concerned by 8 and 16-bit
4358 relocs. BFD_RELOC_8 is basically used for .page0 access (the linker
4359 will warn for overflows). BFD_RELOC_8_PCREL should not be generated
4360 because it's either resolved or turned out into non-relative insns (see
4361 relax table, bcc, bra, bsr transformations)
4363 The BFD_RELOC_32 is necessary for the support of --gstabs. */
4364 where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4366 switch (fixP
->fx_r_type
)
4369 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
4373 case BFD_RELOC_M68HC11_24
:
4374 bfd_putb16 ((bfd_vma
) (value
& 0x0ffff), (unsigned char *) where
);
4375 ((bfd_byte
*) where
)[2] = ((value
>> 16) & 0x0ff);
4379 case BFD_RELOC_16_PCREL
:
4380 case BFD_RELOC_M68HC11_LO16
:
4381 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
4382 if (value
< -65537 || value
> 65535)
4383 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4384 _("Value out of 16-bit range."));
4387 case BFD_RELOC_M68HC11_HI8
:
4388 /* Caution, %hi(<symbol>+%ld) will generate incorrect code if %lo
4390 case BFD_RELOC_M68HC12_HI8XG
:
4394 case BFD_RELOC_M68HC12_LO8XG
:
4395 case BFD_RELOC_M68HC11_LO8
:
4397 case BFD_RELOC_M68HC11_PAGE
:
4398 ((bfd_byte
*) where
)[0] = (bfd_byte
) value
;
4401 case BFD_RELOC_8_PCREL
:
4402 ((bfd_byte
*) where
)[0] = (bfd_byte
) value
;
4404 if (value
< -128 || value
> 127)
4405 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4406 _("Value %ld too large for 8-bit PC-relative branch."),
4410 /* These next two are for XGATE. */
4411 case BFD_RELOC_M68HC12_9_PCREL
:
4412 ((bfd_byte
*) where
)[0] |= (bfd_byte
) ((value
>>9) & 0x01);
4413 ((bfd_byte
*) where
)[1] = (bfd_byte
) ((value
>>1) & 0xff);
4414 if (value
< -512 || value
> 511)
4415 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4416 _("Value %ld too large for 9-bit PC-relative branch."),
4420 case BFD_RELOC_M68HC12_10_PCREL
:
4421 ((bfd_byte
*) where
)[0] |= (bfd_byte
) ((value
>>9) & 0x03);
4422 ((bfd_byte
*) where
)[1] = (bfd_byte
) ((value
>>1) & 0xff);
4423 if (value
< -1024 || value
> 1023)
4424 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4425 _("Value %ld too large for 10-bit PC-relative branch."),
4430 case BFD_RELOC_M68HC11_3B
:
4431 if (value
<= 0 || value
> 8)
4432 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4433 _("Auto increment/decrement offset '%ld' is out of range."),
4440 where
[0] = where
[0] | (value
& 0x07);
4443 case BFD_RELOC_M68HC12_5B
:
4444 if (value
< -16 || value
> 15)
4445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4446 _("Offset out of 5-bit range for movw/movb insn: %ld"),
4451 where
[0] |= (0x10 | (16 + value
));
4454 case BFD_RELOC_M68HC12_9B
:
4455 if (value
< -256 || value
> 255)
4456 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4457 _("Offset out of 9-bit range for movw/movb insn: %ld"),
4459 /* sign bit already in xb postbyte */
4463 where
[1] = (256 + value
);
4466 case BFD_RELOC_M68HC12_16B
:
4467 if (value
< -32768 || value
> 32767)
4468 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4469 _("Offset out of 16-bit range for movw/movb insn: %ld"),
4474 where
[1] = (value
>> 8);
4475 where
[2] = (value
& 0xff);
4478 case BFD_RELOC_M68HC11_RL_JUMP
:
4479 case BFD_RELOC_M68HC11_RL_GROUP
:
4480 case BFD_RELOC_VTABLE_INHERIT
:
4481 case BFD_RELOC_VTABLE_ENTRY
:
4486 as_fatal (_("Line %d: unknown relocation type: 0x%x."),
4487 fixP
->fx_line
, fixP
->fx_r_type
);
4491 /* Set the ELF specific flags. */
4493 m68hc11_elf_final_processing (void)
4495 if (current_architecture
& cpu6812s
)
4496 elf_flags
|= EF_M68HCS12_MACH
;
4497 elf_elfheader (stdoutput
)->e_flags
&= ~EF_M68HC11_ABI
;
4498 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
4501 /* Process directives specified via pseudo ops */
4503 s_m68hc11_parse_pseudo_instruction (int pseudo_insn
)
4505 switch (pseudo_insn
)
4507 case E_M68HC11_NO_BANK_WARNING
:
4508 elf_flags
|= E_M68HC11_NO_BANK_WARNING
;
4511 as_bad (_("Invalid directive"));