1 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12.
2 Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@nerim.fr)
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 #include "safe-ctype.h"
25 #include "opcode/m68hc11.h"
26 #include "dwarf2dbg.h"
27 #include "elf/m68hc11.h"
29 const char comment_chars
[] = ";!";
30 const char line_comment_chars
[] = "#*";
31 const char line_separator_chars
[] = "";
33 const char EXP_CHARS
[] = "eE";
34 const char FLT_CHARS
[] = "dD";
36 #define STATE_CONDITIONAL_BRANCH (1)
37 #define STATE_PC_RELATIVE (2)
38 #define STATE_INDEXED_OFFSET (3)
39 #define STATE_INDEXED_PCREL (4)
40 #define STATE_XBCC_BRANCH (5)
41 #define STATE_CONDITIONAL_BRANCH_6812 (6)
43 #define STATE_BYTE (0)
44 #define STATE_BITS5 (0)
45 #define STATE_WORD (1)
46 #define STATE_BITS9 (1)
47 #define STATE_LONG (2)
48 #define STATE_BITS16 (2)
49 #define STATE_UNDF (3) /* Symbol undefined in pass1 */
51 /* This macro has no side-effects. */
52 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
53 #define RELAX_STATE(s) ((s) >> 2)
54 #define RELAX_LENGTH(s) ((s) & 3)
56 #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF))
58 /* This table describes how you change sizes for the various types of variable
59 size expressions. This version only supports two kinds. */
62 How far Forward this mode will reach.
63 How far Backward this mode will reach.
64 How many bytes this mode will add to the size of the frag.
65 Which mode to go to if the offset won't fit in this one. */
67 relax_typeS md_relax_table
[] = {
68 {1, 1, 0, 0}, /* First entries aren't used. */
69 {1, 1, 0, 0}, /* For no good reason except. */
70 {1, 1, 0, 0}, /* that the VAX doesn't either. */
74 These insns are translated into b!cc +3 jmp L. */
75 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_WORD
)},
80 /* Relax for bsr <L> and bra <L>.
81 These insns are translated into jsr and jmp. */
82 {(127), (-128), 0, ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_WORD
)},
87 /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */
88 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
)},
89 {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
)},
93 /* Relax for PC relative offset: 5-bits, 9-bits, 16-bits.
94 For the 9-bit case, there will be a -1 correction to take into
95 account the new byte that's why the range is -255..256. */
96 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
)},
97 {(256), (-255), 1, ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
)},
101 /* Relax for dbeq/ibeq/tbeq r,<L>:
102 These insns are translated into db!cc +3 jmp L. */
103 {(255), (-256), 0, ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_WORD
)},
108 /* Relax for bcc <L> on 68HC12.
109 These insns are translated into lbcc <L>. */
110 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_WORD
)},
117 /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */
118 typedef enum register_id
{
130 typedef struct operand
{
137 struct m68hc11_opcode_def
{
143 struct m68hc11_opcode
*opcode
;
146 static struct m68hc11_opcode_def
*m68hc11_opcode_defs
= 0;
147 static int m68hc11_nb_opcode_defs
= 0;
149 typedef struct alias
{
154 static alias alias_opcodes
[] = {
161 /* Local functions. */
162 static register_id reg_name_search
PARAMS ((char *));
163 static register_id register_name
PARAMS ((void));
164 static int cmp_opcode
PARAMS ((struct m68hc11_opcode
*,
165 struct m68hc11_opcode
*));
166 static char *print_opcode_format
PARAMS ((struct m68hc11_opcode
*, int));
167 static char *skip_whites
PARAMS ((char *));
168 static int check_range
PARAMS ((long, int));
169 static void print_opcode_list
PARAMS ((void));
170 static void get_default_target
PARAMS ((void));
171 static void print_insn_format
PARAMS ((char *));
172 static int get_operand
PARAMS ((operand
*, int, long));
173 static void fixup8
PARAMS ((expressionS
*, int, int));
174 static void fixup16
PARAMS ((expressionS
*, int, int));
175 static void fixup24
PARAMS ((expressionS
*, int, int));
176 static unsigned char convert_branch
PARAMS ((unsigned char));
177 static char *m68hc11_new_insn
PARAMS ((int));
178 static void build_dbranch_insn
PARAMS ((struct m68hc11_opcode
*,
179 operand
*, int, int));
180 static int build_indexed_byte
PARAMS ((operand
*, int, int));
181 static int build_reg_mode
PARAMS ((operand
*, int));
183 static struct m68hc11_opcode
*find
184 PARAMS ((struct m68hc11_opcode_def
*, operand
*, int));
185 static struct m68hc11_opcode
*find_opcode
186 PARAMS ((struct m68hc11_opcode_def
*, operand
*, int *));
187 static void build_jump_insn
188 PARAMS ((struct m68hc11_opcode
*, operand
*, int, int));
189 static void build_insn
190 PARAMS ((struct m68hc11_opcode
*, operand
*, int));
191 static int relaxable_symbol
PARAMS ((symbolS
*));
193 /* Pseudo op to indicate a relax group. */
194 static void s_m68hc11_relax
PARAMS((int));
196 /* Pseudo op to control the ELF flags. */
197 static void s_m68hc11_mode
PARAMS ((int));
199 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions
200 are using 'rtc' for returning. It is necessary to use 'call'
201 to invoke them. This is also used by the debugger to correctly
202 find the stack frame. */
203 static void s_m68hc11_mark_symbol
PARAMS ((int));
205 /* Controls whether relative branches can be turned into long branches.
206 When the relative offset is too large, the insn are changed:
214 Setting the flag forbidds this. */
215 static short flag_fixed_branchs
= 0;
217 /* Force to use long jumps (absolute) instead of relative branches. */
218 static short flag_force_long_jumps
= 0;
220 /* Change the direct addressing mode into an absolute addressing mode
221 when the insn does not support direct addressing.
222 For example, "clr *ZD0" is normally not possible and is changed
224 static short flag_strict_direct_addressing
= 1;
226 /* When an opcode has invalid operand, print out the syntax of the opcode
228 static short flag_print_insn_syntax
= 0;
230 /* Dumps the list of instructions with syntax and then exit:
231 1 -> Only dumps the list (sorted by name)
232 2 -> Generate an example (or test) that can be compiled. */
233 static short flag_print_opcodes
= 0;
235 /* Opcode hash table. */
236 static struct hash_control
*m68hc11_hash
;
238 /* Current cpu (either cpu6811 or cpu6812). This is determined automagically
239 by 'get_default_target' by looking at default BFD vector. This is overriden
240 with the -m<cpu> option. */
241 static int current_architecture
= 0;
243 /* Default cpu determined by 'get_default_target'. */
244 static const char *default_cpu
;
246 /* Number of opcodes in the sorted table (filtered by current cpu). */
247 static int num_opcodes
;
249 /* The opcodes sorted by name and filtered by current cpu. */
250 static struct m68hc11_opcode
*m68hc11_sorted_opcodes
;
252 /* ELF flags to set in the output file header. */
253 static int elf_flags
= E_M68HC11_F64
;
255 /* These are the machine dependent pseudo-ops. These are included so
256 the assembler can work on the output from the SUN C compiler, which
259 /* This table describes all the machine specific pseudo-ops the assembler
260 has to support. The fields are:
261 pseudo-op name without dot
262 function to call to execute this pseudo-op
263 Integer arg to pass to the function. */
264 const pseudo_typeS md_pseudo_table
[] = {
265 /* The following pseudo-ops are supported for MRI compatibility. */
268 {"fcc", stringer
, 1},
271 /* Dwarf2 support for Gcc. */
272 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
273 {"loc", dwarf2_directive_loc
, 0},
276 {"xrefb", s_ignore
, 0}, /* Same as xref */
278 /* Gcc driven relaxation. */
279 {"relax", s_m68hc11_relax
, 0},
281 /* .mode instruction (ala SH). */
282 {"mode", s_m68hc11_mode
, 0},
284 /* .far instruction. */
285 {"far", s_m68hc11_mark_symbol
, STO_M68HC12_FAR
},
287 /* .interrupt instruction. */
288 {"interrupt", s_m68hc11_mark_symbol
, STO_M68HC12_INTERRUPT
},
293 /* Options and initialization. */
295 const char *md_shortopts
= "Sm:";
297 struct option md_longopts
[] = {
298 #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
299 {"force-long-branchs", no_argument
, NULL
, OPTION_FORCE_LONG_BRANCH
},
301 #define OPTION_SHORT_BRANCHS (OPTION_MD_BASE + 1)
302 {"short-branchs", no_argument
, NULL
, OPTION_SHORT_BRANCHS
},
304 #define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2)
305 {"strict-direct-mode", no_argument
, NULL
, OPTION_STRICT_DIRECT_MODE
},
307 #define OPTION_PRINT_INSN_SYNTAX (OPTION_MD_BASE + 3)
308 {"print-insn-syntax", no_argument
, NULL
, OPTION_PRINT_INSN_SYNTAX
},
310 #define OPTION_PRINT_OPCODES (OPTION_MD_BASE + 4)
311 {"print-opcodes", no_argument
, NULL
, OPTION_PRINT_OPCODES
},
313 #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5)
314 {"generate-example", no_argument
, NULL
, OPTION_GENERATE_EXAMPLE
},
316 #define OPTION_MSHORT (OPTION_MD_BASE + 6)
317 {"mshort", no_argument
, NULL
, OPTION_MSHORT
},
319 #define OPTION_MLONG (OPTION_MD_BASE + 7)
320 {"mlong", no_argument
, NULL
, OPTION_MLONG
},
322 #define OPTION_MSHORT_DOUBLE (OPTION_MD_BASE + 8)
323 {"mshort-double", no_argument
, NULL
, OPTION_MSHORT_DOUBLE
},
325 #define OPTION_MLONG_DOUBLE (OPTION_MD_BASE + 9)
326 {"mlong-double", no_argument
, NULL
, OPTION_MLONG_DOUBLE
},
328 {NULL
, no_argument
, NULL
, 0}
330 size_t md_longopts_size
= sizeof (md_longopts
);
332 /* Get the target cpu for the assembler. This is based on the configure
333 options and on the -m68hc11/-m68hc12 option. If no option is specified,
334 we must get the default. */
336 m68hc11_arch_format ()
338 get_default_target ();
339 if (current_architecture
& cpu6811
)
340 return "elf32-m68hc11";
342 return "elf32-m68hc12";
345 enum bfd_architecture
348 get_default_target ();
349 if (current_architecture
& cpu6811
)
350 return bfd_arch_m68hc11
;
352 return bfd_arch_m68hc12
;
361 /* Listing header selected according to cpu. */
363 m68hc11_listing_header ()
365 if (current_architecture
& cpu6811
)
366 return "M68HC11 GAS ";
368 return "M68HC12 GAS ";
372 md_show_usage (stream
)
375 get_default_target ();
376 fprintf (stream
, _("\
377 Motorola 68HC11/68HC12/68HCS12 options:\n\
378 -m68hc11 | -m68hc12 |\n\
379 -m68hcs12 specify the processor [default %s]\n\
380 -mshort use 16-bit int ABI (default)\n\
381 -mlong use 32-bit int ABI\n\
382 -mshort-double use 32-bit double ABI\n\
383 -mlong-double use 64-bit double ABI (default)\n\
384 --force-long-branchs always turn relative branchs into absolute ones\n\
385 -S,--short-branchs do not turn relative branchs into absolute ones\n\
386 when the offset is out of range\n\
387 --strict-direct-mode do not turn the direct mode into extended mode\n\
388 when the instruction does not support direct mode\n\
389 --print-insn-syntax print the syntax of instruction in case of error\n\
390 --print-opcodes print the list of instructions with syntax\n\
391 --generate-example generate an example of each instruction\n\
392 (used for testing)\n"), default_cpu
);
396 /* Try to identify the default target based on the BFD library. */
398 get_default_target ()
400 const bfd_target
*target
;
403 if (current_architecture
!= 0)
406 default_cpu
= "unknown";
407 target
= bfd_find_target (0, &abfd
);
408 if (target
&& target
->name
)
410 if (strcmp (target
->name
, "elf32-m68hc12") == 0)
412 current_architecture
= cpu6812
;
413 default_cpu
= "m68hc12";
415 else if (strcmp (target
->name
, "elf32-m68hc11") == 0)
417 current_architecture
= cpu6811
;
418 default_cpu
= "m68hc11";
422 as_bad (_("Default target `%s' is not supported."), target
->name
);
428 m68hc11_print_statistics (file
)
432 struct m68hc11_opcode_def
*opc
;
434 hash_print_statistics (file
, "opcode table", m68hc11_hash
);
436 opc
= m68hc11_opcode_defs
;
437 if (opc
== 0 || m68hc11_nb_opcode_defs
== 0)
440 /* Dump the opcode statistics table. */
441 fprintf (file
, _("Name # Modes Min ops Max ops Modes mask # Used\n"));
442 for (i
= 0; i
< m68hc11_nb_opcode_defs
; i
++, opc
++)
444 fprintf (file
, "%-7.7s %5d %7d %7d 0x%08lx %7d\n",
447 opc
->min_operands
, opc
->max_operands
, opc
->format
, opc
->used
);
452 md_parse_option (c
, arg
)
456 get_default_target ();
459 /* -S means keep external to 2 bit offset rather than 16 bit one. */
460 case OPTION_SHORT_BRANCHS
:
462 flag_fixed_branchs
= 1;
465 case OPTION_FORCE_LONG_BRANCH
:
466 flag_force_long_jumps
= 1;
469 case OPTION_PRINT_INSN_SYNTAX
:
470 flag_print_insn_syntax
= 1;
473 case OPTION_PRINT_OPCODES
:
474 flag_print_opcodes
= 1;
477 case OPTION_STRICT_DIRECT_MODE
:
478 flag_strict_direct_addressing
= 0;
481 case OPTION_GENERATE_EXAMPLE
:
482 flag_print_opcodes
= 2;
486 elf_flags
&= ~E_M68HC11_I32
;
490 elf_flags
|= E_M68HC11_I32
;
493 case OPTION_MSHORT_DOUBLE
:
494 elf_flags
&= ~E_M68HC11_F64
;
497 case OPTION_MLONG_DOUBLE
:
498 elf_flags
|= E_M68HC11_F64
;
502 if (strcasecmp (arg
, "68hc11") == 0)
503 current_architecture
= cpu6811
;
504 else if (strcasecmp (arg
, "68hc12") == 0)
505 current_architecture
= cpu6812
;
506 else if (strcasecmp (arg
, "68hcs12") == 0)
507 current_architecture
= cpu6812
| cpu6812s
;
509 as_bad (_("Option `%s' is not recognized."), arg
);
520 md_undefined_symbol (name
)
521 char *name ATTRIBUTE_UNUSED
;
526 /* Equal to MAX_PRECISION in atof-ieee.c. */
527 #define MAX_LITTLENUMS 6
529 /* Turn a string in input_line_pointer into a floating point constant
530 of type TYPE, and store the appropriate bytes in *LITP. The number
531 of LITTLENUMS emitted is stored in *SIZEP. An error message is
532 returned, or NULL on OK. */
534 md_atof (type
, litP
, sizeP
)
540 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
541 LITTLENUM_TYPE
*wordP
;
572 return _("Bad call to MD_ATOF()");
574 t
= atof_ieee (input_line_pointer
, type
, words
);
576 input_line_pointer
= t
;
578 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
579 for (wordP
= words
; prec
--;)
581 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
582 litP
+= sizeof (LITTLENUM_TYPE
);
588 md_section_align (seg
, addr
)
592 int align
= bfd_get_section_alignment (stdoutput
, seg
);
593 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
597 cmp_opcode (op1
, op2
)
598 struct m68hc11_opcode
*op1
;
599 struct m68hc11_opcode
*op2
;
601 return strcmp (op1
->name
, op2
->name
);
604 #define IS_CALL_SYMBOL(MODE) \
605 (((MODE) & (M6812_OP_PAGE|M6811_OP_IND16)) \
606 == ((M6812_OP_PAGE|M6811_OP_IND16)))
608 /* Initialize the assembler. Create the opcode hash table
609 (sorted on the names) with the M6811 opcode table
610 (from opcode library). */
614 char *prev_name
= "";
615 struct m68hc11_opcode
*opcodes
;
616 struct m68hc11_opcode_def
*opc
= 0;
619 get_default_target ();
621 m68hc11_hash
= hash_new ();
623 /* Get a writable copy of the opcode table and sort it on the names. */
624 opcodes
= (struct m68hc11_opcode
*) xmalloc (m68hc11_num_opcodes
*
627 m68hc11_sorted_opcodes
= opcodes
;
629 for (i
= 0; i
< m68hc11_num_opcodes
; i
++)
631 if (m68hc11_opcodes
[i
].arch
& current_architecture
)
633 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
634 if (opcodes
[num_opcodes
].name
[0] == 'b'
635 && opcodes
[num_opcodes
].format
& M6811_OP_JUMP_REL
636 && !(opcodes
[num_opcodes
].format
& M6811_OP_BITMASK
))
639 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
642 for (j
= 0; alias_opcodes
[j
].name
!= 0; j
++)
643 if (strcmp (m68hc11_opcodes
[i
].name
, alias_opcodes
[j
].name
) == 0)
645 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
646 opcodes
[num_opcodes
].name
= alias_opcodes
[j
].alias
;
652 qsort (opcodes
, num_opcodes
, sizeof (struct m68hc11_opcode
),
653 (int (*) PARAMS ((const PTR
, const PTR
))) cmp_opcode
);
655 opc
= (struct m68hc11_opcode_def
*)
656 xmalloc (num_opcodes
* sizeof (struct m68hc11_opcode_def
));
657 m68hc11_opcode_defs
= opc
--;
659 /* Insert unique names into hash table. The M6811 instruction set
660 has several identical opcode names that have different opcodes based
661 on the operands. This hash table then provides a quick index to
662 the first opcode with a particular name in the opcode table. */
663 for (i
= 0; i
< num_opcodes
; i
++, opcodes
++)
667 if (strcmp (prev_name
, opcodes
->name
))
669 prev_name
= (char *) opcodes
->name
;
673 opc
->min_operands
= 100;
674 opc
->max_operands
= 0;
676 opc
->opcode
= opcodes
;
678 hash_insert (m68hc11_hash
, opcodes
->name
, (char *) opc
);
681 opc
->format
|= opcodes
->format
;
683 /* See how many operands this opcode needs. */
685 if (opcodes
->format
& M6811_OP_MASK
)
687 if (opcodes
->format
& M6811_OP_BITMASK
)
689 if (opcodes
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
691 if (opcodes
->format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
693 /* Special case for call instruction. */
694 if ((opcodes
->format
& M6812_OP_PAGE
)
695 && !(opcodes
->format
& M6811_OP_IND16
))
698 if (expect
< opc
->min_operands
)
699 opc
->min_operands
= expect
;
700 if (IS_CALL_SYMBOL (opcodes
->format
))
702 if (expect
> opc
->max_operands
)
703 opc
->max_operands
= expect
;
706 m68hc11_nb_opcode_defs
= opc
- m68hc11_opcode_defs
;
708 if (flag_print_opcodes
)
710 print_opcode_list ();
716 m68hc11_init_after_args ()
722 /* Return a string that represents the operand format for the instruction.
723 When example is true, this generates an example of operand. This is used
724 to give an example and also to generate a test. */
726 print_opcode_format (opcode
, example
)
727 struct m68hc11_opcode
*opcode
;
730 static char buf
[128];
731 int format
= opcode
->format
;
736 if (format
& M6811_OP_IMM8
)
739 sprintf (p
, "#%d", rand () & 0x0FF);
741 strcpy (p
, _("#<imm8>"));
745 if (format
& M6811_OP_IMM16
)
748 sprintf (p
, "#%d", rand () & 0x0FFFF);
750 strcpy (p
, _("#<imm16>"));
754 if (format
& M6811_OP_IX
)
757 sprintf (p
, "%d,X", rand () & 0x0FF);
759 strcpy (p
, _("<imm8>,X"));
763 if (format
& M6811_OP_IY
)
766 sprintf (p
, "%d,X", rand () & 0x0FF);
768 strcpy (p
, _("<imm8>,X"));
772 if (format
& M6812_OP_IDX
)
775 sprintf (p
, "%d,X", rand () & 0x0FF);
781 if (format
& M6812_OP_PAGE
)
784 sprintf (p
, ", %d", rand () & 0x0FF);
786 strcpy (p
, ", <page>");
790 if (format
& M6811_OP_DIRECT
)
793 sprintf (p
, "*Z%d", rand () & 0x0FF);
795 strcpy (p
, _("*<abs8>"));
799 if (format
& M6811_OP_BITMASK
)
805 sprintf (p
, "#$%02x", rand () & 0x0FF);
807 strcpy (p
, _("#<mask>"));
810 if (format
& M6811_OP_JUMP_REL
)
814 if (format
& M6811_OP_IND16
)
817 sprintf (p
, _("symbol%d"), rand () & 0x0FF);
819 strcpy (p
, _("<abs>"));
824 if (format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
828 if (format
& M6811_OP_BITMASK
)
830 sprintf (p
, ".+%d", rand () & 0x7F);
834 sprintf (p
, "L%d", rand () & 0x0FF);
838 strcpy (p
, _("<label>"));
844 /* Prints the list of instructions with the possible operands. */
849 char *prev_name
= "";
850 struct m68hc11_opcode
*opcodes
;
851 int example
= flag_print_opcodes
== 2;
854 printf (_("# Example of `%s' instructions\n\t.sect .text\n_start:\n"),
857 opcodes
= m68hc11_sorted_opcodes
;
859 /* Walk the list sorted on names (by md_begin). We only report
860 one instruction per line, and we collect the different operand
862 for (i
= 0; i
< num_opcodes
; i
++, opcodes
++)
864 char *fmt
= print_opcode_format (opcodes
, example
);
868 printf ("L%d:\t", i
);
869 printf ("%s %s\n", opcodes
->name
, fmt
);
873 if (strcmp (prev_name
, opcodes
->name
))
878 printf ("%-5.5s ", opcodes
->name
);
879 prev_name
= (char *) opcodes
->name
;
882 printf (" [%s]", fmt
);
888 /* Print the instruction format. This operation is called when some
889 instruction is not correct. Instruction format is printed as an
892 print_insn_format (name
)
895 struct m68hc11_opcode_def
*opc
;
896 struct m68hc11_opcode
*opcode
;
899 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, name
);
902 as_bad (_("Instruction `%s' is not recognized."), name
);
905 opcode
= opc
->opcode
;
907 as_bad (_("Instruction formats for `%s':"), name
);
912 fmt
= print_opcode_format (opcode
, 0);
913 sprintf (buf
, "\t%-5.5s %s", opcode
->name
, fmt
);
918 while (strcmp (opcode
->name
, name
) == 0);
921 /* Analysis of 68HC11 and 68HC12 operands. */
923 /* reg_name_search() finds the register number given its name.
924 Returns the register number or REG_NONE on failure. */
926 reg_name_search (name
)
929 if (strcasecmp (name
, "x") == 0 || strcasecmp (name
, "ix") == 0)
931 if (strcasecmp (name
, "y") == 0 || strcasecmp (name
, "iy") == 0)
933 if (strcasecmp (name
, "a") == 0)
935 if (strcasecmp (name
, "b") == 0)
937 if (strcasecmp (name
, "d") == 0)
939 if (strcasecmp (name
, "sp") == 0)
941 if (strcasecmp (name
, "pc") == 0)
943 if (strcasecmp (name
, "ccr") == 0)
953 while (*p
== ' ' || *p
== '\t')
959 /* Check the string at input_line_pointer
960 to see if it is a valid register name. */
964 register_id reg_number
;
965 char c
, *p
= input_line_pointer
;
967 if (!is_name_beginner (*p
++))
970 while (is_part_of_name (*p
++))
977 /* Look to see if it's in the register table. */
978 reg_number
= reg_name_search (input_line_pointer
);
979 if (reg_number
!= REG_NONE
)
984 input_line_pointer
= p
;
993 /* Parse a string of operands and return an array of expressions.
995 Operand mode[0] mode[1] exp[0] exp[1]
996 #n M6811_OP_IMM16 - O_*
997 *<exp> M6811_OP_DIRECT - O_*
998 .{+-}<exp> M6811_OP_JUMP_REL - O_*
999 <exp> M6811_OP_IND16 - O_*
1000 ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register
1001 n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register
1002 n,+r M6812_PRE_INC " "
1003 n,r- M6812_POST_DEC " "
1004 n,r+ M6812_POST_INC " "
1005 A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register
1006 [D,r] M6811_OP_D_IDX M6812_OP_REG O_register O_register
1007 [n,r] M6811_OP_D_IDX_2 M6812_OP_REG O_constant O_register */
1009 get_operand (oper
, which
, opmode
)
1014 char *p
= input_line_pointer
;
1018 oper
->exp
.X_op
= O_absent
;
1019 oper
->reg1
= REG_NONE
;
1020 oper
->reg2
= REG_NONE
;
1021 mode
= M6811_OP_NONE
;
1023 p
= skip_whites (p
);
1025 if (*p
== 0 || *p
== '\n' || *p
== '\r')
1027 input_line_pointer
= p
;
1031 if (*p
== '*' && (opmode
& (M6811_OP_DIRECT
| M6811_OP_IND16
)))
1033 mode
= M6811_OP_DIRECT
;
1038 if (!(opmode
& (M6811_OP_IMM8
| M6811_OP_IMM16
| M6811_OP_BITMASK
)))
1040 as_bad (_("Immediate operand is not allowed for operand %d."),
1045 mode
= M6811_OP_IMM16
;
1047 if (strncmp (p
, "%hi", 3) == 0)
1050 mode
|= M6811_OP_HIGH_ADDR
;
1052 else if (strncmp (p
, "%lo", 3) == 0)
1055 mode
|= M6811_OP_LOW_ADDR
;
1058 else if (*p
== '.' && (p
[1] == '+' || p
[1] == '-'))
1061 mode
= M6811_OP_JUMP_REL
;
1065 if (current_architecture
& cpu6811
)
1066 as_bad (_("Indirect indexed addressing is not valid for 68HC11."));
1069 mode
= M6812_OP_D_IDX
;
1070 p
= skip_whites (p
);
1072 else if (*p
== ',') /* Special handling of ,x and ,y. */
1075 input_line_pointer
= p
;
1077 reg
= register_name ();
1078 if (reg
!= REG_NONE
)
1081 oper
->exp
.X_op
= O_constant
;
1082 oper
->exp
.X_add_number
= 0;
1083 oper
->mode
= M6812_OP_IDX
;
1086 as_bad (_("Spurious `,' or bad indirect register addressing mode."));
1089 input_line_pointer
= p
;
1091 if (mode
== M6811_OP_NONE
|| mode
== M6812_OP_D_IDX
)
1092 reg
= register_name ();
1096 if (reg
!= REG_NONE
)
1098 p
= skip_whites (input_line_pointer
);
1099 if (*p
== ']' && mode
== M6812_OP_D_IDX
)
1102 (_("Missing second register or offset for indexed-indirect mode."));
1107 oper
->mode
= mode
| M6812_OP_REG
;
1110 if (mode
== M6812_OP_D_IDX
)
1112 as_bad (_("Missing second register for indexed-indirect mode."));
1119 input_line_pointer
= p
;
1120 reg
= register_name ();
1121 if (reg
!= REG_NONE
)
1123 p
= skip_whites (input_line_pointer
);
1124 if (mode
== M6812_OP_D_IDX
)
1128 as_bad (_("Missing `]' to close indexed-indirect mode."));
1132 oper
->mode
= M6812_OP_D_IDX
;
1134 input_line_pointer
= p
;
1142 /* In MRI mode, isolate the operand because we can't distinguish
1143 operands from comments. */
1148 p
= skip_whites (p
);
1149 while (*p
&& *p
!= ' ' && *p
!= '\t')
1158 /* Parse as an expression. */
1159 expression (&oper
->exp
);
1168 expression (&oper
->exp
);
1171 if (oper
->exp
.X_op
== O_illegal
)
1173 as_bad (_("Illegal operand."));
1176 else if (oper
->exp
.X_op
== O_absent
)
1178 as_bad (_("Missing operand."));
1182 p
= input_line_pointer
;
1184 if (mode
== M6811_OP_NONE
|| mode
== M6811_OP_DIRECT
1185 || mode
== M6812_OP_D_IDX
)
1187 p
= skip_whites (input_line_pointer
);
1191 int possible_mode
= M6811_OP_NONE
;
1192 char *old_input_line
;
1197 /* 68HC12 pre increment or decrement. */
1198 if (mode
== M6811_OP_NONE
)
1202 possible_mode
= M6812_PRE_DEC
;
1207 possible_mode
= M6812_PRE_INC
;
1210 p
= skip_whites (p
);
1212 input_line_pointer
= p
;
1213 reg
= register_name ();
1215 /* Backtrack if we have a valid constant expression and
1216 it does not correspond to the offset of the 68HC12 indexed
1217 addressing mode (as in N,x). */
1218 if (reg
== REG_NONE
&& mode
== M6811_OP_NONE
1219 && possible_mode
!= M6811_OP_NONE
)
1221 oper
->mode
= M6811_OP_IND16
| M6811_OP_JUMP_REL
;
1222 input_line_pointer
= skip_whites (old_input_line
);
1226 if (possible_mode
!= M6811_OP_NONE
)
1227 mode
= possible_mode
;
1229 if ((current_architecture
& cpu6811
)
1230 && possible_mode
!= M6811_OP_NONE
)
1231 as_bad (_("Pre-increment mode is not valid for 68HC11"));
1233 if (which
== 0 && opmode
& M6812_OP_IDX_P2
1234 && reg
!= REG_X
&& reg
!= REG_Y
1235 && reg
!= REG_PC
&& reg
!= REG_SP
)
1238 input_line_pointer
= p
;
1241 if (reg
== REG_NONE
&& mode
!= M6811_OP_DIRECT
1242 && !(mode
== M6811_OP_NONE
&& opmode
& M6811_OP_IND16
))
1244 as_bad (_("Wrong register in register indirect mode."));
1247 if (mode
== M6812_OP_D_IDX
)
1249 p
= skip_whites (input_line_pointer
);
1252 as_bad (_("Missing `]' to close register indirect operand."));
1255 input_line_pointer
= p
;
1257 oper
->mode
= M6812_OP_D_IDX_2
;
1260 if (reg
!= REG_NONE
)
1263 if (mode
== M6811_OP_NONE
)
1265 p
= input_line_pointer
;
1268 mode
= M6812_POST_DEC
;
1270 if (current_architecture
& cpu6811
)
1272 (_("Post-decrement mode is not valid for 68HC11."));
1276 mode
= M6812_POST_INC
;
1278 if (current_architecture
& cpu6811
)
1280 (_("Post-increment mode is not valid for 68HC11."));
1283 mode
= M6812_OP_IDX
;
1285 input_line_pointer
= p
;
1288 mode
|= M6812_OP_IDX
;
1293 input_line_pointer
= old_input_line
;
1296 if (mode
== M6812_OP_D_IDX_2
)
1298 as_bad (_("Invalid indexed indirect mode."));
1303 /* If the mode is not known until now, this is either a label
1304 or an indirect address. */
1305 if (mode
== M6811_OP_NONE
)
1306 mode
= M6811_OP_IND16
| M6811_OP_JUMP_REL
;
1308 p
= input_line_pointer
;
1309 while (*p
== ' ' || *p
== '\t')
1311 input_line_pointer
= p
;
1317 #define M6812_AUTO_INC_DEC (M6812_PRE_INC | M6812_PRE_DEC \
1318 | M6812_POST_INC | M6812_POST_DEC)
1320 /* Checks that the number 'num' fits for a given mode. */
1322 check_range (num
, mode
)
1326 /* Auto increment and decrement are ok for [-8..8] without 0. */
1327 if (mode
& M6812_AUTO_INC_DEC
)
1328 return (num
!= 0 && num
<= 8 && num
>= -8);
1330 /* The 68HC12 supports 5, 9 and 16-bit offsets. */
1331 if (mode
& (M6812_INDEXED_IND
| M6812_INDEXED
| M6812_OP_IDX
))
1332 mode
= M6811_OP_IND16
;
1334 if (mode
& M6812_OP_JUMP_REL16
)
1335 mode
= M6811_OP_IND16
;
1337 mode
&= ~M6811_OP_BRANCH
;
1342 case M6811_OP_DIRECT
:
1343 return (num
>= 0 && num
<= 255) ? 1 : 0;
1345 case M6811_OP_BITMASK
:
1348 return (((num
& 0xFFFFFF00) == 0) || ((num
& 0xFFFFFF00) == 0xFFFFFF00))
1351 case M6811_OP_JUMP_REL
:
1352 return (num
>= -128 && num
<= 127) ? 1 : 0;
1354 case M6811_OP_IND16
:
1355 case M6811_OP_IND16
| M6812_OP_PAGE
:
1356 case M6811_OP_IMM16
:
1357 return (((num
& 0xFFFF0000) == 0) || ((num
& 0xFFFF0000) == 0xFFFF0000))
1360 case M6812_OP_IBCC_MARKER
:
1361 case M6812_OP_TBCC_MARKER
:
1362 case M6812_OP_DBCC_MARKER
:
1363 return (num
>= -256 && num
<= 255) ? 1 : 0;
1365 case M6812_OP_TRAP_ID
:
1366 return ((num
>= 0x30 && num
<= 0x39)
1367 || (num
>= 0x40 && num
<= 0x0ff)) ? 1 : 0;
1374 /* Gas fixup generation. */
1376 /* Put a 1 byte expression described by 'oper'. If this expression contains
1377 unresolved symbols, generate an 8-bit fixup. */
1379 fixup8 (oper
, mode
, opmode
)
1388 if (oper
->X_op
== O_constant
)
1390 if (mode
& M6812_OP_TRAP_ID
1391 && !check_range (oper
->X_add_number
, M6812_OP_TRAP_ID
))
1393 static char trap_id_warn_once
= 0;
1395 as_bad (_("Trap id `%ld' is out of range."), oper
->X_add_number
);
1396 if (trap_id_warn_once
== 0)
1398 trap_id_warn_once
= 1;
1399 as_bad (_("Trap id must be within [0x30..0x39] or [0x40..0xff]."));
1403 if (!(mode
& M6812_OP_TRAP_ID
)
1404 && !check_range (oper
->X_add_number
, mode
))
1406 as_bad (_("Operand out of 8-bit range: `%ld'."), oper
->X_add_number
);
1408 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FF, 1);
1410 else if (oper
->X_op
!= O_register
)
1412 if (mode
& M6812_OP_TRAP_ID
)
1413 as_bad (_("The trap id must be a constant."));
1415 if (mode
== M6811_OP_JUMP_REL
)
1419 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1420 oper
, TRUE
, BFD_RELOC_8_PCREL
);
1421 fixp
->fx_pcrel_adjust
= 1;
1425 /* Now create an 8-bit fixup. If there was some %hi or %lo
1426 modifier, generate the reloc accordingly. */
1427 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1429 ((opmode
& M6811_OP_HIGH_ADDR
)
1430 ? BFD_RELOC_M68HC11_HI8
1431 : ((opmode
& M6811_OP_LOW_ADDR
)
1432 ? BFD_RELOC_M68HC11_LO8
1433 : ((mode
& M6812_OP_PAGE
)
1434 ? BFD_RELOC_M68HC11_PAGE
: BFD_RELOC_8
))));
1436 number_to_chars_bigendian (f
, 0, 1);
1440 as_fatal (_("Operand `%x' not recognized in fixup8."), oper
->X_op
);
1444 /* Put a 2 byte expression described by 'oper'. If this expression contains
1445 unresolved symbols, generate a 16-bit fixup. */
1447 fixup16 (oper
, mode
, opmode
)
1450 int opmode ATTRIBUTE_UNUSED
;
1456 if (oper
->X_op
== O_constant
)
1458 if (!check_range (oper
->X_add_number
, mode
))
1460 as_bad (_("Operand out of 16-bit range: `%ld'."),
1461 oper
->X_add_number
);
1463 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FFFF, 2);
1465 else if (oper
->X_op
!= O_register
)
1469 /* Now create a 16-bit fixup. */
1470 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 2,
1472 (mode
& M6812_OP_JUMP_REL16
? TRUE
: FALSE
),
1473 (mode
& M6812_OP_JUMP_REL16
1474 ? BFD_RELOC_16_PCREL
1475 : (mode
& M6812_OP_PAGE
)
1476 ? BFD_RELOC_M68HC11_LO16
: BFD_RELOC_16
));
1477 number_to_chars_bigendian (f
, 0, 2);
1478 if (mode
& M6812_OP_JUMP_REL16
)
1479 fixp
->fx_pcrel_adjust
= 2;
1483 as_fatal (_("Operand `%x' not recognized in fixup16."), oper
->X_op
);
1487 /* Put a 3 byte expression described by 'oper'. If this expression contains
1488 unresolved symbols, generate a 24-bit fixup. */
1490 fixup24 (oper
, mode
, opmode
)
1493 int opmode ATTRIBUTE_UNUSED
;
1499 if (oper
->X_op
== O_constant
)
1501 if (!check_range (oper
->X_add_number
, mode
))
1503 as_bad (_("Operand out of 16-bit range: `%ld'."),
1504 oper
->X_add_number
);
1506 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FFFFFF, 3);
1508 else if (oper
->X_op
!= O_register
)
1512 /* Now create a 24-bit fixup. */
1513 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 2,
1514 oper
, FALSE
, BFD_RELOC_M68HC11_24
);
1515 number_to_chars_bigendian (f
, 0, 3);
1519 as_fatal (_("Operand `%x' not recognized in fixup16."), oper
->X_op
);
1523 /* 68HC11 and 68HC12 code generation. */
1525 /* Translate the short branch/bsr instruction into a long branch. */
1526 static unsigned char
1527 convert_branch (code
)
1530 if (IS_OPCODE (code
, M6812_BSR
))
1532 else if (IS_OPCODE (code
, M6811_BSR
))
1534 else if (IS_OPCODE (code
, M6811_BRA
))
1535 return (current_architecture
& cpu6812
) ? M6812_JMP
: M6811_JMP
;
1537 as_fatal (_("Unexpected branch conversion with `%x'"), code
);
1539 /* Keep gcc happy. */
1543 /* Start a new insn that contains at least 'size' bytes. Record the
1544 line information of that insn in the dwarf2 debug sections. */
1546 m68hc11_new_insn (size
)
1551 f
= frag_more (size
);
1553 dwarf2_emit_insn (size
);
1558 /* Builds a jump instruction (bra, bcc, bsr). */
1560 build_jump_insn (opcode
, operands
, nb_operands
, jmp_mode
)
1561 struct m68hc11_opcode
*opcode
;
1572 /* The relative branch convertion is not supported for
1574 assert ((opcode
->format
& M6811_OP_BITMASK
) == 0);
1575 assert (nb_operands
== 1);
1576 assert (operands
[0].reg1
== REG_NONE
&& operands
[0].reg2
== REG_NONE
);
1578 code
= opcode
->opcode
;
1580 n
= operands
[0].exp
.X_add_number
;
1582 /* Turn into a long branch:
1583 - when force long branch option (and not for jbcc pseudos),
1584 - when jbcc and the constant is out of -128..127 range,
1585 - when branch optimization is allowed and branch out of range. */
1586 if ((jmp_mode
== 0 && flag_force_long_jumps
)
1587 || (operands
[0].exp
.X_op
== O_constant
1588 && (!check_range (n
, opcode
->format
) &&
1589 (jmp_mode
== 1 || flag_fixed_branchs
== 0))))
1592 where
= frag_now_fix ();
1594 fix_new (frag_now
, frag_now_fix (), 1,
1595 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1597 if (code
== M6811_BSR
|| code
== M6811_BRA
|| code
== M6812_BSR
)
1599 code
= convert_branch (code
);
1601 f
= m68hc11_new_insn (1);
1602 number_to_chars_bigendian (f
, code
, 1);
1604 else if (current_architecture
& cpu6812
)
1606 /* 68HC12: translate the bcc into a lbcc. */
1607 f
= m68hc11_new_insn (2);
1608 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1609 number_to_chars_bigendian (f
+ 1, code
, 1);
1610 fixup16 (&operands
[0].exp
, M6812_OP_JUMP_REL16
,
1611 M6812_OP_JUMP_REL16
);
1616 /* 68HC11: translate the bcc into b!cc +3; jmp <L>. */
1617 f
= m68hc11_new_insn (3);
1619 number_to_chars_bigendian (f
, code
, 1);
1620 number_to_chars_bigendian (f
+ 1, 3, 1);
1621 number_to_chars_bigendian (f
+ 2, M6811_JMP
, 1);
1623 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, M6811_OP_IND16
);
1627 /* Branch with a constant that must fit in 8-bits. */
1628 if (operands
[0].exp
.X_op
== O_constant
)
1630 if (!check_range (n
, opcode
->format
))
1632 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1635 else if (opcode
->format
& M6812_OP_JUMP_REL16
)
1637 f
= m68hc11_new_insn (4);
1638 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1639 number_to_chars_bigendian (f
+ 1, code
, 1);
1640 number_to_chars_bigendian (f
+ 2, n
& 0x0ffff, 2);
1644 f
= m68hc11_new_insn (2);
1645 number_to_chars_bigendian (f
, code
, 1);
1646 number_to_chars_bigendian (f
+ 1, n
& 0x0FF, 1);
1649 else if (opcode
->format
& M6812_OP_JUMP_REL16
)
1652 where
= frag_now_fix ();
1654 fix_new (frag_now
, frag_now_fix (), 1,
1655 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1657 f
= m68hc11_new_insn (2);
1658 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1659 number_to_chars_bigendian (f
+ 1, code
, 1);
1660 fixup16 (&operands
[0].exp
, M6812_OP_JUMP_REL16
, M6812_OP_JUMP_REL16
);
1667 where
= frag_now_fix ();
1669 fix_new (frag_now
, frag_now_fix (), 1,
1670 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1672 /* Branch offset must fit in 8-bits, don't do some relax. */
1673 if (jmp_mode
== 0 && flag_fixed_branchs
)
1675 opcode
= m68hc11_new_insn (1);
1676 number_to_chars_bigendian (opcode
, code
, 1);
1677 fixup8 (&operands
[0].exp
, M6811_OP_JUMP_REL
, M6811_OP_JUMP_REL
);
1680 /* bra/bsr made be changed into jmp/jsr. */
1681 else if (code
== M6811_BSR
|| code
== M6811_BRA
|| code
== M6812_BSR
)
1683 /* Allocate worst case storage. */
1684 opcode
= m68hc11_new_insn (3);
1685 number_to_chars_bigendian (opcode
, code
, 1);
1686 number_to_chars_bigendian (opcode
+ 1, 0, 1);
1687 frag_variant (rs_machine_dependent
, 1, 1,
1688 ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_UNDF
),
1689 operands
[0].exp
.X_add_symbol
, (offsetT
) n
,
1692 else if (current_architecture
& cpu6812
)
1694 opcode
= m68hc11_new_insn (2);
1695 number_to_chars_bigendian (opcode
, code
, 1);
1696 number_to_chars_bigendian (opcode
+ 1, 0, 1);
1697 frag_var (rs_machine_dependent
, 2, 2,
1698 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_UNDF
),
1699 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, opcode
);
1703 opcode
= m68hc11_new_insn (2);
1704 number_to_chars_bigendian (opcode
, code
, 1);
1705 number_to_chars_bigendian (opcode
+ 1, 0, 1);
1706 frag_var (rs_machine_dependent
, 3, 3,
1707 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_UNDF
),
1708 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, opcode
);
1713 /* Builds a dbne/dbeq/tbne/tbeq instruction. */
1715 build_dbranch_insn (opcode
, operands
, nb_operands
, jmp_mode
)
1716 struct m68hc11_opcode
*opcode
;
1725 /* The relative branch convertion is not supported for
1727 assert ((opcode
->format
& M6811_OP_BITMASK
) == 0);
1728 assert (nb_operands
== 2);
1729 assert (operands
[0].reg1
!= REG_NONE
);
1731 code
= opcode
->opcode
& 0x0FF;
1733 f
= m68hc11_new_insn (1);
1734 number_to_chars_bigendian (f
, code
, 1);
1736 n
= operands
[1].exp
.X_add_number
;
1737 code
= operands
[0].reg1
;
1739 if (operands
[0].reg1
== REG_NONE
|| operands
[0].reg1
== REG_CCR
1740 || operands
[0].reg1
== REG_PC
)
1741 as_bad (_("Invalid register for dbcc/tbcc instruction."));
1743 if (opcode
->format
& M6812_OP_IBCC_MARKER
)
1745 else if (opcode
->format
& M6812_OP_TBCC_MARKER
)
1748 if (!(opcode
->format
& M6812_OP_EQ_MARKER
))
1751 /* Turn into a long branch:
1752 - when force long branch option (and not for jbcc pseudos),
1753 - when jdbcc and the constant is out of -256..255 range,
1754 - when branch optimization is allowed and branch out of range. */
1755 if ((jmp_mode
== 0 && flag_force_long_jumps
)
1756 || (operands
[1].exp
.X_op
== O_constant
1757 && (!check_range (n
, M6812_OP_IBCC_MARKER
) &&
1758 (jmp_mode
== 1 || flag_fixed_branchs
== 0))))
1762 number_to_chars_bigendian (f
, code
, 1);
1763 number_to_chars_bigendian (f
+ 1, M6812_JMP
, 1);
1764 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, M6811_OP_IND16
);
1768 /* Branch with a constant that must fit in 9-bits. */
1769 if (operands
[1].exp
.X_op
== O_constant
)
1771 if (!check_range (n
, M6812_OP_IBCC_MARKER
))
1773 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1782 number_to_chars_bigendian (f
, code
, 1);
1783 number_to_chars_bigendian (f
+ 1, n
& 0x0FF, 1);
1788 /* Branch offset must fit in 8-bits, don't do some relax. */
1789 if (jmp_mode
== 0 && flag_fixed_branchs
)
1791 fixup8 (&operands
[0].exp
, M6811_OP_JUMP_REL
, M6811_OP_JUMP_REL
);
1797 number_to_chars_bigendian (f
, code
, 1);
1798 number_to_chars_bigendian (f
+ 1, 0, 1);
1799 frag_var (rs_machine_dependent
, 3, 3,
1800 ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_UNDF
),
1801 operands
[1].exp
.X_add_symbol
, (offsetT
) n
, f
);
1806 #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4)
1808 /* Assemble the post index byte for 68HC12 extended addressing modes. */
1810 build_indexed_byte (op
, format
, move_insn
)
1812 int format ATTRIBUTE_UNUSED
;
1815 unsigned char byte
= 0;
1820 val
= op
->exp
.X_add_number
;
1822 if (mode
& M6812_AUTO_INC_DEC
)
1825 if (mode
& (M6812_POST_INC
| M6812_POST_DEC
))
1828 if (op
->exp
.X_op
== O_constant
)
1830 if (!check_range (val
, mode
))
1832 as_bad (_("Increment/decrement value is out of range: `%ld'."),
1835 if (mode
& (M6812_POST_INC
| M6812_PRE_INC
))
1836 byte
|= (val
- 1) & 0x07;
1838 byte
|= (8 - ((val
) & 7)) | 0x8;
1843 as_fatal (_("Expecting a register."));
1858 as_bad (_("Invalid register for post/pre increment."));
1863 number_to_chars_bigendian (f
, byte
, 1);
1867 if (mode
& (M6812_OP_IDX
| M6812_OP_D_IDX_2
))
1888 as_bad (_("Invalid register."));
1891 if (op
->exp
.X_op
== O_constant
)
1893 if (!check_range (val
, M6812_OP_IDX
))
1895 as_bad (_("Offset out of 16-bit range: %ld."), val
);
1898 if (move_insn
&& !(val
>= -16 && val
<= 15))
1900 as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."),
1905 if (val
>= -16 && val
<= 15 && !(mode
& M6812_OP_D_IDX_2
))
1910 number_to_chars_bigendian (f
, byte
, 1);
1913 else if (val
>= -256 && val
<= 255 && !(mode
& M6812_OP_D_IDX_2
))
1920 number_to_chars_bigendian (f
, byte
, 1);
1921 number_to_chars_bigendian (f
+ 1, val
& 0x0FF, 1);
1927 if (mode
& M6812_OP_D_IDX_2
)
1933 number_to_chars_bigendian (f
, byte
, 1);
1934 number_to_chars_bigendian (f
+ 1, val
& 0x0FFFF, 2);
1938 if (mode
& M6812_OP_D_IDX_2
)
1940 byte
= (byte
<< 3) | 0xe3;
1942 number_to_chars_bigendian (f
, byte
, 1);
1944 fixup16 (&op
->exp
, 0, 0);
1946 else if (op
->reg1
!= REG_PC
)
1952 number_to_chars_bigendian (f
, byte
, 1);
1953 sym
= op
->exp
.X_add_symbol
;
1954 off
= op
->exp
.X_add_number
;
1955 if (op
->exp
.X_op
!= O_symbol
)
1957 sym
= make_expr_symbol (&op
->exp
);
1960 frag_var (rs_machine_dependent
, 2, 2,
1961 ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_UNDF
),
1967 number_to_chars_bigendian (f
, byte
, 1);
1968 frag_var (rs_machine_dependent
, 2, 2,
1969 ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_UNDF
),
1970 op
->exp
.X_add_symbol
,
1971 op
->exp
.X_add_number
, f
);
1976 if (mode
& (M6812_OP_REG
| M6812_OP_D_IDX
))
1978 if (mode
& M6812_OP_D_IDX
)
1980 if (op
->reg1
!= REG_D
)
1981 as_bad (_("Expecting register D for indexed indirect mode."));
1983 as_bad (_("Indexed indirect mode is not allowed for movb/movw."));
2000 as_bad (_("Invalid accumulator register."));
2025 as_bad (_("Invalid indexed register."));
2029 number_to_chars_bigendian (f
, byte
, 1);
2033 as_fatal (_("Addressing mode not implemented yet."));
2037 /* Assemble the 68HC12 register mode byte. */
2039 build_reg_mode (op
, format
)
2046 if (format
& M6812_OP_SEX_MARKER
2047 && op
->reg1
!= REG_A
&& op
->reg1
!= REG_B
&& op
->reg1
!= REG_CCR
)
2048 as_bad (_("Invalid source register for this instruction, use 'tfr'."));
2049 else if (op
->reg1
== REG_NONE
|| op
->reg1
== REG_PC
)
2050 as_bad (_("Invalid source register."));
2052 if (format
& M6812_OP_SEX_MARKER
2053 && op
->reg2
!= REG_D
2054 && op
->reg2
!= REG_X
&& op
->reg2
!= REG_Y
&& op
->reg2
!= REG_SP
)
2055 as_bad (_("Invalid destination register for this instruction, use 'tfr'."));
2056 else if (op
->reg2
== REG_NONE
|| op
->reg2
== REG_PC
)
2057 as_bad (_("Invalid destination register."));
2059 byte
= (op
->reg1
<< 4) | (op
->reg2
);
2060 if (format
& M6812_OP_EXG_MARKER
)
2064 number_to_chars_bigendian (f
, byte
, 1);
2068 /* build_insn takes a pointer to the opcode entry in the opcode table,
2069 the array of operand expressions and builds the correspding instruction.
2070 This operation only deals with non relative jumps insn (need special
2073 build_insn (opcode
, operands
, nb_operands
)
2074 struct m68hc11_opcode
*opcode
;
2076 int nb_operands ATTRIBUTE_UNUSED
;
2083 /* Put the page code instruction if there is one. */
2084 format
= opcode
->format
;
2086 if (format
& M6811_OP_BRANCH
)
2087 fix_new (frag_now
, frag_now_fix (), 1,
2088 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
2090 if (format
& OP_EXTENDED
)
2094 f
= m68hc11_new_insn (2);
2095 if (format
& M6811_OP_PAGE2
)
2096 page_code
= M6811_OPCODE_PAGE2
;
2097 else if (format
& M6811_OP_PAGE3
)
2098 page_code
= M6811_OPCODE_PAGE3
;
2100 page_code
= M6811_OPCODE_PAGE4
;
2102 number_to_chars_bigendian (f
, page_code
, 1);
2106 f
= m68hc11_new_insn (1);
2108 number_to_chars_bigendian (f
, opcode
->opcode
, 1);
2112 /* The 68HC12 movb and movw instructions are special. We have to handle
2113 them in a special way. */
2114 if (format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
2117 if (format
& M6812_OP_IDX
)
2119 build_indexed_byte (&operands
[0], format
, 1);
2121 format
&= ~M6812_OP_IDX
;
2123 if (format
& M6812_OP_IDX_P2
)
2125 build_indexed_byte (&operands
[1], format
, 1);
2127 format
&= ~M6812_OP_IDX_P2
;
2131 if (format
& (M6811_OP_DIRECT
| M6811_OP_IMM8
))
2133 fixup8 (&operands
[i
].exp
,
2134 format
& (M6811_OP_DIRECT
| M6811_OP_IMM8
| M6812_OP_TRAP_ID
),
2138 else if (IS_CALL_SYMBOL (format
) && nb_operands
== 1)
2140 format
&= ~M6812_OP_PAGE
;
2141 fixup24 (&operands
[i
].exp
, format
& M6811_OP_IND16
,
2145 else if (format
& (M6811_OP_IMM16
| M6811_OP_IND16
))
2147 fixup16 (&operands
[i
].exp
,
2148 format
& (M6811_OP_IMM16
| M6811_OP_IND16
| M6812_OP_PAGE
),
2152 else if (format
& (M6811_OP_IX
| M6811_OP_IY
))
2154 if ((format
& M6811_OP_IX
) && (operands
[0].reg1
!= REG_X
))
2155 as_bad (_("Invalid indexed register, expecting register X."));
2156 if ((format
& M6811_OP_IY
) && (operands
[0].reg1
!= REG_Y
))
2157 as_bad (_("Invalid indexed register, expecting register Y."));
2159 fixup8 (&operands
[0].exp
, M6811_OP_IX
, operands
[0].mode
);
2163 (M6812_OP_IDX
| M6812_OP_IDX_2
| M6812_OP_IDX_1
2164 | M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
2166 build_indexed_byte (&operands
[i
], format
, move_insn
);
2169 else if (format
& M6812_OP_REG
&& current_architecture
& cpu6812
)
2171 build_reg_mode (&operands
[i
], format
);
2174 if (format
& M6811_OP_BITMASK
)
2176 fixup8 (&operands
[i
].exp
, M6811_OP_BITMASK
, operands
[i
].mode
);
2179 if (format
& M6811_OP_JUMP_REL
)
2181 fixup8 (&operands
[i
].exp
, M6811_OP_JUMP_REL
, operands
[i
].mode
);
2183 else if (format
& M6812_OP_IND16_P2
)
2185 fixup16 (&operands
[1].exp
, M6811_OP_IND16
, operands
[1].mode
);
2187 if (format
& M6812_OP_PAGE
)
2189 fixup8 (&operands
[i
].exp
, M6812_OP_PAGE
, operands
[i
].mode
);
2193 /* Opcode identification and operand analysis. */
2195 /* find() gets a pointer to an entry in the opcode table. It must look at all
2196 opcodes with the same name and use the operands to choose the correct
2197 opcode. Returns the opcode pointer if there was a match and 0 if none. */
2198 static struct m68hc11_opcode
*
2199 find (opc
, operands
, nb_operands
)
2200 struct m68hc11_opcode_def
*opc
;
2205 struct m68hc11_opcode
*opcode
;
2206 struct m68hc11_opcode
*op_indirect
;
2209 opcode
= opc
->opcode
;
2211 /* Now search the opcode table table for one with operands
2212 that matches what we've got. We're only done if the operands matched so
2213 far AND there are no more to check. */
2214 for (pos
= match
= 0; match
== 0 && pos
< opc
->nb_modes
; pos
++, opcode
++)
2216 int poss_indirect
= 0;
2217 long format
= opcode
->format
;
2221 if (opcode
->format
& M6811_OP_MASK
)
2223 if (opcode
->format
& M6811_OP_BITMASK
)
2225 if (opcode
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2227 if (opcode
->format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
2229 if ((opcode
->format
& M6812_OP_PAGE
)
2230 && (!IS_CALL_SYMBOL (opcode
->format
) || nb_operands
== 2))
2233 for (i
= 0; expect
== nb_operands
&& i
< nb_operands
; i
++)
2235 int mode
= operands
[i
].mode
;
2237 if (mode
& M6811_OP_IMM16
)
2240 (M6811_OP_IMM8
| M6811_OP_IMM16
| M6811_OP_BITMASK
))
2244 if (mode
== M6811_OP_DIRECT
)
2246 if (format
& M6811_OP_DIRECT
)
2249 /* If the operand is a page 0 operand, remember a
2250 possible <abs-16> addressing mode. We mark
2251 this and continue to check other operands. */
2252 if (format
& M6811_OP_IND16
2253 && flag_strict_direct_addressing
&& op_indirect
== 0)
2260 if (mode
& M6811_OP_IND16
)
2262 if (i
== 0 && (format
& M6811_OP_IND16
) != 0)
2264 if (i
!= 0 && (format
& M6812_OP_PAGE
) != 0)
2266 if (i
!= 0 && (format
& M6812_OP_IND16_P2
) != 0)
2268 if (i
== 0 && (format
& M6811_OP_BITMASK
))
2271 if (mode
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2273 if (format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2276 if (mode
& M6812_OP_REG
)
2279 && (format
& M6812_OP_REG
)
2280 && (operands
[i
].reg2
== REG_NONE
))
2283 && (format
& M6812_OP_REG
)
2284 && (format
& M6812_OP_REG_2
)
2285 && (operands
[i
].reg2
!= REG_NONE
))
2288 && (format
& M6812_OP_IDX
)
2289 && (operands
[i
].reg2
!= REG_NONE
))
2292 && (format
& M6812_OP_IDX
)
2293 && (format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
)))
2296 && (format
& M6812_OP_IDX_P2
))
2300 if (mode
& M6812_OP_IDX
)
2302 if (format
& M6811_OP_IX
&& operands
[i
].reg1
== REG_X
)
2304 if (format
& M6811_OP_IY
&& operands
[i
].reg1
== REG_Y
)
2307 && format
& (M6812_OP_IDX
| M6812_OP_IDX_1
| M6812_OP_IDX_2
)
2308 && (operands
[i
].reg1
== REG_X
2309 || operands
[i
].reg1
== REG_Y
2310 || operands
[i
].reg1
== REG_SP
2311 || operands
[i
].reg1
== REG_PC
))
2313 if (i
== 1 && format
& M6812_OP_IDX_P2
)
2316 if (mode
& format
& (M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
2321 if (mode
& M6812_AUTO_INC_DEC
)
2324 && format
& (M6812_OP_IDX
| M6812_OP_IDX_1
|
2327 if (i
== 1 && format
& M6812_OP_IDX_P2
)
2332 match
= i
== nb_operands
;
2334 /* Operands are ok but an operand uses page 0 addressing mode
2335 while the insn supports abs-16 mode. Keep a reference to this
2336 insns in case there is no insn supporting page 0 addressing. */
2337 if (match
&& poss_indirect
)
2339 op_indirect
= opcode
;
2346 /* Page 0 addressing is used but not supported by any insn.
2347 If absolute addresses are supported, we use that insn. */
2348 if (match
== 0 && op_indirect
)
2350 opcode
= op_indirect
;
2362 /* Find the real opcode and its associated operands. We use a progressive
2363 approach here. On entry, 'opc' points to the first opcode in the
2364 table that matches the opcode name in the source line. We try to
2365 isolate an operand, find a possible match in the opcode table.
2366 We isolate another operand if no match were found. The table 'operands'
2367 is filled while operands are recognized.
2369 Returns the opcode pointer that matches the opcode name in the
2370 source line and the associated operands. */
2371 static struct m68hc11_opcode
*
2372 find_opcode (opc
, operands
, nb_operands
)
2373 struct m68hc11_opcode_def
*opc
;
2377 struct m68hc11_opcode
*opcode
;
2380 if (opc
->max_operands
== 0)
2386 for (i
= 0; i
< opc
->max_operands
;)
2390 result
= get_operand (&operands
[i
], i
, opc
->format
);
2394 /* Special case where the bitmask of the bclr/brclr
2395 instructions is not introduced by #.
2396 Example: bclr 3,x $80. */
2397 if (i
== 1 && (opc
->format
& M6811_OP_BITMASK
)
2398 && (operands
[i
].mode
& M6811_OP_IND16
))
2400 operands
[i
].mode
= M6811_OP_IMM16
;
2405 if (i
>= opc
->min_operands
)
2407 opcode
= find (opc
, operands
, i
);
2408 if (opcode
&& !(opcode
->format
& M6812_OP_PAGE
))
2411 if (opcode
&& *input_line_pointer
!= ',')
2415 if (*input_line_pointer
== ',')
2416 input_line_pointer
++;
2422 #define M6812_XBCC_MARKER (M6812_OP_TBCC_MARKER \
2423 | M6812_OP_DBCC_MARKER \
2424 | M6812_OP_IBCC_MARKER)
2426 /* Gas line assembler entry point. */
2428 /* This is the main entry point for the machine-dependent assembler. str
2429 points to a machine-dependent instruction. This function is supposed to
2430 emit the frags/bytes it assembles to. */
2435 struct m68hc11_opcode_def
*opc
;
2436 struct m68hc11_opcode
*opcode
;
2438 unsigned char *op_start
, *save
;
2439 unsigned char *op_end
;
2442 operand operands
[M6811_MAX_OPERANDS
];
2444 int branch_optimize
= 0;
2447 /* Drop leading whitespace. */
2451 /* Find the opcode end and get the opcode in 'name'. The opcode is forced
2452 lower case (the opcode table only has lower case op-codes). */
2453 for (op_start
= op_end
= (unsigned char *) (str
);
2454 *op_end
&& nlen
< 20 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
2457 name
[nlen
] = TOLOWER (op_start
[nlen
]);
2464 as_bad (_("No instruction or missing opcode."));
2468 /* Find the opcode definition given its name. */
2469 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, name
);
2471 /* If it's not recognized, look for 'jbsr' and 'jbxx'. These are
2472 pseudo insns for relative branch. For these branchs, we always
2473 optimize them (turned into absolute branchs) even if --short-branchs
2475 if (opc
== NULL
&& name
[0] == 'j' && name
[1] == 'b')
2477 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
, &name
[1]);
2479 && (!(opc
->format
& M6811_OP_JUMP_REL
)
2480 || (opc
->format
& M6811_OP_BITMASK
)))
2483 branch_optimize
= 1;
2486 /* The following test should probably be removed. This is not conform
2487 to Motorola assembler specs. */
2488 if (opc
== NULL
&& flag_mri
)
2490 if (*op_end
== ' ' || *op_end
== '\t')
2492 while (*op_end
== ' ' || *op_end
== '\t')
2497 (is_end_of_line
[op_end
[1]]
2498 || op_end
[1] == ' ' || op_end
[1] == '\t'
2499 || !ISALNUM (op_end
[1])))
2500 && (*op_end
== 'a' || *op_end
== 'b'
2501 || *op_end
== 'A' || *op_end
== 'B'
2502 || *op_end
== 'd' || *op_end
== 'D'
2503 || *op_end
== 'x' || *op_end
== 'X'
2504 || *op_end
== 'y' || *op_end
== 'Y'))
2506 name
[nlen
++] = TOLOWER (*op_end
++);
2508 opc
= (struct m68hc11_opcode_def
*) hash_find (m68hc11_hash
,
2514 /* Identify a possible instruction alias. There are some on the
2515 68HC12 to emulate a few 68HC11 instructions. */
2516 if (opc
== NULL
&& (current_architecture
& cpu6812
))
2520 for (i
= 0; i
< m68hc12_num_alias
; i
++)
2521 if (strcmp (m68hc12_alias
[i
].name
, name
) == 0)
2527 if (opc
== NULL
&& alias_id
< 0)
2529 as_bad (_("Opcode `%s' is not recognized."), name
);
2532 save
= input_line_pointer
;
2533 input_line_pointer
= op_end
;
2538 opcode
= find_opcode (opc
, operands
, &nb_operands
);
2543 if ((opcode
|| alias_id
>= 0) && !flag_mri
)
2545 char *p
= input_line_pointer
;
2547 while (*p
== ' ' || *p
== '\t' || *p
== '\n' || *p
== '\r')
2550 if (*p
!= '\n' && *p
)
2551 as_bad (_("Garbage at end of instruction: `%s'."), p
);
2554 input_line_pointer
= save
;
2558 char *f
= m68hc11_new_insn (m68hc12_alias
[alias_id
].size
);
2560 number_to_chars_bigendian (f
, m68hc12_alias
[alias_id
].code1
, 1);
2561 if (m68hc12_alias
[alias_id
].size
> 1)
2562 number_to_chars_bigendian (f
+ 1, m68hc12_alias
[alias_id
].code2
, 1);
2567 /* Opcode is known but does not have valid operands. Print out the
2568 syntax for this opcode. */
2571 if (flag_print_insn_syntax
)
2572 print_insn_format (name
);
2574 as_bad (_("Invalid operand for `%s'"), name
);
2578 /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is
2579 relative and must be in the range -256..255 (9-bits). */
2580 if ((opcode
->format
& M6812_XBCC_MARKER
)
2581 && (opcode
->format
& M6811_OP_JUMP_REL
))
2582 build_dbranch_insn (opcode
, operands
, nb_operands
, branch_optimize
);
2584 /* Relative jumps instructions are taken care of separately. We have to make
2585 sure that the relative branch is within the range -128..127. If it's out
2586 of range, the instructions are changed into absolute instructions.
2587 This is not supported for the brset and brclr instructions. */
2588 else if ((opcode
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2589 && !(opcode
->format
& M6811_OP_BITMASK
))
2590 build_jump_insn (opcode
, operands
, nb_operands
, branch_optimize
);
2592 build_insn (opcode
, operands
, nb_operands
);
2596 /* Pseudo op to control the ELF flags. */
2599 int x ATTRIBUTE_UNUSED
;
2601 char *name
= input_line_pointer
, ch
;
2603 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2604 input_line_pointer
++;
2605 ch
= *input_line_pointer
;
2606 *input_line_pointer
= '\0';
2608 if (strcmp (name
, "mshort") == 0)
2610 elf_flags
&= ~E_M68HC11_I32
;
2612 else if (strcmp (name
, "mlong") == 0)
2614 elf_flags
|= E_M68HC11_I32
;
2616 else if (strcmp (name
, "mshort-double") == 0)
2618 elf_flags
&= ~E_M68HC11_F64
;
2620 else if (strcmp (name
, "mlong-double") == 0)
2622 elf_flags
|= E_M68HC11_F64
;
2626 as_warn (_("Invalid mode: %s\n"), name
);
2628 *input_line_pointer
= ch
;
2629 demand_empty_rest_of_line ();
2632 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions
2633 are using 'rtc' for returning. It is necessary to use 'call'
2634 to invoke them. This is also used by the debugger to correctly
2635 find the stack frame. */
2637 s_m68hc11_mark_symbol (mark
)
2644 elf_symbol_type
*elfsym
;
2648 name
= input_line_pointer
;
2649 c
= get_symbol_end ();
2650 symbolP
= symbol_find_or_make (name
);
2651 *input_line_pointer
= c
;
2655 bfdsym
= symbol_get_bfdsym (symbolP
);
2656 elfsym
= elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
2660 /* Mark the symbol far (using rtc for function return). */
2661 elfsym
->internal_elf_sym
.st_other
|= mark
;
2665 input_line_pointer
++;
2669 if (*input_line_pointer
== '\n')
2675 demand_empty_rest_of_line ();
2679 s_m68hc11_relax (ignore
)
2680 int ignore ATTRIBUTE_UNUSED
;
2686 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
2688 as_bad (_("bad .relax format"));
2689 ignore_rest_of_line ();
2693 fix_new_exp (frag_now
, frag_now_fix (), 1, &ex
, 1,
2694 BFD_RELOC_M68HC11_RL_GROUP
);
2696 demand_empty_rest_of_line ();
2700 /* Relocation, relaxation and frag conversions. */
2702 /* PC-relative offsets are relative to the start of the
2703 next instruction. That is, the address of the offset, plus its
2704 size, since the offset is always the last part of the insn. */
2706 md_pcrel_from (fixP
)
2709 if (fixP
->fx_r_type
== BFD_RELOC_M68HC11_RL_JUMP
)
2712 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2715 /* If while processing a fixup, a reloc really needs to be created
2716 then it is done here. */
2718 tc_gen_reloc (section
, fixp
)
2719 asection
*section ATTRIBUTE_UNUSED
;
2724 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2725 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2726 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2727 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2728 if (fixp
->fx_r_type
== 0)
2729 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
2731 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2732 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
2734 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2735 _("Relocation %d is not supported by object file format."),
2736 (int) fixp
->fx_r_type
);
2740 /* Since we use Rel instead of Rela, encode the vtable entry to be
2741 used in the relocation's section offset. */
2742 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2743 reloc
->address
= fixp
->fx_offset
;
2749 /* We need a port-specific relaxation function to cope with sym2 - sym1
2750 relative expressions with both symbols in the same segment (but not
2751 necessarily in the same frag as this insn), for example:
2752 ldab sym2-(sym1-2),pc
2754 The offset can be 5, 9 or 16 bits long. */
2757 m68hc11_relax_frag (seg
, fragP
, stretch
)
2758 segT seg ATTRIBUTE_UNUSED
;
2760 long stretch ATTRIBUTE_UNUSED
;
2765 const relax_typeS
*this_type
;
2766 const relax_typeS
*start_type
;
2767 relax_substateT next_state
;
2768 relax_substateT this_state
;
2769 const relax_typeS
*table
= TC_GENERIC_RELAX_TABLE
;
2771 /* We only have to cope with frags as prepared by
2772 md_estimate_size_before_relax. The STATE_BITS16 case may geet here
2773 because of the different reasons that it's not relaxable. */
2774 switch (fragP
->fr_subtype
)
2776 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
):
2777 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
):
2778 /* When we get to this state, the frag won't grow any more. */
2781 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS5
):
2782 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS5
):
2783 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
):
2784 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
):
2785 if (fragP
->fr_symbol
== NULL
2786 || S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
2787 as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"),
2788 __FUNCTION__
, (long) fragP
->fr_symbol
);
2789 symbolP
= fragP
->fr_symbol
;
2790 if (symbol_resolved_p (symbolP
))
2791 as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
2793 aim
= S_GET_VALUE (symbolP
);
2797 as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"),
2798 __FUNCTION__
, fragP
->fr_subtype
);
2801 /* The rest is stolen from relax_frag. There's no obvious way to
2802 share the code, but fortunately no requirement to keep in sync as
2803 long as fragP->fr_symbol does not have its segment changed. */
2805 this_state
= fragP
->fr_subtype
;
2806 start_type
= this_type
= table
+ this_state
;
2810 /* Look backwards. */
2811 for (next_state
= this_type
->rlx_more
; next_state
;)
2812 if (aim
>= this_type
->rlx_backward
)
2816 /* Grow to next state. */
2817 this_state
= next_state
;
2818 this_type
= table
+ this_state
;
2819 next_state
= this_type
->rlx_more
;
2824 /* Look forwards. */
2825 for (next_state
= this_type
->rlx_more
; next_state
;)
2826 if (aim
<= this_type
->rlx_forward
)
2830 /* Grow to next state. */
2831 this_state
= next_state
;
2832 this_type
= table
+ this_state
;
2833 next_state
= this_type
->rlx_more
;
2837 growth
= this_type
->rlx_length
- start_type
->rlx_length
;
2839 fragP
->fr_subtype
= this_state
;
2844 md_convert_frag (abfd
, sec
, fragP
)
2845 bfd
*abfd ATTRIBUTE_UNUSED
;
2846 asection
*sec ATTRIBUTE_UNUSED
;
2852 char *buffer_address
= fragP
->fr_literal
;
2854 /* Address in object code of the displacement. */
2855 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
2857 buffer_address
+= fragP
->fr_fix
;
2859 /* The displacement of the address, from current location. */
2860 value
= S_GET_VALUE (fragP
->fr_symbol
);
2861 disp
= (value
+ fragP
->fr_offset
) - object_address
;
2863 switch (fragP
->fr_subtype
)
2865 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_BYTE
):
2866 fragP
->fr_opcode
[1] = disp
;
2869 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_WORD
):
2870 /* This relax is only for bsr and bra. */
2871 assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
2872 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
2873 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
2875 fragP
->fr_opcode
[0] = convert_branch (fragP
->fr_opcode
[0]);
2877 fix_new (fragP
, fragP
->fr_fix
- 1, 2,
2878 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2882 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_BYTE
):
2883 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_BYTE
):
2884 fragP
->fr_opcode
[1] = disp
;
2887 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_WORD
):
2888 /* Invert branch. */
2889 fragP
->fr_opcode
[0] ^= 1;
2890 fragP
->fr_opcode
[1] = 3; /* Branch offset. */
2891 buffer_address
[0] = M6811_JMP
;
2892 fix_new (fragP
, fragP
->fr_fix
+ 1, 2,
2893 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2897 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_WORD
):
2898 /* Translate branch into a long branch. */
2899 fragP
->fr_opcode
[1] = fragP
->fr_opcode
[0];
2900 fragP
->fr_opcode
[0] = M6811_OPCODE_PAGE2
;
2902 fixp
= fix_new (fragP
, fragP
->fr_fix
, 2,
2903 fragP
->fr_symbol
, fragP
->fr_offset
, 1,
2904 BFD_RELOC_16_PCREL
);
2905 fixp
->fx_pcrel_adjust
= 2;
2909 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS5
):
2910 if (fragP
->fr_symbol
!= 0
2911 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
2915 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS5
):
2916 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 6;
2917 fragP
->fr_opcode
[0] |= value
& 0x1f;
2920 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
):
2921 /* For a PC-relative offset, use the displacement with a -1 correction
2922 to take into account the additional byte of the insn. */
2923 if (fragP
->fr_symbol
!= 0
2924 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
2928 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
):
2929 fragP
->fr_opcode
[0] = (fragP
->fr_opcode
[0] << 3);
2930 fragP
->fr_opcode
[0] |= 0xE0;
2931 fragP
->fr_opcode
[0] |= (value
>> 8) & 1;
2932 fragP
->fr_opcode
[1] = value
;
2936 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
):
2937 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
):
2938 fragP
->fr_opcode
[0] = (fragP
->fr_opcode
[0] << 3);
2939 fragP
->fr_opcode
[0] |= 0xe2;
2940 if ((fragP
->fr_opcode
[0] & 0x0ff) == 0x0fa
2941 && fragP
->fr_symbol
!= 0
2942 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
2944 fixp
= fix_new (fragP
, fragP
->fr_fix
, 2,
2945 fragP
->fr_symbol
, fragP
->fr_offset
,
2946 1, BFD_RELOC_16_PCREL
);
2950 fix_new (fragP
, fragP
->fr_fix
, 2,
2951 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2956 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_BYTE
):
2958 fragP
->fr_opcode
[0] |= 0x10;
2960 fragP
->fr_opcode
[1] = disp
& 0x0FF;
2963 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_WORD
):
2964 /* Invert branch. */
2965 fragP
->fr_opcode
[0] ^= 0x20;
2966 fragP
->fr_opcode
[1] = 3; /* Branch offset. */
2967 buffer_address
[0] = M6812_JMP
;
2968 fix_new (fragP
, fragP
->fr_fix
+ 1, 2,
2969 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
2978 /* On an ELF system, we can't relax a weak symbol. The weak symbol
2979 can be overridden at final link time by a non weak symbol. We can
2980 relax externally visible symbol because there is no shared library
2981 and such symbol can't be overridden (unless they are weak). */
2983 relaxable_symbol (symbol
)
2986 return ! S_IS_WEAK (symbol
);
2989 /* Force truly undefined symbols to their maximum size, and generally set up
2990 the frag list to be relaxed. */
2992 md_estimate_size_before_relax (fragP
, segment
)
2996 if (RELAX_LENGTH (fragP
->fr_subtype
) == STATE_UNDF
)
2998 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
2999 || !relaxable_symbol (fragP
->fr_symbol
))
3001 /* Non-relaxable cases. */
3003 char *buffer_address
;
3005 old_fr_fix
= fragP
->fr_fix
;
3006 buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
3008 switch (RELAX_STATE (fragP
->fr_subtype
))
3010 case STATE_PC_RELATIVE
:
3012 /* This relax is only for bsr and bra. */
3013 assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
3014 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
3015 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
3017 if (flag_fixed_branchs
)
3018 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
3019 _("bra or bsr with undefined symbol."));
3021 /* The symbol is undefined or in a separate section.
3022 Turn bra into a jmp and bsr into a jsr. The insn
3023 becomes 3 bytes long (instead of 2). A fixup is
3024 necessary for the unresolved symbol address. */
3025 fragP
->fr_opcode
[0] = convert_branch (fragP
->fr_opcode
[0]);
3027 fix_new (fragP
, fragP
->fr_fix
- 1, 2, fragP
->fr_symbol
,
3028 fragP
->fr_offset
, 0, BFD_RELOC_16
);
3032 case STATE_CONDITIONAL_BRANCH
:
3033 assert (current_architecture
& cpu6811
);
3035 fragP
->fr_opcode
[0] ^= 1; /* Reverse sense of branch. */
3036 fragP
->fr_opcode
[1] = 3; /* Skip next jmp insn (3 bytes). */
3038 /* Don't use fr_opcode[2] because this may be
3039 in a different frag. */
3040 buffer_address
[0] = M6811_JMP
;
3043 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3044 fragP
->fr_offset
, 0, BFD_RELOC_16
);
3048 case STATE_INDEXED_OFFSET
:
3049 assert (current_architecture
& cpu6812
);
3051 if (fragP
->fr_symbol
3052 && S_GET_SEGMENT (fragP
->fr_symbol
) == absolute_section
)
3054 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_OFFSET
,
3056 /* Return the size of the variable part of the frag. */
3057 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3061 /* Switch the indexed operation to 16-bit mode. */
3062 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 3;
3063 fragP
->fr_opcode
[0] |= 0xe2;
3064 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3065 fragP
->fr_offset
, 0, BFD_RELOC_16
);
3070 case STATE_INDEXED_PCREL
:
3071 assert (current_architecture
& cpu6812
);
3073 if (fragP
->fr_symbol
3074 && S_GET_SEGMENT (fragP
->fr_symbol
) == absolute_section
)
3076 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_PCREL
,
3078 /* Return the size of the variable part of the frag. */
3079 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3085 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 3;
3086 fragP
->fr_opcode
[0] |= 0xe2;
3087 fixp
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3088 fragP
->fr_offset
, 1, BFD_RELOC_16_PCREL
);
3093 case STATE_XBCC_BRANCH
:
3094 assert (current_architecture
& cpu6812
);
3096 fragP
->fr_opcode
[0] ^= 0x20; /* Reverse sense of branch. */
3097 fragP
->fr_opcode
[1] = 3; /* Skip next jmp insn (3 bytes). */
3099 /* Don't use fr_opcode[2] because this may be
3100 in a different frag. */
3101 buffer_address
[0] = M6812_JMP
;
3104 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3105 fragP
->fr_offset
, 0, BFD_RELOC_16
);
3109 case STATE_CONDITIONAL_BRANCH_6812
:
3110 assert (current_architecture
& cpu6812
);
3112 /* Translate into a lbcc branch. */
3113 fragP
->fr_opcode
[1] = fragP
->fr_opcode
[0];
3114 fragP
->fr_opcode
[0] = M6811_OPCODE_PAGE2
;
3116 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3117 fragP
->fr_offset
, 1, BFD_RELOC_16_PCREL
);
3122 as_fatal (_("Subtype %d is not recognized."), fragP
->fr_subtype
);
3126 /* Return the growth in the fixed part of the frag. */
3127 return fragP
->fr_fix
- old_fr_fix
;
3130 /* Relaxable cases. */
3131 switch (RELAX_STATE (fragP
->fr_subtype
))
3133 case STATE_PC_RELATIVE
:
3134 /* This relax is only for bsr and bra. */
3135 assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
3136 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
3137 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
3139 fragP
->fr_subtype
= ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_BYTE
);
3142 case STATE_CONDITIONAL_BRANCH
:
3143 assert (current_architecture
& cpu6811
);
3145 fragP
->fr_subtype
= ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
,
3149 case STATE_INDEXED_OFFSET
:
3150 assert (current_architecture
& cpu6812
);
3152 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_OFFSET
,
3156 case STATE_INDEXED_PCREL
:
3157 assert (current_architecture
& cpu6812
);
3159 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_PCREL
,
3163 case STATE_XBCC_BRANCH
:
3164 assert (current_architecture
& cpu6812
);
3166 fragP
->fr_subtype
= ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_BYTE
);
3169 case STATE_CONDITIONAL_BRANCH_6812
:
3170 assert (current_architecture
& cpu6812
);
3172 fragP
->fr_subtype
= ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
,
3178 if (fragP
->fr_subtype
>= sizeof (md_relax_table
) / sizeof (md_relax_table
[0]))
3179 as_fatal (_("Subtype %d is not recognized."), fragP
->fr_subtype
);
3181 /* Return the size of the variable part of the frag. */
3182 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3185 /* See whether we need to force a relocation into the output file. */
3187 tc_m68hc11_force_relocation (fixP
)
3190 switch (fixP
->fx_r_type
)
3192 case BFD_RELOC_VTABLE_INHERIT
:
3193 case BFD_RELOC_VTABLE_ENTRY
:
3194 case BFD_RELOC_M68HC11_RL_GROUP
:
3201 return S_FORCE_RELOC (fixP
->fx_addsy
);
3204 /* Here we decide which fixups can be adjusted to make them relative
3205 to the beginning of the section instead of the symbol. Basically
3206 we need to make sure that the linker relaxation is done
3207 correctly, so in some cases we force the original symbol to be
3210 tc_m68hc11_fix_adjustable (fixP
)
3213 switch (fixP
->fx_r_type
)
3215 /* For the linker relaxation to work correctly, these relocs
3216 need to be on the symbol itself. */
3218 case BFD_RELOC_M68HC11_RL_JUMP
:
3219 case BFD_RELOC_M68HC11_RL_GROUP
:
3220 case BFD_RELOC_VTABLE_INHERIT
:
3221 case BFD_RELOC_VTABLE_ENTRY
:
3223 /* The memory bank addressing translation also needs the original
3225 case BFD_RELOC_LO16
:
3226 case BFD_RELOC_M68HC11_PAGE
:
3227 case BFD_RELOC_M68HC11_24
:
3237 md_apply_fix3 (fixP
, valP
, seg
)
3240 segT seg ATTRIBUTE_UNUSED
;
3243 long value
= * valP
;
3246 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
3249 /* We don't actually support subtracting a symbol. */
3250 if (fixP
->fx_subsy
!= (symbolS
*) NULL
)
3251 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("Expression too complex."));
3253 op_type
= fixP
->fx_r_type
;
3255 /* Patch the instruction with the resolved operand. Elf relocation
3256 info will also be generated to take care of linker/loader fixups.
3257 The 68HC11 addresses only 64Kb, we are only concerned by 8 and 16-bit
3258 relocs. BFD_RELOC_8 is basically used for .page0 access (the linker
3259 will warn for overflows). BFD_RELOC_8_PCREL should not be generated
3260 because it's either resolved or turned out into non-relative insns (see
3261 relax table, bcc, bra, bsr transformations)
3263 The BFD_RELOC_32 is necessary for the support of --gstabs. */
3264 where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
3266 switch (fixP
->fx_r_type
)
3269 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
3273 case BFD_RELOC_M68HC11_24
:
3274 bfd_putb16 ((bfd_vma
) (value
& 0x0ffff), (unsigned char *) where
);
3275 ((bfd_byte
*) where
)[2] = ((value
>> 16) & 0x0ff);
3279 case BFD_RELOC_16_PCREL
:
3280 case BFD_RELOC_M68HC11_LO16
:
3281 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
3282 if (value
< -65537 || value
> 65535)
3283 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3284 _("Value out of 16-bit range."));
3287 case BFD_RELOC_M68HC11_HI8
:
3291 case BFD_RELOC_M68HC11_LO8
:
3293 case BFD_RELOC_M68HC11_PAGE
:
3295 bfd_putb8 ((bfd_vma
) value
, (unsigned char *) where
);
3297 ((bfd_byte
*) where
)[0] = (bfd_byte
) value
;
3300 case BFD_RELOC_8_PCREL
:
3302 bfd_putb8 ((bfd_vma
) value
, (unsigned char *) where
);
3304 ((bfd_byte
*) where
)[0] = (bfd_byte
) value
;
3306 if (value
< -128 || value
> 127)
3307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3308 _("Value %ld too large for 8-bit PC-relative branch."),
3312 case BFD_RELOC_M68HC11_3B
:
3313 if (value
<= 0 || value
> 8)
3314 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3315 _("Auto increment/decrement offset '%ld' is out of range."),
3322 where
[0] = where
[0] | (value
& 0x07);
3325 case BFD_RELOC_M68HC11_RL_JUMP
:
3326 case BFD_RELOC_M68HC11_RL_GROUP
:
3327 case BFD_RELOC_VTABLE_INHERIT
:
3328 case BFD_RELOC_VTABLE_ENTRY
:
3333 as_fatal (_("Line %d: unknown relocation type: 0x%x."),
3334 fixP
->fx_line
, fixP
->fx_r_type
);
3338 /* Set the ELF specific flags. */
3340 m68hc11_elf_final_processing ()
3342 if (current_architecture
& cpu6812s
)
3343 elf_flags
|= EF_M68HCS12_MACH
;
3344 elf_elfheader (stdoutput
)->e_flags
&= ~EF_M68HC11_ABI
;
3345 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;