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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 #include <ctype.h>
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 #if defined (OBJ_ELF)
31 #include "elf/m68k.h"
32 #endif
33
34 /* This string holds the chars that always start a comment. If the
35 pre-processor is disabled, these aren't very useful. The macro
36 tc_comment_chars points to this. We use this, rather than the
37 usual comment_chars, so that the --bitwise-or option will work. */
38 #if defined (TE_SVR4) || defined (TE_DELTA)
39 const char *m68k_comment_chars = "|#";
40 #else
41 const char *m68k_comment_chars = "|";
42 #endif
43
44 /* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47 /* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
49 #NO_APP at the beginning of its output. */
50 /* Also note that comments like this one will always work. */
51 const char line_comment_chars[] = "#*";
52
53 const char line_separator_chars[] = ";";
54
55 /* Chars that can be used to separate mant from exp in floating point nums */
56 CONST char EXP_CHARS[] = "eE";
57
58 /* Chars that mean this number is a floating point constant, as
59 in "0f12.456" or "0d1.2345e12". */
60
61 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
62
63 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
64 changed in read.c . Ideally it shouldn't have to know about it at all,
65 but nothing is ideal around here. */
66
67 const int md_reloc_size = 8; /* Size of relocation record */
68
69 /* Are we trying to generate PIC code? If so, absolute references
70 ought to be made into linkage table references or pc-relative
71 references. Not implemented. For ELF there are other means
72 to denote pic relocations. */
73 int flag_want_pic;
74
75 static int flag_short_refs; /* -l option */
76 static int flag_long_jumps; /* -S option */
77
78 #ifdef REGISTER_PREFIX_OPTIONAL
79 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
80 #else
81 int flag_reg_prefix_optional;
82 #endif
83
84 /* Whether --register-prefix-optional was used on the command line. */
85 static int reg_prefix_optional_seen;
86
87 /* The floating point coprocessor to use by default. */
88 static enum m68k_register m68k_float_copnum = COP1;
89
90 /* If this is non-zero, then references to number(%pc) will be taken
91 to refer to number, rather than to %pc + number. */
92 static int m68k_abspcadd;
93
94 /* If this is non-zero, then the quick forms of the move, add, and sub
95 instructions are used when possible. */
96 static int m68k_quick = 1;
97
98 /* If this is non-zero, then if the size is not specified for a base
99 or outer displacement, the assembler assumes that the size should
100 be 32 bits. */
101 static int m68k_rel32 = 1;
102
103 /* This is non-zero if m68k_rel32 was set from the command line. */
104 static int m68k_rel32_from_cmdline;
105
106 /* The default width to use for an index register when using a base
107 displacement. */
108 static enum m68k_size m68k_index_width_default = SIZE_LONG;
109
110 /* We want to warn if any text labels are misaligned. In order to get
111 the right line number, we need to record the line number for each
112 label. */
113
114 struct label_line
115 {
116 struct label_line *next;
117 symbolS *label;
118 char *file;
119 unsigned int line;
120 int text;
121 };
122
123 /* The list of labels. */
124
125 static struct label_line *labels;
126
127 /* The current label. */
128
129 static struct label_line *current_label;
130
131 /* Its an arbitrary name: This means I don't approve of it */
132 /* See flames below */
133 static struct obstack robyn;
134
135 #define TAB(x,y) (((x)<<2)+(y))
136 #define TABTYPE(xy) ((xy) >> 2)
137 #define BYTE 0
138 #define SHORT 1
139 #define LONG 2
140 #define SZ_UNDEF 3
141 #undef BRANCH
142 /* Case `g' except when BCC68000 is applicable. */
143 #define ABRANCH 1
144 /* Coprocessor branches. */
145 #define FBRANCH 2
146 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
147 supported on all cpus. Widens to 32-bit absolute. */
148 #define PCREL 3
149 /* For inserting an extra jmp instruction with long offset on 68000,
150 for expanding conditional branches. (Not bsr or bra.) Since the
151 68000 doesn't support 32-bit displacements for conditional
152 branches, we fake it by reversing the condition and branching
153 around a jmp with an absolute long operand. */
154 #define BCC68000 4
155 /* For the DBcc "instructions". If the displacement requires 32 bits,
156 the branch-around-a-jump game is played here too. */
157 #define DBCC 5
158 /* Not currently used? */
159 #define PCLEA 6
160 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
161 in 16 or 8 bits. */
162 #define PCINDEX 7
163
164 struct m68k_incant
165 {
166 const char *m_operands;
167 unsigned long m_opcode;
168 short m_opnum;
169 short m_codenum;
170 int m_arch;
171 struct m68k_incant *m_next;
172 };
173
174 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
175 #define gettwo(x) (((x)->m_opcode)&0xffff)
176
177 static const enum m68k_register m68000_control_regs[] = { 0 };
178 static const enum m68k_register m68010_control_regs[] = {
179 SFC, DFC, USP, VBR,
180 0
181 };
182 static const enum m68k_register m68020_control_regs[] = {
183 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
184 0
185 };
186 static const enum m68k_register m68040_control_regs[] = {
187 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
188 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
189 0
190 };
191 static const enum m68k_register m68060_control_regs[] = {
192 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
193 USP, VBR, URP, SRP, PCR,
194 0
195 };
196 static const enum m68k_register mcf_control_regs[] = {
197 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
198 RAMBAR0, RAMBAR1, MBAR,
199 0
200 };
201 #define cpu32_control_regs m68010_control_regs
202
203 static const enum m68k_register *control_regs;
204
205 /* internal form of a 68020 instruction */
206 struct m68k_it
207 {
208 const char *error;
209 const char *args; /* list of opcode info */
210 int numargs;
211
212 int numo; /* Number of shorts in opcode */
213 short opcode[11];
214
215 struct m68k_op operands[6];
216
217 int nexp; /* number of exprs in use */
218 struct m68k_exp exprs[4];
219
220 int nfrag; /* Number of frags we have to produce */
221 struct
222 {
223 int fragoff; /* Where in the current opcode the frag ends */
224 symbolS *fadd;
225 offsetT foff;
226 int fragty;
227 }
228 fragb[4];
229
230 int nrel; /* Num of reloc strucs in use */
231 struct
232 {
233 int n;
234 expressionS exp;
235 char wid;
236 char pcrel;
237 /* In a pc relative address the difference between the address
238 of the offset and the address that the offset is relative
239 to. This depends on the addressing mode. Basically this
240 is the value to put in the offset field to address the
241 first byte of the offset, without regarding the special
242 significance of some values (in the branch instruction, for
243 example). */
244 int pcrel_fix;
245 #ifdef OBJ_ELF
246 /* Whether this expression needs special pic relocation, and if
247 so, which. */
248 enum pic_relocation pic_reloc;
249 #endif
250 }
251 reloc[5]; /* Five is enough??? */
252 };
253
254 #define cpu_of_arch(x) ((x) & (m68000up|mcf))
255 #define float_of_arch(x) ((x) & mfloat)
256 #define mmu_of_arch(x) ((x) & mmmu)
257 #define arch_coldfire_p(x) (((x) & mcf) != 0)
258
259 /* Macros for determining if cpu supports a specific addressing mode */
260 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
261
262 static struct m68k_it the_ins; /* the instruction being assembled */
263
264 #define op(ex) ((ex)->exp.X_op)
265 #define adds(ex) ((ex)->exp.X_add_symbol)
266 #define subs(ex) ((ex)->exp.X_op_symbol)
267 #define offs(ex) ((ex)->exp.X_add_number)
268
269 /* Macros for adding things to the m68k_it struct */
270
271 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
272
273 /* Static functions. */
274
275 static void insop PARAMS ((int, const struct m68k_incant *));
276 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
277 static void add_frag PARAMS ((symbolS *, offsetT, int));
278
279 /* Like addword, but goes BEFORE general operands */
280 static void
281 insop (w, opcode)
282 int w;
283 const struct m68k_incant *opcode;
284 {
285 int z;
286 for(z=the_ins.numo;z>opcode->m_codenum;--z)
287 the_ins.opcode[z]=the_ins.opcode[z-1];
288 for(z=0;z<the_ins.nrel;z++)
289 the_ins.reloc[z].n+=2;
290 for (z = 0; z < the_ins.nfrag; z++)
291 the_ins.fragb[z].fragoff++;
292 the_ins.opcode[opcode->m_codenum]=w;
293 the_ins.numo++;
294 }
295
296 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
297 Blecch. */
298 static void
299 add_fix (width, exp, pc_rel, pc_fix)
300 int width;
301 struct m68k_exp *exp;
302 int pc_rel;
303 int pc_fix;
304 {
305 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
306 ? (the_ins.numo*2-1)
307 : (((width)=='b')
308 ? (the_ins.numo*2+1)
309 : (the_ins.numo*2)));
310 the_ins.reloc[the_ins.nrel].exp = exp->exp;
311 the_ins.reloc[the_ins.nrel].wid = width;
312 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
313 #ifdef OBJ_ELF
314 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
315 #endif
316 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
317 }
318
319 /* Cause an extra frag to be generated here, inserting up to 10 bytes
320 (that value is chosen in the frag_var call in md_assemble). TYPE
321 is the subtype of the frag to be generated; its primary type is
322 rs_machine_dependent.
323
324 The TYPE parameter is also used by md_convert_frag_1 and
325 md_estimate_size_before_relax. The appropriate type of fixup will
326 be emitted by md_convert_frag_1.
327
328 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
329 static void
330 add_frag (add, off, type)
331 symbolS *add;
332 offsetT off;
333 int type;
334 {
335 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
336 the_ins.fragb[the_ins.nfrag].fadd=add;
337 the_ins.fragb[the_ins.nfrag].foff=off;
338 the_ins.fragb[the_ins.nfrag++].fragty=type;
339 }
340
341 #define isvar(ex) \
342 (op (ex) != O_constant && op (ex) != O_big)
343
344 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
345 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
346 static void m68k_ip PARAMS ((char *));
347 static void insert_reg PARAMS ((const char *, int));
348 static void select_control_regs PARAMS ((void));
349 static void init_regtable PARAMS ((void));
350 static int reverse_16_bits PARAMS ((int in));
351 static int reverse_8_bits PARAMS ((int in));
352 static void install_gen_operand PARAMS ((int mode, int val));
353 static void install_operand PARAMS ((int mode, int val));
354 static void s_bss PARAMS ((int));
355 static void s_data1 PARAMS ((int));
356 static void s_data2 PARAMS ((int));
357 static void s_even PARAMS ((int));
358 static void s_proc PARAMS ((int));
359 static void mri_chip PARAMS ((void));
360 static void s_chip PARAMS ((int));
361 static void s_fopt PARAMS ((int));
362 static void s_opt PARAMS ((int));
363 static void s_reg PARAMS ((int));
364 static void s_restore PARAMS ((int));
365 static void s_save PARAMS ((int));
366 static void s_mri_if PARAMS ((int));
367 static void s_mri_else PARAMS ((int));
368 static void s_mri_endi PARAMS ((int));
369 static void s_mri_break PARAMS ((int));
370 static void s_mri_next PARAMS ((int));
371 static void s_mri_for PARAMS ((int));
372 static void s_mri_endf PARAMS ((int));
373 static void s_mri_repeat PARAMS ((int));
374 static void s_mri_until PARAMS ((int));
375 static void s_mri_while PARAMS ((int));
376 static void s_mri_endw PARAMS ((int));
377 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
378 static void md_convert_frag_1 PARAMS ((fragS *));
379
380 static int current_architecture;
381
382 struct m68k_cpu {
383 unsigned long arch;
384 const char *name;
385 int alias;
386 };
387
388 static const struct m68k_cpu archs[] = {
389 { m68000, "68000", 0 },
390 { m68010, "68010", 0 },
391 { m68020, "68020", 0 },
392 { m68030, "68030", 0 },
393 { m68040, "68040", 0 },
394 { m68060, "68060", 0 },
395 { cpu32, "cpu32", 0 },
396 { m68881, "68881", 0 },
397 { m68851, "68851", 0 },
398 { mcf5200, "5200", 0 },
399 { mcf5206e, "5206e", 0 },
400 { mcf5307, "5307", 0},
401 /* Aliases (effectively, so far as gas is concerned) for the above
402 cpus. */
403 { m68020, "68k", 1 },
404 { m68000, "68008", 1 },
405 { m68000, "68302", 1 },
406 { m68000, "68306", 1 },
407 { m68000, "68307", 1 },
408 { m68000, "68322", 1 },
409 { m68000, "68356", 1 },
410 { m68000, "68ec000", 1 },
411 { m68000, "68hc000", 1 },
412 { m68000, "68hc001", 1 },
413 { m68020, "68ec020", 1 },
414 { m68030, "68ec030", 1 },
415 { m68040, "68ec040", 1 },
416 { m68060, "68ec060", 1 },
417 { cpu32, "68330", 1 },
418 { cpu32, "68331", 1 },
419 { cpu32, "68332", 1 },
420 { cpu32, "68333", 1 },
421 { cpu32, "68334", 1 },
422 { cpu32, "68336", 1 },
423 { cpu32, "68340", 1 },
424 { cpu32, "68341", 1 },
425 { cpu32, "68349", 1 },
426 { cpu32, "68360", 1 },
427 { m68881, "68882", 1 },
428 { mcf5200, "5202", 1 },
429 { mcf5200, "5204", 1 },
430 { mcf5200, "5206", 1 },
431 };
432
433 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
434
435 /* BCC68000 is for patching in an extra jmp instruction for long offsets
436 on the 68000. The 68000 doesn't support long branches with branchs */
437
438 /* This table desribes how you change sizes for the various types of variable
439 size expressions. This version only supports two kinds. */
440
441 /* Note that calls to frag_var need to specify the maximum expansion
442 needed; this is currently 10 bytes for DBCC. */
443
444 /* The fields are:
445 How far Forward this mode will reach:
446 How far Backward this mode will reach:
447 How many bytes this mode will add to the size of the frag
448 Which mode to go to if the offset won't fit in this one
449 */
450 relax_typeS md_relax_table[] =
451 {
452 {1, 1, 0, 0}, /* First entries aren't used */
453 {1, 1, 0, 0}, /* For no good reason except */
454 {1, 1, 0, 0}, /* that the VAX doesn't either */
455 {1, 1, 0, 0},
456
457 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
458 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
459 {0, 0, 4, 0},
460 {1, 1, 0, 0},
461
462 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
463 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
464 {0, 0, 4, 0},
465 {1, 1, 0, 0},
466
467 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
468 {(32767), (-32768), 2, TAB (PCREL, LONG)},
469 {0, 0, 4, 0},
470 {1, 1, 0, 0},
471
472 {(127), (-128), 0, TAB (BCC68000, SHORT)},
473 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
474 {0, 0, 6, 0}, /* jmp long space */
475 {1, 1, 0, 0},
476
477 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
478 {(32767), (-32768), 2, TAB (DBCC, LONG)},
479 {0, 0, 10, 0}, /* bra/jmp long space */
480 {1, 1, 0, 0},
481
482 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
483 {32767, -32768, 2, TAB (PCLEA, LONG)},
484 {0, 0, 6, 0},
485 {1, 1, 0, 0},
486
487 /* For, e.g., jmp pcrel indexed. */
488 {125, -130, 0, TAB (PCINDEX, SHORT)},
489 {32765, -32770, 2, TAB (PCINDEX, LONG)},
490 {0, 0, 4, 0},
491 {1, 1, 0, 0},
492 };
493
494 /* These are the machine dependent pseudo-ops. These are included so
495 the assembler can work on the output from the SUN C compiler, which
496 generates these.
497 */
498
499 /* This table describes all the machine specific pseudo-ops the assembler
500 has to support. The fields are:
501 pseudo-op name without dot
502 function to call to execute this pseudo-op
503 Integer arg to pass to the function
504 */
505 const pseudo_typeS md_pseudo_table[] =
506 {
507 {"data1", s_data1, 0},
508 {"data2", s_data2, 0},
509 {"bss", s_bss, 0},
510 {"even", s_even, 0},
511 {"skip", s_space, 0},
512 {"proc", s_proc, 0},
513 #if defined (TE_SUN3) || defined (OBJ_ELF)
514 {"align", s_align_bytes, 0},
515 #endif
516 #ifdef OBJ_ELF
517 {"swbeg", s_ignore, 0},
518 #endif
519 {"extend", float_cons, 'x'},
520 {"ldouble", float_cons, 'x'},
521
522 /* The following pseudo-ops are supported for MRI compatibility. */
523 {"chip", s_chip, 0},
524 {"comline", s_space, 1},
525 {"fopt", s_fopt, 0},
526 {"mask2", s_ignore, 0},
527 {"opt", s_opt, 0},
528 {"reg", s_reg, 0},
529 {"restore", s_restore, 0},
530 {"save", s_save, 0},
531
532 {"if", s_mri_if, 0},
533 {"if.b", s_mri_if, 'b'},
534 {"if.w", s_mri_if, 'w'},
535 {"if.l", s_mri_if, 'l'},
536 {"else", s_mri_else, 0},
537 {"else.s", s_mri_else, 's'},
538 {"else.l", s_mri_else, 'l'},
539 {"endi", s_mri_endi, 0},
540 {"break", s_mri_break, 0},
541 {"break.s", s_mri_break, 's'},
542 {"break.l", s_mri_break, 'l'},
543 {"next", s_mri_next, 0},
544 {"next.s", s_mri_next, 's'},
545 {"next.l", s_mri_next, 'l'},
546 {"for", s_mri_for, 0},
547 {"for.b", s_mri_for, 'b'},
548 {"for.w", s_mri_for, 'w'},
549 {"for.l", s_mri_for, 'l'},
550 {"endf", s_mri_endf, 0},
551 {"repeat", s_mri_repeat, 0},
552 {"until", s_mri_until, 0},
553 {"until.b", s_mri_until, 'b'},
554 {"until.w", s_mri_until, 'w'},
555 {"until.l", s_mri_until, 'l'},
556 {"while", s_mri_while, 0},
557 {"while.b", s_mri_while, 'b'},
558 {"while.w", s_mri_while, 'w'},
559 {"while.l", s_mri_while, 'l'},
560 {"endw", s_mri_endw, 0},
561
562 {0, 0, 0}
563 };
564
565
566 /* The mote pseudo ops are put into the opcode table, since they
567 don't start with a . they look like opcodes to gas.
568 */
569
570 #ifdef M68KCOFF
571 extern void obj_coff_section PARAMS ((int));
572 #endif
573
574 CONST pseudo_typeS mote_pseudo_table[] =
575 {
576
577 {"dcl", cons, 4},
578 {"dc", cons, 2},
579 {"dcw", cons, 2},
580 {"dcb", cons, 1},
581
582 {"dsl", s_space, 4},
583 {"ds", s_space, 2},
584 {"dsw", s_space, 2},
585 {"dsb", s_space, 1},
586
587 {"xdef", s_globl, 0},
588 #ifdef OBJ_ELF
589 {"align", s_align_bytes, 0},
590 #else
591 {"align", s_align_ptwo, 0},
592 #endif
593 #ifdef M68KCOFF
594 {"sect", obj_coff_section, 0},
595 {"section", obj_coff_section, 0},
596 #endif
597 {0, 0, 0}
598 };
599
600 #define issbyte(x) ((x)>=-128 && (x)<=127)
601 #define isubyte(x) ((x)>=0 && (x)<=255)
602 #define issword(x) ((x)>=-32768 && (x)<=32767)
603 #define isuword(x) ((x)>=0 && (x)<=65535)
604
605 #define isbyte(x) ((x)>= -255 && (x)<=255)
606 #define isword(x) ((x)>=-65536 && (x)<=65535)
607 #define islong(x) (1)
608
609 extern char *input_line_pointer;
610
611 static char mklower_table[256];
612 #define mklower(c) (mklower_table[(unsigned char)(c)])
613 static char notend_table[256];
614 static char alt_notend_table[256];
615 #define notend(s) \
616 (! (notend_table[(unsigned char) *s] \
617 || (*s == ':' \
618 && alt_notend_table[(unsigned char) s[1]])))
619
620 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
621
622 #ifdef NO_PCREL_RELOCS
623
624 int
625 make_pcrel_absolute(fixP, add_number)
626 fixS *fixP;
627 long *add_number;
628 {
629 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
630
631 /* rewrite the PC relative instructions to absolute address ones.
632 * these are rumoured to be faster, and the apollo linker refuses
633 * to deal with the PC relative relocations.
634 */
635 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
636 {
637 opcode[0] = 0x4e;
638 opcode[1] = 0xf9;
639 }
640 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
641 {
642 opcode[0] = 0x4e;
643 opcode[1] = 0xb9;
644 }
645 else
646 as_fatal (_("Unknown PC relative instruction"));
647 *add_number -= 4;
648 return 0;
649 }
650
651 #endif /* NO_PCREL_RELOCS */
652
653 short
654 tc_coff_fix2rtype (fixP)
655 fixS *fixP;
656 {
657 if (fixP->fx_tcbit && fixP->fx_size == 4)
658 return R_RELLONG_NEG;
659 #ifdef NO_PCREL_RELOCS
660 know (fixP->fx_pcrel == 0);
661 return (fixP->fx_size == 1 ? R_RELBYTE
662 : fixP->fx_size == 2 ? R_DIR16
663 : R_DIR32);
664 #else
665 return (fixP->fx_pcrel ?
666 (fixP->fx_size == 1 ? R_PCRBYTE :
667 fixP->fx_size == 2 ? R_PCRWORD :
668 R_PCRLONG) :
669 (fixP->fx_size == 1 ? R_RELBYTE :
670 fixP->fx_size == 2 ? R_RELWORD :
671 R_RELLONG));
672 #endif
673 }
674
675 #endif
676
677 #ifdef OBJ_ELF
678
679 /* Compute the relocation code for a fixup of SIZE bytes, using pc
680 relative relocation if PCREL is non-zero. PIC says whether a special
681 pic relocation was requested. */
682
683 static bfd_reloc_code_real_type get_reloc_code
684 PARAMS ((int, int, enum pic_relocation));
685
686 static bfd_reloc_code_real_type
687 get_reloc_code (size, pcrel, pic)
688 int size;
689 int pcrel;
690 enum pic_relocation pic;
691 {
692 switch (pic)
693 {
694 case pic_got_pcrel:
695 switch (size)
696 {
697 case 1:
698 return BFD_RELOC_8_GOT_PCREL;
699 case 2:
700 return BFD_RELOC_16_GOT_PCREL;
701 case 4:
702 return BFD_RELOC_32_GOT_PCREL;
703 }
704 break;
705
706 case pic_got_off:
707 switch (size)
708 {
709 case 1:
710 return BFD_RELOC_8_GOTOFF;
711 case 2:
712 return BFD_RELOC_16_GOTOFF;
713 case 4:
714 return BFD_RELOC_32_GOTOFF;
715 }
716 break;
717
718 case pic_plt_pcrel:
719 switch (size)
720 {
721 case 1:
722 return BFD_RELOC_8_PLT_PCREL;
723 case 2:
724 return BFD_RELOC_16_PLT_PCREL;
725 case 4:
726 return BFD_RELOC_32_PLT_PCREL;
727 }
728 break;
729
730 case pic_plt_off:
731 switch (size)
732 {
733 case 1:
734 return BFD_RELOC_8_PLTOFF;
735 case 2:
736 return BFD_RELOC_16_PLTOFF;
737 case 4:
738 return BFD_RELOC_32_PLTOFF;
739 }
740 break;
741
742 case pic_none:
743 if (pcrel)
744 {
745 switch (size)
746 {
747 case 1:
748 return BFD_RELOC_8_PCREL;
749 case 2:
750 return BFD_RELOC_16_PCREL;
751 case 4:
752 return BFD_RELOC_32_PCREL;
753 }
754 }
755 else
756 {
757 switch (size)
758 {
759 case 1:
760 return BFD_RELOC_8;
761 case 2:
762 return BFD_RELOC_16;
763 case 4:
764 return BFD_RELOC_32;
765 }
766 }
767 }
768
769 if (pcrel)
770 {
771 if (pic == pic_none)
772 as_bad (_("Can not do %d byte pc-relative relocation"), size);
773 else
774 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
775 }
776 else
777 {
778 if (pic == pic_none)
779 as_bad (_("Can not do %d byte relocation"), size);
780 else
781 as_bad (_("Can not do %d byte pic relocation"), size);
782 }
783
784 return BFD_RELOC_NONE;
785 }
786
787 /* Here we decide which fixups can be adjusted to make them relative
788 to the beginning of the section instead of the symbol. Basically
789 we need to make sure that the dynamic relocations are done
790 correctly, so in some cases we force the original symbol to be
791 used. */
792 int
793 tc_m68k_fix_adjustable (fixP)
794 fixS *fixP;
795 {
796 /* Prevent all adjustments to global symbols. */
797 if (S_IS_EXTERNAL (fixP->fx_addsy)
798 || S_IS_WEAK (fixP->fx_addsy))
799 return 0;
800
801 /* adjust_reloc_syms doesn't know about the GOT */
802 switch (fixP->fx_r_type)
803 {
804 case BFD_RELOC_8_GOT_PCREL:
805 case BFD_RELOC_16_GOT_PCREL:
806 case BFD_RELOC_32_GOT_PCREL:
807 case BFD_RELOC_8_GOTOFF:
808 case BFD_RELOC_16_GOTOFF:
809 case BFD_RELOC_32_GOTOFF:
810 case BFD_RELOC_8_PLT_PCREL:
811 case BFD_RELOC_16_PLT_PCREL:
812 case BFD_RELOC_32_PLT_PCREL:
813 case BFD_RELOC_8_PLTOFF:
814 case BFD_RELOC_16_PLTOFF:
815 case BFD_RELOC_32_PLTOFF:
816 return 0;
817
818 case BFD_RELOC_VTABLE_INHERIT:
819 case BFD_RELOC_VTABLE_ENTRY:
820 return 0;
821
822 default:
823 return 1;
824 }
825 }
826
827 #else /* !OBJ_ELF */
828
829 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
830
831 #endif /* OBJ_ELF */
832
833 #ifdef BFD_ASSEMBLER
834
835 arelent *
836 tc_gen_reloc (section, fixp)
837 asection *section;
838 fixS *fixp;
839 {
840 arelent *reloc;
841 bfd_reloc_code_real_type code;
842
843 if (fixp->fx_tcbit)
844 abort ();
845
846 if (fixp->fx_r_type != BFD_RELOC_NONE)
847 {
848 code = fixp->fx_r_type;
849
850 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
851 that fixup_segment converted a non-PC relative reloc into a
852 PC relative reloc. In such a case, we need to convert the
853 reloc code. */
854 if (fixp->fx_pcrel)
855 {
856 switch (code)
857 {
858 case BFD_RELOC_8:
859 code = BFD_RELOC_8_PCREL;
860 break;
861 case BFD_RELOC_16:
862 code = BFD_RELOC_16_PCREL;
863 break;
864 case BFD_RELOC_32:
865 code = BFD_RELOC_32_PCREL;
866 break;
867 case BFD_RELOC_8_PCREL:
868 case BFD_RELOC_16_PCREL:
869 case BFD_RELOC_32_PCREL:
870 case BFD_RELOC_8_GOT_PCREL:
871 case BFD_RELOC_16_GOT_PCREL:
872 case BFD_RELOC_32_GOT_PCREL:
873 case BFD_RELOC_8_GOTOFF:
874 case BFD_RELOC_16_GOTOFF:
875 case BFD_RELOC_32_GOTOFF:
876 case BFD_RELOC_8_PLT_PCREL:
877 case BFD_RELOC_16_PLT_PCREL:
878 case BFD_RELOC_32_PLT_PCREL:
879 case BFD_RELOC_8_PLTOFF:
880 case BFD_RELOC_16_PLTOFF:
881 case BFD_RELOC_32_PLTOFF:
882 break;
883 default:
884 as_bad_where (fixp->fx_file, fixp->fx_line,
885 _("Cannot make %s relocation PC relative"),
886 bfd_get_reloc_code_name (code));
887 }
888 }
889 }
890 else
891 {
892 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
893 switch (F (fixp->fx_size, fixp->fx_pcrel))
894 {
895 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
896 MAP (1, 0, BFD_RELOC_8);
897 MAP (2, 0, BFD_RELOC_16);
898 MAP (4, 0, BFD_RELOC_32);
899 MAP (1, 1, BFD_RELOC_8_PCREL);
900 MAP (2, 1, BFD_RELOC_16_PCREL);
901 MAP (4, 1, BFD_RELOC_32_PCREL);
902 default:
903 abort ();
904 }
905 }
906 #undef F
907 #undef MAP
908
909 reloc = (arelent *) xmalloc (sizeof (arelent));
910 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
911 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
912 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
913 #ifndef OBJ_ELF
914 if (fixp->fx_pcrel)
915 reloc->addend = fixp->fx_addnumber;
916 else
917 reloc->addend = 0;
918 #else
919 if (!fixp->fx_pcrel)
920 reloc->addend = fixp->fx_addnumber;
921 else
922 reloc->addend = (section->vma
923 + (fixp->fx_pcrel_adjust == 64
924 ? -1 : fixp->fx_pcrel_adjust)
925 + fixp->fx_addnumber
926 + md_pcrel_from (fixp));
927 #endif
928
929 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
930 assert (reloc->howto != 0);
931
932 return reloc;
933 }
934
935 #endif /* BFD_ASSEMBLER */
936
937 /* Return zero if the reference to SYMBOL from within the same segment may
938 be relaxed. */
939 #ifdef OBJ_ELF
940
941 /* On an ELF system, we can't relax an externally visible symbol,
942 because it may be overridden by a shared library. However, if
943 TARGET_OS is "elf", then we presume that we are assembling for an
944 embedded system, in which case we don't have to worry about shared
945 libraries, and we can relax anything. */
946
947 #define relaxable_symbol(symbol) \
948 (strcmp (TARGET_OS, "elf") == 0 \
949 || (! S_IS_EXTERNAL (symbol) \
950 && ! S_IS_WEAK (symbol)))
951
952 #else
953
954 #define relaxable_symbol(symbol) 1
955
956 #endif
957
958 /* Handle of the OPCODE hash table. NULL means any use before
959 m68k_ip_begin() will crash. */
960 static struct hash_control *op_hash;
961 \f
962 /* Assemble an m68k instruction. */
963
964 static void
965 m68k_ip (instring)
966 char *instring;
967 {
968 register char *p;
969 register struct m68k_op *opP;
970 register const struct m68k_incant *opcode;
971 register const char *s;
972 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
973 char *pdot, *pdotmove;
974 enum m68k_size siz1, siz2;
975 char c;
976 int losing;
977 int opsfound;
978 LITTLENUM_TYPE words[6];
979 LITTLENUM_TYPE *wordp;
980 unsigned long ok_arch = 0;
981
982 if (*instring == ' ')
983 instring++; /* skip leading whitespace */
984
985 /* Scan up to end of operation-code, which MUST end in end-of-string
986 or exactly 1 space. */
987 pdot = 0;
988 for (p = instring; *p != '\0'; p++)
989 {
990 if (*p == ' ')
991 break;
992 if (*p == '.')
993 pdot = p;
994 }
995
996 if (p == instring)
997 {
998 the_ins.error = _("No operator");
999 return;
1000 }
1001
1002 /* p now points to the end of the opcode name, probably whitespace.
1003 Make sure the name is null terminated by clobbering the
1004 whitespace, look it up in the hash table, then fix it back.
1005 Remove a dot, first, since the opcode tables have none. */
1006 if (pdot != NULL)
1007 {
1008 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1009 *pdotmove = pdotmove[1];
1010 p--;
1011 }
1012
1013 c = *p;
1014 *p = '\0';
1015 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1016 *p = c;
1017
1018 if (pdot != NULL)
1019 {
1020 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1021 *pdotmove = pdotmove[-1];
1022 *pdot = '.';
1023 ++p;
1024 }
1025
1026 if (opcode == NULL)
1027 {
1028 the_ins.error = _("Unknown operator");
1029 return;
1030 }
1031
1032 /* found a legitimate opcode, start matching operands */
1033 while (*p == ' ')
1034 ++p;
1035
1036 if (opcode->m_operands == 0)
1037 {
1038 char *old = input_line_pointer;
1039 *old = '\n';
1040 input_line_pointer = p;
1041 /* Ahh - it's a motorola style psuedo op */
1042 mote_pseudo_table[opcode->m_opnum].poc_handler
1043 (mote_pseudo_table[opcode->m_opnum].poc_val);
1044 input_line_pointer = old;
1045 *old = 0;
1046
1047 return;
1048 }
1049
1050 if (flag_mri && opcode->m_opnum == 0)
1051 {
1052 /* In MRI mode, random garbage is allowed after an instruction
1053 which accepts no operands. */
1054 the_ins.args = opcode->m_operands;
1055 the_ins.numargs = opcode->m_opnum;
1056 the_ins.numo = opcode->m_codenum;
1057 the_ins.opcode[0] = getone (opcode);
1058 the_ins.opcode[1] = gettwo (opcode);
1059 return;
1060 }
1061
1062 for (opP = &the_ins.operands[0]; *p; opP++)
1063 {
1064 p = crack_operand (p, opP);
1065
1066 if (opP->error)
1067 {
1068 the_ins.error = opP->error;
1069 return;
1070 }
1071 }
1072
1073 opsfound = opP - &the_ins.operands[0];
1074
1075 /* This ugly hack is to support the floating pt opcodes in their
1076 standard form. Essentially, we fake a first enty of type COP#1 */
1077 if (opcode->m_operands[0] == 'I')
1078 {
1079 int n;
1080
1081 for (n = opsfound; n > 0; --n)
1082 the_ins.operands[n] = the_ins.operands[n - 1];
1083
1084 memset ((char *) (&the_ins.operands[0]), '\0',
1085 sizeof (the_ins.operands[0]));
1086 the_ins.operands[0].mode = CONTROL;
1087 the_ins.operands[0].reg = m68k_float_copnum;
1088 opsfound++;
1089 }
1090
1091 /* We've got the operands. Find an opcode that'll accept them */
1092 for (losing = 0;;)
1093 {
1094 /* If we didn't get the right number of ops, or we have no
1095 common model with this pattern then reject this pattern. */
1096
1097 ok_arch |= opcode->m_arch;
1098 if (opsfound != opcode->m_opnum
1099 || ((opcode->m_arch & current_architecture) == 0))
1100 ++losing;
1101 else
1102 {
1103 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1104 *s && !losing;
1105 s += 2, opP++)
1106 {
1107 /* Warning: this switch is huge! */
1108 /* I've tried to organize the cases into this order:
1109 non-alpha first, then alpha by letter. Lower-case
1110 goes directly before uppercase counterpart. */
1111 /* Code with multiple case ...: gets sorted by the lowest
1112 case ... it belongs to. I hope this makes sense. */
1113 switch (*s)
1114 {
1115 case '!':
1116 switch (opP->mode)
1117 {
1118 case IMMED:
1119 case DREG:
1120 case AREG:
1121 case FPREG:
1122 case CONTROL:
1123 case AINC:
1124 case ADEC:
1125 case REGLST:
1126 losing++;
1127 break;
1128 default:
1129 break;
1130 }
1131 break;
1132
1133 case '<':
1134 switch (opP->mode)
1135 {
1136 case DREG:
1137 case AREG:
1138 case FPREG:
1139 case CONTROL:
1140 case IMMED:
1141 case ADEC:
1142 case REGLST:
1143 losing++;
1144 break;
1145 default:
1146 break;
1147 }
1148 break;
1149
1150 case '>':
1151 switch (opP->mode)
1152 {
1153 case DREG:
1154 case AREG:
1155 case FPREG:
1156 case CONTROL:
1157 case IMMED:
1158 case AINC:
1159 case REGLST:
1160 losing++;
1161 break;
1162 case ABSL:
1163 break;
1164 default:
1165 if (opP->reg == PC
1166 || opP->reg == ZPC)
1167 losing++;
1168 break;
1169 }
1170 break;
1171
1172 case 'm':
1173 switch (opP->mode)
1174 {
1175 case DREG:
1176 case AREG:
1177 case AINDR:
1178 case AINC:
1179 case ADEC:
1180 break;
1181 default:
1182 losing++;
1183 }
1184 break;
1185
1186 case 'n':
1187 switch (opP->mode)
1188 {
1189 case DISP:
1190 break;
1191 default:
1192 losing++;
1193 }
1194 break;
1195
1196 case 'o':
1197 switch (opP->mode)
1198 {
1199 case BASE:
1200 case ABSL:
1201 case IMMED:
1202 break;
1203 default:
1204 losing++;
1205 }
1206 break;
1207
1208 case 'p':
1209 switch (opP->mode)
1210 {
1211 case DREG:
1212 case AREG:
1213 case AINDR:
1214 case AINC:
1215 case ADEC:
1216 break;
1217 case DISP:
1218 if (opP->reg == PC || opP->reg == ZPC)
1219 losing++;
1220 break;
1221 default:
1222 losing++;
1223 }
1224 break;
1225
1226 case 'q':
1227 switch (opP->mode)
1228 {
1229 case DREG:
1230 case AINDR:
1231 case AINC:
1232 case ADEC:
1233 break;
1234 case DISP:
1235 if (opP->reg == PC || opP->reg == ZPC)
1236 losing++;
1237 break;
1238 default:
1239 losing++;
1240 break;
1241 }
1242 break;
1243
1244 case 'v':
1245 switch (opP->mode)
1246 {
1247 case DREG:
1248 case AINDR:
1249 case AINC:
1250 case ADEC:
1251 case ABSL:
1252 break;
1253 case DISP:
1254 if (opP->reg == PC || opP->reg == ZPC)
1255 losing++;
1256 break;
1257 default:
1258 losing++;
1259 break;
1260 }
1261 break;
1262
1263 case '#':
1264 if (opP->mode != IMMED)
1265 losing++;
1266 else if (s[1] == 'b'
1267 && ! isvar (&opP->disp)
1268 && (opP->disp.exp.X_op != O_constant
1269 || ! isbyte (opP->disp.exp.X_add_number)))
1270 losing++;
1271 else if (s[1] == 'B'
1272 && ! isvar (&opP->disp)
1273 && (opP->disp.exp.X_op != O_constant
1274 || ! issbyte (opP->disp.exp.X_add_number)))
1275 losing++;
1276 else if (s[1] == 'w'
1277 && ! isvar (&opP->disp)
1278 && (opP->disp.exp.X_op != O_constant
1279 || ! isword (opP->disp.exp.X_add_number)))
1280 losing++;
1281 else if (s[1] == 'W'
1282 && ! isvar (&opP->disp)
1283 && (opP->disp.exp.X_op != O_constant
1284 || ! issword (opP->disp.exp.X_add_number)))
1285 losing++;
1286 break;
1287
1288 case '^':
1289 case 'T':
1290 if (opP->mode != IMMED)
1291 losing++;
1292 break;
1293
1294 case '$':
1295 if (opP->mode == AREG
1296 || opP->mode == CONTROL
1297 || opP->mode == FPREG
1298 || opP->mode == IMMED
1299 || opP->mode == REGLST
1300 || (opP->mode != ABSL
1301 && (opP->reg == PC
1302 || opP->reg == ZPC)))
1303 losing++;
1304 break;
1305
1306 case '%':
1307 if (opP->mode == CONTROL
1308 || opP->mode == FPREG
1309 || opP->mode == REGLST
1310 || opP->mode == IMMED
1311 || (opP->mode != ABSL
1312 && (opP->reg == PC
1313 || opP->reg == ZPC)))
1314 losing++;
1315 break;
1316
1317 case '&':
1318 switch (opP->mode)
1319 {
1320 case DREG:
1321 case AREG:
1322 case FPREG:
1323 case CONTROL:
1324 case IMMED:
1325 case AINC:
1326 case ADEC:
1327 case REGLST:
1328 losing++;
1329 break;
1330 case ABSL:
1331 break;
1332 default:
1333 if (opP->reg == PC
1334 || opP->reg == ZPC)
1335 losing++;
1336 break;
1337 }
1338 break;
1339
1340 case '*':
1341 if (opP->mode == CONTROL
1342 || opP->mode == FPREG
1343 || opP->mode == REGLST)
1344 losing++;
1345 break;
1346
1347 case '+':
1348 if (opP->mode != AINC)
1349 losing++;
1350 break;
1351
1352 case '-':
1353 if (opP->mode != ADEC)
1354 losing++;
1355 break;
1356
1357 case '/':
1358 switch (opP->mode)
1359 {
1360 case AREG:
1361 case CONTROL:
1362 case FPREG:
1363 case AINC:
1364 case ADEC:
1365 case IMMED:
1366 case REGLST:
1367 losing++;
1368 break;
1369 default:
1370 break;
1371 }
1372 break;
1373
1374 case ';':
1375 switch (opP->mode)
1376 {
1377 case AREG:
1378 case CONTROL:
1379 case FPREG:
1380 case REGLST:
1381 losing++;
1382 break;
1383 default:
1384 break;
1385 }
1386 break;
1387
1388 case '?':
1389 switch (opP->mode)
1390 {
1391 case AREG:
1392 case CONTROL:
1393 case FPREG:
1394 case AINC:
1395 case ADEC:
1396 case IMMED:
1397 case REGLST:
1398 losing++;
1399 break;
1400 case ABSL:
1401 break;
1402 default:
1403 if (opP->reg == PC || opP->reg == ZPC)
1404 losing++;
1405 break;
1406 }
1407 break;
1408
1409 case '@':
1410 switch (opP->mode)
1411 {
1412 case AREG:
1413 case CONTROL:
1414 case FPREG:
1415 case IMMED:
1416 case REGLST:
1417 losing++;
1418 break;
1419 default:
1420 break;
1421 }
1422 break;
1423
1424 case '~': /* For now! (JF FOO is this right?) */
1425 switch (opP->mode)
1426 {
1427 case DREG:
1428 case AREG:
1429 case CONTROL:
1430 case FPREG:
1431 case IMMED:
1432 case REGLST:
1433 losing++;
1434 break;
1435 case ABSL:
1436 break;
1437 default:
1438 if (opP->reg == PC
1439 || opP->reg == ZPC)
1440 losing++;
1441 break;
1442 }
1443 break;
1444
1445 case '3':
1446 if (opP->mode != CONTROL
1447 || (opP->reg != TT0 && opP->reg != TT1))
1448 losing++;
1449 break;
1450
1451 case 'A':
1452 if (opP->mode != AREG)
1453 losing++;
1454 break;
1455
1456 case 'a':
1457 if (opP->mode != AINDR)
1458 ++losing;
1459 break;
1460
1461 case 'B': /* FOO */
1462 if (opP->mode != ABSL
1463 || (flag_long_jumps
1464 && strncmp (instring, "jbsr", 4) == 0))
1465 losing++;
1466 break;
1467
1468 case 'C':
1469 if (opP->mode != CONTROL || opP->reg != CCR)
1470 losing++;
1471 break;
1472
1473 case 'd':
1474 if (opP->mode != DISP
1475 || opP->reg < ADDR0
1476 || opP->reg > ADDR7)
1477 losing++;
1478 break;
1479
1480 case 'D':
1481 if (opP->mode != DREG)
1482 losing++;
1483 break;
1484
1485 case 'E':
1486 if (opP->reg != ACC)
1487 losing++;
1488 break;
1489
1490 case 'F':
1491 if (opP->mode != FPREG)
1492 losing++;
1493 break;
1494
1495 case 'G':
1496 if (opP->reg != MACSR)
1497 losing++;
1498 break;
1499
1500 case 'H':
1501 if (opP->reg != MASK)
1502 losing++;
1503 break;
1504
1505 case 'I':
1506 if (opP->mode != CONTROL
1507 || opP->reg < COP0
1508 || opP->reg > COP7)
1509 losing++;
1510 break;
1511
1512 case 'J':
1513 if (opP->mode != CONTROL
1514 || opP->reg < USP
1515 || opP->reg > last_movec_reg)
1516 losing++;
1517 else
1518 {
1519 const enum m68k_register *rp;
1520 for (rp = control_regs; *rp; rp++)
1521 if (*rp == opP->reg)
1522 break;
1523 if (*rp == 0)
1524 losing++;
1525 }
1526 break;
1527
1528 case 'k':
1529 if (opP->mode != IMMED)
1530 losing++;
1531 break;
1532
1533 case 'l':
1534 case 'L':
1535 if (opP->mode == DREG
1536 || opP->mode == AREG
1537 || opP->mode == FPREG)
1538 {
1539 if (s[1] == '8')
1540 losing++;
1541 else
1542 {
1543 switch (opP->mode)
1544 {
1545 case DREG:
1546 opP->mask = 1 << (opP->reg - DATA0);
1547 break;
1548 case AREG:
1549 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1550 break;
1551 case FPREG:
1552 opP->mask = 1 << (opP->reg - FP0 + 16);
1553 break;
1554 default:
1555 abort ();
1556 }
1557 opP->mode = REGLST;
1558 }
1559 }
1560 else if (opP->mode == CONTROL)
1561 {
1562 if (s[1] != '8')
1563 losing++;
1564 else
1565 {
1566 switch (opP->reg)
1567 {
1568 case FPI:
1569 opP->mask = 1 << 24;
1570 break;
1571 case FPS:
1572 opP->mask = 1 << 25;
1573 break;
1574 case FPC:
1575 opP->mask = 1 << 26;
1576 break;
1577 default:
1578 losing++;
1579 break;
1580 }
1581 opP->mode = REGLST;
1582 }
1583 }
1584 else if (opP->mode != REGLST)
1585 losing++;
1586 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1587 losing++;
1588 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1589 losing++;
1590 break;
1591
1592 case 'M':
1593 if (opP->mode != IMMED)
1594 losing++;
1595 else if (opP->disp.exp.X_op != O_constant
1596 || ! issbyte (opP->disp.exp.X_add_number))
1597 losing++;
1598 else if (! m68k_quick
1599 && instring[3] != 'q'
1600 && instring[4] != 'q')
1601 losing++;
1602 break;
1603
1604 case 'O':
1605 if (opP->mode != DREG
1606 && opP->mode != IMMED
1607 && opP->mode != ABSL)
1608 losing++;
1609 break;
1610
1611 case 'Q':
1612 if (opP->mode != IMMED)
1613 losing++;
1614 else if (opP->disp.exp.X_op != O_constant
1615 || opP->disp.exp.X_add_number < 1
1616 || opP->disp.exp.X_add_number > 8)
1617 losing++;
1618 else if (! m68k_quick
1619 && (strncmp (instring, "add", 3) == 0
1620 || strncmp (instring, "sub", 3) == 0)
1621 && instring[3] != 'q')
1622 losing++;
1623 break;
1624
1625 case 'R':
1626 if (opP->mode != DREG && opP->mode != AREG)
1627 losing++;
1628 break;
1629
1630 case 'r':
1631 if (opP->mode != AINDR
1632 && (opP->mode != BASE
1633 || (opP->reg != 0
1634 && opP->reg != ZADDR0)
1635 || opP->disp.exp.X_op != O_absent
1636 || ((opP->index.reg < DATA0
1637 || opP->index.reg > DATA7)
1638 && (opP->index.reg < ADDR0
1639 || opP->index.reg > ADDR7))
1640 || opP->index.size != SIZE_UNSPEC
1641 || opP->index.scale != 1))
1642 losing++;
1643 break;
1644
1645 case 's':
1646 if (opP->mode != CONTROL
1647 || ! (opP->reg == FPI
1648 || opP->reg == FPS
1649 || opP->reg == FPC))
1650 losing++;
1651 break;
1652
1653 case 'S':
1654 if (opP->mode != CONTROL || opP->reg != SR)
1655 losing++;
1656 break;
1657
1658 case 't':
1659 if (opP->mode != IMMED)
1660 losing++;
1661 else if (opP->disp.exp.X_op != O_constant
1662 || opP->disp.exp.X_add_number < 0
1663 || opP->disp.exp.X_add_number > 7)
1664 losing++;
1665 break;
1666
1667 case 'U':
1668 if (opP->mode != CONTROL || opP->reg != USP)
1669 losing++;
1670 break;
1671
1672 /* JF these are out of order. We could put them
1673 in order if we were willing to put up with
1674 bunches of #ifdef m68851s in the code.
1675
1676 Don't forget that you need these operands
1677 to use 68030 MMU instructions. */
1678 #ifndef NO_68851
1679 /* Memory addressing mode used by pflushr */
1680 case '|':
1681 if (opP->mode == CONTROL
1682 || opP->mode == FPREG
1683 || opP->mode == DREG
1684 || opP->mode == AREG
1685 || opP->mode == REGLST)
1686 losing++;
1687 /* We should accept immediate operands, but they
1688 supposedly have to be quad word, and we don't
1689 handle that. I would like to see what a Motorola
1690 assembler does before doing something here. */
1691 if (opP->mode == IMMED)
1692 losing++;
1693 break;
1694
1695 case 'f':
1696 if (opP->mode != CONTROL
1697 || (opP->reg != SFC && opP->reg != DFC))
1698 losing++;
1699 break;
1700
1701 case '0':
1702 if (opP->mode != CONTROL || opP->reg != TC)
1703 losing++;
1704 break;
1705
1706 case '1':
1707 if (opP->mode != CONTROL || opP->reg != AC)
1708 losing++;
1709 break;
1710
1711 case '2':
1712 if (opP->mode != CONTROL
1713 || (opP->reg != CAL
1714 && opP->reg != VAL
1715 && opP->reg != SCC))
1716 losing++;
1717 break;
1718
1719 case 'V':
1720 if (opP->mode != CONTROL
1721 || opP->reg != VAL)
1722 losing++;
1723 break;
1724
1725 case 'W':
1726 if (opP->mode != CONTROL
1727 || (opP->reg != DRP
1728 && opP->reg != SRP
1729 && opP->reg != CRP))
1730 losing++;
1731 break;
1732
1733 case 'X':
1734 if (opP->mode != CONTROL
1735 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1736 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1737 losing++;
1738 break;
1739
1740 case 'Y':
1741 if (opP->mode != CONTROL || opP->reg != PSR)
1742 losing++;
1743 break;
1744
1745 case 'Z':
1746 if (opP->mode != CONTROL || opP->reg != PCSR)
1747 losing++;
1748 break;
1749 #endif
1750 case 'c':
1751 if (opP->mode != CONTROL
1752 || (opP->reg != NC
1753 && opP->reg != IC
1754 && opP->reg != DC
1755 && opP->reg != BC))
1756 {
1757 losing++;
1758 } /* not a cache specifier. */
1759 break;
1760
1761 case '_':
1762 if (opP->mode != ABSL)
1763 ++losing;
1764 break;
1765
1766 case 'u':
1767 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1768 losing++;
1769 /* FIXME: kludge instead of fixing parser:
1770 upper/lower registers are *not* CONTROL
1771 registers, but ordinary ones. */
1772 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1773 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1774 opP->mode = DREG;
1775 else
1776 opP->mode = AREG;
1777 break;
1778
1779 default:
1780 abort ();
1781 } /* switch on type of operand */
1782
1783 if (losing)
1784 break;
1785 } /* for each operand */
1786 } /* if immediately wrong */
1787
1788 if (!losing)
1789 {
1790 break;
1791 } /* got it. */
1792
1793 opcode = opcode->m_next;
1794
1795 if (!opcode)
1796 {
1797 if (ok_arch
1798 && !(ok_arch & current_architecture))
1799 {
1800 char buf[200], *cp;
1801
1802 strcpy (buf,
1803 _("invalid instruction for this architecture; needs "));
1804 cp = buf + strlen (buf);
1805 switch (ok_arch)
1806 {
1807 case mfloat:
1808 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1809 break;
1810 case mmmu:
1811 strcpy (cp, _("mmu (68030 or 68851)"));
1812 break;
1813 case m68020up:
1814 strcpy (cp, _("68020 or higher"));
1815 break;
1816 case m68000up:
1817 strcpy (cp, _("68000 or higher"));
1818 break;
1819 case m68010up:
1820 strcpy (cp, _("68010 or higher"));
1821 break;
1822 default:
1823 {
1824 int got_one = 0, idx;
1825 for (idx = 0;
1826 idx < (int) (sizeof (archs) / sizeof (archs[0]));
1827 idx++)
1828 {
1829 if ((archs[idx].arch & ok_arch)
1830 && ! archs[idx].alias)
1831 {
1832 if (got_one)
1833 {
1834 strcpy (cp, " or ");
1835 cp += strlen (cp);
1836 }
1837 got_one = 1;
1838 strcpy (cp, archs[idx].name);
1839 cp += strlen (cp);
1840 }
1841 }
1842 }
1843 }
1844 cp = xmalloc (strlen (buf) + 1);
1845 strcpy (cp, buf);
1846 the_ins.error = cp;
1847 }
1848 else
1849 the_ins.error = _("operands mismatch");
1850 return;
1851 } /* Fell off the end */
1852
1853 losing = 0;
1854 }
1855
1856 /* now assemble it */
1857
1858 the_ins.args = opcode->m_operands;
1859 the_ins.numargs = opcode->m_opnum;
1860 the_ins.numo = opcode->m_codenum;
1861 the_ins.opcode[0] = getone (opcode);
1862 the_ins.opcode[1] = gettwo (opcode);
1863
1864 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1865 {
1866 /* This switch is a doozy.
1867 Watch the first step; its a big one! */
1868 switch (s[0])
1869 {
1870
1871 case '*':
1872 case '~':
1873 case '%':
1874 case ';':
1875 case '@':
1876 case '!':
1877 case '&':
1878 case '$':
1879 case '?':
1880 case '/':
1881 case '<':
1882 case '>':
1883 case 'm':
1884 case 'n':
1885 case 'o':
1886 case 'p':
1887 case 'q':
1888 case 'v':
1889 #ifndef NO_68851
1890 case '|':
1891 #endif
1892 switch (opP->mode)
1893 {
1894 case IMMED:
1895 tmpreg = 0x3c; /* 7.4 */
1896 if (strchr ("bwl", s[1]))
1897 nextword = get_num (&opP->disp, 80);
1898 else
1899 nextword = get_num (&opP->disp, 0);
1900 if (isvar (&opP->disp))
1901 add_fix (s[1], &opP->disp, 0, 0);
1902 switch (s[1])
1903 {
1904 case 'b':
1905 if (!isbyte (nextword))
1906 opP->error = _("operand out of range");
1907 addword (nextword);
1908 baseo = 0;
1909 break;
1910 case 'w':
1911 if (!isword (nextword))
1912 opP->error = _("operand out of range");
1913 addword (nextword);
1914 baseo = 0;
1915 break;
1916 case 'W':
1917 if (!issword (nextword))
1918 opP->error = _("operand out of range");
1919 addword (nextword);
1920 baseo = 0;
1921 break;
1922 case 'l':
1923 addword (nextword >> 16);
1924 addword (nextword);
1925 baseo = 0;
1926 break;
1927
1928 case 'f':
1929 baseo = 2;
1930 outro = 8;
1931 break;
1932 case 'F':
1933 baseo = 4;
1934 outro = 11;
1935 break;
1936 case 'x':
1937 baseo = 6;
1938 outro = 15;
1939 break;
1940 case 'p':
1941 baseo = 6;
1942 outro = -1;
1943 break;
1944 default:
1945 abort ();
1946 }
1947 if (!baseo)
1948 break;
1949
1950 /* We gotta put out some float */
1951 if (op (&opP->disp) != O_big)
1952 {
1953 valueT val;
1954 int gencnt;
1955
1956 /* Can other cases happen here? */
1957 if (op (&opP->disp) != O_constant)
1958 abort ();
1959
1960 val = (valueT) offs (&opP->disp);
1961 gencnt = 0;
1962 do
1963 {
1964 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1965 val >>= LITTLENUM_NUMBER_OF_BITS;
1966 ++gencnt;
1967 }
1968 while (val != 0);
1969 offs (&opP->disp) = gencnt;
1970 }
1971 if (offs (&opP->disp) > 0)
1972 {
1973 if (offs (&opP->disp) > baseo)
1974 {
1975 as_warn (_("Bignum too big for %c format; truncated"),
1976 s[1]);
1977 offs (&opP->disp) = baseo;
1978 }
1979 baseo -= offs (&opP->disp);
1980 while (baseo--)
1981 addword (0);
1982 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1983 offs (&opP->disp)--;
1984 --wordp)
1985 addword (*wordp);
1986 break;
1987 }
1988 gen_to_words (words, baseo, (long) outro);
1989 for (wordp = words; baseo--; wordp++)
1990 addword (*wordp);
1991 break;
1992 case DREG:
1993 tmpreg = opP->reg - DATA; /* 0.dreg */
1994 break;
1995 case AREG:
1996 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1997 break;
1998 case AINDR:
1999 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2000 break;
2001 case ADEC:
2002 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2003 break;
2004 case AINC:
2005 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2006 break;
2007 case DISP:
2008
2009 nextword = get_num (&opP->disp, 80);
2010
2011 if (opP->reg == PC
2012 && ! isvar (&opP->disp)
2013 && m68k_abspcadd)
2014 {
2015 opP->disp.exp.X_op = O_symbol;
2016 #ifndef BFD_ASSEMBLER
2017 opP->disp.exp.X_add_symbol = &abs_symbol;
2018 #else
2019 opP->disp.exp.X_add_symbol =
2020 section_symbol (absolute_section);
2021 #endif
2022 }
2023
2024 /* Force into index mode. Hope this works */
2025
2026 /* We do the first bit for 32-bit displacements, and the
2027 second bit for 16 bit ones. It is possible that we
2028 should make the default be WORD instead of LONG, but
2029 I think that'd break GCC, so we put up with a little
2030 inefficiency for the sake of working output. */
2031
2032 if (!issword (nextword)
2033 || (isvar (&opP->disp)
2034 && ((opP->disp.size == SIZE_UNSPEC
2035 && flag_short_refs == 0
2036 && cpu_of_arch (current_architecture) >= m68020
2037 && ! arch_coldfire_p (current_architecture))
2038 || opP->disp.size == SIZE_LONG)))
2039 {
2040 if (cpu_of_arch (current_architecture) < m68020
2041 || arch_coldfire_p (current_architecture))
2042 opP->error =
2043 _("displacement too large for this architecture; needs 68020 or higher");
2044 if (opP->reg == PC)
2045 tmpreg = 0x3B; /* 7.3 */
2046 else
2047 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2048 if (isvar (&opP->disp))
2049 {
2050 if (opP->reg == PC)
2051 {
2052 if (opP->disp.size == SIZE_LONG
2053 #ifdef OBJ_ELF
2054 /* If the displacement needs pic
2055 relocation it cannot be relaxed. */
2056 || opP->disp.pic_reloc != pic_none
2057 #endif
2058 )
2059 {
2060 addword (0x0170);
2061 add_fix ('l', &opP->disp, 1, 2);
2062 }
2063 else
2064 {
2065 add_frag (adds (&opP->disp),
2066 offs (&opP->disp),
2067 TAB (PCLEA, SZ_UNDEF));
2068 break;
2069 }
2070 }
2071 else
2072 {
2073 addword (0x0170);
2074 add_fix ('l', &opP->disp, 0, 0);
2075 }
2076 }
2077 else
2078 addword (0x0170);
2079 addword (nextword >> 16);
2080 }
2081 else
2082 {
2083 if (opP->reg == PC)
2084 tmpreg = 0x3A; /* 7.2 */
2085 else
2086 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2087
2088 if (isvar (&opP->disp))
2089 {
2090 if (opP->reg == PC)
2091 {
2092 add_fix ('w', &opP->disp, 1, 0);
2093 }
2094 else
2095 add_fix ('w', &opP->disp, 0, 0);
2096 }
2097 }
2098 addword (nextword);
2099 break;
2100
2101 case POST:
2102 case PRE:
2103 case BASE:
2104 nextword = 0;
2105 baseo = get_num (&opP->disp, 80);
2106 if (opP->mode == POST || opP->mode == PRE)
2107 outro = get_num (&opP->odisp, 80);
2108 /* Figure out the `addressing mode'.
2109 Also turn on the BASE_DISABLE bit, if needed. */
2110 if (opP->reg == PC || opP->reg == ZPC)
2111 {
2112 tmpreg = 0x3b; /* 7.3 */
2113 if (opP->reg == ZPC)
2114 nextword |= 0x80;
2115 }
2116 else if (opP->reg == 0)
2117 {
2118 nextword |= 0x80;
2119 tmpreg = 0x30; /* 6.garbage */
2120 }
2121 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2122 {
2123 nextword |= 0x80;
2124 tmpreg = 0x30 + opP->reg - ZADDR0;
2125 }
2126 else
2127 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2128
2129 siz1 = opP->disp.size;
2130 if (opP->mode == POST || opP->mode == PRE)
2131 siz2 = opP->odisp.size;
2132 else
2133 siz2 = SIZE_UNSPEC;
2134
2135 /* Index register stuff */
2136 if (opP->index.reg != 0
2137 && opP->index.reg >= DATA
2138 && opP->index.reg <= ADDR7)
2139 {
2140 nextword |= (opP->index.reg - DATA) << 12;
2141
2142 if (opP->index.size == SIZE_LONG
2143 || (opP->index.size == SIZE_UNSPEC
2144 && m68k_index_width_default == SIZE_LONG))
2145 nextword |= 0x800;
2146
2147 if ((opP->index.scale != 1
2148 && cpu_of_arch (current_architecture) < m68020)
2149 || (opP->index.scale == 8
2150 && arch_coldfire_p (current_architecture)))
2151 {
2152 opP->error =
2153 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2154 }
2155
2156 if (arch_coldfire_p (current_architecture)
2157 && opP->index.size == SIZE_WORD)
2158 opP->error = _("invalid index size for coldfire");
2159
2160 switch (opP->index.scale)
2161 {
2162 case 1:
2163 break;
2164 case 2:
2165 nextword |= 0x200;
2166 break;
2167 case 4:
2168 nextword |= 0x400;
2169 break;
2170 case 8:
2171 nextword |= 0x600;
2172 break;
2173 default:
2174 abort ();
2175 }
2176 /* IF its simple,
2177 GET US OUT OF HERE! */
2178
2179 /* Must be INDEX, with an index register. Address
2180 register cannot be ZERO-PC, and either :b was
2181 forced, or we know it will fit. For a 68000 or
2182 68010, force this mode anyways, because the
2183 larger modes aren't supported. */
2184 if (opP->mode == BASE
2185 && ((opP->reg >= ADDR0
2186 && opP->reg <= ADDR7)
2187 || opP->reg == PC))
2188 {
2189 if (siz1 == SIZE_BYTE
2190 || cpu_of_arch (current_architecture) < m68020
2191 || arch_coldfire_p (current_architecture)
2192 || (siz1 == SIZE_UNSPEC
2193 && ! isvar (&opP->disp)
2194 && issbyte (baseo)))
2195 {
2196 nextword += baseo & 0xff;
2197 addword (nextword);
2198 if (isvar (&opP->disp))
2199 {
2200 /* Do a byte relocation. If it doesn't
2201 fit (possible on m68000) let the
2202 fixup processing complain later. */
2203 if (opP->reg == PC)
2204 add_fix ('B', &opP->disp, 1, 1);
2205 else
2206 add_fix ('B', &opP->disp, 0, 0);
2207 }
2208 else if (siz1 != SIZE_BYTE)
2209 {
2210 if (siz1 != SIZE_UNSPEC)
2211 as_warn (_("Forcing byte displacement"));
2212 if (! issbyte (baseo))
2213 opP->error = _("byte displacement out of range");
2214 }
2215
2216 break;
2217 }
2218 else if (siz1 == SIZE_UNSPEC
2219 && opP->reg == PC
2220 && isvar (&opP->disp)
2221 && subs (&opP->disp) == NULL
2222 #ifdef OBJ_ELF
2223 /* If the displacement needs pic
2224 relocation it cannot be relaxed. */
2225 && opP->disp.pic_reloc == pic_none
2226 #endif
2227 )
2228 {
2229 /* The code in md_convert_frag_1 needs to be
2230 able to adjust nextword. Call frag_grow
2231 to ensure that we have enough space in
2232 the frag obstack to make all the bytes
2233 contiguous. */
2234 frag_grow (14);
2235 nextword += baseo & 0xff;
2236 addword (nextword);
2237 add_frag (adds (&opP->disp), offs (&opP->disp),
2238 TAB (PCINDEX, SZ_UNDEF));
2239
2240 break;
2241 }
2242 }
2243 }
2244 else
2245 {
2246 nextword |= 0x40; /* No index reg */
2247 if (opP->index.reg >= ZDATA0
2248 && opP->index.reg <= ZDATA7)
2249 nextword |= (opP->index.reg - ZDATA0) << 12;
2250 else if (opP->index.reg >= ZADDR0
2251 || opP->index.reg <= ZADDR7)
2252 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2253 }
2254
2255 /* It isn't simple. */
2256
2257 if (cpu_of_arch (current_architecture) < m68020
2258 || arch_coldfire_p (current_architecture))
2259 opP->error =
2260 _("invalid operand mode for this architecture; needs 68020 or higher");
2261
2262 nextword |= 0x100;
2263 /* If the guy specified a width, we assume that it is
2264 wide enough. Maybe it isn't. If so, we lose. */
2265 switch (siz1)
2266 {
2267 case SIZE_UNSPEC:
2268 if (isvar (&opP->disp)
2269 ? m68k_rel32
2270 : ! issword (baseo))
2271 {
2272 siz1 = SIZE_LONG;
2273 nextword |= 0x30;
2274 }
2275 else if (! isvar (&opP->disp) && baseo == 0)
2276 nextword |= 0x10;
2277 else
2278 {
2279 nextword |= 0x20;
2280 siz1 = SIZE_WORD;
2281 }
2282 break;
2283 case SIZE_BYTE:
2284 as_warn (_(":b not permitted; defaulting to :w"));
2285 /* Fall through. */
2286 case SIZE_WORD:
2287 nextword |= 0x20;
2288 break;
2289 case SIZE_LONG:
2290 nextword |= 0x30;
2291 break;
2292 }
2293
2294 /* Figure out innner displacement stuff */
2295 if (opP->mode == POST || opP->mode == PRE)
2296 {
2297 if (cpu_of_arch (current_architecture) & cpu32)
2298 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2299 switch (siz2)
2300 {
2301 case SIZE_UNSPEC:
2302 if (isvar (&opP->odisp)
2303 ? m68k_rel32
2304 : ! issword (outro))
2305 {
2306 siz2 = SIZE_LONG;
2307 nextword |= 0x3;
2308 }
2309 else if (! isvar (&opP->odisp) && outro == 0)
2310 nextword |= 0x1;
2311 else
2312 {
2313 nextword |= 0x2;
2314 siz2 = SIZE_WORD;
2315 }
2316 break;
2317 case 1:
2318 as_warn (_(":b not permitted; defaulting to :w"));
2319 /* Fall through. */
2320 case 2:
2321 nextword |= 0x2;
2322 break;
2323 case 3:
2324 nextword |= 0x3;
2325 break;
2326 }
2327 if (opP->mode == POST
2328 && (nextword & 0x40) == 0)
2329 nextword |= 0x04;
2330 }
2331 addword (nextword);
2332
2333 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2334 {
2335 if (opP->reg == PC || opP->reg == ZPC)
2336 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2337 else
2338 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2339 }
2340 if (siz1 == SIZE_LONG)
2341 addword (baseo >> 16);
2342 if (siz1 != SIZE_UNSPEC)
2343 addword (baseo);
2344
2345 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2346 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2347 if (siz2 == SIZE_LONG)
2348 addword (outro >> 16);
2349 if (siz2 != SIZE_UNSPEC)
2350 addword (outro);
2351
2352 break;
2353
2354 case ABSL:
2355 nextword = get_num (&opP->disp, 80);
2356 switch (opP->disp.size)
2357 {
2358 default:
2359 abort ();
2360 case SIZE_UNSPEC:
2361 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2362 {
2363 tmpreg = 0x38; /* 7.0 */
2364 addword (nextword);
2365 break;
2366 }
2367 if (isvar (&opP->disp)
2368 && !subs (&opP->disp)
2369 && adds (&opP->disp)
2370 #ifdef OBJ_ELF
2371 /* If the displacement needs pic relocation it
2372 cannot be relaxed. */
2373 && opP->disp.pic_reloc == pic_none
2374 #endif
2375 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2376 && relaxable_symbol (adds (&opP->disp))
2377 && !flag_long_jumps
2378 && !strchr ("~%&$?", s[0]))
2379 {
2380 tmpreg = 0x3A; /* 7.2 */
2381 add_frag (adds (&opP->disp),
2382 offs (&opP->disp),
2383 TAB (PCREL, SZ_UNDEF));
2384 break;
2385 }
2386 /* Fall through into long */
2387 case SIZE_LONG:
2388 if (isvar (&opP->disp))
2389 add_fix ('l', &opP->disp, 0, 0);
2390
2391 tmpreg = 0x39;/* 7.1 mode */
2392 addword (nextword >> 16);
2393 addword (nextword);
2394 break;
2395
2396 case SIZE_BYTE:
2397 as_bad (_("unsupported byte value; use a different suffix"));
2398 /* Fall through. */
2399 case SIZE_WORD: /* Word */
2400 if (isvar (&opP->disp))
2401 add_fix ('w', &opP->disp, 0, 0);
2402
2403 tmpreg = 0x38;/* 7.0 mode */
2404 addword (nextword);
2405 break;
2406 }
2407 break;
2408 case CONTROL:
2409 case FPREG:
2410 default:
2411 as_bad (_("unknown/incorrect operand"));
2412 /* abort(); */
2413 }
2414 install_gen_operand (s[1], tmpreg);
2415 break;
2416
2417 case '#':
2418 case '^':
2419 switch (s[1])
2420 { /* JF: I hate floating point! */
2421 case 'j':
2422 tmpreg = 70;
2423 break;
2424 case '8':
2425 tmpreg = 20;
2426 break;
2427 case 'C':
2428 tmpreg = 50;
2429 break;
2430 case '3':
2431 default:
2432 tmpreg = 80;
2433 break;
2434 }
2435 tmpreg = get_num (&opP->disp, tmpreg);
2436 if (isvar (&opP->disp))
2437 add_fix (s[1], &opP->disp, 0, 0);
2438 switch (s[1])
2439 {
2440 case 'b': /* Danger: These do no check for
2441 certain types of overflow.
2442 user beware! */
2443 if (!isbyte (tmpreg))
2444 opP->error = _("out of range");
2445 insop (tmpreg, opcode);
2446 if (isvar (&opP->disp))
2447 the_ins.reloc[the_ins.nrel - 1].n =
2448 (opcode->m_codenum) * 2 + 1;
2449 break;
2450 case 'B':
2451 if (!issbyte (tmpreg))
2452 opP->error = _("out of range");
2453 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2454 if (isvar (&opP->disp))
2455 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2456 break;
2457 case 'w':
2458 if (!isword (tmpreg))
2459 opP->error = _("out of range");
2460 insop (tmpreg, opcode);
2461 if (isvar (&opP->disp))
2462 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2463 break;
2464 case 'W':
2465 if (!issword (tmpreg))
2466 opP->error = _("out of range");
2467 insop (tmpreg, opcode);
2468 if (isvar (&opP->disp))
2469 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2470 break;
2471 case 'l':
2472 /* Because of the way insop works, we put these two out
2473 backwards. */
2474 insop (tmpreg, opcode);
2475 insop (tmpreg >> 16, opcode);
2476 if (isvar (&opP->disp))
2477 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2478 break;
2479 case '3':
2480 tmpreg &= 0xFF;
2481 case '8':
2482 case 'C':
2483 case 'j':
2484 install_operand (s[1], tmpreg);
2485 break;
2486 default:
2487 abort ();
2488 }
2489 break;
2490
2491 case '+':
2492 case '-':
2493 case 'A':
2494 case 'a':
2495 install_operand (s[1], opP->reg - ADDR);
2496 break;
2497
2498 case 'B':
2499 tmpreg = get_num (&opP->disp, 80);
2500 switch (s[1])
2501 {
2502 case 'B':
2503 /* The pc_fix argument winds up in fx_pcrel_adjust,
2504 which is a char, and may therefore be unsigned. We
2505 want to pass -1, but we pass 64 instead, and convert
2506 back in md_pcrel_from. */
2507 add_fix ('B', &opP->disp, 1, 64);
2508 break;
2509 case 'W':
2510 add_fix ('w', &opP->disp, 1, 0);
2511 addword (0);
2512 break;
2513 case 'L':
2514 long_branch:
2515 if (!HAVE_LONG_BRANCH(current_architecture))
2516 as_warn (_("Can't use long branches on 68000/68010/5200"));
2517 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2518 add_fix ('l', &opP->disp, 1, 0);
2519 addword (0);
2520 addword (0);
2521 break;
2522 case 'g':
2523 if (subs (&opP->disp)) /* We can't relax it */
2524 goto long_branch;
2525
2526 #ifdef OBJ_ELF
2527 /* If the displacement needs pic relocation it cannot be
2528 relaxed. */
2529 if (opP->disp.pic_reloc != pic_none)
2530 goto long_branch;
2531 #endif
2532
2533 /* This could either be a symbol, or an absolute
2534 address. No matter, the frag hacking will finger it
2535 out. Not quite: it can't switch from BRANCH to
2536 BCC68000 for the case where opnd is absolute (it
2537 needs to use the 68000 hack since no conditional abs
2538 jumps). */
2539 if (( !HAVE_LONG_BRANCH(current_architecture)
2540 || (0 == adds (&opP->disp)))
2541 && (the_ins.opcode[0] >= 0x6200)
2542 && (the_ins.opcode[0] <= 0x6f00))
2543 add_frag (adds (&opP->disp), offs (&opP->disp),
2544 TAB (BCC68000, SZ_UNDEF));
2545 else
2546 add_frag (adds (&opP->disp), offs (&opP->disp),
2547 TAB (ABRANCH, SZ_UNDEF));
2548 break;
2549 case 'w':
2550 if (isvar (&opP->disp))
2551 {
2552 #if 1
2553 /* check for DBcc instruction */
2554 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2555 {
2556 /* size varies if patch */
2557 /* needed for long form */
2558 add_frag (adds (&opP->disp), offs (&opP->disp),
2559 TAB (DBCC, SZ_UNDEF));
2560 break;
2561 }
2562 #endif
2563 add_fix ('w', &opP->disp, 1, 0);
2564 }
2565 addword (0);
2566 break;
2567 case 'C': /* Fixed size LONG coproc branches */
2568 add_fix ('l', &opP->disp, 1, 0);
2569 addword (0);
2570 addword (0);
2571 break;
2572 case 'c': /* Var size Coprocesssor branches */
2573 if (subs (&opP->disp))
2574 {
2575 add_fix ('l', &opP->disp, 1, 0);
2576 add_frag ((symbolS *) 0, (offsetT) 0, TAB (FBRANCH, LONG));
2577 }
2578 else if (adds (&opP->disp))
2579 add_frag (adds (&opP->disp), offs (&opP->disp),
2580 TAB (FBRANCH, SZ_UNDEF));
2581 else
2582 {
2583 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2584 TAB(FBRANCH,SHORT)); */
2585 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2586 add_fix ('l', &opP->disp, 1, 0);
2587 addword (0);
2588 addword (0);
2589 }
2590 break;
2591 default:
2592 abort ();
2593 }
2594 break;
2595
2596 case 'C': /* Ignore it */
2597 break;
2598
2599 case 'd': /* JF this is a kludge */
2600 install_operand ('s', opP->reg - ADDR);
2601 tmpreg = get_num (&opP->disp, 80);
2602 if (!issword (tmpreg))
2603 {
2604 as_warn (_("Expression out of range, using 0"));
2605 tmpreg = 0;
2606 }
2607 addword (tmpreg);
2608 break;
2609
2610 case 'D':
2611 install_operand (s[1], opP->reg - DATA);
2612 break;
2613
2614 case 'E': /* Ignore it */
2615 break;
2616
2617 case 'F':
2618 install_operand (s[1], opP->reg - FP0);
2619 break;
2620
2621 case 'G': /* Ignore it */
2622 case 'H':
2623 break;
2624
2625 case 'I':
2626 tmpreg = opP->reg - COP0;
2627 install_operand (s[1], tmpreg);
2628 break;
2629
2630 case 'J': /* JF foo */
2631 switch (opP->reg)
2632 {
2633 case SFC:
2634 tmpreg = 0x000;
2635 break;
2636 case DFC:
2637 tmpreg = 0x001;
2638 break;
2639 case CACR:
2640 tmpreg = 0x002;
2641 break;
2642 case TC:
2643 tmpreg = 0x003;
2644 break;
2645 case ITT0:
2646 tmpreg = 0x004;
2647 break;
2648 case ITT1:
2649 tmpreg = 0x005;
2650 break;
2651 case DTT0:
2652 tmpreg = 0x006;
2653 break;
2654 case DTT1:
2655 tmpreg = 0x007;
2656 break;
2657 case BUSCR:
2658 tmpreg = 0x008;
2659 break;
2660
2661 case USP:
2662 tmpreg = 0x800;
2663 break;
2664 case VBR:
2665 tmpreg = 0x801;
2666 break;
2667 case CAAR:
2668 tmpreg = 0x802;
2669 break;
2670 case MSP:
2671 tmpreg = 0x803;
2672 break;
2673 case ISP:
2674 tmpreg = 0x804;
2675 break;
2676 case MMUSR:
2677 tmpreg = 0x805;
2678 break;
2679 case URP:
2680 tmpreg = 0x806;
2681 break;
2682 case SRP:
2683 tmpreg = 0x807;
2684 break;
2685 case PCR:
2686 tmpreg = 0x808;
2687 break;
2688 case ROMBAR:
2689 tmpreg = 0xC00;
2690 break;
2691 case RAMBAR0:
2692 tmpreg = 0xC04;
2693 break;
2694 case RAMBAR1:
2695 tmpreg = 0xC05;
2696 break;
2697 case MBAR:
2698 tmpreg = 0xC0F;
2699 break;
2700 default:
2701 abort ();
2702 }
2703 install_operand (s[1], tmpreg);
2704 break;
2705
2706 case 'k':
2707 tmpreg = get_num (&opP->disp, 55);
2708 install_operand (s[1], tmpreg & 0x7f);
2709 break;
2710
2711 case 'l':
2712 tmpreg = opP->mask;
2713 if (s[1] == 'w')
2714 {
2715 if (tmpreg & 0x7FF0000)
2716 as_bad (_("Floating point register in register list"));
2717 insop (reverse_16_bits (tmpreg), opcode);
2718 }
2719 else
2720 {
2721 if (tmpreg & 0x700FFFF)
2722 as_bad (_("Wrong register in floating-point reglist"));
2723 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2724 }
2725 break;
2726
2727 case 'L':
2728 tmpreg = opP->mask;
2729 if (s[1] == 'w')
2730 {
2731 if (tmpreg & 0x7FF0000)
2732 as_bad (_("Floating point register in register list"));
2733 insop (tmpreg, opcode);
2734 }
2735 else if (s[1] == '8')
2736 {
2737 if (tmpreg & 0x0FFFFFF)
2738 as_bad (_("incorrect register in reglist"));
2739 install_operand (s[1], tmpreg >> 24);
2740 }
2741 else
2742 {
2743 if (tmpreg & 0x700FFFF)
2744 as_bad (_("wrong register in floating-point reglist"));
2745 else
2746 install_operand (s[1], tmpreg >> 16);
2747 }
2748 break;
2749
2750 case 'M':
2751 install_operand (s[1], get_num (&opP->disp, 60));
2752 break;
2753
2754 case 'O':
2755 tmpreg = ((opP->mode == DREG)
2756 ? 0x20 + (int) (opP->reg - DATA)
2757 : (get_num (&opP->disp, 40) & 0x1F));
2758 install_operand (s[1], tmpreg);
2759 break;
2760
2761 case 'Q':
2762 tmpreg = get_num (&opP->disp, 10);
2763 if (tmpreg == 8)
2764 tmpreg = 0;
2765 install_operand (s[1], tmpreg);
2766 break;
2767
2768 case 'R':
2769 /* This depends on the fact that ADDR registers are eight
2770 more than their corresponding DATA regs, so the result
2771 will have the ADDR_REG bit set */
2772 install_operand (s[1], opP->reg - DATA);
2773 break;
2774
2775 case 'r':
2776 if (opP->mode == AINDR)
2777 install_operand (s[1], opP->reg - DATA);
2778 else
2779 install_operand (s[1], opP->index.reg - DATA);
2780 break;
2781
2782 case 's':
2783 if (opP->reg == FPI)
2784 tmpreg = 0x1;
2785 else if (opP->reg == FPS)
2786 tmpreg = 0x2;
2787 else if (opP->reg == FPC)
2788 tmpreg = 0x4;
2789 else
2790 abort ();
2791 install_operand (s[1], tmpreg);
2792 break;
2793
2794 case 'S': /* Ignore it */
2795 break;
2796
2797 case 'T':
2798 install_operand (s[1], get_num (&opP->disp, 30));
2799 break;
2800
2801 case 'U': /* Ignore it */
2802 break;
2803
2804 case 'c':
2805 switch (opP->reg)
2806 {
2807 case NC:
2808 tmpreg = 0;
2809 break;
2810 case DC:
2811 tmpreg = 1;
2812 break;
2813 case IC:
2814 tmpreg = 2;
2815 break;
2816 case BC:
2817 tmpreg = 3;
2818 break;
2819 default:
2820 as_fatal (_("failed sanity check"));
2821 } /* switch on cache token */
2822 install_operand (s[1], tmpreg);
2823 break;
2824 #ifndef NO_68851
2825 /* JF: These are out of order, I fear. */
2826 case 'f':
2827 switch (opP->reg)
2828 {
2829 case SFC:
2830 tmpreg = 0;
2831 break;
2832 case DFC:
2833 tmpreg = 1;
2834 break;
2835 default:
2836 abort ();
2837 }
2838 install_operand (s[1], tmpreg);
2839 break;
2840
2841 case '0':
2842 case '1':
2843 case '2':
2844 switch (opP->reg)
2845 {
2846 case TC:
2847 tmpreg = 0;
2848 break;
2849 case CAL:
2850 tmpreg = 4;
2851 break;
2852 case VAL:
2853 tmpreg = 5;
2854 break;
2855 case SCC:
2856 tmpreg = 6;
2857 break;
2858 case AC:
2859 tmpreg = 7;
2860 break;
2861 default:
2862 abort ();
2863 }
2864 install_operand (s[1], tmpreg);
2865 break;
2866
2867 case 'V':
2868 if (opP->reg == VAL)
2869 break;
2870 abort ();
2871
2872 case 'W':
2873 switch (opP->reg)
2874 {
2875 case DRP:
2876 tmpreg = 1;
2877 break;
2878 case SRP:
2879 tmpreg = 2;
2880 break;
2881 case CRP:
2882 tmpreg = 3;
2883 break;
2884 default:
2885 abort ();
2886 }
2887 install_operand (s[1], tmpreg);
2888 break;
2889
2890 case 'X':
2891 switch (opP->reg)
2892 {
2893 case BAD:
2894 case BAD + 1:
2895 case BAD + 2:
2896 case BAD + 3:
2897 case BAD + 4:
2898 case BAD + 5:
2899 case BAD + 6:
2900 case BAD + 7:
2901 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2902 break;
2903
2904 case BAC:
2905 case BAC + 1:
2906 case BAC + 2:
2907 case BAC + 3:
2908 case BAC + 4:
2909 case BAC + 5:
2910 case BAC + 6:
2911 case BAC + 7:
2912 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2913 break;
2914
2915 default:
2916 abort ();
2917 }
2918 install_operand (s[1], tmpreg);
2919 break;
2920 case 'Y':
2921 know (opP->reg == PSR);
2922 break;
2923 case 'Z':
2924 know (opP->reg == PCSR);
2925 break;
2926 #endif /* m68851 */
2927 case '3':
2928 switch (opP->reg)
2929 {
2930 case TT0:
2931 tmpreg = 2;
2932 break;
2933 case TT1:
2934 tmpreg = 3;
2935 break;
2936 default:
2937 abort ();
2938 }
2939 install_operand (s[1], tmpreg);
2940 break;
2941 case 't':
2942 tmpreg = get_num (&opP->disp, 20);
2943 install_operand (s[1], tmpreg);
2944 break;
2945 case '_': /* used only for move16 absolute 32-bit address */
2946 if (isvar (&opP->disp))
2947 add_fix ('l', &opP->disp, 0, 0);
2948 tmpreg = get_num (&opP->disp, 80);
2949 addword (tmpreg >> 16);
2950 addword (tmpreg & 0xFFFF);
2951 break;
2952 case 'u':
2953 install_operand (s[1], opP->reg - DATA0L);
2954 opP->reg -= (DATA0L);
2955 opP->reg &= 0x0F; /* remove upper/lower bit */
2956 break;
2957 default:
2958 abort ();
2959 }
2960 }
2961
2962 /* By the time whe get here (FINALLY) the_ins contains the complete
2963 instruction, ready to be emitted. . . */
2964 }
2965
2966 static int
2967 reverse_16_bits (in)
2968 int in;
2969 {
2970 int out = 0;
2971 int n;
2972
2973 static int mask[16] =
2974 {
2975 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2976 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2977 };
2978 for (n = 0; n < 16; n++)
2979 {
2980 if (in & mask[n])
2981 out |= mask[15 - n];
2982 }
2983 return out;
2984 } /* reverse_16_bits() */
2985
2986 static int
2987 reverse_8_bits (in)
2988 int in;
2989 {
2990 int out = 0;
2991 int n;
2992
2993 static int mask[8] =
2994 {
2995 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2996 };
2997
2998 for (n = 0; n < 8; n++)
2999 {
3000 if (in & mask[n])
3001 out |= mask[7 - n];
3002 }
3003 return out;
3004 } /* reverse_8_bits() */
3005
3006 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3007 (that value is chosen in the frag_var call in md_assemble). TYPE
3008 is the subtype of the frag to be generated; its primary type is
3009 rs_machine_dependent.
3010
3011 The TYPE parameter is also used by md_convert_frag_1 and
3012 md_estimate_size_before_relax. The appropriate type of fixup will
3013 be emitted by md_convert_frag_1.
3014
3015 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3016 static void
3017 install_operand (mode, val)
3018 int mode;
3019 int val;
3020 {
3021 switch (mode)
3022 {
3023 case 's':
3024 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3025 break;
3026 case 'd':
3027 the_ins.opcode[0] |= val << 9;
3028 break;
3029 case '1':
3030 the_ins.opcode[1] |= val << 12;
3031 break;
3032 case '2':
3033 the_ins.opcode[1] |= val << 6;
3034 break;
3035 case '3':
3036 the_ins.opcode[1] |= val;
3037 break;
3038 case '4':
3039 the_ins.opcode[2] |= val << 12;
3040 break;
3041 case '5':
3042 the_ins.opcode[2] |= val << 6;
3043 break;
3044 case '6':
3045 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3046 three words long! */
3047 the_ins.numo++;
3048 the_ins.opcode[2] |= val;
3049 break;
3050 case '7':
3051 the_ins.opcode[1] |= val << 7;
3052 break;
3053 case '8':
3054 the_ins.opcode[1] |= val << 10;
3055 break;
3056 #ifndef NO_68851
3057 case '9':
3058 the_ins.opcode[1] |= val << 5;
3059 break;
3060 #endif
3061
3062 case 't':
3063 the_ins.opcode[1] |= (val << 10) | (val << 7);
3064 break;
3065 case 'D':
3066 the_ins.opcode[1] |= (val << 12) | val;
3067 break;
3068 case 'g':
3069 the_ins.opcode[0] |= val = 0xff;
3070 break;
3071 case 'i':
3072 the_ins.opcode[0] |= val << 9;
3073 break;
3074 case 'C':
3075 the_ins.opcode[1] |= val;
3076 break;
3077 case 'j':
3078 the_ins.opcode[1] |= val;
3079 the_ins.numo++; /* What a hack */
3080 break;
3081 case 'k':
3082 the_ins.opcode[1] |= val << 4;
3083 break;
3084 case 'b':
3085 case 'w':
3086 case 'W':
3087 case 'l':
3088 break;
3089 case 'e':
3090 the_ins.opcode[0] |= (val << 6);
3091 break;
3092 case 'L':
3093 the_ins.opcode[1] = (val >> 16);
3094 the_ins.opcode[2] = val & 0xffff;
3095 break;
3096 case 'm':
3097 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3098 the_ins.opcode[0] |= ((val & 0x7) << 9);
3099 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3100 break;
3101 case 'n':
3102 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3103 the_ins.opcode[0] |= ((val & 0x7) << 9);
3104 break;
3105 case 'o':
3106 the_ins.opcode[1] |= val << 12;
3107 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3108 break;
3109 case 'M':
3110 the_ins.opcode[0] |= (val & 0xF);
3111 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3112 break;
3113 case 'N':
3114 the_ins.opcode[1] |= (val & 0xF);
3115 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3116 break;
3117 case 'h':
3118 the_ins.opcode[1] |= ((val != 1) << 10);
3119 break;
3120 case 'c':
3121 default:
3122 as_fatal (_("failed sanity check."));
3123 }
3124 } /* install_operand() */
3125
3126 static void
3127 install_gen_operand (mode, val)
3128 int mode;
3129 int val;
3130 {
3131 switch (mode)
3132 {
3133 case 's':
3134 the_ins.opcode[0] |= val;
3135 break;
3136 case 'd':
3137 /* This is a kludge!!! */
3138 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3139 break;
3140 case 'b':
3141 case 'w':
3142 case 'l':
3143 case 'f':
3144 case 'F':
3145 case 'x':
3146 case 'p':
3147 the_ins.opcode[0] |= val;
3148 break;
3149 /* more stuff goes here */
3150 default:
3151 as_fatal (_("failed sanity check."));
3152 }
3153 } /* install_gen_operand() */
3154
3155 /*
3156 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3157 * then deal with the bitfield hack.
3158 */
3159
3160 static char *
3161 crack_operand (str, opP)
3162 register char *str;
3163 register struct m68k_op *opP;
3164 {
3165 register int parens;
3166 register int c;
3167 register char *beg_str;
3168 int inquote = 0;
3169
3170 if (!str)
3171 {
3172 return str;
3173 }
3174 beg_str = str;
3175 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3176 {
3177 if (! inquote)
3178 {
3179 if (*str == '(')
3180 parens++;
3181 else if (*str == ')')
3182 {
3183 if (!parens)
3184 { /* ERROR */
3185 opP->error = _("Extra )");
3186 return str;
3187 }
3188 --parens;
3189 }
3190 }
3191 if (flag_mri && *str == '\'')
3192 inquote = ! inquote;
3193 }
3194 if (!*str && parens)
3195 { /* ERROR */
3196 opP->error = _("Missing )");
3197 return str;
3198 }
3199 c = *str;
3200 *str = '\0';
3201 if (m68k_ip_op (beg_str, opP) != 0)
3202 {
3203 *str = c;
3204 return str;
3205 }
3206 *str = c;
3207 if (c == '}')
3208 c = *++str; /* JF bitfield hack */
3209 if (c)
3210 {
3211 c = *++str;
3212 if (!c)
3213 as_bad (_("Missing operand"));
3214 }
3215
3216 /* Detect MRI REG symbols and convert them to REGLSTs. */
3217 if (opP->mode == CONTROL && (int)opP->reg < 0)
3218 {
3219 opP->mode = REGLST;
3220 opP->mask = ~(int)opP->reg;
3221 opP->reg = 0;
3222 }
3223
3224 return str;
3225 }
3226
3227 /* This is the guts of the machine-dependent assembler. STR points to a
3228 machine dependent instruction. This function is supposed to emit
3229 the frags/bytes it assembles to.
3230 */
3231
3232 static void
3233 insert_reg (regname, regnum)
3234 const char *regname;
3235 int regnum;
3236 {
3237 char buf[100];
3238 int i;
3239
3240 #ifdef REGISTER_PREFIX
3241 if (!flag_reg_prefix_optional)
3242 {
3243 buf[0] = REGISTER_PREFIX;
3244 strcpy (buf + 1, regname);
3245 regname = buf;
3246 }
3247 #endif
3248
3249 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3250 &zero_address_frag));
3251
3252 for (i = 0; regname[i]; i++)
3253 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3254 buf[i] = '\0';
3255
3256 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3257 &zero_address_frag));
3258 }
3259
3260 struct init_entry
3261 {
3262 const char *name;
3263 int number;
3264 };
3265
3266 static const struct init_entry init_table[] =
3267 {
3268 { "d0", DATA0 },
3269 { "d1", DATA1 },
3270 { "d2", DATA2 },
3271 { "d3", DATA3 },
3272 { "d4", DATA4 },
3273 { "d5", DATA5 },
3274 { "d6", DATA6 },
3275 { "d7", DATA7 },
3276 { "a0", ADDR0 },
3277 { "a1", ADDR1 },
3278 { "a2", ADDR2 },
3279 { "a3", ADDR3 },
3280 { "a4", ADDR4 },
3281 { "a5", ADDR5 },
3282 { "a6", ADDR6 },
3283 { "fp", ADDR6 },
3284 { "a7", ADDR7 },
3285 { "sp", ADDR7 },
3286 { "ssp", ADDR7 },
3287 { "fp0", FP0 },
3288 { "fp1", FP1 },
3289 { "fp2", FP2 },
3290 { "fp3", FP3 },
3291 { "fp4", FP4 },
3292 { "fp5", FP5 },
3293 { "fp6", FP6 },
3294 { "fp7", FP7 },
3295 { "fpi", FPI },
3296 { "fpiar", FPI },
3297 { "fpc", FPI },
3298 { "fps", FPS },
3299 { "fpsr", FPS },
3300 { "fpc", FPC },
3301 { "fpcr", FPC },
3302 { "control", FPC },
3303 { "status", FPS },
3304 { "iaddr", FPI },
3305
3306 { "cop0", COP0 },
3307 { "cop1", COP1 },
3308 { "cop2", COP2 },
3309 { "cop3", COP3 },
3310 { "cop4", COP4 },
3311 { "cop5", COP5 },
3312 { "cop6", COP6 },
3313 { "cop7", COP7 },
3314 { "pc", PC },
3315 { "zpc", ZPC },
3316 { "sr", SR },
3317
3318 { "ccr", CCR },
3319 { "cc", CCR },
3320
3321 { "acc", ACC },
3322 { "macsr", MACSR },
3323 { "mask", MASK },
3324
3325 /* control registers */
3326 { "sfc", SFC }, /* Source Function Code */
3327 { "sfcr", SFC },
3328 { "dfc", DFC }, /* Destination Function Code */
3329 { "dfcr", DFC },
3330 { "cacr", CACR }, /* Cache Control Register */
3331 { "caar", CAAR }, /* Cache Address Register */
3332
3333 { "usp", USP }, /* User Stack Pointer */
3334 { "vbr", VBR }, /* Vector Base Register */
3335 { "msp", MSP }, /* Master Stack Pointer */
3336 { "isp", ISP }, /* Interrupt Stack Pointer */
3337
3338 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3339 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3340 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3341 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3342
3343 /* 68ec040 versions of same */
3344 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3345 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3346 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3347 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3348
3349 /* mcf5200 versions of same. The ColdFire programmer's reference
3350 manual indicated that the order is 2,3,0,1, but Ken Rose
3351 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3352 { "acr0", ITT0 }, /* Access Control Unit 0 */
3353 { "acr1", ITT1 }, /* Access Control Unit 1 */
3354 { "acr2", DTT0 }, /* Access Control Unit 2 */
3355 { "acr3", DTT1 }, /* Access Control Unit 3 */
3356
3357 { "tc", TC }, /* MMU Translation Control Register */
3358 { "tcr", TC },
3359
3360 { "mmusr", MMUSR }, /* MMU Status Register */
3361 { "srp", SRP }, /* User Root Pointer */
3362 { "urp", URP }, /* Supervisor Root Pointer */
3363
3364 { "buscr", BUSCR },
3365 { "pcr", PCR },
3366
3367 { "rombar", ROMBAR }, /* ROM Base Address Register */
3368 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3369 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3370 { "mbar", MBAR }, /* Module Base Address Register */
3371 /* end of control registers */
3372
3373 { "ac", AC },
3374 { "bc", BC },
3375 { "cal", CAL },
3376 { "crp", CRP },
3377 { "drp", DRP },
3378 { "pcsr", PCSR },
3379 { "psr", PSR },
3380 { "scc", SCC },
3381 { "val", VAL },
3382 { "bad0", BAD0 },
3383 { "bad1", BAD1 },
3384 { "bad2", BAD2 },
3385 { "bad3", BAD3 },
3386 { "bad4", BAD4 },
3387 { "bad5", BAD5 },
3388 { "bad6", BAD6 },
3389 { "bad7", BAD7 },
3390 { "bac0", BAC0 },
3391 { "bac1", BAC1 },
3392 { "bac2", BAC2 },
3393 { "bac3", BAC3 },
3394 { "bac4", BAC4 },
3395 { "bac5", BAC5 },
3396 { "bac6", BAC6 },
3397 { "bac7", BAC7 },
3398
3399 { "ic", IC },
3400 { "dc", DC },
3401 { "nc", NC },
3402
3403 { "tt0", TT0 },
3404 { "tt1", TT1 },
3405 /* 68ec030 versions of same */
3406 { "ac0", TT0 },
3407 { "ac1", TT1 },
3408 /* 68ec030 access control unit, identical to 030 MMU status reg */
3409 { "acusr", PSR },
3410
3411 /* Suppressed data and address registers. */
3412 { "zd0", ZDATA0 },
3413 { "zd1", ZDATA1 },
3414 { "zd2", ZDATA2 },
3415 { "zd3", ZDATA3 },
3416 { "zd4", ZDATA4 },
3417 { "zd5", ZDATA5 },
3418 { "zd6", ZDATA6 },
3419 { "zd7", ZDATA7 },
3420 { "za0", ZADDR0 },
3421 { "za1", ZADDR1 },
3422 { "za2", ZADDR2 },
3423 { "za3", ZADDR3 },
3424 { "za4", ZADDR4 },
3425 { "za5", ZADDR5 },
3426 { "za6", ZADDR6 },
3427 { "za7", ZADDR7 },
3428
3429 /* Upper and lower data and address registers, used by macw and msacw. */
3430 { "d0l", DATA0L },
3431 { "d1l", DATA1L },
3432 { "d2l", DATA2L },
3433 { "d3l", DATA3L },
3434 { "d4l", DATA4L },
3435 { "d5l", DATA5L },
3436 { "d6l", DATA6L },
3437 { "d7l", DATA7L },
3438
3439 { "a0l", ADDR0L },
3440 { "a1l", ADDR1L },
3441 { "a2l", ADDR2L },
3442 { "a3l", ADDR3L },
3443 { "a4l", ADDR4L },
3444 { "a5l", ADDR5L },
3445 { "a6l", ADDR6L },
3446 { "a7l", ADDR7L },
3447
3448 { "d0u", DATA0U },
3449 { "d1u", DATA1U },
3450 { "d2u", DATA2U },
3451 { "d3u", DATA3U },
3452 { "d4u", DATA4U },
3453 { "d5u", DATA5U },
3454 { "d6u", DATA6U },
3455 { "d7u", DATA7U },
3456
3457 { "a0u", ADDR0U },
3458 { "a1u", ADDR1U },
3459 { "a2u", ADDR2U },
3460 { "a3u", ADDR3U },
3461 { "a4u", ADDR4U },
3462 { "a5u", ADDR5U },
3463 { "a6u", ADDR6U },
3464 { "a7u", ADDR7U },
3465
3466 { 0, 0 }
3467 };
3468
3469 static void
3470 init_regtable ()
3471 {
3472 int i;
3473 for (i = 0; init_table[i].name; i++)
3474 insert_reg (init_table[i].name, init_table[i].number);
3475 }
3476
3477 static int no_68851, no_68881;
3478
3479 #ifdef OBJ_AOUT
3480 /* a.out machine type. Default to 68020. */
3481 int m68k_aout_machtype = 2;
3482 #endif
3483
3484 void
3485 md_assemble (str)
3486 char *str;
3487 {
3488 const char *er;
3489 short *fromP;
3490 char *toP = NULL;
3491 int m, n = 0;
3492 char *to_beg_P;
3493 int shorts_this_frag;
3494 fixS *fixP;
3495
3496 /* In MRI mode, the instruction and operands are separated by a
3497 space. Anything following the operands is a comment. The label
3498 has already been removed. */
3499 if (flag_mri)
3500 {
3501 char *s;
3502 int fields = 0;
3503 int infield = 0;
3504 int inquote = 0;
3505
3506 for (s = str; *s != '\0'; s++)
3507 {
3508 if ((*s == ' ' || *s == '\t') && ! inquote)
3509 {
3510 if (infield)
3511 {
3512 ++fields;
3513 if (fields >= 2)
3514 {
3515 *s = '\0';
3516 break;
3517 }
3518 infield = 0;
3519 }
3520 }
3521 else
3522 {
3523 if (! infield)
3524 infield = 1;
3525 if (*s == '\'')
3526 inquote = ! inquote;
3527 }
3528 }
3529 }
3530
3531 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3532 m68k_ip (str);
3533 er = the_ins.error;
3534 if (!er)
3535 {
3536 for (n = 0; n < the_ins.numargs; n++)
3537 if (the_ins.operands[n].error)
3538 {
3539 er = the_ins.operands[n].error;
3540 break;
3541 }
3542 }
3543 if (er)
3544 {
3545 as_bad (_("%s -- statement `%s' ignored"), er, str);
3546 return;
3547 }
3548
3549 /* If there is a current label, record that it marks an instruction. */
3550 if (current_label != NULL)
3551 {
3552 current_label->text = 1;
3553 current_label = NULL;
3554 }
3555
3556 if (the_ins.nfrag == 0)
3557 {
3558 /* No frag hacking involved; just put it out */
3559 toP = frag_more (2 * the_ins.numo);
3560 fromP = &the_ins.opcode[0];
3561 for (m = the_ins.numo; m; --m)
3562 {
3563 md_number_to_chars (toP, (long) (*fromP), 2);
3564 toP += 2;
3565 fromP++;
3566 }
3567 /* put out symbol-dependent info */
3568 for (m = 0; m < the_ins.nrel; m++)
3569 {
3570 switch (the_ins.reloc[m].wid)
3571 {
3572 case 'B':
3573 n = 1;
3574 break;
3575 case 'b':
3576 n = 1;
3577 break;
3578 case '3':
3579 n = 1;
3580 break;
3581 case 'w':
3582 case 'W':
3583 n = 2;
3584 break;
3585 case 'l':
3586 n = 4;
3587 break;
3588 default:
3589 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3590 the_ins.reloc[m].wid);
3591 }
3592
3593 fixP = fix_new_exp (frag_now,
3594 ((toP - frag_now->fr_literal)
3595 - the_ins.numo * 2 + the_ins.reloc[m].n),
3596 n,
3597 &the_ins.reloc[m].exp,
3598 the_ins.reloc[m].pcrel,
3599 get_reloc_code (n, the_ins.reloc[m].pcrel,
3600 the_ins.reloc[m].pic_reloc));
3601 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3602 if (the_ins.reloc[m].wid == 'B')
3603 fixP->fx_signed = 1;
3604 }
3605 return;
3606 }
3607
3608 /* There's some frag hacking */
3609 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3610 {
3611 int wid;
3612
3613 if (n == 0)
3614 wid = 2 * the_ins.fragb[n].fragoff;
3615 else
3616 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3617 toP = frag_more (wid);
3618 to_beg_P = toP;
3619 shorts_this_frag = 0;
3620 for (m = wid / 2; m; --m)
3621 {
3622 md_number_to_chars (toP, (long) (*fromP), 2);
3623 toP += 2;
3624 fromP++;
3625 shorts_this_frag++;
3626 }
3627 for (m = 0; m < the_ins.nrel; m++)
3628 {
3629 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3630 {
3631 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3632 break;
3633 }
3634 wid = the_ins.reloc[m].wid;
3635 if (wid == 0)
3636 continue;
3637 the_ins.reloc[m].wid = 0;
3638 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3639
3640 fixP = fix_new_exp (frag_now,
3641 ((toP - frag_now->fr_literal)
3642 - the_ins.numo * 2 + the_ins.reloc[m].n),
3643 wid,
3644 &the_ins.reloc[m].exp,
3645 the_ins.reloc[m].pcrel,
3646 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3647 the_ins.reloc[m].pic_reloc));
3648 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3649 }
3650 (void) frag_var (rs_machine_dependent, 10, 0,
3651 (relax_substateT) (the_ins.fragb[n].fragty),
3652 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3653 }
3654 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3655 shorts_this_frag = 0;
3656 if (n)
3657 {
3658 toP = frag_more (n * sizeof (short));
3659 while (n--)
3660 {
3661 md_number_to_chars (toP, (long) (*fromP), 2);
3662 toP += 2;
3663 fromP++;
3664 shorts_this_frag++;
3665 }
3666 }
3667 for (m = 0; m < the_ins.nrel; m++)
3668 {
3669 int wid;
3670
3671 wid = the_ins.reloc[m].wid;
3672 if (wid == 0)
3673 continue;
3674 the_ins.reloc[m].wid = 0;
3675 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3676
3677 fixP = fix_new_exp (frag_now,
3678 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3679 - shorts_this_frag * 2),
3680 wid,
3681 &the_ins.reloc[m].exp,
3682 the_ins.reloc[m].pcrel,
3683 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3684 the_ins.reloc[m].pic_reloc));
3685 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3686 }
3687 }
3688
3689 void
3690 md_begin ()
3691 {
3692 /*
3693 * md_begin -- set up hash tables with 68000 instructions.
3694 * similar to what the vax assembler does. ---phr
3695 */
3696 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3697 a copy of it at runtime, adding in the information we want but isn't
3698 there. I think it'd be better to have an awk script hack the table
3699 at compile time. Or even just xstr the table and use it as-is. But
3700 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3701 names. */
3702
3703 register const struct m68k_opcode *ins;
3704 register struct m68k_incant *hack, *slak;
3705 register const char *retval = 0; /* empty string, or error msg text */
3706 register int i;
3707 register char c;
3708
3709 if (flag_mri)
3710 {
3711 flag_reg_prefix_optional = 1;
3712 m68k_abspcadd = 1;
3713 if (! m68k_rel32_from_cmdline)
3714 m68k_rel32 = 0;
3715 }
3716
3717 op_hash = hash_new ();
3718
3719 obstack_begin (&robyn, 4000);
3720 for (i = 0; i < m68k_numopcodes; i++)
3721 {
3722 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3723 do
3724 {
3725 ins = &m68k_opcodes[i];
3726 /* We *could* ignore insns that don't match our arch here
3727 but just leaving them out of the hash. */
3728 slak->m_operands = ins->args;
3729 slak->m_opnum = strlen (slak->m_operands) / 2;
3730 slak->m_arch = ins->arch;
3731 slak->m_opcode = ins->opcode;
3732 /* This is kludgey */
3733 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3734 if (i + 1 != m68k_numopcodes
3735 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3736 {
3737 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3738 i++;
3739 }
3740 else
3741 slak->m_next = 0;
3742 slak = slak->m_next;
3743 }
3744 while (slak);
3745
3746 retval = hash_insert (op_hash, ins->name, (char *) hack);
3747 if (retval)
3748 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3749 }
3750
3751 for (i = 0; i < m68k_numaliases; i++)
3752 {
3753 const char *name = m68k_opcode_aliases[i].primary;
3754 const char *alias = m68k_opcode_aliases[i].alias;
3755 PTR val = hash_find (op_hash, name);
3756 if (!val)
3757 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3758 retval = hash_insert (op_hash, alias, val);
3759 if (retval)
3760 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3761 }
3762
3763 /* In MRI mode, all unsized branches are variable sized. Normally,
3764 they are word sized. */
3765 if (flag_mri)
3766 {
3767 static struct m68k_opcode_alias mri_aliases[] =
3768 {
3769 { "bhi", "jhi", },
3770 { "bls", "jls", },
3771 { "bcc", "jcc", },
3772 { "bcs", "jcs", },
3773 { "bne", "jne", },
3774 { "beq", "jeq", },
3775 { "bvc", "jvc", },
3776 { "bvs", "jvs", },
3777 { "bpl", "jpl", },
3778 { "bmi", "jmi", },
3779 { "bge", "jge", },
3780 { "blt", "jlt", },
3781 { "bgt", "jgt", },
3782 { "ble", "jle", },
3783 { "bra", "jra", },
3784 { "bsr", "jbsr", },
3785 };
3786
3787 for (i = 0;
3788 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3789 i++)
3790 {
3791 const char *name = mri_aliases[i].primary;
3792 const char *alias = mri_aliases[i].alias;
3793 PTR val = hash_find (op_hash, name);
3794 if (!val)
3795 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3796 retval = hash_jam (op_hash, alias, val);
3797 if (retval)
3798 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3799 }
3800 }
3801
3802 for (i = 0; i < (int) sizeof (mklower_table); i++)
3803 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3804
3805 for (i = 0; i < (int) sizeof (notend_table); i++)
3806 {
3807 notend_table[i] = 0;
3808 alt_notend_table[i] = 0;
3809 }
3810 notend_table[','] = 1;
3811 notend_table['{'] = 1;
3812 notend_table['}'] = 1;
3813 alt_notend_table['a'] = 1;
3814 alt_notend_table['A'] = 1;
3815 alt_notend_table['d'] = 1;
3816 alt_notend_table['D'] = 1;
3817 alt_notend_table['#'] = 1;
3818 alt_notend_table['&'] = 1;
3819 alt_notend_table['f'] = 1;
3820 alt_notend_table['F'] = 1;
3821 #ifdef REGISTER_PREFIX
3822 alt_notend_table[REGISTER_PREFIX] = 1;
3823 #endif
3824
3825 /* We need to put '(' in alt_notend_table to handle
3826 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3827 */
3828 alt_notend_table['('] = 1;
3829
3830 /* We need to put '@' in alt_notend_table to handle
3831 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3832 */
3833 alt_notend_table['@'] = 1;
3834
3835 /* We need to put digits in alt_notend_table to handle
3836 bfextu %d0{24:1},%d0
3837 */
3838 alt_notend_table['0'] = 1;
3839 alt_notend_table['1'] = 1;
3840 alt_notend_table['2'] = 1;
3841 alt_notend_table['3'] = 1;
3842 alt_notend_table['4'] = 1;
3843 alt_notend_table['5'] = 1;
3844 alt_notend_table['6'] = 1;
3845 alt_notend_table['7'] = 1;
3846 alt_notend_table['8'] = 1;
3847 alt_notend_table['9'] = 1;
3848
3849 #ifndef MIT_SYNTAX_ONLY
3850 /* Insert pseudo ops, these have to go into the opcode table since
3851 gas expects pseudo ops to start with a dot */
3852 {
3853 int n = 0;
3854 while (mote_pseudo_table[n].poc_name)
3855 {
3856 hack = (struct m68k_incant *)
3857 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3858 hash_insert (op_hash,
3859 mote_pseudo_table[n].poc_name, (char *) hack);
3860 hack->m_operands = 0;
3861 hack->m_opnum = n;
3862 n++;
3863 }
3864 }
3865 #endif
3866
3867 init_regtable ();
3868
3869 #ifdef OBJ_ELF
3870 record_alignment (text_section, 2);
3871 record_alignment (data_section, 2);
3872 record_alignment (bss_section, 2);
3873 #endif
3874 }
3875
3876 static void
3877 select_control_regs ()
3878 {
3879 /* Note which set of "movec" control registers is available. */
3880 switch (cpu_of_arch (current_architecture))
3881 {
3882 case m68000:
3883 control_regs = m68000_control_regs;
3884 break;
3885 case m68010:
3886 control_regs = m68010_control_regs;
3887 break;
3888 case m68020:
3889 case m68030:
3890 control_regs = m68020_control_regs;
3891 break;
3892 case m68040:
3893 control_regs = m68040_control_regs;
3894 break;
3895 case m68060:
3896 control_regs = m68060_control_regs;
3897 break;
3898 case cpu32:
3899 control_regs = cpu32_control_regs;
3900 break;
3901 case mcf5200:
3902 case mcf5206e:
3903 case mcf5307:
3904 control_regs = mcf_control_regs;
3905 break;
3906 default:
3907 abort ();
3908 }
3909 }
3910
3911 void
3912 m68k_init_after_args ()
3913 {
3914 if (cpu_of_arch (current_architecture) == 0)
3915 {
3916 int i;
3917 const char *default_cpu = TARGET_CPU;
3918
3919 if (*default_cpu == 'm')
3920 default_cpu++;
3921 for (i = 0; i < n_archs; i++)
3922 if (strcasecmp (default_cpu, archs[i].name) == 0)
3923 break;
3924 if (i == n_archs)
3925 {
3926 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3927 current_architecture |= m68020;
3928 }
3929 else
3930 current_architecture |= archs[i].arch;
3931 }
3932 /* Permit m68881 specification with all cpus; those that can't work
3933 with a coprocessor could be doing emulation. */
3934 if (current_architecture & m68851)
3935 {
3936 if (current_architecture & m68040)
3937 {
3938 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
3939 }
3940 }
3941 /* What other incompatibilities could we check for? */
3942
3943 /* Toss in some default assumptions about coprocessors. */
3944 if (!no_68881
3945 && (cpu_of_arch (current_architecture)
3946 /* Can CPU32 have a 68881 coprocessor?? */
3947 & (m68020 | m68030 | cpu32)))
3948 {
3949 current_architecture |= m68881;
3950 }
3951 if (!no_68851
3952 && (cpu_of_arch (current_architecture) & m68020up) != 0
3953 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3954 {
3955 current_architecture |= m68851;
3956 }
3957 if (no_68881 && (current_architecture & m68881))
3958 as_bad (_("options for 68881 and no-68881 both given"));
3959 if (no_68851 && (current_architecture & m68851))
3960 as_bad (_("options for 68851 and no-68851 both given"));
3961
3962 #ifdef OBJ_AOUT
3963 /* Work out the magic number. This isn't very general. */
3964 if (current_architecture & m68000)
3965 m68k_aout_machtype = 0;
3966 else if (current_architecture & m68010)
3967 m68k_aout_machtype = 1;
3968 else if (current_architecture & m68020)
3969 m68k_aout_machtype = 2;
3970 else
3971 m68k_aout_machtype = 2;
3972 #endif
3973
3974 /* Note which set of "movec" control registers is available. */
3975 select_control_regs ();
3976
3977 if (cpu_of_arch (current_architecture) < m68020
3978 || arch_coldfire_p (current_architecture))
3979 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3980 }
3981 \f
3982 /* This is called when a label is defined. */
3983
3984 void
3985 m68k_frob_label (sym)
3986 symbolS *sym;
3987 {
3988 struct label_line *n;
3989
3990 n = (struct label_line *) xmalloc (sizeof *n);
3991 n->next = labels;
3992 n->label = sym;
3993 as_where (&n->file, &n->line);
3994 n->text = 0;
3995 labels = n;
3996 current_label = n;
3997 }
3998
3999 /* This is called when a value that is not an instruction is emitted. */
4000
4001 void
4002 m68k_flush_pending_output ()
4003 {
4004 current_label = NULL;
4005 }
4006
4007 /* This is called at the end of the assembly, when the final value of
4008 the label is known. We warn if this is a text symbol aligned at an
4009 odd location. */
4010
4011 void
4012 m68k_frob_symbol (sym)
4013 symbolS *sym;
4014 {
4015 if (S_GET_SEGMENT (sym) == reg_section
4016 && (int) S_GET_VALUE (sym) < 0)
4017 {
4018 S_SET_SEGMENT (sym, absolute_section);
4019 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4020 }
4021 else if ((S_GET_VALUE (sym) & 1) != 0)
4022 {
4023 struct label_line *l;
4024
4025 for (l = labels; l != NULL; l = l->next)
4026 {
4027 if (l->label == sym)
4028 {
4029 if (l->text)
4030 as_warn_where (l->file, l->line,
4031 _("text label `%s' aligned to odd boundary"),
4032 S_GET_NAME (sym));
4033 break;
4034 }
4035 }
4036 }
4037 }
4038 \f
4039 /* This is called if we go in or out of MRI mode because of the .mri
4040 pseudo-op. */
4041
4042 void
4043 m68k_mri_mode_change (on)
4044 int on;
4045 {
4046 if (on)
4047 {
4048 if (! flag_reg_prefix_optional)
4049 {
4050 flag_reg_prefix_optional = 1;
4051 #ifdef REGISTER_PREFIX
4052 init_regtable ();
4053 #endif
4054 }
4055 m68k_abspcadd = 1;
4056 if (! m68k_rel32_from_cmdline)
4057 m68k_rel32 = 0;
4058 }
4059 else
4060 {
4061 if (! reg_prefix_optional_seen)
4062 {
4063 #ifdef REGISTER_PREFIX_OPTIONAL
4064 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4065 #else
4066 flag_reg_prefix_optional = 0;
4067 #endif
4068 #ifdef REGISTER_PREFIX
4069 init_regtable ();
4070 #endif
4071 }
4072 m68k_abspcadd = 0;
4073 if (! m68k_rel32_from_cmdline)
4074 m68k_rel32 = 1;
4075 }
4076 }
4077
4078 /* Equal to MAX_PRECISION in atof-ieee.c */
4079 #define MAX_LITTLENUMS 6
4080
4081 /* Turn a string in input_line_pointer into a floating point constant
4082 of type TYPE, and store the appropriate bytes in *LITP. The number
4083 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4084 returned, or NULL on OK. */
4085
4086 char *
4087 md_atof (type, litP, sizeP)
4088 char type;
4089 char *litP;
4090 int *sizeP;
4091 {
4092 int prec;
4093 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4094 LITTLENUM_TYPE *wordP;
4095 char *t;
4096
4097 switch (type)
4098 {
4099 case 'f':
4100 case 'F':
4101 case 's':
4102 case 'S':
4103 prec = 2;
4104 break;
4105
4106 case 'd':
4107 case 'D':
4108 case 'r':
4109 case 'R':
4110 prec = 4;
4111 break;
4112
4113 case 'x':
4114 case 'X':
4115 prec = 6;
4116 break;
4117
4118 case 'p':
4119 case 'P':
4120 prec = 6;
4121 break;
4122
4123 default:
4124 *sizeP = 0;
4125 return _("Bad call to MD_ATOF()");
4126 }
4127 t = atof_ieee (input_line_pointer, type, words);
4128 if (t)
4129 input_line_pointer = t;
4130
4131 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4132 for (wordP = words; prec--;)
4133 {
4134 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4135 litP += sizeof (LITTLENUM_TYPE);
4136 }
4137 return 0;
4138 }
4139
4140 void
4141 md_number_to_chars (buf, val, n)
4142 char *buf;
4143 valueT val;
4144 int n;
4145 {
4146 number_to_chars_bigendian (buf, val, n);
4147 }
4148
4149 static void
4150 md_apply_fix_2 (fixP, val)
4151 fixS *fixP;
4152 offsetT val;
4153 {
4154 addressT upper_limit;
4155 offsetT lower_limit;
4156
4157 /* This is unnecessary but it convinces the native rs6000 compiler
4158 to generate the code we want. */
4159 char *buf = fixP->fx_frag->fr_literal;
4160 buf += fixP->fx_where;
4161 /* end ibm compiler workaround */
4162
4163 if (val & 0x80000000)
4164 val |= ~(addressT)0x7fffffff;
4165 else
4166 val &= 0x7fffffff;
4167
4168 #ifdef OBJ_ELF
4169 if (fixP->fx_addsy)
4170 {
4171 memset (buf, 0, fixP->fx_size);
4172 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4173
4174 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4175 && !S_IS_DEFINED (fixP->fx_addsy)
4176 && !S_IS_WEAK (fixP->fx_addsy))
4177 S_SET_WEAK (fixP->fx_addsy);
4178 return;
4179 }
4180 #endif
4181
4182 #ifdef BFD_ASSEMBLER
4183 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4184 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4185 return;
4186 #endif
4187
4188 switch (fixP->fx_size)
4189 {
4190 /* The cast to offsetT below are necessary to make code correct for
4191 machines where ints are smaller than offsetT */
4192 case 1:
4193 *buf++ = val;
4194 upper_limit = 0x7f;
4195 lower_limit = - (offsetT) 0x80;
4196 break;
4197 case 2:
4198 *buf++ = (val >> 8);
4199 *buf++ = val;
4200 upper_limit = 0x7fff;
4201 lower_limit = - (offsetT) 0x8000;
4202 break;
4203 case 4:
4204 *buf++ = (val >> 24);
4205 *buf++ = (val >> 16);
4206 *buf++ = (val >> 8);
4207 *buf++ = val;
4208 upper_limit = 0x7fffffff;
4209 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4210 break;
4211 default:
4212 BAD_CASE (fixP->fx_size);
4213 }
4214
4215 /* Fix up a negative reloc. */
4216 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4217 {
4218 fixP->fx_addsy = fixP->fx_subsy;
4219 fixP->fx_subsy = NULL;
4220 fixP->fx_tcbit = 1;
4221 }
4222
4223 /* For non-pc-relative values, it's conceivable we might get something
4224 like "0xff" for a byte field. So extend the upper part of the range
4225 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4226 so that we can do any range checking at all. */
4227 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4228 upper_limit = upper_limit * 2 + 1;
4229
4230 if ((addressT) val > upper_limit
4231 && (val > 0 || val < lower_limit))
4232 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4233
4234 /* A one byte PC-relative reloc means a short branch. We can't use
4235 a short branch with a value of 0 or -1, because those indicate
4236 different opcodes (branches with longer offsets). fixup_segment
4237 in write.c may have clobbered fx_pcrel, so we need to examine the
4238 reloc type. */
4239 if ((fixP->fx_pcrel
4240 #ifdef BFD_ASSEMBLER
4241 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4242 #endif
4243 )
4244 && fixP->fx_size == 1
4245 && (fixP->fx_addsy == NULL
4246 || S_IS_DEFINED (fixP->fx_addsy))
4247 && (val == 0 || val == -1))
4248 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4249 }
4250
4251 #ifdef BFD_ASSEMBLER
4252 int
4253 md_apply_fix (fixP, valp)
4254 fixS *fixP;
4255 valueT *valp;
4256 {
4257 md_apply_fix_2 (fixP, (addressT) *valp);
4258 return 1;
4259 }
4260 #else
4261 void md_apply_fix (fixP, val)
4262 fixS *fixP;
4263 long val;
4264 {
4265 md_apply_fix_2 (fixP, (addressT) val);
4266 }
4267 #endif
4268
4269 /* *fragP has been relaxed to its final size, and now needs to have
4270 the bytes inside it modified to conform to the new size There is UGLY
4271 MAGIC here. ..
4272 */
4273 static void
4274 md_convert_frag_1 (fragP)
4275 register fragS *fragP;
4276 {
4277 long disp;
4278 long ext = 0;
4279 fixS *fixP;
4280
4281 /* Address in object code of the displacement. */
4282 register int object_address = fragP->fr_fix + fragP->fr_address;
4283
4284 /* Address in gas core of the place to store the displacement. */
4285 /* This convinces the native rs6000 compiler to generate the code we
4286 want. */
4287 register char *buffer_address = fragP->fr_literal;
4288 buffer_address += fragP->fr_fix;
4289 /* end ibm compiler workaround */
4290
4291 /* The displacement of the address, from current location. */
4292 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4293 disp = (disp + fragP->fr_offset) - object_address;
4294
4295 #ifdef BFD_ASSEMBLER
4296 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
4297 #endif
4298
4299 switch (fragP->fr_subtype)
4300 {
4301 case TAB (BCC68000, BYTE):
4302 case TAB (ABRANCH, BYTE):
4303 know (issbyte (disp));
4304 if (disp == 0)
4305 as_bad (_("short branch with zero offset: use :w"));
4306 fragP->fr_opcode[1] = disp;
4307 ext = 0;
4308 break;
4309 case TAB (DBCC, SHORT):
4310 know (issword (disp));
4311 ext = 2;
4312 break;
4313 case TAB (BCC68000, SHORT):
4314 case TAB (ABRANCH, SHORT):
4315 know (issword (disp));
4316 fragP->fr_opcode[1] = 0x00;
4317 ext = 2;
4318 break;
4319 case TAB (ABRANCH, LONG):
4320 if (!HAVE_LONG_BRANCH(current_architecture))
4321 {
4322 if (fragP->fr_opcode[0] == 0x61)
4323 /* BSR */
4324 {
4325 fragP->fr_opcode[0] = 0x4E;
4326 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4327
4328 fix_new (fragP,
4329 fragP->fr_fix,
4330 4,
4331 fragP->fr_symbol,
4332 fragP->fr_offset,
4333 0,
4334 NO_RELOC);
4335
4336 fragP->fr_fix += 4;
4337 ext = 0;
4338 }
4339 /* BRA */
4340 else if (fragP->fr_opcode[0] == 0x60)
4341 {
4342 fragP->fr_opcode[0] = 0x4E;
4343 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4344 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4345 fragP->fr_offset, 0, NO_RELOC);
4346 fragP->fr_fix += 4;
4347 ext = 0;
4348 }
4349 else
4350 {
4351 /* This should never happen, because if it's a conditional
4352 branch and we are on a 68000, BCC68000 should have been
4353 picked instead of ABRANCH. */
4354 abort ();
4355 }
4356 }
4357 else
4358 {
4359 fragP->fr_opcode[1] = (char) 0xff;
4360 ext = 4;
4361 }
4362 break;
4363 case TAB (BCC68000, LONG):
4364 /* only Bcc 68000 instructions can come here */
4365 /* change bcc into b!cc/jmp absl long */
4366 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4367 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4368
4369 /* JF: these used to be fr_opcode[2,3], but they may be in a
4370 different frag, in which case refering to them is a no-no.
4371 Only fr_opcode[0,1] are guaranteed to work. */
4372 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4373 *buffer_address++ = (char) 0xf9;
4374 fragP->fr_fix += 2; /* account for jmp instruction */
4375 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4376 fragP->fr_offset, 0, NO_RELOC);
4377 fragP->fr_fix += 4;
4378 ext = 0;
4379 break;
4380 case TAB (DBCC, LONG):
4381 /* only DBcc 68000 instructions can come here */
4382 /* change dbcc into dbcc/jmp absl long */
4383 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4384 *buffer_address++ = 0x00; /* branch offset = 4 */
4385 *buffer_address++ = 0x04;
4386 *buffer_address++ = 0x60; /* put in bra pc+6 */
4387 *buffer_address++ = 0x06;
4388 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4389 *buffer_address++ = (char) 0xf9;
4390
4391 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4392 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4393 fragP->fr_offset, 0, NO_RELOC);
4394 fragP->fr_fix += 4;
4395 ext = 0;
4396 break;
4397 case TAB (FBRANCH, SHORT):
4398 know ((fragP->fr_opcode[1] & 0x40) == 0);
4399 ext = 2;
4400 break;
4401 case TAB (FBRANCH, LONG):
4402 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4403 ext = 4;
4404 break;
4405 case TAB (PCREL, SHORT):
4406 ext = 2;
4407 break;
4408 case TAB (PCREL, LONG):
4409 /* The thing to do here is force it to ABSOLUTE LONG, since
4410 PCREL is really trying to shorten an ABSOLUTE address anyway */
4411 /* JF FOO This code has not been tested */
4412 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4413 0, NO_RELOC);
4414 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4415 as_bad (_("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx"),
4416 (unsigned) fragP->fr_opcode[0],
4417 (unsigned long) fragP->fr_address);
4418 fragP->fr_opcode[1] &= ~0x3F;
4419 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4420 fragP->fr_fix += 4;
4421 ext = 0;
4422 break;
4423 case TAB (PCLEA, SHORT):
4424 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4425 fragP->fr_offset, 1, NO_RELOC);
4426 fragP->fr_opcode[1] &= ~0x3F;
4427 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4428 ext = 2;
4429 break;
4430 case TAB (PCLEA, LONG):
4431 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4432 fragP->fr_offset, 1, NO_RELOC);
4433 fixP->fx_pcrel_adjust = 2;
4434 /* Already set to mode 7.3; this indicates: PC indirect with
4435 suppressed index, 32-bit displacement. */
4436 *buffer_address++ = 0x01;
4437 *buffer_address++ = 0x70;
4438 fragP->fr_fix += 2;
4439 ext = 4;
4440 break;
4441
4442 case TAB (PCINDEX, BYTE):
4443 disp += 2;
4444 if (!issbyte (disp))
4445 {
4446 as_bad (_("displacement doesn't fit in one byte"));
4447 disp = 0;
4448 }
4449 assert (fragP->fr_fix >= 2);
4450 buffer_address[-2] &= ~1;
4451 buffer_address[-1] = disp;
4452 ext = 0;
4453 break;
4454 case TAB (PCINDEX, SHORT):
4455 disp += 2;
4456 assert (issword (disp));
4457 assert (fragP->fr_fix >= 2);
4458 buffer_address[-2] |= 0x1;
4459 buffer_address[-1] = 0x20;
4460 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4461 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4462 NO_RELOC);
4463 fixP->fx_pcrel_adjust = 2;
4464 ext = 2;
4465 break;
4466 case TAB (PCINDEX, LONG):
4467 disp += 2;
4468 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4469 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4470 NO_RELOC);
4471 fixP->fx_pcrel_adjust = 2;
4472 assert (fragP->fr_fix >= 2);
4473 buffer_address[-2] |= 0x1;
4474 buffer_address[-1] = 0x30;
4475 ext = 4;
4476 break;
4477 }
4478
4479 if (ext)
4480 {
4481 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4482 fragP->fr_fix += ext;
4483 }
4484 }
4485
4486 #ifndef BFD_ASSEMBLER
4487
4488 void
4489 md_convert_frag (headers, sec, fragP)
4490 object_headers *headers ATTRIBUTE_UNUSED;
4491 segT sec ATTRIBUTE_UNUSED;
4492 fragS *fragP;
4493 {
4494 md_convert_frag_1 (fragP);
4495 }
4496
4497 #else
4498
4499 void
4500 md_convert_frag (abfd, sec, fragP)
4501 bfd *abfd ATTRIBUTE_UNUSED;
4502 segT sec ATTRIBUTE_UNUSED;
4503 fragS *fragP;
4504 {
4505 md_convert_frag_1 (fragP);
4506 }
4507 #endif
4508
4509 /* Force truly undefined symbols to their maximum size, and generally set up
4510 the frag list to be relaxed
4511 */
4512 int
4513 md_estimate_size_before_relax (fragP, segment)
4514 register fragS *fragP;
4515 segT segment;
4516 {
4517 int old_fix;
4518 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4519
4520 old_fix = fragP->fr_fix;
4521
4522 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4523 switch (fragP->fr_subtype)
4524 {
4525
4526 case TAB (ABRANCH, SZ_UNDEF):
4527 {
4528 if ((fragP->fr_symbol != NULL) /* Not absolute */
4529 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4530 && relaxable_symbol (fragP->fr_symbol))
4531 {
4532 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4533 break;
4534 }
4535 else if ((fragP->fr_symbol != NULL) && flag_short_refs)
4536 { /* Symbol is undefined and we want short ref */
4537 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4538 fragP->fr_offset, 1, NO_RELOC);
4539 fragP->fr_fix += 2;
4540 frag_wane (fragP);
4541 break;
4542 }
4543 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4544 {
4545 /* On 68000, or for absolute value, switch to abs long */
4546 /* FIXME, we should check abs val, pick short or long */
4547 if (fragP->fr_opcode[0] == 0x61)
4548 {
4549 fragP->fr_opcode[0] = 0x4E;
4550 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4551 fix_new (fragP, fragP->fr_fix, 4,
4552 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4553 fragP->fr_fix += 4;
4554 frag_wane (fragP);
4555 }
4556 else if (fragP->fr_opcode[0] == 0x60)
4557 {
4558 fragP->fr_opcode[0] = 0x4E;
4559 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4560 fix_new (fragP, fragP->fr_fix, 4,
4561 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4562 fragP->fr_fix += 4;
4563 frag_wane (fragP);
4564 }
4565 else
4566 {
4567 /* This should never happen, because if it's a conditional
4568 branch and we are on a 68000, BCC68000 should have been
4569 picked instead of ABRANCH. */
4570 abort ();
4571 }
4572 }
4573 else
4574 { /* Symbol is still undefined. Make it simple */
4575 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4576 fragP->fr_offset, 1, NO_RELOC);
4577 fragP->fr_fix += 4;
4578 fragP->fr_opcode[1] = (char) 0xff;
4579 frag_wane (fragP);
4580 break;
4581 }
4582
4583 break;
4584 } /* case TAB(ABRANCH,SZ_UNDEF) */
4585
4586 case TAB (FBRANCH, SZ_UNDEF):
4587 {
4588 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4589 && relaxable_symbol (fragP->fr_symbol))
4590 || flag_short_refs)
4591 {
4592 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4593 fragP->fr_var += 2;
4594 }
4595 else
4596 {
4597 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4598 fragP->fr_offset, 1, NO_RELOC);
4599 fragP->fr_fix += 4;
4600 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4601 frag_wane (fragP);
4602 }
4603 break;
4604 } /* TAB(FBRANCH,SZ_UNDEF) */
4605
4606 case TAB (PCREL, SZ_UNDEF):
4607 {
4608 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4609 && relaxable_symbol (fragP->fr_symbol))
4610 || flag_short_refs)
4611 {
4612 fragP->fr_subtype = TAB (PCREL, SHORT);
4613 fragP->fr_var += 2;
4614 }
4615 else
4616 {
4617 fragP->fr_subtype = TAB (PCREL, LONG);
4618 fragP->fr_var += 4;
4619 }
4620 break;
4621 } /* TAB(PCREL,SZ_UNDEF) */
4622
4623 case TAB (BCC68000, SZ_UNDEF):
4624 {
4625 if ((fragP->fr_symbol != NULL)
4626 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4627 && relaxable_symbol (fragP->fr_symbol))
4628 {
4629 fragP->fr_subtype = TAB (BCC68000, BYTE);
4630 break;
4631 }
4632 /* only Bcc 68000 instructions can come here */
4633 if ((fragP->fr_symbol != NULL) && flag_short_refs)
4634 {
4635 /* the user wants short refs, so emit one */
4636 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4637 fragP->fr_offset, 1, NO_RELOC);
4638 fragP->fr_fix += 2;
4639 }
4640 else
4641 {
4642 /* change bcc into b!cc/jmp absl long */
4643 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4644 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4645 /* JF: these were fr_opcode[2,3] */
4646 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4647 buffer_address[1] = (char) 0xf9;
4648 fragP->fr_fix += 2; /* account for jmp instruction */
4649 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4650 fragP->fr_offset, 0, NO_RELOC);
4651 fragP->fr_fix += 4;
4652 }
4653 frag_wane (fragP);
4654 break;
4655 } /* case TAB(BCC68000,SZ_UNDEF) */
4656
4657 case TAB (DBCC, SZ_UNDEF):
4658 {
4659 if (fragP->fr_symbol != NULL
4660 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4661 && relaxable_symbol (fragP->fr_symbol))
4662 {
4663 fragP->fr_subtype = TAB (DBCC, SHORT);
4664 fragP->fr_var += 2;
4665 break;
4666 }
4667 /* only DBcc 68000 instructions can come here */
4668
4669 if (fragP->fr_symbol != NULL && flag_short_refs)
4670 {
4671 /* the user wants short refs, so emit one */
4672 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4673 fragP->fr_offset, 1, NO_RELOC);
4674 fragP->fr_fix += 2;
4675 }
4676 else
4677 {
4678 /* change dbcc into dbcc/jmp absl long */
4679 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4680 buffer_address[0] = 0x00; /* branch offset = 4 */
4681 buffer_address[1] = 0x04;
4682 buffer_address[2] = 0x60; /* put in bra pc + ... */
4683 /* JF: these were fr_opcode[5-7] */
4684 buffer_address[3] = 0x06; /* Plus 6 */
4685 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4686 buffer_address[5] = (char) 0xf9;
4687 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4688 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4689 fragP->fr_offset, 0, NO_RELOC);
4690 fragP->fr_fix += 4;
4691 }
4692
4693 frag_wane (fragP);
4694 break;
4695 } /* case TAB(DBCC,SZ_UNDEF) */
4696
4697 case TAB (PCLEA, SZ_UNDEF):
4698 {
4699 if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4700 && relaxable_symbol (fragP->fr_symbol))
4701 || flag_short_refs
4702 || cpu_of_arch (current_architecture) < m68020
4703 || cpu_of_arch (current_architecture) == mcf5200)
4704 {
4705 fragP->fr_subtype = TAB (PCLEA, SHORT);
4706 fragP->fr_var += 2;
4707 }
4708 else
4709 {
4710 fragP->fr_subtype = TAB (PCLEA, LONG);
4711 fragP->fr_var += 6;
4712 }
4713 break;
4714 } /* TAB(PCLEA,SZ_UNDEF) */
4715
4716 case TAB (PCINDEX, SZ_UNDEF):
4717 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4718 && relaxable_symbol (fragP->fr_symbol))
4719 || cpu_of_arch (current_architecture) < m68020
4720 || cpu_of_arch (current_architecture) == mcf5200)
4721 {
4722 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4723 }
4724 else
4725 {
4726 fragP->fr_subtype = TAB (PCINDEX, LONG);
4727 fragP->fr_var += 4;
4728 }
4729 break;
4730
4731 default:
4732 break;
4733 }
4734
4735 /* now that SZ_UNDEF are taken care of, check others */
4736 switch (fragP->fr_subtype)
4737 {
4738 case TAB (BCC68000, BYTE):
4739 case TAB (ABRANCH, BYTE):
4740 /* We can't do a short jump to the next instruction, so in that
4741 case we force word mode. At this point S_GET_VALUE should
4742 return the offset of the symbol within its frag. If the
4743 symbol is at the start of a frag, and it is the next frag
4744 with any data in it (usually this is just the next frag, but
4745 assembler listings may introduce empty frags), we must use
4746 word mode. */
4747 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4748 {
4749 fragS *stop;
4750 fragS *l;
4751
4752 stop = symbol_get_frag (fragP->fr_symbol);
4753 for (l = fragP->fr_next; l != stop; l = l->fr_next)
4754 if (l->fr_fix + l->fr_var != 0)
4755 break;
4756 if (l == stop)
4757 {
4758 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4759 fragP->fr_var += 2;
4760 }
4761 }
4762 break;
4763 default:
4764 break;
4765 }
4766 return fragP->fr_var + fragP->fr_fix - old_fix;
4767 }
4768
4769 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4770 /* the bit-field entries in the relocation_info struct plays hell
4771 with the byte-order problems of cross-assembly. So as a hack,
4772 I added this mach. dependent ri twiddler. Ugly, but it gets
4773 you there. -KWK */
4774 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4775 are symbolnum, most sig. byte first. Last byte is broken up with
4776 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4777 nibble as nuthin. (on Sun 3 at least) */
4778 /* Translate the internal relocation information into target-specific
4779 format. */
4780 #ifdef comment
4781 void
4782 md_ri_to_chars (the_bytes, ri)
4783 char *the_bytes;
4784 struct reloc_info_generic *ri;
4785 {
4786 /* this is easy */
4787 md_number_to_chars (the_bytes, ri->r_address, 4);
4788 /* now the fun stuff */
4789 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4790 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4791 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4792 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4793 ((ri->r_extern << 4) & 0x10));
4794 }
4795
4796 #endif /* comment */
4797
4798 #ifndef BFD_ASSEMBLER
4799 void
4800 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4801 char *where;
4802 fixS *fixP;
4803 relax_addressT segment_address_in_file;
4804 {
4805 /*
4806 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4807 * Out: GNU LD relocation length code: 0, 1, or 2.
4808 */
4809
4810 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4811 long r_symbolnum;
4812
4813 know (fixP->fx_addsy != NULL);
4814
4815 md_number_to_chars (where,
4816 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4817 4);
4818
4819 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4820 ? S_GET_TYPE (fixP->fx_addsy)
4821 : fixP->fx_addsy->sy_number);
4822
4823 where[4] = (r_symbolnum >> 16) & 0x0ff;
4824 where[5] = (r_symbolnum >> 8) & 0x0ff;
4825 where[6] = r_symbolnum & 0x0ff;
4826 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4827 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4828 }
4829 #endif
4830
4831 #endif /* OBJ_AOUT or OBJ_BOUT */
4832
4833 #ifndef WORKING_DOT_WORD
4834 CONST int md_short_jump_size = 4;
4835 CONST int md_long_jump_size = 6;
4836
4837 void
4838 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4839 char *ptr;
4840 addressT from_addr, to_addr;
4841 fragS *frag ATTRIBUTE_UNUSED;
4842 symbolS *to_symbol ATTRIBUTE_UNUSED;
4843 {
4844 valueT offset;
4845
4846 offset = to_addr - (from_addr + 2);
4847
4848 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4849 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4850 }
4851
4852 void
4853 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4854 char *ptr;
4855 addressT from_addr, to_addr;
4856 fragS *frag;
4857 symbolS *to_symbol;
4858 {
4859 valueT offset;
4860
4861 if (!HAVE_LONG_BRANCH(current_architecture))
4862 {
4863 offset = to_addr - S_GET_VALUE (to_symbol);
4864 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4865 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4866 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4867 0, NO_RELOC);
4868 }
4869 else
4870 {
4871 offset = to_addr - (from_addr + 2);
4872 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4873 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4874 }
4875 }
4876
4877 #endif
4878
4879 /* Different values of OK tell what its OK to return. Things that
4880 aren't OK are an error (what a shock, no?)
4881
4882 0: Everything is OK
4883 10: Absolute 1:8 only
4884 20: Absolute 0:7 only
4885 30: absolute 0:15 only
4886 40: Absolute 0:31 only
4887 50: absolute 0:127 only
4888 55: absolute -64:63 only
4889 60: absolute -128:127 only
4890 70: absolute 0:4095 only
4891 80: No bignums
4892
4893 */
4894
4895 static int
4896 get_num (exp, ok)
4897 struct m68k_exp *exp;
4898 int ok;
4899 {
4900 if (exp->exp.X_op == O_absent)
4901 {
4902 /* Do the same thing the VAX asm does */
4903 op (exp) = O_constant;
4904 adds (exp) = 0;
4905 subs (exp) = 0;
4906 offs (exp) = 0;
4907 if (ok == 10)
4908 {
4909 as_warn (_("expression out of range: defaulting to 1"));
4910 offs (exp) = 1;
4911 }
4912 }
4913 else if (exp->exp.X_op == O_constant)
4914 {
4915 switch (ok)
4916 {
4917 case 10:
4918 if (offs (exp) < 1 || offs (exp) > 8)
4919 {
4920 as_warn (_("expression out of range: defaulting to 1"));
4921 offs (exp) = 1;
4922 }
4923 break;
4924 case 20:
4925 if (offs (exp) < 0 || offs (exp) > 7)
4926 goto outrange;
4927 break;
4928 case 30:
4929 if (offs (exp) < 0 || offs (exp) > 15)
4930 goto outrange;
4931 break;
4932 case 40:
4933 if (offs (exp) < 0 || offs (exp) > 32)
4934 goto outrange;
4935 break;
4936 case 50:
4937 if (offs (exp) < 0 || offs (exp) > 127)
4938 goto outrange;
4939 break;
4940 case 55:
4941 if (offs (exp) < -64 || offs (exp) > 63)
4942 goto outrange;
4943 break;
4944 case 60:
4945 if (offs (exp) < -128 || offs (exp) > 127)
4946 goto outrange;
4947 break;
4948 case 70:
4949 if (offs (exp) < 0 || offs (exp) > 4095)
4950 {
4951 outrange:
4952 as_warn (_("expression out of range: defaulting to 0"));
4953 offs (exp) = 0;
4954 }
4955 break;
4956 default:
4957 break;
4958 }
4959 }
4960 else if (exp->exp.X_op == O_big)
4961 {
4962 if (offs (exp) <= 0 /* flonum */
4963 && (ok == 80 /* no bignums */
4964 || (ok > 10 /* small-int ranges including 0 ok */
4965 /* If we have a flonum zero, a zero integer should
4966 do as well (e.g., in moveq). */
4967 && generic_floating_point_number.exponent == 0
4968 && generic_floating_point_number.low[0] == 0)))
4969 {
4970 /* HACK! Turn it into a long */
4971 LITTLENUM_TYPE words[6];
4972
4973 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4974 op (exp) = O_constant;
4975 adds (exp) = 0;
4976 subs (exp) = 0;
4977 offs (exp) = words[1] | (words[0] << 16);
4978 }
4979 else if (ok != 0)
4980 {
4981 op (exp) = O_constant;
4982 adds (exp) = 0;
4983 subs (exp) = 0;
4984 offs (exp) = (ok == 10) ? 1 : 0;
4985 as_warn (_("Can't deal with expression; defaulting to %ld"),
4986 offs (exp));
4987 }
4988 }
4989 else
4990 {
4991 if (ok >= 10 && ok <= 70)
4992 {
4993 op (exp) = O_constant;
4994 adds (exp) = 0;
4995 subs (exp) = 0;
4996 offs (exp) = (ok == 10) ? 1 : 0;
4997 as_warn (_("Can't deal with expression; defaulting to %ld"),
4998 offs (exp));
4999 }
5000 }
5001
5002 if (exp->size != SIZE_UNSPEC)
5003 {
5004 switch (exp->size)
5005 {
5006 case SIZE_UNSPEC:
5007 case SIZE_LONG:
5008 break;
5009 case SIZE_BYTE:
5010 if (!isbyte (offs (exp)))
5011 as_warn (_("expression doesn't fit in BYTE"));
5012 break;
5013 case SIZE_WORD:
5014 if (!isword (offs (exp)))
5015 as_warn (_("expression doesn't fit in WORD"));
5016 break;
5017 }
5018 }
5019
5020 return offs (exp);
5021 }
5022
5023 /* These are the back-ends for the various machine dependent pseudo-ops. */
5024
5025 static void
5026 s_data1 (ignore)
5027 int ignore ATTRIBUTE_UNUSED;
5028 {
5029 subseg_set (data_section, 1);
5030 demand_empty_rest_of_line ();
5031 }
5032
5033 static void
5034 s_data2 (ignore)
5035 int ignore ATTRIBUTE_UNUSED;
5036 {
5037 subseg_set (data_section, 2);
5038 demand_empty_rest_of_line ();
5039 }
5040
5041 static void
5042 s_bss (ignore)
5043 int ignore ATTRIBUTE_UNUSED;
5044 {
5045 /* We don't support putting frags in the BSS segment, we fake it
5046 by marking in_bss, then looking at s_skip for clues. */
5047
5048 subseg_set (bss_section, 0);
5049 demand_empty_rest_of_line ();
5050 }
5051
5052 static void
5053 s_even (ignore)
5054 int ignore ATTRIBUTE_UNUSED;
5055 {
5056 register int temp;
5057 register long temp_fill;
5058
5059 temp = 1; /* JF should be 2? */
5060 temp_fill = get_absolute_expression ();
5061 if (!need_pass_2) /* Never make frag if expect extra pass. */
5062 frag_align (temp, (int) temp_fill, 0);
5063 demand_empty_rest_of_line ();
5064 record_alignment (now_seg, temp);
5065 }
5066
5067 static void
5068 s_proc (ignore)
5069 int ignore ATTRIBUTE_UNUSED;
5070 {
5071 demand_empty_rest_of_line ();
5072 }
5073 \f
5074 /* Pseudo-ops handled for MRI compatibility. */
5075
5076 /* This function returns non-zero if the argument is a conditional
5077 pseudo-op. This is called when checking whether a pending
5078 alignment is needed. */
5079
5080 int
5081 m68k_conditional_pseudoop (pop)
5082 pseudo_typeS *pop;
5083 {
5084 return (pop->poc_handler == s_mri_if
5085 || pop->poc_handler == s_mri_else);
5086 }
5087
5088 /* Handle an MRI style chip specification. */
5089
5090 static void
5091 mri_chip ()
5092 {
5093 char *s;
5094 char c;
5095 int i;
5096
5097 s = input_line_pointer;
5098 /* We can't use get_symbol_end since the processor names are not proper
5099 symbols. */
5100 while (is_part_of_name (c = *input_line_pointer++))
5101 ;
5102 *--input_line_pointer = 0;
5103 for (i = 0; i < n_archs; i++)
5104 if (strcasecmp (s, archs[i].name) == 0)
5105 break;
5106 if (i >= n_archs)
5107 {
5108 as_bad (_("%s: unrecognized processor name"), s);
5109 *input_line_pointer = c;
5110 ignore_rest_of_line ();
5111 return;
5112 }
5113 *input_line_pointer = c;
5114
5115 if (*input_line_pointer == '/')
5116 current_architecture = 0;
5117 else
5118 current_architecture &= m68881 | m68851;
5119 current_architecture |= archs[i].arch;
5120
5121 while (*input_line_pointer == '/')
5122 {
5123 ++input_line_pointer;
5124 s = input_line_pointer;
5125 /* We can't use get_symbol_end since the processor names are not
5126 proper symbols. */
5127 while (is_part_of_name (c = *input_line_pointer++))
5128 ;
5129 *--input_line_pointer = 0;
5130 if (strcmp (s, "68881") == 0)
5131 current_architecture |= m68881;
5132 else if (strcmp (s, "68851") == 0)
5133 current_architecture |= m68851;
5134 *input_line_pointer = c;
5135 }
5136
5137 /* Update info about available control registers. */
5138 select_control_regs ();
5139 }
5140
5141 /* The MRI CHIP pseudo-op. */
5142
5143 static void
5144 s_chip (ignore)
5145 int ignore ATTRIBUTE_UNUSED;
5146 {
5147 char *stop = NULL;
5148 char stopc;
5149
5150 if (flag_mri)
5151 stop = mri_comment_field (&stopc);
5152 mri_chip ();
5153 if (flag_mri)
5154 mri_comment_end (stop, stopc);
5155 demand_empty_rest_of_line ();
5156 }
5157
5158 /* The MRI FOPT pseudo-op. */
5159
5160 static void
5161 s_fopt (ignore)
5162 int ignore ATTRIBUTE_UNUSED;
5163 {
5164 SKIP_WHITESPACE ();
5165
5166 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5167 {
5168 int temp;
5169
5170 input_line_pointer += 3;
5171 temp = get_absolute_expression ();
5172 if (temp < 0 || temp > 7)
5173 as_bad (_("bad coprocessor id"));
5174 else
5175 m68k_float_copnum = COP0 + temp;
5176 }
5177 else
5178 {
5179 as_bad (_("unrecognized fopt option"));
5180 ignore_rest_of_line ();
5181 return;
5182 }
5183
5184 demand_empty_rest_of_line ();
5185 }
5186
5187 /* The structure used to handle the MRI OPT pseudo-op. */
5188
5189 struct opt_action
5190 {
5191 /* The name of the option. */
5192 const char *name;
5193
5194 /* If this is not NULL, just call this function. The first argument
5195 is the ARG field of this structure, the second argument is
5196 whether the option was negated. */
5197 void (*pfn) PARAMS ((int arg, int on));
5198
5199 /* If this is not NULL, and the PFN field is NULL, set the variable
5200 this points to. Set it to the ARG field if the option was not
5201 negated, and the NOTARG field otherwise. */
5202 int *pvar;
5203
5204 /* The value to pass to PFN or to assign to *PVAR. */
5205 int arg;
5206
5207 /* The value to assign to *PVAR if the option is negated. If PFN is
5208 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5209 the option may not be negated. */
5210 int notarg;
5211 };
5212
5213 /* The table used to handle the MRI OPT pseudo-op. */
5214
5215 static void skip_to_comma PARAMS ((int, int));
5216 static void opt_nest PARAMS ((int, int));
5217 static void opt_chip PARAMS ((int, int));
5218 static void opt_list PARAMS ((int, int));
5219 static void opt_list_symbols PARAMS ((int, int));
5220
5221 static const struct opt_action opt_table[] =
5222 {
5223 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5224
5225 /* We do relaxing, so there is little use for these options. */
5226 { "b", 0, 0, 0, 0 },
5227 { "brs", 0, 0, 0, 0 },
5228 { "brb", 0, 0, 0, 0 },
5229 { "brl", 0, 0, 0, 0 },
5230 { "brw", 0, 0, 0, 0 },
5231
5232 { "c", 0, 0, 0, 0 },
5233 { "cex", 0, 0, 0, 0 },
5234 { "case", 0, &symbols_case_sensitive, 1, 0 },
5235 { "cl", 0, 0, 0, 0 },
5236 { "cre", 0, 0, 0, 0 },
5237 { "d", 0, &flag_keep_locals, 1, 0 },
5238 { "e", 0, 0, 0, 0 },
5239 { "f", 0, &flag_short_refs, 1, 0 },
5240 { "frs", 0, &flag_short_refs, 1, 0 },
5241 { "frl", 0, &flag_short_refs, 0, 1 },
5242 { "g", 0, 0, 0, 0 },
5243 { "i", 0, 0, 0, 0 },
5244 { "m", 0, 0, 0, 0 },
5245 { "mex", 0, 0, 0, 0 },
5246 { "mc", 0, 0, 0, 0 },
5247 { "md", 0, 0, 0, 0 },
5248 { "nest", opt_nest, 0, 0, 0 },
5249 { "next", skip_to_comma, 0, 0, 0 },
5250 { "o", 0, 0, 0, 0 },
5251 { "old", 0, 0, 0, 0 },
5252 { "op", skip_to_comma, 0, 0, 0 },
5253 { "pco", 0, 0, 0, 0 },
5254 { "p", opt_chip, 0, 0, 0 },
5255 { "pcr", 0, 0, 0, 0 },
5256 { "pcs", 0, 0, 0, 0 },
5257 { "r", 0, 0, 0, 0 },
5258 { "quick", 0, &m68k_quick, 1, 0 },
5259 { "rel32", 0, &m68k_rel32, 1, 0 },
5260 { "s", opt_list, 0, 0, 0 },
5261 { "t", opt_list_symbols, 0, 0, 0 },
5262 { "w", 0, &flag_no_warnings, 0, 1 },
5263 { "x", 0, 0, 0, 0 }
5264 };
5265
5266 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5267
5268 /* The MRI OPT pseudo-op. */
5269
5270 static void
5271 s_opt (ignore)
5272 int ignore ATTRIBUTE_UNUSED;
5273 {
5274 do
5275 {
5276 int t;
5277 char *s;
5278 char c;
5279 int i;
5280 const struct opt_action *o;
5281
5282 SKIP_WHITESPACE ();
5283
5284 t = 1;
5285 if (*input_line_pointer == '-')
5286 {
5287 ++input_line_pointer;
5288 t = 0;
5289 }
5290 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5291 {
5292 input_line_pointer += 2;
5293 t = 0;
5294 }
5295
5296 s = input_line_pointer;
5297 c = get_symbol_end ();
5298
5299 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5300 {
5301 if (strcasecmp (s, o->name) == 0)
5302 {
5303 if (o->pfn)
5304 {
5305 /* Restore input_line_pointer now in case the option
5306 takes arguments. */
5307 *input_line_pointer = c;
5308 (*o->pfn) (o->arg, t);
5309 }
5310 else if (o->pvar != NULL)
5311 {
5312 if (! t && o->arg == o->notarg)
5313 as_bad (_("option `%s' may not be negated"), s);
5314 *input_line_pointer = c;
5315 *o->pvar = t ? o->arg : o->notarg;
5316 }
5317 else
5318 *input_line_pointer = c;
5319 break;
5320 }
5321 }
5322 if (i >= OPTCOUNT)
5323 {
5324 as_bad (_("option `%s' not recognized"), s);
5325 *input_line_pointer = c;
5326 }
5327 }
5328 while (*input_line_pointer++ == ',');
5329
5330 /* Move back to terminating character. */
5331 --input_line_pointer;
5332 demand_empty_rest_of_line ();
5333 }
5334
5335 /* Skip ahead to a comma. This is used for OPT options which we do
5336 not suppor tand which take arguments. */
5337
5338 static void
5339 skip_to_comma (arg, on)
5340 int arg ATTRIBUTE_UNUSED;
5341 int on ATTRIBUTE_UNUSED;
5342 {
5343 while (*input_line_pointer != ','
5344 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5345 ++input_line_pointer;
5346 }
5347
5348 /* Handle the OPT NEST=depth option. */
5349
5350 static void
5351 opt_nest (arg, on)
5352 int arg ATTRIBUTE_UNUSED;
5353 int on ATTRIBUTE_UNUSED;
5354 {
5355 if (*input_line_pointer != '=')
5356 {
5357 as_bad (_("bad format of OPT NEST=depth"));
5358 return;
5359 }
5360
5361 ++input_line_pointer;
5362 max_macro_nest = get_absolute_expression ();
5363 }
5364
5365 /* Handle the OPT P=chip option. */
5366
5367 static void
5368 opt_chip (arg, on)
5369 int arg ATTRIBUTE_UNUSED;
5370 int on ATTRIBUTE_UNUSED;
5371 {
5372 if (*input_line_pointer != '=')
5373 {
5374 /* This is just OPT P, which we do not support. */
5375 return;
5376 }
5377
5378 ++input_line_pointer;
5379 mri_chip ();
5380 }
5381
5382 /* Handle the OPT S option. */
5383
5384 static void
5385 opt_list (arg, on)
5386 int arg ATTRIBUTE_UNUSED;
5387 int on;
5388 {
5389 listing_list (on);
5390 }
5391
5392 /* Handle the OPT T option. */
5393
5394 static void
5395 opt_list_symbols (arg, on)
5396 int arg ATTRIBUTE_UNUSED;
5397 int on;
5398 {
5399 if (on)
5400 listing |= LISTING_SYMBOLS;
5401 else
5402 listing &=~ LISTING_SYMBOLS;
5403 }
5404
5405 /* Handle the MRI REG pseudo-op. */
5406
5407 static void
5408 s_reg (ignore)
5409 int ignore ATTRIBUTE_UNUSED;
5410 {
5411 char *s;
5412 int c;
5413 struct m68k_op rop;
5414 int mask;
5415 char *stop = NULL;
5416 char stopc;
5417
5418 if (line_label == NULL)
5419 {
5420 as_bad (_("missing label"));
5421 ignore_rest_of_line ();
5422 return;
5423 }
5424
5425 if (flag_mri)
5426 stop = mri_comment_field (&stopc);
5427
5428 SKIP_WHITESPACE ();
5429
5430 s = input_line_pointer;
5431 while (isalnum ((unsigned char) *input_line_pointer)
5432 #ifdef REGISTER_PREFIX
5433 || *input_line_pointer == REGISTER_PREFIX
5434 #endif
5435 || *input_line_pointer == '/'
5436 || *input_line_pointer == '-')
5437 ++input_line_pointer;
5438 c = *input_line_pointer;
5439 *input_line_pointer = '\0';
5440
5441 if (m68k_ip_op (s, &rop) != 0)
5442 {
5443 if (rop.error == NULL)
5444 as_bad (_("bad register list"));
5445 else
5446 as_bad (_("bad register list: %s"), rop.error);
5447 *input_line_pointer = c;
5448 ignore_rest_of_line ();
5449 return;
5450 }
5451
5452 *input_line_pointer = c;
5453
5454 if (rop.mode == REGLST)
5455 mask = rop.mask;
5456 else if (rop.mode == DREG)
5457 mask = 1 << (rop.reg - DATA0);
5458 else if (rop.mode == AREG)
5459 mask = 1 << (rop.reg - ADDR0 + 8);
5460 else if (rop.mode == FPREG)
5461 mask = 1 << (rop.reg - FP0 + 16);
5462 else if (rop.mode == CONTROL
5463 && rop.reg == FPI)
5464 mask = 1 << 24;
5465 else if (rop.mode == CONTROL
5466 && rop.reg == FPS)
5467 mask = 1 << 25;
5468 else if (rop.mode == CONTROL
5469 && rop.reg == FPC)
5470 mask = 1 << 26;
5471 else
5472 {
5473 as_bad (_("bad register list"));
5474 ignore_rest_of_line ();
5475 return;
5476 }
5477
5478 S_SET_SEGMENT (line_label, reg_section);
5479 S_SET_VALUE (line_label, ~mask);
5480 symbol_set_frag (line_label, &zero_address_frag);
5481
5482 if (flag_mri)
5483 mri_comment_end (stop, stopc);
5484
5485 demand_empty_rest_of_line ();
5486 }
5487
5488 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5489
5490 struct save_opts
5491 {
5492 struct save_opts *next;
5493 int abspcadd;
5494 int symbols_case_sensitive;
5495 int keep_locals;
5496 int short_refs;
5497 int architecture;
5498 int quick;
5499 int rel32;
5500 int listing;
5501 int no_warnings;
5502 /* FIXME: We don't save OPT S. */
5503 };
5504
5505 /* This variable holds the stack of saved options. */
5506
5507 static struct save_opts *save_stack;
5508
5509 /* The MRI SAVE pseudo-op. */
5510
5511 static void
5512 s_save (ignore)
5513 int ignore ATTRIBUTE_UNUSED;
5514 {
5515 struct save_opts *s;
5516
5517 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5518 s->abspcadd = m68k_abspcadd;
5519 s->symbols_case_sensitive = symbols_case_sensitive;
5520 s->keep_locals = flag_keep_locals;
5521 s->short_refs = flag_short_refs;
5522 s->architecture = current_architecture;
5523 s->quick = m68k_quick;
5524 s->rel32 = m68k_rel32;
5525 s->listing = listing;
5526 s->no_warnings = flag_no_warnings;
5527
5528 s->next = save_stack;
5529 save_stack = s;
5530
5531 demand_empty_rest_of_line ();
5532 }
5533
5534 /* The MRI RESTORE pseudo-op. */
5535
5536 static void
5537 s_restore (ignore)
5538 int ignore ATTRIBUTE_UNUSED;
5539 {
5540 struct save_opts *s;
5541
5542 if (save_stack == NULL)
5543 {
5544 as_bad (_("restore without save"));
5545 ignore_rest_of_line ();
5546 return;
5547 }
5548
5549 s = save_stack;
5550 save_stack = s->next;
5551
5552 m68k_abspcadd = s->abspcadd;
5553 symbols_case_sensitive = s->symbols_case_sensitive;
5554 flag_keep_locals = s->keep_locals;
5555 flag_short_refs = s->short_refs;
5556 current_architecture = s->architecture;
5557 m68k_quick = s->quick;
5558 m68k_rel32 = s->rel32;
5559 listing = s->listing;
5560 flag_no_warnings = s->no_warnings;
5561
5562 free (s);
5563
5564 demand_empty_rest_of_line ();
5565 }
5566
5567 /* Types of MRI structured control directives. */
5568
5569 enum mri_control_type
5570 {
5571 mri_for,
5572 mri_if,
5573 mri_repeat,
5574 mri_while
5575 };
5576
5577 /* This structure is used to stack the MRI structured control
5578 directives. */
5579
5580 struct mri_control_info
5581 {
5582 /* The directive within which this one is enclosed. */
5583 struct mri_control_info *outer;
5584
5585 /* The type of directive. */
5586 enum mri_control_type type;
5587
5588 /* Whether an ELSE has been in an IF. */
5589 int else_seen;
5590
5591 /* The add or sub statement at the end of a FOR. */
5592 char *incr;
5593
5594 /* The label of the top of a FOR or REPEAT loop. */
5595 char *top;
5596
5597 /* The label to jump to for the next iteration, or the else
5598 expression of a conditional. */
5599 char *next;
5600
5601 /* The label to jump to to break out of the loop, or the label past
5602 the end of a conditional. */
5603 char *bottom;
5604 };
5605
5606 /* The stack of MRI structured control directives. */
5607
5608 static struct mri_control_info *mri_control_stack;
5609
5610 /* The current MRI structured control directive index number, used to
5611 generate label names. */
5612
5613 static int mri_control_index;
5614
5615 /* Some function prototypes. */
5616
5617 static void mri_assemble PARAMS ((char *));
5618 static char *mri_control_label PARAMS ((void));
5619 static struct mri_control_info *push_mri_control
5620 PARAMS ((enum mri_control_type));
5621 static void pop_mri_control PARAMS ((void));
5622 static int parse_mri_condition PARAMS ((int *));
5623 static int parse_mri_control_operand
5624 PARAMS ((int *, char **, char **, char **, char **));
5625 static int swap_mri_condition PARAMS ((int));
5626 static int reverse_mri_condition PARAMS ((int));
5627 static void build_mri_control_operand
5628 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5629 const char *, int));
5630 static void parse_mri_control_expression
5631 PARAMS ((char *, int, const char *, const char *, int));
5632
5633 /* Assemble an instruction for an MRI structured control directive. */
5634
5635 static void
5636 mri_assemble (str)
5637 char *str;
5638 {
5639 char *s;
5640
5641 /* md_assemble expects the opcode to be in lower case. */
5642 for (s = str; *s != ' ' && *s != '\0'; s++)
5643 {
5644 if (isupper ((unsigned char) *s))
5645 *s = tolower ((unsigned char) *s);
5646 }
5647
5648 md_assemble (str);
5649 }
5650
5651 /* Generate a new MRI label structured control directive label name. */
5652
5653 static char *
5654 mri_control_label ()
5655 {
5656 char *n;
5657
5658 n = (char *) xmalloc (20);
5659 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5660 ++mri_control_index;
5661 return n;
5662 }
5663
5664 /* Create a new MRI structured control directive. */
5665
5666 static struct mri_control_info *
5667 push_mri_control (type)
5668 enum mri_control_type type;
5669 {
5670 struct mri_control_info *n;
5671
5672 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5673
5674 n->type = type;
5675 n->else_seen = 0;
5676 if (type == mri_if || type == mri_while)
5677 n->top = NULL;
5678 else
5679 n->top = mri_control_label ();
5680 n->next = mri_control_label ();
5681 n->bottom = mri_control_label ();
5682
5683 n->outer = mri_control_stack;
5684 mri_control_stack = n;
5685
5686 return n;
5687 }
5688
5689 /* Pop off the stack of MRI structured control directives. */
5690
5691 static void
5692 pop_mri_control ()
5693 {
5694 struct mri_control_info *n;
5695
5696 n = mri_control_stack;
5697 mri_control_stack = n->outer;
5698 if (n->top != NULL)
5699 free (n->top);
5700 free (n->next);
5701 free (n->bottom);
5702 free (n);
5703 }
5704
5705 /* Recognize a condition code in an MRI structured control expression. */
5706
5707 static int
5708 parse_mri_condition (pcc)
5709 int *pcc;
5710 {
5711 char c1, c2;
5712
5713 know (*input_line_pointer == '<');
5714
5715 ++input_line_pointer;
5716 c1 = *input_line_pointer++;
5717 c2 = *input_line_pointer++;
5718
5719 if (*input_line_pointer != '>')
5720 {
5721 as_bad (_("syntax error in structured control directive"));
5722 return 0;
5723 }
5724
5725 ++input_line_pointer;
5726 SKIP_WHITESPACE ();
5727
5728 if (isupper (c1))
5729 c1 = tolower (c1);
5730 if (isupper (c2))
5731 c2 = tolower (c2);
5732
5733 *pcc = (c1 << 8) | c2;
5734
5735 return 1;
5736 }
5737
5738 /* Parse a single operand in an MRI structured control expression. */
5739
5740 static int
5741 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5742 int *pcc;
5743 char **leftstart;
5744 char **leftstop;
5745 char **rightstart;
5746 char **rightstop;
5747 {
5748 char *s;
5749
5750 SKIP_WHITESPACE ();
5751
5752 *pcc = -1;
5753 *leftstart = NULL;
5754 *leftstop = NULL;
5755 *rightstart = NULL;
5756 *rightstop = NULL;
5757
5758 if (*input_line_pointer == '<')
5759 {
5760 /* It's just a condition code. */
5761 return parse_mri_condition (pcc);
5762 }
5763
5764 /* Look ahead for the condition code. */
5765 for (s = input_line_pointer; *s != '\0'; ++s)
5766 {
5767 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5768 break;
5769 }
5770 if (*s == '\0')
5771 {
5772 as_bad (_("missing condition code in structured control directive"));
5773 return 0;
5774 }
5775
5776 *leftstart = input_line_pointer;
5777 *leftstop = s;
5778 if (*leftstop > *leftstart
5779 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5780 --*leftstop;
5781
5782 input_line_pointer = s;
5783 if (! parse_mri_condition (pcc))
5784 return 0;
5785
5786 /* Look ahead for AND or OR or end of line. */
5787 for (s = input_line_pointer; *s != '\0'; ++s)
5788 {
5789 if ((strncasecmp (s, "AND", 3) == 0
5790 && (s[3] == '.' || ! is_part_of_name (s[3])))
5791 || (strncasecmp (s, "OR", 2) == 0
5792 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5793 break;
5794 }
5795
5796 *rightstart = input_line_pointer;
5797 *rightstop = s;
5798 if (*rightstop > *rightstart
5799 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5800 --*rightstop;
5801
5802 input_line_pointer = s;
5803
5804 return 1;
5805 }
5806
5807 #define MCC(b1, b2) (((b1) << 8) | (b2))
5808
5809 /* Swap the sense of a condition. This changes the condition so that
5810 it generates the same result when the operands are swapped. */
5811
5812 static int
5813 swap_mri_condition (cc)
5814 int cc;
5815 {
5816 switch (cc)
5817 {
5818 case MCC ('h', 'i'): return MCC ('c', 's');
5819 case MCC ('l', 's'): return MCC ('c', 'c');
5820 case MCC ('c', 'c'): return MCC ('l', 's');
5821 case MCC ('c', 's'): return MCC ('h', 'i');
5822 case MCC ('p', 'l'): return MCC ('m', 'i');
5823 case MCC ('m', 'i'): return MCC ('p', 'l');
5824 case MCC ('g', 'e'): return MCC ('l', 'e');
5825 case MCC ('l', 't'): return MCC ('g', 't');
5826 case MCC ('g', 't'): return MCC ('l', 't');
5827 case MCC ('l', 'e'): return MCC ('g', 'e');
5828 }
5829 return cc;
5830 }
5831
5832 /* Reverse the sense of a condition. */
5833
5834 static int
5835 reverse_mri_condition (cc)
5836 int cc;
5837 {
5838 switch (cc)
5839 {
5840 case MCC ('h', 'i'): return MCC ('l', 's');
5841 case MCC ('l', 's'): return MCC ('h', 'i');
5842 case MCC ('c', 'c'): return MCC ('c', 's');
5843 case MCC ('c', 's'): return MCC ('c', 'c');
5844 case MCC ('n', 'e'): return MCC ('e', 'q');
5845 case MCC ('e', 'q'): return MCC ('n', 'e');
5846 case MCC ('v', 'c'): return MCC ('v', 's');
5847 case MCC ('v', 's'): return MCC ('v', 'c');
5848 case MCC ('p', 'l'): return MCC ('m', 'i');
5849 case MCC ('m', 'i'): return MCC ('p', 'l');
5850 case MCC ('g', 'e'): return MCC ('l', 't');
5851 case MCC ('l', 't'): return MCC ('g', 'e');
5852 case MCC ('g', 't'): return MCC ('l', 'e');
5853 case MCC ('l', 'e'): return MCC ('g', 't');
5854 }
5855 return cc;
5856 }
5857
5858 /* Build an MRI structured control expression. This generates test
5859 and branch instructions. It goes to TRUELAB if the condition is
5860 true, and to FALSELAB if the condition is false. Exactly one of
5861 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5862 is the size qualifier for the expression. EXTENT is the size to
5863 use for the branch. */
5864
5865 static void
5866 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5867 rightstop, truelab, falselab, extent)
5868 int qual;
5869 int cc;
5870 char *leftstart;
5871 char *leftstop;
5872 char *rightstart;
5873 char *rightstop;
5874 const char *truelab;
5875 const char *falselab;
5876 int extent;
5877 {
5878 char *buf;
5879 char *s;
5880
5881 if (leftstart != NULL)
5882 {
5883 struct m68k_op leftop, rightop;
5884 char c;
5885
5886 /* Swap the compare operands, if necessary, to produce a legal
5887 m68k compare instruction. Comparing a register operand with
5888 a non-register operand requires the register to be on the
5889 right (cmp, cmpa). Comparing an immediate value with
5890 anything requires the immediate value to be on the left
5891 (cmpi). */
5892
5893 c = *leftstop;
5894 *leftstop = '\0';
5895 (void) m68k_ip_op (leftstart, &leftop);
5896 *leftstop = c;
5897
5898 c = *rightstop;
5899 *rightstop = '\0';
5900 (void) m68k_ip_op (rightstart, &rightop);
5901 *rightstop = c;
5902
5903 if (rightop.mode == IMMED
5904 || ((leftop.mode == DREG || leftop.mode == AREG)
5905 && (rightop.mode != DREG && rightop.mode != AREG)))
5906 {
5907 char *temp;
5908
5909 cc = swap_mri_condition (cc);
5910 temp = leftstart;
5911 leftstart = rightstart;
5912 rightstart = temp;
5913 temp = leftstop;
5914 leftstop = rightstop;
5915 rightstop = temp;
5916 }
5917 }
5918
5919 if (truelab == NULL)
5920 {
5921 cc = reverse_mri_condition (cc);
5922 truelab = falselab;
5923 }
5924
5925 if (leftstart != NULL)
5926 {
5927 buf = (char *) xmalloc (20
5928 + (leftstop - leftstart)
5929 + (rightstop - rightstart));
5930 s = buf;
5931 *s++ = 'c';
5932 *s++ = 'm';
5933 *s++ = 'p';
5934 if (qual != '\0')
5935 *s++ = qual;
5936 *s++ = ' ';
5937 memcpy (s, leftstart, leftstop - leftstart);
5938 s += leftstop - leftstart;
5939 *s++ = ',';
5940 memcpy (s, rightstart, rightstop - rightstart);
5941 s += rightstop - rightstart;
5942 *s = '\0';
5943 mri_assemble (buf);
5944 free (buf);
5945 }
5946
5947 buf = (char *) xmalloc (20 + strlen (truelab));
5948 s = buf;
5949 *s++ = 'b';
5950 *s++ = cc >> 8;
5951 *s++ = cc & 0xff;
5952 if (extent != '\0')
5953 *s++ = extent;
5954 *s++ = ' ';
5955 strcpy (s, truelab);
5956 mri_assemble (buf);
5957 free (buf);
5958 }
5959
5960 /* Parse an MRI structured control expression. This generates test
5961 and branch instructions. STOP is where the expression ends. It
5962 goes to TRUELAB if the condition is true, and to FALSELAB if the
5963 condition is false. Exactly one of TRUELAB and FALSELAB will be
5964 NULL, meaning to fall through. QUAL is the size qualifier for the
5965 expression. EXTENT is the size to use for the branch. */
5966
5967 static void
5968 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5969 char *stop;
5970 int qual;
5971 const char *truelab;
5972 const char *falselab;
5973 int extent;
5974 {
5975 int c;
5976 int cc;
5977 char *leftstart;
5978 char *leftstop;
5979 char *rightstart;
5980 char *rightstop;
5981
5982 c = *stop;
5983 *stop = '\0';
5984
5985 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5986 &rightstart, &rightstop))
5987 {
5988 *stop = c;
5989 return;
5990 }
5991
5992 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5993 {
5994 const char *flab;
5995
5996 if (falselab != NULL)
5997 flab = falselab;
5998 else
5999 flab = mri_control_label ();
6000
6001 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6002 rightstop, (const char *) NULL, flab, extent);
6003
6004 input_line_pointer += 3;
6005 if (*input_line_pointer != '.'
6006 || input_line_pointer[1] == '\0')
6007 qual = '\0';
6008 else
6009 {
6010 qual = input_line_pointer[1];
6011 input_line_pointer += 2;
6012 }
6013
6014 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6015 &rightstart, &rightstop))
6016 {
6017 *stop = c;
6018 return;
6019 }
6020
6021 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6022 rightstop, truelab, falselab, extent);
6023
6024 if (falselab == NULL)
6025 colon (flab);
6026 }
6027 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6028 {
6029 const char *tlab;
6030
6031 if (truelab != NULL)
6032 tlab = truelab;
6033 else
6034 tlab = mri_control_label ();
6035
6036 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6037 rightstop, tlab, (const char *) NULL, extent);
6038
6039 input_line_pointer += 2;
6040 if (*input_line_pointer != '.'
6041 || input_line_pointer[1] == '\0')
6042 qual = '\0';
6043 else
6044 {
6045 qual = input_line_pointer[1];
6046 input_line_pointer += 2;
6047 }
6048
6049 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6050 &rightstart, &rightstop))
6051 {
6052 *stop = c;
6053 return;
6054 }
6055
6056 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6057 rightstop, truelab, falselab, extent);
6058
6059 if (truelab == NULL)
6060 colon (tlab);
6061 }
6062 else
6063 {
6064 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6065 rightstop, truelab, falselab, extent);
6066 }
6067
6068 *stop = c;
6069 if (input_line_pointer != stop)
6070 as_bad (_("syntax error in structured control directive"));
6071 }
6072
6073 /* Handle the MRI IF pseudo-op. This may be a structured control
6074 directive, or it may be a regular assembler conditional, depending
6075 on its operands. */
6076
6077 static void
6078 s_mri_if (qual)
6079 int qual;
6080 {
6081 char *s;
6082 int c;
6083 struct mri_control_info *n;
6084
6085 /* A structured control directive must end with THEN with an
6086 optional qualifier. */
6087 s = input_line_pointer;
6088 while (! is_end_of_line[(unsigned char) *s]
6089 && (! flag_mri || *s != '*'))
6090 ++s;
6091 --s;
6092 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6093 --s;
6094
6095 if (s - input_line_pointer > 1
6096 && s[-1] == '.')
6097 s -= 2;
6098
6099 if (s - input_line_pointer < 3
6100 || strncasecmp (s - 3, "THEN", 4) != 0)
6101 {
6102 if (qual != '\0')
6103 {
6104 as_bad (_("missing then"));
6105 ignore_rest_of_line ();
6106 return;
6107 }
6108
6109 /* It's a conditional. */
6110 s_if (O_ne);
6111 return;
6112 }
6113
6114 /* Since this might be a conditional if, this pseudo-op will be
6115 called even if we are supported to be ignoring input. Double
6116 check now. Clobber *input_line_pointer so that ignore_input
6117 thinks that this is not a special pseudo-op. */
6118 c = *input_line_pointer;
6119 *input_line_pointer = 0;
6120 if (ignore_input ())
6121 {
6122 *input_line_pointer = c;
6123 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6124 ++input_line_pointer;
6125 demand_empty_rest_of_line ();
6126 return;
6127 }
6128 *input_line_pointer = c;
6129
6130 n = push_mri_control (mri_if);
6131
6132 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6133 n->next, s[1] == '.' ? s[2] : '\0');
6134
6135 if (s[1] == '.')
6136 input_line_pointer = s + 3;
6137 else
6138 input_line_pointer = s + 1;
6139
6140 if (flag_mri)
6141 {
6142 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6143 ++input_line_pointer;
6144 }
6145
6146 demand_empty_rest_of_line ();
6147 }
6148
6149 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6150 structured IF, associate the ELSE with the IF. Otherwise, assume
6151 it is a conditional else. */
6152
6153 static void
6154 s_mri_else (qual)
6155 int qual;
6156 {
6157 int c;
6158 char *buf;
6159 char q[2];
6160
6161 if (qual == '\0'
6162 && (mri_control_stack == NULL
6163 || mri_control_stack->type != mri_if
6164 || mri_control_stack->else_seen))
6165 {
6166 s_else (0);
6167 return;
6168 }
6169
6170 c = *input_line_pointer;
6171 *input_line_pointer = 0;
6172 if (ignore_input ())
6173 {
6174 *input_line_pointer = c;
6175 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6176 ++input_line_pointer;
6177 demand_empty_rest_of_line ();
6178 return;
6179 }
6180 *input_line_pointer = c;
6181
6182 if (mri_control_stack == NULL
6183 || mri_control_stack->type != mri_if
6184 || mri_control_stack->else_seen)
6185 {
6186 as_bad (_("else without matching if"));
6187 ignore_rest_of_line ();
6188 return;
6189 }
6190
6191 mri_control_stack->else_seen = 1;
6192
6193 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6194 q[0] = qual;
6195 q[1] = '\0';
6196 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6197 mri_assemble (buf);
6198 free (buf);
6199
6200 colon (mri_control_stack->next);
6201
6202 if (flag_mri)
6203 {
6204 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6205 ++input_line_pointer;
6206 }
6207
6208 demand_empty_rest_of_line ();
6209 }
6210
6211 /* Handle the MRI ENDI pseudo-op. */
6212
6213 static void
6214 s_mri_endi (ignore)
6215 int ignore ATTRIBUTE_UNUSED;
6216 {
6217 if (mri_control_stack == NULL
6218 || mri_control_stack->type != mri_if)
6219 {
6220 as_bad (_("endi without matching if"));
6221 ignore_rest_of_line ();
6222 return;
6223 }
6224
6225 /* ignore_input will not return true for ENDI, so we don't need to
6226 worry about checking it again here. */
6227
6228 if (! mri_control_stack->else_seen)
6229 colon (mri_control_stack->next);
6230 colon (mri_control_stack->bottom);
6231
6232 pop_mri_control ();
6233
6234 if (flag_mri)
6235 {
6236 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6237 ++input_line_pointer;
6238 }
6239
6240 demand_empty_rest_of_line ();
6241 }
6242
6243 /* Handle the MRI BREAK pseudo-op. */
6244
6245 static void
6246 s_mri_break (extent)
6247 int extent;
6248 {
6249 struct mri_control_info *n;
6250 char *buf;
6251 char ex[2];
6252
6253 n = mri_control_stack;
6254 while (n != NULL
6255 && n->type != mri_for
6256 && n->type != mri_repeat
6257 && n->type != mri_while)
6258 n = n->outer;
6259 if (n == NULL)
6260 {
6261 as_bad (_("break outside of structured loop"));
6262 ignore_rest_of_line ();
6263 return;
6264 }
6265
6266 buf = (char *) xmalloc (20 + strlen (n->bottom));
6267 ex[0] = extent;
6268 ex[1] = '\0';
6269 sprintf (buf, "bra%s %s", ex, n->bottom);
6270 mri_assemble (buf);
6271 free (buf);
6272
6273 if (flag_mri)
6274 {
6275 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6276 ++input_line_pointer;
6277 }
6278
6279 demand_empty_rest_of_line ();
6280 }
6281
6282 /* Handle the MRI NEXT pseudo-op. */
6283
6284 static void
6285 s_mri_next (extent)
6286 int extent;
6287 {
6288 struct mri_control_info *n;
6289 char *buf;
6290 char ex[2];
6291
6292 n = mri_control_stack;
6293 while (n != NULL
6294 && n->type != mri_for
6295 && n->type != mri_repeat
6296 && n->type != mri_while)
6297 n = n->outer;
6298 if (n == NULL)
6299 {
6300 as_bad (_("next outside of structured loop"));
6301 ignore_rest_of_line ();
6302 return;
6303 }
6304
6305 buf = (char *) xmalloc (20 + strlen (n->next));
6306 ex[0] = extent;
6307 ex[1] = '\0';
6308 sprintf (buf, "bra%s %s", ex, n->next);
6309 mri_assemble (buf);
6310 free (buf);
6311
6312 if (flag_mri)
6313 {
6314 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6315 ++input_line_pointer;
6316 }
6317
6318 demand_empty_rest_of_line ();
6319 }
6320
6321 /* Handle the MRI FOR pseudo-op. */
6322
6323 static void
6324 s_mri_for (qual)
6325 int qual;
6326 {
6327 const char *varstart, *varstop;
6328 const char *initstart, *initstop;
6329 const char *endstart, *endstop;
6330 const char *bystart, *bystop;
6331 int up;
6332 int by;
6333 int extent;
6334 struct mri_control_info *n;
6335 char *buf;
6336 char *s;
6337 char ex[2];
6338
6339 /* The syntax is
6340 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6341 */
6342
6343 SKIP_WHITESPACE ();
6344 varstart = input_line_pointer;
6345
6346 /* Look for the '='. */
6347 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6348 && *input_line_pointer != '=')
6349 ++input_line_pointer;
6350 if (*input_line_pointer != '=')
6351 {
6352 as_bad (_("missing ="));
6353 ignore_rest_of_line ();
6354 return;
6355 }
6356
6357 varstop = input_line_pointer;
6358 if (varstop > varstart
6359 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6360 --varstop;
6361
6362 ++input_line_pointer;
6363
6364 initstart = input_line_pointer;
6365
6366 /* Look for TO or DOWNTO. */
6367 up = 1;
6368 initstop = NULL;
6369 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6370 {
6371 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6372 && ! is_part_of_name (input_line_pointer[2]))
6373 {
6374 initstop = input_line_pointer;
6375 input_line_pointer += 2;
6376 break;
6377 }
6378 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6379 && ! is_part_of_name (input_line_pointer[6]))
6380 {
6381 initstop = input_line_pointer;
6382 up = 0;
6383 input_line_pointer += 6;
6384 break;
6385 }
6386 ++input_line_pointer;
6387 }
6388 if (initstop == NULL)
6389 {
6390 as_bad (_("missing to or downto"));
6391 ignore_rest_of_line ();
6392 return;
6393 }
6394 if (initstop > initstart
6395 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6396 --initstop;
6397
6398 SKIP_WHITESPACE ();
6399 endstart = input_line_pointer;
6400
6401 /* Look for BY or DO. */
6402 by = 0;
6403 endstop = NULL;
6404 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6405 {
6406 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6407 && ! is_part_of_name (input_line_pointer[2]))
6408 {
6409 endstop = input_line_pointer;
6410 by = 1;
6411 input_line_pointer += 2;
6412 break;
6413 }
6414 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6415 && (input_line_pointer[2] == '.'
6416 || ! is_part_of_name (input_line_pointer[2])))
6417 {
6418 endstop = input_line_pointer;
6419 input_line_pointer += 2;
6420 break;
6421 }
6422 ++input_line_pointer;
6423 }
6424 if (endstop == NULL)
6425 {
6426 as_bad (_("missing do"));
6427 ignore_rest_of_line ();
6428 return;
6429 }
6430 if (endstop > endstart
6431 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6432 --endstop;
6433
6434 if (! by)
6435 {
6436 bystart = "#1";
6437 bystop = bystart + 2;
6438 }
6439 else
6440 {
6441 SKIP_WHITESPACE ();
6442 bystart = input_line_pointer;
6443
6444 /* Look for DO. */
6445 bystop = NULL;
6446 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6447 {
6448 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6449 && (input_line_pointer[2] == '.'
6450 || ! is_part_of_name (input_line_pointer[2])))
6451 {
6452 bystop = input_line_pointer;
6453 input_line_pointer += 2;
6454 break;
6455 }
6456 ++input_line_pointer;
6457 }
6458 if (bystop == NULL)
6459 {
6460 as_bad (_("missing do"));
6461 ignore_rest_of_line ();
6462 return;
6463 }
6464 if (bystop > bystart
6465 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6466 --bystop;
6467 }
6468
6469 if (*input_line_pointer != '.')
6470 extent = '\0';
6471 else
6472 {
6473 extent = input_line_pointer[1];
6474 input_line_pointer += 2;
6475 }
6476
6477 /* We have fully parsed the FOR operands. Now build the loop. */
6478
6479 n = push_mri_control (mri_for);
6480
6481 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6482
6483 /* move init,var */
6484 s = buf;
6485 *s++ = 'm';
6486 *s++ = 'o';
6487 *s++ = 'v';
6488 *s++ = 'e';
6489 if (qual != '\0')
6490 *s++ = qual;
6491 *s++ = ' ';
6492 memcpy (s, initstart, initstop - initstart);
6493 s += initstop - initstart;
6494 *s++ = ',';
6495 memcpy (s, varstart, varstop - varstart);
6496 s += varstop - varstart;
6497 *s = '\0';
6498 mri_assemble (buf);
6499
6500 colon (n->top);
6501
6502 /* cmp end,var */
6503 s = buf;
6504 *s++ = 'c';
6505 *s++ = 'm';
6506 *s++ = 'p';
6507 if (qual != '\0')
6508 *s++ = qual;
6509 *s++ = ' ';
6510 memcpy (s, endstart, endstop - endstart);
6511 s += endstop - endstart;
6512 *s++ = ',';
6513 memcpy (s, varstart, varstop - varstart);
6514 s += varstop - varstart;
6515 *s = '\0';
6516 mri_assemble (buf);
6517
6518 /* bcc bottom */
6519 ex[0] = extent;
6520 ex[1] = '\0';
6521 if (up)
6522 sprintf (buf, "blt%s %s", ex, n->bottom);
6523 else
6524 sprintf (buf, "bgt%s %s", ex, n->bottom);
6525 mri_assemble (buf);
6526
6527 /* Put together the add or sub instruction used by ENDF. */
6528 s = buf;
6529 if (up)
6530 strcpy (s, "add");
6531 else
6532 strcpy (s, "sub");
6533 s += 3;
6534 if (qual != '\0')
6535 *s++ = qual;
6536 *s++ = ' ';
6537 memcpy (s, bystart, bystop - bystart);
6538 s += bystop - bystart;
6539 *s++ = ',';
6540 memcpy (s, varstart, varstop - varstart);
6541 s += varstop - varstart;
6542 *s = '\0';
6543 n->incr = buf;
6544
6545 if (flag_mri)
6546 {
6547 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6548 ++input_line_pointer;
6549 }
6550
6551 demand_empty_rest_of_line ();
6552 }
6553
6554 /* Handle the MRI ENDF pseudo-op. */
6555
6556 static void
6557 s_mri_endf (ignore)
6558 int ignore ATTRIBUTE_UNUSED;
6559 {
6560 if (mri_control_stack == NULL
6561 || mri_control_stack->type != mri_for)
6562 {
6563 as_bad (_("endf without for"));
6564 ignore_rest_of_line ();
6565 return;
6566 }
6567
6568 colon (mri_control_stack->next);
6569
6570 mri_assemble (mri_control_stack->incr);
6571
6572 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6573 mri_assemble (mri_control_stack->incr);
6574
6575 free (mri_control_stack->incr);
6576
6577 colon (mri_control_stack->bottom);
6578
6579 pop_mri_control ();
6580
6581 if (flag_mri)
6582 {
6583 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6584 ++input_line_pointer;
6585 }
6586
6587 demand_empty_rest_of_line ();
6588 }
6589
6590 /* Handle the MRI REPEAT pseudo-op. */
6591
6592 static void
6593 s_mri_repeat (ignore)
6594 int ignore ATTRIBUTE_UNUSED;
6595 {
6596 struct mri_control_info *n;
6597
6598 n = push_mri_control (mri_repeat);
6599 colon (n->top);
6600 if (flag_mri)
6601 {
6602 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6603 ++input_line_pointer;
6604 }
6605 demand_empty_rest_of_line ();
6606 }
6607
6608 /* Handle the MRI UNTIL pseudo-op. */
6609
6610 static void
6611 s_mri_until (qual)
6612 int qual;
6613 {
6614 char *s;
6615
6616 if (mri_control_stack == NULL
6617 || mri_control_stack->type != mri_repeat)
6618 {
6619 as_bad (_("until without repeat"));
6620 ignore_rest_of_line ();
6621 return;
6622 }
6623
6624 colon (mri_control_stack->next);
6625
6626 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6627 ;
6628
6629 parse_mri_control_expression (s, qual, (const char *) NULL,
6630 mri_control_stack->top, '\0');
6631
6632 colon (mri_control_stack->bottom);
6633
6634 input_line_pointer = s;
6635
6636 pop_mri_control ();
6637
6638 if (flag_mri)
6639 {
6640 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6641 ++input_line_pointer;
6642 }
6643
6644 demand_empty_rest_of_line ();
6645 }
6646
6647 /* Handle the MRI WHILE pseudo-op. */
6648
6649 static void
6650 s_mri_while (qual)
6651 int qual;
6652 {
6653 char *s;
6654
6655 struct mri_control_info *n;
6656
6657 s = input_line_pointer;
6658 while (! is_end_of_line[(unsigned char) *s]
6659 && (! flag_mri || *s != '*'))
6660 s++;
6661 --s;
6662 while (*s == ' ' || *s == '\t')
6663 --s;
6664 if (s - input_line_pointer > 1
6665 && s[-1] == '.')
6666 s -= 2;
6667 if (s - input_line_pointer < 2
6668 || strncasecmp (s - 1, "DO", 2) != 0)
6669 {
6670 as_bad (_("missing do"));
6671 ignore_rest_of_line ();
6672 return;
6673 }
6674
6675 n = push_mri_control (mri_while);
6676
6677 colon (n->next);
6678
6679 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6680 s[1] == '.' ? s[2] : '\0');
6681
6682 input_line_pointer = s + 1;
6683 if (*input_line_pointer == '.')
6684 input_line_pointer += 2;
6685
6686 if (flag_mri)
6687 {
6688 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6689 ++input_line_pointer;
6690 }
6691
6692 demand_empty_rest_of_line ();
6693 }
6694
6695 /* Handle the MRI ENDW pseudo-op. */
6696
6697 static void
6698 s_mri_endw (ignore)
6699 int ignore ATTRIBUTE_UNUSED;
6700 {
6701 char *buf;
6702
6703 if (mri_control_stack == NULL
6704 || mri_control_stack->type != mri_while)
6705 {
6706 as_bad (_("endw without while"));
6707 ignore_rest_of_line ();
6708 return;
6709 }
6710
6711 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6712 sprintf (buf, "bra %s", mri_control_stack->next);
6713 mri_assemble (buf);
6714 free (buf);
6715
6716 colon (mri_control_stack->bottom);
6717
6718 pop_mri_control ();
6719
6720 if (flag_mri)
6721 {
6722 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6723 ++input_line_pointer;
6724 }
6725
6726 demand_empty_rest_of_line ();
6727 }
6728 \f
6729 /*
6730 * md_parse_option
6731 * Invocation line includes a switch not recognized by the base assembler.
6732 * See if it's a processor-specific option. These are:
6733 *
6734 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6735 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6736 * Select the architecture. Instructions or features not
6737 * supported by the selected architecture cause fatal
6738 * errors. More than one may be specified. The default is
6739 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6740 * for -m68000, and -m68882 is a synonym for -m68881.
6741 * -[A]m[c]no-68851, -[A]m[c]no-68881
6742 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6743 * so don't use or document it, but that's the way the parsing
6744 * works).
6745 *
6746 * -pic Indicates PIC.
6747 * -k Indicates PIC. (Sun 3 only.)
6748 *
6749 * --bitwise-or
6750 * Permit `|' to be used in expressions.
6751 *
6752 */
6753
6754 #ifdef OBJ_ELF
6755 CONST char *md_shortopts = "lSA:m:kQ:V";
6756 #else
6757 CONST char *md_shortopts = "lSA:m:k";
6758 #endif
6759
6760 struct option md_longopts[] = {
6761 #define OPTION_PIC (OPTION_MD_BASE)
6762 {"pic", no_argument, NULL, OPTION_PIC},
6763 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6764 {"register-prefix-optional", no_argument, NULL,
6765 OPTION_REGISTER_PREFIX_OPTIONAL},
6766 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6767 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6768 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6769 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6770 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6771 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6772 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6773 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6774 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6775 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6776 {NULL, no_argument, NULL, 0}
6777 };
6778 size_t md_longopts_size = sizeof(md_longopts);
6779
6780 int
6781 md_parse_option (c, arg)
6782 int c;
6783 char *arg;
6784 {
6785 switch (c)
6786 {
6787 case 'l': /* -l means keep external to 2 bit offset
6788 rather than 16 bit one */
6789 flag_short_refs = 1;
6790 break;
6791
6792 case 'S': /* -S means that jbsr's always turn into
6793 jsr's. */
6794 flag_long_jumps = 1;
6795 break;
6796
6797 case 'A':
6798 if (*arg == 'm')
6799 arg++;
6800 /* intentional fall-through */
6801 case 'm':
6802
6803 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6804 {
6805 int i;
6806 unsigned long arch;
6807 const char *oarg = arg;
6808
6809 arg += 3;
6810 if (*arg == 'm')
6811 {
6812 arg++;
6813 if (arg[0] == 'c' && arg[1] == '6')
6814 arg++;
6815 }
6816 for (i = 0; i < n_archs; i++)
6817 if (!strcmp (arg, archs[i].name))
6818 break;
6819 if (i == n_archs)
6820 {
6821 unknown:
6822 as_bad (_("unrecognized option `%s'"), oarg);
6823 return 0;
6824 }
6825 arch = archs[i].arch;
6826 if (arch == m68881)
6827 no_68881 = 1;
6828 else if (arch == m68851)
6829 no_68851 = 1;
6830 else
6831 goto unknown;
6832 }
6833 else
6834 {
6835 int i;
6836
6837 if (arg[0] == 'c' && arg[1] == '6')
6838 arg++;
6839
6840 for (i = 0; i < n_archs; i++)
6841 if (!strcmp (arg, archs[i].name))
6842 {
6843 unsigned long arch = archs[i].arch;
6844 if (cpu_of_arch (arch))
6845 /* It's a cpu spec. */
6846 {
6847 current_architecture &= ~m68000up;
6848 current_architecture |= arch;
6849 }
6850 else if (arch == m68881)
6851 {
6852 current_architecture |= m68881;
6853 no_68881 = 0;
6854 }
6855 else if (arch == m68851)
6856 {
6857 current_architecture |= m68851;
6858 no_68851 = 0;
6859 }
6860 else
6861 /* ??? */
6862 abort ();
6863 break;
6864 }
6865 if (i == n_archs)
6866 {
6867 as_bad (_("unrecognized architecture specification `%s'"), arg);
6868 return 0;
6869 }
6870 }
6871 break;
6872
6873 case OPTION_PIC:
6874 case 'k':
6875 flag_want_pic = 1;
6876 break; /* -pic, Position Independent Code */
6877
6878 case OPTION_REGISTER_PREFIX_OPTIONAL:
6879 flag_reg_prefix_optional = 1;
6880 reg_prefix_optional_seen = 1;
6881 break;
6882
6883 /* -V: SVR4 argument to print version ID. */
6884 case 'V':
6885 print_version_id ();
6886 break;
6887
6888 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6889 should be emitted or not. FIXME: Not implemented. */
6890 case 'Q':
6891 break;
6892
6893 case OPTION_BITWISE_OR:
6894 {
6895 char *n, *t;
6896 const char *s;
6897
6898 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6899 t = n;
6900 for (s = m68k_comment_chars; *s != '\0'; s++)
6901 if (*s != '|')
6902 *t++ = *s;
6903 *t = '\0';
6904 m68k_comment_chars = n;
6905 }
6906 break;
6907
6908 case OPTION_BASE_SIZE_DEFAULT_16:
6909 m68k_index_width_default = SIZE_WORD;
6910 break;
6911
6912 case OPTION_BASE_SIZE_DEFAULT_32:
6913 m68k_index_width_default = SIZE_LONG;
6914 break;
6915
6916 case OPTION_DISP_SIZE_DEFAULT_16:
6917 m68k_rel32 = 0;
6918 m68k_rel32_from_cmdline = 1;
6919 break;
6920
6921 case OPTION_DISP_SIZE_DEFAULT_32:
6922 m68k_rel32 = 1;
6923 m68k_rel32_from_cmdline = 1;
6924 break;
6925
6926 default:
6927 return 0;
6928 }
6929
6930 return 1;
6931 }
6932
6933 void
6934 md_show_usage (stream)
6935 FILE *stream;
6936 {
6937 fprintf(stream, _("\
6938 680X0 options:\n\
6939 -l use 1 word for refs to undefined symbols [default 2]\n\
6940 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6941 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6942 | -mcpu32 | -m5200\n\
6943 specify variant of 680X0 architecture [default 68020]\n\
6944 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6945 target has/lacks floating-point coprocessor\n\
6946 [default yes for 68020, 68030, and cpu32]\n"));
6947 fprintf(stream, _("\
6948 -m68851 | -mno-68851\n\
6949 target has/lacks memory-management unit coprocessor\n\
6950 [default yes for 68020 and up]\n\
6951 -pic, -k generate position independent code\n\
6952 -S turn jbsr into jsr\n\
6953 --register-prefix-optional\n\
6954 recognize register names without prefix character\n\
6955 --bitwise-or do not treat `|' as a comment character\n"));
6956 fprintf (stream, _("\
6957 --base-size-default-16 base reg without size is 16 bits\n\
6958 --base-size-default-32 base reg without size is 32 bits (default)\n\
6959 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6960 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6961 }
6962 \f
6963 #ifdef TEST2
6964
6965 /* TEST2: Test md_assemble() */
6966 /* Warning, this routine probably doesn't work anymore */
6967
6968 main ()
6969 {
6970 struct m68k_it the_ins;
6971 char buf[120];
6972 char *cp;
6973 int n;
6974
6975 m68k_ip_begin ();
6976 for (;;)
6977 {
6978 if (!gets (buf) || !*buf)
6979 break;
6980 if (buf[0] == '|' || buf[1] == '.')
6981 continue;
6982 for (cp = buf; *cp; cp++)
6983 if (*cp == '\t')
6984 *cp = ' ';
6985 if (is_label (buf))
6986 continue;
6987 memset (&the_ins, '\0', sizeof (the_ins));
6988 m68k_ip (&the_ins, buf);
6989 if (the_ins.error)
6990 {
6991 printf (_("Error %s in %s\n"), the_ins.error, buf);
6992 }
6993 else
6994 {
6995 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
6996 for (n = 0; n < the_ins.numo; n++)
6997 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6998 printf (" ");
6999 print_the_insn (&the_ins.opcode[0], stdout);
7000 (void) putchar ('\n');
7001 }
7002 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7003 {
7004 if (the_ins.operands[n].error)
7005 {
7006 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7007 continue;
7008 }
7009 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7010 if (the_ins.operands[n].b_const)
7011 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7012 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7013 if (the_ins.operands[n].b_iadd)
7014 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7015 (void) putchar ('\n');
7016 }
7017 }
7018 m68k_ip_end ();
7019 return 0;
7020 }
7021
7022 is_label (str)
7023 char *str;
7024 {
7025 while (*str == ' ')
7026 str++;
7027 while (*str && *str != ' ')
7028 str++;
7029 if (str[-1] == ':' || str[1] == '=')
7030 return 1;
7031 return 0;
7032 }
7033
7034 #endif
7035
7036 /* Possible states for relaxation:
7037
7038 0 0 branch offset byte (bra, etc)
7039 0 1 word
7040 0 2 long
7041
7042 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7043 1 1 word
7044 1 2 long
7045
7046 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7047 2 1 word-long
7048 2 2 long-word
7049 2 3 long-long
7050
7051 */
7052
7053 /* We have no need to default values of symbols. */
7054
7055 /* ARGSUSED */
7056 symbolS *
7057 md_undefined_symbol (name)
7058 char *name ATTRIBUTE_UNUSED;
7059 {
7060 return 0;
7061 }
7062
7063 /* Round up a section size to the appropriate boundary. */
7064 valueT
7065 md_section_align (segment, size)
7066 segT segment ATTRIBUTE_UNUSED;
7067 valueT size;
7068 {
7069 #ifdef OBJ_AOUT
7070 #ifdef BFD_ASSEMBLER
7071 /* For a.out, force the section size to be aligned. If we don't do
7072 this, BFD will align it for us, but it will not write out the
7073 final bytes of the section. This may be a bug in BFD, but it is
7074 easier to fix it here since that is how the other a.out targets
7075 work. */
7076 int align;
7077
7078 align = bfd_get_section_alignment (stdoutput, segment);
7079 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7080 #endif
7081 #endif
7082
7083 return size;
7084 }
7085
7086 /* Exactly what point is a PC-relative offset relative TO?
7087 On the 68k, it is relative to the address of the first extension
7088 word. The difference between the addresses of the offset and the
7089 first extension word is stored in fx_pcrel_adjust. */
7090 long
7091 md_pcrel_from (fixP)
7092 fixS *fixP;
7093 {
7094 int adjust;
7095
7096 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
7097 -1 as 64. */
7098 adjust = fixP->fx_pcrel_adjust;
7099 if (adjust == 64)
7100 adjust = -1;
7101 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7102 }
7103
7104 #ifndef BFD_ASSEMBLER
7105 #ifdef OBJ_COFF
7106
7107 /*ARGSUSED*/
7108 void
7109 tc_coff_symbol_emit_hook (ignore)
7110 symbolS *ignore ATTRIBUTE_UNUSED;
7111 {
7112 }
7113
7114 int
7115 tc_coff_sizemachdep (frag)
7116 fragS *frag;
7117 {
7118 switch (frag->fr_subtype & 0x3)
7119 {
7120 case BYTE:
7121 return 1;
7122 case SHORT:
7123 return 2;
7124 case LONG:
7125 return 4;
7126 default:
7127 abort ();
7128 return 0;
7129 }
7130 }
7131
7132 #endif
7133 #endif
7134 #ifdef OBJ_ELF
7135 void m68k_elf_final_processing()
7136 {
7137 /* Set file-specific flags if this is a cpu32 processor */
7138 if (cpu_of_arch (current_architecture) & cpu32)
7139 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7140 }
7141 #endif
7142 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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