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* config/tc-m68k.c (md_estimate_size_before_relax): Correct check
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
20
21 #include <ctype.h>
22 #include "as.h"
23 #include "obstack.h"
24 #include "subsegs.h"
25
26 #include "opcode/m68k.h"
27 #include "m68k-parse.h"
28
29 /* This array holds the chars that always start a comment. If the
30 pre-processor is disabled, these aren't very useful */
31 #if (defined (OBJ_ELF) && ! defined (TE_PSOS) && ! defined (TE_LINUX)) || defined (TE_DELTA)
32 const char comment_chars[] = "|#";
33 #else
34 const char comment_chars[] = "|";
35 #endif
36
37 /* This array holds the chars that only start a comment at the beginning of
38 a line. If the line seems to have the form '# 123 filename'
39 .line and .file directives will appear in the pre-processed output */
40 /* Note that input_file.c hand checks for '#' at the beginning of the
41 first line of the input file. This is because the compiler outputs
42 #NO_APP at the beginning of its output. */
43 /* Also note that comments like this one will always work. */
44 const char line_comment_chars[] = "#";
45
46 const char line_separator_chars[] = "";
47
48 /* Chars that can be used to separate mant from exp in floating point nums */
49 CONST char EXP_CHARS[] = "eE";
50
51 /* Chars that mean this number is a floating point constant, as
52 in "0f12.456" or "0d1.2345e12". */
53
54 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
55
56 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
57 changed in read.c . Ideally it shouldn't have to know about it at all,
58 but nothing is ideal around here. */
59
60 const int md_reloc_size = 8; /* Size of relocation record */
61
62 /* Are we trying to generate PIC code? If so, absolute references
63 ought to be made into linkage table references or pc-relative
64 references. Not implemented. For ELF there are other means
65 to denote pic relocations. */
66 int flag_want_pic;
67
68 static int flag_short_refs; /* -l option */
69 static int flag_long_jumps; /* -S option */
70
71 #ifdef REGISTER_PREFIX_OPTIONAL
72 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
73 #else
74 int flag_reg_prefix_optional;
75 #endif
76
77 /* Whether --register-prefix-optional was used on the command line. */
78 static int reg_prefix_optional_seen;
79
80 /* The floating point coprocessor to use by default. */
81 static enum m68k_register m68k_float_copnum = COP1;
82
83 /* If this is non-zero, then references to number(%pc) will be taken
84 to refer to number, rather than to %pc + number. */
85 static int m68k_abspcadd;
86
87 /* If this is non-zero, then the quick forms of the move, add, and sub
88 instructions are used when possible. */
89 static int m68k_quick = 1;
90
91 /* If this is non-zero, then if the size is not specified for a base
92 or outer displacement, the assembler assumes that the size should
93 be 32 bits. */
94 static int m68k_rel32 = 1;
95
96 /* Its an arbitrary name: This means I don't approve of it */
97 /* See flames below */
98 static struct obstack robyn;
99
100 #define TAB(x,y) (((x)<<2)+(y))
101 #define TABTYPE(xy) ((xy) >> 2)
102 #define BYTE 0
103 #define SHORT 1
104 #define LONG 2
105 #define SZ_UNDEF 3
106 #undef BRANCH
107 /* Case `g' except when BCC68000 is applicable. */
108 #define ABRANCH 1
109 /* Coprocessor branches. */
110 #define FBRANCH 2
111 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
112 supported on all cpus. Widens to 32-bit absolute. */
113 #define PCREL 3
114 /* For inserting an extra jmp instruction with long offset on 68000,
115 for expanding conditional branches. (Not bsr or bra.) Since the
116 68000 doesn't support 32-bit displacements for conditional
117 branches, we fake it by reversing the condition and branching
118 around a jmp with an absolute long operand. */
119 #define BCC68000 4
120 /* For the DBcc "instructions". If the displacement requires 32 bits,
121 the branch-around-a-jump game is played here too. */
122 #define DBCC 5
123 /* Not currently used? */
124 #define PCLEA 6
125 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
126 in 16 or 8 bits. */
127 #define PCINDEX 7
128
129 struct m68k_incant
130 {
131 const char *m_operands;
132 unsigned long m_opcode;
133 short m_opnum;
134 short m_codenum;
135 int m_arch;
136 struct m68k_incant *m_next;
137 };
138
139 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
140 #define gettwo(x) (((x)->m_opcode)&0xffff)
141
142 static const enum m68k_register m68000_control_regs[] = { 0 };
143 static const enum m68k_register m68010_control_regs[] = {
144 SFC, DFC, USP, VBR,
145 0
146 };
147 static const enum m68k_register m68020_control_regs[] = {
148 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
149 0
150 };
151 static const enum m68k_register m68040_control_regs[] = {
152 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
153 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
154 0
155 };
156 static const enum m68k_register m68060_control_regs[] = {
157 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
158 USP, VBR, URP, SRP, PCR,
159 0
160 };
161 #define cpu32_control_regs m68010_control_regs
162
163 static const enum m68k_register *control_regs;
164
165 /* internal form of a 68020 instruction */
166 struct m68k_it
167 {
168 const char *error;
169 const char *args; /* list of opcode info */
170 int numargs;
171
172 int numo; /* Number of shorts in opcode */
173 short opcode[11];
174
175 struct m68k_op operands[6];
176
177 int nexp; /* number of exprs in use */
178 struct m68k_exp exprs[4];
179
180 int nfrag; /* Number of frags we have to produce */
181 struct
182 {
183 int fragoff; /* Where in the current opcode the frag ends */
184 symbolS *fadd;
185 long foff;
186 int fragty;
187 }
188 fragb[4];
189
190 int nrel; /* Num of reloc strucs in use */
191 struct
192 {
193 int n;
194 expressionS exp;
195 char wid;
196 char pcrel;
197 /* In a pc relative address the difference between the address
198 of the offset and the address that the offset is relative
199 to. This depends on the addressing mode. Basically this
200 is the value to put in the offset field to address the
201 first byte of the offset, without regarding the special
202 significance of some values (in the branch instruction, for
203 example). */
204 int pcrel_fix;
205 #ifdef OBJ_ELF
206 /* Whether this expression needs special pic relocation, and if
207 so, which. */
208 enum pic_relocation pic_reloc;
209 #endif
210 }
211 reloc[5]; /* Five is enough??? */
212 };
213
214 #define cpu_of_arch(x) ((x) & m68000up)
215 #define float_of_arch(x) ((x) & mfloat)
216 #define mmu_of_arch(x) ((x) & mmmu)
217
218 static struct m68k_it the_ins; /* the instruction being assembled */
219
220 #define op(ex) ((ex)->exp.X_op)
221 #define adds(ex) ((ex)->exp.X_add_symbol)
222 #define subs(ex) ((ex)->exp.X_op_symbol)
223 #define offs(ex) ((ex)->exp.X_add_number)
224
225 /* Macros for adding things to the m68k_it struct */
226
227 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
228
229 /* Like addword, but goes BEFORE general operands */
230 static void
231 insop (w, opcode)
232 int w;
233 struct m68k_incant *opcode;
234 {
235 int z;
236 for(z=the_ins.numo;z>opcode->m_codenum;--z)
237 the_ins.opcode[z]=the_ins.opcode[z-1];
238 for(z=0;z<the_ins.nrel;z++)
239 the_ins.reloc[z].n+=2;
240 for (z = 0; z < the_ins.nfrag; z++)
241 the_ins.fragb[z].fragoff++;
242 the_ins.opcode[opcode->m_codenum]=w;
243 the_ins.numo++;
244 }
245
246 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
247 Blecch. */
248 static void
249 add_fix (width, exp, pc_rel, pc_fix)
250 char width;
251 struct m68k_exp *exp;
252 int pc_rel;
253 int pc_fix;
254 {
255 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
256 ? (the_ins.numo*2-1)
257 : (((width)=='b')
258 ? (the_ins.numo*2+1)
259 : (the_ins.numo*2)));
260 the_ins.reloc[the_ins.nrel].exp = exp->exp;
261 the_ins.reloc[the_ins.nrel].wid = width;
262 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
263 #ifdef OBJ_ELF
264 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
265 #endif
266 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
267 }
268
269 /* Cause an extra frag to be generated here, inserting up to 10 bytes
270 (that value is chosen in the frag_var call in md_assemble). TYPE
271 is the subtype of the frag to be generated; its primary type is
272 rs_machine_dependent.
273
274 The TYPE parameter is also used by md_convert_frag_1 and
275 md_estimate_size_before_relax. The appropriate type of fixup will
276 be emitted by md_convert_frag_1.
277
278 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
279 static void
280 add_frag(add,off,type)
281 symbolS *add;
282 long off;
283 int type;
284 {
285 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
286 the_ins.fragb[the_ins.nfrag].fadd=add;
287 the_ins.fragb[the_ins.nfrag].foff=off;
288 the_ins.fragb[the_ins.nfrag++].fragty=type;
289 }
290
291 #define isvar(ex) \
292 (op (ex) != O_constant && op (ex) != O_big)
293
294 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
295 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
296 static int reverse_16_bits PARAMS ((int in));
297 static int reverse_8_bits PARAMS ((int in));
298 static void install_gen_operand PARAMS ((int mode, int val));
299 static void install_operand PARAMS ((int mode, int val));
300 static void s_bss PARAMS ((int));
301 static void s_data1 PARAMS ((int));
302 static void s_data2 PARAMS ((int));
303 static void s_even PARAMS ((int));
304 static void s_proc PARAMS ((int));
305 static void mri_chip PARAMS ((void));
306 static void s_chip PARAMS ((int));
307 static void s_fopt PARAMS ((int));
308 static void s_opt PARAMS ((int));
309 static void s_reg PARAMS ((int));
310 static void s_restore PARAMS ((int));
311 static void s_save PARAMS ((int));
312 static void s_mri_if PARAMS ((int));
313 static void s_mri_else PARAMS ((int));
314 static void s_mri_endi PARAMS ((int));
315 static void s_mri_break PARAMS ((int));
316 static void s_mri_next PARAMS ((int));
317 static void s_mri_for PARAMS ((int));
318 static void s_mri_endf PARAMS ((int));
319 static void s_mri_repeat PARAMS ((int));
320 static void s_mri_until PARAMS ((int));
321 static void s_mri_while PARAMS ((int));
322 static void s_mri_endw PARAMS ((int));
323
324 static int current_architecture;
325
326 struct m68k_cpu {
327 unsigned long arch;
328 const char *name;
329 int alias;
330 };
331
332 static const struct m68k_cpu archs[] = {
333 { m68000, "68000", 0 },
334 { m68010, "68010", 0 },
335 { m68020, "68020", 0 },
336 { m68030, "68030", 0 },
337 { m68040, "68040", 0 },
338 { m68060, "68060", 0 },
339 { cpu32, "cpu32", 0 },
340 { m68881, "68881", 0 },
341 { m68851, "68851", 0 },
342 /* Aliases (effectively, so far as gas is concerned) for the above
343 cpus. */
344 { m68020, "68k", 1 },
345 { m68000, "68302", 1 },
346 { m68000, "68008", 1 },
347 { m68000, "68ec000", 1 },
348 { m68000, "68hc000", 1 },
349 { m68000, "68hc001", 1 },
350 { m68020, "68ec020", 1 },
351 { m68030, "68ec030", 1 },
352 { m68040, "68ec040", 1 },
353 { cpu32, "68330", 1 },
354 { cpu32, "68331", 1 },
355 { cpu32, "68332", 1 },
356 { cpu32, "68333", 1 },
357 { cpu32, "68340", 1 },
358 { cpu32, "68360", 1 },
359 { m68881, "68882", 1 },
360 };
361
362 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
363
364 /* BCC68000 is for patching in an extra jmp instruction for long offsets
365 on the 68000. The 68000 doesn't support long branches with branchs */
366
367 /* This table desribes how you change sizes for the various types of variable
368 size expressions. This version only supports two kinds. */
369
370 /* Note that calls to frag_var need to specify the maximum expansion
371 needed; this is currently 10 bytes for DBCC. */
372
373 /* The fields are:
374 How far Forward this mode will reach:
375 How far Backward this mode will reach:
376 How many bytes this mode will add to the size of the frag
377 Which mode to go to if the offset won't fit in this one
378 */
379 relax_typeS md_relax_table[] =
380 {
381 {1, 1, 0, 0}, /* First entries aren't used */
382 {1, 1, 0, 0}, /* For no good reason except */
383 {1, 1, 0, 0}, /* that the VAX doesn't either */
384 {1, 1, 0, 0},
385
386 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
387 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
388 {0, 0, 4, 0},
389 {1, 1, 0, 0},
390
391 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
392 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
393 {0, 0, 4, 0},
394 {1, 1, 0, 0},
395
396 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
397 {(32767), (-32768), 2, TAB (PCREL, LONG)},
398 {0, 0, 4, 0},
399 {1, 1, 0, 0},
400
401 {(127), (-128), 0, TAB (BCC68000, SHORT)},
402 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
403 {0, 0, 6, 0}, /* jmp long space */
404 {1, 1, 0, 0},
405
406 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
407 {(32767), (-32768), 2, TAB (DBCC, LONG)},
408 {0, 0, 10, 0}, /* bra/jmp long space */
409 {1, 1, 0, 0},
410
411 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
412 {32767, -32768, 2, TAB (PCLEA, LONG)},
413 {0, 0, 6, 0},
414 {1, 1, 0, 0},
415
416 /* For, e.g., jmp pcrel indexed. */
417 {125, -130, 0, TAB (PCINDEX, SHORT)},
418 {32765, -32770, 2, TAB (PCINDEX, LONG)},
419 {0, 0, 4, 0},
420 {1, 1, 0, 0},
421 };
422
423 /* These are the machine dependent pseudo-ops. These are included so
424 the assembler can work on the output from the SUN C compiler, which
425 generates these.
426 */
427
428 /* This table describes all the machine specific pseudo-ops the assembler
429 has to support. The fields are:
430 pseudo-op name without dot
431 function to call to execute this pseudo-op
432 Integer arg to pass to the function
433 */
434 const pseudo_typeS md_pseudo_table[] =
435 {
436 {"data1", s_data1, 0},
437 {"data2", s_data2, 0},
438 {"bss", s_bss, 0},
439 {"even", s_even, 0},
440 {"skip", s_space, 0},
441 {"proc", s_proc, 0},
442 #if defined (TE_SUN3) || defined (OBJ_ELF)
443 {"align", s_align_bytes, 0},
444 #endif
445 #ifdef OBJ_ELF
446 {"swbeg", s_ignore, 0},
447 #endif
448 {"extend", float_cons, 'x'},
449 {"ldouble", float_cons, 'x'},
450
451 /* The following pseudo-ops are supported for MRI compatibility. */
452 {"chip", s_chip, 0},
453 {"comline", s_space, 1},
454 {"fopt", s_fopt, 0},
455 {"mask2", s_ignore, 0},
456 {"opt", s_opt, 0},
457 {"reg", s_reg, 0},
458 {"restore", s_restore, 0},
459 {"save", s_save, 0},
460
461 {"if", s_mri_if, 0},
462 {"if.b", s_mri_if, 'b'},
463 {"if.w", s_mri_if, 'w'},
464 {"if.l", s_mri_if, 'l'},
465 {"else", s_mri_else, 0},
466 {"else.s", s_mri_else, 's'},
467 {"else.l", s_mri_else, 'l'},
468 {"endi", s_mri_endi, 0},
469 {"break", s_mri_break, 0},
470 {"break.s", s_mri_break, 's'},
471 {"break.l", s_mri_break, 'l'},
472 {"next", s_mri_next, 0},
473 {"next.s", s_mri_next, 's'},
474 {"next.l", s_mri_next, 'l'},
475 {"for", s_mri_for, 0},
476 {"for.b", s_mri_for, 'b'},
477 {"for.w", s_mri_for, 'w'},
478 {"for.l", s_mri_for, 'l'},
479 {"endf", s_mri_endf, 0},
480 {"repeat", s_mri_repeat, 0},
481 {"until", s_mri_until, 0},
482 {"until.b", s_mri_until, 'b'},
483 {"until.w", s_mri_until, 'w'},
484 {"until.l", s_mri_until, 'l'},
485 {"while", s_mri_while, 0},
486 {"while.b", s_mri_while, 'b'},
487 {"while.w", s_mri_while, 'w'},
488 {"while.l", s_mri_while, 'l'},
489 {"endw", s_mri_endw, 0},
490
491 {0, 0, 0}
492 };
493
494
495 /* The mote pseudo ops are put into the opcode table, since they
496 don't start with a . they look like opcodes to gas.
497 */
498 extern void obj_coff_section ();
499
500 CONST pseudo_typeS mote_pseudo_table[] =
501 {
502
503 {"dcl", cons, 4},
504 {"dc", cons, 2},
505 {"dcw", cons, 2},
506 {"dcb", cons, 1},
507
508 {"dsl", s_space, 4},
509 {"ds", s_space, 2},
510 {"dsw", s_space, 2},
511 {"dsb", s_space, 1},
512
513 {"xdef", s_globl, 0},
514 #ifdef OBJ_ELF
515 {"align", s_align_bytes, 0},
516 #else
517 {"align", s_align_ptwo, 0},
518 #endif
519 #ifdef M68KCOFF
520 {"sect", obj_coff_section, 0},
521 {"section", obj_coff_section, 0},
522 #endif
523 {0, 0, 0}
524 };
525
526 #define issbyte(x) ((x)>=-128 && (x)<=127)
527 #define isubyte(x) ((x)>=0 && (x)<=255)
528 #define issword(x) ((x)>=-32768 && (x)<=32767)
529 #define isuword(x) ((x)>=0 && (x)<=65535)
530
531 #define isbyte(x) ((x)>= -255 && (x)<=255)
532 #define isword(x) ((x)>=-65536 && (x)<=65535)
533 #define islong(x) (1)
534
535 extern char *input_line_pointer;
536
537 static char mklower_table[256];
538 #define mklower(c) (mklower_table[(unsigned char)(c)])
539 static char notend_table[256];
540 static char alt_notend_table[256];
541 #define notend(s) \
542 (! (notend_table[(unsigned char) *s] \
543 || (*s == ':' \
544 && alt_notend_table[(unsigned char) s[1]])))
545
546 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
547
548 #ifdef NO_PCREL_RELOCS
549
550 int
551 make_pcrel_absolute(fixP, add_number)
552 fixS *fixP;
553 long *add_number;
554 {
555 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
556
557 /* rewrite the PC relative instructions to absolute address ones.
558 * these are rumoured to be faster, and the apollo linker refuses
559 * to deal with the PC relative relocations.
560 */
561 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
562 {
563 opcode[0] = 0x4e;
564 opcode[1] = 0xf9;
565 }
566 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
567 {
568 opcode[0] = 0x4e;
569 opcode[1] = 0xb9;
570 }
571 else
572 as_fatal ("Unknown PC relative instruction");
573 *add_number -= 4;
574 return 0;
575 }
576
577 #endif /* NO_PCREL_RELOCS */
578
579 short
580 tc_coff_fix2rtype (fixP)
581 fixS *fixP;
582 {
583 if (fixP->fx_tcbit && fixP->fx_size == 4)
584 return R_RELLONG_NEG;
585 #ifdef NO_PCREL_RELOCS
586 know (fixP->fx_pcrel == 0);
587 return (fixP->fx_size == 1 ? R_RELBYTE
588 : fixP->fx_size == 2 ? R_DIR16
589 : R_DIR32);
590 #else
591 return (fixP->fx_pcrel ?
592 (fixP->fx_size == 1 ? R_PCRBYTE :
593 fixP->fx_size == 2 ? R_PCRWORD :
594 R_PCRLONG) :
595 (fixP->fx_size == 1 ? R_RELBYTE :
596 fixP->fx_size == 2 ? R_RELWORD :
597 R_RELLONG));
598 #endif
599 }
600
601 #endif
602
603 #ifdef OBJ_ELF
604
605 /* Compute the relocation code for a fixup of SIZE bytes, using pc
606 relative relocation if PCREL is non-zero. PIC says whether a special
607 pic relocation was requested. */
608
609 static bfd_reloc_code_real_type get_reloc_code
610 PARAMS ((int, int, enum pic_relocation));
611
612 static bfd_reloc_code_real_type
613 get_reloc_code (size, pcrel, pic)
614 int size;
615 int pcrel;
616 enum pic_relocation pic;
617 {
618 switch (pic)
619 {
620 case pic_got_pcrel:
621 switch (size)
622 {
623 case 1:
624 return BFD_RELOC_8_GOT_PCREL;
625 case 2:
626 return BFD_RELOC_16_GOT_PCREL;
627 case 4:
628 return BFD_RELOC_32_GOT_PCREL;
629 }
630 break;
631
632 case pic_got_off:
633 switch (size)
634 {
635 case 1:
636 return BFD_RELOC_8_GOTOFF;
637 case 2:
638 return BFD_RELOC_16_GOTOFF;
639 case 4:
640 return BFD_RELOC_32_GOTOFF;
641 }
642 break;
643
644 case pic_plt_pcrel:
645 switch (size)
646 {
647 case 1:
648 return BFD_RELOC_8_PLT_PCREL;
649 case 2:
650 return BFD_RELOC_16_PLT_PCREL;
651 case 4:
652 return BFD_RELOC_32_PLT_PCREL;
653 }
654 break;
655
656 case pic_plt_off:
657 switch (size)
658 {
659 case 1:
660 return BFD_RELOC_8_PLTOFF;
661 case 2:
662 return BFD_RELOC_16_PLTOFF;
663 case 4:
664 return BFD_RELOC_32_PLTOFF;
665 }
666 break;
667
668 case pic_none:
669 if (pcrel)
670 {
671 switch (size)
672 {
673 case 1:
674 return BFD_RELOC_8_PCREL;
675 case 2:
676 return BFD_RELOC_16_PCREL;
677 case 4:
678 return BFD_RELOC_32_PCREL;
679 }
680 }
681 else
682 {
683 switch (size)
684 {
685 case 1:
686 return BFD_RELOC_8;
687 case 2:
688 return BFD_RELOC_16;
689 case 4:
690 return BFD_RELOC_32;
691 }
692 }
693 }
694
695 as_bad ("Can not do %d byte %s%srelocation", size,
696 pcrel ? "pc-relative " : "",
697 pic == pic_none ? "" : "pic ");
698 return BFD_RELOC_NONE;
699 }
700
701 /* Here we decide which fixups can be adjusted to make them relative
702 to the beginning of the section instead of the symbol. Basically
703 we need to make sure that the dynamic relocations are done
704 correctly, so in some cases we force the original symbol to be
705 used. */
706 int
707 tc_m68k_fix_adjustable (fixP)
708 fixS *fixP;
709 {
710 /* Prevent all adjustments to global symbols. */
711 if (S_IS_EXTERNAL (fixP->fx_addsy))
712 return 0;
713
714 /* adjust_reloc_syms doesn't know about the GOT */
715 switch (fixP->fx_r_type)
716 {
717 case BFD_RELOC_8_GOT_PCREL:
718 case BFD_RELOC_16_GOT_PCREL:
719 case BFD_RELOC_32_GOT_PCREL:
720 case BFD_RELOC_8_GOTOFF:
721 case BFD_RELOC_16_GOTOFF:
722 case BFD_RELOC_32_GOTOFF:
723 case BFD_RELOC_8_PLT_PCREL:
724 case BFD_RELOC_16_PLT_PCREL:
725 case BFD_RELOC_32_PLT_PCREL:
726 case BFD_RELOC_8_PLTOFF:
727 case BFD_RELOC_16_PLTOFF:
728 case BFD_RELOC_32_PLTOFF:
729 return 0;
730
731 default:
732 return 1;
733 }
734 }
735
736 #else /* !OBJ_ELF */
737
738 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
739
740 #endif /* OBJ_ELF */
741
742 #ifdef BFD_ASSEMBLER
743
744 arelent *
745 tc_gen_reloc (section, fixp)
746 asection *section;
747 fixS *fixp;
748 {
749 arelent *reloc;
750 bfd_reloc_code_real_type code;
751
752 if (fixp->fx_tcbit)
753 abort ();
754
755 if (fixp->fx_r_type != BFD_RELOC_NONE)
756 code = fixp->fx_r_type;
757 else
758 {
759 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
760 switch (F (fixp->fx_size, fixp->fx_pcrel))
761 {
762 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
763 MAP (1, 0, BFD_RELOC_8);
764 MAP (2, 0, BFD_RELOC_16);
765 MAP (4, 0, BFD_RELOC_32);
766 MAP (1, 1, BFD_RELOC_8_PCREL);
767 MAP (2, 1, BFD_RELOC_16_PCREL);
768 MAP (4, 1, BFD_RELOC_32_PCREL);
769 default:
770 abort ();
771 }
772 }
773 #undef F
774 #undef MAP
775
776 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
777 assert (reloc != 0);
778 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
779 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
780 #ifndef OBJ_ELF
781 if (fixp->fx_pcrel)
782 reloc->addend = fixp->fx_addnumber;
783 else
784 reloc->addend = 0;
785 #else
786 if (!fixp->fx_pcrel)
787 reloc->addend = fixp->fx_addnumber;
788 else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
789 reloc->addend = (section->vma
790 + (fixp->fx_pcrel_adjust == 64
791 ? -1 : fixp->fx_pcrel_adjust)
792 + fixp->fx_addnumber
793 + md_pcrel_from (fixp));
794 else
795 reloc->addend = (fixp->fx_offset
796 + (fixp->fx_pcrel_adjust == 64
797 ? -1 : fixp->fx_pcrel_adjust));
798 #endif
799
800 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
801 assert (reloc->howto != 0);
802
803 return reloc;
804 }
805
806 #endif /* BFD_ASSEMBLER */
807
808 /* Handle of the OPCODE hash table. NULL means any use before
809 m68k_ip_begin() will crash. */
810 static struct hash_control *op_hash;
811 \f
812 /* Assemble an m68k instruction. */
813
814 void
815 m68k_ip (instring)
816 char *instring;
817 {
818 register char *p;
819 register struct m68k_op *opP;
820 register struct m68k_incant *opcode;
821 register const char *s;
822 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
823 char *pdot, *pdotmove;
824 enum m68k_size siz1, siz2;
825 char c;
826 int losing;
827 int opsfound;
828 char *crack_operand ();
829 LITTLENUM_TYPE words[6];
830 LITTLENUM_TYPE *wordp;
831 unsigned long ok_arch = 0;
832
833 if (*instring == ' ')
834 instring++; /* skip leading whitespace */
835
836 /* Scan up to end of operation-code, which MUST end in end-of-string
837 or exactly 1 space. */
838 pdot = 0;
839 for (p = instring; *p != '\0'; p++)
840 {
841 if (*p == ' ')
842 break;
843 if (*p == '.')
844 pdot = p;
845 }
846
847 if (p == instring)
848 {
849 the_ins.error = "No operator";
850 return;
851 }
852
853 /* p now points to the end of the opcode name, probably whitespace.
854 Make sure the name is null terminated by clobbering the
855 whitespace, look it up in the hash table, then fix it back.
856 Remove a dot, first, since the opcode tables have none. */
857 if (pdot != NULL)
858 {
859 for (pdotmove = pdot; pdotmove < p; pdotmove++)
860 *pdotmove = pdotmove[1];
861 p--;
862 }
863
864 c = *p;
865 *p = '\0';
866 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
867 *p = c;
868
869 if (pdot != NULL)
870 {
871 for (pdotmove = p; pdotmove > pdot; pdotmove--)
872 *pdotmove = pdotmove[-1];
873 *pdot = '.';
874 ++p;
875 }
876
877 if (opcode == NULL)
878 {
879 the_ins.error = "Unknown operator";
880 return;
881 }
882
883 /* found a legitimate opcode, start matching operands */
884 while (*p == ' ')
885 ++p;
886
887 if (opcode->m_operands == 0)
888 {
889 char *old = input_line_pointer;
890 *old = '\n';
891 input_line_pointer = p;
892 /* Ahh - it's a motorola style psuedo op */
893 mote_pseudo_table[opcode->m_opnum].poc_handler
894 (mote_pseudo_table[opcode->m_opnum].poc_val);
895 input_line_pointer = old;
896 *old = 0;
897
898 return;
899 }
900
901 if (flag_mri && opcode->m_opnum == 0)
902 {
903 /* In MRI mode, random garbage is allowed after an instruction
904 which accepts no operands. */
905 the_ins.args = opcode->m_operands;
906 the_ins.numargs = opcode->m_opnum;
907 the_ins.numo = opcode->m_codenum;
908 the_ins.opcode[0] = getone (opcode);
909 the_ins.opcode[1] = gettwo (opcode);
910 return;
911 }
912
913 for (opP = &the_ins.operands[0]; *p; opP++)
914 {
915 p = crack_operand (p, opP);
916
917 if (opP->error)
918 {
919 the_ins.error = opP->error;
920 return;
921 }
922 }
923
924 opsfound = opP - &the_ins.operands[0];
925
926 /* This ugly hack is to support the floating pt opcodes in their
927 standard form. Essentially, we fake a first enty of type COP#1 */
928 if (opcode->m_operands[0] == 'I')
929 {
930 int n;
931
932 for (n = opsfound; n > 0; --n)
933 the_ins.operands[n] = the_ins.operands[n - 1];
934
935 memset ((char *) (&the_ins.operands[0]), '\0',
936 sizeof (the_ins.operands[0]));
937 the_ins.operands[0].mode = CONTROL;
938 the_ins.operands[0].reg = m68k_float_copnum;
939 opsfound++;
940 }
941
942 /* We've got the operands. Find an opcode that'll accept them */
943 for (losing = 0;;)
944 {
945 /* If we didn't get the right number of ops, or we have no
946 common model with this pattern then reject this pattern. */
947
948 if (opsfound != opcode->m_opnum
949 || ((opcode->m_arch & current_architecture) == 0))
950 {
951 ++losing;
952 ok_arch |= opcode->m_arch;
953 }
954 else
955 {
956 for (s = opcode->m_operands, opP = &the_ins.operands[0];
957 *s && !losing;
958 s += 2, opP++)
959 {
960 /* Warning: this switch is huge! */
961 /* I've tried to organize the cases into this order:
962 non-alpha first, then alpha by letter. Lower-case
963 goes directly before uppercase counterpart. */
964 /* Code with multiple case ...: gets sorted by the lowest
965 case ... it belongs to. I hope this makes sense. */
966 switch (*s)
967 {
968 case '!':
969 switch (opP->mode)
970 {
971 case IMMED:
972 case DREG:
973 case AREG:
974 case FPREG:
975 case CONTROL:
976 case AINC:
977 case ADEC:
978 case REGLST:
979 losing++;
980 break;
981 default:
982 break;
983 }
984 break;
985
986 case '`':
987 switch (opP->mode)
988 {
989 case IMMED:
990 case DREG:
991 case AREG:
992 case FPREG:
993 case CONTROL:
994 case AINC:
995 case REGLST:
996 case AINDR:
997 losing++;
998 break;
999 default:
1000 break;
1001 }
1002 break;
1003
1004 case '#':
1005 if (opP->mode != IMMED)
1006 losing++;
1007 else if (s[1] == 'b'
1008 && ! isvar (&opP->disp)
1009 && (opP->disp.exp.X_op != O_constant
1010 || ! isbyte (opP->disp.exp.X_add_number)))
1011 losing++;
1012 else if (s[1] == 'w'
1013 && ! isvar (&opP->disp)
1014 && (opP->disp.exp.X_op != O_constant
1015 || ! isword (opP->disp.exp.X_add_number)))
1016 losing++;
1017 else if (s[1] == 'W'
1018 && ! isvar (&opP->disp)
1019 && (opP->disp.exp.X_op != O_constant
1020 || ! issword (opP->disp.exp.X_add_number)))
1021 losing++;
1022 break;
1023
1024 case '^':
1025 case 'T':
1026 if (opP->mode != IMMED)
1027 losing++;
1028 break;
1029
1030 case '$':
1031 if (opP->mode == AREG
1032 || opP->mode == CONTROL
1033 || opP->mode == FPREG
1034 || opP->mode == IMMED
1035 || opP->mode == REGLST
1036 || (opP->mode != ABSL
1037 && (opP->reg == PC
1038 || opP->reg == ZPC)))
1039 losing++;
1040 break;
1041
1042 case '%':
1043 if (opP->mode == CONTROL
1044 || opP->mode == FPREG
1045 || opP->mode == REGLST
1046 || opP->mode == IMMED
1047 || (opP->mode != ABSL
1048 && (opP->reg == PC
1049 || opP->reg == ZPC)))
1050 losing++;
1051 break;
1052
1053 case '&':
1054 switch (opP->mode)
1055 {
1056 case DREG:
1057 case AREG:
1058 case FPREG:
1059 case CONTROL:
1060 case IMMED:
1061 case AINC:
1062 case ADEC:
1063 case REGLST:
1064 losing++;
1065 break;
1066 case ABSL:
1067 break;
1068 default:
1069 if (opP->reg == PC
1070 || opP->reg == ZPC)
1071 losing++;
1072 break;
1073 }
1074 break;
1075
1076 case '*':
1077 if (opP->mode == CONTROL
1078 || opP->mode == FPREG
1079 || opP->mode == REGLST)
1080 losing++;
1081 break;
1082
1083 case '+':
1084 if (opP->mode != AINC)
1085 losing++;
1086 break;
1087
1088 case '-':
1089 if (opP->mode != ADEC)
1090 losing++;
1091 break;
1092
1093 case '/':
1094 switch (opP->mode)
1095 {
1096 case AREG:
1097 case CONTROL:
1098 case FPREG:
1099 case AINC:
1100 case ADEC:
1101 case IMMED:
1102 case REGLST:
1103 losing++;
1104 break;
1105 default:
1106 break;
1107 }
1108 break;
1109
1110 case ';':
1111 switch (opP->mode)
1112 {
1113 case AREG:
1114 case CONTROL:
1115 case FPREG:
1116 case REGLST:
1117 losing++;
1118 break;
1119 default:
1120 break;
1121 }
1122 break;
1123
1124 case '?':
1125 switch (opP->mode)
1126 {
1127 case AREG:
1128 case CONTROL:
1129 case FPREG:
1130 case AINC:
1131 case ADEC:
1132 case IMMED:
1133 case REGLST:
1134 losing++;
1135 break;
1136 case ABSL:
1137 break;
1138 default:
1139 if (opP->reg == PC || opP->reg == ZPC)
1140 losing++;
1141 break;
1142 }
1143 break;
1144
1145 case '@':
1146 switch (opP->mode)
1147 {
1148 case AREG:
1149 case CONTROL:
1150 case FPREG:
1151 case IMMED:
1152 case REGLST:
1153 losing++;
1154 break;
1155 default:
1156 break;
1157 }
1158 break;
1159
1160 case '~': /* For now! (JF FOO is this right?) */
1161 switch (opP->mode)
1162 {
1163 case DREG:
1164 case AREG:
1165 case CONTROL:
1166 case FPREG:
1167 case IMMED:
1168 case REGLST:
1169 losing++;
1170 break;
1171 case ABSL:
1172 break;
1173 default:
1174 if (opP->reg == PC
1175 || opP->reg == ZPC)
1176 losing++;
1177 break;
1178 }
1179 break;
1180
1181 case '3':
1182 if (opP->mode != CONTROL
1183 || (opP->reg != TT0 && opP->reg != TT1))
1184 losing++;
1185 break;
1186
1187 case 'A':
1188 if (opP->mode != AREG)
1189 losing++;
1190 break;
1191
1192 case 'a':
1193 if (opP->mode != AINDR)
1194 ++losing;
1195 break;
1196
1197 case 'B': /* FOO */
1198 if (opP->mode != ABSL
1199 || (flag_long_jumps
1200 && strncmp (instring, "jbsr", 4) == 0))
1201 losing++;
1202 break;
1203
1204 case 'C':
1205 if (opP->mode != CONTROL || opP->reg != CCR)
1206 losing++;
1207 break;
1208
1209 case 'd':
1210 if (opP->mode != DISP
1211 || opP->reg < ADDR0
1212 || opP->reg > ADDR7)
1213 losing++;
1214 break;
1215
1216 case 'D':
1217 if (opP->mode != DREG)
1218 losing++;
1219 break;
1220
1221 case 'F':
1222 if (opP->mode != FPREG)
1223 losing++;
1224 break;
1225
1226 case 'I':
1227 if (opP->mode != CONTROL
1228 || opP->reg < COP0
1229 || opP->reg > COP7)
1230 losing++;
1231 break;
1232
1233 case 'J':
1234 if (opP->mode != CONTROL
1235 || opP->reg < USP
1236 || opP->reg > last_movec_reg)
1237 losing++;
1238 else
1239 {
1240 const enum m68k_register *rp;
1241 for (rp = control_regs; *rp; rp++)
1242 if (*rp == opP->reg)
1243 break;
1244 if (*rp == 0)
1245 losing++;
1246 }
1247 break;
1248
1249 case 'k':
1250 if (opP->mode != IMMED)
1251 losing++;
1252 break;
1253
1254 case 'l':
1255 case 'L':
1256 if (opP->mode == DREG
1257 || opP->mode == AREG
1258 || opP->mode == FPREG)
1259 {
1260 if (s[1] == '8')
1261 losing++;
1262 else
1263 {
1264 switch (opP->mode)
1265 {
1266 case DREG:
1267 opP->mask = 1 << (opP->reg - DATA0);
1268 break;
1269 case AREG:
1270 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1271 break;
1272 case FPREG:
1273 opP->mask = 1 << (opP->reg - FP0 + 16);
1274 break;
1275 default:
1276 abort ();
1277 }
1278 opP->mode = REGLST;
1279 }
1280 }
1281 else if (opP->mode == CONTROL)
1282 {
1283 if (s[1] != '8')
1284 losing++;
1285 else
1286 {
1287 switch (opP->reg)
1288 {
1289 case FPI:
1290 opP->mask = 1 << 24;
1291 break;
1292 case FPS:
1293 opP->mask = 1 << 25;
1294 break;
1295 case FPC:
1296 opP->mask = 1 << 26;
1297 break;
1298 default:
1299 losing++;
1300 break;
1301 }
1302 opP->mode = REGLST;
1303 }
1304 }
1305 else if (opP->mode == ABSL
1306 && opP->disp.size == SIZE_UNSPEC
1307 && opP->disp.exp.X_op == O_constant)
1308 {
1309 /* This is what the MRI REG pseudo-op generates. */
1310 opP->mode = REGLST;
1311 opP->mask = opP->disp.exp.X_add_number;
1312 }
1313 else if (opP->mode != REGLST)
1314 losing++;
1315 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1316 losing++;
1317 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1318 losing++;
1319 break;
1320
1321 case 'M':
1322 if (opP->mode != IMMED)
1323 losing++;
1324 else if (opP->disp.exp.X_op != O_constant
1325 || ! issbyte (opP->disp.exp.X_add_number))
1326 losing++;
1327 else if (! m68k_quick
1328 && instring[3] != 'q'
1329 && instring[4] != 'q')
1330 losing++;
1331 break;
1332
1333 case 'O':
1334 if (opP->mode != DREG && opP->mode != IMMED)
1335 losing++;
1336 break;
1337
1338 case 'Q':
1339 if (opP->mode != IMMED)
1340 losing++;
1341 else if (opP->disp.exp.X_op != O_constant
1342 || opP->disp.exp.X_add_number < 1
1343 || opP->disp.exp.X_add_number > 8)
1344 losing++;
1345 else if (! m68k_quick
1346 && (strncmp (instring, "add", 3) == 0
1347 || strncmp (instring, "sub", 3) == 0)
1348 && instring[3] != 'q')
1349 losing++;
1350 break;
1351
1352 case 'R':
1353 if (opP->mode != DREG && opP->mode != AREG)
1354 losing++;
1355 break;
1356
1357 case 'r':
1358 if (opP->mode != AINDR
1359 && (opP->mode != BASE
1360 || (opP->reg != 0
1361 && opP->reg != ZADDR0)
1362 || opP->disp.exp.X_op != O_absent
1363 || ((opP->index.reg < DATA0
1364 || opP->index.reg > DATA7)
1365 && (opP->index.reg < ADDR0
1366 || opP->index.reg > ADDR7))
1367 || opP->index.size != SIZE_UNSPEC
1368 || opP->index.scale != 1))
1369 losing++;
1370 break;
1371
1372 case 's':
1373 if (opP->mode != CONTROL
1374 || ! (opP->reg == FPI
1375 || opP->reg == FPS
1376 || opP->reg == FPC))
1377 losing++;
1378 break;
1379
1380 case 'S':
1381 if (opP->mode != CONTROL || opP->reg != SR)
1382 losing++;
1383 break;
1384
1385 case 't':
1386 if (opP->mode != IMMED)
1387 losing++;
1388 else if (opP->disp.exp.X_op != O_constant
1389 || opP->disp.exp.X_add_number < 0
1390 || opP->disp.exp.X_add_number > 7)
1391 losing++;
1392 break;
1393
1394 case 'U':
1395 if (opP->mode != CONTROL || opP->reg != USP)
1396 losing++;
1397 break;
1398
1399 /* JF these are out of order. We could put them
1400 in order if we were willing to put up with
1401 bunches of #ifdef m68851s in the code.
1402
1403 Don't forget that you need these operands
1404 to use 68030 MMU instructions. */
1405 #ifndef NO_68851
1406 /* Memory addressing mode used by pflushr */
1407 case '|':
1408 if (opP->mode == CONTROL
1409 || opP->mode == FPREG
1410 || opP->mode == DREG
1411 || opP->mode == AREG
1412 || opP->mode == REGLST)
1413 losing++;
1414 /* We should accept immediate operands, but they
1415 supposedly have to be quad word, and we don't
1416 handle that. I would like to see what a Motorola
1417 assembler does before doing something here. */
1418 if (opP->mode == IMMED)
1419 losing++;
1420 break;
1421
1422 case 'f':
1423 if (opP->mode != CONTROL
1424 || (opP->reg != SFC && opP->reg != DFC))
1425 losing++;
1426 break;
1427
1428 case '0':
1429 if (opP->mode != CONTROL || opP->reg != TC)
1430 losing++;
1431 break;
1432
1433 case '1':
1434 if (opP->mode != CONTROL || opP->reg != AC)
1435 losing++;
1436 break;
1437
1438 case '2':
1439 if (opP->mode != CONTROL
1440 || (opP->reg != CAL
1441 && opP->reg != VAL
1442 && opP->reg != SCC))
1443 losing++;
1444 break;
1445
1446 case 'V':
1447 if (opP->mode != CONTROL
1448 || opP->reg != VAL)
1449 losing++;
1450 break;
1451
1452 case 'W':
1453 if (opP->mode != CONTROL
1454 || (opP->reg != DRP
1455 && opP->reg != SRP
1456 && opP->reg != CRP))
1457 losing++;
1458 break;
1459
1460 case 'X':
1461 if (opP->mode != CONTROL
1462 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1463 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1464 losing++;
1465 break;
1466
1467 case 'Y':
1468 if (opP->mode != CONTROL || opP->reg != PSR)
1469 losing++;
1470 break;
1471
1472 case 'Z':
1473 if (opP->mode != CONTROL || opP->reg != PCSR)
1474 losing++;
1475 break;
1476 #endif
1477 case 'c':
1478 if (opP->mode != CONTROL
1479 || (opP->reg != NC
1480 && opP->reg != IC
1481 && opP->reg != DC
1482 && opP->reg != BC))
1483 {
1484 losing++;
1485 } /* not a cache specifier. */
1486 break;
1487
1488 case '_':
1489 if (opP->mode != ABSL)
1490 ++losing;
1491 break;
1492
1493 default:
1494 abort ();
1495 } /* switch on type of operand */
1496
1497 if (losing)
1498 break;
1499 } /* for each operand */
1500 } /* if immediately wrong */
1501
1502 if (!losing)
1503 {
1504 break;
1505 } /* got it. */
1506
1507 opcode = opcode->m_next;
1508
1509 if (!opcode)
1510 {
1511 if (ok_arch
1512 && !(ok_arch & current_architecture))
1513 {
1514 char buf[200], *cp;
1515 int len;
1516 strcpy (buf,
1517 "invalid instruction for this architecture; needs ");
1518 cp = buf + strlen (buf);
1519 switch (ok_arch)
1520 {
1521 case mfloat:
1522 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1523 break;
1524 case mmmu:
1525 strcpy (cp, "mmu (68030 or 68851)");
1526 break;
1527 case m68020up:
1528 strcpy (cp, "68020 or higher");
1529 break;
1530 case m68000up:
1531 strcpy (cp, "68000 or higher");
1532 break;
1533 case m68010up:
1534 strcpy (cp, "68010 or higher");
1535 break;
1536 default:
1537 {
1538 int got_one = 0, idx;
1539 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1540 idx++)
1541 {
1542 if ((archs[idx].arch & ok_arch)
1543 && ! archs[idx].alias)
1544 {
1545 if (got_one)
1546 {
1547 strcpy (cp, " or ");
1548 cp += strlen (cp);
1549 }
1550 got_one = 1;
1551 strcpy (cp, archs[idx].name);
1552 cp += strlen (cp);
1553 }
1554 }
1555 }
1556 }
1557 len = cp - buf + 1;
1558 cp = malloc (len);
1559 strcpy (cp, buf);
1560 the_ins.error = cp;
1561 }
1562 else
1563 the_ins.error = "operands mismatch";
1564 return;
1565 } /* Fell off the end */
1566
1567 losing = 0;
1568 }
1569
1570 /* now assemble it */
1571
1572 the_ins.args = opcode->m_operands;
1573 the_ins.numargs = opcode->m_opnum;
1574 the_ins.numo = opcode->m_codenum;
1575 the_ins.opcode[0] = getone (opcode);
1576 the_ins.opcode[1] = gettwo (opcode);
1577
1578 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1579 {
1580 /* This switch is a doozy.
1581 Watch the first step; its a big one! */
1582 switch (s[0])
1583 {
1584
1585 case '*':
1586 case '~':
1587 case '%':
1588 case ';':
1589 case '@':
1590 case '!':
1591 case '&':
1592 case '$':
1593 case '?':
1594 case '/':
1595 case '`':
1596 #ifndef NO_68851
1597 case '|':
1598 #endif
1599 switch (opP->mode)
1600 {
1601 case IMMED:
1602 tmpreg = 0x3c; /* 7.4 */
1603 if (strchr ("bwl", s[1]))
1604 nextword = get_num (&opP->disp, 80);
1605 else
1606 nextword = get_num (&opP->disp, 0);
1607 if (isvar (&opP->disp))
1608 add_fix (s[1], &opP->disp, 0, 0);
1609 switch (s[1])
1610 {
1611 case 'b':
1612 if (!isbyte (nextword))
1613 opP->error = "operand out of range";
1614 addword (nextword);
1615 baseo = 0;
1616 break;
1617 case 'w':
1618 if (!isword (nextword))
1619 opP->error = "operand out of range";
1620 addword (nextword);
1621 baseo = 0;
1622 break;
1623 case 'W':
1624 if (!issword (nextword))
1625 opP->error = "operand out of range";
1626 addword (nextword);
1627 baseo = 0;
1628 break;
1629 case 'l':
1630 addword (nextword >> 16);
1631 addword (nextword);
1632 baseo = 0;
1633 break;
1634
1635 case 'f':
1636 baseo = 2;
1637 outro = 8;
1638 break;
1639 case 'F':
1640 baseo = 4;
1641 outro = 11;
1642 break;
1643 case 'x':
1644 baseo = 6;
1645 outro = 15;
1646 break;
1647 case 'p':
1648 baseo = 6;
1649 outro = -1;
1650 break;
1651 default:
1652 abort ();
1653 }
1654 if (!baseo)
1655 break;
1656
1657 /* We gotta put out some float */
1658 if (op (&opP->disp) != O_big)
1659 {
1660 valueT val;
1661 int gencnt;
1662
1663 /* Can other cases happen here? */
1664 if (op (&opP->disp) != O_constant)
1665 abort ();
1666
1667 val = (valueT) offs (&opP->disp);
1668 gencnt = 0;
1669 do
1670 {
1671 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1672 val >>= LITTLENUM_NUMBER_OF_BITS;
1673 ++gencnt;
1674 }
1675 while (val != 0);
1676 offs (&opP->disp) = gencnt;
1677 }
1678 if (offs (&opP->disp) > 0)
1679 {
1680 if (offs (&opP->disp) > baseo)
1681 {
1682 as_warn ("Bignum too big for %c format; truncated",
1683 s[1]);
1684 offs (&opP->disp) = baseo;
1685 }
1686 baseo -= offs (&opP->disp);
1687 while (baseo--)
1688 addword (0);
1689 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1690 offs (&opP->disp)--;
1691 --wordp)
1692 addword (*wordp);
1693 break;
1694 }
1695 gen_to_words (words, baseo, (long) outro);
1696 for (wordp = words; baseo--; wordp++)
1697 addword (*wordp);
1698 break;
1699 case DREG:
1700 tmpreg = opP->reg - DATA; /* 0.dreg */
1701 break;
1702 case AREG:
1703 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1704 break;
1705 case AINDR:
1706 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1707 break;
1708 case ADEC:
1709 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1710 break;
1711 case AINC:
1712 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1713 break;
1714 case DISP:
1715
1716 nextword = get_num (&opP->disp, 80);
1717
1718 if (opP->reg == PC
1719 && ! isvar (&opP->disp)
1720 && m68k_abspcadd)
1721 {
1722 opP->disp.exp.X_op = O_symbol;
1723 #ifndef BFD_ASSEMBLER
1724 opP->disp.exp.X_add_symbol = &abs_symbol;
1725 #else
1726 opP->disp.exp.X_add_symbol =
1727 section_symbol (absolute_section);
1728 #endif
1729 }
1730
1731 /* Force into index mode. Hope this works */
1732
1733 /* We do the first bit for 32-bit displacements, and the
1734 second bit for 16 bit ones. It is possible that we
1735 should make the default be WORD instead of LONG, but
1736 I think that'd break GCC, so we put up with a little
1737 inefficiency for the sake of working output. */
1738
1739 if (!issword (nextword)
1740 || (isvar (&opP->disp)
1741 && ((opP->disp.size == SIZE_UNSPEC
1742 && flag_short_refs == 0
1743 && cpu_of_arch (current_architecture) >= m68020)
1744 || opP->disp.size == SIZE_LONG)))
1745 {
1746 if (opP->reg == PC)
1747 tmpreg = 0x3B; /* 7.3 */
1748 else
1749 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1750 if (isvar (&opP->disp))
1751 {
1752 if (opP->reg == PC)
1753 {
1754 if (opP->disp.size == SIZE_LONG
1755 #ifdef OBJ_ELF
1756 /* If the displacement needs pic
1757 relocation it cannot be relaxed. */
1758 || opP->disp.pic_reloc != pic_none
1759 #endif
1760 )
1761 {
1762 addword (0x0170);
1763 add_fix ('l', &opP->disp, 1, 2);
1764 }
1765 else
1766 {
1767 add_frag (adds (&opP->disp),
1768 offs (&opP->disp),
1769 TAB (PCLEA, SZ_UNDEF));
1770 break;
1771 }
1772 }
1773 else
1774 {
1775 addword (0x0170);
1776 add_fix ('l', &opP->disp, 0, 0);
1777 }
1778 }
1779 else
1780 addword (0x0170);
1781 addword (nextword >> 16);
1782 }
1783 else
1784 {
1785 if (opP->reg == PC)
1786 tmpreg = 0x3A; /* 7.2 */
1787 else
1788 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1789
1790 if (isvar (&opP->disp))
1791 {
1792 if (opP->reg == PC)
1793 {
1794 add_fix ('w', &opP->disp, 1, 0);
1795 }
1796 else
1797 add_fix ('w', &opP->disp, 0, 0);
1798 }
1799 }
1800 addword (nextword);
1801 break;
1802
1803 case POST:
1804 case PRE:
1805 case BASE:
1806 nextword = 0;
1807 baseo = get_num (&opP->disp, 80);
1808 if (opP->mode == POST || opP->mode == PRE)
1809 outro = get_num (&opP->odisp, 80);
1810 /* Figure out the `addressing mode'.
1811 Also turn on the BASE_DISABLE bit, if needed. */
1812 if (opP->reg == PC || opP->reg == ZPC)
1813 {
1814 tmpreg = 0x3b; /* 7.3 */
1815 if (opP->reg == ZPC)
1816 nextword |= 0x80;
1817 }
1818 else if (opP->reg == 0)
1819 {
1820 nextword |= 0x80;
1821 tmpreg = 0x30; /* 6.garbage */
1822 }
1823 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1824 {
1825 nextword |= 0x80;
1826 tmpreg = 0x30 + opP->reg - ZADDR0;
1827 }
1828 else
1829 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1830
1831 siz1 = opP->disp.size;
1832 if (opP->mode == POST || opP->mode == PRE)
1833 siz2 = opP->odisp.size;
1834 else
1835 siz2 = SIZE_UNSPEC;
1836
1837 /* Index register stuff */
1838 if (opP->index.reg != 0
1839 && opP->index.reg >= DATA
1840 && opP->index.reg <= ADDR7)
1841 {
1842 nextword |= (opP->index.reg - DATA) << 12;
1843
1844 if (opP->index.size == SIZE_UNSPEC
1845 || opP->index.size == SIZE_LONG)
1846 nextword |= 0x800;
1847
1848 if (cpu_of_arch (current_architecture) < m68020)
1849 {
1850 if (opP->index.scale != 1)
1851 {
1852 opP->error =
1853 "scale factor invalid on this architecture; needs 68020 or higher";
1854 }
1855 }
1856
1857 switch (opP->index.scale)
1858 {
1859 case 1:
1860 break;
1861 case 2:
1862 nextword |= 0x200;
1863 break;
1864 case 4:
1865 nextword |= 0x400;
1866 break;
1867 case 8:
1868 nextword |= 0x600;
1869 break;
1870 default:
1871 abort ();
1872 }
1873 /* IF its simple,
1874 GET US OUT OF HERE! */
1875
1876 /* Must be INDEX, with an index register. Address
1877 register cannot be ZERO-PC, and either :b was
1878 forced, or we know it will fit. For a 68000 or
1879 68010, force this mode anyways, because the
1880 larger modes aren't supported. */
1881 if (opP->mode == BASE
1882 && ((opP->reg >= ADDR0
1883 && opP->reg <= ADDR7)
1884 || opP->reg == PC))
1885 {
1886 if (siz1 == SIZE_BYTE
1887 || cpu_of_arch (current_architecture) < m68020
1888 || (siz1 == SIZE_UNSPEC
1889 && ! isvar (&opP->disp)
1890 && issbyte (baseo)))
1891 {
1892 nextword += baseo & 0xff;
1893 addword (nextword);
1894 if (isvar (&opP->disp))
1895 {
1896 /* Do a byte relocation. If it doesn't
1897 fit (possible on m68000) let the
1898 fixup processing complain later. */
1899 if (opP->reg == PC)
1900 add_fix ('B', &opP->disp, 1, 1);
1901 else
1902 add_fix ('B', &opP->disp, 0, 0);
1903 }
1904 else if (siz1 != SIZE_BYTE)
1905 {
1906 if (siz1 != SIZE_UNSPEC)
1907 as_warn ("Forcing byte displacement");
1908 if (! issbyte (baseo))
1909 opP->error = "byte displacement out of range";
1910 }
1911
1912 break;
1913 }
1914 else if (siz1 == SIZE_UNSPEC
1915 && opP->reg == PC
1916 && isvar (&opP->disp)
1917 && subs (&opP->disp) == NULL
1918 #ifdef OBJ_ELF
1919 /* If the displacement needs pic
1920 relocation it cannot be relaxed. */
1921 && opP->disp.pic_reloc == pic_none
1922 #endif
1923 )
1924 {
1925 nextword += baseo & 0xff;
1926 addword (nextword);
1927 add_frag (adds (&opP->disp), offs (&opP->disp),
1928 TAB (PCINDEX, SZ_UNDEF));
1929
1930 break;
1931 }
1932 }
1933 }
1934 else
1935 {
1936 nextword |= 0x40; /* No index reg */
1937 if (opP->index.reg >= ZDATA0
1938 && opP->index.reg <= ZDATA7)
1939 nextword |= (opP->index.reg - ZDATA0) << 12;
1940 else if (opP->index.reg >= ZADDR0
1941 || opP->index.reg <= ZADDR7)
1942 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1943 }
1944
1945 /* It isn't simple. */
1946
1947 if (cpu_of_arch (current_architecture) < m68020)
1948 opP->error =
1949 "invalid operand mode for this architecture; needs 68020 or higher";
1950
1951 nextword |= 0x100;
1952 /* If the guy specified a width, we assume that it is
1953 wide enough. Maybe it isn't. If so, we lose. */
1954 switch (siz1)
1955 {
1956 case SIZE_UNSPEC:
1957 if (isvar (&opP->disp)
1958 ? m68k_rel32
1959 : ! issword (baseo))
1960 {
1961 siz1 = SIZE_LONG;
1962 nextword |= 0x30;
1963 }
1964 else if (! isvar (&opP->disp) && baseo == 0)
1965 nextword |= 0x10;
1966 else
1967 {
1968 nextword |= 0x20;
1969 siz1 = SIZE_WORD;
1970 }
1971 break;
1972 case SIZE_BYTE:
1973 as_warn (":b not permitted; defaulting to :w");
1974 /* Fall through. */
1975 case SIZE_WORD:
1976 nextword |= 0x20;
1977 break;
1978 case SIZE_LONG:
1979 nextword |= 0x30;
1980 break;
1981 }
1982
1983 /* Figure out innner displacement stuff */
1984 if (opP->mode == POST || opP->mode == PRE)
1985 {
1986 switch (siz2)
1987 {
1988 case SIZE_UNSPEC:
1989 if (isvar (&opP->odisp)
1990 ? m68k_rel32
1991 : ! issword (outro))
1992 {
1993 siz2 = SIZE_LONG;
1994 nextword |= 0x3;
1995 }
1996 else if (! isvar (&opP->odisp) && outro == 0)
1997 nextword |= 0x1;
1998 else
1999 {
2000 nextword |= 0x2;
2001 siz2 = SIZE_WORD;
2002 }
2003 break;
2004 case 1:
2005 as_warn (":b not permitted; defaulting to :w");
2006 /* Fall through. */
2007 case 2:
2008 nextword |= 0x2;
2009 break;
2010 case 3:
2011 nextword |= 0x3;
2012 break;
2013 }
2014 if (opP->mode == POST
2015 && (nextword & 0x40) == 0)
2016 nextword |= 0x04;
2017 }
2018 addword (nextword);
2019
2020 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2021 {
2022 if (opP->reg == PC || opP->reg == ZPC)
2023 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2024 else
2025 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2026 }
2027 if (siz1 == SIZE_LONG)
2028 addword (baseo >> 16);
2029 if (siz1 != SIZE_UNSPEC)
2030 addword (baseo);
2031
2032 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2033 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2034 if (siz2 == SIZE_LONG)
2035 addword (outro >> 16);
2036 if (siz2 != SIZE_UNSPEC)
2037 addword (outro);
2038
2039 break;
2040
2041 case ABSL:
2042 nextword = get_num (&opP->disp, 80);
2043 switch (opP->disp.size)
2044 {
2045 default:
2046 abort ();
2047 case SIZE_UNSPEC:
2048 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2049 {
2050 tmpreg = 0x38; /* 7.0 */
2051 addword (nextword);
2052 break;
2053 }
2054 /* Don't generate pc relative code on 68010 and
2055 68000. */
2056 if (isvar (&opP->disp)
2057 && !subs (&opP->disp)
2058 && adds (&opP->disp)
2059 #ifdef OBJ_ELF
2060 /* If the displacement needs pic relocation it
2061 cannot be relaxed. */
2062 && opP->disp.pic_reloc == pic_none
2063 #endif
2064 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2065 && cpu_of_arch (current_architecture) >= m68020
2066 && !flag_long_jumps
2067 && !strchr ("~%&$?", s[0]))
2068 {
2069 tmpreg = 0x3A; /* 7.2 */
2070 add_frag (adds (&opP->disp),
2071 offs (&opP->disp),
2072 TAB (PCREL, SZ_UNDEF));
2073 break;
2074 }
2075 /* Fall through into long */
2076 case SIZE_LONG:
2077 if (isvar (&opP->disp))
2078 add_fix ('l', &opP->disp, 0, 0);
2079
2080 tmpreg = 0x39;/* 7.1 mode */
2081 addword (nextword >> 16);
2082 addword (nextword);
2083 break;
2084
2085 case SIZE_WORD: /* Word */
2086 if (isvar (&opP->disp))
2087 add_fix ('w', &opP->disp, 0, 0);
2088
2089 tmpreg = 0x38;/* 7.0 mode */
2090 addword (nextword);
2091 break;
2092 }
2093 break;
2094 case CONTROL:
2095 case FPREG:
2096 default:
2097 as_bad ("unknown/incorrect operand");
2098 /* abort(); */
2099 }
2100 install_gen_operand (s[1], tmpreg);
2101 break;
2102
2103 case '#':
2104 case '^':
2105 switch (s[1])
2106 { /* JF: I hate floating point! */
2107 case 'j':
2108 tmpreg = 70;
2109 break;
2110 case '8':
2111 tmpreg = 20;
2112 break;
2113 case 'C':
2114 tmpreg = 50;
2115 break;
2116 case '3':
2117 default:
2118 tmpreg = 80;
2119 break;
2120 }
2121 tmpreg = get_num (&opP->disp, tmpreg);
2122 if (isvar (&opP->disp))
2123 add_fix (s[1], &opP->disp, 0, 0);
2124 switch (s[1])
2125 {
2126 case 'b': /* Danger: These do no check for
2127 certain types of overflow.
2128 user beware! */
2129 if (!isbyte (tmpreg))
2130 opP->error = "out of range";
2131 insop (tmpreg, opcode);
2132 if (isvar (&opP->disp))
2133 the_ins.reloc[the_ins.nrel - 1].n =
2134 (opcode->m_codenum) * 2 + 1;
2135 break;
2136 case 'w':
2137 if (!isword (tmpreg))
2138 opP->error = "out of range";
2139 insop (tmpreg, opcode);
2140 if (isvar (&opP->disp))
2141 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2142 break;
2143 case 'W':
2144 if (!issword (tmpreg))
2145 opP->error = "out of range";
2146 insop (tmpreg, opcode);
2147 if (isvar (&opP->disp))
2148 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2149 break;
2150 case 'l':
2151 /* Because of the way insop works, we put these two out
2152 backwards. */
2153 insop (tmpreg, opcode);
2154 insop (tmpreg >> 16, opcode);
2155 if (isvar (&opP->disp))
2156 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2157 break;
2158 case '3':
2159 tmpreg &= 0xFF;
2160 case '8':
2161 case 'C':
2162 install_operand (s[1], tmpreg);
2163 break;
2164 default:
2165 abort ();
2166 }
2167 break;
2168
2169 case '+':
2170 case '-':
2171 case 'A':
2172 case 'a':
2173 install_operand (s[1], opP->reg - ADDR);
2174 break;
2175
2176 case 'B':
2177 tmpreg = get_num (&opP->disp, 80);
2178 switch (s[1])
2179 {
2180 case 'B':
2181 /* The pc_fix argument winds up in fx_pcrel_adjust,
2182 which is a char, and may therefore be unsigned. We
2183 want to pass -1, but we pass 64 instead, and convert
2184 back in md_pcrel_from. */
2185 add_fix ('B', &opP->disp, 1, 64);
2186 break;
2187 case 'W':
2188 add_fix ('w', &opP->disp, 1, 0);
2189 addword (0);
2190 break;
2191 case 'L':
2192 long_branch:
2193 if (cpu_of_arch (current_architecture) < m68020)
2194 as_warn ("Can't use long branches on 68000/68010");
2195 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2196 add_fix ('l', &opP->disp, 1, 0);
2197 addword (0);
2198 addword (0);
2199 break;
2200 case 'g':
2201 if (subs (&opP->disp)) /* We can't relax it */
2202 goto long_branch;
2203
2204 #ifdef OBJ_ELF
2205 /* If the displacement needs pic relocation it cannot be
2206 relaxed. */
2207 if (opP->disp.pic_reloc != pic_none)
2208 goto long_branch;
2209 #endif
2210
2211 /* This could either be a symbol, or an absolute
2212 address. No matter, the frag hacking will finger it
2213 out. Not quite: it can't switch from BRANCH to
2214 BCC68000 for the case where opnd is absolute (it
2215 needs to use the 68000 hack since no conditional abs
2216 jumps). */
2217 if (((cpu_of_arch (current_architecture) < m68020)
2218 || (0 == adds (&opP->disp)))
2219 && (the_ins.opcode[0] >= 0x6200)
2220 && (the_ins.opcode[0] <= 0x6f00))
2221 add_frag (adds (&opP->disp), offs (&opP->disp),
2222 TAB (BCC68000, SZ_UNDEF));
2223 else
2224 add_frag (adds (&opP->disp), offs (&opP->disp),
2225 TAB (ABRANCH, SZ_UNDEF));
2226 break;
2227 case 'w':
2228 if (isvar (&opP->disp))
2229 {
2230 #if 1
2231 /* check for DBcc instruction */
2232 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2233 {
2234 /* size varies if patch */
2235 /* needed for long form */
2236 add_frag (adds (&opP->disp), offs (&opP->disp),
2237 TAB (DBCC, SZ_UNDEF));
2238 break;
2239 }
2240 #endif
2241 add_fix ('w', &opP->disp, 1, 0);
2242 }
2243 addword (0);
2244 break;
2245 case 'C': /* Fixed size LONG coproc branches */
2246 add_fix ('l', &opP->disp, 1, 0);
2247 addword (0);
2248 addword (0);
2249 break;
2250 case 'c': /* Var size Coprocesssor branches */
2251 if (subs (&opP->disp))
2252 {
2253 add_fix ('l', &opP->disp, 1, 0);
2254 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2255 }
2256 else if (adds (&opP->disp))
2257 add_frag (adds (&opP->disp), offs (&opP->disp),
2258 TAB (FBRANCH, SZ_UNDEF));
2259 else
2260 {
2261 /* add_frag((symbolS *) 0, offs(&opP->disp),
2262 TAB(FBRANCH,SHORT)); */
2263 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2264 add_fix ('l', &opP->disp, 1, 0);
2265 addword (0);
2266 addword (0);
2267 }
2268 break;
2269 default:
2270 abort ();
2271 }
2272 break;
2273
2274 case 'C': /* Ignore it */
2275 break;
2276
2277 case 'd': /* JF this is a kludge */
2278 install_operand ('s', opP->reg - ADDR);
2279 tmpreg = get_num (&opP->disp, 80);
2280 if (!issword (tmpreg))
2281 {
2282 as_warn ("Expression out of range, using 0");
2283 tmpreg = 0;
2284 }
2285 addword (tmpreg);
2286 break;
2287
2288 case 'D':
2289 install_operand (s[1], opP->reg - DATA);
2290 break;
2291
2292 case 'F':
2293 install_operand (s[1], opP->reg - FP0);
2294 break;
2295
2296 case 'I':
2297 tmpreg = opP->reg - COP0;
2298 install_operand (s[1], tmpreg);
2299 break;
2300
2301 case 'J': /* JF foo */
2302 switch (opP->reg)
2303 {
2304 case SFC:
2305 tmpreg = 0x000;
2306 break;
2307 case DFC:
2308 tmpreg = 0x001;
2309 break;
2310 case CACR:
2311 tmpreg = 0x002;
2312 break;
2313 case TC:
2314 tmpreg = 0x003;
2315 break;
2316 case ITT0:
2317 tmpreg = 0x004;
2318 break;
2319 case ITT1:
2320 tmpreg = 0x005;
2321 break;
2322 case DTT0:
2323 tmpreg = 0x006;
2324 break;
2325 case DTT1:
2326 tmpreg = 0x007;
2327 break;
2328 case BUSCR:
2329 tmpreg = 0x008;
2330 break;
2331
2332 case USP:
2333 tmpreg = 0x800;
2334 break;
2335 case VBR:
2336 tmpreg = 0x801;
2337 break;
2338 case CAAR:
2339 tmpreg = 0x802;
2340 break;
2341 case MSP:
2342 tmpreg = 0x803;
2343 break;
2344 case ISP:
2345 tmpreg = 0x804;
2346 break;
2347 case MMUSR:
2348 tmpreg = 0x805;
2349 break;
2350 case URP:
2351 tmpreg = 0x806;
2352 break;
2353 case SRP:
2354 tmpreg = 0x807;
2355 break;
2356 case PCR:
2357 tmpreg = 0x808;
2358 break;
2359 default:
2360 abort ();
2361 }
2362 install_operand (s[1], tmpreg);
2363 break;
2364
2365 case 'k':
2366 tmpreg = get_num (&opP->disp, 55);
2367 install_operand (s[1], tmpreg & 0x7f);
2368 break;
2369
2370 case 'l':
2371 tmpreg = opP->mask;
2372 if (s[1] == 'w')
2373 {
2374 if (tmpreg & 0x7FF0000)
2375 as_bad ("Floating point register in register list");
2376 insop (reverse_16_bits (tmpreg), opcode);
2377 }
2378 else
2379 {
2380 if (tmpreg & 0x700FFFF)
2381 as_bad ("Wrong register in floating-point reglist");
2382 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2383 }
2384 break;
2385
2386 case 'L':
2387 tmpreg = opP->mask;
2388 if (s[1] == 'w')
2389 {
2390 if (tmpreg & 0x7FF0000)
2391 as_bad ("Floating point register in register list");
2392 insop (tmpreg, opcode);
2393 }
2394 else if (s[1] == '8')
2395 {
2396 if (tmpreg & 0x0FFFFFF)
2397 as_bad ("incorrect register in reglist");
2398 install_operand (s[1], tmpreg >> 24);
2399 }
2400 else
2401 {
2402 if (tmpreg & 0x700FFFF)
2403 as_bad ("wrong register in floating-point reglist");
2404 else
2405 install_operand (s[1], tmpreg >> 16);
2406 }
2407 break;
2408
2409 case 'M':
2410 install_operand (s[1], get_num (&opP->disp, 60));
2411 break;
2412
2413 case 'O':
2414 tmpreg = ((opP->mode == DREG)
2415 ? 0x20 + opP->reg - DATA
2416 : (get_num (&opP->disp, 40) & 0x1F));
2417 install_operand (s[1], tmpreg);
2418 break;
2419
2420 case 'Q':
2421 tmpreg = get_num (&opP->disp, 10);
2422 if (tmpreg == 8)
2423 tmpreg = 0;
2424 install_operand (s[1], tmpreg);
2425 break;
2426
2427 case 'R':
2428 /* This depends on the fact that ADDR registers are eight
2429 more than their corresponding DATA regs, so the result
2430 will have the ADDR_REG bit set */
2431 install_operand (s[1], opP->reg - DATA);
2432 break;
2433
2434 case 'r':
2435 if (opP->mode == AINDR)
2436 install_operand (s[1], opP->reg - DATA);
2437 else
2438 install_operand (s[1], opP->index.reg - DATA);
2439 break;
2440
2441 case 's':
2442 if (opP->reg == FPI)
2443 tmpreg = 0x1;
2444 else if (opP->reg == FPS)
2445 tmpreg = 0x2;
2446 else if (opP->reg == FPC)
2447 tmpreg = 0x4;
2448 else
2449 abort ();
2450 install_operand (s[1], tmpreg);
2451 break;
2452
2453 case 'S': /* Ignore it */
2454 break;
2455
2456 case 'T':
2457 install_operand (s[1], get_num (&opP->disp, 30));
2458 break;
2459
2460 case 'U': /* Ignore it */
2461 break;
2462
2463 case 'c':
2464 switch (opP->reg)
2465 {
2466 case NC:
2467 tmpreg = 0;
2468 break;
2469 case DC:
2470 tmpreg = 1;
2471 break;
2472 case IC:
2473 tmpreg = 2;
2474 break;
2475 case BC:
2476 tmpreg = 3;
2477 break;
2478 default:
2479 as_fatal ("failed sanity check");
2480 } /* switch on cache token */
2481 install_operand (s[1], tmpreg);
2482 break;
2483 #ifndef NO_68851
2484 /* JF: These are out of order, I fear. */
2485 case 'f':
2486 switch (opP->reg)
2487 {
2488 case SFC:
2489 tmpreg = 0;
2490 break;
2491 case DFC:
2492 tmpreg = 1;
2493 break;
2494 default:
2495 abort ();
2496 }
2497 install_operand (s[1], tmpreg);
2498 break;
2499
2500 case '0':
2501 case '1':
2502 case '2':
2503 switch (opP->reg)
2504 {
2505 case TC:
2506 tmpreg = 0;
2507 break;
2508 case CAL:
2509 tmpreg = 4;
2510 break;
2511 case VAL:
2512 tmpreg = 5;
2513 break;
2514 case SCC:
2515 tmpreg = 6;
2516 break;
2517 case AC:
2518 tmpreg = 7;
2519 break;
2520 default:
2521 abort ();
2522 }
2523 install_operand (s[1], tmpreg);
2524 break;
2525
2526 case 'V':
2527 if (opP->reg == VAL)
2528 break;
2529 abort ();
2530
2531 case 'W':
2532 switch (opP->reg)
2533 {
2534 case DRP:
2535 tmpreg = 1;
2536 break;
2537 case SRP:
2538 tmpreg = 2;
2539 break;
2540 case CRP:
2541 tmpreg = 3;
2542 break;
2543 default:
2544 abort ();
2545 }
2546 install_operand (s[1], tmpreg);
2547 break;
2548
2549 case 'X':
2550 switch (opP->reg)
2551 {
2552 case BAD:
2553 case BAD + 1:
2554 case BAD + 2:
2555 case BAD + 3:
2556 case BAD + 4:
2557 case BAD + 5:
2558 case BAD + 6:
2559 case BAD + 7:
2560 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2561 break;
2562
2563 case BAC:
2564 case BAC + 1:
2565 case BAC + 2:
2566 case BAC + 3:
2567 case BAC + 4:
2568 case BAC + 5:
2569 case BAC + 6:
2570 case BAC + 7:
2571 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2572 break;
2573
2574 default:
2575 abort ();
2576 }
2577 install_operand (s[1], tmpreg);
2578 break;
2579 case 'Y':
2580 know (opP->reg == PSR);
2581 break;
2582 case 'Z':
2583 know (opP->reg == PCSR);
2584 break;
2585 #endif /* m68851 */
2586 case '3':
2587 switch (opP->reg)
2588 {
2589 case TT0:
2590 tmpreg = 2;
2591 break;
2592 case TT1:
2593 tmpreg = 3;
2594 break;
2595 default:
2596 abort ();
2597 }
2598 install_operand (s[1], tmpreg);
2599 break;
2600 case 't':
2601 tmpreg = get_num (&opP->disp, 20);
2602 install_operand (s[1], tmpreg);
2603 break;
2604 case '_': /* used only for move16 absolute 32-bit address */
2605 tmpreg = get_num (&opP->disp, 80);
2606 addword (tmpreg >> 16);
2607 addword (tmpreg & 0xFFFF);
2608 break;
2609 default:
2610 abort ();
2611 }
2612 }
2613
2614 /* By the time whe get here (FINALLY) the_ins contains the complete
2615 instruction, ready to be emitted. . . */
2616 }
2617
2618 static int
2619 reverse_16_bits (in)
2620 int in;
2621 {
2622 int out = 0;
2623 int n;
2624
2625 static int mask[16] =
2626 {
2627 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2628 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2629 };
2630 for (n = 0; n < 16; n++)
2631 {
2632 if (in & mask[n])
2633 out |= mask[15 - n];
2634 }
2635 return out;
2636 } /* reverse_16_bits() */
2637
2638 static int
2639 reverse_8_bits (in)
2640 int in;
2641 {
2642 int out = 0;
2643 int n;
2644
2645 static int mask[8] =
2646 {
2647 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2648 };
2649
2650 for (n = 0; n < 8; n++)
2651 {
2652 if (in & mask[n])
2653 out |= mask[7 - n];
2654 }
2655 return out;
2656 } /* reverse_8_bits() */
2657
2658 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2659 (that value is chosen in the frag_var call in md_assemble). TYPE
2660 is the subtype of the frag to be generated; its primary type is
2661 rs_machine_dependent.
2662
2663 The TYPE parameter is also used by md_convert_frag_1 and
2664 md_estimate_size_before_relax. The appropriate type of fixup will
2665 be emitted by md_convert_frag_1.
2666
2667 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2668 static void
2669 install_operand (mode, val)
2670 int mode;
2671 int val;
2672 {
2673 switch (mode)
2674 {
2675 case 's':
2676 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2677 break;
2678 case 'd':
2679 the_ins.opcode[0] |= val << 9;
2680 break;
2681 case '1':
2682 the_ins.opcode[1] |= val << 12;
2683 break;
2684 case '2':
2685 the_ins.opcode[1] |= val << 6;
2686 break;
2687 case '3':
2688 the_ins.opcode[1] |= val;
2689 break;
2690 case '4':
2691 the_ins.opcode[2] |= val << 12;
2692 break;
2693 case '5':
2694 the_ins.opcode[2] |= val << 6;
2695 break;
2696 case '6':
2697 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2698 three words long! */
2699 the_ins.numo++;
2700 the_ins.opcode[2] |= val;
2701 break;
2702 case '7':
2703 the_ins.opcode[1] |= val << 7;
2704 break;
2705 case '8':
2706 the_ins.opcode[1] |= val << 10;
2707 break;
2708 #ifndef NO_68851
2709 case '9':
2710 the_ins.opcode[1] |= val << 5;
2711 break;
2712 #endif
2713
2714 case 't':
2715 the_ins.opcode[1] |= (val << 10) | (val << 7);
2716 break;
2717 case 'D':
2718 the_ins.opcode[1] |= (val << 12) | val;
2719 break;
2720 case 'g':
2721 the_ins.opcode[0] |= val = 0xff;
2722 break;
2723 case 'i':
2724 the_ins.opcode[0] |= val << 9;
2725 break;
2726 case 'C':
2727 the_ins.opcode[1] |= val;
2728 break;
2729 case 'j':
2730 the_ins.opcode[1] |= val;
2731 the_ins.numo++; /* What a hack */
2732 break;
2733 case 'k':
2734 the_ins.opcode[1] |= val << 4;
2735 break;
2736 case 'b':
2737 case 'w':
2738 case 'W':
2739 case 'l':
2740 break;
2741 case 'e':
2742 the_ins.opcode[0] |= (val << 6);
2743 break;
2744 case 'L':
2745 the_ins.opcode[1] = (val >> 16);
2746 the_ins.opcode[2] = val & 0xffff;
2747 break;
2748 case 'c':
2749 default:
2750 as_fatal ("failed sanity check.");
2751 }
2752 } /* install_operand() */
2753
2754 static void
2755 install_gen_operand (mode, val)
2756 int mode;
2757 int val;
2758 {
2759 switch (mode)
2760 {
2761 case 's':
2762 the_ins.opcode[0] |= val;
2763 break;
2764 case 'd':
2765 /* This is a kludge!!! */
2766 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2767 break;
2768 case 'b':
2769 case 'w':
2770 case 'l':
2771 case 'f':
2772 case 'F':
2773 case 'x':
2774 case 'p':
2775 the_ins.opcode[0] |= val;
2776 break;
2777 /* more stuff goes here */
2778 default:
2779 as_fatal ("failed sanity check.");
2780 }
2781 } /* install_gen_operand() */
2782
2783 /*
2784 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2785 * then deal with the bitfield hack.
2786 */
2787
2788 static char *
2789 crack_operand (str, opP)
2790 register char *str;
2791 register struct m68k_op *opP;
2792 {
2793 register int parens;
2794 register int c;
2795 register char *beg_str;
2796 int inquote = 0;
2797
2798 if (!str)
2799 {
2800 return str;
2801 }
2802 beg_str = str;
2803 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
2804 {
2805 if (! inquote)
2806 {
2807 if (*str == '(')
2808 parens++;
2809 else if (*str == ')')
2810 {
2811 if (!parens)
2812 { /* ERROR */
2813 opP->error = "Extra )";
2814 return str;
2815 }
2816 --parens;
2817 }
2818 }
2819 if (flag_mri && *str == '\'')
2820 inquote = ! inquote;
2821 }
2822 if (!*str && parens)
2823 { /* ERROR */
2824 opP->error = "Missing )";
2825 return str;
2826 }
2827 c = *str;
2828 *str = '\0';
2829 if (m68k_ip_op (beg_str, opP) != 0)
2830 {
2831 *str = c;
2832 return str;
2833 }
2834 *str = c;
2835 if (c == '}')
2836 c = *++str; /* JF bitfield hack */
2837 if (c)
2838 {
2839 c = *++str;
2840 if (!c)
2841 as_bad ("Missing operand");
2842 }
2843 return str;
2844 }
2845
2846 /* This is the guts of the machine-dependent assembler. STR points to a
2847 machine dependent instruction. This function is supposed to emit
2848 the frags/bytes it assembles to.
2849 */
2850
2851 void
2852 insert_reg (regname, regnum)
2853 char *regname;
2854 int regnum;
2855 {
2856 char buf[100];
2857 int i;
2858
2859 #ifdef REGISTER_PREFIX
2860 if (!flag_reg_prefix_optional)
2861 {
2862 buf[0] = REGISTER_PREFIX;
2863 strcpy (buf + 1, regname);
2864 regname = buf;
2865 }
2866 #endif
2867
2868 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2869 &zero_address_frag));
2870
2871 for (i = 0; regname[i]; i++)
2872 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2873 buf[i] = '\0';
2874
2875 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2876 &zero_address_frag));
2877 }
2878
2879 struct init_entry
2880 {
2881 const char *name;
2882 int number;
2883 };
2884
2885 static const struct init_entry init_table[] =
2886 {
2887 { "d0", DATA0 },
2888 { "d1", DATA1 },
2889 { "d2", DATA2 },
2890 { "d3", DATA3 },
2891 { "d4", DATA4 },
2892 { "d5", DATA5 },
2893 { "d6", DATA6 },
2894 { "d7", DATA7 },
2895 { "a0", ADDR0 },
2896 { "a1", ADDR1 },
2897 { "a2", ADDR2 },
2898 { "a3", ADDR3 },
2899 { "a4", ADDR4 },
2900 { "a5", ADDR5 },
2901 { "a6", ADDR6 },
2902 { "fp", ADDR6 },
2903 { "a7", ADDR7 },
2904 { "sp", ADDR7 },
2905 { "ssp", ADDR7 },
2906 { "fp0", FP0 },
2907 { "fp1", FP1 },
2908 { "fp2", FP2 },
2909 { "fp3", FP3 },
2910 { "fp4", FP4 },
2911 { "fp5", FP5 },
2912 { "fp6", FP6 },
2913 { "fp7", FP7 },
2914 { "fpi", FPI },
2915 { "fpiar", FPI },
2916 { "fpc", FPI },
2917 { "fps", FPS },
2918 { "fpsr", FPS },
2919 { "fpc", FPC },
2920 { "fpcr", FPC },
2921 { "control", FPC },
2922 { "status", FPS },
2923 { "iaddr", FPI },
2924
2925 { "cop0", COP0 },
2926 { "cop1", COP1 },
2927 { "cop2", COP2 },
2928 { "cop3", COP3 },
2929 { "cop4", COP4 },
2930 { "cop5", COP5 },
2931 { "cop6", COP6 },
2932 { "cop7", COP7 },
2933 { "pc", PC },
2934 { "zpc", ZPC },
2935 { "sr", SR },
2936
2937 { "ccr", CCR },
2938 { "cc", CCR },
2939
2940 { "usp", USP },
2941 { "isp", ISP },
2942 { "sfc", SFC },
2943 { "sfcr", SFC },
2944 { "dfc", DFC },
2945 { "dfcr", DFC },
2946 { "cacr", CACR },
2947 { "caar", CAAR },
2948
2949 { "vbr", VBR },
2950
2951 { "msp", MSP },
2952 { "itt0", ITT0 },
2953 { "itt1", ITT1 },
2954 { "dtt0", DTT0 },
2955 { "dtt1", DTT1 },
2956 { "mmusr", MMUSR },
2957 { "tc", TC },
2958 { "srp", SRP },
2959 { "urp", URP },
2960 { "buscr", BUSCR },
2961 { "pcr", PCR },
2962
2963 { "ac", AC },
2964 { "bc", BC },
2965 { "cal", CAL },
2966 { "crp", CRP },
2967 { "drp", DRP },
2968 { "pcsr", PCSR },
2969 { "psr", PSR },
2970 { "scc", SCC },
2971 { "val", VAL },
2972 { "bad0", BAD0 },
2973 { "bad1", BAD1 },
2974 { "bad2", BAD2 },
2975 { "bad3", BAD3 },
2976 { "bad4", BAD4 },
2977 { "bad5", BAD5 },
2978 { "bad6", BAD6 },
2979 { "bad7", BAD7 },
2980 { "bac0", BAC0 },
2981 { "bac1", BAC1 },
2982 { "bac2", BAC2 },
2983 { "bac3", BAC3 },
2984 { "bac4", BAC4 },
2985 { "bac5", BAC5 },
2986 { "bac6", BAC6 },
2987 { "bac7", BAC7 },
2988
2989 { "ic", IC },
2990 { "dc", DC },
2991 { "nc", NC },
2992
2993 { "tt0", TT0 },
2994 { "tt1", TT1 },
2995 /* 68ec030 versions of same */
2996 { "ac0", TT0 },
2997 { "ac1", TT1 },
2998 /* 68ec030 access control unit, identical to 030 MMU status reg */
2999 { "acusr", PSR },
3000
3001 /* Suppressed data and address registers. */
3002 { "zd0", ZDATA0 },
3003 { "zd1", ZDATA1 },
3004 { "zd2", ZDATA2 },
3005 { "zd3", ZDATA3 },
3006 { "zd4", ZDATA4 },
3007 { "zd5", ZDATA5 },
3008 { "zd6", ZDATA6 },
3009 { "zd7", ZDATA7 },
3010 { "za0", ZADDR0 },
3011 { "za1", ZADDR1 },
3012 { "za2", ZADDR2 },
3013 { "za3", ZADDR3 },
3014 { "za4", ZADDR4 },
3015 { "za5", ZADDR5 },
3016 { "za6", ZADDR6 },
3017 { "za7", ZADDR7 },
3018
3019 { 0, 0 }
3020 };
3021
3022 void
3023 init_regtable ()
3024 {
3025 int i;
3026 for (i = 0; init_table[i].name; i++)
3027 insert_reg (init_table[i].name, init_table[i].number);
3028 }
3029
3030 static int no_68851, no_68881;
3031
3032 #ifdef OBJ_AOUT
3033 /* a.out machine type. Default to 68020. */
3034 int m68k_aout_machtype = 2;
3035 #endif
3036
3037 void
3038 md_assemble (str)
3039 char *str;
3040 {
3041 const char *er;
3042 short *fromP;
3043 char *toP = NULL;
3044 int m, n = 0;
3045 char *to_beg_P;
3046 int shorts_this_frag;
3047 fixS *fixP;
3048
3049 /* In MRI mode, the instruction and operands are separated by a
3050 space. Anything following the operands is a comment. The label
3051 has already been removed. */
3052 if (flag_mri)
3053 {
3054 char *s;
3055 int fields = 0;
3056 int infield = 0;
3057 int inquote = 0;
3058
3059 for (s = str; *s != '\0'; s++)
3060 {
3061 if ((*s == ' ' || *s == '\t') && ! inquote)
3062 {
3063 if (infield)
3064 {
3065 ++fields;
3066 if (fields >= 2)
3067 {
3068 *s = '\0';
3069 break;
3070 }
3071 infield = 0;
3072 }
3073 }
3074 else
3075 {
3076 if (! infield)
3077 infield = 1;
3078 if (*s == '\'')
3079 inquote = ! inquote;
3080 }
3081 }
3082 }
3083
3084 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3085 m68k_ip (str);
3086 er = the_ins.error;
3087 if (!er)
3088 {
3089 for (n = 0; n < the_ins.numargs; n++)
3090 if (the_ins.operands[n].error)
3091 {
3092 er = the_ins.operands[n].error;
3093 break;
3094 }
3095 }
3096 if (er)
3097 {
3098 as_bad ("%s -- statement `%s' ignored", er, str);
3099 return;
3100 }
3101
3102 if (the_ins.nfrag == 0)
3103 {
3104 /* No frag hacking involved; just put it out */
3105 toP = frag_more (2 * the_ins.numo);
3106 fromP = &the_ins.opcode[0];
3107 for (m = the_ins.numo; m; --m)
3108 {
3109 md_number_to_chars (toP, (long) (*fromP), 2);
3110 toP += 2;
3111 fromP++;
3112 }
3113 /* put out symbol-dependent info */
3114 for (m = 0; m < the_ins.nrel; m++)
3115 {
3116 switch (the_ins.reloc[m].wid)
3117 {
3118 case 'B':
3119 n = 1;
3120 break;
3121 case 'b':
3122 n = 1;
3123 break;
3124 case '3':
3125 n = 2;
3126 break;
3127 case 'w':
3128 n = 2;
3129 break;
3130 case 'l':
3131 n = 4;
3132 break;
3133 default:
3134 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3135 the_ins.reloc[m].wid);
3136 }
3137
3138 fixP = fix_new_exp (frag_now,
3139 ((toP - frag_now->fr_literal)
3140 - the_ins.numo * 2 + the_ins.reloc[m].n),
3141 n,
3142 &the_ins.reloc[m].exp,
3143 the_ins.reloc[m].pcrel,
3144 get_reloc_code (n, the_ins.reloc[m].pcrel,
3145 the_ins.reloc[m].pic_reloc));
3146 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3147 }
3148 return;
3149 }
3150
3151 /* There's some frag hacking */
3152 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3153 {
3154 int wid;
3155
3156 if (n == 0)
3157 wid = 2 * the_ins.fragb[n].fragoff;
3158 else
3159 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3160 toP = frag_more (wid);
3161 to_beg_P = toP;
3162 shorts_this_frag = 0;
3163 for (m = wid / 2; m; --m)
3164 {
3165 md_number_to_chars (toP, (long) (*fromP), 2);
3166 toP += 2;
3167 fromP++;
3168 shorts_this_frag++;
3169 }
3170 for (m = 0; m < the_ins.nrel; m++)
3171 {
3172 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3173 {
3174 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3175 break;
3176 }
3177 wid = the_ins.reloc[m].wid;
3178 if (wid == 0)
3179 continue;
3180 the_ins.reloc[m].wid = 0;
3181 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3182
3183 fixP = fix_new_exp (frag_now,
3184 ((toP - frag_now->fr_literal)
3185 - the_ins.numo * 2 + the_ins.reloc[m].n),
3186 wid,
3187 &the_ins.reloc[m].exp,
3188 the_ins.reloc[m].pcrel,
3189 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3190 the_ins.reloc[m].pic_reloc));
3191 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3192 }
3193 (void) frag_var (rs_machine_dependent, 10, 0,
3194 (relax_substateT) (the_ins.fragb[n].fragty),
3195 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3196 }
3197 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3198 shorts_this_frag = 0;
3199 if (n)
3200 {
3201 toP = frag_more (n * sizeof (short));
3202 while (n--)
3203 {
3204 md_number_to_chars (toP, (long) (*fromP), 2);
3205 toP += 2;
3206 fromP++;
3207 shorts_this_frag++;
3208 }
3209 }
3210 for (m = 0; m < the_ins.nrel; m++)
3211 {
3212 int wid;
3213
3214 wid = the_ins.reloc[m].wid;
3215 if (wid == 0)
3216 continue;
3217 the_ins.reloc[m].wid = 0;
3218 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3219
3220 fixP = fix_new_exp (frag_now,
3221 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3222 - shorts_this_frag * 2),
3223 wid,
3224 &the_ins.reloc[m].exp,
3225 the_ins.reloc[m].pcrel,
3226 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3227 the_ins.reloc[m].pic_reloc));
3228 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3229 }
3230 }
3231
3232 void
3233 md_begin ()
3234 {
3235 /*
3236 * md_begin -- set up hash tables with 68000 instructions.
3237 * similar to what the vax assembler does. ---phr
3238 */
3239 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3240 a copy of it at runtime, adding in the information we want but isn't
3241 there. I think it'd be better to have an awk script hack the table
3242 at compile time. Or even just xstr the table and use it as-is. But
3243 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3244 names. */
3245
3246 register const struct m68k_opcode *ins;
3247 register struct m68k_incant *hack, *slak;
3248 register const char *retval = 0; /* empty string, or error msg text */
3249 register unsigned int i;
3250 register char c;
3251
3252 if (flag_mri)
3253 {
3254 flag_reg_prefix_optional = 1;
3255 m68k_abspcadd = 1;
3256 m68k_rel32 = 0;
3257 }
3258
3259 op_hash = hash_new ();
3260
3261 obstack_begin (&robyn, 4000);
3262 for (i = 0; i < m68k_numopcodes; i++)
3263 {
3264 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3265 do
3266 {
3267 ins = &m68k_opcodes[i];
3268 /* We *could* ignore insns that don't match our arch here
3269 but just leaving them out of the hash. */
3270 slak->m_operands = ins->args;
3271 slak->m_opnum = strlen (slak->m_operands) / 2;
3272 slak->m_arch = ins->arch;
3273 slak->m_opcode = ins->opcode;
3274 /* This is kludgey */
3275 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3276 if (i + 1 != m68k_numopcodes
3277 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3278 {
3279 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3280 i++;
3281 }
3282 else
3283 slak->m_next = 0;
3284 slak = slak->m_next;
3285 }
3286 while (slak);
3287
3288 retval = hash_insert (op_hash, ins->name, (char *) hack);
3289 if (retval)
3290 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3291 }
3292
3293 for (i = 0; i < m68k_numaliases; i++)
3294 {
3295 const char *name = m68k_opcode_aliases[i].primary;
3296 const char *alias = m68k_opcode_aliases[i].alias;
3297 PTR val = hash_find (op_hash, name);
3298 if (!val)
3299 as_fatal ("Internal Error: Can't find %s in hash table", name);
3300 retval = hash_insert (op_hash, alias, val);
3301 if (retval)
3302 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3303 }
3304
3305 /* In MRI mode, all unsized branches are variable sized. Normally,
3306 they are word sized. */
3307 if (flag_mri)
3308 {
3309 static struct m68k_opcode_alias mri_aliases[] =
3310 {
3311 { "bhi", "jhi", },
3312 { "bls", "jls", },
3313 { "bcc", "jcc", },
3314 { "bcs", "jcs", },
3315 { "bne", "jne", },
3316 { "beq", "jeq", },
3317 { "bvc", "jvc", },
3318 { "bvs", "jvs", },
3319 { "bpl", "jpl", },
3320 { "bmi", "jmi", },
3321 { "bge", "jge", },
3322 { "blt", "jlt", },
3323 { "bgt", "jgt", },
3324 { "ble", "jle", },
3325 { "bra", "jra", },
3326 { "bsr", "jbsr", },
3327 };
3328
3329 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3330 {
3331 const char *name = mri_aliases[i].primary;
3332 const char *alias = mri_aliases[i].alias;
3333 PTR val = hash_find (op_hash, name);
3334 if (!val)
3335 as_fatal ("Internal Error: Can't find %s in hash table", name);
3336 retval = hash_jam (op_hash, alias, val);
3337 if (retval)
3338 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3339 }
3340 }
3341
3342 for (i = 0; i < sizeof (mklower_table); i++)
3343 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3344
3345 for (i = 0; i < sizeof (notend_table); i++)
3346 {
3347 notend_table[i] = 0;
3348 alt_notend_table[i] = 0;
3349 }
3350 notend_table[','] = 1;
3351 notend_table['{'] = 1;
3352 notend_table['}'] = 1;
3353 alt_notend_table['a'] = 1;
3354 alt_notend_table['A'] = 1;
3355 alt_notend_table['d'] = 1;
3356 alt_notend_table['D'] = 1;
3357 alt_notend_table['#'] = 1;
3358 alt_notend_table['&'] = 1;
3359 alt_notend_table['f'] = 1;
3360 alt_notend_table['F'] = 1;
3361 #ifdef REGISTER_PREFIX
3362 alt_notend_table[REGISTER_PREFIX] = 1;
3363 #endif
3364
3365 /* We need to put '(' in alt_notend_table to handle
3366 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3367 */
3368 alt_notend_table['('] = 1;
3369
3370 /* We need to put '@' in alt_notend_table to handle
3371 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3372 */
3373 alt_notend_table['@'] = 1;
3374
3375 #ifndef MIT_SYNTAX_ONLY
3376 /* Insert pseudo ops, these have to go into the opcode table since
3377 gas expects pseudo ops to start with a dot */
3378 {
3379 int n = 0;
3380 while (mote_pseudo_table[n].poc_name)
3381 {
3382 hack = (struct m68k_incant *)
3383 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3384 hash_insert (op_hash,
3385 mote_pseudo_table[n].poc_name, (char *) hack);
3386 hack->m_operands = 0;
3387 hack->m_opnum = n;
3388 n++;
3389 }
3390 }
3391 #endif
3392
3393 init_regtable ();
3394
3395 #ifdef OBJ_ELF
3396 record_alignment (text_section, 2);
3397 record_alignment (data_section, 2);
3398 record_alignment (bss_section, 2);
3399 #endif
3400 }
3401
3402 void
3403 m68k_init_after_args ()
3404 {
3405 if (cpu_of_arch (current_architecture) == 0)
3406 {
3407 int i;
3408 const char *default_cpu = TARGET_CPU;
3409
3410 if (*default_cpu == 'm')
3411 default_cpu++;
3412 for (i = 0; i < n_archs; i++)
3413 if (strcasecmp (default_cpu, archs[i].name) == 0)
3414 break;
3415 if (i == n_archs)
3416 {
3417 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3418 current_architecture |= m68020;
3419 }
3420 else
3421 current_architecture |= archs[i].arch;
3422 }
3423 /* Permit m68881 specification with all cpus; those that can't work
3424 with a coprocessor could be doing emulation. */
3425 if (current_architecture & m68851)
3426 {
3427 if (current_architecture & m68040)
3428 {
3429 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3430 }
3431 }
3432 /* What other incompatibilities could we check for? */
3433
3434 /* Toss in some default assumptions about coprocessors. */
3435 if (!no_68881
3436 && (cpu_of_arch (current_architecture)
3437 /* Can CPU32 have a 68881 coprocessor?? */
3438 & (m68020 | m68030 | cpu32)))
3439 {
3440 current_architecture |= m68881;
3441 }
3442 if (!no_68851
3443 && (cpu_of_arch (current_architecture) & m68020up) != 0
3444 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3445 {
3446 current_architecture |= m68851;
3447 }
3448 if (no_68881 && (current_architecture & m68881))
3449 as_bad ("options for 68881 and no-68881 both given");
3450 if (no_68851 && (current_architecture & m68851))
3451 as_bad ("options for 68851 and no-68851 both given");
3452
3453 #ifdef OBJ_AOUT
3454 /* Work out the magic number. This isn't very general. */
3455 if (current_architecture & m68000)
3456 m68k_aout_machtype = 0;
3457 else if (current_architecture & m68010)
3458 m68k_aout_machtype = 1;
3459 else if (current_architecture & m68020)
3460 m68k_aout_machtype = 2;
3461 else
3462 m68k_aout_machtype = 2;
3463 #endif
3464
3465 /* Note which set of "movec" control registers is available. */
3466 switch (cpu_of_arch (current_architecture))
3467 {
3468 case m68000:
3469 control_regs = m68000_control_regs;
3470 break;
3471 case m68010:
3472 control_regs = m68010_control_regs;
3473 break;
3474 case m68020:
3475 case m68030:
3476 control_regs = m68020_control_regs;
3477 break;
3478 case m68040:
3479 control_regs = m68040_control_regs;
3480 break;
3481 case m68060:
3482 control_regs = m68060_control_regs;
3483 break;
3484 case cpu32:
3485 control_regs = cpu32_control_regs;
3486 break;
3487 default:
3488 abort ();
3489 }
3490
3491 if (cpu_of_arch (current_architecture) < m68020)
3492 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3493 }
3494
3495 /* This is called if we go in or out of MRI mode because of the .mri
3496 pseudo-op. */
3497
3498 void
3499 m68k_mri_mode_change (on)
3500 int on;
3501 {
3502 if (on)
3503 {
3504 if (! flag_reg_prefix_optional)
3505 {
3506 flag_reg_prefix_optional = 1;
3507 #ifdef REGISTER_PREFIX
3508 init_regtable ();
3509 #endif
3510 }
3511 m68k_abspcadd = 1;
3512 m68k_rel32 = 0;
3513 }
3514 else
3515 {
3516 if (! reg_prefix_optional_seen)
3517 {
3518 #ifdef REGISTER_PREFIX_OPTIONAL
3519 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3520 #else
3521 flag_reg_prefix_optional = 0;
3522 #endif
3523 #ifdef REGISTER_PREFIX
3524 init_regtable ();
3525 #endif
3526 }
3527 m68k_abspcadd = 0;
3528 m68k_rel32 = 1;
3529 }
3530 }
3531
3532 /* Equal to MAX_PRECISION in atof-ieee.c */
3533 #define MAX_LITTLENUMS 6
3534
3535 /* Turn a string in input_line_pointer into a floating point constant
3536 of type type, and store the appropriate bytes in *litP. The number
3537 of LITTLENUMS emitted is stored in *sizeP . An error message is
3538 returned, or NULL on OK. */
3539
3540 char *
3541 md_atof (type, litP, sizeP)
3542 char type;
3543 char *litP;
3544 int *sizeP;
3545 {
3546 int prec;
3547 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3548 LITTLENUM_TYPE *wordP;
3549 char *t;
3550 char *atof_ieee ();
3551
3552 switch (type)
3553 {
3554 case 'f':
3555 case 'F':
3556 case 's':
3557 case 'S':
3558 prec = 2;
3559 break;
3560
3561 case 'd':
3562 case 'D':
3563 case 'r':
3564 case 'R':
3565 prec = 4;
3566 break;
3567
3568 case 'x':
3569 case 'X':
3570 prec = 6;
3571 break;
3572
3573 case 'p':
3574 case 'P':
3575 prec = 6;
3576 break;
3577
3578 default:
3579 *sizeP = 0;
3580 return "Bad call to MD_ATOF()";
3581 }
3582 t = atof_ieee (input_line_pointer, type, words);
3583 if (t)
3584 input_line_pointer = t;
3585
3586 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3587 for (wordP = words; prec--;)
3588 {
3589 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3590 litP += sizeof (LITTLENUM_TYPE);
3591 }
3592 return 0;
3593 }
3594
3595 void
3596 md_number_to_chars (buf, val, n)
3597 char *buf;
3598 valueT val;
3599 int n;
3600 {
3601 number_to_chars_bigendian (buf, val, n);
3602 }
3603
3604 static void
3605 md_apply_fix_2 (fixP, val)
3606 fixS *fixP;
3607 offsetT val;
3608 {
3609 addressT upper_limit;
3610 offsetT lower_limit;
3611
3612 /* This is unnecessary but it convinces the native rs6000 compiler
3613 to generate the code we want. */
3614 char *buf = fixP->fx_frag->fr_literal;
3615 buf += fixP->fx_where;
3616 /* end ibm compiler workaround */
3617
3618 if (val & 0x80000000)
3619 val |= ~(addressT)0x7fffffff;
3620 else
3621 val &= 0x7fffffff;
3622
3623 #ifdef OBJ_ELF
3624 if (fixP->fx_addsy)
3625 {
3626 memset (buf, 0, fixP->fx_size);
3627 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3628 return;
3629 }
3630 #endif
3631
3632 switch (fixP->fx_size)
3633 {
3634 /* The cast to offsetT below are necessary to make code correct for
3635 machines where ints are smaller than offsetT */
3636 case 1:
3637 *buf++ = val;
3638 upper_limit = 0x7f;
3639 lower_limit = - (offsetT) 0x80;
3640 break;
3641 case 2:
3642 *buf++ = (val >> 8);
3643 *buf++ = val;
3644 upper_limit = 0x7fff;
3645 lower_limit = - (offsetT) 0x8000;
3646 break;
3647 case 4:
3648 *buf++ = (val >> 24);
3649 *buf++ = (val >> 16);
3650 *buf++ = (val >> 8);
3651 *buf++ = val;
3652 upper_limit = 0x7fffffff;
3653 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3654 break;
3655 default:
3656 BAD_CASE (fixP->fx_size);
3657 }
3658
3659 /* Fix up a negative reloc. */
3660 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3661 {
3662 fixP->fx_addsy = fixP->fx_subsy;
3663 fixP->fx_subsy = NULL;
3664 fixP->fx_tcbit = 1;
3665 }
3666
3667 /* For non-pc-relative values, it's conceivable we might get something
3668 like "0xff" for a byte field. So extend the upper part of the range
3669 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3670 so that we can do any range checking at all. */
3671 if (!fixP->fx_pcrel)
3672 upper_limit = upper_limit * 2 + 1;
3673
3674 if ((addressT) val > upper_limit
3675 && (val > 0 || val < lower_limit))
3676 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3677
3678 /* A one byte PC-relative reloc means a short branch. We can't use
3679 a short branch with a value of 0 or -1, because those indicate
3680 different opcodes (branches with longer offsets). */
3681 if (fixP->fx_pcrel
3682 && fixP->fx_size == 1
3683 && (fixP->fx_addsy == NULL
3684 || S_IS_DEFINED (fixP->fx_addsy))
3685 && (val == 0 || val == -1))
3686 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3687 }
3688
3689 #ifdef BFD_ASSEMBLER
3690 int
3691 md_apply_fix (fixP, valp)
3692 fixS *fixP;
3693 valueT *valp;
3694 {
3695 md_apply_fix_2 (fixP, (addressT) *valp);
3696 return 1;
3697 }
3698 #else
3699 void md_apply_fix (fixP, val)
3700 fixS *fixP;
3701 long val;
3702 {
3703 md_apply_fix_2 (fixP, (addressT) val);
3704 }
3705 #endif
3706
3707 /* *fragP has been relaxed to its final size, and now needs to have
3708 the bytes inside it modified to conform to the new size There is UGLY
3709 MAGIC here. ..
3710 */
3711 void
3712 md_convert_frag_1 (fragP)
3713 register fragS *fragP;
3714 {
3715 long disp;
3716 long ext = 0;
3717 fixS *fixP;
3718
3719 /* Address in object code of the displacement. */
3720 register int object_address = fragP->fr_fix + fragP->fr_address;
3721
3722 /* Address in gas core of the place to store the displacement. */
3723 /* This convinces the native rs6000 compiler to generate the code we
3724 want. */
3725 register char *buffer_address = fragP->fr_literal;
3726 buffer_address += fragP->fr_fix;
3727 /* end ibm compiler workaround */
3728
3729 /* The displacement of the address, from current location. */
3730 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3731 disp = (disp + fragP->fr_offset) - object_address;
3732
3733 #ifdef BFD_ASSEMBLER
3734 disp += fragP->fr_symbol->sy_frag->fr_address;
3735 #endif
3736
3737 switch (fragP->fr_subtype)
3738 {
3739 case TAB (BCC68000, BYTE):
3740 case TAB (ABRANCH, BYTE):
3741 know (issbyte (disp));
3742 if (disp == 0)
3743 as_bad ("short branch with zero offset: use :w");
3744 fragP->fr_opcode[1] = disp;
3745 ext = 0;
3746 break;
3747 case TAB (DBCC, SHORT):
3748 know (issword (disp));
3749 ext = 2;
3750 break;
3751 case TAB (BCC68000, SHORT):
3752 case TAB (ABRANCH, SHORT):
3753 know (issword (disp));
3754 fragP->fr_opcode[1] = 0x00;
3755 ext = 2;
3756 break;
3757 case TAB (ABRANCH, LONG):
3758 if (cpu_of_arch (current_architecture) < m68020)
3759 {
3760 if (fragP->fr_opcode[0] == 0x61)
3761 /* BSR */
3762 {
3763 fragP->fr_opcode[0] = 0x4E;
3764 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3765
3766 fix_new (fragP,
3767 fragP->fr_fix,
3768 4,
3769 fragP->fr_symbol,
3770 fragP->fr_offset,
3771 0,
3772 NO_RELOC);
3773
3774 fragP->fr_fix += 4;
3775 ext = 0;
3776 }
3777 /* BRA */
3778 else if (fragP->fr_opcode[0] == 0x60)
3779 {
3780 fragP->fr_opcode[0] = 0x4E;
3781 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3782 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3783 fragP->fr_offset, 0, NO_RELOC);
3784 fragP->fr_fix += 4;
3785 ext = 0;
3786 }
3787 else
3788 {
3789 as_bad ("Long branch offset not supported.");
3790 }
3791 }
3792 else
3793 {
3794 fragP->fr_opcode[1] = (char) 0xff;
3795 ext = 4;
3796 }
3797 break;
3798 case TAB (BCC68000, LONG):
3799 /* only Bcc 68000 instructions can come here */
3800 /* change bcc into b!cc/jmp absl long */
3801 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3802 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3803
3804 /* JF: these used to be fr_opcode[2,3], but they may be in a
3805 different frag, in which case refering to them is a no-no.
3806 Only fr_opcode[0,1] are guaranteed to work. */
3807 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3808 *buffer_address++ = (char) 0xf9;
3809 fragP->fr_fix += 2; /* account for jmp instruction */
3810 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3811 fragP->fr_offset, 0, NO_RELOC);
3812 fragP->fr_fix += 4;
3813 ext = 0;
3814 break;
3815 case TAB (DBCC, LONG):
3816 /* only DBcc 68000 instructions can come here */
3817 /* change dbcc into dbcc/jmp absl long */
3818 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3819 *buffer_address++ = 0x00; /* branch offset = 4 */
3820 *buffer_address++ = 0x04;
3821 *buffer_address++ = 0x60; /* put in bra pc+6 */
3822 *buffer_address++ = 0x06;
3823 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3824 *buffer_address++ = (char) 0xf9;
3825
3826 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3827 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3828 fragP->fr_offset, 0, NO_RELOC);
3829 fragP->fr_fix += 4;
3830 ext = 0;
3831 break;
3832 case TAB (FBRANCH, SHORT):
3833 know ((fragP->fr_opcode[1] & 0x40) == 0);
3834 ext = 2;
3835 break;
3836 case TAB (FBRANCH, LONG):
3837 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3838 ext = 4;
3839 break;
3840 case TAB (PCREL, SHORT):
3841 ext = 2;
3842 break;
3843 case TAB (PCREL, LONG):
3844 /* The thing to do here is force it to ABSOLUTE LONG, since
3845 PCREL is really trying to shorten an ABSOLUTE address anyway */
3846 /* JF FOO This code has not been tested */
3847 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3848 0, NO_RELOC);
3849 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3850 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3851 (unsigned) fragP->fr_opcode[0],
3852 (unsigned long) fragP->fr_address);
3853 fragP->fr_opcode[1] &= ~0x3F;
3854 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3855 fragP->fr_fix += 4;
3856 ext = 0;
3857 break;
3858 case TAB (PCLEA, SHORT):
3859 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3860 fragP->fr_offset, 1, NO_RELOC);
3861 fragP->fr_opcode[1] &= ~0x3F;
3862 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3863 ext = 2;
3864 break;
3865 case TAB (PCLEA, LONG):
3866 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3867 fragP->fr_offset, 1, NO_RELOC);
3868 fixP->fx_pcrel_adjust = 2;
3869 /* Already set to mode 7.3; this indicates: PC indirect with
3870 suppressed index, 32-bit displacement. */
3871 *buffer_address++ = 0x01;
3872 *buffer_address++ = 0x70;
3873 fragP->fr_fix += 2;
3874 ext = 4;
3875 break;
3876
3877 case TAB (PCINDEX, BYTE):
3878 disp += 2;
3879 if (!issbyte (disp))
3880 {
3881 as_bad ("displacement doesn't fit in one byte");
3882 disp = 0;
3883 }
3884 assert (fragP->fr_fix >= 2);
3885 buffer_address[-2] &= ~1;
3886 buffer_address[-1] = disp;
3887 ext = 0;
3888 break;
3889 case TAB (PCINDEX, SHORT):
3890 disp += 2;
3891 assert (issword (disp));
3892 assert (fragP->fr_fix >= 2);
3893 buffer_address[-2] |= 0x1;
3894 buffer_address[-1] = 0x20;
3895 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3896 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3897 NO_RELOC);
3898 fixP->fx_pcrel_adjust = 2;
3899 ext = 2;
3900 break;
3901 case TAB (PCINDEX, LONG):
3902 disp += 2;
3903 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3904 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3905 NO_RELOC);
3906 fixP->fx_pcrel_adjust = 2;
3907 assert (fragP->fr_fix >= 2);
3908 buffer_address[-2] |= 0x1;
3909 buffer_address[-1] = 0x30;
3910 ext = 4;
3911 break;
3912 }
3913
3914 if (ext)
3915 {
3916 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3917 fragP->fr_fix += ext;
3918 }
3919 }
3920
3921 #ifndef BFD_ASSEMBLER
3922
3923 void
3924 md_convert_frag (headers, sec, fragP)
3925 object_headers *headers;
3926 segT sec;
3927 fragS *fragP;
3928 {
3929 md_convert_frag_1 (fragP);
3930 }
3931
3932 #else
3933
3934 void
3935 md_convert_frag (abfd, sec, fragP)
3936 bfd *abfd;
3937 segT sec;
3938 fragS *fragP;
3939 {
3940 md_convert_frag_1 (fragP);
3941 }
3942 #endif
3943
3944 /* Force truly undefined symbols to their maximum size, and generally set up
3945 the frag list to be relaxed
3946 */
3947 int
3948 md_estimate_size_before_relax (fragP, segment)
3949 register fragS *fragP;
3950 segT segment;
3951 {
3952 int old_fix;
3953 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3954
3955 old_fix = fragP->fr_fix;
3956
3957 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3958 switch (fragP->fr_subtype)
3959 {
3960
3961 case TAB (ABRANCH, SZ_UNDEF):
3962 {
3963 if ((fragP->fr_symbol != NULL) /* Not absolute */
3964 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3965 {
3966 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3967 break;
3968 }
3969 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3970 {
3971 /* On 68000, or for absolute value, switch to abs long */
3972 /* FIXME, we should check abs val, pick short or long */
3973 if (fragP->fr_opcode[0] == 0x61)
3974 {
3975 fragP->fr_opcode[0] = 0x4E;
3976 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3977 fix_new (fragP, fragP->fr_fix, 4,
3978 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3979 fragP->fr_fix += 4;
3980 frag_wane (fragP);
3981 }
3982 else if (fragP->fr_opcode[0] == 0x60)
3983 {
3984 fragP->fr_opcode[0] = 0x4E;
3985 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3986 fix_new (fragP, fragP->fr_fix, 4,
3987 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3988 fragP->fr_fix += 4;
3989 frag_wane (fragP);
3990 }
3991 else
3992 {
3993 as_warn ("Long branch offset to extern symbol not supported.");
3994 }
3995 }
3996 else
3997 { /* Symbol is still undefined. Make it simple */
3998 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3999 fragP->fr_offset, 1, NO_RELOC);
4000 fragP->fr_fix += 4;
4001 fragP->fr_opcode[1] = (char) 0xff;
4002 frag_wane (fragP);
4003 break;
4004 }
4005
4006 break;
4007 } /* case TAB(ABRANCH,SZ_UNDEF) */
4008
4009 case TAB (FBRANCH, SZ_UNDEF):
4010 {
4011 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4012 {
4013 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4014 fragP->fr_var += 2;
4015 }
4016 else
4017 {
4018 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4019 fragP->fr_offset, 1, NO_RELOC);
4020 fragP->fr_fix += 4;
4021 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4022 frag_wane (fragP);
4023 }
4024 break;
4025 } /* TAB(FBRANCH,SZ_UNDEF) */
4026
4027 case TAB (PCREL, SZ_UNDEF):
4028 {
4029 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4030 || flag_short_refs
4031 || cpu_of_arch (current_architecture) < m68020)
4032 {
4033 fragP->fr_subtype = TAB (PCREL, SHORT);
4034 fragP->fr_var += 2;
4035 }
4036 else
4037 {
4038 fragP->fr_subtype = TAB (PCREL, LONG);
4039 fragP->fr_var += 4;
4040 }
4041 break;
4042 } /* TAB(PCREL,SZ_UNDEF) */
4043
4044 case TAB (BCC68000, SZ_UNDEF):
4045 {
4046 if ((fragP->fr_symbol != NULL)
4047 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4048 {
4049 fragP->fr_subtype = TAB (BCC68000, BYTE);
4050 break;
4051 }
4052 /* only Bcc 68000 instructions can come here */
4053 /* change bcc into b!cc/jmp absl long */
4054 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4055 if (flag_short_refs)
4056 {
4057 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4058 /* JF: these were fr_opcode[2,3] */
4059 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4060 buffer_address[1] = (char) 0xf8;
4061 fragP->fr_fix += 2; /* account for jmp instruction */
4062 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4063 fragP->fr_offset, 0, NO_RELOC);
4064 fragP->fr_fix += 2;
4065 }
4066 else
4067 {
4068 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4069 /* JF: these were fr_opcode[2,3] */
4070 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4071 buffer_address[1] = (char) 0xf9;
4072 fragP->fr_fix += 2; /* account for jmp instruction */
4073 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4074 fragP->fr_offset, 0, NO_RELOC);
4075 fragP->fr_fix += 4;
4076 }
4077 frag_wane (fragP);
4078 break;
4079 } /* case TAB(BCC68000,SZ_UNDEF) */
4080
4081 case TAB (DBCC, SZ_UNDEF):
4082 {
4083 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4084 {
4085 fragP->fr_subtype = TAB (DBCC, SHORT);
4086 fragP->fr_var += 2;
4087 break;
4088 }
4089 /* only DBcc 68000 instructions can come here */
4090 /* change dbcc into dbcc/jmp absl long */
4091 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4092 buffer_address[0] = 0x00; /* branch offset = 4 */
4093 buffer_address[1] = 0x04;
4094 buffer_address[2] = 0x60; /* put in bra pc + ... */
4095
4096 if (flag_short_refs)
4097 {
4098 /* JF: these were fr_opcode[5-7] */
4099 buffer_address[3] = 0x04; /* plus 4 */
4100 buffer_address[4] = 0x4e; /* Put in Jump Word */
4101 buffer_address[5] = (char) 0xf8;
4102 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4103 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4104 fragP->fr_offset, 0, NO_RELOC);
4105 fragP->fr_fix += 2;
4106 }
4107 else
4108 {
4109 /* JF: these were fr_opcode[5-7] */
4110 buffer_address[3] = 0x06; /* Plus 6 */
4111 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4112 buffer_address[5] = (char) 0xf9;
4113 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4114 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4115 fragP->fr_offset, 0, NO_RELOC);
4116 fragP->fr_fix += 4;
4117 }
4118
4119 frag_wane (fragP);
4120 break;
4121 } /* case TAB(DBCC,SZ_UNDEF) */
4122
4123 case TAB (PCLEA, SZ_UNDEF):
4124 {
4125 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4126 || flag_short_refs
4127 || cpu_of_arch (current_architecture) < m68020)
4128 {
4129 fragP->fr_subtype = TAB (PCLEA, SHORT);
4130 fragP->fr_var += 2;
4131 }
4132 else
4133 {
4134 fragP->fr_subtype = TAB (PCLEA, LONG);
4135 fragP->fr_var += 6;
4136 }
4137 break;
4138 } /* TAB(PCLEA,SZ_UNDEF) */
4139
4140 case TAB (PCINDEX, SZ_UNDEF):
4141 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4142 || cpu_of_arch (current_architecture) < m68020)
4143 {
4144 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4145 }
4146 else
4147 {
4148 fragP->fr_subtype = TAB (PCINDEX, LONG);
4149 fragP->fr_var += 4;
4150 }
4151 break;
4152
4153 default:
4154 break;
4155 }
4156
4157 /* now that SZ_UNDEF are taken care of, check others */
4158 switch (fragP->fr_subtype)
4159 {
4160 case TAB (BCC68000, BYTE):
4161 case TAB (ABRANCH, BYTE):
4162 /* We can't do a short jump to the next instruction, so we force
4163 word mode. At this point S_GET_VALUE should return the
4164 offset of the symbol within its frag. If the symbol is at
4165 the start of a frag, and it is the next frag with any data in
4166 it (usually this just the next frag, but assembler listings
4167 may introduce empty frags), we must use word mode. */
4168 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4169 {
4170 fragS *l;
4171
4172 for (l = fragP->fr_next;
4173 l != fragP->fr_symbol->sy_frag;
4174 l = l->fr_next)
4175 if (l->fr_fix + l->fr_var != 0)
4176 break;
4177 if (l == fragP->fr_symbol->sy_frag)
4178 {
4179 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4180 fragP->fr_var += 2;
4181 }
4182 }
4183 break;
4184 default:
4185 break;
4186 }
4187 return fragP->fr_var + fragP->fr_fix - old_fix;
4188 }
4189
4190 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4191 /* the bit-field entries in the relocation_info struct plays hell
4192 with the byte-order problems of cross-assembly. So as a hack,
4193 I added this mach. dependent ri twiddler. Ugly, but it gets
4194 you there. -KWK */
4195 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4196 are symbolnum, most sig. byte first. Last byte is broken up with
4197 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4198 nibble as nuthin. (on Sun 3 at least) */
4199 /* Translate the internal relocation information into target-specific
4200 format. */
4201 #ifdef comment
4202 void
4203 md_ri_to_chars (the_bytes, ri)
4204 char *the_bytes;
4205 struct reloc_info_generic *ri;
4206 {
4207 /* this is easy */
4208 md_number_to_chars (the_bytes, ri->r_address, 4);
4209 /* now the fun stuff */
4210 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4211 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4212 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4213 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4214 ((ri->r_extern << 4) & 0x10));
4215 }
4216
4217 #endif /* comment */
4218
4219 #ifndef BFD_ASSEMBLER
4220 void
4221 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4222 char *where;
4223 fixS *fixP;
4224 relax_addressT segment_address_in_file;
4225 {
4226 /*
4227 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4228 * Out: GNU LD relocation length code: 0, 1, or 2.
4229 */
4230
4231 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4232 long r_symbolnum;
4233
4234 know (fixP->fx_addsy != NULL);
4235
4236 md_number_to_chars (where,
4237 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4238 4);
4239
4240 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4241 ? S_GET_TYPE (fixP->fx_addsy)
4242 : fixP->fx_addsy->sy_number);
4243
4244 where[4] = (r_symbolnum >> 16) & 0x0ff;
4245 where[5] = (r_symbolnum >> 8) & 0x0ff;
4246 where[6] = r_symbolnum & 0x0ff;
4247 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4248 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4249 }
4250 #endif
4251
4252 #endif /* OBJ_AOUT or OBJ_BOUT */
4253
4254 #ifndef WORKING_DOT_WORD
4255 CONST int md_short_jump_size = 4;
4256 CONST int md_long_jump_size = 6;
4257
4258 void
4259 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4260 char *ptr;
4261 addressT from_addr, to_addr;
4262 fragS *frag;
4263 symbolS *to_symbol;
4264 {
4265 valueT offset;
4266
4267 offset = to_addr - (from_addr + 2);
4268
4269 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4270 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4271 }
4272
4273 void
4274 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4275 char *ptr;
4276 addressT from_addr, to_addr;
4277 fragS *frag;
4278 symbolS *to_symbol;
4279 {
4280 valueT offset;
4281
4282 if (cpu_of_arch (current_architecture) < m68020)
4283 {
4284 offset = to_addr - S_GET_VALUE (to_symbol);
4285 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4286 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4287 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4288 0, NO_RELOC);
4289 }
4290 else
4291 {
4292 offset = to_addr - (from_addr + 2);
4293 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4294 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4295 }
4296 }
4297
4298 #endif
4299
4300 /* Different values of OK tell what its OK to return. Things that
4301 aren't OK are an error (what a shock, no?)
4302
4303 0: Everything is OK
4304 10: Absolute 1:8 only
4305 20: Absolute 0:7 only
4306 30: absolute 0:15 only
4307 40: Absolute 0:31 only
4308 50: absolute 0:127 only
4309 55: absolute -64:63 only
4310 60: absolute -128:127 only
4311 70: absolute 0:4095 only
4312 80: No bignums
4313
4314 */
4315
4316 static int
4317 get_num (exp, ok)
4318 struct m68k_exp *exp;
4319 int ok;
4320 {
4321 if (exp->exp.X_op == O_absent)
4322 {
4323 /* Do the same thing the VAX asm does */
4324 op (exp) = O_constant;
4325 adds (exp) = 0;
4326 subs (exp) = 0;
4327 offs (exp) = 0;
4328 if (ok == 10)
4329 {
4330 as_warn ("expression out of range: defaulting to 1");
4331 offs (exp) = 1;
4332 }
4333 }
4334 else if (exp->exp.X_op == O_constant)
4335 {
4336 switch (ok)
4337 {
4338 case 10:
4339 if (offs (exp) < 1 || offs (exp) > 8)
4340 {
4341 as_warn ("expression out of range: defaulting to 1");
4342 offs (exp) = 1;
4343 }
4344 break;
4345 case 20:
4346 if (offs (exp) < 0 || offs (exp) > 7)
4347 goto outrange;
4348 break;
4349 case 30:
4350 if (offs (exp) < 0 || offs (exp) > 15)
4351 goto outrange;
4352 break;
4353 case 40:
4354 if (offs (exp) < 0 || offs (exp) > 32)
4355 goto outrange;
4356 break;
4357 case 50:
4358 if (offs (exp) < 0 || offs (exp) > 127)
4359 goto outrange;
4360 break;
4361 case 55:
4362 if (offs (exp) < -64 || offs (exp) > 63)
4363 goto outrange;
4364 break;
4365 case 60:
4366 if (offs (exp) < -128 || offs (exp) > 127)
4367 goto outrange;
4368 break;
4369 case 70:
4370 if (offs (exp) < 0 || offs (exp) > 4095)
4371 {
4372 outrange:
4373 as_warn ("expression out of range: defaulting to 0");
4374 offs (exp) = 0;
4375 }
4376 break;
4377 default:
4378 break;
4379 }
4380 }
4381 else if (exp->exp.X_op == O_big)
4382 {
4383 if (offs (exp) <= 0 /* flonum */
4384 && (ok == 80 /* no bignums */
4385 || (ok > 10 /* small-int ranges including 0 ok */
4386 /* If we have a flonum zero, a zero integer should
4387 do as well (e.g., in moveq). */
4388 && generic_floating_point_number.exponent == 0
4389 && generic_floating_point_number.low[0] == 0)))
4390 {
4391 /* HACK! Turn it into a long */
4392 LITTLENUM_TYPE words[6];
4393
4394 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4395 op (exp) = O_constant;
4396 adds (exp) = 0;
4397 subs (exp) = 0;
4398 offs (exp) = words[1] | (words[0] << 16);
4399 }
4400 else if (ok != 0)
4401 {
4402 op (exp) = O_constant;
4403 adds (exp) = 0;
4404 subs (exp) = 0;
4405 offs (exp) = (ok == 10) ? 1 : 0;
4406 as_warn ("Can't deal with expression; defaulting to %ld",
4407 offs (exp));
4408 }
4409 }
4410 else
4411 {
4412 if (ok >= 10 && ok <= 70)
4413 {
4414 op (exp) = O_constant;
4415 adds (exp) = 0;
4416 subs (exp) = 0;
4417 offs (exp) = (ok == 10) ? 1 : 0;
4418 as_warn ("Can't deal with expression; defaulting to %ld",
4419 offs (exp));
4420 }
4421 }
4422
4423 if (exp->size != SIZE_UNSPEC)
4424 {
4425 switch (exp->size)
4426 {
4427 case SIZE_UNSPEC:
4428 case SIZE_LONG:
4429 break;
4430 case SIZE_BYTE:
4431 if (!isbyte (offs (exp)))
4432 as_warn ("expression doesn't fit in BYTE");
4433 break;
4434 case SIZE_WORD:
4435 if (!isword (offs (exp)))
4436 as_warn ("expression doesn't fit in WORD");
4437 break;
4438 }
4439 }
4440
4441 return offs (exp);
4442 }
4443
4444 /* These are the back-ends for the various machine dependent pseudo-ops. */
4445 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4446
4447 static void
4448 s_data1 (ignore)
4449 int ignore;
4450 {
4451 subseg_set (data_section, 1);
4452 demand_empty_rest_of_line ();
4453 }
4454
4455 static void
4456 s_data2 (ignore)
4457 int ignore;
4458 {
4459 subseg_set (data_section, 2);
4460 demand_empty_rest_of_line ();
4461 }
4462
4463 static void
4464 s_bss (ignore)
4465 int ignore;
4466 {
4467 /* We don't support putting frags in the BSS segment, we fake it
4468 by marking in_bss, then looking at s_skip for clues. */
4469
4470 subseg_set (bss_section, 0);
4471 demand_empty_rest_of_line ();
4472 }
4473
4474 static void
4475 s_even (ignore)
4476 int ignore;
4477 {
4478 register int temp;
4479 register long temp_fill;
4480
4481 temp = 1; /* JF should be 2? */
4482 temp_fill = get_absolute_expression ();
4483 if (!need_pass_2) /* Never make frag if expect extra pass. */
4484 frag_align (temp, (int) temp_fill);
4485 demand_empty_rest_of_line ();
4486 }
4487
4488 static void
4489 s_proc (ignore)
4490 int ignore;
4491 {
4492 demand_empty_rest_of_line ();
4493 }
4494 \f
4495 /* Pseudo-ops handled for MRI compatibility. */
4496
4497 /* Handle an MRI style chip specification. */
4498
4499 static void
4500 mri_chip ()
4501 {
4502 char *s;
4503 char c;
4504 int i;
4505
4506 s = input_line_pointer;
4507 c = get_symbol_end ();
4508 for (i = 0; i < n_archs; i++)
4509 if (strcasecmp (s, archs[i].name) == 0)
4510 break;
4511 if (i >= n_archs)
4512 {
4513 as_bad ("%s: unrecognized processor name", s);
4514 *input_line_pointer = c;
4515 ignore_rest_of_line ();
4516 return;
4517 }
4518 *input_line_pointer = c;
4519
4520 if (*input_line_pointer == '/')
4521 current_architecture = 0;
4522 else
4523 current_architecture &= m68881 | m68851;
4524 current_architecture |= archs[i].arch;
4525
4526 while (*input_line_pointer == '/')
4527 {
4528 ++input_line_pointer;
4529 s = input_line_pointer;
4530 c = get_symbol_end ();
4531 if (strcmp (s, "68881") == 0)
4532 current_architecture |= m68881;
4533 else if (strcmp (s, "68851") == 0)
4534 current_architecture |= m68851;
4535 *input_line_pointer = c;
4536 }
4537 }
4538
4539 /* The MRI CHIP pseudo-op. */
4540
4541 static void
4542 s_chip (ignore)
4543 int ignore;
4544 {
4545 char *stop = NULL;
4546 char stopc;
4547
4548 if (flag_mri)
4549 stop = mri_comment_field (&stopc);
4550 mri_chip ();
4551 if (flag_mri)
4552 mri_comment_end (stop, stopc);
4553 demand_empty_rest_of_line ();
4554 }
4555
4556 /* The MRI FOPT pseudo-op. */
4557
4558 static void
4559 s_fopt (ignore)
4560 int ignore;
4561 {
4562 SKIP_WHITESPACE ();
4563
4564 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4565 {
4566 int temp;
4567
4568 input_line_pointer += 3;
4569 temp = get_absolute_expression ();
4570 if (temp < 0 || temp > 7)
4571 as_bad ("bad coprocessor id");
4572 else
4573 m68k_float_copnum = COP0 + temp;
4574 }
4575 else
4576 {
4577 as_bad ("unrecognized fopt option");
4578 ignore_rest_of_line ();
4579 return;
4580 }
4581
4582 demand_empty_rest_of_line ();
4583 }
4584
4585 /* The structure used to handle the MRI OPT pseudo-op. */
4586
4587 struct opt_action
4588 {
4589 /* The name of the option. */
4590 const char *name;
4591
4592 /* If this is not NULL, just call this function. The first argument
4593 is the ARG field of this structure, the second argument is
4594 whether the option was negated. */
4595 void (*pfn) PARAMS ((int arg, int on));
4596
4597 /* If this is not NULL, and the PFN field is NULL, set the variable
4598 this points to. Set it to the ARG field if the option was not
4599 negated, and the NOTARG field otherwise. */
4600 int *pvar;
4601
4602 /* The value to pass to PFN or to assign to *PVAR. */
4603 int arg;
4604
4605 /* The value to assign to *PVAR if the option is negated. If PFN is
4606 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4607 the option may not be negated. */
4608 int notarg;
4609 };
4610
4611 /* The table used to handle the MRI OPT pseudo-op. */
4612
4613 static void skip_to_comma PARAMS ((int, int));
4614 static void opt_nest PARAMS ((int, int));
4615 static void opt_chip PARAMS ((int, int));
4616 static void opt_list PARAMS ((int, int));
4617 static void opt_list_symbols PARAMS ((int, int));
4618
4619 static const struct opt_action opt_table[] =
4620 {
4621 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4622
4623 /* We do relaxing, so there is little use for these options. */
4624 { "b", 0, 0, 0, 0 },
4625 { "brs", 0, 0, 0, 0 },
4626 { "brb", 0, 0, 0, 0 },
4627 { "brl", 0, 0, 0, 0 },
4628 { "brw", 0, 0, 0, 0 },
4629
4630 { "c", 0, 0, 0, 0 },
4631 { "cex", 0, 0, 0, 0 },
4632 { "case", 0, &symbols_case_sensitive, 1, 0 },
4633 { "cl", 0, 0, 0, 0 },
4634 { "cre", 0, 0, 0, 0 },
4635 { "d", 0, &flag_keep_locals, 1, 0 },
4636 { "e", 0, 0, 0, 0 },
4637 { "f", 0, &flag_short_refs, 1, 0 },
4638 { "frs", 0, &flag_short_refs, 1, 0 },
4639 { "frl", 0, &flag_short_refs, 0, 1 },
4640 { "g", 0, 0, 0, 0 },
4641 { "i", 0, 0, 0, 0 },
4642 { "m", 0, 0, 0, 0 },
4643 { "mex", 0, 0, 0, 0 },
4644 { "mc", 0, 0, 0, 0 },
4645 { "md", 0, 0, 0, 0 },
4646 { "nest", opt_nest, 0, 0, 0 },
4647 { "next", skip_to_comma, 0, 0, 0 },
4648 { "o", 0, 0, 0, 0 },
4649 { "old", 0, 0, 0, 0 },
4650 { "op", skip_to_comma, 0, 0, 0 },
4651 { "pco", 0, 0, 0, 0 },
4652 { "p", opt_chip, 0, 0, 0 },
4653 { "pcr", 0, 0, 0, 0 },
4654 { "pcs", 0, 0, 0, 0 },
4655 { "r", 0, 0, 0, 0 },
4656 { "quick", 0, &m68k_quick, 1, 0 },
4657 { "rel32", 0, &m68k_rel32, 1, 0 },
4658 { "s", opt_list, 0, 0, 0 },
4659 { "t", opt_list_symbols, 0, 0, 0 },
4660 { "w", 0, &flag_no_warnings, 0, 1 },
4661 { "x", 0, 0, 0, 0 }
4662 };
4663
4664 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4665
4666 /* The MRI OPT pseudo-op. */
4667
4668 static void
4669 s_opt (ignore)
4670 int ignore;
4671 {
4672 do
4673 {
4674 int t;
4675 char *s;
4676 char c;
4677 int i;
4678 const struct opt_action *o;
4679
4680 SKIP_WHITESPACE ();
4681
4682 t = 1;
4683 if (*input_line_pointer == '-')
4684 {
4685 ++input_line_pointer;
4686 t = 0;
4687 }
4688 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4689 {
4690 input_line_pointer += 2;
4691 t = 0;
4692 }
4693
4694 s = input_line_pointer;
4695 c = get_symbol_end ();
4696
4697 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4698 {
4699 if (strcasecmp (s, o->name) == 0)
4700 {
4701 if (o->pfn)
4702 {
4703 /* Restore input_line_pointer now in case the option
4704 takes arguments. */
4705 *input_line_pointer = c;
4706 (*o->pfn) (o->arg, t);
4707 }
4708 else if (o->pvar != NULL)
4709 {
4710 if (! t && o->arg == o->notarg)
4711 as_bad ("option `%s' may not be negated", s);
4712 *input_line_pointer = c;
4713 *o->pvar = t ? o->arg : o->notarg;
4714 }
4715 else
4716 *input_line_pointer = c;
4717 break;
4718 }
4719 }
4720 if (i >= OPTCOUNT)
4721 {
4722 as_bad ("option `%s' not recognized", s);
4723 *input_line_pointer = c;
4724 }
4725 }
4726 while (*input_line_pointer++ == ',');
4727
4728 /* Move back to terminating character. */
4729 --input_line_pointer;
4730 demand_empty_rest_of_line ();
4731 }
4732
4733 /* Skip ahead to a comma. This is used for OPT options which we do
4734 not suppor tand which take arguments. */
4735
4736 static void
4737 skip_to_comma (arg, on)
4738 int arg;
4739 int on;
4740 {
4741 while (*input_line_pointer != ','
4742 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4743 ++input_line_pointer;
4744 }
4745
4746 /* Handle the OPT NEST=depth option. */
4747
4748 static void
4749 opt_nest (arg, on)
4750 int arg;
4751 int on;
4752 {
4753 if (*input_line_pointer != '=')
4754 {
4755 as_bad ("bad format of OPT NEST=depth");
4756 return;
4757 }
4758
4759 ++input_line_pointer;
4760 max_macro_nest = get_absolute_expression ();
4761 }
4762
4763 /* Handle the OPT P=chip option. */
4764
4765 static void
4766 opt_chip (arg, on)
4767 int arg;
4768 int on;
4769 {
4770 if (*input_line_pointer != '=')
4771 {
4772 /* This is just OPT P, which we do not support. */
4773 return;
4774 }
4775
4776 ++input_line_pointer;
4777 mri_chip ();
4778 }
4779
4780 /* Handle the OPT S option. */
4781
4782 static void
4783 opt_list (arg, on)
4784 int arg;
4785 int on;
4786 {
4787 listing_list (on);
4788 }
4789
4790 /* Handle the OPT T option. */
4791
4792 static void
4793 opt_list_symbols (arg, on)
4794 int arg;
4795 int on;
4796 {
4797 if (on)
4798 listing |= LISTING_SYMBOLS;
4799 else
4800 listing &=~ LISTING_SYMBOLS;
4801 }
4802
4803 /* Handle the MRI REG pseudo-op. */
4804
4805 static void
4806 s_reg (ignore)
4807 int ignore;
4808 {
4809 char *s;
4810 int c;
4811 struct m68k_op rop;
4812 unsigned long mask;
4813 char *stop = NULL;
4814 char stopc;
4815
4816 if (line_label == NULL)
4817 {
4818 as_bad ("missing label");
4819 ignore_rest_of_line ();
4820 return;
4821 }
4822
4823 if (flag_mri)
4824 stop = mri_comment_field (&stopc);
4825
4826 SKIP_WHITESPACE ();
4827
4828 s = input_line_pointer;
4829 while (isalnum ((unsigned char) *input_line_pointer)
4830 #ifdef REGISTER_PREFIX
4831 || *input_line_pointer == REGISTER_PREFIX
4832 #endif
4833 || *input_line_pointer == '/'
4834 || *input_line_pointer == '-')
4835 ++input_line_pointer;
4836 c = *input_line_pointer;
4837 *input_line_pointer = '\0';
4838
4839 if (m68k_ip_op (s, &rop) != 0)
4840 {
4841 if (rop.error == NULL)
4842 as_bad ("bad register list");
4843 else
4844 as_bad ("bad register list: %s", rop.error);
4845 *input_line_pointer = c;
4846 ignore_rest_of_line ();
4847 return;
4848 }
4849
4850 *input_line_pointer = c;
4851
4852 if (rop.mode == REGLST)
4853 mask = rop.mask;
4854 else if (rop.mode == DREG)
4855 mask = 1 << (rop.reg - DATA0);
4856 else if (rop.mode == AREG)
4857 mask = 1 << (rop.reg - ADDR0 + 8);
4858 else if (rop.mode == FPREG)
4859 mask = 1 << (rop.reg - FP0 + 16);
4860 else if (rop.mode == CONTROL
4861 && rop.reg == FPI)
4862 mask = 1 << 24;
4863 else if (rop.mode == CONTROL
4864 && rop.reg == FPS)
4865 mask = 1 << 25;
4866 else if (rop.mode == CONTROL
4867 && rop.reg == FPC)
4868 mask = 1 << 26;
4869 else
4870 {
4871 as_bad ("bad register list");
4872 ignore_rest_of_line ();
4873 return;
4874 }
4875
4876 S_SET_SEGMENT (line_label, absolute_section);
4877 S_SET_VALUE (line_label, mask);
4878 line_label->sy_frag = &zero_address_frag;
4879
4880 if (flag_mri)
4881 mri_comment_end (stop, stopc);
4882
4883 demand_empty_rest_of_line ();
4884 }
4885
4886 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4887
4888 struct save_opts
4889 {
4890 struct save_opts *next;
4891 int abspcadd;
4892 int symbols_case_sensitive;
4893 int keep_locals;
4894 int short_refs;
4895 int architecture;
4896 int quick;
4897 int rel32;
4898 int listing;
4899 int no_warnings;
4900 /* FIXME: We don't save OPT S. */
4901 };
4902
4903 /* This variable holds the stack of saved options. */
4904
4905 static struct save_opts *save_stack;
4906
4907 /* The MRI SAVE pseudo-op. */
4908
4909 static void
4910 s_save (ignore)
4911 int ignore;
4912 {
4913 struct save_opts *s;
4914
4915 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
4916 s->abspcadd = m68k_abspcadd;
4917 s->symbols_case_sensitive = symbols_case_sensitive;
4918 s->keep_locals = flag_keep_locals;
4919 s->short_refs = flag_short_refs;
4920 s->architecture = current_architecture;
4921 s->quick = m68k_quick;
4922 s->rel32 = m68k_rel32;
4923 s->listing = listing;
4924 s->no_warnings = flag_no_warnings;
4925
4926 s->next = save_stack;
4927 save_stack = s;
4928
4929 demand_empty_rest_of_line ();
4930 }
4931
4932 /* The MRI RESTORE pseudo-op. */
4933
4934 static void
4935 s_restore (ignore)
4936 int ignore;
4937 {
4938 struct save_opts *s;
4939
4940 if (save_stack == NULL)
4941 {
4942 as_bad ("restore without save");
4943 ignore_rest_of_line ();
4944 return;
4945 }
4946
4947 s = save_stack;
4948 save_stack = s->next;
4949
4950 m68k_abspcadd = s->abspcadd;
4951 symbols_case_sensitive = s->symbols_case_sensitive;
4952 flag_keep_locals = s->keep_locals;
4953 flag_short_refs = s->short_refs;
4954 current_architecture = s->architecture;
4955 m68k_quick = s->quick;
4956 m68k_rel32 = s->rel32;
4957 listing = s->listing;
4958 flag_no_warnings = s->no_warnings;
4959
4960 free (s);
4961
4962 demand_empty_rest_of_line ();
4963 }
4964
4965 /* Types of MRI structured control directives. */
4966
4967 enum mri_control_type
4968 {
4969 mri_for,
4970 mri_if,
4971 mri_repeat,
4972 mri_while
4973 };
4974
4975 /* This structure is used to stack the MRI structured control
4976 directives. */
4977
4978 struct mri_control_info
4979 {
4980 /* The directive within which this one is enclosed. */
4981 struct mri_control_info *outer;
4982
4983 /* The type of directive. */
4984 enum mri_control_type type;
4985
4986 /* Whether an ELSE has been in an IF. */
4987 int else_seen;
4988
4989 /* The add or sub statement at the end of a FOR. */
4990 char *incr;
4991
4992 /* The label of the top of a FOR or REPEAT loop. */
4993 char *top;
4994
4995 /* The label to jump to for the next iteration, or the else
4996 expression of a conditional. */
4997 char *next;
4998
4999 /* The label to jump to to break out of the loop, or the label past
5000 the end of a conditional. */
5001 char *bottom;
5002 };
5003
5004 /* The stack of MRI structured control directives. */
5005
5006 static struct mri_control_info *mri_control_stack;
5007
5008 /* The current MRI structured control directive index number, used to
5009 generate label names. */
5010
5011 static int mri_control_index;
5012
5013 /* Some function prototypes. */
5014
5015 static char *mri_control_label PARAMS ((void));
5016 static struct mri_control_info *push_mri_control
5017 PARAMS ((enum mri_control_type));
5018 static void pop_mri_control PARAMS ((void));
5019 static int parse_mri_condition PARAMS ((int *));
5020 static int parse_mri_control_operand
5021 PARAMS ((int *, char **, char **, char **, char **));
5022 static int swap_mri_condition PARAMS ((int));
5023 static int reverse_mri_condition PARAMS ((int));
5024 static void build_mri_control_operand
5025 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5026 const char *, int));
5027 static void parse_mri_control_expression
5028 PARAMS ((char *, int, const char *, const char *, int));
5029
5030 /* Generate a new MRI label structured control directive label name. */
5031
5032 static char *
5033 mri_control_label ()
5034 {
5035 char *n;
5036
5037 n = (char *) xmalloc (20);
5038 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5039 ++mri_control_index;
5040 return n;
5041 }
5042
5043 /* Create a new MRI structured control directive. */
5044
5045 static struct mri_control_info *
5046 push_mri_control (type)
5047 enum mri_control_type type;
5048 {
5049 struct mri_control_info *n;
5050
5051 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5052
5053 n->type = type;
5054 n->else_seen = 0;
5055 if (type == mri_if || type == mri_while)
5056 n->top = NULL;
5057 else
5058 n->top = mri_control_label ();
5059 n->next = mri_control_label ();
5060 n->bottom = mri_control_label ();
5061
5062 n->outer = mri_control_stack;
5063 mri_control_stack = n;
5064
5065 return n;
5066 }
5067
5068 /* Pop off the stack of MRI structured control directives. */
5069
5070 static void
5071 pop_mri_control ()
5072 {
5073 struct mri_control_info *n;
5074
5075 n = mri_control_stack;
5076 mri_control_stack = n->outer;
5077 if (n->top != NULL)
5078 free (n->top);
5079 free (n->next);
5080 free (n->bottom);
5081 free (n);
5082 }
5083
5084 /* Recognize a condition code in an MRI structured control expression. */
5085
5086 static int
5087 parse_mri_condition (pcc)
5088 int *pcc;
5089 {
5090 char c1, c2;
5091
5092 know (*input_line_pointer == '<');
5093
5094 ++input_line_pointer;
5095 c1 = *input_line_pointer++;
5096 c2 = *input_line_pointer++;
5097
5098 if (*input_line_pointer != '>')
5099 {
5100 as_bad ("syntax error in structured control directive");
5101 return 0;
5102 }
5103
5104 ++input_line_pointer;
5105 SKIP_WHITESPACE ();
5106
5107 if (isupper (c1))
5108 c1 = tolower (c1);
5109 if (isupper (c2))
5110 c2 = tolower (c2);
5111
5112 *pcc = (c1 << 8) | c2;
5113
5114 return 1;
5115 }
5116
5117 /* Parse a single operand in an MRI structured control expression. */
5118
5119 static int
5120 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5121 int *pcc;
5122 char **leftstart;
5123 char **leftstop;
5124 char **rightstart;
5125 char **rightstop;
5126 {
5127 char *s;
5128
5129 SKIP_WHITESPACE ();
5130
5131 *pcc = -1;
5132 *leftstart = NULL;
5133 *leftstop = NULL;
5134 *rightstart = NULL;
5135 *rightstop = NULL;
5136
5137 if (*input_line_pointer == '<')
5138 {
5139 /* It's just a condition code. */
5140 return parse_mri_condition (pcc);
5141 }
5142
5143 /* Look ahead for the condition code. */
5144 for (s = input_line_pointer; *s != '\0'; ++s)
5145 {
5146 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5147 break;
5148 }
5149 if (*s == '\0')
5150 {
5151 as_bad ("missing condition code in structured control directive");
5152 return 0;
5153 }
5154
5155 *leftstart = input_line_pointer;
5156 *leftstop = s;
5157 if (*leftstop > *leftstart
5158 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5159 --*leftstop;
5160
5161 input_line_pointer = s;
5162 if (! parse_mri_condition (pcc))
5163 return 0;
5164
5165 /* Look ahead for AND or OR or end of line. */
5166 for (s = input_line_pointer; *s != '\0'; ++s)
5167 {
5168 if ((strncasecmp (s, "AND", 3) == 0
5169 && (s[3] == '.' || ! is_part_of_name (s[3])))
5170 || (strncasecmp (s, "OR", 2) == 0
5171 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5172 break;
5173 }
5174
5175 *rightstart = input_line_pointer;
5176 *rightstop = s;
5177 if (*rightstop > *rightstart
5178 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5179 --*rightstop;
5180
5181 input_line_pointer = s;
5182
5183 return 1;
5184 }
5185
5186 #define MCC(b1, b2) (((b1) << 8) | (b2))
5187
5188 /* Swap the sense of a condition. This changes the condition so that
5189 it generates the same result when the operands are swapped. */
5190
5191 static int
5192 swap_mri_condition (cc)
5193 int cc;
5194 {
5195 switch (cc)
5196 {
5197 case MCC ('h', 'i'): return MCC ('c', 's');
5198 case MCC ('l', 's'): return MCC ('c', 'c');
5199 case MCC ('c', 'c'): return MCC ('l', 's');
5200 case MCC ('c', 's'): return MCC ('h', 'i');
5201 case MCC ('p', 'l'): return MCC ('m', 'i');
5202 case MCC ('m', 'i'): return MCC ('p', 'l');
5203 case MCC ('g', 'e'): return MCC ('l', 'e');
5204 case MCC ('l', 't'): return MCC ('g', 't');
5205 case MCC ('g', 't'): return MCC ('l', 't');
5206 case MCC ('l', 'e'): return MCC ('g', 'e');
5207 }
5208 return cc;
5209 }
5210
5211 /* Reverse the sense of a condition. */
5212
5213 static int
5214 reverse_mri_condition (cc)
5215 int cc;
5216 {
5217 switch (cc)
5218 {
5219 case MCC ('h', 'i'): return MCC ('l', 's');
5220 case MCC ('l', 's'): return MCC ('h', 'i');
5221 case MCC ('c', 'c'): return MCC ('c', 's');
5222 case MCC ('c', 's'): return MCC ('c', 'c');
5223 case MCC ('n', 'e'): return MCC ('e', 'q');
5224 case MCC ('e', 'q'): return MCC ('n', 'e');
5225 case MCC ('v', 'c'): return MCC ('v', 's');
5226 case MCC ('v', 's'): return MCC ('v', 'c');
5227 case MCC ('p', 'l'): return MCC ('m', 'i');
5228 case MCC ('m', 'i'): return MCC ('p', 'l');
5229 case MCC ('g', 'e'): return MCC ('l', 't');
5230 case MCC ('l', 't'): return MCC ('g', 'e');
5231 case MCC ('g', 't'): return MCC ('l', 'e');
5232 case MCC ('l', 'e'): return MCC ('g', 't');
5233 }
5234 return cc;
5235 }
5236
5237 /* Build an MRI structured control expression. This generates test
5238 and branch instructions. It goes to TRUELAB if the condition is
5239 true, and to FALSELAB if the condition is false. Exactly one of
5240 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5241 is the size qualifier for the expression. EXTENT is the size to
5242 use for the branch. */
5243
5244 static void
5245 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5246 rightstop, truelab, falselab, extent)
5247 int qual;
5248 int cc;
5249 char *leftstart;
5250 char *leftstop;
5251 char *rightstart;
5252 char *rightstop;
5253 const char *truelab;
5254 const char *falselab;
5255 int extent;
5256 {
5257 char *buf;
5258 char *s;
5259
5260 if (leftstart != NULL)
5261 {
5262 struct m68k_op leftop, rightop;
5263 char c;
5264
5265 /* Swap the compare operands, if necessary, to produce a legal
5266 m68k compare instruction. Comparing a register operand with
5267 a non-register operand requires the register to be on the
5268 right (cmp, cmpa). Comparing an immediate value with
5269 anything requires the immediate value to be on the left
5270 (cmpi). */
5271
5272 c = *leftstop;
5273 *leftstop = '\0';
5274 (void) m68k_ip_op (leftstart, &leftop);
5275 *leftstop = c;
5276
5277 c = *rightstop;
5278 *rightstop = '\0';
5279 (void) m68k_ip_op (rightstart, &rightop);
5280 *rightstop = c;
5281
5282 if (rightop.mode == IMMED
5283 || ((leftop.mode == DREG || leftop.mode == AREG)
5284 && (rightop.mode != DREG && rightop.mode != AREG)))
5285 {
5286 char *temp;
5287
5288 cc = swap_mri_condition (cc);
5289 temp = leftstart;
5290 leftstart = rightstart;
5291 rightstart = temp;
5292 temp = leftstop;
5293 leftstop = rightstop;
5294 rightstop = temp;
5295 }
5296 }
5297
5298 if (truelab == NULL)
5299 {
5300 cc = reverse_mri_condition (cc);
5301 truelab = falselab;
5302 }
5303
5304 if (leftstart != NULL)
5305 {
5306 buf = (char *) xmalloc (20
5307 + (leftstop - leftstart)
5308 + (rightstop - rightstart));
5309 s = buf;
5310 *s++ = 'c';
5311 *s++ = 'm';
5312 *s++ = 'p';
5313 if (qual != '\0')
5314 *s++ = qual;
5315 *s++ = ' ';
5316 memcpy (s, leftstart, leftstop - leftstart);
5317 s += leftstop - leftstart;
5318 *s++ = ',';
5319 memcpy (s, rightstart, rightstop - rightstart);
5320 s += rightstop - rightstart;
5321 *s = '\0';
5322 md_assemble (buf);
5323 free (buf);
5324 }
5325
5326 buf = (char *) xmalloc (20 + strlen (truelab));
5327 s = buf;
5328 *s++ = 'b';
5329 *s++ = cc >> 8;
5330 *s++ = cc & 0xff;
5331 if (extent != '\0')
5332 *s++ = extent;
5333 *s++ = ' ';
5334 strcpy (s, truelab);
5335 md_assemble (buf);
5336 free (buf);
5337 }
5338
5339 /* Parse an MRI structured control expression. This generates test
5340 and branch instructions. STOP is where the expression ends. It
5341 goes to TRUELAB if the condition is true, and to FALSELAB if the
5342 condition is false. Exactly one of TRUELAB and FALSELAB will be
5343 NULL, meaning to fall through. QUAL is the size qualifier for the
5344 expression. EXTENT is the size to use for the branch. */
5345
5346 static void
5347 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5348 char *stop;
5349 int qual;
5350 const char *truelab;
5351 const char *falselab;
5352 int extent;
5353 {
5354 int c;
5355 int cc;
5356 char *leftstart;
5357 char *leftstop;
5358 char *rightstart;
5359 char *rightstop;
5360
5361 c = *stop;
5362 *stop = '\0';
5363
5364 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5365 &rightstart, &rightstop))
5366 {
5367 *stop = c;
5368 return;
5369 }
5370
5371 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5372 {
5373 const char *flab;
5374
5375 if (falselab != NULL)
5376 flab = falselab;
5377 else
5378 flab = mri_control_label ();
5379
5380 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5381 rightstop, (const char *) NULL, flab, extent);
5382
5383 input_line_pointer += 3;
5384 if (*input_line_pointer != '.'
5385 || input_line_pointer[1] == '\0')
5386 qual = '\0';
5387 else
5388 {
5389 qual = input_line_pointer[1];
5390 input_line_pointer += 2;
5391 }
5392
5393 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5394 &rightstart, &rightstop))
5395 {
5396 *stop = c;
5397 return;
5398 }
5399
5400 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5401 rightstop, truelab, falselab, extent);
5402
5403 if (falselab == NULL)
5404 colon (flab);
5405 }
5406 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5407 {
5408 const char *tlab;
5409
5410 if (truelab != NULL)
5411 tlab = truelab;
5412 else
5413 tlab = mri_control_label ();
5414
5415 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5416 rightstop, tlab, (const char *) NULL, extent);
5417
5418 input_line_pointer += 2;
5419 if (*input_line_pointer != '.'
5420 || input_line_pointer[1] == '\0')
5421 qual = '\0';
5422 else
5423 {
5424 qual = input_line_pointer[1];
5425 input_line_pointer += 2;
5426 }
5427
5428 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5429 &rightstart, &rightstop))
5430 {
5431 *stop = c;
5432 return;
5433 }
5434
5435 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5436 rightstop, truelab, falselab, extent);
5437
5438 if (truelab == NULL)
5439 colon (tlab);
5440 }
5441 else
5442 {
5443 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5444 rightstop, truelab, falselab, extent);
5445 }
5446
5447 *stop = c;
5448 if (input_line_pointer != stop)
5449 as_bad ("syntax error in structured control directive");
5450 }
5451
5452 /* Handle the MRI IF pseudo-op. This may be a structured control
5453 directive, or it may be a regular assembler conditional, depending
5454 on its operands. */
5455
5456 static void
5457 s_mri_if (qual)
5458 int qual;
5459 {
5460 char *s;
5461 int c;
5462 struct mri_control_info *n;
5463
5464 /* A structured control directive must end with THEN with an
5465 optional qualifier. */
5466 s = input_line_pointer;
5467 while (! is_end_of_line[(unsigned char) *s]
5468 && (! flag_mri || *s != '*'))
5469 ++s;
5470 --s;
5471 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5472 --s;
5473
5474 if (s - input_line_pointer > 1
5475 && s[-1] == '.')
5476 s -= 2;
5477
5478 if (s - input_line_pointer < 3
5479 || strncasecmp (s - 3, "THEN", 4) != 0)
5480 {
5481 if (qual != '\0')
5482 {
5483 as_bad ("missing then");
5484 ignore_rest_of_line ();
5485 return;
5486 }
5487
5488 /* It's a conditional. */
5489 s_if (O_ne);
5490 return;
5491 }
5492
5493 /* Since this might be a conditional if, this pseudo-op will be
5494 called even if we are supported to be ignoring input. Double
5495 check now. Clobber *input_line_pointer so that ignore_input
5496 thinks that this is not a special pseudo-op. */
5497 c = *input_line_pointer;
5498 *input_line_pointer = 0;
5499 if (ignore_input ())
5500 {
5501 *input_line_pointer = c;
5502 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5503 ++input_line_pointer;
5504 demand_empty_rest_of_line ();
5505 return;
5506 }
5507 *input_line_pointer = c;
5508
5509 n = push_mri_control (mri_if);
5510
5511 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5512 n->next, s[1] == '.' ? s[2] : '\0');
5513
5514 if (s[1] == '.')
5515 input_line_pointer = s + 3;
5516 else
5517 input_line_pointer = s + 1;
5518
5519 if (flag_mri)
5520 {
5521 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5522 ++input_line_pointer;
5523 }
5524
5525 demand_empty_rest_of_line ();
5526 }
5527
5528 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5529 structured IF, associate the ELSE with the IF. Otherwise, assume
5530 it is a conditional else. */
5531
5532 static void
5533 s_mri_else (qual)
5534 int qual;
5535 {
5536 int c;
5537 char *buf;
5538 char q[2];
5539
5540 if (qual == '\0'
5541 && (mri_control_stack == NULL
5542 || mri_control_stack->type != mri_if
5543 || mri_control_stack->else_seen))
5544 {
5545 s_else (0);
5546 return;
5547 }
5548
5549 c = *input_line_pointer;
5550 *input_line_pointer = 0;
5551 if (ignore_input ())
5552 {
5553 *input_line_pointer = c;
5554 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5555 ++input_line_pointer;
5556 demand_empty_rest_of_line ();
5557 return;
5558 }
5559 *input_line_pointer = c;
5560
5561 if (mri_control_stack == NULL
5562 || mri_control_stack->type != mri_if
5563 || mri_control_stack->else_seen)
5564 {
5565 as_bad ("else without matching if");
5566 ignore_rest_of_line ();
5567 return;
5568 }
5569
5570 mri_control_stack->else_seen = 1;
5571
5572 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5573 q[0] = qual;
5574 q[1] = '\0';
5575 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5576 md_assemble (buf);
5577 free (buf);
5578
5579 colon (mri_control_stack->next);
5580
5581 if (flag_mri)
5582 {
5583 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5584 ++input_line_pointer;
5585 }
5586
5587 demand_empty_rest_of_line ();
5588 }
5589
5590 /* Handle the MRI ENDI pseudo-op. */
5591
5592 static void
5593 s_mri_endi (ignore)
5594 int ignore;
5595 {
5596 if (mri_control_stack == NULL
5597 || mri_control_stack->type != mri_if)
5598 {
5599 as_bad ("endi without matching if");
5600 ignore_rest_of_line ();
5601 return;
5602 }
5603
5604 /* ignore_input will not return true for ENDI, so we don't need to
5605 worry about checking it again here. */
5606
5607 if (! mri_control_stack->else_seen)
5608 colon (mri_control_stack->next);
5609 colon (mri_control_stack->bottom);
5610
5611 pop_mri_control ();
5612
5613 if (flag_mri)
5614 {
5615 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5616 ++input_line_pointer;
5617 }
5618
5619 demand_empty_rest_of_line ();
5620 }
5621
5622 /* Handle the MRI BREAK pseudo-op. */
5623
5624 static void
5625 s_mri_break (extent)
5626 int extent;
5627 {
5628 struct mri_control_info *n;
5629 char *buf;
5630 char ex[2];
5631
5632 n = mri_control_stack;
5633 while (n != NULL
5634 && n->type != mri_for
5635 && n->type != mri_repeat
5636 && n->type != mri_while)
5637 n = n->outer;
5638 if (n == NULL)
5639 {
5640 as_bad ("break outside of structured loop");
5641 ignore_rest_of_line ();
5642 return;
5643 }
5644
5645 buf = (char *) xmalloc (20 + strlen (n->bottom));
5646 ex[0] = extent;
5647 ex[1] = '\0';
5648 sprintf (buf, "bra%s %s", ex, n->bottom);
5649 md_assemble (buf);
5650 free (buf);
5651
5652 if (flag_mri)
5653 {
5654 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5655 ++input_line_pointer;
5656 }
5657
5658 demand_empty_rest_of_line ();
5659 }
5660
5661 /* Handle the MRI NEXT pseudo-op. */
5662
5663 static void
5664 s_mri_next (extent)
5665 int extent;
5666 {
5667 struct mri_control_info *n;
5668 char *buf;
5669 char ex[2];
5670
5671 n = mri_control_stack;
5672 while (n != NULL
5673 && n->type != mri_for
5674 && n->type != mri_repeat
5675 && n->type != mri_while)
5676 n = n->outer;
5677 if (n == NULL)
5678 {
5679 as_bad ("next outside of structured loop");
5680 ignore_rest_of_line ();
5681 return;
5682 }
5683
5684 buf = (char *) xmalloc (20 + strlen (n->next));
5685 ex[0] = extent;
5686 ex[1] = '\0';
5687 sprintf (buf, "bra%s %s", ex, n->next);
5688 md_assemble (buf);
5689 free (buf);
5690
5691 if (flag_mri)
5692 {
5693 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5694 ++input_line_pointer;
5695 }
5696
5697 demand_empty_rest_of_line ();
5698 }
5699
5700 /* Handle the MRI FOR pseudo-op. */
5701
5702 static void
5703 s_mri_for (qual)
5704 int qual;
5705 {
5706 const char *varstart, *varstop;
5707 const char *initstart, *initstop;
5708 const char *endstart, *endstop;
5709 const char *bystart, *bystop;
5710 int up;
5711 int by;
5712 int extent;
5713 struct mri_control_info *n;
5714 char *buf;
5715 char *s;
5716 char ex[2];
5717
5718 /* The syntax is
5719 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5720 */
5721
5722 SKIP_WHITESPACE ();
5723 varstart = input_line_pointer;
5724
5725 /* Look for the '='. */
5726 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5727 && *input_line_pointer != '=')
5728 ++input_line_pointer;
5729 if (*input_line_pointer != '=')
5730 {
5731 as_bad ("missing =");
5732 ignore_rest_of_line ();
5733 return;
5734 }
5735
5736 varstop = input_line_pointer;
5737 if (varstop > varstart
5738 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5739 --varstop;
5740
5741 ++input_line_pointer;
5742
5743 initstart = input_line_pointer;
5744
5745 /* Look for TO or DOWNTO. */
5746 up = 1;
5747 initstop = NULL;
5748 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5749 {
5750 if (strncasecmp (input_line_pointer, "TO", 2) == 0
5751 && ! is_part_of_name (input_line_pointer[2]))
5752 {
5753 initstop = input_line_pointer;
5754 input_line_pointer += 2;
5755 break;
5756 }
5757 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
5758 && ! is_part_of_name (input_line_pointer[6]))
5759 {
5760 initstop = input_line_pointer;
5761 up = 0;
5762 input_line_pointer += 6;
5763 break;
5764 }
5765 ++input_line_pointer;
5766 }
5767 if (initstop == NULL)
5768 {
5769 as_bad ("missing to or downto");
5770 ignore_rest_of_line ();
5771 return;
5772 }
5773 if (initstop > initstart
5774 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
5775 --initstop;
5776
5777 SKIP_WHITESPACE ();
5778 endstart = input_line_pointer;
5779
5780 /* Look for BY or DO. */
5781 by = 0;
5782 endstop = NULL;
5783 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5784 {
5785 if (strncasecmp (input_line_pointer, "BY", 2) == 0
5786 && ! is_part_of_name (input_line_pointer[2]))
5787 {
5788 endstop = input_line_pointer;
5789 by = 1;
5790 input_line_pointer += 2;
5791 break;
5792 }
5793 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5794 && (input_line_pointer[2] == '.'
5795 || ! is_part_of_name (input_line_pointer[2])))
5796 {
5797 endstop = input_line_pointer;
5798 input_line_pointer += 2;
5799 break;
5800 }
5801 ++input_line_pointer;
5802 }
5803 if (endstop == NULL)
5804 {
5805 as_bad ("missing do");
5806 ignore_rest_of_line ();
5807 return;
5808 }
5809 if (endstop > endstart
5810 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
5811 --endstop;
5812
5813 if (! by)
5814 {
5815 bystart = "#1";
5816 bystop = bystart + 2;
5817 }
5818 else
5819 {
5820 SKIP_WHITESPACE ();
5821 bystart = input_line_pointer;
5822
5823 /* Look for DO. */
5824 bystop = NULL;
5825 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5826 {
5827 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5828 && (input_line_pointer[2] == '.'
5829 || ! is_part_of_name (input_line_pointer[2])))
5830 {
5831 bystop = input_line_pointer;
5832 input_line_pointer += 2;
5833 break;
5834 }
5835 ++input_line_pointer;
5836 }
5837 if (bystop == NULL)
5838 {
5839 as_bad ("missing do");
5840 ignore_rest_of_line ();
5841 return;
5842 }
5843 if (bystop > bystart
5844 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
5845 --bystop;
5846 }
5847
5848 if (*input_line_pointer != '.')
5849 extent = '\0';
5850 else
5851 {
5852 extent = input_line_pointer[1];
5853 input_line_pointer += 2;
5854 }
5855
5856 /* We have fully parsed the FOR operands. Now build the loop. */
5857
5858 n = push_mri_control (mri_for);
5859
5860 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
5861
5862 /* move init,var */
5863 s = buf;
5864 *s++ = 'm';
5865 *s++ = 'o';
5866 *s++ = 'v';
5867 *s++ = 'e';
5868 if (qual != '\0')
5869 *s++ = qual;
5870 *s++ = ' ';
5871 memcpy (s, initstart, initstop - initstart);
5872 s += initstop - initstart;
5873 *s++ = ',';
5874 memcpy (s, varstart, varstop - varstart);
5875 s += varstop - varstart;
5876 *s = '\0';
5877 md_assemble (buf);
5878
5879 colon (n->top);
5880
5881 /* cmp end,var */
5882 s = buf;
5883 *s++ = 'c';
5884 *s++ = 'm';
5885 *s++ = 'p';
5886 if (qual != '\0')
5887 *s++ = qual;
5888 *s++ = ' ';
5889 memcpy (s, endstart, endstop - endstart);
5890 s += endstop - endstart;
5891 *s++ = ',';
5892 memcpy (s, varstart, varstop - varstart);
5893 s += varstop - varstart;
5894 *s = '\0';
5895 md_assemble (buf);
5896
5897 /* bcc bottom */
5898 ex[0] = extent;
5899 ex[1] = '\0';
5900 if (up)
5901 sprintf (buf, "blt%s %s", ex, n->bottom);
5902 else
5903 sprintf (buf, "bgt%s %s", ex, n->bottom);
5904 md_assemble (buf);
5905
5906 /* Put together the add or sub instruction used by ENDF. */
5907 s = buf;
5908 if (up)
5909 strcpy (s, "add");
5910 else
5911 strcpy (s, "sub");
5912 s += 3;
5913 if (qual != '\0')
5914 *s++ = qual;
5915 *s++ = ' ';
5916 memcpy (s, bystart, bystop - bystart);
5917 s += bystop - bystart;
5918 *s++ = ',';
5919 memcpy (s, varstart, varstop - varstart);
5920 s += varstop - varstart;
5921 *s = '\0';
5922 n->incr = buf;
5923
5924 if (flag_mri)
5925 {
5926 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5927 ++input_line_pointer;
5928 }
5929
5930 demand_empty_rest_of_line ();
5931 }
5932
5933 /* Handle the MRI ENDF pseudo-op. */
5934
5935 static void
5936 s_mri_endf (ignore)
5937 int ignore;
5938 {
5939 if (mri_control_stack == NULL
5940 || mri_control_stack->type != mri_for)
5941 {
5942 as_bad ("endf without for");
5943 ignore_rest_of_line ();
5944 return;
5945 }
5946
5947 colon (mri_control_stack->next);
5948
5949 md_assemble (mri_control_stack->incr);
5950
5951 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
5952 md_assemble (mri_control_stack->incr);
5953
5954 free (mri_control_stack->incr);
5955
5956 colon (mri_control_stack->bottom);
5957
5958 pop_mri_control ();
5959
5960 if (flag_mri)
5961 {
5962 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5963 ++input_line_pointer;
5964 }
5965
5966 demand_empty_rest_of_line ();
5967 }
5968
5969 /* Handle the MRI REPEAT pseudo-op. */
5970
5971 static void
5972 s_mri_repeat (ignore)
5973 int ignore;
5974 {
5975 struct mri_control_info *n;
5976
5977 n = push_mri_control (mri_repeat);
5978 colon (n->top);
5979 if (flag_mri)
5980 {
5981 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5982 ++input_line_pointer;
5983 }
5984 demand_empty_rest_of_line ();
5985 }
5986
5987 /* Handle the MRI UNTIL pseudo-op. */
5988
5989 static void
5990 s_mri_until (qual)
5991 int qual;
5992 {
5993 char *s;
5994
5995 if (mri_control_stack == NULL
5996 || mri_control_stack->type != mri_repeat)
5997 {
5998 as_bad ("until without repeat");
5999 ignore_rest_of_line ();
6000 return;
6001 }
6002
6003 colon (mri_control_stack->next);
6004
6005 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6006 ;
6007
6008 parse_mri_control_expression (s, qual, (const char *) NULL,
6009 mri_control_stack->top, '\0');
6010
6011 colon (mri_control_stack->bottom);
6012
6013 input_line_pointer = s;
6014
6015 pop_mri_control ();
6016
6017 if (flag_mri)
6018 {
6019 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6020 ++input_line_pointer;
6021 }
6022
6023 demand_empty_rest_of_line ();
6024 }
6025
6026 /* Handle the MRI WHILE pseudo-op. */
6027
6028 static void
6029 s_mri_while (qual)
6030 int qual;
6031 {
6032 char *s;
6033
6034 struct mri_control_info *n;
6035
6036 s = input_line_pointer;
6037 while (! is_end_of_line[(unsigned char) *s]
6038 && (! flag_mri || *s != '*'))
6039 s++;
6040 --s;
6041 while (*s == ' ' || *s == '\t')
6042 --s;
6043 if (s - input_line_pointer > 1
6044 && s[-1] == '.')
6045 s -= 2;
6046 if (s - input_line_pointer < 2
6047 || strncasecmp (s - 1, "DO", 2) != 0)
6048 {
6049 as_bad ("missing do");
6050 ignore_rest_of_line ();
6051 return;
6052 }
6053
6054 n = push_mri_control (mri_while);
6055
6056 colon (n->next);
6057
6058 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6059 s[1] == '.' ? s[2] : '\0');
6060
6061 input_line_pointer = s + 1;
6062 if (*input_line_pointer == '.')
6063 input_line_pointer += 2;
6064
6065 if (flag_mri)
6066 {
6067 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6068 ++input_line_pointer;
6069 }
6070
6071 demand_empty_rest_of_line ();
6072 }
6073
6074 /* Handle the MRI ENDW pseudo-op. */
6075
6076 static void
6077 s_mri_endw (ignore)
6078 int ignore;
6079 {
6080 char *buf;
6081
6082 if (mri_control_stack == NULL
6083 || mri_control_stack->type != mri_while)
6084 {
6085 as_bad ("endw without while");
6086 ignore_rest_of_line ();
6087 return;
6088 }
6089
6090 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6091 sprintf (buf, "bra %s", mri_control_stack->next);
6092 md_assemble (buf);
6093 free (buf);
6094
6095 colon (mri_control_stack->bottom);
6096
6097 pop_mri_control ();
6098
6099 if (flag_mri)
6100 {
6101 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6102 ++input_line_pointer;
6103 }
6104
6105 demand_empty_rest_of_line ();
6106 }
6107 \f
6108 /*
6109 * md_parse_option
6110 * Invocation line includes a switch not recognized by the base assembler.
6111 * See if it's a processor-specific option. These are:
6112 *
6113 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6114 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6115 * Select the architecture. Instructions or features not
6116 * supported by the selected architecture cause fatal
6117 * errors. More than one may be specified. The default is
6118 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6119 * for -m68000, and -m68882 is a synonym for -m68881.
6120 * -[A]m[c]no-68851, -[A]m[c]no-68881
6121 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6122 * so don't use or document it, but that's the way the parsing
6123 * works).
6124 *
6125 * -pic Indicates PIC.
6126 * -k Indicates PIC. (Sun 3 only.)
6127 *
6128 */
6129
6130 #ifdef OBJ_ELF
6131 CONST char *md_shortopts = "lSA:m:kQ:V";
6132 #else
6133 CONST char *md_shortopts = "lSA:m:k";
6134 #endif
6135
6136 struct option md_longopts[] = {
6137 #define OPTION_PIC (OPTION_MD_BASE)
6138 {"pic", no_argument, NULL, OPTION_PIC},
6139 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6140 {"register-prefix-optional", no_argument, NULL,
6141 OPTION_REGISTER_PREFIX_OPTIONAL},
6142 {NULL, no_argument, NULL, 0}
6143 };
6144 size_t md_longopts_size = sizeof(md_longopts);
6145
6146 int
6147 md_parse_option (c, arg)
6148 int c;
6149 char *arg;
6150 {
6151 switch (c)
6152 {
6153 case 'l': /* -l means keep external to 2 bit offset
6154 rather than 16 bit one */
6155 flag_short_refs = 1;
6156 break;
6157
6158 case 'S': /* -S means that jbsr's always turn into
6159 jsr's. */
6160 flag_long_jumps = 1;
6161 break;
6162
6163 case 'A':
6164 if (*arg == 'm')
6165 arg++;
6166 /* intentional fall-through */
6167 case 'm':
6168
6169 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6170 {
6171 int i;
6172 unsigned long arch;
6173 const char *oarg = arg;
6174
6175 arg += 3;
6176 if (*arg == 'm')
6177 {
6178 arg++;
6179 if (arg[0] == 'c' && arg[1] == '6')
6180 arg++;
6181 }
6182 for (i = 0; i < n_archs; i++)
6183 if (!strcmp (arg, archs[i].name))
6184 break;
6185 if (i == n_archs)
6186 {
6187 unknown:
6188 as_bad ("unrecognized option `%s'", oarg);
6189 return 0;
6190 }
6191 arch = archs[i].arch;
6192 if (arch == m68881)
6193 no_68881 = 1;
6194 else if (arch == m68851)
6195 no_68851 = 1;
6196 else
6197 goto unknown;
6198 }
6199 else
6200 {
6201 int i;
6202
6203 if (arg[0] == 'c' && arg[1] == '6')
6204 arg++;
6205
6206 for (i = 0; i < n_archs; i++)
6207 if (!strcmp (arg, archs[i].name))
6208 {
6209 unsigned long arch = archs[i].arch;
6210 if (cpu_of_arch (arch))
6211 /* It's a cpu spec. */
6212 {
6213 current_architecture &= ~m68000up;
6214 current_architecture |= arch;
6215 }
6216 else if (arch == m68881)
6217 {
6218 current_architecture |= m68881;
6219 no_68881 = 0;
6220 }
6221 else if (arch == m68851)
6222 {
6223 current_architecture |= m68851;
6224 no_68851 = 0;
6225 }
6226 else
6227 /* ??? */
6228 abort ();
6229 break;
6230 }
6231 if (i == n_archs)
6232 {
6233 as_bad ("unrecognized architecture specification `%s'", arg);
6234 return 0;
6235 }
6236 }
6237 break;
6238
6239 case OPTION_PIC:
6240 case 'k':
6241 flag_want_pic = 1;
6242 break; /* -pic, Position Independent Code */
6243
6244 case OPTION_REGISTER_PREFIX_OPTIONAL:
6245 flag_reg_prefix_optional = 1;
6246 reg_prefix_optional_seen = 1;
6247 break;
6248
6249 /* -V: SVR4 argument to print version ID. */
6250 case 'V':
6251 print_version_id ();
6252 break;
6253
6254 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6255 should be emitted or not. FIXME: Not implemented. */
6256 case 'Q':
6257 break;
6258
6259 default:
6260 return 0;
6261 }
6262
6263 return 1;
6264 }
6265
6266 void
6267 md_show_usage (stream)
6268 FILE *stream;
6269 {
6270 fprintf(stream, "\
6271 680X0 options:\n\
6272 -l use 1 word for refs to undefined symbols [default 2]\n\
6273 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6274 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6275 | -mcpu32\n\
6276 specify variant of 680X0 architecture [default 68020]\n\
6277 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6278 target has/lacks floating-point coprocessor\n\
6279 [default yes for 68020, 68030, and cpu32]\n");
6280 fprintf(stream, "\
6281 -m68851 | -mno-68851\n\
6282 target has/lacks memory-management unit coprocessor\n\
6283 [default yes for 68020 and up]\n\
6284 -pic, -k generate position independent code\n\
6285 -S turn jbsr into jsr\n\
6286 --register-prefix-optional\n\
6287 recognize register names without prefix character\n");
6288 }
6289 \f
6290 #ifdef TEST2
6291
6292 /* TEST2: Test md_assemble() */
6293 /* Warning, this routine probably doesn't work anymore */
6294
6295 main ()
6296 {
6297 struct m68k_it the_ins;
6298 char buf[120];
6299 char *cp;
6300 int n;
6301
6302 m68k_ip_begin ();
6303 for (;;)
6304 {
6305 if (!gets (buf) || !*buf)
6306 break;
6307 if (buf[0] == '|' || buf[1] == '.')
6308 continue;
6309 for (cp = buf; *cp; cp++)
6310 if (*cp == '\t')
6311 *cp = ' ';
6312 if (is_label (buf))
6313 continue;
6314 memset (&the_ins, '\0', sizeof (the_ins));
6315 m68k_ip (&the_ins, buf);
6316 if (the_ins.error)
6317 {
6318 printf ("Error %s in %s\n", the_ins.error, buf);
6319 }
6320 else
6321 {
6322 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6323 for (n = 0; n < the_ins.numo; n++)
6324 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6325 printf (" ");
6326 print_the_insn (&the_ins.opcode[0], stdout);
6327 (void) putchar ('\n');
6328 }
6329 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6330 {
6331 if (the_ins.operands[n].error)
6332 {
6333 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6334 continue;
6335 }
6336 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6337 if (the_ins.operands[n].b_const)
6338 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6339 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6340 if (the_ins.operands[n].b_iadd)
6341 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6342 (void) putchar ('\n');
6343 }
6344 }
6345 m68k_ip_end ();
6346 return 0;
6347 }
6348
6349 is_label (str)
6350 char *str;
6351 {
6352 while (*str == ' ')
6353 str++;
6354 while (*str && *str != ' ')
6355 str++;
6356 if (str[-1] == ':' || str[1] == '=')
6357 return 1;
6358 return 0;
6359 }
6360
6361 #endif
6362
6363 /* Possible states for relaxation:
6364
6365 0 0 branch offset byte (bra, etc)
6366 0 1 word
6367 0 2 long
6368
6369 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6370 1 1 word
6371 1 2 long
6372
6373 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6374 2 1 word-long
6375 2 2 long-word
6376 2 3 long-long
6377
6378 */
6379
6380 /* We have no need to default values of symbols. */
6381
6382 /* ARGSUSED */
6383 symbolS *
6384 md_undefined_symbol (name)
6385 char *name;
6386 {
6387 return 0;
6388 }
6389
6390 /* Round up a section size to the appropriate boundary. */
6391 valueT
6392 md_section_align (segment, size)
6393 segT segment;
6394 valueT size;
6395 {
6396 return size; /* Byte alignment is fine */
6397 }
6398
6399 /* Exactly what point is a PC-relative offset relative TO?
6400 On the 68k, it is relative to the address of the first extension
6401 word. The difference between the addresses of the offset and the
6402 first extension word is stored in fx_pcrel_adjust. */
6403 long
6404 md_pcrel_from (fixP)
6405 fixS *fixP;
6406 {
6407 int adjust;
6408
6409 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6410 -1 as 64. */
6411 adjust = fixP->fx_pcrel_adjust;
6412 if (adjust == 64)
6413 adjust = -1;
6414 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6415 }
6416
6417 #ifndef BFD_ASSEMBLER
6418 /*ARGSUSED*/
6419 void
6420 tc_coff_symbol_emit_hook (ignore)
6421 symbolS *ignore;
6422 {
6423 }
6424
6425 int
6426 tc_coff_sizemachdep (frag)
6427 fragS *frag;
6428 {
6429 switch (frag->fr_subtype & 0x3)
6430 {
6431 case BYTE:
6432 return 1;
6433 case SHORT:
6434 return 2;
6435 case LONG:
6436 return 4;
6437 default:
6438 abort ();
6439 return 0;
6440 }
6441 }
6442 #endif
6443
6444 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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