projects / deliverable / binutils-gdb.git / blob
? search:


199fec5f96835ee9966bd2f38a229a47fb987fb8
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 /* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40 #if defined (TE_SVR4) || defined (TE_DELTA)
41 const char *m68k_comment_chars = "|#";
42 #else
43 const char *m68k_comment_chars = "|";
44 #endif
45
46 /* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49 /* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52 /* Also note that comments like this one will always work. */
53 const char line_comment_chars[] = "#*";
54
55 const char line_separator_chars[] = ";";
56
57 /* Chars that can be used to separate mant from exp in floating point nums. */
58 const char EXP_CHARS[] = "eE";
59
60 /* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
62
63 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
64
65 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
68
69 const int md_reloc_size = 8; /* Size of relocation record. */
70
71 /* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
73 references. Not implemented. For ELF there are other means
74 to denote pic relocations. */
75 int flag_want_pic;
76
77 static int flag_short_refs; /* -l option. */
78 static int flag_long_jumps; /* -S option. */
79 static int flag_keep_pcrel; /* --pcrel option. */
80
81 #ifdef REGISTER_PREFIX_OPTIONAL
82 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
83 #else
84 int flag_reg_prefix_optional;
85 #endif
86
87 /* Whether --register-prefix-optional was used on the command line. */
88 static int reg_prefix_optional_seen;
89
90 /* The floating point coprocessor to use by default. */
91 static enum m68k_register m68k_float_copnum = COP1;
92
93 /* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95 static int m68k_abspcadd;
96
97 /* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99 static int m68k_quick = 1;
100
101 /* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
103 be 32 bits. */
104 static int m68k_rel32 = 1;
105
106 /* This is non-zero if m68k_rel32 was set from the command line. */
107 static int m68k_rel32_from_cmdline;
108
109 /* The default width to use for an index register when using a base
110 displacement. */
111 static enum m68k_size m68k_index_width_default = SIZE_LONG;
112
113 /* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
115 label. */
116 struct label_line
117 {
118 struct label_line *next;
119 symbolS *label;
120 char *file;
121 unsigned int line;
122 int text;
123 };
124
125 /* The list of labels. */
126
127 static struct label_line *labels;
128
129 /* The current label. */
130
131 static struct label_line *current_label;
132
133 /* Pointer to list holding the opcodes sorted by name. */
134 static struct m68k_opcode const ** m68k_sorted_opcodes;
135
136 /* Its an arbitrary name: This means I don't approve of it.
137 See flames below. */
138 static struct obstack robyn;
139
140 struct m68k_incant
141 {
142 const char *m_operands;
143 unsigned long m_opcode;
144 short m_opnum;
145 short m_codenum;
146 int m_arch;
147 struct m68k_incant *m_next;
148 };
149
150 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
151 #define gettwo(x) (((x)->m_opcode)&0xffff)
152
153 static const enum m68k_register m68000_control_regs[] = { 0 };
154 static const enum m68k_register m68010_control_regs[] = {
155 SFC, DFC, USP, VBR,
156 0
157 };
158 static const enum m68k_register m68020_control_regs[] = {
159 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
160 0
161 };
162 static const enum m68k_register m68040_control_regs[] = {
163 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
164 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
165 0
166 };
167 static const enum m68k_register m68060_control_regs[] = {
168 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
169 USP, VBR, URP, SRP, PCR,
170 0
171 };
172 static const enum m68k_register mcf_control_regs[] = {
173 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
174 RAMBAR0, RAMBAR1, MBAR,
175 0
176 };
177 static const enum m68k_register mcf528x_control_regs[] = {
178 CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
179 0
180 };
181 static const enum m68k_register mcfv4e_control_regs[] = {
182 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
183 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
184 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
185 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
186 0
187 };
188 #define cpu32_control_regs m68010_control_regs
189
190 static const enum m68k_register *control_regs;
191
192 /* Internal form of a 68020 instruction. */
193 struct m68k_it
194 {
195 const char *error;
196 const char *args; /* List of opcode info. */
197 int numargs;
198
199 int numo; /* Number of shorts in opcode. */
200 short opcode[11];
201
202 struct m68k_op operands[6];
203
204 int nexp; /* Number of exprs in use. */
205 struct m68k_exp exprs[4];
206
207 int nfrag; /* Number of frags we have to produce. */
208 struct
209 {
210 int fragoff; /* Where in the current opcode the frag ends. */
211 symbolS *fadd;
212 offsetT foff;
213 int fragty;
214 }
215 fragb[4];
216
217 int nrel; /* Num of reloc strucs in use. */
218 struct
219 {
220 int n;
221 expressionS exp;
222 char wid;
223 char pcrel;
224 /* In a pc relative address the difference between the address
225 of the offset and the address that the offset is relative
226 to. This depends on the addressing mode. Basically this
227 is the value to put in the offset field to address the
228 first byte of the offset, without regarding the special
229 significance of some values (in the branch instruction, for
230 example). */
231 int pcrel_fix;
232 #ifdef OBJ_ELF
233 /* Whether this expression needs special pic relocation, and if
234 so, which. */
235 enum pic_relocation pic_reloc;
236 #endif
237 }
238 reloc[5]; /* Five is enough??? */
239 };
240
241 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
242 #define float_of_arch(x) ((x) & mfloat)
243 #define mmu_of_arch(x) ((x) & mmmu)
244 #define arch_coldfire_p(x) ((x) & mcfisa_a)
245 #define arch_coldfire_fpu(x) ((x) & cfloat)
246
247 /* Macros for determining if cpu supports a specific addressing mode. */
248 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
249
250 static struct m68k_it the_ins; /* The instruction being assembled. */
251
252 #define op(ex) ((ex)->exp.X_op)
253 #define adds(ex) ((ex)->exp.X_add_symbol)
254 #define subs(ex) ((ex)->exp.X_op_symbol)
255 #define offs(ex) ((ex)->exp.X_add_number)
256
257 /* Macros for adding things to the m68k_it struct. */
258 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
259
260 /* Static functions. */
261 static void insop PARAMS ((int, const struct m68k_incant *));
262 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
263 static void add_frag PARAMS ((symbolS *, offsetT, int));
264
265 /* Like addword, but goes BEFORE general operands. */
266
267 static void
268 insop (w, opcode)
269 int w;
270 const struct m68k_incant *opcode;
271 {
272 int z;
273 for (z = the_ins.numo; z > opcode->m_codenum; --z)
274 the_ins.opcode[z] = the_ins.opcode[z - 1];
275 for (z = 0; z < the_ins.nrel; z++)
276 the_ins.reloc[z].n += 2;
277 for (z = 0; z < the_ins.nfrag; z++)
278 the_ins.fragb[z].fragoff++;
279 the_ins.opcode[opcode->m_codenum] = w;
280 the_ins.numo++;
281 }
282
283 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
284 Blecch. */
285 static void
286 add_fix (width, exp, pc_rel, pc_fix)
287 int width;
288 struct m68k_exp *exp;
289 int pc_rel;
290 int pc_fix;
291 {
292 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
293 ? (the_ins.numo*2-1)
294 : (((width)=='b')
295 ? (the_ins.numo*2+1)
296 : (the_ins.numo*2)));
297 the_ins.reloc[the_ins.nrel].exp = exp->exp;
298 the_ins.reloc[the_ins.nrel].wid = width;
299 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
300 #ifdef OBJ_ELF
301 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
302 #endif
303 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
304 }
305
306 /* Cause an extra frag to be generated here, inserting up to 10 bytes
307 (that value is chosen in the frag_var call in md_assemble). TYPE
308 is the subtype of the frag to be generated; its primary type is
309 rs_machine_dependent.
310
311 The TYPE parameter is also used by md_convert_frag_1 and
312 md_estimate_size_before_relax. The appropriate type of fixup will
313 be emitted by md_convert_frag_1.
314
315 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
316 static void
317 add_frag (add, off, type)
318 symbolS *add;
319 offsetT off;
320 int type;
321 {
322 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
323 the_ins.fragb[the_ins.nfrag].fadd = add;
324 the_ins.fragb[the_ins.nfrag].foff = off;
325 the_ins.fragb[the_ins.nfrag++].fragty = type;
326 }
327
328 #define isvar(ex) \
329 (op (ex) != O_constant && op (ex) != O_big)
330
331 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
332 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
333 static void m68k_ip PARAMS ((char *));
334 static void insert_reg PARAMS ((const char *, int));
335 static void select_control_regs PARAMS ((void));
336 static void init_regtable PARAMS ((void));
337 static int reverse_16_bits PARAMS ((int in));
338 static int reverse_8_bits PARAMS ((int in));
339 static void install_gen_operand PARAMS ((int mode, int val));
340 static void install_operand PARAMS ((int mode, int val));
341 static void s_bss PARAMS ((int));
342 static void s_data1 PARAMS ((int));
343 static void s_data2 PARAMS ((int));
344 static void s_even PARAMS ((int));
345 static void s_proc PARAMS ((int));
346 static void mri_chip PARAMS ((void));
347 static void s_chip PARAMS ((int));
348 static void s_fopt PARAMS ((int));
349 static void s_opt PARAMS ((int));
350 static void s_reg PARAMS ((int));
351 static void s_restore PARAMS ((int));
352 static void s_save PARAMS ((int));
353 static void s_mri_if PARAMS ((int));
354 static void s_mri_else PARAMS ((int));
355 static void s_mri_endi PARAMS ((int));
356 static void s_mri_break PARAMS ((int));
357 static void s_mri_next PARAMS ((int));
358 static void s_mri_for PARAMS ((int));
359 static void s_mri_endf PARAMS ((int));
360 static void s_mri_repeat PARAMS ((int));
361 static void s_mri_until PARAMS ((int));
362 static void s_mri_while PARAMS ((int));
363 static void s_mri_endw PARAMS ((int));
364 static void md_convert_frag_1 PARAMS ((fragS *));
365
366 static int current_architecture;
367 static int current_chip;
368
369 struct m68k_cpu
370 {
371 unsigned long arch;
372 unsigned long chip;
373 const char *name;
374 int alias;
375 };
376
377 static const struct m68k_cpu archs[] =
378 {
379 { m68000, m68000, "68000", 0 },
380 { m68010, m68010, "68010", 0 },
381 { m68020, m68020, "68020", 0 },
382 { m68030, m68030, "68030", 0 },
383 { m68040, m68040, "68040", 0 },
384 { m68060, m68060, "68060", 0 },
385 { cpu32, cpu32, "cpu32", 0 },
386 { m68881, m68881, "68881", 0 },
387 { m68851, m68851, "68851", 0 },
388 { mcfisa_a, mcf5200, "5200", 0 },
389 { mcfisa_a|mcfhwdiv|mcfmac, mcf5206e, "5206e", 0 },
390 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf521x, "521x", 0 },
391 { mcfisa_a|mcfhwdiv|mcfemac, mcf5249, "5249", 0 },
392 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf528x, "528x", 0 },
393 { mcfisa_a|mcfhwdiv|mcfmac, mcf5307, "5307", 0 },
394 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "5407", 0 },
395 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "547x", 0 },
396 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5480, "548x", 0 },
397 /* Aliases (effectively, so far as gas is concerned) for the above
398 cpus. */
399 { m68020, m68020, "68k", 1 },
400 { m68000, m68000, "68008", 1 },
401 { m68000, m68000, "68302", 1 },
402 { m68000, m68000, "68306", 1 },
403 { m68000, m68000, "68307", 1 },
404 { m68000, m68000, "68322", 1 },
405 { m68000, m68000, "68356", 1 },
406 { m68000, m68000, "68ec000", 1 },
407 { m68000, m68000, "68hc000", 1 },
408 { m68000, m68000, "68hc001", 1 },
409 { m68020, m68020, "68ec020", 1 },
410 { m68030, m68030, "68ec030", 1 },
411 { m68040, m68040, "68ec040", 1 },
412 { m68060, m68060, "68ec060", 1 },
413 { cpu32, cpu32, "68330", 1 },
414 { cpu32, cpu32, "68331", 1 },
415 { cpu32, cpu32, "68332", 1 },
416 { cpu32, cpu32, "68333", 1 },
417 { cpu32, cpu32, "68334", 1 },
418 { cpu32, cpu32, "68336", 1 },
419 { cpu32, cpu32, "68340", 1 },
420 { cpu32, cpu32, "68341", 1 },
421 { cpu32, cpu32, "68349", 1 },
422 { cpu32, cpu32, "68360", 1 },
423 { m68881, m68881, "68882", 1 },
424 { mcfisa_a, mcf5200, "5202", 1 },
425 { mcfisa_a, mcf5200, "5204", 1 },
426 { mcfisa_a, mcf5200, "5206", 1 },
427 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5214", 1 },
428 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5216", 1 },
429 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5280", 1 },
430 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5281", 1 },
431 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5282", 1 },
432 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "cfv4", 1 },
433 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5470", 1 },
434 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5471", 1 },
435 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5472", 1 },
436 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5473", 1 },
437 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5474", 1 },
438 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5475", 1 },
439 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5480", 1 },
440 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5481", 1 },
441 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5482", 1 },
442 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5483", 1 },
443 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5484", 1 },
444 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5485", 1 },
445 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "cfv4e", 1 },
446 };
447
448 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
449
450 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
451 architecture and we have a lot of relaxation modes. */
452
453 /* Macros used in the relaxation code. */
454 #define TAB(x,y) (((x) << 2) + (y))
455 #define TABTYPE(x) ((x) >> 2)
456
457 /* Relaxation states. */
458 #define BYTE 0
459 #define SHORT 1
460 #define LONG 2
461 #define SZ_UNDEF 3
462
463 /* Here are all the relaxation modes we support. First we can relax ordinary
464 branches. On 68020 and higher and on CPU32 all branch instructions take
465 three forms, so on these CPUs all branches always remain as such. When we
466 have to expand to the LONG form on a 68000, though, we substitute an
467 absolute jump instead. This is a direct replacement for unconditional
468 branches and a branch over a jump for conditional branches. However, if the
469 user requires PIC and disables this with --pcrel, we can only relax between
470 BYTE and SHORT forms, punting if that isn't enough. This gives us four
471 different relaxation modes for branches: */
472
473 #define BRANCHBWL 0 /* Branch byte, word, or long. */
474 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
475 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
476 #define BRANCHBW 3 /* Branch byte or word. */
477
478 /* We also relax coprocessor branches and DBcc's. All CPUs that support
479 coprocessor branches support them in word and long forms, so we have only
480 one relaxation mode for them. DBcc's are word only on all CPUs. We can
481 relax them to the LONG form with a branch-around sequence. This sequence
482 can use a long branch (if available) or an absolute jump (if acceptable).
483 This gives us two relaxation modes. If long branches are not available and
484 absolute jumps are not acceptable, we don't relax DBcc's. */
485
486 #define FBRANCH 4 /* Coprocessor branch. */
487 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
488 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
489
490 /* That's all for instruction relaxation. However, we also relax PC-relative
491 operands. Specifically, we have three operand relaxation modes. On the
492 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
493 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
494 two. Also PC+displacement+index operands in their simple form (with a non-
495 suppressed index without memory indirection) are supported on all CPUs, but
496 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
497 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
498 form of the PC+displacement+index operand. Finally, some absolute operands
499 can be relaxed down to 16-bit PC-relative. */
500
501 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
502 #define PCINDEX 8 /* PC + displacement + index. */
503 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
504
505 /* Note that calls to frag_var need to specify the maximum expansion
506 needed; this is currently 10 bytes for DBCC. */
507
508 /* The fields are:
509 How far Forward this mode will reach:
510 How far Backward this mode will reach:
511 How many bytes this mode will add to the size of the frag
512 Which mode to go to if the offset won't fit in this one
513
514 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
515 relax_typeS md_relax_table[] =
516 {
517 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
518 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
519 { 0, 0, 4, 0 },
520 { 1, 1, 0, 0 },
521
522 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
523 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
524 { 0, 0, 4, 0 },
525 { 1, 1, 0, 0 },
526
527 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
528 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
529 { 0, 0, 6, 0 },
530 { 1, 1, 0, 0 },
531
532 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
533 { 0, 0, 2, 0 },
534 { 1, 1, 0, 0 },
535 { 1, 1, 0, 0 },
536
537 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
538 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
539 { 0, 0, 4, 0 },
540 { 1, 1, 0, 0 },
541
542 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
543 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
544 { 0, 0, 10, 0 },
545 { 1, 1, 0, 0 },
546
547 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
548 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
549 { 0, 0, 10, 0 },
550 { 1, 1, 0, 0 },
551
552 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
553 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
554 { 0, 0, 6, 0 },
555 { 1, 1, 0, 0 },
556
557 { 125, -130, 0, TAB (PCINDEX, SHORT) },
558 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
559 { 0, 0, 4, 0 },
560 { 1, 1, 0, 0 },
561
562 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
563 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
564 { 0, 0, 4, 0 },
565 { 1, 1, 0, 0 },
566 };
567
568 /* These are the machine dependent pseudo-ops. These are included so
569 the assembler can work on the output from the SUN C compiler, which
570 generates these. */
571
572 /* This table describes all the machine specific pseudo-ops the assembler
573 has to support. The fields are:
574 pseudo-op name without dot
575 function to call to execute this pseudo-op
576 Integer arg to pass to the function. */
577 const pseudo_typeS md_pseudo_table[] =
578 {
579 {"data1", s_data1, 0},
580 {"data2", s_data2, 0},
581 {"bss", s_bss, 0},
582 {"even", s_even, 0},
583 {"skip", s_space, 0},
584 {"proc", s_proc, 0},
585 #if defined (TE_SUN3) || defined (OBJ_ELF)
586 {"align", s_align_bytes, 0},
587 #endif
588 #ifdef OBJ_ELF
589 {"swbeg", s_ignore, 0},
590 #endif
591 {"extend", float_cons, 'x'},
592 {"ldouble", float_cons, 'x'},
593
594 /* The following pseudo-ops are supported for MRI compatibility. */
595 {"chip", s_chip, 0},
596 {"comline", s_space, 1},
597 {"fopt", s_fopt, 0},
598 {"mask2", s_ignore, 0},
599 {"opt", s_opt, 0},
600 {"reg", s_reg, 0},
601 {"restore", s_restore, 0},
602 {"save", s_save, 0},
603
604 {"if", s_mri_if, 0},
605 {"if.b", s_mri_if, 'b'},
606 {"if.w", s_mri_if, 'w'},
607 {"if.l", s_mri_if, 'l'},
608 {"else", s_mri_else, 0},
609 {"else.s", s_mri_else, 's'},
610 {"else.l", s_mri_else, 'l'},
611 {"endi", s_mri_endi, 0},
612 {"break", s_mri_break, 0},
613 {"break.s", s_mri_break, 's'},
614 {"break.l", s_mri_break, 'l'},
615 {"next", s_mri_next, 0},
616 {"next.s", s_mri_next, 's'},
617 {"next.l", s_mri_next, 'l'},
618 {"for", s_mri_for, 0},
619 {"for.b", s_mri_for, 'b'},
620 {"for.w", s_mri_for, 'w'},
621 {"for.l", s_mri_for, 'l'},
622 {"endf", s_mri_endf, 0},
623 {"repeat", s_mri_repeat, 0},
624 {"until", s_mri_until, 0},
625 {"until.b", s_mri_until, 'b'},
626 {"until.w", s_mri_until, 'w'},
627 {"until.l", s_mri_until, 'l'},
628 {"while", s_mri_while, 0},
629 {"while.b", s_mri_while, 'b'},
630 {"while.w", s_mri_while, 'w'},
631 {"while.l", s_mri_while, 'l'},
632 {"endw", s_mri_endw, 0},
633
634 {0, 0, 0}
635 };
636
637 /* The mote pseudo ops are put into the opcode table, since they
638 don't start with a . they look like opcodes to gas.
639 */
640
641 #ifdef M68KCOFF
642 extern void obj_coff_section PARAMS ((int));
643 #endif
644
645 const pseudo_typeS mote_pseudo_table[] =
646 {
647
648 {"dcl", cons, 4},
649 {"dc", cons, 2},
650 {"dcw", cons, 2},
651 {"dcb", cons, 1},
652
653 {"dsl", s_space, 4},
654 {"ds", s_space, 2},
655 {"dsw", s_space, 2},
656 {"dsb", s_space, 1},
657
658 {"xdef", s_globl, 0},
659 #ifdef OBJ_ELF
660 {"align", s_align_bytes, 0},
661 #else
662 {"align", s_align_ptwo, 0},
663 #endif
664 #ifdef M68KCOFF
665 {"sect", obj_coff_section, 0},
666 {"section", obj_coff_section, 0},
667 #endif
668 {0, 0, 0}
669 };
670
671 #define issbyte(x) ((x)>=-128 && (x)<=127)
672 #define isubyte(x) ((x)>=0 && (x)<=255)
673 #define issword(x) ((x)>=-32768 && (x)<=32767)
674 #define isuword(x) ((x)>=0 && (x)<=65535)
675
676 #define isbyte(x) ((x)>= -255 && (x)<=255)
677 #define isword(x) ((x)>=-65536 && (x)<=65535)
678 #define islong(x) (1)
679
680 extern char *input_line_pointer;
681
682 static char notend_table[256];
683 static char alt_notend_table[256];
684 #define notend(s) \
685 (! (notend_table[(unsigned char) *s] \
686 || (*s == ':' \
687 && alt_notend_table[(unsigned char) s[1]])))
688
689 /* Return a human readable string holding the list of chips that are
690 valid for a particular architecture, suppressing aliases (unless
691 there is only one of them). */
692
693 static char *
694 find_cf_chip (int architecture)
695 {
696 static char buf[1024];
697 int i, j, n_chips, n_alias;
698 char *cp;
699
700 strcpy (buf, " (");
701 cp = buf + strlen (buf);
702
703 for (i = 0, n_chips = 0, n_alias = 0; i < n_archs; ++i)
704 if (archs[i].arch & architecture)
705 {
706 n_chips++;
707 if (archs[i].alias)
708 n_alias++;
709 }
710
711 if (n_chips == 0)
712 as_fatal (_("no matching ColdFire architectures found"));
713
714 if (n_alias > 1)
715 n_chips -= n_alias;
716
717 for (i = 0, j = 0; i < n_archs && j < n_chips; ++i)
718 if (archs[i].arch & architecture)
719 {
720 if (j)
721 {
722 if (((j == n_chips - 1) && !(n_alias > 1))|| ! n_alias)
723 {
724 if (n_chips == 2)
725 {
726 strncpy (cp, _(" or "), (sizeof (buf) - (cp - buf)));
727 cp += strlen (cp);
728 }
729 else
730 {
731 strncpy (cp, _(", or "), (sizeof (buf) - (cp - buf)));
732 cp += strlen (cp);
733 }
734 }
735 else
736 {
737 strncpy (cp, ", ", (sizeof (buf) - (cp - buf)));
738 cp += strlen (cp);
739 }
740 }
741 strncpy (cp, archs[i].name, (sizeof (buf) - (cp - buf)));
742 cp += strlen (cp);
743 j++;
744 }
745
746 if (n_alias > 1)
747 {
748 strncpy (cp, _(", or aliases"), (sizeof (buf) - (cp - buf)));
749 cp += strlen (cp);
750 }
751
752 strncpy (cp, ")", (sizeof (buf) - (cp - buf)));
753
754 return buf;
755 }
756
757 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
758
759 #ifdef NO_PCREL_RELOCS
760
761 int
762 make_pcrel_absolute (fixP, add_number)
763 fixS *fixP;
764 long *add_number;
765 {
766 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
767
768 /* Rewrite the PC relative instructions to absolute address ones.
769 these are rumored to be faster, and the apollo linker refuses
770 to deal with the PC relative relocations. */
771 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */
772 {
773 if (flag_keep_pcrel)
774 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
775 opcode[0] = 0x4e;
776 opcode[1] = 0xf9;
777 }
778 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */
779 {
780 if (flag_keep_pcrel)
781 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
782 opcode[0] = 0x4e;
783 opcode[1] = 0xb9;
784 }
785 else
786 as_fatal (_("Unknown PC relative instruction"));
787 *add_number -= 4;
788 return 0;
789 }
790
791 #endif /* NO_PCREL_RELOCS */
792
793 short
794 tc_coff_fix2rtype (fixP)
795 fixS *fixP;
796 {
797 if (fixP->fx_tcbit && fixP->fx_size == 4)
798 return R_RELLONG_NEG;
799 #ifdef NO_PCREL_RELOCS
800 know (fixP->fx_pcrel == 0);
801 return (fixP->fx_size == 1 ? R_RELBYTE
802 : fixP->fx_size == 2 ? R_DIR16
803 : R_DIR32);
804 #else
805 return (fixP->fx_pcrel ?
806 (fixP->fx_size == 1 ? R_PCRBYTE :
807 fixP->fx_size == 2 ? R_PCRWORD :
808 R_PCRLONG) :
809 (fixP->fx_size == 1 ? R_RELBYTE :
810 fixP->fx_size == 2 ? R_RELWORD :
811 R_RELLONG));
812 #endif
813 }
814
815 #endif
816
817 #ifdef OBJ_ELF
818
819 /* Return zero if the reference to SYMBOL from within the same segment may
820 be relaxed. */
821
822 /* On an ELF system, we can't relax an externally visible symbol,
823 because it may be overridden by a shared library. However, if
824 TARGET_OS is "elf", then we presume that we are assembling for an
825 embedded system, in which case we don't have to worry about shared
826 libraries, and we can relax any external sym. */
827
828 #define relaxable_symbol(symbol) \
829 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
830 || S_IS_WEAK (symbol)))
831
832 /* Compute the relocation code for a fixup of SIZE bytes, using pc
833 relative relocation if PCREL is non-zero. PIC says whether a special
834 pic relocation was requested. */
835
836 static bfd_reloc_code_real_type get_reloc_code
837 PARAMS ((int, int, enum pic_relocation));
838
839 static bfd_reloc_code_real_type
840 get_reloc_code (size, pcrel, pic)
841 int size;
842 int pcrel;
843 enum pic_relocation pic;
844 {
845 switch (pic)
846 {
847 case pic_got_pcrel:
848 switch (size)
849 {
850 case 1:
851 return BFD_RELOC_8_GOT_PCREL;
852 case 2:
853 return BFD_RELOC_16_GOT_PCREL;
854 case 4:
855 return BFD_RELOC_32_GOT_PCREL;
856 }
857 break;
858
859 case pic_got_off:
860 switch (size)
861 {
862 case 1:
863 return BFD_RELOC_8_GOTOFF;
864 case 2:
865 return BFD_RELOC_16_GOTOFF;
866 case 4:
867 return BFD_RELOC_32_GOTOFF;
868 }
869 break;
870
871 case pic_plt_pcrel:
872 switch (size)
873 {
874 case 1:
875 return BFD_RELOC_8_PLT_PCREL;
876 case 2:
877 return BFD_RELOC_16_PLT_PCREL;
878 case 4:
879 return BFD_RELOC_32_PLT_PCREL;
880 }
881 break;
882
883 case pic_plt_off:
884 switch (size)
885 {
886 case 1:
887 return BFD_RELOC_8_PLTOFF;
888 case 2:
889 return BFD_RELOC_16_PLTOFF;
890 case 4:
891 return BFD_RELOC_32_PLTOFF;
892 }
893 break;
894
895 case pic_none:
896 if (pcrel)
897 {
898 switch (size)
899 {
900 case 1:
901 return BFD_RELOC_8_PCREL;
902 case 2:
903 return BFD_RELOC_16_PCREL;
904 case 4:
905 return BFD_RELOC_32_PCREL;
906 }
907 }
908 else
909 {
910 switch (size)
911 {
912 case 1:
913 return BFD_RELOC_8;
914 case 2:
915 return BFD_RELOC_16;
916 case 4:
917 return BFD_RELOC_32;
918 }
919 }
920 }
921
922 if (pcrel)
923 {
924 if (pic == pic_none)
925 as_bad (_("Can not do %d byte pc-relative relocation"), size);
926 else
927 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
928 }
929 else
930 {
931 if (pic == pic_none)
932 as_bad (_("Can not do %d byte relocation"), size);
933 else
934 as_bad (_("Can not do %d byte pic relocation"), size);
935 }
936
937 return BFD_RELOC_NONE;
938 }
939
940 /* Here we decide which fixups can be adjusted to make them relative
941 to the beginning of the section instead of the symbol. Basically
942 we need to make sure that the dynamic relocations are done
943 correctly, so in some cases we force the original symbol to be
944 used. */
945 int
946 tc_m68k_fix_adjustable (fixP)
947 fixS *fixP;
948 {
949 /* Adjust_reloc_syms doesn't know about the GOT. */
950 switch (fixP->fx_r_type)
951 {
952 case BFD_RELOC_8_GOT_PCREL:
953 case BFD_RELOC_16_GOT_PCREL:
954 case BFD_RELOC_32_GOT_PCREL:
955 case BFD_RELOC_8_GOTOFF:
956 case BFD_RELOC_16_GOTOFF:
957 case BFD_RELOC_32_GOTOFF:
958 case BFD_RELOC_8_PLT_PCREL:
959 case BFD_RELOC_16_PLT_PCREL:
960 case BFD_RELOC_32_PLT_PCREL:
961 case BFD_RELOC_8_PLTOFF:
962 case BFD_RELOC_16_PLTOFF:
963 case BFD_RELOC_32_PLTOFF:
964 return 0;
965
966 case BFD_RELOC_VTABLE_INHERIT:
967 case BFD_RELOC_VTABLE_ENTRY:
968 return 0;
969
970 default:
971 return 1;
972 }
973 }
974
975 #else /* !OBJ_ELF */
976
977 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
978
979 #define relaxable_symbol(symbol) 1
980
981 #endif /* OBJ_ELF */
982
983 #ifdef BFD_ASSEMBLER
984
985 arelent *
986 tc_gen_reloc (section, fixp)
987 asection *section ATTRIBUTE_UNUSED;
988 fixS *fixp;
989 {
990 arelent *reloc;
991 bfd_reloc_code_real_type code;
992
993 /* If the tcbit is set, then this was a fixup of a negative value
994 that was never resolved. We do not have a reloc to handle this,
995 so just return. We assume that other code will have detected this
996 situation and produced a helpful error message, so we just tell the
997 user that the reloc cannot be produced. */
998 if (fixp->fx_tcbit)
999 {
1000 if (fixp->fx_addsy)
1001 as_bad_where (fixp->fx_file, fixp->fx_line,
1002 _("Unable to produce reloc against symbol '%s'"),
1003 S_GET_NAME (fixp->fx_addsy));
1004 return NULL;
1005 }
1006
1007 if (fixp->fx_r_type != BFD_RELOC_NONE)
1008 {
1009 code = fixp->fx_r_type;
1010
1011 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1012 that fixup_segment converted a non-PC relative reloc into a
1013 PC relative reloc. In such a case, we need to convert the
1014 reloc code. */
1015 if (fixp->fx_pcrel)
1016 {
1017 switch (code)
1018 {
1019 case BFD_RELOC_8:
1020 code = BFD_RELOC_8_PCREL;
1021 break;
1022 case BFD_RELOC_16:
1023 code = BFD_RELOC_16_PCREL;
1024 break;
1025 case BFD_RELOC_32:
1026 code = BFD_RELOC_32_PCREL;
1027 break;
1028 case BFD_RELOC_8_PCREL:
1029 case BFD_RELOC_16_PCREL:
1030 case BFD_RELOC_32_PCREL:
1031 case BFD_RELOC_8_GOT_PCREL:
1032 case BFD_RELOC_16_GOT_PCREL:
1033 case BFD_RELOC_32_GOT_PCREL:
1034 case BFD_RELOC_8_GOTOFF:
1035 case BFD_RELOC_16_GOTOFF:
1036 case BFD_RELOC_32_GOTOFF:
1037 case BFD_RELOC_8_PLT_PCREL:
1038 case BFD_RELOC_16_PLT_PCREL:
1039 case BFD_RELOC_32_PLT_PCREL:
1040 case BFD_RELOC_8_PLTOFF:
1041 case BFD_RELOC_16_PLTOFF:
1042 case BFD_RELOC_32_PLTOFF:
1043 break;
1044 default:
1045 as_bad_where (fixp->fx_file, fixp->fx_line,
1046 _("Cannot make %s relocation PC relative"),
1047 bfd_get_reloc_code_name (code));
1048 }
1049 }
1050 }
1051 else
1052 {
1053 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1054 switch (F (fixp->fx_size, fixp->fx_pcrel))
1055 {
1056 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1057 MAP (1, 0, BFD_RELOC_8);
1058 MAP (2, 0, BFD_RELOC_16);
1059 MAP (4, 0, BFD_RELOC_32);
1060 MAP (1, 1, BFD_RELOC_8_PCREL);
1061 MAP (2, 1, BFD_RELOC_16_PCREL);
1062 MAP (4, 1, BFD_RELOC_32_PCREL);
1063 default:
1064 abort ();
1065 }
1066 }
1067 #undef F
1068 #undef MAP
1069
1070 reloc = (arelent *) xmalloc (sizeof (arelent));
1071 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1072 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1073 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1074 #ifndef OBJ_ELF
1075 if (fixp->fx_pcrel)
1076 reloc->addend = fixp->fx_addnumber;
1077 else
1078 reloc->addend = 0;
1079 #else
1080 if (!fixp->fx_pcrel)
1081 reloc->addend = fixp->fx_addnumber;
1082 else
1083 reloc->addend = (section->vma
1084 /* Explicit sign extension in case char is
1085 unsigned. */
1086 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1087 + fixp->fx_addnumber
1088 + md_pcrel_from (fixp));
1089 #endif
1090
1091 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1092 assert (reloc->howto != 0);
1093
1094 return reloc;
1095 }
1096
1097 #endif /* BFD_ASSEMBLER */
1098
1099 /* Handle of the OPCODE hash table. NULL means any use before
1100 m68k_ip_begin() will crash. */
1101 static struct hash_control *op_hash;
1102 \f
1103 /* Assemble an m68k instruction. */
1104
1105 static void
1106 m68k_ip (instring)
1107 char *instring;
1108 {
1109 register char *p;
1110 register struct m68k_op *opP;
1111 register const struct m68k_incant *opcode;
1112 register const char *s;
1113 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1114 char *pdot, *pdotmove;
1115 enum m68k_size siz1, siz2;
1116 char c;
1117 int losing;
1118 int opsfound;
1119 LITTLENUM_TYPE words[6];
1120 LITTLENUM_TYPE *wordp;
1121 unsigned long ok_arch = 0;
1122
1123 if (*instring == ' ')
1124 instring++; /* Skip leading whitespace. */
1125
1126 /* Scan up to end of operation-code, which MUST end in end-of-string
1127 or exactly 1 space. */
1128 pdot = 0;
1129 for (p = instring; *p != '\0'; p++)
1130 {
1131 if (*p == ' ')
1132 break;
1133 if (*p == '.')
1134 pdot = p;
1135 }
1136
1137 if (p == instring)
1138 {
1139 the_ins.error = _("No operator");
1140 return;
1141 }
1142
1143 /* p now points to the end of the opcode name, probably whitespace.
1144 Make sure the name is null terminated by clobbering the
1145 whitespace, look it up in the hash table, then fix it back.
1146 Remove a dot, first, since the opcode tables have none. */
1147 if (pdot != NULL)
1148 {
1149 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1150 *pdotmove = pdotmove[1];
1151 p--;
1152 }
1153
1154 c = *p;
1155 *p = '\0';
1156 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1157 *p = c;
1158
1159 if (pdot != NULL)
1160 {
1161 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1162 *pdotmove = pdotmove[-1];
1163 *pdot = '.';
1164 ++p;
1165 }
1166
1167 if (opcode == NULL)
1168 {
1169 the_ins.error = _("Unknown operator");
1170 return;
1171 }
1172
1173 /* Found a legitimate opcode, start matching operands. */
1174 while (*p == ' ')
1175 ++p;
1176
1177 if (opcode->m_operands == 0)
1178 {
1179 char *old = input_line_pointer;
1180 *old = '\n';
1181 input_line_pointer = p;
1182 /* Ahh - it's a motorola style psuedo op. */
1183 mote_pseudo_table[opcode->m_opnum].poc_handler
1184 (mote_pseudo_table[opcode->m_opnum].poc_val);
1185 input_line_pointer = old;
1186 *old = 0;
1187
1188 return;
1189 }
1190
1191 if (flag_mri && opcode->m_opnum == 0)
1192 {
1193 /* In MRI mode, random garbage is allowed after an instruction
1194 which accepts no operands. */
1195 the_ins.args = opcode->m_operands;
1196 the_ins.numargs = opcode->m_opnum;
1197 the_ins.numo = opcode->m_codenum;
1198 the_ins.opcode[0] = getone (opcode);
1199 the_ins.opcode[1] = gettwo (opcode);
1200 return;
1201 }
1202
1203 for (opP = &the_ins.operands[0]; *p; opP++)
1204 {
1205 p = crack_operand (p, opP);
1206
1207 if (opP->error)
1208 {
1209 the_ins.error = opP->error;
1210 return;
1211 }
1212 }
1213
1214 opsfound = opP - &the_ins.operands[0];
1215
1216 /* This ugly hack is to support the floating pt opcodes in their
1217 standard form. Essentially, we fake a first enty of type COP#1 */
1218 if (opcode->m_operands[0] == 'I')
1219 {
1220 int n;
1221
1222 for (n = opsfound; n > 0; --n)
1223 the_ins.operands[n] = the_ins.operands[n - 1];
1224
1225 memset ((char *) (&the_ins.operands[0]), '\0',
1226 sizeof (the_ins.operands[0]));
1227 the_ins.operands[0].mode = CONTROL;
1228 the_ins.operands[0].reg = m68k_float_copnum;
1229 opsfound++;
1230 }
1231
1232 /* We've got the operands. Find an opcode that'll accept them. */
1233 for (losing = 0;;)
1234 {
1235 /* If we didn't get the right number of ops, or we have no
1236 common model with this pattern then reject this pattern. */
1237
1238 ok_arch |= opcode->m_arch;
1239 if (opsfound != opcode->m_opnum
1240 || ((opcode->m_arch & current_architecture) == 0))
1241 ++losing;
1242 else
1243 {
1244 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1245 *s && !losing;
1246 s += 2, opP++)
1247 {
1248 /* Warning: this switch is huge! */
1249 /* I've tried to organize the cases into this order:
1250 non-alpha first, then alpha by letter. Lower-case
1251 goes directly before uppercase counterpart. */
1252 /* Code with multiple case ...: gets sorted by the lowest
1253 case ... it belongs to. I hope this makes sense. */
1254 switch (*s)
1255 {
1256 case '!':
1257 switch (opP->mode)
1258 {
1259 case IMMED:
1260 case DREG:
1261 case AREG:
1262 case FPREG:
1263 case CONTROL:
1264 case AINC:
1265 case ADEC:
1266 case REGLST:
1267 losing++;
1268 break;
1269 default:
1270 break;
1271 }
1272 break;
1273
1274 case '<':
1275 switch (opP->mode)
1276 {
1277 case DREG:
1278 case AREG:
1279 case FPREG:
1280 case CONTROL:
1281 case IMMED:
1282 case ADEC:
1283 case REGLST:
1284 losing++;
1285 break;
1286 default:
1287 break;
1288 }
1289 break;
1290
1291 case '>':
1292 switch (opP->mode)
1293 {
1294 case DREG:
1295 case AREG:
1296 case FPREG:
1297 case CONTROL:
1298 case IMMED:
1299 case AINC:
1300 case REGLST:
1301 losing++;
1302 break;
1303 case ABSL:
1304 break;
1305 default:
1306 if (opP->reg == PC
1307 || opP->reg == ZPC)
1308 losing++;
1309 break;
1310 }
1311 break;
1312
1313 case 'm':
1314 switch (opP->mode)
1315 {
1316 case DREG:
1317 case AREG:
1318 case AINDR:
1319 case AINC:
1320 case ADEC:
1321 break;
1322 default:
1323 losing++;
1324 }
1325 break;
1326
1327 case 'n':
1328 switch (opP->mode)
1329 {
1330 case DISP:
1331 break;
1332 default:
1333 losing++;
1334 }
1335 break;
1336
1337 case 'o':
1338 switch (opP->mode)
1339 {
1340 case BASE:
1341 case ABSL:
1342 case IMMED:
1343 break;
1344 default:
1345 losing++;
1346 }
1347 break;
1348
1349 case 'p':
1350 switch (opP->mode)
1351 {
1352 case DREG:
1353 case AREG:
1354 case AINDR:
1355 case AINC:
1356 case ADEC:
1357 break;
1358 case DISP:
1359 if (opP->reg == PC || opP->reg == ZPC)
1360 losing++;
1361 break;
1362 default:
1363 losing++;
1364 }
1365 break;
1366
1367 case 'q':
1368 switch (opP->mode)
1369 {
1370 case DREG:
1371 case AINDR:
1372 case AINC:
1373 case ADEC:
1374 break;
1375 case DISP:
1376 if (opP->reg == PC || opP->reg == ZPC)
1377 losing++;
1378 break;
1379 default:
1380 losing++;
1381 break;
1382 }
1383 break;
1384
1385 case 'v':
1386 switch (opP->mode)
1387 {
1388 case DREG:
1389 case AINDR:
1390 case AINC:
1391 case ADEC:
1392 case ABSL:
1393 break;
1394 case DISP:
1395 if (opP->reg == PC || opP->reg == ZPC)
1396 losing++;
1397 break;
1398 default:
1399 losing++;
1400 break;
1401 }
1402 break;
1403
1404 case '#':
1405 if (opP->mode != IMMED)
1406 losing++;
1407 else if (s[1] == 'b'
1408 && ! isvar (&opP->disp)
1409 && (opP->disp.exp.X_op != O_constant
1410 || ! isbyte (opP->disp.exp.X_add_number)))
1411 losing++;
1412 else if (s[1] == 'B'
1413 && ! isvar (&opP->disp)
1414 && (opP->disp.exp.X_op != O_constant
1415 || ! issbyte (opP->disp.exp.X_add_number)))
1416 losing++;
1417 else if (s[1] == 'w'
1418 && ! isvar (&opP->disp)
1419 && (opP->disp.exp.X_op != O_constant
1420 || ! isword (opP->disp.exp.X_add_number)))
1421 losing++;
1422 else if (s[1] == 'W'
1423 && ! isvar (&opP->disp)
1424 && (opP->disp.exp.X_op != O_constant
1425 || ! issword (opP->disp.exp.X_add_number)))
1426 losing++;
1427 break;
1428
1429 case '^':
1430 case 'T':
1431 if (opP->mode != IMMED)
1432 losing++;
1433 break;
1434
1435 case '$':
1436 if (opP->mode == AREG
1437 || opP->mode == CONTROL
1438 || opP->mode == FPREG
1439 || opP->mode == IMMED
1440 || opP->mode == REGLST
1441 || (opP->mode != ABSL
1442 && (opP->reg == PC
1443 || opP->reg == ZPC)))
1444 losing++;
1445 break;
1446
1447 case '%':
1448 if (opP->mode == CONTROL
1449 || opP->mode == FPREG
1450 || opP->mode == REGLST
1451 || opP->mode == IMMED
1452 || (opP->mode != ABSL
1453 && (opP->reg == PC
1454 || opP->reg == ZPC)))
1455 losing++;
1456 break;
1457
1458 case '&':
1459 switch (opP->mode)
1460 {
1461 case DREG:
1462 case AREG:
1463 case FPREG:
1464 case CONTROL:
1465 case IMMED:
1466 case AINC:
1467 case ADEC:
1468 case REGLST:
1469 losing++;
1470 break;
1471 case ABSL:
1472 break;
1473 default:
1474 if (opP->reg == PC
1475 || opP->reg == ZPC)
1476 losing++;
1477 break;
1478 }
1479 break;
1480
1481 case '*':
1482 if (opP->mode == CONTROL
1483 || opP->mode == FPREG
1484 || opP->mode == REGLST)
1485 losing++;
1486 break;
1487
1488 case '+':
1489 if (opP->mode != AINC)
1490 losing++;
1491 break;
1492
1493 case '-':
1494 if (opP->mode != ADEC)
1495 losing++;
1496 break;
1497
1498 case '/':
1499 switch (opP->mode)
1500 {
1501 case AREG:
1502 case CONTROL:
1503 case FPREG:
1504 case AINC:
1505 case ADEC:
1506 case IMMED:
1507 case REGLST:
1508 losing++;
1509 break;
1510 default:
1511 break;
1512 }
1513 break;
1514
1515 case ';':
1516 switch (opP->mode)
1517 {
1518 case AREG:
1519 case CONTROL:
1520 case FPREG:
1521 case REGLST:
1522 losing++;
1523 break;
1524 default:
1525 break;
1526 }
1527 break;
1528
1529 case '?':
1530 switch (opP->mode)
1531 {
1532 case AREG:
1533 case CONTROL:
1534 case FPREG:
1535 case AINC:
1536 case ADEC:
1537 case IMMED:
1538 case REGLST:
1539 losing++;
1540 break;
1541 case ABSL:
1542 break;
1543 default:
1544 if (opP->reg == PC || opP->reg == ZPC)
1545 losing++;
1546 break;
1547 }
1548 break;
1549
1550 case '@':
1551 switch (opP->mode)
1552 {
1553 case AREG:
1554 case CONTROL:
1555 case FPREG:
1556 case IMMED:
1557 case REGLST:
1558 losing++;
1559 break;
1560 default:
1561 break;
1562 }
1563 break;
1564
1565 case '~': /* For now! (JF FOO is this right?) */
1566 switch (opP->mode)
1567 {
1568 case DREG:
1569 case AREG:
1570 case CONTROL:
1571 case FPREG:
1572 case IMMED:
1573 case REGLST:
1574 losing++;
1575 break;
1576 case ABSL:
1577 break;
1578 default:
1579 if (opP->reg == PC
1580 || opP->reg == ZPC)
1581 losing++;
1582 break;
1583 }
1584 break;
1585
1586 case '3':
1587 if (opP->mode != CONTROL
1588 || (opP->reg != TT0 && opP->reg != TT1))
1589 losing++;
1590 break;
1591
1592 case 'A':
1593 if (opP->mode != AREG)
1594 losing++;
1595 break;
1596
1597 case 'a':
1598 if (opP->mode != AINDR)
1599 ++losing;
1600 break;
1601
1602 case '4':
1603 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1604 && (opP->mode != DISP
1605 || opP->reg < ADDR0
1606 || opP->reg > ADDR7))
1607 ++losing;
1608 break;
1609
1610 case 'B': /* FOO */
1611 if (opP->mode != ABSL
1612 || (flag_long_jumps
1613 && strncmp (instring, "jbsr", 4) == 0))
1614 losing++;
1615 break;
1616
1617 case 'b':
1618 switch (opP->mode)
1619 {
1620 case IMMED:
1621 case ABSL:
1622 case AREG:
1623 case FPREG:
1624 case CONTROL:
1625 case POST:
1626 case PRE:
1627 case REGLST:
1628 losing++;
1629 break;
1630 default:
1631 break;
1632 }
1633 break;
1634
1635 case 'C':
1636 if (opP->mode != CONTROL || opP->reg != CCR)
1637 losing++;
1638 break;
1639
1640 case 'd':
1641 if (opP->mode != DISP
1642 || opP->reg < ADDR0
1643 || opP->reg > ADDR7)
1644 losing++;
1645 break;
1646
1647 case 'D':
1648 if (opP->mode != DREG)
1649 losing++;
1650 break;
1651
1652 case 'E':
1653 if (opP->reg != ACC)
1654 losing++;
1655 break;
1656
1657 case 'e':
1658 if (opP->reg != ACC && opP->reg != ACC1
1659 && opP->reg != ACC2 && opP->reg != ACC3)
1660 losing++;
1661 break;
1662
1663 case 'F':
1664 if (opP->mode != FPREG)
1665 losing++;
1666 break;
1667
1668 case 'G':
1669 if (opP->reg != MACSR)
1670 losing++;
1671 break;
1672
1673 case 'g':
1674 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1675 losing++;
1676 break;
1677
1678 case 'H':
1679 if (opP->reg != MASK)
1680 losing++;
1681 break;
1682
1683 case 'I':
1684 if (opP->mode != CONTROL
1685 || opP->reg < COP0
1686 || opP->reg > COP7)
1687 losing++;
1688 break;
1689
1690 case 'i':
1691 if (opP->mode != LSH && opP->mode != RSH)
1692 losing++;
1693 break;
1694
1695 case 'J':
1696 if (opP->mode != CONTROL
1697 || opP->reg < USP
1698 || opP->reg > last_movec_reg)
1699 losing++;
1700 else
1701 {
1702 const enum m68k_register *rp;
1703 for (rp = control_regs; *rp; rp++)
1704 if (*rp == opP->reg)
1705 break;
1706 if (*rp == 0)
1707 losing++;
1708 }
1709 break;
1710
1711 case 'k':
1712 if (opP->mode != IMMED)
1713 losing++;
1714 break;
1715
1716 case 'l':
1717 case 'L':
1718 if (opP->mode == DREG
1719 || opP->mode == AREG
1720 || opP->mode == FPREG)
1721 {
1722 if (s[1] == '8')
1723 losing++;
1724 else
1725 {
1726 switch (opP->mode)
1727 {
1728 case DREG:
1729 opP->mask = 1 << (opP->reg - DATA0);
1730 break;
1731 case AREG:
1732 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1733 break;
1734 case FPREG:
1735 opP->mask = 1 << (opP->reg - FP0 + 16);
1736 break;
1737 default:
1738 abort ();
1739 }
1740 opP->mode = REGLST;
1741 }
1742 }
1743 else if (opP->mode == CONTROL)
1744 {
1745 if (s[1] != '8')
1746 losing++;
1747 else
1748 {
1749 switch (opP->reg)
1750 {
1751 case FPI:
1752 opP->mask = 1 << 24;
1753 break;
1754 case FPS:
1755 opP->mask = 1 << 25;
1756 break;
1757 case FPC:
1758 opP->mask = 1 << 26;
1759 break;
1760 default:
1761 losing++;
1762 break;
1763 }
1764 opP->mode = REGLST;
1765 }
1766 }
1767 else if (opP->mode != REGLST)
1768 losing++;
1769 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1770 losing++;
1771 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1772 losing++;
1773 break;
1774
1775 case 'M':
1776 if (opP->mode != IMMED)
1777 losing++;
1778 else if (opP->disp.exp.X_op != O_constant
1779 || ! issbyte (opP->disp.exp.X_add_number))
1780 losing++;
1781 else if (! m68k_quick
1782 && instring[3] != 'q'
1783 && instring[4] != 'q')
1784 losing++;
1785 break;
1786
1787 case 'O':
1788 if (opP->mode != DREG
1789 && opP->mode != IMMED
1790 && opP->mode != ABSL)
1791 losing++;
1792 break;
1793
1794 case 'Q':
1795 if (opP->mode != IMMED)
1796 losing++;
1797 else if (opP->disp.exp.X_op != O_constant
1798 || opP->disp.exp.X_add_number < 1
1799 || opP->disp.exp.X_add_number > 8)
1800 losing++;
1801 else if (! m68k_quick
1802 && (strncmp (instring, "add", 3) == 0
1803 || strncmp (instring, "sub", 3) == 0)
1804 && instring[3] != 'q')
1805 losing++;
1806 break;
1807
1808 case 'R':
1809 if (opP->mode != DREG && opP->mode != AREG)
1810 losing++;
1811 break;
1812
1813 case 'r':
1814 if (opP->mode != AINDR
1815 && (opP->mode != BASE
1816 || (opP->reg != 0
1817 && opP->reg != ZADDR0)
1818 || opP->disp.exp.X_op != O_absent
1819 || ((opP->index.reg < DATA0
1820 || opP->index.reg > DATA7)
1821 && (opP->index.reg < ADDR0
1822 || opP->index.reg > ADDR7))
1823 || opP->index.size != SIZE_UNSPEC
1824 || opP->index.scale != 1))
1825 losing++;
1826 break;
1827
1828 case 's':
1829 if (opP->mode != CONTROL
1830 || ! (opP->reg == FPI
1831 || opP->reg == FPS
1832 || opP->reg == FPC))
1833 losing++;
1834 break;
1835
1836 case 'S':
1837 if (opP->mode != CONTROL || opP->reg != SR)
1838 losing++;
1839 break;
1840
1841 case 't':
1842 if (opP->mode != IMMED)
1843 losing++;
1844 else if (opP->disp.exp.X_op != O_constant
1845 || opP->disp.exp.X_add_number < 0
1846 || opP->disp.exp.X_add_number > 7)
1847 losing++;
1848 break;
1849
1850 case 'U':
1851 if (opP->mode != CONTROL || opP->reg != USP)
1852 losing++;
1853 break;
1854
1855 case 'x':
1856 if (opP->mode != IMMED)
1857 losing++;
1858 else if (opP->disp.exp.X_op != O_constant
1859 || opP->disp.exp.X_add_number < -1
1860 || opP->disp.exp.X_add_number > 7
1861 || opP->disp.exp.X_add_number == 0)
1862 losing++;
1863 break;
1864
1865 /* JF these are out of order. We could put them
1866 in order if we were willing to put up with
1867 bunches of #ifdef m68851s in the code.
1868
1869 Don't forget that you need these operands
1870 to use 68030 MMU instructions. */
1871 #ifndef NO_68851
1872 /* Memory addressing mode used by pflushr. */
1873 case '|':
1874 if (opP->mode == CONTROL
1875 || opP->mode == FPREG
1876 || opP->mode == DREG
1877 || opP->mode == AREG
1878 || opP->mode == REGLST)
1879 losing++;
1880 /* We should accept immediate operands, but they
1881 supposedly have to be quad word, and we don't
1882 handle that. I would like to see what a Motorola
1883 assembler does before doing something here. */
1884 if (opP->mode == IMMED)
1885 losing++;
1886 break;
1887
1888 case 'f':
1889 if (opP->mode != CONTROL
1890 || (opP->reg != SFC && opP->reg != DFC))
1891 losing++;
1892 break;
1893
1894 case '0':
1895 if (opP->mode != CONTROL || opP->reg != TC)
1896 losing++;
1897 break;
1898
1899 case '1':
1900 if (opP->mode != CONTROL || opP->reg != AC)
1901 losing++;
1902 break;
1903
1904 case '2':
1905 if (opP->mode != CONTROL
1906 || (opP->reg != CAL
1907 && opP->reg != VAL
1908 && opP->reg != SCC))
1909 losing++;
1910 break;
1911
1912 case 'V':
1913 if (opP->mode != CONTROL
1914 || opP->reg != VAL)
1915 losing++;
1916 break;
1917
1918 case 'W':
1919 if (opP->mode != CONTROL
1920 || (opP->reg != DRP
1921 && opP->reg != SRP
1922 && opP->reg != CRP))
1923 losing++;
1924 break;
1925
1926 case 'w':
1927 switch (opP->mode)
1928 {
1929 case IMMED:
1930 case ABSL:
1931 case AREG:
1932 case DREG:
1933 case FPREG:
1934 case CONTROL:
1935 case POST:
1936 case PRE:
1937 case REGLST:
1938 losing++;
1939 break;
1940 default:
1941 break;
1942 }
1943 break;
1944
1945 case 'X':
1946 if (opP->mode != CONTROL
1947 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1948 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1949 losing++;
1950 break;
1951
1952 case 'Y':
1953 if (opP->mode != CONTROL || opP->reg != PSR)
1954 losing++;
1955 break;
1956
1957 case 'Z':
1958 if (opP->mode != CONTROL || opP->reg != PCSR)
1959 losing++;
1960 break;
1961 #endif
1962 case 'c':
1963 if (opP->mode != CONTROL
1964 || (opP->reg != NC
1965 && opP->reg != IC
1966 && opP->reg != DC
1967 && opP->reg != BC))
1968 losing++;
1969 break;
1970
1971 case '_':
1972 if (opP->mode != ABSL)
1973 ++losing;
1974 break;
1975
1976 case 'u':
1977 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1978 losing++;
1979 /* FIXME: kludge instead of fixing parser:
1980 upper/lower registers are *not* CONTROL
1981 registers, but ordinary ones. */
1982 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1983 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1984 opP->mode = DREG;
1985 else
1986 opP->mode = AREG;
1987 break;
1988
1989 case 'y':
1990 if (!(opP->mode == AINDR
1991 || (opP->mode == DISP && !(opP->reg == PC ||
1992 opP->reg == ZPC))))
1993 losing++;
1994 break;
1995
1996 case 'z':
1997 if (!(opP->mode == AINDR || opP->mode == DISP))
1998 losing++;
1999 break;
2000
2001 default:
2002 abort ();
2003 }
2004
2005 if (losing)
2006 break;
2007 }
2008 }
2009
2010 if (!losing)
2011 break;
2012
2013 opcode = opcode->m_next;
2014
2015 if (!opcode)
2016 {
2017 if (ok_arch
2018 && !(ok_arch & current_architecture))
2019 {
2020 char buf[200], *cp;
2021
2022 strncpy (buf,
2023 _("invalid instruction for this architecture; needs "), sizeof (buf));
2024 cp = buf + strlen (buf);
2025 switch (ok_arch)
2026 {
2027 case mcfisa_a:
2028 strncpy (cp, _("ColdFire ISA_A"), (sizeof (buf) - (cp - buf)));
2029 cp += strlen (cp);
2030 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2031 cp += strlen (cp);
2032 break;
2033 case mcfhwdiv:
2034 strncpy (cp, _("ColdFire hardware divide"), (sizeof (buf) - (cp - buf)));
2035 cp += strlen (cp);
2036 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2037 cp += strlen (cp);
2038 break;
2039 case mcfisa_aa:
2040 strncpy (cp, _("ColdFire ISA_A+"), (sizeof (buf) - (cp - buf)));
2041 cp += strlen (cp);
2042 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2043 cp += strlen (cp);
2044 break;
2045 case mcfisa_b:
2046 strncpy (cp, _("ColdFire ISA_B"), (sizeof (buf) - (cp - buf)));
2047 cp += strlen (cp);
2048 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2049 cp += strlen (cp);
2050 break;
2051 case cfloat:
2052 strncpy (cp, _("ColdFire fpu"), (sizeof (buf) - (cp - buf)));
2053 cp += strlen (cp);
2054 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2055 cp += strlen (cp);
2056 break;
2057 case mfloat:
2058 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
2059 break;
2060 case mmmu:
2061 strcpy (cp, _("mmu (68030 or 68851)"));
2062 break;
2063 case m68020up:
2064 strcpy (cp, _("68020 or higher"));
2065 break;
2066 case m68000up:
2067 strcpy (cp, _("68000 or higher"));
2068 break;
2069 case m68010up:
2070 strcpy (cp, _("68010 or higher"));
2071 break;
2072 default:
2073 {
2074 int got_one = 0, idx;
2075
2076 for (idx = 0; idx < n_archs; idx++)
2077 {
2078 if ((archs[idx].arch & ok_arch)
2079 && ! archs[idx].alias)
2080 {
2081 if (got_one)
2082 {
2083 strcpy (cp, " or ");
2084 cp += strlen (cp);
2085 }
2086 got_one = 1;
2087 strcpy (cp, archs[idx].name);
2088 cp += strlen (cp);
2089 }
2090 }
2091 }
2092 }
2093 cp = xmalloc (strlen (buf) + 1);
2094 strcpy (cp, buf);
2095 the_ins.error = cp;
2096 }
2097 else
2098 the_ins.error = _("operands mismatch");
2099 return;
2100 }
2101
2102 losing = 0;
2103 }
2104
2105 /* Now assemble it. */
2106 the_ins.args = opcode->m_operands;
2107 the_ins.numargs = opcode->m_opnum;
2108 the_ins.numo = opcode->m_codenum;
2109 the_ins.opcode[0] = getone (opcode);
2110 the_ins.opcode[1] = gettwo (opcode);
2111
2112 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2113 {
2114 /* This switch is a doozy.
2115 Watch the first step; its a big one! */
2116 switch (s[0])
2117 {
2118
2119 case '*':
2120 case '~':
2121 case '%':
2122 case ';':
2123 case '@':
2124 case '!':
2125 case '&':
2126 case '$':
2127 case '?':
2128 case '/':
2129 case '<':
2130 case '>':
2131 case 'b':
2132 case 'm':
2133 case 'n':
2134 case 'o':
2135 case 'p':
2136 case 'q':
2137 case 'v':
2138 case 'w':
2139 case 'y':
2140 case 'z':
2141 case '4':
2142 #ifndef NO_68851
2143 case '|':
2144 #endif
2145 switch (opP->mode)
2146 {
2147 case IMMED:
2148 tmpreg = 0x3c; /* 7.4 */
2149 if (strchr ("bwl", s[1]))
2150 nextword = get_num (&opP->disp, 90);
2151 else
2152 nextword = get_num (&opP->disp, 0);
2153 if (isvar (&opP->disp))
2154 add_fix (s[1], &opP->disp, 0, 0);
2155 switch (s[1])
2156 {
2157 case 'b':
2158 if (!isbyte (nextword))
2159 opP->error = _("operand out of range");
2160 addword (nextword);
2161 baseo = 0;
2162 break;
2163 case 'w':
2164 if (!isword (nextword))
2165 opP->error = _("operand out of range");
2166 addword (nextword);
2167 baseo = 0;
2168 break;
2169 case 'W':
2170 if (!issword (nextword))
2171 opP->error = _("operand out of range");
2172 addword (nextword);
2173 baseo = 0;
2174 break;
2175 case 'l':
2176 addword (nextword >> 16);
2177 addword (nextword);
2178 baseo = 0;
2179 break;
2180
2181 case 'f':
2182 baseo = 2;
2183 outro = 8;
2184 break;
2185 case 'F':
2186 baseo = 4;
2187 outro = 11;
2188 break;
2189 case 'x':
2190 baseo = 6;
2191 outro = 15;
2192 break;
2193 case 'p':
2194 baseo = 6;
2195 outro = -1;
2196 break;
2197 default:
2198 abort ();
2199 }
2200 if (!baseo)
2201 break;
2202
2203 /* We gotta put out some float. */
2204 if (op (&opP->disp) != O_big)
2205 {
2206 valueT val;
2207 int gencnt;
2208
2209 /* Can other cases happen here? */
2210 if (op (&opP->disp) != O_constant)
2211 abort ();
2212
2213 val = (valueT) offs (&opP->disp);
2214 gencnt = 0;
2215 do
2216 {
2217 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2218 val >>= LITTLENUM_NUMBER_OF_BITS;
2219 ++gencnt;
2220 }
2221 while (val != 0);
2222 offs (&opP->disp) = gencnt;
2223 }
2224 if (offs (&opP->disp) > 0)
2225 {
2226 if (offs (&opP->disp) > baseo)
2227 {
2228 as_warn (_("Bignum too big for %c format; truncated"),
2229 s[1]);
2230 offs (&opP->disp) = baseo;
2231 }
2232 baseo -= offs (&opP->disp);
2233 while (baseo--)
2234 addword (0);
2235 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2236 offs (&opP->disp)--;
2237 --wordp)
2238 addword (*wordp);
2239 break;
2240 }
2241 gen_to_words (words, baseo, (long) outro);
2242 for (wordp = words; baseo--; wordp++)
2243 addword (*wordp);
2244 break;
2245 case DREG:
2246 tmpreg = opP->reg - DATA; /* 0.dreg */
2247 break;
2248 case AREG:
2249 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2250 break;
2251 case AINDR:
2252 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2253 break;
2254 case ADEC:
2255 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2256 break;
2257 case AINC:
2258 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2259 break;
2260 case DISP:
2261
2262 nextword = get_num (&opP->disp, 90);
2263
2264 /* Convert mode 5 addressing with a zero offset into
2265 mode 2 addressing to reduce the instruction size by a
2266 word. */
2267 if (! isvar (&opP->disp)
2268 && (nextword == 0)
2269 && (opP->disp.size == SIZE_UNSPEC)
2270 && (opP->reg >= ADDR0)
2271 && (opP->reg <= ADDR7))
2272 {
2273 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2274 break;
2275 }
2276
2277 if (opP->reg == PC
2278 && ! isvar (&opP->disp)
2279 && m68k_abspcadd)
2280 {
2281 opP->disp.exp.X_op = O_symbol;
2282 #ifndef BFD_ASSEMBLER
2283 opP->disp.exp.X_add_symbol = &abs_symbol;
2284 #else
2285 opP->disp.exp.X_add_symbol =
2286 section_symbol (absolute_section);
2287 #endif
2288 }
2289
2290 /* Force into index mode. Hope this works. */
2291
2292 /* We do the first bit for 32-bit displacements, and the
2293 second bit for 16 bit ones. It is possible that we
2294 should make the default be WORD instead of LONG, but
2295 I think that'd break GCC, so we put up with a little
2296 inefficiency for the sake of working output. */
2297
2298 if (!issword (nextword)
2299 || (isvar (&opP->disp)
2300 && ((opP->disp.size == SIZE_UNSPEC
2301 && flag_short_refs == 0
2302 && cpu_of_arch (current_architecture) >= m68020
2303 && ! arch_coldfire_p (current_architecture))
2304 || opP->disp.size == SIZE_LONG)))
2305 {
2306 if (cpu_of_arch (current_architecture) < m68020
2307 || arch_coldfire_p (current_architecture))
2308 opP->error =
2309 _("displacement too large for this architecture; needs 68020 or higher");
2310 if (opP->reg == PC)
2311 tmpreg = 0x3B; /* 7.3 */
2312 else
2313 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2314 if (isvar (&opP->disp))
2315 {
2316 if (opP->reg == PC)
2317 {
2318 if (opP->disp.size == SIZE_LONG
2319 #ifdef OBJ_ELF
2320 /* If the displacement needs pic
2321 relocation it cannot be relaxed. */
2322 || opP->disp.pic_reloc != pic_none
2323 #endif
2324 )
2325 {
2326 addword (0x0170);
2327 add_fix ('l', &opP->disp, 1, 2);
2328 }
2329 else
2330 {
2331 add_frag (adds (&opP->disp),
2332 offs (&opP->disp),
2333 TAB (PCREL1632, SZ_UNDEF));
2334 break;
2335 }
2336 }
2337 else
2338 {
2339 addword (0x0170);
2340 add_fix ('l', &opP->disp, 0, 0);
2341 }
2342 }
2343 else
2344 addword (0x0170);
2345 addword (nextword >> 16);
2346 }
2347 else
2348 {
2349 if (opP->reg == PC)
2350 tmpreg = 0x3A; /* 7.2 */
2351 else
2352 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2353
2354 if (isvar (&opP->disp))
2355 {
2356 if (opP->reg == PC)
2357 {
2358 add_fix ('w', &opP->disp, 1, 0);
2359 }
2360 else
2361 add_fix ('w', &opP->disp, 0, 0);
2362 }
2363 }
2364 addword (nextword);
2365 break;
2366
2367 case POST:
2368 case PRE:
2369 case BASE:
2370 nextword = 0;
2371 baseo = get_num (&opP->disp, 90);
2372 if (opP->mode == POST || opP->mode == PRE)
2373 outro = get_num (&opP->odisp, 90);
2374 /* Figure out the `addressing mode'.
2375 Also turn on the BASE_DISABLE bit, if needed. */
2376 if (opP->reg == PC || opP->reg == ZPC)
2377 {
2378 tmpreg = 0x3b; /* 7.3 */
2379 if (opP->reg == ZPC)
2380 nextword |= 0x80;
2381 }
2382 else if (opP->reg == 0)
2383 {
2384 nextword |= 0x80;
2385 tmpreg = 0x30; /* 6.garbage */
2386 }
2387 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2388 {
2389 nextword |= 0x80;
2390 tmpreg = 0x30 + opP->reg - ZADDR0;
2391 }
2392 else
2393 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2394
2395 siz1 = opP->disp.size;
2396 if (opP->mode == POST || opP->mode == PRE)
2397 siz2 = opP->odisp.size;
2398 else
2399 siz2 = SIZE_UNSPEC;
2400
2401 /* Index register stuff. */
2402 if (opP->index.reg != 0
2403 && opP->index.reg >= DATA
2404 && opP->index.reg <= ADDR7)
2405 {
2406 nextword |= (opP->index.reg - DATA) << 12;
2407
2408 if (opP->index.size == SIZE_LONG
2409 || (opP->index.size == SIZE_UNSPEC
2410 && m68k_index_width_default == SIZE_LONG))
2411 nextword |= 0x800;
2412
2413 if ((opP->index.scale != 1
2414 && cpu_of_arch (current_architecture) < m68020)
2415 || (opP->index.scale == 8
2416 && (arch_coldfire_p (current_architecture)
2417 && !arch_coldfire_fpu (current_architecture))))
2418 {
2419 opP->error =
2420 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2421 }
2422
2423 if (arch_coldfire_p (current_architecture)
2424 && opP->index.size == SIZE_WORD)
2425 opP->error = _("invalid index size for coldfire");
2426
2427 switch (opP->index.scale)
2428 {
2429 case 1:
2430 break;
2431 case 2:
2432 nextword |= 0x200;
2433 break;
2434 case 4:
2435 nextword |= 0x400;
2436 break;
2437 case 8:
2438 nextword |= 0x600;
2439 break;
2440 default:
2441 abort ();
2442 }
2443 /* IF its simple,
2444 GET US OUT OF HERE! */
2445
2446 /* Must be INDEX, with an index register. Address
2447 register cannot be ZERO-PC, and either :b was
2448 forced, or we know it will fit. For a 68000 or
2449 68010, force this mode anyways, because the
2450 larger modes aren't supported. */
2451 if (opP->mode == BASE
2452 && ((opP->reg >= ADDR0
2453 && opP->reg <= ADDR7)
2454 || opP->reg == PC))
2455 {
2456 if (siz1 == SIZE_BYTE
2457 || cpu_of_arch (current_architecture) < m68020
2458 || arch_coldfire_p (current_architecture)
2459 || (siz1 == SIZE_UNSPEC
2460 && ! isvar (&opP->disp)
2461 && issbyte (baseo)))
2462 {
2463 nextword += baseo & 0xff;
2464 addword (nextword);
2465 if (isvar (&opP->disp))
2466 {
2467 /* Do a byte relocation. If it doesn't
2468 fit (possible on m68000) let the
2469 fixup processing complain later. */
2470 if (opP->reg == PC)
2471 add_fix ('B', &opP->disp, 1, 1);
2472 else
2473 add_fix ('B', &opP->disp, 0, 0);
2474 }
2475 else if (siz1 != SIZE_BYTE)
2476 {
2477 if (siz1 != SIZE_UNSPEC)
2478 as_warn (_("Forcing byte displacement"));
2479 if (! issbyte (baseo))
2480 opP->error = _("byte displacement out of range");
2481 }
2482
2483 break;
2484 }
2485 else if (siz1 == SIZE_UNSPEC
2486 && opP->reg == PC
2487 && isvar (&opP->disp)
2488 && subs (&opP->disp) == NULL
2489 #ifdef OBJ_ELF
2490 /* If the displacement needs pic
2491 relocation it cannot be relaxed. */
2492 && opP->disp.pic_reloc == pic_none
2493 #endif
2494 )
2495 {
2496 /* The code in md_convert_frag_1 needs to be
2497 able to adjust nextword. Call frag_grow
2498 to ensure that we have enough space in
2499 the frag obstack to make all the bytes
2500 contiguous. */
2501 frag_grow (14);
2502 nextword += baseo & 0xff;
2503 addword (nextword);
2504 add_frag (adds (&opP->disp), offs (&opP->disp),
2505 TAB (PCINDEX, SZ_UNDEF));
2506
2507 break;
2508 }
2509 }
2510 }
2511 else
2512 {
2513 nextword |= 0x40; /* No index reg. */
2514 if (opP->index.reg >= ZDATA0
2515 && opP->index.reg <= ZDATA7)
2516 nextword |= (opP->index.reg - ZDATA0) << 12;
2517 else if (opP->index.reg >= ZADDR0
2518 || opP->index.reg <= ZADDR7)
2519 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2520 }
2521
2522 /* It isn't simple. */
2523
2524 if (cpu_of_arch (current_architecture) < m68020
2525 || arch_coldfire_p (current_architecture))
2526 opP->error =
2527 _("invalid operand mode for this architecture; needs 68020 or higher");
2528
2529 nextword |= 0x100;
2530 /* If the guy specified a width, we assume that it is
2531 wide enough. Maybe it isn't. If so, we lose. */
2532 switch (siz1)
2533 {
2534 case SIZE_UNSPEC:
2535 if (isvar (&opP->disp)
2536 ? m68k_rel32
2537 : ! issword (baseo))
2538 {
2539 siz1 = SIZE_LONG;
2540 nextword |= 0x30;
2541 }
2542 else if (! isvar (&opP->disp) && baseo == 0)
2543 nextword |= 0x10;
2544 else
2545 {
2546 nextword |= 0x20;
2547 siz1 = SIZE_WORD;
2548 }
2549 break;
2550 case SIZE_BYTE:
2551 as_warn (_(":b not permitted; defaulting to :w"));
2552 /* Fall through. */
2553 case SIZE_WORD:
2554 nextword |= 0x20;
2555 break;
2556 case SIZE_LONG:
2557 nextword |= 0x30;
2558 break;
2559 }
2560
2561 /* Figure out inner displacement stuff. */
2562 if (opP->mode == POST || opP->mode == PRE)
2563 {
2564 if (cpu_of_arch (current_architecture) & cpu32)
2565 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2566 switch (siz2)
2567 {
2568 case SIZE_UNSPEC:
2569 if (isvar (&opP->odisp)
2570 ? m68k_rel32
2571 : ! issword (outro))
2572 {
2573 siz2 = SIZE_LONG;
2574 nextword |= 0x3;
2575 }
2576 else if (! isvar (&opP->odisp) && outro == 0)
2577 nextword |= 0x1;
2578 else
2579 {
2580 nextword |= 0x2;
2581 siz2 = SIZE_WORD;
2582 }
2583 break;
2584 case 1:
2585 as_warn (_(":b not permitted; defaulting to :w"));
2586 /* Fall through. */
2587 case 2:
2588 nextword |= 0x2;
2589 break;
2590 case 3:
2591 nextword |= 0x3;
2592 break;
2593 }
2594 if (opP->mode == POST
2595 && (nextword & 0x40) == 0)
2596 nextword |= 0x04;
2597 }
2598 addword (nextword);
2599
2600 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2601 {
2602 if (opP->reg == PC || opP->reg == ZPC)
2603 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2604 else
2605 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2606 }
2607 if (siz1 == SIZE_LONG)
2608 addword (baseo >> 16);
2609 if (siz1 != SIZE_UNSPEC)
2610 addword (baseo);
2611
2612 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2613 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2614 if (siz2 == SIZE_LONG)
2615 addword (outro >> 16);
2616 if (siz2 != SIZE_UNSPEC)
2617 addword (outro);
2618
2619 break;
2620
2621 case ABSL:
2622 nextword = get_num (&opP->disp, 90);
2623 switch (opP->disp.size)
2624 {
2625 default:
2626 abort ();
2627 case SIZE_UNSPEC:
2628 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2629 {
2630 tmpreg = 0x38; /* 7.0 */
2631 addword (nextword);
2632 break;
2633 }
2634 if (isvar (&opP->disp)
2635 && !subs (&opP->disp)
2636 && adds (&opP->disp)
2637 #ifdef OBJ_ELF
2638 /* If the displacement needs pic relocation it
2639 cannot be relaxed. */
2640 && opP->disp.pic_reloc == pic_none
2641 #endif
2642 && !flag_long_jumps
2643 && !strchr ("~%&$?", s[0]))
2644 {
2645 tmpreg = 0x3A; /* 7.2 */
2646 add_frag (adds (&opP->disp),
2647 offs (&opP->disp),
2648 TAB (ABSTOPCREL, SZ_UNDEF));
2649 break;
2650 }
2651 /* Fall through into long. */
2652 case SIZE_LONG:
2653 if (isvar (&opP->disp))
2654 add_fix ('l', &opP->disp, 0, 0);
2655
2656 tmpreg = 0x39;/* 7.1 mode */
2657 addword (nextword >> 16);
2658 addword (nextword);
2659 break;
2660
2661 case SIZE_BYTE:
2662 as_bad (_("unsupported byte value; use a different suffix"));
2663 /* Fall through. */
2664
2665 case SIZE_WORD:
2666 if (isvar (&opP->disp))
2667 add_fix ('w', &opP->disp, 0, 0);
2668
2669 tmpreg = 0x38;/* 7.0 mode */
2670 addword (nextword);
2671 break;
2672 }
2673 break;
2674 case CONTROL:
2675 case FPREG:
2676 default:
2677 as_bad (_("unknown/incorrect operand"));
2678 /* abort (); */
2679 }
2680
2681 /* If s[0] is '4', then this is for the mac instructions
2682 that can have a trailing_ampersand set. If so, set 0x100
2683 bit on tmpreg so install_gen_operand can check for it and
2684 set the appropriate bit (word2, bit 5). */
2685 if (s[0] == '4')
2686 {
2687 if (opP->trailing_ampersand)
2688 tmpreg |= 0x100;
2689 }
2690 install_gen_operand (s[1], tmpreg);
2691 break;
2692
2693 case '#':
2694 case '^':
2695 switch (s[1])
2696 { /* JF: I hate floating point! */
2697 case 'j':
2698 tmpreg = 70;
2699 break;
2700 case '8':
2701 tmpreg = 20;
2702 break;
2703 case 'C':
2704 tmpreg = 50;
2705 break;
2706 case '3':
2707 default:
2708 tmpreg = 90;
2709 break;
2710 }
2711 tmpreg = get_num (&opP->disp, tmpreg);
2712 if (isvar (&opP->disp))
2713 add_fix (s[1], &opP->disp, 0, 0);
2714 switch (s[1])
2715 {
2716 case 'b': /* Danger: These do no check for
2717 certain types of overflow.
2718 user beware! */
2719 if (!isbyte (tmpreg))
2720 opP->error = _("out of range");
2721 insop (tmpreg, opcode);
2722 if (isvar (&opP->disp))
2723 the_ins.reloc[the_ins.nrel - 1].n =
2724 (opcode->m_codenum) * 2 + 1;
2725 break;
2726 case 'B':
2727 if (!issbyte (tmpreg))
2728 opP->error = _("out of range");
2729 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2730 if (isvar (&opP->disp))
2731 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2732 break;
2733 case 'w':
2734 if (!isword (tmpreg))
2735 opP->error = _("out of range");
2736 insop (tmpreg, opcode);
2737 if (isvar (&opP->disp))
2738 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2739 break;
2740 case 'W':
2741 if (!issword (tmpreg))
2742 opP->error = _("out of range");
2743 insop (tmpreg, opcode);
2744 if (isvar (&opP->disp))
2745 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2746 break;
2747 case 'l':
2748 /* Because of the way insop works, we put these two out
2749 backwards. */
2750 insop (tmpreg, opcode);
2751 insop (tmpreg >> 16, opcode);
2752 if (isvar (&opP->disp))
2753 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2754 break;
2755 case '3':
2756 tmpreg &= 0xFF;
2757 case '8':
2758 case 'C':
2759 case 'j':
2760 install_operand (s[1], tmpreg);
2761 break;
2762 default:
2763 abort ();
2764 }
2765 break;
2766
2767 case '+':
2768 case '-':
2769 case 'A':
2770 case 'a':
2771 install_operand (s[1], opP->reg - ADDR);
2772 break;
2773
2774 case 'B':
2775 tmpreg = get_num (&opP->disp, 90);
2776 switch (s[1])
2777 {
2778 case 'B':
2779 add_fix ('B', &opP->disp, 1, -1);
2780 break;
2781 case 'W':
2782 add_fix ('w', &opP->disp, 1, 0);
2783 addword (0);
2784 break;
2785 case 'L':
2786 long_branch:
2787 if (! HAVE_LONG_BRANCH (current_architecture))
2788 as_warn (_("Can't use long branches on 68000/68010/5200"));
2789 the_ins.opcode[0] |= 0xff;
2790 add_fix ('l', &opP->disp, 1, 0);
2791 addword (0);
2792 addword (0);
2793 break;
2794 case 'g':
2795 if (subs (&opP->disp)) /* We can't relax it. */
2796 goto long_branch;
2797
2798 #ifdef OBJ_ELF
2799 /* If the displacement needs pic relocation it cannot be
2800 relaxed. */
2801 if (opP->disp.pic_reloc != pic_none)
2802 goto long_branch;
2803 #endif
2804 /* This could either be a symbol, or an absolute
2805 address. If it's an absolute address, turn it into
2806 an absolute jump right here and keep it out of the
2807 relaxer. */
2808 if (adds (&opP->disp) == 0)
2809 {
2810 if (the_ins.opcode[0] == 0x6000) /* jbra */
2811 the_ins.opcode[0] = 0x4EF9;
2812 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2813 the_ins.opcode[0] = 0x4EB9;
2814 else /* jCC */
2815 {
2816 the_ins.opcode[0] ^= 0x0100;
2817 the_ins.opcode[0] |= 0x0006;
2818 addword (0x4EF9);
2819 }
2820 add_fix ('l', &opP->disp, 0, 0);
2821 addword (0);
2822 addword (0);
2823 break;
2824 }
2825
2826 /* Now we know it's going into the relaxer. Now figure
2827 out which mode. We try in this order of preference:
2828 long branch, absolute jump, byte/word branches only. */
2829 if (HAVE_LONG_BRANCH (current_architecture))
2830 add_frag (adds (&opP->disp), offs (&opP->disp),
2831 TAB (BRANCHBWL, SZ_UNDEF));
2832 else if (! flag_keep_pcrel)
2833 {
2834 if ((the_ins.opcode[0] == 0x6000)
2835 || (the_ins.opcode[0] == 0x6100))
2836 add_frag (adds (&opP->disp), offs (&opP->disp),
2837 TAB (BRABSJUNC, SZ_UNDEF));
2838 else
2839 add_frag (adds (&opP->disp), offs (&opP->disp),
2840 TAB (BRABSJCOND, SZ_UNDEF));
2841 }
2842 else
2843 add_frag (adds (&opP->disp), offs (&opP->disp),
2844 TAB (BRANCHBW, SZ_UNDEF));
2845 break;
2846 case 'w':
2847 if (isvar (&opP->disp))
2848 {
2849 /* Check for DBcc instructions. We can relax them,
2850 but only if we have long branches and/or absolute
2851 jumps. */
2852 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2853 && (HAVE_LONG_BRANCH (current_architecture)
2854 || (! flag_keep_pcrel)))
2855 {
2856 if (HAVE_LONG_BRANCH (current_architecture))
2857 add_frag (adds (&opP->disp), offs (&opP->disp),
2858 TAB (DBCCLBR, SZ_UNDEF));
2859 else
2860 add_frag (adds (&opP->disp), offs (&opP->disp),
2861 TAB (DBCCABSJ, SZ_UNDEF));
2862 break;
2863 }
2864 add_fix ('w', &opP->disp, 1, 0);
2865 }
2866 addword (0);
2867 break;
2868 case 'C': /* Fixed size LONG coproc branches. */
2869 add_fix ('l', &opP->disp, 1, 0);
2870 addword (0);
2871 addword (0);
2872 break;
2873 case 'c': /* Var size Coprocesssor branches. */
2874 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2875 {
2876 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2877 add_fix ('l', &opP->disp, 1, 0);
2878 addword (0);
2879 addword (0);
2880 }
2881 else
2882 add_frag (adds (&opP->disp), offs (&opP->disp),
2883 TAB (FBRANCH, SZ_UNDEF));
2884 break;
2885 default:
2886 abort ();
2887 }
2888 break;
2889
2890 case 'C': /* Ignore it. */
2891 break;
2892
2893 case 'd': /* JF this is a kludge. */
2894 install_operand ('s', opP->reg - ADDR);
2895 tmpreg = get_num (&opP->disp, 90);
2896 if (!issword (tmpreg))
2897 {
2898 as_warn (_("Expression out of range, using 0"));
2899 tmpreg = 0;
2900 }
2901 addword (tmpreg);
2902 break;
2903
2904 case 'D':
2905 install_operand (s[1], opP->reg - DATA);
2906 break;
2907
2908 case 'e': /* EMAC ACCx, reg/reg. */
2909 install_operand (s[1], opP->reg - ACC);
2910 break;
2911
2912 case 'E': /* Ignore it. */
2913 break;
2914
2915 case 'F':
2916 install_operand (s[1], opP->reg - FP0);
2917 break;
2918
2919 case 'g': /* EMAC ACCEXTx. */
2920 install_operand (s[1], opP->reg - ACCEXT01);
2921 break;
2922
2923 case 'G': /* Ignore it. */
2924 case 'H':
2925 break;
2926
2927 case 'I':
2928 tmpreg = opP->reg - COP0;
2929 install_operand (s[1], tmpreg);
2930 break;
2931
2932 case 'i': /* MAC/EMAC scale factor. */
2933 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2934 break;
2935
2936 case 'J': /* JF foo. */
2937 switch (opP->reg)
2938 {
2939 case SFC:
2940 tmpreg = 0x000;
2941 break;
2942 case DFC:
2943 tmpreg = 0x001;
2944 break;
2945 case CACR:
2946 tmpreg = 0x002;
2947 break;
2948 case TC:
2949 tmpreg = 0x003;
2950 break;
2951 case ACR0:
2952 case ITT0:
2953 tmpreg = 0x004;
2954 break;
2955 case ACR1:
2956 case ITT1:
2957 tmpreg = 0x005;
2958 break;
2959 case ACR2:
2960 case DTT0:
2961 tmpreg = 0x006;
2962 break;
2963 case ACR3:
2964 case DTT1:
2965 tmpreg = 0x007;
2966 break;
2967 case BUSCR:
2968 tmpreg = 0x008;
2969 break;
2970
2971 case USP:
2972 tmpreg = 0x800;
2973 break;
2974 case VBR:
2975 tmpreg = 0x801;
2976 break;
2977 case CAAR:
2978 tmpreg = 0x802;
2979 break;
2980 case MSP:
2981 tmpreg = 0x803;
2982 break;
2983 case ISP:
2984 tmpreg = 0x804;
2985 break;
2986 case MMUSR:
2987 tmpreg = 0x805;
2988 break;
2989 case URP:
2990 tmpreg = 0x806;
2991 break;
2992 case SRP:
2993 tmpreg = 0x807;
2994 break;
2995 case PCR:
2996 tmpreg = 0x808;
2997 break;
2998 case ROMBAR:
2999 tmpreg = 0xC00;
3000 break;
3001 case ROMBAR1:
3002 tmpreg = 0xC01;
3003 break;
3004 case FLASHBAR:
3005 case RAMBAR0:
3006 tmpreg = 0xC04;
3007 break;
3008 case RAMBAR:
3009 case RAMBAR1:
3010 tmpreg = 0xC05;
3011 break;
3012 case MPCR:
3013 tmpreg = 0xC0C;
3014 break;
3015 case EDRAMBAR:
3016 tmpreg = 0xC0D;
3017 break;
3018 case MBAR0:
3019 case SECMBAR:
3020 tmpreg = 0xC0E;
3021 break;
3022 case MBAR1:
3023 case MBAR:
3024 tmpreg = 0xC0F;
3025 break;
3026 case PCR1U0:
3027 tmpreg = 0xD02;
3028 break;
3029 case PCR1L0:
3030 tmpreg = 0xD03;
3031 break;
3032 case PCR2U0:
3033 tmpreg = 0xD04;
3034 break;
3035 case PCR2L0:
3036 tmpreg = 0xD05;
3037 break;
3038 case PCR3U0:
3039 tmpreg = 0xD06;
3040 break;
3041 case PCR3L0:
3042 tmpreg = 0xD07;
3043 break;
3044 case PCR1L1:
3045 tmpreg = 0xD0A;
3046 break;
3047 case PCR1U1:
3048 tmpreg = 0xD0B;
3049 break;
3050 case PCR2L1:
3051 tmpreg = 0xD0C;
3052 break;
3053 case PCR2U1:
3054 tmpreg = 0xD0D;
3055 break;
3056 case PCR3L1:
3057 tmpreg = 0xD0E;
3058 break;
3059 case PCR3U1:
3060 tmpreg = 0xD0F;
3061 break;
3062 default:
3063 abort ();
3064 }
3065 install_operand (s[1], tmpreg);
3066 break;
3067
3068 case 'k':
3069 tmpreg = get_num (&opP->disp, 55);
3070 install_operand (s[1], tmpreg & 0x7f);
3071 break;
3072
3073 case 'l':
3074 tmpreg = opP->mask;
3075 if (s[1] == 'w')
3076 {
3077 if (tmpreg & 0x7FF0000)
3078 as_bad (_("Floating point register in register list"));
3079 insop (reverse_16_bits (tmpreg), opcode);
3080 }
3081 else
3082 {
3083 if (tmpreg & 0x700FFFF)
3084 as_bad (_("Wrong register in floating-point reglist"));
3085 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3086 }
3087 break;
3088
3089 case 'L':
3090 tmpreg = opP->mask;
3091 if (s[1] == 'w')
3092 {
3093 if (tmpreg & 0x7FF0000)
3094 as_bad (_("Floating point register in register list"));
3095 insop (tmpreg, opcode);
3096 }
3097 else if (s[1] == '8')
3098 {
3099 if (tmpreg & 0x0FFFFFF)
3100 as_bad (_("incorrect register in reglist"));
3101 install_operand (s[1], tmpreg >> 24);
3102 }
3103 else
3104 {
3105 if (tmpreg & 0x700FFFF)
3106 as_bad (_("wrong register in floating-point reglist"));
3107 else
3108 install_operand (s[1], tmpreg >> 16);
3109 }
3110 break;
3111
3112 case 'M':
3113 install_operand (s[1], get_num (&opP->disp, 60));
3114 break;
3115
3116 case 'O':
3117 tmpreg = ((opP->mode == DREG)
3118 ? 0x20 + (int) (opP->reg - DATA)
3119 : (get_num (&opP->disp, 40) & 0x1F));
3120 install_operand (s[1], tmpreg);
3121 break;
3122
3123 case 'Q':
3124 tmpreg = get_num (&opP->disp, 10);
3125 if (tmpreg == 8)
3126 tmpreg = 0;
3127 install_operand (s[1], tmpreg);
3128 break;
3129
3130 case 'R':
3131 /* This depends on the fact that ADDR registers are eight
3132 more than their corresponding DATA regs, so the result
3133 will have the ADDR_REG bit set. */
3134 install_operand (s[1], opP->reg - DATA);
3135 break;
3136
3137 case 'r':
3138 if (opP->mode == AINDR)
3139 install_operand (s[1], opP->reg - DATA);
3140 else
3141 install_operand (s[1], opP->index.reg - DATA);
3142 break;
3143
3144 case 's':
3145 if (opP->reg == FPI)
3146 tmpreg = 0x1;
3147 else if (opP->reg == FPS)
3148 tmpreg = 0x2;
3149 else if (opP->reg == FPC)
3150 tmpreg = 0x4;
3151 else
3152 abort ();
3153 install_operand (s[1], tmpreg);
3154 break;
3155
3156 case 'S': /* Ignore it. */
3157 break;
3158
3159 case 'T':
3160 install_operand (s[1], get_num (&opP->disp, 30));
3161 break;
3162
3163 case 'U': /* Ignore it. */
3164 break;
3165
3166 case 'c':
3167 switch (opP->reg)
3168 {
3169 case NC:
3170 tmpreg = 0;
3171 break;
3172 case DC:
3173 tmpreg = 1;
3174 break;
3175 case IC:
3176 tmpreg = 2;
3177 break;
3178 case BC:
3179 tmpreg = 3;
3180 break;
3181 default:
3182 as_fatal (_("failed sanity check"));
3183 } /* switch on cache token. */
3184 install_operand (s[1], tmpreg);
3185 break;
3186 #ifndef NO_68851
3187 /* JF: These are out of order, I fear. */
3188 case 'f':
3189 switch (opP->reg)
3190 {
3191 case SFC:
3192 tmpreg = 0;
3193 break;
3194 case DFC:
3195 tmpreg = 1;
3196 break;
3197 default:
3198 abort ();
3199 }
3200 install_operand (s[1], tmpreg);
3201 break;
3202
3203 case '0':
3204 case '1':
3205 case '2':
3206 switch (opP->reg)
3207 {
3208 case TC:
3209 tmpreg = 0;
3210 break;
3211 case CAL:
3212 tmpreg = 4;
3213 break;
3214 case VAL:
3215 tmpreg = 5;
3216 break;
3217 case SCC:
3218 tmpreg = 6;
3219 break;
3220 case AC:
3221 tmpreg = 7;
3222 break;
3223 default:
3224 abort ();
3225 }
3226 install_operand (s[1], tmpreg);
3227 break;
3228
3229 case 'V':
3230 if (opP->reg == VAL)
3231 break;
3232 abort ();
3233
3234 case 'W':
3235 switch (opP->reg)
3236 {
3237 case DRP:
3238 tmpreg = 1;
3239 break;
3240 case SRP:
3241 tmpreg = 2;
3242 break;
3243 case CRP:
3244 tmpreg = 3;
3245 break;
3246 default:
3247 abort ();
3248 }
3249 install_operand (s[1], tmpreg);
3250 break;
3251
3252 case 'X':
3253 switch (opP->reg)
3254 {
3255 case BAD:
3256 case BAD + 1:
3257 case BAD + 2:
3258 case BAD + 3:
3259 case BAD + 4:
3260 case BAD + 5:
3261 case BAD + 6:
3262 case BAD + 7:
3263 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3264 break;
3265
3266 case BAC:
3267 case BAC + 1:
3268 case BAC + 2:
3269 case BAC + 3:
3270 case BAC + 4:
3271 case BAC + 5:
3272 case BAC + 6:
3273 case BAC + 7:
3274 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3275 break;
3276
3277 default:
3278 abort ();
3279 }
3280 install_operand (s[1], tmpreg);
3281 break;
3282 case 'Y':
3283 know (opP->reg == PSR);
3284 break;
3285 case 'Z':
3286 know (opP->reg == PCSR);
3287 break;
3288 #endif /* m68851 */
3289 case '3':
3290 switch (opP->reg)
3291 {
3292 case TT0:
3293 tmpreg = 2;
3294 break;
3295 case TT1:
3296 tmpreg = 3;
3297 break;
3298 default:
3299 abort ();
3300 }
3301 install_operand (s[1], tmpreg);
3302 break;
3303 case 't':
3304 tmpreg = get_num (&opP->disp, 20);
3305 install_operand (s[1], tmpreg);
3306 break;
3307 case '_': /* used only for move16 absolute 32-bit address. */
3308 if (isvar (&opP->disp))
3309 add_fix ('l', &opP->disp, 0, 0);
3310 tmpreg = get_num (&opP->disp, 90);
3311 addword (tmpreg >> 16);
3312 addword (tmpreg & 0xFFFF);
3313 break;
3314 case 'u':
3315 install_operand (s[1], opP->reg - DATA0L);
3316 opP->reg -= (DATA0L);
3317 opP->reg &= 0x0F; /* remove upper/lower bit. */
3318 break;
3319 case 'x':
3320 tmpreg = get_num (&opP->disp, 80);
3321 if (tmpreg == -1)
3322 tmpreg = 0;
3323 install_operand (s[1], tmpreg);
3324 break;
3325 default:
3326 abort ();
3327 }
3328 }
3329
3330 /* By the time whe get here (FINALLY) the_ins contains the complete
3331 instruction, ready to be emitted. . . */
3332 }
3333
3334 static int
3335 reverse_16_bits (in)
3336 int in;
3337 {
3338 int out = 0;
3339 int n;
3340
3341 static int mask[16] =
3342 {
3343 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3344 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3345 };
3346 for (n = 0; n < 16; n++)
3347 {
3348 if (in & mask[n])
3349 out |= mask[15 - n];
3350 }
3351 return out;
3352 } /* reverse_16_bits() */
3353
3354 static int
3355 reverse_8_bits (in)
3356 int in;
3357 {
3358 int out = 0;
3359 int n;
3360
3361 static int mask[8] =
3362 {
3363 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3364 };
3365
3366 for (n = 0; n < 8; n++)
3367 {
3368 if (in & mask[n])
3369 out |= mask[7 - n];
3370 }
3371 return out;
3372 } /* reverse_8_bits() */
3373
3374 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3375 (that value is chosen in the frag_var call in md_assemble). TYPE
3376 is the subtype of the frag to be generated; its primary type is
3377 rs_machine_dependent.
3378
3379 The TYPE parameter is also used by md_convert_frag_1 and
3380 md_estimate_size_before_relax. The appropriate type of fixup will
3381 be emitted by md_convert_frag_1.
3382
3383 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3384 static void
3385 install_operand (mode, val)
3386 int mode;
3387 int val;
3388 {
3389 switch (mode)
3390 {
3391 case 's':
3392 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3393 break;
3394 case 'd':
3395 the_ins.opcode[0] |= val << 9;
3396 break;
3397 case '1':
3398 the_ins.opcode[1] |= val << 12;
3399 break;
3400 case '2':
3401 the_ins.opcode[1] |= val << 6;
3402 break;
3403 case '3':
3404 the_ins.opcode[1] |= val;
3405 break;
3406 case '4':
3407 the_ins.opcode[2] |= val << 12;
3408 break;
3409 case '5':
3410 the_ins.opcode[2] |= val << 6;
3411 break;
3412 case '6':
3413 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3414 three words long! */
3415 the_ins.numo++;
3416 the_ins.opcode[2] |= val;
3417 break;
3418 case '7':
3419 the_ins.opcode[1] |= val << 7;
3420 break;
3421 case '8':
3422 the_ins.opcode[1] |= val << 10;
3423 break;
3424 #ifndef NO_68851
3425 case '9':
3426 the_ins.opcode[1] |= val << 5;
3427 break;
3428 #endif
3429
3430 case 't':
3431 the_ins.opcode[1] |= (val << 10) | (val << 7);
3432 break;
3433 case 'D':
3434 the_ins.opcode[1] |= (val << 12) | val;
3435 break;
3436 case 'g':
3437 the_ins.opcode[0] |= val = 0xff;
3438 break;
3439 case 'i':
3440 the_ins.opcode[0] |= val << 9;
3441 break;
3442 case 'C':
3443 the_ins.opcode[1] |= val;
3444 break;
3445 case 'j':
3446 the_ins.opcode[1] |= val;
3447 the_ins.numo++; /* What a hack. */
3448 break;
3449 case 'k':
3450 the_ins.opcode[1] |= val << 4;
3451 break;
3452 case 'b':
3453 case 'w':
3454 case 'W':
3455 case 'l':
3456 break;
3457 case 'e':
3458 the_ins.opcode[0] |= (val << 6);
3459 break;
3460 case 'L':
3461 the_ins.opcode[1] = (val >> 16);
3462 the_ins.opcode[2] = val & 0xffff;
3463 break;
3464 case 'm':
3465 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3466 the_ins.opcode[0] |= ((val & 0x7) << 9);
3467 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3468 break;
3469 case 'n': /* MAC/EMAC Rx on !load. */
3470 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3471 the_ins.opcode[0] |= ((val & 0x7) << 9);
3472 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3473 break;
3474 case 'o': /* MAC/EMAC Rx on load. */
3475 the_ins.opcode[1] |= val << 12;
3476 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3477 break;
3478 case 'M': /* MAC/EMAC Ry on !load. */
3479 the_ins.opcode[0] |= (val & 0xF);
3480 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3481 break;
3482 case 'N': /* MAC/EMAC Ry on load. */
3483 the_ins.opcode[1] |= (val & 0xF);
3484 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3485 break;
3486 case 'h':
3487 the_ins.opcode[1] |= ((val != 1) << 10);
3488 break;
3489 case 'F':
3490 the_ins.opcode[0] |= ((val & 0x3) << 9);
3491 break;
3492 case 'f':
3493 the_ins.opcode[0] |= ((val & 0x3) << 0);
3494 break;
3495 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3496 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3497 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3498 break;
3499 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3500 the_ins.opcode[0] |= ((val & 0x1) << 7);
3501 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3502 break;
3503 case 'I':
3504 the_ins.opcode[1] |= ((val & 0x3) << 9);
3505 break;
3506 case ']':
3507 the_ins.opcode[0] |= (val & 0x1) <<10;
3508 break;
3509 case 'c':
3510 default:
3511 as_fatal (_("failed sanity check."));
3512 }
3513 }
3514
3515 static void
3516 install_gen_operand (mode, val)
3517 int mode;
3518 int val;
3519 {
3520 switch (mode)
3521 {
3522 case '/': /* Special for mask loads for mac/msac insns with
3523 possible mask; trailing_ampersend set in bit 8. */
3524 the_ins.opcode[0] |= (val & 0x3f);
3525 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3526 break;
3527 case 's':
3528 the_ins.opcode[0] |= val;
3529 break;
3530 case 'd':
3531 /* This is a kludge!!! */
3532 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3533 break;
3534 case 'b':
3535 case 'w':
3536 case 'l':
3537 case 'f':
3538 case 'F':
3539 case 'x':
3540 case 'p':
3541 the_ins.opcode[0] |= val;
3542 break;
3543 /* more stuff goes here. */
3544 default:
3545 as_fatal (_("failed sanity check."));
3546 }
3547 }
3548
3549 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3550 then deal with the bitfield hack. */
3551
3552 static char *
3553 crack_operand (str, opP)
3554 register char *str;
3555 register struct m68k_op *opP;
3556 {
3557 register int parens;
3558 register int c;
3559 register char *beg_str;
3560 int inquote = 0;
3561
3562 if (!str)
3563 {
3564 return str;
3565 }
3566 beg_str = str;
3567 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3568 {
3569 if (! inquote)
3570 {
3571 if (*str == '(')
3572 parens++;
3573 else if (*str == ')')
3574 {
3575 if (!parens)
3576 { /* ERROR. */
3577 opP->error = _("Extra )");
3578 return str;
3579 }
3580 --parens;
3581 }
3582 }
3583 if (flag_mri && *str == '\'')
3584 inquote = ! inquote;
3585 }
3586 if (!*str && parens)
3587 { /* ERROR. */
3588 opP->error = _("Missing )");
3589 return str;
3590 }
3591 c = *str;
3592 *str = '\0';
3593 if (m68k_ip_op (beg_str, opP) != 0)
3594 {
3595 *str = c;
3596 return str;
3597 }
3598 *str = c;
3599 if (c == '}')
3600 c = *++str; /* JF bitfield hack. */
3601 if (c)
3602 {
3603 c = *++str;
3604 if (!c)
3605 as_bad (_("Missing operand"));
3606 }
3607
3608 /* Detect MRI REG symbols and convert them to REGLSTs. */
3609 if (opP->mode == CONTROL && (int)opP->reg < 0)
3610 {
3611 opP->mode = REGLST;
3612 opP->mask = ~(int)opP->reg;
3613 opP->reg = 0;
3614 }
3615
3616 return str;
3617 }
3618
3619 /* This is the guts of the machine-dependent assembler. STR points to a
3620 machine dependent instruction. This function is supposed to emit
3621 the frags/bytes it assembles to.
3622 */
3623
3624 static void
3625 insert_reg (regname, regnum)
3626 const char *regname;
3627 int regnum;
3628 {
3629 char buf[100];
3630 int i;
3631
3632 #ifdef REGISTER_PREFIX
3633 if (!flag_reg_prefix_optional)
3634 {
3635 buf[0] = REGISTER_PREFIX;
3636 strcpy (buf + 1, regname);
3637 regname = buf;
3638 }
3639 #endif
3640
3641 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3642 &zero_address_frag));
3643
3644 for (i = 0; regname[i]; i++)
3645 buf[i] = TOUPPER (regname[i]);
3646 buf[i] = '\0';
3647
3648 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3649 &zero_address_frag));
3650 }
3651
3652 struct init_entry
3653 {
3654 const char *name;
3655 int number;
3656 };
3657
3658 static const struct init_entry init_table[] =
3659 {
3660 { "d0", DATA0 },
3661 { "d1", DATA1 },
3662 { "d2", DATA2 },
3663 { "d3", DATA3 },
3664 { "d4", DATA4 },
3665 { "d5", DATA5 },
3666 { "d6", DATA6 },
3667 { "d7", DATA7 },
3668 { "a0", ADDR0 },
3669 { "a1", ADDR1 },
3670 { "a2", ADDR2 },
3671 { "a3", ADDR3 },
3672 { "a4", ADDR4 },
3673 { "a5", ADDR5 },
3674 { "a6", ADDR6 },
3675 { "fp", ADDR6 },
3676 { "a7", ADDR7 },
3677 { "sp", ADDR7 },
3678 { "ssp", ADDR7 },
3679 { "fp0", FP0 },
3680 { "fp1", FP1 },
3681 { "fp2", FP2 },
3682 { "fp3", FP3 },
3683 { "fp4", FP4 },
3684 { "fp5", FP5 },
3685 { "fp6", FP6 },
3686 { "fp7", FP7 },
3687 { "fpi", FPI },
3688 { "fpiar", FPI },
3689 { "fpc", FPI },
3690 { "fps", FPS },
3691 { "fpsr", FPS },
3692 { "fpc", FPC },
3693 { "fpcr", FPC },
3694 { "control", FPC },
3695 { "status", FPS },
3696 { "iaddr", FPI },
3697
3698 { "cop0", COP0 },
3699 { "cop1", COP1 },
3700 { "cop2", COP2 },
3701 { "cop3", COP3 },
3702 { "cop4", COP4 },
3703 { "cop5", COP5 },
3704 { "cop6", COP6 },
3705 { "cop7", COP7 },
3706 { "pc", PC },
3707 { "zpc", ZPC },
3708 { "sr", SR },
3709
3710 { "ccr", CCR },
3711 { "cc", CCR },
3712
3713 { "acc", ACC },
3714 { "acc0", ACC },
3715 { "acc1", ACC1 },
3716 { "acc2", ACC2 },
3717 { "acc3", ACC3 },
3718 { "accext01", ACCEXT01 },
3719 { "accext23", ACCEXT23 },
3720 { "macsr", MACSR },
3721 { "mask", MASK },
3722
3723 /* Control registers. */
3724 { "sfc", SFC }, /* Source Function Code. */
3725 { "sfcr", SFC },
3726 { "dfc", DFC }, /* Destination Function Code. */
3727 { "dfcr", DFC },
3728 { "cacr", CACR }, /* Cache Control Register. */
3729 { "caar", CAAR }, /* Cache Address Register. */
3730
3731 { "usp", USP }, /* User Stack Pointer. */
3732 { "vbr", VBR }, /* Vector Base Register. */
3733 { "msp", MSP }, /* Master Stack Pointer. */
3734 { "isp", ISP }, /* Interrupt Stack Pointer. */
3735
3736 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3737 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3738 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3739 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3740
3741 /* 68ec040 versions of same */
3742 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3743 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3744 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3745 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3746
3747 /* mcf5200 versions of same. The ColdFire programmer's reference
3748 manual indicated that the order is 2,3,0,1, but Ken Rose
3749 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3750 { "acr0", ACR0 }, /* Access Control Unit 0. */
3751 { "acr1", ACR1 }, /* Access Control Unit 1. */
3752 { "acr2", ACR2 }, /* Access Control Unit 2. */
3753 { "acr3", ACR3 }, /* Access Control Unit 3. */
3754
3755 { "tc", TC }, /* MMU Translation Control Register. */
3756 { "tcr", TC },
3757
3758 { "mmusr", MMUSR }, /* MMU Status Register. */
3759 { "srp", SRP }, /* User Root Pointer. */
3760 { "urp", URP }, /* Supervisor Root Pointer. */
3761
3762 { "buscr", BUSCR },
3763 { "pcr", PCR },
3764
3765 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3766 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3767 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3768 { "mbar", MBAR }, /* Module Base Address Register. */
3769
3770 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3771 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3772 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3773 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3774 { "mpcr", MPCR }, /* mcfv4e registers. */
3775 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3776 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3777 { "asid", TC }, /* mcfv4e registers. */
3778 { "mmubar", BUSCR }, /* mcfv4e registers. */
3779 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3780 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3781 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3782 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3783 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3784 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3785 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3786 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3787 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3788 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3789 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3790 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3791
3792 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3793 { "rambar", RAMBAR }, /* mcf528x registers. */
3794 /* End of control registers. */
3795
3796 { "ac", AC },
3797 { "bc", BC },
3798 { "cal", CAL },
3799 { "crp", CRP },
3800 { "drp", DRP },
3801 { "pcsr", PCSR },
3802 { "psr", PSR },
3803 { "scc", SCC },
3804 { "val", VAL },
3805 { "bad0", BAD0 },
3806 { "bad1", BAD1 },
3807 { "bad2", BAD2 },
3808 { "bad3", BAD3 },
3809 { "bad4", BAD4 },
3810 { "bad5", BAD5 },
3811 { "bad6", BAD6 },
3812 { "bad7", BAD7 },
3813 { "bac0", BAC0 },
3814 { "bac1", BAC1 },
3815 { "bac2", BAC2 },
3816 { "bac3", BAC3 },
3817 { "bac4", BAC4 },
3818 { "bac5", BAC5 },
3819 { "bac6", BAC6 },
3820 { "bac7", BAC7 },
3821
3822 { "ic", IC },
3823 { "dc", DC },
3824 { "nc", NC },
3825
3826 { "tt0", TT0 },
3827 { "tt1", TT1 },
3828 /* 68ec030 versions of same. */
3829 { "ac0", TT0 },
3830 { "ac1", TT1 },
3831 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3832 { "acusr", PSR },
3833
3834 /* Suppressed data and address registers. */
3835 { "zd0", ZDATA0 },
3836 { "zd1", ZDATA1 },
3837 { "zd2", ZDATA2 },
3838 { "zd3", ZDATA3 },
3839 { "zd4", ZDATA4 },
3840 { "zd5", ZDATA5 },
3841 { "zd6", ZDATA6 },
3842 { "zd7", ZDATA7 },
3843 { "za0", ZADDR0 },
3844 { "za1", ZADDR1 },
3845 { "za2", ZADDR2 },
3846 { "za3", ZADDR3 },
3847 { "za4", ZADDR4 },
3848 { "za5", ZADDR5 },
3849 { "za6", ZADDR6 },
3850 { "za7", ZADDR7 },
3851
3852 /* Upper and lower data and address registers, used by macw and msacw. */
3853 { "d0l", DATA0L },
3854 { "d1l", DATA1L },
3855 { "d2l", DATA2L },
3856 { "d3l", DATA3L },
3857 { "d4l", DATA4L },
3858 { "d5l", DATA5L },
3859 { "d6l", DATA6L },
3860 { "d7l", DATA7L },
3861
3862 { "a0l", ADDR0L },
3863 { "a1l", ADDR1L },
3864 { "a2l", ADDR2L },
3865 { "a3l", ADDR3L },
3866 { "a4l", ADDR4L },
3867 { "a5l", ADDR5L },
3868 { "a6l", ADDR6L },
3869 { "a7l", ADDR7L },
3870
3871 { "d0u", DATA0U },
3872 { "d1u", DATA1U },
3873 { "d2u", DATA2U },
3874 { "d3u", DATA3U },
3875 { "d4u", DATA4U },
3876 { "d5u", DATA5U },
3877 { "d6u", DATA6U },
3878 { "d7u", DATA7U },
3879
3880 { "a0u", ADDR0U },
3881 { "a1u", ADDR1U },
3882 { "a2u", ADDR2U },
3883 { "a3u", ADDR3U },
3884 { "a4u", ADDR4U },
3885 { "a5u", ADDR5U },
3886 { "a6u", ADDR6U },
3887 { "a7u", ADDR7U },
3888
3889 { 0, 0 }
3890 };
3891
3892 static void
3893 init_regtable ()
3894 {
3895 int i;
3896 for (i = 0; init_table[i].name; i++)
3897 insert_reg (init_table[i].name, init_table[i].number);
3898 }
3899
3900 static int no_68851, no_68881;
3901
3902 #ifdef OBJ_AOUT
3903 /* a.out machine type. Default to 68020. */
3904 int m68k_aout_machtype = 2;
3905 #endif
3906
3907 void
3908 md_assemble (str)
3909 char *str;
3910 {
3911 const char *er;
3912 short *fromP;
3913 char *toP = NULL;
3914 int m, n = 0;
3915 char *to_beg_P;
3916 int shorts_this_frag;
3917 fixS *fixP;
3918
3919 /* In MRI mode, the instruction and operands are separated by a
3920 space. Anything following the operands is a comment. The label
3921 has already been removed. */
3922 if (flag_mri)
3923 {
3924 char *s;
3925 int fields = 0;
3926 int infield = 0;
3927 int inquote = 0;
3928
3929 for (s = str; *s != '\0'; s++)
3930 {
3931 if ((*s == ' ' || *s == '\t') && ! inquote)
3932 {
3933 if (infield)
3934 {
3935 ++fields;
3936 if (fields >= 2)
3937 {
3938 *s = '\0';
3939 break;
3940 }
3941 infield = 0;
3942 }
3943 }
3944 else
3945 {
3946 if (! infield)
3947 infield = 1;
3948 if (*s == '\'')
3949 inquote = ! inquote;
3950 }
3951 }
3952 }
3953
3954 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3955 m68k_ip (str);
3956 er = the_ins.error;
3957 if (!er)
3958 {
3959 for (n = 0; n < the_ins.numargs; n++)
3960 if (the_ins.operands[n].error)
3961 {
3962 er = the_ins.operands[n].error;
3963 break;
3964 }
3965 }
3966 if (er)
3967 {
3968 as_bad (_("%s -- statement `%s' ignored"), er, str);
3969 return;
3970 }
3971
3972 /* If there is a current label, record that it marks an instruction. */
3973 if (current_label != NULL)
3974 {
3975 current_label->text = 1;
3976 current_label = NULL;
3977 }
3978
3979 #ifdef OBJ_ELF
3980 /* Tie dwarf2 debug info to the address at the start of the insn. */
3981 dwarf2_emit_insn (0);
3982 #endif
3983
3984 if (the_ins.nfrag == 0)
3985 {
3986 /* No frag hacking involved; just put it out. */
3987 toP = frag_more (2 * the_ins.numo);
3988 fromP = &the_ins.opcode[0];
3989 for (m = the_ins.numo; m; --m)
3990 {
3991 md_number_to_chars (toP, (long) (*fromP), 2);
3992 toP += 2;
3993 fromP++;
3994 }
3995 /* Put out symbol-dependent info. */
3996 for (m = 0; m < the_ins.nrel; m++)
3997 {
3998 switch (the_ins.reloc[m].wid)
3999 {
4000 case 'B':
4001 n = 1;
4002 break;
4003 case 'b':
4004 n = 1;
4005 break;
4006 case '3':
4007 n = 1;
4008 break;
4009 case 'w':
4010 case 'W':
4011 n = 2;
4012 break;
4013 case 'l':
4014 n = 4;
4015 break;
4016 default:
4017 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4018 the_ins.reloc[m].wid);
4019 }
4020
4021 fixP = fix_new_exp (frag_now,
4022 ((toP - frag_now->fr_literal)
4023 - the_ins.numo * 2 + the_ins.reloc[m].n),
4024 n,
4025 &the_ins.reloc[m].exp,
4026 the_ins.reloc[m].pcrel,
4027 get_reloc_code (n, the_ins.reloc[m].pcrel,
4028 the_ins.reloc[m].pic_reloc));
4029 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4030 if (the_ins.reloc[m].wid == 'B')
4031 fixP->fx_signed = 1;
4032 }
4033 return;
4034 }
4035
4036 /* There's some frag hacking. */
4037 {
4038 /* Calculate the max frag size. */
4039 int wid;
4040
4041 wid = 2 * the_ins.fragb[0].fragoff;
4042 for (n = 1; n < the_ins.nfrag; n++)
4043 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4044 /* frag_var part. */
4045 wid += 10;
4046 /* Make sure the whole insn fits in one chunk, in particular that
4047 the var part is attached, as we access one byte before the
4048 variable frag for byte branches. */
4049 frag_grow (wid);
4050 }
4051
4052 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4053 {
4054 int wid;
4055
4056 if (n == 0)
4057 wid = 2 * the_ins.fragb[n].fragoff;
4058 else
4059 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4060 toP = frag_more (wid);
4061 to_beg_P = toP;
4062 shorts_this_frag = 0;
4063 for (m = wid / 2; m; --m)
4064 {
4065 md_number_to_chars (toP, (long) (*fromP), 2);
4066 toP += 2;
4067 fromP++;
4068 shorts_this_frag++;
4069 }
4070 for (m = 0; m < the_ins.nrel; m++)
4071 {
4072 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4073 {
4074 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4075 break;
4076 }
4077 wid = the_ins.reloc[m].wid;
4078 if (wid == 0)
4079 continue;
4080 the_ins.reloc[m].wid = 0;
4081 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4082
4083 fixP = fix_new_exp (frag_now,
4084 ((toP - frag_now->fr_literal)
4085 - the_ins.numo * 2 + the_ins.reloc[m].n),
4086 wid,
4087 &the_ins.reloc[m].exp,
4088 the_ins.reloc[m].pcrel,
4089 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4090 the_ins.reloc[m].pic_reloc));
4091 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4092 }
4093 (void) frag_var (rs_machine_dependent, 10, 0,
4094 (relax_substateT) (the_ins.fragb[n].fragty),
4095 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4096 }
4097 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4098 shorts_this_frag = 0;
4099 if (n)
4100 {
4101 toP = frag_more (n * sizeof (short));
4102 while (n--)
4103 {
4104 md_number_to_chars (toP, (long) (*fromP), 2);
4105 toP += 2;
4106 fromP++;
4107 shorts_this_frag++;
4108 }
4109 }
4110 for (m = 0; m < the_ins.nrel; m++)
4111 {
4112 int wid;
4113
4114 wid = the_ins.reloc[m].wid;
4115 if (wid == 0)
4116 continue;
4117 the_ins.reloc[m].wid = 0;
4118 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4119
4120 fixP = fix_new_exp (frag_now,
4121 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4122 - shorts_this_frag * 2),
4123 wid,
4124 &the_ins.reloc[m].exp,
4125 the_ins.reloc[m].pcrel,
4126 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4127 the_ins.reloc[m].pic_reloc));
4128 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4129 }
4130 }
4131
4132 /* Comparison function used by qsort to rank the opcode entries by name. */
4133
4134 static int
4135 m68k_compare_opcode (const void * v1, const void * v2)
4136 {
4137 struct m68k_opcode * op1, * op2;
4138 int ret;
4139
4140 op1 = *(struct m68k_opcode **) v1;
4141 op2 = *(struct m68k_opcode **) v2;
4142
4143 /* Compare the two names. If different, return the comparison.
4144 If the same, return the order they are in the opcode table. */
4145 ret = strcmp (op1->name, op2->name);
4146 if (ret)
4147 return ret;
4148 if (op1 < op2)
4149 return -1;
4150 return 0;
4151 }
4152
4153 void
4154 md_begin (void)
4155 {
4156 const struct m68k_opcode *ins;
4157 struct m68k_incant *hack, *slak;
4158 const char *retval = 0; /* Empty string, or error msg text. */
4159 int i;
4160
4161 /* Set up hash tables with 68000 instructions.
4162 similar to what the vax assembler does. */
4163 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4164 a copy of it at runtime, adding in the information we want but isn't
4165 there. I think it'd be better to have an awk script hack the table
4166 at compile time. Or even just xstr the table and use it as-is. But
4167 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4168 names. */
4169
4170 if (flag_mri)
4171 {
4172 flag_reg_prefix_optional = 1;
4173 m68k_abspcadd = 1;
4174 if (! m68k_rel32_from_cmdline)
4175 m68k_rel32 = 0;
4176 }
4177
4178 /* First sort the opcode table into alphabetical order to seperate
4179 the order that the assembler wants to see the opcodes from the
4180 order that the disassembler wants to see them. */
4181 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4182 if (!m68k_sorted_opcodes)
4183 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4184 m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4185
4186 for (i = m68k_numopcodes; i--;)
4187 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4188
4189 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4190 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4191
4192 op_hash = hash_new ();
4193
4194 obstack_begin (&robyn, 4000);
4195 for (i = 0; i < m68k_numopcodes; i++)
4196 {
4197 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4198 do
4199 {
4200 ins = m68k_sorted_opcodes[i];
4201
4202 /* We *could* ignore insns that don't match our
4203 arch here by just leaving them out of the hash. */
4204 slak->m_operands = ins->args;
4205 slak->m_opnum = strlen (slak->m_operands) / 2;
4206 slak->m_arch = ins->arch;
4207 slak->m_opcode = ins->opcode;
4208 /* This is kludgey. */
4209 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4210 if (i + 1 != m68k_numopcodes
4211 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4212 {
4213 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4214 i++;
4215 }
4216 else
4217 slak->m_next = 0;
4218 slak = slak->m_next;
4219 }
4220 while (slak);
4221
4222 retval = hash_insert (op_hash, ins->name, (char *) hack);
4223 if (retval)
4224 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4225 }
4226
4227 for (i = 0; i < m68k_numaliases; i++)
4228 {
4229 const char *name = m68k_opcode_aliases[i].primary;
4230 const char *alias = m68k_opcode_aliases[i].alias;
4231 PTR val = hash_find (op_hash, name);
4232
4233 if (!val)
4234 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4235 retval = hash_insert (op_hash, alias, val);
4236 if (retval)
4237 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4238 }
4239
4240 /* In MRI mode, all unsized branches are variable sized. Normally,
4241 they are word sized. */
4242 if (flag_mri)
4243 {
4244 static struct m68k_opcode_alias mri_aliases[] =
4245 {
4246 { "bhi", "jhi", },
4247 { "bls", "jls", },
4248 { "bcc", "jcc", },
4249 { "bcs", "jcs", },
4250 { "bne", "jne", },
4251 { "beq", "jeq", },
4252 { "bvc", "jvc", },
4253 { "bvs", "jvs", },
4254 { "bpl", "jpl", },
4255 { "bmi", "jmi", },
4256 { "bge", "jge", },
4257 { "blt", "jlt", },
4258 { "bgt", "jgt", },
4259 { "ble", "jle", },
4260 { "bra", "jra", },
4261 { "bsr", "jbsr", },
4262 };
4263
4264 for (i = 0;
4265 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4266 i++)
4267 {
4268 const char *name = mri_aliases[i].primary;
4269 const char *alias = mri_aliases[i].alias;
4270 PTR val = hash_find (op_hash, name);
4271
4272 if (!val)
4273 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4274 retval = hash_jam (op_hash, alias, val);
4275 if (retval)
4276 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4277 }
4278 }
4279
4280 for (i = 0; i < (int) sizeof (notend_table); i++)
4281 {
4282 notend_table[i] = 0;
4283 alt_notend_table[i] = 0;
4284 }
4285
4286 notend_table[','] = 1;
4287 notend_table['{'] = 1;
4288 notend_table['}'] = 1;
4289 alt_notend_table['a'] = 1;
4290 alt_notend_table['A'] = 1;
4291 alt_notend_table['d'] = 1;
4292 alt_notend_table['D'] = 1;
4293 alt_notend_table['#'] = 1;
4294 alt_notend_table['&'] = 1;
4295 alt_notend_table['f'] = 1;
4296 alt_notend_table['F'] = 1;
4297 #ifdef REGISTER_PREFIX
4298 alt_notend_table[REGISTER_PREFIX] = 1;
4299 #endif
4300
4301 /* We need to put '(' in alt_notend_table to handle
4302 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4303 alt_notend_table['('] = 1;
4304
4305 /* We need to put '@' in alt_notend_table to handle
4306 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4307 alt_notend_table['@'] = 1;
4308
4309 /* We need to put digits in alt_notend_table to handle
4310 bfextu %d0{24:1},%d0 */
4311 alt_notend_table['0'] = 1;
4312 alt_notend_table['1'] = 1;
4313 alt_notend_table['2'] = 1;
4314 alt_notend_table['3'] = 1;
4315 alt_notend_table['4'] = 1;
4316 alt_notend_table['5'] = 1;
4317 alt_notend_table['6'] = 1;
4318 alt_notend_table['7'] = 1;
4319 alt_notend_table['8'] = 1;
4320 alt_notend_table['9'] = 1;
4321
4322 #ifndef MIT_SYNTAX_ONLY
4323 /* Insert pseudo ops, these have to go into the opcode table since
4324 gas expects pseudo ops to start with a dot. */
4325 {
4326 int n = 0;
4327
4328 while (mote_pseudo_table[n].poc_name)
4329 {
4330 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4331 hash_insert (op_hash,
4332 mote_pseudo_table[n].poc_name, (char *) hack);
4333 hack->m_operands = 0;
4334 hack->m_opnum = n;
4335 n++;
4336 }
4337 }
4338 #endif
4339
4340 init_regtable ();
4341
4342 #ifdef OBJ_ELF
4343 record_alignment (text_section, 2);
4344 record_alignment (data_section, 2);
4345 record_alignment (bss_section, 2);
4346 #endif
4347 }
4348
4349 static void
4350 select_control_regs ()
4351 {
4352 /* Note which set of "movec" control registers is available. */
4353 switch (current_chip)
4354 {
4355 case 0:
4356 if (verbose)
4357 as_warn (_("architecture not yet selected: defaulting to 68020"));
4358 control_regs = m68020_control_regs;
4359 break;
4360
4361 case m68000:
4362 control_regs = m68000_control_regs;
4363 break;
4364 case m68010:
4365 control_regs = m68010_control_regs;
4366 break;
4367 case m68020:
4368 case m68030:
4369 control_regs = m68020_control_regs;
4370 break;
4371 case m68040:
4372 control_regs = m68040_control_regs;
4373 break;
4374 case m68060:
4375 control_regs = m68060_control_regs;
4376 break;
4377 case cpu32:
4378 control_regs = cpu32_control_regs;
4379 break;
4380 case mcf5200:
4381 case mcf5206e:
4382 case mcf5307:
4383 case mcf5407:
4384 control_regs = mcf_control_regs;
4385 break;
4386 case mcf528x:
4387 case mcf521x:
4388 control_regs = mcf528x_control_regs;
4389 break;
4390 case mcf5470:
4391 case mcf5480:
4392 control_regs = mcfv4e_control_regs;
4393 break;
4394 default:
4395 abort ();
4396 }
4397 }
4398
4399 void
4400 m68k_init_after_args ()
4401 {
4402 if (cpu_of_arch (current_architecture) == 0)
4403 {
4404 int i;
4405 const char *default_cpu = TARGET_CPU;
4406
4407 if (*default_cpu == 'm')
4408 default_cpu++;
4409 for (i = 0; i < n_archs; i++)
4410 if (strcasecmp (default_cpu, archs[i].name) == 0)
4411 break;
4412 if (i == n_archs)
4413 {
4414 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4415 current_architecture |= m68020;
4416 }
4417 else
4418 current_architecture |= archs[i].arch;
4419 }
4420 /* Permit m68881 specification with all cpus; those that can't work
4421 with a coprocessor could be doing emulation. */
4422 if (current_architecture & m68851)
4423 {
4424 if (current_architecture & m68040)
4425 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4426 }
4427 /* What other incompatibilities could we check for? */
4428
4429 /* Toss in some default assumptions about coprocessors. */
4430 if (!no_68881
4431 && (cpu_of_arch (current_architecture)
4432 /* Can CPU32 have a 68881 coprocessor?? */
4433 & (m68020 | m68030 | cpu32)))
4434 current_architecture |= m68881;
4435
4436 if (!no_68851
4437 && (cpu_of_arch (current_architecture) & m68020up) != 0
4438 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4439 current_architecture |= m68851;
4440
4441 if (no_68881 && (current_architecture & m68881))
4442 as_bad (_("options for 68881 and no-68881 both given"));
4443
4444 if (no_68851 && (current_architecture & m68851))
4445 as_bad (_("options for 68851 and no-68851 both given"));
4446
4447 #ifdef OBJ_AOUT
4448 /* Work out the magic number. This isn't very general. */
4449 if (current_architecture & m68000)
4450 m68k_aout_machtype = 0;
4451 else if (current_architecture & m68010)
4452 m68k_aout_machtype = 1;
4453 else if (current_architecture & m68020)
4454 m68k_aout_machtype = 2;
4455 else
4456 m68k_aout_machtype = 2;
4457 #endif
4458
4459 /* Note which set of "movec" control registers is available. */
4460 select_control_regs ();
4461
4462 if (cpu_of_arch (current_architecture) < m68020
4463 || arch_coldfire_p (current_architecture))
4464 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4465 }
4466 \f
4467 /* This is called when a label is defined. */
4468
4469 void
4470 m68k_frob_label (sym)
4471 symbolS *sym;
4472 {
4473 struct label_line *n;
4474
4475 n = (struct label_line *) xmalloc (sizeof *n);
4476 n->next = labels;
4477 n->label = sym;
4478 as_where (&n->file, &n->line);
4479 n->text = 0;
4480 labels = n;
4481 current_label = n;
4482 }
4483
4484 /* This is called when a value that is not an instruction is emitted. */
4485
4486 void
4487 m68k_flush_pending_output ()
4488 {
4489 current_label = NULL;
4490 }
4491
4492 /* This is called at the end of the assembly, when the final value of
4493 the label is known. We warn if this is a text symbol aligned at an
4494 odd location. */
4495
4496 void
4497 m68k_frob_symbol (sym)
4498 symbolS *sym;
4499 {
4500 if (S_GET_SEGMENT (sym) == reg_section
4501 && (int) S_GET_VALUE (sym) < 0)
4502 {
4503 S_SET_SEGMENT (sym, absolute_section);
4504 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4505 }
4506 else if ((S_GET_VALUE (sym) & 1) != 0)
4507 {
4508 struct label_line *l;
4509
4510 for (l = labels; l != NULL; l = l->next)
4511 {
4512 if (l->label == sym)
4513 {
4514 if (l->text)
4515 as_warn_where (l->file, l->line,
4516 _("text label `%s' aligned to odd boundary"),
4517 S_GET_NAME (sym));
4518 break;
4519 }
4520 }
4521 }
4522 }
4523 \f
4524 /* This is called if we go in or out of MRI mode because of the .mri
4525 pseudo-op. */
4526
4527 void
4528 m68k_mri_mode_change (on)
4529 int on;
4530 {
4531 if (on)
4532 {
4533 if (! flag_reg_prefix_optional)
4534 {
4535 flag_reg_prefix_optional = 1;
4536 #ifdef REGISTER_PREFIX
4537 init_regtable ();
4538 #endif
4539 }
4540 m68k_abspcadd = 1;
4541 if (! m68k_rel32_from_cmdline)
4542 m68k_rel32 = 0;
4543 }
4544 else
4545 {
4546 if (! reg_prefix_optional_seen)
4547 {
4548 #ifdef REGISTER_PREFIX_OPTIONAL
4549 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4550 #else
4551 flag_reg_prefix_optional = 0;
4552 #endif
4553 #ifdef REGISTER_PREFIX
4554 init_regtable ();
4555 #endif
4556 }
4557 m68k_abspcadd = 0;
4558 if (! m68k_rel32_from_cmdline)
4559 m68k_rel32 = 1;
4560 }
4561 }
4562
4563 /* Equal to MAX_PRECISION in atof-ieee.c. */
4564 #define MAX_LITTLENUMS 6
4565
4566 /* Turn a string in input_line_pointer into a floating point constant
4567 of type TYPE, and store the appropriate bytes in *LITP. The number
4568 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4569 returned, or NULL on OK. */
4570
4571 char *
4572 md_atof (type, litP, sizeP)
4573 char type;
4574 char *litP;
4575 int *sizeP;
4576 {
4577 int prec;
4578 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4579 LITTLENUM_TYPE *wordP;
4580 char *t;
4581
4582 switch (type)
4583 {
4584 case 'f':
4585 case 'F':
4586 case 's':
4587 case 'S':
4588 prec = 2;
4589 break;
4590
4591 case 'd':
4592 case 'D':
4593 case 'r':
4594 case 'R':
4595 prec = 4;
4596 break;
4597
4598 case 'x':
4599 case 'X':
4600 prec = 6;
4601 break;
4602
4603 case 'p':
4604 case 'P':
4605 prec = 6;
4606 break;
4607
4608 default:
4609 *sizeP = 0;
4610 return _("Bad call to MD_ATOF()");
4611 }
4612 t = atof_ieee (input_line_pointer, type, words);
4613 if (t)
4614 input_line_pointer = t;
4615
4616 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4617 for (wordP = words; prec--;)
4618 {
4619 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4620 litP += sizeof (LITTLENUM_TYPE);
4621 }
4622 return 0;
4623 }
4624
4625 void
4626 md_number_to_chars (buf, val, n)
4627 char *buf;
4628 valueT val;
4629 int n;
4630 {
4631 number_to_chars_bigendian (buf, val, n);
4632 }
4633
4634 void
4635 md_apply_fix3 (fixP, valP, seg)
4636 fixS *fixP;
4637 valueT *valP;
4638 segT seg ATTRIBUTE_UNUSED;
4639 {
4640 offsetT val = *valP;
4641 addressT upper_limit;
4642 offsetT lower_limit;
4643
4644 /* This is unnecessary but it convinces the native rs6000 compiler
4645 to generate the code we want. */
4646 char *buf = fixP->fx_frag->fr_literal;
4647 buf += fixP->fx_where;
4648 /* End ibm compiler workaround. */
4649
4650 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
4651
4652 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4653 fixP->fx_done = 1;
4654
4655 #ifdef OBJ_ELF
4656 if (fixP->fx_addsy)
4657 {
4658 memset (buf, 0, fixP->fx_size);
4659 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4660
4661 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4662 && !S_IS_DEFINED (fixP->fx_addsy)
4663 && !S_IS_WEAK (fixP->fx_addsy))
4664 S_SET_WEAK (fixP->fx_addsy);
4665 return;
4666 }
4667 #endif
4668
4669 #ifdef BFD_ASSEMBLER
4670 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4671 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4672 return;
4673 #endif
4674
4675 switch (fixP->fx_size)
4676 {
4677 /* The cast to offsetT below are necessary to make code
4678 correct for machines where ints are smaller than offsetT. */
4679 case 1:
4680 *buf++ = val;
4681 upper_limit = 0x7f;
4682 lower_limit = - (offsetT) 0x80;
4683 break;
4684 case 2:
4685 *buf++ = (val >> 8);
4686 *buf++ = val;
4687 upper_limit = 0x7fff;
4688 lower_limit = - (offsetT) 0x8000;
4689 break;
4690 case 4:
4691 *buf++ = (val >> 24);
4692 *buf++ = (val >> 16);
4693 *buf++ = (val >> 8);
4694 *buf++ = val;
4695 upper_limit = 0x7fffffff;
4696 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4697 break;
4698 default:
4699 BAD_CASE (fixP->fx_size);
4700 }
4701
4702 /* Fix up a negative reloc. */
4703 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4704 {
4705 fixP->fx_addsy = fixP->fx_subsy;
4706 fixP->fx_subsy = NULL;
4707 fixP->fx_tcbit = 1;
4708 }
4709
4710 /* For non-pc-relative values, it's conceivable we might get something
4711 like "0xff" for a byte field. So extend the upper part of the range
4712 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4713 so that we can do any range checking at all. */
4714 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4715 upper_limit = upper_limit * 2 + 1;
4716
4717 if ((addressT) val > upper_limit
4718 && (val > 0 || val < lower_limit))
4719 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4720
4721 /* A one byte PC-relative reloc means a short branch. We can't use
4722 a short branch with a value of 0 or -1, because those indicate
4723 different opcodes (branches with longer offsets). fixup_segment
4724 in write.c may have clobbered fx_pcrel, so we need to examine the
4725 reloc type. */
4726 if ((fixP->fx_pcrel
4727 #ifdef BFD_ASSEMBLER
4728 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4729 #endif
4730 )
4731 && fixP->fx_size == 1
4732 && (fixP->fx_addsy == NULL
4733 || S_IS_DEFINED (fixP->fx_addsy))
4734 && (val == 0 || val == -1))
4735 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4736 }
4737
4738 /* *fragP has been relaxed to its final size, and now needs to have
4739 the bytes inside it modified to conform to the new size There is UGLY
4740 MAGIC here. ..
4741 */
4742 static void
4743 md_convert_frag_1 (fragP)
4744 register fragS *fragP;
4745 {
4746 long disp;
4747 fixS *fixP;
4748
4749 /* Address in object code of the displacement. */
4750 register int object_address = fragP->fr_fix + fragP->fr_address;
4751
4752 /* Address in gas core of the place to store the displacement. */
4753 /* This convinces the native rs6000 compiler to generate the code we
4754 want. */
4755 register char *buffer_address = fragP->fr_literal;
4756 buffer_address += fragP->fr_fix;
4757 /* End ibm compiler workaround. */
4758
4759 /* The displacement of the address, from current location. */
4760 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4761 disp = (disp + fragP->fr_offset) - object_address;
4762
4763 switch (fragP->fr_subtype)
4764 {
4765 case TAB (BRANCHBWL, BYTE):
4766 case TAB (BRABSJUNC, BYTE):
4767 case TAB (BRABSJCOND, BYTE):
4768 case TAB (BRANCHBW, BYTE):
4769 know (issbyte (disp));
4770 if (disp == 0)
4771 as_bad_where (fragP->fr_file, fragP->fr_line,
4772 _("short branch with zero offset: use :w"));
4773 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4774 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4775 fixP->fx_pcrel_adjust = -1;
4776 break;
4777 case TAB (BRANCHBWL, SHORT):
4778 case TAB (BRABSJUNC, SHORT):
4779 case TAB (BRABSJCOND, SHORT):
4780 case TAB (BRANCHBW, SHORT):
4781 fragP->fr_opcode[1] = 0x00;
4782 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4783 1, RELAX_RELOC_PC16);
4784 fragP->fr_fix += 2;
4785 break;
4786 case TAB (BRANCHBWL, LONG):
4787 fragP->fr_opcode[1] = (char) 0xFF;
4788 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4789 1, RELAX_RELOC_PC32);
4790 fragP->fr_fix += 4;
4791 break;
4792 case TAB (BRABSJUNC, LONG):
4793 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4794 {
4795 if (flag_keep_pcrel)
4796 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4797 fragP->fr_opcode[0] = 0x4E;
4798 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4799 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4800 0, RELAX_RELOC_ABS32);
4801 fragP->fr_fix += 4;
4802 }
4803 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4804 {
4805 if (flag_keep_pcrel)
4806 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4807 fragP->fr_opcode[0] = 0x4E;
4808 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4809 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4810 0, RELAX_RELOC_ABS32);
4811 fragP->fr_fix += 4;
4812 }
4813 else
4814 {
4815 /* This cannot happen, because jbsr and jbra are the only two
4816 unconditional branches. */
4817 abort ();
4818 }
4819 break;
4820 case TAB (BRABSJCOND, LONG):
4821 if (flag_keep_pcrel)
4822 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4823
4824 /* Only Bcc 68000 instructions can come here
4825 Change bcc into b!cc/jmp absl long. */
4826 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4827 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4828
4829 /* JF: these used to be fr_opcode[2,3], but they may be in a
4830 different frag, in which case referring to them is a no-no.
4831 Only fr_opcode[0,1] are guaranteed to work. */
4832 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4833 *buffer_address++ = (char) 0xf9;
4834 fragP->fr_fix += 2; /* Account for jmp instruction. */
4835 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4836 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4837 fragP->fr_fix += 4;
4838 break;
4839 case TAB (FBRANCH, SHORT):
4840 know ((fragP->fr_opcode[1] & 0x40) == 0);
4841 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4842 1, RELAX_RELOC_PC16);
4843 fragP->fr_fix += 2;
4844 break;
4845 case TAB (FBRANCH, LONG):
4846 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4847 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4848 1, RELAX_RELOC_PC32);
4849 fragP->fr_fix += 4;
4850 break;
4851 case TAB (DBCCLBR, SHORT):
4852 case TAB (DBCCABSJ, SHORT):
4853 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4854 1, RELAX_RELOC_PC16);
4855 fragP->fr_fix += 2;
4856 break;
4857 case TAB (DBCCLBR, LONG):
4858 /* Only DBcc instructions can come here.
4859 Change dbcc into dbcc/bral.
4860 JF: these used to be fr_opcode[2-7], but that's wrong. */
4861 if (flag_keep_pcrel)
4862 as_fatal (_("Tried to convert DBcc to absolute jump"));
4863
4864 *buffer_address++ = 0x00; /* Branch offset = 4. */
4865 *buffer_address++ = 0x04;
4866 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4867 *buffer_address++ = 0x06;
4868 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4869 *buffer_address++ = (char) 0xff;
4870
4871 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4872 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4873 RELAX_RELOC_PC32);
4874 fragP->fr_fix += 4;
4875 break;
4876 case TAB (DBCCABSJ, LONG):
4877 /* Only DBcc instructions can come here.
4878 Change dbcc into dbcc/jmp.
4879 JF: these used to be fr_opcode[2-7], but that's wrong. */
4880 if (flag_keep_pcrel)
4881 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4882
4883 *buffer_address++ = 0x00; /* Branch offset = 4. */
4884 *buffer_address++ = 0x04;
4885 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4886 *buffer_address++ = 0x06;
4887 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4888 *buffer_address++ = (char) 0xf9;
4889
4890 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4891 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4892 RELAX_RELOC_ABS32);
4893 fragP->fr_fix += 4;
4894 break;
4895 case TAB (PCREL1632, SHORT):
4896 fragP->fr_opcode[1] &= ~0x3F;
4897 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4898 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4899 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4900 fragP->fr_fix += 2;
4901 break;
4902 case TAB (PCREL1632, LONG):
4903 /* Already set to mode 7.3; this indicates: PC indirect with
4904 suppressed index, 32-bit displacement. */
4905 *buffer_address++ = 0x01;
4906 *buffer_address++ = 0x70;
4907 fragP->fr_fix += 2;
4908 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4909 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4910 fixP->fx_pcrel_adjust = 2;
4911 fragP->fr_fix += 4;
4912 break;
4913 case TAB (PCINDEX, BYTE):
4914 assert (fragP->fr_fix >= 2);
4915 buffer_address[-2] &= ~1;
4916 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4917 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4918 fixP->fx_pcrel_adjust = 1;
4919 break;
4920 case TAB (PCINDEX, SHORT):
4921 assert (fragP->fr_fix >= 2);
4922 buffer_address[-2] |= 0x1;
4923 buffer_address[-1] = 0x20;
4924 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4925 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4926 fixP->fx_pcrel_adjust = 2;
4927 fragP->fr_fix += 2;
4928 break;
4929 case TAB (PCINDEX, LONG):
4930 assert (fragP->fr_fix >= 2);
4931 buffer_address[-2] |= 0x1;
4932 buffer_address[-1] = 0x30;
4933 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4934 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4935 fixP->fx_pcrel_adjust = 2;
4936 fragP->fr_fix += 4;
4937 break;
4938 case TAB (ABSTOPCREL, SHORT):
4939 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4940 1, RELAX_RELOC_PC16);
4941 fragP->fr_fix += 2;
4942 break;
4943 case TAB (ABSTOPCREL, LONG):
4944 if (flag_keep_pcrel)
4945 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4946 /* The thing to do here is force it to ABSOLUTE LONG, since
4947 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4948 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4949 abort ();
4950 fragP->fr_opcode[1] &= ~0x3F;
4951 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4952 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4953 0, RELAX_RELOC_ABS32);
4954 fragP->fr_fix += 4;
4955 break;
4956 }
4957 }
4958
4959 #ifndef BFD_ASSEMBLER
4960
4961 void
4962 md_convert_frag (headers, sec, fragP)
4963 object_headers *headers ATTRIBUTE_UNUSED;
4964 segT sec ATTRIBUTE_UNUSED;
4965 fragS *fragP;
4966 {
4967 md_convert_frag_1 (fragP);
4968 }
4969
4970 #else
4971
4972 void
4973 md_convert_frag (abfd, sec, fragP)
4974 bfd *abfd ATTRIBUTE_UNUSED;
4975 segT sec ATTRIBUTE_UNUSED;
4976 fragS *fragP;
4977 {
4978 md_convert_frag_1 (fragP);
4979 }
4980 #endif
4981
4982 /* Force truly undefined symbols to their maximum size, and generally set up
4983 the frag list to be relaxed
4984 */
4985 int
4986 md_estimate_size_before_relax (fragP, segment)
4987 register fragS *fragP;
4988 segT segment;
4989 {
4990 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4991 switch (fragP->fr_subtype)
4992 {
4993 case TAB (BRANCHBWL, SZ_UNDEF):
4994 case TAB (BRABSJUNC, SZ_UNDEF):
4995 case TAB (BRABSJCOND, SZ_UNDEF):
4996 {
4997 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4998 && relaxable_symbol (fragP->fr_symbol))
4999 {
5000 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5001 }
5002 else if (flag_short_refs)
5003 {
5004 /* Symbol is undefined and we want short ref. */
5005 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5006 }
5007 else
5008 {
5009 /* Symbol is still undefined. Make it LONG. */
5010 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5011 }
5012 break;
5013 }
5014
5015 case TAB (BRANCHBW, SZ_UNDEF):
5016 {
5017 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5018 && relaxable_symbol (fragP->fr_symbol))
5019 {
5020 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5021 }
5022 else
5023 {
5024 /* Symbol is undefined and we don't have long branches. */
5025 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5026 }
5027 break;
5028 }
5029
5030 case TAB (FBRANCH, SZ_UNDEF):
5031 case TAB (DBCCLBR, SZ_UNDEF):
5032 case TAB (DBCCABSJ, SZ_UNDEF):
5033 case TAB (PCREL1632, SZ_UNDEF):
5034 {
5035 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5036 && relaxable_symbol (fragP->fr_symbol))
5037 || flag_short_refs)
5038 {
5039 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5040 }
5041 else
5042 {
5043 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5044 }
5045 break;
5046 }
5047
5048 case TAB (PCINDEX, SZ_UNDEF):
5049 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5050 && relaxable_symbol (fragP->fr_symbol)))
5051 {
5052 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5053 }
5054 else
5055 {
5056 fragP->fr_subtype = TAB (PCINDEX, LONG);
5057 }
5058 break;
5059
5060 case TAB (ABSTOPCREL, SZ_UNDEF):
5061 {
5062 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5063 && relaxable_symbol (fragP->fr_symbol)))
5064 {
5065 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5066 }
5067 else
5068 {
5069 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5070 }
5071 break;
5072 }
5073
5074 default:
5075 break;
5076 }
5077
5078 /* Now that SZ_UNDEF are taken care of, check others. */
5079 switch (fragP->fr_subtype)
5080 {
5081 case TAB (BRANCHBWL, BYTE):
5082 case TAB (BRABSJUNC, BYTE):
5083 case TAB (BRABSJCOND, BYTE):
5084 case TAB (BRANCHBW, BYTE):
5085 /* We can't do a short jump to the next instruction, so in that
5086 case we force word mode. If the symbol is at the start of a
5087 frag, and it is the next frag with any data in it (usually
5088 this is just the next frag, but assembler listings may
5089 introduce empty frags), we must use word mode. */
5090 if (fragP->fr_symbol)
5091 {
5092 fragS *sym_frag;
5093
5094 sym_frag = symbol_get_frag (fragP->fr_symbol);
5095 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5096 {
5097 fragS *l;
5098
5099 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5100 if (l->fr_fix != 0)
5101 break;
5102 if (l == sym_frag)
5103 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5104 }
5105 }
5106 break;
5107 default:
5108 break;
5109 }
5110 return md_relax_table[fragP->fr_subtype].rlx_length;
5111 }
5112
5113 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5114 /* the bit-field entries in the relocation_info struct plays hell
5115 with the byte-order problems of cross-assembly. So as a hack,
5116 I added this mach. dependent ri twiddler. Ugly, but it gets
5117 you there. -KWK */
5118 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5119 are symbolnum, most sig. byte first. Last byte is broken up with
5120 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5121 nibble as nuthin. (on Sun 3 at least) */
5122 /* Translate the internal relocation information into target-specific
5123 format. */
5124 #ifdef comment
5125 void
5126 md_ri_to_chars (the_bytes, ri)
5127 char *the_bytes;
5128 struct reloc_info_generic *ri;
5129 {
5130 /* This is easy. */
5131 md_number_to_chars (the_bytes, ri->r_address, 4);
5132 /* Now the fun stuff. */
5133 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5134 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5135 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5136 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
5137 ((ri->r_extern << 4) & 0x10));
5138 }
5139
5140 #endif
5141
5142 #ifndef BFD_ASSEMBLER
5143 void
5144 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5145 char *where;
5146 fixS *fixP;
5147 relax_addressT segment_address_in_file;
5148 {
5149 /*
5150 * In: length of relocation (or of address) in chars: 1, 2 or 4.
5151 * Out: GNU LD relocation length code: 0, 1, or 2.
5152 */
5153
5154 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
5155 long r_symbolnum;
5156
5157 know (fixP->fx_addsy != NULL);
5158
5159 md_number_to_chars (where,
5160 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
5161 4);
5162
5163 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5164 ? S_GET_TYPE (fixP->fx_addsy)
5165 : fixP->fx_addsy->sy_number);
5166
5167 where[4] = (r_symbolnum >> 16) & 0x0ff;
5168 where[5] = (r_symbolnum >> 8) & 0x0ff;
5169 where[6] = r_symbolnum & 0x0ff;
5170 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
5171 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
5172 }
5173 #endif
5174
5175 #endif /* OBJ_AOUT or OBJ_BOUT */
5176
5177 #ifndef WORKING_DOT_WORD
5178 const int md_short_jump_size = 4;
5179 const int md_long_jump_size = 6;
5180
5181 void
5182 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5183 char *ptr;
5184 addressT from_addr, to_addr;
5185 fragS *frag ATTRIBUTE_UNUSED;
5186 symbolS *to_symbol ATTRIBUTE_UNUSED;
5187 {
5188 valueT offset;
5189
5190 offset = to_addr - (from_addr + 2);
5191
5192 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5193 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5194 }
5195
5196 void
5197 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5198 char *ptr;
5199 addressT from_addr, to_addr;
5200 fragS *frag;
5201 symbolS *to_symbol;
5202 {
5203 valueT offset;
5204
5205 if (!HAVE_LONG_BRANCH (current_architecture))
5206 {
5207 if (flag_keep_pcrel)
5208 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5209 offset = to_addr - S_GET_VALUE (to_symbol);
5210 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5211 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5212 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5213 0, NO_RELOC);
5214 }
5215 else
5216 {
5217 offset = to_addr - (from_addr + 2);
5218 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5219 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5220 }
5221 }
5222
5223 #endif
5224
5225 /* Different values of OK tell what its OK to return. Things that
5226 aren't OK are an error (what a shock, no?)
5227
5228 0: Everything is OK
5229 10: Absolute 1:8 only
5230 20: Absolute 0:7 only
5231 30: absolute 0:15 only
5232 40: Absolute 0:31 only
5233 50: absolute 0:127 only
5234 55: absolute -64:63 only
5235 60: absolute -128:127 only
5236 70: absolute 0:4095 only
5237 80: absolute -1, 1:7 only
5238 90: No bignums. */
5239
5240 static int
5241 get_num (exp, ok)
5242 struct m68k_exp *exp;
5243 int ok;
5244 {
5245 if (exp->exp.X_op == O_absent)
5246 {
5247 /* Do the same thing the VAX asm does. */
5248 op (exp) = O_constant;
5249 adds (exp) = 0;
5250 subs (exp) = 0;
5251 offs (exp) = 0;
5252 if (ok == 10)
5253 {
5254 as_warn (_("expression out of range: defaulting to 1"));
5255 offs (exp) = 1;
5256 }
5257 }
5258 else if (exp->exp.X_op == O_constant)
5259 {
5260 switch (ok)
5261 {
5262 case 10:
5263 if (offs (exp) < 1 || offs (exp) > 8)
5264 {
5265 as_warn (_("expression out of range: defaulting to 1"));
5266 offs (exp) = 1;
5267 }
5268 break;
5269 case 20:
5270 if (offs (exp) < 0 || offs (exp) > 7)
5271 goto outrange;
5272 break;
5273 case 30:
5274 if (offs (exp) < 0 || offs (exp) > 15)
5275 goto outrange;
5276 break;
5277 case 40:
5278 if (offs (exp) < 0 || offs (exp) > 32)
5279 goto outrange;
5280 break;
5281 case 50:
5282 if (offs (exp) < 0 || offs (exp) > 127)
5283 goto outrange;
5284 break;
5285 case 55:
5286 if (offs (exp) < -64 || offs (exp) > 63)
5287 goto outrange;
5288 break;
5289 case 60:
5290 if (offs (exp) < -128 || offs (exp) > 127)
5291 goto outrange;
5292 break;
5293 case 70:
5294 if (offs (exp) < 0 || offs (exp) > 4095)
5295 {
5296 outrange:
5297 as_warn (_("expression out of range: defaulting to 0"));
5298 offs (exp) = 0;
5299 }
5300 break;
5301 case 80:
5302 if (offs (exp) < -1
5303 || offs (exp) > 7
5304 || offs (exp) == 0)
5305 {
5306 as_warn (_("expression out of range: defaulting to 1"));
5307 offs (exp) = 1;
5308 }
5309 break;
5310 default:
5311 break;
5312 }
5313 }
5314 else if (exp->exp.X_op == O_big)
5315 {
5316 if (offs (exp) <= 0 /* flonum. */
5317 && (ok == 90 /* no bignums */
5318 || (ok > 10 /* Small-int ranges including 0 ok. */
5319 /* If we have a flonum zero, a zero integer should
5320 do as well (e.g., in moveq). */
5321 && generic_floating_point_number.exponent == 0
5322 && generic_floating_point_number.low[0] == 0)))
5323 {
5324 /* HACK! Turn it into a long. */
5325 LITTLENUM_TYPE words[6];
5326
5327 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5328 op (exp) = O_constant;
5329 adds (exp) = 0;
5330 subs (exp) = 0;
5331 offs (exp) = words[1] | (words[0] << 16);
5332 }
5333 else if (ok != 0)
5334 {
5335 op (exp) = O_constant;
5336 adds (exp) = 0;
5337 subs (exp) = 0;
5338 offs (exp) = (ok == 10) ? 1 : 0;
5339 as_warn (_("Can't deal with expression; defaulting to %ld"),
5340 offs (exp));
5341 }
5342 }
5343 else
5344 {
5345 if (ok >= 10 && ok <= 80)
5346 {
5347 op (exp) = O_constant;
5348 adds (exp) = 0;
5349 subs (exp) = 0;
5350 offs (exp) = (ok == 10) ? 1 : 0;
5351 as_warn (_("Can't deal with expression; defaulting to %ld"),
5352 offs (exp));
5353 }
5354 }
5355
5356 if (exp->size != SIZE_UNSPEC)
5357 {
5358 switch (exp->size)
5359 {
5360 case SIZE_UNSPEC:
5361 case SIZE_LONG:
5362 break;
5363 case SIZE_BYTE:
5364 if (!isbyte (offs (exp)))
5365 as_warn (_("expression doesn't fit in BYTE"));
5366 break;
5367 case SIZE_WORD:
5368 if (!isword (offs (exp)))
5369 as_warn (_("expression doesn't fit in WORD"));
5370 break;
5371 }
5372 }
5373
5374 return offs (exp);
5375 }
5376
5377 /* These are the back-ends for the various machine dependent pseudo-ops. */
5378
5379 static void
5380 s_data1 (ignore)
5381 int ignore ATTRIBUTE_UNUSED;
5382 {
5383 subseg_set (data_section, 1);
5384 demand_empty_rest_of_line ();
5385 }
5386
5387 static void
5388 s_data2 (ignore)
5389 int ignore ATTRIBUTE_UNUSED;
5390 {
5391 subseg_set (data_section, 2);
5392 demand_empty_rest_of_line ();
5393 }
5394
5395 static void
5396 s_bss (ignore)
5397 int ignore ATTRIBUTE_UNUSED;
5398 {
5399 /* We don't support putting frags in the BSS segment, we fake it
5400 by marking in_bss, then looking at s_skip for clues. */
5401
5402 subseg_set (bss_section, 0);
5403 demand_empty_rest_of_line ();
5404 }
5405
5406 static void
5407 s_even (ignore)
5408 int ignore ATTRIBUTE_UNUSED;
5409 {
5410 register int temp;
5411 register long temp_fill;
5412
5413 temp = 1; /* JF should be 2? */
5414 temp_fill = get_absolute_expression ();
5415 if (!need_pass_2) /* Never make frag if expect extra pass. */
5416 frag_align (temp, (int) temp_fill, 0);
5417 demand_empty_rest_of_line ();
5418 record_alignment (now_seg, temp);
5419 }
5420
5421 static void
5422 s_proc (ignore)
5423 int ignore ATTRIBUTE_UNUSED;
5424 {
5425 demand_empty_rest_of_line ();
5426 }
5427 \f
5428 /* Pseudo-ops handled for MRI compatibility. */
5429
5430 /* This function returns non-zero if the argument is a conditional
5431 pseudo-op. This is called when checking whether a pending
5432 alignment is needed. */
5433
5434 int
5435 m68k_conditional_pseudoop (pop)
5436 pseudo_typeS *pop;
5437 {
5438 return (pop->poc_handler == s_mri_if
5439 || pop->poc_handler == s_mri_else);
5440 }
5441
5442 /* Handle an MRI style chip specification. */
5443
5444 static void
5445 mri_chip ()
5446 {
5447 char *s;
5448 char c;
5449 int i;
5450
5451 s = input_line_pointer;
5452 /* We can't use get_symbol_end since the processor names are not proper
5453 symbols. */
5454 while (is_part_of_name (c = *input_line_pointer++))
5455 ;
5456 *--input_line_pointer = 0;
5457 for (i = 0; i < n_archs; i++)
5458 if (strcasecmp (s, archs[i].name) == 0)
5459 break;
5460 if (i >= n_archs)
5461 {
5462 as_bad (_("%s: unrecognized processor name"), s);
5463 *input_line_pointer = c;
5464 ignore_rest_of_line ();
5465 return;
5466 }
5467 *input_line_pointer = c;
5468
5469 if (*input_line_pointer == '/')
5470 current_architecture = 0;
5471 else
5472 current_architecture &= m68881 | m68851;
5473 current_architecture |= archs[i].arch;
5474 current_chip = archs[i].chip;
5475
5476 while (*input_line_pointer == '/')
5477 {
5478 ++input_line_pointer;
5479 s = input_line_pointer;
5480 /* We can't use get_symbol_end since the processor names are not
5481 proper symbols. */
5482 while (is_part_of_name (c = *input_line_pointer++))
5483 ;
5484 *--input_line_pointer = 0;
5485 if (strcmp (s, "68881") == 0)
5486 current_architecture |= m68881;
5487 else if (strcmp (s, "68851") == 0)
5488 current_architecture |= m68851;
5489 *input_line_pointer = c;
5490 }
5491
5492 /* Update info about available control registers. */
5493 select_control_regs ();
5494 }
5495
5496 /* The MRI CHIP pseudo-op. */
5497
5498 static void
5499 s_chip (ignore)
5500 int ignore ATTRIBUTE_UNUSED;
5501 {
5502 char *stop = NULL;
5503 char stopc;
5504
5505 if (flag_mri)
5506 stop = mri_comment_field (&stopc);
5507 mri_chip ();
5508 if (flag_mri)
5509 mri_comment_end (stop, stopc);
5510 demand_empty_rest_of_line ();
5511 }
5512
5513 /* The MRI FOPT pseudo-op. */
5514
5515 static void
5516 s_fopt (ignore)
5517 int ignore ATTRIBUTE_UNUSED;
5518 {
5519 SKIP_WHITESPACE ();
5520
5521 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5522 {
5523 int temp;
5524
5525 input_line_pointer += 3;
5526 temp = get_absolute_expression ();
5527 if (temp < 0 || temp > 7)
5528 as_bad (_("bad coprocessor id"));
5529 else
5530 m68k_float_copnum = COP0 + temp;
5531 }
5532 else
5533 {
5534 as_bad (_("unrecognized fopt option"));
5535 ignore_rest_of_line ();
5536 return;
5537 }
5538
5539 demand_empty_rest_of_line ();
5540 }
5541
5542 /* The structure used to handle the MRI OPT pseudo-op. */
5543
5544 struct opt_action
5545 {
5546 /* The name of the option. */
5547 const char *name;
5548
5549 /* If this is not NULL, just call this function. The first argument
5550 is the ARG field of this structure, the second argument is
5551 whether the option was negated. */
5552 void (*pfn) PARAMS ((int arg, int on));
5553
5554 /* If this is not NULL, and the PFN field is NULL, set the variable
5555 this points to. Set it to the ARG field if the option was not
5556 negated, and the NOTARG field otherwise. */
5557 int *pvar;
5558
5559 /* The value to pass to PFN or to assign to *PVAR. */
5560 int arg;
5561
5562 /* The value to assign to *PVAR if the option is negated. If PFN is
5563 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5564 the option may not be negated. */
5565 int notarg;
5566 };
5567
5568 /* The table used to handle the MRI OPT pseudo-op. */
5569
5570 static void skip_to_comma PARAMS ((int, int));
5571 static void opt_nest PARAMS ((int, int));
5572 static void opt_chip PARAMS ((int, int));
5573 static void opt_list PARAMS ((int, int));
5574 static void opt_list_symbols PARAMS ((int, int));
5575
5576 static const struct opt_action opt_table[] =
5577 {
5578 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5579
5580 /* We do relaxing, so there is little use for these options. */
5581 { "b", 0, 0, 0, 0 },
5582 { "brs", 0, 0, 0, 0 },
5583 { "brb", 0, 0, 0, 0 },
5584 { "brl", 0, 0, 0, 0 },
5585 { "brw", 0, 0, 0, 0 },
5586
5587 { "c", 0, 0, 0, 0 },
5588 { "cex", 0, 0, 0, 0 },
5589 { "case", 0, &symbols_case_sensitive, 1, 0 },
5590 { "cl", 0, 0, 0, 0 },
5591 { "cre", 0, 0, 0, 0 },
5592 { "d", 0, &flag_keep_locals, 1, 0 },
5593 { "e", 0, 0, 0, 0 },
5594 { "f", 0, &flag_short_refs, 1, 0 },
5595 { "frs", 0, &flag_short_refs, 1, 0 },
5596 { "frl", 0, &flag_short_refs, 0, 1 },
5597 { "g", 0, 0, 0, 0 },
5598 { "i", 0, 0, 0, 0 },
5599 { "m", 0, 0, 0, 0 },
5600 { "mex", 0, 0, 0, 0 },
5601 { "mc", 0, 0, 0, 0 },
5602 { "md", 0, 0, 0, 0 },
5603 { "nest", opt_nest, 0, 0, 0 },
5604 { "next", skip_to_comma, 0, 0, 0 },
5605 { "o", 0, 0, 0, 0 },
5606 { "old", 0, 0, 0, 0 },
5607 { "op", skip_to_comma, 0, 0, 0 },
5608 { "pco", 0, 0, 0, 0 },
5609 { "p", opt_chip, 0, 0, 0 },
5610 { "pcr", 0, 0, 0, 0 },
5611 { "pcs", 0, 0, 0, 0 },
5612 { "r", 0, 0, 0, 0 },
5613 { "quick", 0, &m68k_quick, 1, 0 },
5614 { "rel32", 0, &m68k_rel32, 1, 0 },
5615 { "s", opt_list, 0, 0, 0 },
5616 { "t", opt_list_symbols, 0, 0, 0 },
5617 { "w", 0, &flag_no_warnings, 0, 1 },
5618 { "x", 0, 0, 0, 0 }
5619 };
5620
5621 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5622
5623 /* The MRI OPT pseudo-op. */
5624
5625 static void
5626 s_opt (ignore)
5627 int ignore ATTRIBUTE_UNUSED;
5628 {
5629 do
5630 {
5631 int t;
5632 char *s;
5633 char c;
5634 int i;
5635 const struct opt_action *o;
5636
5637 SKIP_WHITESPACE ();
5638
5639 t = 1;
5640 if (*input_line_pointer == '-')
5641 {
5642 ++input_line_pointer;
5643 t = 0;
5644 }
5645 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5646 {
5647 input_line_pointer += 2;
5648 t = 0;
5649 }
5650
5651 s = input_line_pointer;
5652 c = get_symbol_end ();
5653
5654 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5655 {
5656 if (strcasecmp (s, o->name) == 0)
5657 {
5658 if (o->pfn)
5659 {
5660 /* Restore input_line_pointer now in case the option
5661 takes arguments. */
5662 *input_line_pointer = c;
5663 (*o->pfn) (o->arg, t);
5664 }
5665 else if (o->pvar != NULL)
5666 {
5667 if (! t && o->arg == o->notarg)
5668 as_bad (_("option `%s' may not be negated"), s);
5669 *input_line_pointer = c;
5670 *o->pvar = t ? o->arg : o->notarg;
5671 }
5672 else
5673 *input_line_pointer = c;
5674 break;
5675 }
5676 }
5677 if (i >= OPTCOUNT)
5678 {
5679 as_bad (_("option `%s' not recognized"), s);
5680 *input_line_pointer = c;
5681 }
5682 }
5683 while (*input_line_pointer++ == ',');
5684
5685 /* Move back to terminating character. */
5686 --input_line_pointer;
5687 demand_empty_rest_of_line ();
5688 }
5689
5690 /* Skip ahead to a comma. This is used for OPT options which we do
5691 not support and which take arguments. */
5692
5693 static void
5694 skip_to_comma (arg, on)
5695 int arg ATTRIBUTE_UNUSED;
5696 int on ATTRIBUTE_UNUSED;
5697 {
5698 while (*input_line_pointer != ','
5699 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5700 ++input_line_pointer;
5701 }
5702
5703 /* Handle the OPT NEST=depth option. */
5704
5705 static void
5706 opt_nest (arg, on)
5707 int arg ATTRIBUTE_UNUSED;
5708 int on ATTRIBUTE_UNUSED;
5709 {
5710 if (*input_line_pointer != '=')
5711 {
5712 as_bad (_("bad format of OPT NEST=depth"));
5713 return;
5714 }
5715
5716 ++input_line_pointer;
5717 max_macro_nest = get_absolute_expression ();
5718 }
5719
5720 /* Handle the OPT P=chip option. */
5721
5722 static void
5723 opt_chip (arg, on)
5724 int arg ATTRIBUTE_UNUSED;
5725 int on ATTRIBUTE_UNUSED;
5726 {
5727 if (*input_line_pointer != '=')
5728 {
5729 /* This is just OPT P, which we do not support. */
5730 return;
5731 }
5732
5733 ++input_line_pointer;
5734 mri_chip ();
5735 }
5736
5737 /* Handle the OPT S option. */
5738
5739 static void
5740 opt_list (arg, on)
5741 int arg ATTRIBUTE_UNUSED;
5742 int on;
5743 {
5744 listing_list (on);
5745 }
5746
5747 /* Handle the OPT T option. */
5748
5749 static void
5750 opt_list_symbols (arg, on)
5751 int arg ATTRIBUTE_UNUSED;
5752 int on;
5753 {
5754 if (on)
5755 listing |= LISTING_SYMBOLS;
5756 else
5757 listing &= ~LISTING_SYMBOLS;
5758 }
5759
5760 /* Handle the MRI REG pseudo-op. */
5761
5762 static void
5763 s_reg (ignore)
5764 int ignore ATTRIBUTE_UNUSED;
5765 {
5766 char *s;
5767 int c;
5768 struct m68k_op rop;
5769 int mask;
5770 char *stop = NULL;
5771 char stopc;
5772
5773 if (line_label == NULL)
5774 {
5775 as_bad (_("missing label"));
5776 ignore_rest_of_line ();
5777 return;
5778 }
5779
5780 if (flag_mri)
5781 stop = mri_comment_field (&stopc);
5782
5783 SKIP_WHITESPACE ();
5784
5785 s = input_line_pointer;
5786 while (ISALNUM (*input_line_pointer)
5787 #ifdef REGISTER_PREFIX
5788 || *input_line_pointer == REGISTER_PREFIX
5789 #endif
5790 || *input_line_pointer == '/'
5791 || *input_line_pointer == '-')
5792 ++input_line_pointer;
5793 c = *input_line_pointer;
5794 *input_line_pointer = '\0';
5795
5796 if (m68k_ip_op (s, &rop) != 0)
5797 {
5798 if (rop.error == NULL)
5799 as_bad (_("bad register list"));
5800 else
5801 as_bad (_("bad register list: %s"), rop.error);
5802 *input_line_pointer = c;
5803 ignore_rest_of_line ();
5804 return;
5805 }
5806
5807 *input_line_pointer = c;
5808
5809 if (rop.mode == REGLST)
5810 mask = rop.mask;
5811 else if (rop.mode == DREG)
5812 mask = 1 << (rop.reg - DATA0);
5813 else if (rop.mode == AREG)
5814 mask = 1 << (rop.reg - ADDR0 + 8);
5815 else if (rop.mode == FPREG)
5816 mask = 1 << (rop.reg - FP0 + 16);
5817 else if (rop.mode == CONTROL
5818 && rop.reg == FPI)
5819 mask = 1 << 24;
5820 else if (rop.mode == CONTROL
5821 && rop.reg == FPS)
5822 mask = 1 << 25;
5823 else if (rop.mode == CONTROL
5824 && rop.reg == FPC)
5825 mask = 1 << 26;
5826 else
5827 {
5828 as_bad (_("bad register list"));
5829 ignore_rest_of_line ();
5830 return;
5831 }
5832
5833 S_SET_SEGMENT (line_label, reg_section);
5834 S_SET_VALUE (line_label, ~mask);
5835 symbol_set_frag (line_label, &zero_address_frag);
5836
5837 if (flag_mri)
5838 mri_comment_end (stop, stopc);
5839
5840 demand_empty_rest_of_line ();
5841 }
5842
5843 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5844
5845 struct save_opts
5846 {
5847 struct save_opts *next;
5848 int abspcadd;
5849 int symbols_case_sensitive;
5850 int keep_locals;
5851 int short_refs;
5852 int architecture;
5853 int chip;
5854 int quick;
5855 int rel32;
5856 int listing;
5857 int no_warnings;
5858 /* FIXME: We don't save OPT S. */
5859 };
5860
5861 /* This variable holds the stack of saved options. */
5862
5863 static struct save_opts *save_stack;
5864
5865 /* The MRI SAVE pseudo-op. */
5866
5867 static void
5868 s_save (ignore)
5869 int ignore ATTRIBUTE_UNUSED;
5870 {
5871 struct save_opts *s;
5872
5873 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5874 s->abspcadd = m68k_abspcadd;
5875 s->symbols_case_sensitive = symbols_case_sensitive;
5876 s->keep_locals = flag_keep_locals;
5877 s->short_refs = flag_short_refs;
5878 s->architecture = current_architecture;
5879 s->chip = current_chip;
5880 s->quick = m68k_quick;
5881 s->rel32 = m68k_rel32;
5882 s->listing = listing;
5883 s->no_warnings = flag_no_warnings;
5884
5885 s->next = save_stack;
5886 save_stack = s;
5887
5888 demand_empty_rest_of_line ();
5889 }
5890
5891 /* The MRI RESTORE pseudo-op. */
5892
5893 static void
5894 s_restore (ignore)
5895 int ignore ATTRIBUTE_UNUSED;
5896 {
5897 struct save_opts *s;
5898
5899 if (save_stack == NULL)
5900 {
5901 as_bad (_("restore without save"));
5902 ignore_rest_of_line ();
5903 return;
5904 }
5905
5906 s = save_stack;
5907 save_stack = s->next;
5908
5909 m68k_abspcadd = s->abspcadd;
5910 symbols_case_sensitive = s->symbols_case_sensitive;
5911 flag_keep_locals = s->keep_locals;
5912 flag_short_refs = s->short_refs;
5913 current_architecture = s->architecture;
5914 current_chip = s->chip;
5915 m68k_quick = s->quick;
5916 m68k_rel32 = s->rel32;
5917 listing = s->listing;
5918 flag_no_warnings = s->no_warnings;
5919
5920 free (s);
5921
5922 demand_empty_rest_of_line ();
5923 }
5924
5925 /* Types of MRI structured control directives. */
5926
5927 enum mri_control_type
5928 {
5929 mri_for,
5930 mri_if,
5931 mri_repeat,
5932 mri_while
5933 };
5934
5935 /* This structure is used to stack the MRI structured control
5936 directives. */
5937
5938 struct mri_control_info
5939 {
5940 /* The directive within which this one is enclosed. */
5941 struct mri_control_info *outer;
5942
5943 /* The type of directive. */
5944 enum mri_control_type type;
5945
5946 /* Whether an ELSE has been in an IF. */
5947 int else_seen;
5948
5949 /* The add or sub statement at the end of a FOR. */
5950 char *incr;
5951
5952 /* The label of the top of a FOR or REPEAT loop. */
5953 char *top;
5954
5955 /* The label to jump to for the next iteration, or the else
5956 expression of a conditional. */
5957 char *next;
5958
5959 /* The label to jump to to break out of the loop, or the label past
5960 the end of a conditional. */
5961 char *bottom;
5962 };
5963
5964 /* The stack of MRI structured control directives. */
5965
5966 static struct mri_control_info *mri_control_stack;
5967
5968 /* The current MRI structured control directive index number, used to
5969 generate label names. */
5970
5971 static int mri_control_index;
5972
5973 /* Some function prototypes. */
5974
5975 static void mri_assemble PARAMS ((char *));
5976 static char *mri_control_label PARAMS ((void));
5977 static struct mri_control_info *push_mri_control
5978 PARAMS ((enum mri_control_type));
5979 static void pop_mri_control PARAMS ((void));
5980 static int parse_mri_condition PARAMS ((int *));
5981 static int parse_mri_control_operand
5982 PARAMS ((int *, char **, char **, char **, char **));
5983 static int swap_mri_condition PARAMS ((int));
5984 static int reverse_mri_condition PARAMS ((int));
5985 static void build_mri_control_operand
5986 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5987 const char *, int));
5988 static void parse_mri_control_expression
5989 PARAMS ((char *, int, const char *, const char *, int));
5990
5991 /* Assemble an instruction for an MRI structured control directive. */
5992
5993 static void
5994 mri_assemble (str)
5995 char *str;
5996 {
5997 char *s;
5998
5999 /* md_assemble expects the opcode to be in lower case. */
6000 for (s = str; *s != ' ' && *s != '\0'; s++)
6001 *s = TOLOWER (*s);
6002
6003 md_assemble (str);
6004 }
6005
6006 /* Generate a new MRI label structured control directive label name. */
6007
6008 static char *
6009 mri_control_label ()
6010 {
6011 char *n;
6012
6013 n = (char *) xmalloc (20);
6014 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6015 ++mri_control_index;
6016 return n;
6017 }
6018
6019 /* Create a new MRI structured control directive. */
6020
6021 static struct mri_control_info *
6022 push_mri_control (type)
6023 enum mri_control_type type;
6024 {
6025 struct mri_control_info *n;
6026
6027 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6028
6029 n->type = type;
6030 n->else_seen = 0;
6031 if (type == mri_if || type == mri_while)
6032 n->top = NULL;
6033 else
6034 n->top = mri_control_label ();
6035 n->next = mri_control_label ();
6036 n->bottom = mri_control_label ();
6037
6038 n->outer = mri_control_stack;
6039 mri_control_stack = n;
6040
6041 return n;
6042 }
6043
6044 /* Pop off the stack of MRI structured control directives. */
6045
6046 static void
6047 pop_mri_control ()
6048 {
6049 struct mri_control_info *n;
6050
6051 n = mri_control_stack;
6052 mri_control_stack = n->outer;
6053 if (n->top != NULL)
6054 free (n->top);
6055 free (n->next);
6056 free (n->bottom);
6057 free (n);
6058 }
6059
6060 /* Recognize a condition code in an MRI structured control expression. */
6061
6062 static int
6063 parse_mri_condition (pcc)
6064 int *pcc;
6065 {
6066 char c1, c2;
6067
6068 know (*input_line_pointer == '<');
6069
6070 ++input_line_pointer;
6071 c1 = *input_line_pointer++;
6072 c2 = *input_line_pointer++;
6073
6074 if (*input_line_pointer != '>')
6075 {
6076 as_bad (_("syntax error in structured control directive"));
6077 return 0;
6078 }
6079
6080 ++input_line_pointer;
6081 SKIP_WHITESPACE ();
6082
6083 c1 = TOLOWER (c1);
6084 c2 = TOLOWER (c2);
6085
6086 *pcc = (c1 << 8) | c2;
6087
6088 return 1;
6089 }
6090
6091 /* Parse a single operand in an MRI structured control expression. */
6092
6093 static int
6094 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
6095 int *pcc;
6096 char **leftstart;
6097 char **leftstop;
6098 char **rightstart;
6099 char **rightstop;
6100 {
6101 char *s;
6102
6103 SKIP_WHITESPACE ();
6104
6105 *pcc = -1;
6106 *leftstart = NULL;
6107 *leftstop = NULL;
6108 *rightstart = NULL;
6109 *rightstop = NULL;
6110
6111 if (*input_line_pointer == '<')
6112 {
6113 /* It's just a condition code. */
6114 return parse_mri_condition (pcc);
6115 }
6116
6117 /* Look ahead for the condition code. */
6118 for (s = input_line_pointer; *s != '\0'; ++s)
6119 {
6120 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6121 break;
6122 }
6123 if (*s == '\0')
6124 {
6125 as_bad (_("missing condition code in structured control directive"));
6126 return 0;
6127 }
6128
6129 *leftstart = input_line_pointer;
6130 *leftstop = s;
6131 if (*leftstop > *leftstart
6132 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6133 --*leftstop;
6134
6135 input_line_pointer = s;
6136 if (! parse_mri_condition (pcc))
6137 return 0;
6138
6139 /* Look ahead for AND or OR or end of line. */
6140 for (s = input_line_pointer; *s != '\0'; ++s)
6141 {
6142 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6143 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6144 ^^^ ^^ */
6145 if ((s == input_line_pointer
6146 || *(s-1) == ' '
6147 || *(s-1) == '\t')
6148 && ((strncasecmp (s, "AND", 3) == 0
6149 && (s[3] == '.' || ! is_part_of_name (s[3])))
6150 || (strncasecmp (s, "OR", 2) == 0
6151 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6152 break;
6153 }
6154
6155 *rightstart = input_line_pointer;
6156 *rightstop = s;
6157 if (*rightstop > *rightstart
6158 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6159 --*rightstop;
6160
6161 input_line_pointer = s;
6162
6163 return 1;
6164 }
6165
6166 #define MCC(b1, b2) (((b1) << 8) | (b2))
6167
6168 /* Swap the sense of a condition. This changes the condition so that
6169 it generates the same result when the operands are swapped. */
6170
6171 static int
6172 swap_mri_condition (cc)
6173 int cc;
6174 {
6175 switch (cc)
6176 {
6177 case MCC ('h', 'i'): return MCC ('c', 's');
6178 case MCC ('l', 's'): return MCC ('c', 'c');
6179 /* <HS> is an alias for <CC>. */
6180 case MCC ('h', 's'):
6181 case MCC ('c', 'c'): return MCC ('l', 's');
6182 /* <LO> is an alias for <CS>. */
6183 case MCC ('l', 'o'):
6184 case MCC ('c', 's'): return MCC ('h', 'i');
6185 case MCC ('p', 'l'): return MCC ('m', 'i');
6186 case MCC ('m', 'i'): return MCC ('p', 'l');
6187 case MCC ('g', 'e'): return MCC ('l', 'e');
6188 case MCC ('l', 't'): return MCC ('g', 't');
6189 case MCC ('g', 't'): return MCC ('l', 't');
6190 case MCC ('l', 'e'): return MCC ('g', 'e');
6191 /* Issue a warning for conditions we can not swap. */
6192 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6193 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6194 case MCC ('v', 'c'):
6195 case MCC ('v', 's'):
6196 default :
6197 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6198 (char) (cc >> 8), (char) (cc));
6199 break;
6200 }
6201 return cc;
6202 }
6203
6204 /* Reverse the sense of a condition. */
6205
6206 static int
6207 reverse_mri_condition (cc)
6208 int cc;
6209 {
6210 switch (cc)
6211 {
6212 case MCC ('h', 'i'): return MCC ('l', 's');
6213 case MCC ('l', 's'): return MCC ('h', 'i');
6214 /* <HS> is an alias for <CC> */
6215 case MCC ('h', 's'): return MCC ('l', 'o');
6216 case MCC ('c', 'c'): return MCC ('c', 's');
6217 /* <LO> is an alias for <CS> */
6218 case MCC ('l', 'o'): return MCC ('h', 's');
6219 case MCC ('c', 's'): return MCC ('c', 'c');
6220 case MCC ('n', 'e'): return MCC ('e', 'q');
6221 case MCC ('e', 'q'): return MCC ('n', 'e');
6222 case MCC ('v', 'c'): return MCC ('v', 's');
6223 case MCC ('v', 's'): return MCC ('v', 'c');
6224 case MCC ('p', 'l'): return MCC ('m', 'i');
6225 case MCC ('m', 'i'): return MCC ('p', 'l');
6226 case MCC ('g', 'e'): return MCC ('l', 't');
6227 case MCC ('l', 't'): return MCC ('g', 'e');
6228 case MCC ('g', 't'): return MCC ('l', 'e');
6229 case MCC ('l', 'e'): return MCC ('g', 't');
6230 }
6231 return cc;
6232 }
6233
6234 /* Build an MRI structured control expression. This generates test
6235 and branch instructions. It goes to TRUELAB if the condition is
6236 true, and to FALSELAB if the condition is false. Exactly one of
6237 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6238 is the size qualifier for the expression. EXTENT is the size to
6239 use for the branch. */
6240
6241 static void
6242 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6243 rightstop, truelab, falselab, extent)
6244 int qual;
6245 int cc;
6246 char *leftstart;
6247 char *leftstop;
6248 char *rightstart;
6249 char *rightstop;
6250 const char *truelab;
6251 const char *falselab;
6252 int extent;
6253 {
6254 char *buf;
6255 char *s;
6256
6257 if (leftstart != NULL)
6258 {
6259 struct m68k_op leftop, rightop;
6260 char c;
6261
6262 /* Swap the compare operands, if necessary, to produce a legal
6263 m68k compare instruction. Comparing a register operand with
6264 a non-register operand requires the register to be on the
6265 right (cmp, cmpa). Comparing an immediate value with
6266 anything requires the immediate value to be on the left
6267 (cmpi). */
6268
6269 c = *leftstop;
6270 *leftstop = '\0';
6271 (void) m68k_ip_op (leftstart, &leftop);
6272 *leftstop = c;
6273
6274 c = *rightstop;
6275 *rightstop = '\0';
6276 (void) m68k_ip_op (rightstart, &rightop);
6277 *rightstop = c;
6278
6279 if (rightop.mode == IMMED
6280 || ((leftop.mode == DREG || leftop.mode == AREG)
6281 && (rightop.mode != DREG && rightop.mode != AREG)))
6282 {
6283 char *temp;
6284
6285 /* Correct conditional handling:
6286 if #1 <lt> d0 then ;means if (1 < d0)
6287 ...
6288 endi
6289
6290 should assemble to:
6291
6292 cmp #1,d0 if we do *not* swap the operands
6293 bgt true we need the swapped condition!
6294 ble false
6295 true:
6296 ...
6297 false:
6298 */
6299 temp = leftstart;
6300 leftstart = rightstart;
6301 rightstart = temp;
6302 temp = leftstop;
6303 leftstop = rightstop;
6304 rightstop = temp;
6305 }
6306 else
6307 {
6308 cc = swap_mri_condition (cc);
6309 }
6310 }
6311
6312 if (truelab == NULL)
6313 {
6314 cc = reverse_mri_condition (cc);
6315 truelab = falselab;
6316 }
6317
6318 if (leftstart != NULL)
6319 {
6320 buf = (char *) xmalloc (20
6321 + (leftstop - leftstart)
6322 + (rightstop - rightstart));
6323 s = buf;
6324 *s++ = 'c';
6325 *s++ = 'm';
6326 *s++ = 'p';
6327 if (qual != '\0')
6328 *s++ = TOLOWER (qual);
6329 *s++ = ' ';
6330 memcpy (s, leftstart, leftstop - leftstart);
6331 s += leftstop - leftstart;
6332 *s++ = ',';
6333 memcpy (s, rightstart, rightstop - rightstart);
6334 s += rightstop - rightstart;
6335 *s = '\0';
6336 mri_assemble (buf);
6337 free (buf);
6338 }
6339
6340 buf = (char *) xmalloc (20 + strlen (truelab));
6341 s = buf;
6342 *s++ = 'b';
6343 *s++ = cc >> 8;
6344 *s++ = cc & 0xff;
6345 if (extent != '\0')
6346 *s++ = TOLOWER (extent);
6347 *s++ = ' ';
6348 strcpy (s, truelab);
6349 mri_assemble (buf);
6350 free (buf);
6351 }
6352
6353 /* Parse an MRI structured control expression. This generates test
6354 and branch instructions. STOP is where the expression ends. It
6355 goes to TRUELAB if the condition is true, and to FALSELAB if the
6356 condition is false. Exactly one of TRUELAB and FALSELAB will be
6357 NULL, meaning to fall through. QUAL is the size qualifier for the
6358 expression. EXTENT is the size to use for the branch. */
6359
6360 static void
6361 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
6362 char *stop;
6363 int qual;
6364 const char *truelab;
6365 const char *falselab;
6366 int extent;
6367 {
6368 int c;
6369 int cc;
6370 char *leftstart;
6371 char *leftstop;
6372 char *rightstart;
6373 char *rightstop;
6374
6375 c = *stop;
6376 *stop = '\0';
6377
6378 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6379 &rightstart, &rightstop))
6380 {
6381 *stop = c;
6382 return;
6383 }
6384
6385 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6386 {
6387 const char *flab;
6388
6389 if (falselab != NULL)
6390 flab = falselab;
6391 else
6392 flab = mri_control_label ();
6393
6394 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6395 rightstop, (const char *) NULL, flab, extent);
6396
6397 input_line_pointer += 3;
6398 if (*input_line_pointer != '.'
6399 || input_line_pointer[1] == '\0')
6400 qual = '\0';
6401 else
6402 {
6403 qual = input_line_pointer[1];
6404 input_line_pointer += 2;
6405 }
6406
6407 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6408 &rightstart, &rightstop))
6409 {
6410 *stop = c;
6411 return;
6412 }
6413
6414 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6415 rightstop, truelab, falselab, extent);
6416
6417 if (falselab == NULL)
6418 colon (flab);
6419 }
6420 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6421 {
6422 const char *tlab;
6423
6424 if (truelab != NULL)
6425 tlab = truelab;
6426 else
6427 tlab = mri_control_label ();
6428
6429 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6430 rightstop, tlab, (const char *) NULL, extent);
6431
6432 input_line_pointer += 2;
6433 if (*input_line_pointer != '.'
6434 || input_line_pointer[1] == '\0')
6435 qual = '\0';
6436 else
6437 {
6438 qual = input_line_pointer[1];
6439 input_line_pointer += 2;
6440 }
6441
6442 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6443 &rightstart, &rightstop))
6444 {
6445 *stop = c;
6446 return;
6447 }
6448
6449 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6450 rightstop, truelab, falselab, extent);
6451
6452 if (truelab == NULL)
6453 colon (tlab);
6454 }
6455 else
6456 {
6457 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6458 rightstop, truelab, falselab, extent);
6459 }
6460
6461 *stop = c;
6462 if (input_line_pointer != stop)
6463 as_bad (_("syntax error in structured control directive"));
6464 }
6465
6466 /* Handle the MRI IF pseudo-op. This may be a structured control
6467 directive, or it may be a regular assembler conditional, depending
6468 on its operands. */
6469
6470 static void
6471 s_mri_if (qual)
6472 int qual;
6473 {
6474 char *s;
6475 int c;
6476 struct mri_control_info *n;
6477
6478 /* A structured control directive must end with THEN with an
6479 optional qualifier. */
6480 s = input_line_pointer;
6481 /* We only accept '*' as introduction of comments if preceded by white space
6482 or at first column of a line (I think this can't actually happen here?)
6483 This is important when assembling:
6484 if d0 <ne> 12(a0,d0*2) then
6485 if d0 <ne> #CONST*20 then. */
6486 while ( ! ( is_end_of_line[(unsigned char) *s]
6487 || ( flag_mri
6488 && *s == '*'
6489 && ( s == input_line_pointer
6490 || *(s-1) == ' '
6491 || *(s-1) == '\t'))))
6492 ++s;
6493 --s;
6494 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6495 --s;
6496
6497 if (s - input_line_pointer > 1
6498 && s[-1] == '.')
6499 s -= 2;
6500
6501 if (s - input_line_pointer < 3
6502 || strncasecmp (s - 3, "THEN", 4) != 0)
6503 {
6504 if (qual != '\0')
6505 {
6506 as_bad (_("missing then"));
6507 ignore_rest_of_line ();
6508 return;
6509 }
6510
6511 /* It's a conditional. */
6512 s_if (O_ne);
6513 return;
6514 }
6515
6516 /* Since this might be a conditional if, this pseudo-op will be
6517 called even if we are supported to be ignoring input. Double
6518 check now. Clobber *input_line_pointer so that ignore_input
6519 thinks that this is not a special pseudo-op. */
6520 c = *input_line_pointer;
6521 *input_line_pointer = 0;
6522 if (ignore_input ())
6523 {
6524 *input_line_pointer = c;
6525 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6526 ++input_line_pointer;
6527 demand_empty_rest_of_line ();
6528 return;
6529 }
6530 *input_line_pointer = c;
6531
6532 n = push_mri_control (mri_if);
6533
6534 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6535 n->next, s[1] == '.' ? s[2] : '\0');
6536
6537 if (s[1] == '.')
6538 input_line_pointer = s + 3;
6539 else
6540 input_line_pointer = s + 1;
6541
6542 if (flag_mri)
6543 {
6544 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6545 ++input_line_pointer;
6546 }
6547
6548 demand_empty_rest_of_line ();
6549 }
6550
6551 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6552 structured IF, associate the ELSE with the IF. Otherwise, assume
6553 it is a conditional else. */
6554
6555 static void
6556 s_mri_else (qual)
6557 int qual;
6558 {
6559 int c;
6560 char *buf;
6561 char q[2];
6562
6563 if (qual == '\0'
6564 && (mri_control_stack == NULL
6565 || mri_control_stack->type != mri_if
6566 || mri_control_stack->else_seen))
6567 {
6568 s_else (0);
6569 return;
6570 }
6571
6572 c = *input_line_pointer;
6573 *input_line_pointer = 0;
6574 if (ignore_input ())
6575 {
6576 *input_line_pointer = c;
6577 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6578 ++input_line_pointer;
6579 demand_empty_rest_of_line ();
6580 return;
6581 }
6582 *input_line_pointer = c;
6583
6584 if (mri_control_stack == NULL
6585 || mri_control_stack->type != mri_if
6586 || mri_control_stack->else_seen)
6587 {
6588 as_bad (_("else without matching if"));
6589 ignore_rest_of_line ();
6590 return;
6591 }
6592
6593 mri_control_stack->else_seen = 1;
6594
6595 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6596 q[0] = TOLOWER (qual);
6597 q[1] = '\0';
6598 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6599 mri_assemble (buf);
6600 free (buf);
6601
6602 colon (mri_control_stack->next);
6603
6604 if (flag_mri)
6605 {
6606 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6607 ++input_line_pointer;
6608 }
6609
6610 demand_empty_rest_of_line ();
6611 }
6612
6613 /* Handle the MRI ENDI pseudo-op. */
6614
6615 static void
6616 s_mri_endi (ignore)
6617 int ignore ATTRIBUTE_UNUSED;
6618 {
6619 if (mri_control_stack == NULL
6620 || mri_control_stack->type != mri_if)
6621 {
6622 as_bad (_("endi without matching if"));
6623 ignore_rest_of_line ();
6624 return;
6625 }
6626
6627 /* ignore_input will not return true for ENDI, so we don't need to
6628 worry about checking it again here. */
6629
6630 if (! mri_control_stack->else_seen)
6631 colon (mri_control_stack->next);
6632 colon (mri_control_stack->bottom);
6633
6634 pop_mri_control ();
6635
6636 if (flag_mri)
6637 {
6638 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6639 ++input_line_pointer;
6640 }
6641
6642 demand_empty_rest_of_line ();
6643 }
6644
6645 /* Handle the MRI BREAK pseudo-op. */
6646
6647 static void
6648 s_mri_break (extent)
6649 int extent;
6650 {
6651 struct mri_control_info *n;
6652 char *buf;
6653 char ex[2];
6654
6655 n = mri_control_stack;
6656 while (n != NULL
6657 && n->type != mri_for
6658 && n->type != mri_repeat
6659 && n->type != mri_while)
6660 n = n->outer;
6661 if (n == NULL)
6662 {
6663 as_bad (_("break outside of structured loop"));
6664 ignore_rest_of_line ();
6665 return;
6666 }
6667
6668 buf = (char *) xmalloc (20 + strlen (n->bottom));
6669 ex[0] = TOLOWER (extent);
6670 ex[1] = '\0';
6671 sprintf (buf, "bra%s %s", ex, n->bottom);
6672 mri_assemble (buf);
6673 free (buf);
6674
6675 if (flag_mri)
6676 {
6677 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6678 ++input_line_pointer;
6679 }
6680
6681 demand_empty_rest_of_line ();
6682 }
6683
6684 /* Handle the MRI NEXT pseudo-op. */
6685
6686 static void
6687 s_mri_next (extent)
6688 int extent;
6689 {
6690 struct mri_control_info *n;
6691 char *buf;
6692 char ex[2];
6693
6694 n = mri_control_stack;
6695 while (n != NULL
6696 && n->type != mri_for
6697 && n->type != mri_repeat
6698 && n->type != mri_while)
6699 n = n->outer;
6700 if (n == NULL)
6701 {
6702 as_bad (_("next outside of structured loop"));
6703 ignore_rest_of_line ();
6704 return;
6705 }
6706
6707 buf = (char *) xmalloc (20 + strlen (n->next));
6708 ex[0] = TOLOWER (extent);
6709 ex[1] = '\0';
6710 sprintf (buf, "bra%s %s", ex, n->next);
6711 mri_assemble (buf);
6712 free (buf);
6713
6714 if (flag_mri)
6715 {
6716 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6717 ++input_line_pointer;
6718 }
6719
6720 demand_empty_rest_of_line ();
6721 }
6722
6723 /* Handle the MRI FOR pseudo-op. */
6724
6725 static void
6726 s_mri_for (qual)
6727 int qual;
6728 {
6729 const char *varstart, *varstop;
6730 const char *initstart, *initstop;
6731 const char *endstart, *endstop;
6732 const char *bystart, *bystop;
6733 int up;
6734 int by;
6735 int extent;
6736 struct mri_control_info *n;
6737 char *buf;
6738 char *s;
6739 char ex[2];
6740
6741 /* The syntax is
6742 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6743 */
6744
6745 SKIP_WHITESPACE ();
6746 varstart = input_line_pointer;
6747
6748 /* Look for the '='. */
6749 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6750 && *input_line_pointer != '=')
6751 ++input_line_pointer;
6752 if (*input_line_pointer != '=')
6753 {
6754 as_bad (_("missing ="));
6755 ignore_rest_of_line ();
6756 return;
6757 }
6758
6759 varstop = input_line_pointer;
6760 if (varstop > varstart
6761 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6762 --varstop;
6763
6764 ++input_line_pointer;
6765
6766 initstart = input_line_pointer;
6767
6768 /* Look for TO or DOWNTO. */
6769 up = 1;
6770 initstop = NULL;
6771 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6772 {
6773 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6774 && ! is_part_of_name (input_line_pointer[2]))
6775 {
6776 initstop = input_line_pointer;
6777 input_line_pointer += 2;
6778 break;
6779 }
6780 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6781 && ! is_part_of_name (input_line_pointer[6]))
6782 {
6783 initstop = input_line_pointer;
6784 up = 0;
6785 input_line_pointer += 6;
6786 break;
6787 }
6788 ++input_line_pointer;
6789 }
6790 if (initstop == NULL)
6791 {
6792 as_bad (_("missing to or downto"));
6793 ignore_rest_of_line ();
6794 return;
6795 }
6796 if (initstop > initstart
6797 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6798 --initstop;
6799
6800 SKIP_WHITESPACE ();
6801 endstart = input_line_pointer;
6802
6803 /* Look for BY or DO. */
6804 by = 0;
6805 endstop = NULL;
6806 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6807 {
6808 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6809 && ! is_part_of_name (input_line_pointer[2]))
6810 {
6811 endstop = input_line_pointer;
6812 by = 1;
6813 input_line_pointer += 2;
6814 break;
6815 }
6816 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6817 && (input_line_pointer[2] == '.'
6818 || ! is_part_of_name (input_line_pointer[2])))
6819 {
6820 endstop = input_line_pointer;
6821 input_line_pointer += 2;
6822 break;
6823 }
6824 ++input_line_pointer;
6825 }
6826 if (endstop == NULL)
6827 {
6828 as_bad (_("missing do"));
6829 ignore_rest_of_line ();
6830 return;
6831 }
6832 if (endstop > endstart
6833 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6834 --endstop;
6835
6836 if (! by)
6837 {
6838 bystart = "#1";
6839 bystop = bystart + 2;
6840 }
6841 else
6842 {
6843 SKIP_WHITESPACE ();
6844 bystart = input_line_pointer;
6845
6846 /* Look for DO. */
6847 bystop = NULL;
6848 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6849 {
6850 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6851 && (input_line_pointer[2] == '.'
6852 || ! is_part_of_name (input_line_pointer[2])))
6853 {
6854 bystop = input_line_pointer;
6855 input_line_pointer += 2;
6856 break;
6857 }
6858 ++input_line_pointer;
6859 }
6860 if (bystop == NULL)
6861 {
6862 as_bad (_("missing do"));
6863 ignore_rest_of_line ();
6864 return;
6865 }
6866 if (bystop > bystart
6867 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6868 --bystop;
6869 }
6870
6871 if (*input_line_pointer != '.')
6872 extent = '\0';
6873 else
6874 {
6875 extent = input_line_pointer[1];
6876 input_line_pointer += 2;
6877 }
6878
6879 /* We have fully parsed the FOR operands. Now build the loop. */
6880 n = push_mri_control (mri_for);
6881
6882 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6883
6884 /* Move init,var. */
6885 s = buf;
6886 *s++ = 'm';
6887 *s++ = 'o';
6888 *s++ = 'v';
6889 *s++ = 'e';
6890 if (qual != '\0')
6891 *s++ = TOLOWER (qual);
6892 *s++ = ' ';
6893 memcpy (s, initstart, initstop - initstart);
6894 s += initstop - initstart;
6895 *s++ = ',';
6896 memcpy (s, varstart, varstop - varstart);
6897 s += varstop - varstart;
6898 *s = '\0';
6899 mri_assemble (buf);
6900
6901 colon (n->top);
6902
6903 /* cmp end,var. */
6904 s = buf;
6905 *s++ = 'c';
6906 *s++ = 'm';
6907 *s++ = 'p';
6908 if (qual != '\0')
6909 *s++ = TOLOWER (qual);
6910 *s++ = ' ';
6911 memcpy (s, endstart, endstop - endstart);
6912 s += endstop - endstart;
6913 *s++ = ',';
6914 memcpy (s, varstart, varstop - varstart);
6915 s += varstop - varstart;
6916 *s = '\0';
6917 mri_assemble (buf);
6918
6919 /* bcc bottom. */
6920 ex[0] = TOLOWER (extent);
6921 ex[1] = '\0';
6922 if (up)
6923 sprintf (buf, "blt%s %s", ex, n->bottom);
6924 else
6925 sprintf (buf, "bgt%s %s", ex, n->bottom);
6926 mri_assemble (buf);
6927
6928 /* Put together the add or sub instruction used by ENDF. */
6929 s = buf;
6930 if (up)
6931 strcpy (s, "add");
6932 else
6933 strcpy (s, "sub");
6934 s += 3;
6935 if (qual != '\0')
6936 *s++ = TOLOWER (qual);
6937 *s++ = ' ';
6938 memcpy (s, bystart, bystop - bystart);
6939 s += bystop - bystart;
6940 *s++ = ',';
6941 memcpy (s, varstart, varstop - varstart);
6942 s += varstop - varstart;
6943 *s = '\0';
6944 n->incr = buf;
6945
6946 if (flag_mri)
6947 {
6948 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6949 ++input_line_pointer;
6950 }
6951
6952 demand_empty_rest_of_line ();
6953 }
6954
6955 /* Handle the MRI ENDF pseudo-op. */
6956
6957 static void
6958 s_mri_endf (ignore)
6959 int ignore ATTRIBUTE_UNUSED;
6960 {
6961 if (mri_control_stack == NULL
6962 || mri_control_stack->type != mri_for)
6963 {
6964 as_bad (_("endf without for"));
6965 ignore_rest_of_line ();
6966 return;
6967 }
6968
6969 colon (mri_control_stack->next);
6970
6971 mri_assemble (mri_control_stack->incr);
6972
6973 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6974 mri_assemble (mri_control_stack->incr);
6975
6976 free (mri_control_stack->incr);
6977
6978 colon (mri_control_stack->bottom);
6979
6980 pop_mri_control ();
6981
6982 if (flag_mri)
6983 {
6984 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6985 ++input_line_pointer;
6986 }
6987
6988 demand_empty_rest_of_line ();
6989 }
6990
6991 /* Handle the MRI REPEAT pseudo-op. */
6992
6993 static void
6994 s_mri_repeat (ignore)
6995 int ignore ATTRIBUTE_UNUSED;
6996 {
6997 struct mri_control_info *n;
6998
6999 n = push_mri_control (mri_repeat);
7000 colon (n->top);
7001 if (flag_mri)
7002 {
7003 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7004 ++input_line_pointer;
7005 }
7006 demand_empty_rest_of_line ();
7007 }
7008
7009 /* Handle the MRI UNTIL pseudo-op. */
7010
7011 static void
7012 s_mri_until (qual)
7013 int qual;
7014 {
7015 char *s;
7016
7017 if (mri_control_stack == NULL
7018 || mri_control_stack->type != mri_repeat)
7019 {
7020 as_bad (_("until without repeat"));
7021 ignore_rest_of_line ();
7022 return;
7023 }
7024
7025 colon (mri_control_stack->next);
7026
7027 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7028 ;
7029
7030 parse_mri_control_expression (s, qual, (const char *) NULL,
7031 mri_control_stack->top, '\0');
7032
7033 colon (mri_control_stack->bottom);
7034
7035 input_line_pointer = s;
7036
7037 pop_mri_control ();
7038
7039 if (flag_mri)
7040 {
7041 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7042 ++input_line_pointer;
7043 }
7044
7045 demand_empty_rest_of_line ();
7046 }
7047
7048 /* Handle the MRI WHILE pseudo-op. */
7049
7050 static void
7051 s_mri_while (qual)
7052 int qual;
7053 {
7054 char *s;
7055
7056 struct mri_control_info *n;
7057
7058 s = input_line_pointer;
7059 /* We only accept '*' as introduction of comments if preceded by white space
7060 or at first column of a line (I think this can't actually happen here?)
7061 This is important when assembling:
7062 while d0 <ne> 12(a0,d0*2) do
7063 while d0 <ne> #CONST*20 do. */
7064 while (! (is_end_of_line[(unsigned char) *s]
7065 || (flag_mri
7066 && *s == '*'
7067 && (s == input_line_pointer
7068 || *(s-1) == ' '
7069 || *(s-1) == '\t'))))
7070 s++;
7071 --s;
7072 while (*s == ' ' || *s == '\t')
7073 --s;
7074 if (s - input_line_pointer > 1
7075 && s[-1] == '.')
7076 s -= 2;
7077 if (s - input_line_pointer < 2
7078 || strncasecmp (s - 1, "DO", 2) != 0)
7079 {
7080 as_bad (_("missing do"));
7081 ignore_rest_of_line ();
7082 return;
7083 }
7084
7085 n = push_mri_control (mri_while);
7086
7087 colon (n->next);
7088
7089 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7090 s[1] == '.' ? s[2] : '\0');
7091
7092 input_line_pointer = s + 1;
7093 if (*input_line_pointer == '.')
7094 input_line_pointer += 2;
7095
7096 if (flag_mri)
7097 {
7098 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7099 ++input_line_pointer;
7100 }
7101
7102 demand_empty_rest_of_line ();
7103 }
7104
7105 /* Handle the MRI ENDW pseudo-op. */
7106
7107 static void
7108 s_mri_endw (ignore)
7109 int ignore ATTRIBUTE_UNUSED;
7110 {
7111 char *buf;
7112
7113 if (mri_control_stack == NULL
7114 || mri_control_stack->type != mri_while)
7115 {
7116 as_bad (_("endw without while"));
7117 ignore_rest_of_line ();
7118 return;
7119 }
7120
7121 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7122 sprintf (buf, "bra %s", mri_control_stack->next);
7123 mri_assemble (buf);
7124 free (buf);
7125
7126 colon (mri_control_stack->bottom);
7127
7128 pop_mri_control ();
7129
7130 if (flag_mri)
7131 {
7132 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7133 ++input_line_pointer;
7134 }
7135
7136 demand_empty_rest_of_line ();
7137 }
7138 \f
7139 /*
7140 * md_parse_option
7141 * Invocation line includes a switch not recognized by the base assembler.
7142 * See if it's a processor-specific option. These are:
7143 *
7144 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
7145 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
7146 * Select the architecture. Instructions or features not
7147 * supported by the selected architecture cause fatal
7148 * errors. More than one may be specified. The default is
7149 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
7150 * for -m68000, and -m68882 is a synonym for -m68881.
7151 * -[A]m[c]no-68851, -[A]m[c]no-68881
7152 * Don't accept 688?1 instructions. (The "c" is kind of silly,
7153 * so don't use or document it, but that's the way the parsing
7154 * works).
7155 *
7156 * -pic Indicates PIC.
7157 * -k Indicates PIC. (Sun 3 only.)
7158 * --pcrel Never turn PC-relative branches into absolute jumps.
7159 *
7160 * --bitwise-or
7161 * Permit `|' to be used in expressions.
7162 *
7163 */
7164
7165 #ifdef OBJ_ELF
7166 const char *md_shortopts = "lSA:m:kQ:V";
7167 #else
7168 const char *md_shortopts = "lSA:m:k";
7169 #endif
7170
7171 struct option md_longopts[] = {
7172 #define OPTION_PIC (OPTION_MD_BASE)
7173 {"pic", no_argument, NULL, OPTION_PIC},
7174 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7175 {"register-prefix-optional", no_argument, NULL,
7176 OPTION_REGISTER_PREFIX_OPTIONAL},
7177 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7178 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7179 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7180 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7181 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7182 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7183 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7184 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7185 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7186 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7187 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7188 {"pcrel", no_argument, NULL, OPTION_PCREL},
7189 {NULL, no_argument, NULL, 0}
7190 };
7191 size_t md_longopts_size = sizeof (md_longopts);
7192
7193 int
7194 md_parse_option (c, arg)
7195 int c;
7196 char *arg;
7197 {
7198 switch (c)
7199 {
7200 case 'l': /* -l means keep external to 2 bit offset
7201 rather than 16 bit one. */
7202 flag_short_refs = 1;
7203 break;
7204
7205 case 'S': /* -S means that jbsr's always turn into
7206 jsr's. */
7207 flag_long_jumps = 1;
7208 break;
7209
7210 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7211 branches into absolute jumps. */
7212 flag_keep_pcrel = 1;
7213 break;
7214
7215 case 'A':
7216 if (*arg == 'm')
7217 arg++;
7218 /* Intentional fall-through. */
7219 case 'm':
7220
7221 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7222 {
7223 int i;
7224 unsigned long arch;
7225 const char *oarg = arg;
7226
7227 arg += 3;
7228 if (*arg == 'm')
7229 {
7230 arg++;
7231 if (arg[0] == 'c' && arg[1] == '6')
7232 arg++;
7233 }
7234 for (i = 0; i < n_archs; i++)
7235 if (!strcmp (arg, archs[i].name))
7236 break;
7237 if (i == n_archs)
7238 {
7239 unknown:
7240 as_bad (_("unrecognized option `%s'"), oarg);
7241 return 0;
7242 }
7243 arch = archs[i].arch;
7244 if (arch == m68881)
7245 no_68881 = 1;
7246 else if (arch == m68851)
7247 no_68851 = 1;
7248 else
7249 goto unknown;
7250 }
7251 else
7252 {
7253 int i;
7254
7255 if (arg[0] == 'c' && arg[1] == '6')
7256 arg++;
7257
7258 for (i = 0; i < n_archs; i++)
7259 if (!strcmp (arg, archs[i].name))
7260 {
7261 unsigned long arch = archs[i].arch;
7262 if (cpu_of_arch (arch))
7263 /* It's a cpu spec. */
7264 {
7265 current_architecture &= ~m68000up;
7266 current_architecture |= arch;
7267 current_chip = archs[i].chip;
7268 }
7269 else if (arch == m68881)
7270 {
7271 current_architecture |= m68881;
7272 no_68881 = 0;
7273 }
7274 else if (arch == m68851)
7275 {
7276 current_architecture |= m68851;
7277 no_68851 = 0;
7278 }
7279 else
7280 /* ??? */
7281 abort ();
7282 break;
7283 }
7284 if (i == n_archs)
7285 {
7286 as_bad (_("unrecognized architecture specification `%s'"), arg);
7287 return 0;
7288 }
7289 }
7290 break;
7291
7292 case OPTION_PIC:
7293 case 'k':
7294 flag_want_pic = 1;
7295 break; /* -pic, Position Independent Code. */
7296
7297 case OPTION_REGISTER_PREFIX_OPTIONAL:
7298 flag_reg_prefix_optional = 1;
7299 reg_prefix_optional_seen = 1;
7300 break;
7301
7302 /* -V: SVR4 argument to print version ID. */
7303 case 'V':
7304 print_version_id ();
7305 break;
7306
7307 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7308 should be emitted or not. FIXME: Not implemented. */
7309 case 'Q':
7310 break;
7311
7312 case OPTION_BITWISE_OR:
7313 {
7314 char *n, *t;
7315 const char *s;
7316
7317 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7318 t = n;
7319 for (s = m68k_comment_chars; *s != '\0'; s++)
7320 if (*s != '|')
7321 *t++ = *s;
7322 *t = '\0';
7323 m68k_comment_chars = n;
7324 }
7325 break;
7326
7327 case OPTION_BASE_SIZE_DEFAULT_16:
7328 m68k_index_width_default = SIZE_WORD;
7329 break;
7330
7331 case OPTION_BASE_SIZE_DEFAULT_32:
7332 m68k_index_width_default = SIZE_LONG;
7333 break;
7334
7335 case OPTION_DISP_SIZE_DEFAULT_16:
7336 m68k_rel32 = 0;
7337 m68k_rel32_from_cmdline = 1;
7338 break;
7339
7340 case OPTION_DISP_SIZE_DEFAULT_32:
7341 m68k_rel32 = 1;
7342 m68k_rel32_from_cmdline = 1;
7343 break;
7344
7345 default:
7346 return 0;
7347 }
7348
7349 return 1;
7350 }
7351
7352 void
7353 md_show_usage (stream)
7354 FILE *stream;
7355 {
7356 const char *default_cpu = TARGET_CPU;
7357 int i;
7358 unsigned int default_arch;
7359
7360 /* Get the canonical name for the default target CPU. */
7361 if (*default_cpu == 'm')
7362 default_cpu++;
7363 for (i = 0; i < n_archs; i++)
7364 {
7365 if (strcasecmp (default_cpu, archs[i].name) == 0)
7366 {
7367 default_arch = archs[i].arch;
7368 for (i = 0; i < n_archs; i++)
7369 {
7370 if (archs[i].arch == default_arch
7371 && !archs[i].alias)
7372 {
7373 default_cpu = archs[i].name;
7374 break;
7375 }
7376 }
7377 }
7378 }
7379
7380 fprintf (stream, _("\
7381 680X0 options:\n\
7382 -l use 1 word for refs to undefined symbols [default 2]\n\
7383 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
7384 -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
7385 -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m521x | -m5249 |\n\
7386 -m528x | -m5307 | -m5407 | -m547x | -m548x | -mcfv4 | -mcfv4e\n\
7387 specify variant of 680X0 architecture [default %s]\n\
7388 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
7389 target has/lacks floating-point coprocessor\n\
7390 [default yes for 68020, 68030, and cpu32]\n"),
7391 default_cpu);
7392 fprintf (stream, _("\
7393 -m68851 | -mno-68851\n\
7394 target has/lacks memory-management unit coprocessor\n\
7395 [default yes for 68020 and up]\n\
7396 -pic, -k generate position independent code\n\
7397 -S turn jbsr into jsr\n\
7398 --pcrel never turn PC-relative branches into absolute jumps\n\
7399 --register-prefix-optional\n\
7400 recognize register names without prefix character\n\
7401 --bitwise-or do not treat `|' as a comment character\n"));
7402 fprintf (stream, _("\
7403 --base-size-default-16 base reg without size is 16 bits\n\
7404 --base-size-default-32 base reg without size is 32 bits (default)\n\
7405 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7406 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7407 }
7408 \f
7409 #ifdef TEST2
7410
7411 /* TEST2: Test md_assemble() */
7412 /* Warning, this routine probably doesn't work anymore. */
7413 int
7414 main ()
7415 {
7416 struct m68k_it the_ins;
7417 char buf[120];
7418 char *cp;
7419 int n;
7420
7421 m68k_ip_begin ();
7422 for (;;)
7423 {
7424 if (!gets (buf) || !*buf)
7425 break;
7426 if (buf[0] == '|' || buf[1] == '.')
7427 continue;
7428 for (cp = buf; *cp; cp++)
7429 if (*cp == '\t')
7430 *cp = ' ';
7431 if (is_label (buf))
7432 continue;
7433 memset (&the_ins, '\0', sizeof (the_ins));
7434 m68k_ip (&the_ins, buf);
7435 if (the_ins.error)
7436 {
7437 printf (_("Error %s in %s\n"), the_ins.error, buf);
7438 }
7439 else
7440 {
7441 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7442 for (n = 0; n < the_ins.numo; n++)
7443 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7444 printf (" ");
7445 print_the_insn (&the_ins.opcode[0], stdout);
7446 (void) putchar ('\n');
7447 }
7448 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7449 {
7450 if (the_ins.operands[n].error)
7451 {
7452 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7453 continue;
7454 }
7455 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7456 if (the_ins.operands[n].b_const)
7457 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7458 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7459 if (the_ins.operands[n].b_iadd)
7460 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7461 (void) putchar ('\n');
7462 }
7463 }
7464 m68k_ip_end ();
7465 return 0;
7466 }
7467
7468 is_label (str)
7469 char *str;
7470 {
7471 while (*str == ' ')
7472 str++;
7473 while (*str && *str != ' ')
7474 str++;
7475 if (str[-1] == ':' || str[1] == '=')
7476 return 1;
7477 return 0;
7478 }
7479
7480 #endif
7481
7482 /* Possible states for relaxation:
7483
7484 0 0 branch offset byte (bra, etc)
7485 0 1 word
7486 0 2 long
7487
7488 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7489 1 1 word
7490 1 2 long
7491
7492 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7493 2 1 word-long
7494 2 2 long-word
7495 2 3 long-long
7496
7497 */
7498
7499 /* We have no need to default values of symbols. */
7500
7501 symbolS *
7502 md_undefined_symbol (name)
7503 char *name ATTRIBUTE_UNUSED;
7504 {
7505 return 0;
7506 }
7507
7508 /* Round up a section size to the appropriate boundary. */
7509 valueT
7510 md_section_align (segment, size)
7511 segT segment ATTRIBUTE_UNUSED;
7512 valueT size;
7513 {
7514 #ifdef OBJ_AOUT
7515 #ifdef BFD_ASSEMBLER
7516 /* For a.out, force the section size to be aligned. If we don't do
7517 this, BFD will align it for us, but it will not write out the
7518 final bytes of the section. This may be a bug in BFD, but it is
7519 easier to fix it here since that is how the other a.out targets
7520 work. */
7521 int align;
7522
7523 align = bfd_get_section_alignment (stdoutput, segment);
7524 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7525 #endif
7526 #endif
7527
7528 return size;
7529 }
7530
7531 /* Exactly what point is a PC-relative offset relative TO?
7532 On the 68k, it is relative to the address of the first extension
7533 word. The difference between the addresses of the offset and the
7534 first extension word is stored in fx_pcrel_adjust. */
7535 long
7536 md_pcrel_from (fixP)
7537 fixS *fixP;
7538 {
7539 int adjust;
7540
7541 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7542 sign extend the value here. */
7543 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7544 if (adjust == 64)
7545 adjust = -1;
7546 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7547 }
7548
7549 #ifndef BFD_ASSEMBLER
7550 #ifdef OBJ_COFF
7551
7552 void
7553 tc_coff_symbol_emit_hook (ignore)
7554 symbolS *ignore ATTRIBUTE_UNUSED;
7555 {
7556 }
7557
7558 int
7559 tc_coff_sizemachdep (frag)
7560 fragS *frag;
7561 {
7562 switch (frag->fr_subtype & 0x3)
7563 {
7564 case BYTE:
7565 return 1;
7566 case SHORT:
7567 return 2;
7568 case LONG:
7569 return 4;
7570 default:
7571 abort ();
7572 return 0;
7573 }
7574 }
7575
7576 #endif
7577 #endif
7578 #ifdef OBJ_ELF
7579 void
7580 m68k_elf_final_processing ()
7581 {
7582 /* Set file-specific flags if this is a cpu32 processor. */
7583 if (cpu_of_arch (current_architecture) & cpu32)
7584 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7585 else if ((cpu_of_arch (current_architecture) & m68000up)
7586 && !(cpu_of_arch (current_architecture) & m68020up))
7587 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
7588 }
7589 #endif
7590
7591 int
7592 tc_m68k_regname_to_dw2regnum (const char *regname)
7593 {
7594 unsigned int regnum;
7595 static const char *const regnames[] =
7596 {
7597 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7598 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7599 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7600 "pc"
7601 };
7602
7603 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7604 if (strcmp (regname, regnames[regnum]) == 0)
7605 return regnum;
7606
7607 return -1;
7608 }
7609
7610 void
7611 tc_m68k_frame_initial_instructions (void)
7612 {
7613 static int sp_regno = -1;
7614
7615 if (sp_regno < 0)
7616 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7617
7618 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7619 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7620 }
GDB Binutils - Deliverables
This page took 0.310018 seconds and 4 git commands to generate.