1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 #include "safe-ctype.h"
25 #include "dwarf2dbg.h"
26 #include "dw2gencfi.h"
28 #include "opcode/m68k.h"
29 #include "m68k-parse.h"
40 static void m68k_elf_cons (int);
43 /* This string holds the chars that always start a comment. If the
44 pre-processor is disabled, these aren't very useful. The macro
45 tc_comment_chars points to this. We use this, rather than the
46 usual comment_chars, so that the --bitwise-or option will work. */
47 #if defined (TE_SVR4) || defined (TE_DELTA)
48 const char *m68k_comment_chars
= "|#";
50 const char *m68k_comment_chars
= "|";
53 /* This array holds the chars that only start a comment at the beginning of
54 a line. If the line seems to have the form '# 123 filename'
55 .line and .file directives will appear in the pre-processed output */
56 /* Note that input_file.c hand checks for '#' at the beginning of the
57 first line of the input file. This is because the compiler outputs
58 #NO_APP at the beginning of its output. */
59 /* Also note that comments like this one will always work. */
60 const char line_comment_chars
[] = "#*";
62 const char line_separator_chars
[] = ";";
64 /* Chars that can be used to separate mant from exp in floating point nums. */
65 const char EXP_CHARS
[] = "eE";
67 /* Chars that mean this number is a floating point constant, as
68 in "0f12.456" or "0d1.2345e12". */
70 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
72 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
73 changed in read.c . Ideally it shouldn't have to know about it at all,
74 but nothing is ideal around here. */
76 /* Are we trying to generate PIC code? If so, absolute references
77 ought to be made into linkage table references or pc-relative
78 references. Not implemented. For ELF there are other means
79 to denote pic relocations. */
82 static int flag_short_refs
; /* -l option. */
83 static int flag_long_jumps
; /* -S option. */
84 static int flag_keep_pcrel
; /* --pcrel option. */
86 #ifdef REGISTER_PREFIX_OPTIONAL
87 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
89 int flag_reg_prefix_optional
;
92 /* Whether --register-prefix-optional was used on the command line. */
93 static int reg_prefix_optional_seen
;
95 /* The floating point coprocessor to use by default. */
96 static enum m68k_register m68k_float_copnum
= COP1
;
98 /* If this is non-zero, then references to number(%pc) will be taken
99 to refer to number, rather than to %pc + number. */
100 static int m68k_abspcadd
;
102 /* If this is non-zero, then the quick forms of the move, add, and sub
103 instructions are used when possible. */
104 static int m68k_quick
= 1;
106 /* If this is non-zero, then if the size is not specified for a base
107 or outer displacement, the assembler assumes that the size should
109 static int m68k_rel32
= 1;
111 /* This is non-zero if m68k_rel32 was set from the command line. */
112 static int m68k_rel32_from_cmdline
;
114 /* The default width to use for an index register when using a base
116 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
118 /* We want to warn if any text labels are misaligned. In order to get
119 the right line number, we need to record the line number for each
123 struct label_line
*next
;
130 /* The list of labels. */
132 static struct label_line
*labels
;
134 /* The current label. */
136 static struct label_line
*current_label
;
138 /* Pointer to list holding the opcodes sorted by name. */
139 static struct m68k_opcode
const ** m68k_sorted_opcodes
;
141 /* Its an arbitrary name: This means I don't approve of it.
143 static struct obstack robyn
;
147 const char *m_operands
;
148 unsigned long m_opcode
;
152 struct m68k_incant
*m_next
;
155 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
156 #define gettwo(x) (((x)->m_opcode)&0xffff)
158 static const enum m68k_register m68000_ctrl
[] = { 0 };
159 static const enum m68k_register m68010_ctrl
[] = {
163 static const enum m68k_register m68020_ctrl
[] = {
164 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
167 static const enum m68k_register m68040_ctrl
[] = {
168 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
169 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
172 static const enum m68k_register m68060_ctrl
[] = {
173 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
174 USP
, VBR
, URP
, SRP
, PCR
,
177 static const enum m68k_register mcf_ctrl
[] = {
178 CACR
, TC
, ACR0
, ACR1
, ACR2
, ACR3
, VBR
, ROMBAR
,
179 RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
,
182 static const enum m68k_register mcf51_ctrl
[] = {
186 static const enum m68k_register mcf5206_ctrl
[] = {
187 CACR
, ACR0
, ACR1
, VBR
, RAMBAR0
, RAMBAR_ALT
, MBAR
,
190 static const enum m68k_register mcf5208_ctrl
[] = {
191 CACR
, ACR0
, ACR1
, VBR
, RAMBAR
, RAMBAR1
,
194 static const enum m68k_register mcf5210a_ctrl
[] = {
195 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR
, RAMBAR1
, MBAR
,
198 static const enum m68k_register mcf5213_ctrl
[] = {
199 VBR
, RAMBAR
, RAMBAR1
, FLASHBAR
,
202 static const enum m68k_register mcf5216_ctrl
[] = {
203 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
206 static const enum m68k_register mcf5221x_ctrl
[] = {
207 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
210 static const enum m68k_register mcf52223_ctrl
[] = {
211 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
214 static const enum m68k_register mcf52235_ctrl
[] = {
215 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
218 static const enum m68k_register mcf5225_ctrl
[] = {
219 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, MBAR
, RAMBAR1
,
222 static const enum m68k_register mcf52259_ctrl
[] = {
223 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
226 static const enum m68k_register mcf52277_ctrl
[] = {
227 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
230 static const enum m68k_register mcf5235_ctrl
[] = {
231 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
234 static const enum m68k_register mcf5249_ctrl
[] = {
235 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
, MBAR2
,
238 static const enum m68k_register mcf5250_ctrl
[] = {
242 static const enum m68k_register mcf5253_ctrl
[] = {
243 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
, MBAR2
,
246 static const enum m68k_register mcf5271_ctrl
[] = {
247 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
250 static const enum m68k_register mcf5272_ctrl
[] = {
251 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR_ALT
, RAMBAR0
, MBAR
,
254 static const enum m68k_register mcf5275_ctrl
[] = {
255 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
258 static const enum m68k_register mcf5282_ctrl
[] = {
259 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
262 static const enum m68k_register mcf53017_ctrl
[] = {
263 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
266 static const enum m68k_register mcf5307_ctrl
[] = {
267 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR_ALT
, MBAR
,
270 static const enum m68k_register mcf5329_ctrl
[] = {
271 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
274 static const enum m68k_register mcf5373_ctrl
[] = {
275 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
278 static const enum m68k_register mcfv4e_ctrl
[] = {
279 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
280 VBR
, PC
, ROMBAR0
, ROMBAR1
, RAMBAR0
, RAMBAR1
,
282 MPCR
/* Multiprocessor Control register */,
283 EDRAMBAR
/* Embedded DRAM Base Address Register */,
284 /* Permutation control registers. */
285 PCR1U0
, PCR1L0
, PCR1U1
, PCR1L1
, PCR2U0
, PCR2L0
, PCR2U1
, PCR2L1
,
286 PCR3U0
, PCR3L0
, PCR3U1
, PCR3L1
,
288 TC
/* ASID */, BUSCR
/* MMUBAR */,
289 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
290 MBAR1
/* MBAR */, MBAR2
/* SECMBAR */, MBAR0
/* SECMBAR */,
291 ROMBAR
/* ROMBAR0 */, RAMBAR
/* RAMBAR1 */,
294 static const enum m68k_register mcf5407_ctrl
[] = {
295 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
,
296 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
299 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
300 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
303 static const enum m68k_register mcf54418_ctrl
[] = {
304 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, ACR4
, ACR5
, ACR6
, ACR7
, MMUBAR
, RGPIOBAR
,
307 TC
/* ASID */, BUSCR
/* MMUBAR */,
308 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
309 RAMBAR
/* RAMBAR1 */,
312 static const enum m68k_register mcf54455_ctrl
[] = {
313 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
316 TC
/* ASID */, BUSCR
/* MMUBAR */,
317 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
318 RAMBAR
/* RAMBAR1 */,
321 static const enum m68k_register mcf5475_ctrl
[] = {
322 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
323 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
325 TC
/* ASID */, BUSCR
/* MMUBAR */,
326 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
327 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
330 static const enum m68k_register mcf5485_ctrl
[] = {
331 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
332 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
334 TC
/* ASID */, BUSCR
/* MMUBAR */,
335 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
336 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
339 static const enum m68k_register fido_ctrl
[] = {
340 SFC
, DFC
, USP
, VBR
, CAC
, MBO
,
343 #define cpu32_ctrl m68010_ctrl
345 static const enum m68k_register
*control_regs
;
347 /* Internal form of a 68020 instruction. */
351 const char *args
; /* List of opcode info. */
354 int numo
; /* Number of shorts in opcode. */
357 struct m68k_op operands
[6];
359 int nexp
; /* Number of exprs in use. */
360 struct m68k_exp exprs
[4];
362 int nfrag
; /* Number of frags we have to produce. */
365 int fragoff
; /* Where in the current opcode the frag ends. */
372 int nrel
; /* Num of reloc strucs in use. */
379 /* In a pc relative address the difference between the address
380 of the offset and the address that the offset is relative
381 to. This depends on the addressing mode. Basically this
382 is the value to put in the offset field to address the
383 first byte of the offset, without regarding the special
384 significance of some values (in the branch instruction, for
388 /* Whether this expression needs special pic relocation, and if
390 enum pic_relocation pic_reloc
;
393 reloc
[5]; /* Five is enough??? */
396 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
397 #define float_of_arch(x) ((x) & mfloat)
398 #define mmu_of_arch(x) ((x) & mmmu)
399 #define arch_coldfire_p(x) ((x) & mcfisa_a)
400 #define arch_coldfire_fpu(x) ((x) & cfloat)
402 /* Macros for determining if cpu supports a specific addressing mode. */
403 #define HAVE_LONG_DISP(x) \
404 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
405 #define HAVE_LONG_CALL(x) \
406 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
407 #define HAVE_LONG_COND(x) \
408 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
409 #define HAVE_LONG_BRANCH(x) \
410 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
411 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
413 static struct m68k_it the_ins
; /* The instruction being assembled. */
415 #define op(ex) ((ex)->exp.X_op)
416 #define adds(ex) ((ex)->exp.X_add_symbol)
417 #define subs(ex) ((ex)->exp.X_op_symbol)
418 #define offs(ex) ((ex)->exp.X_add_number)
420 /* Macros for adding things to the m68k_it struct. */
421 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
423 /* Like addword, but goes BEFORE general operands. */
426 insop (int w
, const struct m68k_incant
*opcode
)
429 for (z
= the_ins
.numo
; z
> opcode
->m_codenum
; --z
)
430 the_ins
.opcode
[z
] = the_ins
.opcode
[z
- 1];
431 for (z
= 0; z
< the_ins
.nrel
; z
++)
432 the_ins
.reloc
[z
].n
+= 2;
433 for (z
= 0; z
< the_ins
.nfrag
; z
++)
434 the_ins
.fragb
[z
].fragoff
++;
435 the_ins
.opcode
[opcode
->m_codenum
] = w
;
439 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
442 add_fix (int width
, struct m68k_exp
*exp
, int pc_rel
, int pc_fix
)
444 the_ins
.reloc
[the_ins
.nrel
].n
= (width
== 'B' || width
== '3'
445 ? the_ins
.numo
* 2 - 1
447 ? the_ins
.numo
* 2 + 1
448 : the_ins
.numo
* 2));
449 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
450 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
451 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
453 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
455 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
458 /* Cause an extra frag to be generated here, inserting up to 10 bytes
459 (that value is chosen in the frag_var call in md_assemble). TYPE
460 is the subtype of the frag to be generated; its primary type is
461 rs_machine_dependent.
463 The TYPE parameter is also used by md_convert_frag_1 and
464 md_estimate_size_before_relax. The appropriate type of fixup will
465 be emitted by md_convert_frag_1.
467 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
469 add_frag (symbolS
*add
, offsetT off
, int type
)
471 the_ins
.fragb
[the_ins
.nfrag
].fragoff
= the_ins
.numo
;
472 the_ins
.fragb
[the_ins
.nfrag
].fadd
= add
;
473 the_ins
.fragb
[the_ins
.nfrag
].foff
= off
;
474 the_ins
.fragb
[the_ins
.nfrag
++].fragty
= type
;
478 (op (ex) != O_constant && op (ex) != O_big)
480 static char *crack_operand (char *str
, struct m68k_op
*opP
);
481 static int get_num (struct m68k_exp
*exp
, int ok
);
482 static int reverse_16_bits (int in
);
483 static int reverse_8_bits (int in
);
484 static void install_gen_operand (int mode
, int val
);
485 static void install_operand (int mode
, int val
);
486 static void s_bss (int);
487 static void s_data1 (int);
488 static void s_data2 (int);
489 static void s_even (int);
490 static void s_proc (int);
491 static void s_chip (int);
492 static void s_fopt (int);
493 static void s_opt (int);
494 static void s_reg (int);
495 static void s_restore (int);
496 static void s_save (int);
497 static void s_mri_if (int);
498 static void s_mri_else (int);
499 static void s_mri_endi (int);
500 static void s_mri_break (int);
501 static void s_mri_next (int);
502 static void s_mri_for (int);
503 static void s_mri_endf (int);
504 static void s_mri_repeat (int);
505 static void s_mri_until (int);
506 static void s_mri_while (int);
507 static void s_mri_endw (int);
508 static void s_m68k_cpu (int);
509 static void s_m68k_arch (int);
513 unsigned long arch
; /* Architecture features. */
514 const enum m68k_register
*control_regs
; /* Control regs on chip */
515 const char *name
; /* Name */
516 int alias
; /* Alias for a cannonical name. If 1, then
517 succeeds canonical name, if -1 then
518 succeeds canonical name, if <-1 ||>1 this is a
519 deprecated name, and the next/previous name
523 /* We hold flags for features explicitly enabled and explicitly
525 static int current_architecture
;
526 static int not_current_architecture
;
527 static const struct m68k_cpu
*selected_arch
;
528 static const struct m68k_cpu
*selected_cpu
;
529 static int initialized
;
531 /* Architecture models. */
532 static const struct m68k_cpu m68k_archs
[] =
534 {m68000
, m68000_ctrl
, "68000", 0},
535 {m68010
, m68010_ctrl
, "68010", 0},
536 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
537 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
538 {m68040
, m68040_ctrl
, "68040", 0},
539 {m68060
, m68060_ctrl
, "68060", 0},
540 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
541 {fido_a
, fido_ctrl
, "fidoa", 0},
542 {mcfisa_a
|mcfhwdiv
, NULL
, "isaa", 0},
543 {mcfisa_a
|mcfhwdiv
|mcfisa_aa
|mcfusp
, NULL
, "isaaplus", 0},
544 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfusp
, NULL
, "isab", 0},
545 {mcfisa_a
|mcfhwdiv
|mcfisa_c
|mcfusp
, NULL
, "isac", 0},
546 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfmac
|mcfusp
, mcf_ctrl
, "cfv4", 0},
547 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "cfv4e", 0},
551 /* For -mno-mac we want to turn off all types of mac. */
552 static const unsigned no_mac
= mcfmac
| mcfemac
;
554 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
556 static const struct m68k_cpu m68k_extensions
[] =
558 {m68851
, NULL
, "68851", -1},
559 {m68881
, NULL
, "68881", -1},
560 {m68881
, NULL
, "68882", -1},
562 {cfloat
|m68881
, NULL
, "float", 0},
564 {mcfhwdiv
, NULL
, "div", 1},
565 {mcfusp
, NULL
, "usp", 1},
566 {mcfmac
, (void *)&no_mac
, "mac", 1},
567 {mcfemac
, NULL
, "emac", 1},
573 static const struct m68k_cpu m68k_cpus
[] =
575 {m68000
, m68000_ctrl
, "68000", 0},
576 {m68000
, m68000_ctrl
, "68ec000", 1},
577 {m68000
, m68000_ctrl
, "68hc000", 1},
578 {m68000
, m68000_ctrl
, "68hc001", 1},
579 {m68000
, m68000_ctrl
, "68008", 1},
580 {m68000
, m68000_ctrl
, "68302", 1},
581 {m68000
, m68000_ctrl
, "68306", 1},
582 {m68000
, m68000_ctrl
, "68307", 1},
583 {m68000
, m68000_ctrl
, "68322", 1},
584 {m68000
, m68000_ctrl
, "68356", 1},
585 {m68010
, m68010_ctrl
, "68010", 0},
586 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
587 {m68020
|m68881
|m68851
, m68020_ctrl
, "68k", 1},
588 {m68020
|m68881
|m68851
, m68020_ctrl
, "68ec020", 1},
589 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
590 {m68030
|m68881
|m68851
, m68020_ctrl
, "68ec030", 1},
591 {m68040
, m68040_ctrl
, "68040", 0},
592 {m68040
, m68040_ctrl
, "68ec040", 1},
593 {m68060
, m68060_ctrl
, "68060", 0},
594 {m68060
, m68060_ctrl
, "68ec060", 1},
596 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
597 {cpu32
|m68881
, cpu32_ctrl
, "68330", 1},
598 {cpu32
|m68881
, cpu32_ctrl
, "68331", 1},
599 {cpu32
|m68881
, cpu32_ctrl
, "68332", 1},
600 {cpu32
|m68881
, cpu32_ctrl
, "68333", 1},
601 {cpu32
|m68881
, cpu32_ctrl
, "68334", 1},
602 {cpu32
|m68881
, cpu32_ctrl
, "68336", 1},
603 {cpu32
|m68881
, cpu32_ctrl
, "68340", 1},
604 {cpu32
|m68881
, cpu32_ctrl
, "68341", 1},
605 {cpu32
|m68881
, cpu32_ctrl
, "68349", 1},
606 {cpu32
|m68881
, cpu32_ctrl
, "68360", 1},
608 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51", 0},
609 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51ac", 1},
610 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51ag", 1},
611 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51cn", 1},
612 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfmac
, mcf51_ctrl
, "51em", 1},
613 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfmac
, mcf51_ctrl
, "51je", 1},
614 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfemac
, mcf51_ctrl
, "51jf", 1},
615 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfemac
, mcf51_ctrl
, "51jg", 1},
616 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51jm", 1},
617 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfmac
, mcf51_ctrl
, "51mm", 1},
618 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51qe", 1},
619 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfemac
, mcf51_ctrl
, "51qm", 1},
621 {mcfisa_a
, mcf_ctrl
, "5200", 0},
622 {mcfisa_a
, mcf_ctrl
, "5202", 1},
623 {mcfisa_a
, mcf_ctrl
, "5204", 1},
624 {mcfisa_a
, mcf5206_ctrl
, "5206", 1},
626 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5206_ctrl
, "5206e", 0},
628 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5207", -1},
629 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5208", 0},
631 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5210a", 0},
632 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5211a", 1},
634 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5211", -1},
635 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5212", -1},
636 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5213", 0},
638 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5214", -1},
639 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5216", 0},
640 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "521x", 2},
642 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5221x_ctrl
, "5221x", 0},
644 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf52223_ctrl
, "52221", -1},
645 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf52223_ctrl
, "52223", 0},
647 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52230", -1},
648 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52233", -1},
649 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52234", -1},
650 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52235", 0},
652 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5224", -1},
653 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5225", 0},
655 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52277_ctrl
, "52274", -1},
656 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52277_ctrl
, "52277", 0},
658 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5232", -1},
659 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5233", -1},
660 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5234", -1},
661 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5235", -1},
662 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "523x", 0},
664 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5249_ctrl
, "5249", 0},
665 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5250_ctrl
, "5250", 0},
666 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5253_ctrl
, "5253", 0},
668 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52252", -1},
669 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52254", -1},
670 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52255", -1},
671 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52256", -1},
672 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52258", -1},
673 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52259", 0},
675 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5270", -1},
676 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5271", 0},
678 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5272_ctrl
, "5272", 0},
680 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5274", -1},
681 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5275", 0},
683 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5280", -1},
684 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5281", -1},
685 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5282", -1},
686 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "528x", 0},
688 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53011", -1},
689 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53012", -1},
690 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53013", -1},
691 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53014", -1},
692 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53015", -1},
693 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53016", -1},
694 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53017", 0},
696 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5307_ctrl
, "5307", 0},
698 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5327", -1},
699 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5328", -1},
700 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5329", -1},
701 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "532x", 0},
703 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5372", -1},
704 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5373", -1},
705 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "537x", 0},
707 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfmac
, mcf5407_ctrl
, "5407",0},
709 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54410", -1},
710 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54415", -1},
711 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54416", -1},
712 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54417", -1},
713 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54418", 0},
715 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54450", -1},
716 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54451", -1},
717 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54452", -1},
718 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54453", -1},
719 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54454", -1},
720 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54455", 0},
722 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5470", -1},
723 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5471", -1},
724 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5472", -1},
725 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5473", -1},
726 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5474", -1},
727 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5475", -1},
728 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "547x", 0},
730 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5480", -1},
731 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5481", -1},
732 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5482", -1},
733 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5483", -1},
734 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5484", -1},
735 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5485", -1},
736 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "548x", 0},
738 {fido_a
, fido_ctrl
, "fidoa", 0},
739 {fido_a
, fido_ctrl
, "fido", 1},
744 static const struct m68k_cpu
*m68k_lookup_cpu
745 (const char *, const struct m68k_cpu
*, int, int *);
746 static int m68k_set_arch (const char *, int, int);
747 static int m68k_set_cpu (const char *, int, int);
748 static int m68k_set_extension (const char *, int, int);
749 static void m68k_init_arch (void);
751 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
752 architecture and we have a lot of relaxation modes. */
754 /* Macros used in the relaxation code. */
755 #define TAB(x,y) (((x) << 2) + (y))
756 #define TABTYPE(x) ((x) >> 2)
758 /* Relaxation states. */
764 /* Here are all the relaxation modes we support. First we can relax ordinary
765 branches. On 68020 and higher and on CPU32 all branch instructions take
766 three forms, so on these CPUs all branches always remain as such. When we
767 have to expand to the LONG form on a 68000, though, we substitute an
768 absolute jump instead. This is a direct replacement for unconditional
769 branches and a branch over a jump for conditional branches. However, if the
770 user requires PIC and disables this with --pcrel, we can only relax between
771 BYTE and SHORT forms, punting if that isn't enough. This gives us four
772 different relaxation modes for branches: */
774 #define BRANCHBWL 0 /* Branch byte, word, or long. */
775 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
776 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
777 #define BRANCHBW 3 /* Branch byte or word. */
779 /* We also relax coprocessor branches and DBcc's. All CPUs that support
780 coprocessor branches support them in word and long forms, so we have only
781 one relaxation mode for them. DBcc's are word only on all CPUs. We can
782 relax them to the LONG form with a branch-around sequence. This sequence
783 can use a long branch (if available) or an absolute jump (if acceptable).
784 This gives us two relaxation modes. If long branches are not available and
785 absolute jumps are not acceptable, we don't relax DBcc's. */
787 #define FBRANCH 4 /* Coprocessor branch. */
788 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
789 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
791 /* That's all for instruction relaxation. However, we also relax PC-relative
792 operands. Specifically, we have three operand relaxation modes. On the
793 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
794 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
795 two. Also PC+displacement+index operands in their simple form (with a non-
796 suppressed index without memory indirection) are supported on all CPUs, but
797 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
798 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
799 form of the PC+displacement+index operand. Finally, some absolute operands
800 can be relaxed down to 16-bit PC-relative. */
802 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
803 #define PCINDEX 8 /* PC + displacement + index. */
804 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
806 /* This relaxation is required for branches where there is no long
807 branch and we are in pcrel mode. We generate a bne/beq pair. */
808 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs
811 /* Note that calls to frag_var need to specify the maximum expansion
812 needed; this is currently 12 bytes for bne/beq pair. */
813 #define FRAG_VAR_SIZE 12
816 How far Forward this mode will reach:
817 How far Backward this mode will reach:
818 How many bytes this mode will add to the size of the frag
819 Which mode to go to if the offset won't fit in this one
821 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
822 relax_typeS md_relax_table
[] =
824 { 127, -128, 0, TAB (BRANCHBWL
, SHORT
) },
825 { 32767, -32768, 2, TAB (BRANCHBWL
, LONG
) },
829 { 127, -128, 0, TAB (BRABSJUNC
, SHORT
) },
830 { 32767, -32768, 2, TAB (BRABSJUNC
, LONG
) },
834 { 127, -128, 0, TAB (BRABSJCOND
, SHORT
) },
835 { 32767, -32768, 2, TAB (BRABSJCOND
, LONG
) },
839 { 127, -128, 0, TAB (BRANCHBW
, SHORT
) },
844 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
845 { 32767, -32768, 2, TAB (FBRANCH
, LONG
) },
849 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
850 { 32767, -32768, 2, TAB (DBCCLBR
, LONG
) },
854 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
855 { 32767, -32768, 2, TAB (DBCCABSJ
, LONG
) },
859 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
860 { 32767, -32768, 2, TAB (PCREL1632
, LONG
) },
864 { 125, -130, 0, TAB (PCINDEX
, SHORT
) },
865 { 32765, -32770, 2, TAB (PCINDEX
, LONG
) },
869 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
870 { 32767, -32768, 2, TAB (ABSTOPCREL
, LONG
) },
874 { 127, -128, 0, TAB (BRANCHBWPL
, SHORT
) },
875 { 32767, -32768, 2, TAB (BRANCHBWPL
, LONG
) },
880 /* These are the machine dependent pseudo-ops. These are included so
881 the assembler can work on the output from the SUN C compiler, which
884 /* This table describes all the machine specific pseudo-ops the assembler
885 has to support. The fields are:
886 pseudo-op name without dot
887 function to call to execute this pseudo-op
888 Integer arg to pass to the function. */
889 const pseudo_typeS md_pseudo_table
[] =
891 {"data1", s_data1
, 0},
892 {"data2", s_data2
, 0},
895 {"skip", s_space
, 0},
897 #if defined (TE_SUN3) || defined (OBJ_ELF)
898 {"align", s_align_bytes
, 0},
901 {"swbeg", s_ignore
, 0},
902 {"long", m68k_elf_cons
, 4},
904 {"extend", float_cons
, 'x'},
905 {"ldouble", float_cons
, 'x'},
907 {"arch", s_m68k_arch
, 0},
908 {"cpu", s_m68k_cpu
, 0},
910 /* The following pseudo-ops are supported for MRI compatibility. */
912 {"comline", s_space
, 1},
914 {"mask2", s_ignore
, 0},
917 {"restore", s_restore
, 0},
921 {"if.b", s_mri_if
, 'b'},
922 {"if.w", s_mri_if
, 'w'},
923 {"if.l", s_mri_if
, 'l'},
924 {"else", s_mri_else
, 0},
925 {"else.s", s_mri_else
, 's'},
926 {"else.l", s_mri_else
, 'l'},
927 {"endi", s_mri_endi
, 0},
928 {"break", s_mri_break
, 0},
929 {"break.s", s_mri_break
, 's'},
930 {"break.l", s_mri_break
, 'l'},
931 {"next", s_mri_next
, 0},
932 {"next.s", s_mri_next
, 's'},
933 {"next.l", s_mri_next
, 'l'},
934 {"for", s_mri_for
, 0},
935 {"for.b", s_mri_for
, 'b'},
936 {"for.w", s_mri_for
, 'w'},
937 {"for.l", s_mri_for
, 'l'},
938 {"endf", s_mri_endf
, 0},
939 {"repeat", s_mri_repeat
, 0},
940 {"until", s_mri_until
, 0},
941 {"until.b", s_mri_until
, 'b'},
942 {"until.w", s_mri_until
, 'w'},
943 {"until.l", s_mri_until
, 'l'},
944 {"while", s_mri_while
, 0},
945 {"while.b", s_mri_while
, 'b'},
946 {"while.w", s_mri_while
, 'w'},
947 {"while.l", s_mri_while
, 'l'},
948 {"endw", s_mri_endw
, 0},
953 /* The mote pseudo ops are put into the opcode table, since they
954 don't start with a . they look like opcodes to gas. */
956 const pseudo_typeS mote_pseudo_table
[] =
969 {"xdef", s_globl
, 0},
971 {"align", s_align_bytes
, 0},
973 {"align", s_align_ptwo
, 0},
976 {"sect", obj_coff_section
, 0},
977 {"section", obj_coff_section
, 0},
982 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
983 gives identical results to a 32-bit host. */
984 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
985 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
987 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
988 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
989 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
990 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
992 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
993 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
994 #define islong(x) (1)
996 static char notend_table
[256];
997 static char alt_notend_table
[256];
999 (! (notend_table[(unsigned char) *s] \
1001 && alt_notend_table[(unsigned char) s[1]])))
1005 /* Return zero if the reference to SYMBOL from within the same segment may
1008 /* On an ELF system, we can't relax an externally visible symbol,
1009 because it may be overridden by a shared library. However, if
1010 TARGET_OS is "elf", then we presume that we are assembling for an
1011 embedded system, in which case we don't have to worry about shared
1012 libraries, and we can relax any external sym. */
1014 #define relaxable_symbol(symbol) \
1015 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
1016 || S_IS_WEAK (symbol)))
1018 /* Compute the relocation code for a fixup of SIZE bytes, using pc
1019 relative relocation if PCREL is non-zero. PIC says whether a special
1020 pic relocation was requested. */
1022 static bfd_reloc_code_real_type
1023 get_reloc_code (int size
, int pcrel
, enum pic_relocation pic
)
1031 return BFD_RELOC_8_GOT_PCREL
;
1033 return BFD_RELOC_16_GOT_PCREL
;
1035 return BFD_RELOC_32_GOT_PCREL
;
1043 return BFD_RELOC_8_GOTOFF
;
1045 return BFD_RELOC_16_GOTOFF
;
1047 return BFD_RELOC_32_GOTOFF
;
1055 return BFD_RELOC_8_PLT_PCREL
;
1057 return BFD_RELOC_16_PLT_PCREL
;
1059 return BFD_RELOC_32_PLT_PCREL
;
1067 return BFD_RELOC_8_PLTOFF
;
1069 return BFD_RELOC_16_PLTOFF
;
1071 return BFD_RELOC_32_PLTOFF
;
1079 return BFD_RELOC_68K_TLS_GD8
;
1081 return BFD_RELOC_68K_TLS_GD16
;
1083 return BFD_RELOC_68K_TLS_GD32
;
1091 return BFD_RELOC_68K_TLS_LDM8
;
1093 return BFD_RELOC_68K_TLS_LDM16
;
1095 return BFD_RELOC_68K_TLS_LDM32
;
1103 return BFD_RELOC_68K_TLS_LDO8
;
1105 return BFD_RELOC_68K_TLS_LDO16
;
1107 return BFD_RELOC_68K_TLS_LDO32
;
1115 return BFD_RELOC_68K_TLS_IE8
;
1117 return BFD_RELOC_68K_TLS_IE16
;
1119 return BFD_RELOC_68K_TLS_IE32
;
1127 return BFD_RELOC_68K_TLS_LE8
;
1129 return BFD_RELOC_68K_TLS_LE16
;
1131 return BFD_RELOC_68K_TLS_LE32
;
1141 return BFD_RELOC_8_PCREL
;
1143 return BFD_RELOC_16_PCREL
;
1145 return BFD_RELOC_32_PCREL
;
1155 return BFD_RELOC_16
;
1157 return BFD_RELOC_32
;
1164 if (pic
== pic_none
)
1165 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
1167 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
1171 if (pic
== pic_none
)
1172 as_bad (_("Can not do %d byte relocation"), size
);
1174 as_bad (_("Can not do %d byte pic relocation"), size
);
1177 return BFD_RELOC_NONE
;
1180 /* Here we decide which fixups can be adjusted to make them relative
1181 to the beginning of the section instead of the symbol. Basically
1182 we need to make sure that the dynamic relocations are done
1183 correctly, so in some cases we force the original symbol to be
1186 tc_m68k_fix_adjustable (fixS
*fixP
)
1188 /* Adjust_reloc_syms doesn't know about the GOT. */
1189 switch (fixP
->fx_r_type
)
1191 case BFD_RELOC_8_GOT_PCREL
:
1192 case BFD_RELOC_16_GOT_PCREL
:
1193 case BFD_RELOC_32_GOT_PCREL
:
1194 case BFD_RELOC_8_GOTOFF
:
1195 case BFD_RELOC_16_GOTOFF
:
1196 case BFD_RELOC_32_GOTOFF
:
1197 case BFD_RELOC_8_PLT_PCREL
:
1198 case BFD_RELOC_16_PLT_PCREL
:
1199 case BFD_RELOC_32_PLT_PCREL
:
1200 case BFD_RELOC_8_PLTOFF
:
1201 case BFD_RELOC_16_PLTOFF
:
1202 case BFD_RELOC_32_PLTOFF
:
1203 case BFD_RELOC_68K_TLS_GD32
:
1204 case BFD_RELOC_68K_TLS_GD16
:
1205 case BFD_RELOC_68K_TLS_GD8
:
1206 case BFD_RELOC_68K_TLS_LDM32
:
1207 case BFD_RELOC_68K_TLS_LDM16
:
1208 case BFD_RELOC_68K_TLS_LDM8
:
1209 case BFD_RELOC_68K_TLS_LDO32
:
1210 case BFD_RELOC_68K_TLS_LDO16
:
1211 case BFD_RELOC_68K_TLS_LDO8
:
1212 case BFD_RELOC_68K_TLS_IE32
:
1213 case BFD_RELOC_68K_TLS_IE16
:
1214 case BFD_RELOC_68K_TLS_IE8
:
1215 case BFD_RELOC_68K_TLS_LE32
:
1216 case BFD_RELOC_68K_TLS_LE16
:
1217 case BFD_RELOC_68K_TLS_LE8
:
1220 case BFD_RELOC_VTABLE_INHERIT
:
1221 case BFD_RELOC_VTABLE_ENTRY
:
1229 #else /* !OBJ_ELF */
1231 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1233 /* PR gas/3041 Weak symbols are not relaxable
1234 because they must be treated as extern. */
1235 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1237 #endif /* OBJ_ELF */
1240 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
1243 bfd_reloc_code_real_type code
;
1245 /* If the tcbit is set, then this was a fixup of a negative value
1246 that was never resolved. We do not have a reloc to handle this,
1247 so just return. We assume that other code will have detected this
1248 situation and produced a helpful error message, so we just tell the
1249 user that the reloc cannot be produced. */
1253 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1254 _("Unable to produce reloc against symbol '%s'"),
1255 S_GET_NAME (fixp
->fx_addsy
));
1259 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
1261 code
= fixp
->fx_r_type
;
1263 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1264 that fixup_segment converted a non-PC relative reloc into a
1265 PC relative reloc. In such a case, we need to convert the
1272 code
= BFD_RELOC_8_PCREL
;
1275 code
= BFD_RELOC_16_PCREL
;
1278 code
= BFD_RELOC_32_PCREL
;
1280 case BFD_RELOC_8_PCREL
:
1281 case BFD_RELOC_16_PCREL
:
1282 case BFD_RELOC_32_PCREL
:
1283 case BFD_RELOC_8_GOT_PCREL
:
1284 case BFD_RELOC_16_GOT_PCREL
:
1285 case BFD_RELOC_32_GOT_PCREL
:
1286 case BFD_RELOC_8_GOTOFF
:
1287 case BFD_RELOC_16_GOTOFF
:
1288 case BFD_RELOC_32_GOTOFF
:
1289 case BFD_RELOC_8_PLT_PCREL
:
1290 case BFD_RELOC_16_PLT_PCREL
:
1291 case BFD_RELOC_32_PLT_PCREL
:
1292 case BFD_RELOC_8_PLTOFF
:
1293 case BFD_RELOC_16_PLTOFF
:
1294 case BFD_RELOC_32_PLTOFF
:
1295 case BFD_RELOC_68K_TLS_GD32
:
1296 case BFD_RELOC_68K_TLS_GD16
:
1297 case BFD_RELOC_68K_TLS_GD8
:
1298 case BFD_RELOC_68K_TLS_LDM32
:
1299 case BFD_RELOC_68K_TLS_LDM16
:
1300 case BFD_RELOC_68K_TLS_LDM8
:
1301 case BFD_RELOC_68K_TLS_LDO32
:
1302 case BFD_RELOC_68K_TLS_LDO16
:
1303 case BFD_RELOC_68K_TLS_LDO8
:
1304 case BFD_RELOC_68K_TLS_IE32
:
1305 case BFD_RELOC_68K_TLS_IE16
:
1306 case BFD_RELOC_68K_TLS_IE8
:
1307 case BFD_RELOC_68K_TLS_LE32
:
1308 case BFD_RELOC_68K_TLS_LE16
:
1309 case BFD_RELOC_68K_TLS_LE8
:
1312 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1313 _("Cannot make %s relocation PC relative"),
1314 bfd_get_reloc_code_name (code
));
1320 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1321 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
1323 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1324 MAP (1, 0, BFD_RELOC_8
);
1325 MAP (2, 0, BFD_RELOC_16
);
1326 MAP (4, 0, BFD_RELOC_32
);
1327 MAP (1, 1, BFD_RELOC_8_PCREL
);
1328 MAP (2, 1, BFD_RELOC_16_PCREL
);
1329 MAP (4, 1, BFD_RELOC_32_PCREL
);
1337 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1338 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1339 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1340 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1342 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
1344 && S_IS_WEAK (fixp
->fx_addsy
)
1345 && ! bfd_is_und_section (S_GET_SEGMENT (fixp
->fx_addsy
)))
1347 /* PR gas/3041 References to weak symbols must be treated as extern
1348 in order to be overridable by the linker, even if they are defined
1349 in the same object file. So the original addend must be written
1350 "as is" into the output section without further processing.
1351 The addend value must be hacked here in order to force
1352 bfd_install_relocation() to write the original value into the
1354 1) MD_APPLY_SYM_VALUE() is set to 1 for m68k/a.out, so the symbol
1355 value has already been added to the addend in fixup_segment(). We
1357 2) bfd_install_relocation() will incorrectly treat this symbol as
1358 resolved, so it will write the symbol value plus its addend and
1359 section VMA. As a workaround we can tweak the addend value here in
1360 order to get the original value in the section after the call to
1361 bfd_install_relocation(). */
1362 reloc
->addend
= fixp
->fx_addnumber
1363 /* Fix because of MD_APPLY_SYM_VALUE() */
1364 - S_GET_VALUE (fixp
->fx_addsy
)
1365 /* Fix for bfd_install_relocation() */
1366 - (S_GET_VALUE (fixp
->fx_addsy
)
1367 + S_GET_SEGMENT (fixp
->fx_addsy
)->vma
);
1369 else if (fixp
->fx_pcrel
)
1370 reloc
->addend
= fixp
->fx_addnumber
;
1374 if (!fixp
->fx_pcrel
)
1375 reloc
->addend
= fixp
->fx_addnumber
;
1377 reloc
->addend
= (section
->vma
1378 + fixp
->fx_pcrel_adjust
1379 + fixp
->fx_addnumber
1380 + md_pcrel_from (fixp
));
1383 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1384 gas_assert (reloc
->howto
!= 0);
1389 /* Handle of the OPCODE hash table. NULL means any use before
1390 m68k_ip_begin() will crash. */
1391 static struct hash_control
*op_hash
;
1393 /* Assemble an m68k instruction. */
1396 m68k_ip (char *instring
)
1399 register struct m68k_op
*opP
;
1400 register const struct m68k_incant
*opcode
;
1401 register const char *s
;
1402 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1403 char *pdot
, *pdotmove
;
1404 enum m68k_size siz1
, siz2
;
1408 struct m68k_op operands_backup
[6];
1409 LITTLENUM_TYPE words
[6];
1410 LITTLENUM_TYPE
*wordp
;
1411 unsigned long ok_arch
= 0;
1413 if (*instring
== ' ')
1414 instring
++; /* Skip leading whitespace. */
1416 /* Scan up to end of operation-code, which MUST end in end-of-string
1417 or exactly 1 space. */
1419 for (p
= instring
; *p
!= '\0'; p
++)
1429 the_ins
.error
= _("No operator");
1433 /* p now points to the end of the opcode name, probably whitespace.
1434 Make sure the name is null terminated by clobbering the
1435 whitespace, look it up in the hash table, then fix it back.
1436 Remove a dot, first, since the opcode tables have none. */
1439 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1440 *pdotmove
= pdotmove
[1];
1446 opcode
= (const struct m68k_incant
*) hash_find (op_hash
, instring
);
1451 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1452 *pdotmove
= pdotmove
[-1];
1459 the_ins
.error
= _("Unknown operator");
1463 /* Found a legitimate opcode, start matching operands. */
1467 if (opcode
->m_operands
== 0)
1469 char *old
= input_line_pointer
;
1471 input_line_pointer
= p
;
1472 /* Ahh - it's a motorola style psuedo op. */
1473 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1474 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1475 input_line_pointer
= old
;
1481 if (flag_mri
&& opcode
->m_opnum
== 0)
1483 /* In MRI mode, random garbage is allowed after an instruction
1484 which accepts no operands. */
1485 the_ins
.args
= opcode
->m_operands
;
1486 the_ins
.numargs
= opcode
->m_opnum
;
1487 the_ins
.numo
= opcode
->m_codenum
;
1488 the_ins
.opcode
[0] = getone (opcode
);
1489 the_ins
.opcode
[1] = gettwo (opcode
);
1493 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1495 p
= crack_operand (p
, opP
);
1499 the_ins
.error
= opP
->error
;
1504 opsfound
= opP
- &the_ins
.operands
[0];
1506 /* This ugly hack is to support the floating pt opcodes in their
1507 standard form. Essentially, we fake a first enty of type COP#1 */
1508 if (opcode
->m_operands
[0] == 'I')
1512 for (n
= opsfound
; n
> 0; --n
)
1513 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1515 memset (&the_ins
.operands
[0], '\0', sizeof (the_ins
.operands
[0]));
1516 the_ins
.operands
[0].mode
= CONTROL
;
1517 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1521 /* We've got the operands. Find an opcode that'll accept them. */
1524 /* If we didn't get the right number of ops, or we have no
1525 common model with this pattern then reject this pattern. */
1527 ok_arch
|= opcode
->m_arch
;
1528 if (opsfound
!= opcode
->m_opnum
1529 || ((opcode
->m_arch
& current_architecture
) == 0))
1535 /* Make a copy of the operands of this insn so that
1536 we can modify them safely, should we want to. */
1537 gas_assert (opsfound
<= (int) ARRAY_SIZE (operands_backup
));
1538 for (i
= 0; i
< opsfound
; i
++)
1539 operands_backup
[i
] = the_ins
.operands
[i
];
1541 for (s
= opcode
->m_operands
, opP
= &operands_backup
[0];
1545 /* Warning: this switch is huge! */
1546 /* I've tried to organize the cases into this order:
1547 non-alpha first, then alpha by letter. Lower-case
1548 goes directly before uppercase counterpart. */
1549 /* Code with multiple case ...: gets sorted by the lowest
1550 case ... it belongs to. I hope this makes sense. */
1656 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1673 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1692 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1702 if (opP
->mode
!= IMMED
)
1704 else if (s
[1] == 'b'
1705 && ! isvar (&opP
->disp
)
1706 && (opP
->disp
.exp
.X_op
!= O_constant
1707 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1709 else if (s
[1] == 'B'
1710 && ! isvar (&opP
->disp
)
1711 && (opP
->disp
.exp
.X_op
!= O_constant
1712 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1714 else if (s
[1] == 'w'
1715 && ! isvar (&opP
->disp
)
1716 && (opP
->disp
.exp
.X_op
!= O_constant
1717 || ! isword (opP
->disp
.exp
.X_add_number
)))
1719 else if (s
[1] == 'W'
1720 && ! isvar (&opP
->disp
)
1721 && (opP
->disp
.exp
.X_op
!= O_constant
1722 || ! issword (opP
->disp
.exp
.X_add_number
)))
1728 if (opP
->mode
!= IMMED
)
1733 if (opP
->mode
== AREG
1734 || opP
->mode
== CONTROL
1735 || opP
->mode
== FPREG
1736 || opP
->mode
== IMMED
1737 || opP
->mode
== REGLST
1738 || (opP
->mode
!= ABSL
1740 || opP
->reg
== ZPC
)))
1745 if (opP
->mode
== CONTROL
1746 || opP
->mode
== FPREG
1747 || opP
->mode
== REGLST
1748 || opP
->mode
== IMMED
1749 || (opP
->mode
!= ABSL
1751 || opP
->reg
== ZPC
)))
1779 if (opP
->mode
== CONTROL
1780 || opP
->mode
== FPREG
1781 || opP
->mode
== REGLST
)
1786 if (opP
->mode
!= AINC
)
1791 if (opP
->mode
!= ADEC
)
1841 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1862 case '~': /* For now! (JF FOO is this right?) */
1884 if (opP
->mode
!= CONTROL
1885 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1890 if (opP
->mode
!= AREG
)
1895 if (opP
->mode
!= AINDR
)
1900 if (opP
->mode
!= AINDR
&& opP
->mode
!= AINC
&& opP
->mode
!= ADEC
1901 && (opP
->mode
!= DISP
1903 || opP
->reg
> ADDR7
))
1908 if (opP
->mode
!= ABSL
1910 && strncmp (instring
, "jbsr", 4) == 0))
1933 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1938 if (opP
->mode
!= DISP
1940 || opP
->reg
> ADDR7
)
1945 if (opP
->mode
!= DREG
)
1950 if (opP
->reg
!= ACC
)
1955 if (opP
->reg
!= ACC
&& opP
->reg
!= ACC1
1956 && opP
->reg
!= ACC2
&& opP
->reg
!= ACC3
)
1961 if (opP
->mode
!= FPREG
)
1966 if (opP
->reg
!= MACSR
)
1971 if (opP
->reg
!= ACCEXT01
&& opP
->reg
!= ACCEXT23
)
1976 if (opP
->reg
!= MASK
)
1981 if (opP
->mode
!= CONTROL
1988 if (opP
->mode
!= LSH
&& opP
->mode
!= RSH
)
1993 if (opP
->mode
!= CONTROL
1995 || opP
->reg
> last_movec_reg
2000 const enum m68k_register
*rp
;
2002 for (rp
= control_regs
; *rp
; rp
++)
2004 if (*rp
== opP
->reg
)
2006 /* In most CPUs RAMBAR refers to control reg
2007 c05 (RAMBAR1), but a few CPUs have it
2008 refer to c04 (RAMBAR0). */
2009 else if (*rp
== RAMBAR_ALT
&& opP
->reg
== RAMBAR
)
2011 opP
->reg
= RAMBAR_ALT
;
2021 if (opP
->mode
!= IMMED
)
2027 if (opP
->mode
== DREG
2028 || opP
->mode
== AREG
2029 || opP
->mode
== FPREG
)
2038 opP
->mask
= 1 << (opP
->reg
- DATA0
);
2041 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
2044 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
2052 else if (opP
->mode
== CONTROL
)
2061 opP
->mask
= 1 << 24;
2064 opP
->mask
= 1 << 25;
2067 opP
->mask
= 1 << 26;
2076 else if (opP
->mode
!= REGLST
)
2078 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
2080 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
2085 if (opP
->mode
!= IMMED
)
2087 else if (opP
->disp
.exp
.X_op
!= O_constant
2088 || ! issbyte (opP
->disp
.exp
.X_add_number
))
2090 else if (! m68k_quick
2091 && instring
[3] != 'q'
2092 && instring
[4] != 'q')
2097 if (opP
->mode
!= DREG
2098 && opP
->mode
!= IMMED
2099 && opP
->mode
!= ABSL
)
2104 if (opP
->mode
!= IMMED
)
2106 else if (opP
->disp
.exp
.X_op
!= O_constant
2107 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
2109 else if (! m68k_quick
2110 && (strncmp (instring
, "add", 3) == 0
2111 || strncmp (instring
, "sub", 3) == 0)
2112 && instring
[3] != 'q')
2117 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
2122 if (opP
->mode
!= AINDR
2123 && (opP
->mode
!= BASE
2125 && opP
->reg
!= ZADDR0
)
2126 || opP
->disp
.exp
.X_op
!= O_absent
2127 || ((opP
->index
.reg
< DATA0
2128 || opP
->index
.reg
> DATA7
)
2129 && (opP
->index
.reg
< ADDR0
2130 || opP
->index
.reg
> ADDR7
))
2131 || opP
->index
.size
!= SIZE_UNSPEC
2132 || opP
->index
.scale
!= 1))
2137 if (opP
->mode
!= CONTROL
2138 || ! (opP
->reg
== FPI
2140 || opP
->reg
== FPC
))
2145 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
2150 if (opP
->mode
!= IMMED
)
2152 else if (opP
->disp
.exp
.X_op
!= O_constant
2153 || TRUNC (opP
->disp
.exp
.X_add_number
) > 7)
2158 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
2163 if (opP
->mode
!= IMMED
)
2165 else if (opP
->disp
.exp
.X_op
!= O_constant
2166 || (TRUNC (opP
->disp
.exp
.X_add_number
) != 0xffffffff
2167 && TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 6))
2172 if (opP
->mode
!= IMMED
)
2174 else if (opP
->disp
.exp
.X_op
!= O_constant
2175 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
2180 if (opP
->mode
!= IMMED
)
2182 else if (opP
->disp
.exp
.X_op
!= O_constant
2183 || TRUNC (opP
->disp
.exp
.X_add_number
) > 511)
2187 /* JF these are out of order. We could put them
2188 in order if we were willing to put up with
2189 bunches of #ifdef m68851s in the code.
2191 Don't forget that you need these operands
2192 to use 68030 MMU instructions. */
2194 /* Memory addressing mode used by pflushr. */
2196 if (opP
->mode
== CONTROL
2197 || opP
->mode
== FPREG
2198 || opP
->mode
== DREG
2199 || opP
->mode
== AREG
2200 || opP
->mode
== REGLST
)
2202 /* We should accept immediate operands, but they
2203 supposedly have to be quad word, and we don't
2204 handle that. I would like to see what a Motorola
2205 assembler does before doing something here. */
2206 if (opP
->mode
== IMMED
)
2211 if (opP
->mode
!= CONTROL
2212 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
2217 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
2222 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
2227 if (opP
->mode
!= CONTROL
2230 && opP
->reg
!= SCC
))
2235 if (opP
->mode
!= CONTROL
2241 if (opP
->mode
!= CONTROL
2244 && opP
->reg
!= CRP
))
2268 if (opP
->mode
!= CONTROL
2269 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
2270 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
2275 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
2280 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
2285 if (opP
->mode
!= CONTROL
2294 if (opP
->mode
!= ABSL
)
2299 if (opP
->reg
< DATA0L
|| opP
->reg
> ADDR7U
)
2301 /* FIXME: kludge instead of fixing parser:
2302 upper/lower registers are *not* CONTROL
2303 registers, but ordinary ones. */
2304 if ((opP
->reg
>= DATA0L
&& opP
->reg
<= DATA7L
)
2305 || (opP
->reg
>= DATA0U
&& opP
->reg
<= DATA7U
))
2312 if (!(opP
->mode
== AINDR
2313 || (opP
->mode
== DISP
2314 && !(opP
->reg
== PC
|| opP
->reg
== ZPC
))))
2319 if (!(opP
->mode
== AINDR
|| opP
->mode
== DISP
))
2331 /* Since we have found the correct instruction, copy
2332 in the modifications that we may have made. */
2334 for (i
= 0; i
< opsfound
; i
++)
2335 the_ins
.operands
[i
] = operands_backup
[i
];
2341 opcode
= opcode
->m_next
;
2346 && !(ok_arch
& current_architecture
))
2348 const struct m68k_cpu
*cpu
;
2351 char *buf
= xmalloc (space
+ 1);
2355 the_ins
.error
= buf
;
2356 /* Make sure there's a NUL at the end of the buffer -- strncpy
2357 won't write one when it runs out of buffer. */
2359 #define APPEND(STRING) \
2360 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2362 APPEND (_("invalid instruction for this architecture; needs "));
2366 APPEND ("ColdFire ISA_A");
2369 APPEND ("ColdFire ");
2370 APPEND (_("hardware divide"));
2373 APPEND ("ColdFire ISA_A+");
2376 APPEND ("ColdFire ISA_B");
2379 APPEND ("ColdFire ISA_C");
2382 APPEND ("ColdFire fpu");
2385 APPEND ("M68K fpu");
2388 APPEND ("M68K mmu");
2392 APPEND (_("or higher"));
2396 APPEND (_("or higher"));
2400 APPEND (_("or higher"));
2408 for (cpu
= m68k_cpus
; cpu
->name
; cpu
++)
2409 if (!cpu
->alias
&& (cpu
->arch
& ok_arch
))
2411 const struct m68k_cpu
*alias
;
2412 int seen_master
= 0;
2418 for (alias
= cpu
; alias
!= m68k_cpus
; alias
--)
2419 if (alias
[-1].alias
>= 0)
2421 for (; !seen_master
|| alias
->alias
> 0; alias
++)
2431 APPEND (alias
->name
);
2444 /* We ran out of space, so replace the end of the list
2449 strcpy (buf
, " ...");
2453 the_ins
.error
= _("operands mismatch");
2460 /* Now assemble it. */
2461 the_ins
.args
= opcode
->m_operands
;
2462 the_ins
.numargs
= opcode
->m_opnum
;
2463 the_ins
.numo
= opcode
->m_codenum
;
2464 the_ins
.opcode
[0] = getone (opcode
);
2465 the_ins
.opcode
[1] = gettwo (opcode
);
2467 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2472 /* This switch is a doozy.
2473 Watch the first step; its a big one! */
2506 tmpreg
= 0x3c; /* 7.4 */
2507 if (strchr ("bwl", s
[1]))
2508 nextword
= get_num (&opP
->disp
, 90);
2510 nextword
= get_num (&opP
->disp
, 0);
2511 if (isvar (&opP
->disp
))
2512 add_fix (s
[1], &opP
->disp
, 0, 0);
2516 if (!isbyte (nextword
))
2517 opP
->error
= _("operand out of range");
2522 if (!isword (nextword
))
2523 opP
->error
= _("operand out of range");
2528 if (!issword (nextword
))
2529 opP
->error
= _("operand out of range");
2534 addword (nextword
>> 16);
2561 /* We gotta put out some float. */
2562 if (op (&opP
->disp
) != O_big
)
2567 /* Can other cases happen here? */
2568 if (op (&opP
->disp
) != O_constant
)
2571 val
= (valueT
) offs (&opP
->disp
);
2575 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2576 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2580 offs (&opP
->disp
) = gencnt
;
2582 if (offs (&opP
->disp
) > 0)
2584 if (offs (&opP
->disp
) > baseo
)
2586 as_warn (_("Bignum too big for %c format; truncated"),
2588 offs (&opP
->disp
) = baseo
;
2590 baseo
-= offs (&opP
->disp
);
2593 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
2594 offs (&opP
->disp
)--;
2599 gen_to_words (words
, baseo
, (long) outro
);
2600 for (wordp
= words
; baseo
--; wordp
++)
2604 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2607 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2610 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2613 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2616 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2620 nextword
= get_num (&opP
->disp
, 90);
2622 /* Convert mode 5 addressing with a zero offset into
2623 mode 2 addressing to reduce the instruction size by a
2625 if (! isvar (&opP
->disp
)
2627 && (opP
->disp
.size
== SIZE_UNSPEC
)
2628 && (opP
->reg
>= ADDR0
)
2629 && (opP
->reg
<= ADDR7
))
2631 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2636 && ! isvar (&opP
->disp
)
2639 opP
->disp
.exp
.X_op
= O_symbol
;
2640 opP
->disp
.exp
.X_add_symbol
=
2641 section_symbol (absolute_section
);
2644 /* Force into index mode. Hope this works. */
2646 /* We do the first bit for 32-bit displacements, and the
2647 second bit for 16 bit ones. It is possible that we
2648 should make the default be WORD instead of LONG, but
2649 I think that'd break GCC, so we put up with a little
2650 inefficiency for the sake of working output. */
2652 if (!issword (nextword
)
2653 || (isvar (&opP
->disp
)
2654 && ((opP
->disp
.size
== SIZE_UNSPEC
2655 && flag_short_refs
== 0
2656 && cpu_of_arch (current_architecture
) >= m68020
2657 && ! arch_coldfire_p (current_architecture
))
2658 || opP
->disp
.size
== SIZE_LONG
)))
2660 if (cpu_of_arch (current_architecture
) < m68020
2661 || arch_coldfire_p (current_architecture
))
2663 _("displacement too large for this architecture; needs 68020 or higher");
2665 tmpreg
= 0x3B; /* 7.3 */
2667 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2668 if (isvar (&opP
->disp
))
2672 if (opP
->disp
.size
== SIZE_LONG
2674 /* If the displacement needs pic
2675 relocation it cannot be relaxed. */
2676 || opP
->disp
.pic_reloc
!= pic_none
2681 add_fix ('l', &opP
->disp
, 1, 2);
2685 add_frag (adds (&opP
->disp
),
2686 SEXT (offs (&opP
->disp
)),
2687 TAB (PCREL1632
, SZ_UNDEF
));
2694 add_fix ('l', &opP
->disp
, 0, 0);
2699 addword (nextword
>> 16);
2704 tmpreg
= 0x3A; /* 7.2 */
2706 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2708 if (isvar (&opP
->disp
))
2712 add_fix ('w', &opP
->disp
, 1, 0);
2715 add_fix ('w', &opP
->disp
, 0, 0);
2725 baseo
= get_num (&opP
->disp
, 90);
2726 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2727 outro
= get_num (&opP
->odisp
, 90);
2728 /* Figure out the `addressing mode'.
2729 Also turn on the BASE_DISABLE bit, if needed. */
2730 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2732 tmpreg
= 0x3b; /* 7.3 */
2733 if (opP
->reg
== ZPC
)
2736 else if (opP
->reg
== 0)
2739 tmpreg
= 0x30; /* 6.garbage */
2741 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2744 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2747 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2749 siz1
= opP
->disp
.size
;
2750 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2751 siz2
= opP
->odisp
.size
;
2755 /* Index register stuff. */
2756 if (opP
->index
.reg
!= 0
2757 && opP
->index
.reg
>= DATA
2758 && opP
->index
.reg
<= ADDR7
)
2760 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2762 if (opP
->index
.size
== SIZE_LONG
2763 || (opP
->index
.size
== SIZE_UNSPEC
2764 && m68k_index_width_default
== SIZE_LONG
))
2767 if ((opP
->index
.scale
!= 1
2768 && cpu_of_arch (current_architecture
) < m68020
)
2769 || (opP
->index
.scale
== 8
2770 && (arch_coldfire_p (current_architecture
)
2771 && !arch_coldfire_fpu (current_architecture
))))
2774 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2777 if (arch_coldfire_p (current_architecture
)
2778 && opP
->index
.size
== SIZE_WORD
)
2779 opP
->error
= _("invalid index size for coldfire");
2781 switch (opP
->index
.scale
)
2798 GET US OUT OF HERE! */
2800 /* Must be INDEX, with an index register. Address
2801 register cannot be ZERO-PC, and either :b was
2802 forced, or we know it will fit. For a 68000 or
2803 68010, force this mode anyways, because the
2804 larger modes aren't supported. */
2805 if (opP
->mode
== BASE
2806 && ((opP
->reg
>= ADDR0
2807 && opP
->reg
<= ADDR7
)
2810 if (siz1
== SIZE_BYTE
2811 || cpu_of_arch (current_architecture
) < m68020
2812 || arch_coldfire_p (current_architecture
)
2813 || (siz1
== SIZE_UNSPEC
2814 && ! isvar (&opP
->disp
)
2815 && issbyte (baseo
)))
2817 nextword
+= baseo
& 0xff;
2819 if (isvar (&opP
->disp
))
2821 /* Do a byte relocation. If it doesn't
2822 fit (possible on m68000) let the
2823 fixup processing complain later. */
2825 add_fix ('B', &opP
->disp
, 1, 1);
2827 add_fix ('B', &opP
->disp
, 0, 0);
2829 else if (siz1
!= SIZE_BYTE
)
2831 if (siz1
!= SIZE_UNSPEC
)
2832 as_warn (_("Forcing byte displacement"));
2833 if (! issbyte (baseo
))
2834 opP
->error
= _("byte displacement out of range");
2839 else if (siz1
== SIZE_UNSPEC
2841 && isvar (&opP
->disp
)
2842 && subs (&opP
->disp
) == NULL
2844 /* If the displacement needs pic
2845 relocation it cannot be relaxed. */
2846 && opP
->disp
.pic_reloc
== pic_none
2850 /* The code in md_convert_frag_1 needs to be
2851 able to adjust nextword. Call frag_grow
2852 to ensure that we have enough space in
2853 the frag obstack to make all the bytes
2856 nextword
+= baseo
& 0xff;
2858 add_frag (adds (&opP
->disp
),
2859 SEXT (offs (&opP
->disp
)),
2860 TAB (PCINDEX
, SZ_UNDEF
));
2868 nextword
|= 0x40; /* No index reg. */
2869 if (opP
->index
.reg
>= ZDATA0
2870 && opP
->index
.reg
<= ZDATA7
)
2871 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2872 else if (opP
->index
.reg
>= ZADDR0
2873 || opP
->index
.reg
<= ZADDR7
)
2874 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2877 /* It isn't simple. */
2879 if (cpu_of_arch (current_architecture
) < m68020
2880 || arch_coldfire_p (current_architecture
))
2882 _("invalid operand mode for this architecture; needs 68020 or higher");
2885 /* If the guy specified a width, we assume that it is
2886 wide enough. Maybe it isn't. If so, we lose. */
2890 if (isvar (&opP
->disp
)
2892 : ! issword (baseo
))
2897 else if (! isvar (&opP
->disp
) && baseo
== 0)
2906 as_warn (_(":b not permitted; defaulting to :w"));
2916 /* Figure out inner displacement stuff. */
2917 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2919 if (cpu_of_arch (current_architecture
) & cpu32
)
2920 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2924 if (isvar (&opP
->odisp
)
2926 : ! issword (outro
))
2931 else if (! isvar (&opP
->odisp
) && outro
== 0)
2940 as_warn (_(":b not permitted; defaulting to :w"));
2949 if (opP
->mode
== POST
2950 && (nextword
& 0x40) == 0)
2955 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2957 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2958 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2960 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2962 if (siz1
== SIZE_LONG
)
2963 addword (baseo
>> 16);
2964 if (siz1
!= SIZE_UNSPEC
)
2967 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2968 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2969 if (siz2
== SIZE_LONG
)
2970 addword (outro
>> 16);
2971 if (siz2
!= SIZE_UNSPEC
)
2977 nextword
= get_num (&opP
->disp
, 90);
2978 switch (opP
->disp
.size
)
2983 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2985 tmpreg
= 0x38; /* 7.0 */
2989 if (isvar (&opP
->disp
)
2990 && !subs (&opP
->disp
)
2991 && adds (&opP
->disp
)
2993 /* If the displacement needs pic relocation it
2994 cannot be relaxed. */
2995 && opP
->disp
.pic_reloc
== pic_none
2998 && !strchr ("~%&$?", s
[0]))
3000 tmpreg
= 0x3A; /* 7.2 */
3001 add_frag (adds (&opP
->disp
),
3002 SEXT (offs (&opP
->disp
)),
3003 TAB (ABSTOPCREL
, SZ_UNDEF
));
3006 /* Fall through into long. */
3008 if (isvar (&opP
->disp
))
3009 add_fix ('l', &opP
->disp
, 0, 0);
3011 tmpreg
= 0x39;/* 7.1 mode */
3012 addword (nextword
>> 16);
3017 as_bad (_("unsupported byte value; use a different suffix"));
3021 if (isvar (&opP
->disp
))
3022 add_fix ('w', &opP
->disp
, 0, 0);
3024 tmpreg
= 0x38;/* 7.0 mode */
3032 as_bad (_("unknown/incorrect operand"));
3036 /* If s[0] is '4', then this is for the mac instructions
3037 that can have a trailing_ampersand set. If so, set 0x100
3038 bit on tmpreg so install_gen_operand can check for it and
3039 set the appropriate bit (word2, bit 5). */
3042 if (opP
->trailing_ampersand
)
3045 install_gen_operand (s
[1], tmpreg
);
3051 { /* JF: I hate floating point! */
3066 tmpreg
= get_num (&opP
->disp
, tmpreg
);
3067 if (isvar (&opP
->disp
))
3068 add_fix (s
[1], &opP
->disp
, 0, 0);
3071 case 'b': /* Danger: These do no check for
3072 certain types of overflow.
3074 if (!isbyte (tmpreg
))
3075 opP
->error
= _("out of range");
3076 insop (tmpreg
, opcode
);
3077 if (isvar (&opP
->disp
))
3078 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
3079 (opcode
->m_codenum
) * 2 + 1;
3082 if (!issbyte (tmpreg
))
3083 opP
->error
= _("out of range");
3084 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
3085 if (isvar (&opP
->disp
))
3086 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
3089 if (!isword (tmpreg
))
3090 opP
->error
= _("out of range");
3091 insop (tmpreg
, opcode
);
3092 if (isvar (&opP
->disp
))
3093 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
3096 if (!issword (tmpreg
))
3097 opP
->error
= _("out of range");
3098 insop (tmpreg
, opcode
);
3099 if (isvar (&opP
->disp
))
3100 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
3103 /* Because of the way insop works, we put these two out
3105 insop (tmpreg
, opcode
);
3106 insop (tmpreg
>> 16, opcode
);
3107 if (isvar (&opP
->disp
))
3108 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
3115 install_operand (s
[1], tmpreg
);
3126 install_operand (s
[1], opP
->reg
- ADDR
);
3130 tmpreg
= get_num (&opP
->disp
, 90);
3135 add_fix ('B', &opP
->disp
, 1, -1);
3138 add_fix ('w', &opP
->disp
, 1, 0);
3143 the_ins
.opcode
[0] |= 0xff;
3144 add_fix ('l', &opP
->disp
, 1, 0);
3148 case 'g': /* Conditional branch */
3149 have_disp
= HAVE_LONG_CALL (current_architecture
);
3152 case 'b': /* Unconditional branch */
3153 have_disp
= HAVE_LONG_BRANCH (current_architecture
);
3154 use_pl
= LONG_BRANCH_VIA_COND (current_architecture
);
3157 case 's': /* Unconditional subroutine */
3158 have_disp
= HAVE_LONG_CALL (current_architecture
);
3161 if (subs (&opP
->disp
) /* We can't relax it. */
3163 /* If the displacement needs pic relocation it cannot be
3165 || opP
->disp
.pic_reloc
!= pic_none
3170 as_warn (_("Can't use long branches on this architecture"));
3174 /* This could either be a symbol, or an absolute
3175 address. If it's an absolute address, turn it into
3176 an absolute jump right here and keep it out of the
3178 if (adds (&opP
->disp
) == 0)
3180 if (the_ins
.opcode
[0] == 0x6000) /* jbra */
3181 the_ins
.opcode
[0] = 0x4EF9;
3182 else if (the_ins
.opcode
[0] == 0x6100) /* jbsr */
3183 the_ins
.opcode
[0] = 0x4EB9;
3186 the_ins
.opcode
[0] ^= 0x0100;
3187 the_ins
.opcode
[0] |= 0x0006;
3190 add_fix ('l', &opP
->disp
, 0, 0);
3196 /* Now we know it's going into the relaxer. Now figure
3197 out which mode. We try in this order of preference:
3198 long branch, absolute jump, byte/word branches only. */
3200 add_frag (adds (&opP
->disp
),
3201 SEXT (offs (&opP
->disp
)),
3202 TAB (BRANCHBWL
, SZ_UNDEF
));
3203 else if (! flag_keep_pcrel
)
3205 if ((the_ins
.opcode
[0] == 0x6000)
3206 || (the_ins
.opcode
[0] == 0x6100))
3207 add_frag (adds (&opP
->disp
),
3208 SEXT (offs (&opP
->disp
)),
3209 TAB (BRABSJUNC
, SZ_UNDEF
));
3211 add_frag (adds (&opP
->disp
),
3212 SEXT (offs (&opP
->disp
)),
3213 TAB (BRABSJCOND
, SZ_UNDEF
));
3216 add_frag (adds (&opP
->disp
),
3217 SEXT (offs (&opP
->disp
)),
3218 (use_pl
? TAB (BRANCHBWPL
, SZ_UNDEF
)
3219 : TAB (BRANCHBW
, SZ_UNDEF
)));
3222 if (isvar (&opP
->disp
))
3224 /* Check for DBcc instructions. We can relax them,
3225 but only if we have long branches and/or absolute
3227 if (((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
3228 && (HAVE_LONG_BRANCH (current_architecture
)
3229 || ! flag_keep_pcrel
))
3231 if (HAVE_LONG_BRANCH (current_architecture
))
3232 add_frag (adds (&opP
->disp
),
3233 SEXT (offs (&opP
->disp
)),
3234 TAB (DBCCLBR
, SZ_UNDEF
));
3236 add_frag (adds (&opP
->disp
),
3237 SEXT (offs (&opP
->disp
)),
3238 TAB (DBCCABSJ
, SZ_UNDEF
));
3241 add_fix ('w', &opP
->disp
, 1, 0);
3245 case 'C': /* Fixed size LONG coproc branches. */
3246 add_fix ('l', &opP
->disp
, 1, 0);
3250 case 'c': /* Var size Coprocesssor branches. */
3251 if (subs (&opP
->disp
) || (adds (&opP
->disp
) == 0))
3253 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
3254 add_fix ('l', &opP
->disp
, 1, 0);
3259 add_frag (adds (&opP
->disp
),
3260 SEXT (offs (&opP
->disp
)),
3261 TAB (FBRANCH
, SZ_UNDEF
));
3268 case 'C': /* Ignore it. */
3271 case 'd': /* JF this is a kludge. */
3272 install_operand ('s', opP
->reg
- ADDR
);
3273 tmpreg
= get_num (&opP
->disp
, 90);
3274 if (!issword (tmpreg
))
3276 as_warn (_("Expression out of range, using 0"));
3283 install_operand (s
[1], opP
->reg
- DATA
);
3286 case 'e': /* EMAC ACCx, reg/reg. */
3287 install_operand (s
[1], opP
->reg
- ACC
);
3290 case 'E': /* Ignore it. */
3294 install_operand (s
[1], opP
->reg
- FP0
);
3297 case 'g': /* EMAC ACCEXTx. */
3298 install_operand (s
[1], opP
->reg
- ACCEXT01
);
3301 case 'G': /* Ignore it. */
3306 tmpreg
= opP
->reg
- COP0
;
3307 install_operand (s
[1], tmpreg
);
3310 case 'i': /* MAC/EMAC scale factor. */
3311 install_operand (s
[1], opP
->mode
== LSH
? 0x1 : 0x3);
3314 case 'J': /* JF foo. */
3357 tmpreg
= 0x00c + (opP
->reg
- ACR4
);
3464 install_operand (s
[1], tmpreg
);
3468 tmpreg
= get_num (&opP
->disp
, 55);
3469 install_operand (s
[1], tmpreg
& 0x7f);
3476 if (tmpreg
& 0x7FF0000)
3477 as_bad (_("Floating point register in register list"));
3478 insop (reverse_16_bits (tmpreg
), opcode
);
3482 if (tmpreg
& 0x700FFFF)
3483 as_bad (_("Wrong register in floating-point reglist"));
3484 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
3492 if (tmpreg
& 0x7FF0000)
3493 as_bad (_("Floating point register in register list"));
3494 insop (tmpreg
, opcode
);
3496 else if (s
[1] == '8')
3498 if (tmpreg
& 0x0FFFFFF)
3499 as_bad (_("incorrect register in reglist"));
3500 install_operand (s
[1], tmpreg
>> 24);
3504 if (tmpreg
& 0x700FFFF)
3505 as_bad (_("wrong register in floating-point reglist"));
3507 install_operand (s
[1], tmpreg
>> 16);
3512 install_operand (s
[1], get_num (&opP
->disp
, 60));
3516 tmpreg
= ((opP
->mode
== DREG
)
3517 ? 0x20 + (int) (opP
->reg
- DATA
)
3518 : (get_num (&opP
->disp
, 40) & 0x1F));
3519 install_operand (s
[1], tmpreg
);
3523 tmpreg
= get_num (&opP
->disp
, 10);
3526 install_operand (s
[1], tmpreg
);
3530 /* This depends on the fact that ADDR registers are eight
3531 more than their corresponding DATA regs, so the result
3532 will have the ADDR_REG bit set. */
3533 install_operand (s
[1], opP
->reg
- DATA
);
3537 if (opP
->mode
== AINDR
)
3538 install_operand (s
[1], opP
->reg
- DATA
);
3540 install_operand (s
[1], opP
->index
.reg
- DATA
);
3544 if (opP
->reg
== FPI
)
3546 else if (opP
->reg
== FPS
)
3548 else if (opP
->reg
== FPC
)
3552 install_operand (s
[1], tmpreg
);
3555 case 'S': /* Ignore it. */
3559 install_operand (s
[1], get_num (&opP
->disp
, 30));
3562 case 'U': /* Ignore it. */
3581 as_fatal (_("failed sanity check"));
3582 } /* switch on cache token. */
3583 install_operand (s
[1], tmpreg
);
3586 /* JF: These are out of order, I fear. */
3599 install_operand (s
[1], tmpreg
);
3625 install_operand (s
[1], tmpreg
);
3629 if (opP
->reg
== VAL
)
3648 install_operand (s
[1], tmpreg
);
3662 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3673 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3679 install_operand (s
[1], tmpreg
);
3682 know (opP
->reg
== PSR
);
3685 know (opP
->reg
== PCSR
);
3700 install_operand (s
[1], tmpreg
);
3703 tmpreg
= get_num (&opP
->disp
, 20);
3704 install_operand (s
[1], tmpreg
);
3706 case '_': /* used only for move16 absolute 32-bit address. */
3707 if (isvar (&opP
->disp
))
3708 add_fix ('l', &opP
->disp
, 0, 0);
3709 tmpreg
= get_num (&opP
->disp
, 90);
3710 addword (tmpreg
>> 16);
3711 addword (tmpreg
& 0xFFFF);
3714 install_operand (s
[1], opP
->reg
- DATA0L
);
3715 opP
->reg
-= (DATA0L
);
3716 opP
->reg
&= 0x0F; /* remove upper/lower bit. */
3719 tmpreg
= get_num (&opP
->disp
, 80);
3722 install_operand (s
[1], tmpreg
);
3725 tmpreg
= get_num (&opP
->disp
, 10);
3726 install_operand (s
[1], tmpreg
- 1);
3729 tmpreg
= get_num (&opP
->disp
, 65);
3730 install_operand (s
[1], tmpreg
);
3737 /* By the time whe get here (FINALLY) the_ins contains the complete
3738 instruction, ready to be emitted. . . */
3742 reverse_16_bits (int in
)
3747 static int mask
[16] =
3749 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3750 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3752 for (n
= 0; n
< 16; n
++)
3755 out
|= mask
[15 - n
];
3758 } /* reverse_16_bits() */
3761 reverse_8_bits (int in
)
3766 static int mask
[8] =
3768 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3771 for (n
= 0; n
< 8; n
++)
3777 } /* reverse_8_bits() */
3779 /* Cause an extra frag to be generated here, inserting up to
3780 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3781 generated; its primary type is rs_machine_dependent.
3783 The TYPE parameter is also used by md_convert_frag_1 and
3784 md_estimate_size_before_relax. The appropriate type of fixup will
3785 be emitted by md_convert_frag_1.
3787 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3789 install_operand (int mode
, int val
)
3794 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge. */
3797 the_ins
.opcode
[0] |= val
<< 9;
3800 the_ins
.opcode
[1] |= val
<< 9;
3803 the_ins
.opcode
[1] |= val
<< 12;
3806 the_ins
.opcode
[1] |= val
<< 6;
3809 the_ins
.opcode
[1] |= val
;
3812 the_ins
.opcode
[2] |= val
<< 12;
3815 the_ins
.opcode
[2] |= val
<< 6;
3818 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3819 three words long! */
3821 the_ins
.opcode
[2] |= val
;
3824 the_ins
.opcode
[1] |= val
<< 7;
3827 the_ins
.opcode
[1] |= val
<< 10;
3831 the_ins
.opcode
[1] |= val
<< 5;
3836 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3839 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3842 the_ins
.opcode
[0] |= val
= 0xff;
3845 the_ins
.opcode
[0] |= val
<< 9;
3848 the_ins
.opcode
[1] |= val
;
3851 the_ins
.opcode
[1] |= val
;
3852 the_ins
.numo
++; /* What a hack. */
3855 the_ins
.opcode
[1] |= val
<< 4;
3863 the_ins
.opcode
[0] |= (val
<< 6);
3866 the_ins
.opcode
[1] = (val
>> 16);
3867 the_ins
.opcode
[2] = val
& 0xffff;
3870 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3871 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3872 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3874 case 'n': /* MAC/EMAC Rx on !load. */
3875 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3876 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3877 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3879 case 'o': /* MAC/EMAC Rx on load. */
3880 the_ins
.opcode
[1] |= val
<< 12;
3881 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3883 case 'M': /* MAC/EMAC Ry on !load. */
3884 the_ins
.opcode
[0] |= (val
& 0xF);
3885 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3887 case 'N': /* MAC/EMAC Ry on load. */
3888 the_ins
.opcode
[1] |= (val
& 0xF);
3889 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3892 the_ins
.opcode
[1] |= ((val
!= 1) << 10);
3895 the_ins
.opcode
[0] |= ((val
& 0x3) << 9);
3898 the_ins
.opcode
[0] |= ((val
& 0x3) << 0);
3900 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3901 the_ins
.opcode
[0] |= ((~val
& 0x1) << 7);
3902 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3904 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3905 the_ins
.opcode
[0] |= ((val
& 0x1) << 7);
3906 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3909 the_ins
.opcode
[1] |= ((val
& 0x3) << 9);
3912 the_ins
.opcode
[0] |= (val
& 0x1) <<10;
3916 as_fatal (_("failed sanity check."));
3921 install_gen_operand (int mode
, int val
)
3925 case '/': /* Special for mask loads for mac/msac insns with
3926 possible mask; trailing_ampersend set in bit 8. */
3927 the_ins
.opcode
[0] |= (val
& 0x3f);
3928 the_ins
.opcode
[1] |= (((val
& 0x100) >> 8) << 5);
3931 the_ins
.opcode
[0] |= val
;
3934 /* This is a kludge!!! */
3935 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3944 the_ins
.opcode
[0] |= val
;
3946 /* more stuff goes here. */
3948 as_fatal (_("failed sanity check."));
3952 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3953 then deal with the bitfield hack. */
3956 crack_operand (char *str
, struct m68k_op
*opP
)
3958 register int parens
;
3960 register char *beg_str
;
3968 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3974 else if (*str
== ')')
3978 opP
->error
= _("Extra )");
3984 if (flag_mri
&& *str
== '\'')
3985 inquote
= ! inquote
;
3987 if (!*str
&& parens
)
3989 opP
->error
= _("Missing )");
3994 if (m68k_ip_op (beg_str
, opP
) != 0)
4001 c
= *++str
; /* JF bitfield hack. */
4006 as_bad (_("Missing operand"));
4009 /* Detect MRI REG symbols and convert them to REGLSTs. */
4010 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
4013 opP
->mask
= ~(int)opP
->reg
;
4020 /* This is the guts of the machine-dependent assembler. STR points to a
4021 machine dependent instruction. This function is supposed to emit
4022 the frags/bytes it assembles to.
4026 insert_reg (const char *regname
, int regnum
)
4031 #ifdef REGISTER_PREFIX
4032 if (!flag_reg_prefix_optional
)
4034 buf
[0] = REGISTER_PREFIX
;
4035 strcpy (buf
+ 1, regname
);
4040 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
4041 &zero_address_frag
));
4043 for (i
= 0; regname
[i
]; i
++)
4044 buf
[i
] = TOUPPER (regname
[i
]);
4047 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
4048 &zero_address_frag
));
4057 static const struct init_entry init_table
[] =
4117 { "accext01", ACCEXT01
},
4118 { "accext23", ACCEXT23
},
4122 /* Control registers. */
4123 { "sfc", SFC
}, /* Source Function Code. */
4125 { "dfc", DFC
}, /* Destination Function Code. */
4127 { "cacr", CACR
}, /* Cache Control Register. */
4128 { "caar", CAAR
}, /* Cache Address Register. */
4129 { "cpucr", CPUCR
}, /* CPU Control Register. */
4131 { "usp", USP
}, /* User Stack Pointer. */
4132 { "vbr", VBR
}, /* Vector Base Register. */
4133 { "msp", MSP
}, /* Master Stack Pointer. */
4134 { "isp", ISP
}, /* Interrupt Stack Pointer. */
4136 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0. */
4137 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1. */
4138 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0. */
4139 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1. */
4141 /* 68ec040 versions of same */
4142 { "iacr0", ITT0
}, /* Instruction Access Control Register 0. */
4143 { "iacr1", ITT1
}, /* Instruction Access Control Register 0. */
4144 { "dacr0", DTT0
}, /* Data Access Control Register 0. */
4145 { "dacr1", DTT1
}, /* Data Access Control Register 0. */
4147 /* Coldfire versions of same. The ColdFire programmer's reference
4148 manual indicated that the order is 2,3,0,1, but Ken Rose
4149 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
4150 { "acr0", ACR0
}, /* Access Control Unit 0. */
4151 { "acr1", ACR1
}, /* Access Control Unit 1. */
4152 { "acr2", ACR2
}, /* Access Control Unit 2. */
4153 { "acr3", ACR3
}, /* Access Control Unit 3. */
4154 { "acr4", ACR4
}, /* Access Control Unit 4. */
4155 { "acr5", ACR5
}, /* Access Control Unit 5. */
4156 { "acr6", ACR6
}, /* Access Control Unit 6. */
4157 { "acr7", ACR7
}, /* Access Control Unit 7. */
4159 { "tc", TC
}, /* MMU Translation Control Register. */
4163 { "mmusr", MMUSR
}, /* MMU Status Register. */
4164 { "srp", SRP
}, /* User Root Pointer. */
4165 { "urp", URP
}, /* Supervisor Root Pointer. */
4168 { "mmubar", MMUBAR
},
4171 { "rombar", ROMBAR
}, /* ROM Base Address Register. */
4172 { "rambar0", RAMBAR0
}, /* ROM Base Address Register. */
4173 { "rambar1", RAMBAR1
}, /* ROM Base Address Register. */
4174 { "mbar", MBAR
}, /* Module Base Address Register. */
4176 { "mbar0", MBAR0
}, /* mcfv4e registers. */
4177 { "mbar1", MBAR1
}, /* mcfv4e registers. */
4178 { "rombar0", ROMBAR0
}, /* mcfv4e registers. */
4179 { "rombar1", ROMBAR1
}, /* mcfv4e registers. */
4180 { "mpcr", MPCR
}, /* mcfv4e registers. */
4181 { "edrambar", EDRAMBAR
}, /* mcfv4e registers. */
4182 { "secmbar", SECMBAR
}, /* mcfv4e registers. */
4183 { "asid", TC
}, /* mcfv4e registers. */
4184 { "mmubar", BUSCR
}, /* mcfv4e registers. */
4185 { "pcr1u0", PCR1U0
}, /* mcfv4e registers. */
4186 { "pcr1l0", PCR1L0
}, /* mcfv4e registers. */
4187 { "pcr2u0", PCR2U0
}, /* mcfv4e registers. */
4188 { "pcr2l0", PCR2L0
}, /* mcfv4e registers. */
4189 { "pcr3u0", PCR3U0
}, /* mcfv4e registers. */
4190 { "pcr3l0", PCR3L0
}, /* mcfv4e registers. */
4191 { "pcr1u1", PCR1U1
}, /* mcfv4e registers. */
4192 { "pcr1l1", PCR1L1
}, /* mcfv4e registers. */
4193 { "pcr2u1", PCR2U1
}, /* mcfv4e registers. */
4194 { "pcr2l1", PCR2L1
}, /* mcfv4e registers. */
4195 { "pcr3u1", PCR3U1
}, /* mcfv4e registers. */
4196 { "pcr3l1", PCR3L1
}, /* mcfv4e registers. */
4198 { "flashbar", FLASHBAR
}, /* mcf528x registers. */
4199 { "rambar", RAMBAR
}, /* mcf528x registers. */
4201 { "mbar2", MBAR2
}, /* mcf5249 registers. */
4203 { "rgpiobar", RGPIOBAR
}, /* mcf54418 registers. */
4205 { "cac", CAC
}, /* fido registers. */
4206 { "mbb", MBO
}, /* fido registers (obsolete). */
4207 { "mbo", MBO
}, /* fido registers. */
4208 /* End of control registers. */
4242 /* 68ec030 versions of same. */
4245 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4248 /* Suppressed data and address registers. */
4266 /* Upper and lower data and address registers, used by macw and msacw. */
4307 init_regtable (void)
4310 for (i
= 0; init_table
[i
].name
; i
++)
4311 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
4315 md_assemble (char *str
)
4322 int shorts_this_frag
;
4325 if (!selected_cpu
&& !selected_arch
)
4327 /* We've not selected an architecture yet. Set the default
4328 now. We do this lazily so that an initial .cpu or .arch directive
4330 if (!m68k_set_cpu (TARGET_CPU
, 1, 1))
4331 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU
);
4336 /* In MRI mode, the instruction and operands are separated by a
4337 space. Anything following the operands is a comment. The label
4338 has already been removed. */
4346 for (s
= str
; *s
!= '\0'; s
++)
4348 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
4366 inquote
= ! inquote
;
4371 memset (&the_ins
, '\0', sizeof (the_ins
));
4376 for (n
= 0; n
< the_ins
.numargs
; n
++)
4377 if (the_ins
.operands
[n
].error
)
4379 er
= the_ins
.operands
[n
].error
;
4385 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
4389 /* If there is a current label, record that it marks an instruction. */
4390 if (current_label
!= NULL
)
4392 current_label
->text
= 1;
4393 current_label
= NULL
;
4397 /* Tie dwarf2 debug info to the address at the start of the insn. */
4398 dwarf2_emit_insn (0);
4401 if (the_ins
.nfrag
== 0)
4403 /* No frag hacking involved; just put it out. */
4404 toP
= frag_more (2 * the_ins
.numo
);
4405 fromP
= &the_ins
.opcode
[0];
4406 for (m
= the_ins
.numo
; m
; --m
)
4408 md_number_to_chars (toP
, (long) (*fromP
), 2);
4412 /* Put out symbol-dependent info. */
4413 for (m
= 0; m
< the_ins
.nrel
; m
++)
4415 switch (the_ins
.reloc
[m
].wid
)
4434 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4435 the_ins
.reloc
[m
].wid
);
4438 fixP
= fix_new_exp (frag_now
,
4439 ((toP
- frag_now
->fr_literal
)
4440 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4442 &the_ins
.reloc
[m
].exp
,
4443 the_ins
.reloc
[m
].pcrel
,
4444 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
4445 the_ins
.reloc
[m
].pic_reloc
));
4446 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4447 if (the_ins
.reloc
[m
].wid
== 'B')
4448 fixP
->fx_signed
= 1;
4453 /* There's some frag hacking. */
4455 /* Calculate the max frag size. */
4458 wid
= 2 * the_ins
.fragb
[0].fragoff
;
4459 for (n
= 1; n
< the_ins
.nfrag
; n
++)
4460 wid
+= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4461 /* frag_var part. */
4462 wid
+= FRAG_VAR_SIZE
;
4463 /* Make sure the whole insn fits in one chunk, in particular that
4464 the var part is attached, as we access one byte before the
4465 variable frag for byte branches. */
4469 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
4474 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
4476 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4477 toP
= frag_more (wid
);
4479 shorts_this_frag
= 0;
4480 for (m
= wid
/ 2; m
; --m
)
4482 md_number_to_chars (toP
, (long) (*fromP
), 2);
4487 for (m
= 0; m
< the_ins
.nrel
; m
++)
4489 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
4491 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
4494 wid
= the_ins
.reloc
[m
].wid
;
4497 the_ins
.reloc
[m
].wid
= 0;
4498 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4500 fixP
= fix_new_exp (frag_now
,
4501 ((toP
- frag_now
->fr_literal
)
4502 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4504 &the_ins
.reloc
[m
].exp
,
4505 the_ins
.reloc
[m
].pcrel
,
4506 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4507 the_ins
.reloc
[m
].pic_reloc
));
4508 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4510 (void) frag_var (rs_machine_dependent
, FRAG_VAR_SIZE
, 0,
4511 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
4512 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
4514 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4515 shorts_this_frag
= 0;
4518 toP
= frag_more (n
* 2);
4521 md_number_to_chars (toP
, (long) (*fromP
), 2);
4527 for (m
= 0; m
< the_ins
.nrel
; m
++)
4531 wid
= the_ins
.reloc
[m
].wid
;
4534 the_ins
.reloc
[m
].wid
= 0;
4535 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4537 fixP
= fix_new_exp (frag_now
,
4538 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
4539 - shorts_this_frag
* 2),
4541 &the_ins
.reloc
[m
].exp
,
4542 the_ins
.reloc
[m
].pcrel
,
4543 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4544 the_ins
.reloc
[m
].pic_reloc
));
4545 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4549 /* Comparison function used by qsort to rank the opcode entries by name. */
4552 m68k_compare_opcode (const void * v1
, const void * v2
)
4554 struct m68k_opcode
* op1
, * op2
;
4560 op1
= *(struct m68k_opcode
**) v1
;
4561 op2
= *(struct m68k_opcode
**) v2
;
4563 /* Compare the two names. If different, return the comparison.
4564 If the same, return the order they are in the opcode table. */
4565 ret
= strcmp (op1
->name
, op2
->name
);
4576 const struct m68k_opcode
*ins
;
4577 struct m68k_incant
*hack
, *slak
;
4578 const char *retval
= 0; /* Empty string, or error msg text. */
4581 /* Set up hash tables with 68000 instructions.
4582 similar to what the vax assembler does. */
4583 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4584 a copy of it at runtime, adding in the information we want but isn't
4585 there. I think it'd be better to have an awk script hack the table
4586 at compile time. Or even just xstr the table and use it as-is. But
4587 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4592 flag_reg_prefix_optional
= 1;
4594 if (! m68k_rel32_from_cmdline
)
4598 /* First sort the opcode table into alphabetical order to seperate
4599 the order that the assembler wants to see the opcodes from the
4600 order that the disassembler wants to see them. */
4601 m68k_sorted_opcodes
= xmalloc (m68k_numopcodes
* sizeof (* m68k_sorted_opcodes
));
4602 if (!m68k_sorted_opcodes
)
4603 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4604 m68k_numopcodes
* ((int) sizeof (* m68k_sorted_opcodes
)));
4606 for (i
= m68k_numopcodes
; i
--;)
4607 m68k_sorted_opcodes
[i
] = m68k_opcodes
+ i
;
4609 qsort (m68k_sorted_opcodes
, m68k_numopcodes
,
4610 sizeof (m68k_sorted_opcodes
[0]), m68k_compare_opcode
);
4612 op_hash
= hash_new ();
4614 obstack_begin (&robyn
, 4000);
4615 for (i
= 0; i
< m68k_numopcodes
; i
++)
4617 hack
= slak
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4620 ins
= m68k_sorted_opcodes
[i
];
4622 /* We must enter all insns into the table, because .arch and
4623 .cpu directives can change things. */
4624 slak
->m_operands
= ins
->args
;
4625 slak
->m_arch
= ins
->arch
;
4626 slak
->m_opcode
= ins
->opcode
;
4628 /* In most cases we can determine the number of opcode words
4629 by checking the second word of the mask. Unfortunately
4630 some instructions have 2 opcode words, but no fixed bits
4631 in the second word. A leading dot in the operands
4632 string also indicates 2 opcodes. */
4633 if (*slak
->m_operands
== '.')
4636 slak
->m_codenum
= 2;
4638 else if (ins
->match
& 0xffffL
)
4639 slak
->m_codenum
= 2;
4641 slak
->m_codenum
= 1;
4642 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
4644 if (i
+ 1 != m68k_numopcodes
4645 && !strcmp (ins
->name
, m68k_sorted_opcodes
[i
+ 1]->name
))
4647 slak
->m_next
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4652 slak
= slak
->m_next
;
4656 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
4658 as_fatal (_("Internal Error: Can't hash %s: %s"), ins
->name
, retval
);
4661 for (i
= 0; i
< m68k_numaliases
; i
++)
4663 const char *name
= m68k_opcode_aliases
[i
].primary
;
4664 const char *alias
= m68k_opcode_aliases
[i
].alias
;
4665 void *val
= hash_find (op_hash
, name
);
4668 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4669 retval
= hash_insert (op_hash
, alias
, val
);
4671 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4674 /* In MRI mode, all unsized branches are variable sized. Normally,
4675 they are word sized. */
4678 static struct m68k_opcode_alias mri_aliases
[] =
4699 i
< (int) (sizeof mri_aliases
/ sizeof mri_aliases
[0]);
4702 const char *name
= mri_aliases
[i
].primary
;
4703 const char *alias
= mri_aliases
[i
].alias
;
4704 void *val
= hash_find (op_hash
, name
);
4707 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4708 retval
= hash_jam (op_hash
, alias
, val
);
4710 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4714 for (i
= 0; i
< (int) sizeof (notend_table
); i
++)
4716 notend_table
[i
] = 0;
4717 alt_notend_table
[i
] = 0;
4720 notend_table
[','] = 1;
4721 notend_table
['{'] = 1;
4722 notend_table
['}'] = 1;
4723 alt_notend_table
['a'] = 1;
4724 alt_notend_table
['A'] = 1;
4725 alt_notend_table
['d'] = 1;
4726 alt_notend_table
['D'] = 1;
4727 alt_notend_table
['#'] = 1;
4728 alt_notend_table
['&'] = 1;
4729 alt_notend_table
['f'] = 1;
4730 alt_notend_table
['F'] = 1;
4731 #ifdef REGISTER_PREFIX
4732 alt_notend_table
[REGISTER_PREFIX
] = 1;
4735 /* We need to put '(' in alt_notend_table to handle
4736 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4737 alt_notend_table
['('] = 1;
4739 /* We need to put '@' in alt_notend_table to handle
4740 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4741 alt_notend_table
['@'] = 1;
4743 /* We need to put digits in alt_notend_table to handle
4744 bfextu %d0{24:1},%d0 */
4745 alt_notend_table
['0'] = 1;
4746 alt_notend_table
['1'] = 1;
4747 alt_notend_table
['2'] = 1;
4748 alt_notend_table
['3'] = 1;
4749 alt_notend_table
['4'] = 1;
4750 alt_notend_table
['5'] = 1;
4751 alt_notend_table
['6'] = 1;
4752 alt_notend_table
['7'] = 1;
4753 alt_notend_table
['8'] = 1;
4754 alt_notend_table
['9'] = 1;
4756 #ifndef MIT_SYNTAX_ONLY
4757 /* Insert pseudo ops, these have to go into the opcode table since
4758 gas expects pseudo ops to start with a dot. */
4762 while (mote_pseudo_table
[n
].poc_name
)
4764 hack
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4765 hash_insert (op_hash
,
4766 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
4767 hack
->m_operands
= 0;
4777 record_alignment (text_section
, 2);
4778 record_alignment (data_section
, 2);
4779 record_alignment (bss_section
, 2);
4784 /* This is called when a label is defined. */
4787 m68k_frob_label (symbolS
*sym
)
4789 struct label_line
*n
;
4791 n
= (struct label_line
*) xmalloc (sizeof *n
);
4794 as_where (&n
->file
, &n
->line
);
4800 dwarf2_emit_label (sym
);
4804 /* This is called when a value that is not an instruction is emitted. */
4807 m68k_flush_pending_output (void)
4809 current_label
= NULL
;
4812 /* This is called at the end of the assembly, when the final value of
4813 the label is known. We warn if this is a text symbol aligned at an
4817 m68k_frob_symbol (symbolS
*sym
)
4819 if (S_GET_SEGMENT (sym
) == reg_section
4820 && (int) S_GET_VALUE (sym
) < 0)
4822 S_SET_SEGMENT (sym
, absolute_section
);
4823 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
4825 else if ((S_GET_VALUE (sym
) & 1) != 0)
4827 struct label_line
*l
;
4829 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4831 if (l
->label
== sym
)
4834 as_warn_where (l
->file
, l
->line
,
4835 _("text label `%s' aligned to odd boundary"),
4843 /* This is called if we go in or out of MRI mode because of the .mri
4847 m68k_mri_mode_change (int on
)
4851 if (! flag_reg_prefix_optional
)
4853 flag_reg_prefix_optional
= 1;
4854 #ifdef REGISTER_PREFIX
4859 if (! m68k_rel32_from_cmdline
)
4864 if (! reg_prefix_optional_seen
)
4866 #ifdef REGISTER_PREFIX_OPTIONAL
4867 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
4869 flag_reg_prefix_optional
= 0;
4871 #ifdef REGISTER_PREFIX
4876 if (! m68k_rel32_from_cmdline
)
4882 md_atof (int type
, char *litP
, int *sizeP
)
4884 return ieee_md_atof (type
, litP
, sizeP
, TRUE
);
4888 md_number_to_chars (char *buf
, valueT val
, int n
)
4890 number_to_chars_bigendian (buf
, val
, n
);
4894 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4896 offsetT val
= *valP
;
4897 addressT upper_limit
;
4898 offsetT lower_limit
;
4900 /* This is unnecessary but it convinces the native rs6000 compiler
4901 to generate the code we want. */
4902 char *buf
= fixP
->fx_frag
->fr_literal
;
4903 buf
+= fixP
->fx_where
;
4904 /* End ibm compiler workaround. */
4908 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4914 memset (buf
, 0, fixP
->fx_size
);
4915 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4917 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4918 && !S_IS_DEFINED (fixP
->fx_addsy
)
4919 && !S_IS_WEAK (fixP
->fx_addsy
))
4920 S_SET_WEAK (fixP
->fx_addsy
);
4922 switch (fixP
->fx_r_type
)
4924 case BFD_RELOC_68K_TLS_GD32
:
4925 case BFD_RELOC_68K_TLS_GD16
:
4926 case BFD_RELOC_68K_TLS_GD8
:
4927 case BFD_RELOC_68K_TLS_LDM32
:
4928 case BFD_RELOC_68K_TLS_LDM16
:
4929 case BFD_RELOC_68K_TLS_LDM8
:
4930 case BFD_RELOC_68K_TLS_LDO32
:
4931 case BFD_RELOC_68K_TLS_LDO16
:
4932 case BFD_RELOC_68K_TLS_LDO8
:
4933 case BFD_RELOC_68K_TLS_IE32
:
4934 case BFD_RELOC_68K_TLS_IE16
:
4935 case BFD_RELOC_68K_TLS_IE8
:
4936 case BFD_RELOC_68K_TLS_LE32
:
4937 case BFD_RELOC_68K_TLS_LE16
:
4938 case BFD_RELOC_68K_TLS_LE8
:
4939 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4948 #elif defined(OBJ_AOUT)
4949 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4950 if (fixP
->fx_addsy
&& S_IS_WEAK (fixP
->fx_addsy
))
4952 memset (buf
, 0, fixP
->fx_size
);
4953 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4958 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4959 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4962 switch (fixP
->fx_size
)
4964 /* The cast to offsetT below are necessary to make code
4965 correct for machines where ints are smaller than offsetT. */
4969 lower_limit
= - (offsetT
) 0x80;
4972 *buf
++ = (val
>> 8);
4974 upper_limit
= 0x7fff;
4975 lower_limit
= - (offsetT
) 0x8000;
4978 *buf
++ = (val
>> 24);
4979 *buf
++ = (val
>> 16);
4980 *buf
++ = (val
>> 8);
4982 upper_limit
= 0x7fffffff;
4983 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* Avoid constant overflow. */
4986 BAD_CASE (fixP
->fx_size
);
4989 /* Fix up a negative reloc. */
4990 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4992 fixP
->fx_addsy
= fixP
->fx_subsy
;
4993 fixP
->fx_subsy
= NULL
;
4997 /* For non-pc-relative values, it's conceivable we might get something
4998 like "0xff" for a byte field. So extend the upper part of the range
4999 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
5000 so that we can do any range checking at all. */
5001 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
5002 upper_limit
= upper_limit
* 2 + 1;
5004 if ((addressT
) val
> upper_limit
5005 && (val
> 0 || val
< lower_limit
))
5006 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5007 _("value %ld out of range"), (long)val
);
5009 /* A one byte PC-relative reloc means a short branch. We can't use
5010 a short branch with a value of 0 or -1, because those indicate
5011 different opcodes (branches with longer offsets). fixup_segment
5012 in write.c may have clobbered fx_pcrel, so we need to examine the
5015 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
5016 && fixP
->fx_size
== 1
5017 && (fixP
->fx_addsy
== NULL
5018 || S_IS_DEFINED (fixP
->fx_addsy
))
5019 && (val
== 0 || val
== -1))
5020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5021 _("invalid byte branch offset"));
5024 /* *fragP has been relaxed to its final size, and now needs to have
5025 the bytes inside it modified to conform to the new size There is UGLY
5029 md_convert_frag_1 (fragS
*fragP
)
5034 /* Address in object code of the displacement. */
5035 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
5037 /* Address in gas core of the place to store the displacement. */
5038 /* This convinces the native rs6000 compiler to generate the code we
5040 register char *buffer_address
= fragP
->fr_literal
;
5041 buffer_address
+= fragP
->fr_fix
;
5042 /* End ibm compiler workaround. */
5044 /* The displacement of the address, from current location. */
5045 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
5046 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
5048 switch (fragP
->fr_subtype
)
5050 case TAB (BRANCHBWL
, BYTE
):
5051 case TAB (BRABSJUNC
, BYTE
):
5052 case TAB (BRABSJCOND
, BYTE
):
5053 case TAB (BRANCHBW
, BYTE
):
5054 case TAB (BRANCHBWPL
, BYTE
):
5055 know (issbyte (disp
));
5057 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5058 _("short branch with zero offset: use :w"));
5059 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
5060 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
5061 fixP
->fx_pcrel_adjust
= -1;
5063 case TAB (BRANCHBWL
, SHORT
):
5064 case TAB (BRABSJUNC
, SHORT
):
5065 case TAB (BRABSJCOND
, SHORT
):
5066 case TAB (BRANCHBW
, SHORT
):
5067 case TAB (BRANCHBWPL
, SHORT
):
5068 fragP
->fr_opcode
[1] = 0x00;
5069 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5070 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5073 case TAB (BRANCHBWL
, LONG
):
5074 fragP
->fr_opcode
[1] = (char) 0xFF;
5075 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5076 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5079 case TAB (BRANCHBWPL
, LONG
):
5080 /* Here we are converting an unconditional branch into a pair of
5081 conditional branches, in order to get the range. */
5082 fragP
->fr_opcode
[0] = 0x66; /* bne */
5083 fragP
->fr_opcode
[1] = 0xFF;
5084 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5085 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5086 fixP
->fx_file
= fragP
->fr_file
;
5087 fixP
->fx_line
= fragP
->fr_line
;
5088 fragP
->fr_fix
+= 4; /* Skip first offset */
5089 buffer_address
+= 4;
5090 *buffer_address
++ = 0x67; /* beq */
5091 *buffer_address
++ = 0xff;
5092 fragP
->fr_fix
+= 2; /* Skip second branch opcode */
5093 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5094 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5097 case TAB (BRABSJUNC
, LONG
):
5098 if (fragP
->fr_opcode
[0] == 0x61) /* jbsr */
5100 if (flag_keep_pcrel
)
5101 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5102 _("Conversion of PC relative BSR to absolute JSR"));
5103 fragP
->fr_opcode
[0] = 0x4E;
5104 fragP
->fr_opcode
[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
5105 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5106 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5109 else if (fragP
->fr_opcode
[0] == 0x60) /* jbra */
5111 if (flag_keep_pcrel
)
5112 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5113 _("Conversion of PC relative branch to absolute jump"));
5114 fragP
->fr_opcode
[0] = 0x4E;
5115 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
5116 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5117 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5122 /* This cannot happen, because jbsr and jbra are the only two
5123 unconditional branches. */
5127 case TAB (BRABSJCOND
, LONG
):
5128 if (flag_keep_pcrel
)
5129 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5130 _("Conversion of PC relative conditional branch to absolute jump"));
5132 /* Only Bcc 68000 instructions can come here
5133 Change bcc into b!cc/jmp absl long. */
5134 fragP
->fr_opcode
[0] ^= 0x01; /* Invert bcc. */
5135 fragP
->fr_opcode
[1] = 0x06; /* Branch offset = 6. */
5137 /* JF: these used to be fr_opcode[2,3], but they may be in a
5138 different frag, in which case referring to them is a no-no.
5139 Only fr_opcode[0,1] are guaranteed to work. */
5140 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
5141 *buffer_address
++ = (char) 0xf9;
5142 fragP
->fr_fix
+= 2; /* Account for jmp instruction. */
5143 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5144 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5147 case TAB (FBRANCH
, SHORT
):
5148 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
5149 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5150 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5153 case TAB (FBRANCH
, LONG
):
5154 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit. */
5155 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5156 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5159 case TAB (DBCCLBR
, SHORT
):
5160 case TAB (DBCCABSJ
, SHORT
):
5161 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5162 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5165 case TAB (DBCCLBR
, LONG
):
5166 /* Only DBcc instructions can come here.
5167 Change dbcc into dbcc/bral.
5168 JF: these used to be fr_opcode[2-7], but that's wrong. */
5169 if (flag_keep_pcrel
)
5170 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5171 _("Conversion of DBcc to absolute jump"));
5173 *buffer_address
++ = 0x00; /* Branch offset = 4. */
5174 *buffer_address
++ = 0x04;
5175 *buffer_address
++ = 0x60; /* Put in bra pc+6. */
5176 *buffer_address
++ = 0x06;
5177 *buffer_address
++ = 0x60; /* Put in bral (0x60ff). */
5178 *buffer_address
++ = (char) 0xff;
5180 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
5181 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5182 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5185 case TAB (DBCCABSJ
, LONG
):
5186 /* Only DBcc instructions can come here.
5187 Change dbcc into dbcc/jmp.
5188 JF: these used to be fr_opcode[2-7], but that's wrong. */
5189 if (flag_keep_pcrel
)
5190 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5191 _("Conversion of PC relative conditional branch to absolute jump"));
5193 *buffer_address
++ = 0x00; /* Branch offset = 4. */
5194 *buffer_address
++ = 0x04;
5195 *buffer_address
++ = 0x60; /* Put in bra pc + 6. */
5196 *buffer_address
++ = 0x06;
5197 *buffer_address
++ = 0x4e; /* Put in jmp long (0x4ef9). */
5198 *buffer_address
++ = (char) 0xf9;
5200 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
5201 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5202 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5205 case TAB (PCREL1632
, SHORT
):
5206 fragP
->fr_opcode
[1] &= ~0x3F;
5207 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
5208 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
5209 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5212 case TAB (PCREL1632
, LONG
):
5213 /* Already set to mode 7.3; this indicates: PC indirect with
5214 suppressed index, 32-bit displacement. */
5215 *buffer_address
++ = 0x01;
5216 *buffer_address
++ = 0x70;
5218 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
5219 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5220 fixP
->fx_pcrel_adjust
= 2;
5223 case TAB (PCINDEX
, BYTE
):
5224 gas_assert (fragP
->fr_fix
>= 2);
5225 buffer_address
[-2] &= ~1;
5226 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
5227 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
5228 fixP
->fx_pcrel_adjust
= 1;
5230 case TAB (PCINDEX
, SHORT
):
5231 gas_assert (fragP
->fr_fix
>= 2);
5232 buffer_address
[-2] |= 0x1;
5233 buffer_address
[-1] = 0x20;
5234 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
5235 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5236 fixP
->fx_pcrel_adjust
= 2;
5239 case TAB (PCINDEX
, LONG
):
5240 gas_assert (fragP
->fr_fix
>= 2);
5241 buffer_address
[-2] |= 0x1;
5242 buffer_address
[-1] = 0x30;
5243 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
5244 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5245 fixP
->fx_pcrel_adjust
= 2;
5248 case TAB (ABSTOPCREL
, SHORT
):
5249 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5250 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5253 case TAB (ABSTOPCREL
, LONG
):
5254 if (flag_keep_pcrel
)
5255 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5256 _("Conversion of PC relative displacement to absolute"));
5257 /* The thing to do here is force it to ABSOLUTE LONG, since
5258 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5259 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
5261 fragP
->fr_opcode
[1] &= ~0x3F;
5262 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
5263 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5264 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5270 fixP
->fx_file
= fragP
->fr_file
;
5271 fixP
->fx_line
= fragP
->fr_line
;
5276 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
5277 segT sec ATTRIBUTE_UNUSED
,
5280 md_convert_frag_1 (fragP
);
5283 /* Force truly undefined symbols to their maximum size, and generally set up
5284 the frag list to be relaxed
5287 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
5289 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5290 switch (fragP
->fr_subtype
)
5292 case TAB (BRANCHBWL
, SZ_UNDEF
):
5293 case TAB (BRANCHBWPL
, SZ_UNDEF
):
5294 case TAB (BRABSJUNC
, SZ_UNDEF
):
5295 case TAB (BRABSJCOND
, SZ_UNDEF
):
5297 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5298 && relaxable_symbol (fragP
->fr_symbol
))
5300 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
5302 else if (flag_short_refs
)
5304 /* Symbol is undefined and we want short ref. */
5305 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5309 /* Symbol is still undefined. Make it LONG. */
5310 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
5315 case TAB (BRANCHBW
, SZ_UNDEF
):
5317 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5318 && relaxable_symbol (fragP
->fr_symbol
))
5320 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
5324 /* Symbol is undefined and we don't have long branches. */
5325 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5330 case TAB (FBRANCH
, SZ_UNDEF
):
5331 case TAB (DBCCLBR
, SZ_UNDEF
):
5332 case TAB (DBCCABSJ
, SZ_UNDEF
):
5333 case TAB (PCREL1632
, SZ_UNDEF
):
5335 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5336 && relaxable_symbol (fragP
->fr_symbol
))
5339 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5343 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
5348 case TAB (PCINDEX
, SZ_UNDEF
):
5349 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5350 && relaxable_symbol (fragP
->fr_symbol
)))
5352 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
5356 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
5360 case TAB (ABSTOPCREL
, SZ_UNDEF
):
5362 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5363 && relaxable_symbol (fragP
->fr_symbol
)))
5365 fragP
->fr_subtype
= TAB (ABSTOPCREL
, SHORT
);
5369 fragP
->fr_subtype
= TAB (ABSTOPCREL
, LONG
);
5378 /* Now that SZ_UNDEF are taken care of, check others. */
5379 switch (fragP
->fr_subtype
)
5381 case TAB (BRANCHBWL
, BYTE
):
5382 case TAB (BRABSJUNC
, BYTE
):
5383 case TAB (BRABSJCOND
, BYTE
):
5384 case TAB (BRANCHBW
, BYTE
):
5385 /* We can't do a short jump to the next instruction, so in that
5386 case we force word mode. If the symbol is at the start of a
5387 frag, and it is the next frag with any data in it (usually
5388 this is just the next frag, but assembler listings may
5389 introduce empty frags), we must use word mode. */
5390 if (fragP
->fr_symbol
)
5394 sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
5395 if (S_GET_VALUE (fragP
->fr_symbol
) == sym_frag
->fr_address
)
5399 for (l
= fragP
->fr_next
; l
&& l
!= sym_frag
; l
= l
->fr_next
)
5403 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5410 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5413 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5414 /* the bit-field entries in the relocation_info struct plays hell
5415 with the byte-order problems of cross-assembly. So as a hack,
5416 I added this mach. dependent ri twiddler. Ugly, but it gets
5418 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5419 are symbolnum, most sig. byte first. Last byte is broken up with
5420 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5421 nibble as nuthin. (on Sun 3 at least) */
5422 /* Translate the internal relocation information into target-specific
5426 md_ri_to_chars (char *the_bytes
, struct reloc_info_generic
*ri
)
5429 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
5430 /* Now the fun stuff. */
5431 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
5432 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
5433 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
5434 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80)
5435 | ((ri
->r_length
<< 5) & 0x60)
5436 | ((ri
->r_extern
<< 4) & 0x10));
5441 #endif /* OBJ_AOUT or OBJ_BOUT */
5443 #ifndef WORKING_DOT_WORD
5444 int md_short_jump_size
= 4;
5445 int md_long_jump_size
= 6;
5448 md_create_short_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5449 fragS
*frag ATTRIBUTE_UNUSED
,
5450 symbolS
*to_symbol ATTRIBUTE_UNUSED
)
5454 offset
= to_addr
- (from_addr
+ 2);
5456 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
5457 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
5461 md_create_long_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5462 fragS
*frag
, symbolS
*to_symbol
)
5466 if (!HAVE_LONG_BRANCH (current_architecture
))
5468 if (flag_keep_pcrel
)
5469 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5470 offset
= to_addr
- S_GET_VALUE (to_symbol
);
5471 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
5472 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5473 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
5478 offset
= to_addr
- (from_addr
+ 2);
5479 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
5480 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5486 /* Different values of OK tell what its OK to return. Things that
5487 aren't OK are an error (what a shock, no?)
5490 10: Absolute 1:8 only
5491 20: Absolute 0:7 only
5492 30: absolute 0:15 only
5493 40: Absolute 0:31 only
5494 50: absolute 0:127 only
5495 55: absolute -64:63 only
5496 60: absolute -128:127 only
5497 65: absolute 0:511 only
5498 70: absolute 0:4095 only
5499 80: absolute -1, 1:7 only
5503 get_num (struct m68k_exp
*exp
, int ok
)
5505 if (exp
->exp
.X_op
== O_absent
)
5507 /* Do the same thing the VAX asm does. */
5508 op (exp
) = O_constant
;
5514 as_warn (_("expression out of range: defaulting to 1"));
5518 else if (exp
->exp
.X_op
== O_constant
)
5523 if ((valueT
) TRUNC (offs (exp
)) - 1 > 7)
5525 as_warn (_("expression out of range: defaulting to 1"));
5530 if ((valueT
) TRUNC (offs (exp
)) > 7)
5534 if ((valueT
) TRUNC (offs (exp
)) > 15)
5538 if ((valueT
) TRUNC (offs (exp
)) > 32)
5542 if ((valueT
) TRUNC (offs (exp
)) > 127)
5546 if ((valueT
) SEXT (offs (exp
)) + 64 > 127)
5550 if ((valueT
) SEXT (offs (exp
)) + 128 > 255)
5554 if ((valueT
) TRUNC (offs (exp
)) > 511)
5558 if ((valueT
) TRUNC (offs (exp
)) > 4095)
5561 as_warn (_("expression out of range: defaulting to 0"));
5566 if ((valueT
) TRUNC (offs (exp
)) != 0xffffffff
5567 && (valueT
) TRUNC (offs (exp
)) - 1 > 6)
5569 as_warn (_("expression out of range: defaulting to 1"));
5577 else if (exp
->exp
.X_op
== O_big
)
5579 if (offs (exp
) <= 0 /* flonum. */
5580 && (ok
== 90 /* no bignums */
5581 || (ok
> 10 /* Small-int ranges including 0 ok. */
5582 /* If we have a flonum zero, a zero integer should
5583 do as well (e.g., in moveq). */
5584 && generic_floating_point_number
.exponent
== 0
5585 && generic_floating_point_number
.low
[0] == 0)))
5587 /* HACK! Turn it into a long. */
5588 LITTLENUM_TYPE words
[6];
5590 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
5591 op (exp
) = O_constant
;
5594 offs (exp
) = words
[1] | (words
[0] << 16);
5598 op (exp
) = O_constant
;
5601 offs (exp
) = (ok
== 10) ? 1 : 0;
5602 as_warn (_("Can't deal with expression; defaulting to %ld"),
5608 if (ok
>= 10 && ok
<= 80)
5610 op (exp
) = O_constant
;
5613 offs (exp
) = (ok
== 10) ? 1 : 0;
5614 as_warn (_("Can't deal with expression; defaulting to %ld"),
5619 if (exp
->size
!= SIZE_UNSPEC
)
5627 if (!isbyte (offs (exp
)))
5628 as_warn (_("expression doesn't fit in BYTE"));
5631 if (!isword (offs (exp
)))
5632 as_warn (_("expression doesn't fit in WORD"));
5640 /* These are the back-ends for the various machine dependent pseudo-ops. */
5643 s_data1 (int ignore ATTRIBUTE_UNUSED
)
5645 subseg_set (data_section
, 1);
5646 demand_empty_rest_of_line ();
5650 s_data2 (int ignore ATTRIBUTE_UNUSED
)
5652 subseg_set (data_section
, 2);
5653 demand_empty_rest_of_line ();
5657 s_bss (int ignore ATTRIBUTE_UNUSED
)
5659 /* We don't support putting frags in the BSS segment, we fake it
5660 by marking in_bss, then looking at s_skip for clues. */
5662 subseg_set (bss_section
, 0);
5663 demand_empty_rest_of_line ();
5667 s_even (int ignore ATTRIBUTE_UNUSED
)
5670 register long temp_fill
;
5672 temp
= 1; /* JF should be 2? */
5673 temp_fill
= get_absolute_expression ();
5674 if (!need_pass_2
) /* Never make frag if expect extra pass. */
5675 frag_align (temp
, (int) temp_fill
, 0);
5676 demand_empty_rest_of_line ();
5677 record_alignment (now_seg
, temp
);
5681 s_proc (int ignore ATTRIBUTE_UNUSED
)
5683 demand_empty_rest_of_line ();
5686 /* Pseudo-ops handled for MRI compatibility. */
5688 /* This function returns non-zero if the argument is a conditional
5689 pseudo-op. This is called when checking whether a pending
5690 alignment is needed. */
5693 m68k_conditional_pseudoop (pseudo_typeS
*pop
)
5695 return (pop
->poc_handler
== s_mri_if
5696 || pop
->poc_handler
== s_mri_else
);
5699 /* Handle an MRI style chip specification. */
5708 s
= input_line_pointer
;
5709 /* We can't use get_symbol_end since the processor names are not proper
5711 while (is_part_of_name (c
= *input_line_pointer
++))
5713 *--input_line_pointer
= 0;
5714 for (i
= 0; m68k_cpus
[i
].name
; i
++)
5715 if (strcasecmp (s
, m68k_cpus
[i
].name
) == 0)
5717 if (!m68k_cpus
[i
].name
)
5719 as_bad (_("%s: unrecognized processor name"), s
);
5720 *input_line_pointer
= c
;
5721 ignore_rest_of_line ();
5724 *input_line_pointer
= c
;
5726 if (*input_line_pointer
== '/')
5727 current_architecture
= 0;
5729 current_architecture
&= m68881
| m68851
;
5730 current_architecture
|= m68k_cpus
[i
].arch
& ~(m68881
| m68851
);
5731 control_regs
= m68k_cpus
[i
].control_regs
;
5733 while (*input_line_pointer
== '/')
5735 ++input_line_pointer
;
5736 s
= input_line_pointer
;
5737 /* We can't use get_symbol_end since the processor names are not
5739 while (is_part_of_name (c
= *input_line_pointer
++))
5741 *--input_line_pointer
= 0;
5742 if (strcmp (s
, "68881") == 0)
5743 current_architecture
|= m68881
;
5744 else if (strcmp (s
, "68851") == 0)
5745 current_architecture
|= m68851
;
5746 *input_line_pointer
= c
;
5750 /* The MRI CHIP pseudo-op. */
5753 s_chip (int ignore ATTRIBUTE_UNUSED
)
5759 stop
= mri_comment_field (&stopc
);
5762 mri_comment_end (stop
, stopc
);
5763 demand_empty_rest_of_line ();
5766 /* The MRI FOPT pseudo-op. */
5769 s_fopt (int ignore ATTRIBUTE_UNUSED
)
5773 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
5777 input_line_pointer
+= 3;
5778 temp
= get_absolute_expression ();
5779 if (temp
< 0 || temp
> 7)
5780 as_bad (_("bad coprocessor id"));
5782 m68k_float_copnum
= COP0
+ temp
;
5786 as_bad (_("unrecognized fopt option"));
5787 ignore_rest_of_line ();
5791 demand_empty_rest_of_line ();
5794 /* The structure used to handle the MRI OPT pseudo-op. */
5798 /* The name of the option. */
5801 /* If this is not NULL, just call this function. The first argument
5802 is the ARG field of this structure, the second argument is
5803 whether the option was negated. */
5804 void (*pfn
) (int arg
, int on
);
5806 /* If this is not NULL, and the PFN field is NULL, set the variable
5807 this points to. Set it to the ARG field if the option was not
5808 negated, and the NOTARG field otherwise. */
5811 /* The value to pass to PFN or to assign to *PVAR. */
5814 /* The value to assign to *PVAR if the option is negated. If PFN is
5815 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5816 the option may not be negated. */
5820 /* The table used to handle the MRI OPT pseudo-op. */
5822 static void skip_to_comma (int, int);
5823 static void opt_nest (int, int);
5824 static void opt_chip (int, int);
5825 static void opt_list (int, int);
5826 static void opt_list_symbols (int, int);
5828 static const struct opt_action opt_table
[] =
5830 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5832 /* We do relaxing, so there is little use for these options. */
5833 { "b", 0, 0, 0, 0 },
5834 { "brs", 0, 0, 0, 0 },
5835 { "brb", 0, 0, 0, 0 },
5836 { "brl", 0, 0, 0, 0 },
5837 { "brw", 0, 0, 0, 0 },
5839 { "c", 0, 0, 0, 0 },
5840 { "cex", 0, 0, 0, 0 },
5841 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5842 { "cl", 0, 0, 0, 0 },
5843 { "cre", 0, 0, 0, 0 },
5844 { "d", 0, &flag_keep_locals
, 1, 0 },
5845 { "e", 0, 0, 0, 0 },
5846 { "f", 0, &flag_short_refs
, 1, 0 },
5847 { "frs", 0, &flag_short_refs
, 1, 0 },
5848 { "frl", 0, &flag_short_refs
, 0, 1 },
5849 { "g", 0, 0, 0, 0 },
5850 { "i", 0, 0, 0, 0 },
5851 { "m", 0, 0, 0, 0 },
5852 { "mex", 0, 0, 0, 0 },
5853 { "mc", 0, 0, 0, 0 },
5854 { "md", 0, 0, 0, 0 },
5855 { "nest", opt_nest
, 0, 0, 0 },
5856 { "next", skip_to_comma
, 0, 0, 0 },
5857 { "o", 0, 0, 0, 0 },
5858 { "old", 0, 0, 0, 0 },
5859 { "op", skip_to_comma
, 0, 0, 0 },
5860 { "pco", 0, 0, 0, 0 },
5861 { "p", opt_chip
, 0, 0, 0 },
5862 { "pcr", 0, 0, 0, 0 },
5863 { "pcs", 0, 0, 0, 0 },
5864 { "r", 0, 0, 0, 0 },
5865 { "quick", 0, &m68k_quick
, 1, 0 },
5866 { "rel32", 0, &m68k_rel32
, 1, 0 },
5867 { "s", opt_list
, 0, 0, 0 },
5868 { "t", opt_list_symbols
, 0, 0, 0 },
5869 { "w", 0, &flag_no_warnings
, 0, 1 },
5873 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5875 /* The MRI OPT pseudo-op. */
5878 s_opt (int ignore ATTRIBUTE_UNUSED
)
5886 const struct opt_action
*o
;
5891 if (*input_line_pointer
== '-')
5893 ++input_line_pointer
;
5896 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5898 input_line_pointer
+= 2;
5902 s
= input_line_pointer
;
5903 c
= get_symbol_end ();
5905 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5907 if (strcasecmp (s
, o
->name
) == 0)
5911 /* Restore input_line_pointer now in case the option
5913 *input_line_pointer
= c
;
5914 (*o
->pfn
) (o
->arg
, t
);
5916 else if (o
->pvar
!= NULL
)
5918 if (! t
&& o
->arg
== o
->notarg
)
5919 as_bad (_("option `%s' may not be negated"), s
);
5920 *input_line_pointer
= c
;
5921 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5924 *input_line_pointer
= c
;
5930 as_bad (_("option `%s' not recognized"), s
);
5931 *input_line_pointer
= c
;
5934 while (*input_line_pointer
++ == ',');
5936 /* Move back to terminating character. */
5937 --input_line_pointer
;
5938 demand_empty_rest_of_line ();
5941 /* Skip ahead to a comma. This is used for OPT options which we do
5942 not support and which take arguments. */
5945 skip_to_comma (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5947 while (*input_line_pointer
!= ','
5948 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5949 ++input_line_pointer
;
5952 /* Handle the OPT NEST=depth option. */
5955 opt_nest (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5957 if (*input_line_pointer
!= '=')
5959 as_bad (_("bad format of OPT NEST=depth"));
5963 ++input_line_pointer
;
5964 max_macro_nest
= get_absolute_expression ();
5967 /* Handle the OPT P=chip option. */
5970 opt_chip (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5972 if (*input_line_pointer
!= '=')
5974 /* This is just OPT P, which we do not support. */
5978 ++input_line_pointer
;
5982 /* Handle the OPT S option. */
5985 opt_list (int arg ATTRIBUTE_UNUSED
, int on
)
5990 /* Handle the OPT T option. */
5993 opt_list_symbols (int arg ATTRIBUTE_UNUSED
, int on
)
5996 listing
|= LISTING_SYMBOLS
;
5998 listing
&= ~LISTING_SYMBOLS
;
6001 /* Handle the MRI REG pseudo-op. */
6004 s_reg (int ignore ATTRIBUTE_UNUSED
)
6013 if (line_label
== NULL
)
6015 as_bad (_("missing label"));
6016 ignore_rest_of_line ();
6021 stop
= mri_comment_field (&stopc
);
6025 s
= input_line_pointer
;
6026 while (ISALNUM (*input_line_pointer
)
6027 #ifdef REGISTER_PREFIX
6028 || *input_line_pointer
== REGISTER_PREFIX
6030 || *input_line_pointer
== '/'
6031 || *input_line_pointer
== '-')
6032 ++input_line_pointer
;
6033 c
= *input_line_pointer
;
6034 *input_line_pointer
= '\0';
6036 if (m68k_ip_op (s
, &rop
) != 0)
6038 if (rop
.error
== NULL
)
6039 as_bad (_("bad register list"));
6041 as_bad (_("bad register list: %s"), rop
.error
);
6042 *input_line_pointer
= c
;
6043 ignore_rest_of_line ();
6047 *input_line_pointer
= c
;
6049 if (rop
.mode
== REGLST
)
6051 else if (rop
.mode
== DREG
)
6052 mask
= 1 << (rop
.reg
- DATA0
);
6053 else if (rop
.mode
== AREG
)
6054 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
6055 else if (rop
.mode
== FPREG
)
6056 mask
= 1 << (rop
.reg
- FP0
+ 16);
6057 else if (rop
.mode
== CONTROL
6060 else if (rop
.mode
== CONTROL
6063 else if (rop
.mode
== CONTROL
6068 as_bad (_("bad register list"));
6069 ignore_rest_of_line ();
6073 S_SET_SEGMENT (line_label
, reg_section
);
6074 S_SET_VALUE (line_label
, ~mask
);
6075 symbol_set_frag (line_label
, &zero_address_frag
);
6078 mri_comment_end (stop
, stopc
);
6080 demand_empty_rest_of_line ();
6083 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
6087 struct save_opts
*next
;
6089 int symbols_case_sensitive
;
6093 const enum m68k_register
*control_regs
;
6098 /* FIXME: We don't save OPT S. */
6101 /* This variable holds the stack of saved options. */
6103 static struct save_opts
*save_stack
;
6105 /* The MRI SAVE pseudo-op. */
6108 s_save (int ignore ATTRIBUTE_UNUSED
)
6110 struct save_opts
*s
;
6112 s
= (struct save_opts
*) xmalloc (sizeof (struct save_opts
));
6113 s
->abspcadd
= m68k_abspcadd
;
6114 s
->symbols_case_sensitive
= symbols_case_sensitive
;
6115 s
->keep_locals
= flag_keep_locals
;
6116 s
->short_refs
= flag_short_refs
;
6117 s
->architecture
= current_architecture
;
6118 s
->control_regs
= control_regs
;
6119 s
->quick
= m68k_quick
;
6120 s
->rel32
= m68k_rel32
;
6121 s
->listing
= listing
;
6122 s
->no_warnings
= flag_no_warnings
;
6124 s
->next
= save_stack
;
6127 demand_empty_rest_of_line ();
6130 /* The MRI RESTORE pseudo-op. */
6133 s_restore (int ignore ATTRIBUTE_UNUSED
)
6135 struct save_opts
*s
;
6137 if (save_stack
== NULL
)
6139 as_bad (_("restore without save"));
6140 ignore_rest_of_line ();
6145 save_stack
= s
->next
;
6147 m68k_abspcadd
= s
->abspcadd
;
6148 symbols_case_sensitive
= s
->symbols_case_sensitive
;
6149 flag_keep_locals
= s
->keep_locals
;
6150 flag_short_refs
= s
->short_refs
;
6151 current_architecture
= s
->architecture
;
6152 control_regs
= s
->control_regs
;
6153 m68k_quick
= s
->quick
;
6154 m68k_rel32
= s
->rel32
;
6155 listing
= s
->listing
;
6156 flag_no_warnings
= s
->no_warnings
;
6160 demand_empty_rest_of_line ();
6163 /* Types of MRI structured control directives. */
6165 enum mri_control_type
6173 /* This structure is used to stack the MRI structured control
6176 struct mri_control_info
6178 /* The directive within which this one is enclosed. */
6179 struct mri_control_info
*outer
;
6181 /* The type of directive. */
6182 enum mri_control_type type
;
6184 /* Whether an ELSE has been in an IF. */
6187 /* The add or sub statement at the end of a FOR. */
6190 /* The label of the top of a FOR or REPEAT loop. */
6193 /* The label to jump to for the next iteration, or the else
6194 expression of a conditional. */
6197 /* The label to jump to to break out of the loop, or the label past
6198 the end of a conditional. */
6202 /* The stack of MRI structured control directives. */
6204 static struct mri_control_info
*mri_control_stack
;
6206 /* The current MRI structured control directive index number, used to
6207 generate label names. */
6209 static int mri_control_index
;
6211 /* Assemble an instruction for an MRI structured control directive. */
6214 mri_assemble (char *str
)
6218 /* md_assemble expects the opcode to be in lower case. */
6219 for (s
= str
; *s
!= ' ' && *s
!= '\0'; s
++)
6225 /* Generate a new MRI label structured control directive label name. */
6228 mri_control_label (void)
6232 n
= (char *) xmalloc (20);
6233 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
6234 ++mri_control_index
;
6238 /* Create a new MRI structured control directive. */
6240 static struct mri_control_info
*
6241 push_mri_control (enum mri_control_type type
)
6243 struct mri_control_info
*n
;
6245 n
= (struct mri_control_info
*) xmalloc (sizeof (struct mri_control_info
));
6249 if (type
== mri_if
|| type
== mri_while
)
6252 n
->top
= mri_control_label ();
6253 n
->next
= mri_control_label ();
6254 n
->bottom
= mri_control_label ();
6256 n
->outer
= mri_control_stack
;
6257 mri_control_stack
= n
;
6262 /* Pop off the stack of MRI structured control directives. */
6265 pop_mri_control (void)
6267 struct mri_control_info
*n
;
6269 n
= mri_control_stack
;
6270 mri_control_stack
= n
->outer
;
6278 /* Recognize a condition code in an MRI structured control expression. */
6281 parse_mri_condition (int *pcc
)
6285 know (*input_line_pointer
== '<');
6287 ++input_line_pointer
;
6288 c1
= *input_line_pointer
++;
6289 c2
= *input_line_pointer
++;
6291 if (*input_line_pointer
!= '>')
6293 as_bad (_("syntax error in structured control directive"));
6297 ++input_line_pointer
;
6303 *pcc
= (c1
<< 8) | c2
;
6308 /* Parse a single operand in an MRI structured control expression. */
6311 parse_mri_control_operand (int *pcc
, char **leftstart
, char **leftstop
,
6312 char **rightstart
, char **rightstop
)
6324 if (*input_line_pointer
== '<')
6326 /* It's just a condition code. */
6327 return parse_mri_condition (pcc
);
6330 /* Look ahead for the condition code. */
6331 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
6333 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
6338 as_bad (_("missing condition code in structured control directive"));
6342 *leftstart
= input_line_pointer
;
6344 if (*leftstop
> *leftstart
6345 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
6348 input_line_pointer
= s
;
6349 if (! parse_mri_condition (pcc
))
6352 /* Look ahead for AND or OR or end of line. */
6353 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
6355 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6356 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6358 if ((s
== input_line_pointer
6361 && ((strncasecmp (s
, "AND", 3) == 0
6362 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
6363 || (strncasecmp (s
, "OR", 2) == 0
6364 && (s
[2] == '.' || ! is_part_of_name (s
[2])))))
6368 *rightstart
= input_line_pointer
;
6370 if (*rightstop
> *rightstart
6371 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
6374 input_line_pointer
= s
;
6379 #define MCC(b1, b2) (((b1) << 8) | (b2))
6381 /* Swap the sense of a condition. This changes the condition so that
6382 it generates the same result when the operands are swapped. */
6385 swap_mri_condition (int cc
)
6389 case MCC ('h', 'i'): return MCC ('c', 's');
6390 case MCC ('l', 's'): return MCC ('c', 'c');
6391 /* <HS> is an alias for <CC>. */
6392 case MCC ('h', 's'):
6393 case MCC ('c', 'c'): return MCC ('l', 's');
6394 /* <LO> is an alias for <CS>. */
6395 case MCC ('l', 'o'):
6396 case MCC ('c', 's'): return MCC ('h', 'i');
6397 case MCC ('p', 'l'): return MCC ('m', 'i');
6398 case MCC ('m', 'i'): return MCC ('p', 'l');
6399 case MCC ('g', 'e'): return MCC ('l', 'e');
6400 case MCC ('l', 't'): return MCC ('g', 't');
6401 case MCC ('g', 't'): return MCC ('l', 't');
6402 case MCC ('l', 'e'): return MCC ('g', 'e');
6403 /* Issue a warning for conditions we can not swap. */
6404 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6405 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
6406 case MCC ('v', 'c'):
6407 case MCC ('v', 's'):
6409 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6410 (char) (cc
>> 8), (char) (cc
));
6416 /* Reverse the sense of a condition. */
6419 reverse_mri_condition (int cc
)
6423 case MCC ('h', 'i'): return MCC ('l', 's');
6424 case MCC ('l', 's'): return MCC ('h', 'i');
6425 /* <HS> is an alias for <CC> */
6426 case MCC ('h', 's'): return MCC ('l', 'o');
6427 case MCC ('c', 'c'): return MCC ('c', 's');
6428 /* <LO> is an alias for <CS> */
6429 case MCC ('l', 'o'): return MCC ('h', 's');
6430 case MCC ('c', 's'): return MCC ('c', 'c');
6431 case MCC ('n', 'e'): return MCC ('e', 'q');
6432 case MCC ('e', 'q'): return MCC ('n', 'e');
6433 case MCC ('v', 'c'): return MCC ('v', 's');
6434 case MCC ('v', 's'): return MCC ('v', 'c');
6435 case MCC ('p', 'l'): return MCC ('m', 'i');
6436 case MCC ('m', 'i'): return MCC ('p', 'l');
6437 case MCC ('g', 'e'): return MCC ('l', 't');
6438 case MCC ('l', 't'): return MCC ('g', 'e');
6439 case MCC ('g', 't'): return MCC ('l', 'e');
6440 case MCC ('l', 'e'): return MCC ('g', 't');
6445 /* Build an MRI structured control expression. This generates test
6446 and branch instructions. It goes to TRUELAB if the condition is
6447 true, and to FALSELAB if the condition is false. Exactly one of
6448 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6449 is the size qualifier for the expression. EXTENT is the size to
6450 use for the branch. */
6453 build_mri_control_operand (int qual
, int cc
, char *leftstart
, char *leftstop
,
6454 char *rightstart
, char *rightstop
,
6455 const char *truelab
, const char *falselab
,
6461 if (leftstart
!= NULL
)
6463 struct m68k_op leftop
, rightop
;
6466 /* Swap the compare operands, if necessary, to produce a legal
6467 m68k compare instruction. Comparing a register operand with
6468 a non-register operand requires the register to be on the
6469 right (cmp, cmpa). Comparing an immediate value with
6470 anything requires the immediate value to be on the left
6475 (void) m68k_ip_op (leftstart
, &leftop
);
6480 (void) m68k_ip_op (rightstart
, &rightop
);
6483 if (rightop
.mode
== IMMED
6484 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
6485 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
6489 /* Correct conditional handling:
6490 if #1 <lt> d0 then ;means if (1 < d0)
6496 cmp #1,d0 if we do *not* swap the operands
6497 bgt true we need the swapped condition!
6504 leftstart
= rightstart
;
6507 leftstop
= rightstop
;
6512 cc
= swap_mri_condition (cc
);
6516 if (truelab
== NULL
)
6518 cc
= reverse_mri_condition (cc
);
6522 if (leftstart
!= NULL
)
6524 buf
= (char *) xmalloc (20
6525 + (leftstop
- leftstart
)
6526 + (rightstop
- rightstart
));
6532 *s
++ = TOLOWER (qual
);
6534 memcpy (s
, leftstart
, leftstop
- leftstart
);
6535 s
+= leftstop
- leftstart
;
6537 memcpy (s
, rightstart
, rightstop
- rightstart
);
6538 s
+= rightstop
- rightstart
;
6544 buf
= (char *) xmalloc (20 + strlen (truelab
));
6550 *s
++ = TOLOWER (extent
);
6552 strcpy (s
, truelab
);
6557 /* Parse an MRI structured control expression. This generates test
6558 and branch instructions. STOP is where the expression ends. It
6559 goes to TRUELAB if the condition is true, and to FALSELAB if the
6560 condition is false. Exactly one of TRUELAB and FALSELAB will be
6561 NULL, meaning to fall through. QUAL is the size qualifier for the
6562 expression. EXTENT is the size to use for the branch. */
6565 parse_mri_control_expression (char *stop
, int qual
, const char *truelab
,
6566 const char *falselab
, int extent
)
6578 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6579 &rightstart
, &rightstop
))
6585 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
6589 if (falselab
!= NULL
)
6592 flab
= mri_control_label ();
6594 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6595 rightstop
, (const char *) NULL
, flab
, extent
);
6597 input_line_pointer
+= 3;
6598 if (*input_line_pointer
!= '.'
6599 || input_line_pointer
[1] == '\0')
6603 qual
= input_line_pointer
[1];
6604 input_line_pointer
+= 2;
6607 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6608 &rightstart
, &rightstop
))
6614 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6615 rightstop
, truelab
, falselab
, extent
);
6617 if (falselab
== NULL
)
6620 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
6624 if (truelab
!= NULL
)
6627 tlab
= mri_control_label ();
6629 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6630 rightstop
, tlab
, (const char *) NULL
, extent
);
6632 input_line_pointer
+= 2;
6633 if (*input_line_pointer
!= '.'
6634 || input_line_pointer
[1] == '\0')
6638 qual
= input_line_pointer
[1];
6639 input_line_pointer
+= 2;
6642 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6643 &rightstart
, &rightstop
))
6649 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6650 rightstop
, truelab
, falselab
, extent
);
6652 if (truelab
== NULL
)
6657 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6658 rightstop
, truelab
, falselab
, extent
);
6662 if (input_line_pointer
!= stop
)
6663 as_bad (_("syntax error in structured control directive"));
6666 /* Handle the MRI IF pseudo-op. This may be a structured control
6667 directive, or it may be a regular assembler conditional, depending
6675 struct mri_control_info
*n
;
6677 /* A structured control directive must end with THEN with an
6678 optional qualifier. */
6679 s
= input_line_pointer
;
6680 /* We only accept '*' as introduction of comments if preceded by white space
6681 or at first column of a line (I think this can't actually happen here?)
6682 This is important when assembling:
6683 if d0 <ne> 12(a0,d0*2) then
6684 if d0 <ne> #CONST*20 then. */
6685 while (! (is_end_of_line
[(unsigned char) *s
]
6688 && (s
== input_line_pointer
6690 || *(s
-1) == '\t'))))
6693 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
6696 if (s
- input_line_pointer
> 1
6700 if (s
- input_line_pointer
< 3
6701 || strncasecmp (s
- 3, "THEN", 4) != 0)
6705 as_bad (_("missing then"));
6706 ignore_rest_of_line ();
6710 /* It's a conditional. */
6715 /* Since this might be a conditional if, this pseudo-op will be
6716 called even if we are supported to be ignoring input. Double
6717 check now. Clobber *input_line_pointer so that ignore_input
6718 thinks that this is not a special pseudo-op. */
6719 c
= *input_line_pointer
;
6720 *input_line_pointer
= 0;
6721 if (ignore_input ())
6723 *input_line_pointer
= c
;
6724 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6725 ++input_line_pointer
;
6726 demand_empty_rest_of_line ();
6729 *input_line_pointer
= c
;
6731 n
= push_mri_control (mri_if
);
6733 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
6734 n
->next
, s
[1] == '.' ? s
[2] : '\0');
6737 input_line_pointer
= s
+ 3;
6739 input_line_pointer
= s
+ 1;
6743 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6744 ++input_line_pointer
;
6747 demand_empty_rest_of_line ();
6750 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6751 structured IF, associate the ELSE with the IF. Otherwise, assume
6752 it is a conditional else. */
6755 s_mri_else (int qual
)
6762 && (mri_control_stack
== NULL
6763 || mri_control_stack
->type
!= mri_if
6764 || mri_control_stack
->else_seen
))
6770 c
= *input_line_pointer
;
6771 *input_line_pointer
= 0;
6772 if (ignore_input ())
6774 *input_line_pointer
= c
;
6775 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6776 ++input_line_pointer
;
6777 demand_empty_rest_of_line ();
6780 *input_line_pointer
= c
;
6782 if (mri_control_stack
== NULL
6783 || mri_control_stack
->type
!= mri_if
6784 || mri_control_stack
->else_seen
)
6786 as_bad (_("else without matching if"));
6787 ignore_rest_of_line ();
6791 mri_control_stack
->else_seen
= 1;
6793 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->bottom
));
6794 q
[0] = TOLOWER (qual
);
6796 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6800 colon (mri_control_stack
->next
);
6804 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6805 ++input_line_pointer
;
6808 demand_empty_rest_of_line ();
6811 /* Handle the MRI ENDI pseudo-op. */
6814 s_mri_endi (int ignore ATTRIBUTE_UNUSED
)
6816 if (mri_control_stack
== NULL
6817 || mri_control_stack
->type
!= mri_if
)
6819 as_bad (_("endi without matching if"));
6820 ignore_rest_of_line ();
6824 /* ignore_input will not return true for ENDI, so we don't need to
6825 worry about checking it again here. */
6827 if (! mri_control_stack
->else_seen
)
6828 colon (mri_control_stack
->next
);
6829 colon (mri_control_stack
->bottom
);
6835 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6836 ++input_line_pointer
;
6839 demand_empty_rest_of_line ();
6842 /* Handle the MRI BREAK pseudo-op. */
6845 s_mri_break (int extent
)
6847 struct mri_control_info
*n
;
6851 n
= mri_control_stack
;
6853 && n
->type
!= mri_for
6854 && n
->type
!= mri_repeat
6855 && n
->type
!= mri_while
)
6859 as_bad (_("break outside of structured loop"));
6860 ignore_rest_of_line ();
6864 buf
= (char *) xmalloc (20 + strlen (n
->bottom
));
6865 ex
[0] = TOLOWER (extent
);
6867 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6873 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6874 ++input_line_pointer
;
6877 demand_empty_rest_of_line ();
6880 /* Handle the MRI NEXT pseudo-op. */
6883 s_mri_next (int extent
)
6885 struct mri_control_info
*n
;
6889 n
= mri_control_stack
;
6891 && n
->type
!= mri_for
6892 && n
->type
!= mri_repeat
6893 && n
->type
!= mri_while
)
6897 as_bad (_("next outside of structured loop"));
6898 ignore_rest_of_line ();
6902 buf
= (char *) xmalloc (20 + strlen (n
->next
));
6903 ex
[0] = TOLOWER (extent
);
6905 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6911 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6912 ++input_line_pointer
;
6915 demand_empty_rest_of_line ();
6918 /* Handle the MRI FOR pseudo-op. */
6921 s_mri_for (int qual
)
6923 const char *varstart
, *varstop
;
6924 const char *initstart
, *initstop
;
6925 const char *endstart
, *endstop
;
6926 const char *bystart
, *bystop
;
6930 struct mri_control_info
*n
;
6936 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6940 varstart
= input_line_pointer
;
6942 /* Look for the '='. */
6943 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6944 && *input_line_pointer
!= '=')
6945 ++input_line_pointer
;
6946 if (*input_line_pointer
!= '=')
6948 as_bad (_("missing ="));
6949 ignore_rest_of_line ();
6953 varstop
= input_line_pointer
;
6954 if (varstop
> varstart
6955 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6958 ++input_line_pointer
;
6960 initstart
= input_line_pointer
;
6962 /* Look for TO or DOWNTO. */
6965 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6967 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6968 && ! is_part_of_name (input_line_pointer
[2]))
6970 initstop
= input_line_pointer
;
6971 input_line_pointer
+= 2;
6974 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6975 && ! is_part_of_name (input_line_pointer
[6]))
6977 initstop
= input_line_pointer
;
6979 input_line_pointer
+= 6;
6982 ++input_line_pointer
;
6984 if (initstop
== NULL
)
6986 as_bad (_("missing to or downto"));
6987 ignore_rest_of_line ();
6990 if (initstop
> initstart
6991 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6995 endstart
= input_line_pointer
;
6997 /* Look for BY or DO. */
7000 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7002 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
7003 && ! is_part_of_name (input_line_pointer
[2]))
7005 endstop
= input_line_pointer
;
7007 input_line_pointer
+= 2;
7010 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
7011 && (input_line_pointer
[2] == '.'
7012 || ! is_part_of_name (input_line_pointer
[2])))
7014 endstop
= input_line_pointer
;
7015 input_line_pointer
+= 2;
7018 ++input_line_pointer
;
7020 if (endstop
== NULL
)
7022 as_bad (_("missing do"));
7023 ignore_rest_of_line ();
7026 if (endstop
> endstart
7027 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
7033 bystop
= bystart
+ 2;
7038 bystart
= input_line_pointer
;
7042 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7044 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
7045 && (input_line_pointer
[2] == '.'
7046 || ! is_part_of_name (input_line_pointer
[2])))
7048 bystop
= input_line_pointer
;
7049 input_line_pointer
+= 2;
7052 ++input_line_pointer
;
7056 as_bad (_("missing do"));
7057 ignore_rest_of_line ();
7060 if (bystop
> bystart
7061 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
7065 if (*input_line_pointer
!= '.')
7069 extent
= input_line_pointer
[1];
7070 input_line_pointer
+= 2;
7073 /* We have fully parsed the FOR operands. Now build the loop. */
7074 n
= push_mri_control (mri_for
);
7076 buf
= (char *) xmalloc (50 + (input_line_pointer
- varstart
));
7078 /* Move init,var. */
7085 *s
++ = TOLOWER (qual
);
7087 memcpy (s
, initstart
, initstop
- initstart
);
7088 s
+= initstop
- initstart
;
7090 memcpy (s
, varstart
, varstop
- varstart
);
7091 s
+= varstop
- varstart
;
7103 *s
++ = TOLOWER (qual
);
7105 memcpy (s
, endstart
, endstop
- endstart
);
7106 s
+= endstop
- endstart
;
7108 memcpy (s
, varstart
, varstop
- varstart
);
7109 s
+= varstop
- varstart
;
7114 ex
[0] = TOLOWER (extent
);
7117 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
7119 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
7122 /* Put together the add or sub instruction used by ENDF. */
7130 *s
++ = TOLOWER (qual
);
7132 memcpy (s
, bystart
, bystop
- bystart
);
7133 s
+= bystop
- bystart
;
7135 memcpy (s
, varstart
, varstop
- varstart
);
7136 s
+= varstop
- varstart
;
7142 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7143 ++input_line_pointer
;
7146 demand_empty_rest_of_line ();
7149 /* Handle the MRI ENDF pseudo-op. */
7152 s_mri_endf (int ignore ATTRIBUTE_UNUSED
)
7154 if (mri_control_stack
== NULL
7155 || mri_control_stack
->type
!= mri_for
)
7157 as_bad (_("endf without for"));
7158 ignore_rest_of_line ();
7162 colon (mri_control_stack
->next
);
7164 mri_assemble (mri_control_stack
->incr
);
7166 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
7167 mri_assemble (mri_control_stack
->incr
);
7169 free (mri_control_stack
->incr
);
7171 colon (mri_control_stack
->bottom
);
7177 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7178 ++input_line_pointer
;
7181 demand_empty_rest_of_line ();
7184 /* Handle the MRI REPEAT pseudo-op. */
7187 s_mri_repeat (int ignore ATTRIBUTE_UNUSED
)
7189 struct mri_control_info
*n
;
7191 n
= push_mri_control (mri_repeat
);
7195 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7196 ++input_line_pointer
;
7198 demand_empty_rest_of_line ();
7201 /* Handle the MRI UNTIL pseudo-op. */
7204 s_mri_until (int qual
)
7208 if (mri_control_stack
== NULL
7209 || mri_control_stack
->type
!= mri_repeat
)
7211 as_bad (_("until without repeat"));
7212 ignore_rest_of_line ();
7216 colon (mri_control_stack
->next
);
7218 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
7221 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
7222 mri_control_stack
->top
, '\0');
7224 colon (mri_control_stack
->bottom
);
7226 input_line_pointer
= s
;
7232 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7233 ++input_line_pointer
;
7236 demand_empty_rest_of_line ();
7239 /* Handle the MRI WHILE pseudo-op. */
7242 s_mri_while (int qual
)
7246 struct mri_control_info
*n
;
7248 s
= input_line_pointer
;
7249 /* We only accept '*' as introduction of comments if preceded by white space
7250 or at first column of a line (I think this can't actually happen here?)
7251 This is important when assembling:
7252 while d0 <ne> 12(a0,d0*2) do
7253 while d0 <ne> #CONST*20 do. */
7254 while (! (is_end_of_line
[(unsigned char) *s
]
7257 && (s
== input_line_pointer
7259 || *(s
-1) == '\t'))))
7262 while (*s
== ' ' || *s
== '\t')
7264 if (s
- input_line_pointer
> 1
7267 if (s
- input_line_pointer
< 2
7268 || strncasecmp (s
- 1, "DO", 2) != 0)
7270 as_bad (_("missing do"));
7271 ignore_rest_of_line ();
7275 n
= push_mri_control (mri_while
);
7279 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
7280 s
[1] == '.' ? s
[2] : '\0');
7282 input_line_pointer
= s
+ 1;
7283 if (*input_line_pointer
== '.')
7284 input_line_pointer
+= 2;
7288 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7289 ++input_line_pointer
;
7292 demand_empty_rest_of_line ();
7295 /* Handle the MRI ENDW pseudo-op. */
7298 s_mri_endw (int ignore ATTRIBUTE_UNUSED
)
7302 if (mri_control_stack
== NULL
7303 || mri_control_stack
->type
!= mri_while
)
7305 as_bad (_("endw without while"));
7306 ignore_rest_of_line ();
7310 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->next
));
7311 sprintf (buf
, "bra %s", mri_control_stack
->next
);
7315 colon (mri_control_stack
->bottom
);
7321 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7322 ++input_line_pointer
;
7325 demand_empty_rest_of_line ();
7328 /* Parse a .cpu directive. */
7331 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED
)
7338 as_bad (_("already assembled instructions"));
7339 ignore_rest_of_line ();
7343 name
= input_line_pointer
;
7344 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
7345 input_line_pointer
++;
7346 saved_char
= *input_line_pointer
;
7347 *input_line_pointer
= 0;
7349 m68k_set_cpu (name
, 1, 0);
7351 *input_line_pointer
= saved_char
;
7352 demand_empty_rest_of_line ();
7356 /* Parse a .arch directive. */
7359 s_m68k_arch (int ignored ATTRIBUTE_UNUSED
)
7366 as_bad (_("already assembled instructions"));
7367 ignore_rest_of_line ();
7371 name
= input_line_pointer
;
7372 while (*input_line_pointer
&& *input_line_pointer
!= ','
7373 && !ISSPACE (*input_line_pointer
))
7374 input_line_pointer
++;
7375 saved_char
= *input_line_pointer
;
7376 *input_line_pointer
= 0;
7378 if (m68k_set_arch (name
, 1, 0))
7380 /* Scan extensions. */
7383 *input_line_pointer
++ = saved_char
;
7384 if (!*input_line_pointer
|| ISSPACE (*input_line_pointer
))
7386 name
= input_line_pointer
;
7387 while (*input_line_pointer
&& *input_line_pointer
!= ','
7388 && !ISSPACE (*input_line_pointer
))
7389 input_line_pointer
++;
7390 saved_char
= *input_line_pointer
;
7391 *input_line_pointer
= 0;
7393 while (m68k_set_extension (name
, 1, 0));
7396 *input_line_pointer
= saved_char
;
7397 demand_empty_rest_of_line ();
7401 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7402 if none is found, the caller is responsible for emitting an error
7403 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7404 cpu name, if it begins with a '6' (possibly skipping an intervening
7405 'c'. We also allow a 'c' in the same place. if NEGATED is
7406 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7407 the option is indeed negated. */
7409 static const struct m68k_cpu
*
7410 m68k_lookup_cpu (const char *arg
, const struct m68k_cpu
*table
,
7411 int allow_m
, int *negated
)
7413 /* allow negated value? */
7418 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
7425 /* Remove 'm' or 'mc' prefix from 68k variants. */
7432 else if (arg
[1] == 'c' && arg
[2] == '6')
7436 else if (arg
[0] == 'c' && arg
[1] == '6')
7439 for (; table
->name
; table
++)
7440 if (!strcmp (arg
, table
->name
))
7442 if (table
->alias
< -1 || table
->alias
> 1)
7443 as_bad (_("`%s' is deprecated, use `%s'"),
7444 table
->name
, table
[table
->alias
< 0 ? 1 : -1].name
);
7450 /* Set the cpu, issuing errors if it is unrecognized. */
7453 m68k_set_cpu (char const *name
, int allow_m
, int silent
)
7455 const struct m68k_cpu
*cpu
;
7457 cpu
= m68k_lookup_cpu (name
, m68k_cpus
, allow_m
, NULL
);
7462 as_bad (_("cpu `%s' unrecognized"), name
);
7469 /* Set the architecture, issuing errors if it is unrecognized. */
7472 m68k_set_arch (char const *name
, int allow_m
, int silent
)
7474 const struct m68k_cpu
*arch
;
7476 arch
= m68k_lookup_cpu (name
, m68k_archs
, allow_m
, NULL
);
7481 as_bad (_("architecture `%s' unrecognized"), name
);
7484 selected_arch
= arch
;
7488 /* Set the architecture extension, issuing errors if it is
7489 unrecognized, or invalid */
7492 m68k_set_extension (char const *name
, int allow_m
, int silent
)
7495 const struct m68k_cpu
*ext
;
7497 ext
= m68k_lookup_cpu (name
, m68k_extensions
, allow_m
, &negated
);
7502 as_bad (_("extension `%s' unrecognized"), name
);
7507 not_current_architecture
|= (ext
->control_regs
7508 ? *(unsigned *)ext
->control_regs
: ext
->arch
);
7510 current_architecture
|= ext
->arch
;
7515 Invocation line includes a switch not recognized by the base assembler.
7519 const char *md_shortopts
= "lSA:m:kQ:V";
7521 const char *md_shortopts
= "lSA:m:k";
7524 struct option md_longopts
[] = {
7525 #define OPTION_PIC (OPTION_MD_BASE)
7526 {"pic", no_argument
, NULL
, OPTION_PIC
},
7527 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7528 {"register-prefix-optional", no_argument
, NULL
,
7529 OPTION_REGISTER_PREFIX_OPTIONAL
},
7530 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7531 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
7532 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7533 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
7534 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7535 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
7536 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7537 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
7538 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7539 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
7540 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7541 {"pcrel", no_argument
, NULL
, OPTION_PCREL
},
7542 {NULL
, no_argument
, NULL
, 0}
7544 size_t md_longopts_size
= sizeof (md_longopts
);
7547 md_parse_option (int c
, char *arg
)
7551 case 'l': /* -l means keep external to 2 bit offset
7552 rather than 16 bit one. */
7553 flag_short_refs
= 1;
7556 case 'S': /* -S means that jbsr's always turn into
7558 flag_long_jumps
= 1;
7561 case OPTION_PCREL
: /* --pcrel means never turn PC-relative
7562 branches into absolute jumps. */
7563 flag_keep_pcrel
= 1;
7569 break; /* -pic, Position Independent Code. */
7571 case OPTION_REGISTER_PREFIX_OPTIONAL
:
7572 flag_reg_prefix_optional
= 1;
7573 reg_prefix_optional_seen
= 1;
7576 /* -V: SVR4 argument to print version ID. */
7578 print_version_id ();
7581 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7582 should be emitted or not. FIXME: Not implemented. */
7586 case OPTION_BITWISE_OR
:
7591 n
= (char *) xmalloc (strlen (m68k_comment_chars
) + 1);
7593 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
7597 m68k_comment_chars
= n
;
7601 case OPTION_BASE_SIZE_DEFAULT_16
:
7602 m68k_index_width_default
= SIZE_WORD
;
7605 case OPTION_BASE_SIZE_DEFAULT_32
:
7606 m68k_index_width_default
= SIZE_LONG
;
7609 case OPTION_DISP_SIZE_DEFAULT_16
:
7611 m68k_rel32_from_cmdline
= 1;
7614 case OPTION_DISP_SIZE_DEFAULT_32
:
7616 m68k_rel32_from_cmdline
= 1;
7621 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7624 /* Intentional fall-through. */
7626 if (!strncmp (arg
, "arch=", 5))
7627 m68k_set_arch (arg
+ 5, 1, 0);
7628 else if (!strncmp (arg
, "cpu=", 4))
7629 m68k_set_cpu (arg
+ 4, 1, 0);
7630 else if (m68k_set_extension (arg
, 0, 1))
7632 else if (m68k_set_arch (arg
, 0, 1))
7634 else if (m68k_set_cpu (arg
, 0, 1))
7647 /* Setup tables from the selected arch and/or cpu */
7650 m68k_init_arch (void)
7652 if (not_current_architecture
& current_architecture
)
7654 as_bad (_("architecture features both enabled and disabled"));
7655 not_current_architecture
&= ~current_architecture
;
7659 current_architecture
|= selected_arch
->arch
;
7660 control_regs
= selected_arch
->control_regs
;
7663 current_architecture
|= selected_cpu
->arch
;
7665 current_architecture
&= ~not_current_architecture
;
7667 if ((current_architecture
& (cfloat
| m68881
)) == (cfloat
| m68881
))
7669 /* Determine which float is really meant. */
7670 if (current_architecture
& (m68k_mask
& ~m68881
))
7671 current_architecture
^= cfloat
;
7673 current_architecture
^= m68881
;
7678 control_regs
= selected_cpu
->control_regs
;
7679 if (current_architecture
& ~selected_cpu
->arch
)
7681 as_bad (_("selected processor does not have all features of selected architecture"));
7682 current_architecture
7683 = selected_cpu
->arch
& ~not_current_architecture
;
7687 if ((current_architecture
& m68k_mask
)
7688 && (current_architecture
& ~m68k_mask
))
7690 as_bad (_ ("m68k and cf features both selected"));
7691 if (current_architecture
& m68k_mask
)
7692 current_architecture
&= m68k_mask
;
7694 current_architecture
&= ~m68k_mask
;
7697 /* Permit m68881 specification with all cpus; those that can't work
7698 with a coprocessor could be doing emulation. */
7699 if (current_architecture
& m68851
)
7701 if (current_architecture
& m68040
)
7702 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7704 /* What other incompatibilities could we check for? */
7706 if (cpu_of_arch (current_architecture
) < m68020
7707 || arch_coldfire_p (current_architecture
))
7708 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
7714 md_show_usage (FILE *stream
)
7716 const char *default_cpu
= TARGET_CPU
;
7719 /* Get the canonical name for the default target CPU. */
7720 if (*default_cpu
== 'm')
7722 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7724 if (strcasecmp (default_cpu
, m68k_cpus
[i
].name
) == 0)
7726 while (m68k_cpus
[i
].alias
> 0)
7728 while (m68k_cpus
[i
].alias
< 0)
7730 default_cpu
= m68k_cpus
[i
].name
;
7734 fprintf (stream
, _("\
7735 -march=<arch> set architecture\n\
7736 -mcpu=<cpu> set cpu [default %s]\n\
7738 for (i
= 0; m68k_extensions
[i
].name
; i
++)
7739 fprintf (stream
, _("\
7740 -m[no-]%-16s enable/disable%s architecture extension\n\
7741 "), m68k_extensions
[i
].name
,
7742 m68k_extensions
[i
].alias
> 0 ? " ColdFire"
7743 : m68k_extensions
[i
].alias
< 0 ? " m68k" : "");
7745 fprintf (stream
, _("\
7746 -l use 1 word for refs to undefined symbols [default 2]\n\
7747 -pic, -k generate position independent code\n\
7748 -S turn jbsr into jsr\n\
7749 --pcrel never turn PC-relative branches into absolute jumps\n\
7750 --register-prefix-optional\n\
7751 recognize register names without prefix character\n\
7752 --bitwise-or do not treat `|' as a comment character\n\
7753 --base-size-default-16 base reg without size is 16 bits\n\
7754 --base-size-default-32 base reg without size is 32 bits (default)\n\
7755 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7756 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7759 fprintf (stream
, _("Architecture variants are: "));
7760 for (i
= 0; m68k_archs
[i
].name
; i
++)
7763 fprintf (stream
, " | ");
7764 fprintf (stream
, "%s", m68k_archs
[i
].name
);
7766 fprintf (stream
, "\n");
7768 fprintf (stream
, _("Processor variants are: "));
7769 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7772 fprintf (stream
, " | ");
7773 fprintf (stream
, "%s", m68k_cpus
[i
].name
);
7775 fprintf (stream
, _("\n"));
7780 /* TEST2: Test md_assemble() */
7781 /* Warning, this routine probably doesn't work anymore. */
7785 struct m68k_it the_ins
;
7793 if (!gets (buf
) || !*buf
)
7795 if (buf
[0] == '|' || buf
[1] == '.')
7797 for (cp
= buf
; *cp
; cp
++)
7802 memset (&the_ins
, '\0', sizeof (the_ins
));
7803 m68k_ip (&the_ins
, buf
);
7806 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
7810 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
7811 for (n
= 0; n
< the_ins
.numo
; n
++)
7812 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
7814 print_the_insn (&the_ins
.opcode
[0], stdout
);
7815 (void) putchar ('\n');
7817 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
7819 if (the_ins
.operands
[n
].error
)
7821 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
7824 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
,
7825 the_ins
.operands
[n
].reg
);
7826 if (the_ins
.operands
[n
].b_const
)
7827 printf ("Constant: '%.*s', ",
7828 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
,
7829 the_ins
.operands
[n
].b_const
);
7830 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
,
7831 the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
7832 if (the_ins
.operands
[n
].b_iadd
)
7833 printf ("Iadd: '%.*s',",
7834 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
,
7835 the_ins
.operands
[n
].b_iadd
);
7844 is_label (char *str
)
7848 while (*str
&& *str
!= ' ')
7850 if (str
[-1] == ':' || str
[1] == '=')
7857 /* Possible states for relaxation:
7859 0 0 branch offset byte (bra, etc)
7863 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7867 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7874 /* We have no need to default values of symbols. */
7877 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7882 /* Round up a section size to the appropriate boundary. */
7884 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7887 /* For a.out, force the section size to be aligned. If we don't do
7888 this, BFD will align it for us, but it will not write out the
7889 final bytes of the section. This may be a bug in BFD, but it is
7890 easier to fix it here since that is how the other a.out targets
7894 align
= bfd_get_section_alignment (stdoutput
, segment
);
7895 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7901 /* Exactly what point is a PC-relative offset relative TO?
7902 On the 68k, it is relative to the address of the first extension
7903 word. The difference between the addresses of the offset and the
7904 first extension word is stored in fx_pcrel_adjust. */
7906 md_pcrel_from (fixS
*fixP
)
7910 adjust
= fixP
->fx_pcrel_adjust
;
7913 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
7918 m68k_elf_final_processing (void)
7922 if (arch_coldfire_fpu (current_architecture
))
7923 flags
|= EF_M68K_CFV4E
;
7924 /* Set file-specific flags if this is a cpu32 processor. */
7925 if (cpu_of_arch (current_architecture
) & cpu32
)
7926 flags
|= EF_M68K_CPU32
;
7927 else if (cpu_of_arch (current_architecture
) & fido_a
)
7928 flags
|= EF_M68K_FIDO
;
7929 else if ((cpu_of_arch (current_architecture
) & m68000up
)
7930 && !(cpu_of_arch (current_architecture
) & m68020up
))
7931 flags
|= EF_M68K_M68000
;
7933 if (current_architecture
& mcfisa_a
)
7935 static const unsigned isa_features
[][2] =
7937 {EF_M68K_CF_ISA_A_NODIV
,mcfisa_a
},
7938 {EF_M68K_CF_ISA_A
, mcfisa_a
|mcfhwdiv
},
7939 {EF_M68K_CF_ISA_A_PLUS
, mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfusp
},
7940 {EF_M68K_CF_ISA_B_NOUSP
,mcfisa_a
|mcfisa_b
|mcfhwdiv
},
7941 {EF_M68K_CF_ISA_B
, mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfusp
},
7942 {EF_M68K_CF_ISA_C
, mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfusp
},
7943 {EF_M68K_CF_ISA_C_NODIV
,mcfisa_a
|mcfisa_c
|mcfusp
},
7946 static const unsigned mac_features
[][2] =
7948 {EF_M68K_CF_MAC
, mcfmac
},
7949 {EF_M68K_CF_EMAC
, mcfemac
},
7955 pattern
= (current_architecture
7956 & (mcfisa_a
|mcfisa_aa
|mcfisa_b
|mcfisa_c
|mcfhwdiv
|mcfusp
));
7957 for (ix
= 0; isa_features
[ix
][1]; ix
++)
7959 if (pattern
== isa_features
[ix
][1])
7961 flags
|= isa_features
[ix
][0];
7965 if (!isa_features
[ix
][1])
7968 as_warn (_("Not a defined coldfire architecture"));
7972 if (current_architecture
& cfloat
)
7973 flags
|= EF_M68K_CF_FLOAT
| EF_M68K_CFV4E
;
7975 pattern
= current_architecture
& (mcfmac
|mcfemac
);
7978 for (ix
= 0; mac_features
[ix
][1]; ix
++)
7980 if (pattern
== mac_features
[ix
][1])
7982 flags
|= mac_features
[ix
][0];
7986 if (!mac_features
[ix
][1])
7991 elf_elfheader (stdoutput
)->e_flags
|= flags
;
7994 /* Parse @TLSLDO and return the desired relocation. */
7995 static bfd_reloc_code_real_type
7996 m68k_elf_suffix (char **str_p
, expressionS
*exp_p
)
8005 return BFD_RELOC_UNUSED
;
8007 for (ch
= *str
, str2
= ident
;
8008 (str2
< ident
+ sizeof (ident
) - 1
8009 && (ISALNUM (ch
) || ch
== '@'));
8018 if (strncmp (ident
, "TLSLDO", 6) == 0
8021 /* Now check for identifier@suffix+constant. */
8022 if (*str
== '-' || *str
== '+')
8024 char *orig_line
= input_line_pointer
;
8025 expressionS new_exp
;
8027 input_line_pointer
= str
;
8028 expression (&new_exp
);
8029 if (new_exp
.X_op
== O_constant
)
8031 exp_p
->X_add_number
+= new_exp
.X_add_number
;
8032 str
= input_line_pointer
;
8035 if (&input_line_pointer
!= str_p
)
8036 input_line_pointer
= orig_line
;
8040 return BFD_RELOC_68K_TLS_LDO32
;
8043 return BFD_RELOC_UNUSED
;
8046 /* Handles .long <tls_symbol>+0x8000 debug info.
8047 Clobbers input_line_pointer, checks end-of-line.
8048 Adapted from tc-ppc.c:ppc_elf_cons. */
8050 m68k_elf_cons (int nbytes
/* 4=.long */)
8052 if (is_it_end_of_statement ())
8054 demand_empty_rest_of_line ();
8061 bfd_reloc_code_real_type reloc
;
8064 if (exp
.X_op
== O_symbol
8065 && *input_line_pointer
== '@'
8066 && (reloc
= m68k_elf_suffix (&input_line_pointer
,
8067 &exp
)) != BFD_RELOC_UNUSED
)
8069 reloc_howto_type
*reloc_howto
;
8072 reloc_howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
8073 size
= bfd_get_reloc_size (reloc_howto
);
8077 as_bad (_("%s relocations do not fit in %d bytes\n"),
8078 reloc_howto
->name
, nbytes
);
8085 p
= frag_more (nbytes
);
8087 if (target_big_endian
)
8088 offset
= nbytes
- size
;
8089 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
, size
,
8094 emit_expr (&exp
, (unsigned int) nbytes
);
8096 while (*input_line_pointer
++ == ',');
8098 /* Put terminator back into stream. */
8099 input_line_pointer
--;
8100 demand_empty_rest_of_line ();
8105 tc_m68k_regname_to_dw2regnum (char *regname
)
8107 unsigned int regnum
;
8108 static const char *const regnames
[] =
8110 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
8111 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
8112 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
8116 for (regnum
= 0; regnum
< ARRAY_SIZE (regnames
); regnum
++)
8117 if (strcmp (regname
, regnames
[regnum
]) == 0)
8124 tc_m68k_frame_initial_instructions (void)
8126 static int sp_regno
= -1;
8129 sp_regno
= tc_m68k_regname_to_dw2regnum ("sp");
8131 cfi_add_CFA_def_cfa (sp_regno
, -DWARF2_CIE_DATA_ALIGNMENT
);
8132 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, DWARF2_CIE_DATA_ALIGNMENT
);
8135 /* Check and emit error if broken-word handling has failed to fix up a
8136 case-table. This is called from write.c, after doing everything it
8137 knows about how to handle broken words. */
8140 tc_m68k_check_adjusted_broken_word (offsetT new_offset
, struct broken_word
*brokwP
)
8142 if (new_offset
> 32767 || new_offset
< -32768)
8143 as_bad_where (brokwP
->frag
->fr_file
, brokwP
->frag
->fr_line
,
8144 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."),