1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars
= "|#";
47 const char *m68k_comment_chars
= "|";
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars
[] = "#*";
59 const char line_separator_chars
[] = ";";
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS
[] = "eE";
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
67 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
79 static int flag_short_refs
; /* -l option. */
80 static int flag_long_jumps
; /* -S option. */
81 static int flag_keep_pcrel
; /* --pcrel option. */
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
86 int flag_reg_prefix_optional
;
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen
;
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum
= COP1
;
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd
;
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick
= 1;
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
106 static int m68k_rel32
= 1;
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline
;
111 /* The default width to use for an index register when using a base
113 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
120 struct label_line
*next
;
127 /* The list of labels. */
129 static struct label_line
*labels
;
131 /* The current label. */
133 static struct label_line
*current_label
;
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode
const ** m68k_sorted_opcodes
;
138 /* Its an arbitrary name: This means I don't approve of it.
140 static struct obstack robyn
;
144 const char *m_operands
;
145 unsigned long m_opcode
;
149 struct m68k_incant
*m_next
;
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
155 static const enum m68k_register m68000_ctrl
[] = { 0 };
156 static const enum m68k_register m68010_ctrl
[] = {
160 static const enum m68k_register m68020_ctrl
[] = {
161 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
164 static const enum m68k_register m68040_ctrl
[] = {
165 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
166 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
169 static const enum m68k_register m68060_ctrl
[] = {
170 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
171 USP
, VBR
, URP
, SRP
, PCR
,
174 static const enum m68k_register mcf_ctrl
[] = {
175 CACR
, TC
, ACR0
, ACR1
, ACR2
, ACR3
, VBR
, ROMBAR
,
176 RAMBAR0
, RAMBAR1
, MBAR
,
179 static const enum m68k_register mcf5208_ctrl
[] = {
180 CACR
, ACR0
, ACR1
, VBR
, RAMBAR1
,
183 static const enum m68k_register mcf5210a_ctrl
[] = {
184 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR
, MBAR
,
187 static const enum m68k_register mcf5213_ctrl
[] = {
188 VBR
, RAMBAR
, FLASHBAR
,
191 static const enum m68k_register mcf5216_ctrl
[] = {
192 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
,
195 static const enum m68k_register mcf52235_ctrl
[] = {
196 VBR
, FLASHBAR
, RAMBAR
,
199 static const enum m68k_register mcf5225_ctrl
[] = {
200 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, MBAR
,
203 static const enum m68k_register mcf5235_ctrl
[] = {
204 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
207 static const enum m68k_register mcf5249_ctrl
[] = {
208 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, MBAR
, MBAR2
,
211 static const enum m68k_register mcf5250_ctrl
[] = {
215 static const enum m68k_register mcf5271_ctrl
[] = {
216 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
219 static const enum m68k_register mcf5272_ctrl
[] = {
220 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR
, MBAR
,
223 static const enum m68k_register mcf5275_ctrl
[] = {
224 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
227 static const enum m68k_register mcf5282_ctrl
[] = {
228 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
,
231 static const enum m68k_register mcf5329_ctrl
[] = {
232 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
235 static const enum m68k_register mcf5373_ctrl
[] = {
236 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
239 static const enum m68k_register mcfv4e_ctrl
[] = {
240 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
241 VBR
, PC
, ROMBAR0
, ROMBAR1
, RAMBAR0
, RAMBAR1
,
243 MPCR
/* Multiprocessor Control register */,
244 EDRAMBAR
/* Embedded DRAM Base Address Register */,
245 /* Permutation control registers. */
246 PCR1U0
, PCR1L0
, PCR1U1
, PCR1L1
, PCR2U0
, PCR2L0
, PCR2U1
, PCR2L1
,
247 PCR3U0
, PCR3L0
, PCR3U1
, PCR3L1
,
249 TC
/* ASID */, BUSCR
/* MMUBAR */,
250 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
251 MBAR1
/* MBAR */, MBAR2
/* SECMBAR */, MBAR0
/* SECMBAR */,
252 ROMBAR
/* ROMBAR0 */,
255 static const enum m68k_register mcf5475_ctrl
[] = {
256 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
257 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
259 TC
/* ASID */, BUSCR
/* MMUBAR */,
260 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
261 MBAR1
/* MBAR */, ROMBAR
/* ROMBAR0 */,
264 static const enum m68k_register mcf5485_ctrl
[] = {
265 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
266 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
268 TC
/* ASID */, BUSCR
/* MMUBAR */,
269 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
270 MBAR1
/* MBAR */, ROMBAR
/* ROMBAR0 */,
273 static const enum m68k_register fido_ctrl
[] = {
274 SFC
, DFC
, USP
, VBR
, CAC
, MBB
,
277 #define cpu32_ctrl m68010_ctrl
279 static const enum m68k_register
*control_regs
;
281 /* Internal form of a 68020 instruction. */
285 const char *args
; /* List of opcode info. */
288 int numo
; /* Number of shorts in opcode. */
291 struct m68k_op operands
[6];
293 int nexp
; /* Number of exprs in use. */
294 struct m68k_exp exprs
[4];
296 int nfrag
; /* Number of frags we have to produce. */
299 int fragoff
; /* Where in the current opcode the frag ends. */
306 int nrel
; /* Num of reloc strucs in use. */
313 /* In a pc relative address the difference between the address
314 of the offset and the address that the offset is relative
315 to. This depends on the addressing mode. Basically this
316 is the value to put in the offset field to address the
317 first byte of the offset, without regarding the special
318 significance of some values (in the branch instruction, for
322 /* Whether this expression needs special pic relocation, and if
324 enum pic_relocation pic_reloc
;
327 reloc
[5]; /* Five is enough??? */
330 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
331 #define float_of_arch(x) ((x) & mfloat)
332 #define mmu_of_arch(x) ((x) & mmmu)
333 #define arch_coldfire_p(x) ((x) & mcfisa_a)
334 #define arch_coldfire_fpu(x) ((x) & cfloat)
336 /* Macros for determining if cpu supports a specific addressing mode. */
337 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
339 static struct m68k_it the_ins
; /* The instruction being assembled. */
341 #define op(ex) ((ex)->exp.X_op)
342 #define adds(ex) ((ex)->exp.X_add_symbol)
343 #define subs(ex) ((ex)->exp.X_op_symbol)
344 #define offs(ex) ((ex)->exp.X_add_number)
346 /* Macros for adding things to the m68k_it struct. */
347 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
349 /* Like addword, but goes BEFORE general operands. */
352 insop (int w
, const struct m68k_incant
*opcode
)
355 for (z
= the_ins
.numo
; z
> opcode
->m_codenum
; --z
)
356 the_ins
.opcode
[z
] = the_ins
.opcode
[z
- 1];
357 for (z
= 0; z
< the_ins
.nrel
; z
++)
358 the_ins
.reloc
[z
].n
+= 2;
359 for (z
= 0; z
< the_ins
.nfrag
; z
++)
360 the_ins
.fragb
[z
].fragoff
++;
361 the_ins
.opcode
[opcode
->m_codenum
] = w
;
365 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
368 add_fix (int width
, struct m68k_exp
*exp
, int pc_rel
, int pc_fix
)
370 the_ins
.reloc
[the_ins
.nrel
].n
= (width
== 'B' || width
== '3'
371 ? the_ins
.numo
* 2 - 1
373 ? the_ins
.numo
* 2 + 1
374 : the_ins
.numo
* 2));
375 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
376 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
377 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
379 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
381 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
384 /* Cause an extra frag to be generated here, inserting up to 10 bytes
385 (that value is chosen in the frag_var call in md_assemble). TYPE
386 is the subtype of the frag to be generated; its primary type is
387 rs_machine_dependent.
389 The TYPE parameter is also used by md_convert_frag_1 and
390 md_estimate_size_before_relax. The appropriate type of fixup will
391 be emitted by md_convert_frag_1.
393 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
395 add_frag (symbolS
*add
, offsetT off
, int type
)
397 the_ins
.fragb
[the_ins
.nfrag
].fragoff
= the_ins
.numo
;
398 the_ins
.fragb
[the_ins
.nfrag
].fadd
= add
;
399 the_ins
.fragb
[the_ins
.nfrag
].foff
= off
;
400 the_ins
.fragb
[the_ins
.nfrag
++].fragty
= type
;
404 (op (ex) != O_constant && op (ex) != O_big)
406 static char *crack_operand (char *str
, struct m68k_op
*opP
);
407 static int get_num (struct m68k_exp
*exp
, int ok
);
408 static int reverse_16_bits (int in
);
409 static int reverse_8_bits (int in
);
410 static void install_gen_operand (int mode
, int val
);
411 static void install_operand (int mode
, int val
);
412 static void s_bss (int);
413 static void s_data1 (int);
414 static void s_data2 (int);
415 static void s_even (int);
416 static void s_proc (int);
417 static void s_chip (int);
418 static void s_fopt (int);
419 static void s_opt (int);
420 static void s_reg (int);
421 static void s_restore (int);
422 static void s_save (int);
423 static void s_mri_if (int);
424 static void s_mri_else (int);
425 static void s_mri_endi (int);
426 static void s_mri_break (int);
427 static void s_mri_next (int);
428 static void s_mri_for (int);
429 static void s_mri_endf (int);
430 static void s_mri_repeat (int);
431 static void s_mri_until (int);
432 static void s_mri_while (int);
433 static void s_mri_endw (int);
434 static void s_m68k_cpu (int);
435 static void s_m68k_arch (int);
439 unsigned long arch
; /* Architecture features. */
440 const enum m68k_register
*control_regs
; /* Control regs on chip */
441 const char *name
; /* Name */
442 int alias
; /* Alias for a cannonical name. If 1, then
443 succeeds canonical name, if -1 then
444 succeeds canonical name, if <-1 ||>1 this is a
445 deprecated name, and the next/previous name
449 /* We hold flags for features explicitly enabled and explicitly
451 static int current_architecture
;
452 static int not_current_architecture
;
453 static const struct m68k_cpu
*selected_arch
;
454 static const struct m68k_cpu
*selected_cpu
;
455 static int initialized
;
457 /* Architecture models. */
458 static const struct m68k_cpu m68k_archs
[] =
460 {m68000
, m68000_ctrl
, "68000", 0},
461 {m68010
, m68010_ctrl
, "68010", 0},
462 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
463 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
464 {m68040
, m68040_ctrl
, "68040", 0},
465 {m68060
, m68060_ctrl
, "68060", 0},
466 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
467 {fido_a
, fido_ctrl
, "fidoa", 0},
468 {mcfisa_a
|mcfhwdiv
, NULL
, "isaa", 0},
469 {mcfisa_a
|mcfhwdiv
|mcfisa_aa
|mcfusp
, NULL
, "isaaplus", 0},
470 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfusp
, NULL
, "isab", 0},
471 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfmac
|mcfusp
, mcf_ctrl
, "cfv4", 0},
472 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "cfv4e", 0},
476 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
478 static const struct m68k_cpu m68k_extensions
[] =
480 {m68851
, NULL
, "68851", -1},
481 {m68881
, NULL
, "68881", -1},
482 {m68881
, NULL
, "68882", -1},
484 {cfloat
|m68881
, NULL
, "float", 0},
486 {mcfhwdiv
, NULL
, "div", 1},
487 {mcfusp
, NULL
, "usp", 1},
488 {mcfmac
, NULL
, "mac", 1},
489 {mcfemac
, NULL
, "emac", 1},
495 static const struct m68k_cpu m68k_cpus
[] =
497 {m68000
, m68000_ctrl
, "68000", 0},
498 {m68000
, m68000_ctrl
, "68ec000", 1},
499 {m68000
, m68000_ctrl
, "68hc000", 1},
500 {m68000
, m68000_ctrl
, "68hc001", 1},
501 {m68000
, m68000_ctrl
, "68008", 1},
502 {m68000
, m68000_ctrl
, "68302", 1},
503 {m68000
, m68000_ctrl
, "68306", 1},
504 {m68000
, m68000_ctrl
, "68307", 1},
505 {m68000
, m68000_ctrl
, "68322", 1},
506 {m68000
, m68000_ctrl
, "68356", 1},
507 {m68010
, m68010_ctrl
, "68010", 0},
508 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
509 {m68020
|m68881
|m68851
, m68020_ctrl
, "68k", 1},
510 {m68020
|m68881
|m68851
, m68020_ctrl
, "68ec020", 1},
511 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
512 {m68030
|m68881
|m68851
, m68020_ctrl
, "68ec030", 1},
513 {m68040
, m68040_ctrl
, "68040", 0},
514 {m68040
, m68040_ctrl
, "68ec040", 1},
515 {m68060
, m68060_ctrl
, "68060", 0},
516 {m68060
, m68060_ctrl
, "68ec060", 1},
518 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
519 {cpu32
|m68881
, cpu32_ctrl
, "68330", 1},
520 {cpu32
|m68881
, cpu32_ctrl
, "68331", 1},
521 {cpu32
|m68881
, cpu32_ctrl
, "68332", 1},
522 {cpu32
|m68881
, cpu32_ctrl
, "68333", 1},
523 {cpu32
|m68881
, cpu32_ctrl
, "68334", 1},
524 {cpu32
|m68881
, cpu32_ctrl
, "68336", 1},
525 {cpu32
|m68881
, cpu32_ctrl
, "68340", 1},
526 {cpu32
|m68881
, cpu32_ctrl
, "68341", 1},
527 {cpu32
|m68881
, cpu32_ctrl
, "68349", 1},
528 {cpu32
|m68881
, cpu32_ctrl
, "68360", 1},
530 {mcfisa_a
, mcf_ctrl
, "5200", 0},
531 {mcfisa_a
, mcf_ctrl
, "5202", 1},
532 {mcfisa_a
, mcf_ctrl
, "5204", 1},
533 {mcfisa_a
, mcf_ctrl
, "5206", 1},
535 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf_ctrl
, "5206e", 0},
537 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5207", -1},
538 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5208", 0},
540 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5210a", 0},
541 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5211a", 1},
543 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5211", -1},
544 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5212", -1},
545 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5213", 0},
547 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5214", -1},
548 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5216", 0},
549 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "521x", 2},
551 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52230", -1},
552 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52233", -1},
553 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52234", -1},
554 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52235", 0},
556 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5224", -1},
557 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5225", 0},
559 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5232", -1},
560 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5233", -1},
561 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5234", -1},
562 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5235", -1},
563 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "523x", 0},
565 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5249_ctrl
, "5249", 0},
566 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5250_ctrl
, "5250", 0},
568 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5270", -1},
569 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5271", 0},
571 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5272_ctrl
, "5272", 0},
573 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5274", -1},
574 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5275", 0},
576 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5280", -1},
577 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5281", -1},
578 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5282", -1},
579 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "528x", 0},
581 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf_ctrl
, "5307", 0},
583 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5327", -1},
584 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5328", -1},
585 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5329", -1},
586 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "532x", 0},
588 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5372", -1},
589 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5373", -1},
590 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "537x", 0},
592 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfmac
, mcf_ctrl
, "5407",0},
594 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5470", -1},
595 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5471", -1},
596 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5472", -1},
597 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5473", -1},
598 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5474", -1},
599 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5475", -1},
600 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "547x", 0},
602 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5480", -1},
603 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5481", -1},
604 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5482", -1},
605 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5483", -1},
606 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5484", -1},
607 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5485", -1},
608 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "548x", 0},
610 {fido_a
, fido_ctrl
, "fido", 1},
615 static const struct m68k_cpu
*m68k_lookup_cpu
616 (const char *, const struct m68k_cpu
*, int, int *);
617 static int m68k_set_arch (const char *, int, int);
618 static int m68k_set_cpu (const char *, int, int);
619 static int m68k_set_extension (const char *, int, int);
620 static void m68k_init_arch (void);
622 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
623 architecture and we have a lot of relaxation modes. */
625 /* Macros used in the relaxation code. */
626 #define TAB(x,y) (((x) << 2) + (y))
627 #define TABTYPE(x) ((x) >> 2)
629 /* Relaxation states. */
635 /* Here are all the relaxation modes we support. First we can relax ordinary
636 branches. On 68020 and higher and on CPU32 all branch instructions take
637 three forms, so on these CPUs all branches always remain as such. When we
638 have to expand to the LONG form on a 68000, though, we substitute an
639 absolute jump instead. This is a direct replacement for unconditional
640 branches and a branch over a jump for conditional branches. However, if the
641 user requires PIC and disables this with --pcrel, we can only relax between
642 BYTE and SHORT forms, punting if that isn't enough. This gives us four
643 different relaxation modes for branches: */
645 #define BRANCHBWL 0 /* Branch byte, word, or long. */
646 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
647 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
648 #define BRANCHBW 3 /* Branch byte or word. */
650 /* We also relax coprocessor branches and DBcc's. All CPUs that support
651 coprocessor branches support them in word and long forms, so we have only
652 one relaxation mode for them. DBcc's are word only on all CPUs. We can
653 relax them to the LONG form with a branch-around sequence. This sequence
654 can use a long branch (if available) or an absolute jump (if acceptable).
655 This gives us two relaxation modes. If long branches are not available and
656 absolute jumps are not acceptable, we don't relax DBcc's. */
658 #define FBRANCH 4 /* Coprocessor branch. */
659 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
660 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
662 /* That's all for instruction relaxation. However, we also relax PC-relative
663 operands. Specifically, we have three operand relaxation modes. On the
664 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
665 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
666 two. Also PC+displacement+index operands in their simple form (with a non-
667 suppressed index without memory indirection) are supported on all CPUs, but
668 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
669 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
670 form of the PC+displacement+index operand. Finally, some absolute operands
671 can be relaxed down to 16-bit PC-relative. */
673 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
674 #define PCINDEX 8 /* PC + displacement + index. */
675 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
677 /* Note that calls to frag_var need to specify the maximum expansion
678 needed; this is currently 10 bytes for DBCC. */
681 How far Forward this mode will reach:
682 How far Backward this mode will reach:
683 How many bytes this mode will add to the size of the frag
684 Which mode to go to if the offset won't fit in this one
686 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
687 relax_typeS md_relax_table
[] =
689 { 127, -128, 0, TAB (BRANCHBWL
, SHORT
) },
690 { 32767, -32768, 2, TAB (BRANCHBWL
, LONG
) },
694 { 127, -128, 0, TAB (BRABSJUNC
, SHORT
) },
695 { 32767, -32768, 2, TAB (BRABSJUNC
, LONG
) },
699 { 127, -128, 0, TAB (BRABSJCOND
, SHORT
) },
700 { 32767, -32768, 2, TAB (BRABSJCOND
, LONG
) },
704 { 127, -128, 0, TAB (BRANCHBW
, SHORT
) },
709 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
710 { 32767, -32768, 2, TAB (FBRANCH
, LONG
) },
714 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
715 { 32767, -32768, 2, TAB (DBCCLBR
, LONG
) },
719 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
720 { 32767, -32768, 2, TAB (DBCCABSJ
, LONG
) },
724 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
725 { 32767, -32768, 2, TAB (PCREL1632
, LONG
) },
729 { 125, -130, 0, TAB (PCINDEX
, SHORT
) },
730 { 32765, -32770, 2, TAB (PCINDEX
, LONG
) },
734 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
735 { 32767, -32768, 2, TAB (ABSTOPCREL
, LONG
) },
740 /* These are the machine dependent pseudo-ops. These are included so
741 the assembler can work on the output from the SUN C compiler, which
744 /* This table describes all the machine specific pseudo-ops the assembler
745 has to support. The fields are:
746 pseudo-op name without dot
747 function to call to execute this pseudo-op
748 Integer arg to pass to the function. */
749 const pseudo_typeS md_pseudo_table
[] =
751 {"data1", s_data1
, 0},
752 {"data2", s_data2
, 0},
755 {"skip", s_space
, 0},
757 #if defined (TE_SUN3) || defined (OBJ_ELF)
758 {"align", s_align_bytes
, 0},
761 {"swbeg", s_ignore
, 0},
763 {"extend", float_cons
, 'x'},
764 {"ldouble", float_cons
, 'x'},
766 {"arch", s_m68k_arch
, 0},
767 {"cpu", s_m68k_cpu
, 0},
769 /* The following pseudo-ops are supported for MRI compatibility. */
771 {"comline", s_space
, 1},
773 {"mask2", s_ignore
, 0},
776 {"restore", s_restore
, 0},
780 {"if.b", s_mri_if
, 'b'},
781 {"if.w", s_mri_if
, 'w'},
782 {"if.l", s_mri_if
, 'l'},
783 {"else", s_mri_else
, 0},
784 {"else.s", s_mri_else
, 's'},
785 {"else.l", s_mri_else
, 'l'},
786 {"endi", s_mri_endi
, 0},
787 {"break", s_mri_break
, 0},
788 {"break.s", s_mri_break
, 's'},
789 {"break.l", s_mri_break
, 'l'},
790 {"next", s_mri_next
, 0},
791 {"next.s", s_mri_next
, 's'},
792 {"next.l", s_mri_next
, 'l'},
793 {"for", s_mri_for
, 0},
794 {"for.b", s_mri_for
, 'b'},
795 {"for.w", s_mri_for
, 'w'},
796 {"for.l", s_mri_for
, 'l'},
797 {"endf", s_mri_endf
, 0},
798 {"repeat", s_mri_repeat
, 0},
799 {"until", s_mri_until
, 0},
800 {"until.b", s_mri_until
, 'b'},
801 {"until.w", s_mri_until
, 'w'},
802 {"until.l", s_mri_until
, 'l'},
803 {"while", s_mri_while
, 0},
804 {"while.b", s_mri_while
, 'b'},
805 {"while.w", s_mri_while
, 'w'},
806 {"while.l", s_mri_while
, 'l'},
807 {"endw", s_mri_endw
, 0},
812 /* The mote pseudo ops are put into the opcode table, since they
813 don't start with a . they look like opcodes to gas. */
815 const pseudo_typeS mote_pseudo_table
[] =
828 {"xdef", s_globl
, 0},
830 {"align", s_align_bytes
, 0},
832 {"align", s_align_ptwo
, 0},
835 {"sect", obj_coff_section
, 0},
836 {"section", obj_coff_section
, 0},
841 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
842 gives identical results to a 32-bit host. */
843 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
844 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
846 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
847 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
848 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
849 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
851 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
852 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
853 #define islong(x) (1)
855 static char notend_table
[256];
856 static char alt_notend_table
[256];
858 (! (notend_table[(unsigned char) *s] \
860 && alt_notend_table[(unsigned char) s[1]])))
864 /* Return zero if the reference to SYMBOL from within the same segment may
867 /* On an ELF system, we can't relax an externally visible symbol,
868 because it may be overridden by a shared library. However, if
869 TARGET_OS is "elf", then we presume that we are assembling for an
870 embedded system, in which case we don't have to worry about shared
871 libraries, and we can relax any external sym. */
873 #define relaxable_symbol(symbol) \
874 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
875 || S_IS_WEAK (symbol)))
877 /* Compute the relocation code for a fixup of SIZE bytes, using pc
878 relative relocation if PCREL is non-zero. PIC says whether a special
879 pic relocation was requested. */
881 static bfd_reloc_code_real_type
882 get_reloc_code (int size
, int pcrel
, enum pic_relocation pic
)
890 return BFD_RELOC_8_GOT_PCREL
;
892 return BFD_RELOC_16_GOT_PCREL
;
894 return BFD_RELOC_32_GOT_PCREL
;
902 return BFD_RELOC_8_GOTOFF
;
904 return BFD_RELOC_16_GOTOFF
;
906 return BFD_RELOC_32_GOTOFF
;
914 return BFD_RELOC_8_PLT_PCREL
;
916 return BFD_RELOC_16_PLT_PCREL
;
918 return BFD_RELOC_32_PLT_PCREL
;
926 return BFD_RELOC_8_PLTOFF
;
928 return BFD_RELOC_16_PLTOFF
;
930 return BFD_RELOC_32_PLTOFF
;
940 return BFD_RELOC_8_PCREL
;
942 return BFD_RELOC_16_PCREL
;
944 return BFD_RELOC_32_PCREL
;
964 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
966 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
971 as_bad (_("Can not do %d byte relocation"), size
);
973 as_bad (_("Can not do %d byte pic relocation"), size
);
976 return BFD_RELOC_NONE
;
979 /* Here we decide which fixups can be adjusted to make them relative
980 to the beginning of the section instead of the symbol. Basically
981 we need to make sure that the dynamic relocations are done
982 correctly, so in some cases we force the original symbol to be
985 tc_m68k_fix_adjustable (fixS
*fixP
)
987 /* Adjust_reloc_syms doesn't know about the GOT. */
988 switch (fixP
->fx_r_type
)
990 case BFD_RELOC_8_GOT_PCREL
:
991 case BFD_RELOC_16_GOT_PCREL
:
992 case BFD_RELOC_32_GOT_PCREL
:
993 case BFD_RELOC_8_GOTOFF
:
994 case BFD_RELOC_16_GOTOFF
:
995 case BFD_RELOC_32_GOTOFF
:
996 case BFD_RELOC_8_PLT_PCREL
:
997 case BFD_RELOC_16_PLT_PCREL
:
998 case BFD_RELOC_32_PLT_PCREL
:
999 case BFD_RELOC_8_PLTOFF
:
1000 case BFD_RELOC_16_PLTOFF
:
1001 case BFD_RELOC_32_PLTOFF
:
1004 case BFD_RELOC_VTABLE_INHERIT
:
1005 case BFD_RELOC_VTABLE_ENTRY
:
1013 #else /* !OBJ_ELF */
1015 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1017 #define relaxable_symbol(symbol) 1
1019 #endif /* OBJ_ELF */
1022 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
1025 bfd_reloc_code_real_type code
;
1027 /* If the tcbit is set, then this was a fixup of a negative value
1028 that was never resolved. We do not have a reloc to handle this,
1029 so just return. We assume that other code will have detected this
1030 situation and produced a helpful error message, so we just tell the
1031 user that the reloc cannot be produced. */
1035 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1036 _("Unable to produce reloc against symbol '%s'"),
1037 S_GET_NAME (fixp
->fx_addsy
));
1041 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
1043 code
= fixp
->fx_r_type
;
1045 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1046 that fixup_segment converted a non-PC relative reloc into a
1047 PC relative reloc. In such a case, we need to convert the
1054 code
= BFD_RELOC_8_PCREL
;
1057 code
= BFD_RELOC_16_PCREL
;
1060 code
= BFD_RELOC_32_PCREL
;
1062 case BFD_RELOC_8_PCREL
:
1063 case BFD_RELOC_16_PCREL
:
1064 case BFD_RELOC_32_PCREL
:
1065 case BFD_RELOC_8_GOT_PCREL
:
1066 case BFD_RELOC_16_GOT_PCREL
:
1067 case BFD_RELOC_32_GOT_PCREL
:
1068 case BFD_RELOC_8_GOTOFF
:
1069 case BFD_RELOC_16_GOTOFF
:
1070 case BFD_RELOC_32_GOTOFF
:
1071 case BFD_RELOC_8_PLT_PCREL
:
1072 case BFD_RELOC_16_PLT_PCREL
:
1073 case BFD_RELOC_32_PLT_PCREL
:
1074 case BFD_RELOC_8_PLTOFF
:
1075 case BFD_RELOC_16_PLTOFF
:
1076 case BFD_RELOC_32_PLTOFF
:
1079 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1080 _("Cannot make %s relocation PC relative"),
1081 bfd_get_reloc_code_name (code
));
1087 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1088 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
1090 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1091 MAP (1, 0, BFD_RELOC_8
);
1092 MAP (2, 0, BFD_RELOC_16
);
1093 MAP (4, 0, BFD_RELOC_32
);
1094 MAP (1, 1, BFD_RELOC_8_PCREL
);
1095 MAP (2, 1, BFD_RELOC_16_PCREL
);
1096 MAP (4, 1, BFD_RELOC_32_PCREL
);
1104 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1105 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1106 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1107 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1110 reloc
->addend
= fixp
->fx_addnumber
;
1114 if (!fixp
->fx_pcrel
)
1115 reloc
->addend
= fixp
->fx_addnumber
;
1117 reloc
->addend
= (section
->vma
1118 /* Explicit sign extension in case char is
1120 + ((fixp
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80
1121 + fixp
->fx_addnumber
1122 + md_pcrel_from (fixp
));
1125 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1126 assert (reloc
->howto
!= 0);
1131 /* Handle of the OPCODE hash table. NULL means any use before
1132 m68k_ip_begin() will crash. */
1133 static struct hash_control
*op_hash
;
1135 /* Assemble an m68k instruction. */
1138 m68k_ip (char *instring
)
1141 register struct m68k_op
*opP
;
1142 register const struct m68k_incant
*opcode
;
1143 register const char *s
;
1144 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1145 char *pdot
, *pdotmove
;
1146 enum m68k_size siz1
, siz2
;
1150 struct m68k_op operands_backup
[6];
1151 LITTLENUM_TYPE words
[6];
1152 LITTLENUM_TYPE
*wordp
;
1153 unsigned long ok_arch
= 0;
1155 if (*instring
== ' ')
1156 instring
++; /* Skip leading whitespace. */
1158 /* Scan up to end of operation-code, which MUST end in end-of-string
1159 or exactly 1 space. */
1161 for (p
= instring
; *p
!= '\0'; p
++)
1171 the_ins
.error
= _("No operator");
1175 /* p now points to the end of the opcode name, probably whitespace.
1176 Make sure the name is null terminated by clobbering the
1177 whitespace, look it up in the hash table, then fix it back.
1178 Remove a dot, first, since the opcode tables have none. */
1181 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1182 *pdotmove
= pdotmove
[1];
1188 opcode
= (const struct m68k_incant
*) hash_find (op_hash
, instring
);
1193 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1194 *pdotmove
= pdotmove
[-1];
1201 the_ins
.error
= _("Unknown operator");
1205 /* Found a legitimate opcode, start matching operands. */
1209 if (opcode
->m_operands
== 0)
1211 char *old
= input_line_pointer
;
1213 input_line_pointer
= p
;
1214 /* Ahh - it's a motorola style psuedo op. */
1215 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1216 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1217 input_line_pointer
= old
;
1223 if (flag_mri
&& opcode
->m_opnum
== 0)
1225 /* In MRI mode, random garbage is allowed after an instruction
1226 which accepts no operands. */
1227 the_ins
.args
= opcode
->m_operands
;
1228 the_ins
.numargs
= opcode
->m_opnum
;
1229 the_ins
.numo
= opcode
->m_codenum
;
1230 the_ins
.opcode
[0] = getone (opcode
);
1231 the_ins
.opcode
[1] = gettwo (opcode
);
1235 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1237 p
= crack_operand (p
, opP
);
1241 the_ins
.error
= opP
->error
;
1246 opsfound
= opP
- &the_ins
.operands
[0];
1248 /* This ugly hack is to support the floating pt opcodes in their
1249 standard form. Essentially, we fake a first enty of type COP#1 */
1250 if (opcode
->m_operands
[0] == 'I')
1254 for (n
= opsfound
; n
> 0; --n
)
1255 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1257 memset (&the_ins
.operands
[0], '\0', sizeof (the_ins
.operands
[0]));
1258 the_ins
.operands
[0].mode
= CONTROL
;
1259 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1263 /* We've got the operands. Find an opcode that'll accept them. */
1266 /* If we didn't get the right number of ops, or we have no
1267 common model with this pattern then reject this pattern. */
1269 ok_arch
|= opcode
->m_arch
;
1270 if (opsfound
!= opcode
->m_opnum
1271 || ((opcode
->m_arch
& current_architecture
) == 0))
1277 /* Make a copy of the operands of this insn so that
1278 we can modify them safely, should we want to. */
1279 assert (opsfound
<= (int) ARRAY_SIZE (operands_backup
));
1280 for (i
= 0; i
< opsfound
; i
++)
1281 operands_backup
[i
] = the_ins
.operands
[i
];
1283 for (s
= opcode
->m_operands
, opP
= &operands_backup
[0];
1287 /* Warning: this switch is huge! */
1288 /* I've tried to organize the cases into this order:
1289 non-alpha first, then alpha by letter. Lower-case
1290 goes directly before uppercase counterpart. */
1291 /* Code with multiple case ...: gets sorted by the lowest
1292 case ... it belongs to. I hope this makes sense. */
1398 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1415 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1434 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1444 if (opP
->mode
!= IMMED
)
1446 else if (s
[1] == 'b'
1447 && ! isvar (&opP
->disp
)
1448 && (opP
->disp
.exp
.X_op
!= O_constant
1449 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1451 else if (s
[1] == 'B'
1452 && ! isvar (&opP
->disp
)
1453 && (opP
->disp
.exp
.X_op
!= O_constant
1454 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1456 else if (s
[1] == 'w'
1457 && ! isvar (&opP
->disp
)
1458 && (opP
->disp
.exp
.X_op
!= O_constant
1459 || ! isword (opP
->disp
.exp
.X_add_number
)))
1461 else if (s
[1] == 'W'
1462 && ! isvar (&opP
->disp
)
1463 && (opP
->disp
.exp
.X_op
!= O_constant
1464 || ! issword (opP
->disp
.exp
.X_add_number
)))
1470 if (opP
->mode
!= IMMED
)
1475 if (opP
->mode
== AREG
1476 || opP
->mode
== CONTROL
1477 || opP
->mode
== FPREG
1478 || opP
->mode
== IMMED
1479 || opP
->mode
== REGLST
1480 || (opP
->mode
!= ABSL
1482 || opP
->reg
== ZPC
)))
1487 if (opP
->mode
== CONTROL
1488 || opP
->mode
== FPREG
1489 || opP
->mode
== REGLST
1490 || opP
->mode
== IMMED
1491 || (opP
->mode
!= ABSL
1493 || opP
->reg
== ZPC
)))
1521 if (opP
->mode
== CONTROL
1522 || opP
->mode
== FPREG
1523 || opP
->mode
== REGLST
)
1528 if (opP
->mode
!= AINC
)
1533 if (opP
->mode
!= ADEC
)
1583 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1604 case '~': /* For now! (JF FOO is this right?) */
1626 if (opP
->mode
!= CONTROL
1627 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1632 if (opP
->mode
!= AREG
)
1637 if (opP
->mode
!= AINDR
)
1642 if (opP
->mode
!= AINDR
&& opP
->mode
!= AINC
&& opP
->mode
!= ADEC
1643 && (opP
->mode
!= DISP
1645 || opP
->reg
> ADDR7
))
1650 if (opP
->mode
!= ABSL
1652 && strncmp (instring
, "jbsr", 4) == 0))
1675 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1680 if (opP
->mode
!= DISP
1682 || opP
->reg
> ADDR7
)
1687 if (opP
->mode
!= DREG
)
1692 if (opP
->reg
!= ACC
)
1697 if (opP
->reg
!= ACC
&& opP
->reg
!= ACC1
1698 && opP
->reg
!= ACC2
&& opP
->reg
!= ACC3
)
1703 if (opP
->mode
!= FPREG
)
1708 if (opP
->reg
!= MACSR
)
1713 if (opP
->reg
!= ACCEXT01
&& opP
->reg
!= ACCEXT23
)
1718 if (opP
->reg
!= MASK
)
1723 if (opP
->mode
!= CONTROL
1730 if (opP
->mode
!= LSH
&& opP
->mode
!= RSH
)
1735 if (opP
->mode
!= CONTROL
1737 || opP
->reg
> last_movec_reg
1742 const enum m68k_register
*rp
;
1744 for (rp
= control_regs
; *rp
; rp
++)
1745 if (*rp
== opP
->reg
)
1753 if (opP
->mode
!= IMMED
)
1759 if (opP
->mode
== DREG
1760 || opP
->mode
== AREG
1761 || opP
->mode
== FPREG
)
1770 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1773 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1776 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1784 else if (opP
->mode
== CONTROL
)
1793 opP
->mask
= 1 << 24;
1796 opP
->mask
= 1 << 25;
1799 opP
->mask
= 1 << 26;
1808 else if (opP
->mode
!= REGLST
)
1810 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
1812 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
1817 if (opP
->mode
!= IMMED
)
1819 else if (opP
->disp
.exp
.X_op
!= O_constant
1820 || ! issbyte (opP
->disp
.exp
.X_add_number
))
1822 else if (! m68k_quick
1823 && instring
[3] != 'q'
1824 && instring
[4] != 'q')
1829 if (opP
->mode
!= DREG
1830 && opP
->mode
!= IMMED
1831 && opP
->mode
!= ABSL
)
1836 if (opP
->mode
!= IMMED
)
1838 else if (opP
->disp
.exp
.X_op
!= O_constant
1839 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
1841 else if (! m68k_quick
1842 && (strncmp (instring
, "add", 3) == 0
1843 || strncmp (instring
, "sub", 3) == 0)
1844 && instring
[3] != 'q')
1849 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1854 if (opP
->mode
!= AINDR
1855 && (opP
->mode
!= BASE
1857 && opP
->reg
!= ZADDR0
)
1858 || opP
->disp
.exp
.X_op
!= O_absent
1859 || ((opP
->index
.reg
< DATA0
1860 || opP
->index
.reg
> DATA7
)
1861 && (opP
->index
.reg
< ADDR0
1862 || opP
->index
.reg
> ADDR7
))
1863 || opP
->index
.size
!= SIZE_UNSPEC
1864 || opP
->index
.scale
!= 1))
1869 if (opP
->mode
!= CONTROL
1870 || ! (opP
->reg
== FPI
1872 || opP
->reg
== FPC
))
1877 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
1882 if (opP
->mode
!= IMMED
)
1884 else if (opP
->disp
.exp
.X_op
!= O_constant
1885 || TRUNC (opP
->disp
.exp
.X_add_number
) > 7)
1890 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
1895 if (opP
->mode
!= IMMED
)
1897 else if (opP
->disp
.exp
.X_op
!= O_constant
1898 || (TRUNC (opP
->disp
.exp
.X_add_number
) != 0xffffffff
1899 && TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 6))
1903 /* JF these are out of order. We could put them
1904 in order if we were willing to put up with
1905 bunches of #ifdef m68851s in the code.
1907 Don't forget that you need these operands
1908 to use 68030 MMU instructions. */
1910 /* Memory addressing mode used by pflushr. */
1912 if (opP
->mode
== CONTROL
1913 || opP
->mode
== FPREG
1914 || opP
->mode
== DREG
1915 || opP
->mode
== AREG
1916 || opP
->mode
== REGLST
)
1918 /* We should accept immediate operands, but they
1919 supposedly have to be quad word, and we don't
1920 handle that. I would like to see what a Motorola
1921 assembler does before doing something here. */
1922 if (opP
->mode
== IMMED
)
1927 if (opP
->mode
!= CONTROL
1928 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1933 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
1938 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
1943 if (opP
->mode
!= CONTROL
1946 && opP
->reg
!= SCC
))
1951 if (opP
->mode
!= CONTROL
1957 if (opP
->mode
!= CONTROL
1960 && opP
->reg
!= CRP
))
1984 if (opP
->mode
!= CONTROL
1985 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
1986 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
1991 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
1996 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
2001 if (opP
->mode
!= CONTROL
2010 if (opP
->mode
!= ABSL
)
2015 if (opP
->reg
< DATA0L
|| opP
->reg
> ADDR7U
)
2017 /* FIXME: kludge instead of fixing parser:
2018 upper/lower registers are *not* CONTROL
2019 registers, but ordinary ones. */
2020 if ((opP
->reg
>= DATA0L
&& opP
->reg
<= DATA7L
)
2021 || (opP
->reg
>= DATA0U
&& opP
->reg
<= DATA7U
))
2028 if (!(opP
->mode
== AINDR
2029 || (opP
->mode
== DISP
2030 && !(opP
->reg
== PC
|| opP
->reg
== ZPC
))))
2035 if (!(opP
->mode
== AINDR
|| opP
->mode
== DISP
))
2047 /* Since we have found the correct instruction, copy
2048 in the modifications that we may have made. */
2050 for (i
= 0; i
< opsfound
; i
++)
2051 the_ins
.operands
[i
] = operands_backup
[i
];
2057 opcode
= opcode
->m_next
;
2062 && !(ok_arch
& current_architecture
))
2064 const struct m68k_cpu
*cpu
;
2067 char *buf
= xmalloc (space
+ 1);
2071 the_ins
.error
= buf
;
2072 /* Make sure there's a NUL at the end of the buffer -- strncpy
2073 won't write one when it runs out of buffer */
2075 #define APPEND(STRING) \
2076 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2078 APPEND (_("invalid instruction for this architecture; needs "));
2082 APPEND (_("ColdFire ISA_A"));
2085 APPEND (_("ColdFire hardware divide"));
2088 APPEND (_("ColdFire ISA_A+"));
2091 APPEND (_("ColdFire ISA_B"));
2094 APPEND (_("ColdFire fpu"));
2097 APPEND (_("M68K fpu"));
2100 APPEND (_("M68K mmu"));
2103 APPEND (_("68020 or higher"));
2106 APPEND (_("68000 or higher"));
2109 APPEND (_("68010 or higher"));
2117 for (cpu
= m68k_cpus
; cpu
->name
; cpu
++)
2118 if (!cpu
->alias
&& (cpu
->arch
& ok_arch
))
2120 const struct m68k_cpu
*alias
;
2121 int seen_master
= 0;
2127 for (alias
= cpu
; alias
!= m68k_cpus
; alias
--)
2128 if (alias
[-1].alias
>= 0)
2130 for (; !seen_master
|| alias
->alias
> 0; alias
++)
2140 APPEND (alias
->name
);
2153 /* we ran out of space, so replace the end of the list
2158 strcpy (buf
, " ...");
2162 the_ins
.error
= _("operands mismatch");
2169 /* Now assemble it. */
2170 the_ins
.args
= opcode
->m_operands
;
2171 the_ins
.numargs
= opcode
->m_opnum
;
2172 the_ins
.numo
= opcode
->m_codenum
;
2173 the_ins
.opcode
[0] = getone (opcode
);
2174 the_ins
.opcode
[1] = gettwo (opcode
);
2176 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2178 /* This switch is a doozy.
2179 Watch the first step; its a big one! */
2212 tmpreg
= 0x3c; /* 7.4 */
2213 if (strchr ("bwl", s
[1]))
2214 nextword
= get_num (&opP
->disp
, 90);
2216 nextword
= get_num (&opP
->disp
, 0);
2217 if (isvar (&opP
->disp
))
2218 add_fix (s
[1], &opP
->disp
, 0, 0);
2222 if (!isbyte (nextword
))
2223 opP
->error
= _("operand out of range");
2228 if (!isword (nextword
))
2229 opP
->error
= _("operand out of range");
2234 if (!issword (nextword
))
2235 opP
->error
= _("operand out of range");
2240 addword (nextword
>> 16);
2267 /* We gotta put out some float. */
2268 if (op (&opP
->disp
) != O_big
)
2273 /* Can other cases happen here? */
2274 if (op (&opP
->disp
) != O_constant
)
2277 val
= (valueT
) offs (&opP
->disp
);
2281 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2282 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2286 offs (&opP
->disp
) = gencnt
;
2288 if (offs (&opP
->disp
) > 0)
2290 if (offs (&opP
->disp
) > baseo
)
2292 as_warn (_("Bignum too big for %c format; truncated"),
2294 offs (&opP
->disp
) = baseo
;
2296 baseo
-= offs (&opP
->disp
);
2299 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
2300 offs (&opP
->disp
)--;
2305 gen_to_words (words
, baseo
, (long) outro
);
2306 for (wordp
= words
; baseo
--; wordp
++)
2310 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2313 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2316 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2319 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2322 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2326 nextword
= get_num (&opP
->disp
, 90);
2328 /* Convert mode 5 addressing with a zero offset into
2329 mode 2 addressing to reduce the instruction size by a
2331 if (! isvar (&opP
->disp
)
2333 && (opP
->disp
.size
== SIZE_UNSPEC
)
2334 && (opP
->reg
>= ADDR0
)
2335 && (opP
->reg
<= ADDR7
))
2337 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2342 && ! isvar (&opP
->disp
)
2345 opP
->disp
.exp
.X_op
= O_symbol
;
2346 opP
->disp
.exp
.X_add_symbol
=
2347 section_symbol (absolute_section
);
2350 /* Force into index mode. Hope this works. */
2352 /* We do the first bit for 32-bit displacements, and the
2353 second bit for 16 bit ones. It is possible that we
2354 should make the default be WORD instead of LONG, but
2355 I think that'd break GCC, so we put up with a little
2356 inefficiency for the sake of working output. */
2358 if (!issword (nextword
)
2359 || (isvar (&opP
->disp
)
2360 && ((opP
->disp
.size
== SIZE_UNSPEC
2361 && flag_short_refs
== 0
2362 && cpu_of_arch (current_architecture
) >= m68020
2363 && ! arch_coldfire_p (current_architecture
))
2364 || opP
->disp
.size
== SIZE_LONG
)))
2366 if (cpu_of_arch (current_architecture
) < m68020
2367 || arch_coldfire_p (current_architecture
))
2369 _("displacement too large for this architecture; needs 68020 or higher");
2371 tmpreg
= 0x3B; /* 7.3 */
2373 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2374 if (isvar (&opP
->disp
))
2378 if (opP
->disp
.size
== SIZE_LONG
2380 /* If the displacement needs pic
2381 relocation it cannot be relaxed. */
2382 || opP
->disp
.pic_reloc
!= pic_none
2387 add_fix ('l', &opP
->disp
, 1, 2);
2391 add_frag (adds (&opP
->disp
),
2392 SEXT (offs (&opP
->disp
)),
2393 TAB (PCREL1632
, SZ_UNDEF
));
2400 add_fix ('l', &opP
->disp
, 0, 0);
2405 addword (nextword
>> 16);
2410 tmpreg
= 0x3A; /* 7.2 */
2412 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2414 if (isvar (&opP
->disp
))
2418 add_fix ('w', &opP
->disp
, 1, 0);
2421 add_fix ('w', &opP
->disp
, 0, 0);
2431 baseo
= get_num (&opP
->disp
, 90);
2432 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2433 outro
= get_num (&opP
->odisp
, 90);
2434 /* Figure out the `addressing mode'.
2435 Also turn on the BASE_DISABLE bit, if needed. */
2436 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2438 tmpreg
= 0x3b; /* 7.3 */
2439 if (opP
->reg
== ZPC
)
2442 else if (opP
->reg
== 0)
2445 tmpreg
= 0x30; /* 6.garbage */
2447 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2450 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2453 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2455 siz1
= opP
->disp
.size
;
2456 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2457 siz2
= opP
->odisp
.size
;
2461 /* Index register stuff. */
2462 if (opP
->index
.reg
!= 0
2463 && opP
->index
.reg
>= DATA
2464 && opP
->index
.reg
<= ADDR7
)
2466 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2468 if (opP
->index
.size
== SIZE_LONG
2469 || (opP
->index
.size
== SIZE_UNSPEC
2470 && m68k_index_width_default
== SIZE_LONG
))
2473 if ((opP
->index
.scale
!= 1
2474 && cpu_of_arch (current_architecture
) < m68020
)
2475 || (opP
->index
.scale
== 8
2476 && (arch_coldfire_p (current_architecture
)
2477 && !arch_coldfire_fpu (current_architecture
))))
2480 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2483 if (arch_coldfire_p (current_architecture
)
2484 && opP
->index
.size
== SIZE_WORD
)
2485 opP
->error
= _("invalid index size for coldfire");
2487 switch (opP
->index
.scale
)
2504 GET US OUT OF HERE! */
2506 /* Must be INDEX, with an index register. Address
2507 register cannot be ZERO-PC, and either :b was
2508 forced, or we know it will fit. For a 68000 or
2509 68010, force this mode anyways, because the
2510 larger modes aren't supported. */
2511 if (opP
->mode
== BASE
2512 && ((opP
->reg
>= ADDR0
2513 && opP
->reg
<= ADDR7
)
2516 if (siz1
== SIZE_BYTE
2517 || cpu_of_arch (current_architecture
) < m68020
2518 || arch_coldfire_p (current_architecture
)
2519 || (siz1
== SIZE_UNSPEC
2520 && ! isvar (&opP
->disp
)
2521 && issbyte (baseo
)))
2523 nextword
+= baseo
& 0xff;
2525 if (isvar (&opP
->disp
))
2527 /* Do a byte relocation. If it doesn't
2528 fit (possible on m68000) let the
2529 fixup processing complain later. */
2531 add_fix ('B', &opP
->disp
, 1, 1);
2533 add_fix ('B', &opP
->disp
, 0, 0);
2535 else if (siz1
!= SIZE_BYTE
)
2537 if (siz1
!= SIZE_UNSPEC
)
2538 as_warn (_("Forcing byte displacement"));
2539 if (! issbyte (baseo
))
2540 opP
->error
= _("byte displacement out of range");
2545 else if (siz1
== SIZE_UNSPEC
2547 && isvar (&opP
->disp
)
2548 && subs (&opP
->disp
) == NULL
2550 /* If the displacement needs pic
2551 relocation it cannot be relaxed. */
2552 && opP
->disp
.pic_reloc
== pic_none
2556 /* The code in md_convert_frag_1 needs to be
2557 able to adjust nextword. Call frag_grow
2558 to ensure that we have enough space in
2559 the frag obstack to make all the bytes
2562 nextword
+= baseo
& 0xff;
2564 add_frag (adds (&opP
->disp
),
2565 SEXT (offs (&opP
->disp
)),
2566 TAB (PCINDEX
, SZ_UNDEF
));
2574 nextword
|= 0x40; /* No index reg. */
2575 if (opP
->index
.reg
>= ZDATA0
2576 && opP
->index
.reg
<= ZDATA7
)
2577 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2578 else if (opP
->index
.reg
>= ZADDR0
2579 || opP
->index
.reg
<= ZADDR7
)
2580 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2583 /* It isn't simple. */
2585 if (cpu_of_arch (current_architecture
) < m68020
2586 || arch_coldfire_p (current_architecture
))
2588 _("invalid operand mode for this architecture; needs 68020 or higher");
2591 /* If the guy specified a width, we assume that it is
2592 wide enough. Maybe it isn't. If so, we lose. */
2596 if (isvar (&opP
->disp
)
2598 : ! issword (baseo
))
2603 else if (! isvar (&opP
->disp
) && baseo
== 0)
2612 as_warn (_(":b not permitted; defaulting to :w"));
2622 /* Figure out inner displacement stuff. */
2623 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2625 if (cpu_of_arch (current_architecture
) & cpu32
)
2626 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2630 if (isvar (&opP
->odisp
)
2632 : ! issword (outro
))
2637 else if (! isvar (&opP
->odisp
) && outro
== 0)
2646 as_warn (_(":b not permitted; defaulting to :w"));
2655 if (opP
->mode
== POST
2656 && (nextword
& 0x40) == 0)
2661 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2663 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2664 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2666 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2668 if (siz1
== SIZE_LONG
)
2669 addword (baseo
>> 16);
2670 if (siz1
!= SIZE_UNSPEC
)
2673 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2674 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2675 if (siz2
== SIZE_LONG
)
2676 addword (outro
>> 16);
2677 if (siz2
!= SIZE_UNSPEC
)
2683 nextword
= get_num (&opP
->disp
, 90);
2684 switch (opP
->disp
.size
)
2689 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2691 tmpreg
= 0x38; /* 7.0 */
2695 if (isvar (&opP
->disp
)
2696 && !subs (&opP
->disp
)
2697 && adds (&opP
->disp
)
2699 /* If the displacement needs pic relocation it
2700 cannot be relaxed. */
2701 && opP
->disp
.pic_reloc
== pic_none
2704 && !strchr ("~%&$?", s
[0]))
2706 tmpreg
= 0x3A; /* 7.2 */
2707 add_frag (adds (&opP
->disp
),
2708 SEXT (offs (&opP
->disp
)),
2709 TAB (ABSTOPCREL
, SZ_UNDEF
));
2712 /* Fall through into long. */
2714 if (isvar (&opP
->disp
))
2715 add_fix ('l', &opP
->disp
, 0, 0);
2717 tmpreg
= 0x39;/* 7.1 mode */
2718 addword (nextword
>> 16);
2723 as_bad (_("unsupported byte value; use a different suffix"));
2727 if (isvar (&opP
->disp
))
2728 add_fix ('w', &opP
->disp
, 0, 0);
2730 tmpreg
= 0x38;/* 7.0 mode */
2738 as_bad (_("unknown/incorrect operand"));
2742 /* If s[0] is '4', then this is for the mac instructions
2743 that can have a trailing_ampersand set. If so, set 0x100
2744 bit on tmpreg so install_gen_operand can check for it and
2745 set the appropriate bit (word2, bit 5). */
2748 if (opP
->trailing_ampersand
)
2751 install_gen_operand (s
[1], tmpreg
);
2757 { /* JF: I hate floating point! */
2772 tmpreg
= get_num (&opP
->disp
, tmpreg
);
2773 if (isvar (&opP
->disp
))
2774 add_fix (s
[1], &opP
->disp
, 0, 0);
2777 case 'b': /* Danger: These do no check for
2778 certain types of overflow.
2780 if (!isbyte (tmpreg
))
2781 opP
->error
= _("out of range");
2782 insop (tmpreg
, opcode
);
2783 if (isvar (&opP
->disp
))
2784 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
2785 (opcode
->m_codenum
) * 2 + 1;
2788 if (!issbyte (tmpreg
))
2789 opP
->error
= _("out of range");
2790 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
2791 if (isvar (&opP
->disp
))
2792 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
2795 if (!isword (tmpreg
))
2796 opP
->error
= _("out of range");
2797 insop (tmpreg
, opcode
);
2798 if (isvar (&opP
->disp
))
2799 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2802 if (!issword (tmpreg
))
2803 opP
->error
= _("out of range");
2804 insop (tmpreg
, opcode
);
2805 if (isvar (&opP
->disp
))
2806 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2809 /* Because of the way insop works, we put these two out
2811 insop (tmpreg
, opcode
);
2812 insop (tmpreg
>> 16, opcode
);
2813 if (isvar (&opP
->disp
))
2814 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2821 install_operand (s
[1], tmpreg
);
2832 install_operand (s
[1], opP
->reg
- ADDR
);
2836 tmpreg
= get_num (&opP
->disp
, 90);
2840 add_fix ('B', &opP
->disp
, 1, -1);
2843 add_fix ('w', &opP
->disp
, 1, 0);
2848 if (! HAVE_LONG_BRANCH (current_architecture
))
2849 as_warn (_("Can't use long branches on 68000/68010/5200"));
2850 the_ins
.opcode
[0] |= 0xff;
2851 add_fix ('l', &opP
->disp
, 1, 0);
2856 if (subs (&opP
->disp
)) /* We can't relax it. */
2860 /* If the displacement needs pic relocation it cannot be
2862 if (opP
->disp
.pic_reloc
!= pic_none
)
2865 /* This could either be a symbol, or an absolute
2866 address. If it's an absolute address, turn it into
2867 an absolute jump right here and keep it out of the
2869 if (adds (&opP
->disp
) == 0)
2871 if (the_ins
.opcode
[0] == 0x6000) /* jbra */
2872 the_ins
.opcode
[0] = 0x4EF9;
2873 else if (the_ins
.opcode
[0] == 0x6100) /* jbsr */
2874 the_ins
.opcode
[0] = 0x4EB9;
2877 the_ins
.opcode
[0] ^= 0x0100;
2878 the_ins
.opcode
[0] |= 0x0006;
2881 add_fix ('l', &opP
->disp
, 0, 0);
2887 /* Now we know it's going into the relaxer. Now figure
2888 out which mode. We try in this order of preference:
2889 long branch, absolute jump, byte/word branches only. */
2890 if (HAVE_LONG_BRANCH (current_architecture
))
2891 add_frag (adds (&opP
->disp
),
2892 SEXT (offs (&opP
->disp
)),
2893 TAB (BRANCHBWL
, SZ_UNDEF
));
2894 else if (! flag_keep_pcrel
)
2896 if ((the_ins
.opcode
[0] == 0x6000)
2897 || (the_ins
.opcode
[0] == 0x6100))
2898 add_frag (adds (&opP
->disp
),
2899 SEXT (offs (&opP
->disp
)),
2900 TAB (BRABSJUNC
, SZ_UNDEF
));
2902 add_frag (adds (&opP
->disp
),
2903 SEXT (offs (&opP
->disp
)),
2904 TAB (BRABSJCOND
, SZ_UNDEF
));
2907 add_frag (adds (&opP
->disp
),
2908 SEXT (offs (&opP
->disp
)),
2909 TAB (BRANCHBW
, SZ_UNDEF
));
2912 if (isvar (&opP
->disp
))
2914 /* Check for DBcc instructions. We can relax them,
2915 but only if we have long branches and/or absolute
2917 if (((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2918 && (HAVE_LONG_BRANCH (current_architecture
)
2919 || (! flag_keep_pcrel
)))
2921 if (HAVE_LONG_BRANCH (current_architecture
))
2922 add_frag (adds (&opP
->disp
),
2923 SEXT (offs (&opP
->disp
)),
2924 TAB (DBCCLBR
, SZ_UNDEF
));
2926 add_frag (adds (&opP
->disp
),
2927 SEXT (offs (&opP
->disp
)),
2928 TAB (DBCCABSJ
, SZ_UNDEF
));
2931 add_fix ('w', &opP
->disp
, 1, 0);
2935 case 'C': /* Fixed size LONG coproc branches. */
2936 add_fix ('l', &opP
->disp
, 1, 0);
2940 case 'c': /* Var size Coprocesssor branches. */
2941 if (subs (&opP
->disp
) || (adds (&opP
->disp
) == 0))
2943 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2944 add_fix ('l', &opP
->disp
, 1, 0);
2949 add_frag (adds (&opP
->disp
),
2950 SEXT (offs (&opP
->disp
)),
2951 TAB (FBRANCH
, SZ_UNDEF
));
2958 case 'C': /* Ignore it. */
2961 case 'd': /* JF this is a kludge. */
2962 install_operand ('s', opP
->reg
- ADDR
);
2963 tmpreg
= get_num (&opP
->disp
, 90);
2964 if (!issword (tmpreg
))
2966 as_warn (_("Expression out of range, using 0"));
2973 install_operand (s
[1], opP
->reg
- DATA
);
2976 case 'e': /* EMAC ACCx, reg/reg. */
2977 install_operand (s
[1], opP
->reg
- ACC
);
2980 case 'E': /* Ignore it. */
2984 install_operand (s
[1], opP
->reg
- FP0
);
2987 case 'g': /* EMAC ACCEXTx. */
2988 install_operand (s
[1], opP
->reg
- ACCEXT01
);
2991 case 'G': /* Ignore it. */
2996 tmpreg
= opP
->reg
- COP0
;
2997 install_operand (s
[1], tmpreg
);
3000 case 'i': /* MAC/EMAC scale factor. */
3001 install_operand (s
[1], opP
->mode
== LSH
? 0x1 : 0x3);
3004 case 'J': /* JF foo. */
3143 install_operand (s
[1], tmpreg
);
3147 tmpreg
= get_num (&opP
->disp
, 55);
3148 install_operand (s
[1], tmpreg
& 0x7f);
3155 if (tmpreg
& 0x7FF0000)
3156 as_bad (_("Floating point register in register list"));
3157 insop (reverse_16_bits (tmpreg
), opcode
);
3161 if (tmpreg
& 0x700FFFF)
3162 as_bad (_("Wrong register in floating-point reglist"));
3163 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
3171 if (tmpreg
& 0x7FF0000)
3172 as_bad (_("Floating point register in register list"));
3173 insop (tmpreg
, opcode
);
3175 else if (s
[1] == '8')
3177 if (tmpreg
& 0x0FFFFFF)
3178 as_bad (_("incorrect register in reglist"));
3179 install_operand (s
[1], tmpreg
>> 24);
3183 if (tmpreg
& 0x700FFFF)
3184 as_bad (_("wrong register in floating-point reglist"));
3186 install_operand (s
[1], tmpreg
>> 16);
3191 install_operand (s
[1], get_num (&opP
->disp
, 60));
3195 tmpreg
= ((opP
->mode
== DREG
)
3196 ? 0x20 + (int) (opP
->reg
- DATA
)
3197 : (get_num (&opP
->disp
, 40) & 0x1F));
3198 install_operand (s
[1], tmpreg
);
3202 tmpreg
= get_num (&opP
->disp
, 10);
3205 install_operand (s
[1], tmpreg
);
3209 /* This depends on the fact that ADDR registers are eight
3210 more than their corresponding DATA regs, so the result
3211 will have the ADDR_REG bit set. */
3212 install_operand (s
[1], opP
->reg
- DATA
);
3216 if (opP
->mode
== AINDR
)
3217 install_operand (s
[1], opP
->reg
- DATA
);
3219 install_operand (s
[1], opP
->index
.reg
- DATA
);
3223 if (opP
->reg
== FPI
)
3225 else if (opP
->reg
== FPS
)
3227 else if (opP
->reg
== FPC
)
3231 install_operand (s
[1], tmpreg
);
3234 case 'S': /* Ignore it. */
3238 install_operand (s
[1], get_num (&opP
->disp
, 30));
3241 case 'U': /* Ignore it. */
3260 as_fatal (_("failed sanity check"));
3261 } /* switch on cache token. */
3262 install_operand (s
[1], tmpreg
);
3265 /* JF: These are out of order, I fear. */
3278 install_operand (s
[1], tmpreg
);
3304 install_operand (s
[1], tmpreg
);
3308 if (opP
->reg
== VAL
)
3327 install_operand (s
[1], tmpreg
);
3341 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3352 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3358 install_operand (s
[1], tmpreg
);
3361 know (opP
->reg
== PSR
);
3364 know (opP
->reg
== PCSR
);
3379 install_operand (s
[1], tmpreg
);
3382 tmpreg
= get_num (&opP
->disp
, 20);
3383 install_operand (s
[1], tmpreg
);
3385 case '_': /* used only for move16 absolute 32-bit address. */
3386 if (isvar (&opP
->disp
))
3387 add_fix ('l', &opP
->disp
, 0, 0);
3388 tmpreg
= get_num (&opP
->disp
, 90);
3389 addword (tmpreg
>> 16);
3390 addword (tmpreg
& 0xFFFF);
3393 install_operand (s
[1], opP
->reg
- DATA0L
);
3394 opP
->reg
-= (DATA0L
);
3395 opP
->reg
&= 0x0F; /* remove upper/lower bit. */
3398 tmpreg
= get_num (&opP
->disp
, 80);
3401 install_operand (s
[1], tmpreg
);
3408 /* By the time whe get here (FINALLY) the_ins contains the complete
3409 instruction, ready to be emitted. . . */
3413 reverse_16_bits (int in
)
3418 static int mask
[16] =
3420 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3421 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3423 for (n
= 0; n
< 16; n
++)
3426 out
|= mask
[15 - n
];
3429 } /* reverse_16_bits() */
3432 reverse_8_bits (int in
)
3437 static int mask
[8] =
3439 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3442 for (n
= 0; n
< 8; n
++)
3448 } /* reverse_8_bits() */
3450 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3451 (that value is chosen in the frag_var call in md_assemble). TYPE
3452 is the subtype of the frag to be generated; its primary type is
3453 rs_machine_dependent.
3455 The TYPE parameter is also used by md_convert_frag_1 and
3456 md_estimate_size_before_relax. The appropriate type of fixup will
3457 be emitted by md_convert_frag_1.
3459 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3461 install_operand (int mode
, int val
)
3466 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge. */
3469 the_ins
.opcode
[0] |= val
<< 9;
3472 the_ins
.opcode
[1] |= val
<< 12;
3475 the_ins
.opcode
[1] |= val
<< 6;
3478 the_ins
.opcode
[1] |= val
;
3481 the_ins
.opcode
[2] |= val
<< 12;
3484 the_ins
.opcode
[2] |= val
<< 6;
3487 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3488 three words long! */
3490 the_ins
.opcode
[2] |= val
;
3493 the_ins
.opcode
[1] |= val
<< 7;
3496 the_ins
.opcode
[1] |= val
<< 10;
3500 the_ins
.opcode
[1] |= val
<< 5;
3505 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3508 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3511 the_ins
.opcode
[0] |= val
= 0xff;
3514 the_ins
.opcode
[0] |= val
<< 9;
3517 the_ins
.opcode
[1] |= val
;
3520 the_ins
.opcode
[1] |= val
;
3521 the_ins
.numo
++; /* What a hack. */
3524 the_ins
.opcode
[1] |= val
<< 4;
3532 the_ins
.opcode
[0] |= (val
<< 6);
3535 the_ins
.opcode
[1] = (val
>> 16);
3536 the_ins
.opcode
[2] = val
& 0xffff;
3539 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3540 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3541 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3543 case 'n': /* MAC/EMAC Rx on !load. */
3544 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3545 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3546 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3548 case 'o': /* MAC/EMAC Rx on load. */
3549 the_ins
.opcode
[1] |= val
<< 12;
3550 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3552 case 'M': /* MAC/EMAC Ry on !load. */
3553 the_ins
.opcode
[0] |= (val
& 0xF);
3554 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3556 case 'N': /* MAC/EMAC Ry on load. */
3557 the_ins
.opcode
[1] |= (val
& 0xF);
3558 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3561 the_ins
.opcode
[1] |= ((val
!= 1) << 10);
3564 the_ins
.opcode
[0] |= ((val
& 0x3) << 9);
3567 the_ins
.opcode
[0] |= ((val
& 0x3) << 0);
3569 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3570 the_ins
.opcode
[0] |= ((~val
& 0x1) << 7);
3571 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3573 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3574 the_ins
.opcode
[0] |= ((val
& 0x1) << 7);
3575 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3578 the_ins
.opcode
[1] |= ((val
& 0x3) << 9);
3581 the_ins
.opcode
[0] |= (val
& 0x1) <<10;
3585 as_fatal (_("failed sanity check."));
3590 install_gen_operand (int mode
, int val
)
3594 case '/': /* Special for mask loads for mac/msac insns with
3595 possible mask; trailing_ampersend set in bit 8. */
3596 the_ins
.opcode
[0] |= (val
& 0x3f);
3597 the_ins
.opcode
[1] |= (((val
& 0x100) >> 8) << 5);
3600 the_ins
.opcode
[0] |= val
;
3603 /* This is a kludge!!! */
3604 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3613 the_ins
.opcode
[0] |= val
;
3615 /* more stuff goes here. */
3617 as_fatal (_("failed sanity check."));
3621 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3622 then deal with the bitfield hack. */
3625 crack_operand (char *str
, struct m68k_op
*opP
)
3627 register int parens
;
3629 register char *beg_str
;
3637 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3643 else if (*str
== ')')
3647 opP
->error
= _("Extra )");
3653 if (flag_mri
&& *str
== '\'')
3654 inquote
= ! inquote
;
3656 if (!*str
&& parens
)
3658 opP
->error
= _("Missing )");
3663 if (m68k_ip_op (beg_str
, opP
) != 0)
3670 c
= *++str
; /* JF bitfield hack. */
3675 as_bad (_("Missing operand"));
3678 /* Detect MRI REG symbols and convert them to REGLSTs. */
3679 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
3682 opP
->mask
= ~(int)opP
->reg
;
3689 /* This is the guts of the machine-dependent assembler. STR points to a
3690 machine dependent instruction. This function is supposed to emit
3691 the frags/bytes it assembles to.
3695 insert_reg (const char *regname
, int regnum
)
3700 #ifdef REGISTER_PREFIX
3701 if (!flag_reg_prefix_optional
)
3703 buf
[0] = REGISTER_PREFIX
;
3704 strcpy (buf
+ 1, regname
);
3709 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
3710 &zero_address_frag
));
3712 for (i
= 0; regname
[i
]; i
++)
3713 buf
[i
] = TOUPPER (regname
[i
]);
3716 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
3717 &zero_address_frag
));
3726 static const struct init_entry init_table
[] =
3786 { "accext01", ACCEXT01
},
3787 { "accext23", ACCEXT23
},
3791 /* Control registers. */
3792 { "sfc", SFC
}, /* Source Function Code. */
3794 { "dfc", DFC
}, /* Destination Function Code. */
3796 { "cacr", CACR
}, /* Cache Control Register. */
3797 { "caar", CAAR
}, /* Cache Address Register. */
3799 { "usp", USP
}, /* User Stack Pointer. */
3800 { "vbr", VBR
}, /* Vector Base Register. */
3801 { "msp", MSP
}, /* Master Stack Pointer. */
3802 { "isp", ISP
}, /* Interrupt Stack Pointer. */
3804 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0. */
3805 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1. */
3806 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0. */
3807 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1. */
3809 /* 68ec040 versions of same */
3810 { "iacr0", ITT0
}, /* Instruction Access Control Register 0. */
3811 { "iacr1", ITT1
}, /* Instruction Access Control Register 0. */
3812 { "dacr0", DTT0
}, /* Data Access Control Register 0. */
3813 { "dacr1", DTT1
}, /* Data Access Control Register 0. */
3815 /* Coldfire versions of same. The ColdFire programmer's reference
3816 manual indicated that the order is 2,3,0,1, but Ken Rose
3817 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3818 { "acr0", ACR0
}, /* Access Control Unit 0. */
3819 { "acr1", ACR1
}, /* Access Control Unit 1. */
3820 { "acr2", ACR2
}, /* Access Control Unit 2. */
3821 { "acr3", ACR3
}, /* Access Control Unit 3. */
3823 { "tc", TC
}, /* MMU Translation Control Register. */
3827 { "mmusr", MMUSR
}, /* MMU Status Register. */
3828 { "srp", SRP
}, /* User Root Pointer. */
3829 { "urp", URP
}, /* Supervisor Root Pointer. */
3832 { "mmubar", MMUBAR
},
3835 { "rombar", ROMBAR
}, /* ROM Base Address Register. */
3836 { "rambar0", RAMBAR0
}, /* ROM Base Address Register. */
3837 { "rambar1", RAMBAR1
}, /* ROM Base Address Register. */
3838 { "mbar", MBAR
}, /* Module Base Address Register. */
3840 { "mbar0", MBAR0
}, /* mcfv4e registers. */
3841 { "mbar1", MBAR1
}, /* mcfv4e registers. */
3842 { "rombar0", ROMBAR0
}, /* mcfv4e registers. */
3843 { "rombar1", ROMBAR1
}, /* mcfv4e registers. */
3844 { "mpcr", MPCR
}, /* mcfv4e registers. */
3845 { "edrambar", EDRAMBAR
}, /* mcfv4e registers. */
3846 { "secmbar", SECMBAR
}, /* mcfv4e registers. */
3847 { "asid", TC
}, /* mcfv4e registers. */
3848 { "mmubar", BUSCR
}, /* mcfv4e registers. */
3849 { "pcr1u0", PCR1U0
}, /* mcfv4e registers. */
3850 { "pcr1l0", PCR1L0
}, /* mcfv4e registers. */
3851 { "pcr2u0", PCR2U0
}, /* mcfv4e registers. */
3852 { "pcr2l0", PCR2L0
}, /* mcfv4e registers. */
3853 { "pcr3u0", PCR3U0
}, /* mcfv4e registers. */
3854 { "pcr3l0", PCR3L0
}, /* mcfv4e registers. */
3855 { "pcr1u1", PCR1U1
}, /* mcfv4e registers. */
3856 { "pcr1l1", PCR1L1
}, /* mcfv4e registers. */
3857 { "pcr2u1", PCR2U1
}, /* mcfv4e registers. */
3858 { "pcr2l1", PCR2L1
}, /* mcfv4e registers. */
3859 { "pcr3u1", PCR3U1
}, /* mcfv4e registers. */
3860 { "pcr3l1", PCR3L1
}, /* mcfv4e registers. */
3862 { "flashbar", FLASHBAR
}, /* mcf528x registers. */
3863 { "rambar", RAMBAR
}, /* mcf528x registers. */
3865 { "mbar2", MBAR2
}, /* mcf5249 registers. */
3867 { "cac", CAC
}, /* fido registers. */
3868 { "mbb", MBB
}, /* fido registers. */
3869 /* End of control registers. */
3903 /* 68ec030 versions of same. */
3906 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3909 /* Suppressed data and address registers. */
3927 /* Upper and lower data and address registers, used by macw and msacw. */
3968 init_regtable (void)
3971 for (i
= 0; init_table
[i
].name
; i
++)
3972 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
3976 md_assemble (char *str
)
3983 int shorts_this_frag
;
3986 if (!selected_cpu
&& !selected_arch
)
3988 /* We've not selected an architecture yet. Set the default
3989 now. We do this lazily so that an initial .cpu or .arch directive
3991 if (!m68k_set_cpu (TARGET_CPU
, 1, 1))
3992 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU
);
3997 /* In MRI mode, the instruction and operands are separated by a
3998 space. Anything following the operands is a comment. The label
3999 has already been removed. */
4007 for (s
= str
; *s
!= '\0'; s
++)
4009 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
4027 inquote
= ! inquote
;
4032 memset (&the_ins
, '\0', sizeof (the_ins
));
4037 for (n
= 0; n
< the_ins
.numargs
; n
++)
4038 if (the_ins
.operands
[n
].error
)
4040 er
= the_ins
.operands
[n
].error
;
4046 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
4050 /* If there is a current label, record that it marks an instruction. */
4051 if (current_label
!= NULL
)
4053 current_label
->text
= 1;
4054 current_label
= NULL
;
4058 /* Tie dwarf2 debug info to the address at the start of the insn. */
4059 dwarf2_emit_insn (0);
4062 if (the_ins
.nfrag
== 0)
4064 /* No frag hacking involved; just put it out. */
4065 toP
= frag_more (2 * the_ins
.numo
);
4066 fromP
= &the_ins
.opcode
[0];
4067 for (m
= the_ins
.numo
; m
; --m
)
4069 md_number_to_chars (toP
, (long) (*fromP
), 2);
4073 /* Put out symbol-dependent info. */
4074 for (m
= 0; m
< the_ins
.nrel
; m
++)
4076 switch (the_ins
.reloc
[m
].wid
)
4095 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4096 the_ins
.reloc
[m
].wid
);
4099 fixP
= fix_new_exp (frag_now
,
4100 ((toP
- frag_now
->fr_literal
)
4101 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4103 &the_ins
.reloc
[m
].exp
,
4104 the_ins
.reloc
[m
].pcrel
,
4105 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
4106 the_ins
.reloc
[m
].pic_reloc
));
4107 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4108 if (the_ins
.reloc
[m
].wid
== 'B')
4109 fixP
->fx_signed
= 1;
4114 /* There's some frag hacking. */
4116 /* Calculate the max frag size. */
4119 wid
= 2 * the_ins
.fragb
[0].fragoff
;
4120 for (n
= 1; n
< the_ins
.nfrag
; n
++)
4121 wid
+= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4122 /* frag_var part. */
4124 /* Make sure the whole insn fits in one chunk, in particular that
4125 the var part is attached, as we access one byte before the
4126 variable frag for byte branches. */
4130 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
4135 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
4137 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4138 toP
= frag_more (wid
);
4140 shorts_this_frag
= 0;
4141 for (m
= wid
/ 2; m
; --m
)
4143 md_number_to_chars (toP
, (long) (*fromP
), 2);
4148 for (m
= 0; m
< the_ins
.nrel
; m
++)
4150 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
4152 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
4155 wid
= the_ins
.reloc
[m
].wid
;
4158 the_ins
.reloc
[m
].wid
= 0;
4159 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4161 fixP
= fix_new_exp (frag_now
,
4162 ((toP
- frag_now
->fr_literal
)
4163 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4165 &the_ins
.reloc
[m
].exp
,
4166 the_ins
.reloc
[m
].pcrel
,
4167 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4168 the_ins
.reloc
[m
].pic_reloc
));
4169 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4171 (void) frag_var (rs_machine_dependent
, 10, 0,
4172 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
4173 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
4175 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4176 shorts_this_frag
= 0;
4179 toP
= frag_more (n
* 2);
4182 md_number_to_chars (toP
, (long) (*fromP
), 2);
4188 for (m
= 0; m
< the_ins
.nrel
; m
++)
4192 wid
= the_ins
.reloc
[m
].wid
;
4195 the_ins
.reloc
[m
].wid
= 0;
4196 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4198 fixP
= fix_new_exp (frag_now
,
4199 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
4200 - shorts_this_frag
* 2),
4202 &the_ins
.reloc
[m
].exp
,
4203 the_ins
.reloc
[m
].pcrel
,
4204 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4205 the_ins
.reloc
[m
].pic_reloc
));
4206 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4210 /* Comparison function used by qsort to rank the opcode entries by name. */
4213 m68k_compare_opcode (const void * v1
, const void * v2
)
4215 struct m68k_opcode
* op1
, * op2
;
4221 op1
= *(struct m68k_opcode
**) v1
;
4222 op2
= *(struct m68k_opcode
**) v2
;
4224 /* Compare the two names. If different, return the comparison.
4225 If the same, return the order they are in the opcode table. */
4226 ret
= strcmp (op1
->name
, op2
->name
);
4237 const struct m68k_opcode
*ins
;
4238 struct m68k_incant
*hack
, *slak
;
4239 const char *retval
= 0; /* Empty string, or error msg text. */
4242 /* Set up hash tables with 68000 instructions.
4243 similar to what the vax assembler does. */
4244 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4245 a copy of it at runtime, adding in the information we want but isn't
4246 there. I think it'd be better to have an awk script hack the table
4247 at compile time. Or even just xstr the table and use it as-is. But
4248 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4253 flag_reg_prefix_optional
= 1;
4255 if (! m68k_rel32_from_cmdline
)
4259 /* First sort the opcode table into alphabetical order to seperate
4260 the order that the assembler wants to see the opcodes from the
4261 order that the disassembler wants to see them. */
4262 m68k_sorted_opcodes
= xmalloc (m68k_numopcodes
* sizeof (* m68k_sorted_opcodes
));
4263 if (!m68k_sorted_opcodes
)
4264 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4265 m68k_numopcodes
* ((int) sizeof (* m68k_sorted_opcodes
)));
4267 for (i
= m68k_numopcodes
; i
--;)
4268 m68k_sorted_opcodes
[i
] = m68k_opcodes
+ i
;
4270 qsort (m68k_sorted_opcodes
, m68k_numopcodes
,
4271 sizeof (m68k_sorted_opcodes
[0]), m68k_compare_opcode
);
4273 op_hash
= hash_new ();
4275 obstack_begin (&robyn
, 4000);
4276 for (i
= 0; i
< m68k_numopcodes
; i
++)
4278 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4281 ins
= m68k_sorted_opcodes
[i
];
4283 /* We *could* ignore insns that don't match our
4284 arch here by just leaving them out of the hash. */
4285 slak
->m_operands
= ins
->args
;
4286 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
4287 slak
->m_arch
= ins
->arch
;
4288 slak
->m_opcode
= ins
->opcode
;
4289 /* This is kludgey. */
4290 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
4291 if (i
+ 1 != m68k_numopcodes
4292 && !strcmp (ins
->name
, m68k_sorted_opcodes
[i
+ 1]->name
))
4294 slak
->m_next
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4299 slak
= slak
->m_next
;
4303 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
4305 as_fatal (_("Internal Error: Can't hash %s: %s"), ins
->name
, retval
);
4308 for (i
= 0; i
< m68k_numaliases
; i
++)
4310 const char *name
= m68k_opcode_aliases
[i
].primary
;
4311 const char *alias
= m68k_opcode_aliases
[i
].alias
;
4312 PTR val
= hash_find (op_hash
, name
);
4315 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4316 retval
= hash_insert (op_hash
, alias
, val
);
4318 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4321 /* In MRI mode, all unsized branches are variable sized. Normally,
4322 they are word sized. */
4325 static struct m68k_opcode_alias mri_aliases
[] =
4346 i
< (int) (sizeof mri_aliases
/ sizeof mri_aliases
[0]);
4349 const char *name
= mri_aliases
[i
].primary
;
4350 const char *alias
= mri_aliases
[i
].alias
;
4351 PTR val
= hash_find (op_hash
, name
);
4354 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4355 retval
= hash_jam (op_hash
, alias
, val
);
4357 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4361 for (i
= 0; i
< (int) sizeof (notend_table
); i
++)
4363 notend_table
[i
] = 0;
4364 alt_notend_table
[i
] = 0;
4367 notend_table
[','] = 1;
4368 notend_table
['{'] = 1;
4369 notend_table
['}'] = 1;
4370 alt_notend_table
['a'] = 1;
4371 alt_notend_table
['A'] = 1;
4372 alt_notend_table
['d'] = 1;
4373 alt_notend_table
['D'] = 1;
4374 alt_notend_table
['#'] = 1;
4375 alt_notend_table
['&'] = 1;
4376 alt_notend_table
['f'] = 1;
4377 alt_notend_table
['F'] = 1;
4378 #ifdef REGISTER_PREFIX
4379 alt_notend_table
[REGISTER_PREFIX
] = 1;
4382 /* We need to put '(' in alt_notend_table to handle
4383 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4384 alt_notend_table
['('] = 1;
4386 /* We need to put '@' in alt_notend_table to handle
4387 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4388 alt_notend_table
['@'] = 1;
4390 /* We need to put digits in alt_notend_table to handle
4391 bfextu %d0{24:1},%d0 */
4392 alt_notend_table
['0'] = 1;
4393 alt_notend_table
['1'] = 1;
4394 alt_notend_table
['2'] = 1;
4395 alt_notend_table
['3'] = 1;
4396 alt_notend_table
['4'] = 1;
4397 alt_notend_table
['5'] = 1;
4398 alt_notend_table
['6'] = 1;
4399 alt_notend_table
['7'] = 1;
4400 alt_notend_table
['8'] = 1;
4401 alt_notend_table
['9'] = 1;
4403 #ifndef MIT_SYNTAX_ONLY
4404 /* Insert pseudo ops, these have to go into the opcode table since
4405 gas expects pseudo ops to start with a dot. */
4409 while (mote_pseudo_table
[n
].poc_name
)
4411 hack
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4412 hash_insert (op_hash
,
4413 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
4414 hack
->m_operands
= 0;
4424 record_alignment (text_section
, 2);
4425 record_alignment (data_section
, 2);
4426 record_alignment (bss_section
, 2);
4431 /* This is called when a label is defined. */
4434 m68k_frob_label (symbolS
*sym
)
4436 struct label_line
*n
;
4438 n
= (struct label_line
*) xmalloc (sizeof *n
);
4441 as_where (&n
->file
, &n
->line
);
4447 dwarf2_emit_label (sym
);
4451 /* This is called when a value that is not an instruction is emitted. */
4454 m68k_flush_pending_output (void)
4456 current_label
= NULL
;
4459 /* This is called at the end of the assembly, when the final value of
4460 the label is known. We warn if this is a text symbol aligned at an
4464 m68k_frob_symbol (symbolS
*sym
)
4466 if (S_GET_SEGMENT (sym
) == reg_section
4467 && (int) S_GET_VALUE (sym
) < 0)
4469 S_SET_SEGMENT (sym
, absolute_section
);
4470 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
4472 else if ((S_GET_VALUE (sym
) & 1) != 0)
4474 struct label_line
*l
;
4476 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4478 if (l
->label
== sym
)
4481 as_warn_where (l
->file
, l
->line
,
4482 _("text label `%s' aligned to odd boundary"),
4490 /* This is called if we go in or out of MRI mode because of the .mri
4494 m68k_mri_mode_change (int on
)
4498 if (! flag_reg_prefix_optional
)
4500 flag_reg_prefix_optional
= 1;
4501 #ifdef REGISTER_PREFIX
4506 if (! m68k_rel32_from_cmdline
)
4511 if (! reg_prefix_optional_seen
)
4513 #ifdef REGISTER_PREFIX_OPTIONAL
4514 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
4516 flag_reg_prefix_optional
= 0;
4518 #ifdef REGISTER_PREFIX
4523 if (! m68k_rel32_from_cmdline
)
4528 /* Equal to MAX_PRECISION in atof-ieee.c. */
4529 #define MAX_LITTLENUMS 6
4531 /* Turn a string in input_line_pointer into a floating point constant
4532 of type TYPE, and store the appropriate bytes in *LITP. The number
4533 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4534 returned, or NULL on OK. */
4537 md_atof (int type
, char *litP
, int *sizeP
)
4540 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4541 LITTLENUM_TYPE
*wordP
;
4572 return _("Bad call to MD_ATOF()");
4574 t
= atof_ieee (input_line_pointer
, type
, words
);
4576 input_line_pointer
= t
;
4578 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4579 for (wordP
= words
; prec
--;)
4581 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
4582 litP
+= sizeof (LITTLENUM_TYPE
);
4588 md_number_to_chars (char *buf
, valueT val
, int n
)
4590 number_to_chars_bigendian (buf
, val
, n
);
4594 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4596 offsetT val
= *valP
;
4597 addressT upper_limit
;
4598 offsetT lower_limit
;
4600 /* This is unnecessary but it convinces the native rs6000 compiler
4601 to generate the code we want. */
4602 char *buf
= fixP
->fx_frag
->fr_literal
;
4603 buf
+= fixP
->fx_where
;
4604 /* End ibm compiler workaround. */
4608 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4614 memset (buf
, 0, fixP
->fx_size
);
4615 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4617 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4618 && !S_IS_DEFINED (fixP
->fx_addsy
)
4619 && !S_IS_WEAK (fixP
->fx_addsy
))
4620 S_SET_WEAK (fixP
->fx_addsy
);
4625 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4626 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4629 switch (fixP
->fx_size
)
4631 /* The cast to offsetT below are necessary to make code
4632 correct for machines where ints are smaller than offsetT. */
4636 lower_limit
= - (offsetT
) 0x80;
4639 *buf
++ = (val
>> 8);
4641 upper_limit
= 0x7fff;
4642 lower_limit
= - (offsetT
) 0x8000;
4645 *buf
++ = (val
>> 24);
4646 *buf
++ = (val
>> 16);
4647 *buf
++ = (val
>> 8);
4649 upper_limit
= 0x7fffffff;
4650 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* Avoid constant overflow. */
4653 BAD_CASE (fixP
->fx_size
);
4656 /* Fix up a negative reloc. */
4657 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4659 fixP
->fx_addsy
= fixP
->fx_subsy
;
4660 fixP
->fx_subsy
= NULL
;
4664 /* For non-pc-relative values, it's conceivable we might get something
4665 like "0xff" for a byte field. So extend the upper part of the range
4666 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4667 so that we can do any range checking at all. */
4668 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
4669 upper_limit
= upper_limit
* 2 + 1;
4671 if ((addressT
) val
> upper_limit
4672 && (val
> 0 || val
< lower_limit
))
4673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("value out of range"));
4675 /* A one byte PC-relative reloc means a short branch. We can't use
4676 a short branch with a value of 0 or -1, because those indicate
4677 different opcodes (branches with longer offsets). fixup_segment
4678 in write.c may have clobbered fx_pcrel, so we need to examine the
4681 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4682 && fixP
->fx_size
== 1
4683 && (fixP
->fx_addsy
== NULL
4684 || S_IS_DEFINED (fixP
->fx_addsy
))
4685 && (val
== 0 || val
== -1))
4686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("invalid byte branch offset"));
4689 /* *fragP has been relaxed to its final size, and now needs to have
4690 the bytes inside it modified to conform to the new size There is UGLY
4694 md_convert_frag_1 (fragS
*fragP
)
4699 /* Address in object code of the displacement. */
4700 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4702 /* Address in gas core of the place to store the displacement. */
4703 /* This convinces the native rs6000 compiler to generate the code we
4705 register char *buffer_address
= fragP
->fr_literal
;
4706 buffer_address
+= fragP
->fr_fix
;
4707 /* End ibm compiler workaround. */
4709 /* The displacement of the address, from current location. */
4710 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4711 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4713 switch (fragP
->fr_subtype
)
4715 case TAB (BRANCHBWL
, BYTE
):
4716 case TAB (BRABSJUNC
, BYTE
):
4717 case TAB (BRABSJCOND
, BYTE
):
4718 case TAB (BRANCHBW
, BYTE
):
4719 know (issbyte (disp
));
4721 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4722 _("short branch with zero offset: use :w"));
4723 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4724 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4725 fixP
->fx_pcrel_adjust
= -1;
4727 case TAB (BRANCHBWL
, SHORT
):
4728 case TAB (BRABSJUNC
, SHORT
):
4729 case TAB (BRABSJCOND
, SHORT
):
4730 case TAB (BRANCHBW
, SHORT
):
4731 fragP
->fr_opcode
[1] = 0x00;
4732 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4733 1, RELAX_RELOC_PC16
);
4736 case TAB (BRANCHBWL
, LONG
):
4737 fragP
->fr_opcode
[1] = (char) 0xFF;
4738 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4739 1, RELAX_RELOC_PC32
);
4742 case TAB (BRABSJUNC
, LONG
):
4743 if (fragP
->fr_opcode
[0] == 0x61) /* jbsr */
4745 if (flag_keep_pcrel
)
4746 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4747 fragP
->fr_opcode
[0] = 0x4E;
4748 fragP
->fr_opcode
[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4749 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4750 0, RELAX_RELOC_ABS32
);
4753 else if (fragP
->fr_opcode
[0] == 0x60) /* jbra */
4755 if (flag_keep_pcrel
)
4756 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4757 fragP
->fr_opcode
[0] = 0x4E;
4758 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4759 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4760 0, RELAX_RELOC_ABS32
);
4765 /* This cannot happen, because jbsr and jbra are the only two
4766 unconditional branches. */
4770 case TAB (BRABSJCOND
, LONG
):
4771 if (flag_keep_pcrel
)
4772 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4774 /* Only Bcc 68000 instructions can come here
4775 Change bcc into b!cc/jmp absl long. */
4776 fragP
->fr_opcode
[0] ^= 0x01; /* Invert bcc. */
4777 fragP
->fr_opcode
[1] = 0x06; /* Branch offset = 6. */
4779 /* JF: these used to be fr_opcode[2,3], but they may be in a
4780 different frag, in which case referring to them is a no-no.
4781 Only fr_opcode[0,1] are guaranteed to work. */
4782 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4783 *buffer_address
++ = (char) 0xf9;
4784 fragP
->fr_fix
+= 2; /* Account for jmp instruction. */
4785 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4786 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
4789 case TAB (FBRANCH
, SHORT
):
4790 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4791 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4792 1, RELAX_RELOC_PC16
);
4795 case TAB (FBRANCH
, LONG
):
4796 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit. */
4797 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4798 1, RELAX_RELOC_PC32
);
4801 case TAB (DBCCLBR
, SHORT
):
4802 case TAB (DBCCABSJ
, SHORT
):
4803 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4804 1, RELAX_RELOC_PC16
);
4807 case TAB (DBCCLBR
, LONG
):
4808 /* Only DBcc instructions can come here.
4809 Change dbcc into dbcc/bral.
4810 JF: these used to be fr_opcode[2-7], but that's wrong. */
4811 if (flag_keep_pcrel
)
4812 as_fatal (_("Tried to convert DBcc to absolute jump"));
4814 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4815 *buffer_address
++ = 0x04;
4816 *buffer_address
++ = 0x60; /* Put in bra pc+6. */
4817 *buffer_address
++ = 0x06;
4818 *buffer_address
++ = 0x60; /* Put in bral (0x60ff). */
4819 *buffer_address
++ = (char) 0xff;
4821 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4822 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 1,
4826 case TAB (DBCCABSJ
, LONG
):
4827 /* Only DBcc instructions can come here.
4828 Change dbcc into dbcc/jmp.
4829 JF: these used to be fr_opcode[2-7], but that's wrong. */
4830 if (flag_keep_pcrel
)
4831 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4833 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4834 *buffer_address
++ = 0x04;
4835 *buffer_address
++ = 0x60; /* Put in bra pc + 6. */
4836 *buffer_address
++ = 0x06;
4837 *buffer_address
++ = 0x4e; /* Put in jmp long (0x4ef9). */
4838 *buffer_address
++ = (char) 0xf9;
4840 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4841 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 0,
4845 case TAB (PCREL1632
, SHORT
):
4846 fragP
->fr_opcode
[1] &= ~0x3F;
4847 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
4848 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4849 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4852 case TAB (PCREL1632
, LONG
):
4853 /* Already set to mode 7.3; this indicates: PC indirect with
4854 suppressed index, 32-bit displacement. */
4855 *buffer_address
++ = 0x01;
4856 *buffer_address
++ = 0x70;
4858 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4859 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4860 fixP
->fx_pcrel_adjust
= 2;
4863 case TAB (PCINDEX
, BYTE
):
4864 assert (fragP
->fr_fix
>= 2);
4865 buffer_address
[-2] &= ~1;
4866 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4867 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4868 fixP
->fx_pcrel_adjust
= 1;
4870 case TAB (PCINDEX
, SHORT
):
4871 assert (fragP
->fr_fix
>= 2);
4872 buffer_address
[-2] |= 0x1;
4873 buffer_address
[-1] = 0x20;
4874 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4875 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4876 fixP
->fx_pcrel_adjust
= 2;
4879 case TAB (PCINDEX
, LONG
):
4880 assert (fragP
->fr_fix
>= 2);
4881 buffer_address
[-2] |= 0x1;
4882 buffer_address
[-1] = 0x30;
4883 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4884 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4885 fixP
->fx_pcrel_adjust
= 2;
4888 case TAB (ABSTOPCREL
, SHORT
):
4889 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4890 1, RELAX_RELOC_PC16
);
4893 case TAB (ABSTOPCREL
, LONG
):
4894 if (flag_keep_pcrel
)
4895 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4896 /* The thing to do here is force it to ABSOLUTE LONG, since
4897 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4898 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
4900 fragP
->fr_opcode
[1] &= ~0x3F;
4901 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
4902 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4903 0, RELAX_RELOC_ABS32
);
4910 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
4911 segT sec ATTRIBUTE_UNUSED
,
4914 md_convert_frag_1 (fragP
);
4917 /* Force truly undefined symbols to their maximum size, and generally set up
4918 the frag list to be relaxed
4921 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
4923 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4924 switch (fragP
->fr_subtype
)
4926 case TAB (BRANCHBWL
, SZ_UNDEF
):
4927 case TAB (BRABSJUNC
, SZ_UNDEF
):
4928 case TAB (BRABSJCOND
, SZ_UNDEF
):
4930 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4931 && relaxable_symbol (fragP
->fr_symbol
))
4933 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4935 else if (flag_short_refs
)
4937 /* Symbol is undefined and we want short ref. */
4938 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4942 /* Symbol is still undefined. Make it LONG. */
4943 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
4948 case TAB (BRANCHBW
, SZ_UNDEF
):
4950 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4951 && relaxable_symbol (fragP
->fr_symbol
))
4953 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4957 /* Symbol is undefined and we don't have long branches. */
4958 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4963 case TAB (FBRANCH
, SZ_UNDEF
):
4964 case TAB (DBCCLBR
, SZ_UNDEF
):
4965 case TAB (DBCCABSJ
, SZ_UNDEF
):
4966 case TAB (PCREL1632
, SZ_UNDEF
):
4968 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4969 && relaxable_symbol (fragP
->fr_symbol
))
4972 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4976 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
4981 case TAB (PCINDEX
, SZ_UNDEF
):
4982 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4983 && relaxable_symbol (fragP
->fr_symbol
)))
4985 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
4989 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
4993 case TAB (ABSTOPCREL
, SZ_UNDEF
):
4995 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4996 && relaxable_symbol (fragP
->fr_symbol
)))
4998 fragP
->fr_subtype
= TAB (ABSTOPCREL
, SHORT
);
5002 fragP
->fr_subtype
= TAB (ABSTOPCREL
, LONG
);
5011 /* Now that SZ_UNDEF are taken care of, check others. */
5012 switch (fragP
->fr_subtype
)
5014 case TAB (BRANCHBWL
, BYTE
):
5015 case TAB (BRABSJUNC
, BYTE
):
5016 case TAB (BRABSJCOND
, BYTE
):
5017 case TAB (BRANCHBW
, BYTE
):
5018 /* We can't do a short jump to the next instruction, so in that
5019 case we force word mode. If the symbol is at the start of a
5020 frag, and it is the next frag with any data in it (usually
5021 this is just the next frag, but assembler listings may
5022 introduce empty frags), we must use word mode. */
5023 if (fragP
->fr_symbol
)
5027 sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
5028 if (S_GET_VALUE (fragP
->fr_symbol
) == sym_frag
->fr_address
)
5032 for (l
= fragP
->fr_next
; l
&& l
!= sym_frag
; l
= l
->fr_next
)
5036 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5043 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5046 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5047 /* the bit-field entries in the relocation_info struct plays hell
5048 with the byte-order problems of cross-assembly. So as a hack,
5049 I added this mach. dependent ri twiddler. Ugly, but it gets
5051 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5052 are symbolnum, most sig. byte first. Last byte is broken up with
5053 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5054 nibble as nuthin. (on Sun 3 at least) */
5055 /* Translate the internal relocation information into target-specific
5059 md_ri_to_chars (char *the_bytes
, struct reloc_info_generic
*ri
)
5062 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
5063 /* Now the fun stuff. */
5064 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
5065 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
5066 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
5067 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80)
5068 | ((ri
->r_length
<< 5) & 0x60)
5069 | ((ri
->r_extern
<< 4) & 0x10));
5074 #endif /* OBJ_AOUT or OBJ_BOUT */
5076 #ifndef WORKING_DOT_WORD
5077 int md_short_jump_size
= 4;
5078 int md_long_jump_size
= 6;
5081 md_create_short_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5082 fragS
*frag ATTRIBUTE_UNUSED
,
5083 symbolS
*to_symbol ATTRIBUTE_UNUSED
)
5087 offset
= to_addr
- (from_addr
+ 2);
5089 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
5090 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
5094 md_create_long_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5095 fragS
*frag
, symbolS
*to_symbol
)
5099 if (!HAVE_LONG_BRANCH (current_architecture
))
5101 if (flag_keep_pcrel
)
5102 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5103 offset
= to_addr
- S_GET_VALUE (to_symbol
);
5104 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
5105 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5106 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
5111 offset
= to_addr
- (from_addr
+ 2);
5112 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
5113 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5119 /* Different values of OK tell what its OK to return. Things that
5120 aren't OK are an error (what a shock, no?)
5123 10: Absolute 1:8 only
5124 20: Absolute 0:7 only
5125 30: absolute 0:15 only
5126 40: Absolute 0:31 only
5127 50: absolute 0:127 only
5128 55: absolute -64:63 only
5129 60: absolute -128:127 only
5130 70: absolute 0:4095 only
5131 80: absolute -1, 1:7 only
5135 get_num (struct m68k_exp
*exp
, int ok
)
5137 if (exp
->exp
.X_op
== O_absent
)
5139 /* Do the same thing the VAX asm does. */
5140 op (exp
) = O_constant
;
5146 as_warn (_("expression out of range: defaulting to 1"));
5150 else if (exp
->exp
.X_op
== O_constant
)
5155 if ((valueT
) TRUNC (offs (exp
)) - 1 > 7)
5157 as_warn (_("expression out of range: defaulting to 1"));
5162 if ((valueT
) TRUNC (offs (exp
)) > 7)
5166 if ((valueT
) TRUNC (offs (exp
)) > 15)
5170 if ((valueT
) TRUNC (offs (exp
)) > 32)
5174 if ((valueT
) TRUNC (offs (exp
)) > 127)
5178 if ((valueT
) SEXT (offs (exp
)) + 64 > 127)
5182 if ((valueT
) SEXT (offs (exp
)) + 128 > 255)
5186 if ((valueT
) TRUNC (offs (exp
)) > 4095)
5189 as_warn (_("expression out of range: defaulting to 0"));
5194 if ((valueT
) TRUNC (offs (exp
)) != 0xffffffff
5195 && (valueT
) TRUNC (offs (exp
)) - 1 > 6)
5197 as_warn (_("expression out of range: defaulting to 1"));
5205 else if (exp
->exp
.X_op
== O_big
)
5207 if (offs (exp
) <= 0 /* flonum. */
5208 && (ok
== 90 /* no bignums */
5209 || (ok
> 10 /* Small-int ranges including 0 ok. */
5210 /* If we have a flonum zero, a zero integer should
5211 do as well (e.g., in moveq). */
5212 && generic_floating_point_number
.exponent
== 0
5213 && generic_floating_point_number
.low
[0] == 0)))
5215 /* HACK! Turn it into a long. */
5216 LITTLENUM_TYPE words
[6];
5218 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
5219 op (exp
) = O_constant
;
5222 offs (exp
) = words
[1] | (words
[0] << 16);
5226 op (exp
) = O_constant
;
5229 offs (exp
) = (ok
== 10) ? 1 : 0;
5230 as_warn (_("Can't deal with expression; defaulting to %ld"),
5236 if (ok
>= 10 && ok
<= 80)
5238 op (exp
) = O_constant
;
5241 offs (exp
) = (ok
== 10) ? 1 : 0;
5242 as_warn (_("Can't deal with expression; defaulting to %ld"),
5247 if (exp
->size
!= SIZE_UNSPEC
)
5255 if (!isbyte (offs (exp
)))
5256 as_warn (_("expression doesn't fit in BYTE"));
5259 if (!isword (offs (exp
)))
5260 as_warn (_("expression doesn't fit in WORD"));
5268 /* These are the back-ends for the various machine dependent pseudo-ops. */
5271 s_data1 (int ignore ATTRIBUTE_UNUSED
)
5273 subseg_set (data_section
, 1);
5274 demand_empty_rest_of_line ();
5278 s_data2 (int ignore ATTRIBUTE_UNUSED
)
5280 subseg_set (data_section
, 2);
5281 demand_empty_rest_of_line ();
5285 s_bss (int ignore ATTRIBUTE_UNUSED
)
5287 /* We don't support putting frags in the BSS segment, we fake it
5288 by marking in_bss, then looking at s_skip for clues. */
5290 subseg_set (bss_section
, 0);
5291 demand_empty_rest_of_line ();
5295 s_even (int ignore ATTRIBUTE_UNUSED
)
5298 register long temp_fill
;
5300 temp
= 1; /* JF should be 2? */
5301 temp_fill
= get_absolute_expression ();
5302 if (!need_pass_2
) /* Never make frag if expect extra pass. */
5303 frag_align (temp
, (int) temp_fill
, 0);
5304 demand_empty_rest_of_line ();
5305 record_alignment (now_seg
, temp
);
5309 s_proc (int ignore ATTRIBUTE_UNUSED
)
5311 demand_empty_rest_of_line ();
5314 /* Pseudo-ops handled for MRI compatibility. */
5316 /* This function returns non-zero if the argument is a conditional
5317 pseudo-op. This is called when checking whether a pending
5318 alignment is needed. */
5321 m68k_conditional_pseudoop (pseudo_typeS
*pop
)
5323 return (pop
->poc_handler
== s_mri_if
5324 || pop
->poc_handler
== s_mri_else
);
5327 /* Handle an MRI style chip specification. */
5336 s
= input_line_pointer
;
5337 /* We can't use get_symbol_end since the processor names are not proper
5339 while (is_part_of_name (c
= *input_line_pointer
++))
5341 *--input_line_pointer
= 0;
5342 for (i
= 0; m68k_cpus
[i
].name
; i
++)
5343 if (strcasecmp (s
, m68k_cpus
[i
].name
) == 0)
5345 if (!m68k_cpus
[i
].name
)
5347 as_bad (_("%s: unrecognized processor name"), s
);
5348 *input_line_pointer
= c
;
5349 ignore_rest_of_line ();
5352 *input_line_pointer
= c
;
5354 if (*input_line_pointer
== '/')
5355 current_architecture
= 0;
5357 current_architecture
&= m68881
| m68851
;
5358 current_architecture
|= m68k_cpus
[i
].arch
& ~(m68881
| m68851
);
5359 control_regs
= m68k_cpus
[i
].control_regs
;
5361 while (*input_line_pointer
== '/')
5363 ++input_line_pointer
;
5364 s
= input_line_pointer
;
5365 /* We can't use get_symbol_end since the processor names are not
5367 while (is_part_of_name (c
= *input_line_pointer
++))
5369 *--input_line_pointer
= 0;
5370 if (strcmp (s
, "68881") == 0)
5371 current_architecture
|= m68881
;
5372 else if (strcmp (s
, "68851") == 0)
5373 current_architecture
|= m68851
;
5374 *input_line_pointer
= c
;
5378 /* The MRI CHIP pseudo-op. */
5381 s_chip (int ignore ATTRIBUTE_UNUSED
)
5387 stop
= mri_comment_field (&stopc
);
5390 mri_comment_end (stop
, stopc
);
5391 demand_empty_rest_of_line ();
5394 /* The MRI FOPT pseudo-op. */
5397 s_fopt (int ignore ATTRIBUTE_UNUSED
)
5401 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
5405 input_line_pointer
+= 3;
5406 temp
= get_absolute_expression ();
5407 if (temp
< 0 || temp
> 7)
5408 as_bad (_("bad coprocessor id"));
5410 m68k_float_copnum
= COP0
+ temp
;
5414 as_bad (_("unrecognized fopt option"));
5415 ignore_rest_of_line ();
5419 demand_empty_rest_of_line ();
5422 /* The structure used to handle the MRI OPT pseudo-op. */
5426 /* The name of the option. */
5429 /* If this is not NULL, just call this function. The first argument
5430 is the ARG field of this structure, the second argument is
5431 whether the option was negated. */
5432 void (*pfn
) (int arg
, int on
);
5434 /* If this is not NULL, and the PFN field is NULL, set the variable
5435 this points to. Set it to the ARG field if the option was not
5436 negated, and the NOTARG field otherwise. */
5439 /* The value to pass to PFN or to assign to *PVAR. */
5442 /* The value to assign to *PVAR if the option is negated. If PFN is
5443 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5444 the option may not be negated. */
5448 /* The table used to handle the MRI OPT pseudo-op. */
5450 static void skip_to_comma (int, int);
5451 static void opt_nest (int, int);
5452 static void opt_chip (int, int);
5453 static void opt_list (int, int);
5454 static void opt_list_symbols (int, int);
5456 static const struct opt_action opt_table
[] =
5458 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5460 /* We do relaxing, so there is little use for these options. */
5461 { "b", 0, 0, 0, 0 },
5462 { "brs", 0, 0, 0, 0 },
5463 { "brb", 0, 0, 0, 0 },
5464 { "brl", 0, 0, 0, 0 },
5465 { "brw", 0, 0, 0, 0 },
5467 { "c", 0, 0, 0, 0 },
5468 { "cex", 0, 0, 0, 0 },
5469 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5470 { "cl", 0, 0, 0, 0 },
5471 { "cre", 0, 0, 0, 0 },
5472 { "d", 0, &flag_keep_locals
, 1, 0 },
5473 { "e", 0, 0, 0, 0 },
5474 { "f", 0, &flag_short_refs
, 1, 0 },
5475 { "frs", 0, &flag_short_refs
, 1, 0 },
5476 { "frl", 0, &flag_short_refs
, 0, 1 },
5477 { "g", 0, 0, 0, 0 },
5478 { "i", 0, 0, 0, 0 },
5479 { "m", 0, 0, 0, 0 },
5480 { "mex", 0, 0, 0, 0 },
5481 { "mc", 0, 0, 0, 0 },
5482 { "md", 0, 0, 0, 0 },
5483 { "nest", opt_nest
, 0, 0, 0 },
5484 { "next", skip_to_comma
, 0, 0, 0 },
5485 { "o", 0, 0, 0, 0 },
5486 { "old", 0, 0, 0, 0 },
5487 { "op", skip_to_comma
, 0, 0, 0 },
5488 { "pco", 0, 0, 0, 0 },
5489 { "p", opt_chip
, 0, 0, 0 },
5490 { "pcr", 0, 0, 0, 0 },
5491 { "pcs", 0, 0, 0, 0 },
5492 { "r", 0, 0, 0, 0 },
5493 { "quick", 0, &m68k_quick
, 1, 0 },
5494 { "rel32", 0, &m68k_rel32
, 1, 0 },
5495 { "s", opt_list
, 0, 0, 0 },
5496 { "t", opt_list_symbols
, 0, 0, 0 },
5497 { "w", 0, &flag_no_warnings
, 0, 1 },
5501 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5503 /* The MRI OPT pseudo-op. */
5506 s_opt (int ignore ATTRIBUTE_UNUSED
)
5514 const struct opt_action
*o
;
5519 if (*input_line_pointer
== '-')
5521 ++input_line_pointer
;
5524 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5526 input_line_pointer
+= 2;
5530 s
= input_line_pointer
;
5531 c
= get_symbol_end ();
5533 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5535 if (strcasecmp (s
, o
->name
) == 0)
5539 /* Restore input_line_pointer now in case the option
5541 *input_line_pointer
= c
;
5542 (*o
->pfn
) (o
->arg
, t
);
5544 else if (o
->pvar
!= NULL
)
5546 if (! t
&& o
->arg
== o
->notarg
)
5547 as_bad (_("option `%s' may not be negated"), s
);
5548 *input_line_pointer
= c
;
5549 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5552 *input_line_pointer
= c
;
5558 as_bad (_("option `%s' not recognized"), s
);
5559 *input_line_pointer
= c
;
5562 while (*input_line_pointer
++ == ',');
5564 /* Move back to terminating character. */
5565 --input_line_pointer
;
5566 demand_empty_rest_of_line ();
5569 /* Skip ahead to a comma. This is used for OPT options which we do
5570 not support and which take arguments. */
5573 skip_to_comma (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5575 while (*input_line_pointer
!= ','
5576 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5577 ++input_line_pointer
;
5580 /* Handle the OPT NEST=depth option. */
5583 opt_nest (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5585 if (*input_line_pointer
!= '=')
5587 as_bad (_("bad format of OPT NEST=depth"));
5591 ++input_line_pointer
;
5592 max_macro_nest
= get_absolute_expression ();
5595 /* Handle the OPT P=chip option. */
5598 opt_chip (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5600 if (*input_line_pointer
!= '=')
5602 /* This is just OPT P, which we do not support. */
5606 ++input_line_pointer
;
5610 /* Handle the OPT S option. */
5613 opt_list (int arg ATTRIBUTE_UNUSED
, int on
)
5618 /* Handle the OPT T option. */
5621 opt_list_symbols (int arg ATTRIBUTE_UNUSED
, int on
)
5624 listing
|= LISTING_SYMBOLS
;
5626 listing
&= ~LISTING_SYMBOLS
;
5629 /* Handle the MRI REG pseudo-op. */
5632 s_reg (int ignore ATTRIBUTE_UNUSED
)
5641 if (line_label
== NULL
)
5643 as_bad (_("missing label"));
5644 ignore_rest_of_line ();
5649 stop
= mri_comment_field (&stopc
);
5653 s
= input_line_pointer
;
5654 while (ISALNUM (*input_line_pointer
)
5655 #ifdef REGISTER_PREFIX
5656 || *input_line_pointer
== REGISTER_PREFIX
5658 || *input_line_pointer
== '/'
5659 || *input_line_pointer
== '-')
5660 ++input_line_pointer
;
5661 c
= *input_line_pointer
;
5662 *input_line_pointer
= '\0';
5664 if (m68k_ip_op (s
, &rop
) != 0)
5666 if (rop
.error
== NULL
)
5667 as_bad (_("bad register list"));
5669 as_bad (_("bad register list: %s"), rop
.error
);
5670 *input_line_pointer
= c
;
5671 ignore_rest_of_line ();
5675 *input_line_pointer
= c
;
5677 if (rop
.mode
== REGLST
)
5679 else if (rop
.mode
== DREG
)
5680 mask
= 1 << (rop
.reg
- DATA0
);
5681 else if (rop
.mode
== AREG
)
5682 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
5683 else if (rop
.mode
== FPREG
)
5684 mask
= 1 << (rop
.reg
- FP0
+ 16);
5685 else if (rop
.mode
== CONTROL
5688 else if (rop
.mode
== CONTROL
5691 else if (rop
.mode
== CONTROL
5696 as_bad (_("bad register list"));
5697 ignore_rest_of_line ();
5701 S_SET_SEGMENT (line_label
, reg_section
);
5702 S_SET_VALUE (line_label
, ~mask
);
5703 symbol_set_frag (line_label
, &zero_address_frag
);
5706 mri_comment_end (stop
, stopc
);
5708 demand_empty_rest_of_line ();
5711 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5715 struct save_opts
*next
;
5717 int symbols_case_sensitive
;
5721 const enum m68k_register
*control_regs
;
5726 /* FIXME: We don't save OPT S. */
5729 /* This variable holds the stack of saved options. */
5731 static struct save_opts
*save_stack
;
5733 /* The MRI SAVE pseudo-op. */
5736 s_save (int ignore ATTRIBUTE_UNUSED
)
5738 struct save_opts
*s
;
5740 s
= (struct save_opts
*) xmalloc (sizeof (struct save_opts
));
5741 s
->abspcadd
= m68k_abspcadd
;
5742 s
->symbols_case_sensitive
= symbols_case_sensitive
;
5743 s
->keep_locals
= flag_keep_locals
;
5744 s
->short_refs
= flag_short_refs
;
5745 s
->architecture
= current_architecture
;
5746 s
->control_regs
= control_regs
;
5747 s
->quick
= m68k_quick
;
5748 s
->rel32
= m68k_rel32
;
5749 s
->listing
= listing
;
5750 s
->no_warnings
= flag_no_warnings
;
5752 s
->next
= save_stack
;
5755 demand_empty_rest_of_line ();
5758 /* The MRI RESTORE pseudo-op. */
5761 s_restore (int ignore ATTRIBUTE_UNUSED
)
5763 struct save_opts
*s
;
5765 if (save_stack
== NULL
)
5767 as_bad (_("restore without save"));
5768 ignore_rest_of_line ();
5773 save_stack
= s
->next
;
5775 m68k_abspcadd
= s
->abspcadd
;
5776 symbols_case_sensitive
= s
->symbols_case_sensitive
;
5777 flag_keep_locals
= s
->keep_locals
;
5778 flag_short_refs
= s
->short_refs
;
5779 current_architecture
= s
->architecture
;
5780 control_regs
= s
->control_regs
;
5781 m68k_quick
= s
->quick
;
5782 m68k_rel32
= s
->rel32
;
5783 listing
= s
->listing
;
5784 flag_no_warnings
= s
->no_warnings
;
5788 demand_empty_rest_of_line ();
5791 /* Types of MRI structured control directives. */
5793 enum mri_control_type
5801 /* This structure is used to stack the MRI structured control
5804 struct mri_control_info
5806 /* The directive within which this one is enclosed. */
5807 struct mri_control_info
*outer
;
5809 /* The type of directive. */
5810 enum mri_control_type type
;
5812 /* Whether an ELSE has been in an IF. */
5815 /* The add or sub statement at the end of a FOR. */
5818 /* The label of the top of a FOR or REPEAT loop. */
5821 /* The label to jump to for the next iteration, or the else
5822 expression of a conditional. */
5825 /* The label to jump to to break out of the loop, or the label past
5826 the end of a conditional. */
5830 /* The stack of MRI structured control directives. */
5832 static struct mri_control_info
*mri_control_stack
;
5834 /* The current MRI structured control directive index number, used to
5835 generate label names. */
5837 static int mri_control_index
;
5839 /* Assemble an instruction for an MRI structured control directive. */
5842 mri_assemble (char *str
)
5846 /* md_assemble expects the opcode to be in lower case. */
5847 for (s
= str
; *s
!= ' ' && *s
!= '\0'; s
++)
5853 /* Generate a new MRI label structured control directive label name. */
5856 mri_control_label (void)
5860 n
= (char *) xmalloc (20);
5861 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
5862 ++mri_control_index
;
5866 /* Create a new MRI structured control directive. */
5868 static struct mri_control_info
*
5869 push_mri_control (enum mri_control_type type
)
5871 struct mri_control_info
*n
;
5873 n
= (struct mri_control_info
*) xmalloc (sizeof (struct mri_control_info
));
5877 if (type
== mri_if
|| type
== mri_while
)
5880 n
->top
= mri_control_label ();
5881 n
->next
= mri_control_label ();
5882 n
->bottom
= mri_control_label ();
5884 n
->outer
= mri_control_stack
;
5885 mri_control_stack
= n
;
5890 /* Pop off the stack of MRI structured control directives. */
5893 pop_mri_control (void)
5895 struct mri_control_info
*n
;
5897 n
= mri_control_stack
;
5898 mri_control_stack
= n
->outer
;
5906 /* Recognize a condition code in an MRI structured control expression. */
5909 parse_mri_condition (int *pcc
)
5913 know (*input_line_pointer
== '<');
5915 ++input_line_pointer
;
5916 c1
= *input_line_pointer
++;
5917 c2
= *input_line_pointer
++;
5919 if (*input_line_pointer
!= '>')
5921 as_bad (_("syntax error in structured control directive"));
5925 ++input_line_pointer
;
5931 *pcc
= (c1
<< 8) | c2
;
5936 /* Parse a single operand in an MRI structured control expression. */
5939 parse_mri_control_operand (int *pcc
, char **leftstart
, char **leftstop
,
5940 char **rightstart
, char **rightstop
)
5952 if (*input_line_pointer
== '<')
5954 /* It's just a condition code. */
5955 return parse_mri_condition (pcc
);
5958 /* Look ahead for the condition code. */
5959 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5961 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
5966 as_bad (_("missing condition code in structured control directive"));
5970 *leftstart
= input_line_pointer
;
5972 if (*leftstop
> *leftstart
5973 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
5976 input_line_pointer
= s
;
5977 if (! parse_mri_condition (pcc
))
5980 /* Look ahead for AND or OR or end of line. */
5981 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5983 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5984 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5986 if ((s
== input_line_pointer
5989 && ((strncasecmp (s
, "AND", 3) == 0
5990 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
5991 || (strncasecmp (s
, "OR", 2) == 0
5992 && (s
[2] == '.' || ! is_part_of_name (s
[2])))))
5996 *rightstart
= input_line_pointer
;
5998 if (*rightstop
> *rightstart
5999 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
6002 input_line_pointer
= s
;
6007 #define MCC(b1, b2) (((b1) << 8) | (b2))
6009 /* Swap the sense of a condition. This changes the condition so that
6010 it generates the same result when the operands are swapped. */
6013 swap_mri_condition (int cc
)
6017 case MCC ('h', 'i'): return MCC ('c', 's');
6018 case MCC ('l', 's'): return MCC ('c', 'c');
6019 /* <HS> is an alias for <CC>. */
6020 case MCC ('h', 's'):
6021 case MCC ('c', 'c'): return MCC ('l', 's');
6022 /* <LO> is an alias for <CS>. */
6023 case MCC ('l', 'o'):
6024 case MCC ('c', 's'): return MCC ('h', 'i');
6025 case MCC ('p', 'l'): return MCC ('m', 'i');
6026 case MCC ('m', 'i'): return MCC ('p', 'l');
6027 case MCC ('g', 'e'): return MCC ('l', 'e');
6028 case MCC ('l', 't'): return MCC ('g', 't');
6029 case MCC ('g', 't'): return MCC ('l', 't');
6030 case MCC ('l', 'e'): return MCC ('g', 'e');
6031 /* Issue a warning for conditions we can not swap. */
6032 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6033 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6034 case MCC ('v', 'c'):
6035 case MCC ('v', 's'):
6037 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6038 (char) (cc
>> 8), (char) (cc
));
6044 /* Reverse the sense of a condition. */
6047 reverse_mri_condition (int cc
)
6051 case MCC ('h', 'i'): return MCC ('l', 's');
6052 case MCC ('l', 's'): return MCC ('h', 'i');
6053 /* <HS> is an alias for <CC> */
6054 case MCC ('h', 's'): return MCC ('l', 'o');
6055 case MCC ('c', 'c'): return MCC ('c', 's');
6056 /* <LO> is an alias for <CS> */
6057 case MCC ('l', 'o'): return MCC ('h', 's');
6058 case MCC ('c', 's'): return MCC ('c', 'c');
6059 case MCC ('n', 'e'): return MCC ('e', 'q');
6060 case MCC ('e', 'q'): return MCC ('n', 'e');
6061 case MCC ('v', 'c'): return MCC ('v', 's');
6062 case MCC ('v', 's'): return MCC ('v', 'c');
6063 case MCC ('p', 'l'): return MCC ('m', 'i');
6064 case MCC ('m', 'i'): return MCC ('p', 'l');
6065 case MCC ('g', 'e'): return MCC ('l', 't');
6066 case MCC ('l', 't'): return MCC ('g', 'e');
6067 case MCC ('g', 't'): return MCC ('l', 'e');
6068 case MCC ('l', 'e'): return MCC ('g', 't');
6073 /* Build an MRI structured control expression. This generates test
6074 and branch instructions. It goes to TRUELAB if the condition is
6075 true, and to FALSELAB if the condition is false. Exactly one of
6076 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6077 is the size qualifier for the expression. EXTENT is the size to
6078 use for the branch. */
6081 build_mri_control_operand (int qual
, int cc
, char *leftstart
, char *leftstop
,
6082 char *rightstart
, char *rightstop
,
6083 const char *truelab
, const char *falselab
,
6089 if (leftstart
!= NULL
)
6091 struct m68k_op leftop
, rightop
;
6094 /* Swap the compare operands, if necessary, to produce a legal
6095 m68k compare instruction. Comparing a register operand with
6096 a non-register operand requires the register to be on the
6097 right (cmp, cmpa). Comparing an immediate value with
6098 anything requires the immediate value to be on the left
6103 (void) m68k_ip_op (leftstart
, &leftop
);
6108 (void) m68k_ip_op (rightstart
, &rightop
);
6111 if (rightop
.mode
== IMMED
6112 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
6113 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
6117 /* Correct conditional handling:
6118 if #1 <lt> d0 then ;means if (1 < d0)
6124 cmp #1,d0 if we do *not* swap the operands
6125 bgt true we need the swapped condition!
6132 leftstart
= rightstart
;
6135 leftstop
= rightstop
;
6140 cc
= swap_mri_condition (cc
);
6144 if (truelab
== NULL
)
6146 cc
= reverse_mri_condition (cc
);
6150 if (leftstart
!= NULL
)
6152 buf
= (char *) xmalloc (20
6153 + (leftstop
- leftstart
)
6154 + (rightstop
- rightstart
));
6160 *s
++ = TOLOWER (qual
);
6162 memcpy (s
, leftstart
, leftstop
- leftstart
);
6163 s
+= leftstop
- leftstart
;
6165 memcpy (s
, rightstart
, rightstop
- rightstart
);
6166 s
+= rightstop
- rightstart
;
6172 buf
= (char *) xmalloc (20 + strlen (truelab
));
6178 *s
++ = TOLOWER (extent
);
6180 strcpy (s
, truelab
);
6185 /* Parse an MRI structured control expression. This generates test
6186 and branch instructions. STOP is where the expression ends. It
6187 goes to TRUELAB if the condition is true, and to FALSELAB if the
6188 condition is false. Exactly one of TRUELAB and FALSELAB will be
6189 NULL, meaning to fall through. QUAL is the size qualifier for the
6190 expression. EXTENT is the size to use for the branch. */
6193 parse_mri_control_expression (char *stop
, int qual
, const char *truelab
,
6194 const char *falselab
, int extent
)
6206 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6207 &rightstart
, &rightstop
))
6213 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
6217 if (falselab
!= NULL
)
6220 flab
= mri_control_label ();
6222 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6223 rightstop
, (const char *) NULL
, flab
, extent
);
6225 input_line_pointer
+= 3;
6226 if (*input_line_pointer
!= '.'
6227 || input_line_pointer
[1] == '\0')
6231 qual
= input_line_pointer
[1];
6232 input_line_pointer
+= 2;
6235 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6236 &rightstart
, &rightstop
))
6242 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6243 rightstop
, truelab
, falselab
, extent
);
6245 if (falselab
== NULL
)
6248 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
6252 if (truelab
!= NULL
)
6255 tlab
= mri_control_label ();
6257 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6258 rightstop
, tlab
, (const char *) NULL
, extent
);
6260 input_line_pointer
+= 2;
6261 if (*input_line_pointer
!= '.'
6262 || input_line_pointer
[1] == '\0')
6266 qual
= input_line_pointer
[1];
6267 input_line_pointer
+= 2;
6270 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6271 &rightstart
, &rightstop
))
6277 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6278 rightstop
, truelab
, falselab
, extent
);
6280 if (truelab
== NULL
)
6285 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6286 rightstop
, truelab
, falselab
, extent
);
6290 if (input_line_pointer
!= stop
)
6291 as_bad (_("syntax error in structured control directive"));
6294 /* Handle the MRI IF pseudo-op. This may be a structured control
6295 directive, or it may be a regular assembler conditional, depending
6303 struct mri_control_info
*n
;
6305 /* A structured control directive must end with THEN with an
6306 optional qualifier. */
6307 s
= input_line_pointer
;
6308 /* We only accept '*' as introduction of comments if preceded by white space
6309 or at first column of a line (I think this can't actually happen here?)
6310 This is important when assembling:
6311 if d0 <ne> 12(a0,d0*2) then
6312 if d0 <ne> #CONST*20 then. */
6313 while (! (is_end_of_line
[(unsigned char) *s
]
6316 && (s
== input_line_pointer
6318 || *(s
-1) == '\t'))))
6321 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
6324 if (s
- input_line_pointer
> 1
6328 if (s
- input_line_pointer
< 3
6329 || strncasecmp (s
- 3, "THEN", 4) != 0)
6333 as_bad (_("missing then"));
6334 ignore_rest_of_line ();
6338 /* It's a conditional. */
6343 /* Since this might be a conditional if, this pseudo-op will be
6344 called even if we are supported to be ignoring input. Double
6345 check now. Clobber *input_line_pointer so that ignore_input
6346 thinks that this is not a special pseudo-op. */
6347 c
= *input_line_pointer
;
6348 *input_line_pointer
= 0;
6349 if (ignore_input ())
6351 *input_line_pointer
= c
;
6352 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6353 ++input_line_pointer
;
6354 demand_empty_rest_of_line ();
6357 *input_line_pointer
= c
;
6359 n
= push_mri_control (mri_if
);
6361 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
6362 n
->next
, s
[1] == '.' ? s
[2] : '\0');
6365 input_line_pointer
= s
+ 3;
6367 input_line_pointer
= s
+ 1;
6371 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6372 ++input_line_pointer
;
6375 demand_empty_rest_of_line ();
6378 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6379 structured IF, associate the ELSE with the IF. Otherwise, assume
6380 it is a conditional else. */
6383 s_mri_else (int qual
)
6390 && (mri_control_stack
== NULL
6391 || mri_control_stack
->type
!= mri_if
6392 || mri_control_stack
->else_seen
))
6398 c
= *input_line_pointer
;
6399 *input_line_pointer
= 0;
6400 if (ignore_input ())
6402 *input_line_pointer
= c
;
6403 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6404 ++input_line_pointer
;
6405 demand_empty_rest_of_line ();
6408 *input_line_pointer
= c
;
6410 if (mri_control_stack
== NULL
6411 || mri_control_stack
->type
!= mri_if
6412 || mri_control_stack
->else_seen
)
6414 as_bad (_("else without matching if"));
6415 ignore_rest_of_line ();
6419 mri_control_stack
->else_seen
= 1;
6421 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->bottom
));
6422 q
[0] = TOLOWER (qual
);
6424 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6428 colon (mri_control_stack
->next
);
6432 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6433 ++input_line_pointer
;
6436 demand_empty_rest_of_line ();
6439 /* Handle the MRI ENDI pseudo-op. */
6442 s_mri_endi (int ignore ATTRIBUTE_UNUSED
)
6444 if (mri_control_stack
== NULL
6445 || mri_control_stack
->type
!= mri_if
)
6447 as_bad (_("endi without matching if"));
6448 ignore_rest_of_line ();
6452 /* ignore_input will not return true for ENDI, so we don't need to
6453 worry about checking it again here. */
6455 if (! mri_control_stack
->else_seen
)
6456 colon (mri_control_stack
->next
);
6457 colon (mri_control_stack
->bottom
);
6463 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6464 ++input_line_pointer
;
6467 demand_empty_rest_of_line ();
6470 /* Handle the MRI BREAK pseudo-op. */
6473 s_mri_break (int extent
)
6475 struct mri_control_info
*n
;
6479 n
= mri_control_stack
;
6481 && n
->type
!= mri_for
6482 && n
->type
!= mri_repeat
6483 && n
->type
!= mri_while
)
6487 as_bad (_("break outside of structured loop"));
6488 ignore_rest_of_line ();
6492 buf
= (char *) xmalloc (20 + strlen (n
->bottom
));
6493 ex
[0] = TOLOWER (extent
);
6495 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6501 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6502 ++input_line_pointer
;
6505 demand_empty_rest_of_line ();
6508 /* Handle the MRI NEXT pseudo-op. */
6511 s_mri_next (int extent
)
6513 struct mri_control_info
*n
;
6517 n
= mri_control_stack
;
6519 && n
->type
!= mri_for
6520 && n
->type
!= mri_repeat
6521 && n
->type
!= mri_while
)
6525 as_bad (_("next outside of structured loop"));
6526 ignore_rest_of_line ();
6530 buf
= (char *) xmalloc (20 + strlen (n
->next
));
6531 ex
[0] = TOLOWER (extent
);
6533 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6539 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6540 ++input_line_pointer
;
6543 demand_empty_rest_of_line ();
6546 /* Handle the MRI FOR pseudo-op. */
6549 s_mri_for (int qual
)
6551 const char *varstart
, *varstop
;
6552 const char *initstart
, *initstop
;
6553 const char *endstart
, *endstop
;
6554 const char *bystart
, *bystop
;
6558 struct mri_control_info
*n
;
6564 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6568 varstart
= input_line_pointer
;
6570 /* Look for the '='. */
6571 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6572 && *input_line_pointer
!= '=')
6573 ++input_line_pointer
;
6574 if (*input_line_pointer
!= '=')
6576 as_bad (_("missing ="));
6577 ignore_rest_of_line ();
6581 varstop
= input_line_pointer
;
6582 if (varstop
> varstart
6583 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6586 ++input_line_pointer
;
6588 initstart
= input_line_pointer
;
6590 /* Look for TO or DOWNTO. */
6593 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6595 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6596 && ! is_part_of_name (input_line_pointer
[2]))
6598 initstop
= input_line_pointer
;
6599 input_line_pointer
+= 2;
6602 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6603 && ! is_part_of_name (input_line_pointer
[6]))
6605 initstop
= input_line_pointer
;
6607 input_line_pointer
+= 6;
6610 ++input_line_pointer
;
6612 if (initstop
== NULL
)
6614 as_bad (_("missing to or downto"));
6615 ignore_rest_of_line ();
6618 if (initstop
> initstart
6619 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6623 endstart
= input_line_pointer
;
6625 /* Look for BY or DO. */
6628 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6630 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
6631 && ! is_part_of_name (input_line_pointer
[2]))
6633 endstop
= input_line_pointer
;
6635 input_line_pointer
+= 2;
6638 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6639 && (input_line_pointer
[2] == '.'
6640 || ! is_part_of_name (input_line_pointer
[2])))
6642 endstop
= input_line_pointer
;
6643 input_line_pointer
+= 2;
6646 ++input_line_pointer
;
6648 if (endstop
== NULL
)
6650 as_bad (_("missing do"));
6651 ignore_rest_of_line ();
6654 if (endstop
> endstart
6655 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
6661 bystop
= bystart
+ 2;
6666 bystart
= input_line_pointer
;
6670 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6672 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6673 && (input_line_pointer
[2] == '.'
6674 || ! is_part_of_name (input_line_pointer
[2])))
6676 bystop
= input_line_pointer
;
6677 input_line_pointer
+= 2;
6680 ++input_line_pointer
;
6684 as_bad (_("missing do"));
6685 ignore_rest_of_line ();
6688 if (bystop
> bystart
6689 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
6693 if (*input_line_pointer
!= '.')
6697 extent
= input_line_pointer
[1];
6698 input_line_pointer
+= 2;
6701 /* We have fully parsed the FOR operands. Now build the loop. */
6702 n
= push_mri_control (mri_for
);
6704 buf
= (char *) xmalloc (50 + (input_line_pointer
- varstart
));
6706 /* Move init,var. */
6713 *s
++ = TOLOWER (qual
);
6715 memcpy (s
, initstart
, initstop
- initstart
);
6716 s
+= initstop
- initstart
;
6718 memcpy (s
, varstart
, varstop
- varstart
);
6719 s
+= varstop
- varstart
;
6731 *s
++ = TOLOWER (qual
);
6733 memcpy (s
, endstart
, endstop
- endstart
);
6734 s
+= endstop
- endstart
;
6736 memcpy (s
, varstart
, varstop
- varstart
);
6737 s
+= varstop
- varstart
;
6742 ex
[0] = TOLOWER (extent
);
6745 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
6747 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
6750 /* Put together the add or sub instruction used by ENDF. */
6758 *s
++ = TOLOWER (qual
);
6760 memcpy (s
, bystart
, bystop
- bystart
);
6761 s
+= bystop
- bystart
;
6763 memcpy (s
, varstart
, varstop
- varstart
);
6764 s
+= varstop
- varstart
;
6770 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6771 ++input_line_pointer
;
6774 demand_empty_rest_of_line ();
6777 /* Handle the MRI ENDF pseudo-op. */
6780 s_mri_endf (int ignore ATTRIBUTE_UNUSED
)
6782 if (mri_control_stack
== NULL
6783 || mri_control_stack
->type
!= mri_for
)
6785 as_bad (_("endf without for"));
6786 ignore_rest_of_line ();
6790 colon (mri_control_stack
->next
);
6792 mri_assemble (mri_control_stack
->incr
);
6794 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
6795 mri_assemble (mri_control_stack
->incr
);
6797 free (mri_control_stack
->incr
);
6799 colon (mri_control_stack
->bottom
);
6805 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6806 ++input_line_pointer
;
6809 demand_empty_rest_of_line ();
6812 /* Handle the MRI REPEAT pseudo-op. */
6815 s_mri_repeat (int ignore ATTRIBUTE_UNUSED
)
6817 struct mri_control_info
*n
;
6819 n
= push_mri_control (mri_repeat
);
6823 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6824 ++input_line_pointer
;
6826 demand_empty_rest_of_line ();
6829 /* Handle the MRI UNTIL pseudo-op. */
6832 s_mri_until (int qual
)
6836 if (mri_control_stack
== NULL
6837 || mri_control_stack
->type
!= mri_repeat
)
6839 as_bad (_("until without repeat"));
6840 ignore_rest_of_line ();
6844 colon (mri_control_stack
->next
);
6846 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
6849 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
6850 mri_control_stack
->top
, '\0');
6852 colon (mri_control_stack
->bottom
);
6854 input_line_pointer
= s
;
6860 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6861 ++input_line_pointer
;
6864 demand_empty_rest_of_line ();
6867 /* Handle the MRI WHILE pseudo-op. */
6870 s_mri_while (int qual
)
6874 struct mri_control_info
*n
;
6876 s
= input_line_pointer
;
6877 /* We only accept '*' as introduction of comments if preceded by white space
6878 or at first column of a line (I think this can't actually happen here?)
6879 This is important when assembling:
6880 while d0 <ne> 12(a0,d0*2) do
6881 while d0 <ne> #CONST*20 do. */
6882 while (! (is_end_of_line
[(unsigned char) *s
]
6885 && (s
== input_line_pointer
6887 || *(s
-1) == '\t'))))
6890 while (*s
== ' ' || *s
== '\t')
6892 if (s
- input_line_pointer
> 1
6895 if (s
- input_line_pointer
< 2
6896 || strncasecmp (s
- 1, "DO", 2) != 0)
6898 as_bad (_("missing do"));
6899 ignore_rest_of_line ();
6903 n
= push_mri_control (mri_while
);
6907 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
6908 s
[1] == '.' ? s
[2] : '\0');
6910 input_line_pointer
= s
+ 1;
6911 if (*input_line_pointer
== '.')
6912 input_line_pointer
+= 2;
6916 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6917 ++input_line_pointer
;
6920 demand_empty_rest_of_line ();
6923 /* Handle the MRI ENDW pseudo-op. */
6926 s_mri_endw (int ignore ATTRIBUTE_UNUSED
)
6930 if (mri_control_stack
== NULL
6931 || mri_control_stack
->type
!= mri_while
)
6933 as_bad (_("endw without while"));
6934 ignore_rest_of_line ();
6938 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->next
));
6939 sprintf (buf
, "bra %s", mri_control_stack
->next
);
6943 colon (mri_control_stack
->bottom
);
6949 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6950 ++input_line_pointer
;
6953 demand_empty_rest_of_line ();
6956 /* Parse a .cpu directive. */
6959 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED
)
6966 as_bad (_("already assembled instructions"));
6967 ignore_rest_of_line ();
6971 name
= input_line_pointer
;
6972 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
6973 input_line_pointer
++;
6974 saved_char
= *input_line_pointer
;
6975 *input_line_pointer
= 0;
6977 m68k_set_cpu (name
, 1, 0);
6979 *input_line_pointer
= saved_char
;
6980 demand_empty_rest_of_line ();
6984 /* Parse a .arch directive. */
6987 s_m68k_arch (int ignored ATTRIBUTE_UNUSED
)
6994 as_bad (_("already assembled instructions"));
6995 ignore_rest_of_line ();
6999 name
= input_line_pointer
;
7000 while (*input_line_pointer
&& *input_line_pointer
!= ','
7001 && !ISSPACE (*input_line_pointer
))
7002 input_line_pointer
++;
7003 saved_char
= *input_line_pointer
;
7004 *input_line_pointer
= 0;
7006 if (m68k_set_arch (name
, 1, 0))
7008 /* Scan extensions. */
7011 *input_line_pointer
++ = saved_char
;
7012 if (!*input_line_pointer
|| ISSPACE (*input_line_pointer
))
7014 name
= input_line_pointer
;
7015 while (*input_line_pointer
&& *input_line_pointer
!= ','
7016 && !ISSPACE (*input_line_pointer
))
7017 input_line_pointer
++;
7018 saved_char
= *input_line_pointer
;
7019 *input_line_pointer
= 0;
7021 while (m68k_set_extension (name
, 1, 0));
7024 *input_line_pointer
= saved_char
;
7025 demand_empty_rest_of_line ();
7029 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7030 if none is found, the caller is responsible for emitting an error
7031 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7032 cpu name, if it begins with a '6' (possibly skipping an intervening
7033 'c'. We also allow a 'c' in the same place. if NEGATED is
7034 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7035 the option is indeed negated. */
7037 static const struct m68k_cpu
*
7038 m68k_lookup_cpu (const char *arg
, const struct m68k_cpu
*table
,
7039 int allow_m
, int *negated
)
7041 /* allow negated value? */
7046 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
7053 /* Remove 'm' or 'mc' prefix from 68k variants. */
7060 else if (arg
[1] == 'c' && arg
[2] == '6')
7064 else if (arg
[0] == 'c' && arg
[1] == '6')
7067 for (; table
->name
; table
++)
7068 if (!strcmp (arg
, table
->name
))
7070 if (table
->alias
< -1 || table
->alias
> 1)
7071 as_bad (_("`%s' is deprecated, use `%s'"),
7072 table
->name
, table
[table
->alias
< 0 ? 1 : -1].name
);
7078 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7081 m68k_set_cpu (char const *name
, int allow_m
, int silent
)
7083 const struct m68k_cpu
*cpu
;
7085 cpu
= m68k_lookup_cpu (name
, m68k_cpus
, allow_m
, NULL
);
7090 as_bad (_("cpu `%s' unrecognized"), name
);
7094 if (selected_cpu
&& selected_cpu
!= cpu
)
7096 as_bad (_("already selected `%s' processor"),
7097 selected_cpu
->name
);
7104 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7107 m68k_set_arch (char const *name
, int allow_m
, int silent
)
7109 const struct m68k_cpu
*arch
;
7111 arch
= m68k_lookup_cpu (name
, m68k_archs
, allow_m
, NULL
);
7116 as_bad (_("architecture `%s' unrecognized"), name
);
7120 if (selected_arch
&& selected_arch
!= arch
)
7122 as_bad (_("already selected `%s' architecture"),
7123 selected_arch
->name
);
7127 selected_arch
= arch
;
7131 /* Set the architecture extension, issuing errors if it is
7132 unrecognized, or invalid */
7135 m68k_set_extension (char const *name
, int allow_m
, int silent
)
7138 const struct m68k_cpu
*ext
;
7140 ext
= m68k_lookup_cpu (name
, m68k_extensions
, allow_m
, &negated
);
7145 as_bad (_("extension `%s' unrecognized"), name
);
7150 not_current_architecture
|= ext
->arch
;
7152 current_architecture
|= ext
->arch
;
7157 Invocation line includes a switch not recognized by the base assembler.
7161 const char *md_shortopts
= "lSA:m:kQ:V";
7163 const char *md_shortopts
= "lSA:m:k";
7166 struct option md_longopts
[] = {
7167 #define OPTION_PIC (OPTION_MD_BASE)
7168 {"pic", no_argument
, NULL
, OPTION_PIC
},
7169 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7170 {"register-prefix-optional", no_argument
, NULL
,
7171 OPTION_REGISTER_PREFIX_OPTIONAL
},
7172 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7173 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
7174 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7175 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
7176 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7177 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
7178 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7179 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
7180 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7181 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
7182 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7183 {"pcrel", no_argument
, NULL
, OPTION_PCREL
},
7184 {NULL
, no_argument
, NULL
, 0}
7186 size_t md_longopts_size
= sizeof (md_longopts
);
7189 md_parse_option (int c
, char *arg
)
7193 case 'l': /* -l means keep external to 2 bit offset
7194 rather than 16 bit one. */
7195 flag_short_refs
= 1;
7198 case 'S': /* -S means that jbsr's always turn into
7200 flag_long_jumps
= 1;
7203 case OPTION_PCREL
: /* --pcrel means never turn PC-relative
7204 branches into absolute jumps. */
7205 flag_keep_pcrel
= 1;
7211 break; /* -pic, Position Independent Code. */
7213 case OPTION_REGISTER_PREFIX_OPTIONAL
:
7214 flag_reg_prefix_optional
= 1;
7215 reg_prefix_optional_seen
= 1;
7218 /* -V: SVR4 argument to print version ID. */
7220 print_version_id ();
7223 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7224 should be emitted or not. FIXME: Not implemented. */
7228 case OPTION_BITWISE_OR
:
7233 n
= (char *) xmalloc (strlen (m68k_comment_chars
) + 1);
7235 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
7239 m68k_comment_chars
= n
;
7243 case OPTION_BASE_SIZE_DEFAULT_16
:
7244 m68k_index_width_default
= SIZE_WORD
;
7247 case OPTION_BASE_SIZE_DEFAULT_32
:
7248 m68k_index_width_default
= SIZE_LONG
;
7251 case OPTION_DISP_SIZE_DEFAULT_16
:
7253 m68k_rel32_from_cmdline
= 1;
7256 case OPTION_DISP_SIZE_DEFAULT_32
:
7258 m68k_rel32_from_cmdline
= 1;
7263 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7266 /* Intentional fall-through. */
7268 if (!strncmp (arg
, "arch=", 5))
7269 m68k_set_arch (arg
+ 5, 1, 0);
7270 else if (!strncmp (arg
, "cpu=", 4))
7271 m68k_set_cpu (arg
+ 4, 1, 0);
7272 else if (m68k_set_extension (arg
, 0, 1))
7274 else if (m68k_set_arch (arg
, 0, 1))
7276 else if (m68k_set_cpu (arg
, 0, 1))
7289 /* Setup tables from the selected arch and/or cpu */
7292 m68k_init_arch (void)
7294 if (not_current_architecture
& current_architecture
)
7296 as_bad (_("architecture features both enabled and disabled"));
7297 not_current_architecture
&= ~current_architecture
;
7301 current_architecture
|= selected_arch
->arch
;
7302 control_regs
= selected_arch
->control_regs
;
7305 current_architecture
|= selected_cpu
->arch
;
7307 current_architecture
&= ~not_current_architecture
;
7309 if ((current_architecture
& (cfloat
| m68881
)) == (cfloat
| m68881
))
7311 /* Determine which float is really meant. */
7312 if (current_architecture
& (m68k_mask
& ~m68881
))
7313 current_architecture
^= cfloat
;
7315 current_architecture
^= m68881
;
7320 control_regs
= selected_cpu
->control_regs
;
7321 if (current_architecture
& ~selected_cpu
->arch
)
7323 as_bad (_("selected processor does not have all features of selected architecture"));
7324 current_architecture
7325 = selected_cpu
->arch
& ~not_current_architecture
;
7329 if ((current_architecture
& m68k_mask
)
7330 && (current_architecture
& ~m68k_mask
))
7332 as_bad (_ ("m68k and cf features both selected"));
7333 if (current_architecture
& m68k_mask
)
7334 current_architecture
&= m68k_mask
;
7336 current_architecture
&= ~m68k_mask
;
7339 /* Permit m68881 specification with all cpus; those that can't work
7340 with a coprocessor could be doing emulation. */
7341 if (current_architecture
& m68851
)
7343 if (current_architecture
& m68040
)
7344 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7346 /* What other incompatibilities could we check for? */
7348 if (cpu_of_arch (current_architecture
) < m68020
7349 || arch_coldfire_p (current_architecture
))
7350 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
7356 md_show_usage (FILE *stream
)
7358 const char *default_cpu
= TARGET_CPU
;
7360 unsigned int default_arch
;
7362 /* Get the canonical name for the default target CPU. */
7363 if (*default_cpu
== 'm')
7365 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7367 if (strcasecmp (default_cpu
, m68k_cpus
[i
].name
) == 0)
7369 default_arch
= m68k_cpus
[i
].arch
;
7370 while (m68k_cpus
[i
].alias
> 0)
7372 while (m68k_cpus
[i
].alias
< 0)
7374 default_cpu
= m68k_cpus
[i
].name
;
7378 fprintf (stream
, _("\
7379 -march=<arch> set architecture\n\
7380 -mcpu=<cpu> set cpu [default %s]\n\
7382 for (i
= 0; m68k_extensions
[i
].name
; i
++)
7383 fprintf (stream
, _("\
7384 -m[no-]%-16s enable/disable%s architecture extension\n\
7385 "), m68k_extensions
[i
].name
,
7386 m68k_extensions
[i
].alias
> 0 ? " ColdFire"
7387 : m68k_extensions
[i
].alias
< 0 ? " m68k" : "");
7389 fprintf (stream
, _("\
7390 -l use 1 word for refs to undefined symbols [default 2]\n\
7391 -pic, -k generate position independent code\n\
7392 -S turn jbsr into jsr\n\
7393 --pcrel never turn PC-relative branches into absolute jumps\n\
7394 --register-prefix-optional\n\
7395 recognize register names without prefix character\n\
7396 --bitwise-or do not treat `|' as a comment character\n\
7397 --base-size-default-16 base reg without size is 16 bits\n\
7398 --base-size-default-32 base reg without size is 32 bits (default)\n\
7399 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7400 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7403 fprintf (stream
, _("Architecture variants are: "));
7404 for (i
= 0; m68k_archs
[i
].name
; i
++)
7407 fprintf (stream
, " | ");
7408 fprintf (stream
, m68k_archs
[i
].name
);
7410 fprintf (stream
, "\n");
7412 fprintf (stream
, _("Processor variants are: "));
7413 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7416 fprintf (stream
, " | ");
7417 fprintf (stream
, m68k_cpus
[i
].name
);
7419 fprintf (stream
, _("\n"));
7424 /* TEST2: Test md_assemble() */
7425 /* Warning, this routine probably doesn't work anymore. */
7429 struct m68k_it the_ins
;
7437 if (!gets (buf
) || !*buf
)
7439 if (buf
[0] == '|' || buf
[1] == '.')
7441 for (cp
= buf
; *cp
; cp
++)
7446 memset (&the_ins
, '\0', sizeof (the_ins
));
7447 m68k_ip (&the_ins
, buf
);
7450 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
7454 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
7455 for (n
= 0; n
< the_ins
.numo
; n
++)
7456 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
7458 print_the_insn (&the_ins
.opcode
[0], stdout
);
7459 (void) putchar ('\n');
7461 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
7463 if (the_ins
.operands
[n
].error
)
7465 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
7468 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
,
7469 the_ins
.operands
[n
].reg
);
7470 if (the_ins
.operands
[n
].b_const
)
7471 printf ("Constant: '%.*s', ",
7472 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
,
7473 the_ins
.operands
[n
].b_const
);
7474 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
,
7475 the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
7476 if (the_ins
.operands
[n
].b_iadd
)
7477 printf ("Iadd: '%.*s',",
7478 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
,
7479 the_ins
.operands
[n
].b_iadd
);
7488 is_label (char *str
)
7492 while (*str
&& *str
!= ' ')
7494 if (str
[-1] == ':' || str
[1] == '=')
7501 /* Possible states for relaxation:
7503 0 0 branch offset byte (bra, etc)
7507 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7511 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7518 /* We have no need to default values of symbols. */
7521 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7526 /* Round up a section size to the appropriate boundary. */
7528 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7531 /* For a.out, force the section size to be aligned. If we don't do
7532 this, BFD will align it for us, but it will not write out the
7533 final bytes of the section. This may be a bug in BFD, but it is
7534 easier to fix it here since that is how the other a.out targets
7538 align
= bfd_get_section_alignment (stdoutput
, segment
);
7539 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7545 /* Exactly what point is a PC-relative offset relative TO?
7546 On the 68k, it is relative to the address of the first extension
7547 word. The difference between the addresses of the offset and the
7548 first extension word is stored in fx_pcrel_adjust. */
7550 md_pcrel_from (fixS
*fixP
)
7554 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7555 sign extend the value here. */
7556 adjust
= ((fixP
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80;
7559 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
7564 m68k_elf_final_processing (void)
7568 if (arch_coldfire_fpu (current_architecture
))
7569 flags
|= EF_M68K_CFV4E
;
7570 /* Set file-specific flags if this is a cpu32 processor. */
7571 if (cpu_of_arch (current_architecture
) & cpu32
)
7572 flags
|= EF_M68K_CPU32
;
7573 else if (cpu_of_arch (current_architecture
) & fido_a
)
7574 flags
|= EF_M68K_FIDO
;
7575 else if ((cpu_of_arch (current_architecture
) & m68000up
)
7576 && !(cpu_of_arch (current_architecture
) & m68020up
))
7577 flags
|= EF_M68K_M68000
;
7579 if (current_architecture
& mcfisa_a
)
7581 static const unsigned isa_features
[][2] =
7583 {EF_M68K_CF_ISA_A_NODIV
, mcfisa_a
},
7584 {EF_M68K_CF_ISA_A
, mcfisa_a
|mcfhwdiv
},
7585 {EF_M68K_CF_ISA_A_PLUS
,mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfusp
},
7586 {EF_M68K_CF_ISA_B_NOUSP
,mcfisa_a
|mcfisa_b
|mcfhwdiv
},
7587 {EF_M68K_CF_ISA_B
, mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfusp
},
7590 static const unsigned mac_features
[][2] =
7592 {EF_M68K_CF_MAC
, mcfmac
},
7593 {EF_M68K_CF_EMAC
, mcfemac
},
7599 pattern
= (current_architecture
7600 & (mcfisa_a
|mcfisa_aa
|mcfisa_b
|mcfhwdiv
|mcfusp
));
7601 for (ix
= 0; isa_features
[ix
][1]; ix
++)
7603 if (pattern
== isa_features
[ix
][1])
7605 flags
|= isa_features
[ix
][0];
7609 if (!isa_features
[ix
][1])
7612 as_warn (_("Not a defined coldfire architecture"));
7616 if (current_architecture
& cfloat
)
7617 flags
|= EF_M68K_CF_FLOAT
| EF_M68K_CFV4E
;
7619 pattern
= current_architecture
& (mcfmac
|mcfemac
);
7622 for (ix
= 0; mac_features
[ix
][1]; ix
++)
7624 if (pattern
== mac_features
[ix
][1])
7626 flags
|= mac_features
[ix
][0];
7630 if (!mac_features
[ix
][1])
7635 elf_elfheader (stdoutput
)->e_flags
|= flags
;
7640 tc_m68k_regname_to_dw2regnum (char *regname
)
7642 unsigned int regnum
;
7643 static const char *const regnames
[] =
7645 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7646 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7647 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7651 for (regnum
= 0; regnum
< ARRAY_SIZE (regnames
); regnum
++)
7652 if (strcmp (regname
, regnames
[regnum
]) == 0)
7659 tc_m68k_frame_initial_instructions (void)
7661 static int sp_regno
= -1;
7664 sp_regno
= tc_m68k_regname_to_dw2regnum ("sp");
7666 cfi_add_CFA_def_cfa (sp_regno
, -DWARF2_CIE_DATA_ALIGNMENT
);
7667 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, DWARF2_CIE_DATA_ALIGNMENT
);