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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 #include <ctype.h>
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if defined (TE_SVR4) || defined (TE_DELTA)
35 const char *m68k_comment_chars = "|#";
36 #else
37 const char *m68k_comment_chars = "|";
38 #endif
39
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars[] = "#";
48
49 const char line_separator_chars[] = "";
50
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST char EXP_CHARS[] = "eE";
53
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
56
57 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
58
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
62
63 const int md_reloc_size = 8; /* Size of relocation record */
64
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
69 int flag_want_pic;
70
71 static int flag_short_refs; /* -l option */
72 static int flag_long_jumps; /* -S option */
73
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
76 #else
77 int flag_reg_prefix_optional;
78 #endif
79
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen;
82
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum = COP1;
85
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd;
89
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick = 1;
93
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
96 be 32 bits. */
97 static int m68k_rel32 = 1;
98
99 /* This is non-zero if m68k_rel32 was set from the command line. */
100 static int m68k_rel32_from_cmdline;
101
102 /* The default width to use for an index register when using a base
103 displacement. */
104 static enum m68k_size m68k_index_width_default = SIZE_LONG;
105
106 /* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
108 label. */
109
110 struct label_line
111 {
112 struct label_line *next;
113 symbolS *label;
114 char *file;
115 unsigned int line;
116 int text;
117 };
118
119 /* The list of labels. */
120
121 static struct label_line *labels;
122
123 /* The current label. */
124
125 static struct label_line *current_label;
126
127 /* Its an arbitrary name: This means I don't approve of it */
128 /* See flames below */
129 static struct obstack robyn;
130
131 #define TAB(x,y) (((x)<<2)+(y))
132 #define TABTYPE(xy) ((xy) >> 2)
133 #define BYTE 0
134 #define SHORT 1
135 #define LONG 2
136 #define SZ_UNDEF 3
137 #undef BRANCH
138 /* Case `g' except when BCC68000 is applicable. */
139 #define ABRANCH 1
140 /* Coprocessor branches. */
141 #define FBRANCH 2
142 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
144 #define PCREL 3
145 /* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
150 #define BCC68000 4
151 /* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
153 #define DBCC 5
154 /* Not currently used? */
155 #define PCLEA 6
156 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
157 in 16 or 8 bits. */
158 #define PCINDEX 7
159
160 struct m68k_incant
161 {
162 const char *m_operands;
163 unsigned long m_opcode;
164 short m_opnum;
165 short m_codenum;
166 int m_arch;
167 struct m68k_incant *m_next;
168 };
169
170 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171 #define gettwo(x) (((x)->m_opcode)&0xffff)
172
173 static const enum m68k_register m68000_control_regs[] = { 0 };
174 static const enum m68k_register m68010_control_regs[] = {
175 SFC, DFC, USP, VBR,
176 0
177 };
178 static const enum m68k_register m68020_control_regs[] = {
179 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
180 0
181 };
182 static const enum m68k_register m68040_control_regs[] = {
183 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
184 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
185 0
186 };
187 static const enum m68k_register m68060_control_regs[] = {
188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
189 USP, VBR, URP, SRP, PCR,
190 0
191 };
192 static const enum m68k_register mcf5200_control_regs[] = {
193 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
194 RAMBAR0, RAMBAR1, MBAR,
195 0
196 };
197 #define cpu32_control_regs m68010_control_regs
198
199 static const enum m68k_register *control_regs;
200
201 /* internal form of a 68020 instruction */
202 struct m68k_it
203 {
204 const char *error;
205 const char *args; /* list of opcode info */
206 int numargs;
207
208 int numo; /* Number of shorts in opcode */
209 short opcode[11];
210
211 struct m68k_op operands[6];
212
213 int nexp; /* number of exprs in use */
214 struct m68k_exp exprs[4];
215
216 int nfrag; /* Number of frags we have to produce */
217 struct
218 {
219 int fragoff; /* Where in the current opcode the frag ends */
220 symbolS *fadd;
221 long foff;
222 int fragty;
223 }
224 fragb[4];
225
226 int nrel; /* Num of reloc strucs in use */
227 struct
228 {
229 int n;
230 expressionS exp;
231 char wid;
232 char pcrel;
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
239 example). */
240 int pcrel_fix;
241 #ifdef OBJ_ELF
242 /* Whether this expression needs special pic relocation, and if
243 so, which. */
244 enum pic_relocation pic_reloc;
245 #endif
246 }
247 reloc[5]; /* Five is enough??? */
248 };
249
250 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
251 #define float_of_arch(x) ((x) & mfloat)
252 #define mmu_of_arch(x) ((x) & mmmu)
253
254 /* Macros for determining if cpu supports a specific addressing mode */
255 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
256
257 static struct m68k_it the_ins; /* the instruction being assembled */
258
259 #define op(ex) ((ex)->exp.X_op)
260 #define adds(ex) ((ex)->exp.X_add_symbol)
261 #define subs(ex) ((ex)->exp.X_op_symbol)
262 #define offs(ex) ((ex)->exp.X_add_number)
263
264 /* Macros for adding things to the m68k_it struct */
265
266 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
267
268 /* Like addword, but goes BEFORE general operands */
269 static void
270 insop (w, opcode)
271 int w;
272 struct m68k_incant *opcode;
273 {
274 int z;
275 for(z=the_ins.numo;z>opcode->m_codenum;--z)
276 the_ins.opcode[z]=the_ins.opcode[z-1];
277 for(z=0;z<the_ins.nrel;z++)
278 the_ins.reloc[z].n+=2;
279 for (z = 0; z < the_ins.nfrag; z++)
280 the_ins.fragb[z].fragoff++;
281 the_ins.opcode[opcode->m_codenum]=w;
282 the_ins.numo++;
283 }
284
285 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
286 Blecch. */
287 static void
288 add_fix (width, exp, pc_rel, pc_fix)
289 char width;
290 struct m68k_exp *exp;
291 int pc_rel;
292 int pc_fix;
293 {
294 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
295 ? (the_ins.numo*2-1)
296 : (((width)=='b')
297 ? (the_ins.numo*2+1)
298 : (the_ins.numo*2)));
299 the_ins.reloc[the_ins.nrel].exp = exp->exp;
300 the_ins.reloc[the_ins.nrel].wid = width;
301 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
302 #ifdef OBJ_ELF
303 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
304 #endif
305 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
306 }
307
308 /* Cause an extra frag to be generated here, inserting up to 10 bytes
309 (that value is chosen in the frag_var call in md_assemble). TYPE
310 is the subtype of the frag to be generated; its primary type is
311 rs_machine_dependent.
312
313 The TYPE parameter is also used by md_convert_frag_1 and
314 md_estimate_size_before_relax. The appropriate type of fixup will
315 be emitted by md_convert_frag_1.
316
317 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
318 static void
319 add_frag(add,off,type)
320 symbolS *add;
321 long off;
322 int type;
323 {
324 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
325 the_ins.fragb[the_ins.nfrag].fadd=add;
326 the_ins.fragb[the_ins.nfrag].foff=off;
327 the_ins.fragb[the_ins.nfrag++].fragty=type;
328 }
329
330 #define isvar(ex) \
331 (op (ex) != O_constant && op (ex) != O_big)
332
333 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
334 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
335 static int reverse_16_bits PARAMS ((int in));
336 static int reverse_8_bits PARAMS ((int in));
337 static void install_gen_operand PARAMS ((int mode, int val));
338 static void install_operand PARAMS ((int mode, int val));
339 static void s_bss PARAMS ((int));
340 static void s_data1 PARAMS ((int));
341 static void s_data2 PARAMS ((int));
342 static void s_even PARAMS ((int));
343 static void s_proc PARAMS ((int));
344 static void mri_chip PARAMS ((void));
345 static void s_chip PARAMS ((int));
346 static void s_fopt PARAMS ((int));
347 static void s_opt PARAMS ((int));
348 static void s_reg PARAMS ((int));
349 static void s_restore PARAMS ((int));
350 static void s_save PARAMS ((int));
351 static void s_mri_if PARAMS ((int));
352 static void s_mri_else PARAMS ((int));
353 static void s_mri_endi PARAMS ((int));
354 static void s_mri_break PARAMS ((int));
355 static void s_mri_next PARAMS ((int));
356 static void s_mri_for PARAMS ((int));
357 static void s_mri_endf PARAMS ((int));
358 static void s_mri_repeat PARAMS ((int));
359 static void s_mri_until PARAMS ((int));
360 static void s_mri_while PARAMS ((int));
361 static void s_mri_endw PARAMS ((int));
362
363 static int current_architecture;
364
365 struct m68k_cpu {
366 unsigned long arch;
367 const char *name;
368 int alias;
369 };
370
371 static const struct m68k_cpu archs[] = {
372 { m68000, "68000", 0 },
373 { m68010, "68010", 0 },
374 { m68020, "68020", 0 },
375 { m68030, "68030", 0 },
376 { m68040, "68040", 0 },
377 { m68060, "68060", 0 },
378 { cpu32, "cpu32", 0 },
379 { m68881, "68881", 0 },
380 { m68851, "68851", 0 },
381 { mcf5200, "5200", 0 },
382 /* Aliases (effectively, so far as gas is concerned) for the above
383 cpus. */
384 { m68020, "68k", 1 },
385 { m68000, "68302", 1 },
386 { m68000, "68008", 1 },
387 { m68000, "68ec000", 1 },
388 { m68000, "68hc000", 1 },
389 { m68000, "68hc001", 1 },
390 { m68020, "68ec020", 1 },
391 { m68030, "68ec030", 1 },
392 { m68040, "68ec040", 1 },
393 { m68060, "68ec060", 1 },
394 { cpu32, "68330", 1 },
395 { cpu32, "68331", 1 },
396 { cpu32, "68332", 1 },
397 { cpu32, "68333", 1 },
398 { cpu32, "68340", 1 },
399 { cpu32, "68360", 1 },
400 { m68881, "68882", 1 },
401 };
402
403 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
404
405 /* BCC68000 is for patching in an extra jmp instruction for long offsets
406 on the 68000. The 68000 doesn't support long branches with branchs */
407
408 /* This table desribes how you change sizes for the various types of variable
409 size expressions. This version only supports two kinds. */
410
411 /* Note that calls to frag_var need to specify the maximum expansion
412 needed; this is currently 10 bytes for DBCC. */
413
414 /* The fields are:
415 How far Forward this mode will reach:
416 How far Backward this mode will reach:
417 How many bytes this mode will add to the size of the frag
418 Which mode to go to if the offset won't fit in this one
419 */
420 relax_typeS md_relax_table[] =
421 {
422 {1, 1, 0, 0}, /* First entries aren't used */
423 {1, 1, 0, 0}, /* For no good reason except */
424 {1, 1, 0, 0}, /* that the VAX doesn't either */
425 {1, 1, 0, 0},
426
427 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
428 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
429 {0, 0, 4, 0},
430 {1, 1, 0, 0},
431
432 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
433 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
434 {0, 0, 4, 0},
435 {1, 1, 0, 0},
436
437 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
438 {(32767), (-32768), 2, TAB (PCREL, LONG)},
439 {0, 0, 4, 0},
440 {1, 1, 0, 0},
441
442 {(127), (-128), 0, TAB (BCC68000, SHORT)},
443 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
444 {0, 0, 6, 0}, /* jmp long space */
445 {1, 1, 0, 0},
446
447 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
448 {(32767), (-32768), 2, TAB (DBCC, LONG)},
449 {0, 0, 10, 0}, /* bra/jmp long space */
450 {1, 1, 0, 0},
451
452 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
453 {32767, -32768, 2, TAB (PCLEA, LONG)},
454 {0, 0, 6, 0},
455 {1, 1, 0, 0},
456
457 /* For, e.g., jmp pcrel indexed. */
458 {125, -130, 0, TAB (PCINDEX, SHORT)},
459 {32765, -32770, 2, TAB (PCINDEX, LONG)},
460 {0, 0, 4, 0},
461 {1, 1, 0, 0},
462 };
463
464 /* These are the machine dependent pseudo-ops. These are included so
465 the assembler can work on the output from the SUN C compiler, which
466 generates these.
467 */
468
469 /* This table describes all the machine specific pseudo-ops the assembler
470 has to support. The fields are:
471 pseudo-op name without dot
472 function to call to execute this pseudo-op
473 Integer arg to pass to the function
474 */
475 const pseudo_typeS md_pseudo_table[] =
476 {
477 {"data1", s_data1, 0},
478 {"data2", s_data2, 0},
479 {"bss", s_bss, 0},
480 {"even", s_even, 0},
481 {"skip", s_space, 0},
482 {"proc", s_proc, 0},
483 #if defined (TE_SUN3) || defined (OBJ_ELF)
484 {"align", s_align_bytes, 0},
485 #endif
486 #ifdef OBJ_ELF
487 {"swbeg", s_ignore, 0},
488 #endif
489 {"extend", float_cons, 'x'},
490 {"ldouble", float_cons, 'x'},
491
492 /* The following pseudo-ops are supported for MRI compatibility. */
493 {"chip", s_chip, 0},
494 {"comline", s_space, 1},
495 {"fopt", s_fopt, 0},
496 {"mask2", s_ignore, 0},
497 {"opt", s_opt, 0},
498 {"reg", s_reg, 0},
499 {"restore", s_restore, 0},
500 {"save", s_save, 0},
501
502 {"if", s_mri_if, 0},
503 {"if.b", s_mri_if, 'b'},
504 {"if.w", s_mri_if, 'w'},
505 {"if.l", s_mri_if, 'l'},
506 {"else", s_mri_else, 0},
507 {"else.s", s_mri_else, 's'},
508 {"else.l", s_mri_else, 'l'},
509 {"endi", s_mri_endi, 0},
510 {"break", s_mri_break, 0},
511 {"break.s", s_mri_break, 's'},
512 {"break.l", s_mri_break, 'l'},
513 {"next", s_mri_next, 0},
514 {"next.s", s_mri_next, 's'},
515 {"next.l", s_mri_next, 'l'},
516 {"for", s_mri_for, 0},
517 {"for.b", s_mri_for, 'b'},
518 {"for.w", s_mri_for, 'w'},
519 {"for.l", s_mri_for, 'l'},
520 {"endf", s_mri_endf, 0},
521 {"repeat", s_mri_repeat, 0},
522 {"until", s_mri_until, 0},
523 {"until.b", s_mri_until, 'b'},
524 {"until.w", s_mri_until, 'w'},
525 {"until.l", s_mri_until, 'l'},
526 {"while", s_mri_while, 0},
527 {"while.b", s_mri_while, 'b'},
528 {"while.w", s_mri_while, 'w'},
529 {"while.l", s_mri_while, 'l'},
530 {"endw", s_mri_endw, 0},
531
532 {0, 0, 0}
533 };
534
535
536 /* The mote pseudo ops are put into the opcode table, since they
537 don't start with a . they look like opcodes to gas.
538 */
539 extern void obj_coff_section ();
540
541 CONST pseudo_typeS mote_pseudo_table[] =
542 {
543
544 {"dcl", cons, 4},
545 {"dc", cons, 2},
546 {"dcw", cons, 2},
547 {"dcb", cons, 1},
548
549 {"dsl", s_space, 4},
550 {"ds", s_space, 2},
551 {"dsw", s_space, 2},
552 {"dsb", s_space, 1},
553
554 {"xdef", s_globl, 0},
555 #ifdef OBJ_ELF
556 {"align", s_align_bytes, 0},
557 #else
558 {"align", s_align_ptwo, 0},
559 #endif
560 #ifdef M68KCOFF
561 {"sect", obj_coff_section, 0},
562 {"section", obj_coff_section, 0},
563 #endif
564 {0, 0, 0}
565 };
566
567 #define issbyte(x) ((x)>=-128 && (x)<=127)
568 #define isubyte(x) ((x)>=0 && (x)<=255)
569 #define issword(x) ((x)>=-32768 && (x)<=32767)
570 #define isuword(x) ((x)>=0 && (x)<=65535)
571
572 #define isbyte(x) ((x)>= -255 && (x)<=255)
573 #define isword(x) ((x)>=-65536 && (x)<=65535)
574 #define islong(x) (1)
575
576 extern char *input_line_pointer;
577
578 static char mklower_table[256];
579 #define mklower(c) (mklower_table[(unsigned char)(c)])
580 static char notend_table[256];
581 static char alt_notend_table[256];
582 #define notend(s) \
583 (! (notend_table[(unsigned char) *s] \
584 || (*s == ':' \
585 && alt_notend_table[(unsigned char) s[1]])))
586
587 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
588
589 #ifdef NO_PCREL_RELOCS
590
591 int
592 make_pcrel_absolute(fixP, add_number)
593 fixS *fixP;
594 long *add_number;
595 {
596 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
597
598 /* rewrite the PC relative instructions to absolute address ones.
599 * these are rumoured to be faster, and the apollo linker refuses
600 * to deal with the PC relative relocations.
601 */
602 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
603 {
604 opcode[0] = 0x4e;
605 opcode[1] = 0xf9;
606 }
607 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
608 {
609 opcode[0] = 0x4e;
610 opcode[1] = 0xb9;
611 }
612 else
613 as_fatal ("Unknown PC relative instruction");
614 *add_number -= 4;
615 return 0;
616 }
617
618 #endif /* NO_PCREL_RELOCS */
619
620 short
621 tc_coff_fix2rtype (fixP)
622 fixS *fixP;
623 {
624 if (fixP->fx_tcbit && fixP->fx_size == 4)
625 return R_RELLONG_NEG;
626 #ifdef NO_PCREL_RELOCS
627 know (fixP->fx_pcrel == 0);
628 return (fixP->fx_size == 1 ? R_RELBYTE
629 : fixP->fx_size == 2 ? R_DIR16
630 : R_DIR32);
631 #else
632 return (fixP->fx_pcrel ?
633 (fixP->fx_size == 1 ? R_PCRBYTE :
634 fixP->fx_size == 2 ? R_PCRWORD :
635 R_PCRLONG) :
636 (fixP->fx_size == 1 ? R_RELBYTE :
637 fixP->fx_size == 2 ? R_RELWORD :
638 R_RELLONG));
639 #endif
640 }
641
642 #endif
643
644 #ifdef OBJ_ELF
645
646 /* Compute the relocation code for a fixup of SIZE bytes, using pc
647 relative relocation if PCREL is non-zero. PIC says whether a special
648 pic relocation was requested. */
649
650 static bfd_reloc_code_real_type get_reloc_code
651 PARAMS ((int, int, enum pic_relocation));
652
653 static bfd_reloc_code_real_type
654 get_reloc_code (size, pcrel, pic)
655 int size;
656 int pcrel;
657 enum pic_relocation pic;
658 {
659 switch (pic)
660 {
661 case pic_got_pcrel:
662 switch (size)
663 {
664 case 1:
665 return BFD_RELOC_8_GOT_PCREL;
666 case 2:
667 return BFD_RELOC_16_GOT_PCREL;
668 case 4:
669 return BFD_RELOC_32_GOT_PCREL;
670 }
671 break;
672
673 case pic_got_off:
674 switch (size)
675 {
676 case 1:
677 return BFD_RELOC_8_GOTOFF;
678 case 2:
679 return BFD_RELOC_16_GOTOFF;
680 case 4:
681 return BFD_RELOC_32_GOTOFF;
682 }
683 break;
684
685 case pic_plt_pcrel:
686 switch (size)
687 {
688 case 1:
689 return BFD_RELOC_8_PLT_PCREL;
690 case 2:
691 return BFD_RELOC_16_PLT_PCREL;
692 case 4:
693 return BFD_RELOC_32_PLT_PCREL;
694 }
695 break;
696
697 case pic_plt_off:
698 switch (size)
699 {
700 case 1:
701 return BFD_RELOC_8_PLTOFF;
702 case 2:
703 return BFD_RELOC_16_PLTOFF;
704 case 4:
705 return BFD_RELOC_32_PLTOFF;
706 }
707 break;
708
709 case pic_none:
710 if (pcrel)
711 {
712 switch (size)
713 {
714 case 1:
715 return BFD_RELOC_8_PCREL;
716 case 2:
717 return BFD_RELOC_16_PCREL;
718 case 4:
719 return BFD_RELOC_32_PCREL;
720 }
721 }
722 else
723 {
724 switch (size)
725 {
726 case 1:
727 return BFD_RELOC_8;
728 case 2:
729 return BFD_RELOC_16;
730 case 4:
731 return BFD_RELOC_32;
732 }
733 }
734 }
735
736 as_bad ("Can not do %d byte %s%srelocation", size,
737 pcrel ? "pc-relative " : "",
738 pic == pic_none ? "" : "pic ");
739 return BFD_RELOC_NONE;
740 }
741
742 /* Here we decide which fixups can be adjusted to make them relative
743 to the beginning of the section instead of the symbol. Basically
744 we need to make sure that the dynamic relocations are done
745 correctly, so in some cases we force the original symbol to be
746 used. */
747 int
748 tc_m68k_fix_adjustable (fixP)
749 fixS *fixP;
750 {
751 /* Prevent all adjustments to global symbols. */
752 if (S_IS_EXTERNAL (fixP->fx_addsy))
753 return 0;
754
755 /* adjust_reloc_syms doesn't know about the GOT */
756 switch (fixP->fx_r_type)
757 {
758 case BFD_RELOC_8_GOT_PCREL:
759 case BFD_RELOC_16_GOT_PCREL:
760 case BFD_RELOC_32_GOT_PCREL:
761 case BFD_RELOC_8_GOTOFF:
762 case BFD_RELOC_16_GOTOFF:
763 case BFD_RELOC_32_GOTOFF:
764 case BFD_RELOC_8_PLT_PCREL:
765 case BFD_RELOC_16_PLT_PCREL:
766 case BFD_RELOC_32_PLT_PCREL:
767 case BFD_RELOC_8_PLTOFF:
768 case BFD_RELOC_16_PLTOFF:
769 case BFD_RELOC_32_PLTOFF:
770 return 0;
771
772 default:
773 return 1;
774 }
775 }
776
777 #else /* !OBJ_ELF */
778
779 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
780
781 #endif /* OBJ_ELF */
782
783 #ifdef BFD_ASSEMBLER
784
785 arelent *
786 tc_gen_reloc (section, fixp)
787 asection *section;
788 fixS *fixp;
789 {
790 arelent *reloc;
791 bfd_reloc_code_real_type code;
792
793 if (fixp->fx_tcbit)
794 abort ();
795
796 if (fixp->fx_r_type != BFD_RELOC_NONE)
797 {
798 code = fixp->fx_r_type;
799
800 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
801 that fixup_segment converted a non-PC relative reloc into a
802 PC relative reloc. In such a case, we need to convert the
803 reloc code. */
804 if (fixp->fx_pcrel)
805 {
806 switch (code)
807 {
808 case BFD_RELOC_8:
809 code = BFD_RELOC_8_PCREL;
810 break;
811 case BFD_RELOC_16:
812 code = BFD_RELOC_16_PCREL;
813 break;
814 case BFD_RELOC_32:
815 code = BFD_RELOC_32_PCREL;
816 break;
817 case BFD_RELOC_8_PCREL:
818 case BFD_RELOC_16_PCREL:
819 case BFD_RELOC_32_PCREL:
820 case BFD_RELOC_8_GOT_PCREL:
821 case BFD_RELOC_16_GOT_PCREL:
822 case BFD_RELOC_32_GOT_PCREL:
823 case BFD_RELOC_8_GOTOFF:
824 case BFD_RELOC_16_GOTOFF:
825 case BFD_RELOC_32_GOTOFF:
826 case BFD_RELOC_8_PLT_PCREL:
827 case BFD_RELOC_16_PLT_PCREL:
828 case BFD_RELOC_32_PLT_PCREL:
829 case BFD_RELOC_8_PLTOFF:
830 case BFD_RELOC_16_PLTOFF:
831 case BFD_RELOC_32_PLTOFF:
832 break;
833 default:
834 as_bad_where (fixp->fx_file, fixp->fx_line,
835 "Cannot make %s relocation PC relative",
836 bfd_get_reloc_code_name (code));
837 }
838 }
839 }
840 else
841 {
842 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
843 switch (F (fixp->fx_size, fixp->fx_pcrel))
844 {
845 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
846 MAP (1, 0, BFD_RELOC_8);
847 MAP (2, 0, BFD_RELOC_16);
848 MAP (4, 0, BFD_RELOC_32);
849 MAP (1, 1, BFD_RELOC_8_PCREL);
850 MAP (2, 1, BFD_RELOC_16_PCREL);
851 MAP (4, 1, BFD_RELOC_32_PCREL);
852 default:
853 abort ();
854 }
855 }
856 #undef F
857 #undef MAP
858
859 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
860 assert (reloc != 0);
861 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
862 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
863 #ifndef OBJ_ELF
864 if (fixp->fx_pcrel)
865 reloc->addend = fixp->fx_addnumber;
866 else
867 reloc->addend = 0;
868 #else
869 if (!fixp->fx_pcrel)
870 reloc->addend = fixp->fx_addnumber;
871 else
872 reloc->addend = (section->vma
873 + (fixp->fx_pcrel_adjust == 64
874 ? -1 : fixp->fx_pcrel_adjust)
875 + fixp->fx_addnumber
876 + md_pcrel_from (fixp));
877 #endif
878
879 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
880 assert (reloc->howto != 0);
881
882 return reloc;
883 }
884
885 #endif /* BFD_ASSEMBLER */
886
887 /* Handle of the OPCODE hash table. NULL means any use before
888 m68k_ip_begin() will crash. */
889 static struct hash_control *op_hash;
890 \f
891 /* Assemble an m68k instruction. */
892
893 void
894 m68k_ip (instring)
895 char *instring;
896 {
897 register char *p;
898 register struct m68k_op *opP;
899 register struct m68k_incant *opcode;
900 register const char *s;
901 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
902 char *pdot, *pdotmove;
903 enum m68k_size siz1, siz2;
904 char c;
905 int losing;
906 int opsfound;
907 char *crack_operand ();
908 LITTLENUM_TYPE words[6];
909 LITTLENUM_TYPE *wordp;
910 unsigned long ok_arch = 0;
911
912 if (*instring == ' ')
913 instring++; /* skip leading whitespace */
914
915 /* Scan up to end of operation-code, which MUST end in end-of-string
916 or exactly 1 space. */
917 pdot = 0;
918 for (p = instring; *p != '\0'; p++)
919 {
920 if (*p == ' ')
921 break;
922 if (*p == '.')
923 pdot = p;
924 }
925
926 if (p == instring)
927 {
928 the_ins.error = "No operator";
929 return;
930 }
931
932 /* p now points to the end of the opcode name, probably whitespace.
933 Make sure the name is null terminated by clobbering the
934 whitespace, look it up in the hash table, then fix it back.
935 Remove a dot, first, since the opcode tables have none. */
936 if (pdot != NULL)
937 {
938 for (pdotmove = pdot; pdotmove < p; pdotmove++)
939 *pdotmove = pdotmove[1];
940 p--;
941 }
942
943 c = *p;
944 *p = '\0';
945 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
946 *p = c;
947
948 if (pdot != NULL)
949 {
950 for (pdotmove = p; pdotmove > pdot; pdotmove--)
951 *pdotmove = pdotmove[-1];
952 *pdot = '.';
953 ++p;
954 }
955
956 if (opcode == NULL)
957 {
958 the_ins.error = "Unknown operator";
959 return;
960 }
961
962 /* found a legitimate opcode, start matching operands */
963 while (*p == ' ')
964 ++p;
965
966 if (opcode->m_operands == 0)
967 {
968 char *old = input_line_pointer;
969 *old = '\n';
970 input_line_pointer = p;
971 /* Ahh - it's a motorola style psuedo op */
972 mote_pseudo_table[opcode->m_opnum].poc_handler
973 (mote_pseudo_table[opcode->m_opnum].poc_val);
974 input_line_pointer = old;
975 *old = 0;
976
977 return;
978 }
979
980 if (flag_mri && opcode->m_opnum == 0)
981 {
982 /* In MRI mode, random garbage is allowed after an instruction
983 which accepts no operands. */
984 the_ins.args = opcode->m_operands;
985 the_ins.numargs = opcode->m_opnum;
986 the_ins.numo = opcode->m_codenum;
987 the_ins.opcode[0] = getone (opcode);
988 the_ins.opcode[1] = gettwo (opcode);
989 return;
990 }
991
992 for (opP = &the_ins.operands[0]; *p; opP++)
993 {
994 p = crack_operand (p, opP);
995
996 if (opP->error)
997 {
998 the_ins.error = opP->error;
999 return;
1000 }
1001 }
1002
1003 opsfound = opP - &the_ins.operands[0];
1004
1005 /* This ugly hack is to support the floating pt opcodes in their
1006 standard form. Essentially, we fake a first enty of type COP#1 */
1007 if (opcode->m_operands[0] == 'I')
1008 {
1009 int n;
1010
1011 for (n = opsfound; n > 0; --n)
1012 the_ins.operands[n] = the_ins.operands[n - 1];
1013
1014 memset ((char *) (&the_ins.operands[0]), '\0',
1015 sizeof (the_ins.operands[0]));
1016 the_ins.operands[0].mode = CONTROL;
1017 the_ins.operands[0].reg = m68k_float_copnum;
1018 opsfound++;
1019 }
1020
1021 /* We've got the operands. Find an opcode that'll accept them */
1022 for (losing = 0;;)
1023 {
1024 /* If we didn't get the right number of ops, or we have no
1025 common model with this pattern then reject this pattern. */
1026
1027 ok_arch |= opcode->m_arch;
1028 if (opsfound != opcode->m_opnum
1029 || ((opcode->m_arch & current_architecture) == 0))
1030 ++losing;
1031 else
1032 {
1033 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1034 *s && !losing;
1035 s += 2, opP++)
1036 {
1037 /* Warning: this switch is huge! */
1038 /* I've tried to organize the cases into this order:
1039 non-alpha first, then alpha by letter. Lower-case
1040 goes directly before uppercase counterpart. */
1041 /* Code with multiple case ...: gets sorted by the lowest
1042 case ... it belongs to. I hope this makes sense. */
1043 switch (*s)
1044 {
1045 case '!':
1046 switch (opP->mode)
1047 {
1048 case IMMED:
1049 case DREG:
1050 case AREG:
1051 case FPREG:
1052 case CONTROL:
1053 case AINC:
1054 case ADEC:
1055 case REGLST:
1056 losing++;
1057 break;
1058 default:
1059 break;
1060 }
1061 break;
1062
1063 case '`':
1064 switch (opP->mode)
1065 {
1066 case IMMED:
1067 case DREG:
1068 case AREG:
1069 case FPREG:
1070 case CONTROL:
1071 case AINC:
1072 case REGLST:
1073 case AINDR:
1074 losing++;
1075 break;
1076 default:
1077 break;
1078 }
1079 break;
1080
1081 case '<':
1082 switch (opP->mode)
1083 {
1084 case DREG:
1085 case AREG:
1086 case FPREG:
1087 case CONTROL:
1088 case IMMED:
1089 case ADEC:
1090 case REGLST:
1091 losing++;
1092 break;
1093 default:
1094 break;
1095 }
1096 break;
1097
1098 case '>':
1099 switch (opP->mode)
1100 {
1101 case DREG:
1102 case AREG:
1103 case FPREG:
1104 case CONTROL:
1105 case IMMED:
1106 case AINC:
1107 case REGLST:
1108 losing++;
1109 break;
1110 case ABSL:
1111 break;
1112 default:
1113 if (opP->reg == PC
1114 || opP->reg == ZPC)
1115 losing++;
1116 break;
1117 }
1118 break;
1119
1120 case 'm':
1121 switch (opP->mode)
1122 {
1123 case DREG:
1124 case AREG:
1125 case AINDR:
1126 case AINC:
1127 case ADEC:
1128 break;
1129 default:
1130 losing++;
1131 }
1132 break;
1133
1134 case 'n':
1135 switch (opP->mode)
1136 {
1137 case DISP:
1138 break;
1139 default:
1140 losing++;
1141 }
1142 break;
1143
1144 case 'o':
1145 switch (opP->mode)
1146 {
1147 case BASE:
1148 case ABSL:
1149 case IMMED:
1150 break;
1151 default:
1152 losing++;
1153 }
1154 break;
1155
1156 case 'p':
1157 switch (opP->mode)
1158 {
1159 case DREG:
1160 case AREG:
1161 case AINDR:
1162 case AINC:
1163 case ADEC:
1164 break;
1165 case DISP:
1166 if (opP->reg == PC || opP->reg == ZPC)
1167 losing++;
1168 break;
1169 default:
1170 losing++;
1171 }
1172 break;
1173
1174 case '#':
1175 if (opP->mode != IMMED)
1176 losing++;
1177 else if (s[1] == 'b'
1178 && ! isvar (&opP->disp)
1179 && (opP->disp.exp.X_op != O_constant
1180 || ! isbyte (opP->disp.exp.X_add_number)))
1181 losing++;
1182 else if (s[1] == 'B'
1183 && ! isvar (&opP->disp)
1184 && (opP->disp.exp.X_op != O_constant
1185 || ! issbyte (opP->disp.exp.X_add_number)))
1186 losing++;
1187 else if (s[1] == 'w'
1188 && ! isvar (&opP->disp)
1189 && (opP->disp.exp.X_op != O_constant
1190 || ! isword (opP->disp.exp.X_add_number)))
1191 losing++;
1192 else if (s[1] == 'W'
1193 && ! isvar (&opP->disp)
1194 && (opP->disp.exp.X_op != O_constant
1195 || ! issword (opP->disp.exp.X_add_number)))
1196 losing++;
1197 break;
1198
1199 case '^':
1200 case 'T':
1201 if (opP->mode != IMMED)
1202 losing++;
1203 break;
1204
1205 case '$':
1206 if (opP->mode == AREG
1207 || opP->mode == CONTROL
1208 || opP->mode == FPREG
1209 || opP->mode == IMMED
1210 || opP->mode == REGLST
1211 || (opP->mode != ABSL
1212 && (opP->reg == PC
1213 || opP->reg == ZPC)))
1214 losing++;
1215 break;
1216
1217 case '%':
1218 if (opP->mode == CONTROL
1219 || opP->mode == FPREG
1220 || opP->mode == REGLST
1221 || opP->mode == IMMED
1222 || (opP->mode != ABSL
1223 && (opP->reg == PC
1224 || opP->reg == ZPC)))
1225 losing++;
1226 break;
1227
1228 case '&':
1229 switch (opP->mode)
1230 {
1231 case DREG:
1232 case AREG:
1233 case FPREG:
1234 case CONTROL:
1235 case IMMED:
1236 case AINC:
1237 case ADEC:
1238 case REGLST:
1239 losing++;
1240 break;
1241 case ABSL:
1242 break;
1243 default:
1244 if (opP->reg == PC
1245 || opP->reg == ZPC)
1246 losing++;
1247 break;
1248 }
1249 break;
1250
1251 case '*':
1252 if (opP->mode == CONTROL
1253 || opP->mode == FPREG
1254 || opP->mode == REGLST)
1255 losing++;
1256 break;
1257
1258 case '+':
1259 if (opP->mode != AINC)
1260 losing++;
1261 break;
1262
1263 case '-':
1264 if (opP->mode != ADEC)
1265 losing++;
1266 break;
1267
1268 case '/':
1269 switch (opP->mode)
1270 {
1271 case AREG:
1272 case CONTROL:
1273 case FPREG:
1274 case AINC:
1275 case ADEC:
1276 case IMMED:
1277 case REGLST:
1278 losing++;
1279 break;
1280 default:
1281 break;
1282 }
1283 break;
1284
1285 case ';':
1286 switch (opP->mode)
1287 {
1288 case AREG:
1289 case CONTROL:
1290 case FPREG:
1291 case REGLST:
1292 losing++;
1293 break;
1294 default:
1295 break;
1296 }
1297 break;
1298
1299 case '?':
1300 switch (opP->mode)
1301 {
1302 case AREG:
1303 case CONTROL:
1304 case FPREG:
1305 case AINC:
1306 case ADEC:
1307 case IMMED:
1308 case REGLST:
1309 losing++;
1310 break;
1311 case ABSL:
1312 break;
1313 default:
1314 if (opP->reg == PC || opP->reg == ZPC)
1315 losing++;
1316 break;
1317 }
1318 break;
1319
1320 case '@':
1321 switch (opP->mode)
1322 {
1323 case AREG:
1324 case CONTROL:
1325 case FPREG:
1326 case IMMED:
1327 case REGLST:
1328 losing++;
1329 break;
1330 default:
1331 break;
1332 }
1333 break;
1334
1335 case '~': /* For now! (JF FOO is this right?) */
1336 switch (opP->mode)
1337 {
1338 case DREG:
1339 case AREG:
1340 case CONTROL:
1341 case FPREG:
1342 case IMMED:
1343 case REGLST:
1344 losing++;
1345 break;
1346 case ABSL:
1347 break;
1348 default:
1349 if (opP->reg == PC
1350 || opP->reg == ZPC)
1351 losing++;
1352 break;
1353 }
1354 break;
1355
1356 case '3':
1357 if (opP->mode != CONTROL
1358 || (opP->reg != TT0 && opP->reg != TT1))
1359 losing++;
1360 break;
1361
1362 case 'A':
1363 if (opP->mode != AREG)
1364 losing++;
1365 break;
1366
1367 case 'a':
1368 if (opP->mode != AINDR)
1369 ++losing;
1370 break;
1371
1372 case 'B': /* FOO */
1373 if (opP->mode != ABSL
1374 || (flag_long_jumps
1375 && strncmp (instring, "jbsr", 4) == 0))
1376 losing++;
1377 break;
1378
1379 case 'C':
1380 if (opP->mode != CONTROL || opP->reg != CCR)
1381 losing++;
1382 break;
1383
1384 case 'd':
1385 if (opP->mode != DISP
1386 || opP->reg < ADDR0
1387 || opP->reg > ADDR7)
1388 losing++;
1389 break;
1390
1391 case 'D':
1392 if (opP->mode != DREG)
1393 losing++;
1394 break;
1395
1396 case 'F':
1397 if (opP->mode != FPREG)
1398 losing++;
1399 break;
1400
1401 case 'I':
1402 if (opP->mode != CONTROL
1403 || opP->reg < COP0
1404 || opP->reg > COP7)
1405 losing++;
1406 break;
1407
1408 case 'J':
1409 if (opP->mode != CONTROL
1410 || opP->reg < USP
1411 || opP->reg > last_movec_reg)
1412 losing++;
1413 else
1414 {
1415 const enum m68k_register *rp;
1416 for (rp = control_regs; *rp; rp++)
1417 if (*rp == opP->reg)
1418 break;
1419 if (*rp == 0)
1420 losing++;
1421 }
1422 break;
1423
1424 case 'k':
1425 if (opP->mode != IMMED)
1426 losing++;
1427 break;
1428
1429 case 'l':
1430 case 'L':
1431 if (opP->mode == DREG
1432 || opP->mode == AREG
1433 || opP->mode == FPREG)
1434 {
1435 if (s[1] == '8')
1436 losing++;
1437 else
1438 {
1439 switch (opP->mode)
1440 {
1441 case DREG:
1442 opP->mask = 1 << (opP->reg - DATA0);
1443 break;
1444 case AREG:
1445 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1446 break;
1447 case FPREG:
1448 opP->mask = 1 << (opP->reg - FP0 + 16);
1449 break;
1450 default:
1451 abort ();
1452 }
1453 opP->mode = REGLST;
1454 }
1455 }
1456 else if (opP->mode == CONTROL)
1457 {
1458 if (s[1] != '8')
1459 losing++;
1460 else
1461 {
1462 switch (opP->reg)
1463 {
1464 case FPI:
1465 opP->mask = 1 << 24;
1466 break;
1467 case FPS:
1468 opP->mask = 1 << 25;
1469 break;
1470 case FPC:
1471 opP->mask = 1 << 26;
1472 break;
1473 default:
1474 losing++;
1475 break;
1476 }
1477 opP->mode = REGLST;
1478 }
1479 }
1480 else if (opP->mode == ABSL
1481 && opP->disp.size == SIZE_UNSPEC
1482 && opP->disp.exp.X_op == O_constant)
1483 {
1484 /* This is what the MRI REG pseudo-op generates. */
1485 opP->mode = REGLST;
1486 opP->mask = opP->disp.exp.X_add_number;
1487 }
1488 else if (opP->mode != REGLST)
1489 losing++;
1490 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1491 losing++;
1492 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1493 losing++;
1494 break;
1495
1496 case 'M':
1497 if (opP->mode != IMMED)
1498 losing++;
1499 else if (opP->disp.exp.X_op != O_constant
1500 || ! issbyte (opP->disp.exp.X_add_number))
1501 losing++;
1502 else if (! m68k_quick
1503 && instring[3] != 'q'
1504 && instring[4] != 'q')
1505 losing++;
1506 break;
1507
1508 case 'O':
1509 if (opP->mode != DREG
1510 && opP->mode != IMMED
1511 && opP->mode != ABSL)
1512 losing++;
1513 break;
1514
1515 case 'Q':
1516 if (opP->mode != IMMED)
1517 losing++;
1518 else if (opP->disp.exp.X_op != O_constant
1519 || opP->disp.exp.X_add_number < 1
1520 || opP->disp.exp.X_add_number > 8)
1521 losing++;
1522 else if (! m68k_quick
1523 && (strncmp (instring, "add", 3) == 0
1524 || strncmp (instring, "sub", 3) == 0)
1525 && instring[3] != 'q')
1526 losing++;
1527 break;
1528
1529 case 'R':
1530 if (opP->mode != DREG && opP->mode != AREG)
1531 losing++;
1532 break;
1533
1534 case 'r':
1535 if (opP->mode != AINDR
1536 && (opP->mode != BASE
1537 || (opP->reg != 0
1538 && opP->reg != ZADDR0)
1539 || opP->disp.exp.X_op != O_absent
1540 || ((opP->index.reg < DATA0
1541 || opP->index.reg > DATA7)
1542 && (opP->index.reg < ADDR0
1543 || opP->index.reg > ADDR7))
1544 || opP->index.size != SIZE_UNSPEC
1545 || opP->index.scale != 1))
1546 losing++;
1547 break;
1548
1549 case 's':
1550 if (opP->mode != CONTROL
1551 || ! (opP->reg == FPI
1552 || opP->reg == FPS
1553 || opP->reg == FPC))
1554 losing++;
1555 break;
1556
1557 case 'S':
1558 if (opP->mode != CONTROL || opP->reg != SR)
1559 losing++;
1560 break;
1561
1562 case 't':
1563 if (opP->mode != IMMED)
1564 losing++;
1565 else if (opP->disp.exp.X_op != O_constant
1566 || opP->disp.exp.X_add_number < 0
1567 || opP->disp.exp.X_add_number > 7)
1568 losing++;
1569 break;
1570
1571 case 'U':
1572 if (opP->mode != CONTROL || opP->reg != USP)
1573 losing++;
1574 break;
1575
1576 /* JF these are out of order. We could put them
1577 in order if we were willing to put up with
1578 bunches of #ifdef m68851s in the code.
1579
1580 Don't forget that you need these operands
1581 to use 68030 MMU instructions. */
1582 #ifndef NO_68851
1583 /* Memory addressing mode used by pflushr */
1584 case '|':
1585 if (opP->mode == CONTROL
1586 || opP->mode == FPREG
1587 || opP->mode == DREG
1588 || opP->mode == AREG
1589 || opP->mode == REGLST)
1590 losing++;
1591 /* We should accept immediate operands, but they
1592 supposedly have to be quad word, and we don't
1593 handle that. I would like to see what a Motorola
1594 assembler does before doing something here. */
1595 if (opP->mode == IMMED)
1596 losing++;
1597 break;
1598
1599 case 'f':
1600 if (opP->mode != CONTROL
1601 || (opP->reg != SFC && opP->reg != DFC))
1602 losing++;
1603 break;
1604
1605 case '0':
1606 if (opP->mode != CONTROL || opP->reg != TC)
1607 losing++;
1608 break;
1609
1610 case '1':
1611 if (opP->mode != CONTROL || opP->reg != AC)
1612 losing++;
1613 break;
1614
1615 case '2':
1616 if (opP->mode != CONTROL
1617 || (opP->reg != CAL
1618 && opP->reg != VAL
1619 && opP->reg != SCC))
1620 losing++;
1621 break;
1622
1623 case 'V':
1624 if (opP->mode != CONTROL
1625 || opP->reg != VAL)
1626 losing++;
1627 break;
1628
1629 case 'W':
1630 if (opP->mode != CONTROL
1631 || (opP->reg != DRP
1632 && opP->reg != SRP
1633 && opP->reg != CRP))
1634 losing++;
1635 break;
1636
1637 case 'X':
1638 if (opP->mode != CONTROL
1639 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1640 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1641 losing++;
1642 break;
1643
1644 case 'Y':
1645 if (opP->mode != CONTROL || opP->reg != PSR)
1646 losing++;
1647 break;
1648
1649 case 'Z':
1650 if (opP->mode != CONTROL || opP->reg != PCSR)
1651 losing++;
1652 break;
1653 #endif
1654 case 'c':
1655 if (opP->mode != CONTROL
1656 || (opP->reg != NC
1657 && opP->reg != IC
1658 && opP->reg != DC
1659 && opP->reg != BC))
1660 {
1661 losing++;
1662 } /* not a cache specifier. */
1663 break;
1664
1665 case '_':
1666 if (opP->mode != ABSL)
1667 ++losing;
1668 break;
1669
1670 default:
1671 abort ();
1672 } /* switch on type of operand */
1673
1674 if (losing)
1675 break;
1676 } /* for each operand */
1677 } /* if immediately wrong */
1678
1679 if (!losing)
1680 {
1681 break;
1682 } /* got it. */
1683
1684 opcode = opcode->m_next;
1685
1686 if (!opcode)
1687 {
1688 if (ok_arch
1689 && !(ok_arch & current_architecture))
1690 {
1691 char buf[200], *cp;
1692
1693 strcpy (buf,
1694 "invalid instruction for this architecture; needs ");
1695 cp = buf + strlen (buf);
1696 switch (ok_arch)
1697 {
1698 case mfloat:
1699 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1700 break;
1701 case mmmu:
1702 strcpy (cp, "mmu (68030 or 68851)");
1703 break;
1704 case m68020up:
1705 strcpy (cp, "68020 or higher");
1706 break;
1707 case m68000up:
1708 strcpy (cp, "68000 or higher");
1709 break;
1710 case m68010up:
1711 strcpy (cp, "68010 or higher");
1712 break;
1713 default:
1714 {
1715 int got_one = 0, idx;
1716 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1717 idx++)
1718 {
1719 if ((archs[idx].arch & ok_arch)
1720 && ! archs[idx].alias)
1721 {
1722 if (got_one)
1723 {
1724 strcpy (cp, " or ");
1725 cp += strlen (cp);
1726 }
1727 got_one = 1;
1728 strcpy (cp, archs[idx].name);
1729 cp += strlen (cp);
1730 }
1731 }
1732 }
1733 }
1734 cp = xmalloc (strlen (buf) + 1);
1735 strcpy (cp, buf);
1736 the_ins.error = cp;
1737 }
1738 else
1739 the_ins.error = "operands mismatch";
1740 return;
1741 } /* Fell off the end */
1742
1743 losing = 0;
1744 }
1745
1746 /* now assemble it */
1747
1748 the_ins.args = opcode->m_operands;
1749 the_ins.numargs = opcode->m_opnum;
1750 the_ins.numo = opcode->m_codenum;
1751 the_ins.opcode[0] = getone (opcode);
1752 the_ins.opcode[1] = gettwo (opcode);
1753
1754 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1755 {
1756 /* This switch is a doozy.
1757 Watch the first step; its a big one! */
1758 switch (s[0])
1759 {
1760
1761 case '*':
1762 case '~':
1763 case '%':
1764 case ';':
1765 case '@':
1766 case '!':
1767 case '&':
1768 case '$':
1769 case '?':
1770 case '/':
1771 case '`':
1772 case '<':
1773 case '>':
1774 case 'm':
1775 case 'n':
1776 case 'o':
1777 case 'p':
1778 #ifndef NO_68851
1779 case '|':
1780 #endif
1781 switch (opP->mode)
1782 {
1783 case IMMED:
1784 tmpreg = 0x3c; /* 7.4 */
1785 if (strchr ("bwl", s[1]))
1786 nextword = get_num (&opP->disp, 80);
1787 else
1788 nextword = get_num (&opP->disp, 0);
1789 if (isvar (&opP->disp))
1790 add_fix (s[1], &opP->disp, 0, 0);
1791 switch (s[1])
1792 {
1793 case 'b':
1794 if (!isbyte (nextword))
1795 opP->error = "operand out of range";
1796 addword (nextword);
1797 baseo = 0;
1798 break;
1799 case 'w':
1800 if (!isword (nextword))
1801 opP->error = "operand out of range";
1802 addword (nextword);
1803 baseo = 0;
1804 break;
1805 case 'W':
1806 if (!issword (nextword))
1807 opP->error = "operand out of range";
1808 addword (nextword);
1809 baseo = 0;
1810 break;
1811 case 'l':
1812 addword (nextword >> 16);
1813 addword (nextword);
1814 baseo = 0;
1815 break;
1816
1817 case 'f':
1818 baseo = 2;
1819 outro = 8;
1820 break;
1821 case 'F':
1822 baseo = 4;
1823 outro = 11;
1824 break;
1825 case 'x':
1826 baseo = 6;
1827 outro = 15;
1828 break;
1829 case 'p':
1830 baseo = 6;
1831 outro = -1;
1832 break;
1833 default:
1834 abort ();
1835 }
1836 if (!baseo)
1837 break;
1838
1839 /* We gotta put out some float */
1840 if (op (&opP->disp) != O_big)
1841 {
1842 valueT val;
1843 int gencnt;
1844
1845 /* Can other cases happen here? */
1846 if (op (&opP->disp) != O_constant)
1847 abort ();
1848
1849 val = (valueT) offs (&opP->disp);
1850 gencnt = 0;
1851 do
1852 {
1853 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1854 val >>= LITTLENUM_NUMBER_OF_BITS;
1855 ++gencnt;
1856 }
1857 while (val != 0);
1858 offs (&opP->disp) = gencnt;
1859 }
1860 if (offs (&opP->disp) > 0)
1861 {
1862 if (offs (&opP->disp) > baseo)
1863 {
1864 as_warn ("Bignum too big for %c format; truncated",
1865 s[1]);
1866 offs (&opP->disp) = baseo;
1867 }
1868 baseo -= offs (&opP->disp);
1869 while (baseo--)
1870 addword (0);
1871 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1872 offs (&opP->disp)--;
1873 --wordp)
1874 addword (*wordp);
1875 break;
1876 }
1877 gen_to_words (words, baseo, (long) outro);
1878 for (wordp = words; baseo--; wordp++)
1879 addword (*wordp);
1880 break;
1881 case DREG:
1882 tmpreg = opP->reg - DATA; /* 0.dreg */
1883 break;
1884 case AREG:
1885 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1886 break;
1887 case AINDR:
1888 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1889 break;
1890 case ADEC:
1891 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1892 break;
1893 case AINC:
1894 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1895 break;
1896 case DISP:
1897
1898 nextword = get_num (&opP->disp, 80);
1899
1900 if (opP->reg == PC
1901 && ! isvar (&opP->disp)
1902 && m68k_abspcadd)
1903 {
1904 opP->disp.exp.X_op = O_symbol;
1905 #ifndef BFD_ASSEMBLER
1906 opP->disp.exp.X_add_symbol = &abs_symbol;
1907 #else
1908 opP->disp.exp.X_add_symbol =
1909 section_symbol (absolute_section);
1910 #endif
1911 }
1912
1913 /* Force into index mode. Hope this works */
1914
1915 /* We do the first bit for 32-bit displacements, and the
1916 second bit for 16 bit ones. It is possible that we
1917 should make the default be WORD instead of LONG, but
1918 I think that'd break GCC, so we put up with a little
1919 inefficiency for the sake of working output. */
1920
1921 if (!issword (nextword)
1922 || (isvar (&opP->disp)
1923 && ((opP->disp.size == SIZE_UNSPEC
1924 && flag_short_refs == 0
1925 && cpu_of_arch (current_architecture) >= m68020)
1926 || opP->disp.size == SIZE_LONG)))
1927 {
1928 if (cpu_of_arch (current_architecture) < m68020)
1929 opP->error =
1930 "displacement too large for this architecture; needs 68020 or higher";
1931 if (opP->reg == PC)
1932 tmpreg = 0x3B; /* 7.3 */
1933 else
1934 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1935 if (isvar (&opP->disp))
1936 {
1937 if (opP->reg == PC)
1938 {
1939 if (opP->disp.size == SIZE_LONG
1940 #ifdef OBJ_ELF
1941 /* If the displacement needs pic
1942 relocation it cannot be relaxed. */
1943 || opP->disp.pic_reloc != pic_none
1944 #endif
1945 )
1946 {
1947 addword (0x0170);
1948 add_fix ('l', &opP->disp, 1, 2);
1949 }
1950 else
1951 {
1952 add_frag (adds (&opP->disp),
1953 offs (&opP->disp),
1954 TAB (PCLEA, SZ_UNDEF));
1955 break;
1956 }
1957 }
1958 else
1959 {
1960 addword (0x0170);
1961 add_fix ('l', &opP->disp, 0, 0);
1962 }
1963 }
1964 else
1965 addword (0x0170);
1966 addword (nextword >> 16);
1967 }
1968 else
1969 {
1970 if (opP->reg == PC)
1971 tmpreg = 0x3A; /* 7.2 */
1972 else
1973 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1974
1975 if (isvar (&opP->disp))
1976 {
1977 if (opP->reg == PC)
1978 {
1979 add_fix ('w', &opP->disp, 1, 0);
1980 }
1981 else
1982 add_fix ('w', &opP->disp, 0, 0);
1983 }
1984 }
1985 addword (nextword);
1986 break;
1987
1988 case POST:
1989 case PRE:
1990 case BASE:
1991 nextword = 0;
1992 baseo = get_num (&opP->disp, 80);
1993 if (opP->mode == POST || opP->mode == PRE)
1994 outro = get_num (&opP->odisp, 80);
1995 /* Figure out the `addressing mode'.
1996 Also turn on the BASE_DISABLE bit, if needed. */
1997 if (opP->reg == PC || opP->reg == ZPC)
1998 {
1999 tmpreg = 0x3b; /* 7.3 */
2000 if (opP->reg == ZPC)
2001 nextword |= 0x80;
2002 }
2003 else if (opP->reg == 0)
2004 {
2005 nextword |= 0x80;
2006 tmpreg = 0x30; /* 6.garbage */
2007 }
2008 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2009 {
2010 nextword |= 0x80;
2011 tmpreg = 0x30 + opP->reg - ZADDR0;
2012 }
2013 else
2014 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2015
2016 siz1 = opP->disp.size;
2017 if (opP->mode == POST || opP->mode == PRE)
2018 siz2 = opP->odisp.size;
2019 else
2020 siz2 = SIZE_UNSPEC;
2021
2022 /* Index register stuff */
2023 if (opP->index.reg != 0
2024 && opP->index.reg >= DATA
2025 && opP->index.reg <= ADDR7)
2026 {
2027 nextword |= (opP->index.reg - DATA) << 12;
2028
2029 if (opP->index.size == SIZE_LONG
2030 || (opP->index.size == SIZE_UNSPEC
2031 && m68k_index_width_default == SIZE_LONG))
2032 nextword |= 0x800;
2033
2034 if ((opP->index.scale != 1
2035 && cpu_of_arch (current_architecture) < m68020)
2036 || (opP->index.scale == 8
2037 && current_architecture == mcf5200))
2038 {
2039 opP->error =
2040 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
2041 }
2042
2043 switch (opP->index.scale)
2044 {
2045 case 1:
2046 break;
2047 case 2:
2048 nextword |= 0x200;
2049 break;
2050 case 4:
2051 nextword |= 0x400;
2052 break;
2053 case 8:
2054 nextword |= 0x600;
2055 break;
2056 default:
2057 abort ();
2058 }
2059 /* IF its simple,
2060 GET US OUT OF HERE! */
2061
2062 /* Must be INDEX, with an index register. Address
2063 register cannot be ZERO-PC, and either :b was
2064 forced, or we know it will fit. For a 68000 or
2065 68010, force this mode anyways, because the
2066 larger modes aren't supported. */
2067 if (opP->mode == BASE
2068 && ((opP->reg >= ADDR0
2069 && opP->reg <= ADDR7)
2070 || opP->reg == PC))
2071 {
2072 if (siz1 == SIZE_BYTE
2073 || cpu_of_arch (current_architecture) < m68020
2074 || (siz1 == SIZE_UNSPEC
2075 && ! isvar (&opP->disp)
2076 && issbyte (baseo)))
2077 {
2078 nextword += baseo & 0xff;
2079 addword (nextword);
2080 if (isvar (&opP->disp))
2081 {
2082 /* Do a byte relocation. If it doesn't
2083 fit (possible on m68000) let the
2084 fixup processing complain later. */
2085 if (opP->reg == PC)
2086 add_fix ('B', &opP->disp, 1, 1);
2087 else
2088 add_fix ('B', &opP->disp, 0, 0);
2089 }
2090 else if (siz1 != SIZE_BYTE)
2091 {
2092 if (siz1 != SIZE_UNSPEC)
2093 as_warn ("Forcing byte displacement");
2094 if (! issbyte (baseo))
2095 opP->error = "byte displacement out of range";
2096 }
2097
2098 break;
2099 }
2100 else if (siz1 == SIZE_UNSPEC
2101 && opP->reg == PC
2102 && isvar (&opP->disp)
2103 && subs (&opP->disp) == NULL
2104 #ifdef OBJ_ELF
2105 /* If the displacement needs pic
2106 relocation it cannot be relaxed. */
2107 && opP->disp.pic_reloc == pic_none
2108 #endif
2109 )
2110 {
2111 /* The code in md_convert_frag_1 needs to be
2112 able to adjust nextword. Call frag_grow
2113 to ensure that we have enough space in
2114 the frag obstack to make all the bytes
2115 contiguous. */
2116 frag_grow (14);
2117 nextword += baseo & 0xff;
2118 addword (nextword);
2119 add_frag (adds (&opP->disp), offs (&opP->disp),
2120 TAB (PCINDEX, SZ_UNDEF));
2121
2122 break;
2123 }
2124 }
2125 }
2126 else
2127 {
2128 nextword |= 0x40; /* No index reg */
2129 if (opP->index.reg >= ZDATA0
2130 && opP->index.reg <= ZDATA7)
2131 nextword |= (opP->index.reg - ZDATA0) << 12;
2132 else if (opP->index.reg >= ZADDR0
2133 || opP->index.reg <= ZADDR7)
2134 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2135 }
2136
2137 /* It isn't simple. */
2138
2139 if (cpu_of_arch (current_architecture) < m68020)
2140 opP->error =
2141 "invalid operand mode for this architecture; needs 68020 or higher";
2142
2143 nextword |= 0x100;
2144 /* If the guy specified a width, we assume that it is
2145 wide enough. Maybe it isn't. If so, we lose. */
2146 switch (siz1)
2147 {
2148 case SIZE_UNSPEC:
2149 if (isvar (&opP->disp)
2150 ? m68k_rel32
2151 : ! issword (baseo))
2152 {
2153 siz1 = SIZE_LONG;
2154 nextword |= 0x30;
2155 }
2156 else if (! isvar (&opP->disp) && baseo == 0)
2157 nextword |= 0x10;
2158 else
2159 {
2160 nextword |= 0x20;
2161 siz1 = SIZE_WORD;
2162 }
2163 break;
2164 case SIZE_BYTE:
2165 as_warn (":b not permitted; defaulting to :w");
2166 /* Fall through. */
2167 case SIZE_WORD:
2168 nextword |= 0x20;
2169 break;
2170 case SIZE_LONG:
2171 nextword |= 0x30;
2172 break;
2173 }
2174
2175 /* Figure out innner displacement stuff */
2176 if (opP->mode == POST || opP->mode == PRE)
2177 {
2178 if (cpu_of_arch (current_architecture) & cpu32)
2179 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
2180 switch (siz2)
2181 {
2182 case SIZE_UNSPEC:
2183 if (isvar (&opP->odisp)
2184 ? m68k_rel32
2185 : ! issword (outro))
2186 {
2187 siz2 = SIZE_LONG;
2188 nextword |= 0x3;
2189 }
2190 else if (! isvar (&opP->odisp) && outro == 0)
2191 nextword |= 0x1;
2192 else
2193 {
2194 nextword |= 0x2;
2195 siz2 = SIZE_WORD;
2196 }
2197 break;
2198 case 1:
2199 as_warn (":b not permitted; defaulting to :w");
2200 /* Fall through. */
2201 case 2:
2202 nextword |= 0x2;
2203 break;
2204 case 3:
2205 nextword |= 0x3;
2206 break;
2207 }
2208 if (opP->mode == POST
2209 && (nextword & 0x40) == 0)
2210 nextword |= 0x04;
2211 }
2212 addword (nextword);
2213
2214 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2215 {
2216 if (opP->reg == PC || opP->reg == ZPC)
2217 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2218 else
2219 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2220 }
2221 if (siz1 == SIZE_LONG)
2222 addword (baseo >> 16);
2223 if (siz1 != SIZE_UNSPEC)
2224 addword (baseo);
2225
2226 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2227 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2228 if (siz2 == SIZE_LONG)
2229 addword (outro >> 16);
2230 if (siz2 != SIZE_UNSPEC)
2231 addword (outro);
2232
2233 break;
2234
2235 case ABSL:
2236 nextword = get_num (&opP->disp, 80);
2237 switch (opP->disp.size)
2238 {
2239 default:
2240 abort ();
2241 case SIZE_UNSPEC:
2242 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2243 {
2244 tmpreg = 0x38; /* 7.0 */
2245 addword (nextword);
2246 break;
2247 }
2248 /* Don't generate pc relative code on 68010 and
2249 68000. */
2250 if (isvar (&opP->disp)
2251 && !subs (&opP->disp)
2252 && adds (&opP->disp)
2253 #ifdef OBJ_ELF
2254 /* If the displacement needs pic relocation it
2255 cannot be relaxed. */
2256 && opP->disp.pic_reloc == pic_none
2257 #endif
2258 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2259 && HAVE_LONG_BRANCH(current_architecture)
2260 && !flag_long_jumps
2261 && !strchr ("~%&$?", s[0]))
2262 {
2263 tmpreg = 0x3A; /* 7.2 */
2264 add_frag (adds (&opP->disp),
2265 offs (&opP->disp),
2266 TAB (PCREL, SZ_UNDEF));
2267 break;
2268 }
2269 /* Fall through into long */
2270 case SIZE_LONG:
2271 if (isvar (&opP->disp))
2272 add_fix ('l', &opP->disp, 0, 0);
2273
2274 tmpreg = 0x39;/* 7.1 mode */
2275 addword (nextword >> 16);
2276 addword (nextword);
2277 break;
2278
2279 case SIZE_WORD: /* Word */
2280 if (isvar (&opP->disp))
2281 add_fix ('w', &opP->disp, 0, 0);
2282
2283 tmpreg = 0x38;/* 7.0 mode */
2284 addword (nextword);
2285 break;
2286 }
2287 break;
2288 case CONTROL:
2289 case FPREG:
2290 default:
2291 as_bad ("unknown/incorrect operand");
2292 /* abort(); */
2293 }
2294 install_gen_operand (s[1], tmpreg);
2295 break;
2296
2297 case '#':
2298 case '^':
2299 switch (s[1])
2300 { /* JF: I hate floating point! */
2301 case 'j':
2302 tmpreg = 70;
2303 break;
2304 case '8':
2305 tmpreg = 20;
2306 break;
2307 case 'C':
2308 tmpreg = 50;
2309 break;
2310 case '3':
2311 default:
2312 tmpreg = 80;
2313 break;
2314 }
2315 tmpreg = get_num (&opP->disp, tmpreg);
2316 if (isvar (&opP->disp))
2317 add_fix (s[1], &opP->disp, 0, 0);
2318 switch (s[1])
2319 {
2320 case 'b': /* Danger: These do no check for
2321 certain types of overflow.
2322 user beware! */
2323 if (!isbyte (tmpreg))
2324 opP->error = "out of range";
2325 insop (tmpreg, opcode);
2326 if (isvar (&opP->disp))
2327 the_ins.reloc[the_ins.nrel - 1].n =
2328 (opcode->m_codenum) * 2 + 1;
2329 break;
2330 case 'B':
2331 if (!issbyte (tmpreg))
2332 opP->error = "out of range";
2333 opcode->m_opcode |= tmpreg;
2334 if (isvar (&opP->disp))
2335 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2336 break;
2337 case 'w':
2338 if (!isword (tmpreg))
2339 opP->error = "out of range";
2340 insop (tmpreg, opcode);
2341 if (isvar (&opP->disp))
2342 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2343 break;
2344 case 'W':
2345 if (!issword (tmpreg))
2346 opP->error = "out of range";
2347 insop (tmpreg, opcode);
2348 if (isvar (&opP->disp))
2349 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2350 break;
2351 case 'l':
2352 /* Because of the way insop works, we put these two out
2353 backwards. */
2354 insop (tmpreg, opcode);
2355 insop (tmpreg >> 16, opcode);
2356 if (isvar (&opP->disp))
2357 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2358 break;
2359 case '3':
2360 tmpreg &= 0xFF;
2361 case '8':
2362 case 'C':
2363 install_operand (s[1], tmpreg);
2364 break;
2365 default:
2366 abort ();
2367 }
2368 break;
2369
2370 case '+':
2371 case '-':
2372 case 'A':
2373 case 'a':
2374 install_operand (s[1], opP->reg - ADDR);
2375 break;
2376
2377 case 'B':
2378 tmpreg = get_num (&opP->disp, 80);
2379 switch (s[1])
2380 {
2381 case 'B':
2382 /* The pc_fix argument winds up in fx_pcrel_adjust,
2383 which is a char, and may therefore be unsigned. We
2384 want to pass -1, but we pass 64 instead, and convert
2385 back in md_pcrel_from. */
2386 add_fix ('B', &opP->disp, 1, 64);
2387 break;
2388 case 'W':
2389 add_fix ('w', &opP->disp, 1, 0);
2390 addword (0);
2391 break;
2392 case 'L':
2393 long_branch:
2394 if (!HAVE_LONG_BRANCH(current_architecture))
2395 as_warn ("Can't use long branches on 68000/68010/5200");
2396 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2397 add_fix ('l', &opP->disp, 1, 0);
2398 addword (0);
2399 addword (0);
2400 break;
2401 case 'g':
2402 if (subs (&opP->disp)) /* We can't relax it */
2403 goto long_branch;
2404
2405 #ifdef OBJ_ELF
2406 /* If the displacement needs pic relocation it cannot be
2407 relaxed. */
2408 if (opP->disp.pic_reloc != pic_none)
2409 goto long_branch;
2410 #endif
2411
2412 /* This could either be a symbol, or an absolute
2413 address. No matter, the frag hacking will finger it
2414 out. Not quite: it can't switch from BRANCH to
2415 BCC68000 for the case where opnd is absolute (it
2416 needs to use the 68000 hack since no conditional abs
2417 jumps). */
2418 if (( !HAVE_LONG_BRANCH(current_architecture)
2419 || (0 == adds (&opP->disp)))
2420 && (the_ins.opcode[0] >= 0x6200)
2421 && (the_ins.opcode[0] <= 0x6f00))
2422 add_frag (adds (&opP->disp), offs (&opP->disp),
2423 TAB (BCC68000, SZ_UNDEF));
2424 else
2425 add_frag (adds (&opP->disp), offs (&opP->disp),
2426 TAB (ABRANCH, SZ_UNDEF));
2427 break;
2428 case 'w':
2429 if (isvar (&opP->disp))
2430 {
2431 #if 1
2432 /* check for DBcc instruction */
2433 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2434 {
2435 /* size varies if patch */
2436 /* needed for long form */
2437 add_frag (adds (&opP->disp), offs (&opP->disp),
2438 TAB (DBCC, SZ_UNDEF));
2439 break;
2440 }
2441 #endif
2442 add_fix ('w', &opP->disp, 1, 0);
2443 }
2444 addword (0);
2445 break;
2446 case 'C': /* Fixed size LONG coproc branches */
2447 add_fix ('l', &opP->disp, 1, 0);
2448 addword (0);
2449 addword (0);
2450 break;
2451 case 'c': /* Var size Coprocesssor branches */
2452 if (subs (&opP->disp))
2453 {
2454 add_fix ('l', &opP->disp, 1, 0);
2455 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2456 }
2457 else if (adds (&opP->disp))
2458 add_frag (adds (&opP->disp), offs (&opP->disp),
2459 TAB (FBRANCH, SZ_UNDEF));
2460 else
2461 {
2462 /* add_frag((symbolS *) 0, offs(&opP->disp),
2463 TAB(FBRANCH,SHORT)); */
2464 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2465 add_fix ('l', &opP->disp, 1, 0);
2466 addword (0);
2467 addword (0);
2468 }
2469 break;
2470 default:
2471 abort ();
2472 }
2473 break;
2474
2475 case 'C': /* Ignore it */
2476 break;
2477
2478 case 'd': /* JF this is a kludge */
2479 install_operand ('s', opP->reg - ADDR);
2480 tmpreg = get_num (&opP->disp, 80);
2481 if (!issword (tmpreg))
2482 {
2483 as_warn ("Expression out of range, using 0");
2484 tmpreg = 0;
2485 }
2486 addword (tmpreg);
2487 break;
2488
2489 case 'D':
2490 install_operand (s[1], opP->reg - DATA);
2491 break;
2492
2493 case 'F':
2494 install_operand (s[1], opP->reg - FP0);
2495 break;
2496
2497 case 'I':
2498 tmpreg = opP->reg - COP0;
2499 install_operand (s[1], tmpreg);
2500 break;
2501
2502 case 'J': /* JF foo */
2503 switch (opP->reg)
2504 {
2505 case SFC:
2506 tmpreg = 0x000;
2507 break;
2508 case DFC:
2509 tmpreg = 0x001;
2510 break;
2511 case CACR:
2512 tmpreg = 0x002;
2513 break;
2514 case TC:
2515 tmpreg = 0x003;
2516 break;
2517 case ITT0:
2518 tmpreg = 0x004;
2519 break;
2520 case ITT1:
2521 tmpreg = 0x005;
2522 break;
2523 case DTT0:
2524 tmpreg = 0x006;
2525 break;
2526 case DTT1:
2527 tmpreg = 0x007;
2528 break;
2529 case BUSCR:
2530 tmpreg = 0x008;
2531 break;
2532
2533 case USP:
2534 tmpreg = 0x800;
2535 break;
2536 case VBR:
2537 tmpreg = 0x801;
2538 break;
2539 case CAAR:
2540 tmpreg = 0x802;
2541 break;
2542 case MSP:
2543 tmpreg = 0x803;
2544 break;
2545 case ISP:
2546 tmpreg = 0x804;
2547 break;
2548 case MMUSR:
2549 tmpreg = 0x805;
2550 break;
2551 case URP:
2552 tmpreg = 0x806;
2553 break;
2554 case SRP:
2555 tmpreg = 0x807;
2556 break;
2557 case PCR:
2558 tmpreg = 0x808;
2559 break;
2560 case ROMBAR:
2561 tmpreg = 0xC00;
2562 break;
2563 case RAMBAR0:
2564 tmpreg = 0xC04;
2565 break;
2566 case RAMBAR1:
2567 tmpreg = 0xC05;
2568 break;
2569 case MBAR:
2570 tmpreg = 0xC0F;
2571 break;
2572 default:
2573 abort ();
2574 }
2575 install_operand (s[1], tmpreg);
2576 break;
2577
2578 case 'k':
2579 tmpreg = get_num (&opP->disp, 55);
2580 install_operand (s[1], tmpreg & 0x7f);
2581 break;
2582
2583 case 'l':
2584 tmpreg = opP->mask;
2585 if (s[1] == 'w')
2586 {
2587 if (tmpreg & 0x7FF0000)
2588 as_bad ("Floating point register in register list");
2589 insop (reverse_16_bits (tmpreg), opcode);
2590 }
2591 else
2592 {
2593 if (tmpreg & 0x700FFFF)
2594 as_bad ("Wrong register in floating-point reglist");
2595 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2596 }
2597 break;
2598
2599 case 'L':
2600 tmpreg = opP->mask;
2601 if (s[1] == 'w')
2602 {
2603 if (tmpreg & 0x7FF0000)
2604 as_bad ("Floating point register in register list");
2605 insop (tmpreg, opcode);
2606 }
2607 else if (s[1] == '8')
2608 {
2609 if (tmpreg & 0x0FFFFFF)
2610 as_bad ("incorrect register in reglist");
2611 install_operand (s[1], tmpreg >> 24);
2612 }
2613 else
2614 {
2615 if (tmpreg & 0x700FFFF)
2616 as_bad ("wrong register in floating-point reglist");
2617 else
2618 install_operand (s[1], tmpreg >> 16);
2619 }
2620 break;
2621
2622 case 'M':
2623 install_operand (s[1], get_num (&opP->disp, 60));
2624 break;
2625
2626 case 'O':
2627 tmpreg = ((opP->mode == DREG)
2628 ? 0x20 + opP->reg - DATA
2629 : (get_num (&opP->disp, 40) & 0x1F));
2630 install_operand (s[1], tmpreg);
2631 break;
2632
2633 case 'Q':
2634 tmpreg = get_num (&opP->disp, 10);
2635 if (tmpreg == 8)
2636 tmpreg = 0;
2637 install_operand (s[1], tmpreg);
2638 break;
2639
2640 case 'R':
2641 /* This depends on the fact that ADDR registers are eight
2642 more than their corresponding DATA regs, so the result
2643 will have the ADDR_REG bit set */
2644 install_operand (s[1], opP->reg - DATA);
2645 break;
2646
2647 case 'r':
2648 if (opP->mode == AINDR)
2649 install_operand (s[1], opP->reg - DATA);
2650 else
2651 install_operand (s[1], opP->index.reg - DATA);
2652 break;
2653
2654 case 's':
2655 if (opP->reg == FPI)
2656 tmpreg = 0x1;
2657 else if (opP->reg == FPS)
2658 tmpreg = 0x2;
2659 else if (opP->reg == FPC)
2660 tmpreg = 0x4;
2661 else
2662 abort ();
2663 install_operand (s[1], tmpreg);
2664 break;
2665
2666 case 'S': /* Ignore it */
2667 break;
2668
2669 case 'T':
2670 install_operand (s[1], get_num (&opP->disp, 30));
2671 break;
2672
2673 case 'U': /* Ignore it */
2674 break;
2675
2676 case 'c':
2677 switch (opP->reg)
2678 {
2679 case NC:
2680 tmpreg = 0;
2681 break;
2682 case DC:
2683 tmpreg = 1;
2684 break;
2685 case IC:
2686 tmpreg = 2;
2687 break;
2688 case BC:
2689 tmpreg = 3;
2690 break;
2691 default:
2692 as_fatal ("failed sanity check");
2693 } /* switch on cache token */
2694 install_operand (s[1], tmpreg);
2695 break;
2696 #ifndef NO_68851
2697 /* JF: These are out of order, I fear. */
2698 case 'f':
2699 switch (opP->reg)
2700 {
2701 case SFC:
2702 tmpreg = 0;
2703 break;
2704 case DFC:
2705 tmpreg = 1;
2706 break;
2707 default:
2708 abort ();
2709 }
2710 install_operand (s[1], tmpreg);
2711 break;
2712
2713 case '0':
2714 case '1':
2715 case '2':
2716 switch (opP->reg)
2717 {
2718 case TC:
2719 tmpreg = 0;
2720 break;
2721 case CAL:
2722 tmpreg = 4;
2723 break;
2724 case VAL:
2725 tmpreg = 5;
2726 break;
2727 case SCC:
2728 tmpreg = 6;
2729 break;
2730 case AC:
2731 tmpreg = 7;
2732 break;
2733 default:
2734 abort ();
2735 }
2736 install_operand (s[1], tmpreg);
2737 break;
2738
2739 case 'V':
2740 if (opP->reg == VAL)
2741 break;
2742 abort ();
2743
2744 case 'W':
2745 switch (opP->reg)
2746 {
2747 case DRP:
2748 tmpreg = 1;
2749 break;
2750 case SRP:
2751 tmpreg = 2;
2752 break;
2753 case CRP:
2754 tmpreg = 3;
2755 break;
2756 default:
2757 abort ();
2758 }
2759 install_operand (s[1], tmpreg);
2760 break;
2761
2762 case 'X':
2763 switch (opP->reg)
2764 {
2765 case BAD:
2766 case BAD + 1:
2767 case BAD + 2:
2768 case BAD + 3:
2769 case BAD + 4:
2770 case BAD + 5:
2771 case BAD + 6:
2772 case BAD + 7:
2773 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2774 break;
2775
2776 case BAC:
2777 case BAC + 1:
2778 case BAC + 2:
2779 case BAC + 3:
2780 case BAC + 4:
2781 case BAC + 5:
2782 case BAC + 6:
2783 case BAC + 7:
2784 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2785 break;
2786
2787 default:
2788 abort ();
2789 }
2790 install_operand (s[1], tmpreg);
2791 break;
2792 case 'Y':
2793 know (opP->reg == PSR);
2794 break;
2795 case 'Z':
2796 know (opP->reg == PCSR);
2797 break;
2798 #endif /* m68851 */
2799 case '3':
2800 switch (opP->reg)
2801 {
2802 case TT0:
2803 tmpreg = 2;
2804 break;
2805 case TT1:
2806 tmpreg = 3;
2807 break;
2808 default:
2809 abort ();
2810 }
2811 install_operand (s[1], tmpreg);
2812 break;
2813 case 't':
2814 tmpreg = get_num (&opP->disp, 20);
2815 install_operand (s[1], tmpreg);
2816 break;
2817 case '_': /* used only for move16 absolute 32-bit address */
2818 tmpreg = get_num (&opP->disp, 80);
2819 addword (tmpreg >> 16);
2820 addword (tmpreg & 0xFFFF);
2821 break;
2822 default:
2823 abort ();
2824 }
2825 }
2826
2827 /* By the time whe get here (FINALLY) the_ins contains the complete
2828 instruction, ready to be emitted. . . */
2829 }
2830
2831 static int
2832 reverse_16_bits (in)
2833 int in;
2834 {
2835 int out = 0;
2836 int n;
2837
2838 static int mask[16] =
2839 {
2840 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2841 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2842 };
2843 for (n = 0; n < 16; n++)
2844 {
2845 if (in & mask[n])
2846 out |= mask[15 - n];
2847 }
2848 return out;
2849 } /* reverse_16_bits() */
2850
2851 static int
2852 reverse_8_bits (in)
2853 int in;
2854 {
2855 int out = 0;
2856 int n;
2857
2858 static int mask[8] =
2859 {
2860 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2861 };
2862
2863 for (n = 0; n < 8; n++)
2864 {
2865 if (in & mask[n])
2866 out |= mask[7 - n];
2867 }
2868 return out;
2869 } /* reverse_8_bits() */
2870
2871 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2872 (that value is chosen in the frag_var call in md_assemble). TYPE
2873 is the subtype of the frag to be generated; its primary type is
2874 rs_machine_dependent.
2875
2876 The TYPE parameter is also used by md_convert_frag_1 and
2877 md_estimate_size_before_relax. The appropriate type of fixup will
2878 be emitted by md_convert_frag_1.
2879
2880 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2881 static void
2882 install_operand (mode, val)
2883 int mode;
2884 int val;
2885 {
2886 switch (mode)
2887 {
2888 case 's':
2889 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2890 break;
2891 case 'd':
2892 the_ins.opcode[0] |= val << 9;
2893 break;
2894 case '1':
2895 the_ins.opcode[1] |= val << 12;
2896 break;
2897 case '2':
2898 the_ins.opcode[1] |= val << 6;
2899 break;
2900 case '3':
2901 the_ins.opcode[1] |= val;
2902 break;
2903 case '4':
2904 the_ins.opcode[2] |= val << 12;
2905 break;
2906 case '5':
2907 the_ins.opcode[2] |= val << 6;
2908 break;
2909 case '6':
2910 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2911 three words long! */
2912 the_ins.numo++;
2913 the_ins.opcode[2] |= val;
2914 break;
2915 case '7':
2916 the_ins.opcode[1] |= val << 7;
2917 break;
2918 case '8':
2919 the_ins.opcode[1] |= val << 10;
2920 break;
2921 #ifndef NO_68851
2922 case '9':
2923 the_ins.opcode[1] |= val << 5;
2924 break;
2925 #endif
2926
2927 case 't':
2928 the_ins.opcode[1] |= (val << 10) | (val << 7);
2929 break;
2930 case 'D':
2931 the_ins.opcode[1] |= (val << 12) | val;
2932 break;
2933 case 'g':
2934 the_ins.opcode[0] |= val = 0xff;
2935 break;
2936 case 'i':
2937 the_ins.opcode[0] |= val << 9;
2938 break;
2939 case 'C':
2940 the_ins.opcode[1] |= val;
2941 break;
2942 case 'j':
2943 the_ins.opcode[1] |= val;
2944 the_ins.numo++; /* What a hack */
2945 break;
2946 case 'k':
2947 the_ins.opcode[1] |= val << 4;
2948 break;
2949 case 'b':
2950 case 'w':
2951 case 'W':
2952 case 'l':
2953 break;
2954 case 'e':
2955 the_ins.opcode[0] |= (val << 6);
2956 break;
2957 case 'L':
2958 the_ins.opcode[1] = (val >> 16);
2959 the_ins.opcode[2] = val & 0xffff;
2960 break;
2961 case 'c':
2962 default:
2963 as_fatal ("failed sanity check.");
2964 }
2965 } /* install_operand() */
2966
2967 static void
2968 install_gen_operand (mode, val)
2969 int mode;
2970 int val;
2971 {
2972 switch (mode)
2973 {
2974 case 's':
2975 the_ins.opcode[0] |= val;
2976 break;
2977 case 'd':
2978 /* This is a kludge!!! */
2979 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2980 break;
2981 case 'b':
2982 case 'w':
2983 case 'l':
2984 case 'f':
2985 case 'F':
2986 case 'x':
2987 case 'p':
2988 the_ins.opcode[0] |= val;
2989 break;
2990 /* more stuff goes here */
2991 default:
2992 as_fatal ("failed sanity check.");
2993 }
2994 } /* install_gen_operand() */
2995
2996 /*
2997 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2998 * then deal with the bitfield hack.
2999 */
3000
3001 static char *
3002 crack_operand (str, opP)
3003 register char *str;
3004 register struct m68k_op *opP;
3005 {
3006 register int parens;
3007 register int c;
3008 register char *beg_str;
3009 int inquote = 0;
3010
3011 if (!str)
3012 {
3013 return str;
3014 }
3015 beg_str = str;
3016 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3017 {
3018 if (! inquote)
3019 {
3020 if (*str == '(')
3021 parens++;
3022 else if (*str == ')')
3023 {
3024 if (!parens)
3025 { /* ERROR */
3026 opP->error = "Extra )";
3027 return str;
3028 }
3029 --parens;
3030 }
3031 }
3032 if (flag_mri && *str == '\'')
3033 inquote = ! inquote;
3034 }
3035 if (!*str && parens)
3036 { /* ERROR */
3037 opP->error = "Missing )";
3038 return str;
3039 }
3040 c = *str;
3041 *str = '\0';
3042 if (m68k_ip_op (beg_str, opP) != 0)
3043 {
3044 *str = c;
3045 return str;
3046 }
3047 *str = c;
3048 if (c == '}')
3049 c = *++str; /* JF bitfield hack */
3050 if (c)
3051 {
3052 c = *++str;
3053 if (!c)
3054 as_bad ("Missing operand");
3055 }
3056 return str;
3057 }
3058
3059 /* This is the guts of the machine-dependent assembler. STR points to a
3060 machine dependent instruction. This function is supposed to emit
3061 the frags/bytes it assembles to.
3062 */
3063
3064 void
3065 insert_reg (regname, regnum)
3066 char *regname;
3067 int regnum;
3068 {
3069 char buf[100];
3070 int i;
3071
3072 #ifdef REGISTER_PREFIX
3073 if (!flag_reg_prefix_optional)
3074 {
3075 buf[0] = REGISTER_PREFIX;
3076 strcpy (buf + 1, regname);
3077 regname = buf;
3078 }
3079 #endif
3080
3081 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3082 &zero_address_frag));
3083
3084 for (i = 0; regname[i]; i++)
3085 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3086 buf[i] = '\0';
3087
3088 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3089 &zero_address_frag));
3090 }
3091
3092 struct init_entry
3093 {
3094 const char *name;
3095 int number;
3096 };
3097
3098 static const struct init_entry init_table[] =
3099 {
3100 { "d0", DATA0 },
3101 { "d1", DATA1 },
3102 { "d2", DATA2 },
3103 { "d3", DATA3 },
3104 { "d4", DATA4 },
3105 { "d5", DATA5 },
3106 { "d6", DATA6 },
3107 { "d7", DATA7 },
3108 { "a0", ADDR0 },
3109 { "a1", ADDR1 },
3110 { "a2", ADDR2 },
3111 { "a3", ADDR3 },
3112 { "a4", ADDR4 },
3113 { "a5", ADDR5 },
3114 { "a6", ADDR6 },
3115 { "fp", ADDR6 },
3116 { "a7", ADDR7 },
3117 { "sp", ADDR7 },
3118 { "ssp", ADDR7 },
3119 { "fp0", FP0 },
3120 { "fp1", FP1 },
3121 { "fp2", FP2 },
3122 { "fp3", FP3 },
3123 { "fp4", FP4 },
3124 { "fp5", FP5 },
3125 { "fp6", FP6 },
3126 { "fp7", FP7 },
3127 { "fpi", FPI },
3128 { "fpiar", FPI },
3129 { "fpc", FPI },
3130 { "fps", FPS },
3131 { "fpsr", FPS },
3132 { "fpc", FPC },
3133 { "fpcr", FPC },
3134 { "control", FPC },
3135 { "status", FPS },
3136 { "iaddr", FPI },
3137
3138 { "cop0", COP0 },
3139 { "cop1", COP1 },
3140 { "cop2", COP2 },
3141 { "cop3", COP3 },
3142 { "cop4", COP4 },
3143 { "cop5", COP5 },
3144 { "cop6", COP6 },
3145 { "cop7", COP7 },
3146 { "pc", PC },
3147 { "zpc", ZPC },
3148 { "sr", SR },
3149
3150 { "ccr", CCR },
3151 { "cc", CCR },
3152
3153 /* control registers */
3154 { "sfc", SFC }, /* Source Function Code */
3155 { "sfcr", SFC },
3156 { "dfc", DFC }, /* Destination Function Code */
3157 { "dfcr", DFC },
3158 { "cacr", CACR }, /* Cache Control Register */
3159 { "caar", CAAR }, /* Cache Address Register */
3160
3161 { "usp", USP }, /* User Stack Pointer */
3162 { "vbr", VBR }, /* Vector Base Register */
3163 { "msp", MSP }, /* Master Stack Pointer */
3164 { "isp", ISP }, /* Interrupt Stack Pointer */
3165
3166 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3167 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3168 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3169 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3170
3171 /* 68ec040 versions of same */
3172 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3173 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3174 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3175 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3176
3177 /* mcf5200 versions of same. The ColdFire programmer's reference
3178 manual indicated that the order is 2,3,0,1, but Ken Rose
3179 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3180 { "acr0", ITT0 }, /* Access Control Unit 0 */
3181 { "acr1", ITT1 }, /* Access Control Unit 1 */
3182 { "acr2", DTT0 }, /* Access Control Unit 2 */
3183 { "acr3", DTT1 }, /* Access Control Unit 3 */
3184
3185 { "tc", TC }, /* MMU Translation Control Register */
3186 { "tcr", TC },
3187
3188 { "mmusr", MMUSR }, /* MMU Status Register */
3189 { "srp", SRP }, /* User Root Pointer */
3190 { "urp", URP }, /* Supervisor Root Pointer */
3191
3192 { "buscr", BUSCR },
3193 { "pcr", PCR },
3194
3195 { "rombar", ROMBAR }, /* ROM Base Address Register */
3196 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3197 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3198 { "mbar", MBAR }, /* Module Base Address Register */
3199 /* end of control registers */
3200
3201 { "ac", AC },
3202 { "bc", BC },
3203 { "cal", CAL },
3204 { "crp", CRP },
3205 { "drp", DRP },
3206 { "pcsr", PCSR },
3207 { "psr", PSR },
3208 { "scc", SCC },
3209 { "val", VAL },
3210 { "bad0", BAD0 },
3211 { "bad1", BAD1 },
3212 { "bad2", BAD2 },
3213 { "bad3", BAD3 },
3214 { "bad4", BAD4 },
3215 { "bad5", BAD5 },
3216 { "bad6", BAD6 },
3217 { "bad7", BAD7 },
3218 { "bac0", BAC0 },
3219 { "bac1", BAC1 },
3220 { "bac2", BAC2 },
3221 { "bac3", BAC3 },
3222 { "bac4", BAC4 },
3223 { "bac5", BAC5 },
3224 { "bac6", BAC6 },
3225 { "bac7", BAC7 },
3226
3227 { "ic", IC },
3228 { "dc", DC },
3229 { "nc", NC },
3230
3231 { "tt0", TT0 },
3232 { "tt1", TT1 },
3233 /* 68ec030 versions of same */
3234 { "ac0", TT0 },
3235 { "ac1", TT1 },
3236 /* 68ec030 access control unit, identical to 030 MMU status reg */
3237 { "acusr", PSR },
3238
3239 /* Suppressed data and address registers. */
3240 { "zd0", ZDATA0 },
3241 { "zd1", ZDATA1 },
3242 { "zd2", ZDATA2 },
3243 { "zd3", ZDATA3 },
3244 { "zd4", ZDATA4 },
3245 { "zd5", ZDATA5 },
3246 { "zd6", ZDATA6 },
3247 { "zd7", ZDATA7 },
3248 { "za0", ZADDR0 },
3249 { "za1", ZADDR1 },
3250 { "za2", ZADDR2 },
3251 { "za3", ZADDR3 },
3252 { "za4", ZADDR4 },
3253 { "za5", ZADDR5 },
3254 { "za6", ZADDR6 },
3255 { "za7", ZADDR7 },
3256
3257 { 0, 0 }
3258 };
3259
3260 void
3261 init_regtable ()
3262 {
3263 int i;
3264 for (i = 0; init_table[i].name; i++)
3265 insert_reg (init_table[i].name, init_table[i].number);
3266 }
3267
3268 static int no_68851, no_68881;
3269
3270 #ifdef OBJ_AOUT
3271 /* a.out machine type. Default to 68020. */
3272 int m68k_aout_machtype = 2;
3273 #endif
3274
3275 void
3276 md_assemble (str)
3277 char *str;
3278 {
3279 const char *er;
3280 short *fromP;
3281 char *toP = NULL;
3282 int m, n = 0;
3283 char *to_beg_P;
3284 int shorts_this_frag;
3285 fixS *fixP;
3286
3287 /* In MRI mode, the instruction and operands are separated by a
3288 space. Anything following the operands is a comment. The label
3289 has already been removed. */
3290 if (flag_mri)
3291 {
3292 char *s;
3293 int fields = 0;
3294 int infield = 0;
3295 int inquote = 0;
3296
3297 for (s = str; *s != '\0'; s++)
3298 {
3299 if ((*s == ' ' || *s == '\t') && ! inquote)
3300 {
3301 if (infield)
3302 {
3303 ++fields;
3304 if (fields >= 2)
3305 {
3306 *s = '\0';
3307 break;
3308 }
3309 infield = 0;
3310 }
3311 }
3312 else
3313 {
3314 if (! infield)
3315 infield = 1;
3316 if (*s == '\'')
3317 inquote = ! inquote;
3318 }
3319 }
3320 }
3321
3322 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3323 m68k_ip (str);
3324 er = the_ins.error;
3325 if (!er)
3326 {
3327 for (n = 0; n < the_ins.numargs; n++)
3328 if (the_ins.operands[n].error)
3329 {
3330 er = the_ins.operands[n].error;
3331 break;
3332 }
3333 }
3334 if (er)
3335 {
3336 as_bad ("%s -- statement `%s' ignored", er, str);
3337 return;
3338 }
3339
3340 /* If there is a current label, record that it marks an instruction. */
3341 if (current_label != NULL)
3342 {
3343 current_label->text = 1;
3344 current_label = NULL;
3345 }
3346
3347 if (the_ins.nfrag == 0)
3348 {
3349 /* No frag hacking involved; just put it out */
3350 toP = frag_more (2 * the_ins.numo);
3351 fromP = &the_ins.opcode[0];
3352 for (m = the_ins.numo; m; --m)
3353 {
3354 md_number_to_chars (toP, (long) (*fromP), 2);
3355 toP += 2;
3356 fromP++;
3357 }
3358 /* put out symbol-dependent info */
3359 for (m = 0; m < the_ins.nrel; m++)
3360 {
3361 switch (the_ins.reloc[m].wid)
3362 {
3363 case 'B':
3364 n = 1;
3365 break;
3366 case 'b':
3367 n = 1;
3368 break;
3369 case '3':
3370 n = 1;
3371 break;
3372 case 'w':
3373 n = 2;
3374 break;
3375 case 'l':
3376 n = 4;
3377 break;
3378 default:
3379 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3380 the_ins.reloc[m].wid);
3381 }
3382
3383 fixP = fix_new_exp (frag_now,
3384 ((toP - frag_now->fr_literal)
3385 - the_ins.numo * 2 + the_ins.reloc[m].n),
3386 n,
3387 &the_ins.reloc[m].exp,
3388 the_ins.reloc[m].pcrel,
3389 get_reloc_code (n, the_ins.reloc[m].pcrel,
3390 the_ins.reloc[m].pic_reloc));
3391 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3392 if (the_ins.reloc[m].wid == 'B')
3393 fixP->fx_signed = 1;
3394 }
3395 return;
3396 }
3397
3398 /* There's some frag hacking */
3399 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3400 {
3401 int wid;
3402
3403 if (n == 0)
3404 wid = 2 * the_ins.fragb[n].fragoff;
3405 else
3406 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3407 toP = frag_more (wid);
3408 to_beg_P = toP;
3409 shorts_this_frag = 0;
3410 for (m = wid / 2; m; --m)
3411 {
3412 md_number_to_chars (toP, (long) (*fromP), 2);
3413 toP += 2;
3414 fromP++;
3415 shorts_this_frag++;
3416 }
3417 for (m = 0; m < the_ins.nrel; m++)
3418 {
3419 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3420 {
3421 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3422 break;
3423 }
3424 wid = the_ins.reloc[m].wid;
3425 if (wid == 0)
3426 continue;
3427 the_ins.reloc[m].wid = 0;
3428 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3429
3430 fixP = fix_new_exp (frag_now,
3431 ((toP - frag_now->fr_literal)
3432 - the_ins.numo * 2 + the_ins.reloc[m].n),
3433 wid,
3434 &the_ins.reloc[m].exp,
3435 the_ins.reloc[m].pcrel,
3436 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3437 the_ins.reloc[m].pic_reloc));
3438 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3439 }
3440 (void) frag_var (rs_machine_dependent, 10, 0,
3441 (relax_substateT) (the_ins.fragb[n].fragty),
3442 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3443 }
3444 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3445 shorts_this_frag = 0;
3446 if (n)
3447 {
3448 toP = frag_more (n * sizeof (short));
3449 while (n--)
3450 {
3451 md_number_to_chars (toP, (long) (*fromP), 2);
3452 toP += 2;
3453 fromP++;
3454 shorts_this_frag++;
3455 }
3456 }
3457 for (m = 0; m < the_ins.nrel; m++)
3458 {
3459 int wid;
3460
3461 wid = the_ins.reloc[m].wid;
3462 if (wid == 0)
3463 continue;
3464 the_ins.reloc[m].wid = 0;
3465 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3466
3467 fixP = fix_new_exp (frag_now,
3468 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3469 - shorts_this_frag * 2),
3470 wid,
3471 &the_ins.reloc[m].exp,
3472 the_ins.reloc[m].pcrel,
3473 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3474 the_ins.reloc[m].pic_reloc));
3475 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3476 }
3477 }
3478
3479 void
3480 md_begin ()
3481 {
3482 /*
3483 * md_begin -- set up hash tables with 68000 instructions.
3484 * similar to what the vax assembler does. ---phr
3485 */
3486 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3487 a copy of it at runtime, adding in the information we want but isn't
3488 there. I think it'd be better to have an awk script hack the table
3489 at compile time. Or even just xstr the table and use it as-is. But
3490 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3491 names. */
3492
3493 register const struct m68k_opcode *ins;
3494 register struct m68k_incant *hack, *slak;
3495 register const char *retval = 0; /* empty string, or error msg text */
3496 register unsigned int i;
3497 register char c;
3498
3499 if (flag_mri)
3500 {
3501 flag_reg_prefix_optional = 1;
3502 m68k_abspcadd = 1;
3503 if (! m68k_rel32_from_cmdline)
3504 m68k_rel32 = 0;
3505 }
3506
3507 op_hash = hash_new ();
3508
3509 obstack_begin (&robyn, 4000);
3510 for (i = 0; i < m68k_numopcodes; i++)
3511 {
3512 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3513 do
3514 {
3515 ins = &m68k_opcodes[i];
3516 /* We *could* ignore insns that don't match our arch here
3517 but just leaving them out of the hash. */
3518 slak->m_operands = ins->args;
3519 slak->m_opnum = strlen (slak->m_operands) / 2;
3520 slak->m_arch = ins->arch;
3521 slak->m_opcode = ins->opcode;
3522 /* This is kludgey */
3523 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3524 if (i + 1 != m68k_numopcodes
3525 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3526 {
3527 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3528 i++;
3529 }
3530 else
3531 slak->m_next = 0;
3532 slak = slak->m_next;
3533 }
3534 while (slak);
3535
3536 retval = hash_insert (op_hash, ins->name, (char *) hack);
3537 if (retval)
3538 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3539 }
3540
3541 for (i = 0; i < m68k_numaliases; i++)
3542 {
3543 const char *name = m68k_opcode_aliases[i].primary;
3544 const char *alias = m68k_opcode_aliases[i].alias;
3545 PTR val = hash_find (op_hash, name);
3546 if (!val)
3547 as_fatal ("Internal Error: Can't find %s in hash table", name);
3548 retval = hash_insert (op_hash, alias, val);
3549 if (retval)
3550 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3551 }
3552
3553 /* In MRI mode, all unsized branches are variable sized. Normally,
3554 they are word sized. */
3555 if (flag_mri)
3556 {
3557 static struct m68k_opcode_alias mri_aliases[] =
3558 {
3559 { "bhi", "jhi", },
3560 { "bls", "jls", },
3561 { "bcc", "jcc", },
3562 { "bcs", "jcs", },
3563 { "bne", "jne", },
3564 { "beq", "jeq", },
3565 { "bvc", "jvc", },
3566 { "bvs", "jvs", },
3567 { "bpl", "jpl", },
3568 { "bmi", "jmi", },
3569 { "bge", "jge", },
3570 { "blt", "jlt", },
3571 { "bgt", "jgt", },
3572 { "ble", "jle", },
3573 { "bra", "jra", },
3574 { "bsr", "jbsr", },
3575 };
3576
3577 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3578 {
3579 const char *name = mri_aliases[i].primary;
3580 const char *alias = mri_aliases[i].alias;
3581 PTR val = hash_find (op_hash, name);
3582 if (!val)
3583 as_fatal ("Internal Error: Can't find %s in hash table", name);
3584 retval = hash_jam (op_hash, alias, val);
3585 if (retval)
3586 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3587 }
3588 }
3589
3590 for (i = 0; i < sizeof (mklower_table); i++)
3591 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3592
3593 for (i = 0; i < sizeof (notend_table); i++)
3594 {
3595 notend_table[i] = 0;
3596 alt_notend_table[i] = 0;
3597 }
3598 notend_table[','] = 1;
3599 notend_table['{'] = 1;
3600 notend_table['}'] = 1;
3601 alt_notend_table['a'] = 1;
3602 alt_notend_table['A'] = 1;
3603 alt_notend_table['d'] = 1;
3604 alt_notend_table['D'] = 1;
3605 alt_notend_table['#'] = 1;
3606 alt_notend_table['&'] = 1;
3607 alt_notend_table['f'] = 1;
3608 alt_notend_table['F'] = 1;
3609 #ifdef REGISTER_PREFIX
3610 alt_notend_table[REGISTER_PREFIX] = 1;
3611 #endif
3612
3613 /* We need to put '(' in alt_notend_table to handle
3614 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3615 */
3616 alt_notend_table['('] = 1;
3617
3618 /* We need to put '@' in alt_notend_table to handle
3619 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3620 */
3621 alt_notend_table['@'] = 1;
3622
3623 /* We need to put digits in alt_notend_table to handle
3624 bfextu %d0{24:1},%d0
3625 */
3626 alt_notend_table['0'] = 1;
3627 alt_notend_table['1'] = 1;
3628 alt_notend_table['2'] = 1;
3629 alt_notend_table['3'] = 1;
3630 alt_notend_table['4'] = 1;
3631 alt_notend_table['5'] = 1;
3632 alt_notend_table['6'] = 1;
3633 alt_notend_table['7'] = 1;
3634 alt_notend_table['8'] = 1;
3635 alt_notend_table['9'] = 1;
3636
3637 #ifndef MIT_SYNTAX_ONLY
3638 /* Insert pseudo ops, these have to go into the opcode table since
3639 gas expects pseudo ops to start with a dot */
3640 {
3641 int n = 0;
3642 while (mote_pseudo_table[n].poc_name)
3643 {
3644 hack = (struct m68k_incant *)
3645 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3646 hash_insert (op_hash,
3647 mote_pseudo_table[n].poc_name, (char *) hack);
3648 hack->m_operands = 0;
3649 hack->m_opnum = n;
3650 n++;
3651 }
3652 }
3653 #endif
3654
3655 init_regtable ();
3656
3657 #ifdef OBJ_ELF
3658 record_alignment (text_section, 2);
3659 record_alignment (data_section, 2);
3660 record_alignment (bss_section, 2);
3661 #endif
3662 }
3663
3664 static void
3665 select_control_regs ()
3666 {
3667 /* Note which set of "movec" control registers is available. */
3668 switch (cpu_of_arch (current_architecture))
3669 {
3670 case m68000:
3671 control_regs = m68000_control_regs;
3672 break;
3673 case m68010:
3674 control_regs = m68010_control_regs;
3675 break;
3676 case m68020:
3677 case m68030:
3678 control_regs = m68020_control_regs;
3679 break;
3680 case m68040:
3681 control_regs = m68040_control_regs;
3682 break;
3683 case m68060:
3684 control_regs = m68060_control_regs;
3685 break;
3686 case cpu32:
3687 control_regs = cpu32_control_regs;
3688 break;
3689 case mcf5200:
3690 control_regs = mcf5200_control_regs;
3691 break;
3692 default:
3693 abort ();
3694 }
3695 }
3696
3697 void
3698 m68k_init_after_args ()
3699 {
3700 if (cpu_of_arch (current_architecture) == 0)
3701 {
3702 int i;
3703 const char *default_cpu = TARGET_CPU;
3704
3705 if (*default_cpu == 'm')
3706 default_cpu++;
3707 for (i = 0; i < n_archs; i++)
3708 if (strcasecmp (default_cpu, archs[i].name) == 0)
3709 break;
3710 if (i == n_archs)
3711 {
3712 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3713 current_architecture |= m68020;
3714 }
3715 else
3716 current_architecture |= archs[i].arch;
3717 }
3718 /* Permit m68881 specification with all cpus; those that can't work
3719 with a coprocessor could be doing emulation. */
3720 if (current_architecture & m68851)
3721 {
3722 if (current_architecture & m68040)
3723 {
3724 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3725 }
3726 }
3727 /* What other incompatibilities could we check for? */
3728
3729 /* Toss in some default assumptions about coprocessors. */
3730 if (!no_68881
3731 && (cpu_of_arch (current_architecture)
3732 /* Can CPU32 have a 68881 coprocessor?? */
3733 & (m68020 | m68030 | cpu32)))
3734 {
3735 current_architecture |= m68881;
3736 }
3737 if (!no_68851
3738 && (cpu_of_arch (current_architecture) & m68020up) != 0
3739 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3740 {
3741 current_architecture |= m68851;
3742 }
3743 if (no_68881 && (current_architecture & m68881))
3744 as_bad ("options for 68881 and no-68881 both given");
3745 if (no_68851 && (current_architecture & m68851))
3746 as_bad ("options for 68851 and no-68851 both given");
3747
3748 #ifdef OBJ_AOUT
3749 /* Work out the magic number. This isn't very general. */
3750 if (current_architecture & m68000)
3751 m68k_aout_machtype = 0;
3752 else if (current_architecture & m68010)
3753 m68k_aout_machtype = 1;
3754 else if (current_architecture & m68020)
3755 m68k_aout_machtype = 2;
3756 else
3757 m68k_aout_machtype = 2;
3758 #endif
3759
3760 /* Note which set of "movec" control registers is available. */
3761 select_control_regs ();
3762
3763 if (cpu_of_arch (current_architecture) < m68020)
3764 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3765 }
3766 \f
3767 /* This is called when a label is defined. */
3768
3769 void
3770 m68k_frob_label (sym)
3771 symbolS *sym;
3772 {
3773 struct label_line *n;
3774
3775 n = (struct label_line *) xmalloc (sizeof *n);
3776 n->next = labels;
3777 n->label = sym;
3778 as_where (&n->file, &n->line);
3779 n->text = 0;
3780 labels = n;
3781 current_label = n;
3782 }
3783
3784 /* This is called when a value that is not an instruction is emitted. */
3785
3786 void
3787 m68k_flush_pending_output ()
3788 {
3789 current_label = NULL;
3790 }
3791
3792 /* This is called at the end of the assembly, when the final value of
3793 the label is known. We warn if this is a text symbol aligned at an
3794 odd location. */
3795
3796 void
3797 m68k_frob_symbol (sym)
3798 symbolS *sym;
3799 {
3800 if ((S_GET_VALUE (sym) & 1) != 0)
3801 {
3802 struct label_line *l;
3803
3804 for (l = labels; l != NULL; l = l->next)
3805 {
3806 if (l->label == sym)
3807 {
3808 if (l->text)
3809 as_warn_where (l->file, l->line,
3810 "text label `%s' aligned to odd boundary",
3811 S_GET_NAME (sym));
3812 break;
3813 }
3814 }
3815 }
3816 }
3817 \f
3818 /* This is called if we go in or out of MRI mode because of the .mri
3819 pseudo-op. */
3820
3821 void
3822 m68k_mri_mode_change (on)
3823 int on;
3824 {
3825 if (on)
3826 {
3827 if (! flag_reg_prefix_optional)
3828 {
3829 flag_reg_prefix_optional = 1;
3830 #ifdef REGISTER_PREFIX
3831 init_regtable ();
3832 #endif
3833 }
3834 m68k_abspcadd = 1;
3835 if (! m68k_rel32_from_cmdline)
3836 m68k_rel32 = 0;
3837 }
3838 else
3839 {
3840 if (! reg_prefix_optional_seen)
3841 {
3842 #ifdef REGISTER_PREFIX_OPTIONAL
3843 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3844 #else
3845 flag_reg_prefix_optional = 0;
3846 #endif
3847 #ifdef REGISTER_PREFIX
3848 init_regtable ();
3849 #endif
3850 }
3851 m68k_abspcadd = 0;
3852 if (! m68k_rel32_from_cmdline)
3853 m68k_rel32 = 1;
3854 }
3855 }
3856
3857 /* Equal to MAX_PRECISION in atof-ieee.c */
3858 #define MAX_LITTLENUMS 6
3859
3860 /* Turn a string in input_line_pointer into a floating point constant
3861 of type type, and store the appropriate bytes in *litP. The number
3862 of LITTLENUMS emitted is stored in *sizeP . An error message is
3863 returned, or NULL on OK. */
3864
3865 char *
3866 md_atof (type, litP, sizeP)
3867 char type;
3868 char *litP;
3869 int *sizeP;
3870 {
3871 int prec;
3872 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3873 LITTLENUM_TYPE *wordP;
3874 char *t;
3875 char *atof_ieee ();
3876
3877 switch (type)
3878 {
3879 case 'f':
3880 case 'F':
3881 case 's':
3882 case 'S':
3883 prec = 2;
3884 break;
3885
3886 case 'd':
3887 case 'D':
3888 case 'r':
3889 case 'R':
3890 prec = 4;
3891 break;
3892
3893 case 'x':
3894 case 'X':
3895 prec = 6;
3896 break;
3897
3898 case 'p':
3899 case 'P':
3900 prec = 6;
3901 break;
3902
3903 default:
3904 *sizeP = 0;
3905 return "Bad call to MD_ATOF()";
3906 }
3907 t = atof_ieee (input_line_pointer, type, words);
3908 if (t)
3909 input_line_pointer = t;
3910
3911 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3912 for (wordP = words; prec--;)
3913 {
3914 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3915 litP += sizeof (LITTLENUM_TYPE);
3916 }
3917 return 0;
3918 }
3919
3920 void
3921 md_number_to_chars (buf, val, n)
3922 char *buf;
3923 valueT val;
3924 int n;
3925 {
3926 number_to_chars_bigendian (buf, val, n);
3927 }
3928
3929 static void
3930 md_apply_fix_2 (fixP, val)
3931 fixS *fixP;
3932 offsetT val;
3933 {
3934 addressT upper_limit;
3935 offsetT lower_limit;
3936
3937 /* This is unnecessary but it convinces the native rs6000 compiler
3938 to generate the code we want. */
3939 char *buf = fixP->fx_frag->fr_literal;
3940 buf += fixP->fx_where;
3941 /* end ibm compiler workaround */
3942
3943 if (val & 0x80000000)
3944 val |= ~(addressT)0x7fffffff;
3945 else
3946 val &= 0x7fffffff;
3947
3948 #ifdef OBJ_ELF
3949 if (fixP->fx_addsy)
3950 {
3951 memset (buf, 0, fixP->fx_size);
3952 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3953 return;
3954 }
3955 #endif
3956
3957 switch (fixP->fx_size)
3958 {
3959 /* The cast to offsetT below are necessary to make code correct for
3960 machines where ints are smaller than offsetT */
3961 case 1:
3962 *buf++ = val;
3963 upper_limit = 0x7f;
3964 lower_limit = - (offsetT) 0x80;
3965 break;
3966 case 2:
3967 *buf++ = (val >> 8);
3968 *buf++ = val;
3969 upper_limit = 0x7fff;
3970 lower_limit = - (offsetT) 0x8000;
3971 break;
3972 case 4:
3973 *buf++ = (val >> 24);
3974 *buf++ = (val >> 16);
3975 *buf++ = (val >> 8);
3976 *buf++ = val;
3977 upper_limit = 0x7fffffff;
3978 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3979 break;
3980 default:
3981 BAD_CASE (fixP->fx_size);
3982 }
3983
3984 /* Fix up a negative reloc. */
3985 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3986 {
3987 fixP->fx_addsy = fixP->fx_subsy;
3988 fixP->fx_subsy = NULL;
3989 fixP->fx_tcbit = 1;
3990 }
3991
3992 /* For non-pc-relative values, it's conceivable we might get something
3993 like "0xff" for a byte field. So extend the upper part of the range
3994 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3995 so that we can do any range checking at all. */
3996 if (! fixP->fx_pcrel && ! fixP->fx_signed)
3997 upper_limit = upper_limit * 2 + 1;
3998
3999 if ((addressT) val > upper_limit
4000 && (val > 0 || val < lower_limit))
4001 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
4002
4003 /* A one byte PC-relative reloc means a short branch. We can't use
4004 a short branch with a value of 0 or -1, because those indicate
4005 different opcodes (branches with longer offsets). */
4006 if (fixP->fx_pcrel
4007 && fixP->fx_size == 1
4008 && (fixP->fx_addsy == NULL
4009 || S_IS_DEFINED (fixP->fx_addsy))
4010 && (val == 0 || val == -1))
4011 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
4012 }
4013
4014 #ifdef BFD_ASSEMBLER
4015 int
4016 md_apply_fix (fixP, valp)
4017 fixS *fixP;
4018 valueT *valp;
4019 {
4020 md_apply_fix_2 (fixP, (addressT) *valp);
4021 return 1;
4022 }
4023 #else
4024 void md_apply_fix (fixP, val)
4025 fixS *fixP;
4026 long val;
4027 {
4028 md_apply_fix_2 (fixP, (addressT) val);
4029 }
4030 #endif
4031
4032 /* *fragP has been relaxed to its final size, and now needs to have
4033 the bytes inside it modified to conform to the new size There is UGLY
4034 MAGIC here. ..
4035 */
4036 void
4037 md_convert_frag_1 (fragP)
4038 register fragS *fragP;
4039 {
4040 long disp;
4041 long ext = 0;
4042 fixS *fixP;
4043
4044 /* Address in object code of the displacement. */
4045 register int object_address = fragP->fr_fix + fragP->fr_address;
4046
4047 /* Address in gas core of the place to store the displacement. */
4048 /* This convinces the native rs6000 compiler to generate the code we
4049 want. */
4050 register char *buffer_address = fragP->fr_literal;
4051 buffer_address += fragP->fr_fix;
4052 /* end ibm compiler workaround */
4053
4054 /* The displacement of the address, from current location. */
4055 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4056 disp = (disp + fragP->fr_offset) - object_address;
4057
4058 #ifdef BFD_ASSEMBLER
4059 disp += fragP->fr_symbol->sy_frag->fr_address;
4060 #endif
4061
4062 switch (fragP->fr_subtype)
4063 {
4064 case TAB (BCC68000, BYTE):
4065 case TAB (ABRANCH, BYTE):
4066 know (issbyte (disp));
4067 if (disp == 0)
4068 as_bad ("short branch with zero offset: use :w");
4069 fragP->fr_opcode[1] = disp;
4070 ext = 0;
4071 break;
4072 case TAB (DBCC, SHORT):
4073 know (issword (disp));
4074 ext = 2;
4075 break;
4076 case TAB (BCC68000, SHORT):
4077 case TAB (ABRANCH, SHORT):
4078 know (issword (disp));
4079 fragP->fr_opcode[1] = 0x00;
4080 ext = 2;
4081 break;
4082 case TAB (ABRANCH, LONG):
4083 if (!HAVE_LONG_BRANCH(current_architecture))
4084 {
4085 if (fragP->fr_opcode[0] == 0x61)
4086 /* BSR */
4087 {
4088 fragP->fr_opcode[0] = 0x4E;
4089 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4090
4091 fix_new (fragP,
4092 fragP->fr_fix,
4093 4,
4094 fragP->fr_symbol,
4095 fragP->fr_offset,
4096 0,
4097 NO_RELOC);
4098
4099 fragP->fr_fix += 4;
4100 ext = 0;
4101 }
4102 /* BRA */
4103 else if (fragP->fr_opcode[0] == 0x60)
4104 {
4105 fragP->fr_opcode[0] = 0x4E;
4106 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4107 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4108 fragP->fr_offset, 0, NO_RELOC);
4109 fragP->fr_fix += 4;
4110 ext = 0;
4111 }
4112 else
4113 {
4114 as_bad ("Long branch offset not supported.");
4115 }
4116 }
4117 else
4118 {
4119 fragP->fr_opcode[1] = (char) 0xff;
4120 ext = 4;
4121 }
4122 break;
4123 case TAB (BCC68000, LONG):
4124 /* only Bcc 68000 instructions can come here */
4125 /* change bcc into b!cc/jmp absl long */
4126 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4127 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4128
4129 /* JF: these used to be fr_opcode[2,3], but they may be in a
4130 different frag, in which case refering to them is a no-no.
4131 Only fr_opcode[0,1] are guaranteed to work. */
4132 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4133 *buffer_address++ = (char) 0xf9;
4134 fragP->fr_fix += 2; /* account for jmp instruction */
4135 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4136 fragP->fr_offset, 0, NO_RELOC);
4137 fragP->fr_fix += 4;
4138 ext = 0;
4139 break;
4140 case TAB (DBCC, LONG):
4141 /* only DBcc 68000 instructions can come here */
4142 /* change dbcc into dbcc/jmp absl long */
4143 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4144 *buffer_address++ = 0x00; /* branch offset = 4 */
4145 *buffer_address++ = 0x04;
4146 *buffer_address++ = 0x60; /* put in bra pc+6 */
4147 *buffer_address++ = 0x06;
4148 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4149 *buffer_address++ = (char) 0xf9;
4150
4151 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4152 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4153 fragP->fr_offset, 0, NO_RELOC);
4154 fragP->fr_fix += 4;
4155 ext = 0;
4156 break;
4157 case TAB (FBRANCH, SHORT):
4158 know ((fragP->fr_opcode[1] & 0x40) == 0);
4159 ext = 2;
4160 break;
4161 case TAB (FBRANCH, LONG):
4162 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4163 ext = 4;
4164 break;
4165 case TAB (PCREL, SHORT):
4166 ext = 2;
4167 break;
4168 case TAB (PCREL, LONG):
4169 /* The thing to do here is force it to ABSOLUTE LONG, since
4170 PCREL is really trying to shorten an ABSOLUTE address anyway */
4171 /* JF FOO This code has not been tested */
4172 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4173 0, NO_RELOC);
4174 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4175 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4176 (unsigned) fragP->fr_opcode[0],
4177 (unsigned long) fragP->fr_address);
4178 fragP->fr_opcode[1] &= ~0x3F;
4179 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4180 fragP->fr_fix += 4;
4181 ext = 0;
4182 break;
4183 case TAB (PCLEA, SHORT):
4184 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4185 fragP->fr_offset, 1, NO_RELOC);
4186 fragP->fr_opcode[1] &= ~0x3F;
4187 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4188 ext = 2;
4189 break;
4190 case TAB (PCLEA, LONG):
4191 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4192 fragP->fr_offset, 1, NO_RELOC);
4193 fixP->fx_pcrel_adjust = 2;
4194 /* Already set to mode 7.3; this indicates: PC indirect with
4195 suppressed index, 32-bit displacement. */
4196 *buffer_address++ = 0x01;
4197 *buffer_address++ = 0x70;
4198 fragP->fr_fix += 2;
4199 ext = 4;
4200 break;
4201
4202 case TAB (PCINDEX, BYTE):
4203 disp += 2;
4204 if (!issbyte (disp))
4205 {
4206 as_bad ("displacement doesn't fit in one byte");
4207 disp = 0;
4208 }
4209 assert (fragP->fr_fix >= 2);
4210 buffer_address[-2] &= ~1;
4211 buffer_address[-1] = disp;
4212 ext = 0;
4213 break;
4214 case TAB (PCINDEX, SHORT):
4215 disp += 2;
4216 assert (issword (disp));
4217 assert (fragP->fr_fix >= 2);
4218 buffer_address[-2] |= 0x1;
4219 buffer_address[-1] = 0x20;
4220 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4221 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4222 NO_RELOC);
4223 fixP->fx_pcrel_adjust = 2;
4224 ext = 2;
4225 break;
4226 case TAB (PCINDEX, LONG):
4227 disp += 2;
4228 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4229 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4230 NO_RELOC);
4231 fixP->fx_pcrel_adjust = 2;
4232 assert (fragP->fr_fix >= 2);
4233 buffer_address[-2] |= 0x1;
4234 buffer_address[-1] = 0x30;
4235 ext = 4;
4236 break;
4237 }
4238
4239 if (ext)
4240 {
4241 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4242 fragP->fr_fix += ext;
4243 }
4244 }
4245
4246 #ifndef BFD_ASSEMBLER
4247
4248 void
4249 md_convert_frag (headers, sec, fragP)
4250 object_headers *headers;
4251 segT sec;
4252 fragS *fragP;
4253 {
4254 md_convert_frag_1 (fragP);
4255 }
4256
4257 #else
4258
4259 void
4260 md_convert_frag (abfd, sec, fragP)
4261 bfd *abfd;
4262 segT sec;
4263 fragS *fragP;
4264 {
4265 md_convert_frag_1 (fragP);
4266 }
4267 #endif
4268
4269 /* Force truly undefined symbols to their maximum size, and generally set up
4270 the frag list to be relaxed
4271 */
4272 int
4273 md_estimate_size_before_relax (fragP, segment)
4274 register fragS *fragP;
4275 segT segment;
4276 {
4277 int old_fix;
4278 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4279
4280 old_fix = fragP->fr_fix;
4281
4282 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4283 switch (fragP->fr_subtype)
4284 {
4285
4286 case TAB (ABRANCH, SZ_UNDEF):
4287 {
4288 if ((fragP->fr_symbol != NULL) /* Not absolute */
4289 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4290 {
4291 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4292 break;
4293 }
4294 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4295 {
4296 /* On 68000, or for absolute value, switch to abs long */
4297 /* FIXME, we should check abs val, pick short or long */
4298 if (fragP->fr_opcode[0] == 0x61)
4299 {
4300 fragP->fr_opcode[0] = 0x4E;
4301 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4302 fix_new (fragP, fragP->fr_fix, 4,
4303 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4304 fragP->fr_fix += 4;
4305 frag_wane (fragP);
4306 }
4307 else if (fragP->fr_opcode[0] == 0x60)
4308 {
4309 fragP->fr_opcode[0] = 0x4E;
4310 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4311 fix_new (fragP, fragP->fr_fix, 4,
4312 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4313 fragP->fr_fix += 4;
4314 frag_wane (fragP);
4315 }
4316 else
4317 {
4318 as_warn ("Long branch offset to extern symbol not supported.");
4319 }
4320 }
4321 else
4322 { /* Symbol is still undefined. Make it simple */
4323 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4324 fragP->fr_offset, 1, NO_RELOC);
4325 fragP->fr_fix += 4;
4326 fragP->fr_opcode[1] = (char) 0xff;
4327 frag_wane (fragP);
4328 break;
4329 }
4330
4331 break;
4332 } /* case TAB(ABRANCH,SZ_UNDEF) */
4333
4334 case TAB (FBRANCH, SZ_UNDEF):
4335 {
4336 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4337 {
4338 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4339 fragP->fr_var += 2;
4340 }
4341 else
4342 {
4343 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4344 fragP->fr_offset, 1, NO_RELOC);
4345 fragP->fr_fix += 4;
4346 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4347 frag_wane (fragP);
4348 }
4349 break;
4350 } /* TAB(FBRANCH,SZ_UNDEF) */
4351
4352 case TAB (PCREL, SZ_UNDEF):
4353 {
4354 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4355 || flag_short_refs
4356 || cpu_of_arch (current_architecture) < m68020)
4357 {
4358 fragP->fr_subtype = TAB (PCREL, SHORT);
4359 fragP->fr_var += 2;
4360 }
4361 else
4362 {
4363 fragP->fr_subtype = TAB (PCREL, LONG);
4364 fragP->fr_var += 4;
4365 }
4366 break;
4367 } /* TAB(PCREL,SZ_UNDEF) */
4368
4369 case TAB (BCC68000, SZ_UNDEF):
4370 {
4371 if ((fragP->fr_symbol != NULL)
4372 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4373 {
4374 fragP->fr_subtype = TAB (BCC68000, BYTE);
4375 break;
4376 }
4377 /* only Bcc 68000 instructions can come here */
4378 /* change bcc into b!cc/jmp absl long */
4379 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4380 if (flag_short_refs)
4381 {
4382 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4383 /* JF: these were fr_opcode[2,3] */
4384 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4385 buffer_address[1] = (char) 0xf8;
4386 fragP->fr_fix += 2; /* account for jmp instruction */
4387 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4388 fragP->fr_offset, 0, NO_RELOC);
4389 fragP->fr_fix += 2;
4390 }
4391 else
4392 {
4393 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4394 /* JF: these were fr_opcode[2,3] */
4395 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4396 buffer_address[1] = (char) 0xf9;
4397 fragP->fr_fix += 2; /* account for jmp instruction */
4398 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4399 fragP->fr_offset, 0, NO_RELOC);
4400 fragP->fr_fix += 4;
4401 }
4402 frag_wane (fragP);
4403 break;
4404 } /* case TAB(BCC68000,SZ_UNDEF) */
4405
4406 case TAB (DBCC, SZ_UNDEF):
4407 {
4408 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4409 {
4410 fragP->fr_subtype = TAB (DBCC, SHORT);
4411 fragP->fr_var += 2;
4412 break;
4413 }
4414 /* only DBcc 68000 instructions can come here */
4415 /* change dbcc into dbcc/jmp absl long */
4416 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4417 buffer_address[0] = 0x00; /* branch offset = 4 */
4418 buffer_address[1] = 0x04;
4419 buffer_address[2] = 0x60; /* put in bra pc + ... */
4420
4421 if (flag_short_refs)
4422 {
4423 /* JF: these were fr_opcode[5-7] */
4424 buffer_address[3] = 0x04; /* plus 4 */
4425 buffer_address[4] = 0x4e; /* Put in Jump Word */
4426 buffer_address[5] = (char) 0xf8;
4427 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4428 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4429 fragP->fr_offset, 0, NO_RELOC);
4430 fragP->fr_fix += 2;
4431 }
4432 else
4433 {
4434 /* JF: these were fr_opcode[5-7] */
4435 buffer_address[3] = 0x06; /* Plus 6 */
4436 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4437 buffer_address[5] = (char) 0xf9;
4438 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4439 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4440 fragP->fr_offset, 0, NO_RELOC);
4441 fragP->fr_fix += 4;
4442 }
4443
4444 frag_wane (fragP);
4445 break;
4446 } /* case TAB(DBCC,SZ_UNDEF) */
4447
4448 case TAB (PCLEA, SZ_UNDEF):
4449 {
4450 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4451 || flag_short_refs
4452 || cpu_of_arch (current_architecture) < m68020)
4453 {
4454 fragP->fr_subtype = TAB (PCLEA, SHORT);
4455 fragP->fr_var += 2;
4456 }
4457 else
4458 {
4459 fragP->fr_subtype = TAB (PCLEA, LONG);
4460 fragP->fr_var += 6;
4461 }
4462 break;
4463 } /* TAB(PCLEA,SZ_UNDEF) */
4464
4465 case TAB (PCINDEX, SZ_UNDEF):
4466 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4467 || cpu_of_arch (current_architecture) < m68020)
4468 {
4469 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4470 }
4471 else
4472 {
4473 fragP->fr_subtype = TAB (PCINDEX, LONG);
4474 fragP->fr_var += 4;
4475 }
4476 break;
4477
4478 default:
4479 break;
4480 }
4481
4482 /* now that SZ_UNDEF are taken care of, check others */
4483 switch (fragP->fr_subtype)
4484 {
4485 case TAB (BCC68000, BYTE):
4486 case TAB (ABRANCH, BYTE):
4487 /* We can't do a short jump to the next instruction, so in that
4488 case we force word mode. At this point S_GET_VALUE should
4489 return the offset of the symbol within its frag. If the
4490 symbol is at the start of a frag, and it is the next frag
4491 with any data in it (usually this is just the next frag, but
4492 assembler listings may introduce empty frags), we must use
4493 word mode. */
4494 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4495 {
4496 fragS *l;
4497
4498 for (l = fragP->fr_next;
4499 l != fragP->fr_symbol->sy_frag;
4500 l = l->fr_next)
4501 if (l->fr_fix + l->fr_var != 0)
4502 break;
4503 if (l == fragP->fr_symbol->sy_frag)
4504 {
4505 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4506 fragP->fr_var += 2;
4507 }
4508 }
4509 break;
4510 default:
4511 break;
4512 }
4513 return fragP->fr_var + fragP->fr_fix - old_fix;
4514 }
4515
4516 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4517 /* the bit-field entries in the relocation_info struct plays hell
4518 with the byte-order problems of cross-assembly. So as a hack,
4519 I added this mach. dependent ri twiddler. Ugly, but it gets
4520 you there. -KWK */
4521 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4522 are symbolnum, most sig. byte first. Last byte is broken up with
4523 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4524 nibble as nuthin. (on Sun 3 at least) */
4525 /* Translate the internal relocation information into target-specific
4526 format. */
4527 #ifdef comment
4528 void
4529 md_ri_to_chars (the_bytes, ri)
4530 char *the_bytes;
4531 struct reloc_info_generic *ri;
4532 {
4533 /* this is easy */
4534 md_number_to_chars (the_bytes, ri->r_address, 4);
4535 /* now the fun stuff */
4536 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4537 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4538 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4539 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4540 ((ri->r_extern << 4) & 0x10));
4541 }
4542
4543 #endif /* comment */
4544
4545 #ifndef BFD_ASSEMBLER
4546 void
4547 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4548 char *where;
4549 fixS *fixP;
4550 relax_addressT segment_address_in_file;
4551 {
4552 /*
4553 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4554 * Out: GNU LD relocation length code: 0, 1, or 2.
4555 */
4556
4557 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4558 long r_symbolnum;
4559
4560 know (fixP->fx_addsy != NULL);
4561
4562 md_number_to_chars (where,
4563 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4564 4);
4565
4566 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4567 ? S_GET_TYPE (fixP->fx_addsy)
4568 : fixP->fx_addsy->sy_number);
4569
4570 where[4] = (r_symbolnum >> 16) & 0x0ff;
4571 where[5] = (r_symbolnum >> 8) & 0x0ff;
4572 where[6] = r_symbolnum & 0x0ff;
4573 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4574 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4575 }
4576 #endif
4577
4578 #endif /* OBJ_AOUT or OBJ_BOUT */
4579
4580 #ifndef WORKING_DOT_WORD
4581 CONST int md_short_jump_size = 4;
4582 CONST int md_long_jump_size = 6;
4583
4584 void
4585 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4586 char *ptr;
4587 addressT from_addr, to_addr;
4588 fragS *frag;
4589 symbolS *to_symbol;
4590 {
4591 valueT offset;
4592
4593 offset = to_addr - (from_addr + 2);
4594
4595 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4596 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4597 }
4598
4599 void
4600 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4601 char *ptr;
4602 addressT from_addr, to_addr;
4603 fragS *frag;
4604 symbolS *to_symbol;
4605 {
4606 valueT offset;
4607
4608 if (!HAVE_LONG_BRANCH(current_architecture))
4609 {
4610 offset = to_addr - S_GET_VALUE (to_symbol);
4611 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4612 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4613 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4614 0, NO_RELOC);
4615 }
4616 else
4617 {
4618 offset = to_addr - (from_addr + 2);
4619 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4620 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4621 }
4622 }
4623
4624 #endif
4625
4626 /* Different values of OK tell what its OK to return. Things that
4627 aren't OK are an error (what a shock, no?)
4628
4629 0: Everything is OK
4630 10: Absolute 1:8 only
4631 20: Absolute 0:7 only
4632 30: absolute 0:15 only
4633 40: Absolute 0:31 only
4634 50: absolute 0:127 only
4635 55: absolute -64:63 only
4636 60: absolute -128:127 only
4637 70: absolute 0:4095 only
4638 80: No bignums
4639
4640 */
4641
4642 static int
4643 get_num (exp, ok)
4644 struct m68k_exp *exp;
4645 int ok;
4646 {
4647 if (exp->exp.X_op == O_absent)
4648 {
4649 /* Do the same thing the VAX asm does */
4650 op (exp) = O_constant;
4651 adds (exp) = 0;
4652 subs (exp) = 0;
4653 offs (exp) = 0;
4654 if (ok == 10)
4655 {
4656 as_warn ("expression out of range: defaulting to 1");
4657 offs (exp) = 1;
4658 }
4659 }
4660 else if (exp->exp.X_op == O_constant)
4661 {
4662 switch (ok)
4663 {
4664 case 10:
4665 if (offs (exp) < 1 || offs (exp) > 8)
4666 {
4667 as_warn ("expression out of range: defaulting to 1");
4668 offs (exp) = 1;
4669 }
4670 break;
4671 case 20:
4672 if (offs (exp) < 0 || offs (exp) > 7)
4673 goto outrange;
4674 break;
4675 case 30:
4676 if (offs (exp) < 0 || offs (exp) > 15)
4677 goto outrange;
4678 break;
4679 case 40:
4680 if (offs (exp) < 0 || offs (exp) > 32)
4681 goto outrange;
4682 break;
4683 case 50:
4684 if (offs (exp) < 0 || offs (exp) > 127)
4685 goto outrange;
4686 break;
4687 case 55:
4688 if (offs (exp) < -64 || offs (exp) > 63)
4689 goto outrange;
4690 break;
4691 case 60:
4692 if (offs (exp) < -128 || offs (exp) > 127)
4693 goto outrange;
4694 break;
4695 case 70:
4696 if (offs (exp) < 0 || offs (exp) > 4095)
4697 {
4698 outrange:
4699 as_warn ("expression out of range: defaulting to 0");
4700 offs (exp) = 0;
4701 }
4702 break;
4703 default:
4704 break;
4705 }
4706 }
4707 else if (exp->exp.X_op == O_big)
4708 {
4709 if (offs (exp) <= 0 /* flonum */
4710 && (ok == 80 /* no bignums */
4711 || (ok > 10 /* small-int ranges including 0 ok */
4712 /* If we have a flonum zero, a zero integer should
4713 do as well (e.g., in moveq). */
4714 && generic_floating_point_number.exponent == 0
4715 && generic_floating_point_number.low[0] == 0)))
4716 {
4717 /* HACK! Turn it into a long */
4718 LITTLENUM_TYPE words[6];
4719
4720 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4721 op (exp) = O_constant;
4722 adds (exp) = 0;
4723 subs (exp) = 0;
4724 offs (exp) = words[1] | (words[0] << 16);
4725 }
4726 else if (ok != 0)
4727 {
4728 op (exp) = O_constant;
4729 adds (exp) = 0;
4730 subs (exp) = 0;
4731 offs (exp) = (ok == 10) ? 1 : 0;
4732 as_warn ("Can't deal with expression; defaulting to %ld",
4733 offs (exp));
4734 }
4735 }
4736 else
4737 {
4738 if (ok >= 10 && ok <= 70)
4739 {
4740 op (exp) = O_constant;
4741 adds (exp) = 0;
4742 subs (exp) = 0;
4743 offs (exp) = (ok == 10) ? 1 : 0;
4744 as_warn ("Can't deal with expression; defaulting to %ld",
4745 offs (exp));
4746 }
4747 }
4748
4749 if (exp->size != SIZE_UNSPEC)
4750 {
4751 switch (exp->size)
4752 {
4753 case SIZE_UNSPEC:
4754 case SIZE_LONG:
4755 break;
4756 case SIZE_BYTE:
4757 if (!isbyte (offs (exp)))
4758 as_warn ("expression doesn't fit in BYTE");
4759 break;
4760 case SIZE_WORD:
4761 if (!isword (offs (exp)))
4762 as_warn ("expression doesn't fit in WORD");
4763 break;
4764 }
4765 }
4766
4767 return offs (exp);
4768 }
4769
4770 /* These are the back-ends for the various machine dependent pseudo-ops. */
4771 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4772
4773 static void
4774 s_data1 (ignore)
4775 int ignore;
4776 {
4777 subseg_set (data_section, 1);
4778 demand_empty_rest_of_line ();
4779 }
4780
4781 static void
4782 s_data2 (ignore)
4783 int ignore;
4784 {
4785 subseg_set (data_section, 2);
4786 demand_empty_rest_of_line ();
4787 }
4788
4789 static void
4790 s_bss (ignore)
4791 int ignore;
4792 {
4793 /* We don't support putting frags in the BSS segment, we fake it
4794 by marking in_bss, then looking at s_skip for clues. */
4795
4796 subseg_set (bss_section, 0);
4797 demand_empty_rest_of_line ();
4798 }
4799
4800 static void
4801 s_even (ignore)
4802 int ignore;
4803 {
4804 register int temp;
4805 register long temp_fill;
4806
4807 temp = 1; /* JF should be 2? */
4808 temp_fill = get_absolute_expression ();
4809 if (!need_pass_2) /* Never make frag if expect extra pass. */
4810 frag_align (temp, (int) temp_fill, 0);
4811 demand_empty_rest_of_line ();
4812 record_alignment (now_seg, temp);
4813 }
4814
4815 static void
4816 s_proc (ignore)
4817 int ignore;
4818 {
4819 demand_empty_rest_of_line ();
4820 }
4821 \f
4822 /* Pseudo-ops handled for MRI compatibility. */
4823
4824 /* This function returns non-zero if the argument is a conditional
4825 pseudo-op. This is called when checking whether a pending
4826 alignment is needed. */
4827
4828 int
4829 m68k_conditional_pseudoop (pop)
4830 pseudo_typeS *pop;
4831 {
4832 return (pop->poc_handler == s_mri_if
4833 || pop->poc_handler == s_mri_else);
4834 }
4835
4836 /* Handle an MRI style chip specification. */
4837
4838 static void
4839 mri_chip ()
4840 {
4841 char *s;
4842 char c;
4843 int i;
4844
4845 s = input_line_pointer;
4846 c = get_symbol_end ();
4847 for (i = 0; i < n_archs; i++)
4848 if (strcasecmp (s, archs[i].name) == 0)
4849 break;
4850 if (i >= n_archs)
4851 {
4852 as_bad ("%s: unrecognized processor name", s);
4853 *input_line_pointer = c;
4854 ignore_rest_of_line ();
4855 return;
4856 }
4857 *input_line_pointer = c;
4858
4859 if (*input_line_pointer == '/')
4860 current_architecture = 0;
4861 else
4862 current_architecture &= m68881 | m68851;
4863 current_architecture |= archs[i].arch;
4864
4865 while (*input_line_pointer == '/')
4866 {
4867 ++input_line_pointer;
4868 s = input_line_pointer;
4869 c = get_symbol_end ();
4870 if (strcmp (s, "68881") == 0)
4871 current_architecture |= m68881;
4872 else if (strcmp (s, "68851") == 0)
4873 current_architecture |= m68851;
4874 *input_line_pointer = c;
4875 }
4876
4877 /* Update info about available control registers. */
4878 select_control_regs ();
4879 }
4880
4881 /* The MRI CHIP pseudo-op. */
4882
4883 static void
4884 s_chip (ignore)
4885 int ignore;
4886 {
4887 char *stop = NULL;
4888 char stopc;
4889
4890 if (flag_mri)
4891 stop = mri_comment_field (&stopc);
4892 mri_chip ();
4893 if (flag_mri)
4894 mri_comment_end (stop, stopc);
4895 demand_empty_rest_of_line ();
4896 }
4897
4898 /* The MRI FOPT pseudo-op. */
4899
4900 static void
4901 s_fopt (ignore)
4902 int ignore;
4903 {
4904 SKIP_WHITESPACE ();
4905
4906 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4907 {
4908 int temp;
4909
4910 input_line_pointer += 3;
4911 temp = get_absolute_expression ();
4912 if (temp < 0 || temp > 7)
4913 as_bad ("bad coprocessor id");
4914 else
4915 m68k_float_copnum = COP0 + temp;
4916 }
4917 else
4918 {
4919 as_bad ("unrecognized fopt option");
4920 ignore_rest_of_line ();
4921 return;
4922 }
4923
4924 demand_empty_rest_of_line ();
4925 }
4926
4927 /* The structure used to handle the MRI OPT pseudo-op. */
4928
4929 struct opt_action
4930 {
4931 /* The name of the option. */
4932 const char *name;
4933
4934 /* If this is not NULL, just call this function. The first argument
4935 is the ARG field of this structure, the second argument is
4936 whether the option was negated. */
4937 void (*pfn) PARAMS ((int arg, int on));
4938
4939 /* If this is not NULL, and the PFN field is NULL, set the variable
4940 this points to. Set it to the ARG field if the option was not
4941 negated, and the NOTARG field otherwise. */
4942 int *pvar;
4943
4944 /* The value to pass to PFN or to assign to *PVAR. */
4945 int arg;
4946
4947 /* The value to assign to *PVAR if the option is negated. If PFN is
4948 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4949 the option may not be negated. */
4950 int notarg;
4951 };
4952
4953 /* The table used to handle the MRI OPT pseudo-op. */
4954
4955 static void skip_to_comma PARAMS ((int, int));
4956 static void opt_nest PARAMS ((int, int));
4957 static void opt_chip PARAMS ((int, int));
4958 static void opt_list PARAMS ((int, int));
4959 static void opt_list_symbols PARAMS ((int, int));
4960
4961 static const struct opt_action opt_table[] =
4962 {
4963 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4964
4965 /* We do relaxing, so there is little use for these options. */
4966 { "b", 0, 0, 0, 0 },
4967 { "brs", 0, 0, 0, 0 },
4968 { "brb", 0, 0, 0, 0 },
4969 { "brl", 0, 0, 0, 0 },
4970 { "brw", 0, 0, 0, 0 },
4971
4972 { "c", 0, 0, 0, 0 },
4973 { "cex", 0, 0, 0, 0 },
4974 { "case", 0, &symbols_case_sensitive, 1, 0 },
4975 { "cl", 0, 0, 0, 0 },
4976 { "cre", 0, 0, 0, 0 },
4977 { "d", 0, &flag_keep_locals, 1, 0 },
4978 { "e", 0, 0, 0, 0 },
4979 { "f", 0, &flag_short_refs, 1, 0 },
4980 { "frs", 0, &flag_short_refs, 1, 0 },
4981 { "frl", 0, &flag_short_refs, 0, 1 },
4982 { "g", 0, 0, 0, 0 },
4983 { "i", 0, 0, 0, 0 },
4984 { "m", 0, 0, 0, 0 },
4985 { "mex", 0, 0, 0, 0 },
4986 { "mc", 0, 0, 0, 0 },
4987 { "md", 0, 0, 0, 0 },
4988 { "nest", opt_nest, 0, 0, 0 },
4989 { "next", skip_to_comma, 0, 0, 0 },
4990 { "o", 0, 0, 0, 0 },
4991 { "old", 0, 0, 0, 0 },
4992 { "op", skip_to_comma, 0, 0, 0 },
4993 { "pco", 0, 0, 0, 0 },
4994 { "p", opt_chip, 0, 0, 0 },
4995 { "pcr", 0, 0, 0, 0 },
4996 { "pcs", 0, 0, 0, 0 },
4997 { "r", 0, 0, 0, 0 },
4998 { "quick", 0, &m68k_quick, 1, 0 },
4999 { "rel32", 0, &m68k_rel32, 1, 0 },
5000 { "s", opt_list, 0, 0, 0 },
5001 { "t", opt_list_symbols, 0, 0, 0 },
5002 { "w", 0, &flag_no_warnings, 0, 1 },
5003 { "x", 0, 0, 0, 0 }
5004 };
5005
5006 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5007
5008 /* The MRI OPT pseudo-op. */
5009
5010 static void
5011 s_opt (ignore)
5012 int ignore;
5013 {
5014 do
5015 {
5016 int t;
5017 char *s;
5018 char c;
5019 int i;
5020 const struct opt_action *o;
5021
5022 SKIP_WHITESPACE ();
5023
5024 t = 1;
5025 if (*input_line_pointer == '-')
5026 {
5027 ++input_line_pointer;
5028 t = 0;
5029 }
5030 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5031 {
5032 input_line_pointer += 2;
5033 t = 0;
5034 }
5035
5036 s = input_line_pointer;
5037 c = get_symbol_end ();
5038
5039 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5040 {
5041 if (strcasecmp (s, o->name) == 0)
5042 {
5043 if (o->pfn)
5044 {
5045 /* Restore input_line_pointer now in case the option
5046 takes arguments. */
5047 *input_line_pointer = c;
5048 (*o->pfn) (o->arg, t);
5049 }
5050 else if (o->pvar != NULL)
5051 {
5052 if (! t && o->arg == o->notarg)
5053 as_bad ("option `%s' may not be negated", s);
5054 *input_line_pointer = c;
5055 *o->pvar = t ? o->arg : o->notarg;
5056 }
5057 else
5058 *input_line_pointer = c;
5059 break;
5060 }
5061 }
5062 if (i >= OPTCOUNT)
5063 {
5064 as_bad ("option `%s' not recognized", s);
5065 *input_line_pointer = c;
5066 }
5067 }
5068 while (*input_line_pointer++ == ',');
5069
5070 /* Move back to terminating character. */
5071 --input_line_pointer;
5072 demand_empty_rest_of_line ();
5073 }
5074
5075 /* Skip ahead to a comma. This is used for OPT options which we do
5076 not suppor tand which take arguments. */
5077
5078 static void
5079 skip_to_comma (arg, on)
5080 int arg;
5081 int on;
5082 {
5083 while (*input_line_pointer != ','
5084 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5085 ++input_line_pointer;
5086 }
5087
5088 /* Handle the OPT NEST=depth option. */
5089
5090 static void
5091 opt_nest (arg, on)
5092 int arg;
5093 int on;
5094 {
5095 if (*input_line_pointer != '=')
5096 {
5097 as_bad ("bad format of OPT NEST=depth");
5098 return;
5099 }
5100
5101 ++input_line_pointer;
5102 max_macro_nest = get_absolute_expression ();
5103 }
5104
5105 /* Handle the OPT P=chip option. */
5106
5107 static void
5108 opt_chip (arg, on)
5109 int arg;
5110 int on;
5111 {
5112 if (*input_line_pointer != '=')
5113 {
5114 /* This is just OPT P, which we do not support. */
5115 return;
5116 }
5117
5118 ++input_line_pointer;
5119 mri_chip ();
5120 }
5121
5122 /* Handle the OPT S option. */
5123
5124 static void
5125 opt_list (arg, on)
5126 int arg;
5127 int on;
5128 {
5129 listing_list (on);
5130 }
5131
5132 /* Handle the OPT T option. */
5133
5134 static void
5135 opt_list_symbols (arg, on)
5136 int arg;
5137 int on;
5138 {
5139 if (on)
5140 listing |= LISTING_SYMBOLS;
5141 else
5142 listing &=~ LISTING_SYMBOLS;
5143 }
5144
5145 /* Handle the MRI REG pseudo-op. */
5146
5147 static void
5148 s_reg (ignore)
5149 int ignore;
5150 {
5151 char *s;
5152 int c;
5153 struct m68k_op rop;
5154 unsigned long mask;
5155 char *stop = NULL;
5156 char stopc;
5157
5158 if (line_label == NULL)
5159 {
5160 as_bad ("missing label");
5161 ignore_rest_of_line ();
5162 return;
5163 }
5164
5165 if (flag_mri)
5166 stop = mri_comment_field (&stopc);
5167
5168 SKIP_WHITESPACE ();
5169
5170 s = input_line_pointer;
5171 while (isalnum ((unsigned char) *input_line_pointer)
5172 #ifdef REGISTER_PREFIX
5173 || *input_line_pointer == REGISTER_PREFIX
5174 #endif
5175 || *input_line_pointer == '/'
5176 || *input_line_pointer == '-')
5177 ++input_line_pointer;
5178 c = *input_line_pointer;
5179 *input_line_pointer = '\0';
5180
5181 if (m68k_ip_op (s, &rop) != 0)
5182 {
5183 if (rop.error == NULL)
5184 as_bad ("bad register list");
5185 else
5186 as_bad ("bad register list: %s", rop.error);
5187 *input_line_pointer = c;
5188 ignore_rest_of_line ();
5189 return;
5190 }
5191
5192 *input_line_pointer = c;
5193
5194 if (rop.mode == REGLST)
5195 mask = rop.mask;
5196 else if (rop.mode == DREG)
5197 mask = 1 << (rop.reg - DATA0);
5198 else if (rop.mode == AREG)
5199 mask = 1 << (rop.reg - ADDR0 + 8);
5200 else if (rop.mode == FPREG)
5201 mask = 1 << (rop.reg - FP0 + 16);
5202 else if (rop.mode == CONTROL
5203 && rop.reg == FPI)
5204 mask = 1 << 24;
5205 else if (rop.mode == CONTROL
5206 && rop.reg == FPS)
5207 mask = 1 << 25;
5208 else if (rop.mode == CONTROL
5209 && rop.reg == FPC)
5210 mask = 1 << 26;
5211 else
5212 {
5213 as_bad ("bad register list");
5214 ignore_rest_of_line ();
5215 return;
5216 }
5217
5218 S_SET_SEGMENT (line_label, absolute_section);
5219 S_SET_VALUE (line_label, mask);
5220 line_label->sy_frag = &zero_address_frag;
5221
5222 if (flag_mri)
5223 mri_comment_end (stop, stopc);
5224
5225 demand_empty_rest_of_line ();
5226 }
5227
5228 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5229
5230 struct save_opts
5231 {
5232 struct save_opts *next;
5233 int abspcadd;
5234 int symbols_case_sensitive;
5235 int keep_locals;
5236 int short_refs;
5237 int architecture;
5238 int quick;
5239 int rel32;
5240 int listing;
5241 int no_warnings;
5242 /* FIXME: We don't save OPT S. */
5243 };
5244
5245 /* This variable holds the stack of saved options. */
5246
5247 static struct save_opts *save_stack;
5248
5249 /* The MRI SAVE pseudo-op. */
5250
5251 static void
5252 s_save (ignore)
5253 int ignore;
5254 {
5255 struct save_opts *s;
5256
5257 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5258 s->abspcadd = m68k_abspcadd;
5259 s->symbols_case_sensitive = symbols_case_sensitive;
5260 s->keep_locals = flag_keep_locals;
5261 s->short_refs = flag_short_refs;
5262 s->architecture = current_architecture;
5263 s->quick = m68k_quick;
5264 s->rel32 = m68k_rel32;
5265 s->listing = listing;
5266 s->no_warnings = flag_no_warnings;
5267
5268 s->next = save_stack;
5269 save_stack = s;
5270
5271 demand_empty_rest_of_line ();
5272 }
5273
5274 /* The MRI RESTORE pseudo-op. */
5275
5276 static void
5277 s_restore (ignore)
5278 int ignore;
5279 {
5280 struct save_opts *s;
5281
5282 if (save_stack == NULL)
5283 {
5284 as_bad ("restore without save");
5285 ignore_rest_of_line ();
5286 return;
5287 }
5288
5289 s = save_stack;
5290 save_stack = s->next;
5291
5292 m68k_abspcadd = s->abspcadd;
5293 symbols_case_sensitive = s->symbols_case_sensitive;
5294 flag_keep_locals = s->keep_locals;
5295 flag_short_refs = s->short_refs;
5296 current_architecture = s->architecture;
5297 m68k_quick = s->quick;
5298 m68k_rel32 = s->rel32;
5299 listing = s->listing;
5300 flag_no_warnings = s->no_warnings;
5301
5302 free (s);
5303
5304 demand_empty_rest_of_line ();
5305 }
5306
5307 /* Types of MRI structured control directives. */
5308
5309 enum mri_control_type
5310 {
5311 mri_for,
5312 mri_if,
5313 mri_repeat,
5314 mri_while
5315 };
5316
5317 /* This structure is used to stack the MRI structured control
5318 directives. */
5319
5320 struct mri_control_info
5321 {
5322 /* The directive within which this one is enclosed. */
5323 struct mri_control_info *outer;
5324
5325 /* The type of directive. */
5326 enum mri_control_type type;
5327
5328 /* Whether an ELSE has been in an IF. */
5329 int else_seen;
5330
5331 /* The add or sub statement at the end of a FOR. */
5332 char *incr;
5333
5334 /* The label of the top of a FOR or REPEAT loop. */
5335 char *top;
5336
5337 /* The label to jump to for the next iteration, or the else
5338 expression of a conditional. */
5339 char *next;
5340
5341 /* The label to jump to to break out of the loop, or the label past
5342 the end of a conditional. */
5343 char *bottom;
5344 };
5345
5346 /* The stack of MRI structured control directives. */
5347
5348 static struct mri_control_info *mri_control_stack;
5349
5350 /* The current MRI structured control directive index number, used to
5351 generate label names. */
5352
5353 static int mri_control_index;
5354
5355 /* Some function prototypes. */
5356
5357 static char *mri_control_label PARAMS ((void));
5358 static struct mri_control_info *push_mri_control
5359 PARAMS ((enum mri_control_type));
5360 static void pop_mri_control PARAMS ((void));
5361 static int parse_mri_condition PARAMS ((int *));
5362 static int parse_mri_control_operand
5363 PARAMS ((int *, char **, char **, char **, char **));
5364 static int swap_mri_condition PARAMS ((int));
5365 static int reverse_mri_condition PARAMS ((int));
5366 static void build_mri_control_operand
5367 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5368 const char *, int));
5369 static void parse_mri_control_expression
5370 PARAMS ((char *, int, const char *, const char *, int));
5371
5372 /* Generate a new MRI label structured control directive label name. */
5373
5374 static char *
5375 mri_control_label ()
5376 {
5377 char *n;
5378
5379 n = (char *) xmalloc (20);
5380 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5381 ++mri_control_index;
5382 return n;
5383 }
5384
5385 /* Create a new MRI structured control directive. */
5386
5387 static struct mri_control_info *
5388 push_mri_control (type)
5389 enum mri_control_type type;
5390 {
5391 struct mri_control_info *n;
5392
5393 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5394
5395 n->type = type;
5396 n->else_seen = 0;
5397 if (type == mri_if || type == mri_while)
5398 n->top = NULL;
5399 else
5400 n->top = mri_control_label ();
5401 n->next = mri_control_label ();
5402 n->bottom = mri_control_label ();
5403
5404 n->outer = mri_control_stack;
5405 mri_control_stack = n;
5406
5407 return n;
5408 }
5409
5410 /* Pop off the stack of MRI structured control directives. */
5411
5412 static void
5413 pop_mri_control ()
5414 {
5415 struct mri_control_info *n;
5416
5417 n = mri_control_stack;
5418 mri_control_stack = n->outer;
5419 if (n->top != NULL)
5420 free (n->top);
5421 free (n->next);
5422 free (n->bottom);
5423 free (n);
5424 }
5425
5426 /* Recognize a condition code in an MRI structured control expression. */
5427
5428 static int
5429 parse_mri_condition (pcc)
5430 int *pcc;
5431 {
5432 char c1, c2;
5433
5434 know (*input_line_pointer == '<');
5435
5436 ++input_line_pointer;
5437 c1 = *input_line_pointer++;
5438 c2 = *input_line_pointer++;
5439
5440 if (*input_line_pointer != '>')
5441 {
5442 as_bad ("syntax error in structured control directive");
5443 return 0;
5444 }
5445
5446 ++input_line_pointer;
5447 SKIP_WHITESPACE ();
5448
5449 if (isupper (c1))
5450 c1 = tolower (c1);
5451 if (isupper (c2))
5452 c2 = tolower (c2);
5453
5454 *pcc = (c1 << 8) | c2;
5455
5456 return 1;
5457 }
5458
5459 /* Parse a single operand in an MRI structured control expression. */
5460
5461 static int
5462 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5463 int *pcc;
5464 char **leftstart;
5465 char **leftstop;
5466 char **rightstart;
5467 char **rightstop;
5468 {
5469 char *s;
5470
5471 SKIP_WHITESPACE ();
5472
5473 *pcc = -1;
5474 *leftstart = NULL;
5475 *leftstop = NULL;
5476 *rightstart = NULL;
5477 *rightstop = NULL;
5478
5479 if (*input_line_pointer == '<')
5480 {
5481 /* It's just a condition code. */
5482 return parse_mri_condition (pcc);
5483 }
5484
5485 /* Look ahead for the condition code. */
5486 for (s = input_line_pointer; *s != '\0'; ++s)
5487 {
5488 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5489 break;
5490 }
5491 if (*s == '\0')
5492 {
5493 as_bad ("missing condition code in structured control directive");
5494 return 0;
5495 }
5496
5497 *leftstart = input_line_pointer;
5498 *leftstop = s;
5499 if (*leftstop > *leftstart
5500 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5501 --*leftstop;
5502
5503 input_line_pointer = s;
5504 if (! parse_mri_condition (pcc))
5505 return 0;
5506
5507 /* Look ahead for AND or OR or end of line. */
5508 for (s = input_line_pointer; *s != '\0'; ++s)
5509 {
5510 if ((strncasecmp (s, "AND", 3) == 0
5511 && (s[3] == '.' || ! is_part_of_name (s[3])))
5512 || (strncasecmp (s, "OR", 2) == 0
5513 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5514 break;
5515 }
5516
5517 *rightstart = input_line_pointer;
5518 *rightstop = s;
5519 if (*rightstop > *rightstart
5520 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5521 --*rightstop;
5522
5523 input_line_pointer = s;
5524
5525 return 1;
5526 }
5527
5528 #define MCC(b1, b2) (((b1) << 8) | (b2))
5529
5530 /* Swap the sense of a condition. This changes the condition so that
5531 it generates the same result when the operands are swapped. */
5532
5533 static int
5534 swap_mri_condition (cc)
5535 int cc;
5536 {
5537 switch (cc)
5538 {
5539 case MCC ('h', 'i'): return MCC ('c', 's');
5540 case MCC ('l', 's'): return MCC ('c', 'c');
5541 case MCC ('c', 'c'): return MCC ('l', 's');
5542 case MCC ('c', 's'): return MCC ('h', 'i');
5543 case MCC ('p', 'l'): return MCC ('m', 'i');
5544 case MCC ('m', 'i'): return MCC ('p', 'l');
5545 case MCC ('g', 'e'): return MCC ('l', 'e');
5546 case MCC ('l', 't'): return MCC ('g', 't');
5547 case MCC ('g', 't'): return MCC ('l', 't');
5548 case MCC ('l', 'e'): return MCC ('g', 'e');
5549 }
5550 return cc;
5551 }
5552
5553 /* Reverse the sense of a condition. */
5554
5555 static int
5556 reverse_mri_condition (cc)
5557 int cc;
5558 {
5559 switch (cc)
5560 {
5561 case MCC ('h', 'i'): return MCC ('l', 's');
5562 case MCC ('l', 's'): return MCC ('h', 'i');
5563 case MCC ('c', 'c'): return MCC ('c', 's');
5564 case MCC ('c', 's'): return MCC ('c', 'c');
5565 case MCC ('n', 'e'): return MCC ('e', 'q');
5566 case MCC ('e', 'q'): return MCC ('n', 'e');
5567 case MCC ('v', 'c'): return MCC ('v', 's');
5568 case MCC ('v', 's'): return MCC ('v', 'c');
5569 case MCC ('p', 'l'): return MCC ('m', 'i');
5570 case MCC ('m', 'i'): return MCC ('p', 'l');
5571 case MCC ('g', 'e'): return MCC ('l', 't');
5572 case MCC ('l', 't'): return MCC ('g', 'e');
5573 case MCC ('g', 't'): return MCC ('l', 'e');
5574 case MCC ('l', 'e'): return MCC ('g', 't');
5575 }
5576 return cc;
5577 }
5578
5579 /* Build an MRI structured control expression. This generates test
5580 and branch instructions. It goes to TRUELAB if the condition is
5581 true, and to FALSELAB if the condition is false. Exactly one of
5582 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5583 is the size qualifier for the expression. EXTENT is the size to
5584 use for the branch. */
5585
5586 static void
5587 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5588 rightstop, truelab, falselab, extent)
5589 int qual;
5590 int cc;
5591 char *leftstart;
5592 char *leftstop;
5593 char *rightstart;
5594 char *rightstop;
5595 const char *truelab;
5596 const char *falselab;
5597 int extent;
5598 {
5599 char *buf;
5600 char *s;
5601
5602 if (leftstart != NULL)
5603 {
5604 struct m68k_op leftop, rightop;
5605 char c;
5606
5607 /* Swap the compare operands, if necessary, to produce a legal
5608 m68k compare instruction. Comparing a register operand with
5609 a non-register operand requires the register to be on the
5610 right (cmp, cmpa). Comparing an immediate value with
5611 anything requires the immediate value to be on the left
5612 (cmpi). */
5613
5614 c = *leftstop;
5615 *leftstop = '\0';
5616 (void) m68k_ip_op (leftstart, &leftop);
5617 *leftstop = c;
5618
5619 c = *rightstop;
5620 *rightstop = '\0';
5621 (void) m68k_ip_op (rightstart, &rightop);
5622 *rightstop = c;
5623
5624 if (rightop.mode == IMMED
5625 || ((leftop.mode == DREG || leftop.mode == AREG)
5626 && (rightop.mode != DREG && rightop.mode != AREG)))
5627 {
5628 char *temp;
5629
5630 cc = swap_mri_condition (cc);
5631 temp = leftstart;
5632 leftstart = rightstart;
5633 rightstart = temp;
5634 temp = leftstop;
5635 leftstop = rightstop;
5636 rightstop = temp;
5637 }
5638 }
5639
5640 if (truelab == NULL)
5641 {
5642 cc = reverse_mri_condition (cc);
5643 truelab = falselab;
5644 }
5645
5646 if (leftstart != NULL)
5647 {
5648 buf = (char *) xmalloc (20
5649 + (leftstop - leftstart)
5650 + (rightstop - rightstart));
5651 s = buf;
5652 *s++ = 'c';
5653 *s++ = 'm';
5654 *s++ = 'p';
5655 if (qual != '\0')
5656 *s++ = qual;
5657 *s++ = ' ';
5658 memcpy (s, leftstart, leftstop - leftstart);
5659 s += leftstop - leftstart;
5660 *s++ = ',';
5661 memcpy (s, rightstart, rightstop - rightstart);
5662 s += rightstop - rightstart;
5663 *s = '\0';
5664 md_assemble (buf);
5665 free (buf);
5666 }
5667
5668 buf = (char *) xmalloc (20 + strlen (truelab));
5669 s = buf;
5670 *s++ = 'b';
5671 *s++ = cc >> 8;
5672 *s++ = cc & 0xff;
5673 if (extent != '\0')
5674 *s++ = extent;
5675 *s++ = ' ';
5676 strcpy (s, truelab);
5677 md_assemble (buf);
5678 free (buf);
5679 }
5680
5681 /* Parse an MRI structured control expression. This generates test
5682 and branch instructions. STOP is where the expression ends. It
5683 goes to TRUELAB if the condition is true, and to FALSELAB if the
5684 condition is false. Exactly one of TRUELAB and FALSELAB will be
5685 NULL, meaning to fall through. QUAL is the size qualifier for the
5686 expression. EXTENT is the size to use for the branch. */
5687
5688 static void
5689 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5690 char *stop;
5691 int qual;
5692 const char *truelab;
5693 const char *falselab;
5694 int extent;
5695 {
5696 int c;
5697 int cc;
5698 char *leftstart;
5699 char *leftstop;
5700 char *rightstart;
5701 char *rightstop;
5702
5703 c = *stop;
5704 *stop = '\0';
5705
5706 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5707 &rightstart, &rightstop))
5708 {
5709 *stop = c;
5710 return;
5711 }
5712
5713 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5714 {
5715 const char *flab;
5716
5717 if (falselab != NULL)
5718 flab = falselab;
5719 else
5720 flab = mri_control_label ();
5721
5722 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5723 rightstop, (const char *) NULL, flab, extent);
5724
5725 input_line_pointer += 3;
5726 if (*input_line_pointer != '.'
5727 || input_line_pointer[1] == '\0')
5728 qual = '\0';
5729 else
5730 {
5731 qual = input_line_pointer[1];
5732 input_line_pointer += 2;
5733 }
5734
5735 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5736 &rightstart, &rightstop))
5737 {
5738 *stop = c;
5739 return;
5740 }
5741
5742 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5743 rightstop, truelab, falselab, extent);
5744
5745 if (falselab == NULL)
5746 colon (flab);
5747 }
5748 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5749 {
5750 const char *tlab;
5751
5752 if (truelab != NULL)
5753 tlab = truelab;
5754 else
5755 tlab = mri_control_label ();
5756
5757 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5758 rightstop, tlab, (const char *) NULL, extent);
5759
5760 input_line_pointer += 2;
5761 if (*input_line_pointer != '.'
5762 || input_line_pointer[1] == '\0')
5763 qual = '\0';
5764 else
5765 {
5766 qual = input_line_pointer[1];
5767 input_line_pointer += 2;
5768 }
5769
5770 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5771 &rightstart, &rightstop))
5772 {
5773 *stop = c;
5774 return;
5775 }
5776
5777 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5778 rightstop, truelab, falselab, extent);
5779
5780 if (truelab == NULL)
5781 colon (tlab);
5782 }
5783 else
5784 {
5785 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5786 rightstop, truelab, falselab, extent);
5787 }
5788
5789 *stop = c;
5790 if (input_line_pointer != stop)
5791 as_bad ("syntax error in structured control directive");
5792 }
5793
5794 /* Handle the MRI IF pseudo-op. This may be a structured control
5795 directive, or it may be a regular assembler conditional, depending
5796 on its operands. */
5797
5798 static void
5799 s_mri_if (qual)
5800 int qual;
5801 {
5802 char *s;
5803 int c;
5804 struct mri_control_info *n;
5805
5806 /* A structured control directive must end with THEN with an
5807 optional qualifier. */
5808 s = input_line_pointer;
5809 while (! is_end_of_line[(unsigned char) *s]
5810 && (! flag_mri || *s != '*'))
5811 ++s;
5812 --s;
5813 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5814 --s;
5815
5816 if (s - input_line_pointer > 1
5817 && s[-1] == '.')
5818 s -= 2;
5819
5820 if (s - input_line_pointer < 3
5821 || strncasecmp (s - 3, "THEN", 4) != 0)
5822 {
5823 if (qual != '\0')
5824 {
5825 as_bad ("missing then");
5826 ignore_rest_of_line ();
5827 return;
5828 }
5829
5830 /* It's a conditional. */
5831 s_if (O_ne);
5832 return;
5833 }
5834
5835 /* Since this might be a conditional if, this pseudo-op will be
5836 called even if we are supported to be ignoring input. Double
5837 check now. Clobber *input_line_pointer so that ignore_input
5838 thinks that this is not a special pseudo-op. */
5839 c = *input_line_pointer;
5840 *input_line_pointer = 0;
5841 if (ignore_input ())
5842 {
5843 *input_line_pointer = c;
5844 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5845 ++input_line_pointer;
5846 demand_empty_rest_of_line ();
5847 return;
5848 }
5849 *input_line_pointer = c;
5850
5851 n = push_mri_control (mri_if);
5852
5853 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5854 n->next, s[1] == '.' ? s[2] : '\0');
5855
5856 if (s[1] == '.')
5857 input_line_pointer = s + 3;
5858 else
5859 input_line_pointer = s + 1;
5860
5861 if (flag_mri)
5862 {
5863 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5864 ++input_line_pointer;
5865 }
5866
5867 demand_empty_rest_of_line ();
5868 }
5869
5870 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5871 structured IF, associate the ELSE with the IF. Otherwise, assume
5872 it is a conditional else. */
5873
5874 static void
5875 s_mri_else (qual)
5876 int qual;
5877 {
5878 int c;
5879 char *buf;
5880 char q[2];
5881
5882 if (qual == '\0'
5883 && (mri_control_stack == NULL
5884 || mri_control_stack->type != mri_if
5885 || mri_control_stack->else_seen))
5886 {
5887 s_else (0);
5888 return;
5889 }
5890
5891 c = *input_line_pointer;
5892 *input_line_pointer = 0;
5893 if (ignore_input ())
5894 {
5895 *input_line_pointer = c;
5896 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5897 ++input_line_pointer;
5898 demand_empty_rest_of_line ();
5899 return;
5900 }
5901 *input_line_pointer = c;
5902
5903 if (mri_control_stack == NULL
5904 || mri_control_stack->type != mri_if
5905 || mri_control_stack->else_seen)
5906 {
5907 as_bad ("else without matching if");
5908 ignore_rest_of_line ();
5909 return;
5910 }
5911
5912 mri_control_stack->else_seen = 1;
5913
5914 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5915 q[0] = qual;
5916 q[1] = '\0';
5917 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5918 md_assemble (buf);
5919 free (buf);
5920
5921 colon (mri_control_stack->next);
5922
5923 if (flag_mri)
5924 {
5925 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5926 ++input_line_pointer;
5927 }
5928
5929 demand_empty_rest_of_line ();
5930 }
5931
5932 /* Handle the MRI ENDI pseudo-op. */
5933
5934 static void
5935 s_mri_endi (ignore)
5936 int ignore;
5937 {
5938 if (mri_control_stack == NULL
5939 || mri_control_stack->type != mri_if)
5940 {
5941 as_bad ("endi without matching if");
5942 ignore_rest_of_line ();
5943 return;
5944 }
5945
5946 /* ignore_input will not return true for ENDI, so we don't need to
5947 worry about checking it again here. */
5948
5949 if (! mri_control_stack->else_seen)
5950 colon (mri_control_stack->next);
5951 colon (mri_control_stack->bottom);
5952
5953 pop_mri_control ();
5954
5955 if (flag_mri)
5956 {
5957 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5958 ++input_line_pointer;
5959 }
5960
5961 demand_empty_rest_of_line ();
5962 }
5963
5964 /* Handle the MRI BREAK pseudo-op. */
5965
5966 static void
5967 s_mri_break (extent)
5968 int extent;
5969 {
5970 struct mri_control_info *n;
5971 char *buf;
5972 char ex[2];
5973
5974 n = mri_control_stack;
5975 while (n != NULL
5976 && n->type != mri_for
5977 && n->type != mri_repeat
5978 && n->type != mri_while)
5979 n = n->outer;
5980 if (n == NULL)
5981 {
5982 as_bad ("break outside of structured loop");
5983 ignore_rest_of_line ();
5984 return;
5985 }
5986
5987 buf = (char *) xmalloc (20 + strlen (n->bottom));
5988 ex[0] = extent;
5989 ex[1] = '\0';
5990 sprintf (buf, "bra%s %s", ex, n->bottom);
5991 md_assemble (buf);
5992 free (buf);
5993
5994 if (flag_mri)
5995 {
5996 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5997 ++input_line_pointer;
5998 }
5999
6000 demand_empty_rest_of_line ();
6001 }
6002
6003 /* Handle the MRI NEXT pseudo-op. */
6004
6005 static void
6006 s_mri_next (extent)
6007 int extent;
6008 {
6009 struct mri_control_info *n;
6010 char *buf;
6011 char ex[2];
6012
6013 n = mri_control_stack;
6014 while (n != NULL
6015 && n->type != mri_for
6016 && n->type != mri_repeat
6017 && n->type != mri_while)
6018 n = n->outer;
6019 if (n == NULL)
6020 {
6021 as_bad ("next outside of structured loop");
6022 ignore_rest_of_line ();
6023 return;
6024 }
6025
6026 buf = (char *) xmalloc (20 + strlen (n->next));
6027 ex[0] = extent;
6028 ex[1] = '\0';
6029 sprintf (buf, "bra%s %s", ex, n->next);
6030 md_assemble (buf);
6031 free (buf);
6032
6033 if (flag_mri)
6034 {
6035 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6036 ++input_line_pointer;
6037 }
6038
6039 demand_empty_rest_of_line ();
6040 }
6041
6042 /* Handle the MRI FOR pseudo-op. */
6043
6044 static void
6045 s_mri_for (qual)
6046 int qual;
6047 {
6048 const char *varstart, *varstop;
6049 const char *initstart, *initstop;
6050 const char *endstart, *endstop;
6051 const char *bystart, *bystop;
6052 int up;
6053 int by;
6054 int extent;
6055 struct mri_control_info *n;
6056 char *buf;
6057 char *s;
6058 char ex[2];
6059
6060 /* The syntax is
6061 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6062 */
6063
6064 SKIP_WHITESPACE ();
6065 varstart = input_line_pointer;
6066
6067 /* Look for the '='. */
6068 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6069 && *input_line_pointer != '=')
6070 ++input_line_pointer;
6071 if (*input_line_pointer != '=')
6072 {
6073 as_bad ("missing =");
6074 ignore_rest_of_line ();
6075 return;
6076 }
6077
6078 varstop = input_line_pointer;
6079 if (varstop > varstart
6080 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6081 --varstop;
6082
6083 ++input_line_pointer;
6084
6085 initstart = input_line_pointer;
6086
6087 /* Look for TO or DOWNTO. */
6088 up = 1;
6089 initstop = NULL;
6090 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6091 {
6092 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6093 && ! is_part_of_name (input_line_pointer[2]))
6094 {
6095 initstop = input_line_pointer;
6096 input_line_pointer += 2;
6097 break;
6098 }
6099 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6100 && ! is_part_of_name (input_line_pointer[6]))
6101 {
6102 initstop = input_line_pointer;
6103 up = 0;
6104 input_line_pointer += 6;
6105 break;
6106 }
6107 ++input_line_pointer;
6108 }
6109 if (initstop == NULL)
6110 {
6111 as_bad ("missing to or downto");
6112 ignore_rest_of_line ();
6113 return;
6114 }
6115 if (initstop > initstart
6116 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6117 --initstop;
6118
6119 SKIP_WHITESPACE ();
6120 endstart = input_line_pointer;
6121
6122 /* Look for BY or DO. */
6123 by = 0;
6124 endstop = NULL;
6125 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6126 {
6127 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6128 && ! is_part_of_name (input_line_pointer[2]))
6129 {
6130 endstop = input_line_pointer;
6131 by = 1;
6132 input_line_pointer += 2;
6133 break;
6134 }
6135 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6136 && (input_line_pointer[2] == '.'
6137 || ! is_part_of_name (input_line_pointer[2])))
6138 {
6139 endstop = input_line_pointer;
6140 input_line_pointer += 2;
6141 break;
6142 }
6143 ++input_line_pointer;
6144 }
6145 if (endstop == NULL)
6146 {
6147 as_bad ("missing do");
6148 ignore_rest_of_line ();
6149 return;
6150 }
6151 if (endstop > endstart
6152 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6153 --endstop;
6154
6155 if (! by)
6156 {
6157 bystart = "#1";
6158 bystop = bystart + 2;
6159 }
6160 else
6161 {
6162 SKIP_WHITESPACE ();
6163 bystart = input_line_pointer;
6164
6165 /* Look for DO. */
6166 bystop = NULL;
6167 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6168 {
6169 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6170 && (input_line_pointer[2] == '.'
6171 || ! is_part_of_name (input_line_pointer[2])))
6172 {
6173 bystop = input_line_pointer;
6174 input_line_pointer += 2;
6175 break;
6176 }
6177 ++input_line_pointer;
6178 }
6179 if (bystop == NULL)
6180 {
6181 as_bad ("missing do");
6182 ignore_rest_of_line ();
6183 return;
6184 }
6185 if (bystop > bystart
6186 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6187 --bystop;
6188 }
6189
6190 if (*input_line_pointer != '.')
6191 extent = '\0';
6192 else
6193 {
6194 extent = input_line_pointer[1];
6195 input_line_pointer += 2;
6196 }
6197
6198 /* We have fully parsed the FOR operands. Now build the loop. */
6199
6200 n = push_mri_control (mri_for);
6201
6202 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6203
6204 /* move init,var */
6205 s = buf;
6206 *s++ = 'm';
6207 *s++ = 'o';
6208 *s++ = 'v';
6209 *s++ = 'e';
6210 if (qual != '\0')
6211 *s++ = qual;
6212 *s++ = ' ';
6213 memcpy (s, initstart, initstop - initstart);
6214 s += initstop - initstart;
6215 *s++ = ',';
6216 memcpy (s, varstart, varstop - varstart);
6217 s += varstop - varstart;
6218 *s = '\0';
6219 md_assemble (buf);
6220
6221 colon (n->top);
6222
6223 /* cmp end,var */
6224 s = buf;
6225 *s++ = 'c';
6226 *s++ = 'm';
6227 *s++ = 'p';
6228 if (qual != '\0')
6229 *s++ = qual;
6230 *s++ = ' ';
6231 memcpy (s, endstart, endstop - endstart);
6232 s += endstop - endstart;
6233 *s++ = ',';
6234 memcpy (s, varstart, varstop - varstart);
6235 s += varstop - varstart;
6236 *s = '\0';
6237 md_assemble (buf);
6238
6239 /* bcc bottom */
6240 ex[0] = extent;
6241 ex[1] = '\0';
6242 if (up)
6243 sprintf (buf, "blt%s %s", ex, n->bottom);
6244 else
6245 sprintf (buf, "bgt%s %s", ex, n->bottom);
6246 md_assemble (buf);
6247
6248 /* Put together the add or sub instruction used by ENDF. */
6249 s = buf;
6250 if (up)
6251 strcpy (s, "add");
6252 else
6253 strcpy (s, "sub");
6254 s += 3;
6255 if (qual != '\0')
6256 *s++ = qual;
6257 *s++ = ' ';
6258 memcpy (s, bystart, bystop - bystart);
6259 s += bystop - bystart;
6260 *s++ = ',';
6261 memcpy (s, varstart, varstop - varstart);
6262 s += varstop - varstart;
6263 *s = '\0';
6264 n->incr = buf;
6265
6266 if (flag_mri)
6267 {
6268 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6269 ++input_line_pointer;
6270 }
6271
6272 demand_empty_rest_of_line ();
6273 }
6274
6275 /* Handle the MRI ENDF pseudo-op. */
6276
6277 static void
6278 s_mri_endf (ignore)
6279 int ignore;
6280 {
6281 if (mri_control_stack == NULL
6282 || mri_control_stack->type != mri_for)
6283 {
6284 as_bad ("endf without for");
6285 ignore_rest_of_line ();
6286 return;
6287 }
6288
6289 colon (mri_control_stack->next);
6290
6291 md_assemble (mri_control_stack->incr);
6292
6293 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6294 md_assemble (mri_control_stack->incr);
6295
6296 free (mri_control_stack->incr);
6297
6298 colon (mri_control_stack->bottom);
6299
6300 pop_mri_control ();
6301
6302 if (flag_mri)
6303 {
6304 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6305 ++input_line_pointer;
6306 }
6307
6308 demand_empty_rest_of_line ();
6309 }
6310
6311 /* Handle the MRI REPEAT pseudo-op. */
6312
6313 static void
6314 s_mri_repeat (ignore)
6315 int ignore;
6316 {
6317 struct mri_control_info *n;
6318
6319 n = push_mri_control (mri_repeat);
6320 colon (n->top);
6321 if (flag_mri)
6322 {
6323 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6324 ++input_line_pointer;
6325 }
6326 demand_empty_rest_of_line ();
6327 }
6328
6329 /* Handle the MRI UNTIL pseudo-op. */
6330
6331 static void
6332 s_mri_until (qual)
6333 int qual;
6334 {
6335 char *s;
6336
6337 if (mri_control_stack == NULL
6338 || mri_control_stack->type != mri_repeat)
6339 {
6340 as_bad ("until without repeat");
6341 ignore_rest_of_line ();
6342 return;
6343 }
6344
6345 colon (mri_control_stack->next);
6346
6347 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6348 ;
6349
6350 parse_mri_control_expression (s, qual, (const char *) NULL,
6351 mri_control_stack->top, '\0');
6352
6353 colon (mri_control_stack->bottom);
6354
6355 input_line_pointer = s;
6356
6357 pop_mri_control ();
6358
6359 if (flag_mri)
6360 {
6361 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6362 ++input_line_pointer;
6363 }
6364
6365 demand_empty_rest_of_line ();
6366 }
6367
6368 /* Handle the MRI WHILE pseudo-op. */
6369
6370 static void
6371 s_mri_while (qual)
6372 int qual;
6373 {
6374 char *s;
6375
6376 struct mri_control_info *n;
6377
6378 s = input_line_pointer;
6379 while (! is_end_of_line[(unsigned char) *s]
6380 && (! flag_mri || *s != '*'))
6381 s++;
6382 --s;
6383 while (*s == ' ' || *s == '\t')
6384 --s;
6385 if (s - input_line_pointer > 1
6386 && s[-1] == '.')
6387 s -= 2;
6388 if (s - input_line_pointer < 2
6389 || strncasecmp (s - 1, "DO", 2) != 0)
6390 {
6391 as_bad ("missing do");
6392 ignore_rest_of_line ();
6393 return;
6394 }
6395
6396 n = push_mri_control (mri_while);
6397
6398 colon (n->next);
6399
6400 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6401 s[1] == '.' ? s[2] : '\0');
6402
6403 input_line_pointer = s + 1;
6404 if (*input_line_pointer == '.')
6405 input_line_pointer += 2;
6406
6407 if (flag_mri)
6408 {
6409 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6410 ++input_line_pointer;
6411 }
6412
6413 demand_empty_rest_of_line ();
6414 }
6415
6416 /* Handle the MRI ENDW pseudo-op. */
6417
6418 static void
6419 s_mri_endw (ignore)
6420 int ignore;
6421 {
6422 char *buf;
6423
6424 if (mri_control_stack == NULL
6425 || mri_control_stack->type != mri_while)
6426 {
6427 as_bad ("endw without while");
6428 ignore_rest_of_line ();
6429 return;
6430 }
6431
6432 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6433 sprintf (buf, "bra %s", mri_control_stack->next);
6434 md_assemble (buf);
6435 free (buf);
6436
6437 colon (mri_control_stack->bottom);
6438
6439 pop_mri_control ();
6440
6441 if (flag_mri)
6442 {
6443 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6444 ++input_line_pointer;
6445 }
6446
6447 demand_empty_rest_of_line ();
6448 }
6449 \f
6450 /*
6451 * md_parse_option
6452 * Invocation line includes a switch not recognized by the base assembler.
6453 * See if it's a processor-specific option. These are:
6454 *
6455 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6456 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6457 * Select the architecture. Instructions or features not
6458 * supported by the selected architecture cause fatal
6459 * errors. More than one may be specified. The default is
6460 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6461 * for -m68000, and -m68882 is a synonym for -m68881.
6462 * -[A]m[c]no-68851, -[A]m[c]no-68881
6463 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6464 * so don't use or document it, but that's the way the parsing
6465 * works).
6466 *
6467 * -pic Indicates PIC.
6468 * -k Indicates PIC. (Sun 3 only.)
6469 *
6470 * --bitwise-or
6471 * Permit `|' to be used in expressions.
6472 *
6473 */
6474
6475 #ifdef OBJ_ELF
6476 CONST char *md_shortopts = "lSA:m:kQ:V";
6477 #else
6478 CONST char *md_shortopts = "lSA:m:k";
6479 #endif
6480
6481 struct option md_longopts[] = {
6482 #define OPTION_PIC (OPTION_MD_BASE)
6483 {"pic", no_argument, NULL, OPTION_PIC},
6484 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6485 {"register-prefix-optional", no_argument, NULL,
6486 OPTION_REGISTER_PREFIX_OPTIONAL},
6487 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6488 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6489 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6490 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6491 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6492 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6493 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6494 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6495 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6496 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6497 {NULL, no_argument, NULL, 0}
6498 };
6499 size_t md_longopts_size = sizeof(md_longopts);
6500
6501 int
6502 md_parse_option (c, arg)
6503 int c;
6504 char *arg;
6505 {
6506 switch (c)
6507 {
6508 case 'l': /* -l means keep external to 2 bit offset
6509 rather than 16 bit one */
6510 flag_short_refs = 1;
6511 break;
6512
6513 case 'S': /* -S means that jbsr's always turn into
6514 jsr's. */
6515 flag_long_jumps = 1;
6516 break;
6517
6518 case 'A':
6519 if (*arg == 'm')
6520 arg++;
6521 /* intentional fall-through */
6522 case 'm':
6523
6524 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6525 {
6526 int i;
6527 unsigned long arch;
6528 const char *oarg = arg;
6529
6530 arg += 3;
6531 if (*arg == 'm')
6532 {
6533 arg++;
6534 if (arg[0] == 'c' && arg[1] == '6')
6535 arg++;
6536 }
6537 for (i = 0; i < n_archs; i++)
6538 if (!strcmp (arg, archs[i].name))
6539 break;
6540 if (i == n_archs)
6541 {
6542 unknown:
6543 as_bad ("unrecognized option `%s'", oarg);
6544 return 0;
6545 }
6546 arch = archs[i].arch;
6547 if (arch == m68881)
6548 no_68881 = 1;
6549 else if (arch == m68851)
6550 no_68851 = 1;
6551 else
6552 goto unknown;
6553 }
6554 else
6555 {
6556 int i;
6557
6558 if (arg[0] == 'c' && arg[1] == '6')
6559 arg++;
6560
6561 for (i = 0; i < n_archs; i++)
6562 if (!strcmp (arg, archs[i].name))
6563 {
6564 unsigned long arch = archs[i].arch;
6565 if (cpu_of_arch (arch))
6566 /* It's a cpu spec. */
6567 {
6568 current_architecture &= ~m68000up;
6569 current_architecture |= arch;
6570 }
6571 else if (arch == m68881)
6572 {
6573 current_architecture |= m68881;
6574 no_68881 = 0;
6575 }
6576 else if (arch == m68851)
6577 {
6578 current_architecture |= m68851;
6579 no_68851 = 0;
6580 }
6581 else
6582 /* ??? */
6583 abort ();
6584 break;
6585 }
6586 if (i == n_archs)
6587 {
6588 as_bad ("unrecognized architecture specification `%s'", arg);
6589 return 0;
6590 }
6591 }
6592 break;
6593
6594 case OPTION_PIC:
6595 case 'k':
6596 flag_want_pic = 1;
6597 break; /* -pic, Position Independent Code */
6598
6599 case OPTION_REGISTER_PREFIX_OPTIONAL:
6600 flag_reg_prefix_optional = 1;
6601 reg_prefix_optional_seen = 1;
6602 break;
6603
6604 /* -V: SVR4 argument to print version ID. */
6605 case 'V':
6606 print_version_id ();
6607 break;
6608
6609 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6610 should be emitted or not. FIXME: Not implemented. */
6611 case 'Q':
6612 break;
6613
6614 case OPTION_BITWISE_OR:
6615 {
6616 char *n, *t;
6617 const char *s;
6618
6619 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6620 t = n;
6621 for (s = m68k_comment_chars; *s != '\0'; s++)
6622 if (*s != '|')
6623 *t++ = *s;
6624 *t = '\0';
6625 m68k_comment_chars = n;
6626 }
6627 break;
6628
6629 case OPTION_BASE_SIZE_DEFAULT_16:
6630 m68k_index_width_default = SIZE_WORD;
6631 break;
6632
6633 case OPTION_BASE_SIZE_DEFAULT_32:
6634 m68k_index_width_default = SIZE_LONG;
6635 break;
6636
6637 case OPTION_DISP_SIZE_DEFAULT_16:
6638 m68k_rel32 = 0;
6639 m68k_rel32_from_cmdline = 1;
6640 break;
6641
6642 case OPTION_DISP_SIZE_DEFAULT_32:
6643 m68k_rel32 = 1;
6644 m68k_rel32_from_cmdline = 1;
6645 break;
6646
6647 default:
6648 return 0;
6649 }
6650
6651 return 1;
6652 }
6653
6654 void
6655 md_show_usage (stream)
6656 FILE *stream;
6657 {
6658 fprintf(stream, "\
6659 680X0 options:\n\
6660 -l use 1 word for refs to undefined symbols [default 2]\n\
6661 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6662 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6663 | -mcpu32 | -m5200\n\
6664 specify variant of 680X0 architecture [default 68020]\n\
6665 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6666 target has/lacks floating-point coprocessor\n\
6667 [default yes for 68020, 68030, and cpu32]\n");
6668 fprintf(stream, "\
6669 -m68851 | -mno-68851\n\
6670 target has/lacks memory-management unit coprocessor\n\
6671 [default yes for 68020 and up]\n\
6672 -pic, -k generate position independent code\n\
6673 -S turn jbsr into jsr\n\
6674 --register-prefix-optional\n\
6675 recognize register names without prefix character\n\
6676 --bitwise-or do not treat `|' as a comment character\n");
6677 fprintf (stream, "\
6678 --base-size-default-16 base reg without size is 16 bits\n\
6679 --base-size-default-32 base reg without size is 32 bits (default)\n\
6680 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6681 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n");
6682 }
6683 \f
6684 #ifdef TEST2
6685
6686 /* TEST2: Test md_assemble() */
6687 /* Warning, this routine probably doesn't work anymore */
6688
6689 main ()
6690 {
6691 struct m68k_it the_ins;
6692 char buf[120];
6693 char *cp;
6694 int n;
6695
6696 m68k_ip_begin ();
6697 for (;;)
6698 {
6699 if (!gets (buf) || !*buf)
6700 break;
6701 if (buf[0] == '|' || buf[1] == '.')
6702 continue;
6703 for (cp = buf; *cp; cp++)
6704 if (*cp == '\t')
6705 *cp = ' ';
6706 if (is_label (buf))
6707 continue;
6708 memset (&the_ins, '\0', sizeof (the_ins));
6709 m68k_ip (&the_ins, buf);
6710 if (the_ins.error)
6711 {
6712 printf ("Error %s in %s\n", the_ins.error, buf);
6713 }
6714 else
6715 {
6716 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6717 for (n = 0; n < the_ins.numo; n++)
6718 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6719 printf (" ");
6720 print_the_insn (&the_ins.opcode[0], stdout);
6721 (void) putchar ('\n');
6722 }
6723 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6724 {
6725 if (the_ins.operands[n].error)
6726 {
6727 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6728 continue;
6729 }
6730 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6731 if (the_ins.operands[n].b_const)
6732 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6733 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6734 if (the_ins.operands[n].b_iadd)
6735 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6736 (void) putchar ('\n');
6737 }
6738 }
6739 m68k_ip_end ();
6740 return 0;
6741 }
6742
6743 is_label (str)
6744 char *str;
6745 {
6746 while (*str == ' ')
6747 str++;
6748 while (*str && *str != ' ')
6749 str++;
6750 if (str[-1] == ':' || str[1] == '=')
6751 return 1;
6752 return 0;
6753 }
6754
6755 #endif
6756
6757 /* Possible states for relaxation:
6758
6759 0 0 branch offset byte (bra, etc)
6760 0 1 word
6761 0 2 long
6762
6763 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6764 1 1 word
6765 1 2 long
6766
6767 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6768 2 1 word-long
6769 2 2 long-word
6770 2 3 long-long
6771
6772 */
6773
6774 /* We have no need to default values of symbols. */
6775
6776 /* ARGSUSED */
6777 symbolS *
6778 md_undefined_symbol (name)
6779 char *name;
6780 {
6781 return 0;
6782 }
6783
6784 /* Round up a section size to the appropriate boundary. */
6785 valueT
6786 md_section_align (segment, size)
6787 segT segment;
6788 valueT size;
6789 {
6790 return size; /* Byte alignment is fine */
6791 }
6792
6793 /* Exactly what point is a PC-relative offset relative TO?
6794 On the 68k, it is relative to the address of the first extension
6795 word. The difference between the addresses of the offset and the
6796 first extension word is stored in fx_pcrel_adjust. */
6797 long
6798 md_pcrel_from (fixP)
6799 fixS *fixP;
6800 {
6801 int adjust;
6802
6803 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6804 -1 as 64. */
6805 adjust = fixP->fx_pcrel_adjust;
6806 if (adjust == 64)
6807 adjust = -1;
6808 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6809 }
6810
6811 #ifndef BFD_ASSEMBLER
6812 /*ARGSUSED*/
6813 void
6814 tc_coff_symbol_emit_hook (ignore)
6815 symbolS *ignore;
6816 {
6817 }
6818
6819 int
6820 tc_coff_sizemachdep (frag)
6821 fragS *frag;
6822 {
6823 switch (frag->fr_subtype & 0x3)
6824 {
6825 case BYTE:
6826 return 1;
6827 case SHORT:
6828 return 2;
6829 case LONG:
6830 return 4;
6831 default:
6832 abort ();
6833 return 0;
6834 }
6835 }
6836 #endif
6837
6838 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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