1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 #include "safe-ctype.h"
25 #include "dwarf2dbg.h"
26 #include "dw2gencfi.h"
28 #include "opcode/m68k.h"
29 #include "m68k-parse.h"
40 static void m68k_elf_cons (int);
43 /* This string holds the chars that always start a comment. If the
44 pre-processor is disabled, these aren't very useful. The macro
45 tc_comment_chars points to this. We use this, rather than the
46 usual comment_chars, so that the --bitwise-or option will work. */
47 #if defined (TE_SVR4) || defined (TE_DELTA)
48 const char *m68k_comment_chars
= "|#";
50 const char *m68k_comment_chars
= "|";
53 /* This array holds the chars that only start a comment at the beginning of
54 a line. If the line seems to have the form '# 123 filename'
55 .line and .file directives will appear in the pre-processed output */
56 /* Note that input_file.c hand checks for '#' at the beginning of the
57 first line of the input file. This is because the compiler outputs
58 #NO_APP at the beginning of its output. */
59 /* Also note that comments like this one will always work. */
60 const char line_comment_chars
[] = "#*";
62 const char line_separator_chars
[] = ";";
64 /* Chars that can be used to separate mant from exp in floating point nums. */
65 const char EXP_CHARS
[] = "eE";
67 /* Chars that mean this number is a floating point constant, as
68 in "0f12.456" or "0d1.2345e12". */
70 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
72 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
73 changed in read.c . Ideally it shouldn't have to know about it at all,
74 but nothing is ideal around here. */
76 /* Are we trying to generate PIC code? If so, absolute references
77 ought to be made into linkage table references or pc-relative
78 references. Not implemented. For ELF there are other means
79 to denote pic relocations. */
82 static int flag_short_refs
; /* -l option. */
83 static int flag_long_jumps
; /* -S option. */
84 static int flag_keep_pcrel
; /* --pcrel option. */
86 #ifdef REGISTER_PREFIX_OPTIONAL
87 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
89 int flag_reg_prefix_optional
;
92 /* Whether --register-prefix-optional was used on the command line. */
93 static int reg_prefix_optional_seen
;
95 /* The floating point coprocessor to use by default. */
96 static enum m68k_register m68k_float_copnum
= COP1
;
98 /* If this is non-zero, then references to number(%pc) will be taken
99 to refer to number, rather than to %pc + number. */
100 static int m68k_abspcadd
;
102 /* If this is non-zero, then the quick forms of the move, add, and sub
103 instructions are used when possible. */
104 static int m68k_quick
= 1;
106 /* If this is non-zero, then if the size is not specified for a base
107 or outer displacement, the assembler assumes that the size should
109 static int m68k_rel32
= 1;
111 /* This is non-zero if m68k_rel32 was set from the command line. */
112 static int m68k_rel32_from_cmdline
;
114 /* The default width to use for an index register when using a base
116 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
118 /* We want to warn if any text labels are misaligned. In order to get
119 the right line number, we need to record the line number for each
123 struct label_line
*next
;
130 /* The list of labels. */
132 static struct label_line
*labels
;
134 /* The current label. */
136 static struct label_line
*current_label
;
138 /* Pointer to list holding the opcodes sorted by name. */
139 static struct m68k_opcode
const ** m68k_sorted_opcodes
;
141 /* Its an arbitrary name: This means I don't approve of it.
143 static struct obstack robyn
;
147 const char *m_operands
;
148 unsigned long m_opcode
;
152 struct m68k_incant
*m_next
;
155 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
156 #define gettwo(x) (((x)->m_opcode)&0xffff)
158 static const enum m68k_register m68000_ctrl
[] = { 0 };
159 static const enum m68k_register m68010_ctrl
[] = {
163 static const enum m68k_register m68020_ctrl
[] = {
164 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
167 static const enum m68k_register m68040_ctrl
[] = {
168 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
169 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
172 static const enum m68k_register m68060_ctrl
[] = {
173 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
174 USP
, VBR
, URP
, SRP
, PCR
,
177 static const enum m68k_register mcf_ctrl
[] = {
178 CACR
, TC
, ACR0
, ACR1
, ACR2
, ACR3
, VBR
, ROMBAR
,
179 RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
,
182 static const enum m68k_register mcf51_ctrl
[] = {
186 static const enum m68k_register mcf5206_ctrl
[] = {
187 CACR
, ACR0
, ACR1
, VBR
, RAMBAR0
, RAMBAR_ALT
, MBAR
,
190 static const enum m68k_register mcf5208_ctrl
[] = {
191 CACR
, ACR0
, ACR1
, VBR
, RAMBAR
, RAMBAR1
,
194 static const enum m68k_register mcf5210a_ctrl
[] = {
195 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR
, RAMBAR1
, MBAR
,
198 static const enum m68k_register mcf5213_ctrl
[] = {
199 VBR
, RAMBAR
, RAMBAR1
, FLASHBAR
,
202 static const enum m68k_register mcf5216_ctrl
[] = {
203 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
206 static const enum m68k_register mcf5221x_ctrl
[] = {
207 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
210 static const enum m68k_register mcf52223_ctrl
[] = {
211 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
214 static const enum m68k_register mcf52235_ctrl
[] = {
215 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
218 static const enum m68k_register mcf5225_ctrl
[] = {
219 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, MBAR
, RAMBAR1
,
222 static const enum m68k_register mcf52259_ctrl
[] = {
223 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
226 static const enum m68k_register mcf52277_ctrl
[] = {
227 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
230 static const enum m68k_register mcf5235_ctrl
[] = {
231 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
234 static const enum m68k_register mcf5249_ctrl
[] = {
235 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
, MBAR2
,
238 static const enum m68k_register mcf5250_ctrl
[] = {
242 static const enum m68k_register mcf5253_ctrl
[] = {
243 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
, MBAR2
,
246 static const enum m68k_register mcf5271_ctrl
[] = {
247 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
250 static const enum m68k_register mcf5272_ctrl
[] = {
251 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR_ALT
, RAMBAR0
, MBAR
,
254 static const enum m68k_register mcf5275_ctrl
[] = {
255 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
258 static const enum m68k_register mcf5282_ctrl
[] = {
259 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
262 static const enum m68k_register mcf53017_ctrl
[] = {
263 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
266 static const enum m68k_register mcf5307_ctrl
[] = {
267 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR_ALT
, MBAR
,
270 static const enum m68k_register mcf5329_ctrl
[] = {
271 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
274 static const enum m68k_register mcf5373_ctrl
[] = {
275 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
278 static const enum m68k_register mcfv4e_ctrl
[] = {
279 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
280 VBR
, PC
, ROMBAR0
, ROMBAR1
, RAMBAR0
, RAMBAR1
,
282 MPCR
/* Multiprocessor Control register */,
283 EDRAMBAR
/* Embedded DRAM Base Address Register */,
284 /* Permutation control registers. */
285 PCR1U0
, PCR1L0
, PCR1U1
, PCR1L1
, PCR2U0
, PCR2L0
, PCR2U1
, PCR2L1
,
286 PCR3U0
, PCR3L0
, PCR3U1
, PCR3L1
,
288 TC
/* ASID */, BUSCR
/* MMUBAR */,
289 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
290 MBAR1
/* MBAR */, MBAR2
/* SECMBAR */, MBAR0
/* SECMBAR */,
291 ROMBAR
/* ROMBAR0 */, RAMBAR
/* RAMBAR1 */,
294 static const enum m68k_register mcf5407_ctrl
[] = {
295 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
,
296 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
299 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
300 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
303 static const enum m68k_register mcf54418_ctrl
[] = {
304 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, ACR4
, ACR5
, ACR6
, ACR7
, MMUBAR
, RGPIOBAR
,
307 TC
/* ASID */, BUSCR
/* MMUBAR */,
308 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
309 RAMBAR
/* RAMBAR1 */,
312 static const enum m68k_register mcf54455_ctrl
[] = {
313 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
316 TC
/* ASID */, BUSCR
/* MMUBAR */,
317 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
318 RAMBAR
/* RAMBAR1 */,
321 static const enum m68k_register mcf5475_ctrl
[] = {
322 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
323 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
325 TC
/* ASID */, BUSCR
/* MMUBAR */,
326 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
327 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
330 static const enum m68k_register mcf5485_ctrl
[] = {
331 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
332 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
334 TC
/* ASID */, BUSCR
/* MMUBAR */,
335 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
336 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
339 static const enum m68k_register fido_ctrl
[] = {
340 SFC
, DFC
, USP
, VBR
, CAC
, MBO
,
343 #define cpu32_ctrl m68010_ctrl
345 static const enum m68k_register
*control_regs
;
347 /* Internal form of a 68020 instruction. */
351 const char *args
; /* List of opcode info. */
354 int numo
; /* Number of shorts in opcode. */
357 struct m68k_op operands
[6];
359 int nexp
; /* Number of exprs in use. */
360 struct m68k_exp exprs
[4];
362 int nfrag
; /* Number of frags we have to produce. */
365 int fragoff
; /* Where in the current opcode the frag ends. */
372 int nrel
; /* Num of reloc strucs in use. */
379 /* In a pc relative address the difference between the address
380 of the offset and the address that the offset is relative
381 to. This depends on the addressing mode. Basically this
382 is the value to put in the offset field to address the
383 first byte of the offset, without regarding the special
384 significance of some values (in the branch instruction, for
388 /* Whether this expression needs special pic relocation, and if
390 enum pic_relocation pic_reloc
;
393 reloc
[5]; /* Five is enough??? */
396 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
397 #define float_of_arch(x) ((x) & mfloat)
398 #define mmu_of_arch(x) ((x) & mmmu)
399 #define arch_coldfire_p(x) ((x) & mcfisa_a)
400 #define arch_coldfire_fpu(x) ((x) & cfloat)
402 /* Macros for determining if cpu supports a specific addressing mode. */
403 #define HAVE_LONG_DISP(x) \
404 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
405 #define HAVE_LONG_CALL(x) \
406 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
407 #define HAVE_LONG_COND(x) \
408 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
409 #define HAVE_LONG_BRANCH(x) \
410 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
411 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
413 static struct m68k_it the_ins
; /* The instruction being assembled. */
415 #define op(ex) ((ex)->exp.X_op)
416 #define adds(ex) ((ex)->exp.X_add_symbol)
417 #define subs(ex) ((ex)->exp.X_op_symbol)
418 #define offs(ex) ((ex)->exp.X_add_number)
420 /* Macros for adding things to the m68k_it struct. */
421 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
423 /* Like addword, but goes BEFORE general operands. */
426 insop (int w
, const struct m68k_incant
*opcode
)
429 for (z
= the_ins
.numo
; z
> opcode
->m_codenum
; --z
)
430 the_ins
.opcode
[z
] = the_ins
.opcode
[z
- 1];
431 for (z
= 0; z
< the_ins
.nrel
; z
++)
432 the_ins
.reloc
[z
].n
+= 2;
433 for (z
= 0; z
< the_ins
.nfrag
; z
++)
434 the_ins
.fragb
[z
].fragoff
++;
435 the_ins
.opcode
[opcode
->m_codenum
] = w
;
439 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
442 add_fix (int width
, struct m68k_exp
*exp
, int pc_rel
, int pc_fix
)
444 the_ins
.reloc
[the_ins
.nrel
].n
= (width
== 'B' || width
== '3'
445 ? the_ins
.numo
* 2 - 1
447 ? the_ins
.numo
* 2 + 1
448 : the_ins
.numo
* 2));
449 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
450 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
451 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
453 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
455 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
458 /* Cause an extra frag to be generated here, inserting up to 10 bytes
459 (that value is chosen in the frag_var call in md_assemble). TYPE
460 is the subtype of the frag to be generated; its primary type is
461 rs_machine_dependent.
463 The TYPE parameter is also used by md_convert_frag_1 and
464 md_estimate_size_before_relax. The appropriate type of fixup will
465 be emitted by md_convert_frag_1.
467 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
469 add_frag (symbolS
*add
, offsetT off
, int type
)
471 the_ins
.fragb
[the_ins
.nfrag
].fragoff
= the_ins
.numo
;
472 the_ins
.fragb
[the_ins
.nfrag
].fadd
= add
;
473 the_ins
.fragb
[the_ins
.nfrag
].foff
= off
;
474 the_ins
.fragb
[the_ins
.nfrag
++].fragty
= type
;
478 (op (ex) != O_constant && op (ex) != O_big)
480 static char *crack_operand (char *str
, struct m68k_op
*opP
);
481 static int get_num (struct m68k_exp
*exp
, int ok
);
482 static int reverse_16_bits (int in
);
483 static int reverse_8_bits (int in
);
484 static void install_gen_operand (int mode
, int val
);
485 static void install_operand (int mode
, int val
);
486 static void s_bss (int);
487 static void s_data1 (int);
488 static void s_data2 (int);
489 static void s_even (int);
490 static void s_proc (int);
491 static void s_chip (int);
492 static void s_fopt (int);
493 static void s_opt (int);
494 static void s_reg (int);
495 static void s_restore (int);
496 static void s_save (int);
497 static void s_mri_if (int);
498 static void s_mri_else (int);
499 static void s_mri_endi (int);
500 static void s_mri_break (int);
501 static void s_mri_next (int);
502 static void s_mri_for (int);
503 static void s_mri_endf (int);
504 static void s_mri_repeat (int);
505 static void s_mri_until (int);
506 static void s_mri_while (int);
507 static void s_mri_endw (int);
508 static void s_m68k_cpu (int);
509 static void s_m68k_arch (int);
513 unsigned long arch
; /* Architecture features. */
514 const enum m68k_register
*control_regs
; /* Control regs on chip */
515 const char *name
; /* Name */
516 int alias
; /* Alias for a cannonical name. If 1, then
517 succeeds canonical name, if -1 then
518 succeeds canonical name, if <-1 ||>1 this is a
519 deprecated name, and the next/previous name
523 /* We hold flags for features explicitly enabled and explicitly
525 static int current_architecture
;
526 static int not_current_architecture
;
527 static const struct m68k_cpu
*selected_arch
;
528 static const struct m68k_cpu
*selected_cpu
;
529 static int initialized
;
531 /* Architecture models. */
532 static const struct m68k_cpu m68k_archs
[] =
534 {m68000
, m68000_ctrl
, "68000", 0},
535 {m68010
, m68010_ctrl
, "68010", 0},
536 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
537 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
538 {m68040
, m68040_ctrl
, "68040", 0},
539 {m68060
, m68060_ctrl
, "68060", 0},
540 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
541 {fido_a
, fido_ctrl
, "fidoa", 0},
542 {mcfisa_a
|mcfhwdiv
, NULL
, "isaa", 0},
543 {mcfisa_a
|mcfhwdiv
|mcfisa_aa
|mcfusp
, NULL
, "isaaplus", 0},
544 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfusp
, NULL
, "isab", 0},
545 {mcfisa_a
|mcfhwdiv
|mcfisa_c
|mcfusp
, NULL
, "isac", 0},
546 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfmac
|mcfusp
, mcf_ctrl
, "cfv4", 0},
547 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "cfv4e", 0},
551 /* For -mno-mac we want to turn off all types of mac. */
552 static const unsigned no_mac
= mcfmac
| mcfemac
;
554 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
556 static const struct m68k_cpu m68k_extensions
[] =
558 {m68851
, NULL
, "68851", -1},
559 {m68881
, NULL
, "68881", -1},
560 {m68881
, NULL
, "68882", -1},
562 {cfloat
|m68881
, NULL
, "float", 0},
564 {mcfhwdiv
, NULL
, "div", 1},
565 {mcfusp
, NULL
, "usp", 1},
566 {mcfmac
, (void *)&no_mac
, "mac", 1},
567 {mcfemac
, NULL
, "emac", 1},
573 static const struct m68k_cpu m68k_cpus
[] =
575 {m68000
, m68000_ctrl
, "68000", 0},
576 {m68000
, m68000_ctrl
, "68ec000", 1},
577 {m68000
, m68000_ctrl
, "68hc000", 1},
578 {m68000
, m68000_ctrl
, "68hc001", 1},
579 {m68000
, m68000_ctrl
, "68008", 1},
580 {m68000
, m68000_ctrl
, "68302", 1},
581 {m68000
, m68000_ctrl
, "68306", 1},
582 {m68000
, m68000_ctrl
, "68307", 1},
583 {m68000
, m68000_ctrl
, "68322", 1},
584 {m68000
, m68000_ctrl
, "68356", 1},
585 {m68010
, m68010_ctrl
, "68010", 0},
586 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
587 {m68020
|m68881
|m68851
, m68020_ctrl
, "68k", 1},
588 {m68020
|m68881
|m68851
, m68020_ctrl
, "68ec020", 1},
589 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
590 {m68030
|m68881
|m68851
, m68020_ctrl
, "68ec030", 1},
591 {m68040
, m68040_ctrl
, "68040", 0},
592 {m68040
, m68040_ctrl
, "68ec040", 1},
593 {m68060
, m68060_ctrl
, "68060", 0},
594 {m68060
, m68060_ctrl
, "68ec060", 1},
596 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
597 {cpu32
|m68881
, cpu32_ctrl
, "68330", 1},
598 {cpu32
|m68881
, cpu32_ctrl
, "68331", 1},
599 {cpu32
|m68881
, cpu32_ctrl
, "68332", 1},
600 {cpu32
|m68881
, cpu32_ctrl
, "68333", 1},
601 {cpu32
|m68881
, cpu32_ctrl
, "68334", 1},
602 {cpu32
|m68881
, cpu32_ctrl
, "68336", 1},
603 {cpu32
|m68881
, cpu32_ctrl
, "68340", 1},
604 {cpu32
|m68881
, cpu32_ctrl
, "68341", 1},
605 {cpu32
|m68881
, cpu32_ctrl
, "68349", 1},
606 {cpu32
|m68881
, cpu32_ctrl
, "68360", 1},
608 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51", 0},
609 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51ac", 1},
610 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51ag", 1},
611 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51cn", 1},
612 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfmac
, mcf51_ctrl
, "51em", 1},
613 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfmac
, mcf51_ctrl
, "51je", 1},
614 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfemac
, mcf51_ctrl
, "51jf", 1},
615 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfemac
, mcf51_ctrl
, "51jg", 1},
616 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51jm", 1},
617 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfmac
, mcf51_ctrl
, "51mm", 1},
618 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51qe", 1},
619 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfemac
, mcf51_ctrl
, "51qm", 1},
621 {mcfisa_a
, mcf_ctrl
, "5200", 0},
622 {mcfisa_a
, mcf_ctrl
, "5202", 1},
623 {mcfisa_a
, mcf_ctrl
, "5204", 1},
624 {mcfisa_a
, mcf5206_ctrl
, "5206", 1},
626 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5206_ctrl
, "5206e", 0},
628 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5207", -1},
629 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5208", 0},
631 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5210a", 0},
632 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5211a", 1},
634 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5211", -1},
635 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5212", -1},
636 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5213", 0},
638 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5214", -1},
639 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5216", 0},
640 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "521x", 2},
642 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5221x_ctrl
, "5221x", 0},
644 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf52223_ctrl
, "52221", -1},
645 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf52223_ctrl
, "52223", 0},
647 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52230", -1},
648 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52233", -1},
649 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52234", -1},
650 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52235", 0},
652 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5224", -1},
653 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5225", 0},
655 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52277_ctrl
, "52274", -1},
656 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52277_ctrl
, "52277", 0},
658 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5232", -1},
659 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5233", -1},
660 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5234", -1},
661 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5235", -1},
662 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "523x", 0},
664 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5249_ctrl
, "5249", 0},
665 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5250_ctrl
, "5250", 0},
666 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5253_ctrl
, "5253", 0},
668 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52252", -1},
669 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52254", -1},
670 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52255", -1},
671 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52256", -1},
672 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52258", -1},
673 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52259", 0},
675 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5270", -1},
676 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5271", 0},
678 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5272_ctrl
, "5272", 0},
680 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5274", -1},
681 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5275", 0},
683 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5280", -1},
684 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5281", -1},
685 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5282", -1},
686 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "528x", 0},
688 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53011", -1},
689 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53012", -1},
690 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53013", -1},
691 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53014", -1},
692 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53015", -1},
693 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53016", -1},
694 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53017", 0},
696 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5307_ctrl
, "5307", 0},
698 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5327", -1},
699 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5328", -1},
700 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5329", -1},
701 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "532x", 0},
703 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5372", -1},
704 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5373", -1},
705 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "537x", 0},
707 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfmac
, mcf5407_ctrl
, "5407",0},
709 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54410", -1},
710 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54415", -1},
711 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54416", -1},
712 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54417", -1},
713 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54418", 0},
715 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54450", -1},
716 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54451", -1},
717 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54452", -1},
718 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54453", -1},
719 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54454", -1},
720 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54455", 0},
722 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5470", -1},
723 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5471", -1},
724 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5472", -1},
725 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5473", -1},
726 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5474", -1},
727 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5475", -1},
728 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "547x", 0},
730 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5480", -1},
731 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5481", -1},
732 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5482", -1},
733 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5483", -1},
734 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5484", -1},
735 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5485", -1},
736 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "548x", 0},
738 {fido_a
, fido_ctrl
, "fidoa", 0},
739 {fido_a
, fido_ctrl
, "fido", 1},
744 static const struct m68k_cpu
*m68k_lookup_cpu
745 (const char *, const struct m68k_cpu
*, int, int *);
746 static int m68k_set_arch (const char *, int, int);
747 static int m68k_set_cpu (const char *, int, int);
748 static int m68k_set_extension (const char *, int, int);
749 static void m68k_init_arch (void);
751 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
752 architecture and we have a lot of relaxation modes. */
754 /* Macros used in the relaxation code. */
755 #define TAB(x,y) (((x) << 2) + (y))
756 #define TABTYPE(x) ((x) >> 2)
758 /* Relaxation states. */
764 /* Here are all the relaxation modes we support. First we can relax ordinary
765 branches. On 68020 and higher and on CPU32 all branch instructions take
766 three forms, so on these CPUs all branches always remain as such. When we
767 have to expand to the LONG form on a 68000, though, we substitute an
768 absolute jump instead. This is a direct replacement for unconditional
769 branches and a branch over a jump for conditional branches. However, if the
770 user requires PIC and disables this with --pcrel, we can only relax between
771 BYTE and SHORT forms, punting if that isn't enough. This gives us four
772 different relaxation modes for branches: */
774 #define BRANCHBWL 0 /* Branch byte, word, or long. */
775 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
776 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
777 #define BRANCHBW 3 /* Branch byte or word. */
779 /* We also relax coprocessor branches and DBcc's. All CPUs that support
780 coprocessor branches support them in word and long forms, so we have only
781 one relaxation mode for them. DBcc's are word only on all CPUs. We can
782 relax them to the LONG form with a branch-around sequence. This sequence
783 can use a long branch (if available) or an absolute jump (if acceptable).
784 This gives us two relaxation modes. If long branches are not available and
785 absolute jumps are not acceptable, we don't relax DBcc's. */
787 #define FBRANCH 4 /* Coprocessor branch. */
788 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
789 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
791 /* That's all for instruction relaxation. However, we also relax PC-relative
792 operands. Specifically, we have three operand relaxation modes. On the
793 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
794 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
795 two. Also PC+displacement+index operands in their simple form (with a non-
796 suppressed index without memory indirection) are supported on all CPUs, but
797 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
798 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
799 form of the PC+displacement+index operand. Finally, some absolute operands
800 can be relaxed down to 16-bit PC-relative. */
802 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
803 #define PCINDEX 8 /* PC + displacement + index. */
804 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
806 /* This relaxation is required for branches where there is no long
807 branch and we are in pcrel mode. We generate a bne/beq pair. */
808 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs
811 /* Note that calls to frag_var need to specify the maximum expansion
812 needed; this is currently 12 bytes for bne/beq pair. */
813 #define FRAG_VAR_SIZE 12
816 How far Forward this mode will reach:
817 How far Backward this mode will reach:
818 How many bytes this mode will add to the size of the frag
819 Which mode to go to if the offset won't fit in this one
821 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
822 relax_typeS md_relax_table
[] =
824 { 127, -128, 0, TAB (BRANCHBWL
, SHORT
) },
825 { 32767, -32768, 2, TAB (BRANCHBWL
, LONG
) },
829 { 127, -128, 0, TAB (BRABSJUNC
, SHORT
) },
830 { 32767, -32768, 2, TAB (BRABSJUNC
, LONG
) },
834 { 127, -128, 0, TAB (BRABSJCOND
, SHORT
) },
835 { 32767, -32768, 2, TAB (BRABSJCOND
, LONG
) },
839 { 127, -128, 0, TAB (BRANCHBW
, SHORT
) },
844 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
845 { 32767, -32768, 2, TAB (FBRANCH
, LONG
) },
849 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
850 { 32767, -32768, 2, TAB (DBCCLBR
, LONG
) },
854 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
855 { 32767, -32768, 2, TAB (DBCCABSJ
, LONG
) },
859 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
860 { 32767, -32768, 2, TAB (PCREL1632
, LONG
) },
864 { 125, -130, 0, TAB (PCINDEX
, SHORT
) },
865 { 32765, -32770, 2, TAB (PCINDEX
, LONG
) },
869 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
870 { 32767, -32768, 2, TAB (ABSTOPCREL
, LONG
) },
874 { 127, -128, 0, TAB (BRANCHBWPL
, SHORT
) },
875 { 32767, -32768, 2, TAB (BRANCHBWPL
, LONG
) },
880 /* These are the machine dependent pseudo-ops. These are included so
881 the assembler can work on the output from the SUN C compiler, which
884 /* This table describes all the machine specific pseudo-ops the assembler
885 has to support. The fields are:
886 pseudo-op name without dot
887 function to call to execute this pseudo-op
888 Integer arg to pass to the function. */
889 const pseudo_typeS md_pseudo_table
[] =
891 {"data1", s_data1
, 0},
892 {"data2", s_data2
, 0},
895 {"skip", s_space
, 0},
897 #if defined (TE_SUN3) || defined (OBJ_ELF)
898 {"align", s_align_bytes
, 0},
901 {"swbeg", s_ignore
, 0},
902 {"long", m68k_elf_cons
, 4},
904 {"extend", float_cons
, 'x'},
905 {"ldouble", float_cons
, 'x'},
907 {"arch", s_m68k_arch
, 0},
908 {"cpu", s_m68k_cpu
, 0},
910 /* The following pseudo-ops are supported for MRI compatibility. */
912 {"comline", s_space
, 1},
914 {"mask2", s_ignore
, 0},
917 {"restore", s_restore
, 0},
921 {"if.b", s_mri_if
, 'b'},
922 {"if.w", s_mri_if
, 'w'},
923 {"if.l", s_mri_if
, 'l'},
924 {"else", s_mri_else
, 0},
925 {"else.s", s_mri_else
, 's'},
926 {"else.l", s_mri_else
, 'l'},
927 {"endi", s_mri_endi
, 0},
928 {"break", s_mri_break
, 0},
929 {"break.s", s_mri_break
, 's'},
930 {"break.l", s_mri_break
, 'l'},
931 {"next", s_mri_next
, 0},
932 {"next.s", s_mri_next
, 's'},
933 {"next.l", s_mri_next
, 'l'},
934 {"for", s_mri_for
, 0},
935 {"for.b", s_mri_for
, 'b'},
936 {"for.w", s_mri_for
, 'w'},
937 {"for.l", s_mri_for
, 'l'},
938 {"endf", s_mri_endf
, 0},
939 {"repeat", s_mri_repeat
, 0},
940 {"until", s_mri_until
, 0},
941 {"until.b", s_mri_until
, 'b'},
942 {"until.w", s_mri_until
, 'w'},
943 {"until.l", s_mri_until
, 'l'},
944 {"while", s_mri_while
, 0},
945 {"while.b", s_mri_while
, 'b'},
946 {"while.w", s_mri_while
, 'w'},
947 {"while.l", s_mri_while
, 'l'},
948 {"endw", s_mri_endw
, 0},
953 /* The mote pseudo ops are put into the opcode table, since they
954 don't start with a . they look like opcodes to gas. */
956 const pseudo_typeS mote_pseudo_table
[] =
969 {"xdef", s_globl
, 0},
971 {"align", s_align_bytes
, 0},
973 {"align", s_align_ptwo
, 0},
976 {"sect", obj_coff_section
, 0},
977 {"section", obj_coff_section
, 0},
982 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
983 gives identical results to a 32-bit host. */
984 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
985 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
987 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
988 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
989 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
990 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
992 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
993 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
994 #define islong(x) (1)
996 static char notend_table
[256];
997 static char alt_notend_table
[256];
999 (! (notend_table[(unsigned char) *s] \
1001 && alt_notend_table[(unsigned char) s[1]])))
1005 /* Return zero if the reference to SYMBOL from within the same segment may
1008 /* On an ELF system, we can't relax an externally visible symbol,
1009 because it may be overridden by a shared library. However, if
1010 TARGET_OS is "elf", then we presume that we are assembling for an
1011 embedded system, in which case we don't have to worry about shared
1012 libraries, and we can relax any external sym. */
1014 #define relaxable_symbol(symbol) \
1015 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
1016 || S_IS_WEAK (symbol)))
1018 /* Compute the relocation code for a fixup of SIZE bytes, using pc
1019 relative relocation if PCREL is non-zero. PIC says whether a special
1020 pic relocation was requested. */
1022 static bfd_reloc_code_real_type
1023 get_reloc_code (int size
, int pcrel
, enum pic_relocation pic
)
1031 return BFD_RELOC_8_GOT_PCREL
;
1033 return BFD_RELOC_16_GOT_PCREL
;
1035 return BFD_RELOC_32_GOT_PCREL
;
1043 return BFD_RELOC_8_GOTOFF
;
1045 return BFD_RELOC_16_GOTOFF
;
1047 return BFD_RELOC_32_GOTOFF
;
1055 return BFD_RELOC_8_PLT_PCREL
;
1057 return BFD_RELOC_16_PLT_PCREL
;
1059 return BFD_RELOC_32_PLT_PCREL
;
1067 return BFD_RELOC_8_PLTOFF
;
1069 return BFD_RELOC_16_PLTOFF
;
1071 return BFD_RELOC_32_PLTOFF
;
1079 return BFD_RELOC_68K_TLS_GD8
;
1081 return BFD_RELOC_68K_TLS_GD16
;
1083 return BFD_RELOC_68K_TLS_GD32
;
1091 return BFD_RELOC_68K_TLS_LDM8
;
1093 return BFD_RELOC_68K_TLS_LDM16
;
1095 return BFD_RELOC_68K_TLS_LDM32
;
1103 return BFD_RELOC_68K_TLS_LDO8
;
1105 return BFD_RELOC_68K_TLS_LDO16
;
1107 return BFD_RELOC_68K_TLS_LDO32
;
1115 return BFD_RELOC_68K_TLS_IE8
;
1117 return BFD_RELOC_68K_TLS_IE16
;
1119 return BFD_RELOC_68K_TLS_IE32
;
1127 return BFD_RELOC_68K_TLS_LE8
;
1129 return BFD_RELOC_68K_TLS_LE16
;
1131 return BFD_RELOC_68K_TLS_LE32
;
1141 return BFD_RELOC_8_PCREL
;
1143 return BFD_RELOC_16_PCREL
;
1145 return BFD_RELOC_32_PCREL
;
1155 return BFD_RELOC_16
;
1157 return BFD_RELOC_32
;
1164 if (pic
== pic_none
)
1165 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
1167 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
1171 if (pic
== pic_none
)
1172 as_bad (_("Can not do %d byte relocation"), size
);
1174 as_bad (_("Can not do %d byte pic relocation"), size
);
1177 return BFD_RELOC_NONE
;
1180 /* Here we decide which fixups can be adjusted to make them relative
1181 to the beginning of the section instead of the symbol. Basically
1182 we need to make sure that the dynamic relocations are done
1183 correctly, so in some cases we force the original symbol to be
1186 tc_m68k_fix_adjustable (fixS
*fixP
)
1188 /* Adjust_reloc_syms doesn't know about the GOT. */
1189 switch (fixP
->fx_r_type
)
1191 case BFD_RELOC_8_GOT_PCREL
:
1192 case BFD_RELOC_16_GOT_PCREL
:
1193 case BFD_RELOC_32_GOT_PCREL
:
1194 case BFD_RELOC_8_GOTOFF
:
1195 case BFD_RELOC_16_GOTOFF
:
1196 case BFD_RELOC_32_GOTOFF
:
1197 case BFD_RELOC_8_PLT_PCREL
:
1198 case BFD_RELOC_16_PLT_PCREL
:
1199 case BFD_RELOC_32_PLT_PCREL
:
1200 case BFD_RELOC_8_PLTOFF
:
1201 case BFD_RELOC_16_PLTOFF
:
1202 case BFD_RELOC_32_PLTOFF
:
1203 case BFD_RELOC_68K_TLS_GD32
:
1204 case BFD_RELOC_68K_TLS_GD16
:
1205 case BFD_RELOC_68K_TLS_GD8
:
1206 case BFD_RELOC_68K_TLS_LDM32
:
1207 case BFD_RELOC_68K_TLS_LDM16
:
1208 case BFD_RELOC_68K_TLS_LDM8
:
1209 case BFD_RELOC_68K_TLS_LDO32
:
1210 case BFD_RELOC_68K_TLS_LDO16
:
1211 case BFD_RELOC_68K_TLS_LDO8
:
1212 case BFD_RELOC_68K_TLS_IE32
:
1213 case BFD_RELOC_68K_TLS_IE16
:
1214 case BFD_RELOC_68K_TLS_IE8
:
1215 case BFD_RELOC_68K_TLS_LE32
:
1216 case BFD_RELOC_68K_TLS_LE16
:
1217 case BFD_RELOC_68K_TLS_LE8
:
1220 case BFD_RELOC_VTABLE_INHERIT
:
1221 case BFD_RELOC_VTABLE_ENTRY
:
1229 #else /* !OBJ_ELF */
1231 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1233 /* PR gas/3041 Weak symbols are not relaxable
1234 because they must be treated as extern. */
1235 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1237 #endif /* OBJ_ELF */
1240 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
1243 bfd_reloc_code_real_type code
;
1245 /* If the tcbit is set, then this was a fixup of a negative value
1246 that was never resolved. We do not have a reloc to handle this,
1247 so just return. We assume that other code will have detected this
1248 situation and produced a helpful error message, so we just tell the
1249 user that the reloc cannot be produced. */
1253 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1254 _("Unable to produce reloc against symbol '%s'"),
1255 S_GET_NAME (fixp
->fx_addsy
));
1259 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
1261 code
= fixp
->fx_r_type
;
1263 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1264 that fixup_segment converted a non-PC relative reloc into a
1265 PC relative reloc. In such a case, we need to convert the
1272 code
= BFD_RELOC_8_PCREL
;
1275 code
= BFD_RELOC_16_PCREL
;
1278 code
= BFD_RELOC_32_PCREL
;
1280 case BFD_RELOC_8_PCREL
:
1281 case BFD_RELOC_16_PCREL
:
1282 case BFD_RELOC_32_PCREL
:
1283 case BFD_RELOC_8_GOT_PCREL
:
1284 case BFD_RELOC_16_GOT_PCREL
:
1285 case BFD_RELOC_32_GOT_PCREL
:
1286 case BFD_RELOC_8_GOTOFF
:
1287 case BFD_RELOC_16_GOTOFF
:
1288 case BFD_RELOC_32_GOTOFF
:
1289 case BFD_RELOC_8_PLT_PCREL
:
1290 case BFD_RELOC_16_PLT_PCREL
:
1291 case BFD_RELOC_32_PLT_PCREL
:
1292 case BFD_RELOC_8_PLTOFF
:
1293 case BFD_RELOC_16_PLTOFF
:
1294 case BFD_RELOC_32_PLTOFF
:
1295 case BFD_RELOC_68K_TLS_GD32
:
1296 case BFD_RELOC_68K_TLS_GD16
:
1297 case BFD_RELOC_68K_TLS_GD8
:
1298 case BFD_RELOC_68K_TLS_LDM32
:
1299 case BFD_RELOC_68K_TLS_LDM16
:
1300 case BFD_RELOC_68K_TLS_LDM8
:
1301 case BFD_RELOC_68K_TLS_LDO32
:
1302 case BFD_RELOC_68K_TLS_LDO16
:
1303 case BFD_RELOC_68K_TLS_LDO8
:
1304 case BFD_RELOC_68K_TLS_IE32
:
1305 case BFD_RELOC_68K_TLS_IE16
:
1306 case BFD_RELOC_68K_TLS_IE8
:
1307 case BFD_RELOC_68K_TLS_LE32
:
1308 case BFD_RELOC_68K_TLS_LE16
:
1309 case BFD_RELOC_68K_TLS_LE8
:
1312 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1313 _("Cannot make %s relocation PC relative"),
1314 bfd_get_reloc_code_name (code
));
1320 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1321 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
1323 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1324 MAP (1, 0, BFD_RELOC_8
);
1325 MAP (2, 0, BFD_RELOC_16
);
1326 MAP (4, 0, BFD_RELOC_32
);
1327 MAP (1, 1, BFD_RELOC_8_PCREL
);
1328 MAP (2, 1, BFD_RELOC_16_PCREL
);
1329 MAP (4, 1, BFD_RELOC_32_PCREL
);
1337 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1338 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1339 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1340 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1342 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
1344 && S_IS_WEAK (fixp
->fx_addsy
)
1345 && ! bfd_is_und_section (S_GET_SEGMENT (fixp
->fx_addsy
)))
1347 /* PR gas/3041 References to weak symbols must be treated as extern
1348 in order to be overridable by the linker, even if they are defined
1349 in the same object file. So the original addend must be written
1350 "as is" into the output section without further processing.
1351 The addend value must be hacked here in order to force
1352 bfd_install_relocation() to write the original value into the
1354 1) MD_APPLY_SYM_VALUE() is set to 1 for m68k/a.out, so the symbol
1355 value has already been added to the addend in fixup_segment(). We
1357 2) bfd_install_relocation() will incorrectly treat this symbol as
1358 resolved, so it will write the symbol value plus its addend and
1359 section VMA. As a workaround we can tweak the addend value here in
1360 order to get the original value in the section after the call to
1361 bfd_install_relocation(). */
1362 reloc
->addend
= fixp
->fx_addnumber
1363 /* Fix because of MD_APPLY_SYM_VALUE() */
1364 - S_GET_VALUE (fixp
->fx_addsy
)
1365 /* Fix for bfd_install_relocation() */
1366 - (S_GET_VALUE (fixp
->fx_addsy
)
1367 + S_GET_SEGMENT (fixp
->fx_addsy
)->vma
);
1369 else if (fixp
->fx_pcrel
)
1370 reloc
->addend
= fixp
->fx_addnumber
;
1374 if (!fixp
->fx_pcrel
)
1375 reloc
->addend
= fixp
->fx_addnumber
;
1377 reloc
->addend
= (section
->vma
1378 + fixp
->fx_pcrel_adjust
1379 + fixp
->fx_addnumber
1380 + md_pcrel_from (fixp
));
1383 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1384 gas_assert (reloc
->howto
!= 0);
1389 /* Handle of the OPCODE hash table. NULL means any use before
1390 m68k_ip_begin() will crash. */
1391 static struct hash_control
*op_hash
;
1393 /* Assemble an m68k instruction. */
1396 m68k_ip (char *instring
)
1399 struct m68k_op
*opP
;
1400 const struct m68k_incant
*opcode
;
1402 int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1403 char *pdot
, *pdotmove
;
1404 enum m68k_size siz1
, siz2
;
1408 struct m68k_op operands_backup
[6];
1409 LITTLENUM_TYPE words
[6];
1410 LITTLENUM_TYPE
*wordp
;
1411 unsigned long ok_arch
= 0;
1413 if (*instring
== ' ')
1414 instring
++; /* Skip leading whitespace. */
1416 /* Scan up to end of operation-code, which MUST end in end-of-string
1417 or exactly 1 space. */
1419 for (p
= instring
; *p
!= '\0'; p
++)
1429 the_ins
.error
= _("No operator");
1433 /* p now points to the end of the opcode name, probably whitespace.
1434 Make sure the name is null terminated by clobbering the
1435 whitespace, look it up in the hash table, then fix it back.
1436 Remove a dot, first, since the opcode tables have none. */
1439 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1440 *pdotmove
= pdotmove
[1];
1446 opcode
= (const struct m68k_incant
*) hash_find (op_hash
, instring
);
1451 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1452 *pdotmove
= pdotmove
[-1];
1459 the_ins
.error
= _("Unknown operator");
1463 /* Found a legitimate opcode, start matching operands. */
1467 if (opcode
->m_operands
== 0)
1469 char *old
= input_line_pointer
;
1471 input_line_pointer
= p
;
1472 /* Ahh - it's a motorola style psuedo op. */
1473 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1474 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1475 input_line_pointer
= old
;
1481 if (flag_mri
&& opcode
->m_opnum
== 0)
1483 /* In MRI mode, random garbage is allowed after an instruction
1484 which accepts no operands. */
1485 the_ins
.args
= opcode
->m_operands
;
1486 the_ins
.numargs
= opcode
->m_opnum
;
1487 the_ins
.numo
= opcode
->m_codenum
;
1488 the_ins
.opcode
[0] = getone (opcode
);
1489 the_ins
.opcode
[1] = gettwo (opcode
);
1493 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1495 p
= crack_operand (p
, opP
);
1499 the_ins
.error
= opP
->error
;
1504 opsfound
= opP
- &the_ins
.operands
[0];
1506 /* This ugly hack is to support the floating pt opcodes in their
1507 standard form. Essentially, we fake a first enty of type COP#1 */
1508 if (opcode
->m_operands
[0] == 'I')
1512 for (n
= opsfound
; n
> 0; --n
)
1513 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1515 memset (&the_ins
.operands
[0], '\0', sizeof (the_ins
.operands
[0]));
1516 the_ins
.operands
[0].mode
= CONTROL
;
1517 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1521 /* We've got the operands. Find an opcode that'll accept them. */
1524 /* If we didn't get the right number of ops, or we have no
1525 common model with this pattern then reject this pattern. */
1527 ok_arch
|= opcode
->m_arch
;
1528 if (opsfound
!= opcode
->m_opnum
1529 || ((opcode
->m_arch
& current_architecture
) == 0))
1535 /* Make a copy of the operands of this insn so that
1536 we can modify them safely, should we want to. */
1537 gas_assert (opsfound
<= (int) ARRAY_SIZE (operands_backup
));
1538 for (i
= 0; i
< opsfound
; i
++)
1539 operands_backup
[i
] = the_ins
.operands
[i
];
1541 for (s
= opcode
->m_operands
, opP
= &operands_backup
[0];
1545 /* Warning: this switch is huge! */
1546 /* I've tried to organize the cases into this order:
1547 non-alpha first, then alpha by letter. Lower-case
1548 goes directly before uppercase counterpart. */
1549 /* Code with multiple case ...: gets sorted by the lowest
1550 case ... it belongs to. I hope this makes sense. */
1656 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1673 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1692 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1702 if (opP
->mode
!= IMMED
)
1704 else if (s
[1] == 'b'
1705 && ! isvar (&opP
->disp
)
1706 && (opP
->disp
.exp
.X_op
!= O_constant
1707 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1709 else if (s
[1] == 'B'
1710 && ! isvar (&opP
->disp
)
1711 && (opP
->disp
.exp
.X_op
!= O_constant
1712 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1714 else if (s
[1] == 'w'
1715 && ! isvar (&opP
->disp
)
1716 && (opP
->disp
.exp
.X_op
!= O_constant
1717 || ! isword (opP
->disp
.exp
.X_add_number
)))
1719 else if (s
[1] == 'W'
1720 && ! isvar (&opP
->disp
)
1721 && (opP
->disp
.exp
.X_op
!= O_constant
1722 || ! issword (opP
->disp
.exp
.X_add_number
)))
1728 if (opP
->mode
!= IMMED
)
1733 if (opP
->mode
== AREG
1734 || opP
->mode
== CONTROL
1735 || opP
->mode
== FPREG
1736 || opP
->mode
== IMMED
1737 || opP
->mode
== REGLST
1738 || (opP
->mode
!= ABSL
1740 || opP
->reg
== ZPC
)))
1745 if (opP
->mode
== CONTROL
1746 || opP
->mode
== FPREG
1747 || opP
->mode
== REGLST
1748 || opP
->mode
== IMMED
1749 || (opP
->mode
!= ABSL
1751 || opP
->reg
== ZPC
)))
1779 if (opP
->mode
== CONTROL
1780 || opP
->mode
== FPREG
1781 || opP
->mode
== REGLST
)
1786 if (opP
->mode
!= AINC
)
1791 if (opP
->mode
!= ADEC
)
1841 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1862 case '~': /* For now! (JF FOO is this right?) */
1884 if (opP
->mode
!= CONTROL
1885 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1890 if (opP
->mode
!= AREG
)
1895 if (opP
->mode
!= AINDR
)
1900 if (opP
->mode
!= AINDR
&& opP
->mode
!= AINC
&& opP
->mode
!= ADEC
1901 && (opP
->mode
!= DISP
1903 || opP
->reg
> ADDR7
))
1908 if (opP
->mode
!= ABSL
1910 && strncmp (instring
, "jbsr", 4) == 0))
1933 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1938 if (opP
->mode
!= DISP
1940 || opP
->reg
> ADDR7
)
1945 if (opP
->mode
!= DREG
)
1950 if (opP
->reg
!= ACC
)
1955 if (opP
->reg
!= ACC
&& opP
->reg
!= ACC1
1956 && opP
->reg
!= ACC2
&& opP
->reg
!= ACC3
)
1961 if (opP
->mode
!= FPREG
)
1966 if (opP
->reg
!= MACSR
)
1971 if (opP
->reg
!= ACCEXT01
&& opP
->reg
!= ACCEXT23
)
1976 if (opP
->reg
!= MASK
)
1981 if (opP
->mode
!= CONTROL
1988 if (opP
->mode
!= LSH
&& opP
->mode
!= RSH
)
1993 if (opP
->mode
!= CONTROL
1995 || opP
->reg
> last_movec_reg
2000 const enum m68k_register
*rp
;
2002 for (rp
= control_regs
; *rp
; rp
++)
2004 if (*rp
== opP
->reg
)
2006 /* In most CPUs RAMBAR refers to control reg
2007 c05 (RAMBAR1), but a few CPUs have it
2008 refer to c04 (RAMBAR0). */
2009 else if (*rp
== RAMBAR_ALT
&& opP
->reg
== RAMBAR
)
2011 opP
->reg
= RAMBAR_ALT
;
2021 if (opP
->mode
!= IMMED
)
2027 if (opP
->mode
== DREG
2028 || opP
->mode
== AREG
2029 || opP
->mode
== FPREG
)
2038 opP
->mask
= 1 << (opP
->reg
- DATA0
);
2041 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
2044 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
2052 else if (opP
->mode
== CONTROL
)
2061 opP
->mask
= 1 << 24;
2064 opP
->mask
= 1 << 25;
2067 opP
->mask
= 1 << 26;
2076 else if (opP
->mode
!= REGLST
)
2078 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
2080 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
2085 if (opP
->mode
!= IMMED
)
2087 else if (opP
->disp
.exp
.X_op
!= O_constant
2088 || ! issbyte (opP
->disp
.exp
.X_add_number
))
2090 else if (! m68k_quick
2091 && instring
[3] != 'q'
2092 && instring
[4] != 'q')
2097 if (opP
->mode
!= DREG
2098 && opP
->mode
!= IMMED
2099 && opP
->mode
!= ABSL
)
2104 if (opP
->mode
!= IMMED
)
2106 else if (opP
->disp
.exp
.X_op
!= O_constant
2107 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
2109 else if (! m68k_quick
2110 && (strncmp (instring
, "add", 3) == 0
2111 || strncmp (instring
, "sub", 3) == 0)
2112 && instring
[3] != 'q')
2117 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
2122 if (opP
->mode
!= AINDR
2123 && (opP
->mode
!= BASE
2125 && opP
->reg
!= ZADDR0
)
2126 || opP
->disp
.exp
.X_op
!= O_absent
2127 || ((opP
->index
.reg
< DATA0
2128 || opP
->index
.reg
> DATA7
)
2129 && (opP
->index
.reg
< ADDR0
2130 || opP
->index
.reg
> ADDR7
))
2131 || opP
->index
.size
!= SIZE_UNSPEC
2132 || opP
->index
.scale
!= 1))
2137 if (opP
->mode
!= CONTROL
2138 || ! (opP
->reg
== FPI
2140 || opP
->reg
== FPC
))
2145 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
2150 if (opP
->mode
!= IMMED
)
2152 else if (opP
->disp
.exp
.X_op
!= O_constant
2153 || TRUNC (opP
->disp
.exp
.X_add_number
) > 7)
2158 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
2163 if (opP
->mode
!= IMMED
)
2165 else if (opP
->disp
.exp
.X_op
!= O_constant
2166 || (TRUNC (opP
->disp
.exp
.X_add_number
) != 0xffffffff
2167 && TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 6))
2172 if (opP
->mode
!= IMMED
)
2174 else if (opP
->disp
.exp
.X_op
!= O_constant
2175 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
2180 if (opP
->mode
!= IMMED
)
2182 else if (opP
->disp
.exp
.X_op
!= O_constant
2183 || TRUNC (opP
->disp
.exp
.X_add_number
) > 511)
2187 /* JF these are out of order. We could put them
2188 in order if we were willing to put up with
2189 bunches of #ifdef m68851s in the code.
2191 Don't forget that you need these operands
2192 to use 68030 MMU instructions. */
2194 /* Memory addressing mode used by pflushr. */
2196 if (opP
->mode
== CONTROL
2197 || opP
->mode
== FPREG
2198 || opP
->mode
== DREG
2199 || opP
->mode
== AREG
2200 || opP
->mode
== REGLST
)
2202 /* We should accept immediate operands, but they
2203 supposedly have to be quad word, and we don't
2204 handle that. I would like to see what a Motorola
2205 assembler does before doing something here. */
2206 if (opP
->mode
== IMMED
)
2211 if (opP
->mode
!= CONTROL
2212 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
2217 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
2222 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
2227 if (opP
->mode
!= CONTROL
2230 && opP
->reg
!= SCC
))
2235 if (opP
->mode
!= CONTROL
2241 if (opP
->mode
!= CONTROL
2244 && opP
->reg
!= CRP
))
2268 if (opP
->mode
!= CONTROL
2269 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
2270 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
2275 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
2280 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
2285 if (opP
->mode
!= CONTROL
2294 if (opP
->mode
!= ABSL
)
2299 if (opP
->reg
< DATA0L
|| opP
->reg
> ADDR7U
)
2301 /* FIXME: kludge instead of fixing parser:
2302 upper/lower registers are *not* CONTROL
2303 registers, but ordinary ones. */
2304 if ((opP
->reg
>= DATA0L
&& opP
->reg
<= DATA7L
)
2305 || (opP
->reg
>= DATA0U
&& opP
->reg
<= DATA7U
))
2312 if (!(opP
->mode
== AINDR
2313 || (opP
->mode
== DISP
2314 && !(opP
->reg
== PC
|| opP
->reg
== ZPC
))))
2319 if (!(opP
->mode
== AINDR
|| opP
->mode
== DISP
))
2331 /* Since we have found the correct instruction, copy
2332 in the modifications that we may have made. */
2334 for (i
= 0; i
< opsfound
; i
++)
2335 the_ins
.operands
[i
] = operands_backup
[i
];
2341 opcode
= opcode
->m_next
;
2346 && !(ok_arch
& current_architecture
))
2348 const struct m68k_cpu
*cpu
;
2351 char *buf
= XNEWVEC (char, space
+ 1);
2355 the_ins
.error
= buf
;
2356 /* Make sure there's a NUL at the end of the buffer -- strncpy
2357 won't write one when it runs out of buffer. */
2359 #define APPEND(STRING) \
2360 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2362 APPEND (_("invalid instruction for this architecture; needs "));
2366 APPEND ("ColdFire ISA_A");
2369 APPEND ("ColdFire ");
2370 APPEND (_("hardware divide"));
2373 APPEND ("ColdFire ISA_A+");
2376 APPEND ("ColdFire ISA_B");
2379 APPEND ("ColdFire ISA_C");
2382 APPEND ("ColdFire fpu");
2385 APPEND ("M68K fpu");
2388 APPEND ("M68K mmu");
2392 APPEND (_("or higher"));
2396 APPEND (_("or higher"));
2400 APPEND (_("or higher"));
2408 for (cpu
= m68k_cpus
; cpu
->name
; cpu
++)
2409 if (!cpu
->alias
&& (cpu
->arch
& ok_arch
))
2411 const struct m68k_cpu
*alias
;
2412 int seen_master
= 0;
2418 for (alias
= cpu
; alias
!= m68k_cpus
; alias
--)
2419 if (alias
[-1].alias
>= 0)
2421 for (; !seen_master
|| alias
->alias
> 0; alias
++)
2431 APPEND (alias
->name
);
2444 /* We ran out of space, so replace the end of the list
2449 strcpy (buf
, " ...");
2453 the_ins
.error
= _("operands mismatch");
2460 /* Now assemble it. */
2461 the_ins
.args
= opcode
->m_operands
;
2462 the_ins
.numargs
= opcode
->m_opnum
;
2463 the_ins
.numo
= opcode
->m_codenum
;
2464 the_ins
.opcode
[0] = getone (opcode
);
2465 the_ins
.opcode
[1] = gettwo (opcode
);
2467 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2472 /* This switch is a doozy.
2473 Watch the first step; its a big one! */
2506 tmpreg
= 0x3c; /* 7.4 */
2507 if (strchr ("bwl", s
[1]))
2508 nextword
= get_num (&opP
->disp
, 90);
2510 nextword
= get_num (&opP
->disp
, 0);
2511 if (isvar (&opP
->disp
))
2512 add_fix (s
[1], &opP
->disp
, 0, 0);
2516 if (!isbyte (nextword
))
2517 opP
->error
= _("operand out of range");
2522 if (!isword (nextword
))
2523 opP
->error
= _("operand out of range");
2528 if (!issword (nextword
))
2529 opP
->error
= _("operand out of range");
2534 addword (nextword
>> 16);
2561 /* We gotta put out some float. */
2562 if (op (&opP
->disp
) != O_big
)
2567 /* Can other cases happen here? */
2568 if (op (&opP
->disp
) != O_constant
)
2571 val
= (valueT
) offs (&opP
->disp
);
2575 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2576 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2580 offs (&opP
->disp
) = gencnt
;
2582 if (offs (&opP
->disp
) > 0)
2584 if (offs (&opP
->disp
) > baseo
)
2586 as_warn (_("Bignum too big for %c format; truncated"),
2588 offs (&opP
->disp
) = baseo
;
2590 baseo
-= offs (&opP
->disp
);
2593 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
2594 offs (&opP
->disp
)--;
2599 gen_to_words (words
, baseo
, (long) outro
);
2600 for (wordp
= words
; baseo
--; wordp
++)
2604 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2607 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2610 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2613 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2616 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2620 nextword
= get_num (&opP
->disp
, 90);
2622 /* Convert mode 5 addressing with a zero offset into
2623 mode 2 addressing to reduce the instruction size by a
2625 if (! isvar (&opP
->disp
)
2627 && (opP
->disp
.size
== SIZE_UNSPEC
)
2628 && (opP
->reg
>= ADDR0
)
2629 && (opP
->reg
<= ADDR7
))
2631 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2636 && ! isvar (&opP
->disp
)
2639 opP
->disp
.exp
.X_op
= O_symbol
;
2640 opP
->disp
.exp
.X_add_symbol
=
2641 section_symbol (absolute_section
);
2644 /* Force into index mode. Hope this works. */
2646 /* We do the first bit for 32-bit displacements, and the
2647 second bit for 16 bit ones. It is possible that we
2648 should make the default be WORD instead of LONG, but
2649 I think that'd break GCC, so we put up with a little
2650 inefficiency for the sake of working output. */
2652 if (!issword (nextword
)
2653 || (isvar (&opP
->disp
)
2654 && ((opP
->disp
.size
== SIZE_UNSPEC
2655 && flag_short_refs
== 0
2656 && cpu_of_arch (current_architecture
) >= m68020
2657 && ! arch_coldfire_p (current_architecture
))
2658 || opP
->disp
.size
== SIZE_LONG
)))
2660 if (cpu_of_arch (current_architecture
) < m68020
2661 || arch_coldfire_p (current_architecture
))
2663 _("displacement too large for this architecture; needs 68020 or higher");
2665 tmpreg
= 0x3B; /* 7.3 */
2667 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2668 if (isvar (&opP
->disp
))
2672 if (opP
->disp
.size
== SIZE_LONG
2674 /* If the displacement needs pic
2675 relocation it cannot be relaxed. */
2676 || opP
->disp
.pic_reloc
!= pic_none
2681 add_fix ('l', &opP
->disp
, 1, 2);
2685 add_frag (adds (&opP
->disp
),
2686 SEXT (offs (&opP
->disp
)),
2687 TAB (PCREL1632
, SZ_UNDEF
));
2694 add_fix ('l', &opP
->disp
, 0, 0);
2699 addword (nextword
>> 16);
2704 tmpreg
= 0x3A; /* 7.2 */
2706 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2708 if (isvar (&opP
->disp
))
2712 add_fix ('w', &opP
->disp
, 1, 0);
2715 add_fix ('w', &opP
->disp
, 0, 0);
2725 baseo
= get_num (&opP
->disp
, 90);
2726 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2727 outro
= get_num (&opP
->odisp
, 90);
2728 /* Figure out the `addressing mode'.
2729 Also turn on the BASE_DISABLE bit, if needed. */
2730 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2732 tmpreg
= 0x3b; /* 7.3 */
2733 if (opP
->reg
== ZPC
)
2736 else if (opP
->reg
== 0)
2739 tmpreg
= 0x30; /* 6.garbage */
2741 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2744 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2747 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2749 siz1
= opP
->disp
.size
;
2750 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2751 siz2
= opP
->odisp
.size
;
2755 /* Index register stuff. */
2756 if (opP
->index
.reg
!= 0
2757 && opP
->index
.reg
>= DATA
2758 && opP
->index
.reg
<= ADDR7
)
2760 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2762 if (opP
->index
.size
== SIZE_LONG
2763 || (opP
->index
.size
== SIZE_UNSPEC
2764 && m68k_index_width_default
== SIZE_LONG
))
2767 if ((opP
->index
.scale
!= 1
2768 && cpu_of_arch (current_architecture
) < m68020
)
2769 || (opP
->index
.scale
== 8
2770 && (arch_coldfire_p (current_architecture
)
2771 && !arch_coldfire_fpu (current_architecture
))))
2774 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2777 if (arch_coldfire_p (current_architecture
)
2778 && opP
->index
.size
== SIZE_WORD
)
2779 opP
->error
= _("invalid index size for coldfire");
2781 switch (opP
->index
.scale
)
2798 GET US OUT OF HERE! */
2800 /* Must be INDEX, with an index register. Address
2801 register cannot be ZERO-PC, and either :b was
2802 forced, or we know it will fit. For a 68000 or
2803 68010, force this mode anyways, because the
2804 larger modes aren't supported. */
2805 if (opP
->mode
== BASE
2806 && ((opP
->reg
>= ADDR0
2807 && opP
->reg
<= ADDR7
)
2810 if (siz1
== SIZE_BYTE
2811 || cpu_of_arch (current_architecture
) < m68020
2812 || arch_coldfire_p (current_architecture
)
2813 || (siz1
== SIZE_UNSPEC
2814 && ! isvar (&opP
->disp
)
2815 && issbyte (baseo
)))
2817 nextword
+= baseo
& 0xff;
2819 if (isvar (&opP
->disp
))
2821 /* Do a byte relocation. If it doesn't
2822 fit (possible on m68000) let the
2823 fixup processing complain later. */
2825 add_fix ('B', &opP
->disp
, 1, 1);
2827 add_fix ('B', &opP
->disp
, 0, 0);
2829 else if (siz1
!= SIZE_BYTE
)
2831 if (siz1
!= SIZE_UNSPEC
)
2832 as_warn (_("Forcing byte displacement"));
2833 if (! issbyte (baseo
))
2834 opP
->error
= _("byte displacement out of range");
2839 else if (siz1
== SIZE_UNSPEC
2841 && isvar (&opP
->disp
)
2842 && subs (&opP
->disp
) == NULL
2844 /* If the displacement needs pic
2845 relocation it cannot be relaxed. */
2846 && opP
->disp
.pic_reloc
== pic_none
2850 /* The code in md_convert_frag_1 needs to be
2851 able to adjust nextword. Call frag_grow
2852 to ensure that we have enough space in
2853 the frag obstack to make all the bytes
2856 nextword
+= baseo
& 0xff;
2858 add_frag (adds (&opP
->disp
),
2859 SEXT (offs (&opP
->disp
)),
2860 TAB (PCINDEX
, SZ_UNDEF
));
2868 nextword
|= 0x40; /* No index reg. */
2869 if (opP
->index
.reg
>= ZDATA0
2870 && opP
->index
.reg
<= ZDATA7
)
2871 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2872 else if (opP
->index
.reg
>= ZADDR0
2873 || opP
->index
.reg
<= ZADDR7
)
2874 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2877 /* It isn't simple. */
2879 if (cpu_of_arch (current_architecture
) < m68020
2880 || arch_coldfire_p (current_architecture
))
2882 _("invalid operand mode for this architecture; needs 68020 or higher");
2885 /* If the guy specified a width, we assume that it is
2886 wide enough. Maybe it isn't. If so, we lose. */
2890 if (isvar (&opP
->disp
)
2892 : ! issword (baseo
))
2897 else if (! isvar (&opP
->disp
) && baseo
== 0)
2906 as_warn (_(":b not permitted; defaulting to :w"));
2916 /* Figure out inner displacement stuff. */
2917 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2919 if (cpu_of_arch (current_architecture
) & cpu32
)
2920 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2924 if (isvar (&opP
->odisp
)
2926 : ! issword (outro
))
2931 else if (! isvar (&opP
->odisp
) && outro
== 0)
2940 as_warn (_(":b not permitted; defaulting to :w"));
2949 if (opP
->mode
== POST
2950 && (nextword
& 0x40) == 0)
2955 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2957 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2958 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2960 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2962 if (siz1
== SIZE_LONG
)
2963 addword (baseo
>> 16);
2964 if (siz1
!= SIZE_UNSPEC
)
2967 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2968 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2969 if (siz2
== SIZE_LONG
)
2970 addword (outro
>> 16);
2971 if (siz2
!= SIZE_UNSPEC
)
2977 nextword
= get_num (&opP
->disp
, 90);
2978 switch (opP
->disp
.size
)
2983 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2985 tmpreg
= 0x38; /* 7.0 */
2989 if (isvar (&opP
->disp
)
2990 && !subs (&opP
->disp
)
2991 && adds (&opP
->disp
)
2993 /* If the displacement needs pic relocation it
2994 cannot be relaxed. */
2995 && opP
->disp
.pic_reloc
== pic_none
2998 && !strchr ("~%&$?", s
[0]))
3000 tmpreg
= 0x3A; /* 7.2 */
3001 add_frag (adds (&opP
->disp
),
3002 SEXT (offs (&opP
->disp
)),
3003 TAB (ABSTOPCREL
, SZ_UNDEF
));
3006 /* Fall through into long. */
3008 if (isvar (&opP
->disp
))
3009 add_fix ('l', &opP
->disp
, 0, 0);
3011 tmpreg
= 0x39;/* 7.1 mode */
3012 addword (nextword
>> 16);
3017 as_bad (_("unsupported byte value; use a different suffix"));
3021 if (isvar (&opP
->disp
))
3022 add_fix ('w', &opP
->disp
, 0, 0);
3024 tmpreg
= 0x38;/* 7.0 mode */
3032 as_bad (_("unknown/incorrect operand"));
3036 /* If s[0] is '4', then this is for the mac instructions
3037 that can have a trailing_ampersand set. If so, set 0x100
3038 bit on tmpreg so install_gen_operand can check for it and
3039 set the appropriate bit (word2, bit 5). */
3042 if (opP
->trailing_ampersand
)
3045 install_gen_operand (s
[1], tmpreg
);
3051 { /* JF: I hate floating point! */
3066 tmpreg
= get_num (&opP
->disp
, tmpreg
);
3067 if (isvar (&opP
->disp
))
3068 add_fix (s
[1], &opP
->disp
, 0, 0);
3071 case 'b': /* Danger: These do no check for
3072 certain types of overflow.
3074 if (!isbyte (tmpreg
))
3075 opP
->error
= _("out of range");
3076 insop (tmpreg
, opcode
);
3077 if (isvar (&opP
->disp
))
3078 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
3079 (opcode
->m_codenum
) * 2 + 1;
3082 if (!issbyte (tmpreg
))
3083 opP
->error
= _("out of range");
3084 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
3085 if (isvar (&opP
->disp
))
3086 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
3089 if (!isword (tmpreg
))
3090 opP
->error
= _("out of range");
3091 insop (tmpreg
, opcode
);
3092 if (isvar (&opP
->disp
))
3093 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
3096 if (!issword (tmpreg
))
3097 opP
->error
= _("out of range");
3098 insop (tmpreg
, opcode
);
3099 if (isvar (&opP
->disp
))
3100 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
3103 /* Because of the way insop works, we put these two out
3105 insop (tmpreg
, opcode
);
3106 insop (tmpreg
>> 16, opcode
);
3107 if (isvar (&opP
->disp
))
3108 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
3115 install_operand (s
[1], tmpreg
);
3126 install_operand (s
[1], opP
->reg
- ADDR
);
3130 tmpreg
= get_num (&opP
->disp
, 90);
3135 add_fix ('B', &opP
->disp
, 1, -1);
3138 add_fix ('w', &opP
->disp
, 1, 0);
3143 the_ins
.opcode
[0] |= 0xff;
3144 add_fix ('l', &opP
->disp
, 1, 0);
3148 case 'g': /* Conditional branch */
3149 have_disp
= HAVE_LONG_CALL (current_architecture
);
3152 case 'b': /* Unconditional branch */
3153 have_disp
= HAVE_LONG_BRANCH (current_architecture
);
3154 use_pl
= LONG_BRANCH_VIA_COND (current_architecture
);
3157 case 's': /* Unconditional subroutine */
3158 have_disp
= HAVE_LONG_CALL (current_architecture
);
3161 if (subs (&opP
->disp
) /* We can't relax it. */
3163 /* If the displacement needs pic relocation it cannot be
3165 || opP
->disp
.pic_reloc
!= pic_none
3170 as_warn (_("Can't use long branches on this architecture"));
3174 /* This could either be a symbol, or an absolute
3175 address. If it's an absolute address, turn it into
3176 an absolute jump right here and keep it out of the
3178 if (adds (&opP
->disp
) == 0)
3180 if (the_ins
.opcode
[0] == 0x6000) /* jbra */
3181 the_ins
.opcode
[0] = 0x4EF9;
3182 else if (the_ins
.opcode
[0] == 0x6100) /* jbsr */
3183 the_ins
.opcode
[0] = 0x4EB9;
3186 the_ins
.opcode
[0] ^= 0x0100;
3187 the_ins
.opcode
[0] |= 0x0006;
3190 add_fix ('l', &opP
->disp
, 0, 0);
3196 /* Now we know it's going into the relaxer. Now figure
3197 out which mode. We try in this order of preference:
3198 long branch, absolute jump, byte/word branches only. */
3200 add_frag (adds (&opP
->disp
),
3201 SEXT (offs (&opP
->disp
)),
3202 TAB (BRANCHBWL
, SZ_UNDEF
));
3203 else if (! flag_keep_pcrel
)
3205 if ((the_ins
.opcode
[0] == 0x6000)
3206 || (the_ins
.opcode
[0] == 0x6100))
3207 add_frag (adds (&opP
->disp
),
3208 SEXT (offs (&opP
->disp
)),
3209 TAB (BRABSJUNC
, SZ_UNDEF
));
3211 add_frag (adds (&opP
->disp
),
3212 SEXT (offs (&opP
->disp
)),
3213 TAB (BRABSJCOND
, SZ_UNDEF
));
3216 add_frag (adds (&opP
->disp
),
3217 SEXT (offs (&opP
->disp
)),
3218 (use_pl
? TAB (BRANCHBWPL
, SZ_UNDEF
)
3219 : TAB (BRANCHBW
, SZ_UNDEF
)));
3222 if (isvar (&opP
->disp
))
3224 /* Check for DBcc instructions. We can relax them,
3225 but only if we have long branches and/or absolute
3227 if (((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
3228 && (HAVE_LONG_BRANCH (current_architecture
)
3229 || ! flag_keep_pcrel
))
3231 if (HAVE_LONG_BRANCH (current_architecture
))
3232 add_frag (adds (&opP
->disp
),
3233 SEXT (offs (&opP
->disp
)),
3234 TAB (DBCCLBR
, SZ_UNDEF
));
3236 add_frag (adds (&opP
->disp
),
3237 SEXT (offs (&opP
->disp
)),
3238 TAB (DBCCABSJ
, SZ_UNDEF
));
3241 add_fix ('w', &opP
->disp
, 1, 0);
3245 case 'C': /* Fixed size LONG coproc branches. */
3246 add_fix ('l', &opP
->disp
, 1, 0);
3250 case 'c': /* Var size Coprocesssor branches. */
3251 if (subs (&opP
->disp
) || (adds (&opP
->disp
) == 0))
3253 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
3254 add_fix ('l', &opP
->disp
, 1, 0);
3259 add_frag (adds (&opP
->disp
),
3260 SEXT (offs (&opP
->disp
)),
3261 TAB (FBRANCH
, SZ_UNDEF
));
3268 case 'C': /* Ignore it. */
3271 case 'd': /* JF this is a kludge. */
3272 install_operand ('s', opP
->reg
- ADDR
);
3273 tmpreg
= get_num (&opP
->disp
, 90);
3274 if (!issword (tmpreg
))
3276 as_warn (_("Expression out of range, using 0"));
3283 install_operand (s
[1], opP
->reg
- DATA
);
3286 case 'e': /* EMAC ACCx, reg/reg. */
3287 install_operand (s
[1], opP
->reg
- ACC
);
3290 case 'E': /* Ignore it. */
3294 install_operand (s
[1], opP
->reg
- FP0
);
3297 case 'g': /* EMAC ACCEXTx. */
3298 install_operand (s
[1], opP
->reg
- ACCEXT01
);
3301 case 'G': /* Ignore it. */
3306 tmpreg
= opP
->reg
- COP0
;
3307 install_operand (s
[1], tmpreg
);
3310 case 'i': /* MAC/EMAC scale factor. */
3311 install_operand (s
[1], opP
->mode
== LSH
? 0x1 : 0x3);
3314 case 'J': /* JF foo. */
3357 tmpreg
= 0x00c + (opP
->reg
- ACR4
);
3464 install_operand (s
[1], tmpreg
);
3468 tmpreg
= get_num (&opP
->disp
, 55);
3469 install_operand (s
[1], tmpreg
& 0x7f);
3476 if (tmpreg
& 0x7FF0000)
3477 as_bad (_("Floating point register in register list"));
3478 insop (reverse_16_bits (tmpreg
), opcode
);
3482 if (tmpreg
& 0x700FFFF)
3483 as_bad (_("Wrong register in floating-point reglist"));
3484 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
3492 if (tmpreg
& 0x7FF0000)
3493 as_bad (_("Floating point register in register list"));
3494 insop (tmpreg
, opcode
);
3496 else if (s
[1] == '8')
3498 if (tmpreg
& 0x0FFFFFF)
3499 as_bad (_("incorrect register in reglist"));
3500 install_operand (s
[1], tmpreg
>> 24);
3504 if (tmpreg
& 0x700FFFF)
3505 as_bad (_("wrong register in floating-point reglist"));
3507 install_operand (s
[1], tmpreg
>> 16);
3512 install_operand (s
[1], get_num (&opP
->disp
, 60));
3516 tmpreg
= ((opP
->mode
== DREG
)
3517 ? 0x20 + (int) (opP
->reg
- DATA
)
3518 : (get_num (&opP
->disp
, 40) & 0x1F));
3519 install_operand (s
[1], tmpreg
);
3523 tmpreg
= get_num (&opP
->disp
, 10);
3526 install_operand (s
[1], tmpreg
);
3530 /* This depends on the fact that ADDR registers are eight
3531 more than their corresponding DATA regs, so the result
3532 will have the ADDR_REG bit set. */
3533 install_operand (s
[1], opP
->reg
- DATA
);
3537 if (opP
->mode
== AINDR
)
3538 install_operand (s
[1], opP
->reg
- DATA
);
3540 install_operand (s
[1], opP
->index
.reg
- DATA
);
3544 if (opP
->reg
== FPI
)
3546 else if (opP
->reg
== FPS
)
3548 else if (opP
->reg
== FPC
)
3552 install_operand (s
[1], tmpreg
);
3555 case 'S': /* Ignore it. */
3559 install_operand (s
[1], get_num (&opP
->disp
, 30));
3562 case 'U': /* Ignore it. */
3581 as_fatal (_("failed sanity check"));
3582 } /* switch on cache token. */
3583 install_operand (s
[1], tmpreg
);
3586 /* JF: These are out of order, I fear. */
3599 install_operand (s
[1], tmpreg
);
3625 install_operand (s
[1], tmpreg
);
3629 if (opP
->reg
== VAL
)
3648 install_operand (s
[1], tmpreg
);
3662 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3673 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3679 install_operand (s
[1], tmpreg
);
3682 know (opP
->reg
== PSR
);
3685 know (opP
->reg
== PCSR
);
3700 install_operand (s
[1], tmpreg
);
3703 tmpreg
= get_num (&opP
->disp
, 20);
3704 install_operand (s
[1], tmpreg
);
3706 case '_': /* used only for move16 absolute 32-bit address. */
3707 if (isvar (&opP
->disp
))
3708 add_fix ('l', &opP
->disp
, 0, 0);
3709 tmpreg
= get_num (&opP
->disp
, 90);
3710 addword (tmpreg
>> 16);
3711 addword (tmpreg
& 0xFFFF);
3714 install_operand (s
[1], opP
->reg
- DATA0L
);
3715 opP
->reg
-= (DATA0L
);
3716 opP
->reg
&= 0x0F; /* remove upper/lower bit. */
3719 tmpreg
= get_num (&opP
->disp
, 80);
3722 install_operand (s
[1], tmpreg
);
3725 tmpreg
= get_num (&opP
->disp
, 10);
3726 install_operand (s
[1], tmpreg
- 1);
3729 tmpreg
= get_num (&opP
->disp
, 65);
3730 install_operand (s
[1], tmpreg
);
3737 /* By the time whe get here (FINALLY) the_ins contains the complete
3738 instruction, ready to be emitted. . . */
3742 reverse_16_bits (int in
)
3747 static int mask
[16] =
3749 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3750 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3752 for (n
= 0; n
< 16; n
++)
3755 out
|= mask
[15 - n
];
3758 } /* reverse_16_bits() */
3761 reverse_8_bits (int in
)
3766 static int mask
[8] =
3768 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3771 for (n
= 0; n
< 8; n
++)
3777 } /* reverse_8_bits() */
3779 /* Cause an extra frag to be generated here, inserting up to
3780 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3781 generated; its primary type is rs_machine_dependent.
3783 The TYPE parameter is also used by md_convert_frag_1 and
3784 md_estimate_size_before_relax. The appropriate type of fixup will
3785 be emitted by md_convert_frag_1.
3787 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3789 install_operand (int mode
, int val
)
3794 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge. */
3797 the_ins
.opcode
[0] |= val
<< 9;
3800 the_ins
.opcode
[1] |= val
<< 9;
3803 the_ins
.opcode
[1] |= val
<< 12;
3806 the_ins
.opcode
[1] |= val
<< 6;
3809 the_ins
.opcode
[1] |= val
;
3812 the_ins
.opcode
[2] |= val
<< 12;
3815 the_ins
.opcode
[2] |= val
<< 6;
3818 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3819 three words long! */
3821 the_ins
.opcode
[2] |= val
;
3824 the_ins
.opcode
[1] |= val
<< 7;
3827 the_ins
.opcode
[1] |= val
<< 10;
3831 the_ins
.opcode
[1] |= val
<< 5;
3836 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3839 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3842 the_ins
.opcode
[0] |= val
= 0xff;
3845 the_ins
.opcode
[0] |= val
<< 9;
3848 the_ins
.opcode
[1] |= val
;
3851 the_ins
.opcode
[1] |= val
;
3852 the_ins
.numo
++; /* What a hack. */
3855 the_ins
.opcode
[1] |= val
<< 4;
3863 the_ins
.opcode
[0] |= (val
<< 6);
3866 the_ins
.opcode
[1] = (val
>> 16);
3867 the_ins
.opcode
[2] = val
& 0xffff;
3870 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3871 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3872 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3874 case 'n': /* MAC/EMAC Rx on !load. */
3875 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3876 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3877 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3879 case 'o': /* MAC/EMAC Rx on load. */
3880 the_ins
.opcode
[1] |= val
<< 12;
3881 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3883 case 'M': /* MAC/EMAC Ry on !load. */
3884 the_ins
.opcode
[0] |= (val
& 0xF);
3885 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3887 case 'N': /* MAC/EMAC Ry on load. */
3888 the_ins
.opcode
[1] |= (val
& 0xF);
3889 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3892 the_ins
.opcode
[1] |= ((val
!= 1) << 10);
3895 the_ins
.opcode
[0] |= ((val
& 0x3) << 9);
3898 the_ins
.opcode
[0] |= ((val
& 0x3) << 0);
3900 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3901 the_ins
.opcode
[0] |= ((~val
& 0x1) << 7);
3902 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3904 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3905 the_ins
.opcode
[0] |= ((val
& 0x1) << 7);
3906 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3909 the_ins
.opcode
[1] |= ((val
& 0x3) << 9);
3912 the_ins
.opcode
[0] |= (val
& 0x1) <<10;
3916 as_fatal (_("failed sanity check."));
3921 install_gen_operand (int mode
, int val
)
3925 case '/': /* Special for mask loads for mac/msac insns with
3926 possible mask; trailing_ampersend set in bit 8. */
3927 the_ins
.opcode
[0] |= (val
& 0x3f);
3928 the_ins
.opcode
[1] |= (((val
& 0x100) >> 8) << 5);
3931 the_ins
.opcode
[0] |= val
;
3934 /* This is a kludge!!! */
3935 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3944 the_ins
.opcode
[0] |= val
;
3946 /* more stuff goes here. */
3948 as_fatal (_("failed sanity check."));
3952 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3953 then deal with the bitfield hack. */
3956 crack_operand (char *str
, struct m68k_op
*opP
)
3968 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3974 else if (*str
== ')')
3978 opP
->error
= _("Extra )");
3984 if (flag_mri
&& *str
== '\'')
3985 inquote
= ! inquote
;
3987 if (!*str
&& parens
)
3989 opP
->error
= _("Missing )");
3994 if (m68k_ip_op (beg_str
, opP
) != 0)
4001 c
= *++str
; /* JF bitfield hack. */
4006 as_bad (_("Missing operand"));
4009 /* Detect MRI REG symbols and convert them to REGLSTs. */
4010 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
4013 opP
->mask
= ~(int)opP
->reg
;
4020 /* This is the guts of the machine-dependent assembler. STR points to a
4021 machine dependent instruction. This function is supposed to emit
4022 the frags/bytes it assembles to.
4026 insert_reg (const char *regname
, int regnum
)
4031 #ifdef REGISTER_PREFIX
4032 if (!flag_reg_prefix_optional
)
4034 buf
[0] = REGISTER_PREFIX
;
4035 strcpy (buf
+ 1, regname
);
4040 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
4041 &zero_address_frag
));
4043 for (i
= 0; regname
[i
]; i
++)
4044 buf
[i
] = TOUPPER (regname
[i
]);
4047 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
4048 &zero_address_frag
));
4057 static const struct init_entry init_table
[] =
4117 { "accext01", ACCEXT01
},
4118 { "accext23", ACCEXT23
},
4122 /* Control registers. */
4123 { "sfc", SFC
}, /* Source Function Code. */
4125 { "dfc", DFC
}, /* Destination Function Code. */
4127 { "cacr", CACR
}, /* Cache Control Register. */
4128 { "caar", CAAR
}, /* Cache Address Register. */
4129 { "cpucr", CPUCR
}, /* CPU Control Register. */
4131 { "usp", USP
}, /* User Stack Pointer. */
4132 { "vbr", VBR
}, /* Vector Base Register. */
4133 { "msp", MSP
}, /* Master Stack Pointer. */
4134 { "isp", ISP
}, /* Interrupt Stack Pointer. */
4136 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0. */
4137 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1. */
4138 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0. */
4139 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1. */
4141 /* 68ec040 versions of same */
4142 { "iacr0", ITT0
}, /* Instruction Access Control Register 0. */
4143 { "iacr1", ITT1
}, /* Instruction Access Control Register 0. */
4144 { "dacr0", DTT0
}, /* Data Access Control Register 0. */
4145 { "dacr1", DTT1
}, /* Data Access Control Register 0. */
4147 /* Coldfire versions of same. The ColdFire programmer's reference
4148 manual indicated that the order is 2,3,0,1, but Ken Rose
4149 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
4150 { "acr0", ACR0
}, /* Access Control Unit 0. */
4151 { "acr1", ACR1
}, /* Access Control Unit 1. */
4152 { "acr2", ACR2
}, /* Access Control Unit 2. */
4153 { "acr3", ACR3
}, /* Access Control Unit 3. */
4154 { "acr4", ACR4
}, /* Access Control Unit 4. */
4155 { "acr5", ACR5
}, /* Access Control Unit 5. */
4156 { "acr6", ACR6
}, /* Access Control Unit 6. */
4157 { "acr7", ACR7
}, /* Access Control Unit 7. */
4159 { "tc", TC
}, /* MMU Translation Control Register. */
4163 { "mmusr", MMUSR
}, /* MMU Status Register. */
4164 { "srp", SRP
}, /* User Root Pointer. */
4165 { "urp", URP
}, /* Supervisor Root Pointer. */
4168 { "mmubar", MMUBAR
},
4171 { "rombar", ROMBAR
}, /* ROM Base Address Register. */
4172 { "rambar0", RAMBAR0
}, /* ROM Base Address Register. */
4173 { "rambar1", RAMBAR1
}, /* ROM Base Address Register. */
4174 { "mbar", MBAR
}, /* Module Base Address Register. */
4176 { "mbar0", MBAR0
}, /* mcfv4e registers. */
4177 { "mbar1", MBAR1
}, /* mcfv4e registers. */
4178 { "rombar0", ROMBAR0
}, /* mcfv4e registers. */
4179 { "rombar1", ROMBAR1
}, /* mcfv4e registers. */
4180 { "mpcr", MPCR
}, /* mcfv4e registers. */
4181 { "edrambar", EDRAMBAR
}, /* mcfv4e registers. */
4182 { "secmbar", SECMBAR
}, /* mcfv4e registers. */
4183 { "asid", TC
}, /* mcfv4e registers. */
4184 { "mmubar", BUSCR
}, /* mcfv4e registers. */
4185 { "pcr1u0", PCR1U0
}, /* mcfv4e registers. */
4186 { "pcr1l0", PCR1L0
}, /* mcfv4e registers. */
4187 { "pcr2u0", PCR2U0
}, /* mcfv4e registers. */
4188 { "pcr2l0", PCR2L0
}, /* mcfv4e registers. */
4189 { "pcr3u0", PCR3U0
}, /* mcfv4e registers. */
4190 { "pcr3l0", PCR3L0
}, /* mcfv4e registers. */
4191 { "pcr1u1", PCR1U1
}, /* mcfv4e registers. */
4192 { "pcr1l1", PCR1L1
}, /* mcfv4e registers. */
4193 { "pcr2u1", PCR2U1
}, /* mcfv4e registers. */
4194 { "pcr2l1", PCR2L1
}, /* mcfv4e registers. */
4195 { "pcr3u1", PCR3U1
}, /* mcfv4e registers. */
4196 { "pcr3l1", PCR3L1
}, /* mcfv4e registers. */
4198 { "flashbar", FLASHBAR
}, /* mcf528x registers. */
4199 { "rambar", RAMBAR
}, /* mcf528x registers. */
4201 { "mbar2", MBAR2
}, /* mcf5249 registers. */
4203 { "rgpiobar", RGPIOBAR
}, /* mcf54418 registers. */
4205 { "cac", CAC
}, /* fido registers. */
4206 { "mbb", MBO
}, /* fido registers (obsolete). */
4207 { "mbo", MBO
}, /* fido registers. */
4208 /* End of control registers. */
4242 /* 68ec030 versions of same. */
4245 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4248 /* Suppressed data and address registers. */
4266 /* Upper and lower data and address registers, used by macw and msacw. */
4307 init_regtable (void)
4310 for (i
= 0; init_table
[i
].name
; i
++)
4311 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
4315 md_assemble (char *str
)
4322 int shorts_this_frag
;
4325 if (!selected_cpu
&& !selected_arch
)
4327 /* We've not selected an architecture yet. Set the default
4328 now. We do this lazily so that an initial .cpu or .arch directive
4330 if (!m68k_set_cpu (TARGET_CPU
, 1, 1))
4331 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU
);
4336 /* In MRI mode, the instruction and operands are separated by a
4337 space. Anything following the operands is a comment. The label
4338 has already been removed. */
4346 for (s
= str
; *s
!= '\0'; s
++)
4348 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
4366 inquote
= ! inquote
;
4371 memset (&the_ins
, '\0', sizeof (the_ins
));
4376 for (n
= 0; n
< the_ins
.numargs
; n
++)
4377 if (the_ins
.operands
[n
].error
)
4379 er
= the_ins
.operands
[n
].error
;
4385 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
4389 /* If there is a current label, record that it marks an instruction. */
4390 if (current_label
!= NULL
)
4392 current_label
->text
= 1;
4393 current_label
= NULL
;
4397 /* Tie dwarf2 debug info to the address at the start of the insn. */
4398 dwarf2_emit_insn (0);
4401 if (the_ins
.nfrag
== 0)
4403 /* No frag hacking involved; just put it out. */
4404 toP
= frag_more (2 * the_ins
.numo
);
4405 fromP
= &the_ins
.opcode
[0];
4406 for (m
= the_ins
.numo
; m
; --m
)
4408 md_number_to_chars (toP
, (long) (*fromP
), 2);
4412 /* Put out symbol-dependent info. */
4413 for (m
= 0; m
< the_ins
.nrel
; m
++)
4415 switch (the_ins
.reloc
[m
].wid
)
4434 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4435 the_ins
.reloc
[m
].wid
);
4438 fixP
= fix_new_exp (frag_now
,
4439 ((toP
- frag_now
->fr_literal
)
4440 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4442 &the_ins
.reloc
[m
].exp
,
4443 the_ins
.reloc
[m
].pcrel
,
4444 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
4445 the_ins
.reloc
[m
].pic_reloc
));
4446 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4447 if (the_ins
.reloc
[m
].wid
== 'B')
4448 fixP
->fx_signed
= 1;
4453 /* There's some frag hacking. */
4455 /* Calculate the max frag size. */
4458 wid
= 2 * the_ins
.fragb
[0].fragoff
;
4459 for (n
= 1; n
< the_ins
.nfrag
; n
++)
4460 wid
+= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4461 /* frag_var part. */
4462 wid
+= FRAG_VAR_SIZE
;
4463 /* Make sure the whole insn fits in one chunk, in particular that
4464 the var part is attached, as we access one byte before the
4465 variable frag for byte branches. */
4469 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
4474 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
4476 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4477 toP
= frag_more (wid
);
4479 shorts_this_frag
= 0;
4480 for (m
= wid
/ 2; m
; --m
)
4482 md_number_to_chars (toP
, (long) (*fromP
), 2);
4487 for (m
= 0; m
< the_ins
.nrel
; m
++)
4489 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
4491 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
4494 wid
= the_ins
.reloc
[m
].wid
;
4497 the_ins
.reloc
[m
].wid
= 0;
4498 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4500 fixP
= fix_new_exp (frag_now
,
4501 ((toP
- frag_now
->fr_literal
)
4502 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4504 &the_ins
.reloc
[m
].exp
,
4505 the_ins
.reloc
[m
].pcrel
,
4506 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4507 the_ins
.reloc
[m
].pic_reloc
));
4508 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4510 (void) frag_var (rs_machine_dependent
, FRAG_VAR_SIZE
, 0,
4511 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
4512 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
4514 gas_assert (the_ins
.nfrag
>= 1);
4515 n
= the_ins
.numo
- the_ins
.fragb
[the_ins
.nfrag
- 1].fragoff
;
4516 shorts_this_frag
= 0;
4519 toP
= frag_more (n
* 2);
4522 md_number_to_chars (toP
, (long) (*fromP
), 2);
4528 for (m
= 0; m
< the_ins
.nrel
; m
++)
4532 wid
= the_ins
.reloc
[m
].wid
;
4535 the_ins
.reloc
[m
].wid
= 0;
4536 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4538 fixP
= fix_new_exp (frag_now
,
4539 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
4540 - shorts_this_frag
* 2),
4542 &the_ins
.reloc
[m
].exp
,
4543 the_ins
.reloc
[m
].pcrel
,
4544 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4545 the_ins
.reloc
[m
].pic_reloc
));
4546 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4550 /* Comparison function used by qsort to rank the opcode entries by name. */
4553 m68k_compare_opcode (const void * v1
, const void * v2
)
4555 struct m68k_opcode
* op1
, * op2
;
4561 op1
= *(struct m68k_opcode
**) v1
;
4562 op2
= *(struct m68k_opcode
**) v2
;
4564 /* Compare the two names. If different, return the comparison.
4565 If the same, return the order they are in the opcode table. */
4566 ret
= strcmp (op1
->name
, op2
->name
);
4577 const struct m68k_opcode
*ins
;
4578 struct m68k_incant
*hack
, *slak
;
4579 const char *retval
= 0; /* Empty string, or error msg text. */
4582 /* Set up hash tables with 68000 instructions.
4583 similar to what the vax assembler does. */
4584 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4585 a copy of it at runtime, adding in the information we want but isn't
4586 there. I think it'd be better to have an awk script hack the table
4587 at compile time. Or even just xstr the table and use it as-is. But
4588 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4593 flag_reg_prefix_optional
= 1;
4595 if (! m68k_rel32_from_cmdline
)
4599 /* First sort the opcode table into alphabetical order to seperate
4600 the order that the assembler wants to see the opcodes from the
4601 order that the disassembler wants to see them. */
4602 m68k_sorted_opcodes
= XNEWVEC (const struct m68k_opcode
*, m68k_numopcodes
);
4604 for (i
= m68k_numopcodes
; i
--;)
4605 m68k_sorted_opcodes
[i
] = m68k_opcodes
+ i
;
4607 qsort (m68k_sorted_opcodes
, m68k_numopcodes
,
4608 sizeof (m68k_sorted_opcodes
[0]), m68k_compare_opcode
);
4610 op_hash
= hash_new ();
4612 obstack_begin (&robyn
, 4000);
4613 for (i
= 0; i
< m68k_numopcodes
; i
++)
4615 hack
= slak
= XOBNEW (&robyn
, struct m68k_incant
);
4618 ins
= m68k_sorted_opcodes
[i
];
4620 /* We must enter all insns into the table, because .arch and
4621 .cpu directives can change things. */
4622 slak
->m_operands
= ins
->args
;
4623 slak
->m_arch
= ins
->arch
;
4624 slak
->m_opcode
= ins
->opcode
;
4626 /* In most cases we can determine the number of opcode words
4627 by checking the second word of the mask. Unfortunately
4628 some instructions have 2 opcode words, but no fixed bits
4629 in the second word. A leading dot in the operands
4630 string also indicates 2 opcodes. */
4631 if (*slak
->m_operands
== '.')
4634 slak
->m_codenum
= 2;
4636 else if (ins
->match
& 0xffffL
)
4637 slak
->m_codenum
= 2;
4639 slak
->m_codenum
= 1;
4640 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
4642 if (i
+ 1 != m68k_numopcodes
4643 && !strcmp (ins
->name
, m68k_sorted_opcodes
[i
+ 1]->name
))
4645 slak
->m_next
= XOBNEW (&robyn
, struct m68k_incant
);
4650 slak
= slak
->m_next
;
4654 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
4656 as_fatal (_("Internal Error: Can't hash %s: %s"), ins
->name
, retval
);
4659 for (i
= 0; i
< m68k_numaliases
; i
++)
4661 const char *name
= m68k_opcode_aliases
[i
].primary
;
4662 const char *alias
= m68k_opcode_aliases
[i
].alias
;
4663 void *val
= hash_find (op_hash
, name
);
4666 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4667 retval
= hash_insert (op_hash
, alias
, val
);
4669 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4672 /* In MRI mode, all unsized branches are variable sized. Normally,
4673 they are word sized. */
4676 static struct m68k_opcode_alias mri_aliases
[] =
4697 i
< (int) (sizeof mri_aliases
/ sizeof mri_aliases
[0]);
4700 const char *name
= mri_aliases
[i
].primary
;
4701 const char *alias
= mri_aliases
[i
].alias
;
4702 void *val
= hash_find (op_hash
, name
);
4705 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4706 retval
= hash_jam (op_hash
, alias
, val
);
4708 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4712 for (i
= 0; i
< (int) sizeof (notend_table
); i
++)
4714 notend_table
[i
] = 0;
4715 alt_notend_table
[i
] = 0;
4718 notend_table
[','] = 1;
4719 notend_table
['{'] = 1;
4720 notend_table
['}'] = 1;
4721 alt_notend_table
['a'] = 1;
4722 alt_notend_table
['A'] = 1;
4723 alt_notend_table
['d'] = 1;
4724 alt_notend_table
['D'] = 1;
4725 alt_notend_table
['#'] = 1;
4726 alt_notend_table
['&'] = 1;
4727 alt_notend_table
['f'] = 1;
4728 alt_notend_table
['F'] = 1;
4729 #ifdef REGISTER_PREFIX
4730 alt_notend_table
[REGISTER_PREFIX
] = 1;
4733 /* We need to put '(' in alt_notend_table to handle
4734 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4735 alt_notend_table
['('] = 1;
4737 /* We need to put '@' in alt_notend_table to handle
4738 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4739 alt_notend_table
['@'] = 1;
4741 /* We need to put digits in alt_notend_table to handle
4742 bfextu %d0{24:1},%d0 */
4743 alt_notend_table
['0'] = 1;
4744 alt_notend_table
['1'] = 1;
4745 alt_notend_table
['2'] = 1;
4746 alt_notend_table
['3'] = 1;
4747 alt_notend_table
['4'] = 1;
4748 alt_notend_table
['5'] = 1;
4749 alt_notend_table
['6'] = 1;
4750 alt_notend_table
['7'] = 1;
4751 alt_notend_table
['8'] = 1;
4752 alt_notend_table
['9'] = 1;
4754 #ifndef MIT_SYNTAX_ONLY
4755 /* Insert pseudo ops, these have to go into the opcode table since
4756 gas expects pseudo ops to start with a dot. */
4760 while (mote_pseudo_table
[n
].poc_name
)
4762 hack
= XOBNEW (&robyn
, struct m68k_incant
);
4763 hash_insert (op_hash
,
4764 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
4765 hack
->m_operands
= 0;
4775 record_alignment (text_section
, 2);
4776 record_alignment (data_section
, 2);
4777 record_alignment (bss_section
, 2);
4782 /* This is called when a label is defined. */
4785 m68k_frob_label (symbolS
*sym
)
4787 struct label_line
*n
;
4789 n
= (struct label_line
*) xmalloc (sizeof *n
);
4792 n
->file
= as_where (&n
->line
);
4798 dwarf2_emit_label (sym
);
4802 /* This is called when a value that is not an instruction is emitted. */
4805 m68k_flush_pending_output (void)
4807 current_label
= NULL
;
4810 /* This is called at the end of the assembly, when the final value of
4811 the label is known. We warn if this is a text symbol aligned at an
4815 m68k_frob_symbol (symbolS
*sym
)
4817 if (S_GET_SEGMENT (sym
) == reg_section
4818 && (int) S_GET_VALUE (sym
) < 0)
4820 S_SET_SEGMENT (sym
, absolute_section
);
4821 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
4823 else if ((S_GET_VALUE (sym
) & 1) != 0)
4825 struct label_line
*l
;
4827 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4829 if (l
->label
== sym
)
4832 as_warn_where (l
->file
, l
->line
,
4833 _("text label `%s' aligned to odd boundary"),
4841 /* This is called if we go in or out of MRI mode because of the .mri
4845 m68k_mri_mode_change (int on
)
4849 if (! flag_reg_prefix_optional
)
4851 flag_reg_prefix_optional
= 1;
4852 #ifdef REGISTER_PREFIX
4857 if (! m68k_rel32_from_cmdline
)
4862 if (! reg_prefix_optional_seen
)
4864 #ifdef REGISTER_PREFIX_OPTIONAL
4865 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
4867 flag_reg_prefix_optional
= 0;
4869 #ifdef REGISTER_PREFIX
4874 if (! m68k_rel32_from_cmdline
)
4880 md_atof (int type
, char *litP
, int *sizeP
)
4882 return ieee_md_atof (type
, litP
, sizeP
, TRUE
);
4886 md_number_to_chars (char *buf
, valueT val
, int n
)
4888 number_to_chars_bigendian (buf
, val
, n
);
4892 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4894 offsetT val
= *valP
;
4895 addressT upper_limit
;
4896 offsetT lower_limit
;
4898 /* This is unnecessary but it convinces the native rs6000 compiler
4899 to generate the code we want. */
4900 char *buf
= fixP
->fx_frag
->fr_literal
;
4901 buf
+= fixP
->fx_where
;
4902 /* End ibm compiler workaround. */
4906 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4912 memset (buf
, 0, fixP
->fx_size
);
4913 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4915 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4916 && !S_IS_DEFINED (fixP
->fx_addsy
)
4917 && !S_IS_WEAK (fixP
->fx_addsy
))
4918 S_SET_WEAK (fixP
->fx_addsy
);
4920 switch (fixP
->fx_r_type
)
4922 case BFD_RELOC_68K_TLS_GD32
:
4923 case BFD_RELOC_68K_TLS_GD16
:
4924 case BFD_RELOC_68K_TLS_GD8
:
4925 case BFD_RELOC_68K_TLS_LDM32
:
4926 case BFD_RELOC_68K_TLS_LDM16
:
4927 case BFD_RELOC_68K_TLS_LDM8
:
4928 case BFD_RELOC_68K_TLS_LDO32
:
4929 case BFD_RELOC_68K_TLS_LDO16
:
4930 case BFD_RELOC_68K_TLS_LDO8
:
4931 case BFD_RELOC_68K_TLS_IE32
:
4932 case BFD_RELOC_68K_TLS_IE16
:
4933 case BFD_RELOC_68K_TLS_IE8
:
4934 case BFD_RELOC_68K_TLS_LE32
:
4935 case BFD_RELOC_68K_TLS_LE16
:
4936 case BFD_RELOC_68K_TLS_LE8
:
4937 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4946 #elif defined(OBJ_AOUT)
4947 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4948 if (fixP
->fx_addsy
&& S_IS_WEAK (fixP
->fx_addsy
))
4950 memset (buf
, 0, fixP
->fx_size
);
4951 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4956 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4957 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4960 switch (fixP
->fx_size
)
4962 /* The cast to offsetT below are necessary to make code
4963 correct for machines where ints are smaller than offsetT. */
4967 lower_limit
= - (offsetT
) 0x80;
4970 *buf
++ = (val
>> 8);
4972 upper_limit
= 0x7fff;
4973 lower_limit
= - (offsetT
) 0x8000;
4976 *buf
++ = (val
>> 24);
4977 *buf
++ = (val
>> 16);
4978 *buf
++ = (val
>> 8);
4980 upper_limit
= 0x7fffffff;
4981 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* Avoid constant overflow. */
4984 BAD_CASE (fixP
->fx_size
);
4987 /* Fix up a negative reloc. */
4988 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4990 fixP
->fx_addsy
= fixP
->fx_subsy
;
4991 fixP
->fx_subsy
= NULL
;
4995 /* For non-pc-relative values, it's conceivable we might get something
4996 like "0xff" for a byte field. So extend the upper part of the range
4997 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4998 so that we can do any range checking at all. */
4999 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
5000 upper_limit
= upper_limit
* 2 + 1;
5002 if ((addressT
) val
> upper_limit
5003 && (val
> 0 || val
< lower_limit
))
5004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5005 _("value %ld out of range"), (long)val
);
5007 /* A one byte PC-relative reloc means a short branch. We can't use
5008 a short branch with a value of 0 or -1, because those indicate
5009 different opcodes (branches with longer offsets). fixup_segment
5010 in write.c may have clobbered fx_pcrel, so we need to examine the
5013 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
5014 && fixP
->fx_size
== 1
5015 && (fixP
->fx_addsy
== NULL
5016 || S_IS_DEFINED (fixP
->fx_addsy
))
5017 && (val
== 0 || val
== -1))
5018 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5019 _("invalid byte branch offset"));
5022 /* *fragP has been relaxed to its final size, and now needs to have
5023 the bytes inside it modified to conform to the new size There is UGLY
5027 md_convert_frag_1 (fragS
*fragP
)
5032 /* Address in object code of the displacement. */
5033 int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
5035 /* Address in gas core of the place to store the displacement. */
5036 /* This convinces the native rs6000 compiler to generate the code we
5038 char *buffer_address
= fragP
->fr_literal
;
5039 buffer_address
+= fragP
->fr_fix
;
5040 /* End ibm compiler workaround. */
5042 /* The displacement of the address, from current location. */
5043 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
5044 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
5046 switch (fragP
->fr_subtype
)
5048 case TAB (BRANCHBWL
, BYTE
):
5049 case TAB (BRABSJUNC
, BYTE
):
5050 case TAB (BRABSJCOND
, BYTE
):
5051 case TAB (BRANCHBW
, BYTE
):
5052 case TAB (BRANCHBWPL
, BYTE
):
5053 know (issbyte (disp
));
5055 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5056 _("short branch with zero offset: use :w"));
5057 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
5058 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
5059 fixP
->fx_pcrel_adjust
= -1;
5061 case TAB (BRANCHBWL
, SHORT
):
5062 case TAB (BRABSJUNC
, SHORT
):
5063 case TAB (BRABSJCOND
, SHORT
):
5064 case TAB (BRANCHBW
, SHORT
):
5065 case TAB (BRANCHBWPL
, SHORT
):
5066 fragP
->fr_opcode
[1] = 0x00;
5067 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5068 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5071 case TAB (BRANCHBWL
, LONG
):
5072 fragP
->fr_opcode
[1] = (char) 0xFF;
5073 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5074 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5077 case TAB (BRANCHBWPL
, LONG
):
5078 /* Here we are converting an unconditional branch into a pair of
5079 conditional branches, in order to get the range. */
5080 fragP
->fr_opcode
[0] = 0x66; /* bne */
5081 fragP
->fr_opcode
[1] = 0xFF;
5082 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5083 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5084 fixP
->fx_file
= fragP
->fr_file
;
5085 fixP
->fx_line
= fragP
->fr_line
;
5086 fragP
->fr_fix
+= 4; /* Skip first offset */
5087 buffer_address
+= 4;
5088 *buffer_address
++ = 0x67; /* beq */
5089 *buffer_address
++ = 0xff;
5090 fragP
->fr_fix
+= 2; /* Skip second branch opcode */
5091 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5092 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5095 case TAB (BRABSJUNC
, LONG
):
5096 if (fragP
->fr_opcode
[0] == 0x61) /* jbsr */
5098 if (flag_keep_pcrel
)
5099 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5100 _("Conversion of PC relative BSR to absolute JSR"));
5101 fragP
->fr_opcode
[0] = 0x4E;
5102 fragP
->fr_opcode
[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
5103 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5104 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5107 else if (fragP
->fr_opcode
[0] == 0x60) /* jbra */
5109 if (flag_keep_pcrel
)
5110 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5111 _("Conversion of PC relative branch to absolute jump"));
5112 fragP
->fr_opcode
[0] = 0x4E;
5113 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
5114 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5115 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5120 /* This cannot happen, because jbsr and jbra are the only two
5121 unconditional branches. */
5125 case TAB (BRABSJCOND
, LONG
):
5126 if (flag_keep_pcrel
)
5127 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5128 _("Conversion of PC relative conditional branch to absolute jump"));
5130 /* Only Bcc 68000 instructions can come here
5131 Change bcc into b!cc/jmp absl long. */
5132 fragP
->fr_opcode
[0] ^= 0x01; /* Invert bcc. */
5133 fragP
->fr_opcode
[1] = 0x06; /* Branch offset = 6. */
5135 /* JF: these used to be fr_opcode[2,3], but they may be in a
5136 different frag, in which case referring to them is a no-no.
5137 Only fr_opcode[0,1] are guaranteed to work. */
5138 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
5139 *buffer_address
++ = (char) 0xf9;
5140 fragP
->fr_fix
+= 2; /* Account for jmp instruction. */
5141 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5142 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5145 case TAB (FBRANCH
, SHORT
):
5146 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
5147 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5148 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5151 case TAB (FBRANCH
, LONG
):
5152 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit. */
5153 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5154 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5157 case TAB (DBCCLBR
, SHORT
):
5158 case TAB (DBCCABSJ
, SHORT
):
5159 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5160 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5163 case TAB (DBCCLBR
, LONG
):
5164 /* Only DBcc instructions can come here.
5165 Change dbcc into dbcc/bral.
5166 JF: these used to be fr_opcode[2-7], but that's wrong. */
5167 *buffer_address
++ = 0x00; /* Branch offset = 4. */
5168 *buffer_address
++ = 0x04;
5169 *buffer_address
++ = 0x60; /* Put in bra pc+6. */
5170 *buffer_address
++ = 0x06;
5171 *buffer_address
++ = 0x60; /* Put in bral (0x60ff). */
5172 *buffer_address
++ = (char) 0xff;
5174 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
5175 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5176 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5179 case TAB (DBCCABSJ
, LONG
):
5180 /* Only DBcc instructions can come here.
5181 Change dbcc into dbcc/jmp.
5182 JF: these used to be fr_opcode[2-7], but that's wrong. */
5183 if (flag_keep_pcrel
)
5184 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5185 _("Conversion of PC relative conditional branch to absolute jump"));
5187 *buffer_address
++ = 0x00; /* Branch offset = 4. */
5188 *buffer_address
++ = 0x04;
5189 *buffer_address
++ = 0x60; /* Put in bra pc + 6. */
5190 *buffer_address
++ = 0x06;
5191 *buffer_address
++ = 0x4e; /* Put in jmp long (0x4ef9). */
5192 *buffer_address
++ = (char) 0xf9;
5194 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
5195 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5196 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5199 case TAB (PCREL1632
, SHORT
):
5200 fragP
->fr_opcode
[1] &= ~0x3F;
5201 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
5202 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
5203 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5206 case TAB (PCREL1632
, LONG
):
5207 /* Already set to mode 7.3; this indicates: PC indirect with
5208 suppressed index, 32-bit displacement. */
5209 *buffer_address
++ = 0x01;
5210 *buffer_address
++ = 0x70;
5212 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
5213 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5214 fixP
->fx_pcrel_adjust
= 2;
5217 case TAB (PCINDEX
, BYTE
):
5218 gas_assert (fragP
->fr_fix
>= 2);
5219 buffer_address
[-2] &= ~1;
5220 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
5221 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
5222 fixP
->fx_pcrel_adjust
= 1;
5224 case TAB (PCINDEX
, SHORT
):
5225 gas_assert (fragP
->fr_fix
>= 2);
5226 buffer_address
[-2] |= 0x1;
5227 buffer_address
[-1] = 0x20;
5228 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
5229 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5230 fixP
->fx_pcrel_adjust
= 2;
5233 case TAB (PCINDEX
, LONG
):
5234 gas_assert (fragP
->fr_fix
>= 2);
5235 buffer_address
[-2] |= 0x1;
5236 buffer_address
[-1] = 0x30;
5237 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
5238 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5239 fixP
->fx_pcrel_adjust
= 2;
5242 case TAB (ABSTOPCREL
, SHORT
):
5243 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5244 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5247 case TAB (ABSTOPCREL
, LONG
):
5248 if (flag_keep_pcrel
)
5249 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5250 _("Conversion of PC relative displacement to absolute"));
5251 /* The thing to do here is force it to ABSOLUTE LONG, since
5252 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5253 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
5255 fragP
->fr_opcode
[1] &= ~0x3F;
5256 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
5257 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5258 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5264 fixP
->fx_file
= fragP
->fr_file
;
5265 fixP
->fx_line
= fragP
->fr_line
;
5270 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
5271 segT sec ATTRIBUTE_UNUSED
,
5274 md_convert_frag_1 (fragP
);
5277 /* Force truly undefined symbols to their maximum size, and generally set up
5278 the frag list to be relaxed
5281 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
5283 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5284 switch (fragP
->fr_subtype
)
5286 case TAB (BRANCHBWL
, SZ_UNDEF
):
5287 case TAB (BRANCHBWPL
, SZ_UNDEF
):
5288 case TAB (BRABSJUNC
, SZ_UNDEF
):
5289 case TAB (BRABSJCOND
, SZ_UNDEF
):
5291 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5292 && relaxable_symbol (fragP
->fr_symbol
))
5294 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
5296 else if (flag_short_refs
)
5298 /* Symbol is undefined and we want short ref. */
5299 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5303 /* Symbol is still undefined. Make it LONG. */
5304 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
5309 case TAB (BRANCHBW
, SZ_UNDEF
):
5311 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5312 && relaxable_symbol (fragP
->fr_symbol
))
5314 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
5318 /* Symbol is undefined and we don't have long branches. */
5319 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5324 case TAB (FBRANCH
, SZ_UNDEF
):
5325 case TAB (DBCCLBR
, SZ_UNDEF
):
5326 case TAB (DBCCABSJ
, SZ_UNDEF
):
5327 case TAB (PCREL1632
, SZ_UNDEF
):
5329 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5330 && relaxable_symbol (fragP
->fr_symbol
))
5333 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5337 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
5342 case TAB (PCINDEX
, SZ_UNDEF
):
5343 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5344 && relaxable_symbol (fragP
->fr_symbol
)))
5346 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
5350 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
5354 case TAB (ABSTOPCREL
, SZ_UNDEF
):
5356 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5357 && relaxable_symbol (fragP
->fr_symbol
)))
5359 fragP
->fr_subtype
= TAB (ABSTOPCREL
, SHORT
);
5363 fragP
->fr_subtype
= TAB (ABSTOPCREL
, LONG
);
5372 /* Now that SZ_UNDEF are taken care of, check others. */
5373 switch (fragP
->fr_subtype
)
5375 case TAB (BRANCHBWL
, BYTE
):
5376 case TAB (BRABSJUNC
, BYTE
):
5377 case TAB (BRABSJCOND
, BYTE
):
5378 case TAB (BRANCHBW
, BYTE
):
5379 /* We can't do a short jump to the next instruction, so in that
5380 case we force word mode. If the symbol is at the start of a
5381 frag, and it is the next frag with any data in it (usually
5382 this is just the next frag, but assembler listings may
5383 introduce empty frags), we must use word mode. */
5384 if (fragP
->fr_symbol
)
5388 sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
5389 if (S_GET_VALUE (fragP
->fr_symbol
) == sym_frag
->fr_address
)
5393 for (l
= fragP
->fr_next
; l
&& l
!= sym_frag
; l
= l
->fr_next
)
5397 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5404 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5407 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5408 /* the bit-field entries in the relocation_info struct plays hell
5409 with the byte-order problems of cross-assembly. So as a hack,
5410 I added this mach. dependent ri twiddler. Ugly, but it gets
5412 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5413 are symbolnum, most sig. byte first. Last byte is broken up with
5414 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5415 nibble as nuthin. (on Sun 3 at least) */
5416 /* Translate the internal relocation information into target-specific
5420 md_ri_to_chars (char *the_bytes
, struct reloc_info_generic
*ri
)
5423 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
5424 /* Now the fun stuff. */
5425 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
5426 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
5427 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
5428 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80)
5429 | ((ri
->r_length
<< 5) & 0x60)
5430 | ((ri
->r_extern
<< 4) & 0x10));
5435 #endif /* OBJ_AOUT or OBJ_BOUT */
5437 #ifndef WORKING_DOT_WORD
5438 int md_short_jump_size
= 4;
5439 int md_long_jump_size
= 6;
5442 md_create_short_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5443 fragS
*frag ATTRIBUTE_UNUSED
,
5444 symbolS
*to_symbol ATTRIBUTE_UNUSED
)
5448 offset
= to_addr
- (from_addr
+ 2);
5450 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
5451 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
5455 md_create_long_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5456 fragS
*frag
, symbolS
*to_symbol
)
5460 if (!HAVE_LONG_BRANCH (current_architecture
))
5462 if (flag_keep_pcrel
)
5463 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5464 offset
= to_addr
- S_GET_VALUE (to_symbol
);
5465 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
5466 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5467 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
5472 offset
= to_addr
- (from_addr
+ 2);
5473 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
5474 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5480 /* Different values of OK tell what its OK to return. Things that
5481 aren't OK are an error (what a shock, no?)
5484 10: Absolute 1:8 only
5485 20: Absolute 0:7 only
5486 30: absolute 0:15 only
5487 40: Absolute 0:31 only
5488 50: absolute 0:127 only
5489 55: absolute -64:63 only
5490 60: absolute -128:127 only
5491 65: absolute 0:511 only
5492 70: absolute 0:4095 only
5493 80: absolute -1, 1:7 only
5497 get_num (struct m68k_exp
*exp
, int ok
)
5499 if (exp
->exp
.X_op
== O_absent
)
5501 /* Do the same thing the VAX asm does. */
5502 op (exp
) = O_constant
;
5508 as_warn (_("expression out of range: defaulting to 1"));
5512 else if (exp
->exp
.X_op
== O_constant
)
5517 if ((valueT
) TRUNC (offs (exp
)) - 1 > 7)
5519 as_warn (_("expression out of range: defaulting to 1"));
5524 if ((valueT
) TRUNC (offs (exp
)) > 7)
5528 if ((valueT
) TRUNC (offs (exp
)) > 15)
5532 if ((valueT
) TRUNC (offs (exp
)) > 32)
5536 if ((valueT
) TRUNC (offs (exp
)) > 127)
5540 if ((valueT
) SEXT (offs (exp
)) + 64 > 127)
5544 if ((valueT
) SEXT (offs (exp
)) + 128 > 255)
5548 if ((valueT
) TRUNC (offs (exp
)) > 511)
5552 if ((valueT
) TRUNC (offs (exp
)) > 4095)
5555 as_warn (_("expression out of range: defaulting to 0"));
5560 if ((valueT
) TRUNC (offs (exp
)) != 0xffffffff
5561 && (valueT
) TRUNC (offs (exp
)) - 1 > 6)
5563 as_warn (_("expression out of range: defaulting to 1"));
5571 else if (exp
->exp
.X_op
== O_big
)
5573 if (offs (exp
) <= 0 /* flonum. */
5574 && (ok
== 90 /* no bignums */
5575 || (ok
> 10 /* Small-int ranges including 0 ok. */
5576 /* If we have a flonum zero, a zero integer should
5577 do as well (e.g., in moveq). */
5578 && generic_floating_point_number
.exponent
== 0
5579 && generic_floating_point_number
.low
[0] == 0)))
5581 /* HACK! Turn it into a long. */
5582 LITTLENUM_TYPE words
[6];
5584 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
5585 op (exp
) = O_constant
;
5588 offs (exp
) = words
[1] | (words
[0] << 16);
5592 op (exp
) = O_constant
;
5595 offs (exp
) = (ok
== 10) ? 1 : 0;
5596 as_warn (_("Can't deal with expression; defaulting to %ld"),
5602 if (ok
>= 10 && ok
<= 80)
5604 op (exp
) = O_constant
;
5607 offs (exp
) = (ok
== 10) ? 1 : 0;
5608 as_warn (_("Can't deal with expression; defaulting to %ld"),
5613 if (exp
->size
!= SIZE_UNSPEC
)
5621 if (!isbyte (offs (exp
)))
5622 as_warn (_("expression doesn't fit in BYTE"));
5625 if (!isword (offs (exp
)))
5626 as_warn (_("expression doesn't fit in WORD"));
5634 /* These are the back-ends for the various machine dependent pseudo-ops. */
5637 s_data1 (int ignore ATTRIBUTE_UNUSED
)
5639 subseg_set (data_section
, 1);
5640 demand_empty_rest_of_line ();
5644 s_data2 (int ignore ATTRIBUTE_UNUSED
)
5646 subseg_set (data_section
, 2);
5647 demand_empty_rest_of_line ();
5651 s_bss (int ignore ATTRIBUTE_UNUSED
)
5653 /* We don't support putting frags in the BSS segment, we fake it
5654 by marking in_bss, then looking at s_skip for clues. */
5656 subseg_set (bss_section
, 0);
5657 demand_empty_rest_of_line ();
5661 s_even (int ignore ATTRIBUTE_UNUSED
)
5666 temp
= 1; /* JF should be 2? */
5667 temp_fill
= get_absolute_expression ();
5668 if (!need_pass_2
) /* Never make frag if expect extra pass. */
5669 frag_align (temp
, (int) temp_fill
, 0);
5670 demand_empty_rest_of_line ();
5671 record_alignment (now_seg
, temp
);
5675 s_proc (int ignore ATTRIBUTE_UNUSED
)
5677 demand_empty_rest_of_line ();
5680 /* Pseudo-ops handled for MRI compatibility. */
5682 /* This function returns non-zero if the argument is a conditional
5683 pseudo-op. This is called when checking whether a pending
5684 alignment is needed. */
5687 m68k_conditional_pseudoop (pseudo_typeS
*pop
)
5689 return (pop
->poc_handler
== s_mri_if
5690 || pop
->poc_handler
== s_mri_else
);
5693 /* Handle an MRI style chip specification. */
5702 s
= input_line_pointer
;
5703 /* We can't use get_symbol_name since the processor names are not proper
5705 while (is_part_of_name (c
= *input_line_pointer
++))
5707 *--input_line_pointer
= 0;
5708 for (i
= 0; m68k_cpus
[i
].name
; i
++)
5709 if (strcasecmp (s
, m68k_cpus
[i
].name
) == 0)
5711 if (!m68k_cpus
[i
].name
)
5713 as_bad (_("%s: unrecognized processor name"), s
);
5714 *input_line_pointer
= c
;
5715 ignore_rest_of_line ();
5718 *input_line_pointer
= c
;
5720 if (*input_line_pointer
== '/')
5721 current_architecture
= 0;
5723 current_architecture
&= m68881
| m68851
;
5724 current_architecture
|= m68k_cpus
[i
].arch
& ~(m68881
| m68851
);
5725 control_regs
= m68k_cpus
[i
].control_regs
;
5727 while (*input_line_pointer
== '/')
5729 ++input_line_pointer
;
5730 s
= input_line_pointer
;
5731 /* We can't use get_symbol_name since the processor names are not
5733 while (is_part_of_name (c
= *input_line_pointer
++))
5735 *--input_line_pointer
= 0;
5736 if (strcmp (s
, "68881") == 0)
5737 current_architecture
|= m68881
;
5738 else if (strcmp (s
, "68851") == 0)
5739 current_architecture
|= m68851
;
5740 *input_line_pointer
= c
;
5744 /* The MRI CHIP pseudo-op. */
5747 s_chip (int ignore ATTRIBUTE_UNUSED
)
5753 stop
= mri_comment_field (&stopc
);
5756 mri_comment_end (stop
, stopc
);
5757 demand_empty_rest_of_line ();
5760 /* The MRI FOPT pseudo-op. */
5763 s_fopt (int ignore ATTRIBUTE_UNUSED
)
5767 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
5771 input_line_pointer
+= 3;
5772 temp
= get_absolute_expression ();
5773 if (temp
< 0 || temp
> 7)
5774 as_bad (_("bad coprocessor id"));
5776 m68k_float_copnum
= COP0
+ temp
;
5780 as_bad (_("unrecognized fopt option"));
5781 ignore_rest_of_line ();
5785 demand_empty_rest_of_line ();
5788 /* The structure used to handle the MRI OPT pseudo-op. */
5792 /* The name of the option. */
5795 /* If this is not NULL, just call this function. The first argument
5796 is the ARG field of this structure, the second argument is
5797 whether the option was negated. */
5798 void (*pfn
) (int arg
, int on
);
5800 /* If this is not NULL, and the PFN field is NULL, set the variable
5801 this points to. Set it to the ARG field if the option was not
5802 negated, and the NOTARG field otherwise. */
5805 /* The value to pass to PFN or to assign to *PVAR. */
5808 /* The value to assign to *PVAR if the option is negated. If PFN is
5809 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5810 the option may not be negated. */
5814 /* The table used to handle the MRI OPT pseudo-op. */
5816 static void skip_to_comma (int, int);
5817 static void opt_nest (int, int);
5818 static void opt_chip (int, int);
5819 static void opt_list (int, int);
5820 static void opt_list_symbols (int, int);
5822 static const struct opt_action opt_table
[] =
5824 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5826 /* We do relaxing, so there is little use for these options. */
5827 { "b", 0, 0, 0, 0 },
5828 { "brs", 0, 0, 0, 0 },
5829 { "brb", 0, 0, 0, 0 },
5830 { "brl", 0, 0, 0, 0 },
5831 { "brw", 0, 0, 0, 0 },
5833 { "c", 0, 0, 0, 0 },
5834 { "cex", 0, 0, 0, 0 },
5835 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5836 { "cl", 0, 0, 0, 0 },
5837 { "cre", 0, 0, 0, 0 },
5838 { "d", 0, &flag_keep_locals
, 1, 0 },
5839 { "e", 0, 0, 0, 0 },
5840 { "f", 0, &flag_short_refs
, 1, 0 },
5841 { "frs", 0, &flag_short_refs
, 1, 0 },
5842 { "frl", 0, &flag_short_refs
, 0, 1 },
5843 { "g", 0, 0, 0, 0 },
5844 { "i", 0, 0, 0, 0 },
5845 { "m", 0, 0, 0, 0 },
5846 { "mex", 0, 0, 0, 0 },
5847 { "mc", 0, 0, 0, 0 },
5848 { "md", 0, 0, 0, 0 },
5849 { "nest", opt_nest
, 0, 0, 0 },
5850 { "next", skip_to_comma
, 0, 0, 0 },
5851 { "o", 0, 0, 0, 0 },
5852 { "old", 0, 0, 0, 0 },
5853 { "op", skip_to_comma
, 0, 0, 0 },
5854 { "pco", 0, 0, 0, 0 },
5855 { "p", opt_chip
, 0, 0, 0 },
5856 { "pcr", 0, 0, 0, 0 },
5857 { "pcs", 0, 0, 0, 0 },
5858 { "r", 0, 0, 0, 0 },
5859 { "quick", 0, &m68k_quick
, 1, 0 },
5860 { "rel32", 0, &m68k_rel32
, 1, 0 },
5861 { "s", opt_list
, 0, 0, 0 },
5862 { "t", opt_list_symbols
, 0, 0, 0 },
5863 { "w", 0, &flag_no_warnings
, 0, 1 },
5867 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5869 /* The MRI OPT pseudo-op. */
5872 s_opt (int ignore ATTRIBUTE_UNUSED
)
5880 const struct opt_action
*o
;
5885 if (*input_line_pointer
== '-')
5887 ++input_line_pointer
;
5890 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5892 input_line_pointer
+= 2;
5896 c
= get_symbol_name (&s
);
5898 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5900 if (strcasecmp (s
, o
->name
) == 0)
5904 /* Restore input_line_pointer now in case the option
5906 (void) restore_line_pointer (c
);
5907 (*o
->pfn
) (o
->arg
, t
);
5909 else if (o
->pvar
!= NULL
)
5911 if (! t
&& o
->arg
== o
->notarg
)
5912 as_bad (_("option `%s' may not be negated"), s
);
5913 restore_line_pointer (c
);
5914 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5917 *input_line_pointer
= c
;
5923 as_bad (_("option `%s' not recognized"), s
);
5924 restore_line_pointer (c
);
5927 while (*input_line_pointer
++ == ',');
5929 /* Move back to terminating character. */
5930 --input_line_pointer
;
5931 demand_empty_rest_of_line ();
5934 /* Skip ahead to a comma. This is used for OPT options which we do
5935 not support and which take arguments. */
5938 skip_to_comma (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5940 while (*input_line_pointer
!= ','
5941 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5942 ++input_line_pointer
;
5945 /* Handle the OPT NEST=depth option. */
5948 opt_nest (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5950 if (*input_line_pointer
!= '=')
5952 as_bad (_("bad format of OPT NEST=depth"));
5956 ++input_line_pointer
;
5957 max_macro_nest
= get_absolute_expression ();
5960 /* Handle the OPT P=chip option. */
5963 opt_chip (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5965 if (*input_line_pointer
!= '=')
5967 /* This is just OPT P, which we do not support. */
5971 ++input_line_pointer
;
5975 /* Handle the OPT S option. */
5978 opt_list (int arg ATTRIBUTE_UNUSED
, int on
)
5983 /* Handle the OPT T option. */
5986 opt_list_symbols (int arg ATTRIBUTE_UNUSED
, int on
)
5989 listing
|= LISTING_SYMBOLS
;
5991 listing
&= ~LISTING_SYMBOLS
;
5994 /* Handle the MRI REG pseudo-op. */
5997 s_reg (int ignore ATTRIBUTE_UNUSED
)
6006 if (line_label
== NULL
)
6008 as_bad (_("missing label"));
6009 ignore_rest_of_line ();
6014 stop
= mri_comment_field (&stopc
);
6018 s
= input_line_pointer
;
6019 while (ISALNUM (*input_line_pointer
)
6020 #ifdef REGISTER_PREFIX
6021 || *input_line_pointer
== REGISTER_PREFIX
6023 || *input_line_pointer
== '/'
6024 || *input_line_pointer
== '-')
6025 ++input_line_pointer
;
6026 c
= *input_line_pointer
;
6027 *input_line_pointer
= '\0';
6029 if (m68k_ip_op (s
, &rop
) != 0)
6031 if (rop
.error
== NULL
)
6032 as_bad (_("bad register list"));
6034 as_bad (_("bad register list: %s"), rop
.error
);
6035 *input_line_pointer
= c
;
6036 ignore_rest_of_line ();
6040 *input_line_pointer
= c
;
6042 if (rop
.mode
== REGLST
)
6044 else if (rop
.mode
== DREG
)
6045 mask
= 1 << (rop
.reg
- DATA0
);
6046 else if (rop
.mode
== AREG
)
6047 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
6048 else if (rop
.mode
== FPREG
)
6049 mask
= 1 << (rop
.reg
- FP0
+ 16);
6050 else if (rop
.mode
== CONTROL
6053 else if (rop
.mode
== CONTROL
6056 else if (rop
.mode
== CONTROL
6061 as_bad (_("bad register list"));
6062 ignore_rest_of_line ();
6066 S_SET_SEGMENT (line_label
, reg_section
);
6067 S_SET_VALUE (line_label
, ~mask
);
6068 symbol_set_frag (line_label
, &zero_address_frag
);
6071 mri_comment_end (stop
, stopc
);
6073 demand_empty_rest_of_line ();
6076 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
6080 struct save_opts
*next
;
6082 int symbols_case_sensitive
;
6086 const enum m68k_register
*control_regs
;
6091 /* FIXME: We don't save OPT S. */
6094 /* This variable holds the stack of saved options. */
6096 static struct save_opts
*save_stack
;
6098 /* The MRI SAVE pseudo-op. */
6101 s_save (int ignore ATTRIBUTE_UNUSED
)
6103 struct save_opts
*s
;
6105 s
= (struct save_opts
*) xmalloc (sizeof (struct save_opts
));
6106 s
->abspcadd
= m68k_abspcadd
;
6107 s
->symbols_case_sensitive
= symbols_case_sensitive
;
6108 s
->keep_locals
= flag_keep_locals
;
6109 s
->short_refs
= flag_short_refs
;
6110 s
->architecture
= current_architecture
;
6111 s
->control_regs
= control_regs
;
6112 s
->quick
= m68k_quick
;
6113 s
->rel32
= m68k_rel32
;
6114 s
->listing
= listing
;
6115 s
->no_warnings
= flag_no_warnings
;
6117 s
->next
= save_stack
;
6120 demand_empty_rest_of_line ();
6123 /* The MRI RESTORE pseudo-op. */
6126 s_restore (int ignore ATTRIBUTE_UNUSED
)
6128 struct save_opts
*s
;
6130 if (save_stack
== NULL
)
6132 as_bad (_("restore without save"));
6133 ignore_rest_of_line ();
6138 save_stack
= s
->next
;
6140 m68k_abspcadd
= s
->abspcadd
;
6141 symbols_case_sensitive
= s
->symbols_case_sensitive
;
6142 flag_keep_locals
= s
->keep_locals
;
6143 flag_short_refs
= s
->short_refs
;
6144 current_architecture
= s
->architecture
;
6145 control_regs
= s
->control_regs
;
6146 m68k_quick
= s
->quick
;
6147 m68k_rel32
= s
->rel32
;
6148 listing
= s
->listing
;
6149 flag_no_warnings
= s
->no_warnings
;
6153 demand_empty_rest_of_line ();
6156 /* Types of MRI structured control directives. */
6158 enum mri_control_type
6166 /* This structure is used to stack the MRI structured control
6169 struct mri_control_info
6171 /* The directive within which this one is enclosed. */
6172 struct mri_control_info
*outer
;
6174 /* The type of directive. */
6175 enum mri_control_type type
;
6177 /* Whether an ELSE has been in an IF. */
6180 /* The add or sub statement at the end of a FOR. */
6183 /* The label of the top of a FOR or REPEAT loop. */
6186 /* The label to jump to for the next iteration, or the else
6187 expression of a conditional. */
6190 /* The label to jump to to break out of the loop, or the label past
6191 the end of a conditional. */
6195 /* The stack of MRI structured control directives. */
6197 static struct mri_control_info
*mri_control_stack
;
6199 /* The current MRI structured control directive index number, used to
6200 generate label names. */
6202 static int mri_control_index
;
6204 /* Assemble an instruction for an MRI structured control directive. */
6207 mri_assemble (char *str
)
6211 /* md_assemble expects the opcode to be in lower case. */
6212 for (s
= str
; *s
!= ' ' && *s
!= '\0'; s
++)
6218 /* Generate a new MRI label structured control directive label name. */
6221 mri_control_label (void)
6225 n
= (char *) xmalloc (20);
6226 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
6227 ++mri_control_index
;
6231 /* Create a new MRI structured control directive. */
6233 static struct mri_control_info
*
6234 push_mri_control (enum mri_control_type type
)
6236 struct mri_control_info
*n
;
6238 n
= (struct mri_control_info
*) xmalloc (sizeof (struct mri_control_info
));
6242 if (type
== mri_if
|| type
== mri_while
)
6245 n
->top
= mri_control_label ();
6246 n
->next
= mri_control_label ();
6247 n
->bottom
= mri_control_label ();
6249 n
->outer
= mri_control_stack
;
6250 mri_control_stack
= n
;
6255 /* Pop off the stack of MRI structured control directives. */
6258 pop_mri_control (void)
6260 struct mri_control_info
*n
;
6262 n
= mri_control_stack
;
6263 mri_control_stack
= n
->outer
;
6271 /* Recognize a condition code in an MRI structured control expression. */
6274 parse_mri_condition (int *pcc
)
6278 know (*input_line_pointer
== '<');
6280 ++input_line_pointer
;
6281 c1
= *input_line_pointer
++;
6282 c2
= *input_line_pointer
++;
6284 if (*input_line_pointer
!= '>')
6286 as_bad (_("syntax error in structured control directive"));
6290 ++input_line_pointer
;
6296 *pcc
= (c1
<< 8) | c2
;
6301 /* Parse a single operand in an MRI structured control expression. */
6304 parse_mri_control_operand (int *pcc
, char **leftstart
, char **leftstop
,
6305 char **rightstart
, char **rightstop
)
6317 if (*input_line_pointer
== '<')
6319 /* It's just a condition code. */
6320 return parse_mri_condition (pcc
);
6323 /* Look ahead for the condition code. */
6324 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
6326 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
6331 as_bad (_("missing condition code in structured control directive"));
6335 *leftstart
= input_line_pointer
;
6337 if (*leftstop
> *leftstart
6338 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
6341 input_line_pointer
= s
;
6342 if (! parse_mri_condition (pcc
))
6345 /* Look ahead for AND or OR or end of line. */
6346 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
6348 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6349 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6351 if ((s
== input_line_pointer
6354 && ((strncasecmp (s
, "AND", 3) == 0
6355 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
6356 || (strncasecmp (s
, "OR", 2) == 0
6357 && (s
[2] == '.' || ! is_part_of_name (s
[2])))))
6361 *rightstart
= input_line_pointer
;
6363 if (*rightstop
> *rightstart
6364 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
6367 input_line_pointer
= s
;
6372 #define MCC(b1, b2) (((b1) << 8) | (b2))
6374 /* Swap the sense of a condition. This changes the condition so that
6375 it generates the same result when the operands are swapped. */
6378 swap_mri_condition (int cc
)
6382 case MCC ('h', 'i'): return MCC ('c', 's');
6383 case MCC ('l', 's'): return MCC ('c', 'c');
6384 /* <HS> is an alias for <CC>. */
6385 case MCC ('h', 's'):
6386 case MCC ('c', 'c'): return MCC ('l', 's');
6387 /* <LO> is an alias for <CS>. */
6388 case MCC ('l', 'o'):
6389 case MCC ('c', 's'): return MCC ('h', 'i');
6390 case MCC ('p', 'l'): return MCC ('m', 'i');
6391 case MCC ('m', 'i'): return MCC ('p', 'l');
6392 case MCC ('g', 'e'): return MCC ('l', 'e');
6393 case MCC ('l', 't'): return MCC ('g', 't');
6394 case MCC ('g', 't'): return MCC ('l', 't');
6395 case MCC ('l', 'e'): return MCC ('g', 'e');
6396 /* Issue a warning for conditions we can not swap. */
6397 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6398 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
6399 case MCC ('v', 'c'):
6400 case MCC ('v', 's'):
6402 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6403 (char) (cc
>> 8), (char) (cc
));
6409 /* Reverse the sense of a condition. */
6412 reverse_mri_condition (int cc
)
6416 case MCC ('h', 'i'): return MCC ('l', 's');
6417 case MCC ('l', 's'): return MCC ('h', 'i');
6418 /* <HS> is an alias for <CC> */
6419 case MCC ('h', 's'): return MCC ('l', 'o');
6420 case MCC ('c', 'c'): return MCC ('c', 's');
6421 /* <LO> is an alias for <CS> */
6422 case MCC ('l', 'o'): return MCC ('h', 's');
6423 case MCC ('c', 's'): return MCC ('c', 'c');
6424 case MCC ('n', 'e'): return MCC ('e', 'q');
6425 case MCC ('e', 'q'): return MCC ('n', 'e');
6426 case MCC ('v', 'c'): return MCC ('v', 's');
6427 case MCC ('v', 's'): return MCC ('v', 'c');
6428 case MCC ('p', 'l'): return MCC ('m', 'i');
6429 case MCC ('m', 'i'): return MCC ('p', 'l');
6430 case MCC ('g', 'e'): return MCC ('l', 't');
6431 case MCC ('l', 't'): return MCC ('g', 'e');
6432 case MCC ('g', 't'): return MCC ('l', 'e');
6433 case MCC ('l', 'e'): return MCC ('g', 't');
6438 /* Build an MRI structured control expression. This generates test
6439 and branch instructions. It goes to TRUELAB if the condition is
6440 true, and to FALSELAB if the condition is false. Exactly one of
6441 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6442 is the size qualifier for the expression. EXTENT is the size to
6443 use for the branch. */
6446 build_mri_control_operand (int qual
, int cc
, char *leftstart
, char *leftstop
,
6447 char *rightstart
, char *rightstop
,
6448 const char *truelab
, const char *falselab
,
6454 if (leftstart
!= NULL
)
6456 struct m68k_op leftop
, rightop
;
6459 /* Swap the compare operands, if necessary, to produce a legal
6460 m68k compare instruction. Comparing a register operand with
6461 a non-register operand requires the register to be on the
6462 right (cmp, cmpa). Comparing an immediate value with
6463 anything requires the immediate value to be on the left
6468 (void) m68k_ip_op (leftstart
, &leftop
);
6473 (void) m68k_ip_op (rightstart
, &rightop
);
6476 if (rightop
.mode
== IMMED
6477 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
6478 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
6482 /* Correct conditional handling:
6483 if #1 <lt> d0 then ;means if (1 < d0)
6489 cmp #1,d0 if we do *not* swap the operands
6490 bgt true we need the swapped condition!
6497 leftstart
= rightstart
;
6500 leftstop
= rightstop
;
6505 cc
= swap_mri_condition (cc
);
6509 if (truelab
== NULL
)
6511 cc
= reverse_mri_condition (cc
);
6515 if (leftstart
!= NULL
)
6517 buf
= (char *) xmalloc (20
6518 + (leftstop
- leftstart
)
6519 + (rightstop
- rightstart
));
6525 *s
++ = TOLOWER (qual
);
6527 memcpy (s
, leftstart
, leftstop
- leftstart
);
6528 s
+= leftstop
- leftstart
;
6530 memcpy (s
, rightstart
, rightstop
- rightstart
);
6531 s
+= rightstop
- rightstart
;
6537 buf
= (char *) xmalloc (20 + strlen (truelab
));
6543 *s
++ = TOLOWER (extent
);
6545 strcpy (s
, truelab
);
6550 /* Parse an MRI structured control expression. This generates test
6551 and branch instructions. STOP is where the expression ends. It
6552 goes to TRUELAB if the condition is true, and to FALSELAB if the
6553 condition is false. Exactly one of TRUELAB and FALSELAB will be
6554 NULL, meaning to fall through. QUAL is the size qualifier for the
6555 expression. EXTENT is the size to use for the branch. */
6558 parse_mri_control_expression (char *stop
, int qual
, const char *truelab
,
6559 const char *falselab
, int extent
)
6571 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6572 &rightstart
, &rightstop
))
6578 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
6582 if (falselab
!= NULL
)
6585 flab
= mri_control_label ();
6587 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6588 rightstop
, (const char *) NULL
, flab
, extent
);
6590 input_line_pointer
+= 3;
6591 if (*input_line_pointer
!= '.'
6592 || input_line_pointer
[1] == '\0')
6596 qual
= input_line_pointer
[1];
6597 input_line_pointer
+= 2;
6600 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6601 &rightstart
, &rightstop
))
6607 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6608 rightstop
, truelab
, falselab
, extent
);
6610 if (falselab
== NULL
)
6613 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
6617 if (truelab
!= NULL
)
6620 tlab
= mri_control_label ();
6622 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6623 rightstop
, tlab
, (const char *) NULL
, extent
);
6625 input_line_pointer
+= 2;
6626 if (*input_line_pointer
!= '.'
6627 || input_line_pointer
[1] == '\0')
6631 qual
= input_line_pointer
[1];
6632 input_line_pointer
+= 2;
6635 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6636 &rightstart
, &rightstop
))
6642 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6643 rightstop
, truelab
, falselab
, extent
);
6645 if (truelab
== NULL
)
6650 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6651 rightstop
, truelab
, falselab
, extent
);
6655 if (input_line_pointer
!= stop
)
6656 as_bad (_("syntax error in structured control directive"));
6659 /* Handle the MRI IF pseudo-op. This may be a structured control
6660 directive, or it may be a regular assembler conditional, depending
6668 struct mri_control_info
*n
;
6670 /* A structured control directive must end with THEN with an
6671 optional qualifier. */
6672 s
= input_line_pointer
;
6673 /* We only accept '*' as introduction of comments if preceded by white space
6674 or at first column of a line (I think this can't actually happen here?)
6675 This is important when assembling:
6676 if d0 <ne> 12(a0,d0*2) then
6677 if d0 <ne> #CONST*20 then. */
6678 while (! (is_end_of_line
[(unsigned char) *s
]
6681 && (s
== input_line_pointer
6683 || *(s
-1) == '\t'))))
6686 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
6689 if (s
- input_line_pointer
> 1
6693 if (s
- input_line_pointer
< 3
6694 || strncasecmp (s
- 3, "THEN", 4) != 0)
6698 as_bad (_("missing then"));
6699 ignore_rest_of_line ();
6703 /* It's a conditional. */
6708 /* Since this might be a conditional if, this pseudo-op will be
6709 called even if we are supported to be ignoring input. Double
6710 check now. Clobber *input_line_pointer so that ignore_input
6711 thinks that this is not a special pseudo-op. */
6712 c
= *input_line_pointer
;
6713 *input_line_pointer
= 0;
6714 if (ignore_input ())
6716 *input_line_pointer
= c
;
6717 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6718 ++input_line_pointer
;
6719 demand_empty_rest_of_line ();
6722 *input_line_pointer
= c
;
6724 n
= push_mri_control (mri_if
);
6726 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
6727 n
->next
, s
[1] == '.' ? s
[2] : '\0');
6730 input_line_pointer
= s
+ 3;
6732 input_line_pointer
= s
+ 1;
6736 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6737 ++input_line_pointer
;
6740 demand_empty_rest_of_line ();
6743 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6744 structured IF, associate the ELSE with the IF. Otherwise, assume
6745 it is a conditional else. */
6748 s_mri_else (int qual
)
6755 && (mri_control_stack
== NULL
6756 || mri_control_stack
->type
!= mri_if
6757 || mri_control_stack
->else_seen
))
6763 c
= *input_line_pointer
;
6764 *input_line_pointer
= 0;
6765 if (ignore_input ())
6767 *input_line_pointer
= c
;
6768 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6769 ++input_line_pointer
;
6770 demand_empty_rest_of_line ();
6773 *input_line_pointer
= c
;
6775 if (mri_control_stack
== NULL
6776 || mri_control_stack
->type
!= mri_if
6777 || mri_control_stack
->else_seen
)
6779 as_bad (_("else without matching if"));
6780 ignore_rest_of_line ();
6784 mri_control_stack
->else_seen
= 1;
6786 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->bottom
));
6787 q
[0] = TOLOWER (qual
);
6789 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6793 colon (mri_control_stack
->next
);
6797 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6798 ++input_line_pointer
;
6801 demand_empty_rest_of_line ();
6804 /* Handle the MRI ENDI pseudo-op. */
6807 s_mri_endi (int ignore ATTRIBUTE_UNUSED
)
6809 if (mri_control_stack
== NULL
6810 || mri_control_stack
->type
!= mri_if
)
6812 as_bad (_("endi without matching if"));
6813 ignore_rest_of_line ();
6817 /* ignore_input will not return true for ENDI, so we don't need to
6818 worry about checking it again here. */
6820 if (! mri_control_stack
->else_seen
)
6821 colon (mri_control_stack
->next
);
6822 colon (mri_control_stack
->bottom
);
6828 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6829 ++input_line_pointer
;
6832 demand_empty_rest_of_line ();
6835 /* Handle the MRI BREAK pseudo-op. */
6838 s_mri_break (int extent
)
6840 struct mri_control_info
*n
;
6844 n
= mri_control_stack
;
6846 && n
->type
!= mri_for
6847 && n
->type
!= mri_repeat
6848 && n
->type
!= mri_while
)
6852 as_bad (_("break outside of structured loop"));
6853 ignore_rest_of_line ();
6857 buf
= (char *) xmalloc (20 + strlen (n
->bottom
));
6858 ex
[0] = TOLOWER (extent
);
6860 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6866 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6867 ++input_line_pointer
;
6870 demand_empty_rest_of_line ();
6873 /* Handle the MRI NEXT pseudo-op. */
6876 s_mri_next (int extent
)
6878 struct mri_control_info
*n
;
6882 n
= mri_control_stack
;
6884 && n
->type
!= mri_for
6885 && n
->type
!= mri_repeat
6886 && n
->type
!= mri_while
)
6890 as_bad (_("next outside of structured loop"));
6891 ignore_rest_of_line ();
6895 buf
= (char *) xmalloc (20 + strlen (n
->next
));
6896 ex
[0] = TOLOWER (extent
);
6898 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6904 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6905 ++input_line_pointer
;
6908 demand_empty_rest_of_line ();
6911 /* Handle the MRI FOR pseudo-op. */
6914 s_mri_for (int qual
)
6916 const char *varstart
, *varstop
;
6917 const char *initstart
, *initstop
;
6918 const char *endstart
, *endstop
;
6919 const char *bystart
, *bystop
;
6923 struct mri_control_info
*n
;
6929 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6933 varstart
= input_line_pointer
;
6935 /* Look for the '='. */
6936 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6937 && *input_line_pointer
!= '=')
6938 ++input_line_pointer
;
6939 if (*input_line_pointer
!= '=')
6941 as_bad (_("missing ="));
6942 ignore_rest_of_line ();
6946 varstop
= input_line_pointer
;
6947 if (varstop
> varstart
6948 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6951 ++input_line_pointer
;
6953 initstart
= input_line_pointer
;
6955 /* Look for TO or DOWNTO. */
6958 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6960 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6961 && ! is_part_of_name (input_line_pointer
[2]))
6963 initstop
= input_line_pointer
;
6964 input_line_pointer
+= 2;
6967 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6968 && ! is_part_of_name (input_line_pointer
[6]))
6970 initstop
= input_line_pointer
;
6972 input_line_pointer
+= 6;
6975 ++input_line_pointer
;
6977 if (initstop
== NULL
)
6979 as_bad (_("missing to or downto"));
6980 ignore_rest_of_line ();
6983 if (initstop
> initstart
6984 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6988 endstart
= input_line_pointer
;
6990 /* Look for BY or DO. */
6993 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6995 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
6996 && ! is_part_of_name (input_line_pointer
[2]))
6998 endstop
= input_line_pointer
;
7000 input_line_pointer
+= 2;
7003 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
7004 && (input_line_pointer
[2] == '.'
7005 || ! is_part_of_name (input_line_pointer
[2])))
7007 endstop
= input_line_pointer
;
7008 input_line_pointer
+= 2;
7011 ++input_line_pointer
;
7013 if (endstop
== NULL
)
7015 as_bad (_("missing do"));
7016 ignore_rest_of_line ();
7019 if (endstop
> endstart
7020 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
7026 bystop
= bystart
+ 2;
7031 bystart
= input_line_pointer
;
7035 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7037 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
7038 && (input_line_pointer
[2] == '.'
7039 || ! is_part_of_name (input_line_pointer
[2])))
7041 bystop
= input_line_pointer
;
7042 input_line_pointer
+= 2;
7045 ++input_line_pointer
;
7049 as_bad (_("missing do"));
7050 ignore_rest_of_line ();
7053 if (bystop
> bystart
7054 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
7058 if (*input_line_pointer
!= '.')
7062 extent
= input_line_pointer
[1];
7063 input_line_pointer
+= 2;
7066 /* We have fully parsed the FOR operands. Now build the loop. */
7067 n
= push_mri_control (mri_for
);
7069 buf
= (char *) xmalloc (50 + (input_line_pointer
- varstart
));
7071 /* Move init,var. */
7078 *s
++ = TOLOWER (qual
);
7080 memcpy (s
, initstart
, initstop
- initstart
);
7081 s
+= initstop
- initstart
;
7083 memcpy (s
, varstart
, varstop
- varstart
);
7084 s
+= varstop
- varstart
;
7096 *s
++ = TOLOWER (qual
);
7098 memcpy (s
, endstart
, endstop
- endstart
);
7099 s
+= endstop
- endstart
;
7101 memcpy (s
, varstart
, varstop
- varstart
);
7102 s
+= varstop
- varstart
;
7107 ex
[0] = TOLOWER (extent
);
7110 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
7112 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
7115 /* Put together the add or sub instruction used by ENDF. */
7123 *s
++ = TOLOWER (qual
);
7125 memcpy (s
, bystart
, bystop
- bystart
);
7126 s
+= bystop
- bystart
;
7128 memcpy (s
, varstart
, varstop
- varstart
);
7129 s
+= varstop
- varstart
;
7135 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7136 ++input_line_pointer
;
7139 demand_empty_rest_of_line ();
7142 /* Handle the MRI ENDF pseudo-op. */
7145 s_mri_endf (int ignore ATTRIBUTE_UNUSED
)
7147 if (mri_control_stack
== NULL
7148 || mri_control_stack
->type
!= mri_for
)
7150 as_bad (_("endf without for"));
7151 ignore_rest_of_line ();
7155 colon (mri_control_stack
->next
);
7157 mri_assemble (mri_control_stack
->incr
);
7159 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
7160 mri_assemble (mri_control_stack
->incr
);
7162 free (mri_control_stack
->incr
);
7164 colon (mri_control_stack
->bottom
);
7170 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7171 ++input_line_pointer
;
7174 demand_empty_rest_of_line ();
7177 /* Handle the MRI REPEAT pseudo-op. */
7180 s_mri_repeat (int ignore ATTRIBUTE_UNUSED
)
7182 struct mri_control_info
*n
;
7184 n
= push_mri_control (mri_repeat
);
7188 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7189 ++input_line_pointer
;
7191 demand_empty_rest_of_line ();
7194 /* Handle the MRI UNTIL pseudo-op. */
7197 s_mri_until (int qual
)
7201 if (mri_control_stack
== NULL
7202 || mri_control_stack
->type
!= mri_repeat
)
7204 as_bad (_("until without repeat"));
7205 ignore_rest_of_line ();
7209 colon (mri_control_stack
->next
);
7211 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
7214 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
7215 mri_control_stack
->top
, '\0');
7217 colon (mri_control_stack
->bottom
);
7219 input_line_pointer
= s
;
7225 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7226 ++input_line_pointer
;
7229 demand_empty_rest_of_line ();
7232 /* Handle the MRI WHILE pseudo-op. */
7235 s_mri_while (int qual
)
7239 struct mri_control_info
*n
;
7241 s
= input_line_pointer
;
7242 /* We only accept '*' as introduction of comments if preceded by white space
7243 or at first column of a line (I think this can't actually happen here?)
7244 This is important when assembling:
7245 while d0 <ne> 12(a0,d0*2) do
7246 while d0 <ne> #CONST*20 do. */
7247 while (! (is_end_of_line
[(unsigned char) *s
]
7250 && (s
== input_line_pointer
7252 || *(s
-1) == '\t'))))
7255 while (*s
== ' ' || *s
== '\t')
7257 if (s
- input_line_pointer
> 1
7260 if (s
- input_line_pointer
< 2
7261 || strncasecmp (s
- 1, "DO", 2) != 0)
7263 as_bad (_("missing do"));
7264 ignore_rest_of_line ();
7268 n
= push_mri_control (mri_while
);
7272 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
7273 s
[1] == '.' ? s
[2] : '\0');
7275 input_line_pointer
= s
+ 1;
7276 if (*input_line_pointer
== '.')
7277 input_line_pointer
+= 2;
7281 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7282 ++input_line_pointer
;
7285 demand_empty_rest_of_line ();
7288 /* Handle the MRI ENDW pseudo-op. */
7291 s_mri_endw (int ignore ATTRIBUTE_UNUSED
)
7295 if (mri_control_stack
== NULL
7296 || mri_control_stack
->type
!= mri_while
)
7298 as_bad (_("endw without while"));
7299 ignore_rest_of_line ();
7303 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->next
));
7304 sprintf (buf
, "bra %s", mri_control_stack
->next
);
7308 colon (mri_control_stack
->bottom
);
7314 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7315 ++input_line_pointer
;
7318 demand_empty_rest_of_line ();
7321 /* Parse a .cpu directive. */
7324 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED
)
7331 as_bad (_("already assembled instructions"));
7332 ignore_rest_of_line ();
7336 name
= input_line_pointer
;
7337 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
7338 input_line_pointer
++;
7339 saved_char
= *input_line_pointer
;
7340 *input_line_pointer
= 0;
7342 m68k_set_cpu (name
, 1, 0);
7344 *input_line_pointer
= saved_char
;
7345 demand_empty_rest_of_line ();
7349 /* Parse a .arch directive. */
7352 s_m68k_arch (int ignored ATTRIBUTE_UNUSED
)
7359 as_bad (_("already assembled instructions"));
7360 ignore_rest_of_line ();
7364 name
= input_line_pointer
;
7365 while (*input_line_pointer
&& *input_line_pointer
!= ','
7366 && !ISSPACE (*input_line_pointer
))
7367 input_line_pointer
++;
7368 saved_char
= *input_line_pointer
;
7369 *input_line_pointer
= 0;
7371 if (m68k_set_arch (name
, 1, 0))
7373 /* Scan extensions. */
7376 *input_line_pointer
++ = saved_char
;
7377 if (!*input_line_pointer
|| ISSPACE (*input_line_pointer
))
7379 name
= input_line_pointer
;
7380 while (*input_line_pointer
&& *input_line_pointer
!= ','
7381 && !ISSPACE (*input_line_pointer
))
7382 input_line_pointer
++;
7383 saved_char
= *input_line_pointer
;
7384 *input_line_pointer
= 0;
7386 while (m68k_set_extension (name
, 1, 0));
7389 *input_line_pointer
= saved_char
;
7390 demand_empty_rest_of_line ();
7394 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7395 if none is found, the caller is responsible for emitting an error
7396 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7397 cpu name, if it begins with a '6' (possibly skipping an intervening
7398 'c'. We also allow a 'c' in the same place. if NEGATED is
7399 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7400 the option is indeed negated. */
7402 static const struct m68k_cpu
*
7403 m68k_lookup_cpu (const char *arg
, const struct m68k_cpu
*table
,
7404 int allow_m
, int *negated
)
7406 /* allow negated value? */
7411 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
7418 /* Remove 'm' or 'mc' prefix from 68k variants. */
7425 else if (arg
[1] == 'c' && arg
[2] == '6')
7429 else if (arg
[0] == 'c' && arg
[1] == '6')
7432 for (; table
->name
; table
++)
7433 if (!strcmp (arg
, table
->name
))
7435 if (table
->alias
< -1 || table
->alias
> 1)
7436 as_bad (_("`%s' is deprecated, use `%s'"),
7437 table
->name
, table
[table
->alias
< 0 ? 1 : -1].name
);
7443 /* Set the cpu, issuing errors if it is unrecognized. */
7446 m68k_set_cpu (char const *name
, int allow_m
, int silent
)
7448 const struct m68k_cpu
*cpu
;
7450 cpu
= m68k_lookup_cpu (name
, m68k_cpus
, allow_m
, NULL
);
7455 as_bad (_("cpu `%s' unrecognized"), name
);
7462 /* Set the architecture, issuing errors if it is unrecognized. */
7465 m68k_set_arch (char const *name
, int allow_m
, int silent
)
7467 const struct m68k_cpu
*arch
;
7469 arch
= m68k_lookup_cpu (name
, m68k_archs
, allow_m
, NULL
);
7474 as_bad (_("architecture `%s' unrecognized"), name
);
7477 selected_arch
= arch
;
7481 /* Set the architecture extension, issuing errors if it is
7482 unrecognized, or invalid */
7485 m68k_set_extension (char const *name
, int allow_m
, int silent
)
7488 const struct m68k_cpu
*ext
;
7490 ext
= m68k_lookup_cpu (name
, m68k_extensions
, allow_m
, &negated
);
7495 as_bad (_("extension `%s' unrecognized"), name
);
7500 not_current_architecture
|= (ext
->control_regs
7501 ? *(unsigned *)ext
->control_regs
: ext
->arch
);
7503 current_architecture
|= ext
->arch
;
7508 Invocation line includes a switch not recognized by the base assembler.
7512 const char *md_shortopts
= "lSA:m:kQ:V";
7514 const char *md_shortopts
= "lSA:m:k";
7517 struct option md_longopts
[] = {
7518 #define OPTION_PIC (OPTION_MD_BASE)
7519 {"pic", no_argument
, NULL
, OPTION_PIC
},
7520 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7521 {"register-prefix-optional", no_argument
, NULL
,
7522 OPTION_REGISTER_PREFIX_OPTIONAL
},
7523 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7524 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
7525 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7526 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
7527 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7528 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
7529 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7530 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
7531 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7532 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
7533 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7534 {"pcrel", no_argument
, NULL
, OPTION_PCREL
},
7535 {NULL
, no_argument
, NULL
, 0}
7537 size_t md_longopts_size
= sizeof (md_longopts
);
7540 md_parse_option (int c
, const char *arg
)
7544 case 'l': /* -l means keep external to 2 bit offset
7545 rather than 16 bit one. */
7546 flag_short_refs
= 1;
7549 case 'S': /* -S means that jbsr's always turn into
7551 flag_long_jumps
= 1;
7554 case OPTION_PCREL
: /* --pcrel means never turn PC-relative
7555 branches into absolute jumps. */
7556 flag_keep_pcrel
= 1;
7562 break; /* -pic, Position Independent Code. */
7564 case OPTION_REGISTER_PREFIX_OPTIONAL
:
7565 flag_reg_prefix_optional
= 1;
7566 reg_prefix_optional_seen
= 1;
7569 /* -V: SVR4 argument to print version ID. */
7571 print_version_id ();
7574 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7575 should be emitted or not. FIXME: Not implemented. */
7579 case OPTION_BITWISE_OR
:
7584 n
= (char *) xmalloc (strlen (m68k_comment_chars
) + 1);
7586 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
7590 m68k_comment_chars
= n
;
7594 case OPTION_BASE_SIZE_DEFAULT_16
:
7595 m68k_index_width_default
= SIZE_WORD
;
7598 case OPTION_BASE_SIZE_DEFAULT_32
:
7599 m68k_index_width_default
= SIZE_LONG
;
7602 case OPTION_DISP_SIZE_DEFAULT_16
:
7604 m68k_rel32_from_cmdline
= 1;
7607 case OPTION_DISP_SIZE_DEFAULT_32
:
7609 m68k_rel32_from_cmdline
= 1;
7614 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7617 /* Intentional fall-through. */
7619 if (!strncmp (arg
, "arch=", 5))
7620 m68k_set_arch (arg
+ 5, 1, 0);
7621 else if (!strncmp (arg
, "cpu=", 4))
7622 m68k_set_cpu (arg
+ 4, 1, 0);
7623 else if (m68k_set_extension (arg
, 0, 1))
7625 else if (m68k_set_arch (arg
, 0, 1))
7627 else if (m68k_set_cpu (arg
, 0, 1))
7640 /* Setup tables from the selected arch and/or cpu */
7643 m68k_init_arch (void)
7645 if (not_current_architecture
& current_architecture
)
7647 as_bad (_("architecture features both enabled and disabled"));
7648 not_current_architecture
&= ~current_architecture
;
7652 current_architecture
|= selected_arch
->arch
;
7653 control_regs
= selected_arch
->control_regs
;
7656 current_architecture
|= selected_cpu
->arch
;
7658 current_architecture
&= ~not_current_architecture
;
7660 if ((current_architecture
& (cfloat
| m68881
)) == (cfloat
| m68881
))
7662 /* Determine which float is really meant. */
7663 if (current_architecture
& (m68k_mask
& ~m68881
))
7664 current_architecture
^= cfloat
;
7666 current_architecture
^= m68881
;
7671 control_regs
= selected_cpu
->control_regs
;
7672 if (current_architecture
& ~selected_cpu
->arch
)
7674 as_bad (_("selected processor does not have all features of selected architecture"));
7675 current_architecture
7676 = selected_cpu
->arch
& ~not_current_architecture
;
7680 if ((current_architecture
& m68k_mask
)
7681 && (current_architecture
& ~m68k_mask
))
7683 as_bad (_ ("m68k and cf features both selected"));
7684 if (current_architecture
& m68k_mask
)
7685 current_architecture
&= m68k_mask
;
7687 current_architecture
&= ~m68k_mask
;
7690 /* Permit m68881 specification with all cpus; those that can't work
7691 with a coprocessor could be doing emulation. */
7692 if (current_architecture
& m68851
)
7694 if (current_architecture
& m68040
)
7695 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7697 /* What other incompatibilities could we check for? */
7699 if (cpu_of_arch (current_architecture
) < m68020
7700 || arch_coldfire_p (current_architecture
))
7701 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
7707 md_show_usage (FILE *stream
)
7709 const char *default_cpu
= TARGET_CPU
;
7712 /* Get the canonical name for the default target CPU. */
7713 if (*default_cpu
== 'm')
7715 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7717 if (strcasecmp (default_cpu
, m68k_cpus
[i
].name
) == 0)
7719 while (m68k_cpus
[i
].alias
> 0)
7721 while (m68k_cpus
[i
].alias
< 0)
7723 default_cpu
= m68k_cpus
[i
].name
;
7727 fprintf (stream
, _("\
7728 -march=<arch> set architecture\n\
7729 -mcpu=<cpu> set cpu [default %s]\n\
7731 for (i
= 0; m68k_extensions
[i
].name
; i
++)
7732 fprintf (stream
, _("\
7733 -m[no-]%-16s enable/disable%s architecture extension\n\
7734 "), m68k_extensions
[i
].name
,
7735 m68k_extensions
[i
].alias
> 0 ? " ColdFire"
7736 : m68k_extensions
[i
].alias
< 0 ? " m68k" : "");
7738 fprintf (stream
, _("\
7739 -l use 1 word for refs to undefined symbols [default 2]\n\
7740 -pic, -k generate position independent code\n\
7741 -S turn jbsr into jsr\n\
7742 --pcrel never turn PC-relative branches into absolute jumps\n\
7743 --register-prefix-optional\n\
7744 recognize register names without prefix character\n\
7745 --bitwise-or do not treat `|' as a comment character\n\
7746 --base-size-default-16 base reg without size is 16 bits\n\
7747 --base-size-default-32 base reg without size is 32 bits (default)\n\
7748 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7749 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7752 fprintf (stream
, _("Architecture variants are: "));
7753 for (i
= 0; m68k_archs
[i
].name
; i
++)
7756 fprintf (stream
, " | ");
7757 fprintf (stream
, "%s", m68k_archs
[i
].name
);
7759 fprintf (stream
, "\n");
7761 fprintf (stream
, _("Processor variants are: "));
7762 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7765 fprintf (stream
, " | ");
7766 fprintf (stream
, "%s", m68k_cpus
[i
].name
);
7768 fprintf (stream
, _("\n"));
7773 /* TEST2: Test md_assemble() */
7774 /* Warning, this routine probably doesn't work anymore. */
7778 struct m68k_it the_ins
;
7786 if (!gets (buf
) || !*buf
)
7788 if (buf
[0] == '|' || buf
[1] == '.')
7790 for (cp
= buf
; *cp
; cp
++)
7795 memset (&the_ins
, '\0', sizeof (the_ins
));
7796 m68k_ip (&the_ins
, buf
);
7799 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
7803 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
7804 for (n
= 0; n
< the_ins
.numo
; n
++)
7805 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
7807 print_the_insn (&the_ins
.opcode
[0], stdout
);
7808 (void) putchar ('\n');
7810 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
7812 if (the_ins
.operands
[n
].error
)
7814 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
7817 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
,
7818 the_ins
.operands
[n
].reg
);
7819 if (the_ins
.operands
[n
].b_const
)
7820 printf ("Constant: '%.*s', ",
7821 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
,
7822 the_ins
.operands
[n
].b_const
);
7823 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
,
7824 the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
7825 if (the_ins
.operands
[n
].b_iadd
)
7826 printf ("Iadd: '%.*s',",
7827 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
,
7828 the_ins
.operands
[n
].b_iadd
);
7837 is_label (char *str
)
7841 while (*str
&& *str
!= ' ')
7843 if (str
[-1] == ':' || str
[1] == '=')
7850 /* Possible states for relaxation:
7852 0 0 branch offset byte (bra, etc)
7856 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7860 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7867 /* We have no need to default values of symbols. */
7870 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7875 /* Round up a section size to the appropriate boundary. */
7877 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7880 /* For a.out, force the section size to be aligned. If we don't do
7881 this, BFD will align it for us, but it will not write out the
7882 final bytes of the section. This may be a bug in BFD, but it is
7883 easier to fix it here since that is how the other a.out targets
7887 align
= bfd_get_section_alignment (stdoutput
, segment
);
7888 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
7894 /* Exactly what point is a PC-relative offset relative TO?
7895 On the 68k, it is relative to the address of the first extension
7896 word. The difference between the addresses of the offset and the
7897 first extension word is stored in fx_pcrel_adjust. */
7899 md_pcrel_from (fixS
*fixP
)
7903 adjust
= fixP
->fx_pcrel_adjust
;
7906 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
7911 m68k_elf_final_processing (void)
7915 if (arch_coldfire_fpu (current_architecture
))
7916 flags
|= EF_M68K_CFV4E
;
7917 /* Set file-specific flags if this is a cpu32 processor. */
7918 if (cpu_of_arch (current_architecture
) & cpu32
)
7919 flags
|= EF_M68K_CPU32
;
7920 else if (cpu_of_arch (current_architecture
) & fido_a
)
7921 flags
|= EF_M68K_FIDO
;
7922 else if ((cpu_of_arch (current_architecture
) & m68000up
)
7923 && !(cpu_of_arch (current_architecture
) & m68020up
))
7924 flags
|= EF_M68K_M68000
;
7926 if (current_architecture
& mcfisa_a
)
7928 static const unsigned isa_features
[][2] =
7930 {EF_M68K_CF_ISA_A_NODIV
,mcfisa_a
},
7931 {EF_M68K_CF_ISA_A
, mcfisa_a
|mcfhwdiv
},
7932 {EF_M68K_CF_ISA_A_PLUS
, mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfusp
},
7933 {EF_M68K_CF_ISA_B_NOUSP
,mcfisa_a
|mcfisa_b
|mcfhwdiv
},
7934 {EF_M68K_CF_ISA_B
, mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfusp
},
7935 {EF_M68K_CF_ISA_C
, mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfusp
},
7936 {EF_M68K_CF_ISA_C_NODIV
,mcfisa_a
|mcfisa_c
|mcfusp
},
7939 static const unsigned mac_features
[][2] =
7941 {EF_M68K_CF_MAC
, mcfmac
},
7942 {EF_M68K_CF_EMAC
, mcfemac
},
7948 pattern
= (current_architecture
7949 & (mcfisa_a
|mcfisa_aa
|mcfisa_b
|mcfisa_c
|mcfhwdiv
|mcfusp
));
7950 for (ix
= 0; isa_features
[ix
][1]; ix
++)
7952 if (pattern
== isa_features
[ix
][1])
7954 flags
|= isa_features
[ix
][0];
7958 if (!isa_features
[ix
][1])
7961 as_warn (_("Not a defined coldfire architecture"));
7965 if (current_architecture
& cfloat
)
7966 flags
|= EF_M68K_CF_FLOAT
| EF_M68K_CFV4E
;
7968 pattern
= current_architecture
& (mcfmac
|mcfemac
);
7971 for (ix
= 0; mac_features
[ix
][1]; ix
++)
7973 if (pattern
== mac_features
[ix
][1])
7975 flags
|= mac_features
[ix
][0];
7979 if (!mac_features
[ix
][1])
7984 elf_elfheader (stdoutput
)->e_flags
|= flags
;
7987 /* Parse @TLSLDO and return the desired relocation. */
7988 static bfd_reloc_code_real_type
7989 m68k_elf_suffix (char **str_p
, expressionS
*exp_p
)
7998 return BFD_RELOC_UNUSED
;
8000 for (ch
= *str
, str2
= ident
;
8001 (str2
< ident
+ sizeof (ident
) - 1
8002 && (ISALNUM (ch
) || ch
== '@'));
8011 if (strncmp (ident
, "TLSLDO", 6) == 0
8014 /* Now check for identifier@suffix+constant. */
8015 if (*str
== '-' || *str
== '+')
8017 char *orig_line
= input_line_pointer
;
8018 expressionS new_exp
;
8020 input_line_pointer
= str
;
8021 expression (&new_exp
);
8022 if (new_exp
.X_op
== O_constant
)
8024 exp_p
->X_add_number
+= new_exp
.X_add_number
;
8025 str
= input_line_pointer
;
8028 if (&input_line_pointer
!= str_p
)
8029 input_line_pointer
= orig_line
;
8033 return BFD_RELOC_68K_TLS_LDO32
;
8036 return BFD_RELOC_UNUSED
;
8039 /* Handles .long <tls_symbol>+0x8000 debug info.
8040 Clobbers input_line_pointer, checks end-of-line.
8041 Adapted from tc-ppc.c:ppc_elf_cons. */
8043 m68k_elf_cons (int nbytes
/* 4=.long */)
8045 if (is_it_end_of_statement ())
8047 demand_empty_rest_of_line ();
8054 bfd_reloc_code_real_type reloc
;
8057 if (exp
.X_op
== O_symbol
8058 && *input_line_pointer
== '@'
8059 && (reloc
= m68k_elf_suffix (&input_line_pointer
,
8060 &exp
)) != BFD_RELOC_UNUSED
)
8062 reloc_howto_type
*reloc_howto
;
8065 reloc_howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
8066 size
= bfd_get_reloc_size (reloc_howto
);
8070 as_bad (_("%s relocations do not fit in %d bytes\n"),
8071 reloc_howto
->name
, nbytes
);
8078 p
= frag_more (nbytes
);
8080 if (target_big_endian
)
8081 offset
= nbytes
- size
;
8082 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
, size
,
8087 emit_expr (&exp
, (unsigned int) nbytes
);
8089 while (*input_line_pointer
++ == ',');
8091 /* Put terminator back into stream. */
8092 input_line_pointer
--;
8093 demand_empty_rest_of_line ();
8098 tc_m68k_regname_to_dw2regnum (const char *regname
)
8100 unsigned int regnum
;
8101 static const char *const regnames
[] =
8103 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
8104 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
8105 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
8109 for (regnum
= 0; regnum
< ARRAY_SIZE (regnames
); regnum
++)
8110 if (strcmp (regname
, regnames
[regnum
]) == 0)
8117 tc_m68k_frame_initial_instructions (void)
8119 static int sp_regno
= -1;
8122 sp_regno
= tc_m68k_regname_to_dw2regnum ("sp");
8124 cfi_add_CFA_def_cfa (sp_regno
, -DWARF2_CIE_DATA_ALIGNMENT
);
8125 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, DWARF2_CIE_DATA_ALIGNMENT
);
8128 /* Check and emit error if broken-word handling has failed to fix up a
8129 case-table. This is called from write.c, after doing everything it
8130 knows about how to handle broken words. */
8133 tc_m68k_check_adjusted_broken_word (offsetT new_offset
, struct broken_word
*brokwP
)
8135 if (new_offset
> 32767 || new_offset
< -32768)
8136 as_bad_where (brokwP
->frag
->fr_file
, brokwP
->frag
->fr_line
,
8137 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."),