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2000-09-03 Kazu Hirata <kazu@hxi.com>
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 #include <ctype.h>
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 #if defined (OBJ_ELF)
31 #include "elf/m68k.h"
32 #endif
33
34 /* This string holds the chars that always start a comment. If the
35 pre-processor is disabled, these aren't very useful. The macro
36 tc_comment_chars points to this. We use this, rather than the
37 usual comment_chars, so that the --bitwise-or option will work. */
38 #if defined (TE_SVR4) || defined (TE_DELTA)
39 const char *m68k_comment_chars = "|#";
40 #else
41 const char *m68k_comment_chars = "|";
42 #endif
43
44 /* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47 /* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
49 #NO_APP at the beginning of its output. */
50 /* Also note that comments like this one will always work. */
51 const char line_comment_chars[] = "#*";
52
53 const char line_separator_chars[] = ";";
54
55 /* Chars that can be used to separate mant from exp in floating point nums */
56 CONST char EXP_CHARS[] = "eE";
57
58 /* Chars that mean this number is a floating point constant, as
59 in "0f12.456" or "0d1.2345e12". */
60
61 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
62
63 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
64 changed in read.c . Ideally it shouldn't have to know about it at all,
65 but nothing is ideal around here. */
66
67 const int md_reloc_size = 8; /* Size of relocation record */
68
69 /* Are we trying to generate PIC code? If so, absolute references
70 ought to be made into linkage table references or pc-relative
71 references. Not implemented. For ELF there are other means
72 to denote pic relocations. */
73 int flag_want_pic;
74
75 static int flag_short_refs; /* -l option */
76 static int flag_long_jumps; /* -S option */
77 static int flag_keep_pcrel; /* --pcrel option. */
78
79 #ifdef REGISTER_PREFIX_OPTIONAL
80 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
81 #else
82 int flag_reg_prefix_optional;
83 #endif
84
85 /* Whether --register-prefix-optional was used on the command line. */
86 static int reg_prefix_optional_seen;
87
88 /* The floating point coprocessor to use by default. */
89 static enum m68k_register m68k_float_copnum = COP1;
90
91 /* If this is non-zero, then references to number(%pc) will be taken
92 to refer to number, rather than to %pc + number. */
93 static int m68k_abspcadd;
94
95 /* If this is non-zero, then the quick forms of the move, add, and sub
96 instructions are used when possible. */
97 static int m68k_quick = 1;
98
99 /* If this is non-zero, then if the size is not specified for a base
100 or outer displacement, the assembler assumes that the size should
101 be 32 bits. */
102 static int m68k_rel32 = 1;
103
104 /* This is non-zero if m68k_rel32 was set from the command line. */
105 static int m68k_rel32_from_cmdline;
106
107 /* The default width to use for an index register when using a base
108 displacement. */
109 static enum m68k_size m68k_index_width_default = SIZE_LONG;
110
111 /* We want to warn if any text labels are misaligned. In order to get
112 the right line number, we need to record the line number for each
113 label. */
114
115 struct label_line
116 {
117 struct label_line *next;
118 symbolS *label;
119 char *file;
120 unsigned int line;
121 int text;
122 };
123
124 /* The list of labels. */
125
126 static struct label_line *labels;
127
128 /* The current label. */
129
130 static struct label_line *current_label;
131
132 /* Its an arbitrary name: This means I don't approve of it */
133 /* See flames below */
134 static struct obstack robyn;
135
136 #define TAB(x,y) (((x)<<2)+(y))
137 #define TABTYPE(xy) ((xy) >> 2)
138 #define BYTE 0
139 #define SHORT 1
140 #define LONG 2
141 #define SZ_UNDEF 3
142 #undef BRANCH
143 /* Case `g' except when BCC68000 is applicable. */
144 #define ABRANCH 1
145 /* Coprocessor branches. */
146 #define FBRANCH 2
147 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
148 supported on all cpus. Widens to 32-bit absolute. */
149 #define PCREL 3
150 /* For inserting an extra jmp instruction with long offset on 68000,
151 for expanding conditional branches. (Not bsr or bra.) Since the
152 68000 doesn't support 32-bit displacements for conditional
153 branches, we fake it by reversing the condition and branching
154 around a jmp with an absolute long operand. */
155 #define BCC68000 4
156 /* For the DBcc "instructions". If the displacement requires 32 bits,
157 the branch-around-a-jump game is played here too. */
158 #define DBCC 5
159 /* Not currently used? */
160 #define PCLEA 6
161 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
162 in 16 or 8 bits. */
163 #define PCINDEX 7
164
165 struct m68k_incant
166 {
167 const char *m_operands;
168 unsigned long m_opcode;
169 short m_opnum;
170 short m_codenum;
171 int m_arch;
172 struct m68k_incant *m_next;
173 };
174
175 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
176 #define gettwo(x) (((x)->m_opcode)&0xffff)
177
178 static const enum m68k_register m68000_control_regs[] = { 0 };
179 static const enum m68k_register m68010_control_regs[] = {
180 SFC, DFC, USP, VBR,
181 0
182 };
183 static const enum m68k_register m68020_control_regs[] = {
184 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
185 0
186 };
187 static const enum m68k_register m68040_control_regs[] = {
188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
189 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
190 0
191 };
192 static const enum m68k_register m68060_control_regs[] = {
193 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
194 USP, VBR, URP, SRP, PCR,
195 0
196 };
197 static const enum m68k_register mcf_control_regs[] = {
198 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
199 RAMBAR0, RAMBAR1, MBAR,
200 0
201 };
202 #define cpu32_control_regs m68010_control_regs
203
204 static const enum m68k_register *control_regs;
205
206 /* internal form of a 68020 instruction */
207 struct m68k_it
208 {
209 const char *error;
210 const char *args; /* list of opcode info */
211 int numargs;
212
213 int numo; /* Number of shorts in opcode */
214 short opcode[11];
215
216 struct m68k_op operands[6];
217
218 int nexp; /* number of exprs in use */
219 struct m68k_exp exprs[4];
220
221 int nfrag; /* Number of frags we have to produce */
222 struct
223 {
224 int fragoff; /* Where in the current opcode the frag ends */
225 symbolS *fadd;
226 offsetT foff;
227 int fragty;
228 }
229 fragb[4];
230
231 int nrel; /* Num of reloc strucs in use */
232 struct
233 {
234 int n;
235 expressionS exp;
236 char wid;
237 char pcrel;
238 /* In a pc relative address the difference between the address
239 of the offset and the address that the offset is relative
240 to. This depends on the addressing mode. Basically this
241 is the value to put in the offset field to address the
242 first byte of the offset, without regarding the special
243 significance of some values (in the branch instruction, for
244 example). */
245 int pcrel_fix;
246 #ifdef OBJ_ELF
247 /* Whether this expression needs special pic relocation, and if
248 so, which. */
249 enum pic_relocation pic_reloc;
250 #endif
251 }
252 reloc[5]; /* Five is enough??? */
253 };
254
255 #define cpu_of_arch(x) ((x) & (m68000up|mcf))
256 #define float_of_arch(x) ((x) & mfloat)
257 #define mmu_of_arch(x) ((x) & mmmu)
258 #define arch_coldfire_p(x) (((x) & mcf) != 0)
259
260 /* Macros for determining if cpu supports a specific addressing mode */
261 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
262
263 static struct m68k_it the_ins; /* the instruction being assembled */
264
265 #define op(ex) ((ex)->exp.X_op)
266 #define adds(ex) ((ex)->exp.X_add_symbol)
267 #define subs(ex) ((ex)->exp.X_op_symbol)
268 #define offs(ex) ((ex)->exp.X_add_number)
269
270 /* Macros for adding things to the m68k_it struct */
271
272 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
273
274 /* Static functions. */
275
276 static void insop PARAMS ((int, const struct m68k_incant *));
277 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
278 static void add_frag PARAMS ((symbolS *, offsetT, int));
279
280 /* Like addword, but goes BEFORE general operands */
281 static void
282 insop (w, opcode)
283 int w;
284 const struct m68k_incant *opcode;
285 {
286 int z;
287 for(z=the_ins.numo;z>opcode->m_codenum;--z)
288 the_ins.opcode[z]=the_ins.opcode[z-1];
289 for(z=0;z<the_ins.nrel;z++)
290 the_ins.reloc[z].n+=2;
291 for (z = 0; z < the_ins.nfrag; z++)
292 the_ins.fragb[z].fragoff++;
293 the_ins.opcode[opcode->m_codenum]=w;
294 the_ins.numo++;
295 }
296
297 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
298 Blecch. */
299 static void
300 add_fix (width, exp, pc_rel, pc_fix)
301 int width;
302 struct m68k_exp *exp;
303 int pc_rel;
304 int pc_fix;
305 {
306 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
307 ? (the_ins.numo*2-1)
308 : (((width)=='b')
309 ? (the_ins.numo*2+1)
310 : (the_ins.numo*2)));
311 the_ins.reloc[the_ins.nrel].exp = exp->exp;
312 the_ins.reloc[the_ins.nrel].wid = width;
313 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
314 #ifdef OBJ_ELF
315 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
316 #endif
317 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
318 }
319
320 /* Cause an extra frag to be generated here, inserting up to 10 bytes
321 (that value is chosen in the frag_var call in md_assemble). TYPE
322 is the subtype of the frag to be generated; its primary type is
323 rs_machine_dependent.
324
325 The TYPE parameter is also used by md_convert_frag_1 and
326 md_estimate_size_before_relax. The appropriate type of fixup will
327 be emitted by md_convert_frag_1.
328
329 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
330 static void
331 add_frag (add, off, type)
332 symbolS *add;
333 offsetT off;
334 int type;
335 {
336 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
337 the_ins.fragb[the_ins.nfrag].fadd=add;
338 the_ins.fragb[the_ins.nfrag].foff=off;
339 the_ins.fragb[the_ins.nfrag++].fragty=type;
340 }
341
342 #define isvar(ex) \
343 (op (ex) != O_constant && op (ex) != O_big)
344
345 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
346 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
347 static void m68k_ip PARAMS ((char *));
348 static void insert_reg PARAMS ((const char *, int));
349 static void select_control_regs PARAMS ((void));
350 static void init_regtable PARAMS ((void));
351 static int reverse_16_bits PARAMS ((int in));
352 static int reverse_8_bits PARAMS ((int in));
353 static void install_gen_operand PARAMS ((int mode, int val));
354 static void install_operand PARAMS ((int mode, int val));
355 static void s_bss PARAMS ((int));
356 static void s_data1 PARAMS ((int));
357 static void s_data2 PARAMS ((int));
358 static void s_even PARAMS ((int));
359 static void s_proc PARAMS ((int));
360 static void mri_chip PARAMS ((void));
361 static void s_chip PARAMS ((int));
362 static void s_fopt PARAMS ((int));
363 static void s_opt PARAMS ((int));
364 static void s_reg PARAMS ((int));
365 static void s_restore PARAMS ((int));
366 static void s_save PARAMS ((int));
367 static void s_mri_if PARAMS ((int));
368 static void s_mri_else PARAMS ((int));
369 static void s_mri_endi PARAMS ((int));
370 static void s_mri_break PARAMS ((int));
371 static void s_mri_next PARAMS ((int));
372 static void s_mri_for PARAMS ((int));
373 static void s_mri_endf PARAMS ((int));
374 static void s_mri_repeat PARAMS ((int));
375 static void s_mri_until PARAMS ((int));
376 static void s_mri_while PARAMS ((int));
377 static void s_mri_endw PARAMS ((int));
378 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
379 static void md_convert_frag_1 PARAMS ((fragS *));
380
381 static int current_architecture;
382
383 struct m68k_cpu {
384 unsigned long arch;
385 const char *name;
386 int alias;
387 };
388
389 static const struct m68k_cpu archs[] = {
390 { m68000, "68000", 0 },
391 { m68010, "68010", 0 },
392 { m68020, "68020", 0 },
393 { m68030, "68030", 0 },
394 { m68040, "68040", 0 },
395 { m68060, "68060", 0 },
396 { cpu32, "cpu32", 0 },
397 { m68881, "68881", 0 },
398 { m68851, "68851", 0 },
399 { mcf5200, "5200", 0 },
400 { mcf5206e, "5206e", 0 },
401 { mcf5307, "5307", 0},
402 /* Aliases (effectively, so far as gas is concerned) for the above
403 cpus. */
404 { m68020, "68k", 1 },
405 { m68000, "68008", 1 },
406 { m68000, "68302", 1 },
407 { m68000, "68306", 1 },
408 { m68000, "68307", 1 },
409 { m68000, "68322", 1 },
410 { m68000, "68356", 1 },
411 { m68000, "68ec000", 1 },
412 { m68000, "68hc000", 1 },
413 { m68000, "68hc001", 1 },
414 { m68020, "68ec020", 1 },
415 { m68030, "68ec030", 1 },
416 { m68040, "68ec040", 1 },
417 { m68060, "68ec060", 1 },
418 { cpu32, "68330", 1 },
419 { cpu32, "68331", 1 },
420 { cpu32, "68332", 1 },
421 { cpu32, "68333", 1 },
422 { cpu32, "68334", 1 },
423 { cpu32, "68336", 1 },
424 { cpu32, "68340", 1 },
425 { cpu32, "68341", 1 },
426 { cpu32, "68349", 1 },
427 { cpu32, "68360", 1 },
428 { m68881, "68882", 1 },
429 { mcf5200, "5202", 1 },
430 { mcf5200, "5204", 1 },
431 { mcf5200, "5206", 1 },
432 };
433
434 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
435
436 /* BCC68000 is for patching in an extra jmp instruction for long offsets
437 on the 68000. The 68000 doesn't support long branches with branchs */
438
439 /* This table desribes how you change sizes for the various types of variable
440 size expressions. This version only supports two kinds. */
441
442 /* Note that calls to frag_var need to specify the maximum expansion
443 needed; this is currently 10 bytes for DBCC. */
444
445 /* The fields are:
446 How far Forward this mode will reach:
447 How far Backward this mode will reach:
448 How many bytes this mode will add to the size of the frag
449 Which mode to go to if the offset won't fit in this one
450 */
451 relax_typeS md_relax_table[] =
452 {
453 {1, 1, 0, 0}, /* First entries aren't used */
454 {1, 1, 0, 0}, /* For no good reason except */
455 {1, 1, 0, 0}, /* that the VAX doesn't either */
456 {1, 1, 0, 0},
457
458 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
459 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
460 {0, 0, 4, 0},
461 {1, 1, 0, 0},
462
463 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
464 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
465 {0, 0, 4, 0},
466 {1, 1, 0, 0},
467
468 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
469 {(32767), (-32768), 2, TAB (PCREL, LONG)},
470 {0, 0, 4, 0},
471 {1, 1, 0, 0},
472
473 {(127), (-128), 0, TAB (BCC68000, SHORT)},
474 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
475 {0, 0, 6, 0}, /* jmp long space */
476 {1, 1, 0, 0},
477
478 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
479 {(32767), (-32768), 2, TAB (DBCC, LONG)},
480 {0, 0, 10, 0}, /* bra/jmp long space */
481 {1, 1, 0, 0},
482
483 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
484 {32767, -32768, 2, TAB (PCLEA, LONG)},
485 {0, 0, 6, 0},
486 {1, 1, 0, 0},
487
488 /* For, e.g., jmp pcrel indexed. */
489 {125, -130, 0, TAB (PCINDEX, SHORT)},
490 {32765, -32770, 2, TAB (PCINDEX, LONG)},
491 {0, 0, 4, 0},
492 {1, 1, 0, 0},
493 };
494
495 /* These are the machine dependent pseudo-ops. These are included so
496 the assembler can work on the output from the SUN C compiler, which
497 generates these.
498 */
499
500 /* This table describes all the machine specific pseudo-ops the assembler
501 has to support. The fields are:
502 pseudo-op name without dot
503 function to call to execute this pseudo-op
504 Integer arg to pass to the function
505 */
506 const pseudo_typeS md_pseudo_table[] =
507 {
508 {"data1", s_data1, 0},
509 {"data2", s_data2, 0},
510 {"bss", s_bss, 0},
511 {"even", s_even, 0},
512 {"skip", s_space, 0},
513 {"proc", s_proc, 0},
514 #if defined (TE_SUN3) || defined (OBJ_ELF)
515 {"align", s_align_bytes, 0},
516 #endif
517 #ifdef OBJ_ELF
518 {"swbeg", s_ignore, 0},
519 #endif
520 {"extend", float_cons, 'x'},
521 {"ldouble", float_cons, 'x'},
522
523 /* The following pseudo-ops are supported for MRI compatibility. */
524 {"chip", s_chip, 0},
525 {"comline", s_space, 1},
526 {"fopt", s_fopt, 0},
527 {"mask2", s_ignore, 0},
528 {"opt", s_opt, 0},
529 {"reg", s_reg, 0},
530 {"restore", s_restore, 0},
531 {"save", s_save, 0},
532
533 {"if", s_mri_if, 0},
534 {"if.b", s_mri_if, 'b'},
535 {"if.w", s_mri_if, 'w'},
536 {"if.l", s_mri_if, 'l'},
537 {"else", s_mri_else, 0},
538 {"else.s", s_mri_else, 's'},
539 {"else.l", s_mri_else, 'l'},
540 {"endi", s_mri_endi, 0},
541 {"break", s_mri_break, 0},
542 {"break.s", s_mri_break, 's'},
543 {"break.l", s_mri_break, 'l'},
544 {"next", s_mri_next, 0},
545 {"next.s", s_mri_next, 's'},
546 {"next.l", s_mri_next, 'l'},
547 {"for", s_mri_for, 0},
548 {"for.b", s_mri_for, 'b'},
549 {"for.w", s_mri_for, 'w'},
550 {"for.l", s_mri_for, 'l'},
551 {"endf", s_mri_endf, 0},
552 {"repeat", s_mri_repeat, 0},
553 {"until", s_mri_until, 0},
554 {"until.b", s_mri_until, 'b'},
555 {"until.w", s_mri_until, 'w'},
556 {"until.l", s_mri_until, 'l'},
557 {"while", s_mri_while, 0},
558 {"while.b", s_mri_while, 'b'},
559 {"while.w", s_mri_while, 'w'},
560 {"while.l", s_mri_while, 'l'},
561 {"endw", s_mri_endw, 0},
562
563 {0, 0, 0}
564 };
565
566
567 /* The mote pseudo ops are put into the opcode table, since they
568 don't start with a . they look like opcodes to gas.
569 */
570
571 #ifdef M68KCOFF
572 extern void obj_coff_section PARAMS ((int));
573 #endif
574
575 CONST pseudo_typeS mote_pseudo_table[] =
576 {
577
578 {"dcl", cons, 4},
579 {"dc", cons, 2},
580 {"dcw", cons, 2},
581 {"dcb", cons, 1},
582
583 {"dsl", s_space, 4},
584 {"ds", s_space, 2},
585 {"dsw", s_space, 2},
586 {"dsb", s_space, 1},
587
588 {"xdef", s_globl, 0},
589 #ifdef OBJ_ELF
590 {"align", s_align_bytes, 0},
591 #else
592 {"align", s_align_ptwo, 0},
593 #endif
594 #ifdef M68KCOFF
595 {"sect", obj_coff_section, 0},
596 {"section", obj_coff_section, 0},
597 #endif
598 {0, 0, 0}
599 };
600
601 #define issbyte(x) ((x)>=-128 && (x)<=127)
602 #define isubyte(x) ((x)>=0 && (x)<=255)
603 #define issword(x) ((x)>=-32768 && (x)<=32767)
604 #define isuword(x) ((x)>=0 && (x)<=65535)
605
606 #define isbyte(x) ((x)>= -255 && (x)<=255)
607 #define isword(x) ((x)>=-65536 && (x)<=65535)
608 #define islong(x) (1)
609
610 extern char *input_line_pointer;
611
612 static char mklower_table[256];
613 #define mklower(c) (mklower_table[(unsigned char)(c)])
614 static char notend_table[256];
615 static char alt_notend_table[256];
616 #define notend(s) \
617 (! (notend_table[(unsigned char) *s] \
618 || (*s == ':' \
619 && alt_notend_table[(unsigned char) s[1]])))
620
621 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
622
623 #ifdef NO_PCREL_RELOCS
624
625 int
626 make_pcrel_absolute(fixP, add_number)
627 fixS *fixP;
628 long *add_number;
629 {
630 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
631
632 /* rewrite the PC relative instructions to absolute address ones.
633 * these are rumoured to be faster, and the apollo linker refuses
634 * to deal with the PC relative relocations.
635 */
636 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
637 {
638 opcode[0] = 0x4e;
639 opcode[1] = 0xf9;
640 }
641 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
642 {
643 opcode[0] = 0x4e;
644 opcode[1] = 0xb9;
645 }
646 else
647 as_fatal (_("Unknown PC relative instruction"));
648 *add_number -= 4;
649 return 0;
650 }
651
652 #endif /* NO_PCREL_RELOCS */
653
654 short
655 tc_coff_fix2rtype (fixP)
656 fixS *fixP;
657 {
658 if (fixP->fx_tcbit && fixP->fx_size == 4)
659 return R_RELLONG_NEG;
660 #ifdef NO_PCREL_RELOCS
661 know (fixP->fx_pcrel == 0);
662 return (fixP->fx_size == 1 ? R_RELBYTE
663 : fixP->fx_size == 2 ? R_DIR16
664 : R_DIR32);
665 #else
666 return (fixP->fx_pcrel ?
667 (fixP->fx_size == 1 ? R_PCRBYTE :
668 fixP->fx_size == 2 ? R_PCRWORD :
669 R_PCRLONG) :
670 (fixP->fx_size == 1 ? R_RELBYTE :
671 fixP->fx_size == 2 ? R_RELWORD :
672 R_RELLONG));
673 #endif
674 }
675
676 #endif
677
678 #ifdef OBJ_ELF
679
680 /* Compute the relocation code for a fixup of SIZE bytes, using pc
681 relative relocation if PCREL is non-zero. PIC says whether a special
682 pic relocation was requested. */
683
684 static bfd_reloc_code_real_type get_reloc_code
685 PARAMS ((int, int, enum pic_relocation));
686
687 static bfd_reloc_code_real_type
688 get_reloc_code (size, pcrel, pic)
689 int size;
690 int pcrel;
691 enum pic_relocation pic;
692 {
693 switch (pic)
694 {
695 case pic_got_pcrel:
696 switch (size)
697 {
698 case 1:
699 return BFD_RELOC_8_GOT_PCREL;
700 case 2:
701 return BFD_RELOC_16_GOT_PCREL;
702 case 4:
703 return BFD_RELOC_32_GOT_PCREL;
704 }
705 break;
706
707 case pic_got_off:
708 switch (size)
709 {
710 case 1:
711 return BFD_RELOC_8_GOTOFF;
712 case 2:
713 return BFD_RELOC_16_GOTOFF;
714 case 4:
715 return BFD_RELOC_32_GOTOFF;
716 }
717 break;
718
719 case pic_plt_pcrel:
720 switch (size)
721 {
722 case 1:
723 return BFD_RELOC_8_PLT_PCREL;
724 case 2:
725 return BFD_RELOC_16_PLT_PCREL;
726 case 4:
727 return BFD_RELOC_32_PLT_PCREL;
728 }
729 break;
730
731 case pic_plt_off:
732 switch (size)
733 {
734 case 1:
735 return BFD_RELOC_8_PLTOFF;
736 case 2:
737 return BFD_RELOC_16_PLTOFF;
738 case 4:
739 return BFD_RELOC_32_PLTOFF;
740 }
741 break;
742
743 case pic_none:
744 if (pcrel)
745 {
746 switch (size)
747 {
748 case 1:
749 return BFD_RELOC_8_PCREL;
750 case 2:
751 return BFD_RELOC_16_PCREL;
752 case 4:
753 return BFD_RELOC_32_PCREL;
754 }
755 }
756 else
757 {
758 switch (size)
759 {
760 case 1:
761 return BFD_RELOC_8;
762 case 2:
763 return BFD_RELOC_16;
764 case 4:
765 return BFD_RELOC_32;
766 }
767 }
768 }
769
770 if (pcrel)
771 {
772 if (pic == pic_none)
773 as_bad (_("Can not do %d byte pc-relative relocation"), size);
774 else
775 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
776 }
777 else
778 {
779 if (pic == pic_none)
780 as_bad (_("Can not do %d byte relocation"), size);
781 else
782 as_bad (_("Can not do %d byte pic relocation"), size);
783 }
784
785 return BFD_RELOC_NONE;
786 }
787
788 /* Here we decide which fixups can be adjusted to make them relative
789 to the beginning of the section instead of the symbol. Basically
790 we need to make sure that the dynamic relocations are done
791 correctly, so in some cases we force the original symbol to be
792 used. */
793 int
794 tc_m68k_fix_adjustable (fixP)
795 fixS *fixP;
796 {
797 /* Prevent all adjustments to global symbols. */
798 if (S_IS_EXTERNAL (fixP->fx_addsy)
799 || S_IS_WEAK (fixP->fx_addsy))
800 return 0;
801
802 /* adjust_reloc_syms doesn't know about the GOT */
803 switch (fixP->fx_r_type)
804 {
805 case BFD_RELOC_8_GOT_PCREL:
806 case BFD_RELOC_16_GOT_PCREL:
807 case BFD_RELOC_32_GOT_PCREL:
808 case BFD_RELOC_8_GOTOFF:
809 case BFD_RELOC_16_GOTOFF:
810 case BFD_RELOC_32_GOTOFF:
811 case BFD_RELOC_8_PLT_PCREL:
812 case BFD_RELOC_16_PLT_PCREL:
813 case BFD_RELOC_32_PLT_PCREL:
814 case BFD_RELOC_8_PLTOFF:
815 case BFD_RELOC_16_PLTOFF:
816 case BFD_RELOC_32_PLTOFF:
817 return 0;
818
819 case BFD_RELOC_VTABLE_INHERIT:
820 case BFD_RELOC_VTABLE_ENTRY:
821 return 0;
822
823 default:
824 return 1;
825 }
826 }
827
828 #else /* !OBJ_ELF */
829
830 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
831
832 #endif /* OBJ_ELF */
833
834 #ifdef BFD_ASSEMBLER
835
836 arelent *
837 tc_gen_reloc (section, fixp)
838 asection *section;
839 fixS *fixp;
840 {
841 arelent *reloc;
842 bfd_reloc_code_real_type code;
843
844 if (fixp->fx_tcbit)
845 abort ();
846
847 if (fixp->fx_r_type != BFD_RELOC_NONE)
848 {
849 code = fixp->fx_r_type;
850
851 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
852 that fixup_segment converted a non-PC relative reloc into a
853 PC relative reloc. In such a case, we need to convert the
854 reloc code. */
855 if (fixp->fx_pcrel)
856 {
857 switch (code)
858 {
859 case BFD_RELOC_8:
860 code = BFD_RELOC_8_PCREL;
861 break;
862 case BFD_RELOC_16:
863 code = BFD_RELOC_16_PCREL;
864 break;
865 case BFD_RELOC_32:
866 code = BFD_RELOC_32_PCREL;
867 break;
868 case BFD_RELOC_8_PCREL:
869 case BFD_RELOC_16_PCREL:
870 case BFD_RELOC_32_PCREL:
871 case BFD_RELOC_8_GOT_PCREL:
872 case BFD_RELOC_16_GOT_PCREL:
873 case BFD_RELOC_32_GOT_PCREL:
874 case BFD_RELOC_8_GOTOFF:
875 case BFD_RELOC_16_GOTOFF:
876 case BFD_RELOC_32_GOTOFF:
877 case BFD_RELOC_8_PLT_PCREL:
878 case BFD_RELOC_16_PLT_PCREL:
879 case BFD_RELOC_32_PLT_PCREL:
880 case BFD_RELOC_8_PLTOFF:
881 case BFD_RELOC_16_PLTOFF:
882 case BFD_RELOC_32_PLTOFF:
883 break;
884 default:
885 as_bad_where (fixp->fx_file, fixp->fx_line,
886 _("Cannot make %s relocation PC relative"),
887 bfd_get_reloc_code_name (code));
888 }
889 }
890 }
891 else
892 {
893 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
894 switch (F (fixp->fx_size, fixp->fx_pcrel))
895 {
896 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
897 MAP (1, 0, BFD_RELOC_8);
898 MAP (2, 0, BFD_RELOC_16);
899 MAP (4, 0, BFD_RELOC_32);
900 MAP (1, 1, BFD_RELOC_8_PCREL);
901 MAP (2, 1, BFD_RELOC_16_PCREL);
902 MAP (4, 1, BFD_RELOC_32_PCREL);
903 default:
904 abort ();
905 }
906 }
907 #undef F
908 #undef MAP
909
910 reloc = (arelent *) xmalloc (sizeof (arelent));
911 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
912 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
913 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
914 #ifndef OBJ_ELF
915 if (fixp->fx_pcrel)
916 reloc->addend = fixp->fx_addnumber;
917 else
918 reloc->addend = 0;
919 #else
920 if (!fixp->fx_pcrel)
921 reloc->addend = fixp->fx_addnumber;
922 else
923 reloc->addend = (section->vma
924 + (fixp->fx_pcrel_adjust == 64
925 ? -1 : fixp->fx_pcrel_adjust)
926 + fixp->fx_addnumber
927 + md_pcrel_from (fixp));
928 #endif
929
930 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
931 assert (reloc->howto != 0);
932
933 return reloc;
934 }
935
936 #endif /* BFD_ASSEMBLER */
937
938 /* Return zero if the reference to SYMBOL from within the same segment may
939 be relaxed. */
940 #ifdef OBJ_ELF
941
942 /* On an ELF system, we can't relax an externally visible symbol,
943 because it may be overridden by a shared library. However, if
944 TARGET_OS is "elf", then we presume that we are assembling for an
945 embedded system, in which case we don't have to worry about shared
946 libraries, and we can relax anything. */
947
948 #define relaxable_symbol(symbol) \
949 (strcmp (TARGET_OS, "elf") == 0 \
950 || (! S_IS_EXTERNAL (symbol) \
951 && ! S_IS_WEAK (symbol)))
952
953 #else
954
955 #define relaxable_symbol(symbol) 1
956
957 #endif
958
959 /* Handle of the OPCODE hash table. NULL means any use before
960 m68k_ip_begin() will crash. */
961 static struct hash_control *op_hash;
962 \f
963 /* Assemble an m68k instruction. */
964
965 static void
966 m68k_ip (instring)
967 char *instring;
968 {
969 register char *p;
970 register struct m68k_op *opP;
971 register const struct m68k_incant *opcode;
972 register const char *s;
973 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
974 char *pdot, *pdotmove;
975 enum m68k_size siz1, siz2;
976 char c;
977 int losing;
978 int opsfound;
979 LITTLENUM_TYPE words[6];
980 LITTLENUM_TYPE *wordp;
981 unsigned long ok_arch = 0;
982
983 if (*instring == ' ')
984 instring++; /* skip leading whitespace */
985
986 /* Scan up to end of operation-code, which MUST end in end-of-string
987 or exactly 1 space. */
988 pdot = 0;
989 for (p = instring; *p != '\0'; p++)
990 {
991 if (*p == ' ')
992 break;
993 if (*p == '.')
994 pdot = p;
995 }
996
997 if (p == instring)
998 {
999 the_ins.error = _("No operator");
1000 return;
1001 }
1002
1003 /* p now points to the end of the opcode name, probably whitespace.
1004 Make sure the name is null terminated by clobbering the
1005 whitespace, look it up in the hash table, then fix it back.
1006 Remove a dot, first, since the opcode tables have none. */
1007 if (pdot != NULL)
1008 {
1009 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1010 *pdotmove = pdotmove[1];
1011 p--;
1012 }
1013
1014 c = *p;
1015 *p = '\0';
1016 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1017 *p = c;
1018
1019 if (pdot != NULL)
1020 {
1021 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1022 *pdotmove = pdotmove[-1];
1023 *pdot = '.';
1024 ++p;
1025 }
1026
1027 if (opcode == NULL)
1028 {
1029 the_ins.error = _("Unknown operator");
1030 return;
1031 }
1032
1033 /* found a legitimate opcode, start matching operands */
1034 while (*p == ' ')
1035 ++p;
1036
1037 if (opcode->m_operands == 0)
1038 {
1039 char *old = input_line_pointer;
1040 *old = '\n';
1041 input_line_pointer = p;
1042 /* Ahh - it's a motorola style psuedo op */
1043 mote_pseudo_table[opcode->m_opnum].poc_handler
1044 (mote_pseudo_table[opcode->m_opnum].poc_val);
1045 input_line_pointer = old;
1046 *old = 0;
1047
1048 return;
1049 }
1050
1051 if (flag_mri && opcode->m_opnum == 0)
1052 {
1053 /* In MRI mode, random garbage is allowed after an instruction
1054 which accepts no operands. */
1055 the_ins.args = opcode->m_operands;
1056 the_ins.numargs = opcode->m_opnum;
1057 the_ins.numo = opcode->m_codenum;
1058 the_ins.opcode[0] = getone (opcode);
1059 the_ins.opcode[1] = gettwo (opcode);
1060 return;
1061 }
1062
1063 for (opP = &the_ins.operands[0]; *p; opP++)
1064 {
1065 p = crack_operand (p, opP);
1066
1067 if (opP->error)
1068 {
1069 the_ins.error = opP->error;
1070 return;
1071 }
1072 }
1073
1074 opsfound = opP - &the_ins.operands[0];
1075
1076 /* This ugly hack is to support the floating pt opcodes in their
1077 standard form. Essentially, we fake a first enty of type COP#1 */
1078 if (opcode->m_operands[0] == 'I')
1079 {
1080 int n;
1081
1082 for (n = opsfound; n > 0; --n)
1083 the_ins.operands[n] = the_ins.operands[n - 1];
1084
1085 memset ((char *) (&the_ins.operands[0]), '\0',
1086 sizeof (the_ins.operands[0]));
1087 the_ins.operands[0].mode = CONTROL;
1088 the_ins.operands[0].reg = m68k_float_copnum;
1089 opsfound++;
1090 }
1091
1092 /* We've got the operands. Find an opcode that'll accept them */
1093 for (losing = 0;;)
1094 {
1095 /* If we didn't get the right number of ops, or we have no
1096 common model with this pattern then reject this pattern. */
1097
1098 ok_arch |= opcode->m_arch;
1099 if (opsfound != opcode->m_opnum
1100 || ((opcode->m_arch & current_architecture) == 0))
1101 ++losing;
1102 else
1103 {
1104 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1105 *s && !losing;
1106 s += 2, opP++)
1107 {
1108 /* Warning: this switch is huge! */
1109 /* I've tried to organize the cases into this order:
1110 non-alpha first, then alpha by letter. Lower-case
1111 goes directly before uppercase counterpart. */
1112 /* Code with multiple case ...: gets sorted by the lowest
1113 case ... it belongs to. I hope this makes sense. */
1114 switch (*s)
1115 {
1116 case '!':
1117 switch (opP->mode)
1118 {
1119 case IMMED:
1120 case DREG:
1121 case AREG:
1122 case FPREG:
1123 case CONTROL:
1124 case AINC:
1125 case ADEC:
1126 case REGLST:
1127 losing++;
1128 break;
1129 default:
1130 break;
1131 }
1132 break;
1133
1134 case '<':
1135 switch (opP->mode)
1136 {
1137 case DREG:
1138 case AREG:
1139 case FPREG:
1140 case CONTROL:
1141 case IMMED:
1142 case ADEC:
1143 case REGLST:
1144 losing++;
1145 break;
1146 default:
1147 break;
1148 }
1149 break;
1150
1151 case '>':
1152 switch (opP->mode)
1153 {
1154 case DREG:
1155 case AREG:
1156 case FPREG:
1157 case CONTROL:
1158 case IMMED:
1159 case AINC:
1160 case REGLST:
1161 losing++;
1162 break;
1163 case ABSL:
1164 break;
1165 default:
1166 if (opP->reg == PC
1167 || opP->reg == ZPC)
1168 losing++;
1169 break;
1170 }
1171 break;
1172
1173 case 'm':
1174 switch (opP->mode)
1175 {
1176 case DREG:
1177 case AREG:
1178 case AINDR:
1179 case AINC:
1180 case ADEC:
1181 break;
1182 default:
1183 losing++;
1184 }
1185 break;
1186
1187 case 'n':
1188 switch (opP->mode)
1189 {
1190 case DISP:
1191 break;
1192 default:
1193 losing++;
1194 }
1195 break;
1196
1197 case 'o':
1198 switch (opP->mode)
1199 {
1200 case BASE:
1201 case ABSL:
1202 case IMMED:
1203 break;
1204 default:
1205 losing++;
1206 }
1207 break;
1208
1209 case 'p':
1210 switch (opP->mode)
1211 {
1212 case DREG:
1213 case AREG:
1214 case AINDR:
1215 case AINC:
1216 case ADEC:
1217 break;
1218 case DISP:
1219 if (opP->reg == PC || opP->reg == ZPC)
1220 losing++;
1221 break;
1222 default:
1223 losing++;
1224 }
1225 break;
1226
1227 case 'q':
1228 switch (opP->mode)
1229 {
1230 case DREG:
1231 case AINDR:
1232 case AINC:
1233 case ADEC:
1234 break;
1235 case DISP:
1236 if (opP->reg == PC || opP->reg == ZPC)
1237 losing++;
1238 break;
1239 default:
1240 losing++;
1241 break;
1242 }
1243 break;
1244
1245 case 'v':
1246 switch (opP->mode)
1247 {
1248 case DREG:
1249 case AINDR:
1250 case AINC:
1251 case ADEC:
1252 case ABSL:
1253 break;
1254 case DISP:
1255 if (opP->reg == PC || opP->reg == ZPC)
1256 losing++;
1257 break;
1258 default:
1259 losing++;
1260 break;
1261 }
1262 break;
1263
1264 case '#':
1265 if (opP->mode != IMMED)
1266 losing++;
1267 else if (s[1] == 'b'
1268 && ! isvar (&opP->disp)
1269 && (opP->disp.exp.X_op != O_constant
1270 || ! isbyte (opP->disp.exp.X_add_number)))
1271 losing++;
1272 else if (s[1] == 'B'
1273 && ! isvar (&opP->disp)
1274 && (opP->disp.exp.X_op != O_constant
1275 || ! issbyte (opP->disp.exp.X_add_number)))
1276 losing++;
1277 else if (s[1] == 'w'
1278 && ! isvar (&opP->disp)
1279 && (opP->disp.exp.X_op != O_constant
1280 || ! isword (opP->disp.exp.X_add_number)))
1281 losing++;
1282 else if (s[1] == 'W'
1283 && ! isvar (&opP->disp)
1284 && (opP->disp.exp.X_op != O_constant
1285 || ! issword (opP->disp.exp.X_add_number)))
1286 losing++;
1287 break;
1288
1289 case '^':
1290 case 'T':
1291 if (opP->mode != IMMED)
1292 losing++;
1293 break;
1294
1295 case '$':
1296 if (opP->mode == AREG
1297 || opP->mode == CONTROL
1298 || opP->mode == FPREG
1299 || opP->mode == IMMED
1300 || opP->mode == REGLST
1301 || (opP->mode != ABSL
1302 && (opP->reg == PC
1303 || opP->reg == ZPC)))
1304 losing++;
1305 break;
1306
1307 case '%':
1308 if (opP->mode == CONTROL
1309 || opP->mode == FPREG
1310 || opP->mode == REGLST
1311 || opP->mode == IMMED
1312 || (opP->mode != ABSL
1313 && (opP->reg == PC
1314 || opP->reg == ZPC)))
1315 losing++;
1316 break;
1317
1318 case '&':
1319 switch (opP->mode)
1320 {
1321 case DREG:
1322 case AREG:
1323 case FPREG:
1324 case CONTROL:
1325 case IMMED:
1326 case AINC:
1327 case ADEC:
1328 case REGLST:
1329 losing++;
1330 break;
1331 case ABSL:
1332 break;
1333 default:
1334 if (opP->reg == PC
1335 || opP->reg == ZPC)
1336 losing++;
1337 break;
1338 }
1339 break;
1340
1341 case '*':
1342 if (opP->mode == CONTROL
1343 || opP->mode == FPREG
1344 || opP->mode == REGLST)
1345 losing++;
1346 break;
1347
1348 case '+':
1349 if (opP->mode != AINC)
1350 losing++;
1351 break;
1352
1353 case '-':
1354 if (opP->mode != ADEC)
1355 losing++;
1356 break;
1357
1358 case '/':
1359 switch (opP->mode)
1360 {
1361 case AREG:
1362 case CONTROL:
1363 case FPREG:
1364 case AINC:
1365 case ADEC:
1366 case IMMED:
1367 case REGLST:
1368 losing++;
1369 break;
1370 default:
1371 break;
1372 }
1373 break;
1374
1375 case ';':
1376 switch (opP->mode)
1377 {
1378 case AREG:
1379 case CONTROL:
1380 case FPREG:
1381 case REGLST:
1382 losing++;
1383 break;
1384 default:
1385 break;
1386 }
1387 break;
1388
1389 case '?':
1390 switch (opP->mode)
1391 {
1392 case AREG:
1393 case CONTROL:
1394 case FPREG:
1395 case AINC:
1396 case ADEC:
1397 case IMMED:
1398 case REGLST:
1399 losing++;
1400 break;
1401 case ABSL:
1402 break;
1403 default:
1404 if (opP->reg == PC || opP->reg == ZPC)
1405 losing++;
1406 break;
1407 }
1408 break;
1409
1410 case '@':
1411 switch (opP->mode)
1412 {
1413 case AREG:
1414 case CONTROL:
1415 case FPREG:
1416 case IMMED:
1417 case REGLST:
1418 losing++;
1419 break;
1420 default:
1421 break;
1422 }
1423 break;
1424
1425 case '~': /* For now! (JF FOO is this right?) */
1426 switch (opP->mode)
1427 {
1428 case DREG:
1429 case AREG:
1430 case CONTROL:
1431 case FPREG:
1432 case IMMED:
1433 case REGLST:
1434 losing++;
1435 break;
1436 case ABSL:
1437 break;
1438 default:
1439 if (opP->reg == PC
1440 || opP->reg == ZPC)
1441 losing++;
1442 break;
1443 }
1444 break;
1445
1446 case '3':
1447 if (opP->mode != CONTROL
1448 || (opP->reg != TT0 && opP->reg != TT1))
1449 losing++;
1450 break;
1451
1452 case 'A':
1453 if (opP->mode != AREG)
1454 losing++;
1455 break;
1456
1457 case 'a':
1458 if (opP->mode != AINDR)
1459 ++losing;
1460 break;
1461
1462 case 'B': /* FOO */
1463 if (opP->mode != ABSL
1464 || (flag_long_jumps
1465 && strncmp (instring, "jbsr", 4) == 0))
1466 losing++;
1467 break;
1468
1469 case 'C':
1470 if (opP->mode != CONTROL || opP->reg != CCR)
1471 losing++;
1472 break;
1473
1474 case 'd':
1475 if (opP->mode != DISP
1476 || opP->reg < ADDR0
1477 || opP->reg > ADDR7)
1478 losing++;
1479 break;
1480
1481 case 'D':
1482 if (opP->mode != DREG)
1483 losing++;
1484 break;
1485
1486 case 'E':
1487 if (opP->reg != ACC)
1488 losing++;
1489 break;
1490
1491 case 'F':
1492 if (opP->mode != FPREG)
1493 losing++;
1494 break;
1495
1496 case 'G':
1497 if (opP->reg != MACSR)
1498 losing++;
1499 break;
1500
1501 case 'H':
1502 if (opP->reg != MASK)
1503 losing++;
1504 break;
1505
1506 case 'I':
1507 if (opP->mode != CONTROL
1508 || opP->reg < COP0
1509 || opP->reg > COP7)
1510 losing++;
1511 break;
1512
1513 case 'J':
1514 if (opP->mode != CONTROL
1515 || opP->reg < USP
1516 || opP->reg > last_movec_reg)
1517 losing++;
1518 else
1519 {
1520 const enum m68k_register *rp;
1521 for (rp = control_regs; *rp; rp++)
1522 if (*rp == opP->reg)
1523 break;
1524 if (*rp == 0)
1525 losing++;
1526 }
1527 break;
1528
1529 case 'k':
1530 if (opP->mode != IMMED)
1531 losing++;
1532 break;
1533
1534 case 'l':
1535 case 'L':
1536 if (opP->mode == DREG
1537 || opP->mode == AREG
1538 || opP->mode == FPREG)
1539 {
1540 if (s[1] == '8')
1541 losing++;
1542 else
1543 {
1544 switch (opP->mode)
1545 {
1546 case DREG:
1547 opP->mask = 1 << (opP->reg - DATA0);
1548 break;
1549 case AREG:
1550 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1551 break;
1552 case FPREG:
1553 opP->mask = 1 << (opP->reg - FP0 + 16);
1554 break;
1555 default:
1556 abort ();
1557 }
1558 opP->mode = REGLST;
1559 }
1560 }
1561 else if (opP->mode == CONTROL)
1562 {
1563 if (s[1] != '8')
1564 losing++;
1565 else
1566 {
1567 switch (opP->reg)
1568 {
1569 case FPI:
1570 opP->mask = 1 << 24;
1571 break;
1572 case FPS:
1573 opP->mask = 1 << 25;
1574 break;
1575 case FPC:
1576 opP->mask = 1 << 26;
1577 break;
1578 default:
1579 losing++;
1580 break;
1581 }
1582 opP->mode = REGLST;
1583 }
1584 }
1585 else if (opP->mode != REGLST)
1586 losing++;
1587 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1588 losing++;
1589 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1590 losing++;
1591 break;
1592
1593 case 'M':
1594 if (opP->mode != IMMED)
1595 losing++;
1596 else if (opP->disp.exp.X_op != O_constant
1597 || ! issbyte (opP->disp.exp.X_add_number))
1598 losing++;
1599 else if (! m68k_quick
1600 && instring[3] != 'q'
1601 && instring[4] != 'q')
1602 losing++;
1603 break;
1604
1605 case 'O':
1606 if (opP->mode != DREG
1607 && opP->mode != IMMED
1608 && opP->mode != ABSL)
1609 losing++;
1610 break;
1611
1612 case 'Q':
1613 if (opP->mode != IMMED)
1614 losing++;
1615 else if (opP->disp.exp.X_op != O_constant
1616 || opP->disp.exp.X_add_number < 1
1617 || opP->disp.exp.X_add_number > 8)
1618 losing++;
1619 else if (! m68k_quick
1620 && (strncmp (instring, "add", 3) == 0
1621 || strncmp (instring, "sub", 3) == 0)
1622 && instring[3] != 'q')
1623 losing++;
1624 break;
1625
1626 case 'R':
1627 if (opP->mode != DREG && opP->mode != AREG)
1628 losing++;
1629 break;
1630
1631 case 'r':
1632 if (opP->mode != AINDR
1633 && (opP->mode != BASE
1634 || (opP->reg != 0
1635 && opP->reg != ZADDR0)
1636 || opP->disp.exp.X_op != O_absent
1637 || ((opP->index.reg < DATA0
1638 || opP->index.reg > DATA7)
1639 && (opP->index.reg < ADDR0
1640 || opP->index.reg > ADDR7))
1641 || opP->index.size != SIZE_UNSPEC
1642 || opP->index.scale != 1))
1643 losing++;
1644 break;
1645
1646 case 's':
1647 if (opP->mode != CONTROL
1648 || ! (opP->reg == FPI
1649 || opP->reg == FPS
1650 || opP->reg == FPC))
1651 losing++;
1652 break;
1653
1654 case 'S':
1655 if (opP->mode != CONTROL || opP->reg != SR)
1656 losing++;
1657 break;
1658
1659 case 't':
1660 if (opP->mode != IMMED)
1661 losing++;
1662 else if (opP->disp.exp.X_op != O_constant
1663 || opP->disp.exp.X_add_number < 0
1664 || opP->disp.exp.X_add_number > 7)
1665 losing++;
1666 break;
1667
1668 case 'U':
1669 if (opP->mode != CONTROL || opP->reg != USP)
1670 losing++;
1671 break;
1672
1673 /* JF these are out of order. We could put them
1674 in order if we were willing to put up with
1675 bunches of #ifdef m68851s in the code.
1676
1677 Don't forget that you need these operands
1678 to use 68030 MMU instructions. */
1679 #ifndef NO_68851
1680 /* Memory addressing mode used by pflushr */
1681 case '|':
1682 if (opP->mode == CONTROL
1683 || opP->mode == FPREG
1684 || opP->mode == DREG
1685 || opP->mode == AREG
1686 || opP->mode == REGLST)
1687 losing++;
1688 /* We should accept immediate operands, but they
1689 supposedly have to be quad word, and we don't
1690 handle that. I would like to see what a Motorola
1691 assembler does before doing something here. */
1692 if (opP->mode == IMMED)
1693 losing++;
1694 break;
1695
1696 case 'f':
1697 if (opP->mode != CONTROL
1698 || (opP->reg != SFC && opP->reg != DFC))
1699 losing++;
1700 break;
1701
1702 case '0':
1703 if (opP->mode != CONTROL || opP->reg != TC)
1704 losing++;
1705 break;
1706
1707 case '1':
1708 if (opP->mode != CONTROL || opP->reg != AC)
1709 losing++;
1710 break;
1711
1712 case '2':
1713 if (opP->mode != CONTROL
1714 || (opP->reg != CAL
1715 && opP->reg != VAL
1716 && opP->reg != SCC))
1717 losing++;
1718 break;
1719
1720 case 'V':
1721 if (opP->mode != CONTROL
1722 || opP->reg != VAL)
1723 losing++;
1724 break;
1725
1726 case 'W':
1727 if (opP->mode != CONTROL
1728 || (opP->reg != DRP
1729 && opP->reg != SRP
1730 && opP->reg != CRP))
1731 losing++;
1732 break;
1733
1734 case 'X':
1735 if (opP->mode != CONTROL
1736 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1737 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1738 losing++;
1739 break;
1740
1741 case 'Y':
1742 if (opP->mode != CONTROL || opP->reg != PSR)
1743 losing++;
1744 break;
1745
1746 case 'Z':
1747 if (opP->mode != CONTROL || opP->reg != PCSR)
1748 losing++;
1749 break;
1750 #endif
1751 case 'c':
1752 if (opP->mode != CONTROL
1753 || (opP->reg != NC
1754 && opP->reg != IC
1755 && opP->reg != DC
1756 && opP->reg != BC))
1757 {
1758 losing++;
1759 } /* not a cache specifier. */
1760 break;
1761
1762 case '_':
1763 if (opP->mode != ABSL)
1764 ++losing;
1765 break;
1766
1767 case 'u':
1768 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1769 losing++;
1770 /* FIXME: kludge instead of fixing parser:
1771 upper/lower registers are *not* CONTROL
1772 registers, but ordinary ones. */
1773 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1774 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1775 opP->mode = DREG;
1776 else
1777 opP->mode = AREG;
1778 break;
1779
1780 default:
1781 abort ();
1782 } /* switch on type of operand */
1783
1784 if (losing)
1785 break;
1786 } /* for each operand */
1787 } /* if immediately wrong */
1788
1789 if (!losing)
1790 {
1791 break;
1792 } /* got it. */
1793
1794 opcode = opcode->m_next;
1795
1796 if (!opcode)
1797 {
1798 if (ok_arch
1799 && !(ok_arch & current_architecture))
1800 {
1801 char buf[200], *cp;
1802
1803 strcpy (buf,
1804 _("invalid instruction for this architecture; needs "));
1805 cp = buf + strlen (buf);
1806 switch (ok_arch)
1807 {
1808 case mfloat:
1809 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1810 break;
1811 case mmmu:
1812 strcpy (cp, _("mmu (68030 or 68851)"));
1813 break;
1814 case m68020up:
1815 strcpy (cp, _("68020 or higher"));
1816 break;
1817 case m68000up:
1818 strcpy (cp, _("68000 or higher"));
1819 break;
1820 case m68010up:
1821 strcpy (cp, _("68010 or higher"));
1822 break;
1823 default:
1824 {
1825 int got_one = 0, idx;
1826 for (idx = 0;
1827 idx < (int) (sizeof (archs) / sizeof (archs[0]));
1828 idx++)
1829 {
1830 if ((archs[idx].arch & ok_arch)
1831 && ! archs[idx].alias)
1832 {
1833 if (got_one)
1834 {
1835 strcpy (cp, " or ");
1836 cp += strlen (cp);
1837 }
1838 got_one = 1;
1839 strcpy (cp, archs[idx].name);
1840 cp += strlen (cp);
1841 }
1842 }
1843 }
1844 }
1845 cp = xmalloc (strlen (buf) + 1);
1846 strcpy (cp, buf);
1847 the_ins.error = cp;
1848 }
1849 else
1850 the_ins.error = _("operands mismatch");
1851 return;
1852 } /* Fell off the end */
1853
1854 losing = 0;
1855 }
1856
1857 /* now assemble it */
1858
1859 the_ins.args = opcode->m_operands;
1860 the_ins.numargs = opcode->m_opnum;
1861 the_ins.numo = opcode->m_codenum;
1862 the_ins.opcode[0] = getone (opcode);
1863 the_ins.opcode[1] = gettwo (opcode);
1864
1865 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1866 {
1867 /* This switch is a doozy.
1868 Watch the first step; its a big one! */
1869 switch (s[0])
1870 {
1871
1872 case '*':
1873 case '~':
1874 case '%':
1875 case ';':
1876 case '@':
1877 case '!':
1878 case '&':
1879 case '$':
1880 case '?':
1881 case '/':
1882 case '<':
1883 case '>':
1884 case 'm':
1885 case 'n':
1886 case 'o':
1887 case 'p':
1888 case 'q':
1889 case 'v':
1890 #ifndef NO_68851
1891 case '|':
1892 #endif
1893 switch (opP->mode)
1894 {
1895 case IMMED:
1896 tmpreg = 0x3c; /* 7.4 */
1897 if (strchr ("bwl", s[1]))
1898 nextword = get_num (&opP->disp, 80);
1899 else
1900 nextword = get_num (&opP->disp, 0);
1901 if (isvar (&opP->disp))
1902 add_fix (s[1], &opP->disp, 0, 0);
1903 switch (s[1])
1904 {
1905 case 'b':
1906 if (!isbyte (nextword))
1907 opP->error = _("operand out of range");
1908 addword (nextword);
1909 baseo = 0;
1910 break;
1911 case 'w':
1912 if (!isword (nextword))
1913 opP->error = _("operand out of range");
1914 addword (nextword);
1915 baseo = 0;
1916 break;
1917 case 'W':
1918 if (!issword (nextword))
1919 opP->error = _("operand out of range");
1920 addword (nextword);
1921 baseo = 0;
1922 break;
1923 case 'l':
1924 addword (nextword >> 16);
1925 addword (nextword);
1926 baseo = 0;
1927 break;
1928
1929 case 'f':
1930 baseo = 2;
1931 outro = 8;
1932 break;
1933 case 'F':
1934 baseo = 4;
1935 outro = 11;
1936 break;
1937 case 'x':
1938 baseo = 6;
1939 outro = 15;
1940 break;
1941 case 'p':
1942 baseo = 6;
1943 outro = -1;
1944 break;
1945 default:
1946 abort ();
1947 }
1948 if (!baseo)
1949 break;
1950
1951 /* We gotta put out some float */
1952 if (op (&opP->disp) != O_big)
1953 {
1954 valueT val;
1955 int gencnt;
1956
1957 /* Can other cases happen here? */
1958 if (op (&opP->disp) != O_constant)
1959 abort ();
1960
1961 val = (valueT) offs (&opP->disp);
1962 gencnt = 0;
1963 do
1964 {
1965 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1966 val >>= LITTLENUM_NUMBER_OF_BITS;
1967 ++gencnt;
1968 }
1969 while (val != 0);
1970 offs (&opP->disp) = gencnt;
1971 }
1972 if (offs (&opP->disp) > 0)
1973 {
1974 if (offs (&opP->disp) > baseo)
1975 {
1976 as_warn (_("Bignum too big for %c format; truncated"),
1977 s[1]);
1978 offs (&opP->disp) = baseo;
1979 }
1980 baseo -= offs (&opP->disp);
1981 while (baseo--)
1982 addword (0);
1983 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1984 offs (&opP->disp)--;
1985 --wordp)
1986 addword (*wordp);
1987 break;
1988 }
1989 gen_to_words (words, baseo, (long) outro);
1990 for (wordp = words; baseo--; wordp++)
1991 addword (*wordp);
1992 break;
1993 case DREG:
1994 tmpreg = opP->reg - DATA; /* 0.dreg */
1995 break;
1996 case AREG:
1997 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1998 break;
1999 case AINDR:
2000 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2001 break;
2002 case ADEC:
2003 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2004 break;
2005 case AINC:
2006 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2007 break;
2008 case DISP:
2009
2010 nextword = get_num (&opP->disp, 80);
2011
2012 if (opP->reg == PC
2013 && ! isvar (&opP->disp)
2014 && m68k_abspcadd)
2015 {
2016 opP->disp.exp.X_op = O_symbol;
2017 #ifndef BFD_ASSEMBLER
2018 opP->disp.exp.X_add_symbol = &abs_symbol;
2019 #else
2020 opP->disp.exp.X_add_symbol =
2021 section_symbol (absolute_section);
2022 #endif
2023 }
2024
2025 /* Force into index mode. Hope this works */
2026
2027 /* We do the first bit for 32-bit displacements, and the
2028 second bit for 16 bit ones. It is possible that we
2029 should make the default be WORD instead of LONG, but
2030 I think that'd break GCC, so we put up with a little
2031 inefficiency for the sake of working output. */
2032
2033 if (!issword (nextword)
2034 || (isvar (&opP->disp)
2035 && ((opP->disp.size == SIZE_UNSPEC
2036 && flag_short_refs == 0
2037 && cpu_of_arch (current_architecture) >= m68020
2038 && ! arch_coldfire_p (current_architecture))
2039 || opP->disp.size == SIZE_LONG)))
2040 {
2041 if (cpu_of_arch (current_architecture) < m68020
2042 || arch_coldfire_p (current_architecture))
2043 opP->error =
2044 _("displacement too large for this architecture; needs 68020 or higher");
2045 if (opP->reg == PC)
2046 tmpreg = 0x3B; /* 7.3 */
2047 else
2048 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2049 if (isvar (&opP->disp))
2050 {
2051 if (opP->reg == PC)
2052 {
2053 if (opP->disp.size == SIZE_LONG
2054 #ifdef OBJ_ELF
2055 /* If the displacement needs pic
2056 relocation it cannot be relaxed. */
2057 || opP->disp.pic_reloc != pic_none
2058 #endif
2059 )
2060 {
2061 addword (0x0170);
2062 add_fix ('l', &opP->disp, 1, 2);
2063 }
2064 else
2065 {
2066 add_frag (adds (&opP->disp),
2067 offs (&opP->disp),
2068 TAB (PCLEA, SZ_UNDEF));
2069 break;
2070 }
2071 }
2072 else
2073 {
2074 addword (0x0170);
2075 add_fix ('l', &opP->disp, 0, 0);
2076 }
2077 }
2078 else
2079 addword (0x0170);
2080 addword (nextword >> 16);
2081 }
2082 else
2083 {
2084 if (opP->reg == PC)
2085 tmpreg = 0x3A; /* 7.2 */
2086 else
2087 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2088
2089 if (isvar (&opP->disp))
2090 {
2091 if (opP->reg == PC)
2092 {
2093 add_fix ('w', &opP->disp, 1, 0);
2094 }
2095 else
2096 add_fix ('w', &opP->disp, 0, 0);
2097 }
2098 }
2099 addword (nextword);
2100 break;
2101
2102 case POST:
2103 case PRE:
2104 case BASE:
2105 nextword = 0;
2106 baseo = get_num (&opP->disp, 80);
2107 if (opP->mode == POST || opP->mode == PRE)
2108 outro = get_num (&opP->odisp, 80);
2109 /* Figure out the `addressing mode'.
2110 Also turn on the BASE_DISABLE bit, if needed. */
2111 if (opP->reg == PC || opP->reg == ZPC)
2112 {
2113 tmpreg = 0x3b; /* 7.3 */
2114 if (opP->reg == ZPC)
2115 nextword |= 0x80;
2116 }
2117 else if (opP->reg == 0)
2118 {
2119 nextword |= 0x80;
2120 tmpreg = 0x30; /* 6.garbage */
2121 }
2122 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2123 {
2124 nextword |= 0x80;
2125 tmpreg = 0x30 + opP->reg - ZADDR0;
2126 }
2127 else
2128 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2129
2130 siz1 = opP->disp.size;
2131 if (opP->mode == POST || opP->mode == PRE)
2132 siz2 = opP->odisp.size;
2133 else
2134 siz2 = SIZE_UNSPEC;
2135
2136 /* Index register stuff */
2137 if (opP->index.reg != 0
2138 && opP->index.reg >= DATA
2139 && opP->index.reg <= ADDR7)
2140 {
2141 nextword |= (opP->index.reg - DATA) << 12;
2142
2143 if (opP->index.size == SIZE_LONG
2144 || (opP->index.size == SIZE_UNSPEC
2145 && m68k_index_width_default == SIZE_LONG))
2146 nextword |= 0x800;
2147
2148 if ((opP->index.scale != 1
2149 && cpu_of_arch (current_architecture) < m68020)
2150 || (opP->index.scale == 8
2151 && arch_coldfire_p (current_architecture)))
2152 {
2153 opP->error =
2154 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2155 }
2156
2157 if (arch_coldfire_p (current_architecture)
2158 && opP->index.size == SIZE_WORD)
2159 opP->error = _("invalid index size for coldfire");
2160
2161 switch (opP->index.scale)
2162 {
2163 case 1:
2164 break;
2165 case 2:
2166 nextword |= 0x200;
2167 break;
2168 case 4:
2169 nextword |= 0x400;
2170 break;
2171 case 8:
2172 nextword |= 0x600;
2173 break;
2174 default:
2175 abort ();
2176 }
2177 /* IF its simple,
2178 GET US OUT OF HERE! */
2179
2180 /* Must be INDEX, with an index register. Address
2181 register cannot be ZERO-PC, and either :b was
2182 forced, or we know it will fit. For a 68000 or
2183 68010, force this mode anyways, because the
2184 larger modes aren't supported. */
2185 if (opP->mode == BASE
2186 && ((opP->reg >= ADDR0
2187 && opP->reg <= ADDR7)
2188 || opP->reg == PC))
2189 {
2190 if (siz1 == SIZE_BYTE
2191 || cpu_of_arch (current_architecture) < m68020
2192 || arch_coldfire_p (current_architecture)
2193 || (siz1 == SIZE_UNSPEC
2194 && ! isvar (&opP->disp)
2195 && issbyte (baseo)))
2196 {
2197 nextword += baseo & 0xff;
2198 addword (nextword);
2199 if (isvar (&opP->disp))
2200 {
2201 /* Do a byte relocation. If it doesn't
2202 fit (possible on m68000) let the
2203 fixup processing complain later. */
2204 if (opP->reg == PC)
2205 add_fix ('B', &opP->disp, 1, 1);
2206 else
2207 add_fix ('B', &opP->disp, 0, 0);
2208 }
2209 else if (siz1 != SIZE_BYTE)
2210 {
2211 if (siz1 != SIZE_UNSPEC)
2212 as_warn (_("Forcing byte displacement"));
2213 if (! issbyte (baseo))
2214 opP->error = _("byte displacement out of range");
2215 }
2216
2217 break;
2218 }
2219 else if (siz1 == SIZE_UNSPEC
2220 && opP->reg == PC
2221 && isvar (&opP->disp)
2222 && subs (&opP->disp) == NULL
2223 #ifdef OBJ_ELF
2224 /* If the displacement needs pic
2225 relocation it cannot be relaxed. */
2226 && opP->disp.pic_reloc == pic_none
2227 #endif
2228 )
2229 {
2230 /* The code in md_convert_frag_1 needs to be
2231 able to adjust nextword. Call frag_grow
2232 to ensure that we have enough space in
2233 the frag obstack to make all the bytes
2234 contiguous. */
2235 frag_grow (14);
2236 nextword += baseo & 0xff;
2237 addword (nextword);
2238 add_frag (adds (&opP->disp), offs (&opP->disp),
2239 TAB (PCINDEX, SZ_UNDEF));
2240
2241 break;
2242 }
2243 }
2244 }
2245 else
2246 {
2247 nextword |= 0x40; /* No index reg */
2248 if (opP->index.reg >= ZDATA0
2249 && opP->index.reg <= ZDATA7)
2250 nextword |= (opP->index.reg - ZDATA0) << 12;
2251 else if (opP->index.reg >= ZADDR0
2252 || opP->index.reg <= ZADDR7)
2253 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2254 }
2255
2256 /* It isn't simple. */
2257
2258 if (cpu_of_arch (current_architecture) < m68020
2259 || arch_coldfire_p (current_architecture))
2260 opP->error =
2261 _("invalid operand mode for this architecture; needs 68020 or higher");
2262
2263 nextword |= 0x100;
2264 /* If the guy specified a width, we assume that it is
2265 wide enough. Maybe it isn't. If so, we lose. */
2266 switch (siz1)
2267 {
2268 case SIZE_UNSPEC:
2269 if (isvar (&opP->disp)
2270 ? m68k_rel32
2271 : ! issword (baseo))
2272 {
2273 siz1 = SIZE_LONG;
2274 nextword |= 0x30;
2275 }
2276 else if (! isvar (&opP->disp) && baseo == 0)
2277 nextword |= 0x10;
2278 else
2279 {
2280 nextword |= 0x20;
2281 siz1 = SIZE_WORD;
2282 }
2283 break;
2284 case SIZE_BYTE:
2285 as_warn (_(":b not permitted; defaulting to :w"));
2286 /* Fall through. */
2287 case SIZE_WORD:
2288 nextword |= 0x20;
2289 break;
2290 case SIZE_LONG:
2291 nextword |= 0x30;
2292 break;
2293 }
2294
2295 /* Figure out innner displacement stuff */
2296 if (opP->mode == POST || opP->mode == PRE)
2297 {
2298 if (cpu_of_arch (current_architecture) & cpu32)
2299 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2300 switch (siz2)
2301 {
2302 case SIZE_UNSPEC:
2303 if (isvar (&opP->odisp)
2304 ? m68k_rel32
2305 : ! issword (outro))
2306 {
2307 siz2 = SIZE_LONG;
2308 nextword |= 0x3;
2309 }
2310 else if (! isvar (&opP->odisp) && outro == 0)
2311 nextword |= 0x1;
2312 else
2313 {
2314 nextword |= 0x2;
2315 siz2 = SIZE_WORD;
2316 }
2317 break;
2318 case 1:
2319 as_warn (_(":b not permitted; defaulting to :w"));
2320 /* Fall through. */
2321 case 2:
2322 nextword |= 0x2;
2323 break;
2324 case 3:
2325 nextword |= 0x3;
2326 break;
2327 }
2328 if (opP->mode == POST
2329 && (nextword & 0x40) == 0)
2330 nextword |= 0x04;
2331 }
2332 addword (nextword);
2333
2334 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2335 {
2336 if (opP->reg == PC || opP->reg == ZPC)
2337 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2338 else
2339 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2340 }
2341 if (siz1 == SIZE_LONG)
2342 addword (baseo >> 16);
2343 if (siz1 != SIZE_UNSPEC)
2344 addword (baseo);
2345
2346 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2347 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2348 if (siz2 == SIZE_LONG)
2349 addword (outro >> 16);
2350 if (siz2 != SIZE_UNSPEC)
2351 addword (outro);
2352
2353 break;
2354
2355 case ABSL:
2356 nextword = get_num (&opP->disp, 80);
2357 switch (opP->disp.size)
2358 {
2359 default:
2360 abort ();
2361 case SIZE_UNSPEC:
2362 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2363 {
2364 tmpreg = 0x38; /* 7.0 */
2365 addword (nextword);
2366 break;
2367 }
2368 if (isvar (&opP->disp)
2369 && !subs (&opP->disp)
2370 && adds (&opP->disp)
2371 #ifdef OBJ_ELF
2372 /* If the displacement needs pic relocation it
2373 cannot be relaxed. */
2374 && opP->disp.pic_reloc == pic_none
2375 #endif
2376 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2377 && relaxable_symbol (adds (&opP->disp))
2378 && !flag_long_jumps
2379 && !strchr ("~%&$?", s[0]))
2380 {
2381 tmpreg = 0x3A; /* 7.2 */
2382 add_frag (adds (&opP->disp),
2383 offs (&opP->disp),
2384 TAB (PCREL, SZ_UNDEF));
2385 break;
2386 }
2387 /* Fall through into long */
2388 case SIZE_LONG:
2389 if (isvar (&opP->disp))
2390 add_fix ('l', &opP->disp, 0, 0);
2391
2392 tmpreg = 0x39;/* 7.1 mode */
2393 addword (nextword >> 16);
2394 addword (nextword);
2395 break;
2396
2397 case SIZE_BYTE:
2398 as_bad (_("unsupported byte value; use a different suffix"));
2399 /* Fall through. */
2400 case SIZE_WORD: /* Word */
2401 if (isvar (&opP->disp))
2402 add_fix ('w', &opP->disp, 0, 0);
2403
2404 tmpreg = 0x38;/* 7.0 mode */
2405 addword (nextword);
2406 break;
2407 }
2408 break;
2409 case CONTROL:
2410 case FPREG:
2411 default:
2412 as_bad (_("unknown/incorrect operand"));
2413 /* abort(); */
2414 }
2415 install_gen_operand (s[1], tmpreg);
2416 break;
2417
2418 case '#':
2419 case '^':
2420 switch (s[1])
2421 { /* JF: I hate floating point! */
2422 case 'j':
2423 tmpreg = 70;
2424 break;
2425 case '8':
2426 tmpreg = 20;
2427 break;
2428 case 'C':
2429 tmpreg = 50;
2430 break;
2431 case '3':
2432 default:
2433 tmpreg = 80;
2434 break;
2435 }
2436 tmpreg = get_num (&opP->disp, tmpreg);
2437 if (isvar (&opP->disp))
2438 add_fix (s[1], &opP->disp, 0, 0);
2439 switch (s[1])
2440 {
2441 case 'b': /* Danger: These do no check for
2442 certain types of overflow.
2443 user beware! */
2444 if (!isbyte (tmpreg))
2445 opP->error = _("out of range");
2446 insop (tmpreg, opcode);
2447 if (isvar (&opP->disp))
2448 the_ins.reloc[the_ins.nrel - 1].n =
2449 (opcode->m_codenum) * 2 + 1;
2450 break;
2451 case 'B':
2452 if (!issbyte (tmpreg))
2453 opP->error = _("out of range");
2454 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2455 if (isvar (&opP->disp))
2456 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2457 break;
2458 case 'w':
2459 if (!isword (tmpreg))
2460 opP->error = _("out of range");
2461 insop (tmpreg, opcode);
2462 if (isvar (&opP->disp))
2463 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2464 break;
2465 case 'W':
2466 if (!issword (tmpreg))
2467 opP->error = _("out of range");
2468 insop (tmpreg, opcode);
2469 if (isvar (&opP->disp))
2470 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2471 break;
2472 case 'l':
2473 /* Because of the way insop works, we put these two out
2474 backwards. */
2475 insop (tmpreg, opcode);
2476 insop (tmpreg >> 16, opcode);
2477 if (isvar (&opP->disp))
2478 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2479 break;
2480 case '3':
2481 tmpreg &= 0xFF;
2482 case '8':
2483 case 'C':
2484 case 'j':
2485 install_operand (s[1], tmpreg);
2486 break;
2487 default:
2488 abort ();
2489 }
2490 break;
2491
2492 case '+':
2493 case '-':
2494 case 'A':
2495 case 'a':
2496 install_operand (s[1], opP->reg - ADDR);
2497 break;
2498
2499 case 'B':
2500 tmpreg = get_num (&opP->disp, 80);
2501 switch (s[1])
2502 {
2503 case 'B':
2504 /* The pc_fix argument winds up in fx_pcrel_adjust,
2505 which is a char, and may therefore be unsigned. We
2506 want to pass -1, but we pass 64 instead, and convert
2507 back in md_pcrel_from. */
2508 add_fix ('B', &opP->disp, 1, 64);
2509 break;
2510 case 'W':
2511 add_fix ('w', &opP->disp, 1, 0);
2512 addword (0);
2513 break;
2514 case 'L':
2515 long_branch:
2516 if (!HAVE_LONG_BRANCH(current_architecture))
2517 as_warn (_("Can't use long branches on 68000/68010/5200"));
2518 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2519 add_fix ('l', &opP->disp, 1, 0);
2520 addword (0);
2521 addword (0);
2522 break;
2523 case 'g':
2524 if (subs (&opP->disp)) /* We can't relax it */
2525 goto long_branch;
2526
2527 #ifdef OBJ_ELF
2528 /* If the displacement needs pic relocation it cannot be
2529 relaxed. */
2530 if (opP->disp.pic_reloc != pic_none)
2531 goto long_branch;
2532 #endif
2533
2534 /* This could either be a symbol, or an absolute
2535 address. No matter, the frag hacking will finger it
2536 out. Not quite: it can't switch from BRANCH to
2537 BCC68000 for the case where opnd is absolute (it
2538 needs to use the 68000 hack since no conditional abs
2539 jumps). */
2540 if (( !HAVE_LONG_BRANCH(current_architecture)
2541 || (0 == adds (&opP->disp)))
2542 && (the_ins.opcode[0] >= 0x6200)
2543 && (the_ins.opcode[0] <= 0x6f00))
2544 add_frag (adds (&opP->disp), offs (&opP->disp),
2545 TAB (BCC68000, SZ_UNDEF));
2546 else
2547 add_frag (adds (&opP->disp), offs (&opP->disp),
2548 TAB (ABRANCH, SZ_UNDEF));
2549 break;
2550 case 'w':
2551 if (isvar (&opP->disp))
2552 {
2553 #if 1
2554 /* check for DBcc instruction */
2555 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2556 {
2557 /* size varies if patch */
2558 /* needed for long form */
2559 add_frag (adds (&opP->disp), offs (&opP->disp),
2560 TAB (DBCC, SZ_UNDEF));
2561 break;
2562 }
2563 #endif
2564 add_fix ('w', &opP->disp, 1, 0);
2565 }
2566 addword (0);
2567 break;
2568 case 'C': /* Fixed size LONG coproc branches */
2569 add_fix ('l', &opP->disp, 1, 0);
2570 addword (0);
2571 addword (0);
2572 break;
2573 case 'c': /* Var size Coprocesssor branches */
2574 if (subs (&opP->disp))
2575 {
2576 add_fix ('l', &opP->disp, 1, 0);
2577 add_frag ((symbolS *) 0, (offsetT) 0, TAB (FBRANCH, LONG));
2578 }
2579 else if (adds (&opP->disp))
2580 add_frag (adds (&opP->disp), offs (&opP->disp),
2581 TAB (FBRANCH, SZ_UNDEF));
2582 else
2583 {
2584 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2585 TAB(FBRANCH,SHORT)); */
2586 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2587 add_fix ('l', &opP->disp, 1, 0);
2588 addword (0);
2589 addword (0);
2590 }
2591 break;
2592 default:
2593 abort ();
2594 }
2595 break;
2596
2597 case 'C': /* Ignore it */
2598 break;
2599
2600 case 'd': /* JF this is a kludge */
2601 install_operand ('s', opP->reg - ADDR);
2602 tmpreg = get_num (&opP->disp, 80);
2603 if (!issword (tmpreg))
2604 {
2605 as_warn (_("Expression out of range, using 0"));
2606 tmpreg = 0;
2607 }
2608 addword (tmpreg);
2609 break;
2610
2611 case 'D':
2612 install_operand (s[1], opP->reg - DATA);
2613 break;
2614
2615 case 'E': /* Ignore it */
2616 break;
2617
2618 case 'F':
2619 install_operand (s[1], opP->reg - FP0);
2620 break;
2621
2622 case 'G': /* Ignore it */
2623 case 'H':
2624 break;
2625
2626 case 'I':
2627 tmpreg = opP->reg - COP0;
2628 install_operand (s[1], tmpreg);
2629 break;
2630
2631 case 'J': /* JF foo */
2632 switch (opP->reg)
2633 {
2634 case SFC:
2635 tmpreg = 0x000;
2636 break;
2637 case DFC:
2638 tmpreg = 0x001;
2639 break;
2640 case CACR:
2641 tmpreg = 0x002;
2642 break;
2643 case TC:
2644 tmpreg = 0x003;
2645 break;
2646 case ITT0:
2647 tmpreg = 0x004;
2648 break;
2649 case ITT1:
2650 tmpreg = 0x005;
2651 break;
2652 case DTT0:
2653 tmpreg = 0x006;
2654 break;
2655 case DTT1:
2656 tmpreg = 0x007;
2657 break;
2658 case BUSCR:
2659 tmpreg = 0x008;
2660 break;
2661
2662 case USP:
2663 tmpreg = 0x800;
2664 break;
2665 case VBR:
2666 tmpreg = 0x801;
2667 break;
2668 case CAAR:
2669 tmpreg = 0x802;
2670 break;
2671 case MSP:
2672 tmpreg = 0x803;
2673 break;
2674 case ISP:
2675 tmpreg = 0x804;
2676 break;
2677 case MMUSR:
2678 tmpreg = 0x805;
2679 break;
2680 case URP:
2681 tmpreg = 0x806;
2682 break;
2683 case SRP:
2684 tmpreg = 0x807;
2685 break;
2686 case PCR:
2687 tmpreg = 0x808;
2688 break;
2689 case ROMBAR:
2690 tmpreg = 0xC00;
2691 break;
2692 case RAMBAR0:
2693 tmpreg = 0xC04;
2694 break;
2695 case RAMBAR1:
2696 tmpreg = 0xC05;
2697 break;
2698 case MBAR:
2699 tmpreg = 0xC0F;
2700 break;
2701 default:
2702 abort ();
2703 }
2704 install_operand (s[1], tmpreg);
2705 break;
2706
2707 case 'k':
2708 tmpreg = get_num (&opP->disp, 55);
2709 install_operand (s[1], tmpreg & 0x7f);
2710 break;
2711
2712 case 'l':
2713 tmpreg = opP->mask;
2714 if (s[1] == 'w')
2715 {
2716 if (tmpreg & 0x7FF0000)
2717 as_bad (_("Floating point register in register list"));
2718 insop (reverse_16_bits (tmpreg), opcode);
2719 }
2720 else
2721 {
2722 if (tmpreg & 0x700FFFF)
2723 as_bad (_("Wrong register in floating-point reglist"));
2724 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2725 }
2726 break;
2727
2728 case 'L':
2729 tmpreg = opP->mask;
2730 if (s[1] == 'w')
2731 {
2732 if (tmpreg & 0x7FF0000)
2733 as_bad (_("Floating point register in register list"));
2734 insop (tmpreg, opcode);
2735 }
2736 else if (s[1] == '8')
2737 {
2738 if (tmpreg & 0x0FFFFFF)
2739 as_bad (_("incorrect register in reglist"));
2740 install_operand (s[1], tmpreg >> 24);
2741 }
2742 else
2743 {
2744 if (tmpreg & 0x700FFFF)
2745 as_bad (_("wrong register in floating-point reglist"));
2746 else
2747 install_operand (s[1], tmpreg >> 16);
2748 }
2749 break;
2750
2751 case 'M':
2752 install_operand (s[1], get_num (&opP->disp, 60));
2753 break;
2754
2755 case 'O':
2756 tmpreg = ((opP->mode == DREG)
2757 ? 0x20 + (int) (opP->reg - DATA)
2758 : (get_num (&opP->disp, 40) & 0x1F));
2759 install_operand (s[1], tmpreg);
2760 break;
2761
2762 case 'Q':
2763 tmpreg = get_num (&opP->disp, 10);
2764 if (tmpreg == 8)
2765 tmpreg = 0;
2766 install_operand (s[1], tmpreg);
2767 break;
2768
2769 case 'R':
2770 /* This depends on the fact that ADDR registers are eight
2771 more than their corresponding DATA regs, so the result
2772 will have the ADDR_REG bit set */
2773 install_operand (s[1], opP->reg - DATA);
2774 break;
2775
2776 case 'r':
2777 if (opP->mode == AINDR)
2778 install_operand (s[1], opP->reg - DATA);
2779 else
2780 install_operand (s[1], opP->index.reg - DATA);
2781 break;
2782
2783 case 's':
2784 if (opP->reg == FPI)
2785 tmpreg = 0x1;
2786 else if (opP->reg == FPS)
2787 tmpreg = 0x2;
2788 else if (opP->reg == FPC)
2789 tmpreg = 0x4;
2790 else
2791 abort ();
2792 install_operand (s[1], tmpreg);
2793 break;
2794
2795 case 'S': /* Ignore it */
2796 break;
2797
2798 case 'T':
2799 install_operand (s[1], get_num (&opP->disp, 30));
2800 break;
2801
2802 case 'U': /* Ignore it */
2803 break;
2804
2805 case 'c':
2806 switch (opP->reg)
2807 {
2808 case NC:
2809 tmpreg = 0;
2810 break;
2811 case DC:
2812 tmpreg = 1;
2813 break;
2814 case IC:
2815 tmpreg = 2;
2816 break;
2817 case BC:
2818 tmpreg = 3;
2819 break;
2820 default:
2821 as_fatal (_("failed sanity check"));
2822 } /* switch on cache token */
2823 install_operand (s[1], tmpreg);
2824 break;
2825 #ifndef NO_68851
2826 /* JF: These are out of order, I fear. */
2827 case 'f':
2828 switch (opP->reg)
2829 {
2830 case SFC:
2831 tmpreg = 0;
2832 break;
2833 case DFC:
2834 tmpreg = 1;
2835 break;
2836 default:
2837 abort ();
2838 }
2839 install_operand (s[1], tmpreg);
2840 break;
2841
2842 case '0':
2843 case '1':
2844 case '2':
2845 switch (opP->reg)
2846 {
2847 case TC:
2848 tmpreg = 0;
2849 break;
2850 case CAL:
2851 tmpreg = 4;
2852 break;
2853 case VAL:
2854 tmpreg = 5;
2855 break;
2856 case SCC:
2857 tmpreg = 6;
2858 break;
2859 case AC:
2860 tmpreg = 7;
2861 break;
2862 default:
2863 abort ();
2864 }
2865 install_operand (s[1], tmpreg);
2866 break;
2867
2868 case 'V':
2869 if (opP->reg == VAL)
2870 break;
2871 abort ();
2872
2873 case 'W':
2874 switch (opP->reg)
2875 {
2876 case DRP:
2877 tmpreg = 1;
2878 break;
2879 case SRP:
2880 tmpreg = 2;
2881 break;
2882 case CRP:
2883 tmpreg = 3;
2884 break;
2885 default:
2886 abort ();
2887 }
2888 install_operand (s[1], tmpreg);
2889 break;
2890
2891 case 'X':
2892 switch (opP->reg)
2893 {
2894 case BAD:
2895 case BAD + 1:
2896 case BAD + 2:
2897 case BAD + 3:
2898 case BAD + 4:
2899 case BAD + 5:
2900 case BAD + 6:
2901 case BAD + 7:
2902 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2903 break;
2904
2905 case BAC:
2906 case BAC + 1:
2907 case BAC + 2:
2908 case BAC + 3:
2909 case BAC + 4:
2910 case BAC + 5:
2911 case BAC + 6:
2912 case BAC + 7:
2913 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2914 break;
2915
2916 default:
2917 abort ();
2918 }
2919 install_operand (s[1], tmpreg);
2920 break;
2921 case 'Y':
2922 know (opP->reg == PSR);
2923 break;
2924 case 'Z':
2925 know (opP->reg == PCSR);
2926 break;
2927 #endif /* m68851 */
2928 case '3':
2929 switch (opP->reg)
2930 {
2931 case TT0:
2932 tmpreg = 2;
2933 break;
2934 case TT1:
2935 tmpreg = 3;
2936 break;
2937 default:
2938 abort ();
2939 }
2940 install_operand (s[1], tmpreg);
2941 break;
2942 case 't':
2943 tmpreg = get_num (&opP->disp, 20);
2944 install_operand (s[1], tmpreg);
2945 break;
2946 case '_': /* used only for move16 absolute 32-bit address */
2947 if (isvar (&opP->disp))
2948 add_fix ('l', &opP->disp, 0, 0);
2949 tmpreg = get_num (&opP->disp, 80);
2950 addword (tmpreg >> 16);
2951 addword (tmpreg & 0xFFFF);
2952 break;
2953 case 'u':
2954 install_operand (s[1], opP->reg - DATA0L);
2955 opP->reg -= (DATA0L);
2956 opP->reg &= 0x0F; /* remove upper/lower bit */
2957 break;
2958 default:
2959 abort ();
2960 }
2961 }
2962
2963 /* By the time whe get here (FINALLY) the_ins contains the complete
2964 instruction, ready to be emitted. . . */
2965 }
2966
2967 static int
2968 reverse_16_bits (in)
2969 int in;
2970 {
2971 int out = 0;
2972 int n;
2973
2974 static int mask[16] =
2975 {
2976 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2977 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2978 };
2979 for (n = 0; n < 16; n++)
2980 {
2981 if (in & mask[n])
2982 out |= mask[15 - n];
2983 }
2984 return out;
2985 } /* reverse_16_bits() */
2986
2987 static int
2988 reverse_8_bits (in)
2989 int in;
2990 {
2991 int out = 0;
2992 int n;
2993
2994 static int mask[8] =
2995 {
2996 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2997 };
2998
2999 for (n = 0; n < 8; n++)
3000 {
3001 if (in & mask[n])
3002 out |= mask[7 - n];
3003 }
3004 return out;
3005 } /* reverse_8_bits() */
3006
3007 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3008 (that value is chosen in the frag_var call in md_assemble). TYPE
3009 is the subtype of the frag to be generated; its primary type is
3010 rs_machine_dependent.
3011
3012 The TYPE parameter is also used by md_convert_frag_1 and
3013 md_estimate_size_before_relax. The appropriate type of fixup will
3014 be emitted by md_convert_frag_1.
3015
3016 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3017 static void
3018 install_operand (mode, val)
3019 int mode;
3020 int val;
3021 {
3022 switch (mode)
3023 {
3024 case 's':
3025 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3026 break;
3027 case 'd':
3028 the_ins.opcode[0] |= val << 9;
3029 break;
3030 case '1':
3031 the_ins.opcode[1] |= val << 12;
3032 break;
3033 case '2':
3034 the_ins.opcode[1] |= val << 6;
3035 break;
3036 case '3':
3037 the_ins.opcode[1] |= val;
3038 break;
3039 case '4':
3040 the_ins.opcode[2] |= val << 12;
3041 break;
3042 case '5':
3043 the_ins.opcode[2] |= val << 6;
3044 break;
3045 case '6':
3046 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3047 three words long! */
3048 the_ins.numo++;
3049 the_ins.opcode[2] |= val;
3050 break;
3051 case '7':
3052 the_ins.opcode[1] |= val << 7;
3053 break;
3054 case '8':
3055 the_ins.opcode[1] |= val << 10;
3056 break;
3057 #ifndef NO_68851
3058 case '9':
3059 the_ins.opcode[1] |= val << 5;
3060 break;
3061 #endif
3062
3063 case 't':
3064 the_ins.opcode[1] |= (val << 10) | (val << 7);
3065 break;
3066 case 'D':
3067 the_ins.opcode[1] |= (val << 12) | val;
3068 break;
3069 case 'g':
3070 the_ins.opcode[0] |= val = 0xff;
3071 break;
3072 case 'i':
3073 the_ins.opcode[0] |= val << 9;
3074 break;
3075 case 'C':
3076 the_ins.opcode[1] |= val;
3077 break;
3078 case 'j':
3079 the_ins.opcode[1] |= val;
3080 the_ins.numo++; /* What a hack */
3081 break;
3082 case 'k':
3083 the_ins.opcode[1] |= val << 4;
3084 break;
3085 case 'b':
3086 case 'w':
3087 case 'W':
3088 case 'l':
3089 break;
3090 case 'e':
3091 the_ins.opcode[0] |= (val << 6);
3092 break;
3093 case 'L':
3094 the_ins.opcode[1] = (val >> 16);
3095 the_ins.opcode[2] = val & 0xffff;
3096 break;
3097 case 'm':
3098 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3099 the_ins.opcode[0] |= ((val & 0x7) << 9);
3100 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3101 break;
3102 case 'n':
3103 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3104 the_ins.opcode[0] |= ((val & 0x7) << 9);
3105 break;
3106 case 'o':
3107 the_ins.opcode[1] |= val << 12;
3108 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3109 break;
3110 case 'M':
3111 the_ins.opcode[0] |= (val & 0xF);
3112 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3113 break;
3114 case 'N':
3115 the_ins.opcode[1] |= (val & 0xF);
3116 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3117 break;
3118 case 'h':
3119 the_ins.opcode[1] |= ((val != 1) << 10);
3120 break;
3121 case 'c':
3122 default:
3123 as_fatal (_("failed sanity check."));
3124 }
3125 } /* install_operand() */
3126
3127 static void
3128 install_gen_operand (mode, val)
3129 int mode;
3130 int val;
3131 {
3132 switch (mode)
3133 {
3134 case 's':
3135 the_ins.opcode[0] |= val;
3136 break;
3137 case 'd':
3138 /* This is a kludge!!! */
3139 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3140 break;
3141 case 'b':
3142 case 'w':
3143 case 'l':
3144 case 'f':
3145 case 'F':
3146 case 'x':
3147 case 'p':
3148 the_ins.opcode[0] |= val;
3149 break;
3150 /* more stuff goes here */
3151 default:
3152 as_fatal (_("failed sanity check."));
3153 }
3154 } /* install_gen_operand() */
3155
3156 /*
3157 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3158 * then deal with the bitfield hack.
3159 */
3160
3161 static char *
3162 crack_operand (str, opP)
3163 register char *str;
3164 register struct m68k_op *opP;
3165 {
3166 register int parens;
3167 register int c;
3168 register char *beg_str;
3169 int inquote = 0;
3170
3171 if (!str)
3172 {
3173 return str;
3174 }
3175 beg_str = str;
3176 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3177 {
3178 if (! inquote)
3179 {
3180 if (*str == '(')
3181 parens++;
3182 else if (*str == ')')
3183 {
3184 if (!parens)
3185 { /* ERROR */
3186 opP->error = _("Extra )");
3187 return str;
3188 }
3189 --parens;
3190 }
3191 }
3192 if (flag_mri && *str == '\'')
3193 inquote = ! inquote;
3194 }
3195 if (!*str && parens)
3196 { /* ERROR */
3197 opP->error = _("Missing )");
3198 return str;
3199 }
3200 c = *str;
3201 *str = '\0';
3202 if (m68k_ip_op (beg_str, opP) != 0)
3203 {
3204 *str = c;
3205 return str;
3206 }
3207 *str = c;
3208 if (c == '}')
3209 c = *++str; /* JF bitfield hack */
3210 if (c)
3211 {
3212 c = *++str;
3213 if (!c)
3214 as_bad (_("Missing operand"));
3215 }
3216
3217 /* Detect MRI REG symbols and convert them to REGLSTs. */
3218 if (opP->mode == CONTROL && (int)opP->reg < 0)
3219 {
3220 opP->mode = REGLST;
3221 opP->mask = ~(int)opP->reg;
3222 opP->reg = 0;
3223 }
3224
3225 return str;
3226 }
3227
3228 /* This is the guts of the machine-dependent assembler. STR points to a
3229 machine dependent instruction. This function is supposed to emit
3230 the frags/bytes it assembles to.
3231 */
3232
3233 static void
3234 insert_reg (regname, regnum)
3235 const char *regname;
3236 int regnum;
3237 {
3238 char buf[100];
3239 int i;
3240
3241 #ifdef REGISTER_PREFIX
3242 if (!flag_reg_prefix_optional)
3243 {
3244 buf[0] = REGISTER_PREFIX;
3245 strcpy (buf + 1, regname);
3246 regname = buf;
3247 }
3248 #endif
3249
3250 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3251 &zero_address_frag));
3252
3253 for (i = 0; regname[i]; i++)
3254 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3255 buf[i] = '\0';
3256
3257 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3258 &zero_address_frag));
3259 }
3260
3261 struct init_entry
3262 {
3263 const char *name;
3264 int number;
3265 };
3266
3267 static const struct init_entry init_table[] =
3268 {
3269 { "d0", DATA0 },
3270 { "d1", DATA1 },
3271 { "d2", DATA2 },
3272 { "d3", DATA3 },
3273 { "d4", DATA4 },
3274 { "d5", DATA5 },
3275 { "d6", DATA6 },
3276 { "d7", DATA7 },
3277 { "a0", ADDR0 },
3278 { "a1", ADDR1 },
3279 { "a2", ADDR2 },
3280 { "a3", ADDR3 },
3281 { "a4", ADDR4 },
3282 { "a5", ADDR5 },
3283 { "a6", ADDR6 },
3284 { "fp", ADDR6 },
3285 { "a7", ADDR7 },
3286 { "sp", ADDR7 },
3287 { "ssp", ADDR7 },
3288 { "fp0", FP0 },
3289 { "fp1", FP1 },
3290 { "fp2", FP2 },
3291 { "fp3", FP3 },
3292 { "fp4", FP4 },
3293 { "fp5", FP5 },
3294 { "fp6", FP6 },
3295 { "fp7", FP7 },
3296 { "fpi", FPI },
3297 { "fpiar", FPI },
3298 { "fpc", FPI },
3299 { "fps", FPS },
3300 { "fpsr", FPS },
3301 { "fpc", FPC },
3302 { "fpcr", FPC },
3303 { "control", FPC },
3304 { "status", FPS },
3305 { "iaddr", FPI },
3306
3307 { "cop0", COP0 },
3308 { "cop1", COP1 },
3309 { "cop2", COP2 },
3310 { "cop3", COP3 },
3311 { "cop4", COP4 },
3312 { "cop5", COP5 },
3313 { "cop6", COP6 },
3314 { "cop7", COP7 },
3315 { "pc", PC },
3316 { "zpc", ZPC },
3317 { "sr", SR },
3318
3319 { "ccr", CCR },
3320 { "cc", CCR },
3321
3322 { "acc", ACC },
3323 { "macsr", MACSR },
3324 { "mask", MASK },
3325
3326 /* control registers */
3327 { "sfc", SFC }, /* Source Function Code */
3328 { "sfcr", SFC },
3329 { "dfc", DFC }, /* Destination Function Code */
3330 { "dfcr", DFC },
3331 { "cacr", CACR }, /* Cache Control Register */
3332 { "caar", CAAR }, /* Cache Address Register */
3333
3334 { "usp", USP }, /* User Stack Pointer */
3335 { "vbr", VBR }, /* Vector Base Register */
3336 { "msp", MSP }, /* Master Stack Pointer */
3337 { "isp", ISP }, /* Interrupt Stack Pointer */
3338
3339 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3340 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3341 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3342 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3343
3344 /* 68ec040 versions of same */
3345 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3346 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3347 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3348 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3349
3350 /* mcf5200 versions of same. The ColdFire programmer's reference
3351 manual indicated that the order is 2,3,0,1, but Ken Rose
3352 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3353 { "acr0", ITT0 }, /* Access Control Unit 0 */
3354 { "acr1", ITT1 }, /* Access Control Unit 1 */
3355 { "acr2", DTT0 }, /* Access Control Unit 2 */
3356 { "acr3", DTT1 }, /* Access Control Unit 3 */
3357
3358 { "tc", TC }, /* MMU Translation Control Register */
3359 { "tcr", TC },
3360
3361 { "mmusr", MMUSR }, /* MMU Status Register */
3362 { "srp", SRP }, /* User Root Pointer */
3363 { "urp", URP }, /* Supervisor Root Pointer */
3364
3365 { "buscr", BUSCR },
3366 { "pcr", PCR },
3367
3368 { "rombar", ROMBAR }, /* ROM Base Address Register */
3369 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3370 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3371 { "mbar", MBAR }, /* Module Base Address Register */
3372 /* end of control registers */
3373
3374 { "ac", AC },
3375 { "bc", BC },
3376 { "cal", CAL },
3377 { "crp", CRP },
3378 { "drp", DRP },
3379 { "pcsr", PCSR },
3380 { "psr", PSR },
3381 { "scc", SCC },
3382 { "val", VAL },
3383 { "bad0", BAD0 },
3384 { "bad1", BAD1 },
3385 { "bad2", BAD2 },
3386 { "bad3", BAD3 },
3387 { "bad4", BAD4 },
3388 { "bad5", BAD5 },
3389 { "bad6", BAD6 },
3390 { "bad7", BAD7 },
3391 { "bac0", BAC0 },
3392 { "bac1", BAC1 },
3393 { "bac2", BAC2 },
3394 { "bac3", BAC3 },
3395 { "bac4", BAC4 },
3396 { "bac5", BAC5 },
3397 { "bac6", BAC6 },
3398 { "bac7", BAC7 },
3399
3400 { "ic", IC },
3401 { "dc", DC },
3402 { "nc", NC },
3403
3404 { "tt0", TT0 },
3405 { "tt1", TT1 },
3406 /* 68ec030 versions of same */
3407 { "ac0", TT0 },
3408 { "ac1", TT1 },
3409 /* 68ec030 access control unit, identical to 030 MMU status reg */
3410 { "acusr", PSR },
3411
3412 /* Suppressed data and address registers. */
3413 { "zd0", ZDATA0 },
3414 { "zd1", ZDATA1 },
3415 { "zd2", ZDATA2 },
3416 { "zd3", ZDATA3 },
3417 { "zd4", ZDATA4 },
3418 { "zd5", ZDATA5 },
3419 { "zd6", ZDATA6 },
3420 { "zd7", ZDATA7 },
3421 { "za0", ZADDR0 },
3422 { "za1", ZADDR1 },
3423 { "za2", ZADDR2 },
3424 { "za3", ZADDR3 },
3425 { "za4", ZADDR4 },
3426 { "za5", ZADDR5 },
3427 { "za6", ZADDR6 },
3428 { "za7", ZADDR7 },
3429
3430 /* Upper and lower data and address registers, used by macw and msacw. */
3431 { "d0l", DATA0L },
3432 { "d1l", DATA1L },
3433 { "d2l", DATA2L },
3434 { "d3l", DATA3L },
3435 { "d4l", DATA4L },
3436 { "d5l", DATA5L },
3437 { "d6l", DATA6L },
3438 { "d7l", DATA7L },
3439
3440 { "a0l", ADDR0L },
3441 { "a1l", ADDR1L },
3442 { "a2l", ADDR2L },
3443 { "a3l", ADDR3L },
3444 { "a4l", ADDR4L },
3445 { "a5l", ADDR5L },
3446 { "a6l", ADDR6L },
3447 { "a7l", ADDR7L },
3448
3449 { "d0u", DATA0U },
3450 { "d1u", DATA1U },
3451 { "d2u", DATA2U },
3452 { "d3u", DATA3U },
3453 { "d4u", DATA4U },
3454 { "d5u", DATA5U },
3455 { "d6u", DATA6U },
3456 { "d7u", DATA7U },
3457
3458 { "a0u", ADDR0U },
3459 { "a1u", ADDR1U },
3460 { "a2u", ADDR2U },
3461 { "a3u", ADDR3U },
3462 { "a4u", ADDR4U },
3463 { "a5u", ADDR5U },
3464 { "a6u", ADDR6U },
3465 { "a7u", ADDR7U },
3466
3467 { 0, 0 }
3468 };
3469
3470 static void
3471 init_regtable ()
3472 {
3473 int i;
3474 for (i = 0; init_table[i].name; i++)
3475 insert_reg (init_table[i].name, init_table[i].number);
3476 }
3477
3478 static int no_68851, no_68881;
3479
3480 #ifdef OBJ_AOUT
3481 /* a.out machine type. Default to 68020. */
3482 int m68k_aout_machtype = 2;
3483 #endif
3484
3485 void
3486 md_assemble (str)
3487 char *str;
3488 {
3489 const char *er;
3490 short *fromP;
3491 char *toP = NULL;
3492 int m, n = 0;
3493 char *to_beg_P;
3494 int shorts_this_frag;
3495 fixS *fixP;
3496
3497 /* In MRI mode, the instruction and operands are separated by a
3498 space. Anything following the operands is a comment. The label
3499 has already been removed. */
3500 if (flag_mri)
3501 {
3502 char *s;
3503 int fields = 0;
3504 int infield = 0;
3505 int inquote = 0;
3506
3507 for (s = str; *s != '\0'; s++)
3508 {
3509 if ((*s == ' ' || *s == '\t') && ! inquote)
3510 {
3511 if (infield)
3512 {
3513 ++fields;
3514 if (fields >= 2)
3515 {
3516 *s = '\0';
3517 break;
3518 }
3519 infield = 0;
3520 }
3521 }
3522 else
3523 {
3524 if (! infield)
3525 infield = 1;
3526 if (*s == '\'')
3527 inquote = ! inquote;
3528 }
3529 }
3530 }
3531
3532 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3533 m68k_ip (str);
3534 er = the_ins.error;
3535 if (!er)
3536 {
3537 for (n = 0; n < the_ins.numargs; n++)
3538 if (the_ins.operands[n].error)
3539 {
3540 er = the_ins.operands[n].error;
3541 break;
3542 }
3543 }
3544 if (er)
3545 {
3546 as_bad (_("%s -- statement `%s' ignored"), er, str);
3547 return;
3548 }
3549
3550 /* If there is a current label, record that it marks an instruction. */
3551 if (current_label != NULL)
3552 {
3553 current_label->text = 1;
3554 current_label = NULL;
3555 }
3556
3557 if (the_ins.nfrag == 0)
3558 {
3559 /* No frag hacking involved; just put it out */
3560 toP = frag_more (2 * the_ins.numo);
3561 fromP = &the_ins.opcode[0];
3562 for (m = the_ins.numo; m; --m)
3563 {
3564 md_number_to_chars (toP, (long) (*fromP), 2);
3565 toP += 2;
3566 fromP++;
3567 }
3568 /* put out symbol-dependent info */
3569 for (m = 0; m < the_ins.nrel; m++)
3570 {
3571 switch (the_ins.reloc[m].wid)
3572 {
3573 case 'B':
3574 n = 1;
3575 break;
3576 case 'b':
3577 n = 1;
3578 break;
3579 case '3':
3580 n = 1;
3581 break;
3582 case 'w':
3583 case 'W':
3584 n = 2;
3585 break;
3586 case 'l':
3587 n = 4;
3588 break;
3589 default:
3590 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3591 the_ins.reloc[m].wid);
3592 }
3593
3594 fixP = fix_new_exp (frag_now,
3595 ((toP - frag_now->fr_literal)
3596 - the_ins.numo * 2 + the_ins.reloc[m].n),
3597 n,
3598 &the_ins.reloc[m].exp,
3599 the_ins.reloc[m].pcrel,
3600 get_reloc_code (n, the_ins.reloc[m].pcrel,
3601 the_ins.reloc[m].pic_reloc));
3602 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3603 if (the_ins.reloc[m].wid == 'B')
3604 fixP->fx_signed = 1;
3605 }
3606 return;
3607 }
3608
3609 /* There's some frag hacking */
3610 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3611 {
3612 int wid;
3613
3614 if (n == 0)
3615 wid = 2 * the_ins.fragb[n].fragoff;
3616 else
3617 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3618 toP = frag_more (wid);
3619 to_beg_P = toP;
3620 shorts_this_frag = 0;
3621 for (m = wid / 2; m; --m)
3622 {
3623 md_number_to_chars (toP, (long) (*fromP), 2);
3624 toP += 2;
3625 fromP++;
3626 shorts_this_frag++;
3627 }
3628 for (m = 0; m < the_ins.nrel; m++)
3629 {
3630 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3631 {
3632 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3633 break;
3634 }
3635 wid = the_ins.reloc[m].wid;
3636 if (wid == 0)
3637 continue;
3638 the_ins.reloc[m].wid = 0;
3639 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3640
3641 fixP = fix_new_exp (frag_now,
3642 ((toP - frag_now->fr_literal)
3643 - the_ins.numo * 2 + the_ins.reloc[m].n),
3644 wid,
3645 &the_ins.reloc[m].exp,
3646 the_ins.reloc[m].pcrel,
3647 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3648 the_ins.reloc[m].pic_reloc));
3649 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3650 }
3651 (void) frag_var (rs_machine_dependent, 10, 0,
3652 (relax_substateT) (the_ins.fragb[n].fragty),
3653 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3654 }
3655 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3656 shorts_this_frag = 0;
3657 if (n)
3658 {
3659 toP = frag_more (n * sizeof (short));
3660 while (n--)
3661 {
3662 md_number_to_chars (toP, (long) (*fromP), 2);
3663 toP += 2;
3664 fromP++;
3665 shorts_this_frag++;
3666 }
3667 }
3668 for (m = 0; m < the_ins.nrel; m++)
3669 {
3670 int wid;
3671
3672 wid = the_ins.reloc[m].wid;
3673 if (wid == 0)
3674 continue;
3675 the_ins.reloc[m].wid = 0;
3676 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3677
3678 fixP = fix_new_exp (frag_now,
3679 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3680 - shorts_this_frag * 2),
3681 wid,
3682 &the_ins.reloc[m].exp,
3683 the_ins.reloc[m].pcrel,
3684 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3685 the_ins.reloc[m].pic_reloc));
3686 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3687 }
3688 }
3689
3690 void
3691 md_begin ()
3692 {
3693 /*
3694 * md_begin -- set up hash tables with 68000 instructions.
3695 * similar to what the vax assembler does. ---phr
3696 */
3697 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3698 a copy of it at runtime, adding in the information we want but isn't
3699 there. I think it'd be better to have an awk script hack the table
3700 at compile time. Or even just xstr the table and use it as-is. But
3701 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3702 names. */
3703
3704 register const struct m68k_opcode *ins;
3705 register struct m68k_incant *hack, *slak;
3706 register const char *retval = 0; /* empty string, or error msg text */
3707 register int i;
3708 register char c;
3709
3710 if (flag_mri)
3711 {
3712 flag_reg_prefix_optional = 1;
3713 m68k_abspcadd = 1;
3714 if (! m68k_rel32_from_cmdline)
3715 m68k_rel32 = 0;
3716 }
3717
3718 op_hash = hash_new ();
3719
3720 obstack_begin (&robyn, 4000);
3721 for (i = 0; i < m68k_numopcodes; i++)
3722 {
3723 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3724 do
3725 {
3726 ins = &m68k_opcodes[i];
3727 /* We *could* ignore insns that don't match our arch here
3728 but just leaving them out of the hash. */
3729 slak->m_operands = ins->args;
3730 slak->m_opnum = strlen (slak->m_operands) / 2;
3731 slak->m_arch = ins->arch;
3732 slak->m_opcode = ins->opcode;
3733 /* This is kludgey */
3734 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3735 if (i + 1 != m68k_numopcodes
3736 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3737 {
3738 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3739 i++;
3740 }
3741 else
3742 slak->m_next = 0;
3743 slak = slak->m_next;
3744 }
3745 while (slak);
3746
3747 retval = hash_insert (op_hash, ins->name, (char *) hack);
3748 if (retval)
3749 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3750 }
3751
3752 for (i = 0; i < m68k_numaliases; i++)
3753 {
3754 const char *name = m68k_opcode_aliases[i].primary;
3755 const char *alias = m68k_opcode_aliases[i].alias;
3756 PTR val = hash_find (op_hash, name);
3757 if (!val)
3758 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3759 retval = hash_insert (op_hash, alias, val);
3760 if (retval)
3761 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3762 }
3763
3764 /* In MRI mode, all unsized branches are variable sized. Normally,
3765 they are word sized. */
3766 if (flag_mri)
3767 {
3768 static struct m68k_opcode_alias mri_aliases[] =
3769 {
3770 { "bhi", "jhi", },
3771 { "bls", "jls", },
3772 { "bcc", "jcc", },
3773 { "bcs", "jcs", },
3774 { "bne", "jne", },
3775 { "beq", "jeq", },
3776 { "bvc", "jvc", },
3777 { "bvs", "jvs", },
3778 { "bpl", "jpl", },
3779 { "bmi", "jmi", },
3780 { "bge", "jge", },
3781 { "blt", "jlt", },
3782 { "bgt", "jgt", },
3783 { "ble", "jle", },
3784 { "bra", "jra", },
3785 { "bsr", "jbsr", },
3786 };
3787
3788 for (i = 0;
3789 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3790 i++)
3791 {
3792 const char *name = mri_aliases[i].primary;
3793 const char *alias = mri_aliases[i].alias;
3794 PTR val = hash_find (op_hash, name);
3795 if (!val)
3796 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3797 retval = hash_jam (op_hash, alias, val);
3798 if (retval)
3799 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3800 }
3801 }
3802
3803 for (i = 0; i < (int) sizeof (mklower_table); i++)
3804 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3805
3806 for (i = 0; i < (int) sizeof (notend_table); i++)
3807 {
3808 notend_table[i] = 0;
3809 alt_notend_table[i] = 0;
3810 }
3811 notend_table[','] = 1;
3812 notend_table['{'] = 1;
3813 notend_table['}'] = 1;
3814 alt_notend_table['a'] = 1;
3815 alt_notend_table['A'] = 1;
3816 alt_notend_table['d'] = 1;
3817 alt_notend_table['D'] = 1;
3818 alt_notend_table['#'] = 1;
3819 alt_notend_table['&'] = 1;
3820 alt_notend_table['f'] = 1;
3821 alt_notend_table['F'] = 1;
3822 #ifdef REGISTER_PREFIX
3823 alt_notend_table[REGISTER_PREFIX] = 1;
3824 #endif
3825
3826 /* We need to put '(' in alt_notend_table to handle
3827 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3828 */
3829 alt_notend_table['('] = 1;
3830
3831 /* We need to put '@' in alt_notend_table to handle
3832 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3833 */
3834 alt_notend_table['@'] = 1;
3835
3836 /* We need to put digits in alt_notend_table to handle
3837 bfextu %d0{24:1},%d0
3838 */
3839 alt_notend_table['0'] = 1;
3840 alt_notend_table['1'] = 1;
3841 alt_notend_table['2'] = 1;
3842 alt_notend_table['3'] = 1;
3843 alt_notend_table['4'] = 1;
3844 alt_notend_table['5'] = 1;
3845 alt_notend_table['6'] = 1;
3846 alt_notend_table['7'] = 1;
3847 alt_notend_table['8'] = 1;
3848 alt_notend_table['9'] = 1;
3849
3850 #ifndef MIT_SYNTAX_ONLY
3851 /* Insert pseudo ops, these have to go into the opcode table since
3852 gas expects pseudo ops to start with a dot */
3853 {
3854 int n = 0;
3855 while (mote_pseudo_table[n].poc_name)
3856 {
3857 hack = (struct m68k_incant *)
3858 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3859 hash_insert (op_hash,
3860 mote_pseudo_table[n].poc_name, (char *) hack);
3861 hack->m_operands = 0;
3862 hack->m_opnum = n;
3863 n++;
3864 }
3865 }
3866 #endif
3867
3868 init_regtable ();
3869
3870 #ifdef OBJ_ELF
3871 record_alignment (text_section, 2);
3872 record_alignment (data_section, 2);
3873 record_alignment (bss_section, 2);
3874 #endif
3875 }
3876
3877 static void
3878 select_control_regs ()
3879 {
3880 /* Note which set of "movec" control registers is available. */
3881 switch (cpu_of_arch (current_architecture))
3882 {
3883 case m68000:
3884 control_regs = m68000_control_regs;
3885 break;
3886 case m68010:
3887 control_regs = m68010_control_regs;
3888 break;
3889 case m68020:
3890 case m68030:
3891 control_regs = m68020_control_regs;
3892 break;
3893 case m68040:
3894 control_regs = m68040_control_regs;
3895 break;
3896 case m68060:
3897 control_regs = m68060_control_regs;
3898 break;
3899 case cpu32:
3900 control_regs = cpu32_control_regs;
3901 break;
3902 case mcf5200:
3903 case mcf5206e:
3904 case mcf5307:
3905 control_regs = mcf_control_regs;
3906 break;
3907 default:
3908 abort ();
3909 }
3910 }
3911
3912 void
3913 m68k_init_after_args ()
3914 {
3915 if (cpu_of_arch (current_architecture) == 0)
3916 {
3917 int i;
3918 const char *default_cpu = TARGET_CPU;
3919
3920 if (*default_cpu == 'm')
3921 default_cpu++;
3922 for (i = 0; i < n_archs; i++)
3923 if (strcasecmp (default_cpu, archs[i].name) == 0)
3924 break;
3925 if (i == n_archs)
3926 {
3927 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3928 current_architecture |= m68020;
3929 }
3930 else
3931 current_architecture |= archs[i].arch;
3932 }
3933 /* Permit m68881 specification with all cpus; those that can't work
3934 with a coprocessor could be doing emulation. */
3935 if (current_architecture & m68851)
3936 {
3937 if (current_architecture & m68040)
3938 {
3939 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
3940 }
3941 }
3942 /* What other incompatibilities could we check for? */
3943
3944 /* Toss in some default assumptions about coprocessors. */
3945 if (!no_68881
3946 && (cpu_of_arch (current_architecture)
3947 /* Can CPU32 have a 68881 coprocessor?? */
3948 & (m68020 | m68030 | cpu32)))
3949 {
3950 current_architecture |= m68881;
3951 }
3952 if (!no_68851
3953 && (cpu_of_arch (current_architecture) & m68020up) != 0
3954 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3955 {
3956 current_architecture |= m68851;
3957 }
3958 if (no_68881 && (current_architecture & m68881))
3959 as_bad (_("options for 68881 and no-68881 both given"));
3960 if (no_68851 && (current_architecture & m68851))
3961 as_bad (_("options for 68851 and no-68851 both given"));
3962
3963 #ifdef OBJ_AOUT
3964 /* Work out the magic number. This isn't very general. */
3965 if (current_architecture & m68000)
3966 m68k_aout_machtype = 0;
3967 else if (current_architecture & m68010)
3968 m68k_aout_machtype = 1;
3969 else if (current_architecture & m68020)
3970 m68k_aout_machtype = 2;
3971 else
3972 m68k_aout_machtype = 2;
3973 #endif
3974
3975 /* Note which set of "movec" control registers is available. */
3976 select_control_regs ();
3977
3978 if (cpu_of_arch (current_architecture) < m68020
3979 || arch_coldfire_p (current_architecture))
3980 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3981 }
3982 \f
3983 /* This is called when a label is defined. */
3984
3985 void
3986 m68k_frob_label (sym)
3987 symbolS *sym;
3988 {
3989 struct label_line *n;
3990
3991 n = (struct label_line *) xmalloc (sizeof *n);
3992 n->next = labels;
3993 n->label = sym;
3994 as_where (&n->file, &n->line);
3995 n->text = 0;
3996 labels = n;
3997 current_label = n;
3998 }
3999
4000 /* This is called when a value that is not an instruction is emitted. */
4001
4002 void
4003 m68k_flush_pending_output ()
4004 {
4005 current_label = NULL;
4006 }
4007
4008 /* This is called at the end of the assembly, when the final value of
4009 the label is known. We warn if this is a text symbol aligned at an
4010 odd location. */
4011
4012 void
4013 m68k_frob_symbol (sym)
4014 symbolS *sym;
4015 {
4016 if (S_GET_SEGMENT (sym) == reg_section
4017 && (int) S_GET_VALUE (sym) < 0)
4018 {
4019 S_SET_SEGMENT (sym, absolute_section);
4020 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4021 }
4022 else if ((S_GET_VALUE (sym) & 1) != 0)
4023 {
4024 struct label_line *l;
4025
4026 for (l = labels; l != NULL; l = l->next)
4027 {
4028 if (l->label == sym)
4029 {
4030 if (l->text)
4031 as_warn_where (l->file, l->line,
4032 _("text label `%s' aligned to odd boundary"),
4033 S_GET_NAME (sym));
4034 break;
4035 }
4036 }
4037 }
4038 }
4039 \f
4040 /* This is called if we go in or out of MRI mode because of the .mri
4041 pseudo-op. */
4042
4043 void
4044 m68k_mri_mode_change (on)
4045 int on;
4046 {
4047 if (on)
4048 {
4049 if (! flag_reg_prefix_optional)
4050 {
4051 flag_reg_prefix_optional = 1;
4052 #ifdef REGISTER_PREFIX
4053 init_regtable ();
4054 #endif
4055 }
4056 m68k_abspcadd = 1;
4057 if (! m68k_rel32_from_cmdline)
4058 m68k_rel32 = 0;
4059 }
4060 else
4061 {
4062 if (! reg_prefix_optional_seen)
4063 {
4064 #ifdef REGISTER_PREFIX_OPTIONAL
4065 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4066 #else
4067 flag_reg_prefix_optional = 0;
4068 #endif
4069 #ifdef REGISTER_PREFIX
4070 init_regtable ();
4071 #endif
4072 }
4073 m68k_abspcadd = 0;
4074 if (! m68k_rel32_from_cmdline)
4075 m68k_rel32 = 1;
4076 }
4077 }
4078
4079 /* Equal to MAX_PRECISION in atof-ieee.c */
4080 #define MAX_LITTLENUMS 6
4081
4082 /* Turn a string in input_line_pointer into a floating point constant
4083 of type TYPE, and store the appropriate bytes in *LITP. The number
4084 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4085 returned, or NULL on OK. */
4086
4087 char *
4088 md_atof (type, litP, sizeP)
4089 char type;
4090 char *litP;
4091 int *sizeP;
4092 {
4093 int prec;
4094 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4095 LITTLENUM_TYPE *wordP;
4096 char *t;
4097
4098 switch (type)
4099 {
4100 case 'f':
4101 case 'F':
4102 case 's':
4103 case 'S':
4104 prec = 2;
4105 break;
4106
4107 case 'd':
4108 case 'D':
4109 case 'r':
4110 case 'R':
4111 prec = 4;
4112 break;
4113
4114 case 'x':
4115 case 'X':
4116 prec = 6;
4117 break;
4118
4119 case 'p':
4120 case 'P':
4121 prec = 6;
4122 break;
4123
4124 default:
4125 *sizeP = 0;
4126 return _("Bad call to MD_ATOF()");
4127 }
4128 t = atof_ieee (input_line_pointer, type, words);
4129 if (t)
4130 input_line_pointer = t;
4131
4132 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4133 for (wordP = words; prec--;)
4134 {
4135 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4136 litP += sizeof (LITTLENUM_TYPE);
4137 }
4138 return 0;
4139 }
4140
4141 void
4142 md_number_to_chars (buf, val, n)
4143 char *buf;
4144 valueT val;
4145 int n;
4146 {
4147 number_to_chars_bigendian (buf, val, n);
4148 }
4149
4150 static void
4151 md_apply_fix_2 (fixP, val)
4152 fixS *fixP;
4153 offsetT val;
4154 {
4155 addressT upper_limit;
4156 offsetT lower_limit;
4157
4158 /* This is unnecessary but it convinces the native rs6000 compiler
4159 to generate the code we want. */
4160 char *buf = fixP->fx_frag->fr_literal;
4161 buf += fixP->fx_where;
4162 /* end ibm compiler workaround */
4163
4164 if (val & 0x80000000)
4165 val |= ~(addressT)0x7fffffff;
4166 else
4167 val &= 0x7fffffff;
4168
4169 #ifdef OBJ_ELF
4170 if (fixP->fx_addsy)
4171 {
4172 memset (buf, 0, fixP->fx_size);
4173 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4174
4175 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4176 && !S_IS_DEFINED (fixP->fx_addsy)
4177 && !S_IS_WEAK (fixP->fx_addsy))
4178 S_SET_WEAK (fixP->fx_addsy);
4179 return;
4180 }
4181 #endif
4182
4183 #ifdef BFD_ASSEMBLER
4184 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4185 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4186 return;
4187 #endif
4188
4189 switch (fixP->fx_size)
4190 {
4191 /* The cast to offsetT below are necessary to make code correct for
4192 machines where ints are smaller than offsetT */
4193 case 1:
4194 *buf++ = val;
4195 upper_limit = 0x7f;
4196 lower_limit = - (offsetT) 0x80;
4197 break;
4198 case 2:
4199 *buf++ = (val >> 8);
4200 *buf++ = val;
4201 upper_limit = 0x7fff;
4202 lower_limit = - (offsetT) 0x8000;
4203 break;
4204 case 4:
4205 *buf++ = (val >> 24);
4206 *buf++ = (val >> 16);
4207 *buf++ = (val >> 8);
4208 *buf++ = val;
4209 upper_limit = 0x7fffffff;
4210 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4211 break;
4212 default:
4213 BAD_CASE (fixP->fx_size);
4214 }
4215
4216 /* Fix up a negative reloc. */
4217 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4218 {
4219 fixP->fx_addsy = fixP->fx_subsy;
4220 fixP->fx_subsy = NULL;
4221 fixP->fx_tcbit = 1;
4222 }
4223
4224 /* For non-pc-relative values, it's conceivable we might get something
4225 like "0xff" for a byte field. So extend the upper part of the range
4226 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4227 so that we can do any range checking at all. */
4228 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4229 upper_limit = upper_limit * 2 + 1;
4230
4231 if ((addressT) val > upper_limit
4232 && (val > 0 || val < lower_limit))
4233 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4234
4235 /* A one byte PC-relative reloc means a short branch. We can't use
4236 a short branch with a value of 0 or -1, because those indicate
4237 different opcodes (branches with longer offsets). fixup_segment
4238 in write.c may have clobbered fx_pcrel, so we need to examine the
4239 reloc type. */
4240 if ((fixP->fx_pcrel
4241 #ifdef BFD_ASSEMBLER
4242 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4243 #endif
4244 )
4245 && fixP->fx_size == 1
4246 && (fixP->fx_addsy == NULL
4247 || S_IS_DEFINED (fixP->fx_addsy))
4248 && (val == 0 || val == -1))
4249 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4250 }
4251
4252 #ifdef BFD_ASSEMBLER
4253 int
4254 md_apply_fix (fixP, valp)
4255 fixS *fixP;
4256 valueT *valp;
4257 {
4258 md_apply_fix_2 (fixP, (addressT) *valp);
4259 return 1;
4260 }
4261 #else
4262 void md_apply_fix (fixP, val)
4263 fixS *fixP;
4264 long val;
4265 {
4266 md_apply_fix_2 (fixP, (addressT) val);
4267 }
4268 #endif
4269
4270 /* *fragP has been relaxed to its final size, and now needs to have
4271 the bytes inside it modified to conform to the new size There is UGLY
4272 MAGIC here. ..
4273 */
4274 static void
4275 md_convert_frag_1 (fragP)
4276 register fragS *fragP;
4277 {
4278 long disp;
4279 long ext = 0;
4280 fixS *fixP;
4281
4282 /* Address in object code of the displacement. */
4283 register int object_address = fragP->fr_fix + fragP->fr_address;
4284
4285 /* Address in gas core of the place to store the displacement. */
4286 /* This convinces the native rs6000 compiler to generate the code we
4287 want. */
4288 register char *buffer_address = fragP->fr_literal;
4289 buffer_address += fragP->fr_fix;
4290 /* end ibm compiler workaround */
4291
4292 /* The displacement of the address, from current location. */
4293 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4294 disp = (disp + fragP->fr_offset) - object_address;
4295
4296 #ifdef BFD_ASSEMBLER
4297 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
4298 #endif
4299
4300 switch (fragP->fr_subtype)
4301 {
4302 case TAB (BCC68000, BYTE):
4303 case TAB (ABRANCH, BYTE):
4304 know (issbyte (disp));
4305 if (disp == 0)
4306 as_bad (_("short branch with zero offset: use :w"));
4307 fragP->fr_opcode[1] = disp;
4308 ext = 0;
4309 break;
4310 case TAB (DBCC, SHORT):
4311 know (issword (disp));
4312 ext = 2;
4313 break;
4314 case TAB (BCC68000, SHORT):
4315 case TAB (ABRANCH, SHORT):
4316 know (issword (disp));
4317 fragP->fr_opcode[1] = 0x00;
4318 ext = 2;
4319 break;
4320 case TAB (ABRANCH, LONG):
4321 if (!HAVE_LONG_BRANCH (current_architecture))
4322 {
4323 if (flag_keep_pcrel)
4324 as_bad (_("long branch not supported"));
4325
4326 if (fragP->fr_opcode[0] == 0x61)
4327 /* BSR */
4328 {
4329 fragP->fr_opcode[0] = 0x4E;
4330 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4331
4332 fix_new (fragP,
4333 fragP->fr_fix,
4334 4,
4335 fragP->fr_symbol,
4336 fragP->fr_offset,
4337 0,
4338 NO_RELOC);
4339
4340 fragP->fr_fix += 4;
4341 ext = 0;
4342 }
4343 /* BRA */
4344 else if (fragP->fr_opcode[0] == 0x60)
4345 {
4346 fragP->fr_opcode[0] = 0x4E;
4347 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4348 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4349 fragP->fr_offset, 0, NO_RELOC);
4350 fragP->fr_fix += 4;
4351 ext = 0;
4352 }
4353 else
4354 {
4355 /* This should never happen, because if it's a conditional
4356 branch and we are on a 68000, BCC68000 should have been
4357 picked instead of ABRANCH. */
4358 abort ();
4359 }
4360 }
4361 else
4362 {
4363 fragP->fr_opcode[1] = (char) 0xff;
4364 ext = 4;
4365 }
4366 break;
4367 case TAB (BCC68000, LONG):
4368 /* only Bcc 68000 instructions can come here */
4369 /* change bcc into b!cc/jmp absl long */
4370 if (flag_keep_pcrel)
4371 as_bad (_("long branch not supported"));
4372
4373 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4374 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4375
4376 /* JF: these used to be fr_opcode[2,3], but they may be in a
4377 different frag, in which case refering to them is a no-no.
4378 Only fr_opcode[0,1] are guaranteed to work. */
4379 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4380 *buffer_address++ = (char) 0xf9;
4381 fragP->fr_fix += 2; /* account for jmp instruction */
4382 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4383 fragP->fr_offset, 0, NO_RELOC);
4384 fragP->fr_fix += 4;
4385 ext = 0;
4386 break;
4387 case TAB (DBCC, LONG):
4388 /* only DBcc 68000 instructions can come here */
4389 /* Change dbcc into dbcc/bral. */
4390 if (! HAVE_LONG_BRANCH (current_architecture) && flag_keep_pcrel)
4391 as_bad (_("long branch not supported"));
4392
4393 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4394 *buffer_address++ = 0x00; /* branch offset = 4 */
4395 *buffer_address++ = 0x04;
4396 *buffer_address++ = 0x60; /* put in bra pc+6 */
4397 *buffer_address++ = 0x06;
4398 if (HAVE_LONG_BRANCH (current_architecture))
4399 {
4400 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4401 *buffer_address++ = (char) 0xff;
4402 }
4403 else
4404 {
4405 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4406 *buffer_address++ = (char) 0xf9;
4407 }
4408
4409 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4410 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4411 fragP->fr_offset, HAVE_LONG_BRANCH (current_architecture),
4412 NO_RELOC);
4413 fragP->fr_fix += 4;
4414 ext = 0;
4415 break;
4416 case TAB (FBRANCH, SHORT):
4417 know ((fragP->fr_opcode[1] & 0x40) == 0);
4418 ext = 2;
4419 break;
4420 case TAB (FBRANCH, LONG):
4421 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4422 ext = 4;
4423 break;
4424 case TAB (PCREL, SHORT):
4425 ext = 2;
4426 break;
4427 case TAB (PCREL, LONG):
4428 /* The thing to do here is force it to ABSOLUTE LONG, since
4429 PCREL is really trying to shorten an ABSOLUTE address anyway */
4430 /* JF FOO This code has not been tested */
4431 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4432 0, NO_RELOC);
4433 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4434 as_bad (_("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx"),
4435 (unsigned) fragP->fr_opcode[0],
4436 (unsigned long) fragP->fr_address);
4437 fragP->fr_opcode[1] &= ~0x3F;
4438 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4439 fragP->fr_fix += 4;
4440 ext = 0;
4441 break;
4442 case TAB (PCLEA, SHORT):
4443 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4444 fragP->fr_offset, 1, NO_RELOC);
4445 fragP->fr_opcode[1] &= ~0x3F;
4446 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4447 ext = 2;
4448 break;
4449 case TAB (PCLEA, LONG):
4450 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4451 fragP->fr_offset, 1, NO_RELOC);
4452 fixP->fx_pcrel_adjust = 2;
4453 /* Already set to mode 7.3; this indicates: PC indirect with
4454 suppressed index, 32-bit displacement. */
4455 *buffer_address++ = 0x01;
4456 *buffer_address++ = 0x70;
4457 fragP->fr_fix += 2;
4458 ext = 4;
4459 break;
4460
4461 case TAB (PCINDEX, BYTE):
4462 disp += 2;
4463 if (!issbyte (disp))
4464 {
4465 as_bad (_("displacement doesn't fit in one byte"));
4466 disp = 0;
4467 }
4468 assert (fragP->fr_fix >= 2);
4469 buffer_address[-2] &= ~1;
4470 buffer_address[-1] = disp;
4471 ext = 0;
4472 break;
4473 case TAB (PCINDEX, SHORT):
4474 disp += 2;
4475 assert (issword (disp));
4476 assert (fragP->fr_fix >= 2);
4477 buffer_address[-2] |= 0x1;
4478 buffer_address[-1] = 0x20;
4479 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4480 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4481 NO_RELOC);
4482 fixP->fx_pcrel_adjust = 2;
4483 ext = 2;
4484 break;
4485 case TAB (PCINDEX, LONG):
4486 disp += 2;
4487 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4488 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4489 NO_RELOC);
4490 fixP->fx_pcrel_adjust = 2;
4491 assert (fragP->fr_fix >= 2);
4492 buffer_address[-2] |= 0x1;
4493 buffer_address[-1] = 0x30;
4494 ext = 4;
4495 break;
4496 }
4497
4498 if (ext)
4499 {
4500 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4501 fragP->fr_fix += ext;
4502 }
4503 }
4504
4505 #ifndef BFD_ASSEMBLER
4506
4507 void
4508 md_convert_frag (headers, sec, fragP)
4509 object_headers *headers ATTRIBUTE_UNUSED;
4510 segT sec ATTRIBUTE_UNUSED;
4511 fragS *fragP;
4512 {
4513 md_convert_frag_1 (fragP);
4514 }
4515
4516 #else
4517
4518 void
4519 md_convert_frag (abfd, sec, fragP)
4520 bfd *abfd ATTRIBUTE_UNUSED;
4521 segT sec ATTRIBUTE_UNUSED;
4522 fragS *fragP;
4523 {
4524 md_convert_frag_1 (fragP);
4525 }
4526 #endif
4527
4528 /* Force truly undefined symbols to their maximum size, and generally set up
4529 the frag list to be relaxed
4530 */
4531 int
4532 md_estimate_size_before_relax (fragP, segment)
4533 register fragS *fragP;
4534 segT segment;
4535 {
4536 int old_fix;
4537 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4538
4539 old_fix = fragP->fr_fix;
4540
4541 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4542 switch (fragP->fr_subtype)
4543 {
4544
4545 case TAB (ABRANCH, SZ_UNDEF):
4546 {
4547 if ((fragP->fr_symbol != NULL) /* Not absolute */
4548 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4549 && relaxable_symbol (fragP->fr_symbol))
4550 {
4551 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4552 break;
4553 }
4554 else if ((fragP->fr_symbol != NULL)
4555 && (flag_short_refs || flag_keep_pcrel))
4556 { /* Symbol is undefined and we want short ref */
4557 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4558 fragP->fr_offset, 1, NO_RELOC);
4559 fragP->fr_fix += 2;
4560 frag_wane (fragP);
4561 break;
4562 }
4563 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4564 {
4565 /* On 68000, or for absolute value, switch to abs long */
4566 /* FIXME, we should check abs val, pick short or long */
4567 if (fragP->fr_opcode[0] == 0x61)
4568 {
4569 fragP->fr_opcode[0] = 0x4E;
4570 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4571 fix_new (fragP, fragP->fr_fix, 4,
4572 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4573 fragP->fr_fix += 4;
4574 frag_wane (fragP);
4575 }
4576 else if (fragP->fr_opcode[0] == 0x60)
4577 {
4578 fragP->fr_opcode[0] = 0x4E;
4579 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4580 fix_new (fragP, fragP->fr_fix, 4,
4581 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4582 fragP->fr_fix += 4;
4583 frag_wane (fragP);
4584 }
4585 else
4586 {
4587 /* This should never happen, because if it's a conditional
4588 branch and we are on a 68000, BCC68000 should have been
4589 picked instead of ABRANCH. */
4590 abort ();
4591 }
4592 }
4593 else
4594 { /* Symbol is still undefined. Make it simple */
4595 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4596 fragP->fr_offset, 1, NO_RELOC);
4597 fragP->fr_fix += 4;
4598 fragP->fr_opcode[1] = (char) 0xff;
4599 frag_wane (fragP);
4600 break;
4601 }
4602
4603 break;
4604 } /* case TAB(ABRANCH,SZ_UNDEF) */
4605
4606 case TAB (FBRANCH, SZ_UNDEF):
4607 {
4608 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4609 && relaxable_symbol (fragP->fr_symbol))
4610 || flag_short_refs)
4611 {
4612 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4613 fragP->fr_var += 2;
4614 }
4615 else
4616 {
4617 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4618 fragP->fr_offset, 1, NO_RELOC);
4619 fragP->fr_fix += 4;
4620 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4621 frag_wane (fragP);
4622 }
4623 break;
4624 } /* TAB(FBRANCH,SZ_UNDEF) */
4625
4626 case TAB (PCREL, SZ_UNDEF):
4627 {
4628 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4629 && relaxable_symbol (fragP->fr_symbol))
4630 || flag_short_refs)
4631 {
4632 fragP->fr_subtype = TAB (PCREL, SHORT);
4633 fragP->fr_var += 2;
4634 }
4635 else
4636 {
4637 fragP->fr_subtype = TAB (PCREL, LONG);
4638 fragP->fr_var += 4;
4639 }
4640 break;
4641 } /* TAB(PCREL,SZ_UNDEF) */
4642
4643 case TAB (BCC68000, SZ_UNDEF):
4644 {
4645 if ((fragP->fr_symbol != NULL)
4646 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4647 && relaxable_symbol (fragP->fr_symbol))
4648 {
4649 fragP->fr_subtype = TAB (BCC68000, BYTE);
4650 break;
4651 }
4652 /* only Bcc 68000 instructions can come here */
4653 if ((fragP->fr_symbol != NULL) && (flag_short_refs || flag_keep_pcrel))
4654 {
4655 /* the user wants short refs, so emit one */
4656 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4657 fragP->fr_offset, 1, NO_RELOC);
4658 fragP->fr_fix += 2;
4659 }
4660 else
4661 {
4662 /* change bcc into b!cc/jmp absl long */
4663 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4664 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4665 /* JF: these were fr_opcode[2,3] */
4666 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4667 buffer_address[1] = (char) 0xf9;
4668 fragP->fr_fix += 2; /* account for jmp instruction */
4669 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4670 fragP->fr_offset, 0, NO_RELOC);
4671 fragP->fr_fix += 4;
4672 }
4673 frag_wane (fragP);
4674 break;
4675 } /* case TAB(BCC68000,SZ_UNDEF) */
4676
4677 case TAB (DBCC, SZ_UNDEF):
4678 {
4679 if (fragP->fr_symbol != NULL
4680 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4681 && relaxable_symbol (fragP->fr_symbol))
4682 {
4683 fragP->fr_subtype = TAB (DBCC, SHORT);
4684 fragP->fr_var += 2;
4685 break;
4686 }
4687 /* only DBcc 68000 instructions can come here */
4688
4689 if (fragP->fr_symbol != NULL
4690 && (flag_short_refs
4691 || (! HAVE_LONG_BRANCH (current_architecture)
4692 && flag_keep_pcrel)))
4693 {
4694 /* the user wants short refs, so emit one */
4695 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4696 fragP->fr_offset, 1, NO_RELOC);
4697 fragP->fr_fix += 2;
4698 }
4699 else
4700 {
4701 /* Change dbcc into dbcc/bral. */
4702 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4703 buffer_address[0] = 0x00; /* branch offset = 4 */
4704 buffer_address[1] = 0x04;
4705 buffer_address[2] = 0x60; /* put in bra pc + ... */
4706 /* JF: these were fr_opcode[5-7] */
4707 buffer_address[3] = 0x06; /* Plus 6 */
4708 if (HAVE_LONG_BRANCH (current_architecture))
4709 {
4710 buffer_address[4] = 0x60; /* Put in bral (0x60ff). */
4711 buffer_address[5] = (char) 0xff;
4712 }
4713 else
4714 {
4715 buffer_address[4] = 0x4e; /* Put in jmp long (0x4ef9). */
4716 buffer_address[5] = (char) 0xf9;
4717 }
4718 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4719 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4720 fragP->fr_offset, HAVE_LONG_BRANCH (current_architecture),
4721 NO_RELOC);
4722 fragP->fr_fix += 4;
4723 }
4724
4725 frag_wane (fragP);
4726 break;
4727 } /* case TAB(DBCC,SZ_UNDEF) */
4728
4729 case TAB (PCLEA, SZ_UNDEF):
4730 {
4731 if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4732 && relaxable_symbol (fragP->fr_symbol))
4733 || flag_short_refs
4734 || cpu_of_arch (current_architecture) < m68020
4735 || cpu_of_arch (current_architecture) == mcf5200)
4736 {
4737 fragP->fr_subtype = TAB (PCLEA, SHORT);
4738 fragP->fr_var += 2;
4739 }
4740 else
4741 {
4742 fragP->fr_subtype = TAB (PCLEA, LONG);
4743 fragP->fr_var += 6;
4744 }
4745 break;
4746 } /* TAB(PCLEA,SZ_UNDEF) */
4747
4748 case TAB (PCINDEX, SZ_UNDEF):
4749 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4750 && relaxable_symbol (fragP->fr_symbol))
4751 || cpu_of_arch (current_architecture) < m68020
4752 || cpu_of_arch (current_architecture) == mcf5200)
4753 {
4754 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4755 }
4756 else
4757 {
4758 fragP->fr_subtype = TAB (PCINDEX, LONG);
4759 fragP->fr_var += 4;
4760 }
4761 break;
4762
4763 default:
4764 break;
4765 }
4766
4767 /* now that SZ_UNDEF are taken care of, check others */
4768 switch (fragP->fr_subtype)
4769 {
4770 case TAB (BCC68000, BYTE):
4771 case TAB (ABRANCH, BYTE):
4772 /* We can't do a short jump to the next instruction, so in that
4773 case we force word mode. At this point S_GET_VALUE should
4774 return the offset of the symbol within its frag. If the
4775 symbol is at the start of a frag, and it is the next frag
4776 with any data in it (usually this is just the next frag, but
4777 assembler listings may introduce empty frags), we must use
4778 word mode. */
4779 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4780 {
4781 fragS *stop;
4782 fragS *l;
4783
4784 stop = symbol_get_frag (fragP->fr_symbol);
4785 for (l = fragP->fr_next; l != stop; l = l->fr_next)
4786 if (l->fr_fix + l->fr_var != 0)
4787 break;
4788 if (l == stop)
4789 {
4790 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4791 fragP->fr_var += 2;
4792 }
4793 }
4794 break;
4795 default:
4796 break;
4797 }
4798 return fragP->fr_var + fragP->fr_fix - old_fix;
4799 }
4800
4801 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4802 /* the bit-field entries in the relocation_info struct plays hell
4803 with the byte-order problems of cross-assembly. So as a hack,
4804 I added this mach. dependent ri twiddler. Ugly, but it gets
4805 you there. -KWK */
4806 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4807 are symbolnum, most sig. byte first. Last byte is broken up with
4808 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4809 nibble as nuthin. (on Sun 3 at least) */
4810 /* Translate the internal relocation information into target-specific
4811 format. */
4812 #ifdef comment
4813 void
4814 md_ri_to_chars (the_bytes, ri)
4815 char *the_bytes;
4816 struct reloc_info_generic *ri;
4817 {
4818 /* this is easy */
4819 md_number_to_chars (the_bytes, ri->r_address, 4);
4820 /* now the fun stuff */
4821 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4822 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4823 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4824 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4825 ((ri->r_extern << 4) & 0x10));
4826 }
4827
4828 #endif /* comment */
4829
4830 #ifndef BFD_ASSEMBLER
4831 void
4832 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4833 char *where;
4834 fixS *fixP;
4835 relax_addressT segment_address_in_file;
4836 {
4837 /*
4838 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4839 * Out: GNU LD relocation length code: 0, 1, or 2.
4840 */
4841
4842 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4843 long r_symbolnum;
4844
4845 know (fixP->fx_addsy != NULL);
4846
4847 md_number_to_chars (where,
4848 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4849 4);
4850
4851 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4852 ? S_GET_TYPE (fixP->fx_addsy)
4853 : fixP->fx_addsy->sy_number);
4854
4855 where[4] = (r_symbolnum >> 16) & 0x0ff;
4856 where[5] = (r_symbolnum >> 8) & 0x0ff;
4857 where[6] = r_symbolnum & 0x0ff;
4858 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4859 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4860 }
4861 #endif
4862
4863 #endif /* OBJ_AOUT or OBJ_BOUT */
4864
4865 #ifndef WORKING_DOT_WORD
4866 CONST int md_short_jump_size = 4;
4867 CONST int md_long_jump_size = 6;
4868
4869 void
4870 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4871 char *ptr;
4872 addressT from_addr, to_addr;
4873 fragS *frag ATTRIBUTE_UNUSED;
4874 symbolS *to_symbol ATTRIBUTE_UNUSED;
4875 {
4876 valueT offset;
4877
4878 offset = to_addr - (from_addr + 2);
4879
4880 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4881 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4882 }
4883
4884 void
4885 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4886 char *ptr;
4887 addressT from_addr, to_addr;
4888 fragS *frag;
4889 symbolS *to_symbol;
4890 {
4891 valueT offset;
4892
4893 if (!HAVE_LONG_BRANCH(current_architecture))
4894 {
4895 offset = to_addr - S_GET_VALUE (to_symbol);
4896 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4897 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4898 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4899 0, NO_RELOC);
4900 }
4901 else
4902 {
4903 offset = to_addr - (from_addr + 2);
4904 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4905 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4906 }
4907 }
4908
4909 #endif
4910
4911 /* Different values of OK tell what its OK to return. Things that
4912 aren't OK are an error (what a shock, no?)
4913
4914 0: Everything is OK
4915 10: Absolute 1:8 only
4916 20: Absolute 0:7 only
4917 30: absolute 0:15 only
4918 40: Absolute 0:31 only
4919 50: absolute 0:127 only
4920 55: absolute -64:63 only
4921 60: absolute -128:127 only
4922 70: absolute 0:4095 only
4923 80: No bignums
4924
4925 */
4926
4927 static int
4928 get_num (exp, ok)
4929 struct m68k_exp *exp;
4930 int ok;
4931 {
4932 if (exp->exp.X_op == O_absent)
4933 {
4934 /* Do the same thing the VAX asm does */
4935 op (exp) = O_constant;
4936 adds (exp) = 0;
4937 subs (exp) = 0;
4938 offs (exp) = 0;
4939 if (ok == 10)
4940 {
4941 as_warn (_("expression out of range: defaulting to 1"));
4942 offs (exp) = 1;
4943 }
4944 }
4945 else if (exp->exp.X_op == O_constant)
4946 {
4947 switch (ok)
4948 {
4949 case 10:
4950 if (offs (exp) < 1 || offs (exp) > 8)
4951 {
4952 as_warn (_("expression out of range: defaulting to 1"));
4953 offs (exp) = 1;
4954 }
4955 break;
4956 case 20:
4957 if (offs (exp) < 0 || offs (exp) > 7)
4958 goto outrange;
4959 break;
4960 case 30:
4961 if (offs (exp) < 0 || offs (exp) > 15)
4962 goto outrange;
4963 break;
4964 case 40:
4965 if (offs (exp) < 0 || offs (exp) > 32)
4966 goto outrange;
4967 break;
4968 case 50:
4969 if (offs (exp) < 0 || offs (exp) > 127)
4970 goto outrange;
4971 break;
4972 case 55:
4973 if (offs (exp) < -64 || offs (exp) > 63)
4974 goto outrange;
4975 break;
4976 case 60:
4977 if (offs (exp) < -128 || offs (exp) > 127)
4978 goto outrange;
4979 break;
4980 case 70:
4981 if (offs (exp) < 0 || offs (exp) > 4095)
4982 {
4983 outrange:
4984 as_warn (_("expression out of range: defaulting to 0"));
4985 offs (exp) = 0;
4986 }
4987 break;
4988 default:
4989 break;
4990 }
4991 }
4992 else if (exp->exp.X_op == O_big)
4993 {
4994 if (offs (exp) <= 0 /* flonum */
4995 && (ok == 80 /* no bignums */
4996 || (ok > 10 /* small-int ranges including 0 ok */
4997 /* If we have a flonum zero, a zero integer should
4998 do as well (e.g., in moveq). */
4999 && generic_floating_point_number.exponent == 0
5000 && generic_floating_point_number.low[0] == 0)))
5001 {
5002 /* HACK! Turn it into a long */
5003 LITTLENUM_TYPE words[6];
5004
5005 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5006 op (exp) = O_constant;
5007 adds (exp) = 0;
5008 subs (exp) = 0;
5009 offs (exp) = words[1] | (words[0] << 16);
5010 }
5011 else if (ok != 0)
5012 {
5013 op (exp) = O_constant;
5014 adds (exp) = 0;
5015 subs (exp) = 0;
5016 offs (exp) = (ok == 10) ? 1 : 0;
5017 as_warn (_("Can't deal with expression; defaulting to %ld"),
5018 offs (exp));
5019 }
5020 }
5021 else
5022 {
5023 if (ok >= 10 && ok <= 70)
5024 {
5025 op (exp) = O_constant;
5026 adds (exp) = 0;
5027 subs (exp) = 0;
5028 offs (exp) = (ok == 10) ? 1 : 0;
5029 as_warn (_("Can't deal with expression; defaulting to %ld"),
5030 offs (exp));
5031 }
5032 }
5033
5034 if (exp->size != SIZE_UNSPEC)
5035 {
5036 switch (exp->size)
5037 {
5038 case SIZE_UNSPEC:
5039 case SIZE_LONG:
5040 break;
5041 case SIZE_BYTE:
5042 if (!isbyte (offs (exp)))
5043 as_warn (_("expression doesn't fit in BYTE"));
5044 break;
5045 case SIZE_WORD:
5046 if (!isword (offs (exp)))
5047 as_warn (_("expression doesn't fit in WORD"));
5048 break;
5049 }
5050 }
5051
5052 return offs (exp);
5053 }
5054
5055 /* These are the back-ends for the various machine dependent pseudo-ops. */
5056
5057 static void
5058 s_data1 (ignore)
5059 int ignore ATTRIBUTE_UNUSED;
5060 {
5061 subseg_set (data_section, 1);
5062 demand_empty_rest_of_line ();
5063 }
5064
5065 static void
5066 s_data2 (ignore)
5067 int ignore ATTRIBUTE_UNUSED;
5068 {
5069 subseg_set (data_section, 2);
5070 demand_empty_rest_of_line ();
5071 }
5072
5073 static void
5074 s_bss (ignore)
5075 int ignore ATTRIBUTE_UNUSED;
5076 {
5077 /* We don't support putting frags in the BSS segment, we fake it
5078 by marking in_bss, then looking at s_skip for clues. */
5079
5080 subseg_set (bss_section, 0);
5081 demand_empty_rest_of_line ();
5082 }
5083
5084 static void
5085 s_even (ignore)
5086 int ignore ATTRIBUTE_UNUSED;
5087 {
5088 register int temp;
5089 register long temp_fill;
5090
5091 temp = 1; /* JF should be 2? */
5092 temp_fill = get_absolute_expression ();
5093 if (!need_pass_2) /* Never make frag if expect extra pass. */
5094 frag_align (temp, (int) temp_fill, 0);
5095 demand_empty_rest_of_line ();
5096 record_alignment (now_seg, temp);
5097 }
5098
5099 static void
5100 s_proc (ignore)
5101 int ignore ATTRIBUTE_UNUSED;
5102 {
5103 demand_empty_rest_of_line ();
5104 }
5105 \f
5106 /* Pseudo-ops handled for MRI compatibility. */
5107
5108 /* This function returns non-zero if the argument is a conditional
5109 pseudo-op. This is called when checking whether a pending
5110 alignment is needed. */
5111
5112 int
5113 m68k_conditional_pseudoop (pop)
5114 pseudo_typeS *pop;
5115 {
5116 return (pop->poc_handler == s_mri_if
5117 || pop->poc_handler == s_mri_else);
5118 }
5119
5120 /* Handle an MRI style chip specification. */
5121
5122 static void
5123 mri_chip ()
5124 {
5125 char *s;
5126 char c;
5127 int i;
5128
5129 s = input_line_pointer;
5130 /* We can't use get_symbol_end since the processor names are not proper
5131 symbols. */
5132 while (is_part_of_name (c = *input_line_pointer++))
5133 ;
5134 *--input_line_pointer = 0;
5135 for (i = 0; i < n_archs; i++)
5136 if (strcasecmp (s, archs[i].name) == 0)
5137 break;
5138 if (i >= n_archs)
5139 {
5140 as_bad (_("%s: unrecognized processor name"), s);
5141 *input_line_pointer = c;
5142 ignore_rest_of_line ();
5143 return;
5144 }
5145 *input_line_pointer = c;
5146
5147 if (*input_line_pointer == '/')
5148 current_architecture = 0;
5149 else
5150 current_architecture &= m68881 | m68851;
5151 current_architecture |= archs[i].arch;
5152
5153 while (*input_line_pointer == '/')
5154 {
5155 ++input_line_pointer;
5156 s = input_line_pointer;
5157 /* We can't use get_symbol_end since the processor names are not
5158 proper symbols. */
5159 while (is_part_of_name (c = *input_line_pointer++))
5160 ;
5161 *--input_line_pointer = 0;
5162 if (strcmp (s, "68881") == 0)
5163 current_architecture |= m68881;
5164 else if (strcmp (s, "68851") == 0)
5165 current_architecture |= m68851;
5166 *input_line_pointer = c;
5167 }
5168
5169 /* Update info about available control registers. */
5170 select_control_regs ();
5171 }
5172
5173 /* The MRI CHIP pseudo-op. */
5174
5175 static void
5176 s_chip (ignore)
5177 int ignore ATTRIBUTE_UNUSED;
5178 {
5179 char *stop = NULL;
5180 char stopc;
5181
5182 if (flag_mri)
5183 stop = mri_comment_field (&stopc);
5184 mri_chip ();
5185 if (flag_mri)
5186 mri_comment_end (stop, stopc);
5187 demand_empty_rest_of_line ();
5188 }
5189
5190 /* The MRI FOPT pseudo-op. */
5191
5192 static void
5193 s_fopt (ignore)
5194 int ignore ATTRIBUTE_UNUSED;
5195 {
5196 SKIP_WHITESPACE ();
5197
5198 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5199 {
5200 int temp;
5201
5202 input_line_pointer += 3;
5203 temp = get_absolute_expression ();
5204 if (temp < 0 || temp > 7)
5205 as_bad (_("bad coprocessor id"));
5206 else
5207 m68k_float_copnum = COP0 + temp;
5208 }
5209 else
5210 {
5211 as_bad (_("unrecognized fopt option"));
5212 ignore_rest_of_line ();
5213 return;
5214 }
5215
5216 demand_empty_rest_of_line ();
5217 }
5218
5219 /* The structure used to handle the MRI OPT pseudo-op. */
5220
5221 struct opt_action
5222 {
5223 /* The name of the option. */
5224 const char *name;
5225
5226 /* If this is not NULL, just call this function. The first argument
5227 is the ARG field of this structure, the second argument is
5228 whether the option was negated. */
5229 void (*pfn) PARAMS ((int arg, int on));
5230
5231 /* If this is not NULL, and the PFN field is NULL, set the variable
5232 this points to. Set it to the ARG field if the option was not
5233 negated, and the NOTARG field otherwise. */
5234 int *pvar;
5235
5236 /* The value to pass to PFN or to assign to *PVAR. */
5237 int arg;
5238
5239 /* The value to assign to *PVAR if the option is negated. If PFN is
5240 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5241 the option may not be negated. */
5242 int notarg;
5243 };
5244
5245 /* The table used to handle the MRI OPT pseudo-op. */
5246
5247 static void skip_to_comma PARAMS ((int, int));
5248 static void opt_nest PARAMS ((int, int));
5249 static void opt_chip PARAMS ((int, int));
5250 static void opt_list PARAMS ((int, int));
5251 static void opt_list_symbols PARAMS ((int, int));
5252
5253 static const struct opt_action opt_table[] =
5254 {
5255 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5256
5257 /* We do relaxing, so there is little use for these options. */
5258 { "b", 0, 0, 0, 0 },
5259 { "brs", 0, 0, 0, 0 },
5260 { "brb", 0, 0, 0, 0 },
5261 { "brl", 0, 0, 0, 0 },
5262 { "brw", 0, 0, 0, 0 },
5263
5264 { "c", 0, 0, 0, 0 },
5265 { "cex", 0, 0, 0, 0 },
5266 { "case", 0, &symbols_case_sensitive, 1, 0 },
5267 { "cl", 0, 0, 0, 0 },
5268 { "cre", 0, 0, 0, 0 },
5269 { "d", 0, &flag_keep_locals, 1, 0 },
5270 { "e", 0, 0, 0, 0 },
5271 { "f", 0, &flag_short_refs, 1, 0 },
5272 { "frs", 0, &flag_short_refs, 1, 0 },
5273 { "frl", 0, &flag_short_refs, 0, 1 },
5274 { "g", 0, 0, 0, 0 },
5275 { "i", 0, 0, 0, 0 },
5276 { "m", 0, 0, 0, 0 },
5277 { "mex", 0, 0, 0, 0 },
5278 { "mc", 0, 0, 0, 0 },
5279 { "md", 0, 0, 0, 0 },
5280 { "nest", opt_nest, 0, 0, 0 },
5281 { "next", skip_to_comma, 0, 0, 0 },
5282 { "o", 0, 0, 0, 0 },
5283 { "old", 0, 0, 0, 0 },
5284 { "op", skip_to_comma, 0, 0, 0 },
5285 { "pco", 0, 0, 0, 0 },
5286 { "p", opt_chip, 0, 0, 0 },
5287 { "pcr", 0, 0, 0, 0 },
5288 { "pcs", 0, 0, 0, 0 },
5289 { "r", 0, 0, 0, 0 },
5290 { "quick", 0, &m68k_quick, 1, 0 },
5291 { "rel32", 0, &m68k_rel32, 1, 0 },
5292 { "s", opt_list, 0, 0, 0 },
5293 { "t", opt_list_symbols, 0, 0, 0 },
5294 { "w", 0, &flag_no_warnings, 0, 1 },
5295 { "x", 0, 0, 0, 0 }
5296 };
5297
5298 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5299
5300 /* The MRI OPT pseudo-op. */
5301
5302 static void
5303 s_opt (ignore)
5304 int ignore ATTRIBUTE_UNUSED;
5305 {
5306 do
5307 {
5308 int t;
5309 char *s;
5310 char c;
5311 int i;
5312 const struct opt_action *o;
5313
5314 SKIP_WHITESPACE ();
5315
5316 t = 1;
5317 if (*input_line_pointer == '-')
5318 {
5319 ++input_line_pointer;
5320 t = 0;
5321 }
5322 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5323 {
5324 input_line_pointer += 2;
5325 t = 0;
5326 }
5327
5328 s = input_line_pointer;
5329 c = get_symbol_end ();
5330
5331 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5332 {
5333 if (strcasecmp (s, o->name) == 0)
5334 {
5335 if (o->pfn)
5336 {
5337 /* Restore input_line_pointer now in case the option
5338 takes arguments. */
5339 *input_line_pointer = c;
5340 (*o->pfn) (o->arg, t);
5341 }
5342 else if (o->pvar != NULL)
5343 {
5344 if (! t && o->arg == o->notarg)
5345 as_bad (_("option `%s' may not be negated"), s);
5346 *input_line_pointer = c;
5347 *o->pvar = t ? o->arg : o->notarg;
5348 }
5349 else
5350 *input_line_pointer = c;
5351 break;
5352 }
5353 }
5354 if (i >= OPTCOUNT)
5355 {
5356 as_bad (_("option `%s' not recognized"), s);
5357 *input_line_pointer = c;
5358 }
5359 }
5360 while (*input_line_pointer++ == ',');
5361
5362 /* Move back to terminating character. */
5363 --input_line_pointer;
5364 demand_empty_rest_of_line ();
5365 }
5366
5367 /* Skip ahead to a comma. This is used for OPT options which we do
5368 not suppor tand which take arguments. */
5369
5370 static void
5371 skip_to_comma (arg, on)
5372 int arg ATTRIBUTE_UNUSED;
5373 int on ATTRIBUTE_UNUSED;
5374 {
5375 while (*input_line_pointer != ','
5376 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5377 ++input_line_pointer;
5378 }
5379
5380 /* Handle the OPT NEST=depth option. */
5381
5382 static void
5383 opt_nest (arg, on)
5384 int arg ATTRIBUTE_UNUSED;
5385 int on ATTRIBUTE_UNUSED;
5386 {
5387 if (*input_line_pointer != '=')
5388 {
5389 as_bad (_("bad format of OPT NEST=depth"));
5390 return;
5391 }
5392
5393 ++input_line_pointer;
5394 max_macro_nest = get_absolute_expression ();
5395 }
5396
5397 /* Handle the OPT P=chip option. */
5398
5399 static void
5400 opt_chip (arg, on)
5401 int arg ATTRIBUTE_UNUSED;
5402 int on ATTRIBUTE_UNUSED;
5403 {
5404 if (*input_line_pointer != '=')
5405 {
5406 /* This is just OPT P, which we do not support. */
5407 return;
5408 }
5409
5410 ++input_line_pointer;
5411 mri_chip ();
5412 }
5413
5414 /* Handle the OPT S option. */
5415
5416 static void
5417 opt_list (arg, on)
5418 int arg ATTRIBUTE_UNUSED;
5419 int on;
5420 {
5421 listing_list (on);
5422 }
5423
5424 /* Handle the OPT T option. */
5425
5426 static void
5427 opt_list_symbols (arg, on)
5428 int arg ATTRIBUTE_UNUSED;
5429 int on;
5430 {
5431 if (on)
5432 listing |= LISTING_SYMBOLS;
5433 else
5434 listing &=~ LISTING_SYMBOLS;
5435 }
5436
5437 /* Handle the MRI REG pseudo-op. */
5438
5439 static void
5440 s_reg (ignore)
5441 int ignore ATTRIBUTE_UNUSED;
5442 {
5443 char *s;
5444 int c;
5445 struct m68k_op rop;
5446 int mask;
5447 char *stop = NULL;
5448 char stopc;
5449
5450 if (line_label == NULL)
5451 {
5452 as_bad (_("missing label"));
5453 ignore_rest_of_line ();
5454 return;
5455 }
5456
5457 if (flag_mri)
5458 stop = mri_comment_field (&stopc);
5459
5460 SKIP_WHITESPACE ();
5461
5462 s = input_line_pointer;
5463 while (isalnum ((unsigned char) *input_line_pointer)
5464 #ifdef REGISTER_PREFIX
5465 || *input_line_pointer == REGISTER_PREFIX
5466 #endif
5467 || *input_line_pointer == '/'
5468 || *input_line_pointer == '-')
5469 ++input_line_pointer;
5470 c = *input_line_pointer;
5471 *input_line_pointer = '\0';
5472
5473 if (m68k_ip_op (s, &rop) != 0)
5474 {
5475 if (rop.error == NULL)
5476 as_bad (_("bad register list"));
5477 else
5478 as_bad (_("bad register list: %s"), rop.error);
5479 *input_line_pointer = c;
5480 ignore_rest_of_line ();
5481 return;
5482 }
5483
5484 *input_line_pointer = c;
5485
5486 if (rop.mode == REGLST)
5487 mask = rop.mask;
5488 else if (rop.mode == DREG)
5489 mask = 1 << (rop.reg - DATA0);
5490 else if (rop.mode == AREG)
5491 mask = 1 << (rop.reg - ADDR0 + 8);
5492 else if (rop.mode == FPREG)
5493 mask = 1 << (rop.reg - FP0 + 16);
5494 else if (rop.mode == CONTROL
5495 && rop.reg == FPI)
5496 mask = 1 << 24;
5497 else if (rop.mode == CONTROL
5498 && rop.reg == FPS)
5499 mask = 1 << 25;
5500 else if (rop.mode == CONTROL
5501 && rop.reg == FPC)
5502 mask = 1 << 26;
5503 else
5504 {
5505 as_bad (_("bad register list"));
5506 ignore_rest_of_line ();
5507 return;
5508 }
5509
5510 S_SET_SEGMENT (line_label, reg_section);
5511 S_SET_VALUE (line_label, ~mask);
5512 symbol_set_frag (line_label, &zero_address_frag);
5513
5514 if (flag_mri)
5515 mri_comment_end (stop, stopc);
5516
5517 demand_empty_rest_of_line ();
5518 }
5519
5520 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5521
5522 struct save_opts
5523 {
5524 struct save_opts *next;
5525 int abspcadd;
5526 int symbols_case_sensitive;
5527 int keep_locals;
5528 int short_refs;
5529 int architecture;
5530 int quick;
5531 int rel32;
5532 int listing;
5533 int no_warnings;
5534 /* FIXME: We don't save OPT S. */
5535 };
5536
5537 /* This variable holds the stack of saved options. */
5538
5539 static struct save_opts *save_stack;
5540
5541 /* The MRI SAVE pseudo-op. */
5542
5543 static void
5544 s_save (ignore)
5545 int ignore ATTRIBUTE_UNUSED;
5546 {
5547 struct save_opts *s;
5548
5549 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5550 s->abspcadd = m68k_abspcadd;
5551 s->symbols_case_sensitive = symbols_case_sensitive;
5552 s->keep_locals = flag_keep_locals;
5553 s->short_refs = flag_short_refs;
5554 s->architecture = current_architecture;
5555 s->quick = m68k_quick;
5556 s->rel32 = m68k_rel32;
5557 s->listing = listing;
5558 s->no_warnings = flag_no_warnings;
5559
5560 s->next = save_stack;
5561 save_stack = s;
5562
5563 demand_empty_rest_of_line ();
5564 }
5565
5566 /* The MRI RESTORE pseudo-op. */
5567
5568 static void
5569 s_restore (ignore)
5570 int ignore ATTRIBUTE_UNUSED;
5571 {
5572 struct save_opts *s;
5573
5574 if (save_stack == NULL)
5575 {
5576 as_bad (_("restore without save"));
5577 ignore_rest_of_line ();
5578 return;
5579 }
5580
5581 s = save_stack;
5582 save_stack = s->next;
5583
5584 m68k_abspcadd = s->abspcadd;
5585 symbols_case_sensitive = s->symbols_case_sensitive;
5586 flag_keep_locals = s->keep_locals;
5587 flag_short_refs = s->short_refs;
5588 current_architecture = s->architecture;
5589 m68k_quick = s->quick;
5590 m68k_rel32 = s->rel32;
5591 listing = s->listing;
5592 flag_no_warnings = s->no_warnings;
5593
5594 free (s);
5595
5596 demand_empty_rest_of_line ();
5597 }
5598
5599 /* Types of MRI structured control directives. */
5600
5601 enum mri_control_type
5602 {
5603 mri_for,
5604 mri_if,
5605 mri_repeat,
5606 mri_while
5607 };
5608
5609 /* This structure is used to stack the MRI structured control
5610 directives. */
5611
5612 struct mri_control_info
5613 {
5614 /* The directive within which this one is enclosed. */
5615 struct mri_control_info *outer;
5616
5617 /* The type of directive. */
5618 enum mri_control_type type;
5619
5620 /* Whether an ELSE has been in an IF. */
5621 int else_seen;
5622
5623 /* The add or sub statement at the end of a FOR. */
5624 char *incr;
5625
5626 /* The label of the top of a FOR or REPEAT loop. */
5627 char *top;
5628
5629 /* The label to jump to for the next iteration, or the else
5630 expression of a conditional. */
5631 char *next;
5632
5633 /* The label to jump to to break out of the loop, or the label past
5634 the end of a conditional. */
5635 char *bottom;
5636 };
5637
5638 /* The stack of MRI structured control directives. */
5639
5640 static struct mri_control_info *mri_control_stack;
5641
5642 /* The current MRI structured control directive index number, used to
5643 generate label names. */
5644
5645 static int mri_control_index;
5646
5647 /* Some function prototypes. */
5648
5649 static void mri_assemble PARAMS ((char *));
5650 static char *mri_control_label PARAMS ((void));
5651 static struct mri_control_info *push_mri_control
5652 PARAMS ((enum mri_control_type));
5653 static void pop_mri_control PARAMS ((void));
5654 static int parse_mri_condition PARAMS ((int *));
5655 static int parse_mri_control_operand
5656 PARAMS ((int *, char **, char **, char **, char **));
5657 static int swap_mri_condition PARAMS ((int));
5658 static int reverse_mri_condition PARAMS ((int));
5659 static void build_mri_control_operand
5660 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5661 const char *, int));
5662 static void parse_mri_control_expression
5663 PARAMS ((char *, int, const char *, const char *, int));
5664
5665 /* Assemble an instruction for an MRI structured control directive. */
5666
5667 static void
5668 mri_assemble (str)
5669 char *str;
5670 {
5671 char *s;
5672
5673 /* md_assemble expects the opcode to be in lower case. */
5674 for (s = str; *s != ' ' && *s != '\0'; s++)
5675 {
5676 if (isupper ((unsigned char) *s))
5677 *s = tolower ((unsigned char) *s);
5678 }
5679
5680 md_assemble (str);
5681 }
5682
5683 /* Generate a new MRI label structured control directive label name. */
5684
5685 static char *
5686 mri_control_label ()
5687 {
5688 char *n;
5689
5690 n = (char *) xmalloc (20);
5691 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5692 ++mri_control_index;
5693 return n;
5694 }
5695
5696 /* Create a new MRI structured control directive. */
5697
5698 static struct mri_control_info *
5699 push_mri_control (type)
5700 enum mri_control_type type;
5701 {
5702 struct mri_control_info *n;
5703
5704 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5705
5706 n->type = type;
5707 n->else_seen = 0;
5708 if (type == mri_if || type == mri_while)
5709 n->top = NULL;
5710 else
5711 n->top = mri_control_label ();
5712 n->next = mri_control_label ();
5713 n->bottom = mri_control_label ();
5714
5715 n->outer = mri_control_stack;
5716 mri_control_stack = n;
5717
5718 return n;
5719 }
5720
5721 /* Pop off the stack of MRI structured control directives. */
5722
5723 static void
5724 pop_mri_control ()
5725 {
5726 struct mri_control_info *n;
5727
5728 n = mri_control_stack;
5729 mri_control_stack = n->outer;
5730 if (n->top != NULL)
5731 free (n->top);
5732 free (n->next);
5733 free (n->bottom);
5734 free (n);
5735 }
5736
5737 /* Recognize a condition code in an MRI structured control expression. */
5738
5739 static int
5740 parse_mri_condition (pcc)
5741 int *pcc;
5742 {
5743 char c1, c2;
5744
5745 know (*input_line_pointer == '<');
5746
5747 ++input_line_pointer;
5748 c1 = *input_line_pointer++;
5749 c2 = *input_line_pointer++;
5750
5751 if (*input_line_pointer != '>')
5752 {
5753 as_bad (_("syntax error in structured control directive"));
5754 return 0;
5755 }
5756
5757 ++input_line_pointer;
5758 SKIP_WHITESPACE ();
5759
5760 if (isupper (c1))
5761 c1 = tolower (c1);
5762 if (isupper (c2))
5763 c2 = tolower (c2);
5764
5765 *pcc = (c1 << 8) | c2;
5766
5767 return 1;
5768 }
5769
5770 /* Parse a single operand in an MRI structured control expression. */
5771
5772 static int
5773 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5774 int *pcc;
5775 char **leftstart;
5776 char **leftstop;
5777 char **rightstart;
5778 char **rightstop;
5779 {
5780 char *s;
5781
5782 SKIP_WHITESPACE ();
5783
5784 *pcc = -1;
5785 *leftstart = NULL;
5786 *leftstop = NULL;
5787 *rightstart = NULL;
5788 *rightstop = NULL;
5789
5790 if (*input_line_pointer == '<')
5791 {
5792 /* It's just a condition code. */
5793 return parse_mri_condition (pcc);
5794 }
5795
5796 /* Look ahead for the condition code. */
5797 for (s = input_line_pointer; *s != '\0'; ++s)
5798 {
5799 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5800 break;
5801 }
5802 if (*s == '\0')
5803 {
5804 as_bad (_("missing condition code in structured control directive"));
5805 return 0;
5806 }
5807
5808 *leftstart = input_line_pointer;
5809 *leftstop = s;
5810 if (*leftstop > *leftstart
5811 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5812 --*leftstop;
5813
5814 input_line_pointer = s;
5815 if (! parse_mri_condition (pcc))
5816 return 0;
5817
5818 /* Look ahead for AND or OR or end of line. */
5819 for (s = input_line_pointer; *s != '\0'; ++s)
5820 {
5821 if ((strncasecmp (s, "AND", 3) == 0
5822 && (s[3] == '.' || ! is_part_of_name (s[3])))
5823 || (strncasecmp (s, "OR", 2) == 0
5824 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5825 break;
5826 }
5827
5828 *rightstart = input_line_pointer;
5829 *rightstop = s;
5830 if (*rightstop > *rightstart
5831 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5832 --*rightstop;
5833
5834 input_line_pointer = s;
5835
5836 return 1;
5837 }
5838
5839 #define MCC(b1, b2) (((b1) << 8) | (b2))
5840
5841 /* Swap the sense of a condition. This changes the condition so that
5842 it generates the same result when the operands are swapped. */
5843
5844 static int
5845 swap_mri_condition (cc)
5846 int cc;
5847 {
5848 switch (cc)
5849 {
5850 case MCC ('h', 'i'): return MCC ('c', 's');
5851 case MCC ('l', 's'): return MCC ('c', 'c');
5852 case MCC ('c', 'c'): return MCC ('l', 's');
5853 case MCC ('c', 's'): return MCC ('h', 'i');
5854 case MCC ('p', 'l'): return MCC ('m', 'i');
5855 case MCC ('m', 'i'): return MCC ('p', 'l');
5856 case MCC ('g', 'e'): return MCC ('l', 'e');
5857 case MCC ('l', 't'): return MCC ('g', 't');
5858 case MCC ('g', 't'): return MCC ('l', 't');
5859 case MCC ('l', 'e'): return MCC ('g', 'e');
5860 }
5861 return cc;
5862 }
5863
5864 /* Reverse the sense of a condition. */
5865
5866 static int
5867 reverse_mri_condition (cc)
5868 int cc;
5869 {
5870 switch (cc)
5871 {
5872 case MCC ('h', 'i'): return MCC ('l', 's');
5873 case MCC ('l', 's'): return MCC ('h', 'i');
5874 case MCC ('c', 'c'): return MCC ('c', 's');
5875 case MCC ('c', 's'): return MCC ('c', 'c');
5876 case MCC ('n', 'e'): return MCC ('e', 'q');
5877 case MCC ('e', 'q'): return MCC ('n', 'e');
5878 case MCC ('v', 'c'): return MCC ('v', 's');
5879 case MCC ('v', 's'): return MCC ('v', 'c');
5880 case MCC ('p', 'l'): return MCC ('m', 'i');
5881 case MCC ('m', 'i'): return MCC ('p', 'l');
5882 case MCC ('g', 'e'): return MCC ('l', 't');
5883 case MCC ('l', 't'): return MCC ('g', 'e');
5884 case MCC ('g', 't'): return MCC ('l', 'e');
5885 case MCC ('l', 'e'): return MCC ('g', 't');
5886 }
5887 return cc;
5888 }
5889
5890 /* Build an MRI structured control expression. This generates test
5891 and branch instructions. It goes to TRUELAB if the condition is
5892 true, and to FALSELAB if the condition is false. Exactly one of
5893 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5894 is the size qualifier for the expression. EXTENT is the size to
5895 use for the branch. */
5896
5897 static void
5898 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5899 rightstop, truelab, falselab, extent)
5900 int qual;
5901 int cc;
5902 char *leftstart;
5903 char *leftstop;
5904 char *rightstart;
5905 char *rightstop;
5906 const char *truelab;
5907 const char *falselab;
5908 int extent;
5909 {
5910 char *buf;
5911 char *s;
5912
5913 if (leftstart != NULL)
5914 {
5915 struct m68k_op leftop, rightop;
5916 char c;
5917
5918 /* Swap the compare operands, if necessary, to produce a legal
5919 m68k compare instruction. Comparing a register operand with
5920 a non-register operand requires the register to be on the
5921 right (cmp, cmpa). Comparing an immediate value with
5922 anything requires the immediate value to be on the left
5923 (cmpi). */
5924
5925 c = *leftstop;
5926 *leftstop = '\0';
5927 (void) m68k_ip_op (leftstart, &leftop);
5928 *leftstop = c;
5929
5930 c = *rightstop;
5931 *rightstop = '\0';
5932 (void) m68k_ip_op (rightstart, &rightop);
5933 *rightstop = c;
5934
5935 if (rightop.mode == IMMED
5936 || ((leftop.mode == DREG || leftop.mode == AREG)
5937 && (rightop.mode != DREG && rightop.mode != AREG)))
5938 {
5939 char *temp;
5940
5941 cc = swap_mri_condition (cc);
5942 temp = leftstart;
5943 leftstart = rightstart;
5944 rightstart = temp;
5945 temp = leftstop;
5946 leftstop = rightstop;
5947 rightstop = temp;
5948 }
5949 }
5950
5951 if (truelab == NULL)
5952 {
5953 cc = reverse_mri_condition (cc);
5954 truelab = falselab;
5955 }
5956
5957 if (leftstart != NULL)
5958 {
5959 buf = (char *) xmalloc (20
5960 + (leftstop - leftstart)
5961 + (rightstop - rightstart));
5962 s = buf;
5963 *s++ = 'c';
5964 *s++ = 'm';
5965 *s++ = 'p';
5966 if (qual != '\0')
5967 *s++ = qual;
5968 *s++ = ' ';
5969 memcpy (s, leftstart, leftstop - leftstart);
5970 s += leftstop - leftstart;
5971 *s++ = ',';
5972 memcpy (s, rightstart, rightstop - rightstart);
5973 s += rightstop - rightstart;
5974 *s = '\0';
5975 mri_assemble (buf);
5976 free (buf);
5977 }
5978
5979 buf = (char *) xmalloc (20 + strlen (truelab));
5980 s = buf;
5981 *s++ = 'b';
5982 *s++ = cc >> 8;
5983 *s++ = cc & 0xff;
5984 if (extent != '\0')
5985 *s++ = extent;
5986 *s++ = ' ';
5987 strcpy (s, truelab);
5988 mri_assemble (buf);
5989 free (buf);
5990 }
5991
5992 /* Parse an MRI structured control expression. This generates test
5993 and branch instructions. STOP is where the expression ends. It
5994 goes to TRUELAB if the condition is true, and to FALSELAB if the
5995 condition is false. Exactly one of TRUELAB and FALSELAB will be
5996 NULL, meaning to fall through. QUAL is the size qualifier for the
5997 expression. EXTENT is the size to use for the branch. */
5998
5999 static void
6000 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
6001 char *stop;
6002 int qual;
6003 const char *truelab;
6004 const char *falselab;
6005 int extent;
6006 {
6007 int c;
6008 int cc;
6009 char *leftstart;
6010 char *leftstop;
6011 char *rightstart;
6012 char *rightstop;
6013
6014 c = *stop;
6015 *stop = '\0';
6016
6017 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6018 &rightstart, &rightstop))
6019 {
6020 *stop = c;
6021 return;
6022 }
6023
6024 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6025 {
6026 const char *flab;
6027
6028 if (falselab != NULL)
6029 flab = falselab;
6030 else
6031 flab = mri_control_label ();
6032
6033 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6034 rightstop, (const char *) NULL, flab, extent);
6035
6036 input_line_pointer += 3;
6037 if (*input_line_pointer != '.'
6038 || input_line_pointer[1] == '\0')
6039 qual = '\0';
6040 else
6041 {
6042 qual = input_line_pointer[1];
6043 input_line_pointer += 2;
6044 }
6045
6046 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6047 &rightstart, &rightstop))
6048 {
6049 *stop = c;
6050 return;
6051 }
6052
6053 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6054 rightstop, truelab, falselab, extent);
6055
6056 if (falselab == NULL)
6057 colon (flab);
6058 }
6059 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6060 {
6061 const char *tlab;
6062
6063 if (truelab != NULL)
6064 tlab = truelab;
6065 else
6066 tlab = mri_control_label ();
6067
6068 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6069 rightstop, tlab, (const char *) NULL, extent);
6070
6071 input_line_pointer += 2;
6072 if (*input_line_pointer != '.'
6073 || input_line_pointer[1] == '\0')
6074 qual = '\0';
6075 else
6076 {
6077 qual = input_line_pointer[1];
6078 input_line_pointer += 2;
6079 }
6080
6081 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6082 &rightstart, &rightstop))
6083 {
6084 *stop = c;
6085 return;
6086 }
6087
6088 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6089 rightstop, truelab, falselab, extent);
6090
6091 if (truelab == NULL)
6092 colon (tlab);
6093 }
6094 else
6095 {
6096 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6097 rightstop, truelab, falselab, extent);
6098 }
6099
6100 *stop = c;
6101 if (input_line_pointer != stop)
6102 as_bad (_("syntax error in structured control directive"));
6103 }
6104
6105 /* Handle the MRI IF pseudo-op. This may be a structured control
6106 directive, or it may be a regular assembler conditional, depending
6107 on its operands. */
6108
6109 static void
6110 s_mri_if (qual)
6111 int qual;
6112 {
6113 char *s;
6114 int c;
6115 struct mri_control_info *n;
6116
6117 /* A structured control directive must end with THEN with an
6118 optional qualifier. */
6119 s = input_line_pointer;
6120 while (! is_end_of_line[(unsigned char) *s]
6121 && (! flag_mri || *s != '*'))
6122 ++s;
6123 --s;
6124 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6125 --s;
6126
6127 if (s - input_line_pointer > 1
6128 && s[-1] == '.')
6129 s -= 2;
6130
6131 if (s - input_line_pointer < 3
6132 || strncasecmp (s - 3, "THEN", 4) != 0)
6133 {
6134 if (qual != '\0')
6135 {
6136 as_bad (_("missing then"));
6137 ignore_rest_of_line ();
6138 return;
6139 }
6140
6141 /* It's a conditional. */
6142 s_if (O_ne);
6143 return;
6144 }
6145
6146 /* Since this might be a conditional if, this pseudo-op will be
6147 called even if we are supported to be ignoring input. Double
6148 check now. Clobber *input_line_pointer so that ignore_input
6149 thinks that this is not a special pseudo-op. */
6150 c = *input_line_pointer;
6151 *input_line_pointer = 0;
6152 if (ignore_input ())
6153 {
6154 *input_line_pointer = c;
6155 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6156 ++input_line_pointer;
6157 demand_empty_rest_of_line ();
6158 return;
6159 }
6160 *input_line_pointer = c;
6161
6162 n = push_mri_control (mri_if);
6163
6164 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6165 n->next, s[1] == '.' ? s[2] : '\0');
6166
6167 if (s[1] == '.')
6168 input_line_pointer = s + 3;
6169 else
6170 input_line_pointer = s + 1;
6171
6172 if (flag_mri)
6173 {
6174 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6175 ++input_line_pointer;
6176 }
6177
6178 demand_empty_rest_of_line ();
6179 }
6180
6181 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6182 structured IF, associate the ELSE with the IF. Otherwise, assume
6183 it is a conditional else. */
6184
6185 static void
6186 s_mri_else (qual)
6187 int qual;
6188 {
6189 int c;
6190 char *buf;
6191 char q[2];
6192
6193 if (qual == '\0'
6194 && (mri_control_stack == NULL
6195 || mri_control_stack->type != mri_if
6196 || mri_control_stack->else_seen))
6197 {
6198 s_else (0);
6199 return;
6200 }
6201
6202 c = *input_line_pointer;
6203 *input_line_pointer = 0;
6204 if (ignore_input ())
6205 {
6206 *input_line_pointer = c;
6207 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6208 ++input_line_pointer;
6209 demand_empty_rest_of_line ();
6210 return;
6211 }
6212 *input_line_pointer = c;
6213
6214 if (mri_control_stack == NULL
6215 || mri_control_stack->type != mri_if
6216 || mri_control_stack->else_seen)
6217 {
6218 as_bad (_("else without matching if"));
6219 ignore_rest_of_line ();
6220 return;
6221 }
6222
6223 mri_control_stack->else_seen = 1;
6224
6225 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6226 q[0] = qual;
6227 q[1] = '\0';
6228 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6229 mri_assemble (buf);
6230 free (buf);
6231
6232 colon (mri_control_stack->next);
6233
6234 if (flag_mri)
6235 {
6236 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6237 ++input_line_pointer;
6238 }
6239
6240 demand_empty_rest_of_line ();
6241 }
6242
6243 /* Handle the MRI ENDI pseudo-op. */
6244
6245 static void
6246 s_mri_endi (ignore)
6247 int ignore ATTRIBUTE_UNUSED;
6248 {
6249 if (mri_control_stack == NULL
6250 || mri_control_stack->type != mri_if)
6251 {
6252 as_bad (_("endi without matching if"));
6253 ignore_rest_of_line ();
6254 return;
6255 }
6256
6257 /* ignore_input will not return true for ENDI, so we don't need to
6258 worry about checking it again here. */
6259
6260 if (! mri_control_stack->else_seen)
6261 colon (mri_control_stack->next);
6262 colon (mri_control_stack->bottom);
6263
6264 pop_mri_control ();
6265
6266 if (flag_mri)
6267 {
6268 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6269 ++input_line_pointer;
6270 }
6271
6272 demand_empty_rest_of_line ();
6273 }
6274
6275 /* Handle the MRI BREAK pseudo-op. */
6276
6277 static void
6278 s_mri_break (extent)
6279 int extent;
6280 {
6281 struct mri_control_info *n;
6282 char *buf;
6283 char ex[2];
6284
6285 n = mri_control_stack;
6286 while (n != NULL
6287 && n->type != mri_for
6288 && n->type != mri_repeat
6289 && n->type != mri_while)
6290 n = n->outer;
6291 if (n == NULL)
6292 {
6293 as_bad (_("break outside of structured loop"));
6294 ignore_rest_of_line ();
6295 return;
6296 }
6297
6298 buf = (char *) xmalloc (20 + strlen (n->bottom));
6299 ex[0] = extent;
6300 ex[1] = '\0';
6301 sprintf (buf, "bra%s %s", ex, n->bottom);
6302 mri_assemble (buf);
6303 free (buf);
6304
6305 if (flag_mri)
6306 {
6307 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6308 ++input_line_pointer;
6309 }
6310
6311 demand_empty_rest_of_line ();
6312 }
6313
6314 /* Handle the MRI NEXT pseudo-op. */
6315
6316 static void
6317 s_mri_next (extent)
6318 int extent;
6319 {
6320 struct mri_control_info *n;
6321 char *buf;
6322 char ex[2];
6323
6324 n = mri_control_stack;
6325 while (n != NULL
6326 && n->type != mri_for
6327 && n->type != mri_repeat
6328 && n->type != mri_while)
6329 n = n->outer;
6330 if (n == NULL)
6331 {
6332 as_bad (_("next outside of structured loop"));
6333 ignore_rest_of_line ();
6334 return;
6335 }
6336
6337 buf = (char *) xmalloc (20 + strlen (n->next));
6338 ex[0] = extent;
6339 ex[1] = '\0';
6340 sprintf (buf, "bra%s %s", ex, n->next);
6341 mri_assemble (buf);
6342 free (buf);
6343
6344 if (flag_mri)
6345 {
6346 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6347 ++input_line_pointer;
6348 }
6349
6350 demand_empty_rest_of_line ();
6351 }
6352
6353 /* Handle the MRI FOR pseudo-op. */
6354
6355 static void
6356 s_mri_for (qual)
6357 int qual;
6358 {
6359 const char *varstart, *varstop;
6360 const char *initstart, *initstop;
6361 const char *endstart, *endstop;
6362 const char *bystart, *bystop;
6363 int up;
6364 int by;
6365 int extent;
6366 struct mri_control_info *n;
6367 char *buf;
6368 char *s;
6369 char ex[2];
6370
6371 /* The syntax is
6372 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6373 */
6374
6375 SKIP_WHITESPACE ();
6376 varstart = input_line_pointer;
6377
6378 /* Look for the '='. */
6379 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6380 && *input_line_pointer != '=')
6381 ++input_line_pointer;
6382 if (*input_line_pointer != '=')
6383 {
6384 as_bad (_("missing ="));
6385 ignore_rest_of_line ();
6386 return;
6387 }
6388
6389 varstop = input_line_pointer;
6390 if (varstop > varstart
6391 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6392 --varstop;
6393
6394 ++input_line_pointer;
6395
6396 initstart = input_line_pointer;
6397
6398 /* Look for TO or DOWNTO. */
6399 up = 1;
6400 initstop = NULL;
6401 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6402 {
6403 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6404 && ! is_part_of_name (input_line_pointer[2]))
6405 {
6406 initstop = input_line_pointer;
6407 input_line_pointer += 2;
6408 break;
6409 }
6410 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6411 && ! is_part_of_name (input_line_pointer[6]))
6412 {
6413 initstop = input_line_pointer;
6414 up = 0;
6415 input_line_pointer += 6;
6416 break;
6417 }
6418 ++input_line_pointer;
6419 }
6420 if (initstop == NULL)
6421 {
6422 as_bad (_("missing to or downto"));
6423 ignore_rest_of_line ();
6424 return;
6425 }
6426 if (initstop > initstart
6427 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6428 --initstop;
6429
6430 SKIP_WHITESPACE ();
6431 endstart = input_line_pointer;
6432
6433 /* Look for BY or DO. */
6434 by = 0;
6435 endstop = NULL;
6436 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6437 {
6438 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6439 && ! is_part_of_name (input_line_pointer[2]))
6440 {
6441 endstop = input_line_pointer;
6442 by = 1;
6443 input_line_pointer += 2;
6444 break;
6445 }
6446 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6447 && (input_line_pointer[2] == '.'
6448 || ! is_part_of_name (input_line_pointer[2])))
6449 {
6450 endstop = input_line_pointer;
6451 input_line_pointer += 2;
6452 break;
6453 }
6454 ++input_line_pointer;
6455 }
6456 if (endstop == NULL)
6457 {
6458 as_bad (_("missing do"));
6459 ignore_rest_of_line ();
6460 return;
6461 }
6462 if (endstop > endstart
6463 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6464 --endstop;
6465
6466 if (! by)
6467 {
6468 bystart = "#1";
6469 bystop = bystart + 2;
6470 }
6471 else
6472 {
6473 SKIP_WHITESPACE ();
6474 bystart = input_line_pointer;
6475
6476 /* Look for DO. */
6477 bystop = NULL;
6478 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6479 {
6480 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6481 && (input_line_pointer[2] == '.'
6482 || ! is_part_of_name (input_line_pointer[2])))
6483 {
6484 bystop = input_line_pointer;
6485 input_line_pointer += 2;
6486 break;
6487 }
6488 ++input_line_pointer;
6489 }
6490 if (bystop == NULL)
6491 {
6492 as_bad (_("missing do"));
6493 ignore_rest_of_line ();
6494 return;
6495 }
6496 if (bystop > bystart
6497 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6498 --bystop;
6499 }
6500
6501 if (*input_line_pointer != '.')
6502 extent = '\0';
6503 else
6504 {
6505 extent = input_line_pointer[1];
6506 input_line_pointer += 2;
6507 }
6508
6509 /* We have fully parsed the FOR operands. Now build the loop. */
6510
6511 n = push_mri_control (mri_for);
6512
6513 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6514
6515 /* move init,var */
6516 s = buf;
6517 *s++ = 'm';
6518 *s++ = 'o';
6519 *s++ = 'v';
6520 *s++ = 'e';
6521 if (qual != '\0')
6522 *s++ = qual;
6523 *s++ = ' ';
6524 memcpy (s, initstart, initstop - initstart);
6525 s += initstop - initstart;
6526 *s++ = ',';
6527 memcpy (s, varstart, varstop - varstart);
6528 s += varstop - varstart;
6529 *s = '\0';
6530 mri_assemble (buf);
6531
6532 colon (n->top);
6533
6534 /* cmp end,var */
6535 s = buf;
6536 *s++ = 'c';
6537 *s++ = 'm';
6538 *s++ = 'p';
6539 if (qual != '\0')
6540 *s++ = qual;
6541 *s++ = ' ';
6542 memcpy (s, endstart, endstop - endstart);
6543 s += endstop - endstart;
6544 *s++ = ',';
6545 memcpy (s, varstart, varstop - varstart);
6546 s += varstop - varstart;
6547 *s = '\0';
6548 mri_assemble (buf);
6549
6550 /* bcc bottom */
6551 ex[0] = extent;
6552 ex[1] = '\0';
6553 if (up)
6554 sprintf (buf, "blt%s %s", ex, n->bottom);
6555 else
6556 sprintf (buf, "bgt%s %s", ex, n->bottom);
6557 mri_assemble (buf);
6558
6559 /* Put together the add or sub instruction used by ENDF. */
6560 s = buf;
6561 if (up)
6562 strcpy (s, "add");
6563 else
6564 strcpy (s, "sub");
6565 s += 3;
6566 if (qual != '\0')
6567 *s++ = qual;
6568 *s++ = ' ';
6569 memcpy (s, bystart, bystop - bystart);
6570 s += bystop - bystart;
6571 *s++ = ',';
6572 memcpy (s, varstart, varstop - varstart);
6573 s += varstop - varstart;
6574 *s = '\0';
6575 n->incr = buf;
6576
6577 if (flag_mri)
6578 {
6579 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6580 ++input_line_pointer;
6581 }
6582
6583 demand_empty_rest_of_line ();
6584 }
6585
6586 /* Handle the MRI ENDF pseudo-op. */
6587
6588 static void
6589 s_mri_endf (ignore)
6590 int ignore ATTRIBUTE_UNUSED;
6591 {
6592 if (mri_control_stack == NULL
6593 || mri_control_stack->type != mri_for)
6594 {
6595 as_bad (_("endf without for"));
6596 ignore_rest_of_line ();
6597 return;
6598 }
6599
6600 colon (mri_control_stack->next);
6601
6602 mri_assemble (mri_control_stack->incr);
6603
6604 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6605 mri_assemble (mri_control_stack->incr);
6606
6607 free (mri_control_stack->incr);
6608
6609 colon (mri_control_stack->bottom);
6610
6611 pop_mri_control ();
6612
6613 if (flag_mri)
6614 {
6615 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6616 ++input_line_pointer;
6617 }
6618
6619 demand_empty_rest_of_line ();
6620 }
6621
6622 /* Handle the MRI REPEAT pseudo-op. */
6623
6624 static void
6625 s_mri_repeat (ignore)
6626 int ignore ATTRIBUTE_UNUSED;
6627 {
6628 struct mri_control_info *n;
6629
6630 n = push_mri_control (mri_repeat);
6631 colon (n->top);
6632 if (flag_mri)
6633 {
6634 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6635 ++input_line_pointer;
6636 }
6637 demand_empty_rest_of_line ();
6638 }
6639
6640 /* Handle the MRI UNTIL pseudo-op. */
6641
6642 static void
6643 s_mri_until (qual)
6644 int qual;
6645 {
6646 char *s;
6647
6648 if (mri_control_stack == NULL
6649 || mri_control_stack->type != mri_repeat)
6650 {
6651 as_bad (_("until without repeat"));
6652 ignore_rest_of_line ();
6653 return;
6654 }
6655
6656 colon (mri_control_stack->next);
6657
6658 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6659 ;
6660
6661 parse_mri_control_expression (s, qual, (const char *) NULL,
6662 mri_control_stack->top, '\0');
6663
6664 colon (mri_control_stack->bottom);
6665
6666 input_line_pointer = s;
6667
6668 pop_mri_control ();
6669
6670 if (flag_mri)
6671 {
6672 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6673 ++input_line_pointer;
6674 }
6675
6676 demand_empty_rest_of_line ();
6677 }
6678
6679 /* Handle the MRI WHILE pseudo-op. */
6680
6681 static void
6682 s_mri_while (qual)
6683 int qual;
6684 {
6685 char *s;
6686
6687 struct mri_control_info *n;
6688
6689 s = input_line_pointer;
6690 while (! is_end_of_line[(unsigned char) *s]
6691 && (! flag_mri || *s != '*'))
6692 s++;
6693 --s;
6694 while (*s == ' ' || *s == '\t')
6695 --s;
6696 if (s - input_line_pointer > 1
6697 && s[-1] == '.')
6698 s -= 2;
6699 if (s - input_line_pointer < 2
6700 || strncasecmp (s - 1, "DO", 2) != 0)
6701 {
6702 as_bad (_("missing do"));
6703 ignore_rest_of_line ();
6704 return;
6705 }
6706
6707 n = push_mri_control (mri_while);
6708
6709 colon (n->next);
6710
6711 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6712 s[1] == '.' ? s[2] : '\0');
6713
6714 input_line_pointer = s + 1;
6715 if (*input_line_pointer == '.')
6716 input_line_pointer += 2;
6717
6718 if (flag_mri)
6719 {
6720 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6721 ++input_line_pointer;
6722 }
6723
6724 demand_empty_rest_of_line ();
6725 }
6726
6727 /* Handle the MRI ENDW pseudo-op. */
6728
6729 static void
6730 s_mri_endw (ignore)
6731 int ignore ATTRIBUTE_UNUSED;
6732 {
6733 char *buf;
6734
6735 if (mri_control_stack == NULL
6736 || mri_control_stack->type != mri_while)
6737 {
6738 as_bad (_("endw without while"));
6739 ignore_rest_of_line ();
6740 return;
6741 }
6742
6743 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6744 sprintf (buf, "bra %s", mri_control_stack->next);
6745 mri_assemble (buf);
6746 free (buf);
6747
6748 colon (mri_control_stack->bottom);
6749
6750 pop_mri_control ();
6751
6752 if (flag_mri)
6753 {
6754 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6755 ++input_line_pointer;
6756 }
6757
6758 demand_empty_rest_of_line ();
6759 }
6760 \f
6761 /*
6762 * md_parse_option
6763 * Invocation line includes a switch not recognized by the base assembler.
6764 * See if it's a processor-specific option. These are:
6765 *
6766 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6767 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6768 * Select the architecture. Instructions or features not
6769 * supported by the selected architecture cause fatal
6770 * errors. More than one may be specified. The default is
6771 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6772 * for -m68000, and -m68882 is a synonym for -m68881.
6773 * -[A]m[c]no-68851, -[A]m[c]no-68881
6774 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6775 * so don't use or document it, but that's the way the parsing
6776 * works).
6777 *
6778 * -pic Indicates PIC.
6779 * -k Indicates PIC. (Sun 3 only.)
6780 * --pcrel Never turn PC-relative branches into absolute jumps.
6781 *
6782 * --bitwise-or
6783 * Permit `|' to be used in expressions.
6784 *
6785 */
6786
6787 #ifdef OBJ_ELF
6788 CONST char *md_shortopts = "lSA:m:kQ:V";
6789 #else
6790 CONST char *md_shortopts = "lSA:m:k";
6791 #endif
6792
6793 struct option md_longopts[] = {
6794 #define OPTION_PIC (OPTION_MD_BASE)
6795 {"pic", no_argument, NULL, OPTION_PIC},
6796 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6797 {"register-prefix-optional", no_argument, NULL,
6798 OPTION_REGISTER_PREFIX_OPTIONAL},
6799 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6800 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6801 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6802 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6803 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6804 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6805 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6806 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6807 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6808 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6809 #define OPTION_PCREL (OPTION_MD_BASE + 7)
6810 {"pcrel", no_argument, NULL, OPTION_PCREL},
6811 {NULL, no_argument, NULL, 0}
6812 };
6813 size_t md_longopts_size = sizeof(md_longopts);
6814
6815 int
6816 md_parse_option (c, arg)
6817 int c;
6818 char *arg;
6819 {
6820 switch (c)
6821 {
6822 case 'l': /* -l means keep external to 2 bit offset
6823 rather than 16 bit one */
6824 flag_short_refs = 1;
6825 break;
6826
6827 case 'S': /* -S means that jbsr's always turn into
6828 jsr's. */
6829 flag_long_jumps = 1;
6830 break;
6831
6832 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6833 branches into absolute jumps. */
6834 flag_keep_pcrel = 1;
6835 break;
6836
6837 case 'A':
6838 if (*arg == 'm')
6839 arg++;
6840 /* intentional fall-through */
6841 case 'm':
6842
6843 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6844 {
6845 int i;
6846 unsigned long arch;
6847 const char *oarg = arg;
6848
6849 arg += 3;
6850 if (*arg == 'm')
6851 {
6852 arg++;
6853 if (arg[0] == 'c' && arg[1] == '6')
6854 arg++;
6855 }
6856 for (i = 0; i < n_archs; i++)
6857 if (!strcmp (arg, archs[i].name))
6858 break;
6859 if (i == n_archs)
6860 {
6861 unknown:
6862 as_bad (_("unrecognized option `%s'"), oarg);
6863 return 0;
6864 }
6865 arch = archs[i].arch;
6866 if (arch == m68881)
6867 no_68881 = 1;
6868 else if (arch == m68851)
6869 no_68851 = 1;
6870 else
6871 goto unknown;
6872 }
6873 else
6874 {
6875 int i;
6876
6877 if (arg[0] == 'c' && arg[1] == '6')
6878 arg++;
6879
6880 for (i = 0; i < n_archs; i++)
6881 if (!strcmp (arg, archs[i].name))
6882 {
6883 unsigned long arch = archs[i].arch;
6884 if (cpu_of_arch (arch))
6885 /* It's a cpu spec. */
6886 {
6887 current_architecture &= ~m68000up;
6888 current_architecture |= arch;
6889 }
6890 else if (arch == m68881)
6891 {
6892 current_architecture |= m68881;
6893 no_68881 = 0;
6894 }
6895 else if (arch == m68851)
6896 {
6897 current_architecture |= m68851;
6898 no_68851 = 0;
6899 }
6900 else
6901 /* ??? */
6902 abort ();
6903 break;
6904 }
6905 if (i == n_archs)
6906 {
6907 as_bad (_("unrecognized architecture specification `%s'"), arg);
6908 return 0;
6909 }
6910 }
6911 break;
6912
6913 case OPTION_PIC:
6914 case 'k':
6915 flag_want_pic = 1;
6916 break; /* -pic, Position Independent Code */
6917
6918 case OPTION_REGISTER_PREFIX_OPTIONAL:
6919 flag_reg_prefix_optional = 1;
6920 reg_prefix_optional_seen = 1;
6921 break;
6922
6923 /* -V: SVR4 argument to print version ID. */
6924 case 'V':
6925 print_version_id ();
6926 break;
6927
6928 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6929 should be emitted or not. FIXME: Not implemented. */
6930 case 'Q':
6931 break;
6932
6933 case OPTION_BITWISE_OR:
6934 {
6935 char *n, *t;
6936 const char *s;
6937
6938 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6939 t = n;
6940 for (s = m68k_comment_chars; *s != '\0'; s++)
6941 if (*s != '|')
6942 *t++ = *s;
6943 *t = '\0';
6944 m68k_comment_chars = n;
6945 }
6946 break;
6947
6948 case OPTION_BASE_SIZE_DEFAULT_16:
6949 m68k_index_width_default = SIZE_WORD;
6950 break;
6951
6952 case OPTION_BASE_SIZE_DEFAULT_32:
6953 m68k_index_width_default = SIZE_LONG;
6954 break;
6955
6956 case OPTION_DISP_SIZE_DEFAULT_16:
6957 m68k_rel32 = 0;
6958 m68k_rel32_from_cmdline = 1;
6959 break;
6960
6961 case OPTION_DISP_SIZE_DEFAULT_32:
6962 m68k_rel32 = 1;
6963 m68k_rel32_from_cmdline = 1;
6964 break;
6965
6966 default:
6967 return 0;
6968 }
6969
6970 return 1;
6971 }
6972
6973 void
6974 md_show_usage (stream)
6975 FILE *stream;
6976 {
6977 fprintf(stream, _("\
6978 680X0 options:\n\
6979 -l use 1 word for refs to undefined symbols [default 2]\n\
6980 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6981 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6982 | -mcpu32 | -m5200\n\
6983 specify variant of 680X0 architecture [default 68020]\n\
6984 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6985 target has/lacks floating-point coprocessor\n\
6986 [default yes for 68020, 68030, and cpu32]\n"));
6987 fprintf(stream, _("\
6988 -m68851 | -mno-68851\n\
6989 target has/lacks memory-management unit coprocessor\n\
6990 [default yes for 68020 and up]\n\
6991 -pic, -k generate position independent code\n\
6992 -S turn jbsr into jsr\n\
6993 --pcrel never turn PC-relative branches into absolute jumps\n\
6994 --register-prefix-optional\n\
6995 recognize register names without prefix character\n\
6996 --bitwise-or do not treat `|' as a comment character\n"));
6997 fprintf (stream, _("\
6998 --base-size-default-16 base reg without size is 16 bits\n\
6999 --base-size-default-32 base reg without size is 32 bits (default)\n\
7000 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7001 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7002 }
7003 \f
7004 #ifdef TEST2
7005
7006 /* TEST2: Test md_assemble() */
7007 /* Warning, this routine probably doesn't work anymore */
7008
7009 main ()
7010 {
7011 struct m68k_it the_ins;
7012 char buf[120];
7013 char *cp;
7014 int n;
7015
7016 m68k_ip_begin ();
7017 for (;;)
7018 {
7019 if (!gets (buf) || !*buf)
7020 break;
7021 if (buf[0] == '|' || buf[1] == '.')
7022 continue;
7023 for (cp = buf; *cp; cp++)
7024 if (*cp == '\t')
7025 *cp = ' ';
7026 if (is_label (buf))
7027 continue;
7028 memset (&the_ins, '\0', sizeof (the_ins));
7029 m68k_ip (&the_ins, buf);
7030 if (the_ins.error)
7031 {
7032 printf (_("Error %s in %s\n"), the_ins.error, buf);
7033 }
7034 else
7035 {
7036 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7037 for (n = 0; n < the_ins.numo; n++)
7038 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7039 printf (" ");
7040 print_the_insn (&the_ins.opcode[0], stdout);
7041 (void) putchar ('\n');
7042 }
7043 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7044 {
7045 if (the_ins.operands[n].error)
7046 {
7047 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7048 continue;
7049 }
7050 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7051 if (the_ins.operands[n].b_const)
7052 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7053 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7054 if (the_ins.operands[n].b_iadd)
7055 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7056 (void) putchar ('\n');
7057 }
7058 }
7059 m68k_ip_end ();
7060 return 0;
7061 }
7062
7063 is_label (str)
7064 char *str;
7065 {
7066 while (*str == ' ')
7067 str++;
7068 while (*str && *str != ' ')
7069 str++;
7070 if (str[-1] == ':' || str[1] == '=')
7071 return 1;
7072 return 0;
7073 }
7074
7075 #endif
7076
7077 /* Possible states for relaxation:
7078
7079 0 0 branch offset byte (bra, etc)
7080 0 1 word
7081 0 2 long
7082
7083 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7084 1 1 word
7085 1 2 long
7086
7087 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7088 2 1 word-long
7089 2 2 long-word
7090 2 3 long-long
7091
7092 */
7093
7094 /* We have no need to default values of symbols. */
7095
7096 /* ARGSUSED */
7097 symbolS *
7098 md_undefined_symbol (name)
7099 char *name ATTRIBUTE_UNUSED;
7100 {
7101 return 0;
7102 }
7103
7104 /* Round up a section size to the appropriate boundary. */
7105 valueT
7106 md_section_align (segment, size)
7107 segT segment ATTRIBUTE_UNUSED;
7108 valueT size;
7109 {
7110 #ifdef OBJ_AOUT
7111 #ifdef BFD_ASSEMBLER
7112 /* For a.out, force the section size to be aligned. If we don't do
7113 this, BFD will align it for us, but it will not write out the
7114 final bytes of the section. This may be a bug in BFD, but it is
7115 easier to fix it here since that is how the other a.out targets
7116 work. */
7117 int align;
7118
7119 align = bfd_get_section_alignment (stdoutput, segment);
7120 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7121 #endif
7122 #endif
7123
7124 return size;
7125 }
7126
7127 /* Exactly what point is a PC-relative offset relative TO?
7128 On the 68k, it is relative to the address of the first extension
7129 word. The difference between the addresses of the offset and the
7130 first extension word is stored in fx_pcrel_adjust. */
7131 long
7132 md_pcrel_from (fixP)
7133 fixS *fixP;
7134 {
7135 int adjust;
7136
7137 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
7138 -1 as 64. */
7139 adjust = fixP->fx_pcrel_adjust;
7140 if (adjust == 64)
7141 adjust = -1;
7142 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7143 }
7144
7145 #ifndef BFD_ASSEMBLER
7146 #ifdef OBJ_COFF
7147
7148 /*ARGSUSED*/
7149 void
7150 tc_coff_symbol_emit_hook (ignore)
7151 symbolS *ignore ATTRIBUTE_UNUSED;
7152 {
7153 }
7154
7155 int
7156 tc_coff_sizemachdep (frag)
7157 fragS *frag;
7158 {
7159 switch (frag->fr_subtype & 0x3)
7160 {
7161 case BYTE:
7162 return 1;
7163 case SHORT:
7164 return 2;
7165 case LONG:
7166 return 4;
7167 default:
7168 abort ();
7169 return 0;
7170 }
7171 }
7172
7173 #endif
7174 #endif
7175 #ifdef OBJ_ELF
7176 void m68k_elf_final_processing()
7177 {
7178 /* Set file-specific flags if this is a cpu32 processor */
7179 if (cpu_of_arch (current_architecture) & cpu32)
7180 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7181 }
7182 #endif
7183 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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