1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "opcode/m68k.h"
27 #include "m68k-parse.h"
29 /* This array holds the chars that always start a comment. If the
30 pre-processor is disabled, these aren't very useful */
32 CONST
char comment_chars
[] = "|#";
34 CONST
char comment_chars
[] = "|";
37 /* This array holds the chars that only start a comment at the beginning of
38 a line. If the line seems to have the form '# 123 filename'
39 .line and .file directives will appear in the pre-processed output */
40 /* Note that input_file.c hand checks for '#' at the beginning of the
41 first line of the input file. This is because the compiler outputs
42 #NO_APP at the beginning of its output. */
43 /* Also note that comments like this one will always work. */
44 CONST
char line_comment_chars
[] = "#";
46 CONST
char line_separator_chars
[] = "";
48 /* Chars that can be used to separate mant from exp in floating point nums */
49 CONST
char EXP_CHARS
[] = "eE";
51 /* Chars that mean this number is a floating point constant, as
52 in "0f12.456" or "0d1.2345e12". */
54 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
56 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
57 changed in read.c . Ideally it shouldn't have to know about it at all,
58 but nothing is ideal around here. */
60 const int md_reloc_size
= 8; /* Size of relocation record */
62 /* Are we trying to generate PIC code? If so, absolute references
63 ought to be made into linkage table references or pc-relative
67 static int flag_short_refs
; /* -l option */
68 static int flag_long_jumps
; /* -S option */
70 #ifdef REGISTER_PREFIX_OPTIONAL
71 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
73 int flag_reg_prefix_optional
;
76 /* The floating point coprocessor to use by default. */
77 static enum m68k_register m68k_float_copnum
= COP1
;
79 /* Its an arbitrary name: This means I don't approve of it */
80 /* See flames below */
81 static struct obstack robyn
;
83 #define TAB(x,y) (((x)<<2)+(y))
84 #define TABTYPE(xy) ((xy) >> 2)
90 /* Case `g' except when BCC68000 is applicable. */
92 /* Coprocessor branches. */
94 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
95 supported on all cpus. Widens to 32-bit absolute. */
97 /* For inserting an extra jmp instruction with long offset on 68000,
98 for expanding conditional branches. (Not bsr or bra.) Since the
99 68000 doesn't support 32-bit displacements for conditional
100 branches, we fake it by reversing the condition and branching
101 around a jmp with an absolute long operand. */
103 /* For the DBcc "instructions". If the displacement requires 32 bits,
104 the branch-around-a-jump game is played here too. */
106 /* Not currently used? */
108 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
114 const char *m_operands
;
115 unsigned long m_opcode
;
119 struct m68k_incant
*m_next
;
122 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
123 #define gettwo(x) (((x)->m_opcode)&0xffff)
125 static const enum m68k_register m68000_control_regs
[] = { 0 };
126 static const enum m68k_register m68010_control_regs
[] = {
130 static const enum m68k_register m68020_control_regs
[] = {
131 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
134 static const enum m68k_register m68040_control_regs
[] = {
135 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
136 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
139 static const enum m68k_register m68060_control_regs
[] = {
140 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
141 USP
, VBR
, URP
, SRP
, PCR
,
144 #define cpu32_control_regs m68010_control_regs
146 static const enum m68k_register
*control_regs
;
148 /* internal form of a 68020 instruction */
152 const char *args
; /* list of opcode info */
155 int numo
; /* Number of shorts in opcode */
158 struct m68k_op operands
[6];
160 int nexp
; /* number of exprs in use */
161 struct m68k_exp exprs
[4];
163 int nfrag
; /* Number of frags we have to produce */
166 int fragoff
; /* Where in the current opcode the frag ends */
173 int nrel
; /* Num of reloc strucs in use */
180 /* In a pc relative address the difference between the address
181 of the offset and the address that the offset is relative
182 to. This depends on the addressing mode. Basically this
183 is the value to put in the offset field to address the
184 first byte of the offset, without regarding the special
185 significance of some values (in the branch instruction, for
189 reloc
[5]; /* Five is enough??? */
192 #define cpu_of_arch(x) ((x) & m68000up)
193 #define float_of_arch(x) ((x) & mfloat)
194 #define mmu_of_arch(x) ((x) & mmmu)
196 static struct m68k_it the_ins
; /* the instruction being assembled */
198 #define op(ex) ((ex)->exp.X_op)
199 #define adds(ex) ((ex)->exp.X_add_symbol)
200 #define subs(ex) ((ex)->exp.X_op_symbol)
201 #define offs(ex) ((ex)->exp.X_add_number)
203 /* Macros for adding things to the m68k_it struct */
205 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
207 /* Like addword, but goes BEFORE general operands */
211 struct m68k_incant
*opcode
;
214 for(z
=the_ins
.numo
;z
>opcode
->m_codenum
;--z
)
215 the_ins
.opcode
[z
]=the_ins
.opcode
[z
-1];
216 for(z
=0;z
<the_ins
.nrel
;z
++)
217 the_ins
.reloc
[z
].n
+=2;
218 for (z
= 0; z
< the_ins
.nfrag
; z
++)
219 the_ins
.fragb
[z
].fragoff
++;
220 the_ins
.opcode
[opcode
->m_codenum
]=w
;
224 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
227 add_fix (width
, exp
, pc_rel
, pc_fix
)
229 struct m68k_exp
*exp
;
233 the_ins
.reloc
[the_ins
.nrel
].n
= (((width
)=='B')
237 : (the_ins
.numo
*2)));
238 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
239 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
240 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
241 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
244 /* Cause an extra frag to be generated here, inserting up to 10 bytes
245 (that value is chosen in the frag_var call in md_assemble). TYPE
246 is the subtype of the frag to be generated; its primary type is
247 rs_machine_dependent.
249 The TYPE parameter is also used by md_convert_frag_1 and
250 md_estimate_size_before_relax. The appropriate type of fixup will
251 be emitted by md_convert_frag_1.
253 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
255 add_frag(add
,off
,type
)
260 the_ins
.fragb
[the_ins
.nfrag
].fragoff
=the_ins
.numo
;
261 the_ins
.fragb
[the_ins
.nfrag
].fadd
=add
;
262 the_ins
.fragb
[the_ins
.nfrag
].foff
=off
;
263 the_ins
.fragb
[the_ins
.nfrag
++].fragty
=type
;
267 (op (ex) != O_constant && op (ex) != O_big)
269 static char *crack_operand
PARAMS ((char *str
, struct m68k_op
*opP
));
270 static int get_num
PARAMS ((struct m68k_exp
*exp
, int ok
));
271 static int reverse_16_bits
PARAMS ((int in
));
272 static int reverse_8_bits
PARAMS ((int in
));
273 static void install_gen_operand
PARAMS ((int mode
, int val
));
274 static void install_operand
PARAMS ((int mode
, int val
));
275 static void s_bss
PARAMS ((int));
276 static void s_data1
PARAMS ((int));
277 static void s_data2
PARAMS ((int));
278 static void s_even
PARAMS ((int));
279 static void s_proc
PARAMS ((int));
280 static void mri_chip
PARAMS ((void));
281 static void s_chip
PARAMS ((int));
282 static void s_fopt
PARAMS ((int));
284 static int current_architecture
;
291 static const struct m68k_cpu archs
[] = {
301 /* Aliases (effectively, so far as gas is concerned) for the above
306 { m68000
, "68ec000" },
307 { m68000
, "68hc000" },
308 { m68000
, "68hc001" },
309 { m68020
, "68ec020" },
310 { m68030
, "68ec030" },
311 { m68040
, "68ec040" },
321 static const int n_archs
= sizeof (archs
) / sizeof (archs
[0]);
323 /* BCC68000 is for patching in an extra jmp instruction for long offsets
324 on the 68000. The 68000 doesn't support long branches with branchs */
326 /* This table desribes how you change sizes for the various types of variable
327 size expressions. This version only supports two kinds. */
329 /* Note that calls to frag_var need to specify the maximum expansion
330 needed; this is currently 10 bytes for DBCC. */
333 How far Forward this mode will reach:
334 How far Backward this mode will reach:
335 How many bytes this mode will add to the size of the frag
336 Which mode to go to if the offset won't fit in this one
338 relax_typeS md_relax_table
[] =
340 {1, 1, 0, 0}, /* First entries aren't used */
341 {1, 1, 0, 0}, /* For no good reason except */
342 {1, 1, 0, 0}, /* that the VAX doesn't either */
345 {(127), (-128), 0, TAB (ABRANCH
, SHORT
)},
346 {(32767), (-32768), 2, TAB (ABRANCH
, LONG
)},
350 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
351 {(32767), (-32768), 2, TAB (FBRANCH
, LONG
)},
355 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
356 {(32767), (-32768), 2, TAB (PCREL
, LONG
)},
360 {(127), (-128), 0, TAB (BCC68000
, SHORT
)},
361 {(32767), (-32768), 2, TAB (BCC68000
, LONG
)},
362 {0, 0, 6, 0}, /* jmp long space */
365 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
366 {(32767), (-32768), 2, TAB (DBCC
, LONG
)},
367 {0, 0, 10, 0}, /* bra/jmp long space */
370 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
371 {32767, -32768, 2, TAB (PCLEA
, LONG
)},
375 /* For, e.g., jmp pcrel indexed. */
376 {125, -130, 0, TAB (PCINDEX
, SHORT
)},
377 {32765, -32770, 2, TAB (PCINDEX
, LONG
)},
382 /* These are the machine dependent pseudo-ops. These are included so
383 the assembler can work on the output from the SUN C compiler, which
387 /* This table describes all the machine specific pseudo-ops the assembler
388 has to support. The fields are:
389 pseudo-op name without dot
390 function to call to execute this pseudo-op
391 Integer arg to pass to the function
393 CONST pseudo_typeS md_pseudo_table
[] =
395 {"data1", s_data1
, 0},
396 {"data2", s_data2
, 0},
399 {"skip", s_space
, 0},
402 {"align", s_align_bytes
, 0},
405 {"swbeg", s_ignore
, 0},
408 /* The following pseudo-ops are supported for MRI compatibility. */
410 {"comline", s_space
, 1},
412 {"mask2", s_ignore
, 0},
418 /* The mote pseudo ops are put into the opcode table, since they
419 don't start with a . they look like opcodes to gas.
421 extern void obj_coff_section ();
423 CONST pseudo_typeS mote_pseudo_table
[] =
436 {"xdef", s_globl
, 0},
437 {"align", s_align_ptwo
, 0},
439 {"sect", obj_coff_section
, 0},
440 {"section", obj_coff_section
, 0},
445 #define issbyte(x) ((x)>=-128 && (x)<=127)
446 #define isubyte(x) ((x)>=0 && (x)<=255)
447 #define issword(x) ((x)>=-32768 && (x)<=32767)
448 #define isuword(x) ((x)>=0 && (x)<=65535)
450 #define isbyte(x) ((x)>= -255 && (x)<=255)
451 #define isword(x) ((x)>=-32768 && (x)<=65535)
452 #define islong(x) (1)
454 extern char *input_line_pointer
;
456 static char mklower_table
[256];
457 #define mklower(c) (mklower_table[(unsigned char)(c)])
458 static char notend_table
[256];
459 static char alt_notend_table
[256];
461 (! (notend_table[(unsigned char) *s] \
463 && alt_notend_table[(unsigned char) s[1]])))
465 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
467 #ifdef NO_PCREL_RELOCS
470 make_pcrel_absolute(fixP
, add_number
)
474 register unsigned char *opcode
= fixP
->fx_frag
->fr_opcode
;
476 /* rewrite the PC relative instructions to absolute address ones.
477 * these are rumoured to be faster, and the apollo linker refuses
478 * to deal with the PC relative relocations.
480 if (opcode
[0] == 0x60 && opcode
[1] == 0xff) /* BRA -> JMP */
485 else if (opcode
[0] == 0x61 && opcode
[1] == 0xff) /* BSR -> JSR */
491 as_fatal ("Unknown PC relative instruction");
496 #endif /* NO_PCREL_RELOCS */
499 tc_coff_fix2rtype (fixP
)
502 #ifdef NO_PCREL_RELOCS
503 know (fixP
->fx_pcrel
== 0);
504 return (fixP
->fx_size
== 1 ? R_RELBYTE
505 : fixP
->fx_size
== 2 ? R_DIR16
508 return (fixP
->fx_pcrel
?
509 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
510 fixP
->fx_size
== 2 ? R_PCRWORD
:
512 (fixP
->fx_size
== 1 ? R_RELBYTE
:
513 fixP
->fx_size
== 2 ? R_RELWORD
:
523 tc_gen_reloc (section
, fixp
)
528 bfd_reloc_code_real_type code
;
530 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
531 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
533 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
534 MAP (1, 0, BFD_RELOC_8
);
535 MAP (2, 0, BFD_RELOC_16
);
536 MAP (4, 0, BFD_RELOC_32
);
537 MAP (1, 1, BFD_RELOC_8_PCREL
);
538 MAP (2, 1, BFD_RELOC_16_PCREL
);
539 MAP (4, 1, BFD_RELOC_32_PCREL
);
544 reloc
= (arelent
*) bfd_alloc_by_size_t (stdoutput
, sizeof (arelent
));
546 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
547 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
549 reloc
->addend
= fixp
->fx_addnumber
;
553 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
554 assert (reloc
->howto
!= 0);
559 #endif /* BFD_ASSEMBLER */
561 /* Handle of the OPCODE hash table. NULL means any use before
562 m68k_ip_begin() will crash. */
563 static struct hash_control
*op_hash
;
565 /* Assemble an m68k instruction. */
572 register struct m68k_op
*opP
;
573 register struct m68k_incant
*opcode
;
574 register const char *s
;
575 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
576 char *pdot
, *pdotmove
;
577 enum m68k_size siz1
, siz2
;
581 char *crack_operand ();
582 LITTLENUM_TYPE words
[6];
583 LITTLENUM_TYPE
*wordp
;
584 unsigned long ok_arch
= 0;
586 if (*instring
== ' ')
587 instring
++; /* skip leading whitespace */
589 /* Scan up to end of operation-code, which MUST end in end-of-string
590 or exactly 1 space. */
592 for (p
= instring
; *p
!= '\0'; p
++)
602 the_ins
.error
= "No operator";
606 /* p now points to the end of the opcode name, probably whitespace.
607 Make sure the name is null terminated by clobbering the
608 whitespace, look it up in the hash table, then fix it back.
609 Remove a dot, first, since the opcode tables have none. */
612 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
613 *pdotmove
= pdotmove
[1];
619 opcode
= (struct m68k_incant
*) hash_find (op_hash
, instring
);
624 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
625 *pdotmove
= pdotmove
[-1];
632 the_ins
.error
= "Unknown operator";
636 /* found a legitimate opcode, start matching operands */
640 if (opcode
->m_operands
== 0)
642 char *old
= input_line_pointer
;
644 input_line_pointer
= p
;
645 /* Ahh - it's a motorola style psuedo op */
646 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
647 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
648 input_line_pointer
= old
;
654 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
656 p
= crack_operand (p
, opP
);
660 the_ins
.error
= opP
->error
;
665 opsfound
= opP
- &the_ins
.operands
[0];
667 /* This ugly hack is to support the floating pt opcodes in their
668 standard form. Essentially, we fake a first enty of type COP#1 */
669 if (opcode
->m_operands
[0] == 'I')
673 for (n
= opsfound
; n
> 0; --n
)
674 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
676 memset ((char *) (&the_ins
.operands
[0]), '\0',
677 sizeof (the_ins
.operands
[0]));
678 the_ins
.operands
[0].mode
= CONTROL
;
679 the_ins
.operands
[0].reg
= m68k_float_copnum
;
683 /* We've got the operands. Find an opcode that'll accept them */
686 /* If we didn't get the right number of ops, or we have no
687 common model with this pattern then reject this pattern. */
689 if (opsfound
!= opcode
->m_opnum
690 || ((opcode
->m_arch
& current_architecture
) == 0))
693 ok_arch
|= opcode
->m_arch
;
697 for (s
= opcode
->m_operands
, opP
= &the_ins
.operands
[0];
701 /* Warning: this switch is huge! */
702 /* I've tried to organize the cases into this order:
703 non-alpha first, then alpha by letter. Lower-case
704 goes directly before uppercase counterpart. */
705 /* Code with multiple case ...: gets sorted by the lowest
706 case ... it belongs to. I hope this makes sense. */
746 if (opP
->mode
!= IMMED
)
749 && ! isvar (&opP
->disp
)
750 && ! expr8 (&opP
->disp
))
753 && ! isvar (&opP
->disp
)
754 && ! expr16 (&opP
->disp
))
760 if (opP
->mode
!= IMMED
)
765 if (opP
->mode
== AREG
766 || opP
->mode
== CONTROL
767 || opP
->mode
== FPREG
768 || opP
->mode
== IMMED
769 || opP
->mode
== REGLST
770 || (opP
->mode
!= ABSL
772 || opP
->reg
== ZPC
)))
777 if (opP
->mode
== CONTROL
778 || opP
->mode
== FPREG
779 || opP
->mode
== REGLST
780 || (opP
->mode
!= ABSL
781 && opP
->mode
!= IMMED
783 || opP
->reg
== ZPC
)))
811 if (opP
->mode
== CONTROL
812 || opP
->mode
== FPREG
813 || opP
->mode
== REGLST
)
818 if (opP
->mode
!= AINC
)
823 if (opP
->mode
!= ADEC
)
873 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
894 case '~': /* For now! (JF FOO is this right?) */
916 if (opP
->mode
!= CONTROL
917 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
922 if (opP
->mode
!= AREG
)
927 if (opP
->mode
!= AINDR
)
932 if (opP
->mode
!= ABSL
934 && strncmp (instring
, "jbsr", 4) == 0))
939 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
944 if (opP
->mode
!= DISP
951 if (opP
->mode
!= DREG
)
956 if (opP
->mode
!= FPREG
)
961 if (opP
->mode
!= CONTROL
968 if (opP
->mode
!= CONTROL
970 || opP
->reg
> last_movec_reg
)
974 const enum m68k_register
*rp
;
975 for (rp
= control_regs
; *rp
; rp
++)
984 if (opP
->mode
!= IMMED
)
990 if (opP
->mode
== DREG
992 || opP
->mode
== FPREG
)
1001 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1004 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1007 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1015 else if (opP
->mode
== CONTROL
)
1024 opP
->mask
= 1 << 24;
1027 opP
->mask
= 1 << 25;
1030 opP
->mask
= 1 << 26;
1039 else if (opP
->mode
!= REGLST
)
1041 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
1043 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
1048 if (opP
->mode
!= IMMED
)
1050 else if (! expr8 (&opP
->disp
))
1055 if (opP
->mode
!= DREG
&& opP
->mode
!= IMMED
)
1060 if (opP
->mode
!= IMMED
)
1062 else if (! expr8 (&opP
->disp
)
1063 || opP
->disp
.exp
.X_add_number
< 1
1064 || opP
->disp
.exp
.X_add_number
> 8)
1069 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1074 if (opP
->mode
!= AINDR
1075 && (opP
->mode
!= BASE
1077 && opP
->reg
!= ZADDR0
)
1078 || opP
->disp
.exp
.X_op
!= O_absent
1079 || ((opP
->index
.reg
< DATA0
1080 || opP
->index
.reg
> DATA7
)
1081 && (opP
->index
.reg
< ADDR0
1082 || opP
->index
.reg
> ADDR7
))
1083 || opP
->index
.size
!= SIZE_UNSPEC
1084 || opP
->index
.scale
!= 1))
1089 if (opP
->mode
!= CONTROL
1090 || ! (opP
->reg
== FPI
1092 || opP
->reg
== FPC
))
1097 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
1102 if (opP
->mode
!= IMMED
)
1104 else if (! expr8 (&opP
->disp
)
1105 || opP
->disp
.exp
.X_add_number
< 0
1106 || opP
->disp
.exp
.X_add_number
> 7)
1111 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
1115 /* JF these are out of order. We could put them
1116 in order if we were willing to put up with
1117 bunches of #ifdef m68851s in the code.
1119 Don't forget that you need these operands
1120 to use 68030 MMU instructions. */
1122 /* Memory addressing mode used by pflushr */
1124 if (opP
->mode
== CONTROL
1125 || opP
->mode
== FPREG
1126 || opP
->mode
== DREG
1127 || opP
->mode
== AREG
1128 || opP
->mode
== REGLST
)
1133 if (opP
->mode
!= CONTROL
1134 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1139 if (opP
->mode
!= CONTROL
1149 if (opP
->mode
!= CONTROL
1155 if (opP
->mode
!= CONTROL
1158 && opP
->reg
!= CRP
))
1163 if (opP
->mode
!= CONTROL
1164 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
1165 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
1170 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
1175 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
1180 if (opP
->mode
!= CONTROL
1187 } /* not a cache specifier. */
1191 if (opP
->mode
!= ABSL
)
1197 } /* switch on type of operand */
1201 } /* for each operand */
1202 } /* if immediately wrong */
1209 opcode
= opcode
->m_next
;
1214 && !(ok_arch
& current_architecture
))
1219 "invalid instruction for this architecture; needs ");
1220 cp
= buf
+ strlen (buf
);
1224 strcpy (cp
, "fpu (68040, 68060 or 68881/68882)");
1227 strcpy (cp
, "mmu (68030 or 68851)");
1230 strcpy (cp
, "68020 or higher");
1233 strcpy (cp
, "68000 or higher");
1236 strcpy (cp
, "68010 or higher");
1240 int got_one
= 0, idx
;
1241 for (idx
= 0; idx
< sizeof (archs
) / sizeof (archs
[0]);
1244 if (archs
[idx
].arch
& ok_arch
)
1248 strcpy (cp
, " or ");
1252 strcpy (cp
, archs
[idx
].name
);
1264 the_ins
.error
= "operands mismatch";
1266 } /* Fell off the end */
1271 /* now assemble it */
1273 the_ins
.args
= opcode
->m_operands
;
1274 the_ins
.numargs
= opcode
->m_opnum
;
1275 the_ins
.numo
= opcode
->m_codenum
;
1276 the_ins
.opcode
[0] = getone (opcode
);
1277 the_ins
.opcode
[1] = gettwo (opcode
);
1279 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
1281 /* This switch is a doozy.
1282 Watch the first step; its a big one! */
1303 tmpreg
= 0x3c; /* 7.4 */
1304 if (strchr ("bwl", s
[1]))
1305 nextword
= get_num (&opP
->disp
, 80);
1307 nextword
= get_num (&opP
->disp
, 0);
1308 if (isvar (&opP
->disp
))
1309 add_fix (s
[1], &opP
->disp
, 0, 0);
1313 if (!isbyte (nextword
))
1314 opP
->error
= "operand out of range";
1319 if (!isword (nextword
))
1320 opP
->error
= "operand out of range";
1325 addword (nextword
>> 16);
1352 /* We gotta put out some float */
1353 if (op (&opP
->disp
) != O_big
)
1358 /* Can other cases happen here? */
1359 if (op (&opP
->disp
) != O_constant
)
1362 val
= (valueT
) offs (&opP
->disp
);
1366 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
1367 val
>>= LITTLENUM_NUMBER_OF_BITS
;
1371 offs (&opP
->disp
) = gencnt
;
1373 if (offs (&opP
->disp
) > 0)
1375 if (offs (&opP
->disp
) > baseo
)
1377 as_warn ("Bignum too big for %c format; truncated",
1379 offs (&opP
->disp
) = baseo
;
1381 baseo
-= offs (&opP
->disp
);
1384 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
1385 offs (&opP
->disp
)--;
1390 gen_to_words (words
, baseo
, (long) outro
);
1391 for (wordp
= words
; baseo
--; wordp
++)
1395 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
1398 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
1401 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
1404 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
1407 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
1411 nextword
= get_num (&opP
->disp
, 80);
1412 /* Force into index mode. Hope this works */
1414 /* We do the first bit for 32-bit displacements, and the
1415 second bit for 16 bit ones. It is possible that we
1416 should make the default be WORD instead of LONG, but
1417 I think that'd break GCC, so we put up with a little
1418 inefficiency for the sake of working output. */
1420 if (!issword (nextword
)
1421 || (isvar (&opP
->disp
)
1422 && ((opP
->disp
.size
== SIZE_UNSPEC
1423 && flag_short_refs
== 0
1424 && cpu_of_arch (current_architecture
) >= m68020
)
1425 || opP
->disp
.size
== SIZE_LONG
)))
1428 tmpreg
= 0x3B; /* 7.3 */
1430 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
1431 if (isvar (&opP
->disp
))
1437 add_fix ('l', &opP
->disp
, 1, 2);
1438 addword (0), addword (0);
1440 add_frag (adds (&opP
->disp
),
1442 TAB (PCLEA
, SZ_UNDEF
));
1449 add_fix ('l', &opP
->disp
, 0, 0);
1454 addword (nextword
>> 16);
1459 tmpreg
= 0x3A; /* 7.2 */
1461 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
1463 if (isvar (&opP
->disp
))
1467 add_fix ('w', &opP
->disp
, 1, 0);
1470 add_fix ('w', &opP
->disp
, 0, 0);
1480 baseo
= get_num (&opP
->disp
, 80);
1481 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
1482 outro
= get_num (&opP
->odisp
, 80);
1483 /* Figure out the `addressing mode'.
1484 Also turn on the BASE_DISABLE bit, if needed. */
1485 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1487 tmpreg
= 0x3b; /* 7.3 */
1488 if (opP
->reg
== ZPC
)
1491 else if (opP
->reg
== 0)
1494 tmpreg
= 0x30; /* 6.garbage */
1496 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
1499 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
1502 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
1504 siz1
= opP
->disp
.size
;
1505 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
1506 siz2
= opP
->odisp
.size
;
1510 /* Index register stuff */
1511 if (opP
->index
.reg
!= 0
1512 && opP
->index
.reg
>= DATA
1513 && opP
->index
.reg
<= ADDR7
)
1515 nextword
|= (opP
->index
.reg
- DATA
) << 12;
1517 if (opP
->index
.size
== SIZE_UNSPEC
1518 || opP
->index
.size
== SIZE_LONG
)
1521 if (cpu_of_arch (current_architecture
) < m68020
)
1523 if (opP
->index
.scale
!= 1)
1526 "scale factor invalid on this architecture; needs 68020 or higher";
1530 switch (opP
->index
.scale
)
1547 GET US OUT OF HERE! */
1549 /* Must be INDEX, with an index register. Address
1550 register cannot be ZERO-PC, and either :b was
1551 forced, or we know it will fit. For a 68000 or
1552 68010, force this mode anyways, because the
1553 larger modes aren't supported. */
1554 if (opP
->mode
== BASE
1555 && ((opP
->reg
>= ADDR0
1556 && opP
->reg
<= ADDR7
)
1559 if (siz1
== SIZE_BYTE
1560 || cpu_of_arch (current_architecture
) < m68020
1561 || (siz1
== SIZE_UNSPEC
1562 && ! isvar (&opP
->disp
)
1563 && issbyte (baseo
)))
1565 nextword
+= baseo
& 0xff;
1567 if (isvar (&opP
->disp
))
1569 /* Do a byte relocation. If it doesn't
1570 fit (possible on m68000) let the
1571 fixup processing complain later. */
1573 add_fix ('B', &opP
->disp
, 1, 1);
1575 add_fix ('B', &opP
->disp
, 0, 0);
1577 else if (siz1
!= SIZE_BYTE
)
1579 if (siz1
!= SIZE_UNSPEC
)
1580 as_warn ("Forcing byte displacement");
1581 if (! issbyte (baseo
))
1582 opP
->error
= "byte displacement out of range";
1587 else if (siz1
== SIZE_UNSPEC
1589 && isvar (&opP
->disp
)
1590 && subs (&opP
->disp
) == NULL
)
1592 nextword
+= baseo
& 0xff;
1594 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
1595 TAB (PCINDEX
, SZ_UNDEF
));
1603 nextword
|= 0x40; /* No index reg */
1604 if (opP
->index
.reg
>= ZDATA0
1605 && opP
->index
.reg
<= ZDATA7
)
1606 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
1607 else if (opP
->index
.reg
>= ZADDR0
1608 || opP
->index
.reg
<= ZADDR7
)
1609 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
1612 /* It isn't simple. */
1614 if (cpu_of_arch (current_architecture
) < m68020
)
1616 "invalid operand mode for this architecture; needs 68020 or higher";
1619 /* If the guy specified a width, we assume that it is
1620 wide enough. Maybe it isn't. If so, we lose. */
1624 if (isvar (&opP
->disp
) || !issword (baseo
))
1629 else if (baseo
== 0)
1638 as_warn (":b not permitted; defaulting to :w");
1648 /* Figure out innner displacement stuff */
1649 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
1654 if (isvar (&opP
->odisp
) || !issword (outro
))
1659 else if (outro
== 0)
1668 as_warn (":b not permitted; defaulting to :w");
1677 if (opP
->mode
== POST
)
1682 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
1684 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1685 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
1687 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
1689 if (siz1
== SIZE_LONG
)
1690 addword (baseo
>> 16);
1691 if (siz1
!= SIZE_UNSPEC
)
1694 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
1695 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
1696 if (siz2
== SIZE_LONG
)
1697 addword (outro
>> 16);
1698 if (siz2
!= SIZE_UNSPEC
)
1704 nextword
= get_num (&opP
->disp
, 80);
1705 switch (opP
->disp
.size
)
1710 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
1712 tmpreg
= 0x38; /* 7.0 */
1716 /* Don't generate pc relative code on 68010 and
1718 if (isvar (&opP
->disp
)
1719 && !subs (&opP
->disp
)
1720 && adds (&opP
->disp
)
1721 && (S_GET_SEGMENT (adds (&opP
->disp
)) == text_section
)
1722 && now_seg
== text_section
1723 && cpu_of_arch (current_architecture
) >= m68020
1725 && !strchr ("~%&$?", s
[0]))
1727 tmpreg
= 0x3A; /* 7.2 */
1728 add_frag (adds (&opP
->disp
),
1730 TAB (PCREL
, SZ_UNDEF
));
1733 /* Fall through into long */
1735 if (isvar (&opP
->disp
))
1736 add_fix ('l', &opP
->disp
, 0, 0);
1738 tmpreg
= 0x39;/* 7.1 mode */
1739 addword (nextword
>> 16);
1743 case SIZE_WORD
: /* Word */
1744 if (isvar (&opP
->disp
))
1745 add_fix ('w', &opP
->disp
, 0, 0);
1747 tmpreg
= 0x38;/* 7.0 mode */
1755 as_bad ("unknown/incorrect operand");
1758 install_gen_operand (s
[1], tmpreg
);
1764 { /* JF: I hate floating point! */
1779 tmpreg
= get_num (&opP
->disp
, tmpreg
);
1780 if (isvar (&opP
->disp
))
1781 add_fix (s
[1], &opP
->disp
, 0, 0);
1784 case 'b': /* Danger: These do no check for
1785 certain types of overflow.
1787 if (!isbyte (tmpreg
))
1788 opP
->error
= "out of range";
1789 insop (tmpreg
, opcode
);
1790 if (isvar (&opP
->disp
))
1791 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
1794 if (!isword (tmpreg
))
1795 opP
->error
= "out of range";
1796 insop (tmpreg
, opcode
);
1797 if (isvar (&opP
->disp
))
1798 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
1801 /* Because of the way insop works, we put these two out
1803 insop (tmpreg
, opcode
);
1804 insop (tmpreg
>> 16, opcode
);
1805 if (isvar (&opP
->disp
))
1806 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
1812 install_operand (s
[1], tmpreg
);
1823 install_operand (s
[1], opP
->reg
- ADDR
);
1827 tmpreg
= get_num (&opP
->disp
, 80);
1831 add_fix ('B', &opP
->disp
, 1, -1);
1834 add_fix ('w', &opP
->disp
, 1, 0);
1839 if (cpu_of_arch (current_architecture
) < m68020
)
1840 as_warn ("Can't use long branches on 68000/68010");
1841 the_ins
.opcode
[the_ins
.numo
- 1] |= 0xff;
1842 add_fix ('l', &opP
->disp
, 1, 0);
1847 if (subs (&opP
->disp
)) /* We can't relax it */
1850 /* This could either be a symbol, or an absolute
1851 address. No matter, the frag hacking will finger it
1852 out. Not quite: it can't switch from BRANCH to
1853 BCC68000 for the case where opnd is absolute (it
1854 needs to use the 68000 hack since no conditional abs
1856 if (((cpu_of_arch (current_architecture
) < m68020
)
1857 || (0 == adds (&opP
->disp
)))
1858 && (the_ins
.opcode
[0] >= 0x6200)
1859 && (the_ins
.opcode
[0] <= 0x6f00))
1860 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
1861 TAB (BCC68000
, SZ_UNDEF
));
1863 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
1864 TAB (ABRANCH
, SZ_UNDEF
));
1867 if (isvar (&opP
->disp
))
1870 /* check for DBcc instruction */
1871 if ((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
1873 /* size varies if patch */
1874 /* needed for long form */
1875 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
1876 TAB (DBCC
, SZ_UNDEF
));
1880 add_fix ('w', &opP
->disp
, 1, 0);
1884 case 'C': /* Fixed size LONG coproc branches */
1885 add_fix ('l', &opP
->disp
, 1, 0);
1889 case 'c': /* Var size Coprocesssor branches */
1890 if (subs (&opP
->disp
))
1892 add_fix ('l', &opP
->disp
, 1, 0);
1893 add_frag ((symbolS
*) 0, (long) 0, TAB (FBRANCH
, LONG
));
1895 else if (adds (&opP
->disp
))
1896 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
1897 TAB (FBRANCH
, SZ_UNDEF
));
1900 /* add_frag((symbolS *) 0, offs(&opP->disp),
1901 TAB(FBRANCH,SHORT)); */
1902 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
1903 add_fix ('l', &opP
->disp
, 1, 0);
1913 case 'C': /* Ignore it */
1916 case 'd': /* JF this is a kludge */
1917 install_operand ('s', opP
->reg
- ADDR
);
1918 tmpreg
= get_num (&opP
->disp
, 80);
1919 if (!issword (tmpreg
))
1921 as_warn ("Expression out of range, using 0");
1928 install_operand (s
[1], opP
->reg
- DATA
);
1932 install_operand (s
[1], opP
->reg
- FP0
);
1936 tmpreg
= opP
->reg
- COP0
;
1937 install_operand (s
[1], tmpreg
);
1940 case 'J': /* JF foo */
2001 install_operand (s
[1], tmpreg
);
2005 tmpreg
= get_num (&opP
->disp
, 55);
2006 install_operand (s
[1], tmpreg
& 0x7f);
2013 if (tmpreg
& 0x7FF0000)
2014 as_bad ("Floating point register in register list");
2015 insop (reverse_16_bits (tmpreg
), opcode
);
2019 if (tmpreg
& 0x700FFFF)
2020 as_bad ("Wrong register in floating-point reglist");
2021 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
2029 if (tmpreg
& 0x7FF0000)
2030 as_bad ("Floating point register in register list");
2031 insop (tmpreg
, opcode
);
2033 else if (s
[1] == '8')
2035 if (tmpreg
& 0x0FFFFFF)
2036 as_bad ("incorrect register in reglist");
2037 install_operand (s
[1], tmpreg
>> 24);
2041 if (tmpreg
& 0x700FFFF)
2042 as_bad ("wrong register in floating-point reglist");
2044 install_operand (s
[1], tmpreg
>> 16);
2049 install_operand (s
[1], get_num (&opP
->disp
, 60));
2053 tmpreg
= ((opP
->mode
== DREG
)
2054 ? 0x20 + opP
->reg
- DATA
2055 : (get_num (&opP
->disp
, 40) & 0x1F));
2056 install_operand (s
[1], tmpreg
);
2060 tmpreg
= get_num (&opP
->disp
, 10);
2063 install_operand (s
[1], tmpreg
);
2067 /* This depends on the fact that ADDR registers are eight
2068 more than their corresponding DATA regs, so the result
2069 will have the ADDR_REG bit set */
2070 install_operand (s
[1], opP
->reg
- DATA
);
2074 if (opP
->mode
== AINDR
)
2075 install_operand (s
[1], opP
->reg
- DATA
);
2077 install_operand (s
[1], opP
->index
.reg
- DATA
);
2081 if (opP
->reg
== FPI
)
2083 else if (opP
->reg
== FPS
)
2085 else if (opP
->reg
== FPC
)
2089 install_operand (s
[1], tmpreg
);
2092 case 'S': /* Ignore it */
2096 install_operand (s
[1], get_num (&opP
->disp
, 30));
2099 case 'U': /* Ignore it */
2118 as_fatal ("failed sanity check");
2119 } /* switch on cache token */
2120 install_operand (s
[1], tmpreg
);
2123 /* JF: These are out of order, I fear. */
2136 install_operand (s
[1], tmpreg
);
2160 install_operand (s
[1], tmpreg
);
2164 if (opP
->reg
== VAL
)
2183 install_operand (s
[1], tmpreg
);
2197 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
2208 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
2214 install_operand (s
[1], tmpreg
);
2217 know (opP
->reg
== PSR
);
2220 know (opP
->reg
== PCSR
);
2235 install_operand (s
[1], tmpreg
);
2238 tmpreg
= get_num (&opP
->disp
, 20);
2239 install_operand (s
[1], tmpreg
);
2241 case '_': /* used only for move16 absolute 32-bit address */
2242 tmpreg
= get_num (&opP
->disp
, 80);
2243 addword (tmpreg
>> 16);
2244 addword (tmpreg
& 0xFFFF);
2251 /* By the time whe get here (FINALLY) the_ins contains the complete
2252 instruction, ready to be emitted. . . */
2256 reverse_16_bits (in
)
2262 static int mask
[16] =
2264 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2265 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2267 for (n
= 0; n
< 16; n
++)
2270 out
|= mask
[15 - n
];
2273 } /* reverse_16_bits() */
2282 static int mask
[8] =
2284 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2287 for (n
= 0; n
< 8; n
++)
2293 } /* reverse_8_bits() */
2295 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2296 (that value is chosen in the frag_var call in md_assemble). TYPE
2297 is the subtype of the frag to be generated; its primary type is
2298 rs_machine_dependent.
2300 The TYPE parameter is also used by md_convert_frag_1 and
2301 md_estimate_size_before_relax. The appropriate type of fixup will
2302 be emitted by md_convert_frag_1.
2304 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2306 install_operand (mode
, val
)
2313 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge */
2316 the_ins
.opcode
[0] |= val
<< 9;
2319 the_ins
.opcode
[1] |= val
<< 12;
2322 the_ins
.opcode
[1] |= val
<< 6;
2325 the_ins
.opcode
[1] |= val
;
2328 the_ins
.opcode
[2] |= val
<< 12;
2331 the_ins
.opcode
[2] |= val
<< 6;
2334 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2335 three words long! */
2337 the_ins
.opcode
[2] |= val
;
2340 the_ins
.opcode
[1] |= val
<< 7;
2343 the_ins
.opcode
[1] |= val
<< 10;
2347 the_ins
.opcode
[1] |= val
<< 5;
2352 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
2355 the_ins
.opcode
[1] |= (val
<< 12) | val
;
2358 the_ins
.opcode
[0] |= val
= 0xff;
2361 the_ins
.opcode
[0] |= val
<< 9;
2364 the_ins
.opcode
[1] |= val
;
2367 the_ins
.opcode
[1] |= val
;
2368 the_ins
.numo
++; /* What a hack */
2371 the_ins
.opcode
[1] |= val
<< 4;
2378 the_ins
.opcode
[0] |= (val
<< 6);
2381 the_ins
.opcode
[1] = (val
>> 16);
2382 the_ins
.opcode
[2] = val
& 0xffff;
2386 as_fatal ("failed sanity check.");
2388 } /* install_operand() */
2391 install_gen_operand (mode
, val
)
2398 the_ins
.opcode
[0] |= val
;
2401 /* This is a kludge!!! */
2402 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
2411 the_ins
.opcode
[0] |= val
;
2413 /* more stuff goes here */
2415 as_fatal ("failed sanity check.");
2417 } /* install_gen_operand() */
2420 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2421 * then deal with the bitfield hack.
2425 crack_operand (str
, opP
)
2427 register struct m68k_op
*opP
;
2429 register int parens
;
2431 register char *beg_str
;
2438 for (parens
= 0; *str
&& (parens
> 0 || notend (str
)); str
++)
2442 else if (*str
== ')')
2446 opP
->error
= "Extra )";
2452 if (!*str
&& parens
)
2454 opP
->error
= "Missing )";
2459 if (m68k_ip_op (beg_str
, opP
) != 0)
2466 c
= *++str
; /* JF bitfield hack */
2471 as_bad ("Missing operand");
2476 /* This is the guts of the machine-dependent assembler. STR points to a
2477 machine dependent instruction. This function is supposed to emit
2478 the frags/bytes it assembles to.
2482 insert_reg (regname
, regnum
)
2489 #ifdef REGISTER_PREFIX
2490 if (!flag_reg_prefix_optional
)
2492 buf
[0] = REGISTER_PREFIX
;
2493 strcpy (buf
+ 1, regname
);
2498 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
2499 &zero_address_frag
));
2501 for (i
= 0; regname
[i
]; i
++)
2502 buf
[i
] = islower (regname
[i
]) ? toupper (regname
[i
]) : regname
[i
];
2505 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
2506 &zero_address_frag
));
2515 static const struct init_entry init_table
[] =
2625 /* 68ec030 versions of same */
2628 /* 68ec030 access control unit, identical to 030 MMU status reg */
2631 /* Suppressed data and address registers. */
2656 for (i
= 0; init_table
[i
].name
; i
++)
2657 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
2660 static int no_68851
, no_68881
;
2663 /* a.out machine type. Default to 68020. */
2664 int m68k_aout_machtype
= 2;
2676 int shorts_this_frag
;
2679 memset ((char *) (&the_ins
), '\0', sizeof (the_ins
));
2684 for (n
= 0; n
< the_ins
.numargs
; n
++)
2685 if (the_ins
.operands
[n
].error
)
2687 er
= the_ins
.operands
[n
].error
;
2693 as_bad ("%s -- statement `%s' ignored", er
, str
);
2697 if (the_ins
.nfrag
== 0)
2699 /* No frag hacking involved; just put it out */
2700 toP
= frag_more (2 * the_ins
.numo
);
2701 fromP
= &the_ins
.opcode
[0];
2702 for (m
= the_ins
.numo
; m
; --m
)
2704 md_number_to_chars (toP
, (long) (*fromP
), 2);
2708 /* put out symbol-dependent info */
2709 for (m
= 0; m
< the_ins
.nrel
; m
++)
2711 switch (the_ins
.reloc
[m
].wid
)
2729 as_fatal ("Don't know how to figure width of %c in md_assemble()",
2730 the_ins
.reloc
[m
].wid
);
2733 fixP
= fix_new_exp (frag_now
,
2734 ((toP
- frag_now
->fr_literal
)
2735 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
2737 &the_ins
.reloc
[m
].exp
,
2738 the_ins
.reloc
[m
].pcrel
,
2740 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
2745 /* There's some frag hacking */
2746 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
2751 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
2753 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
2754 toP
= frag_more (wid
);
2756 shorts_this_frag
= 0;
2757 for (m
= wid
/ 2; m
; --m
)
2759 md_number_to_chars (toP
, (long) (*fromP
), 2);
2764 for (m
= 0; m
< the_ins
.nrel
; m
++)
2766 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
2768 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
2771 wid
= the_ins
.reloc
[m
].wid
;
2774 the_ins
.reloc
[m
].wid
= 0;
2775 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
2777 fixP
= fix_new_exp (frag_now
,
2778 ((toP
- frag_now
->fr_literal
)
2779 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
2781 &the_ins
.reloc
[m
].exp
,
2782 the_ins
.reloc
[m
].pcrel
,
2784 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
2786 (void) frag_var (rs_machine_dependent
, 10, 0,
2787 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
2788 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
2790 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
2791 shorts_this_frag
= 0;
2794 toP
= frag_more (n
* sizeof (short));
2797 md_number_to_chars (toP
, (long) (*fromP
), 2);
2803 for (m
= 0; m
< the_ins
.nrel
; m
++)
2807 wid
= the_ins
.reloc
[m
].wid
;
2810 the_ins
.reloc
[m
].wid
= 0;
2811 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
2813 fixP
= fix_new_exp (frag_now
,
2814 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
2815 - shorts_this_frag
* 2),
2817 &the_ins
.reloc
[m
].exp
,
2818 the_ins
.reloc
[m
].pcrel
,
2820 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
2828 * md_begin -- set up hash tables with 68000 instructions.
2829 * similar to what the vax assembler does. ---phr
2831 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
2832 a copy of it at runtime, adding in the information we want but isn't
2833 there. I think it'd be better to have an awk script hack the table
2834 at compile time. Or even just xstr the table and use it as-is. But
2835 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
2838 register const struct m68k_opcode
*ins
;
2839 register struct m68k_incant
*hack
, *slak
;
2840 register const char *retval
= 0; /* empty string, or error msg text */
2841 register unsigned int i
;
2845 flag_reg_prefix_optional
= 1;
2847 op_hash
= hash_new ();
2849 obstack_begin (&robyn
, 4000);
2850 for (i
= 0; i
< m68k_numopcodes
; i
++)
2852 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
2855 ins
= &m68k_opcodes
[i
];
2856 /* We *could* ignore insns that don't match our arch here
2857 but just leaving them out of the hash. */
2858 slak
->m_operands
= ins
->args
;
2859 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
2860 slak
->m_arch
= ins
->arch
;
2861 slak
->m_opcode
= ins
->opcode
;
2862 /* This is kludgey */
2863 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
2864 if (i
+ 1 != m68k_numopcodes
2865 && !strcmp (ins
->name
, m68k_opcodes
[i
+ 1].name
))
2867 slak
->m_next
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
2872 slak
= slak
->m_next
;
2876 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
2878 as_fatal ("Internal Error: Can't hash %s: %s", ins
->name
, retval
);
2881 for (i
= 0; i
< m68k_numaliases
; i
++)
2883 const char *name
= m68k_opcode_aliases
[i
].primary
;
2884 const char *alias
= m68k_opcode_aliases
[i
].alias
;
2885 PTR val
= hash_find (op_hash
, name
);
2887 as_fatal ("Internal Error: Can't find %s in hash table", name
);
2888 retval
= hash_insert (op_hash
, alias
, val
);
2890 as_fatal ("Internal Error: Can't hash %s: %s", alias
, retval
);
2893 for (i
= 0; i
< sizeof (mklower_table
); i
++)
2894 mklower_table
[i
] = (isupper (c
= (char) i
)) ? tolower (c
) : c
;
2896 for (i
= 0; i
< sizeof (notend_table
); i
++)
2898 notend_table
[i
] = 0;
2899 alt_notend_table
[i
] = 0;
2901 notend_table
[','] = 1;
2902 notend_table
['{'] = 1;
2903 notend_table
['}'] = 1;
2904 alt_notend_table
['a'] = 1;
2905 alt_notend_table
['A'] = 1;
2906 alt_notend_table
['d'] = 1;
2907 alt_notend_table
['D'] = 1;
2908 alt_notend_table
['#'] = 1;
2909 alt_notend_table
['&'] = 1;
2910 alt_notend_table
['f'] = 1;
2911 alt_notend_table
['F'] = 1;
2912 #ifdef REGISTER_PREFIX
2913 alt_notend_table
[REGISTER_PREFIX
] = 1;
2916 /* We need to put '(' in alt_notend_table to handle
2917 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
2919 alt_notend_table
['('] = 1;
2921 /* We need to put '@' in alt_notend_table to handle
2922 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
2924 alt_notend_table
['@'] = 1;
2926 #ifndef MIT_SYNTAX_ONLY
2927 /* Insert pseudo ops, these have to go into the opcode table since
2928 gas expects pseudo ops to start with a dot */
2931 while (mote_pseudo_table
[n
].poc_name
)
2933 hack
= (struct m68k_incant
*)
2934 obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
2935 hash_insert (op_hash
,
2936 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
2937 hack
->m_operands
= 0;
2948 m68k_init_after_args ()
2950 if (cpu_of_arch (current_architecture
) == 0)
2953 const char *default_cpu
= TARGET_CPU
;
2955 if (*default_cpu
== 'm')
2957 for (i
= 0; i
< n_archs
; i
++)
2958 if (strcasecmp (default_cpu
, archs
[i
].name
) == 0)
2962 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU
);
2963 current_architecture
|= m68020
;
2966 current_architecture
|= archs
[i
].arch
;
2968 /* Permit m68881 specification with all cpus; those that can't work
2969 with a coprocessor could be doing emulation. */
2970 if (current_architecture
& m68851
)
2972 if (current_architecture
& m68040
)
2974 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
2977 /* What other incompatibilities could we check for? */
2979 /* Toss in some default assumptions about coprocessors. */
2981 && (cpu_of_arch (current_architecture
)
2982 /* Can CPU32 have a 68881 coprocessor?? */
2983 & (m68020
| m68030
| cpu32
)))
2985 current_architecture
|= m68881
;
2988 && (cpu_of_arch (current_architecture
) & m68020up
) != 0
2989 && (cpu_of_arch (current_architecture
) & m68040up
) == 0)
2991 current_architecture
|= m68851
;
2993 if (no_68881
&& (current_architecture
& m68881
))
2994 as_bad ("options for 68881 and no-68881 both given");
2995 if (no_68851
&& (current_architecture
& m68851
))
2996 as_bad ("options for 68851 and no-68851 both given");
2999 /* Work out the magic number. This isn't very general. */
3000 if (current_architecture
& m68000
)
3001 m68k_aout_machtype
= 0;
3002 else if (current_architecture
& m68010
)
3003 m68k_aout_machtype
= 1;
3004 else if (current_architecture
& m68020
)
3005 m68k_aout_machtype
= 2;
3007 m68k_aout_machtype
= 2;
3010 /* Note which set of "movec" control registers is available. */
3011 switch (cpu_of_arch (current_architecture
))
3014 control_regs
= m68000_control_regs
;
3017 control_regs
= m68010_control_regs
;
3021 control_regs
= m68020_control_regs
;
3024 control_regs
= m68040_control_regs
;
3027 control_regs
= m68060_control_regs
;
3030 control_regs
= cpu32_control_regs
;
3036 if (cpu_of_arch (current_architecture
) < m68020
)
3037 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
3040 /* Equal to MAX_PRECISION in atof-ieee.c */
3041 #define MAX_LITTLENUMS 6
3043 /* Turn a string in input_line_pointer into a floating point constant
3044 of type type, and store the appropriate bytes in *litP. The number
3045 of LITTLENUMS emitted is stored in *sizeP . An error message is
3046 returned, or NULL on OK. */
3049 md_atof (type
, litP
, sizeP
)
3055 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3056 LITTLENUM_TYPE
*wordP
;
3088 return "Bad call to MD_ATOF()";
3090 t
= atof_ieee (input_line_pointer
, type
, words
);
3092 input_line_pointer
= t
;
3094 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
3095 for (wordP
= words
; prec
--;)
3097 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
3098 litP
+= sizeof (LITTLENUM_TYPE
);
3104 md_number_to_chars (buf
, val
, n
)
3109 number_to_chars_bigendian (buf
, val
, n
);
3113 md_apply_fix_2 (fixP
, val
)
3117 addressT upper_limit
;
3118 offsetT lower_limit
;
3120 /* This is unnecessary but it convinces the native rs6000 compiler
3121 to generate the code we want. */
3122 char *buf
= fixP
->fx_frag
->fr_literal
;
3123 buf
+= fixP
->fx_where
;
3124 /* end ibm compiler workaround */
3126 if (val
& 0x80000000)
3127 val
|= ~(addressT
)0x7fffffff;
3131 switch (fixP
->fx_size
)
3133 /* The cast to offsetT below are necessary to make code correct for
3134 machines where ints are smaller than offsetT */
3138 lower_limit
= - (offsetT
) 0x80;
3141 *buf
++ = (val
>> 8);
3143 upper_limit
= 0x7fff;
3144 lower_limit
= - (offsetT
) 0x8000;
3147 *buf
++ = (val
>> 24);
3148 *buf
++ = (val
>> 16);
3149 *buf
++ = (val
>> 8);
3151 upper_limit
= 0x7fffffff;
3152 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* avoid constant overflow */
3155 BAD_CASE (fixP
->fx_size
);
3158 /* For non-pc-relative values, it's conceivable we might get something
3159 like "0xff" for a byte field. So extend the upper part of the range
3160 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3161 so that we can do any range checking at all. */
3162 if (!fixP
->fx_pcrel
)
3163 upper_limit
= upper_limit
* 2 + 1;
3165 if ((addressT
) val
> upper_limit
3166 && (val
> 0 || val
< lower_limit
))
3167 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "value out of range");
3169 /* A one byte PC-relative reloc means a short branch. We can't use
3170 a short branch with a value of 0 or -1, because those indicate
3171 different opcodes (branches with longer offsets). */
3173 && fixP
->fx_size
== 1
3174 && (fixP
->fx_addsy
== NULL
3175 || S_IS_DEFINED (fixP
->fx_addsy
))
3176 && (val
== 0 || val
== -1))
3177 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "invalid byte branch offset");
3180 #ifdef BFD_ASSEMBLER
3182 md_apply_fix (fixP
, valp
)
3186 md_apply_fix_2 (fixP
, (addressT
) *valp
);
3190 void md_apply_fix (fixP
, val
)
3194 md_apply_fix_2 (fixP
, (addressT
) val
);
3198 /* *fragP has been relaxed to its final size, and now needs to have
3199 the bytes inside it modified to conform to the new size There is UGLY
3203 md_convert_frag_1 (fragP
)
3204 register fragS
*fragP
;
3210 /* Address in object code of the displacement. */
3211 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
3213 /* Address in gas core of the place to store the displacement. */
3214 /* This convinces the native rs6000 compiler to generate the code we
3216 register char *buffer_address
= fragP
->fr_literal
;
3217 buffer_address
+= fragP
->fr_fix
;
3218 /* end ibm compiler workaround */
3220 /* The displacement of the address, from current location. */
3221 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
3222 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
3224 #ifdef BFD_ASSEMBLER
3225 disp
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
3228 switch (fragP
->fr_subtype
)
3230 case TAB (BCC68000
, BYTE
):
3231 case TAB (ABRANCH
, BYTE
):
3232 know (issbyte (disp
));
3234 as_bad ("short branch with zero offset: use :w");
3235 fragP
->fr_opcode
[1] = disp
;
3238 case TAB (DBCC
, SHORT
):
3239 know (issword (disp
));
3242 case TAB (BCC68000
, SHORT
):
3243 case TAB (ABRANCH
, SHORT
):
3244 know (issword (disp
));
3245 fragP
->fr_opcode
[1] = 0x00;
3248 case TAB (ABRANCH
, LONG
):
3249 if (cpu_of_arch (current_architecture
) < m68020
)
3251 if (fragP
->fr_opcode
[0] == 0x61)
3254 fragP
->fr_opcode
[0] = 0x4E;
3255 fragP
->fr_opcode
[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3256 subseg_change (text_section
, 0); /* @@ */
3270 else if (fragP
->fr_opcode
[0] == 0x60)
3272 fragP
->fr_opcode
[0] = 0x4E;
3273 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3274 subseg_change (text_section
, 0); /* @@ */
3275 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
3276 fragP
->fr_offset
, 0, NO_RELOC
);
3282 as_bad ("Long branch offset not supported.");
3287 fragP
->fr_opcode
[1] = (char) 0xff;
3291 case TAB (BCC68000
, LONG
):
3292 /* only Bcc 68000 instructions can come here */
3293 /* change bcc into b!cc/jmp absl long */
3294 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
3295 fragP
->fr_opcode
[1] = 0x6;/* branch offset = 6 */
3297 /* JF: these used to be fr_opcode[2,3], but they may be in a
3298 different frag, in which case refering to them is a no-no.
3299 Only fr_opcode[0,1] are guaranteed to work. */
3300 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
3301 *buffer_address
++ = (char) 0xf9;
3302 fragP
->fr_fix
+= 2; /* account for jmp instruction */
3303 subseg_change (text_section
, 0);
3304 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
3305 fragP
->fr_offset
, 0, NO_RELOC
);
3309 case TAB (DBCC
, LONG
):
3310 /* only DBcc 68000 instructions can come here */
3311 /* change dbcc into dbcc/jmp absl long */
3312 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3313 *buffer_address
++ = 0x00; /* branch offset = 4 */
3314 *buffer_address
++ = 0x04;
3315 *buffer_address
++ = 0x60; /* put in bra pc+6 */
3316 *buffer_address
++ = 0x06;
3317 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
3318 *buffer_address
++ = (char) 0xf9;
3320 fragP
->fr_fix
+= 6; /* account for bra/jmp instructions */
3321 subseg_change (text_section
, 0);
3322 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
3323 fragP
->fr_offset
, 0, NO_RELOC
);
3327 case TAB (FBRANCH
, SHORT
):
3328 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
3331 case TAB (FBRANCH
, LONG
):
3332 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit */
3335 case TAB (PCREL
, SHORT
):
3338 case TAB (PCREL
, LONG
):
3339 /* The thing to do here is force it to ABSOLUTE LONG, since
3340 PCREL is really trying to shorten an ABSOLUTE address anyway */
3341 /* JF FOO This code has not been tested */
3342 subseg_change (text_section
, 0);
3343 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
3345 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
3346 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3347 (unsigned) fragP
->fr_opcode
[0],
3348 (unsigned long) fragP
->fr_address
);
3349 fragP
->fr_opcode
[1] &= ~0x3F;
3350 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
3354 case TAB (PCLEA
, SHORT
):
3355 subseg_change (text_section
, 0);
3356 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
3357 fragP
->fr_offset
, 1, NO_RELOC
);
3358 fragP
->fr_opcode
[1] &= ~0x3F;
3359 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
3362 case TAB (PCLEA
, LONG
):
3363 subseg_change (text_section
, 0);
3364 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
) + 2, 4, fragP
->fr_symbol
,
3365 fragP
->fr_offset
, 1, NO_RELOC
);
3366 fixP
->fx_pcrel_adjust
= 2;
3367 /* Already set to mode 7.3; this indicates: PC indirect with
3368 suppressed index, 32-bit displacement. */
3369 *buffer_address
++ = 0x01;
3370 *buffer_address
++ = 0x70;
3375 case TAB (PCINDEX
, BYTE
):
3377 if (!issbyte (disp
))
3379 as_bad ("displacement doesn't fit in one byte");
3382 assert (fragP
->fr_fix
>= 2);
3383 buffer_address
[-2] &= ~1;
3384 buffer_address
[-1] = disp
;
3387 case TAB (PCINDEX
, SHORT
):
3388 subseg_change (text_section
, 0);
3390 assert (issword (disp
));
3391 assert (fragP
->fr_fix
>= 2);
3392 buffer_address
[-2] |= 0x1;
3393 buffer_address
[-1] = 0x20;
3394 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
3395 fragP
->fr_offset
, (fragP
->fr_opcode
[1] & 077) == 073,
3397 fixP
->fx_pcrel_adjust
= 2;
3400 case TAB (PCINDEX
, LONG
):
3401 subseg_change (text_section
, 0);
3403 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
3404 fragP
->fr_offset
, (fragP
->fr_opcode
[1] & 077) == 073,
3406 fixP
->fx_pcrel_adjust
= 2;
3407 assert (fragP
->fr_fix
>= 2);
3408 buffer_address
[-2] |= 0x1;
3409 buffer_address
[-1] = 0x30;
3416 md_number_to_chars (buffer_address
, (long) disp
, (int) ext
);
3417 fragP
->fr_fix
+= ext
;
3421 #ifndef BFD_ASSEMBLER
3424 md_convert_frag (headers
, sec
, fragP
)
3425 object_headers
*headers
;
3429 md_convert_frag_1 (fragP
);
3435 md_convert_frag (abfd
, sec
, fragP
)
3440 md_convert_frag_1 (fragP
);
3444 /* Force truly undefined symbols to their maximum size, and generally set up
3445 the frag list to be relaxed
3448 md_estimate_size_before_relax (fragP
, segment
)
3449 register fragS
*fragP
;
3453 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
3455 old_fix
= fragP
->fr_fix
;
3457 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3458 switch (fragP
->fr_subtype
)
3461 case TAB (ABRANCH
, SZ_UNDEF
):
3463 if ((fragP
->fr_symbol
!= NULL
) /* Not absolute */
3464 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
3466 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
3469 else if ((fragP
->fr_symbol
== 0) || (cpu_of_arch (current_architecture
) < m68020
))
3471 /* On 68000, or for absolute value, switch to abs long */
3472 /* FIXME, we should check abs val, pick short or long */
3473 if (fragP
->fr_opcode
[0] == 0x61)
3475 fragP
->fr_opcode
[0] = 0x4E;
3476 fragP
->fr_opcode
[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3477 subseg_change (text_section
, 0);
3478 fix_new (fragP
, fragP
->fr_fix
, 4,
3479 fragP
->fr_symbol
, fragP
->fr_offset
, 0, NO_RELOC
);
3483 else if (fragP
->fr_opcode
[0] == 0x60)
3485 fragP
->fr_opcode
[0] = 0x4E;
3486 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3487 subseg_change (text_section
, 0);
3488 fix_new (fragP
, fragP
->fr_fix
, 4,
3489 fragP
->fr_symbol
, fragP
->fr_offset
, 0, NO_RELOC
);
3495 as_warn ("Long branch offset to extern symbol not supported.");
3499 { /* Symbol is still undefined. Make it simple */
3500 fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
3501 fragP
->fr_offset
, 1, NO_RELOC
);
3503 fragP
->fr_opcode
[1] = (char) 0xff;
3509 } /* case TAB(ABRANCH,SZ_UNDEF) */
3511 case TAB (FBRANCH
, SZ_UNDEF
):
3513 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
|| flag_short_refs
)
3515 fragP
->fr_subtype
= TAB (FBRANCH
, SHORT
);
3520 fix_new (fragP
, (int) fragP
->fr_fix
, 4, fragP
->fr_symbol
,
3521 fragP
->fr_offset
, 1, NO_RELOC
);
3523 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit */
3527 } /* TAB(FBRANCH,SZ_UNDEF) */
3529 case TAB (PCREL
, SZ_UNDEF
):
3531 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
3533 || cpu_of_arch (current_architecture
) < m68020
)
3535 fragP
->fr_subtype
= TAB (PCREL
, SHORT
);
3540 fragP
->fr_subtype
= TAB (PCREL
, LONG
);
3544 } /* TAB(PCREL,SZ_UNDEF) */
3546 case TAB (BCC68000
, SZ_UNDEF
):
3548 if ((fragP
->fr_symbol
!= NULL
)
3549 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
3551 fragP
->fr_subtype
= TAB (BCC68000
, BYTE
);
3554 /* only Bcc 68000 instructions can come here */
3555 /* change bcc into b!cc/jmp absl long */
3556 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
3557 if (flag_short_refs
)
3559 fragP
->fr_opcode
[1] = 0x04; /* branch offset = 6 */
3560 /* JF: these were fr_opcode[2,3] */
3561 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
3562 buffer_address
[1] = (char) 0xf8;
3563 fragP
->fr_fix
+= 2; /* account for jmp instruction */
3564 subseg_change (text_section
, 0);
3565 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3566 fragP
->fr_offset
, 0, NO_RELOC
);
3571 fragP
->fr_opcode
[1] = 0x06; /* branch offset = 6 */
3572 /* JF: these were fr_opcode[2,3] */
3573 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
3574 buffer_address
[1] = (char) 0xf9;
3575 fragP
->fr_fix
+= 2; /* account for jmp instruction */
3576 subseg_change (text_section
, 0);
3577 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
3578 fragP
->fr_offset
, 0, NO_RELOC
);
3583 } /* case TAB(BCC68000,SZ_UNDEF) */
3585 case TAB (DBCC
, SZ_UNDEF
):
3587 if (fragP
->fr_symbol
!= NULL
&& S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
3589 fragP
->fr_subtype
= TAB (DBCC
, SHORT
);
3593 /* only DBcc 68000 instructions can come here */
3594 /* change dbcc into dbcc/jmp absl long */
3595 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3596 buffer_address
[0] = 0x00; /* branch offset = 4 */
3597 buffer_address
[1] = 0x04;
3598 buffer_address
[2] = 0x60; /* put in bra pc + ... */
3600 if (flag_short_refs
)
3602 /* JF: these were fr_opcode[5-7] */
3603 buffer_address
[3] = 0x04; /* plus 4 */
3604 buffer_address
[4] = 0x4e; /* Put in Jump Word */
3605 buffer_address
[5] = (char) 0xf8;
3606 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
3607 subseg_change (text_section
, 0);
3608 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3609 fragP
->fr_offset
, 0, NO_RELOC
);
3614 /* JF: these were fr_opcode[5-7] */
3615 buffer_address
[3] = 0x06; /* Plus 6 */
3616 buffer_address
[4] = 0x4e; /* put in jmp long (0x4ef9) */
3617 buffer_address
[5] = (char) 0xf9;
3618 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
3619 subseg_change (text_section
, 0);
3620 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
3621 fragP
->fr_offset
, 0, NO_RELOC
);
3627 } /* case TAB(DBCC,SZ_UNDEF) */
3629 case TAB (PCLEA
, SZ_UNDEF
):
3631 if ((S_GET_SEGMENT (fragP
->fr_symbol
)) == segment
3633 || cpu_of_arch (current_architecture
) < m68020
)
3635 fragP
->fr_subtype
= TAB (PCLEA
, SHORT
);
3640 fragP
->fr_subtype
= TAB (PCLEA
, LONG
);
3644 } /* TAB(PCLEA,SZ_UNDEF) */
3646 case TAB (PCINDEX
, SZ_UNDEF
):
3647 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
3648 || cpu_of_arch (current_architecture
) < m68020
)
3650 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
3654 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
3663 /* now that SZ_UNDEF are taken care of, check others */
3664 switch (fragP
->fr_subtype
)
3666 case TAB (BCC68000
, BYTE
):
3667 case TAB (ABRANCH
, BYTE
):
3668 /* We can't do a short jump to the next instruction,
3669 so we force word mode. */
3670 if (fragP
->fr_symbol
&& S_GET_VALUE (fragP
->fr_symbol
) == 0 &&
3671 fragP
->fr_symbol
->sy_frag
== fragP
->fr_next
)
3673 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
3680 return fragP
->fr_var
+ fragP
->fr_fix
- old_fix
;
3683 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3684 /* the bit-field entries in the relocation_info struct plays hell
3685 with the byte-order problems of cross-assembly. So as a hack,
3686 I added this mach. dependent ri twiddler. Ugly, but it gets
3688 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3689 are symbolnum, most sig. byte first. Last byte is broken up with
3690 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3691 nibble as nuthin. (on Sun 3 at least) */
3692 /* Translate the internal relocation information into target-specific
3696 md_ri_to_chars (the_bytes
, ri
)
3698 struct reloc_info_generic
*ri
;
3701 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
3702 /* now the fun stuff */
3703 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
3704 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
3705 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
3706 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80) | ((ri
->r_length
<< 5) & 0x60) |
3707 ((ri
->r_extern
<< 4) & 0x10));
3710 #endif /* comment */
3712 #ifndef BFD_ASSEMBLER
3714 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
3717 relax_addressT segment_address_in_file
;
3720 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3721 * Out: GNU LD relocation length code: 0, 1, or 2.
3724 static CONST
unsigned char nbytes_r_length
[] = {42, 0, 1, 42, 2};
3727 know (fixP
->fx_addsy
!= NULL
);
3729 md_number_to_chars (where
,
3730 fixP
->fx_frag
->fr_address
+ fixP
->fx_where
- segment_address_in_file
,
3733 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
3734 ? S_GET_TYPE (fixP
->fx_addsy
)
3735 : fixP
->fx_addsy
->sy_number
);
3737 where
[4] = (r_symbolnum
>> 16) & 0x0ff;
3738 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
3739 where
[6] = r_symbolnum
& 0x0ff;
3740 where
[7] = (((fixP
->fx_pcrel
<< 7) & 0x80) | ((nbytes_r_length
[fixP
->fx_size
] << 5) & 0x60) |
3741 (((!S_IS_DEFINED (fixP
->fx_addsy
)) << 4) & 0x10));
3745 #endif /* OBJ_AOUT or OBJ_BOUT */
3747 #ifndef WORKING_DOT_WORD
3748 CONST
int md_short_jump_size
= 4;
3749 CONST
int md_long_jump_size
= 6;
3752 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3754 addressT from_addr
, to_addr
;
3760 offset
= to_addr
- (from_addr
+ 2);
3762 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
3763 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
3767 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3769 addressT from_addr
, to_addr
;
3775 if (cpu_of_arch (current_architecture
) < m68020
)
3777 offset
= to_addr
- S_GET_VALUE (to_symbol
);
3778 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
3779 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
3780 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
3785 offset
= to_addr
- (from_addr
+ 2);
3786 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
3787 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
3793 /* Different values of OK tell what its OK to return. Things that
3794 aren't OK are an error (what a shock, no?)
3797 10: Absolute 1:8 only
3798 20: Absolute 0:7 only
3799 30: absolute 0:15 only
3800 40: Absolute 0:31 only
3801 50: absolute 0:127 only
3802 55: absolute -64:63 only
3803 60: absolute -128:127 only
3804 70: absolute 0:4095 only
3811 struct m68k_exp
*exp
;
3814 if (exp
->exp
.X_op
== O_absent
)
3816 /* Do the same thing the VAX asm does */
3817 op (exp
) = O_constant
;
3823 as_warn ("expression out of range: defaulting to 1");
3827 else if (exp
->exp
.X_op
== O_constant
)
3832 if (offs (exp
) < 1 || offs (exp
) > 8)
3834 as_warn ("expression out of range: defaulting to 1");
3839 if (offs (exp
) < 0 || offs (exp
) > 7)
3843 if (offs (exp
) < 0 || offs (exp
) > 15)
3847 if (offs (exp
) < 0 || offs (exp
) > 32)
3851 if (offs (exp
) < 0 || offs (exp
) > 127)
3855 if (offs (exp
) < -64 || offs (exp
) > 63)
3859 if (offs (exp
) < -128 || offs (exp
) > 127)
3863 if (offs (exp
) < 0 || offs (exp
) > 4095)
3866 as_warn ("expression out of range: defaulting to 0");
3874 else if (exp
->exp
.X_op
== O_big
)
3876 if (offs (exp
) <= 0 /* flonum */
3877 && (ok
== 80 /* no bignums */
3878 || (ok
> 10 /* small-int ranges including 0 ok */
3879 /* If we have a flonum zero, a zero integer should
3880 do as well (e.g., in moveq). */
3881 && generic_floating_point_number
.exponent
== 0
3882 && generic_floating_point_number
.low
[0] == 0)))
3884 /* HACK! Turn it into a long */
3885 LITTLENUM_TYPE words
[6];
3887 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
3888 op (exp
) = O_constant
;
3891 offs (exp
) = words
[1] | (words
[0] << 16);
3895 op (exp
) = O_constant
;
3898 offs (exp
) = (ok
== 10) ? 1 : 0;
3899 as_warn ("Can't deal with expression; defaulting to %ld",
3905 if (ok
>= 10 && ok
<= 70)
3907 op (exp
) = O_constant
;
3910 offs (exp
) = (ok
== 10) ? 1 : 0;
3911 as_warn ("Can't deal with expression; defaulting to %ld",
3916 if (exp
->size
!= SIZE_UNSPEC
)
3924 if (!isbyte (offs (exp
)))
3925 as_warn ("expression doesn't fit in BYTE");
3928 if (!isword (offs (exp
)))
3929 as_warn ("expression doesn't fit in WORD");
3937 /* These are the back-ends for the various machine dependent pseudo-ops. */
3938 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
3944 subseg_set (data_section
, 1);
3945 demand_empty_rest_of_line ();
3952 subseg_set (data_section
, 2);
3953 demand_empty_rest_of_line ();
3960 /* We don't support putting frags in the BSS segment, we fake it
3961 by marking in_bss, then looking at s_skip for clues. */
3963 subseg_set (bss_section
, 0);
3964 demand_empty_rest_of_line ();
3972 register long temp_fill
;
3974 temp
= 1; /* JF should be 2? */
3975 temp_fill
= get_absolute_expression ();
3976 if (!need_pass_2
) /* Never make frag if expect extra pass. */
3977 frag_align (temp
, (int) temp_fill
);
3978 demand_empty_rest_of_line ();
3985 demand_empty_rest_of_line ();
3988 /* Pseudo-ops handled for MRI compatibility. */
3990 /* Handle an MRI style chip specification. */
3999 s
= input_line_pointer
;
4000 c
= get_symbol_end ();
4001 for (i
= 0; i
< n_archs
; i
++)
4002 if (strcasecmp (s
, archs
[i
].name
) == 0)
4006 as_bad ("%s: unrecognized processor name", s
);
4007 *input_line_pointer
= c
;
4008 ignore_rest_of_line ();
4011 *input_line_pointer
= c
;
4013 if (*input_line_pointer
== '/')
4014 current_architecture
= 0;
4016 current_architecture
&= m68881
| m68851
;
4017 current_architecture
|= archs
[i
].arch
;
4019 while (*input_line_pointer
== '/')
4021 ++input_line_pointer
;
4022 s
= input_line_pointer
;
4023 c
= get_symbol_end ();
4024 if (strcmp (s
, "68881") == 0)
4025 current_architecture
|= m68881
;
4026 else if (strcmp (s
, "68851") == 0)
4027 current_architecture
|= m68851
;
4028 *input_line_pointer
= c
;
4032 /* The MRI CHIP pseudo-op. */
4039 demand_empty_rest_of_line ();
4042 /* The MRI FOPT pseudo-op. */
4050 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
4054 input_line_pointer
+= 3;
4055 temp
= get_absolute_expression ();
4056 if (temp
< 0 || temp
> 7)
4057 as_bad ("bad coprocessor id");
4059 m68k_float_copnum
= COP0
+ temp
;
4063 as_bad ("unrecognized fopt option");
4064 ignore_rest_of_line ();
4068 demand_empty_rest_of_line ();
4073 * Invocation line includes a switch not recognized by the base assembler.
4074 * See if it's a processor-specific option. These are:
4076 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4077 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4078 * Select the architecture. Instructions or features not
4079 * supported by the selected architecture cause fatal
4080 * errors. More than one may be specified. The default is
4081 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4082 * for -m68000, and -m68882 is a synonym for -m68881.
4083 * -[A]m[c]no-68851, -[A]m[c]no-68881
4084 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4085 * so don't use or document it, but that's the way the parsing
4088 * -pic Indicates PIC.
4089 * -k Indicates PIC. (Sun 3 only.)
4094 CONST
char *md_shortopts
= "lSA:m:kQ:V";
4096 CONST
char *md_shortopts
= "lSA:m:k";
4099 struct option md_longopts
[] = {
4100 #define OPTION_PIC (OPTION_MD_BASE)
4101 {"pic", no_argument
, NULL
, OPTION_PIC
},
4102 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
4103 {"register-prefix-optional", no_argument
, NULL
,
4104 OPTION_REGISTER_PREFIX_OPTIONAL
},
4105 {NULL
, no_argument
, NULL
, 0}
4107 size_t md_longopts_size
= sizeof(md_longopts
);
4110 md_parse_option (c
, arg
)
4116 case 'l': /* -l means keep external to 2 bit offset
4117 rather than 16 bit one */
4118 flag_short_refs
= 1;
4121 case 'S': /* -S means that jbsr's always turn into
4123 flag_long_jumps
= 1;
4129 /* intentional fall-through */
4132 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
4136 const char *oarg
= arg
;
4142 if (arg
[0] == 'c' && arg
[1] == '6')
4145 for (i
= 0; i
< n_archs
; i
++)
4146 if (!strcmp (arg
, archs
[i
].name
))
4151 as_bad ("unrecognized option `%s'", oarg
);
4154 arch
= archs
[i
].arch
;
4157 else if (arch
== m68851
)
4166 if (arg
[0] == 'c' && arg
[1] == '6')
4169 for (i
= 0; i
< n_archs
; i
++)
4170 if (!strcmp (arg
, archs
[i
].name
))
4172 unsigned long arch
= archs
[i
].arch
;
4173 if (cpu_of_arch (arch
))
4174 /* It's a cpu spec. */
4176 current_architecture
&= ~m68000up
;
4177 current_architecture
|= arch
;
4179 else if (arch
== m68881
)
4181 current_architecture
|= m68881
;
4184 else if (arch
== m68851
)
4186 current_architecture
|= m68851
;
4196 as_bad ("unrecognized architecture specification `%s'", arg
);
4205 break; /* -pic, Position Independent Code */
4207 case OPTION_REGISTER_PREFIX_OPTIONAL
:
4208 flag_reg_prefix_optional
= 1;
4223 md_show_usage (stream
)
4228 -l use 1 word for refs to undefined symbols [default 2]\n\
4229 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
4230 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
4232 specify variant of 680X0 architecture [default 68020]\n\
4233 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
4234 target has/lacks floating-point coprocessor\n\
4235 [default yes for 68020, 68030, and cpu32]\n\
4236 -m68851 | -mno-68851\n\
4237 target has/lacks memory-management unit coprocessor\n\
4238 [default yes for 68020 and up]\n\
4239 -pic, -k generate position independent code\n\
4240 -S turn jbsr into jsr\n\
4241 --register-prefix-optional\n\
4242 recognize register names without prefix character\n");
4247 /* TEST2: Test md_assemble() */
4248 /* Warning, this routine probably doesn't work anymore */
4252 struct m68k_it the_ins
;
4260 if (!gets (buf
) || !*buf
)
4262 if (buf
[0] == '|' || buf
[1] == '.')
4264 for (cp
= buf
; *cp
; cp
++)
4269 memset (&the_ins
, '\0', sizeof (the_ins
));
4270 m68k_ip (&the_ins
, buf
);
4273 printf ("Error %s in %s\n", the_ins
.error
, buf
);
4277 printf ("Opcode(%d.%s): ", the_ins
.numo
, the_ins
.args
);
4278 for (n
= 0; n
< the_ins
.numo
; n
++)
4279 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
4281 print_the_insn (&the_ins
.opcode
[0], stdout
);
4282 (void) putchar ('\n');
4284 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
4286 if (the_ins
.operands
[n
].error
)
4288 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
4291 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
, the_ins
.operands
[n
].reg
);
4292 if (the_ins
.operands
[n
].b_const
)
4293 printf ("Constant: '%.*s', ", 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
, the_ins
.operands
[n
].b_const
);
4294 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
, the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
4295 if (the_ins
.operands
[n
].b_iadd
)
4296 printf ("Iadd: '%.*s',", 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
, the_ins
.operands
[n
].b_iadd
);
4297 (void) putchar ('\n');
4309 while (*str
&& *str
!= ' ')
4311 if (str
[-1] == ':' || str
[1] == '=')
4318 /* Possible states for relaxation:
4320 0 0 branch offset byte (bra, etc)
4324 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4328 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4335 /* We have no need to default values of symbols. */
4339 md_undefined_symbol (name
)
4345 /* Round up a section size to the appropriate boundary. */
4347 md_section_align (segment
, size
)
4351 return size
; /* Byte alignment is fine */
4354 /* Exactly what point is a PC-relative offset relative TO?
4355 On the 68k, it is relative to the address of the first extension
4356 word. The difference between the addresses of the offset and the
4357 first extension word is stored in fx_pcrel_adjust. */
4359 md_pcrel_from (fixP
)
4362 return (fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- fixP
->fx_pcrel_adjust
);
4365 #ifndef BFD_ASSEMBLER
4368 tc_coff_symbol_emit_hook (ignore
)
4374 tc_coff_sizemachdep (frag
)
4377 switch (frag
->fr_subtype
& 0x3)
4392 /* end of tc-m68k.c */