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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 1998
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 #include <ctype.h>
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 #if defined (OBJ_ELF)
31 #include "elf/m68k.h"
32 #endif
33
34 /* This string holds the chars that always start a comment. If the
35 pre-processor is disabled, these aren't very useful. The macro
36 tc_comment_chars points to this. We use this, rather than the
37 usual comment_chars, so that the --bitwise-or option will work. */
38 #if defined (TE_SVR4) || defined (TE_DELTA)
39 const char *m68k_comment_chars = "|#";
40 #else
41 const char *m68k_comment_chars = "|";
42 #endif
43
44 /* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47 /* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
49 #NO_APP at the beginning of its output. */
50 /* Also note that comments like this one will always work. */
51 const char line_comment_chars[] = "#*";
52
53 const char line_separator_chars[] = "";
54
55 /* Chars that can be used to separate mant from exp in floating point nums */
56 CONST char EXP_CHARS[] = "eE";
57
58 /* Chars that mean this number is a floating point constant, as
59 in "0f12.456" or "0d1.2345e12". */
60
61 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
62
63 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
64 changed in read.c . Ideally it shouldn't have to know about it at all,
65 but nothing is ideal around here. */
66
67 const int md_reloc_size = 8; /* Size of relocation record */
68
69 /* Are we trying to generate PIC code? If so, absolute references
70 ought to be made into linkage table references or pc-relative
71 references. Not implemented. For ELF there are other means
72 to denote pic relocations. */
73 int flag_want_pic;
74
75 static int flag_short_refs; /* -l option */
76 static int flag_long_jumps; /* -S option */
77
78 #ifdef REGISTER_PREFIX_OPTIONAL
79 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
80 #else
81 int flag_reg_prefix_optional;
82 #endif
83
84 /* Whether --register-prefix-optional was used on the command line. */
85 static int reg_prefix_optional_seen;
86
87 /* The floating point coprocessor to use by default. */
88 static enum m68k_register m68k_float_copnum = COP1;
89
90 /* If this is non-zero, then references to number(%pc) will be taken
91 to refer to number, rather than to %pc + number. */
92 static int m68k_abspcadd;
93
94 /* If this is non-zero, then the quick forms of the move, add, and sub
95 instructions are used when possible. */
96 static int m68k_quick = 1;
97
98 /* If this is non-zero, then if the size is not specified for a base
99 or outer displacement, the assembler assumes that the size should
100 be 32 bits. */
101 static int m68k_rel32 = 1;
102
103 /* This is non-zero if m68k_rel32 was set from the command line. */
104 static int m68k_rel32_from_cmdline;
105
106 /* The default width to use for an index register when using a base
107 displacement. */
108 static enum m68k_size m68k_index_width_default = SIZE_LONG;
109
110 /* We want to warn if any text labels are misaligned. In order to get
111 the right line number, we need to record the line number for each
112 label. */
113
114 struct label_line
115 {
116 struct label_line *next;
117 symbolS *label;
118 char *file;
119 unsigned int line;
120 int text;
121 };
122
123 /* The list of labels. */
124
125 static struct label_line *labels;
126
127 /* The current label. */
128
129 static struct label_line *current_label;
130
131 /* Its an arbitrary name: This means I don't approve of it */
132 /* See flames below */
133 static struct obstack robyn;
134
135 #define TAB(x,y) (((x)<<2)+(y))
136 #define TABTYPE(xy) ((xy) >> 2)
137 #define BYTE 0
138 #define SHORT 1
139 #define LONG 2
140 #define SZ_UNDEF 3
141 #undef BRANCH
142 /* Case `g' except when BCC68000 is applicable. */
143 #define ABRANCH 1
144 /* Coprocessor branches. */
145 #define FBRANCH 2
146 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
147 supported on all cpus. Widens to 32-bit absolute. */
148 #define PCREL 3
149 /* For inserting an extra jmp instruction with long offset on 68000,
150 for expanding conditional branches. (Not bsr or bra.) Since the
151 68000 doesn't support 32-bit displacements for conditional
152 branches, we fake it by reversing the condition and branching
153 around a jmp with an absolute long operand. */
154 #define BCC68000 4
155 /* For the DBcc "instructions". If the displacement requires 32 bits,
156 the branch-around-a-jump game is played here too. */
157 #define DBCC 5
158 /* Not currently used? */
159 #define PCLEA 6
160 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
161 in 16 or 8 bits. */
162 #define PCINDEX 7
163
164 struct m68k_incant
165 {
166 const char *m_operands;
167 unsigned long m_opcode;
168 short m_opnum;
169 short m_codenum;
170 int m_arch;
171 struct m68k_incant *m_next;
172 };
173
174 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
175 #define gettwo(x) (((x)->m_opcode)&0xffff)
176
177 static const enum m68k_register m68000_control_regs[] = { 0 };
178 static const enum m68k_register m68010_control_regs[] = {
179 SFC, DFC, USP, VBR,
180 0
181 };
182 static const enum m68k_register m68020_control_regs[] = {
183 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
184 0
185 };
186 static const enum m68k_register m68040_control_regs[] = {
187 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
188 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
189 0
190 };
191 static const enum m68k_register m68060_control_regs[] = {
192 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
193 USP, VBR, URP, SRP, PCR,
194 0
195 };
196 static const enum m68k_register mcf5200_control_regs[] = {
197 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
198 RAMBAR0, RAMBAR1, MBAR,
199 0
200 };
201 #define cpu32_control_regs m68010_control_regs
202
203 static const enum m68k_register *control_regs;
204
205 /* internal form of a 68020 instruction */
206 struct m68k_it
207 {
208 const char *error;
209 const char *args; /* list of opcode info */
210 int numargs;
211
212 int numo; /* Number of shorts in opcode */
213 short opcode[11];
214
215 struct m68k_op operands[6];
216
217 int nexp; /* number of exprs in use */
218 struct m68k_exp exprs[4];
219
220 int nfrag; /* Number of frags we have to produce */
221 struct
222 {
223 int fragoff; /* Where in the current opcode the frag ends */
224 symbolS *fadd;
225 offsetT foff;
226 int fragty;
227 }
228 fragb[4];
229
230 int nrel; /* Num of reloc strucs in use */
231 struct
232 {
233 int n;
234 expressionS exp;
235 char wid;
236 char pcrel;
237 /* In a pc relative address the difference between the address
238 of the offset and the address that the offset is relative
239 to. This depends on the addressing mode. Basically this
240 is the value to put in the offset field to address the
241 first byte of the offset, without regarding the special
242 significance of some values (in the branch instruction, for
243 example). */
244 int pcrel_fix;
245 #ifdef OBJ_ELF
246 /* Whether this expression needs special pic relocation, and if
247 so, which. */
248 enum pic_relocation pic_reloc;
249 #endif
250 }
251 reloc[5]; /* Five is enough??? */
252 };
253
254 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
255 #define float_of_arch(x) ((x) & mfloat)
256 #define mmu_of_arch(x) ((x) & mmmu)
257
258 /* Macros for determining if cpu supports a specific addressing mode */
259 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
260
261 static struct m68k_it the_ins; /* the instruction being assembled */
262
263 #define op(ex) ((ex)->exp.X_op)
264 #define adds(ex) ((ex)->exp.X_add_symbol)
265 #define subs(ex) ((ex)->exp.X_op_symbol)
266 #define offs(ex) ((ex)->exp.X_add_number)
267
268 /* Macros for adding things to the m68k_it struct */
269
270 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
271
272 /* Static functions. */
273
274 static void insop PARAMS ((int, const struct m68k_incant *));
275 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
276 static void add_frag PARAMS ((symbolS *, offsetT, int));
277
278 /* Like addword, but goes BEFORE general operands */
279 static void
280 insop (w, opcode)
281 int w;
282 const struct m68k_incant *opcode;
283 {
284 int z;
285 for(z=the_ins.numo;z>opcode->m_codenum;--z)
286 the_ins.opcode[z]=the_ins.opcode[z-1];
287 for(z=0;z<the_ins.nrel;z++)
288 the_ins.reloc[z].n+=2;
289 for (z = 0; z < the_ins.nfrag; z++)
290 the_ins.fragb[z].fragoff++;
291 the_ins.opcode[opcode->m_codenum]=w;
292 the_ins.numo++;
293 }
294
295 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
296 Blecch. */
297 static void
298 add_fix (width, exp, pc_rel, pc_fix)
299 int width;
300 struct m68k_exp *exp;
301 int pc_rel;
302 int pc_fix;
303 {
304 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
305 ? (the_ins.numo*2-1)
306 : (((width)=='b')
307 ? (the_ins.numo*2+1)
308 : (the_ins.numo*2)));
309 the_ins.reloc[the_ins.nrel].exp = exp->exp;
310 the_ins.reloc[the_ins.nrel].wid = width;
311 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
312 #ifdef OBJ_ELF
313 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
314 #endif
315 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
316 }
317
318 /* Cause an extra frag to be generated here, inserting up to 10 bytes
319 (that value is chosen in the frag_var call in md_assemble). TYPE
320 is the subtype of the frag to be generated; its primary type is
321 rs_machine_dependent.
322
323 The TYPE parameter is also used by md_convert_frag_1 and
324 md_estimate_size_before_relax. The appropriate type of fixup will
325 be emitted by md_convert_frag_1.
326
327 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
328 static void
329 add_frag (add, off, type)
330 symbolS *add;
331 offsetT off;
332 int type;
333 {
334 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
335 the_ins.fragb[the_ins.nfrag].fadd=add;
336 the_ins.fragb[the_ins.nfrag].foff=off;
337 the_ins.fragb[the_ins.nfrag++].fragty=type;
338 }
339
340 #define isvar(ex) \
341 (op (ex) != O_constant && op (ex) != O_big)
342
343 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
344 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
345 static void m68k_ip PARAMS ((char *));
346 static void insert_reg PARAMS ((const char *, int));
347 static void select_control_regs PARAMS ((void));
348 static void init_regtable PARAMS ((void));
349 static int reverse_16_bits PARAMS ((int in));
350 static int reverse_8_bits PARAMS ((int in));
351 static void install_gen_operand PARAMS ((int mode, int val));
352 static void install_operand PARAMS ((int mode, int val));
353 static void s_bss PARAMS ((int));
354 static void s_data1 PARAMS ((int));
355 static void s_data2 PARAMS ((int));
356 static void s_even PARAMS ((int));
357 static void s_proc PARAMS ((int));
358 static void mri_chip PARAMS ((void));
359 static void s_chip PARAMS ((int));
360 static void s_fopt PARAMS ((int));
361 static void s_opt PARAMS ((int));
362 static void s_reg PARAMS ((int));
363 static void s_restore PARAMS ((int));
364 static void s_save PARAMS ((int));
365 static void s_mri_if PARAMS ((int));
366 static void s_mri_else PARAMS ((int));
367 static void s_mri_endi PARAMS ((int));
368 static void s_mri_break PARAMS ((int));
369 static void s_mri_next PARAMS ((int));
370 static void s_mri_for PARAMS ((int));
371 static void s_mri_endf PARAMS ((int));
372 static void s_mri_repeat PARAMS ((int));
373 static void s_mri_until PARAMS ((int));
374 static void s_mri_while PARAMS ((int));
375 static void s_mri_endw PARAMS ((int));
376 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
377 static void md_convert_frag_1 PARAMS ((fragS *));
378
379 static int current_architecture;
380
381 struct m68k_cpu {
382 unsigned long arch;
383 const char *name;
384 int alias;
385 };
386
387 static const struct m68k_cpu archs[] = {
388 { m68000, "68000", 0 },
389 { m68010, "68010", 0 },
390 { m68020, "68020", 0 },
391 { m68030, "68030", 0 },
392 { m68040, "68040", 0 },
393 { m68060, "68060", 0 },
394 { cpu32, "cpu32", 0 },
395 { m68881, "68881", 0 },
396 { m68851, "68851", 0 },
397 { mcf5200, "5200", 0 },
398 /* Aliases (effectively, so far as gas is concerned) for the above
399 cpus. */
400 { m68020, "68k", 1 },
401 { m68000, "68008", 1 },
402 { m68000, "68302", 1 },
403 { m68000, "68306", 1 },
404 { m68000, "68307", 1 },
405 { m68000, "68322", 1 },
406 { m68000, "68356", 1 },
407 { m68000, "68ec000", 1 },
408 { m68000, "68hc000", 1 },
409 { m68000, "68hc001", 1 },
410 { m68020, "68ec020", 1 },
411 { m68030, "68ec030", 1 },
412 { m68040, "68ec040", 1 },
413 { m68060, "68ec060", 1 },
414 { cpu32, "68330", 1 },
415 { cpu32, "68331", 1 },
416 { cpu32, "68332", 1 },
417 { cpu32, "68333", 1 },
418 { cpu32, "68334", 1 },
419 { cpu32, "68336", 1 },
420 { cpu32, "68340", 1 },
421 { cpu32, "68341", 1 },
422 { cpu32, "68349", 1 },
423 { cpu32, "68360", 1 },
424 { m68881, "68882", 1 },
425 };
426
427 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
428
429 /* BCC68000 is for patching in an extra jmp instruction for long offsets
430 on the 68000. The 68000 doesn't support long branches with branchs */
431
432 /* This table desribes how you change sizes for the various types of variable
433 size expressions. This version only supports two kinds. */
434
435 /* Note that calls to frag_var need to specify the maximum expansion
436 needed; this is currently 10 bytes for DBCC. */
437
438 /* The fields are:
439 How far Forward this mode will reach:
440 How far Backward this mode will reach:
441 How many bytes this mode will add to the size of the frag
442 Which mode to go to if the offset won't fit in this one
443 */
444 relax_typeS md_relax_table[] =
445 {
446 {1, 1, 0, 0}, /* First entries aren't used */
447 {1, 1, 0, 0}, /* For no good reason except */
448 {1, 1, 0, 0}, /* that the VAX doesn't either */
449 {1, 1, 0, 0},
450
451 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
452 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
453 {0, 0, 4, 0},
454 {1, 1, 0, 0},
455
456 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
457 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
458 {0, 0, 4, 0},
459 {1, 1, 0, 0},
460
461 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
462 {(32767), (-32768), 2, TAB (PCREL, LONG)},
463 {0, 0, 4, 0},
464 {1, 1, 0, 0},
465
466 {(127), (-128), 0, TAB (BCC68000, SHORT)},
467 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
468 {0, 0, 6, 0}, /* jmp long space */
469 {1, 1, 0, 0},
470
471 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
472 {(32767), (-32768), 2, TAB (DBCC, LONG)},
473 {0, 0, 10, 0}, /* bra/jmp long space */
474 {1, 1, 0, 0},
475
476 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
477 {32767, -32768, 2, TAB (PCLEA, LONG)},
478 {0, 0, 6, 0},
479 {1, 1, 0, 0},
480
481 /* For, e.g., jmp pcrel indexed. */
482 {125, -130, 0, TAB (PCINDEX, SHORT)},
483 {32765, -32770, 2, TAB (PCINDEX, LONG)},
484 {0, 0, 4, 0},
485 {1, 1, 0, 0},
486 };
487
488 /* These are the machine dependent pseudo-ops. These are included so
489 the assembler can work on the output from the SUN C compiler, which
490 generates these.
491 */
492
493 /* This table describes all the machine specific pseudo-ops the assembler
494 has to support. The fields are:
495 pseudo-op name without dot
496 function to call to execute this pseudo-op
497 Integer arg to pass to the function
498 */
499 const pseudo_typeS md_pseudo_table[] =
500 {
501 {"data1", s_data1, 0},
502 {"data2", s_data2, 0},
503 {"bss", s_bss, 0},
504 {"even", s_even, 0},
505 {"skip", s_space, 0},
506 {"proc", s_proc, 0},
507 #if defined (TE_SUN3) || defined (OBJ_ELF)
508 {"align", s_align_bytes, 0},
509 #endif
510 #ifdef OBJ_ELF
511 {"swbeg", s_ignore, 0},
512 #endif
513 {"extend", float_cons, 'x'},
514 {"ldouble", float_cons, 'x'},
515
516 /* The following pseudo-ops are supported for MRI compatibility. */
517 {"chip", s_chip, 0},
518 {"comline", s_space, 1},
519 {"fopt", s_fopt, 0},
520 {"mask2", s_ignore, 0},
521 {"opt", s_opt, 0},
522 {"reg", s_reg, 0},
523 {"restore", s_restore, 0},
524 {"save", s_save, 0},
525
526 {"if", s_mri_if, 0},
527 {"if.b", s_mri_if, 'b'},
528 {"if.w", s_mri_if, 'w'},
529 {"if.l", s_mri_if, 'l'},
530 {"else", s_mri_else, 0},
531 {"else.s", s_mri_else, 's'},
532 {"else.l", s_mri_else, 'l'},
533 {"endi", s_mri_endi, 0},
534 {"break", s_mri_break, 0},
535 {"break.s", s_mri_break, 's'},
536 {"break.l", s_mri_break, 'l'},
537 {"next", s_mri_next, 0},
538 {"next.s", s_mri_next, 's'},
539 {"next.l", s_mri_next, 'l'},
540 {"for", s_mri_for, 0},
541 {"for.b", s_mri_for, 'b'},
542 {"for.w", s_mri_for, 'w'},
543 {"for.l", s_mri_for, 'l'},
544 {"endf", s_mri_endf, 0},
545 {"repeat", s_mri_repeat, 0},
546 {"until", s_mri_until, 0},
547 {"until.b", s_mri_until, 'b'},
548 {"until.w", s_mri_until, 'w'},
549 {"until.l", s_mri_until, 'l'},
550 {"while", s_mri_while, 0},
551 {"while.b", s_mri_while, 'b'},
552 {"while.w", s_mri_while, 'w'},
553 {"while.l", s_mri_while, 'l'},
554 {"endw", s_mri_endw, 0},
555
556 {0, 0, 0}
557 };
558
559
560 /* The mote pseudo ops are put into the opcode table, since they
561 don't start with a . they look like opcodes to gas.
562 */
563
564 #ifdef M68KCOFF
565 extern void obj_coff_section PARAMS ((int));
566 #endif
567
568 CONST pseudo_typeS mote_pseudo_table[] =
569 {
570
571 {"dcl", cons, 4},
572 {"dc", cons, 2},
573 {"dcw", cons, 2},
574 {"dcb", cons, 1},
575
576 {"dsl", s_space, 4},
577 {"ds", s_space, 2},
578 {"dsw", s_space, 2},
579 {"dsb", s_space, 1},
580
581 {"xdef", s_globl, 0},
582 #ifdef OBJ_ELF
583 {"align", s_align_bytes, 0},
584 #else
585 {"align", s_align_ptwo, 0},
586 #endif
587 #ifdef M68KCOFF
588 {"sect", obj_coff_section, 0},
589 {"section", obj_coff_section, 0},
590 #endif
591 {0, 0, 0}
592 };
593
594 #define issbyte(x) ((x)>=-128 && (x)<=127)
595 #define isubyte(x) ((x)>=0 && (x)<=255)
596 #define issword(x) ((x)>=-32768 && (x)<=32767)
597 #define isuword(x) ((x)>=0 && (x)<=65535)
598
599 #define isbyte(x) ((x)>= -255 && (x)<=255)
600 #define isword(x) ((x)>=-65536 && (x)<=65535)
601 #define islong(x) (1)
602
603 extern char *input_line_pointer;
604
605 static char mklower_table[256];
606 #define mklower(c) (mklower_table[(unsigned char)(c)])
607 static char notend_table[256];
608 static char alt_notend_table[256];
609 #define notend(s) \
610 (! (notend_table[(unsigned char) *s] \
611 || (*s == ':' \
612 && alt_notend_table[(unsigned char) s[1]])))
613
614 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
615
616 #ifdef NO_PCREL_RELOCS
617
618 int
619 make_pcrel_absolute(fixP, add_number)
620 fixS *fixP;
621 long *add_number;
622 {
623 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
624
625 /* rewrite the PC relative instructions to absolute address ones.
626 * these are rumoured to be faster, and the apollo linker refuses
627 * to deal with the PC relative relocations.
628 */
629 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
630 {
631 opcode[0] = 0x4e;
632 opcode[1] = 0xf9;
633 }
634 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
635 {
636 opcode[0] = 0x4e;
637 opcode[1] = 0xb9;
638 }
639 else
640 as_fatal (_("Unknown PC relative instruction"));
641 *add_number -= 4;
642 return 0;
643 }
644
645 #endif /* NO_PCREL_RELOCS */
646
647 short
648 tc_coff_fix2rtype (fixP)
649 fixS *fixP;
650 {
651 if (fixP->fx_tcbit && fixP->fx_size == 4)
652 return R_RELLONG_NEG;
653 #ifdef NO_PCREL_RELOCS
654 know (fixP->fx_pcrel == 0);
655 return (fixP->fx_size == 1 ? R_RELBYTE
656 : fixP->fx_size == 2 ? R_DIR16
657 : R_DIR32);
658 #else
659 return (fixP->fx_pcrel ?
660 (fixP->fx_size == 1 ? R_PCRBYTE :
661 fixP->fx_size == 2 ? R_PCRWORD :
662 R_PCRLONG) :
663 (fixP->fx_size == 1 ? R_RELBYTE :
664 fixP->fx_size == 2 ? R_RELWORD :
665 R_RELLONG));
666 #endif
667 }
668
669 #endif
670
671 #ifdef OBJ_ELF
672
673 /* Compute the relocation code for a fixup of SIZE bytes, using pc
674 relative relocation if PCREL is non-zero. PIC says whether a special
675 pic relocation was requested. */
676
677 static bfd_reloc_code_real_type get_reloc_code
678 PARAMS ((int, int, enum pic_relocation));
679
680 static bfd_reloc_code_real_type
681 get_reloc_code (size, pcrel, pic)
682 int size;
683 int pcrel;
684 enum pic_relocation pic;
685 {
686 switch (pic)
687 {
688 case pic_got_pcrel:
689 switch (size)
690 {
691 case 1:
692 return BFD_RELOC_8_GOT_PCREL;
693 case 2:
694 return BFD_RELOC_16_GOT_PCREL;
695 case 4:
696 return BFD_RELOC_32_GOT_PCREL;
697 }
698 break;
699
700 case pic_got_off:
701 switch (size)
702 {
703 case 1:
704 return BFD_RELOC_8_GOTOFF;
705 case 2:
706 return BFD_RELOC_16_GOTOFF;
707 case 4:
708 return BFD_RELOC_32_GOTOFF;
709 }
710 break;
711
712 case pic_plt_pcrel:
713 switch (size)
714 {
715 case 1:
716 return BFD_RELOC_8_PLT_PCREL;
717 case 2:
718 return BFD_RELOC_16_PLT_PCREL;
719 case 4:
720 return BFD_RELOC_32_PLT_PCREL;
721 }
722 break;
723
724 case pic_plt_off:
725 switch (size)
726 {
727 case 1:
728 return BFD_RELOC_8_PLTOFF;
729 case 2:
730 return BFD_RELOC_16_PLTOFF;
731 case 4:
732 return BFD_RELOC_32_PLTOFF;
733 }
734 break;
735
736 case pic_none:
737 if (pcrel)
738 {
739 switch (size)
740 {
741 case 1:
742 return BFD_RELOC_8_PCREL;
743 case 2:
744 return BFD_RELOC_16_PCREL;
745 case 4:
746 return BFD_RELOC_32_PCREL;
747 }
748 }
749 else
750 {
751 switch (size)
752 {
753 case 1:
754 return BFD_RELOC_8;
755 case 2:
756 return BFD_RELOC_16;
757 case 4:
758 return BFD_RELOC_32;
759 }
760 }
761 }
762
763 if (pcrel)
764 {
765 if (pic == pic_none)
766 as_bad (_("Can not do %d byte pc-relative relocation"), size);
767 else
768 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
769 }
770 else
771 {
772 if (pic == pic_none)
773 as_bad (_("Can not do %d byte relocation"), size);
774 else
775 as_bad (_("Can not do %d byte pic relocation"), size);
776 }
777
778 return BFD_RELOC_NONE;
779 }
780
781 /* Here we decide which fixups can be adjusted to make them relative
782 to the beginning of the section instead of the symbol. Basically
783 we need to make sure that the dynamic relocations are done
784 correctly, so in some cases we force the original symbol to be
785 used. */
786 int
787 tc_m68k_fix_adjustable (fixP)
788 fixS *fixP;
789 {
790 /* Prevent all adjustments to global symbols. */
791 if (S_IS_EXTERNAL (fixP->fx_addsy)
792 || S_IS_WEAK (fixP->fx_addsy))
793 return 0;
794
795 /* adjust_reloc_syms doesn't know about the GOT */
796 switch (fixP->fx_r_type)
797 {
798 case BFD_RELOC_8_GOT_PCREL:
799 case BFD_RELOC_16_GOT_PCREL:
800 case BFD_RELOC_32_GOT_PCREL:
801 case BFD_RELOC_8_GOTOFF:
802 case BFD_RELOC_16_GOTOFF:
803 case BFD_RELOC_32_GOTOFF:
804 case BFD_RELOC_8_PLT_PCREL:
805 case BFD_RELOC_16_PLT_PCREL:
806 case BFD_RELOC_32_PLT_PCREL:
807 case BFD_RELOC_8_PLTOFF:
808 case BFD_RELOC_16_PLTOFF:
809 case BFD_RELOC_32_PLTOFF:
810 return 0;
811
812 case BFD_RELOC_VTABLE_INHERIT:
813 case BFD_RELOC_VTABLE_ENTRY:
814 return 0;
815
816 default:
817 return 1;
818 }
819 }
820
821 #else /* !OBJ_ELF */
822
823 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
824
825 #endif /* OBJ_ELF */
826
827 #ifdef BFD_ASSEMBLER
828
829 arelent *
830 tc_gen_reloc (section, fixp)
831 asection *section;
832 fixS *fixp;
833 {
834 arelent *reloc;
835 bfd_reloc_code_real_type code;
836
837 if (fixp->fx_tcbit)
838 abort ();
839
840 if (fixp->fx_r_type != BFD_RELOC_NONE)
841 {
842 code = fixp->fx_r_type;
843
844 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
845 that fixup_segment converted a non-PC relative reloc into a
846 PC relative reloc. In such a case, we need to convert the
847 reloc code. */
848 if (fixp->fx_pcrel)
849 {
850 switch (code)
851 {
852 case BFD_RELOC_8:
853 code = BFD_RELOC_8_PCREL;
854 break;
855 case BFD_RELOC_16:
856 code = BFD_RELOC_16_PCREL;
857 break;
858 case BFD_RELOC_32:
859 code = BFD_RELOC_32_PCREL;
860 break;
861 case BFD_RELOC_8_PCREL:
862 case BFD_RELOC_16_PCREL:
863 case BFD_RELOC_32_PCREL:
864 case BFD_RELOC_8_GOT_PCREL:
865 case BFD_RELOC_16_GOT_PCREL:
866 case BFD_RELOC_32_GOT_PCREL:
867 case BFD_RELOC_8_GOTOFF:
868 case BFD_RELOC_16_GOTOFF:
869 case BFD_RELOC_32_GOTOFF:
870 case BFD_RELOC_8_PLT_PCREL:
871 case BFD_RELOC_16_PLT_PCREL:
872 case BFD_RELOC_32_PLT_PCREL:
873 case BFD_RELOC_8_PLTOFF:
874 case BFD_RELOC_16_PLTOFF:
875 case BFD_RELOC_32_PLTOFF:
876 break;
877 default:
878 as_bad_where (fixp->fx_file, fixp->fx_line,
879 _("Cannot make %s relocation PC relative"),
880 bfd_get_reloc_code_name (code));
881 }
882 }
883 }
884 else
885 {
886 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
887 switch (F (fixp->fx_size, fixp->fx_pcrel))
888 {
889 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
890 MAP (1, 0, BFD_RELOC_8);
891 MAP (2, 0, BFD_RELOC_16);
892 MAP (4, 0, BFD_RELOC_32);
893 MAP (1, 1, BFD_RELOC_8_PCREL);
894 MAP (2, 1, BFD_RELOC_16_PCREL);
895 MAP (4, 1, BFD_RELOC_32_PCREL);
896 default:
897 abort ();
898 }
899 }
900 #undef F
901 #undef MAP
902
903 reloc = (arelent *) xmalloc (sizeof (arelent));
904 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
905 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
906 #ifndef OBJ_ELF
907 if (fixp->fx_pcrel)
908 reloc->addend = fixp->fx_addnumber;
909 else
910 reloc->addend = 0;
911 #else
912 if (!fixp->fx_pcrel)
913 reloc->addend = fixp->fx_addnumber;
914 else
915 reloc->addend = (section->vma
916 + (fixp->fx_pcrel_adjust == 64
917 ? -1 : fixp->fx_pcrel_adjust)
918 + fixp->fx_addnumber
919 + md_pcrel_from (fixp));
920 #endif
921
922 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
923 assert (reloc->howto != 0);
924
925 return reloc;
926 }
927
928 #endif /* BFD_ASSEMBLER */
929
930 /* Return zero if the reference to SYMBOL from within the same segment may
931 be relaxed. */
932 #ifdef OBJ_ELF
933
934 /* On an ELF system, we can't relax an externally visible symbol,
935 because it may be overridden by a shared library. However, if
936 TARGET_OS is "elf", then we presume that we are assembling for an
937 embedded system, in which case we don't have to worry about shared
938 libraries, and we can relax anything. */
939
940 #define relaxable_symbol(symbol) \
941 (strcmp (TARGET_OS, "elf") == 0 \
942 || (! S_IS_EXTERNAL (symbol) \
943 && ! S_IS_WEAK (symbol)))
944
945 #else
946
947 #define relaxable_symbol(symbol) 1
948
949 #endif
950
951 /* Handle of the OPCODE hash table. NULL means any use before
952 m68k_ip_begin() will crash. */
953 static struct hash_control *op_hash;
954 \f
955 /* Assemble an m68k instruction. */
956
957 static void
958 m68k_ip (instring)
959 char *instring;
960 {
961 register char *p;
962 register struct m68k_op *opP;
963 register const struct m68k_incant *opcode;
964 register const char *s;
965 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
966 char *pdot, *pdotmove;
967 enum m68k_size siz1, siz2;
968 char c;
969 int losing;
970 int opsfound;
971 LITTLENUM_TYPE words[6];
972 LITTLENUM_TYPE *wordp;
973 unsigned long ok_arch = 0;
974
975 if (*instring == ' ')
976 instring++; /* skip leading whitespace */
977
978 /* Scan up to end of operation-code, which MUST end in end-of-string
979 or exactly 1 space. */
980 pdot = 0;
981 for (p = instring; *p != '\0'; p++)
982 {
983 if (*p == ' ')
984 break;
985 if (*p == '.')
986 pdot = p;
987 }
988
989 if (p == instring)
990 {
991 the_ins.error = _("No operator");
992 return;
993 }
994
995 /* p now points to the end of the opcode name, probably whitespace.
996 Make sure the name is null terminated by clobbering the
997 whitespace, look it up in the hash table, then fix it back.
998 Remove a dot, first, since the opcode tables have none. */
999 if (pdot != NULL)
1000 {
1001 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1002 *pdotmove = pdotmove[1];
1003 p--;
1004 }
1005
1006 c = *p;
1007 *p = '\0';
1008 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1009 *p = c;
1010
1011 if (pdot != NULL)
1012 {
1013 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1014 *pdotmove = pdotmove[-1];
1015 *pdot = '.';
1016 ++p;
1017 }
1018
1019 if (opcode == NULL)
1020 {
1021 the_ins.error = _("Unknown operator");
1022 return;
1023 }
1024
1025 /* found a legitimate opcode, start matching operands */
1026 while (*p == ' ')
1027 ++p;
1028
1029 if (opcode->m_operands == 0)
1030 {
1031 char *old = input_line_pointer;
1032 *old = '\n';
1033 input_line_pointer = p;
1034 /* Ahh - it's a motorola style psuedo op */
1035 mote_pseudo_table[opcode->m_opnum].poc_handler
1036 (mote_pseudo_table[opcode->m_opnum].poc_val);
1037 input_line_pointer = old;
1038 *old = 0;
1039
1040 return;
1041 }
1042
1043 if (flag_mri && opcode->m_opnum == 0)
1044 {
1045 /* In MRI mode, random garbage is allowed after an instruction
1046 which accepts no operands. */
1047 the_ins.args = opcode->m_operands;
1048 the_ins.numargs = opcode->m_opnum;
1049 the_ins.numo = opcode->m_codenum;
1050 the_ins.opcode[0] = getone (opcode);
1051 the_ins.opcode[1] = gettwo (opcode);
1052 return;
1053 }
1054
1055 for (opP = &the_ins.operands[0]; *p; opP++)
1056 {
1057 p = crack_operand (p, opP);
1058
1059 if (opP->error)
1060 {
1061 the_ins.error = opP->error;
1062 return;
1063 }
1064 }
1065
1066 opsfound = opP - &the_ins.operands[0];
1067
1068 /* This ugly hack is to support the floating pt opcodes in their
1069 standard form. Essentially, we fake a first enty of type COP#1 */
1070 if (opcode->m_operands[0] == 'I')
1071 {
1072 int n;
1073
1074 for (n = opsfound; n > 0; --n)
1075 the_ins.operands[n] = the_ins.operands[n - 1];
1076
1077 memset ((char *) (&the_ins.operands[0]), '\0',
1078 sizeof (the_ins.operands[0]));
1079 the_ins.operands[0].mode = CONTROL;
1080 the_ins.operands[0].reg = m68k_float_copnum;
1081 opsfound++;
1082 }
1083
1084 /* We've got the operands. Find an opcode that'll accept them */
1085 for (losing = 0;;)
1086 {
1087 /* If we didn't get the right number of ops, or we have no
1088 common model with this pattern then reject this pattern. */
1089
1090 ok_arch |= opcode->m_arch;
1091 if (opsfound != opcode->m_opnum
1092 || ((opcode->m_arch & current_architecture) == 0))
1093 ++losing;
1094 else
1095 {
1096 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1097 *s && !losing;
1098 s += 2, opP++)
1099 {
1100 /* Warning: this switch is huge! */
1101 /* I've tried to organize the cases into this order:
1102 non-alpha first, then alpha by letter. Lower-case
1103 goes directly before uppercase counterpart. */
1104 /* Code with multiple case ...: gets sorted by the lowest
1105 case ... it belongs to. I hope this makes sense. */
1106 switch (*s)
1107 {
1108 case '!':
1109 switch (opP->mode)
1110 {
1111 case IMMED:
1112 case DREG:
1113 case AREG:
1114 case FPREG:
1115 case CONTROL:
1116 case AINC:
1117 case ADEC:
1118 case REGLST:
1119 losing++;
1120 break;
1121 default:
1122 break;
1123 }
1124 break;
1125
1126 case '<':
1127 switch (opP->mode)
1128 {
1129 case DREG:
1130 case AREG:
1131 case FPREG:
1132 case CONTROL:
1133 case IMMED:
1134 case ADEC:
1135 case REGLST:
1136 losing++;
1137 break;
1138 default:
1139 break;
1140 }
1141 break;
1142
1143 case '>':
1144 switch (opP->mode)
1145 {
1146 case DREG:
1147 case AREG:
1148 case FPREG:
1149 case CONTROL:
1150 case IMMED:
1151 case AINC:
1152 case REGLST:
1153 losing++;
1154 break;
1155 case ABSL:
1156 break;
1157 default:
1158 if (opP->reg == PC
1159 || opP->reg == ZPC)
1160 losing++;
1161 break;
1162 }
1163 break;
1164
1165 case 'm':
1166 switch (opP->mode)
1167 {
1168 case DREG:
1169 case AREG:
1170 case AINDR:
1171 case AINC:
1172 case ADEC:
1173 break;
1174 default:
1175 losing++;
1176 }
1177 break;
1178
1179 case 'n':
1180 switch (opP->mode)
1181 {
1182 case DISP:
1183 break;
1184 default:
1185 losing++;
1186 }
1187 break;
1188
1189 case 'o':
1190 switch (opP->mode)
1191 {
1192 case BASE:
1193 case ABSL:
1194 case IMMED:
1195 break;
1196 default:
1197 losing++;
1198 }
1199 break;
1200
1201 case 'p':
1202 switch (opP->mode)
1203 {
1204 case DREG:
1205 case AREG:
1206 case AINDR:
1207 case AINC:
1208 case ADEC:
1209 break;
1210 case DISP:
1211 if (opP->reg == PC || opP->reg == ZPC)
1212 losing++;
1213 break;
1214 default:
1215 losing++;
1216 }
1217 break;
1218
1219 case 'q':
1220 switch (opP->mode)
1221 {
1222 case DREG:
1223 case AINDR:
1224 case AINC:
1225 case ADEC:
1226 break;
1227 case DISP:
1228 if (opP->reg == PC || opP->reg == ZPC)
1229 losing++;
1230 break;
1231 default:
1232 losing++;
1233 break;
1234 }
1235 break;
1236
1237 case 'v':
1238 switch (opP->mode)
1239 {
1240 case DREG:
1241 case AINDR:
1242 case AINC:
1243 case ADEC:
1244 case ABSL:
1245 break;
1246 case DISP:
1247 if (opP->reg == PC || opP->reg == ZPC)
1248 losing++;
1249 break;
1250 default:
1251 losing++;
1252 break;
1253 }
1254 break;
1255
1256 case '#':
1257 if (opP->mode != IMMED)
1258 losing++;
1259 else if (s[1] == 'b'
1260 && ! isvar (&opP->disp)
1261 && (opP->disp.exp.X_op != O_constant
1262 || ! isbyte (opP->disp.exp.X_add_number)))
1263 losing++;
1264 else if (s[1] == 'B'
1265 && ! isvar (&opP->disp)
1266 && (opP->disp.exp.X_op != O_constant
1267 || ! issbyte (opP->disp.exp.X_add_number)))
1268 losing++;
1269 else if (s[1] == 'w'
1270 && ! isvar (&opP->disp)
1271 && (opP->disp.exp.X_op != O_constant
1272 || ! isword (opP->disp.exp.X_add_number)))
1273 losing++;
1274 else if (s[1] == 'W'
1275 && ! isvar (&opP->disp)
1276 && (opP->disp.exp.X_op != O_constant
1277 || ! issword (opP->disp.exp.X_add_number)))
1278 losing++;
1279 break;
1280
1281 case '^':
1282 case 'T':
1283 if (opP->mode != IMMED)
1284 losing++;
1285 break;
1286
1287 case '$':
1288 if (opP->mode == AREG
1289 || opP->mode == CONTROL
1290 || opP->mode == FPREG
1291 || opP->mode == IMMED
1292 || opP->mode == REGLST
1293 || (opP->mode != ABSL
1294 && (opP->reg == PC
1295 || opP->reg == ZPC)))
1296 losing++;
1297 break;
1298
1299 case '%':
1300 if (opP->mode == CONTROL
1301 || opP->mode == FPREG
1302 || opP->mode == REGLST
1303 || opP->mode == IMMED
1304 || (opP->mode != ABSL
1305 && (opP->reg == PC
1306 || opP->reg == ZPC)))
1307 losing++;
1308 break;
1309
1310 case '&':
1311 switch (opP->mode)
1312 {
1313 case DREG:
1314 case AREG:
1315 case FPREG:
1316 case CONTROL:
1317 case IMMED:
1318 case AINC:
1319 case ADEC:
1320 case REGLST:
1321 losing++;
1322 break;
1323 case ABSL:
1324 break;
1325 default:
1326 if (opP->reg == PC
1327 || opP->reg == ZPC)
1328 losing++;
1329 break;
1330 }
1331 break;
1332
1333 case '*':
1334 if (opP->mode == CONTROL
1335 || opP->mode == FPREG
1336 || opP->mode == REGLST)
1337 losing++;
1338 break;
1339
1340 case '+':
1341 if (opP->mode != AINC)
1342 losing++;
1343 break;
1344
1345 case '-':
1346 if (opP->mode != ADEC)
1347 losing++;
1348 break;
1349
1350 case '/':
1351 switch (opP->mode)
1352 {
1353 case AREG:
1354 case CONTROL:
1355 case FPREG:
1356 case AINC:
1357 case ADEC:
1358 case IMMED:
1359 case REGLST:
1360 losing++;
1361 break;
1362 default:
1363 break;
1364 }
1365 break;
1366
1367 case ';':
1368 switch (opP->mode)
1369 {
1370 case AREG:
1371 case CONTROL:
1372 case FPREG:
1373 case REGLST:
1374 losing++;
1375 break;
1376 default:
1377 break;
1378 }
1379 break;
1380
1381 case '?':
1382 switch (opP->mode)
1383 {
1384 case AREG:
1385 case CONTROL:
1386 case FPREG:
1387 case AINC:
1388 case ADEC:
1389 case IMMED:
1390 case REGLST:
1391 losing++;
1392 break;
1393 case ABSL:
1394 break;
1395 default:
1396 if (opP->reg == PC || opP->reg == ZPC)
1397 losing++;
1398 break;
1399 }
1400 break;
1401
1402 case '@':
1403 switch (opP->mode)
1404 {
1405 case AREG:
1406 case CONTROL:
1407 case FPREG:
1408 case IMMED:
1409 case REGLST:
1410 losing++;
1411 break;
1412 default:
1413 break;
1414 }
1415 break;
1416
1417 case '~': /* For now! (JF FOO is this right?) */
1418 switch (opP->mode)
1419 {
1420 case DREG:
1421 case AREG:
1422 case CONTROL:
1423 case FPREG:
1424 case IMMED:
1425 case REGLST:
1426 losing++;
1427 break;
1428 case ABSL:
1429 break;
1430 default:
1431 if (opP->reg == PC
1432 || opP->reg == ZPC)
1433 losing++;
1434 break;
1435 }
1436 break;
1437
1438 case '3':
1439 if (opP->mode != CONTROL
1440 || (opP->reg != TT0 && opP->reg != TT1))
1441 losing++;
1442 break;
1443
1444 case 'A':
1445 if (opP->mode != AREG)
1446 losing++;
1447 break;
1448
1449 case 'a':
1450 if (opP->mode != AINDR)
1451 ++losing;
1452 break;
1453
1454 case 'B': /* FOO */
1455 if (opP->mode != ABSL
1456 || (flag_long_jumps
1457 && strncmp (instring, "jbsr", 4) == 0))
1458 losing++;
1459 break;
1460
1461 case 'C':
1462 if (opP->mode != CONTROL || opP->reg != CCR)
1463 losing++;
1464 break;
1465
1466 case 'd':
1467 if (opP->mode != DISP
1468 || opP->reg < ADDR0
1469 || opP->reg > ADDR7)
1470 losing++;
1471 break;
1472
1473 case 'D':
1474 if (opP->mode != DREG)
1475 losing++;
1476 break;
1477
1478 case 'F':
1479 if (opP->mode != FPREG)
1480 losing++;
1481 break;
1482
1483 case 'I':
1484 if (opP->mode != CONTROL
1485 || opP->reg < COP0
1486 || opP->reg > COP7)
1487 losing++;
1488 break;
1489
1490 case 'J':
1491 if (opP->mode != CONTROL
1492 || opP->reg < USP
1493 || opP->reg > last_movec_reg)
1494 losing++;
1495 else
1496 {
1497 const enum m68k_register *rp;
1498 for (rp = control_regs; *rp; rp++)
1499 if (*rp == opP->reg)
1500 break;
1501 if (*rp == 0)
1502 losing++;
1503 }
1504 break;
1505
1506 case 'k':
1507 if (opP->mode != IMMED)
1508 losing++;
1509 break;
1510
1511 case 'l':
1512 case 'L':
1513 if (opP->mode == DREG
1514 || opP->mode == AREG
1515 || opP->mode == FPREG)
1516 {
1517 if (s[1] == '8')
1518 losing++;
1519 else
1520 {
1521 switch (opP->mode)
1522 {
1523 case DREG:
1524 opP->mask = 1 << (opP->reg - DATA0);
1525 break;
1526 case AREG:
1527 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1528 break;
1529 case FPREG:
1530 opP->mask = 1 << (opP->reg - FP0 + 16);
1531 break;
1532 default:
1533 abort ();
1534 }
1535 opP->mode = REGLST;
1536 }
1537 }
1538 else if (opP->mode == CONTROL)
1539 {
1540 if (s[1] != '8')
1541 losing++;
1542 else
1543 {
1544 switch (opP->reg)
1545 {
1546 case FPI:
1547 opP->mask = 1 << 24;
1548 break;
1549 case FPS:
1550 opP->mask = 1 << 25;
1551 break;
1552 case FPC:
1553 opP->mask = 1 << 26;
1554 break;
1555 default:
1556 losing++;
1557 break;
1558 }
1559 opP->mode = REGLST;
1560 }
1561 }
1562 else if (opP->mode != REGLST)
1563 losing++;
1564 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1565 losing++;
1566 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1567 losing++;
1568 break;
1569
1570 case 'M':
1571 if (opP->mode != IMMED)
1572 losing++;
1573 else if (opP->disp.exp.X_op != O_constant
1574 || ! issbyte (opP->disp.exp.X_add_number))
1575 losing++;
1576 else if (! m68k_quick
1577 && instring[3] != 'q'
1578 && instring[4] != 'q')
1579 losing++;
1580 break;
1581
1582 case 'O':
1583 if (opP->mode != DREG
1584 && opP->mode != IMMED
1585 && opP->mode != ABSL)
1586 losing++;
1587 break;
1588
1589 case 'Q':
1590 if (opP->mode != IMMED)
1591 losing++;
1592 else if (opP->disp.exp.X_op != O_constant
1593 || opP->disp.exp.X_add_number < 1
1594 || opP->disp.exp.X_add_number > 8)
1595 losing++;
1596 else if (! m68k_quick
1597 && (strncmp (instring, "add", 3) == 0
1598 || strncmp (instring, "sub", 3) == 0)
1599 && instring[3] != 'q')
1600 losing++;
1601 break;
1602
1603 case 'R':
1604 if (opP->mode != DREG && opP->mode != AREG)
1605 losing++;
1606 break;
1607
1608 case 'r':
1609 if (opP->mode != AINDR
1610 && (opP->mode != BASE
1611 || (opP->reg != 0
1612 && opP->reg != ZADDR0)
1613 || opP->disp.exp.X_op != O_absent
1614 || ((opP->index.reg < DATA0
1615 || opP->index.reg > DATA7)
1616 && (opP->index.reg < ADDR0
1617 || opP->index.reg > ADDR7))
1618 || opP->index.size != SIZE_UNSPEC
1619 || opP->index.scale != 1))
1620 losing++;
1621 break;
1622
1623 case 's':
1624 if (opP->mode != CONTROL
1625 || ! (opP->reg == FPI
1626 || opP->reg == FPS
1627 || opP->reg == FPC))
1628 losing++;
1629 break;
1630
1631 case 'S':
1632 if (opP->mode != CONTROL || opP->reg != SR)
1633 losing++;
1634 break;
1635
1636 case 't':
1637 if (opP->mode != IMMED)
1638 losing++;
1639 else if (opP->disp.exp.X_op != O_constant
1640 || opP->disp.exp.X_add_number < 0
1641 || opP->disp.exp.X_add_number > 7)
1642 losing++;
1643 break;
1644
1645 case 'U':
1646 if (opP->mode != CONTROL || opP->reg != USP)
1647 losing++;
1648 break;
1649
1650 /* JF these are out of order. We could put them
1651 in order if we were willing to put up with
1652 bunches of #ifdef m68851s in the code.
1653
1654 Don't forget that you need these operands
1655 to use 68030 MMU instructions. */
1656 #ifndef NO_68851
1657 /* Memory addressing mode used by pflushr */
1658 case '|':
1659 if (opP->mode == CONTROL
1660 || opP->mode == FPREG
1661 || opP->mode == DREG
1662 || opP->mode == AREG
1663 || opP->mode == REGLST)
1664 losing++;
1665 /* We should accept immediate operands, but they
1666 supposedly have to be quad word, and we don't
1667 handle that. I would like to see what a Motorola
1668 assembler does before doing something here. */
1669 if (opP->mode == IMMED)
1670 losing++;
1671 break;
1672
1673 case 'f':
1674 if (opP->mode != CONTROL
1675 || (opP->reg != SFC && opP->reg != DFC))
1676 losing++;
1677 break;
1678
1679 case '0':
1680 if (opP->mode != CONTROL || opP->reg != TC)
1681 losing++;
1682 break;
1683
1684 case '1':
1685 if (opP->mode != CONTROL || opP->reg != AC)
1686 losing++;
1687 break;
1688
1689 case '2':
1690 if (opP->mode != CONTROL
1691 || (opP->reg != CAL
1692 && opP->reg != VAL
1693 && opP->reg != SCC))
1694 losing++;
1695 break;
1696
1697 case 'V':
1698 if (opP->mode != CONTROL
1699 || opP->reg != VAL)
1700 losing++;
1701 break;
1702
1703 case 'W':
1704 if (opP->mode != CONTROL
1705 || (opP->reg != DRP
1706 && opP->reg != SRP
1707 && opP->reg != CRP))
1708 losing++;
1709 break;
1710
1711 case 'X':
1712 if (opP->mode != CONTROL
1713 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1714 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1715 losing++;
1716 break;
1717
1718 case 'Y':
1719 if (opP->mode != CONTROL || opP->reg != PSR)
1720 losing++;
1721 break;
1722
1723 case 'Z':
1724 if (opP->mode != CONTROL || opP->reg != PCSR)
1725 losing++;
1726 break;
1727 #endif
1728 case 'c':
1729 if (opP->mode != CONTROL
1730 || (opP->reg != NC
1731 && opP->reg != IC
1732 && opP->reg != DC
1733 && opP->reg != BC))
1734 {
1735 losing++;
1736 } /* not a cache specifier. */
1737 break;
1738
1739 case '_':
1740 if (opP->mode != ABSL)
1741 ++losing;
1742 break;
1743
1744 default:
1745 abort ();
1746 } /* switch on type of operand */
1747
1748 if (losing)
1749 break;
1750 } /* for each operand */
1751 } /* if immediately wrong */
1752
1753 if (!losing)
1754 {
1755 break;
1756 } /* got it. */
1757
1758 opcode = opcode->m_next;
1759
1760 if (!opcode)
1761 {
1762 if (ok_arch
1763 && !(ok_arch & current_architecture))
1764 {
1765 char buf[200], *cp;
1766
1767 strcpy (buf,
1768 _("invalid instruction for this architecture; needs "));
1769 cp = buf + strlen (buf);
1770 switch (ok_arch)
1771 {
1772 case mfloat:
1773 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1774 break;
1775 case mmmu:
1776 strcpy (cp, _("mmu (68030 or 68851)"));
1777 break;
1778 case m68020up:
1779 strcpy (cp, _("68020 or higher"));
1780 break;
1781 case m68000up:
1782 strcpy (cp, _("68000 or higher"));
1783 break;
1784 case m68010up:
1785 strcpy (cp, _("68010 or higher"));
1786 break;
1787 default:
1788 {
1789 int got_one = 0, idx;
1790 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1791 idx++)
1792 {
1793 if ((archs[idx].arch & ok_arch)
1794 && ! archs[idx].alias)
1795 {
1796 if (got_one)
1797 {
1798 strcpy (cp, " or ");
1799 cp += strlen (cp);
1800 }
1801 got_one = 1;
1802 strcpy (cp, archs[idx].name);
1803 cp += strlen (cp);
1804 }
1805 }
1806 }
1807 }
1808 cp = xmalloc (strlen (buf) + 1);
1809 strcpy (cp, buf);
1810 the_ins.error = cp;
1811 }
1812 else
1813 the_ins.error = _("operands mismatch");
1814 return;
1815 } /* Fell off the end */
1816
1817 losing = 0;
1818 }
1819
1820 /* now assemble it */
1821
1822 the_ins.args = opcode->m_operands;
1823 the_ins.numargs = opcode->m_opnum;
1824 the_ins.numo = opcode->m_codenum;
1825 the_ins.opcode[0] = getone (opcode);
1826 the_ins.opcode[1] = gettwo (opcode);
1827
1828 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1829 {
1830 /* This switch is a doozy.
1831 Watch the first step; its a big one! */
1832 switch (s[0])
1833 {
1834
1835 case '*':
1836 case '~':
1837 case '%':
1838 case ';':
1839 case '@':
1840 case '!':
1841 case '&':
1842 case '$':
1843 case '?':
1844 case '/':
1845 case '<':
1846 case '>':
1847 case 'm':
1848 case 'n':
1849 case 'o':
1850 case 'p':
1851 case 'q':
1852 case 'v':
1853 #ifndef NO_68851
1854 case '|':
1855 #endif
1856 switch (opP->mode)
1857 {
1858 case IMMED:
1859 tmpreg = 0x3c; /* 7.4 */
1860 if (strchr ("bwl", s[1]))
1861 nextword = get_num (&opP->disp, 80);
1862 else
1863 nextword = get_num (&opP->disp, 0);
1864 if (isvar (&opP->disp))
1865 add_fix (s[1], &opP->disp, 0, 0);
1866 switch (s[1])
1867 {
1868 case 'b':
1869 if (!isbyte (nextword))
1870 opP->error = _("operand out of range");
1871 addword (nextword);
1872 baseo = 0;
1873 break;
1874 case 'w':
1875 if (!isword (nextword))
1876 opP->error = _("operand out of range");
1877 addword (nextword);
1878 baseo = 0;
1879 break;
1880 case 'W':
1881 if (!issword (nextword))
1882 opP->error = _("operand out of range");
1883 addword (nextword);
1884 baseo = 0;
1885 break;
1886 case 'l':
1887 addword (nextword >> 16);
1888 addword (nextword);
1889 baseo = 0;
1890 break;
1891
1892 case 'f':
1893 baseo = 2;
1894 outro = 8;
1895 break;
1896 case 'F':
1897 baseo = 4;
1898 outro = 11;
1899 break;
1900 case 'x':
1901 baseo = 6;
1902 outro = 15;
1903 break;
1904 case 'p':
1905 baseo = 6;
1906 outro = -1;
1907 break;
1908 default:
1909 abort ();
1910 }
1911 if (!baseo)
1912 break;
1913
1914 /* We gotta put out some float */
1915 if (op (&opP->disp) != O_big)
1916 {
1917 valueT val;
1918 int gencnt;
1919
1920 /* Can other cases happen here? */
1921 if (op (&opP->disp) != O_constant)
1922 abort ();
1923
1924 val = (valueT) offs (&opP->disp);
1925 gencnt = 0;
1926 do
1927 {
1928 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1929 val >>= LITTLENUM_NUMBER_OF_BITS;
1930 ++gencnt;
1931 }
1932 while (val != 0);
1933 offs (&opP->disp) = gencnt;
1934 }
1935 if (offs (&opP->disp) > 0)
1936 {
1937 if (offs (&opP->disp) > baseo)
1938 {
1939 as_warn (_("Bignum too big for %c format; truncated"),
1940 s[1]);
1941 offs (&opP->disp) = baseo;
1942 }
1943 baseo -= offs (&opP->disp);
1944 while (baseo--)
1945 addword (0);
1946 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1947 offs (&opP->disp)--;
1948 --wordp)
1949 addword (*wordp);
1950 break;
1951 }
1952 gen_to_words (words, baseo, (long) outro);
1953 for (wordp = words; baseo--; wordp++)
1954 addword (*wordp);
1955 break;
1956 case DREG:
1957 tmpreg = opP->reg - DATA; /* 0.dreg */
1958 break;
1959 case AREG:
1960 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1961 break;
1962 case AINDR:
1963 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1964 break;
1965 case ADEC:
1966 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1967 break;
1968 case AINC:
1969 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1970 break;
1971 case DISP:
1972
1973 nextword = get_num (&opP->disp, 80);
1974
1975 if (opP->reg == PC
1976 && ! isvar (&opP->disp)
1977 && m68k_abspcadd)
1978 {
1979 opP->disp.exp.X_op = O_symbol;
1980 #ifndef BFD_ASSEMBLER
1981 opP->disp.exp.X_add_symbol = &abs_symbol;
1982 #else
1983 opP->disp.exp.X_add_symbol =
1984 section_symbol (absolute_section);
1985 #endif
1986 }
1987
1988 /* Force into index mode. Hope this works */
1989
1990 /* We do the first bit for 32-bit displacements, and the
1991 second bit for 16 bit ones. It is possible that we
1992 should make the default be WORD instead of LONG, but
1993 I think that'd break GCC, so we put up with a little
1994 inefficiency for the sake of working output. */
1995
1996 if (!issword (nextword)
1997 || (isvar (&opP->disp)
1998 && ((opP->disp.size == SIZE_UNSPEC
1999 && flag_short_refs == 0
2000 && cpu_of_arch (current_architecture) >= m68020
2001 && cpu_of_arch (current_architecture) != mcf5200)
2002 || opP->disp.size == SIZE_LONG)))
2003 {
2004 if (cpu_of_arch (current_architecture) < m68020
2005 || cpu_of_arch (current_architecture) == mcf5200)
2006 opP->error =
2007 _("displacement too large for this architecture; needs 68020 or higher");
2008 if (opP->reg == PC)
2009 tmpreg = 0x3B; /* 7.3 */
2010 else
2011 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2012 if (isvar (&opP->disp))
2013 {
2014 if (opP->reg == PC)
2015 {
2016 if (opP->disp.size == SIZE_LONG
2017 #ifdef OBJ_ELF
2018 /* If the displacement needs pic
2019 relocation it cannot be relaxed. */
2020 || opP->disp.pic_reloc != pic_none
2021 #endif
2022 )
2023 {
2024 addword (0x0170);
2025 add_fix ('l', &opP->disp, 1, 2);
2026 }
2027 else
2028 {
2029 add_frag (adds (&opP->disp),
2030 offs (&opP->disp),
2031 TAB (PCLEA, SZ_UNDEF));
2032 break;
2033 }
2034 }
2035 else
2036 {
2037 addword (0x0170);
2038 add_fix ('l', &opP->disp, 0, 0);
2039 }
2040 }
2041 else
2042 addword (0x0170);
2043 addword (nextword >> 16);
2044 }
2045 else
2046 {
2047 if (opP->reg == PC)
2048 tmpreg = 0x3A; /* 7.2 */
2049 else
2050 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2051
2052 if (isvar (&opP->disp))
2053 {
2054 if (opP->reg == PC)
2055 {
2056 add_fix ('w', &opP->disp, 1, 0);
2057 }
2058 else
2059 add_fix ('w', &opP->disp, 0, 0);
2060 }
2061 }
2062 addword (nextword);
2063 break;
2064
2065 case POST:
2066 case PRE:
2067 case BASE:
2068 nextword = 0;
2069 baseo = get_num (&opP->disp, 80);
2070 if (opP->mode == POST || opP->mode == PRE)
2071 outro = get_num (&opP->odisp, 80);
2072 /* Figure out the `addressing mode'.
2073 Also turn on the BASE_DISABLE bit, if needed. */
2074 if (opP->reg == PC || opP->reg == ZPC)
2075 {
2076 tmpreg = 0x3b; /* 7.3 */
2077 if (opP->reg == ZPC)
2078 nextword |= 0x80;
2079 }
2080 else if (opP->reg == 0)
2081 {
2082 nextword |= 0x80;
2083 tmpreg = 0x30; /* 6.garbage */
2084 }
2085 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2086 {
2087 nextword |= 0x80;
2088 tmpreg = 0x30 + opP->reg - ZADDR0;
2089 }
2090 else
2091 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2092
2093 siz1 = opP->disp.size;
2094 if (opP->mode == POST || opP->mode == PRE)
2095 siz2 = opP->odisp.size;
2096 else
2097 siz2 = SIZE_UNSPEC;
2098
2099 /* Index register stuff */
2100 if (opP->index.reg != 0
2101 && opP->index.reg >= DATA
2102 && opP->index.reg <= ADDR7)
2103 {
2104 nextword |= (opP->index.reg - DATA) << 12;
2105
2106 if (opP->index.size == SIZE_LONG
2107 || (opP->index.size == SIZE_UNSPEC
2108 && m68k_index_width_default == SIZE_LONG))
2109 nextword |= 0x800;
2110
2111 if ((opP->index.scale != 1
2112 && cpu_of_arch (current_architecture) < m68020)
2113 || (opP->index.scale == 8
2114 && current_architecture == mcf5200))
2115 {
2116 opP->error =
2117 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2118 }
2119
2120 switch (opP->index.scale)
2121 {
2122 case 1:
2123 break;
2124 case 2:
2125 nextword |= 0x200;
2126 break;
2127 case 4:
2128 nextword |= 0x400;
2129 break;
2130 case 8:
2131 nextword |= 0x600;
2132 break;
2133 default:
2134 abort ();
2135 }
2136 /* IF its simple,
2137 GET US OUT OF HERE! */
2138
2139 /* Must be INDEX, with an index register. Address
2140 register cannot be ZERO-PC, and either :b was
2141 forced, or we know it will fit. For a 68000 or
2142 68010, force this mode anyways, because the
2143 larger modes aren't supported. */
2144 if (opP->mode == BASE
2145 && ((opP->reg >= ADDR0
2146 && opP->reg <= ADDR7)
2147 || opP->reg == PC))
2148 {
2149 if (siz1 == SIZE_BYTE
2150 || cpu_of_arch (current_architecture) < m68020
2151 || cpu_of_arch (current_architecture) == mcf5200
2152 || (siz1 == SIZE_UNSPEC
2153 && ! isvar (&opP->disp)
2154 && issbyte (baseo)))
2155 {
2156 nextword += baseo & 0xff;
2157 addword (nextword);
2158 if (isvar (&opP->disp))
2159 {
2160 /* Do a byte relocation. If it doesn't
2161 fit (possible on m68000) let the
2162 fixup processing complain later. */
2163 if (opP->reg == PC)
2164 add_fix ('B', &opP->disp, 1, 1);
2165 else
2166 add_fix ('B', &opP->disp, 0, 0);
2167 }
2168 else if (siz1 != SIZE_BYTE)
2169 {
2170 if (siz1 != SIZE_UNSPEC)
2171 as_warn (_("Forcing byte displacement"));
2172 if (! issbyte (baseo))
2173 opP->error = _("byte displacement out of range");
2174 }
2175
2176 break;
2177 }
2178 else if (siz1 == SIZE_UNSPEC
2179 && opP->reg == PC
2180 && isvar (&opP->disp)
2181 && subs (&opP->disp) == NULL
2182 #ifdef OBJ_ELF
2183 /* If the displacement needs pic
2184 relocation it cannot be relaxed. */
2185 && opP->disp.pic_reloc == pic_none
2186 #endif
2187 )
2188 {
2189 /* The code in md_convert_frag_1 needs to be
2190 able to adjust nextword. Call frag_grow
2191 to ensure that we have enough space in
2192 the frag obstack to make all the bytes
2193 contiguous. */
2194 frag_grow (14);
2195 nextword += baseo & 0xff;
2196 addword (nextword);
2197 add_frag (adds (&opP->disp), offs (&opP->disp),
2198 TAB (PCINDEX, SZ_UNDEF));
2199
2200 break;
2201 }
2202 }
2203 }
2204 else
2205 {
2206 nextword |= 0x40; /* No index reg */
2207 if (opP->index.reg >= ZDATA0
2208 && opP->index.reg <= ZDATA7)
2209 nextword |= (opP->index.reg - ZDATA0) << 12;
2210 else if (opP->index.reg >= ZADDR0
2211 || opP->index.reg <= ZADDR7)
2212 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2213 }
2214
2215 /* It isn't simple. */
2216
2217 if (cpu_of_arch (current_architecture) < m68020
2218 || cpu_of_arch (current_architecture) == mcf5200)
2219 opP->error =
2220 _("invalid operand mode for this architecture; needs 68020 or higher");
2221
2222 nextword |= 0x100;
2223 /* If the guy specified a width, we assume that it is
2224 wide enough. Maybe it isn't. If so, we lose. */
2225 switch (siz1)
2226 {
2227 case SIZE_UNSPEC:
2228 if (isvar (&opP->disp)
2229 ? m68k_rel32
2230 : ! issword (baseo))
2231 {
2232 siz1 = SIZE_LONG;
2233 nextword |= 0x30;
2234 }
2235 else if (! isvar (&opP->disp) && baseo == 0)
2236 nextword |= 0x10;
2237 else
2238 {
2239 nextword |= 0x20;
2240 siz1 = SIZE_WORD;
2241 }
2242 break;
2243 case SIZE_BYTE:
2244 as_warn (_(":b not permitted; defaulting to :w"));
2245 /* Fall through. */
2246 case SIZE_WORD:
2247 nextword |= 0x20;
2248 break;
2249 case SIZE_LONG:
2250 nextword |= 0x30;
2251 break;
2252 }
2253
2254 /* Figure out innner displacement stuff */
2255 if (opP->mode == POST || opP->mode == PRE)
2256 {
2257 if (cpu_of_arch (current_architecture) & cpu32)
2258 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2259 switch (siz2)
2260 {
2261 case SIZE_UNSPEC:
2262 if (isvar (&opP->odisp)
2263 ? m68k_rel32
2264 : ! issword (outro))
2265 {
2266 siz2 = SIZE_LONG;
2267 nextword |= 0x3;
2268 }
2269 else if (! isvar (&opP->odisp) && outro == 0)
2270 nextword |= 0x1;
2271 else
2272 {
2273 nextword |= 0x2;
2274 siz2 = SIZE_WORD;
2275 }
2276 break;
2277 case 1:
2278 as_warn (_(":b not permitted; defaulting to :w"));
2279 /* Fall through. */
2280 case 2:
2281 nextword |= 0x2;
2282 break;
2283 case 3:
2284 nextword |= 0x3;
2285 break;
2286 }
2287 if (opP->mode == POST
2288 && (nextword & 0x40) == 0)
2289 nextword |= 0x04;
2290 }
2291 addword (nextword);
2292
2293 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2294 {
2295 if (opP->reg == PC || opP->reg == ZPC)
2296 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2297 else
2298 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2299 }
2300 if (siz1 == SIZE_LONG)
2301 addword (baseo >> 16);
2302 if (siz1 != SIZE_UNSPEC)
2303 addword (baseo);
2304
2305 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2306 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2307 if (siz2 == SIZE_LONG)
2308 addword (outro >> 16);
2309 if (siz2 != SIZE_UNSPEC)
2310 addword (outro);
2311
2312 break;
2313
2314 case ABSL:
2315 nextword = get_num (&opP->disp, 80);
2316 switch (opP->disp.size)
2317 {
2318 default:
2319 abort ();
2320 case SIZE_UNSPEC:
2321 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2322 {
2323 tmpreg = 0x38; /* 7.0 */
2324 addword (nextword);
2325 break;
2326 }
2327 /* Don't generate pc relative code on 68010 and
2328 68000. */
2329 if (isvar (&opP->disp)
2330 && !subs (&opP->disp)
2331 && adds (&opP->disp)
2332 #ifdef OBJ_ELF
2333 /* If the displacement needs pic relocation it
2334 cannot be relaxed. */
2335 && opP->disp.pic_reloc == pic_none
2336 #endif
2337 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2338 && relaxable_symbol (adds (&opP->disp))
2339 && HAVE_LONG_BRANCH(current_architecture)
2340 && !flag_long_jumps
2341 && !strchr ("~%&$?", s[0]))
2342 {
2343 tmpreg = 0x3A; /* 7.2 */
2344 add_frag (adds (&opP->disp),
2345 offs (&opP->disp),
2346 TAB (PCREL, SZ_UNDEF));
2347 break;
2348 }
2349 /* Fall through into long */
2350 case SIZE_LONG:
2351 if (isvar (&opP->disp))
2352 add_fix ('l', &opP->disp, 0, 0);
2353
2354 tmpreg = 0x39;/* 7.1 mode */
2355 addword (nextword >> 16);
2356 addword (nextword);
2357 break;
2358
2359 case SIZE_BYTE:
2360 as_bad (_("unsupported byte value; use a different suffix"));
2361 /* Fall through. */
2362 case SIZE_WORD: /* Word */
2363 if (isvar (&opP->disp))
2364 add_fix ('w', &opP->disp, 0, 0);
2365
2366 tmpreg = 0x38;/* 7.0 mode */
2367 addword (nextword);
2368 break;
2369 }
2370 break;
2371 case CONTROL:
2372 case FPREG:
2373 default:
2374 as_bad (_("unknown/incorrect operand"));
2375 /* abort(); */
2376 }
2377 install_gen_operand (s[1], tmpreg);
2378 break;
2379
2380 case '#':
2381 case '^':
2382 switch (s[1])
2383 { /* JF: I hate floating point! */
2384 case 'j':
2385 tmpreg = 70;
2386 break;
2387 case '8':
2388 tmpreg = 20;
2389 break;
2390 case 'C':
2391 tmpreg = 50;
2392 break;
2393 case '3':
2394 default:
2395 tmpreg = 80;
2396 break;
2397 }
2398 tmpreg = get_num (&opP->disp, tmpreg);
2399 if (isvar (&opP->disp))
2400 add_fix (s[1], &opP->disp, 0, 0);
2401 switch (s[1])
2402 {
2403 case 'b': /* Danger: These do no check for
2404 certain types of overflow.
2405 user beware! */
2406 if (!isbyte (tmpreg))
2407 opP->error = _("out of range");
2408 insop (tmpreg, opcode);
2409 if (isvar (&opP->disp))
2410 the_ins.reloc[the_ins.nrel - 1].n =
2411 (opcode->m_codenum) * 2 + 1;
2412 break;
2413 case 'B':
2414 if (!issbyte (tmpreg))
2415 opP->error = _("out of range");
2416 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2417 if (isvar (&opP->disp))
2418 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2419 break;
2420 case 'w':
2421 if (!isword (tmpreg))
2422 opP->error = _("out of range");
2423 insop (tmpreg, opcode);
2424 if (isvar (&opP->disp))
2425 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2426 break;
2427 case 'W':
2428 if (!issword (tmpreg))
2429 opP->error = _("out of range");
2430 insop (tmpreg, opcode);
2431 if (isvar (&opP->disp))
2432 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2433 break;
2434 case 'l':
2435 /* Because of the way insop works, we put these two out
2436 backwards. */
2437 insop (tmpreg, opcode);
2438 insop (tmpreg >> 16, opcode);
2439 if (isvar (&opP->disp))
2440 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2441 break;
2442 case '3':
2443 tmpreg &= 0xFF;
2444 case '8':
2445 case 'C':
2446 case 'j':
2447 install_operand (s[1], tmpreg);
2448 break;
2449 default:
2450 abort ();
2451 }
2452 break;
2453
2454 case '+':
2455 case '-':
2456 case 'A':
2457 case 'a':
2458 install_operand (s[1], opP->reg - ADDR);
2459 break;
2460
2461 case 'B':
2462 tmpreg = get_num (&opP->disp, 80);
2463 switch (s[1])
2464 {
2465 case 'B':
2466 /* The pc_fix argument winds up in fx_pcrel_adjust,
2467 which is a char, and may therefore be unsigned. We
2468 want to pass -1, but we pass 64 instead, and convert
2469 back in md_pcrel_from. */
2470 add_fix ('B', &opP->disp, 1, 64);
2471 break;
2472 case 'W':
2473 add_fix ('w', &opP->disp, 1, 0);
2474 addword (0);
2475 break;
2476 case 'L':
2477 long_branch:
2478 if (!HAVE_LONG_BRANCH(current_architecture))
2479 as_warn (_("Can't use long branches on 68000/68010/5200"));
2480 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2481 add_fix ('l', &opP->disp, 1, 0);
2482 addword (0);
2483 addword (0);
2484 break;
2485 case 'g':
2486 if (subs (&opP->disp)) /* We can't relax it */
2487 goto long_branch;
2488
2489 #ifdef OBJ_ELF
2490 /* If the displacement needs pic relocation it cannot be
2491 relaxed. */
2492 if (opP->disp.pic_reloc != pic_none)
2493 goto long_branch;
2494 #endif
2495
2496 /* This could either be a symbol, or an absolute
2497 address. No matter, the frag hacking will finger it
2498 out. Not quite: it can't switch from BRANCH to
2499 BCC68000 for the case where opnd is absolute (it
2500 needs to use the 68000 hack since no conditional abs
2501 jumps). */
2502 if (( !HAVE_LONG_BRANCH(current_architecture)
2503 || (0 == adds (&opP->disp)))
2504 && (the_ins.opcode[0] >= 0x6200)
2505 && (the_ins.opcode[0] <= 0x6f00))
2506 add_frag (adds (&opP->disp), offs (&opP->disp),
2507 TAB (BCC68000, SZ_UNDEF));
2508 else
2509 add_frag (adds (&opP->disp), offs (&opP->disp),
2510 TAB (ABRANCH, SZ_UNDEF));
2511 break;
2512 case 'w':
2513 if (isvar (&opP->disp))
2514 {
2515 #if 1
2516 /* check for DBcc instruction */
2517 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2518 {
2519 /* size varies if patch */
2520 /* needed for long form */
2521 add_frag (adds (&opP->disp), offs (&opP->disp),
2522 TAB (DBCC, SZ_UNDEF));
2523 break;
2524 }
2525 #endif
2526 add_fix ('w', &opP->disp, 1, 0);
2527 }
2528 addword (0);
2529 break;
2530 case 'C': /* Fixed size LONG coproc branches */
2531 add_fix ('l', &opP->disp, 1, 0);
2532 addword (0);
2533 addword (0);
2534 break;
2535 case 'c': /* Var size Coprocesssor branches */
2536 if (subs (&opP->disp))
2537 {
2538 add_fix ('l', &opP->disp, 1, 0);
2539 add_frag ((symbolS *) 0, (offsetT) 0, TAB (FBRANCH, LONG));
2540 }
2541 else if (adds (&opP->disp))
2542 add_frag (adds (&opP->disp), offs (&opP->disp),
2543 TAB (FBRANCH, SZ_UNDEF));
2544 else
2545 {
2546 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2547 TAB(FBRANCH,SHORT)); */
2548 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2549 add_fix ('l', &opP->disp, 1, 0);
2550 addword (0);
2551 addword (0);
2552 }
2553 break;
2554 default:
2555 abort ();
2556 }
2557 break;
2558
2559 case 'C': /* Ignore it */
2560 break;
2561
2562 case 'd': /* JF this is a kludge */
2563 install_operand ('s', opP->reg - ADDR);
2564 tmpreg = get_num (&opP->disp, 80);
2565 if (!issword (tmpreg))
2566 {
2567 as_warn (_("Expression out of range, using 0"));
2568 tmpreg = 0;
2569 }
2570 addword (tmpreg);
2571 break;
2572
2573 case 'D':
2574 install_operand (s[1], opP->reg - DATA);
2575 break;
2576
2577 case 'F':
2578 install_operand (s[1], opP->reg - FP0);
2579 break;
2580
2581 case 'I':
2582 tmpreg = opP->reg - COP0;
2583 install_operand (s[1], tmpreg);
2584 break;
2585
2586 case 'J': /* JF foo */
2587 switch (opP->reg)
2588 {
2589 case SFC:
2590 tmpreg = 0x000;
2591 break;
2592 case DFC:
2593 tmpreg = 0x001;
2594 break;
2595 case CACR:
2596 tmpreg = 0x002;
2597 break;
2598 case TC:
2599 tmpreg = 0x003;
2600 break;
2601 case ITT0:
2602 tmpreg = 0x004;
2603 break;
2604 case ITT1:
2605 tmpreg = 0x005;
2606 break;
2607 case DTT0:
2608 tmpreg = 0x006;
2609 break;
2610 case DTT1:
2611 tmpreg = 0x007;
2612 break;
2613 case BUSCR:
2614 tmpreg = 0x008;
2615 break;
2616
2617 case USP:
2618 tmpreg = 0x800;
2619 break;
2620 case VBR:
2621 tmpreg = 0x801;
2622 break;
2623 case CAAR:
2624 tmpreg = 0x802;
2625 break;
2626 case MSP:
2627 tmpreg = 0x803;
2628 break;
2629 case ISP:
2630 tmpreg = 0x804;
2631 break;
2632 case MMUSR:
2633 tmpreg = 0x805;
2634 break;
2635 case URP:
2636 tmpreg = 0x806;
2637 break;
2638 case SRP:
2639 tmpreg = 0x807;
2640 break;
2641 case PCR:
2642 tmpreg = 0x808;
2643 break;
2644 case ROMBAR:
2645 tmpreg = 0xC00;
2646 break;
2647 case RAMBAR0:
2648 tmpreg = 0xC04;
2649 break;
2650 case RAMBAR1:
2651 tmpreg = 0xC05;
2652 break;
2653 case MBAR:
2654 tmpreg = 0xC0F;
2655 break;
2656 default:
2657 abort ();
2658 }
2659 install_operand (s[1], tmpreg);
2660 break;
2661
2662 case 'k':
2663 tmpreg = get_num (&opP->disp, 55);
2664 install_operand (s[1], tmpreg & 0x7f);
2665 break;
2666
2667 case 'l':
2668 tmpreg = opP->mask;
2669 if (s[1] == 'w')
2670 {
2671 if (tmpreg & 0x7FF0000)
2672 as_bad (_("Floating point register in register list"));
2673 insop (reverse_16_bits (tmpreg), opcode);
2674 }
2675 else
2676 {
2677 if (tmpreg & 0x700FFFF)
2678 as_bad (_("Wrong register in floating-point reglist"));
2679 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2680 }
2681 break;
2682
2683 case 'L':
2684 tmpreg = opP->mask;
2685 if (s[1] == 'w')
2686 {
2687 if (tmpreg & 0x7FF0000)
2688 as_bad (_("Floating point register in register list"));
2689 insop (tmpreg, opcode);
2690 }
2691 else if (s[1] == '8')
2692 {
2693 if (tmpreg & 0x0FFFFFF)
2694 as_bad (_("incorrect register in reglist"));
2695 install_operand (s[1], tmpreg >> 24);
2696 }
2697 else
2698 {
2699 if (tmpreg & 0x700FFFF)
2700 as_bad (_("wrong register in floating-point reglist"));
2701 else
2702 install_operand (s[1], tmpreg >> 16);
2703 }
2704 break;
2705
2706 case 'M':
2707 install_operand (s[1], get_num (&opP->disp, 60));
2708 break;
2709
2710 case 'O':
2711 tmpreg = ((opP->mode == DREG)
2712 ? 0x20 + opP->reg - DATA
2713 : (get_num (&opP->disp, 40) & 0x1F));
2714 install_operand (s[1], tmpreg);
2715 break;
2716
2717 case 'Q':
2718 tmpreg = get_num (&opP->disp, 10);
2719 if (tmpreg == 8)
2720 tmpreg = 0;
2721 install_operand (s[1], tmpreg);
2722 break;
2723
2724 case 'R':
2725 /* This depends on the fact that ADDR registers are eight
2726 more than their corresponding DATA regs, so the result
2727 will have the ADDR_REG bit set */
2728 install_operand (s[1], opP->reg - DATA);
2729 break;
2730
2731 case 'r':
2732 if (opP->mode == AINDR)
2733 install_operand (s[1], opP->reg - DATA);
2734 else
2735 install_operand (s[1], opP->index.reg - DATA);
2736 break;
2737
2738 case 's':
2739 if (opP->reg == FPI)
2740 tmpreg = 0x1;
2741 else if (opP->reg == FPS)
2742 tmpreg = 0x2;
2743 else if (opP->reg == FPC)
2744 tmpreg = 0x4;
2745 else
2746 abort ();
2747 install_operand (s[1], tmpreg);
2748 break;
2749
2750 case 'S': /* Ignore it */
2751 break;
2752
2753 case 'T':
2754 install_operand (s[1], get_num (&opP->disp, 30));
2755 break;
2756
2757 case 'U': /* Ignore it */
2758 break;
2759
2760 case 'c':
2761 switch (opP->reg)
2762 {
2763 case NC:
2764 tmpreg = 0;
2765 break;
2766 case DC:
2767 tmpreg = 1;
2768 break;
2769 case IC:
2770 tmpreg = 2;
2771 break;
2772 case BC:
2773 tmpreg = 3;
2774 break;
2775 default:
2776 as_fatal (_("failed sanity check"));
2777 } /* switch on cache token */
2778 install_operand (s[1], tmpreg);
2779 break;
2780 #ifndef NO_68851
2781 /* JF: These are out of order, I fear. */
2782 case 'f':
2783 switch (opP->reg)
2784 {
2785 case SFC:
2786 tmpreg = 0;
2787 break;
2788 case DFC:
2789 tmpreg = 1;
2790 break;
2791 default:
2792 abort ();
2793 }
2794 install_operand (s[1], tmpreg);
2795 break;
2796
2797 case '0':
2798 case '1':
2799 case '2':
2800 switch (opP->reg)
2801 {
2802 case TC:
2803 tmpreg = 0;
2804 break;
2805 case CAL:
2806 tmpreg = 4;
2807 break;
2808 case VAL:
2809 tmpreg = 5;
2810 break;
2811 case SCC:
2812 tmpreg = 6;
2813 break;
2814 case AC:
2815 tmpreg = 7;
2816 break;
2817 default:
2818 abort ();
2819 }
2820 install_operand (s[1], tmpreg);
2821 break;
2822
2823 case 'V':
2824 if (opP->reg == VAL)
2825 break;
2826 abort ();
2827
2828 case 'W':
2829 switch (opP->reg)
2830 {
2831 case DRP:
2832 tmpreg = 1;
2833 break;
2834 case SRP:
2835 tmpreg = 2;
2836 break;
2837 case CRP:
2838 tmpreg = 3;
2839 break;
2840 default:
2841 abort ();
2842 }
2843 install_operand (s[1], tmpreg);
2844 break;
2845
2846 case 'X':
2847 switch (opP->reg)
2848 {
2849 case BAD:
2850 case BAD + 1:
2851 case BAD + 2:
2852 case BAD + 3:
2853 case BAD + 4:
2854 case BAD + 5:
2855 case BAD + 6:
2856 case BAD + 7:
2857 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2858 break;
2859
2860 case BAC:
2861 case BAC + 1:
2862 case BAC + 2:
2863 case BAC + 3:
2864 case BAC + 4:
2865 case BAC + 5:
2866 case BAC + 6:
2867 case BAC + 7:
2868 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2869 break;
2870
2871 default:
2872 abort ();
2873 }
2874 install_operand (s[1], tmpreg);
2875 break;
2876 case 'Y':
2877 know (opP->reg == PSR);
2878 break;
2879 case 'Z':
2880 know (opP->reg == PCSR);
2881 break;
2882 #endif /* m68851 */
2883 case '3':
2884 switch (opP->reg)
2885 {
2886 case TT0:
2887 tmpreg = 2;
2888 break;
2889 case TT1:
2890 tmpreg = 3;
2891 break;
2892 default:
2893 abort ();
2894 }
2895 install_operand (s[1], tmpreg);
2896 break;
2897 case 't':
2898 tmpreg = get_num (&opP->disp, 20);
2899 install_operand (s[1], tmpreg);
2900 break;
2901 case '_': /* used only for move16 absolute 32-bit address */
2902 if (isvar (&opP->disp))
2903 add_fix ('l', &opP->disp, 0, 0);
2904 tmpreg = get_num (&opP->disp, 80);
2905 addword (tmpreg >> 16);
2906 addword (tmpreg & 0xFFFF);
2907 break;
2908 default:
2909 abort ();
2910 }
2911 }
2912
2913 /* By the time whe get here (FINALLY) the_ins contains the complete
2914 instruction, ready to be emitted. . . */
2915 }
2916
2917 static int
2918 reverse_16_bits (in)
2919 int in;
2920 {
2921 int out = 0;
2922 int n;
2923
2924 static int mask[16] =
2925 {
2926 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2927 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2928 };
2929 for (n = 0; n < 16; n++)
2930 {
2931 if (in & mask[n])
2932 out |= mask[15 - n];
2933 }
2934 return out;
2935 } /* reverse_16_bits() */
2936
2937 static int
2938 reverse_8_bits (in)
2939 int in;
2940 {
2941 int out = 0;
2942 int n;
2943
2944 static int mask[8] =
2945 {
2946 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2947 };
2948
2949 for (n = 0; n < 8; n++)
2950 {
2951 if (in & mask[n])
2952 out |= mask[7 - n];
2953 }
2954 return out;
2955 } /* reverse_8_bits() */
2956
2957 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2958 (that value is chosen in the frag_var call in md_assemble). TYPE
2959 is the subtype of the frag to be generated; its primary type is
2960 rs_machine_dependent.
2961
2962 The TYPE parameter is also used by md_convert_frag_1 and
2963 md_estimate_size_before_relax. The appropriate type of fixup will
2964 be emitted by md_convert_frag_1.
2965
2966 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2967 static void
2968 install_operand (mode, val)
2969 int mode;
2970 int val;
2971 {
2972 switch (mode)
2973 {
2974 case 's':
2975 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2976 break;
2977 case 'd':
2978 the_ins.opcode[0] |= val << 9;
2979 break;
2980 case '1':
2981 the_ins.opcode[1] |= val << 12;
2982 break;
2983 case '2':
2984 the_ins.opcode[1] |= val << 6;
2985 break;
2986 case '3':
2987 the_ins.opcode[1] |= val;
2988 break;
2989 case '4':
2990 the_ins.opcode[2] |= val << 12;
2991 break;
2992 case '5':
2993 the_ins.opcode[2] |= val << 6;
2994 break;
2995 case '6':
2996 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2997 three words long! */
2998 the_ins.numo++;
2999 the_ins.opcode[2] |= val;
3000 break;
3001 case '7':
3002 the_ins.opcode[1] |= val << 7;
3003 break;
3004 case '8':
3005 the_ins.opcode[1] |= val << 10;
3006 break;
3007 #ifndef NO_68851
3008 case '9':
3009 the_ins.opcode[1] |= val << 5;
3010 break;
3011 #endif
3012
3013 case 't':
3014 the_ins.opcode[1] |= (val << 10) | (val << 7);
3015 break;
3016 case 'D':
3017 the_ins.opcode[1] |= (val << 12) | val;
3018 break;
3019 case 'g':
3020 the_ins.opcode[0] |= val = 0xff;
3021 break;
3022 case 'i':
3023 the_ins.opcode[0] |= val << 9;
3024 break;
3025 case 'C':
3026 the_ins.opcode[1] |= val;
3027 break;
3028 case 'j':
3029 the_ins.opcode[1] |= val;
3030 the_ins.numo++; /* What a hack */
3031 break;
3032 case 'k':
3033 the_ins.opcode[1] |= val << 4;
3034 break;
3035 case 'b':
3036 case 'w':
3037 case 'W':
3038 case 'l':
3039 break;
3040 case 'e':
3041 the_ins.opcode[0] |= (val << 6);
3042 break;
3043 case 'L':
3044 the_ins.opcode[1] = (val >> 16);
3045 the_ins.opcode[2] = val & 0xffff;
3046 break;
3047 case 'c':
3048 default:
3049 as_fatal (_("failed sanity check."));
3050 }
3051 } /* install_operand() */
3052
3053 static void
3054 install_gen_operand (mode, val)
3055 int mode;
3056 int val;
3057 {
3058 switch (mode)
3059 {
3060 case 's':
3061 the_ins.opcode[0] |= val;
3062 break;
3063 case 'd':
3064 /* This is a kludge!!! */
3065 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3066 break;
3067 case 'b':
3068 case 'w':
3069 case 'l':
3070 case 'f':
3071 case 'F':
3072 case 'x':
3073 case 'p':
3074 the_ins.opcode[0] |= val;
3075 break;
3076 /* more stuff goes here */
3077 default:
3078 as_fatal (_("failed sanity check."));
3079 }
3080 } /* install_gen_operand() */
3081
3082 /*
3083 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3084 * then deal with the bitfield hack.
3085 */
3086
3087 static char *
3088 crack_operand (str, opP)
3089 register char *str;
3090 register struct m68k_op *opP;
3091 {
3092 register int parens;
3093 register int c;
3094 register char *beg_str;
3095 int inquote = 0;
3096
3097 if (!str)
3098 {
3099 return str;
3100 }
3101 beg_str = str;
3102 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3103 {
3104 if (! inquote)
3105 {
3106 if (*str == '(')
3107 parens++;
3108 else if (*str == ')')
3109 {
3110 if (!parens)
3111 { /* ERROR */
3112 opP->error = _("Extra )");
3113 return str;
3114 }
3115 --parens;
3116 }
3117 }
3118 if (flag_mri && *str == '\'')
3119 inquote = ! inquote;
3120 }
3121 if (!*str && parens)
3122 { /* ERROR */
3123 opP->error = _("Missing )");
3124 return str;
3125 }
3126 c = *str;
3127 *str = '\0';
3128 if (m68k_ip_op (beg_str, opP) != 0)
3129 {
3130 *str = c;
3131 return str;
3132 }
3133 *str = c;
3134 if (c == '}')
3135 c = *++str; /* JF bitfield hack */
3136 if (c)
3137 {
3138 c = *++str;
3139 if (!c)
3140 as_bad (_("Missing operand"));
3141 }
3142
3143 /* Detect MRI REG symbols and convert them to REGLSTs. */
3144 if (opP->mode == CONTROL && (int)opP->reg < 0)
3145 {
3146 opP->mode = REGLST;
3147 opP->mask = ~(int)opP->reg;
3148 opP->reg = 0;
3149 }
3150
3151 return str;
3152 }
3153
3154 /* This is the guts of the machine-dependent assembler. STR points to a
3155 machine dependent instruction. This function is supposed to emit
3156 the frags/bytes it assembles to.
3157 */
3158
3159 static void
3160 insert_reg (regname, regnum)
3161 const char *regname;
3162 int regnum;
3163 {
3164 char buf[100];
3165 int i;
3166
3167 #ifdef REGISTER_PREFIX
3168 if (!flag_reg_prefix_optional)
3169 {
3170 buf[0] = REGISTER_PREFIX;
3171 strcpy (buf + 1, regname);
3172 regname = buf;
3173 }
3174 #endif
3175
3176 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3177 &zero_address_frag));
3178
3179 for (i = 0; regname[i]; i++)
3180 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3181 buf[i] = '\0';
3182
3183 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3184 &zero_address_frag));
3185 }
3186
3187 struct init_entry
3188 {
3189 const char *name;
3190 int number;
3191 };
3192
3193 static const struct init_entry init_table[] =
3194 {
3195 { "d0", DATA0 },
3196 { "d1", DATA1 },
3197 { "d2", DATA2 },
3198 { "d3", DATA3 },
3199 { "d4", DATA4 },
3200 { "d5", DATA5 },
3201 { "d6", DATA6 },
3202 { "d7", DATA7 },
3203 { "a0", ADDR0 },
3204 { "a1", ADDR1 },
3205 { "a2", ADDR2 },
3206 { "a3", ADDR3 },
3207 { "a4", ADDR4 },
3208 { "a5", ADDR5 },
3209 { "a6", ADDR6 },
3210 { "fp", ADDR6 },
3211 { "a7", ADDR7 },
3212 { "sp", ADDR7 },
3213 { "ssp", ADDR7 },
3214 { "fp0", FP0 },
3215 { "fp1", FP1 },
3216 { "fp2", FP2 },
3217 { "fp3", FP3 },
3218 { "fp4", FP4 },
3219 { "fp5", FP5 },
3220 { "fp6", FP6 },
3221 { "fp7", FP7 },
3222 { "fpi", FPI },
3223 { "fpiar", FPI },
3224 { "fpc", FPI },
3225 { "fps", FPS },
3226 { "fpsr", FPS },
3227 { "fpc", FPC },
3228 { "fpcr", FPC },
3229 { "control", FPC },
3230 { "status", FPS },
3231 { "iaddr", FPI },
3232
3233 { "cop0", COP0 },
3234 { "cop1", COP1 },
3235 { "cop2", COP2 },
3236 { "cop3", COP3 },
3237 { "cop4", COP4 },
3238 { "cop5", COP5 },
3239 { "cop6", COP6 },
3240 { "cop7", COP7 },
3241 { "pc", PC },
3242 { "zpc", ZPC },
3243 { "sr", SR },
3244
3245 { "ccr", CCR },
3246 { "cc", CCR },
3247
3248 /* control registers */
3249 { "sfc", SFC }, /* Source Function Code */
3250 { "sfcr", SFC },
3251 { "dfc", DFC }, /* Destination Function Code */
3252 { "dfcr", DFC },
3253 { "cacr", CACR }, /* Cache Control Register */
3254 { "caar", CAAR }, /* Cache Address Register */
3255
3256 { "usp", USP }, /* User Stack Pointer */
3257 { "vbr", VBR }, /* Vector Base Register */
3258 { "msp", MSP }, /* Master Stack Pointer */
3259 { "isp", ISP }, /* Interrupt Stack Pointer */
3260
3261 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3262 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3263 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3264 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3265
3266 /* 68ec040 versions of same */
3267 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3268 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3269 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3270 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3271
3272 /* mcf5200 versions of same. The ColdFire programmer's reference
3273 manual indicated that the order is 2,3,0,1, but Ken Rose
3274 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3275 { "acr0", ITT0 }, /* Access Control Unit 0 */
3276 { "acr1", ITT1 }, /* Access Control Unit 1 */
3277 { "acr2", DTT0 }, /* Access Control Unit 2 */
3278 { "acr3", DTT1 }, /* Access Control Unit 3 */
3279
3280 { "tc", TC }, /* MMU Translation Control Register */
3281 { "tcr", TC },
3282
3283 { "mmusr", MMUSR }, /* MMU Status Register */
3284 { "srp", SRP }, /* User Root Pointer */
3285 { "urp", URP }, /* Supervisor Root Pointer */
3286
3287 { "buscr", BUSCR },
3288 { "pcr", PCR },
3289
3290 { "rombar", ROMBAR }, /* ROM Base Address Register */
3291 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3292 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3293 { "mbar", MBAR }, /* Module Base Address Register */
3294 /* end of control registers */
3295
3296 { "ac", AC },
3297 { "bc", BC },
3298 { "cal", CAL },
3299 { "crp", CRP },
3300 { "drp", DRP },
3301 { "pcsr", PCSR },
3302 { "psr", PSR },
3303 { "scc", SCC },
3304 { "val", VAL },
3305 { "bad0", BAD0 },
3306 { "bad1", BAD1 },
3307 { "bad2", BAD2 },
3308 { "bad3", BAD3 },
3309 { "bad4", BAD4 },
3310 { "bad5", BAD5 },
3311 { "bad6", BAD6 },
3312 { "bad7", BAD7 },
3313 { "bac0", BAC0 },
3314 { "bac1", BAC1 },
3315 { "bac2", BAC2 },
3316 { "bac3", BAC3 },
3317 { "bac4", BAC4 },
3318 { "bac5", BAC5 },
3319 { "bac6", BAC6 },
3320 { "bac7", BAC7 },
3321
3322 { "ic", IC },
3323 { "dc", DC },
3324 { "nc", NC },
3325
3326 { "tt0", TT0 },
3327 { "tt1", TT1 },
3328 /* 68ec030 versions of same */
3329 { "ac0", TT0 },
3330 { "ac1", TT1 },
3331 /* 68ec030 access control unit, identical to 030 MMU status reg */
3332 { "acusr", PSR },
3333
3334 /* Suppressed data and address registers. */
3335 { "zd0", ZDATA0 },
3336 { "zd1", ZDATA1 },
3337 { "zd2", ZDATA2 },
3338 { "zd3", ZDATA3 },
3339 { "zd4", ZDATA4 },
3340 { "zd5", ZDATA5 },
3341 { "zd6", ZDATA6 },
3342 { "zd7", ZDATA7 },
3343 { "za0", ZADDR0 },
3344 { "za1", ZADDR1 },
3345 { "za2", ZADDR2 },
3346 { "za3", ZADDR3 },
3347 { "za4", ZADDR4 },
3348 { "za5", ZADDR5 },
3349 { "za6", ZADDR6 },
3350 { "za7", ZADDR7 },
3351
3352 { 0, 0 }
3353 };
3354
3355 static void
3356 init_regtable ()
3357 {
3358 int i;
3359 for (i = 0; init_table[i].name; i++)
3360 insert_reg (init_table[i].name, init_table[i].number);
3361 }
3362
3363 static int no_68851, no_68881;
3364
3365 #ifdef OBJ_AOUT
3366 /* a.out machine type. Default to 68020. */
3367 int m68k_aout_machtype = 2;
3368 #endif
3369
3370 void
3371 md_assemble (str)
3372 char *str;
3373 {
3374 const char *er;
3375 short *fromP;
3376 char *toP = NULL;
3377 int m, n = 0;
3378 char *to_beg_P;
3379 int shorts_this_frag;
3380 fixS *fixP;
3381
3382 /* In MRI mode, the instruction and operands are separated by a
3383 space. Anything following the operands is a comment. The label
3384 has already been removed. */
3385 if (flag_mri)
3386 {
3387 char *s;
3388 int fields = 0;
3389 int infield = 0;
3390 int inquote = 0;
3391
3392 for (s = str; *s != '\0'; s++)
3393 {
3394 if ((*s == ' ' || *s == '\t') && ! inquote)
3395 {
3396 if (infield)
3397 {
3398 ++fields;
3399 if (fields >= 2)
3400 {
3401 *s = '\0';
3402 break;
3403 }
3404 infield = 0;
3405 }
3406 }
3407 else
3408 {
3409 if (! infield)
3410 infield = 1;
3411 if (*s == '\'')
3412 inquote = ! inquote;
3413 }
3414 }
3415 }
3416
3417 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3418 m68k_ip (str);
3419 er = the_ins.error;
3420 if (!er)
3421 {
3422 for (n = 0; n < the_ins.numargs; n++)
3423 if (the_ins.operands[n].error)
3424 {
3425 er = the_ins.operands[n].error;
3426 break;
3427 }
3428 }
3429 if (er)
3430 {
3431 as_bad (_("%s -- statement `%s' ignored"), er, str);
3432 return;
3433 }
3434
3435 /* If there is a current label, record that it marks an instruction. */
3436 if (current_label != NULL)
3437 {
3438 current_label->text = 1;
3439 current_label = NULL;
3440 }
3441
3442 if (the_ins.nfrag == 0)
3443 {
3444 /* No frag hacking involved; just put it out */
3445 toP = frag_more (2 * the_ins.numo);
3446 fromP = &the_ins.opcode[0];
3447 for (m = the_ins.numo; m; --m)
3448 {
3449 md_number_to_chars (toP, (long) (*fromP), 2);
3450 toP += 2;
3451 fromP++;
3452 }
3453 /* put out symbol-dependent info */
3454 for (m = 0; m < the_ins.nrel; m++)
3455 {
3456 switch (the_ins.reloc[m].wid)
3457 {
3458 case 'B':
3459 n = 1;
3460 break;
3461 case 'b':
3462 n = 1;
3463 break;
3464 case '3':
3465 n = 1;
3466 break;
3467 case 'w':
3468 case 'W':
3469 n = 2;
3470 break;
3471 case 'l':
3472 n = 4;
3473 break;
3474 default:
3475 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3476 the_ins.reloc[m].wid);
3477 }
3478
3479 fixP = fix_new_exp (frag_now,
3480 ((toP - frag_now->fr_literal)
3481 - the_ins.numo * 2 + the_ins.reloc[m].n),
3482 n,
3483 &the_ins.reloc[m].exp,
3484 the_ins.reloc[m].pcrel,
3485 get_reloc_code (n, the_ins.reloc[m].pcrel,
3486 the_ins.reloc[m].pic_reloc));
3487 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3488 if (the_ins.reloc[m].wid == 'B')
3489 fixP->fx_signed = 1;
3490 }
3491 return;
3492 }
3493
3494 /* There's some frag hacking */
3495 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3496 {
3497 int wid;
3498
3499 if (n == 0)
3500 wid = 2 * the_ins.fragb[n].fragoff;
3501 else
3502 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3503 toP = frag_more (wid);
3504 to_beg_P = toP;
3505 shorts_this_frag = 0;
3506 for (m = wid / 2; m; --m)
3507 {
3508 md_number_to_chars (toP, (long) (*fromP), 2);
3509 toP += 2;
3510 fromP++;
3511 shorts_this_frag++;
3512 }
3513 for (m = 0; m < the_ins.nrel; m++)
3514 {
3515 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3516 {
3517 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3518 break;
3519 }
3520 wid = the_ins.reloc[m].wid;
3521 if (wid == 0)
3522 continue;
3523 the_ins.reloc[m].wid = 0;
3524 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3525
3526 fixP = fix_new_exp (frag_now,
3527 ((toP - frag_now->fr_literal)
3528 - the_ins.numo * 2 + the_ins.reloc[m].n),
3529 wid,
3530 &the_ins.reloc[m].exp,
3531 the_ins.reloc[m].pcrel,
3532 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3533 the_ins.reloc[m].pic_reloc));
3534 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3535 }
3536 (void) frag_var (rs_machine_dependent, 10, 0,
3537 (relax_substateT) (the_ins.fragb[n].fragty),
3538 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3539 }
3540 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3541 shorts_this_frag = 0;
3542 if (n)
3543 {
3544 toP = frag_more (n * sizeof (short));
3545 while (n--)
3546 {
3547 md_number_to_chars (toP, (long) (*fromP), 2);
3548 toP += 2;
3549 fromP++;
3550 shorts_this_frag++;
3551 }
3552 }
3553 for (m = 0; m < the_ins.nrel; m++)
3554 {
3555 int wid;
3556
3557 wid = the_ins.reloc[m].wid;
3558 if (wid == 0)
3559 continue;
3560 the_ins.reloc[m].wid = 0;
3561 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3562
3563 fixP = fix_new_exp (frag_now,
3564 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3565 - shorts_this_frag * 2),
3566 wid,
3567 &the_ins.reloc[m].exp,
3568 the_ins.reloc[m].pcrel,
3569 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3570 the_ins.reloc[m].pic_reloc));
3571 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3572 }
3573 }
3574
3575 void
3576 md_begin ()
3577 {
3578 /*
3579 * md_begin -- set up hash tables with 68000 instructions.
3580 * similar to what the vax assembler does. ---phr
3581 */
3582 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3583 a copy of it at runtime, adding in the information we want but isn't
3584 there. I think it'd be better to have an awk script hack the table
3585 at compile time. Or even just xstr the table and use it as-is. But
3586 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3587 names. */
3588
3589 register const struct m68k_opcode *ins;
3590 register struct m68k_incant *hack, *slak;
3591 register const char *retval = 0; /* empty string, or error msg text */
3592 register unsigned int i;
3593 register char c;
3594
3595 if (flag_mri)
3596 {
3597 flag_reg_prefix_optional = 1;
3598 m68k_abspcadd = 1;
3599 if (! m68k_rel32_from_cmdline)
3600 m68k_rel32 = 0;
3601 }
3602
3603 op_hash = hash_new ();
3604
3605 obstack_begin (&robyn, 4000);
3606 for (i = 0; i < m68k_numopcodes; i++)
3607 {
3608 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3609 do
3610 {
3611 ins = &m68k_opcodes[i];
3612 /* We *could* ignore insns that don't match our arch here
3613 but just leaving them out of the hash. */
3614 slak->m_operands = ins->args;
3615 slak->m_opnum = strlen (slak->m_operands) / 2;
3616 slak->m_arch = ins->arch;
3617 slak->m_opcode = ins->opcode;
3618 /* This is kludgey */
3619 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3620 if (i + 1 != m68k_numopcodes
3621 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3622 {
3623 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3624 i++;
3625 }
3626 else
3627 slak->m_next = 0;
3628 slak = slak->m_next;
3629 }
3630 while (slak);
3631
3632 retval = hash_insert (op_hash, ins->name, (char *) hack);
3633 if (retval)
3634 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3635 }
3636
3637 for (i = 0; i < m68k_numaliases; i++)
3638 {
3639 const char *name = m68k_opcode_aliases[i].primary;
3640 const char *alias = m68k_opcode_aliases[i].alias;
3641 PTR val = hash_find (op_hash, name);
3642 if (!val)
3643 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3644 retval = hash_insert (op_hash, alias, val);
3645 if (retval)
3646 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3647 }
3648
3649 /* In MRI mode, all unsized branches are variable sized. Normally,
3650 they are word sized. */
3651 if (flag_mri)
3652 {
3653 static struct m68k_opcode_alias mri_aliases[] =
3654 {
3655 { "bhi", "jhi", },
3656 { "bls", "jls", },
3657 { "bcc", "jcc", },
3658 { "bcs", "jcs", },
3659 { "bne", "jne", },
3660 { "beq", "jeq", },
3661 { "bvc", "jvc", },
3662 { "bvs", "jvs", },
3663 { "bpl", "jpl", },
3664 { "bmi", "jmi", },
3665 { "bge", "jge", },
3666 { "blt", "jlt", },
3667 { "bgt", "jgt", },
3668 { "ble", "jle", },
3669 { "bra", "jra", },
3670 { "bsr", "jbsr", },
3671 };
3672
3673 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3674 {
3675 const char *name = mri_aliases[i].primary;
3676 const char *alias = mri_aliases[i].alias;
3677 PTR val = hash_find (op_hash, name);
3678 if (!val)
3679 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3680 retval = hash_jam (op_hash, alias, val);
3681 if (retval)
3682 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3683 }
3684 }
3685
3686 for (i = 0; i < sizeof (mklower_table); i++)
3687 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3688
3689 for (i = 0; i < sizeof (notend_table); i++)
3690 {
3691 notend_table[i] = 0;
3692 alt_notend_table[i] = 0;
3693 }
3694 notend_table[','] = 1;
3695 notend_table['{'] = 1;
3696 notend_table['}'] = 1;
3697 alt_notend_table['a'] = 1;
3698 alt_notend_table['A'] = 1;
3699 alt_notend_table['d'] = 1;
3700 alt_notend_table['D'] = 1;
3701 alt_notend_table['#'] = 1;
3702 alt_notend_table['&'] = 1;
3703 alt_notend_table['f'] = 1;
3704 alt_notend_table['F'] = 1;
3705 #ifdef REGISTER_PREFIX
3706 alt_notend_table[REGISTER_PREFIX] = 1;
3707 #endif
3708
3709 /* We need to put '(' in alt_notend_table to handle
3710 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3711 */
3712 alt_notend_table['('] = 1;
3713
3714 /* We need to put '@' in alt_notend_table to handle
3715 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3716 */
3717 alt_notend_table['@'] = 1;
3718
3719 /* We need to put digits in alt_notend_table to handle
3720 bfextu %d0{24:1},%d0
3721 */
3722 alt_notend_table['0'] = 1;
3723 alt_notend_table['1'] = 1;
3724 alt_notend_table['2'] = 1;
3725 alt_notend_table['3'] = 1;
3726 alt_notend_table['4'] = 1;
3727 alt_notend_table['5'] = 1;
3728 alt_notend_table['6'] = 1;
3729 alt_notend_table['7'] = 1;
3730 alt_notend_table['8'] = 1;
3731 alt_notend_table['9'] = 1;
3732
3733 #ifndef MIT_SYNTAX_ONLY
3734 /* Insert pseudo ops, these have to go into the opcode table since
3735 gas expects pseudo ops to start with a dot */
3736 {
3737 int n = 0;
3738 while (mote_pseudo_table[n].poc_name)
3739 {
3740 hack = (struct m68k_incant *)
3741 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3742 hash_insert (op_hash,
3743 mote_pseudo_table[n].poc_name, (char *) hack);
3744 hack->m_operands = 0;
3745 hack->m_opnum = n;
3746 n++;
3747 }
3748 }
3749 #endif
3750
3751 init_regtable ();
3752
3753 #ifdef OBJ_ELF
3754 record_alignment (text_section, 2);
3755 record_alignment (data_section, 2);
3756 record_alignment (bss_section, 2);
3757 #endif
3758 }
3759
3760 static void
3761 select_control_regs ()
3762 {
3763 /* Note which set of "movec" control registers is available. */
3764 switch (cpu_of_arch (current_architecture))
3765 {
3766 case m68000:
3767 control_regs = m68000_control_regs;
3768 break;
3769 case m68010:
3770 control_regs = m68010_control_regs;
3771 break;
3772 case m68020:
3773 case m68030:
3774 control_regs = m68020_control_regs;
3775 break;
3776 case m68040:
3777 control_regs = m68040_control_regs;
3778 break;
3779 case m68060:
3780 control_regs = m68060_control_regs;
3781 break;
3782 case cpu32:
3783 control_regs = cpu32_control_regs;
3784 break;
3785 case mcf5200:
3786 control_regs = mcf5200_control_regs;
3787 break;
3788 default:
3789 abort ();
3790 }
3791 }
3792
3793 void
3794 m68k_init_after_args ()
3795 {
3796 if (cpu_of_arch (current_architecture) == 0)
3797 {
3798 int i;
3799 const char *default_cpu = TARGET_CPU;
3800
3801 if (*default_cpu == 'm')
3802 default_cpu++;
3803 for (i = 0; i < n_archs; i++)
3804 if (strcasecmp (default_cpu, archs[i].name) == 0)
3805 break;
3806 if (i == n_archs)
3807 {
3808 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3809 current_architecture |= m68020;
3810 }
3811 else
3812 current_architecture |= archs[i].arch;
3813 }
3814 /* Permit m68881 specification with all cpus; those that can't work
3815 with a coprocessor could be doing emulation. */
3816 if (current_architecture & m68851)
3817 {
3818 if (current_architecture & m68040)
3819 {
3820 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
3821 }
3822 }
3823 /* What other incompatibilities could we check for? */
3824
3825 /* Toss in some default assumptions about coprocessors. */
3826 if (!no_68881
3827 && (cpu_of_arch (current_architecture)
3828 /* Can CPU32 have a 68881 coprocessor?? */
3829 & (m68020 | m68030 | cpu32)))
3830 {
3831 current_architecture |= m68881;
3832 }
3833 if (!no_68851
3834 && (cpu_of_arch (current_architecture) & m68020up) != 0
3835 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3836 {
3837 current_architecture |= m68851;
3838 }
3839 if (no_68881 && (current_architecture & m68881))
3840 as_bad (_("options for 68881 and no-68881 both given"));
3841 if (no_68851 && (current_architecture & m68851))
3842 as_bad (_("options for 68851 and no-68851 both given"));
3843
3844 #ifdef OBJ_AOUT
3845 /* Work out the magic number. This isn't very general. */
3846 if (current_architecture & m68000)
3847 m68k_aout_machtype = 0;
3848 else if (current_architecture & m68010)
3849 m68k_aout_machtype = 1;
3850 else if (current_architecture & m68020)
3851 m68k_aout_machtype = 2;
3852 else
3853 m68k_aout_machtype = 2;
3854 #endif
3855
3856 /* Note which set of "movec" control registers is available. */
3857 select_control_regs ();
3858
3859 if (cpu_of_arch (current_architecture) < m68020
3860 || cpu_of_arch (current_architecture) == mcf5200)
3861 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3862 }
3863 \f
3864 /* This is called when a label is defined. */
3865
3866 void
3867 m68k_frob_label (sym)
3868 symbolS *sym;
3869 {
3870 struct label_line *n;
3871
3872 n = (struct label_line *) xmalloc (sizeof *n);
3873 n->next = labels;
3874 n->label = sym;
3875 as_where (&n->file, &n->line);
3876 n->text = 0;
3877 labels = n;
3878 current_label = n;
3879 }
3880
3881 /* This is called when a value that is not an instruction is emitted. */
3882
3883 void
3884 m68k_flush_pending_output ()
3885 {
3886 current_label = NULL;
3887 }
3888
3889 /* This is called at the end of the assembly, when the final value of
3890 the label is known. We warn if this is a text symbol aligned at an
3891 odd location. */
3892
3893 void
3894 m68k_frob_symbol (sym)
3895 symbolS *sym;
3896 {
3897 if (S_GET_SEGMENT (sym) == reg_section
3898 && (int) S_GET_VALUE (sym) < 0)
3899 {
3900 S_SET_SEGMENT (sym, absolute_section);
3901 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
3902 }
3903 else if ((S_GET_VALUE (sym) & 1) != 0)
3904 {
3905 struct label_line *l;
3906
3907 for (l = labels; l != NULL; l = l->next)
3908 {
3909 if (l->label == sym)
3910 {
3911 if (l->text)
3912 as_warn_where (l->file, l->line,
3913 _("text label `%s' aligned to odd boundary"),
3914 S_GET_NAME (sym));
3915 break;
3916 }
3917 }
3918 }
3919 }
3920 \f
3921 /* This is called if we go in or out of MRI mode because of the .mri
3922 pseudo-op. */
3923
3924 void
3925 m68k_mri_mode_change (on)
3926 int on;
3927 {
3928 if (on)
3929 {
3930 if (! flag_reg_prefix_optional)
3931 {
3932 flag_reg_prefix_optional = 1;
3933 #ifdef REGISTER_PREFIX
3934 init_regtable ();
3935 #endif
3936 }
3937 m68k_abspcadd = 1;
3938 if (! m68k_rel32_from_cmdline)
3939 m68k_rel32 = 0;
3940 }
3941 else
3942 {
3943 if (! reg_prefix_optional_seen)
3944 {
3945 #ifdef REGISTER_PREFIX_OPTIONAL
3946 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3947 #else
3948 flag_reg_prefix_optional = 0;
3949 #endif
3950 #ifdef REGISTER_PREFIX
3951 init_regtable ();
3952 #endif
3953 }
3954 m68k_abspcadd = 0;
3955 if (! m68k_rel32_from_cmdline)
3956 m68k_rel32 = 1;
3957 }
3958 }
3959
3960 /* Equal to MAX_PRECISION in atof-ieee.c */
3961 #define MAX_LITTLENUMS 6
3962
3963 /* Turn a string in input_line_pointer into a floating point constant
3964 of type type, and store the appropriate bytes in *litP. The number
3965 of LITTLENUMS emitted is stored in *sizeP . An error message is
3966 returned, or NULL on OK. */
3967
3968 char *
3969 md_atof (type, litP, sizeP)
3970 char type;
3971 char *litP;
3972 int *sizeP;
3973 {
3974 int prec;
3975 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3976 LITTLENUM_TYPE *wordP;
3977 char *t;
3978
3979 switch (type)
3980 {
3981 case 'f':
3982 case 'F':
3983 case 's':
3984 case 'S':
3985 prec = 2;
3986 break;
3987
3988 case 'd':
3989 case 'D':
3990 case 'r':
3991 case 'R':
3992 prec = 4;
3993 break;
3994
3995 case 'x':
3996 case 'X':
3997 prec = 6;
3998 break;
3999
4000 case 'p':
4001 case 'P':
4002 prec = 6;
4003 break;
4004
4005 default:
4006 *sizeP = 0;
4007 return _("Bad call to MD_ATOF()");
4008 }
4009 t = atof_ieee (input_line_pointer, type, words);
4010 if (t)
4011 input_line_pointer = t;
4012
4013 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4014 for (wordP = words; prec--;)
4015 {
4016 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4017 litP += sizeof (LITTLENUM_TYPE);
4018 }
4019 return 0;
4020 }
4021
4022 void
4023 md_number_to_chars (buf, val, n)
4024 char *buf;
4025 valueT val;
4026 int n;
4027 {
4028 number_to_chars_bigendian (buf, val, n);
4029 }
4030
4031 static void
4032 md_apply_fix_2 (fixP, val)
4033 fixS *fixP;
4034 offsetT val;
4035 {
4036 addressT upper_limit;
4037 offsetT lower_limit;
4038
4039 /* This is unnecessary but it convinces the native rs6000 compiler
4040 to generate the code we want. */
4041 char *buf = fixP->fx_frag->fr_literal;
4042 buf += fixP->fx_where;
4043 /* end ibm compiler workaround */
4044
4045 if (val & 0x80000000)
4046 val |= ~(addressT)0x7fffffff;
4047 else
4048 val &= 0x7fffffff;
4049
4050 #ifdef OBJ_ELF
4051 if (fixP->fx_addsy)
4052 {
4053 memset (buf, 0, fixP->fx_size);
4054 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4055
4056 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4057 && !S_IS_DEFINED (fixP->fx_addsy)
4058 && !S_IS_WEAK (fixP->fx_addsy))
4059 S_SET_WEAK (fixP->fx_addsy);
4060 return;
4061 }
4062 #endif
4063
4064 #ifdef BFD_ASSEMBLER
4065 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4066 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4067 return;
4068 #endif
4069
4070 switch (fixP->fx_size)
4071 {
4072 /* The cast to offsetT below are necessary to make code correct for
4073 machines where ints are smaller than offsetT */
4074 case 1:
4075 *buf++ = val;
4076 upper_limit = 0x7f;
4077 lower_limit = - (offsetT) 0x80;
4078 break;
4079 case 2:
4080 *buf++ = (val >> 8);
4081 *buf++ = val;
4082 upper_limit = 0x7fff;
4083 lower_limit = - (offsetT) 0x8000;
4084 break;
4085 case 4:
4086 *buf++ = (val >> 24);
4087 *buf++ = (val >> 16);
4088 *buf++ = (val >> 8);
4089 *buf++ = val;
4090 upper_limit = 0x7fffffff;
4091 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4092 break;
4093 default:
4094 BAD_CASE (fixP->fx_size);
4095 }
4096
4097 /* Fix up a negative reloc. */
4098 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4099 {
4100 fixP->fx_addsy = fixP->fx_subsy;
4101 fixP->fx_subsy = NULL;
4102 fixP->fx_tcbit = 1;
4103 }
4104
4105 /* For non-pc-relative values, it's conceivable we might get something
4106 like "0xff" for a byte field. So extend the upper part of the range
4107 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4108 so that we can do any range checking at all. */
4109 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4110 upper_limit = upper_limit * 2 + 1;
4111
4112 if ((addressT) val > upper_limit
4113 && (val > 0 || val < lower_limit))
4114 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4115
4116 /* A one byte PC-relative reloc means a short branch. We can't use
4117 a short branch with a value of 0 or -1, because those indicate
4118 different opcodes (branches with longer offsets). fixup_segment
4119 in write.c may have clobbered fx_pcrel, so we need to examine the
4120 reloc type. */
4121 if ((fixP->fx_pcrel
4122 #ifdef BFD_ASSEMBLER
4123 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4124 #endif
4125 )
4126 && fixP->fx_size == 1
4127 && (fixP->fx_addsy == NULL
4128 || S_IS_DEFINED (fixP->fx_addsy))
4129 && (val == 0 || val == -1))
4130 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4131 }
4132
4133 #ifdef BFD_ASSEMBLER
4134 int
4135 md_apply_fix (fixP, valp)
4136 fixS *fixP;
4137 valueT *valp;
4138 {
4139 md_apply_fix_2 (fixP, (addressT) *valp);
4140 return 1;
4141 }
4142 #else
4143 void md_apply_fix (fixP, val)
4144 fixS *fixP;
4145 long val;
4146 {
4147 md_apply_fix_2 (fixP, (addressT) val);
4148 }
4149 #endif
4150
4151 /* *fragP has been relaxed to its final size, and now needs to have
4152 the bytes inside it modified to conform to the new size There is UGLY
4153 MAGIC here. ..
4154 */
4155 static void
4156 md_convert_frag_1 (fragP)
4157 register fragS *fragP;
4158 {
4159 long disp;
4160 long ext = 0;
4161 fixS *fixP;
4162
4163 /* Address in object code of the displacement. */
4164 register int object_address = fragP->fr_fix + fragP->fr_address;
4165
4166 /* Address in gas core of the place to store the displacement. */
4167 /* This convinces the native rs6000 compiler to generate the code we
4168 want. */
4169 register char *buffer_address = fragP->fr_literal;
4170 buffer_address += fragP->fr_fix;
4171 /* end ibm compiler workaround */
4172
4173 /* The displacement of the address, from current location. */
4174 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4175 disp = (disp + fragP->fr_offset) - object_address;
4176
4177 #ifdef BFD_ASSEMBLER
4178 disp += fragP->fr_symbol->sy_frag->fr_address;
4179 #endif
4180
4181 switch (fragP->fr_subtype)
4182 {
4183 case TAB (BCC68000, BYTE):
4184 case TAB (ABRANCH, BYTE):
4185 know (issbyte (disp));
4186 if (disp == 0)
4187 as_bad (_("short branch with zero offset: use :w"));
4188 fragP->fr_opcode[1] = disp;
4189 ext = 0;
4190 break;
4191 case TAB (DBCC, SHORT):
4192 know (issword (disp));
4193 ext = 2;
4194 break;
4195 case TAB (BCC68000, SHORT):
4196 case TAB (ABRANCH, SHORT):
4197 know (issword (disp));
4198 fragP->fr_opcode[1] = 0x00;
4199 ext = 2;
4200 break;
4201 case TAB (ABRANCH, LONG):
4202 if (!HAVE_LONG_BRANCH(current_architecture))
4203 {
4204 if (fragP->fr_opcode[0] == 0x61)
4205 /* BSR */
4206 {
4207 fragP->fr_opcode[0] = 0x4E;
4208 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4209
4210 fix_new (fragP,
4211 fragP->fr_fix,
4212 4,
4213 fragP->fr_symbol,
4214 fragP->fr_offset,
4215 0,
4216 NO_RELOC);
4217
4218 fragP->fr_fix += 4;
4219 ext = 0;
4220 }
4221 /* BRA */
4222 else if (fragP->fr_opcode[0] == 0x60)
4223 {
4224 fragP->fr_opcode[0] = 0x4E;
4225 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4226 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4227 fragP->fr_offset, 0, NO_RELOC);
4228 fragP->fr_fix += 4;
4229 ext = 0;
4230 }
4231 else
4232 {
4233 as_bad (_("Long branch offset not supported."));
4234 }
4235 }
4236 else
4237 {
4238 fragP->fr_opcode[1] = (char) 0xff;
4239 ext = 4;
4240 }
4241 break;
4242 case TAB (BCC68000, LONG):
4243 /* only Bcc 68000 instructions can come here */
4244 /* change bcc into b!cc/jmp absl long */
4245 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4246 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4247
4248 /* JF: these used to be fr_opcode[2,3], but they may be in a
4249 different frag, in which case refering to them is a no-no.
4250 Only fr_opcode[0,1] are guaranteed to work. */
4251 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4252 *buffer_address++ = (char) 0xf9;
4253 fragP->fr_fix += 2; /* account for jmp instruction */
4254 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4255 fragP->fr_offset, 0, NO_RELOC);
4256 fragP->fr_fix += 4;
4257 ext = 0;
4258 break;
4259 case TAB (DBCC, LONG):
4260 /* only DBcc 68000 instructions can come here */
4261 /* change dbcc into dbcc/jmp absl long */
4262 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4263 *buffer_address++ = 0x00; /* branch offset = 4 */
4264 *buffer_address++ = 0x04;
4265 *buffer_address++ = 0x60; /* put in bra pc+6 */
4266 *buffer_address++ = 0x06;
4267 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4268 *buffer_address++ = (char) 0xf9;
4269
4270 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4271 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4272 fragP->fr_offset, 0, NO_RELOC);
4273 fragP->fr_fix += 4;
4274 ext = 0;
4275 break;
4276 case TAB (FBRANCH, SHORT):
4277 know ((fragP->fr_opcode[1] & 0x40) == 0);
4278 ext = 2;
4279 break;
4280 case TAB (FBRANCH, LONG):
4281 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4282 ext = 4;
4283 break;
4284 case TAB (PCREL, SHORT):
4285 ext = 2;
4286 break;
4287 case TAB (PCREL, LONG):
4288 /* The thing to do here is force it to ABSOLUTE LONG, since
4289 PCREL is really trying to shorten an ABSOLUTE address anyway */
4290 /* JF FOO This code has not been tested */
4291 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4292 0, NO_RELOC);
4293 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4294 as_bad (_("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx"),
4295 (unsigned) fragP->fr_opcode[0],
4296 (unsigned long) fragP->fr_address);
4297 fragP->fr_opcode[1] &= ~0x3F;
4298 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4299 fragP->fr_fix += 4;
4300 ext = 0;
4301 break;
4302 case TAB (PCLEA, SHORT):
4303 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4304 fragP->fr_offset, 1, NO_RELOC);
4305 fragP->fr_opcode[1] &= ~0x3F;
4306 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4307 ext = 2;
4308 break;
4309 case TAB (PCLEA, LONG):
4310 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4311 fragP->fr_offset, 1, NO_RELOC);
4312 fixP->fx_pcrel_adjust = 2;
4313 /* Already set to mode 7.3; this indicates: PC indirect with
4314 suppressed index, 32-bit displacement. */
4315 *buffer_address++ = 0x01;
4316 *buffer_address++ = 0x70;
4317 fragP->fr_fix += 2;
4318 ext = 4;
4319 break;
4320
4321 case TAB (PCINDEX, BYTE):
4322 disp += 2;
4323 if (!issbyte (disp))
4324 {
4325 as_bad (_("displacement doesn't fit in one byte"));
4326 disp = 0;
4327 }
4328 assert (fragP->fr_fix >= 2);
4329 buffer_address[-2] &= ~1;
4330 buffer_address[-1] = disp;
4331 ext = 0;
4332 break;
4333 case TAB (PCINDEX, SHORT):
4334 disp += 2;
4335 assert (issword (disp));
4336 assert (fragP->fr_fix >= 2);
4337 buffer_address[-2] |= 0x1;
4338 buffer_address[-1] = 0x20;
4339 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4340 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4341 NO_RELOC);
4342 fixP->fx_pcrel_adjust = 2;
4343 ext = 2;
4344 break;
4345 case TAB (PCINDEX, LONG):
4346 disp += 2;
4347 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4348 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4349 NO_RELOC);
4350 fixP->fx_pcrel_adjust = 2;
4351 assert (fragP->fr_fix >= 2);
4352 buffer_address[-2] |= 0x1;
4353 buffer_address[-1] = 0x30;
4354 ext = 4;
4355 break;
4356 }
4357
4358 if (ext)
4359 {
4360 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4361 fragP->fr_fix += ext;
4362 }
4363 }
4364
4365 #ifndef BFD_ASSEMBLER
4366
4367 void
4368 md_convert_frag (headers, sec, fragP)
4369 object_headers *headers;
4370 segT sec;
4371 fragS *fragP;
4372 {
4373 md_convert_frag_1 (fragP);
4374 }
4375
4376 #else
4377
4378 void
4379 md_convert_frag (abfd, sec, fragP)
4380 bfd *abfd;
4381 segT sec;
4382 fragS *fragP;
4383 {
4384 md_convert_frag_1 (fragP);
4385 }
4386 #endif
4387
4388 /* Force truly undefined symbols to their maximum size, and generally set up
4389 the frag list to be relaxed
4390 */
4391 int
4392 md_estimate_size_before_relax (fragP, segment)
4393 register fragS *fragP;
4394 segT segment;
4395 {
4396 int old_fix;
4397 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4398
4399 old_fix = fragP->fr_fix;
4400
4401 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4402 switch (fragP->fr_subtype)
4403 {
4404
4405 case TAB (ABRANCH, SZ_UNDEF):
4406 {
4407 if ((fragP->fr_symbol != NULL) /* Not absolute */
4408 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4409 && relaxable_symbol (fragP->fr_symbol))
4410 {
4411 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4412 break;
4413 }
4414 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4415 {
4416 /* On 68000, or for absolute value, switch to abs long */
4417 /* FIXME, we should check abs val, pick short or long */
4418 if (fragP->fr_opcode[0] == 0x61)
4419 {
4420 fragP->fr_opcode[0] = 0x4E;
4421 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4422 fix_new (fragP, fragP->fr_fix, 4,
4423 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4424 fragP->fr_fix += 4;
4425 frag_wane (fragP);
4426 }
4427 else if (fragP->fr_opcode[0] == 0x60)
4428 {
4429 fragP->fr_opcode[0] = 0x4E;
4430 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4431 fix_new (fragP, fragP->fr_fix, 4,
4432 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4433 fragP->fr_fix += 4;
4434 frag_wane (fragP);
4435 }
4436 else
4437 {
4438 as_warn (_("Long branch offset to extern symbol not supported."));
4439 }
4440 }
4441 else
4442 { /* Symbol is still undefined. Make it simple */
4443 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4444 fragP->fr_offset, 1, NO_RELOC);
4445 fragP->fr_fix += 4;
4446 fragP->fr_opcode[1] = (char) 0xff;
4447 frag_wane (fragP);
4448 break;
4449 }
4450
4451 break;
4452 } /* case TAB(ABRANCH,SZ_UNDEF) */
4453
4454 case TAB (FBRANCH, SZ_UNDEF):
4455 {
4456 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4457 && relaxable_symbol (fragP->fr_symbol))
4458 || flag_short_refs)
4459 {
4460 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4461 fragP->fr_var += 2;
4462 }
4463 else
4464 {
4465 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4466 fragP->fr_offset, 1, NO_RELOC);
4467 fragP->fr_fix += 4;
4468 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4469 frag_wane (fragP);
4470 }
4471 break;
4472 } /* TAB(FBRANCH,SZ_UNDEF) */
4473
4474 case TAB (PCREL, SZ_UNDEF):
4475 {
4476 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4477 && relaxable_symbol (fragP->fr_symbol))
4478 || flag_short_refs
4479 || cpu_of_arch (current_architecture) < m68020
4480 || cpu_of_arch (current_architecture) == mcf5200)
4481 {
4482 fragP->fr_subtype = TAB (PCREL, SHORT);
4483 fragP->fr_var += 2;
4484 }
4485 else
4486 {
4487 fragP->fr_subtype = TAB (PCREL, LONG);
4488 fragP->fr_var += 4;
4489 }
4490 break;
4491 } /* TAB(PCREL,SZ_UNDEF) */
4492
4493 case TAB (BCC68000, SZ_UNDEF):
4494 {
4495 if ((fragP->fr_symbol != NULL)
4496 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4497 && relaxable_symbol (fragP->fr_symbol))
4498 {
4499 fragP->fr_subtype = TAB (BCC68000, BYTE);
4500 break;
4501 }
4502 /* only Bcc 68000 instructions can come here */
4503 /* change bcc into b!cc/jmp absl long */
4504 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4505 if (flag_short_refs)
4506 {
4507 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4508 /* JF: these were fr_opcode[2,3] */
4509 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4510 buffer_address[1] = (char) 0xf8;
4511 fragP->fr_fix += 2; /* account for jmp instruction */
4512 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4513 fragP->fr_offset, 0, NO_RELOC);
4514 fragP->fr_fix += 2;
4515 }
4516 else
4517 {
4518 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4519 /* JF: these were fr_opcode[2,3] */
4520 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4521 buffer_address[1] = (char) 0xf9;
4522 fragP->fr_fix += 2; /* account for jmp instruction */
4523 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4524 fragP->fr_offset, 0, NO_RELOC);
4525 fragP->fr_fix += 4;
4526 }
4527 frag_wane (fragP);
4528 break;
4529 } /* case TAB(BCC68000,SZ_UNDEF) */
4530
4531 case TAB (DBCC, SZ_UNDEF):
4532 {
4533 if (fragP->fr_symbol != NULL
4534 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4535 && relaxable_symbol (fragP->fr_symbol))
4536 {
4537 fragP->fr_subtype = TAB (DBCC, SHORT);
4538 fragP->fr_var += 2;
4539 break;
4540 }
4541 /* only DBcc 68000 instructions can come here */
4542 /* change dbcc into dbcc/jmp absl long */
4543 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4544 buffer_address[0] = 0x00; /* branch offset = 4 */
4545 buffer_address[1] = 0x04;
4546 buffer_address[2] = 0x60; /* put in bra pc + ... */
4547
4548 if (flag_short_refs)
4549 {
4550 /* JF: these were fr_opcode[5-7] */
4551 buffer_address[3] = 0x04; /* plus 4 */
4552 buffer_address[4] = 0x4e; /* Put in Jump Word */
4553 buffer_address[5] = (char) 0xf8;
4554 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4555 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4556 fragP->fr_offset, 0, NO_RELOC);
4557 fragP->fr_fix += 2;
4558 }
4559 else
4560 {
4561 /* JF: these were fr_opcode[5-7] */
4562 buffer_address[3] = 0x06; /* Plus 6 */
4563 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4564 buffer_address[5] = (char) 0xf9;
4565 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4566 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4567 fragP->fr_offset, 0, NO_RELOC);
4568 fragP->fr_fix += 4;
4569 }
4570
4571 frag_wane (fragP);
4572 break;
4573 } /* case TAB(DBCC,SZ_UNDEF) */
4574
4575 case TAB (PCLEA, SZ_UNDEF):
4576 {
4577 if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4578 && relaxable_symbol (fragP->fr_symbol))
4579 || flag_short_refs
4580 || cpu_of_arch (current_architecture) < m68020
4581 || cpu_of_arch (current_architecture) == mcf5200)
4582 {
4583 fragP->fr_subtype = TAB (PCLEA, SHORT);
4584 fragP->fr_var += 2;
4585 }
4586 else
4587 {
4588 fragP->fr_subtype = TAB (PCLEA, LONG);
4589 fragP->fr_var += 6;
4590 }
4591 break;
4592 } /* TAB(PCLEA,SZ_UNDEF) */
4593
4594 case TAB (PCINDEX, SZ_UNDEF):
4595 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4596 && relaxable_symbol (fragP->fr_symbol))
4597 || cpu_of_arch (current_architecture) < m68020
4598 || cpu_of_arch (current_architecture) == mcf5200)
4599 {
4600 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4601 }
4602 else
4603 {
4604 fragP->fr_subtype = TAB (PCINDEX, LONG);
4605 fragP->fr_var += 4;
4606 }
4607 break;
4608
4609 default:
4610 break;
4611 }
4612
4613 /* now that SZ_UNDEF are taken care of, check others */
4614 switch (fragP->fr_subtype)
4615 {
4616 case TAB (BCC68000, BYTE):
4617 case TAB (ABRANCH, BYTE):
4618 /* We can't do a short jump to the next instruction, so in that
4619 case we force word mode. At this point S_GET_VALUE should
4620 return the offset of the symbol within its frag. If the
4621 symbol is at the start of a frag, and it is the next frag
4622 with any data in it (usually this is just the next frag, but
4623 assembler listings may introduce empty frags), we must use
4624 word mode. */
4625 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4626 {
4627 fragS *l;
4628
4629 for (l = fragP->fr_next;
4630 l != fragP->fr_symbol->sy_frag;
4631 l = l->fr_next)
4632 if (l->fr_fix + l->fr_var != 0)
4633 break;
4634 if (l == fragP->fr_symbol->sy_frag)
4635 {
4636 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4637 fragP->fr_var += 2;
4638 }
4639 }
4640 break;
4641 default:
4642 break;
4643 }
4644 return fragP->fr_var + fragP->fr_fix - old_fix;
4645 }
4646
4647 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4648 /* the bit-field entries in the relocation_info struct plays hell
4649 with the byte-order problems of cross-assembly. So as a hack,
4650 I added this mach. dependent ri twiddler. Ugly, but it gets
4651 you there. -KWK */
4652 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4653 are symbolnum, most sig. byte first. Last byte is broken up with
4654 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4655 nibble as nuthin. (on Sun 3 at least) */
4656 /* Translate the internal relocation information into target-specific
4657 format. */
4658 #ifdef comment
4659 void
4660 md_ri_to_chars (the_bytes, ri)
4661 char *the_bytes;
4662 struct reloc_info_generic *ri;
4663 {
4664 /* this is easy */
4665 md_number_to_chars (the_bytes, ri->r_address, 4);
4666 /* now the fun stuff */
4667 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4668 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4669 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4670 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4671 ((ri->r_extern << 4) & 0x10));
4672 }
4673
4674 #endif /* comment */
4675
4676 #ifndef BFD_ASSEMBLER
4677 void
4678 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4679 char *where;
4680 fixS *fixP;
4681 relax_addressT segment_address_in_file;
4682 {
4683 /*
4684 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4685 * Out: GNU LD relocation length code: 0, 1, or 2.
4686 */
4687
4688 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4689 long r_symbolnum;
4690
4691 know (fixP->fx_addsy != NULL);
4692
4693 md_number_to_chars (where,
4694 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4695 4);
4696
4697 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4698 ? S_GET_TYPE (fixP->fx_addsy)
4699 : fixP->fx_addsy->sy_number);
4700
4701 where[4] = (r_symbolnum >> 16) & 0x0ff;
4702 where[5] = (r_symbolnum >> 8) & 0x0ff;
4703 where[6] = r_symbolnum & 0x0ff;
4704 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4705 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4706 }
4707 #endif
4708
4709 #endif /* OBJ_AOUT or OBJ_BOUT */
4710
4711 #ifndef WORKING_DOT_WORD
4712 CONST int md_short_jump_size = 4;
4713 CONST int md_long_jump_size = 6;
4714
4715 void
4716 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4717 char *ptr;
4718 addressT from_addr, to_addr;
4719 fragS *frag;
4720 symbolS *to_symbol;
4721 {
4722 valueT offset;
4723
4724 offset = to_addr - (from_addr + 2);
4725
4726 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4727 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4728 }
4729
4730 void
4731 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4732 char *ptr;
4733 addressT from_addr, to_addr;
4734 fragS *frag;
4735 symbolS *to_symbol;
4736 {
4737 valueT offset;
4738
4739 if (!HAVE_LONG_BRANCH(current_architecture))
4740 {
4741 offset = to_addr - S_GET_VALUE (to_symbol);
4742 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4743 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4744 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4745 0, NO_RELOC);
4746 }
4747 else
4748 {
4749 offset = to_addr - (from_addr + 2);
4750 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4751 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4752 }
4753 }
4754
4755 #endif
4756
4757 /* Different values of OK tell what its OK to return. Things that
4758 aren't OK are an error (what a shock, no?)
4759
4760 0: Everything is OK
4761 10: Absolute 1:8 only
4762 20: Absolute 0:7 only
4763 30: absolute 0:15 only
4764 40: Absolute 0:31 only
4765 50: absolute 0:127 only
4766 55: absolute -64:63 only
4767 60: absolute -128:127 only
4768 70: absolute 0:4095 only
4769 80: No bignums
4770
4771 */
4772
4773 static int
4774 get_num (exp, ok)
4775 struct m68k_exp *exp;
4776 int ok;
4777 {
4778 if (exp->exp.X_op == O_absent)
4779 {
4780 /* Do the same thing the VAX asm does */
4781 op (exp) = O_constant;
4782 adds (exp) = 0;
4783 subs (exp) = 0;
4784 offs (exp) = 0;
4785 if (ok == 10)
4786 {
4787 as_warn (_("expression out of range: defaulting to 1"));
4788 offs (exp) = 1;
4789 }
4790 }
4791 else if (exp->exp.X_op == O_constant)
4792 {
4793 switch (ok)
4794 {
4795 case 10:
4796 if (offs (exp) < 1 || offs (exp) > 8)
4797 {
4798 as_warn (_("expression out of range: defaulting to 1"));
4799 offs (exp) = 1;
4800 }
4801 break;
4802 case 20:
4803 if (offs (exp) < 0 || offs (exp) > 7)
4804 goto outrange;
4805 break;
4806 case 30:
4807 if (offs (exp) < 0 || offs (exp) > 15)
4808 goto outrange;
4809 break;
4810 case 40:
4811 if (offs (exp) < 0 || offs (exp) > 32)
4812 goto outrange;
4813 break;
4814 case 50:
4815 if (offs (exp) < 0 || offs (exp) > 127)
4816 goto outrange;
4817 break;
4818 case 55:
4819 if (offs (exp) < -64 || offs (exp) > 63)
4820 goto outrange;
4821 break;
4822 case 60:
4823 if (offs (exp) < -128 || offs (exp) > 127)
4824 goto outrange;
4825 break;
4826 case 70:
4827 if (offs (exp) < 0 || offs (exp) > 4095)
4828 {
4829 outrange:
4830 as_warn (_("expression out of range: defaulting to 0"));
4831 offs (exp) = 0;
4832 }
4833 break;
4834 default:
4835 break;
4836 }
4837 }
4838 else if (exp->exp.X_op == O_big)
4839 {
4840 if (offs (exp) <= 0 /* flonum */
4841 && (ok == 80 /* no bignums */
4842 || (ok > 10 /* small-int ranges including 0 ok */
4843 /* If we have a flonum zero, a zero integer should
4844 do as well (e.g., in moveq). */
4845 && generic_floating_point_number.exponent == 0
4846 && generic_floating_point_number.low[0] == 0)))
4847 {
4848 /* HACK! Turn it into a long */
4849 LITTLENUM_TYPE words[6];
4850
4851 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4852 op (exp) = O_constant;
4853 adds (exp) = 0;
4854 subs (exp) = 0;
4855 offs (exp) = words[1] | (words[0] << 16);
4856 }
4857 else if (ok != 0)
4858 {
4859 op (exp) = O_constant;
4860 adds (exp) = 0;
4861 subs (exp) = 0;
4862 offs (exp) = (ok == 10) ? 1 : 0;
4863 as_warn (_("Can't deal with expression; defaulting to %ld"),
4864 offs (exp));
4865 }
4866 }
4867 else
4868 {
4869 if (ok >= 10 && ok <= 70)
4870 {
4871 op (exp) = O_constant;
4872 adds (exp) = 0;
4873 subs (exp) = 0;
4874 offs (exp) = (ok == 10) ? 1 : 0;
4875 as_warn (_("Can't deal with expression; defaulting to %ld"),
4876 offs (exp));
4877 }
4878 }
4879
4880 if (exp->size != SIZE_UNSPEC)
4881 {
4882 switch (exp->size)
4883 {
4884 case SIZE_UNSPEC:
4885 case SIZE_LONG:
4886 break;
4887 case SIZE_BYTE:
4888 if (!isbyte (offs (exp)))
4889 as_warn (_("expression doesn't fit in BYTE"));
4890 break;
4891 case SIZE_WORD:
4892 if (!isword (offs (exp)))
4893 as_warn (_("expression doesn't fit in WORD"));
4894 break;
4895 }
4896 }
4897
4898 return offs (exp);
4899 }
4900
4901 /* These are the back-ends for the various machine dependent pseudo-ops. */
4902
4903 static void
4904 s_data1 (ignore)
4905 int ignore;
4906 {
4907 subseg_set (data_section, 1);
4908 demand_empty_rest_of_line ();
4909 }
4910
4911 static void
4912 s_data2 (ignore)
4913 int ignore;
4914 {
4915 subseg_set (data_section, 2);
4916 demand_empty_rest_of_line ();
4917 }
4918
4919 static void
4920 s_bss (ignore)
4921 int ignore;
4922 {
4923 /* We don't support putting frags in the BSS segment, we fake it
4924 by marking in_bss, then looking at s_skip for clues. */
4925
4926 subseg_set (bss_section, 0);
4927 demand_empty_rest_of_line ();
4928 }
4929
4930 static void
4931 s_even (ignore)
4932 int ignore;
4933 {
4934 register int temp;
4935 register long temp_fill;
4936
4937 temp = 1; /* JF should be 2? */
4938 temp_fill = get_absolute_expression ();
4939 if (!need_pass_2) /* Never make frag if expect extra pass. */
4940 frag_align (temp, (int) temp_fill, 0);
4941 demand_empty_rest_of_line ();
4942 record_alignment (now_seg, temp);
4943 }
4944
4945 static void
4946 s_proc (ignore)
4947 int ignore;
4948 {
4949 demand_empty_rest_of_line ();
4950 }
4951 \f
4952 /* Pseudo-ops handled for MRI compatibility. */
4953
4954 /* This function returns non-zero if the argument is a conditional
4955 pseudo-op. This is called when checking whether a pending
4956 alignment is needed. */
4957
4958 int
4959 m68k_conditional_pseudoop (pop)
4960 pseudo_typeS *pop;
4961 {
4962 return (pop->poc_handler == s_mri_if
4963 || pop->poc_handler == s_mri_else);
4964 }
4965
4966 /* Handle an MRI style chip specification. */
4967
4968 static void
4969 mri_chip ()
4970 {
4971 char *s;
4972 char c;
4973 int i;
4974
4975 s = input_line_pointer;
4976 /* We can't use get_symbol_end since the processor names are not proper
4977 symbols. */
4978 while (is_part_of_name (c = *input_line_pointer++))
4979 ;
4980 *--input_line_pointer = 0;
4981 for (i = 0; i < n_archs; i++)
4982 if (strcasecmp (s, archs[i].name) == 0)
4983 break;
4984 if (i >= n_archs)
4985 {
4986 as_bad (_("%s: unrecognized processor name"), s);
4987 *input_line_pointer = c;
4988 ignore_rest_of_line ();
4989 return;
4990 }
4991 *input_line_pointer = c;
4992
4993 if (*input_line_pointer == '/')
4994 current_architecture = 0;
4995 else
4996 current_architecture &= m68881 | m68851;
4997 current_architecture |= archs[i].arch;
4998
4999 while (*input_line_pointer == '/')
5000 {
5001 ++input_line_pointer;
5002 s = input_line_pointer;
5003 /* We can't use get_symbol_end since the processor names are not
5004 proper symbols. */
5005 while (is_part_of_name (c = *input_line_pointer++))
5006 ;
5007 *--input_line_pointer = 0;
5008 if (strcmp (s, "68881") == 0)
5009 current_architecture |= m68881;
5010 else if (strcmp (s, "68851") == 0)
5011 current_architecture |= m68851;
5012 *input_line_pointer = c;
5013 }
5014
5015 /* Update info about available control registers. */
5016 select_control_regs ();
5017 }
5018
5019 /* The MRI CHIP pseudo-op. */
5020
5021 static void
5022 s_chip (ignore)
5023 int ignore;
5024 {
5025 char *stop = NULL;
5026 char stopc;
5027
5028 if (flag_mri)
5029 stop = mri_comment_field (&stopc);
5030 mri_chip ();
5031 if (flag_mri)
5032 mri_comment_end (stop, stopc);
5033 demand_empty_rest_of_line ();
5034 }
5035
5036 /* The MRI FOPT pseudo-op. */
5037
5038 static void
5039 s_fopt (ignore)
5040 int ignore;
5041 {
5042 SKIP_WHITESPACE ();
5043
5044 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5045 {
5046 int temp;
5047
5048 input_line_pointer += 3;
5049 temp = get_absolute_expression ();
5050 if (temp < 0 || temp > 7)
5051 as_bad (_("bad coprocessor id"));
5052 else
5053 m68k_float_copnum = COP0 + temp;
5054 }
5055 else
5056 {
5057 as_bad (_("unrecognized fopt option"));
5058 ignore_rest_of_line ();
5059 return;
5060 }
5061
5062 demand_empty_rest_of_line ();
5063 }
5064
5065 /* The structure used to handle the MRI OPT pseudo-op. */
5066
5067 struct opt_action
5068 {
5069 /* The name of the option. */
5070 const char *name;
5071
5072 /* If this is not NULL, just call this function. The first argument
5073 is the ARG field of this structure, the second argument is
5074 whether the option was negated. */
5075 void (*pfn) PARAMS ((int arg, int on));
5076
5077 /* If this is not NULL, and the PFN field is NULL, set the variable
5078 this points to. Set it to the ARG field if the option was not
5079 negated, and the NOTARG field otherwise. */
5080 int *pvar;
5081
5082 /* The value to pass to PFN or to assign to *PVAR. */
5083 int arg;
5084
5085 /* The value to assign to *PVAR if the option is negated. If PFN is
5086 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5087 the option may not be negated. */
5088 int notarg;
5089 };
5090
5091 /* The table used to handle the MRI OPT pseudo-op. */
5092
5093 static void skip_to_comma PARAMS ((int, int));
5094 static void opt_nest PARAMS ((int, int));
5095 static void opt_chip PARAMS ((int, int));
5096 static void opt_list PARAMS ((int, int));
5097 static void opt_list_symbols PARAMS ((int, int));
5098
5099 static const struct opt_action opt_table[] =
5100 {
5101 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5102
5103 /* We do relaxing, so there is little use for these options. */
5104 { "b", 0, 0, 0, 0 },
5105 { "brs", 0, 0, 0, 0 },
5106 { "brb", 0, 0, 0, 0 },
5107 { "brl", 0, 0, 0, 0 },
5108 { "brw", 0, 0, 0, 0 },
5109
5110 { "c", 0, 0, 0, 0 },
5111 { "cex", 0, 0, 0, 0 },
5112 { "case", 0, &symbols_case_sensitive, 1, 0 },
5113 { "cl", 0, 0, 0, 0 },
5114 { "cre", 0, 0, 0, 0 },
5115 { "d", 0, &flag_keep_locals, 1, 0 },
5116 { "e", 0, 0, 0, 0 },
5117 { "f", 0, &flag_short_refs, 1, 0 },
5118 { "frs", 0, &flag_short_refs, 1, 0 },
5119 { "frl", 0, &flag_short_refs, 0, 1 },
5120 { "g", 0, 0, 0, 0 },
5121 { "i", 0, 0, 0, 0 },
5122 { "m", 0, 0, 0, 0 },
5123 { "mex", 0, 0, 0, 0 },
5124 { "mc", 0, 0, 0, 0 },
5125 { "md", 0, 0, 0, 0 },
5126 { "nest", opt_nest, 0, 0, 0 },
5127 { "next", skip_to_comma, 0, 0, 0 },
5128 { "o", 0, 0, 0, 0 },
5129 { "old", 0, 0, 0, 0 },
5130 { "op", skip_to_comma, 0, 0, 0 },
5131 { "pco", 0, 0, 0, 0 },
5132 { "p", opt_chip, 0, 0, 0 },
5133 { "pcr", 0, 0, 0, 0 },
5134 { "pcs", 0, 0, 0, 0 },
5135 { "r", 0, 0, 0, 0 },
5136 { "quick", 0, &m68k_quick, 1, 0 },
5137 { "rel32", 0, &m68k_rel32, 1, 0 },
5138 { "s", opt_list, 0, 0, 0 },
5139 { "t", opt_list_symbols, 0, 0, 0 },
5140 { "w", 0, &flag_no_warnings, 0, 1 },
5141 { "x", 0, 0, 0, 0 }
5142 };
5143
5144 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5145
5146 /* The MRI OPT pseudo-op. */
5147
5148 static void
5149 s_opt (ignore)
5150 int ignore;
5151 {
5152 do
5153 {
5154 int t;
5155 char *s;
5156 char c;
5157 int i;
5158 const struct opt_action *o;
5159
5160 SKIP_WHITESPACE ();
5161
5162 t = 1;
5163 if (*input_line_pointer == '-')
5164 {
5165 ++input_line_pointer;
5166 t = 0;
5167 }
5168 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5169 {
5170 input_line_pointer += 2;
5171 t = 0;
5172 }
5173
5174 s = input_line_pointer;
5175 c = get_symbol_end ();
5176
5177 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5178 {
5179 if (strcasecmp (s, o->name) == 0)
5180 {
5181 if (o->pfn)
5182 {
5183 /* Restore input_line_pointer now in case the option
5184 takes arguments. */
5185 *input_line_pointer = c;
5186 (*o->pfn) (o->arg, t);
5187 }
5188 else if (o->pvar != NULL)
5189 {
5190 if (! t && o->arg == o->notarg)
5191 as_bad (_("option `%s' may not be negated"), s);
5192 *input_line_pointer = c;
5193 *o->pvar = t ? o->arg : o->notarg;
5194 }
5195 else
5196 *input_line_pointer = c;
5197 break;
5198 }
5199 }
5200 if (i >= OPTCOUNT)
5201 {
5202 as_bad (_("option `%s' not recognized"), s);
5203 *input_line_pointer = c;
5204 }
5205 }
5206 while (*input_line_pointer++ == ',');
5207
5208 /* Move back to terminating character. */
5209 --input_line_pointer;
5210 demand_empty_rest_of_line ();
5211 }
5212
5213 /* Skip ahead to a comma. This is used for OPT options which we do
5214 not suppor tand which take arguments. */
5215
5216 static void
5217 skip_to_comma (arg, on)
5218 int arg;
5219 int on;
5220 {
5221 while (*input_line_pointer != ','
5222 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5223 ++input_line_pointer;
5224 }
5225
5226 /* Handle the OPT NEST=depth option. */
5227
5228 static void
5229 opt_nest (arg, on)
5230 int arg;
5231 int on;
5232 {
5233 if (*input_line_pointer != '=')
5234 {
5235 as_bad (_("bad format of OPT NEST=depth"));
5236 return;
5237 }
5238
5239 ++input_line_pointer;
5240 max_macro_nest = get_absolute_expression ();
5241 }
5242
5243 /* Handle the OPT P=chip option. */
5244
5245 static void
5246 opt_chip (arg, on)
5247 int arg;
5248 int on;
5249 {
5250 if (*input_line_pointer != '=')
5251 {
5252 /* This is just OPT P, which we do not support. */
5253 return;
5254 }
5255
5256 ++input_line_pointer;
5257 mri_chip ();
5258 }
5259
5260 /* Handle the OPT S option. */
5261
5262 static void
5263 opt_list (arg, on)
5264 int arg;
5265 int on;
5266 {
5267 listing_list (on);
5268 }
5269
5270 /* Handle the OPT T option. */
5271
5272 static void
5273 opt_list_symbols (arg, on)
5274 int arg;
5275 int on;
5276 {
5277 if (on)
5278 listing |= LISTING_SYMBOLS;
5279 else
5280 listing &=~ LISTING_SYMBOLS;
5281 }
5282
5283 /* Handle the MRI REG pseudo-op. */
5284
5285 static void
5286 s_reg (ignore)
5287 int ignore;
5288 {
5289 char *s;
5290 int c;
5291 struct m68k_op rop;
5292 int mask;
5293 char *stop = NULL;
5294 char stopc;
5295
5296 if (line_label == NULL)
5297 {
5298 as_bad (_("missing label"));
5299 ignore_rest_of_line ();
5300 return;
5301 }
5302
5303 if (flag_mri)
5304 stop = mri_comment_field (&stopc);
5305
5306 SKIP_WHITESPACE ();
5307
5308 s = input_line_pointer;
5309 while (isalnum ((unsigned char) *input_line_pointer)
5310 #ifdef REGISTER_PREFIX
5311 || *input_line_pointer == REGISTER_PREFIX
5312 #endif
5313 || *input_line_pointer == '/'
5314 || *input_line_pointer == '-')
5315 ++input_line_pointer;
5316 c = *input_line_pointer;
5317 *input_line_pointer = '\0';
5318
5319 if (m68k_ip_op (s, &rop) != 0)
5320 {
5321 if (rop.error == NULL)
5322 as_bad (_("bad register list"));
5323 else
5324 as_bad (_("bad register list: %s"), rop.error);
5325 *input_line_pointer = c;
5326 ignore_rest_of_line ();
5327 return;
5328 }
5329
5330 *input_line_pointer = c;
5331
5332 if (rop.mode == REGLST)
5333 mask = rop.mask;
5334 else if (rop.mode == DREG)
5335 mask = 1 << (rop.reg - DATA0);
5336 else if (rop.mode == AREG)
5337 mask = 1 << (rop.reg - ADDR0 + 8);
5338 else if (rop.mode == FPREG)
5339 mask = 1 << (rop.reg - FP0 + 16);
5340 else if (rop.mode == CONTROL
5341 && rop.reg == FPI)
5342 mask = 1 << 24;
5343 else if (rop.mode == CONTROL
5344 && rop.reg == FPS)
5345 mask = 1 << 25;
5346 else if (rop.mode == CONTROL
5347 && rop.reg == FPC)
5348 mask = 1 << 26;
5349 else
5350 {
5351 as_bad (_("bad register list"));
5352 ignore_rest_of_line ();
5353 return;
5354 }
5355
5356 S_SET_SEGMENT (line_label, reg_section);
5357 S_SET_VALUE (line_label, ~mask);
5358 line_label->sy_frag = &zero_address_frag;
5359
5360 if (flag_mri)
5361 mri_comment_end (stop, stopc);
5362
5363 demand_empty_rest_of_line ();
5364 }
5365
5366 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5367
5368 struct save_opts
5369 {
5370 struct save_opts *next;
5371 int abspcadd;
5372 int symbols_case_sensitive;
5373 int keep_locals;
5374 int short_refs;
5375 int architecture;
5376 int quick;
5377 int rel32;
5378 int listing;
5379 int no_warnings;
5380 /* FIXME: We don't save OPT S. */
5381 };
5382
5383 /* This variable holds the stack of saved options. */
5384
5385 static struct save_opts *save_stack;
5386
5387 /* The MRI SAVE pseudo-op. */
5388
5389 static void
5390 s_save (ignore)
5391 int ignore;
5392 {
5393 struct save_opts *s;
5394
5395 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5396 s->abspcadd = m68k_abspcadd;
5397 s->symbols_case_sensitive = symbols_case_sensitive;
5398 s->keep_locals = flag_keep_locals;
5399 s->short_refs = flag_short_refs;
5400 s->architecture = current_architecture;
5401 s->quick = m68k_quick;
5402 s->rel32 = m68k_rel32;
5403 s->listing = listing;
5404 s->no_warnings = flag_no_warnings;
5405
5406 s->next = save_stack;
5407 save_stack = s;
5408
5409 demand_empty_rest_of_line ();
5410 }
5411
5412 /* The MRI RESTORE pseudo-op. */
5413
5414 static void
5415 s_restore (ignore)
5416 int ignore;
5417 {
5418 struct save_opts *s;
5419
5420 if (save_stack == NULL)
5421 {
5422 as_bad (_("restore without save"));
5423 ignore_rest_of_line ();
5424 return;
5425 }
5426
5427 s = save_stack;
5428 save_stack = s->next;
5429
5430 m68k_abspcadd = s->abspcadd;
5431 symbols_case_sensitive = s->symbols_case_sensitive;
5432 flag_keep_locals = s->keep_locals;
5433 flag_short_refs = s->short_refs;
5434 current_architecture = s->architecture;
5435 m68k_quick = s->quick;
5436 m68k_rel32 = s->rel32;
5437 listing = s->listing;
5438 flag_no_warnings = s->no_warnings;
5439
5440 free (s);
5441
5442 demand_empty_rest_of_line ();
5443 }
5444
5445 /* Types of MRI structured control directives. */
5446
5447 enum mri_control_type
5448 {
5449 mri_for,
5450 mri_if,
5451 mri_repeat,
5452 mri_while
5453 };
5454
5455 /* This structure is used to stack the MRI structured control
5456 directives. */
5457
5458 struct mri_control_info
5459 {
5460 /* The directive within which this one is enclosed. */
5461 struct mri_control_info *outer;
5462
5463 /* The type of directive. */
5464 enum mri_control_type type;
5465
5466 /* Whether an ELSE has been in an IF. */
5467 int else_seen;
5468
5469 /* The add or sub statement at the end of a FOR. */
5470 char *incr;
5471
5472 /* The label of the top of a FOR or REPEAT loop. */
5473 char *top;
5474
5475 /* The label to jump to for the next iteration, or the else
5476 expression of a conditional. */
5477 char *next;
5478
5479 /* The label to jump to to break out of the loop, or the label past
5480 the end of a conditional. */
5481 char *bottom;
5482 };
5483
5484 /* The stack of MRI structured control directives. */
5485
5486 static struct mri_control_info *mri_control_stack;
5487
5488 /* The current MRI structured control directive index number, used to
5489 generate label names. */
5490
5491 static int mri_control_index;
5492
5493 /* Some function prototypes. */
5494
5495 static void mri_assemble PARAMS ((char *));
5496 static char *mri_control_label PARAMS ((void));
5497 static struct mri_control_info *push_mri_control
5498 PARAMS ((enum mri_control_type));
5499 static void pop_mri_control PARAMS ((void));
5500 static int parse_mri_condition PARAMS ((int *));
5501 static int parse_mri_control_operand
5502 PARAMS ((int *, char **, char **, char **, char **));
5503 static int swap_mri_condition PARAMS ((int));
5504 static int reverse_mri_condition PARAMS ((int));
5505 static void build_mri_control_operand
5506 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5507 const char *, int));
5508 static void parse_mri_control_expression
5509 PARAMS ((char *, int, const char *, const char *, int));
5510
5511 /* Assemble an instruction for an MRI structured control directive. */
5512
5513 static void
5514 mri_assemble (str)
5515 char *str;
5516 {
5517 char *s;
5518
5519 /* md_assemble expects the opcode to be in lower case. */
5520 for (s = str; *s != ' ' && *s != '\0'; s++)
5521 {
5522 if (isupper ((unsigned char) *s))
5523 *s = tolower ((unsigned char) *s);
5524 }
5525
5526 md_assemble (str);
5527 }
5528
5529 /* Generate a new MRI label structured control directive label name. */
5530
5531 static char *
5532 mri_control_label ()
5533 {
5534 char *n;
5535
5536 n = (char *) xmalloc (20);
5537 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5538 ++mri_control_index;
5539 return n;
5540 }
5541
5542 /* Create a new MRI structured control directive. */
5543
5544 static struct mri_control_info *
5545 push_mri_control (type)
5546 enum mri_control_type type;
5547 {
5548 struct mri_control_info *n;
5549
5550 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5551
5552 n->type = type;
5553 n->else_seen = 0;
5554 if (type == mri_if || type == mri_while)
5555 n->top = NULL;
5556 else
5557 n->top = mri_control_label ();
5558 n->next = mri_control_label ();
5559 n->bottom = mri_control_label ();
5560
5561 n->outer = mri_control_stack;
5562 mri_control_stack = n;
5563
5564 return n;
5565 }
5566
5567 /* Pop off the stack of MRI structured control directives. */
5568
5569 static void
5570 pop_mri_control ()
5571 {
5572 struct mri_control_info *n;
5573
5574 n = mri_control_stack;
5575 mri_control_stack = n->outer;
5576 if (n->top != NULL)
5577 free (n->top);
5578 free (n->next);
5579 free (n->bottom);
5580 free (n);
5581 }
5582
5583 /* Recognize a condition code in an MRI structured control expression. */
5584
5585 static int
5586 parse_mri_condition (pcc)
5587 int *pcc;
5588 {
5589 char c1, c2;
5590
5591 know (*input_line_pointer == '<');
5592
5593 ++input_line_pointer;
5594 c1 = *input_line_pointer++;
5595 c2 = *input_line_pointer++;
5596
5597 if (*input_line_pointer != '>')
5598 {
5599 as_bad (_("syntax error in structured control directive"));
5600 return 0;
5601 }
5602
5603 ++input_line_pointer;
5604 SKIP_WHITESPACE ();
5605
5606 if (isupper (c1))
5607 c1 = tolower (c1);
5608 if (isupper (c2))
5609 c2 = tolower (c2);
5610
5611 *pcc = (c1 << 8) | c2;
5612
5613 return 1;
5614 }
5615
5616 /* Parse a single operand in an MRI structured control expression. */
5617
5618 static int
5619 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5620 int *pcc;
5621 char **leftstart;
5622 char **leftstop;
5623 char **rightstart;
5624 char **rightstop;
5625 {
5626 char *s;
5627
5628 SKIP_WHITESPACE ();
5629
5630 *pcc = -1;
5631 *leftstart = NULL;
5632 *leftstop = NULL;
5633 *rightstart = NULL;
5634 *rightstop = NULL;
5635
5636 if (*input_line_pointer == '<')
5637 {
5638 /* It's just a condition code. */
5639 return parse_mri_condition (pcc);
5640 }
5641
5642 /* Look ahead for the condition code. */
5643 for (s = input_line_pointer; *s != '\0'; ++s)
5644 {
5645 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5646 break;
5647 }
5648 if (*s == '\0')
5649 {
5650 as_bad (_("missing condition code in structured control directive"));
5651 return 0;
5652 }
5653
5654 *leftstart = input_line_pointer;
5655 *leftstop = s;
5656 if (*leftstop > *leftstart
5657 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5658 --*leftstop;
5659
5660 input_line_pointer = s;
5661 if (! parse_mri_condition (pcc))
5662 return 0;
5663
5664 /* Look ahead for AND or OR or end of line. */
5665 for (s = input_line_pointer; *s != '\0'; ++s)
5666 {
5667 if ((strncasecmp (s, "AND", 3) == 0
5668 && (s[3] == '.' || ! is_part_of_name (s[3])))
5669 || (strncasecmp (s, "OR", 2) == 0
5670 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5671 break;
5672 }
5673
5674 *rightstart = input_line_pointer;
5675 *rightstop = s;
5676 if (*rightstop > *rightstart
5677 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5678 --*rightstop;
5679
5680 input_line_pointer = s;
5681
5682 return 1;
5683 }
5684
5685 #define MCC(b1, b2) (((b1) << 8) | (b2))
5686
5687 /* Swap the sense of a condition. This changes the condition so that
5688 it generates the same result when the operands are swapped. */
5689
5690 static int
5691 swap_mri_condition (cc)
5692 int cc;
5693 {
5694 switch (cc)
5695 {
5696 case MCC ('h', 'i'): return MCC ('c', 's');
5697 case MCC ('l', 's'): return MCC ('c', 'c');
5698 case MCC ('c', 'c'): return MCC ('l', 's');
5699 case MCC ('c', 's'): return MCC ('h', 'i');
5700 case MCC ('p', 'l'): return MCC ('m', 'i');
5701 case MCC ('m', 'i'): return MCC ('p', 'l');
5702 case MCC ('g', 'e'): return MCC ('l', 'e');
5703 case MCC ('l', 't'): return MCC ('g', 't');
5704 case MCC ('g', 't'): return MCC ('l', 't');
5705 case MCC ('l', 'e'): return MCC ('g', 'e');
5706 }
5707 return cc;
5708 }
5709
5710 /* Reverse the sense of a condition. */
5711
5712 static int
5713 reverse_mri_condition (cc)
5714 int cc;
5715 {
5716 switch (cc)
5717 {
5718 case MCC ('h', 'i'): return MCC ('l', 's');
5719 case MCC ('l', 's'): return MCC ('h', 'i');
5720 case MCC ('c', 'c'): return MCC ('c', 's');
5721 case MCC ('c', 's'): return MCC ('c', 'c');
5722 case MCC ('n', 'e'): return MCC ('e', 'q');
5723 case MCC ('e', 'q'): return MCC ('n', 'e');
5724 case MCC ('v', 'c'): return MCC ('v', 's');
5725 case MCC ('v', 's'): return MCC ('v', 'c');
5726 case MCC ('p', 'l'): return MCC ('m', 'i');
5727 case MCC ('m', 'i'): return MCC ('p', 'l');
5728 case MCC ('g', 'e'): return MCC ('l', 't');
5729 case MCC ('l', 't'): return MCC ('g', 'e');
5730 case MCC ('g', 't'): return MCC ('l', 'e');
5731 case MCC ('l', 'e'): return MCC ('g', 't');
5732 }
5733 return cc;
5734 }
5735
5736 /* Build an MRI structured control expression. This generates test
5737 and branch instructions. It goes to TRUELAB if the condition is
5738 true, and to FALSELAB if the condition is false. Exactly one of
5739 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5740 is the size qualifier for the expression. EXTENT is the size to
5741 use for the branch. */
5742
5743 static void
5744 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5745 rightstop, truelab, falselab, extent)
5746 int qual;
5747 int cc;
5748 char *leftstart;
5749 char *leftstop;
5750 char *rightstart;
5751 char *rightstop;
5752 const char *truelab;
5753 const char *falselab;
5754 int extent;
5755 {
5756 char *buf;
5757 char *s;
5758
5759 if (leftstart != NULL)
5760 {
5761 struct m68k_op leftop, rightop;
5762 char c;
5763
5764 /* Swap the compare operands, if necessary, to produce a legal
5765 m68k compare instruction. Comparing a register operand with
5766 a non-register operand requires the register to be on the
5767 right (cmp, cmpa). Comparing an immediate value with
5768 anything requires the immediate value to be on the left
5769 (cmpi). */
5770
5771 c = *leftstop;
5772 *leftstop = '\0';
5773 (void) m68k_ip_op (leftstart, &leftop);
5774 *leftstop = c;
5775
5776 c = *rightstop;
5777 *rightstop = '\0';
5778 (void) m68k_ip_op (rightstart, &rightop);
5779 *rightstop = c;
5780
5781 if (rightop.mode == IMMED
5782 || ((leftop.mode == DREG || leftop.mode == AREG)
5783 && (rightop.mode != DREG && rightop.mode != AREG)))
5784 {
5785 char *temp;
5786
5787 cc = swap_mri_condition (cc);
5788 temp = leftstart;
5789 leftstart = rightstart;
5790 rightstart = temp;
5791 temp = leftstop;
5792 leftstop = rightstop;
5793 rightstop = temp;
5794 }
5795 }
5796
5797 if (truelab == NULL)
5798 {
5799 cc = reverse_mri_condition (cc);
5800 truelab = falselab;
5801 }
5802
5803 if (leftstart != NULL)
5804 {
5805 buf = (char *) xmalloc (20
5806 + (leftstop - leftstart)
5807 + (rightstop - rightstart));
5808 s = buf;
5809 *s++ = 'c';
5810 *s++ = 'm';
5811 *s++ = 'p';
5812 if (qual != '\0')
5813 *s++ = qual;
5814 *s++ = ' ';
5815 memcpy (s, leftstart, leftstop - leftstart);
5816 s += leftstop - leftstart;
5817 *s++ = ',';
5818 memcpy (s, rightstart, rightstop - rightstart);
5819 s += rightstop - rightstart;
5820 *s = '\0';
5821 mri_assemble (buf);
5822 free (buf);
5823 }
5824
5825 buf = (char *) xmalloc (20 + strlen (truelab));
5826 s = buf;
5827 *s++ = 'b';
5828 *s++ = cc >> 8;
5829 *s++ = cc & 0xff;
5830 if (extent != '\0')
5831 *s++ = extent;
5832 *s++ = ' ';
5833 strcpy (s, truelab);
5834 mri_assemble (buf);
5835 free (buf);
5836 }
5837
5838 /* Parse an MRI structured control expression. This generates test
5839 and branch instructions. STOP is where the expression ends. It
5840 goes to TRUELAB if the condition is true, and to FALSELAB if the
5841 condition is false. Exactly one of TRUELAB and FALSELAB will be
5842 NULL, meaning to fall through. QUAL is the size qualifier for the
5843 expression. EXTENT is the size to use for the branch. */
5844
5845 static void
5846 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5847 char *stop;
5848 int qual;
5849 const char *truelab;
5850 const char *falselab;
5851 int extent;
5852 {
5853 int c;
5854 int cc;
5855 char *leftstart;
5856 char *leftstop;
5857 char *rightstart;
5858 char *rightstop;
5859
5860 c = *stop;
5861 *stop = '\0';
5862
5863 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5864 &rightstart, &rightstop))
5865 {
5866 *stop = c;
5867 return;
5868 }
5869
5870 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5871 {
5872 const char *flab;
5873
5874 if (falselab != NULL)
5875 flab = falselab;
5876 else
5877 flab = mri_control_label ();
5878
5879 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5880 rightstop, (const char *) NULL, flab, extent);
5881
5882 input_line_pointer += 3;
5883 if (*input_line_pointer != '.'
5884 || input_line_pointer[1] == '\0')
5885 qual = '\0';
5886 else
5887 {
5888 qual = input_line_pointer[1];
5889 input_line_pointer += 2;
5890 }
5891
5892 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5893 &rightstart, &rightstop))
5894 {
5895 *stop = c;
5896 return;
5897 }
5898
5899 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5900 rightstop, truelab, falselab, extent);
5901
5902 if (falselab == NULL)
5903 colon (flab);
5904 }
5905 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5906 {
5907 const char *tlab;
5908
5909 if (truelab != NULL)
5910 tlab = truelab;
5911 else
5912 tlab = mri_control_label ();
5913
5914 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5915 rightstop, tlab, (const char *) NULL, extent);
5916
5917 input_line_pointer += 2;
5918 if (*input_line_pointer != '.'
5919 || input_line_pointer[1] == '\0')
5920 qual = '\0';
5921 else
5922 {
5923 qual = input_line_pointer[1];
5924 input_line_pointer += 2;
5925 }
5926
5927 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5928 &rightstart, &rightstop))
5929 {
5930 *stop = c;
5931 return;
5932 }
5933
5934 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5935 rightstop, truelab, falselab, extent);
5936
5937 if (truelab == NULL)
5938 colon (tlab);
5939 }
5940 else
5941 {
5942 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5943 rightstop, truelab, falselab, extent);
5944 }
5945
5946 *stop = c;
5947 if (input_line_pointer != stop)
5948 as_bad (_("syntax error in structured control directive"));
5949 }
5950
5951 /* Handle the MRI IF pseudo-op. This may be a structured control
5952 directive, or it may be a regular assembler conditional, depending
5953 on its operands. */
5954
5955 static void
5956 s_mri_if (qual)
5957 int qual;
5958 {
5959 char *s;
5960 int c;
5961 struct mri_control_info *n;
5962
5963 /* A structured control directive must end with THEN with an
5964 optional qualifier. */
5965 s = input_line_pointer;
5966 while (! is_end_of_line[(unsigned char) *s]
5967 && (! flag_mri || *s != '*'))
5968 ++s;
5969 --s;
5970 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5971 --s;
5972
5973 if (s - input_line_pointer > 1
5974 && s[-1] == '.')
5975 s -= 2;
5976
5977 if (s - input_line_pointer < 3
5978 || strncasecmp (s - 3, "THEN", 4) != 0)
5979 {
5980 if (qual != '\0')
5981 {
5982 as_bad (_("missing then"));
5983 ignore_rest_of_line ();
5984 return;
5985 }
5986
5987 /* It's a conditional. */
5988 s_if (O_ne);
5989 return;
5990 }
5991
5992 /* Since this might be a conditional if, this pseudo-op will be
5993 called even if we are supported to be ignoring input. Double
5994 check now. Clobber *input_line_pointer so that ignore_input
5995 thinks that this is not a special pseudo-op. */
5996 c = *input_line_pointer;
5997 *input_line_pointer = 0;
5998 if (ignore_input ())
5999 {
6000 *input_line_pointer = c;
6001 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6002 ++input_line_pointer;
6003 demand_empty_rest_of_line ();
6004 return;
6005 }
6006 *input_line_pointer = c;
6007
6008 n = push_mri_control (mri_if);
6009
6010 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6011 n->next, s[1] == '.' ? s[2] : '\0');
6012
6013 if (s[1] == '.')
6014 input_line_pointer = s + 3;
6015 else
6016 input_line_pointer = s + 1;
6017
6018 if (flag_mri)
6019 {
6020 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6021 ++input_line_pointer;
6022 }
6023
6024 demand_empty_rest_of_line ();
6025 }
6026
6027 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6028 structured IF, associate the ELSE with the IF. Otherwise, assume
6029 it is a conditional else. */
6030
6031 static void
6032 s_mri_else (qual)
6033 int qual;
6034 {
6035 int c;
6036 char *buf;
6037 char q[2];
6038
6039 if (qual == '\0'
6040 && (mri_control_stack == NULL
6041 || mri_control_stack->type != mri_if
6042 || mri_control_stack->else_seen))
6043 {
6044 s_else (0);
6045 return;
6046 }
6047
6048 c = *input_line_pointer;
6049 *input_line_pointer = 0;
6050 if (ignore_input ())
6051 {
6052 *input_line_pointer = c;
6053 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6054 ++input_line_pointer;
6055 demand_empty_rest_of_line ();
6056 return;
6057 }
6058 *input_line_pointer = c;
6059
6060 if (mri_control_stack == NULL
6061 || mri_control_stack->type != mri_if
6062 || mri_control_stack->else_seen)
6063 {
6064 as_bad (_("else without matching if"));
6065 ignore_rest_of_line ();
6066 return;
6067 }
6068
6069 mri_control_stack->else_seen = 1;
6070
6071 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6072 q[0] = qual;
6073 q[1] = '\0';
6074 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6075 mri_assemble (buf);
6076 free (buf);
6077
6078 colon (mri_control_stack->next);
6079
6080 if (flag_mri)
6081 {
6082 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6083 ++input_line_pointer;
6084 }
6085
6086 demand_empty_rest_of_line ();
6087 }
6088
6089 /* Handle the MRI ENDI pseudo-op. */
6090
6091 static void
6092 s_mri_endi (ignore)
6093 int ignore;
6094 {
6095 if (mri_control_stack == NULL
6096 || mri_control_stack->type != mri_if)
6097 {
6098 as_bad (_("endi without matching if"));
6099 ignore_rest_of_line ();
6100 return;
6101 }
6102
6103 /* ignore_input will not return true for ENDI, so we don't need to
6104 worry about checking it again here. */
6105
6106 if (! mri_control_stack->else_seen)
6107 colon (mri_control_stack->next);
6108 colon (mri_control_stack->bottom);
6109
6110 pop_mri_control ();
6111
6112 if (flag_mri)
6113 {
6114 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6115 ++input_line_pointer;
6116 }
6117
6118 demand_empty_rest_of_line ();
6119 }
6120
6121 /* Handle the MRI BREAK pseudo-op. */
6122
6123 static void
6124 s_mri_break (extent)
6125 int extent;
6126 {
6127 struct mri_control_info *n;
6128 char *buf;
6129 char ex[2];
6130
6131 n = mri_control_stack;
6132 while (n != NULL
6133 && n->type != mri_for
6134 && n->type != mri_repeat
6135 && n->type != mri_while)
6136 n = n->outer;
6137 if (n == NULL)
6138 {
6139 as_bad (_("break outside of structured loop"));
6140 ignore_rest_of_line ();
6141 return;
6142 }
6143
6144 buf = (char *) xmalloc (20 + strlen (n->bottom));
6145 ex[0] = extent;
6146 ex[1] = '\0';
6147 sprintf (buf, "bra%s %s", ex, n->bottom);
6148 mri_assemble (buf);
6149 free (buf);
6150
6151 if (flag_mri)
6152 {
6153 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6154 ++input_line_pointer;
6155 }
6156
6157 demand_empty_rest_of_line ();
6158 }
6159
6160 /* Handle the MRI NEXT pseudo-op. */
6161
6162 static void
6163 s_mri_next (extent)
6164 int extent;
6165 {
6166 struct mri_control_info *n;
6167 char *buf;
6168 char ex[2];
6169
6170 n = mri_control_stack;
6171 while (n != NULL
6172 && n->type != mri_for
6173 && n->type != mri_repeat
6174 && n->type != mri_while)
6175 n = n->outer;
6176 if (n == NULL)
6177 {
6178 as_bad (_("next outside of structured loop"));
6179 ignore_rest_of_line ();
6180 return;
6181 }
6182
6183 buf = (char *) xmalloc (20 + strlen (n->next));
6184 ex[0] = extent;
6185 ex[1] = '\0';
6186 sprintf (buf, "bra%s %s", ex, n->next);
6187 mri_assemble (buf);
6188 free (buf);
6189
6190 if (flag_mri)
6191 {
6192 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6193 ++input_line_pointer;
6194 }
6195
6196 demand_empty_rest_of_line ();
6197 }
6198
6199 /* Handle the MRI FOR pseudo-op. */
6200
6201 static void
6202 s_mri_for (qual)
6203 int qual;
6204 {
6205 const char *varstart, *varstop;
6206 const char *initstart, *initstop;
6207 const char *endstart, *endstop;
6208 const char *bystart, *bystop;
6209 int up;
6210 int by;
6211 int extent;
6212 struct mri_control_info *n;
6213 char *buf;
6214 char *s;
6215 char ex[2];
6216
6217 /* The syntax is
6218 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6219 */
6220
6221 SKIP_WHITESPACE ();
6222 varstart = input_line_pointer;
6223
6224 /* Look for the '='. */
6225 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6226 && *input_line_pointer != '=')
6227 ++input_line_pointer;
6228 if (*input_line_pointer != '=')
6229 {
6230 as_bad (_("missing ="));
6231 ignore_rest_of_line ();
6232 return;
6233 }
6234
6235 varstop = input_line_pointer;
6236 if (varstop > varstart
6237 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6238 --varstop;
6239
6240 ++input_line_pointer;
6241
6242 initstart = input_line_pointer;
6243
6244 /* Look for TO or DOWNTO. */
6245 up = 1;
6246 initstop = NULL;
6247 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6248 {
6249 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6250 && ! is_part_of_name (input_line_pointer[2]))
6251 {
6252 initstop = input_line_pointer;
6253 input_line_pointer += 2;
6254 break;
6255 }
6256 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6257 && ! is_part_of_name (input_line_pointer[6]))
6258 {
6259 initstop = input_line_pointer;
6260 up = 0;
6261 input_line_pointer += 6;
6262 break;
6263 }
6264 ++input_line_pointer;
6265 }
6266 if (initstop == NULL)
6267 {
6268 as_bad (_("missing to or downto"));
6269 ignore_rest_of_line ();
6270 return;
6271 }
6272 if (initstop > initstart
6273 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6274 --initstop;
6275
6276 SKIP_WHITESPACE ();
6277 endstart = input_line_pointer;
6278
6279 /* Look for BY or DO. */
6280 by = 0;
6281 endstop = NULL;
6282 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6283 {
6284 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6285 && ! is_part_of_name (input_line_pointer[2]))
6286 {
6287 endstop = input_line_pointer;
6288 by = 1;
6289 input_line_pointer += 2;
6290 break;
6291 }
6292 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6293 && (input_line_pointer[2] == '.'
6294 || ! is_part_of_name (input_line_pointer[2])))
6295 {
6296 endstop = input_line_pointer;
6297 input_line_pointer += 2;
6298 break;
6299 }
6300 ++input_line_pointer;
6301 }
6302 if (endstop == NULL)
6303 {
6304 as_bad (_("missing do"));
6305 ignore_rest_of_line ();
6306 return;
6307 }
6308 if (endstop > endstart
6309 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6310 --endstop;
6311
6312 if (! by)
6313 {
6314 bystart = "#1";
6315 bystop = bystart + 2;
6316 }
6317 else
6318 {
6319 SKIP_WHITESPACE ();
6320 bystart = input_line_pointer;
6321
6322 /* Look for DO. */
6323 bystop = NULL;
6324 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6325 {
6326 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6327 && (input_line_pointer[2] == '.'
6328 || ! is_part_of_name (input_line_pointer[2])))
6329 {
6330 bystop = input_line_pointer;
6331 input_line_pointer += 2;
6332 break;
6333 }
6334 ++input_line_pointer;
6335 }
6336 if (bystop == NULL)
6337 {
6338 as_bad (_("missing do"));
6339 ignore_rest_of_line ();
6340 return;
6341 }
6342 if (bystop > bystart
6343 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6344 --bystop;
6345 }
6346
6347 if (*input_line_pointer != '.')
6348 extent = '\0';
6349 else
6350 {
6351 extent = input_line_pointer[1];
6352 input_line_pointer += 2;
6353 }
6354
6355 /* We have fully parsed the FOR operands. Now build the loop. */
6356
6357 n = push_mri_control (mri_for);
6358
6359 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6360
6361 /* move init,var */
6362 s = buf;
6363 *s++ = 'm';
6364 *s++ = 'o';
6365 *s++ = 'v';
6366 *s++ = 'e';
6367 if (qual != '\0')
6368 *s++ = qual;
6369 *s++ = ' ';
6370 memcpy (s, initstart, initstop - initstart);
6371 s += initstop - initstart;
6372 *s++ = ',';
6373 memcpy (s, varstart, varstop - varstart);
6374 s += varstop - varstart;
6375 *s = '\0';
6376 mri_assemble (buf);
6377
6378 colon (n->top);
6379
6380 /* cmp end,var */
6381 s = buf;
6382 *s++ = 'c';
6383 *s++ = 'm';
6384 *s++ = 'p';
6385 if (qual != '\0')
6386 *s++ = qual;
6387 *s++ = ' ';
6388 memcpy (s, endstart, endstop - endstart);
6389 s += endstop - endstart;
6390 *s++ = ',';
6391 memcpy (s, varstart, varstop - varstart);
6392 s += varstop - varstart;
6393 *s = '\0';
6394 mri_assemble (buf);
6395
6396 /* bcc bottom */
6397 ex[0] = extent;
6398 ex[1] = '\0';
6399 if (up)
6400 sprintf (buf, "blt%s %s", ex, n->bottom);
6401 else
6402 sprintf (buf, "bgt%s %s", ex, n->bottom);
6403 mri_assemble (buf);
6404
6405 /* Put together the add or sub instruction used by ENDF. */
6406 s = buf;
6407 if (up)
6408 strcpy (s, "add");
6409 else
6410 strcpy (s, "sub");
6411 s += 3;
6412 if (qual != '\0')
6413 *s++ = qual;
6414 *s++ = ' ';
6415 memcpy (s, bystart, bystop - bystart);
6416 s += bystop - bystart;
6417 *s++ = ',';
6418 memcpy (s, varstart, varstop - varstart);
6419 s += varstop - varstart;
6420 *s = '\0';
6421 n->incr = buf;
6422
6423 if (flag_mri)
6424 {
6425 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6426 ++input_line_pointer;
6427 }
6428
6429 demand_empty_rest_of_line ();
6430 }
6431
6432 /* Handle the MRI ENDF pseudo-op. */
6433
6434 static void
6435 s_mri_endf (ignore)
6436 int ignore;
6437 {
6438 if (mri_control_stack == NULL
6439 || mri_control_stack->type != mri_for)
6440 {
6441 as_bad (_("endf without for"));
6442 ignore_rest_of_line ();
6443 return;
6444 }
6445
6446 colon (mri_control_stack->next);
6447
6448 mri_assemble (mri_control_stack->incr);
6449
6450 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6451 mri_assemble (mri_control_stack->incr);
6452
6453 free (mri_control_stack->incr);
6454
6455 colon (mri_control_stack->bottom);
6456
6457 pop_mri_control ();
6458
6459 if (flag_mri)
6460 {
6461 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6462 ++input_line_pointer;
6463 }
6464
6465 demand_empty_rest_of_line ();
6466 }
6467
6468 /* Handle the MRI REPEAT pseudo-op. */
6469
6470 static void
6471 s_mri_repeat (ignore)
6472 int ignore;
6473 {
6474 struct mri_control_info *n;
6475
6476 n = push_mri_control (mri_repeat);
6477 colon (n->top);
6478 if (flag_mri)
6479 {
6480 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6481 ++input_line_pointer;
6482 }
6483 demand_empty_rest_of_line ();
6484 }
6485
6486 /* Handle the MRI UNTIL pseudo-op. */
6487
6488 static void
6489 s_mri_until (qual)
6490 int qual;
6491 {
6492 char *s;
6493
6494 if (mri_control_stack == NULL
6495 || mri_control_stack->type != mri_repeat)
6496 {
6497 as_bad (_("until without repeat"));
6498 ignore_rest_of_line ();
6499 return;
6500 }
6501
6502 colon (mri_control_stack->next);
6503
6504 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6505 ;
6506
6507 parse_mri_control_expression (s, qual, (const char *) NULL,
6508 mri_control_stack->top, '\0');
6509
6510 colon (mri_control_stack->bottom);
6511
6512 input_line_pointer = s;
6513
6514 pop_mri_control ();
6515
6516 if (flag_mri)
6517 {
6518 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6519 ++input_line_pointer;
6520 }
6521
6522 demand_empty_rest_of_line ();
6523 }
6524
6525 /* Handle the MRI WHILE pseudo-op. */
6526
6527 static void
6528 s_mri_while (qual)
6529 int qual;
6530 {
6531 char *s;
6532
6533 struct mri_control_info *n;
6534
6535 s = input_line_pointer;
6536 while (! is_end_of_line[(unsigned char) *s]
6537 && (! flag_mri || *s != '*'))
6538 s++;
6539 --s;
6540 while (*s == ' ' || *s == '\t')
6541 --s;
6542 if (s - input_line_pointer > 1
6543 && s[-1] == '.')
6544 s -= 2;
6545 if (s - input_line_pointer < 2
6546 || strncasecmp (s - 1, "DO", 2) != 0)
6547 {
6548 as_bad (_("missing do"));
6549 ignore_rest_of_line ();
6550 return;
6551 }
6552
6553 n = push_mri_control (mri_while);
6554
6555 colon (n->next);
6556
6557 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6558 s[1] == '.' ? s[2] : '\0');
6559
6560 input_line_pointer = s + 1;
6561 if (*input_line_pointer == '.')
6562 input_line_pointer += 2;
6563
6564 if (flag_mri)
6565 {
6566 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6567 ++input_line_pointer;
6568 }
6569
6570 demand_empty_rest_of_line ();
6571 }
6572
6573 /* Handle the MRI ENDW pseudo-op. */
6574
6575 static void
6576 s_mri_endw (ignore)
6577 int ignore;
6578 {
6579 char *buf;
6580
6581 if (mri_control_stack == NULL
6582 || mri_control_stack->type != mri_while)
6583 {
6584 as_bad (_("endw without while"));
6585 ignore_rest_of_line ();
6586 return;
6587 }
6588
6589 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6590 sprintf (buf, "bra %s", mri_control_stack->next);
6591 mri_assemble (buf);
6592 free (buf);
6593
6594 colon (mri_control_stack->bottom);
6595
6596 pop_mri_control ();
6597
6598 if (flag_mri)
6599 {
6600 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6601 ++input_line_pointer;
6602 }
6603
6604 demand_empty_rest_of_line ();
6605 }
6606 \f
6607 /*
6608 * md_parse_option
6609 * Invocation line includes a switch not recognized by the base assembler.
6610 * See if it's a processor-specific option. These are:
6611 *
6612 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6613 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6614 * Select the architecture. Instructions or features not
6615 * supported by the selected architecture cause fatal
6616 * errors. More than one may be specified. The default is
6617 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6618 * for -m68000, and -m68882 is a synonym for -m68881.
6619 * -[A]m[c]no-68851, -[A]m[c]no-68881
6620 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6621 * so don't use or document it, but that's the way the parsing
6622 * works).
6623 *
6624 * -pic Indicates PIC.
6625 * -k Indicates PIC. (Sun 3 only.)
6626 *
6627 * --bitwise-or
6628 * Permit `|' to be used in expressions.
6629 *
6630 */
6631
6632 #ifdef OBJ_ELF
6633 CONST char *md_shortopts = "lSA:m:kQ:V";
6634 #else
6635 CONST char *md_shortopts = "lSA:m:k";
6636 #endif
6637
6638 struct option md_longopts[] = {
6639 #define OPTION_PIC (OPTION_MD_BASE)
6640 {"pic", no_argument, NULL, OPTION_PIC},
6641 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6642 {"register-prefix-optional", no_argument, NULL,
6643 OPTION_REGISTER_PREFIX_OPTIONAL},
6644 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6645 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6646 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6647 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6648 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6649 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6650 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6651 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6652 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6653 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6654 {NULL, no_argument, NULL, 0}
6655 };
6656 size_t md_longopts_size = sizeof(md_longopts);
6657
6658 int
6659 md_parse_option (c, arg)
6660 int c;
6661 char *arg;
6662 {
6663 switch (c)
6664 {
6665 case 'l': /* -l means keep external to 2 bit offset
6666 rather than 16 bit one */
6667 flag_short_refs = 1;
6668 break;
6669
6670 case 'S': /* -S means that jbsr's always turn into
6671 jsr's. */
6672 flag_long_jumps = 1;
6673 break;
6674
6675 case 'A':
6676 if (*arg == 'm')
6677 arg++;
6678 /* intentional fall-through */
6679 case 'm':
6680
6681 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6682 {
6683 int i;
6684 unsigned long arch;
6685 const char *oarg = arg;
6686
6687 arg += 3;
6688 if (*arg == 'm')
6689 {
6690 arg++;
6691 if (arg[0] == 'c' && arg[1] == '6')
6692 arg++;
6693 }
6694 for (i = 0; i < n_archs; i++)
6695 if (!strcmp (arg, archs[i].name))
6696 break;
6697 if (i == n_archs)
6698 {
6699 unknown:
6700 as_bad (_("unrecognized option `%s'"), oarg);
6701 return 0;
6702 }
6703 arch = archs[i].arch;
6704 if (arch == m68881)
6705 no_68881 = 1;
6706 else if (arch == m68851)
6707 no_68851 = 1;
6708 else
6709 goto unknown;
6710 }
6711 else
6712 {
6713 int i;
6714
6715 if (arg[0] == 'c' && arg[1] == '6')
6716 arg++;
6717
6718 for (i = 0; i < n_archs; i++)
6719 if (!strcmp (arg, archs[i].name))
6720 {
6721 unsigned long arch = archs[i].arch;
6722 if (cpu_of_arch (arch))
6723 /* It's a cpu spec. */
6724 {
6725 current_architecture &= ~m68000up;
6726 current_architecture |= arch;
6727 }
6728 else if (arch == m68881)
6729 {
6730 current_architecture |= m68881;
6731 no_68881 = 0;
6732 }
6733 else if (arch == m68851)
6734 {
6735 current_architecture |= m68851;
6736 no_68851 = 0;
6737 }
6738 else
6739 /* ??? */
6740 abort ();
6741 break;
6742 }
6743 if (i == n_archs)
6744 {
6745 as_bad (_("unrecognized architecture specification `%s'"), arg);
6746 return 0;
6747 }
6748 }
6749 break;
6750
6751 case OPTION_PIC:
6752 case 'k':
6753 flag_want_pic = 1;
6754 break; /* -pic, Position Independent Code */
6755
6756 case OPTION_REGISTER_PREFIX_OPTIONAL:
6757 flag_reg_prefix_optional = 1;
6758 reg_prefix_optional_seen = 1;
6759 break;
6760
6761 /* -V: SVR4 argument to print version ID. */
6762 case 'V':
6763 print_version_id ();
6764 break;
6765
6766 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6767 should be emitted or not. FIXME: Not implemented. */
6768 case 'Q':
6769 break;
6770
6771 case OPTION_BITWISE_OR:
6772 {
6773 char *n, *t;
6774 const char *s;
6775
6776 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6777 t = n;
6778 for (s = m68k_comment_chars; *s != '\0'; s++)
6779 if (*s != '|')
6780 *t++ = *s;
6781 *t = '\0';
6782 m68k_comment_chars = n;
6783 }
6784 break;
6785
6786 case OPTION_BASE_SIZE_DEFAULT_16:
6787 m68k_index_width_default = SIZE_WORD;
6788 break;
6789
6790 case OPTION_BASE_SIZE_DEFAULT_32:
6791 m68k_index_width_default = SIZE_LONG;
6792 break;
6793
6794 case OPTION_DISP_SIZE_DEFAULT_16:
6795 m68k_rel32 = 0;
6796 m68k_rel32_from_cmdline = 1;
6797 break;
6798
6799 case OPTION_DISP_SIZE_DEFAULT_32:
6800 m68k_rel32 = 1;
6801 m68k_rel32_from_cmdline = 1;
6802 break;
6803
6804 default:
6805 return 0;
6806 }
6807
6808 return 1;
6809 }
6810
6811 void
6812 md_show_usage (stream)
6813 FILE *stream;
6814 {
6815 fprintf(stream, _("\
6816 680X0 options:\n\
6817 -l use 1 word for refs to undefined symbols [default 2]\n\
6818 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6819 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6820 | -mcpu32 | -m5200\n\
6821 specify variant of 680X0 architecture [default 68020]\n\
6822 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6823 target has/lacks floating-point coprocessor\n\
6824 [default yes for 68020, 68030, and cpu32]\n"));
6825 fprintf(stream, _("\
6826 -m68851 | -mno-68851\n\
6827 target has/lacks memory-management unit coprocessor\n\
6828 [default yes for 68020 and up]\n\
6829 -pic, -k generate position independent code\n\
6830 -S turn jbsr into jsr\n\
6831 --register-prefix-optional\n\
6832 recognize register names without prefix character\n\
6833 --bitwise-or do not treat `|' as a comment character\n"));
6834 fprintf (stream, _("\
6835 --base-size-default-16 base reg without size is 16 bits\n\
6836 --base-size-default-32 base reg without size is 32 bits (default)\n\
6837 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6838 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6839 }
6840 \f
6841 #ifdef TEST2
6842
6843 /* TEST2: Test md_assemble() */
6844 /* Warning, this routine probably doesn't work anymore */
6845
6846 main ()
6847 {
6848 struct m68k_it the_ins;
6849 char buf[120];
6850 char *cp;
6851 int n;
6852
6853 m68k_ip_begin ();
6854 for (;;)
6855 {
6856 if (!gets (buf) || !*buf)
6857 break;
6858 if (buf[0] == '|' || buf[1] == '.')
6859 continue;
6860 for (cp = buf; *cp; cp++)
6861 if (*cp == '\t')
6862 *cp = ' ';
6863 if (is_label (buf))
6864 continue;
6865 memset (&the_ins, '\0', sizeof (the_ins));
6866 m68k_ip (&the_ins, buf);
6867 if (the_ins.error)
6868 {
6869 printf (_("Error %s in %s\n"), the_ins.error, buf);
6870 }
6871 else
6872 {
6873 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
6874 for (n = 0; n < the_ins.numo; n++)
6875 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6876 printf (" ");
6877 print_the_insn (&the_ins.opcode[0], stdout);
6878 (void) putchar ('\n');
6879 }
6880 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6881 {
6882 if (the_ins.operands[n].error)
6883 {
6884 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6885 continue;
6886 }
6887 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6888 if (the_ins.operands[n].b_const)
6889 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6890 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6891 if (the_ins.operands[n].b_iadd)
6892 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6893 (void) putchar ('\n');
6894 }
6895 }
6896 m68k_ip_end ();
6897 return 0;
6898 }
6899
6900 is_label (str)
6901 char *str;
6902 {
6903 while (*str == ' ')
6904 str++;
6905 while (*str && *str != ' ')
6906 str++;
6907 if (str[-1] == ':' || str[1] == '=')
6908 return 1;
6909 return 0;
6910 }
6911
6912 #endif
6913
6914 /* Possible states for relaxation:
6915
6916 0 0 branch offset byte (bra, etc)
6917 0 1 word
6918 0 2 long
6919
6920 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6921 1 1 word
6922 1 2 long
6923
6924 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6925 2 1 word-long
6926 2 2 long-word
6927 2 3 long-long
6928
6929 */
6930
6931 /* We have no need to default values of symbols. */
6932
6933 /* ARGSUSED */
6934 symbolS *
6935 md_undefined_symbol (name)
6936 char *name;
6937 {
6938 return 0;
6939 }
6940
6941 /* Round up a section size to the appropriate boundary. */
6942 valueT
6943 md_section_align (segment, size)
6944 segT segment;
6945 valueT size;
6946 {
6947 #ifdef OBJ_AOUT
6948 #ifdef BFD_ASSEMBLER
6949 /* For a.out, force the section size to be aligned. If we don't do
6950 this, BFD will align it for us, but it will not write out the
6951 final bytes of the section. This may be a bug in BFD, but it is
6952 easier to fix it here since that is how the other a.out targets
6953 work. */
6954 int align;
6955
6956 align = bfd_get_section_alignment (stdoutput, segment);
6957 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6958 #endif
6959 #endif
6960
6961 return size;
6962 }
6963
6964 /* Exactly what point is a PC-relative offset relative TO?
6965 On the 68k, it is relative to the address of the first extension
6966 word. The difference between the addresses of the offset and the
6967 first extension word is stored in fx_pcrel_adjust. */
6968 long
6969 md_pcrel_from (fixP)
6970 fixS *fixP;
6971 {
6972 int adjust;
6973
6974 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6975 -1 as 64. */
6976 adjust = fixP->fx_pcrel_adjust;
6977 if (adjust == 64)
6978 adjust = -1;
6979 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6980 }
6981
6982 #ifndef BFD_ASSEMBLER
6983 #ifdef OBJ_COFF
6984
6985 /*ARGSUSED*/
6986 void
6987 tc_coff_symbol_emit_hook (ignore)
6988 symbolS *ignore;
6989 {
6990 }
6991
6992 int
6993 tc_coff_sizemachdep (frag)
6994 fragS *frag;
6995 {
6996 switch (frag->fr_subtype & 0x3)
6997 {
6998 case BYTE:
6999 return 1;
7000 case SHORT:
7001 return 2;
7002 case LONG:
7003 return 4;
7004 default:
7005 abort ();
7006 return 0;
7007 }
7008 }
7009
7010 #endif
7011 #endif
7012 #ifdef OBJ_ELF
7013 void m68k_elf_final_processing()
7014 {
7015 /* Set file-specific flags if this is a cpu32 processor */
7016 if (cpu_of_arch (current_architecture) & cpu32)
7017 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7018 }
7019 #endif
7020 /* end of tc-m68k.c */
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