1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 1998
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
34 /* This string holds the chars that always start a comment. If the
35 pre-processor is disabled, these aren't very useful. The macro
36 tc_comment_chars points to this. We use this, rather than the
37 usual comment_chars, so that the --bitwise-or option will work. */
38 #if defined (TE_SVR4) || defined (TE_DELTA)
39 const char *m68k_comment_chars
= "|#";
41 const char *m68k_comment_chars
= "|";
44 /* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47 /* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
49 #NO_APP at the beginning of its output. */
50 /* Also note that comments like this one will always work. */
51 const char line_comment_chars
[] = "#*";
53 const char line_separator_chars
[] = "";
55 /* Chars that can be used to separate mant from exp in floating point nums */
56 CONST
char EXP_CHARS
[] = "eE";
58 /* Chars that mean this number is a floating point constant, as
59 in "0f12.456" or "0d1.2345e12". */
61 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
63 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
64 changed in read.c . Ideally it shouldn't have to know about it at all,
65 but nothing is ideal around here. */
67 const int md_reloc_size
= 8; /* Size of relocation record */
69 /* Are we trying to generate PIC code? If so, absolute references
70 ought to be made into linkage table references or pc-relative
71 references. Not implemented. For ELF there are other means
72 to denote pic relocations. */
75 static int flag_short_refs
; /* -l option */
76 static int flag_long_jumps
; /* -S option */
78 #ifdef REGISTER_PREFIX_OPTIONAL
79 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
81 int flag_reg_prefix_optional
;
84 /* Whether --register-prefix-optional was used on the command line. */
85 static int reg_prefix_optional_seen
;
87 /* The floating point coprocessor to use by default. */
88 static enum m68k_register m68k_float_copnum
= COP1
;
90 /* If this is non-zero, then references to number(%pc) will be taken
91 to refer to number, rather than to %pc + number. */
92 static int m68k_abspcadd
;
94 /* If this is non-zero, then the quick forms of the move, add, and sub
95 instructions are used when possible. */
96 static int m68k_quick
= 1;
98 /* If this is non-zero, then if the size is not specified for a base
99 or outer displacement, the assembler assumes that the size should
101 static int m68k_rel32
= 1;
103 /* This is non-zero if m68k_rel32 was set from the command line. */
104 static int m68k_rel32_from_cmdline
;
106 /* The default width to use for an index register when using a base
108 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
110 /* We want to warn if any text labels are misaligned. In order to get
111 the right line number, we need to record the line number for each
116 struct label_line
*next
;
123 /* The list of labels. */
125 static struct label_line
*labels
;
127 /* The current label. */
129 static struct label_line
*current_label
;
131 /* Its an arbitrary name: This means I don't approve of it */
132 /* See flames below */
133 static struct obstack robyn
;
135 #define TAB(x,y) (((x)<<2)+(y))
136 #define TABTYPE(xy) ((xy) >> 2)
142 /* Case `g' except when BCC68000 is applicable. */
144 /* Coprocessor branches. */
146 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
147 supported on all cpus. Widens to 32-bit absolute. */
149 /* For inserting an extra jmp instruction with long offset on 68000,
150 for expanding conditional branches. (Not bsr or bra.) Since the
151 68000 doesn't support 32-bit displacements for conditional
152 branches, we fake it by reversing the condition and branching
153 around a jmp with an absolute long operand. */
155 /* For the DBcc "instructions". If the displacement requires 32 bits,
156 the branch-around-a-jump game is played here too. */
158 /* Not currently used? */
160 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
166 const char *m_operands
;
167 unsigned long m_opcode
;
171 struct m68k_incant
*m_next
;
174 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
175 #define gettwo(x) (((x)->m_opcode)&0xffff)
177 static const enum m68k_register m68000_control_regs
[] = { 0 };
178 static const enum m68k_register m68010_control_regs
[] = {
182 static const enum m68k_register m68020_control_regs
[] = {
183 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
186 static const enum m68k_register m68040_control_regs
[] = {
187 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
188 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
191 static const enum m68k_register m68060_control_regs
[] = {
192 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
193 USP
, VBR
, URP
, SRP
, PCR
,
196 static const enum m68k_register mcf5200_control_regs
[] = {
197 CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, VBR
, ROMBAR
,
198 RAMBAR0
, RAMBAR1
, MBAR
,
201 #define cpu32_control_regs m68010_control_regs
203 static const enum m68k_register
*control_regs
;
205 /* internal form of a 68020 instruction */
209 const char *args
; /* list of opcode info */
212 int numo
; /* Number of shorts in opcode */
215 struct m68k_op operands
[6];
217 int nexp
; /* number of exprs in use */
218 struct m68k_exp exprs
[4];
220 int nfrag
; /* Number of frags we have to produce */
223 int fragoff
; /* Where in the current opcode the frag ends */
230 int nrel
; /* Num of reloc strucs in use */
237 /* In a pc relative address the difference between the address
238 of the offset and the address that the offset is relative
239 to. This depends on the addressing mode. Basically this
240 is the value to put in the offset field to address the
241 first byte of the offset, without regarding the special
242 significance of some values (in the branch instruction, for
246 /* Whether this expression needs special pic relocation, and if
248 enum pic_relocation pic_reloc
;
251 reloc
[5]; /* Five is enough??? */
254 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
255 #define float_of_arch(x) ((x) & mfloat)
256 #define mmu_of_arch(x) ((x) & mmmu)
258 /* Macros for determining if cpu supports a specific addressing mode */
259 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
261 static struct m68k_it the_ins
; /* the instruction being assembled */
263 #define op(ex) ((ex)->exp.X_op)
264 #define adds(ex) ((ex)->exp.X_add_symbol)
265 #define subs(ex) ((ex)->exp.X_op_symbol)
266 #define offs(ex) ((ex)->exp.X_add_number)
268 /* Macros for adding things to the m68k_it struct */
270 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
272 /* Static functions. */
274 static void insop
PARAMS ((int, const struct m68k_incant
*));
275 static void add_fix
PARAMS ((int, struct m68k_exp
*, int, int));
276 static void add_frag
PARAMS ((symbolS
*, offsetT
, int));
278 /* Like addword, but goes BEFORE general operands */
282 const struct m68k_incant
*opcode
;
285 for(z
=the_ins
.numo
;z
>opcode
->m_codenum
;--z
)
286 the_ins
.opcode
[z
]=the_ins
.opcode
[z
-1];
287 for(z
=0;z
<the_ins
.nrel
;z
++)
288 the_ins
.reloc
[z
].n
+=2;
289 for (z
= 0; z
< the_ins
.nfrag
; z
++)
290 the_ins
.fragb
[z
].fragoff
++;
291 the_ins
.opcode
[opcode
->m_codenum
]=w
;
295 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
298 add_fix (width
, exp
, pc_rel
, pc_fix
)
300 struct m68k_exp
*exp
;
304 the_ins
.reloc
[the_ins
.nrel
].n
= ((width
== 'B' || width
== '3')
308 : (the_ins
.numo
*2)));
309 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
310 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
311 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
313 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
315 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
318 /* Cause an extra frag to be generated here, inserting up to 10 bytes
319 (that value is chosen in the frag_var call in md_assemble). TYPE
320 is the subtype of the frag to be generated; its primary type is
321 rs_machine_dependent.
323 The TYPE parameter is also used by md_convert_frag_1 and
324 md_estimate_size_before_relax. The appropriate type of fixup will
325 be emitted by md_convert_frag_1.
327 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
329 add_frag (add
, off
, type
)
334 the_ins
.fragb
[the_ins
.nfrag
].fragoff
=the_ins
.numo
;
335 the_ins
.fragb
[the_ins
.nfrag
].fadd
=add
;
336 the_ins
.fragb
[the_ins
.nfrag
].foff
=off
;
337 the_ins
.fragb
[the_ins
.nfrag
++].fragty
=type
;
341 (op (ex) != O_constant && op (ex) != O_big)
343 static char *crack_operand
PARAMS ((char *str
, struct m68k_op
*opP
));
344 static int get_num
PARAMS ((struct m68k_exp
*exp
, int ok
));
345 static void m68k_ip
PARAMS ((char *));
346 static void insert_reg
PARAMS ((const char *, int));
347 static void select_control_regs
PARAMS ((void));
348 static void init_regtable
PARAMS ((void));
349 static int reverse_16_bits
PARAMS ((int in
));
350 static int reverse_8_bits
PARAMS ((int in
));
351 static void install_gen_operand
PARAMS ((int mode
, int val
));
352 static void install_operand
PARAMS ((int mode
, int val
));
353 static void s_bss
PARAMS ((int));
354 static void s_data1
PARAMS ((int));
355 static void s_data2
PARAMS ((int));
356 static void s_even
PARAMS ((int));
357 static void s_proc
PARAMS ((int));
358 static void mri_chip
PARAMS ((void));
359 static void s_chip
PARAMS ((int));
360 static void s_fopt
PARAMS ((int));
361 static void s_opt
PARAMS ((int));
362 static void s_reg
PARAMS ((int));
363 static void s_restore
PARAMS ((int));
364 static void s_save
PARAMS ((int));
365 static void s_mri_if
PARAMS ((int));
366 static void s_mri_else
PARAMS ((int));
367 static void s_mri_endi
PARAMS ((int));
368 static void s_mri_break
PARAMS ((int));
369 static void s_mri_next
PARAMS ((int));
370 static void s_mri_for
PARAMS ((int));
371 static void s_mri_endf
PARAMS ((int));
372 static void s_mri_repeat
PARAMS ((int));
373 static void s_mri_until
PARAMS ((int));
374 static void s_mri_while
PARAMS ((int));
375 static void s_mri_endw
PARAMS ((int));
376 static void md_apply_fix_2
PARAMS ((fixS
*, offsetT
));
377 static void md_convert_frag_1
PARAMS ((fragS
*));
379 static int current_architecture
;
387 static const struct m68k_cpu archs
[] = {
388 { m68000
, "68000", 0 },
389 { m68010
, "68010", 0 },
390 { m68020
, "68020", 0 },
391 { m68030
, "68030", 0 },
392 { m68040
, "68040", 0 },
393 { m68060
, "68060", 0 },
394 { cpu32
, "cpu32", 0 },
395 { m68881
, "68881", 0 },
396 { m68851
, "68851", 0 },
397 { mcf5200
, "5200", 0 },
398 /* Aliases (effectively, so far as gas is concerned) for the above
400 { m68020
, "68k", 1 },
401 { m68000
, "68008", 1 },
402 { m68000
, "68302", 1 },
403 { m68000
, "68306", 1 },
404 { m68000
, "68307", 1 },
405 { m68000
, "68322", 1 },
406 { m68000
, "68356", 1 },
407 { m68000
, "68ec000", 1 },
408 { m68000
, "68hc000", 1 },
409 { m68000
, "68hc001", 1 },
410 { m68020
, "68ec020", 1 },
411 { m68030
, "68ec030", 1 },
412 { m68040
, "68ec040", 1 },
413 { m68060
, "68ec060", 1 },
414 { cpu32
, "68330", 1 },
415 { cpu32
, "68331", 1 },
416 { cpu32
, "68332", 1 },
417 { cpu32
, "68333", 1 },
418 { cpu32
, "68334", 1 },
419 { cpu32
, "68336", 1 },
420 { cpu32
, "68340", 1 },
421 { cpu32
, "68341", 1 },
422 { cpu32
, "68349", 1 },
423 { cpu32
, "68360", 1 },
424 { m68881
, "68882", 1 },
427 static const int n_archs
= sizeof (archs
) / sizeof (archs
[0]);
429 /* BCC68000 is for patching in an extra jmp instruction for long offsets
430 on the 68000. The 68000 doesn't support long branches with branchs */
432 /* This table desribes how you change sizes for the various types of variable
433 size expressions. This version only supports two kinds. */
435 /* Note that calls to frag_var need to specify the maximum expansion
436 needed; this is currently 10 bytes for DBCC. */
439 How far Forward this mode will reach:
440 How far Backward this mode will reach:
441 How many bytes this mode will add to the size of the frag
442 Which mode to go to if the offset won't fit in this one
444 relax_typeS md_relax_table
[] =
446 {1, 1, 0, 0}, /* First entries aren't used */
447 {1, 1, 0, 0}, /* For no good reason except */
448 {1, 1, 0, 0}, /* that the VAX doesn't either */
451 {(127), (-128), 0, TAB (ABRANCH
, SHORT
)},
452 {(32767), (-32768), 2, TAB (ABRANCH
, LONG
)},
456 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
457 {(32767), (-32768), 2, TAB (FBRANCH
, LONG
)},
461 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
462 {(32767), (-32768), 2, TAB (PCREL
, LONG
)},
466 {(127), (-128), 0, TAB (BCC68000
, SHORT
)},
467 {(32767), (-32768), 2, TAB (BCC68000
, LONG
)},
468 {0, 0, 6, 0}, /* jmp long space */
471 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
472 {(32767), (-32768), 2, TAB (DBCC
, LONG
)},
473 {0, 0, 10, 0}, /* bra/jmp long space */
476 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
477 {32767, -32768, 2, TAB (PCLEA
, LONG
)},
481 /* For, e.g., jmp pcrel indexed. */
482 {125, -130, 0, TAB (PCINDEX
, SHORT
)},
483 {32765, -32770, 2, TAB (PCINDEX
, LONG
)},
488 /* These are the machine dependent pseudo-ops. These are included so
489 the assembler can work on the output from the SUN C compiler, which
493 /* This table describes all the machine specific pseudo-ops the assembler
494 has to support. The fields are:
495 pseudo-op name without dot
496 function to call to execute this pseudo-op
497 Integer arg to pass to the function
499 const pseudo_typeS md_pseudo_table
[] =
501 {"data1", s_data1
, 0},
502 {"data2", s_data2
, 0},
505 {"skip", s_space
, 0},
507 #if defined (TE_SUN3) || defined (OBJ_ELF)
508 {"align", s_align_bytes
, 0},
511 {"swbeg", s_ignore
, 0},
513 {"extend", float_cons
, 'x'},
514 {"ldouble", float_cons
, 'x'},
516 /* The following pseudo-ops are supported for MRI compatibility. */
518 {"comline", s_space
, 1},
520 {"mask2", s_ignore
, 0},
523 {"restore", s_restore
, 0},
527 {"if.b", s_mri_if
, 'b'},
528 {"if.w", s_mri_if
, 'w'},
529 {"if.l", s_mri_if
, 'l'},
530 {"else", s_mri_else
, 0},
531 {"else.s", s_mri_else
, 's'},
532 {"else.l", s_mri_else
, 'l'},
533 {"endi", s_mri_endi
, 0},
534 {"break", s_mri_break
, 0},
535 {"break.s", s_mri_break
, 's'},
536 {"break.l", s_mri_break
, 'l'},
537 {"next", s_mri_next
, 0},
538 {"next.s", s_mri_next
, 's'},
539 {"next.l", s_mri_next
, 'l'},
540 {"for", s_mri_for
, 0},
541 {"for.b", s_mri_for
, 'b'},
542 {"for.w", s_mri_for
, 'w'},
543 {"for.l", s_mri_for
, 'l'},
544 {"endf", s_mri_endf
, 0},
545 {"repeat", s_mri_repeat
, 0},
546 {"until", s_mri_until
, 0},
547 {"until.b", s_mri_until
, 'b'},
548 {"until.w", s_mri_until
, 'w'},
549 {"until.l", s_mri_until
, 'l'},
550 {"while", s_mri_while
, 0},
551 {"while.b", s_mri_while
, 'b'},
552 {"while.w", s_mri_while
, 'w'},
553 {"while.l", s_mri_while
, 'l'},
554 {"endw", s_mri_endw
, 0},
560 /* The mote pseudo ops are put into the opcode table, since they
561 don't start with a . they look like opcodes to gas.
565 extern void obj_coff_section
PARAMS ((int));
568 CONST pseudo_typeS mote_pseudo_table
[] =
581 {"xdef", s_globl
, 0},
583 {"align", s_align_bytes
, 0},
585 {"align", s_align_ptwo
, 0},
588 {"sect", obj_coff_section
, 0},
589 {"section", obj_coff_section
, 0},
594 #define issbyte(x) ((x)>=-128 && (x)<=127)
595 #define isubyte(x) ((x)>=0 && (x)<=255)
596 #define issword(x) ((x)>=-32768 && (x)<=32767)
597 #define isuword(x) ((x)>=0 && (x)<=65535)
599 #define isbyte(x) ((x)>= -255 && (x)<=255)
600 #define isword(x) ((x)>=-65536 && (x)<=65535)
601 #define islong(x) (1)
603 extern char *input_line_pointer
;
605 static char mklower_table
[256];
606 #define mklower(c) (mklower_table[(unsigned char)(c)])
607 static char notend_table
[256];
608 static char alt_notend_table
[256];
610 (! (notend_table[(unsigned char) *s] \
612 && alt_notend_table[(unsigned char) s[1]])))
614 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
616 #ifdef NO_PCREL_RELOCS
619 make_pcrel_absolute(fixP
, add_number
)
623 register unsigned char *opcode
= fixP
->fx_frag
->fr_opcode
;
625 /* rewrite the PC relative instructions to absolute address ones.
626 * these are rumoured to be faster, and the apollo linker refuses
627 * to deal with the PC relative relocations.
629 if (opcode
[0] == 0x60 && opcode
[1] == 0xff) /* BRA -> JMP */
634 else if (opcode
[0] == 0x61 && opcode
[1] == 0xff) /* BSR -> JSR */
640 as_fatal (_("Unknown PC relative instruction"));
645 #endif /* NO_PCREL_RELOCS */
648 tc_coff_fix2rtype (fixP
)
651 if (fixP
->fx_tcbit
&& fixP
->fx_size
== 4)
652 return R_RELLONG_NEG
;
653 #ifdef NO_PCREL_RELOCS
654 know (fixP
->fx_pcrel
== 0);
655 return (fixP
->fx_size
== 1 ? R_RELBYTE
656 : fixP
->fx_size
== 2 ? R_DIR16
659 return (fixP
->fx_pcrel
?
660 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
661 fixP
->fx_size
== 2 ? R_PCRWORD
:
663 (fixP
->fx_size
== 1 ? R_RELBYTE
:
664 fixP
->fx_size
== 2 ? R_RELWORD
:
673 /* Compute the relocation code for a fixup of SIZE bytes, using pc
674 relative relocation if PCREL is non-zero. PIC says whether a special
675 pic relocation was requested. */
677 static bfd_reloc_code_real_type get_reloc_code
678 PARAMS ((int, int, enum pic_relocation
));
680 static bfd_reloc_code_real_type
681 get_reloc_code (size
, pcrel
, pic
)
684 enum pic_relocation pic
;
692 return BFD_RELOC_8_GOT_PCREL
;
694 return BFD_RELOC_16_GOT_PCREL
;
696 return BFD_RELOC_32_GOT_PCREL
;
704 return BFD_RELOC_8_GOTOFF
;
706 return BFD_RELOC_16_GOTOFF
;
708 return BFD_RELOC_32_GOTOFF
;
716 return BFD_RELOC_8_PLT_PCREL
;
718 return BFD_RELOC_16_PLT_PCREL
;
720 return BFD_RELOC_32_PLT_PCREL
;
728 return BFD_RELOC_8_PLTOFF
;
730 return BFD_RELOC_16_PLTOFF
;
732 return BFD_RELOC_32_PLTOFF
;
742 return BFD_RELOC_8_PCREL
;
744 return BFD_RELOC_16_PCREL
;
746 return BFD_RELOC_32_PCREL
;
766 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
768 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
773 as_bad (_("Can not do %d byte relocation"), size
);
775 as_bad (_("Can not do %d byte pic relocation"), size
);
778 return BFD_RELOC_NONE
;
781 /* Here we decide which fixups can be adjusted to make them relative
782 to the beginning of the section instead of the symbol. Basically
783 we need to make sure that the dynamic relocations are done
784 correctly, so in some cases we force the original symbol to be
787 tc_m68k_fix_adjustable (fixP
)
790 /* Prevent all adjustments to global symbols. */
791 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
792 || S_IS_WEAK (fixP
->fx_addsy
))
795 /* adjust_reloc_syms doesn't know about the GOT */
796 switch (fixP
->fx_r_type
)
798 case BFD_RELOC_8_GOT_PCREL
:
799 case BFD_RELOC_16_GOT_PCREL
:
800 case BFD_RELOC_32_GOT_PCREL
:
801 case BFD_RELOC_8_GOTOFF
:
802 case BFD_RELOC_16_GOTOFF
:
803 case BFD_RELOC_32_GOTOFF
:
804 case BFD_RELOC_8_PLT_PCREL
:
805 case BFD_RELOC_16_PLT_PCREL
:
806 case BFD_RELOC_32_PLT_PCREL
:
807 case BFD_RELOC_8_PLTOFF
:
808 case BFD_RELOC_16_PLTOFF
:
809 case BFD_RELOC_32_PLTOFF
:
812 case BFD_RELOC_VTABLE_INHERIT
:
813 case BFD_RELOC_VTABLE_ENTRY
:
823 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
830 tc_gen_reloc (section
, fixp
)
835 bfd_reloc_code_real_type code
;
840 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
842 code
= fixp
->fx_r_type
;
844 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
845 that fixup_segment converted a non-PC relative reloc into a
846 PC relative reloc. In such a case, we need to convert the
853 code
= BFD_RELOC_8_PCREL
;
856 code
= BFD_RELOC_16_PCREL
;
859 code
= BFD_RELOC_32_PCREL
;
861 case BFD_RELOC_8_PCREL
:
862 case BFD_RELOC_16_PCREL
:
863 case BFD_RELOC_32_PCREL
:
864 case BFD_RELOC_8_GOT_PCREL
:
865 case BFD_RELOC_16_GOT_PCREL
:
866 case BFD_RELOC_32_GOT_PCREL
:
867 case BFD_RELOC_8_GOTOFF
:
868 case BFD_RELOC_16_GOTOFF
:
869 case BFD_RELOC_32_GOTOFF
:
870 case BFD_RELOC_8_PLT_PCREL
:
871 case BFD_RELOC_16_PLT_PCREL
:
872 case BFD_RELOC_32_PLT_PCREL
:
873 case BFD_RELOC_8_PLTOFF
:
874 case BFD_RELOC_16_PLTOFF
:
875 case BFD_RELOC_32_PLTOFF
:
878 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
879 _("Cannot make %s relocation PC relative"),
880 bfd_get_reloc_code_name (code
));
886 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
887 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
889 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
890 MAP (1, 0, BFD_RELOC_8
);
891 MAP (2, 0, BFD_RELOC_16
);
892 MAP (4, 0, BFD_RELOC_32
);
893 MAP (1, 1, BFD_RELOC_8_PCREL
);
894 MAP (2, 1, BFD_RELOC_16_PCREL
);
895 MAP (4, 1, BFD_RELOC_32_PCREL
);
903 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
904 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
905 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
908 reloc
->addend
= fixp
->fx_addnumber
;
913 reloc
->addend
= fixp
->fx_addnumber
;
915 reloc
->addend
= (section
->vma
916 + (fixp
->fx_pcrel_adjust
== 64
917 ? -1 : fixp
->fx_pcrel_adjust
)
919 + md_pcrel_from (fixp
));
922 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
923 assert (reloc
->howto
!= 0);
928 #endif /* BFD_ASSEMBLER */
930 /* Return zero if the reference to SYMBOL from within the same segment may
934 /* On an ELF system, we can't relax an externally visible symbol,
935 because it may be overridden by a shared library. However, if
936 TARGET_OS is "elf", then we presume that we are assembling for an
937 embedded system, in which case we don't have to worry about shared
938 libraries, and we can relax anything. */
940 #define relaxable_symbol(symbol) \
941 (strcmp (TARGET_OS, "elf") == 0 \
942 || (! S_IS_EXTERNAL (symbol) \
943 && ! S_IS_WEAK (symbol)))
947 #define relaxable_symbol(symbol) 1
951 /* Handle of the OPCODE hash table. NULL means any use before
952 m68k_ip_begin() will crash. */
953 static struct hash_control
*op_hash
;
955 /* Assemble an m68k instruction. */
962 register struct m68k_op
*opP
;
963 register const struct m68k_incant
*opcode
;
964 register const char *s
;
965 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
966 char *pdot
, *pdotmove
;
967 enum m68k_size siz1
, siz2
;
971 LITTLENUM_TYPE words
[6];
972 LITTLENUM_TYPE
*wordp
;
973 unsigned long ok_arch
= 0;
975 if (*instring
== ' ')
976 instring
++; /* skip leading whitespace */
978 /* Scan up to end of operation-code, which MUST end in end-of-string
979 or exactly 1 space. */
981 for (p
= instring
; *p
!= '\0'; p
++)
991 the_ins
.error
= _("No operator");
995 /* p now points to the end of the opcode name, probably whitespace.
996 Make sure the name is null terminated by clobbering the
997 whitespace, look it up in the hash table, then fix it back.
998 Remove a dot, first, since the opcode tables have none. */
1001 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1002 *pdotmove
= pdotmove
[1];
1008 opcode
= (const struct m68k_incant
*) hash_find (op_hash
, instring
);
1013 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1014 *pdotmove
= pdotmove
[-1];
1021 the_ins
.error
= _("Unknown operator");
1025 /* found a legitimate opcode, start matching operands */
1029 if (opcode
->m_operands
== 0)
1031 char *old
= input_line_pointer
;
1033 input_line_pointer
= p
;
1034 /* Ahh - it's a motorola style psuedo op */
1035 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1036 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1037 input_line_pointer
= old
;
1043 if (flag_mri
&& opcode
->m_opnum
== 0)
1045 /* In MRI mode, random garbage is allowed after an instruction
1046 which accepts no operands. */
1047 the_ins
.args
= opcode
->m_operands
;
1048 the_ins
.numargs
= opcode
->m_opnum
;
1049 the_ins
.numo
= opcode
->m_codenum
;
1050 the_ins
.opcode
[0] = getone (opcode
);
1051 the_ins
.opcode
[1] = gettwo (opcode
);
1055 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1057 p
= crack_operand (p
, opP
);
1061 the_ins
.error
= opP
->error
;
1066 opsfound
= opP
- &the_ins
.operands
[0];
1068 /* This ugly hack is to support the floating pt opcodes in their
1069 standard form. Essentially, we fake a first enty of type COP#1 */
1070 if (opcode
->m_operands
[0] == 'I')
1074 for (n
= opsfound
; n
> 0; --n
)
1075 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1077 memset ((char *) (&the_ins
.operands
[0]), '\0',
1078 sizeof (the_ins
.operands
[0]));
1079 the_ins
.operands
[0].mode
= CONTROL
;
1080 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1084 /* We've got the operands. Find an opcode that'll accept them */
1087 /* If we didn't get the right number of ops, or we have no
1088 common model with this pattern then reject this pattern. */
1090 ok_arch
|= opcode
->m_arch
;
1091 if (opsfound
!= opcode
->m_opnum
1092 || ((opcode
->m_arch
& current_architecture
) == 0))
1096 for (s
= opcode
->m_operands
, opP
= &the_ins
.operands
[0];
1100 /* Warning: this switch is huge! */
1101 /* I've tried to organize the cases into this order:
1102 non-alpha first, then alpha by letter. Lower-case
1103 goes directly before uppercase counterpart. */
1104 /* Code with multiple case ...: gets sorted by the lowest
1105 case ... it belongs to. I hope this makes sense. */
1211 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1228 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1247 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1257 if (opP
->mode
!= IMMED
)
1259 else if (s
[1] == 'b'
1260 && ! isvar (&opP
->disp
)
1261 && (opP
->disp
.exp
.X_op
!= O_constant
1262 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1264 else if (s
[1] == 'B'
1265 && ! isvar (&opP
->disp
)
1266 && (opP
->disp
.exp
.X_op
!= O_constant
1267 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1269 else if (s
[1] == 'w'
1270 && ! isvar (&opP
->disp
)
1271 && (opP
->disp
.exp
.X_op
!= O_constant
1272 || ! isword (opP
->disp
.exp
.X_add_number
)))
1274 else if (s
[1] == 'W'
1275 && ! isvar (&opP
->disp
)
1276 && (opP
->disp
.exp
.X_op
!= O_constant
1277 || ! issword (opP
->disp
.exp
.X_add_number
)))
1283 if (opP
->mode
!= IMMED
)
1288 if (opP
->mode
== AREG
1289 || opP
->mode
== CONTROL
1290 || opP
->mode
== FPREG
1291 || opP
->mode
== IMMED
1292 || opP
->mode
== REGLST
1293 || (opP
->mode
!= ABSL
1295 || opP
->reg
== ZPC
)))
1300 if (opP
->mode
== CONTROL
1301 || opP
->mode
== FPREG
1302 || opP
->mode
== REGLST
1303 || opP
->mode
== IMMED
1304 || (opP
->mode
!= ABSL
1306 || opP
->reg
== ZPC
)))
1334 if (opP
->mode
== CONTROL
1335 || opP
->mode
== FPREG
1336 || opP
->mode
== REGLST
)
1341 if (opP
->mode
!= AINC
)
1346 if (opP
->mode
!= ADEC
)
1396 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1417 case '~': /* For now! (JF FOO is this right?) */
1439 if (opP
->mode
!= CONTROL
1440 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1445 if (opP
->mode
!= AREG
)
1450 if (opP
->mode
!= AINDR
)
1455 if (opP
->mode
!= ABSL
1457 && strncmp (instring
, "jbsr", 4) == 0))
1462 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1467 if (opP
->mode
!= DISP
1469 || opP
->reg
> ADDR7
)
1474 if (opP
->mode
!= DREG
)
1479 if (opP
->mode
!= FPREG
)
1484 if (opP
->mode
!= CONTROL
1491 if (opP
->mode
!= CONTROL
1493 || opP
->reg
> last_movec_reg
)
1497 const enum m68k_register
*rp
;
1498 for (rp
= control_regs
; *rp
; rp
++)
1499 if (*rp
== opP
->reg
)
1507 if (opP
->mode
!= IMMED
)
1513 if (opP
->mode
== DREG
1514 || opP
->mode
== AREG
1515 || opP
->mode
== FPREG
)
1524 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1527 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1530 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1538 else if (opP
->mode
== CONTROL
)
1547 opP
->mask
= 1 << 24;
1550 opP
->mask
= 1 << 25;
1553 opP
->mask
= 1 << 26;
1562 else if (opP
->mode
!= REGLST
)
1564 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
1566 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
1571 if (opP
->mode
!= IMMED
)
1573 else if (opP
->disp
.exp
.X_op
!= O_constant
1574 || ! issbyte (opP
->disp
.exp
.X_add_number
))
1576 else if (! m68k_quick
1577 && instring
[3] != 'q'
1578 && instring
[4] != 'q')
1583 if (opP
->mode
!= DREG
1584 && opP
->mode
!= IMMED
1585 && opP
->mode
!= ABSL
)
1590 if (opP
->mode
!= IMMED
)
1592 else if (opP
->disp
.exp
.X_op
!= O_constant
1593 || opP
->disp
.exp
.X_add_number
< 1
1594 || opP
->disp
.exp
.X_add_number
> 8)
1596 else if (! m68k_quick
1597 && (strncmp (instring
, "add", 3) == 0
1598 || strncmp (instring
, "sub", 3) == 0)
1599 && instring
[3] != 'q')
1604 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1609 if (opP
->mode
!= AINDR
1610 && (opP
->mode
!= BASE
1612 && opP
->reg
!= ZADDR0
)
1613 || opP
->disp
.exp
.X_op
!= O_absent
1614 || ((opP
->index
.reg
< DATA0
1615 || opP
->index
.reg
> DATA7
)
1616 && (opP
->index
.reg
< ADDR0
1617 || opP
->index
.reg
> ADDR7
))
1618 || opP
->index
.size
!= SIZE_UNSPEC
1619 || opP
->index
.scale
!= 1))
1624 if (opP
->mode
!= CONTROL
1625 || ! (opP
->reg
== FPI
1627 || opP
->reg
== FPC
))
1632 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
1637 if (opP
->mode
!= IMMED
)
1639 else if (opP
->disp
.exp
.X_op
!= O_constant
1640 || opP
->disp
.exp
.X_add_number
< 0
1641 || opP
->disp
.exp
.X_add_number
> 7)
1646 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
1650 /* JF these are out of order. We could put them
1651 in order if we were willing to put up with
1652 bunches of #ifdef m68851s in the code.
1654 Don't forget that you need these operands
1655 to use 68030 MMU instructions. */
1657 /* Memory addressing mode used by pflushr */
1659 if (opP
->mode
== CONTROL
1660 || opP
->mode
== FPREG
1661 || opP
->mode
== DREG
1662 || opP
->mode
== AREG
1663 || opP
->mode
== REGLST
)
1665 /* We should accept immediate operands, but they
1666 supposedly have to be quad word, and we don't
1667 handle that. I would like to see what a Motorola
1668 assembler does before doing something here. */
1669 if (opP
->mode
== IMMED
)
1674 if (opP
->mode
!= CONTROL
1675 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1680 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
1685 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
1690 if (opP
->mode
!= CONTROL
1693 && opP
->reg
!= SCC
))
1698 if (opP
->mode
!= CONTROL
1704 if (opP
->mode
!= CONTROL
1707 && opP
->reg
!= CRP
))
1712 if (opP
->mode
!= CONTROL
1713 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
1714 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
1719 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
1724 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
1729 if (opP
->mode
!= CONTROL
1736 } /* not a cache specifier. */
1740 if (opP
->mode
!= ABSL
)
1746 } /* switch on type of operand */
1750 } /* for each operand */
1751 } /* if immediately wrong */
1758 opcode
= opcode
->m_next
;
1763 && !(ok_arch
& current_architecture
))
1768 _("invalid instruction for this architecture; needs "));
1769 cp
= buf
+ strlen (buf
);
1773 strcpy (cp
, _("fpu (68040, 68060 or 68881/68882)"));
1776 strcpy (cp
, _("mmu (68030 or 68851)"));
1779 strcpy (cp
, _("68020 or higher"));
1782 strcpy (cp
, _("68000 or higher"));
1785 strcpy (cp
, _("68010 or higher"));
1789 int got_one
= 0, idx
;
1790 for (idx
= 0; idx
< sizeof (archs
) / sizeof (archs
[0]);
1793 if ((archs
[idx
].arch
& ok_arch
)
1794 && ! archs
[idx
].alias
)
1798 strcpy (cp
, " or ");
1802 strcpy (cp
, archs
[idx
].name
);
1808 cp
= xmalloc (strlen (buf
) + 1);
1813 the_ins
.error
= _("operands mismatch");
1815 } /* Fell off the end */
1820 /* now assemble it */
1822 the_ins
.args
= opcode
->m_operands
;
1823 the_ins
.numargs
= opcode
->m_opnum
;
1824 the_ins
.numo
= opcode
->m_codenum
;
1825 the_ins
.opcode
[0] = getone (opcode
);
1826 the_ins
.opcode
[1] = gettwo (opcode
);
1828 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
1830 /* This switch is a doozy.
1831 Watch the first step; its a big one! */
1859 tmpreg
= 0x3c; /* 7.4 */
1860 if (strchr ("bwl", s
[1]))
1861 nextword
= get_num (&opP
->disp
, 80);
1863 nextword
= get_num (&opP
->disp
, 0);
1864 if (isvar (&opP
->disp
))
1865 add_fix (s
[1], &opP
->disp
, 0, 0);
1869 if (!isbyte (nextword
))
1870 opP
->error
= _("operand out of range");
1875 if (!isword (nextword
))
1876 opP
->error
= _("operand out of range");
1881 if (!issword (nextword
))
1882 opP
->error
= _("operand out of range");
1887 addword (nextword
>> 16);
1914 /* We gotta put out some float */
1915 if (op (&opP
->disp
) != O_big
)
1920 /* Can other cases happen here? */
1921 if (op (&opP
->disp
) != O_constant
)
1924 val
= (valueT
) offs (&opP
->disp
);
1928 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
1929 val
>>= LITTLENUM_NUMBER_OF_BITS
;
1933 offs (&opP
->disp
) = gencnt
;
1935 if (offs (&opP
->disp
) > 0)
1937 if (offs (&opP
->disp
) > baseo
)
1939 as_warn (_("Bignum too big for %c format; truncated"),
1941 offs (&opP
->disp
) = baseo
;
1943 baseo
-= offs (&opP
->disp
);
1946 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
1947 offs (&opP
->disp
)--;
1952 gen_to_words (words
, baseo
, (long) outro
);
1953 for (wordp
= words
; baseo
--; wordp
++)
1957 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
1960 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
1963 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
1966 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
1969 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
1973 nextword
= get_num (&opP
->disp
, 80);
1976 && ! isvar (&opP
->disp
)
1979 opP
->disp
.exp
.X_op
= O_symbol
;
1980 #ifndef BFD_ASSEMBLER
1981 opP
->disp
.exp
.X_add_symbol
= &abs_symbol
;
1983 opP
->disp
.exp
.X_add_symbol
=
1984 section_symbol (absolute_section
);
1988 /* Force into index mode. Hope this works */
1990 /* We do the first bit for 32-bit displacements, and the
1991 second bit for 16 bit ones. It is possible that we
1992 should make the default be WORD instead of LONG, but
1993 I think that'd break GCC, so we put up with a little
1994 inefficiency for the sake of working output. */
1996 if (!issword (nextword
)
1997 || (isvar (&opP
->disp
)
1998 && ((opP
->disp
.size
== SIZE_UNSPEC
1999 && flag_short_refs
== 0
2000 && cpu_of_arch (current_architecture
) >= m68020
2001 && cpu_of_arch (current_architecture
) != mcf5200
)
2002 || opP
->disp
.size
== SIZE_LONG
)))
2004 if (cpu_of_arch (current_architecture
) < m68020
2005 || cpu_of_arch (current_architecture
) == mcf5200
)
2007 _("displacement too large for this architecture; needs 68020 or higher");
2009 tmpreg
= 0x3B; /* 7.3 */
2011 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2012 if (isvar (&opP
->disp
))
2016 if (opP
->disp
.size
== SIZE_LONG
2018 /* If the displacement needs pic
2019 relocation it cannot be relaxed. */
2020 || opP
->disp
.pic_reloc
!= pic_none
2025 add_fix ('l', &opP
->disp
, 1, 2);
2029 add_frag (adds (&opP
->disp
),
2031 TAB (PCLEA
, SZ_UNDEF
));
2038 add_fix ('l', &opP
->disp
, 0, 0);
2043 addword (nextword
>> 16);
2048 tmpreg
= 0x3A; /* 7.2 */
2050 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2052 if (isvar (&opP
->disp
))
2056 add_fix ('w', &opP
->disp
, 1, 0);
2059 add_fix ('w', &opP
->disp
, 0, 0);
2069 baseo
= get_num (&opP
->disp
, 80);
2070 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2071 outro
= get_num (&opP
->odisp
, 80);
2072 /* Figure out the `addressing mode'.
2073 Also turn on the BASE_DISABLE bit, if needed. */
2074 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2076 tmpreg
= 0x3b; /* 7.3 */
2077 if (opP
->reg
== ZPC
)
2080 else if (opP
->reg
== 0)
2083 tmpreg
= 0x30; /* 6.garbage */
2085 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2088 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2091 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2093 siz1
= opP
->disp
.size
;
2094 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2095 siz2
= opP
->odisp
.size
;
2099 /* Index register stuff */
2100 if (opP
->index
.reg
!= 0
2101 && opP
->index
.reg
>= DATA
2102 && opP
->index
.reg
<= ADDR7
)
2104 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2106 if (opP
->index
.size
== SIZE_LONG
2107 || (opP
->index
.size
== SIZE_UNSPEC
2108 && m68k_index_width_default
== SIZE_LONG
))
2111 if ((opP
->index
.scale
!= 1
2112 && cpu_of_arch (current_architecture
) < m68020
)
2113 || (opP
->index
.scale
== 8
2114 && current_architecture
== mcf5200
))
2117 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2120 switch (opP
->index
.scale
)
2137 GET US OUT OF HERE! */
2139 /* Must be INDEX, with an index register. Address
2140 register cannot be ZERO-PC, and either :b was
2141 forced, or we know it will fit. For a 68000 or
2142 68010, force this mode anyways, because the
2143 larger modes aren't supported. */
2144 if (opP
->mode
== BASE
2145 && ((opP
->reg
>= ADDR0
2146 && opP
->reg
<= ADDR7
)
2149 if (siz1
== SIZE_BYTE
2150 || cpu_of_arch (current_architecture
) < m68020
2151 || cpu_of_arch (current_architecture
) == mcf5200
2152 || (siz1
== SIZE_UNSPEC
2153 && ! isvar (&opP
->disp
)
2154 && issbyte (baseo
)))
2156 nextword
+= baseo
& 0xff;
2158 if (isvar (&opP
->disp
))
2160 /* Do a byte relocation. If it doesn't
2161 fit (possible on m68000) let the
2162 fixup processing complain later. */
2164 add_fix ('B', &opP
->disp
, 1, 1);
2166 add_fix ('B', &opP
->disp
, 0, 0);
2168 else if (siz1
!= SIZE_BYTE
)
2170 if (siz1
!= SIZE_UNSPEC
)
2171 as_warn (_("Forcing byte displacement"));
2172 if (! issbyte (baseo
))
2173 opP
->error
= _("byte displacement out of range");
2178 else if (siz1
== SIZE_UNSPEC
2180 && isvar (&opP
->disp
)
2181 && subs (&opP
->disp
) == NULL
2183 /* If the displacement needs pic
2184 relocation it cannot be relaxed. */
2185 && opP
->disp
.pic_reloc
== pic_none
2189 /* The code in md_convert_frag_1 needs to be
2190 able to adjust nextword. Call frag_grow
2191 to ensure that we have enough space in
2192 the frag obstack to make all the bytes
2195 nextword
+= baseo
& 0xff;
2197 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2198 TAB (PCINDEX
, SZ_UNDEF
));
2206 nextword
|= 0x40; /* No index reg */
2207 if (opP
->index
.reg
>= ZDATA0
2208 && opP
->index
.reg
<= ZDATA7
)
2209 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2210 else if (opP
->index
.reg
>= ZADDR0
2211 || opP
->index
.reg
<= ZADDR7
)
2212 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2215 /* It isn't simple. */
2217 if (cpu_of_arch (current_architecture
) < m68020
2218 || cpu_of_arch (current_architecture
) == mcf5200
)
2220 _("invalid operand mode for this architecture; needs 68020 or higher");
2223 /* If the guy specified a width, we assume that it is
2224 wide enough. Maybe it isn't. If so, we lose. */
2228 if (isvar (&opP
->disp
)
2230 : ! issword (baseo
))
2235 else if (! isvar (&opP
->disp
) && baseo
== 0)
2244 as_warn (_(":b not permitted; defaulting to :w"));
2254 /* Figure out innner displacement stuff */
2255 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2257 if (cpu_of_arch (current_architecture
) & cpu32
)
2258 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2262 if (isvar (&opP
->odisp
)
2264 : ! issword (outro
))
2269 else if (! isvar (&opP
->odisp
) && outro
== 0)
2278 as_warn (_(":b not permitted; defaulting to :w"));
2287 if (opP
->mode
== POST
2288 && (nextword
& 0x40) == 0)
2293 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2295 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2296 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2298 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2300 if (siz1
== SIZE_LONG
)
2301 addword (baseo
>> 16);
2302 if (siz1
!= SIZE_UNSPEC
)
2305 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2306 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2307 if (siz2
== SIZE_LONG
)
2308 addword (outro
>> 16);
2309 if (siz2
!= SIZE_UNSPEC
)
2315 nextword
= get_num (&opP
->disp
, 80);
2316 switch (opP
->disp
.size
)
2321 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2323 tmpreg
= 0x38; /* 7.0 */
2327 /* Don't generate pc relative code on 68010 and
2329 if (isvar (&opP
->disp
)
2330 && !subs (&opP
->disp
)
2331 && adds (&opP
->disp
)
2333 /* If the displacement needs pic relocation it
2334 cannot be relaxed. */
2335 && opP
->disp
.pic_reloc
== pic_none
2337 && S_GET_SEGMENT (adds (&opP
->disp
)) == now_seg
2338 && relaxable_symbol (adds (&opP
->disp
))
2339 && HAVE_LONG_BRANCH(current_architecture
)
2341 && !strchr ("~%&$?", s
[0]))
2343 tmpreg
= 0x3A; /* 7.2 */
2344 add_frag (adds (&opP
->disp
),
2346 TAB (PCREL
, SZ_UNDEF
));
2349 /* Fall through into long */
2351 if (isvar (&opP
->disp
))
2352 add_fix ('l', &opP
->disp
, 0, 0);
2354 tmpreg
= 0x39;/* 7.1 mode */
2355 addword (nextword
>> 16);
2360 as_bad (_("unsupported byte value; use a different suffix"));
2362 case SIZE_WORD
: /* Word */
2363 if (isvar (&opP
->disp
))
2364 add_fix ('w', &opP
->disp
, 0, 0);
2366 tmpreg
= 0x38;/* 7.0 mode */
2374 as_bad (_("unknown/incorrect operand"));
2377 install_gen_operand (s
[1], tmpreg
);
2383 { /* JF: I hate floating point! */
2398 tmpreg
= get_num (&opP
->disp
, tmpreg
);
2399 if (isvar (&opP
->disp
))
2400 add_fix (s
[1], &opP
->disp
, 0, 0);
2403 case 'b': /* Danger: These do no check for
2404 certain types of overflow.
2406 if (!isbyte (tmpreg
))
2407 opP
->error
= _("out of range");
2408 insop (tmpreg
, opcode
);
2409 if (isvar (&opP
->disp
))
2410 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
2411 (opcode
->m_codenum
) * 2 + 1;
2414 if (!issbyte (tmpreg
))
2415 opP
->error
= _("out of range");
2416 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
2417 if (isvar (&opP
->disp
))
2418 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
2421 if (!isword (tmpreg
))
2422 opP
->error
= _("out of range");
2423 insop (tmpreg
, opcode
);
2424 if (isvar (&opP
->disp
))
2425 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2428 if (!issword (tmpreg
))
2429 opP
->error
= _("out of range");
2430 insop (tmpreg
, opcode
);
2431 if (isvar (&opP
->disp
))
2432 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2435 /* Because of the way insop works, we put these two out
2437 insop (tmpreg
, opcode
);
2438 insop (tmpreg
>> 16, opcode
);
2439 if (isvar (&opP
->disp
))
2440 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2447 install_operand (s
[1], tmpreg
);
2458 install_operand (s
[1], opP
->reg
- ADDR
);
2462 tmpreg
= get_num (&opP
->disp
, 80);
2466 /* The pc_fix argument winds up in fx_pcrel_adjust,
2467 which is a char, and may therefore be unsigned. We
2468 want to pass -1, but we pass 64 instead, and convert
2469 back in md_pcrel_from. */
2470 add_fix ('B', &opP
->disp
, 1, 64);
2473 add_fix ('w', &opP
->disp
, 1, 0);
2478 if (!HAVE_LONG_BRANCH(current_architecture
))
2479 as_warn (_("Can't use long branches on 68000/68010/5200"));
2480 the_ins
.opcode
[the_ins
.numo
- 1] |= 0xff;
2481 add_fix ('l', &opP
->disp
, 1, 0);
2486 if (subs (&opP
->disp
)) /* We can't relax it */
2490 /* If the displacement needs pic relocation it cannot be
2492 if (opP
->disp
.pic_reloc
!= pic_none
)
2496 /* This could either be a symbol, or an absolute
2497 address. No matter, the frag hacking will finger it
2498 out. Not quite: it can't switch from BRANCH to
2499 BCC68000 for the case where opnd is absolute (it
2500 needs to use the 68000 hack since no conditional abs
2502 if (( !HAVE_LONG_BRANCH(current_architecture
)
2503 || (0 == adds (&opP
->disp
)))
2504 && (the_ins
.opcode
[0] >= 0x6200)
2505 && (the_ins
.opcode
[0] <= 0x6f00))
2506 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2507 TAB (BCC68000
, SZ_UNDEF
));
2509 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2510 TAB (ABRANCH
, SZ_UNDEF
));
2513 if (isvar (&opP
->disp
))
2516 /* check for DBcc instruction */
2517 if ((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2519 /* size varies if patch */
2520 /* needed for long form */
2521 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2522 TAB (DBCC
, SZ_UNDEF
));
2526 add_fix ('w', &opP
->disp
, 1, 0);
2530 case 'C': /* Fixed size LONG coproc branches */
2531 add_fix ('l', &opP
->disp
, 1, 0);
2535 case 'c': /* Var size Coprocesssor branches */
2536 if (subs (&opP
->disp
))
2538 add_fix ('l', &opP
->disp
, 1, 0);
2539 add_frag ((symbolS
*) 0, (offsetT
) 0, TAB (FBRANCH
, LONG
));
2541 else if (adds (&opP
->disp
))
2542 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2543 TAB (FBRANCH
, SZ_UNDEF
));
2546 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2547 TAB(FBRANCH,SHORT)); */
2548 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2549 add_fix ('l', &opP
->disp
, 1, 0);
2559 case 'C': /* Ignore it */
2562 case 'd': /* JF this is a kludge */
2563 install_operand ('s', opP
->reg
- ADDR
);
2564 tmpreg
= get_num (&opP
->disp
, 80);
2565 if (!issword (tmpreg
))
2567 as_warn (_("Expression out of range, using 0"));
2574 install_operand (s
[1], opP
->reg
- DATA
);
2578 install_operand (s
[1], opP
->reg
- FP0
);
2582 tmpreg
= opP
->reg
- COP0
;
2583 install_operand (s
[1], tmpreg
);
2586 case 'J': /* JF foo */
2659 install_operand (s
[1], tmpreg
);
2663 tmpreg
= get_num (&opP
->disp
, 55);
2664 install_operand (s
[1], tmpreg
& 0x7f);
2671 if (tmpreg
& 0x7FF0000)
2672 as_bad (_("Floating point register in register list"));
2673 insop (reverse_16_bits (tmpreg
), opcode
);
2677 if (tmpreg
& 0x700FFFF)
2678 as_bad (_("Wrong register in floating-point reglist"));
2679 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
2687 if (tmpreg
& 0x7FF0000)
2688 as_bad (_("Floating point register in register list"));
2689 insop (tmpreg
, opcode
);
2691 else if (s
[1] == '8')
2693 if (tmpreg
& 0x0FFFFFF)
2694 as_bad (_("incorrect register in reglist"));
2695 install_operand (s
[1], tmpreg
>> 24);
2699 if (tmpreg
& 0x700FFFF)
2700 as_bad (_("wrong register in floating-point reglist"));
2702 install_operand (s
[1], tmpreg
>> 16);
2707 install_operand (s
[1], get_num (&opP
->disp
, 60));
2711 tmpreg
= ((opP
->mode
== DREG
)
2712 ? 0x20 + opP
->reg
- DATA
2713 : (get_num (&opP
->disp
, 40) & 0x1F));
2714 install_operand (s
[1], tmpreg
);
2718 tmpreg
= get_num (&opP
->disp
, 10);
2721 install_operand (s
[1], tmpreg
);
2725 /* This depends on the fact that ADDR registers are eight
2726 more than their corresponding DATA regs, so the result
2727 will have the ADDR_REG bit set */
2728 install_operand (s
[1], opP
->reg
- DATA
);
2732 if (opP
->mode
== AINDR
)
2733 install_operand (s
[1], opP
->reg
- DATA
);
2735 install_operand (s
[1], opP
->index
.reg
- DATA
);
2739 if (opP
->reg
== FPI
)
2741 else if (opP
->reg
== FPS
)
2743 else if (opP
->reg
== FPC
)
2747 install_operand (s
[1], tmpreg
);
2750 case 'S': /* Ignore it */
2754 install_operand (s
[1], get_num (&opP
->disp
, 30));
2757 case 'U': /* Ignore it */
2776 as_fatal (_("failed sanity check"));
2777 } /* switch on cache token */
2778 install_operand (s
[1], tmpreg
);
2781 /* JF: These are out of order, I fear. */
2794 install_operand (s
[1], tmpreg
);
2820 install_operand (s
[1], tmpreg
);
2824 if (opP
->reg
== VAL
)
2843 install_operand (s
[1], tmpreg
);
2857 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
2868 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
2874 install_operand (s
[1], tmpreg
);
2877 know (opP
->reg
== PSR
);
2880 know (opP
->reg
== PCSR
);
2895 install_operand (s
[1], tmpreg
);
2898 tmpreg
= get_num (&opP
->disp
, 20);
2899 install_operand (s
[1], tmpreg
);
2901 case '_': /* used only for move16 absolute 32-bit address */
2902 if (isvar (&opP
->disp
))
2903 add_fix ('l', &opP
->disp
, 0, 0);
2904 tmpreg
= get_num (&opP
->disp
, 80);
2905 addword (tmpreg
>> 16);
2906 addword (tmpreg
& 0xFFFF);
2913 /* By the time whe get here (FINALLY) the_ins contains the complete
2914 instruction, ready to be emitted. . . */
2918 reverse_16_bits (in
)
2924 static int mask
[16] =
2926 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2927 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2929 for (n
= 0; n
< 16; n
++)
2932 out
|= mask
[15 - n
];
2935 } /* reverse_16_bits() */
2944 static int mask
[8] =
2946 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2949 for (n
= 0; n
< 8; n
++)
2955 } /* reverse_8_bits() */
2957 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2958 (that value is chosen in the frag_var call in md_assemble). TYPE
2959 is the subtype of the frag to be generated; its primary type is
2960 rs_machine_dependent.
2962 The TYPE parameter is also used by md_convert_frag_1 and
2963 md_estimate_size_before_relax. The appropriate type of fixup will
2964 be emitted by md_convert_frag_1.
2966 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2968 install_operand (mode
, val
)
2975 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge */
2978 the_ins
.opcode
[0] |= val
<< 9;
2981 the_ins
.opcode
[1] |= val
<< 12;
2984 the_ins
.opcode
[1] |= val
<< 6;
2987 the_ins
.opcode
[1] |= val
;
2990 the_ins
.opcode
[2] |= val
<< 12;
2993 the_ins
.opcode
[2] |= val
<< 6;
2996 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2997 three words long! */
2999 the_ins
.opcode
[2] |= val
;
3002 the_ins
.opcode
[1] |= val
<< 7;
3005 the_ins
.opcode
[1] |= val
<< 10;
3009 the_ins
.opcode
[1] |= val
<< 5;
3014 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3017 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3020 the_ins
.opcode
[0] |= val
= 0xff;
3023 the_ins
.opcode
[0] |= val
<< 9;
3026 the_ins
.opcode
[1] |= val
;
3029 the_ins
.opcode
[1] |= val
;
3030 the_ins
.numo
++; /* What a hack */
3033 the_ins
.opcode
[1] |= val
<< 4;
3041 the_ins
.opcode
[0] |= (val
<< 6);
3044 the_ins
.opcode
[1] = (val
>> 16);
3045 the_ins
.opcode
[2] = val
& 0xffff;
3049 as_fatal (_("failed sanity check."));
3051 } /* install_operand() */
3054 install_gen_operand (mode
, val
)
3061 the_ins
.opcode
[0] |= val
;
3064 /* This is a kludge!!! */
3065 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3074 the_ins
.opcode
[0] |= val
;
3076 /* more stuff goes here */
3078 as_fatal (_("failed sanity check."));
3080 } /* install_gen_operand() */
3083 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3084 * then deal with the bitfield hack.
3088 crack_operand (str
, opP
)
3090 register struct m68k_op
*opP
;
3092 register int parens
;
3094 register char *beg_str
;
3102 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3108 else if (*str
== ')')
3112 opP
->error
= _("Extra )");
3118 if (flag_mri
&& *str
== '\'')
3119 inquote
= ! inquote
;
3121 if (!*str
&& parens
)
3123 opP
->error
= _("Missing )");
3128 if (m68k_ip_op (beg_str
, opP
) != 0)
3135 c
= *++str
; /* JF bitfield hack */
3140 as_bad (_("Missing operand"));
3143 /* Detect MRI REG symbols and convert them to REGLSTs. */
3144 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
3147 opP
->mask
= ~(int)opP
->reg
;
3154 /* This is the guts of the machine-dependent assembler. STR points to a
3155 machine dependent instruction. This function is supposed to emit
3156 the frags/bytes it assembles to.
3160 insert_reg (regname
, regnum
)
3161 const char *regname
;
3167 #ifdef REGISTER_PREFIX
3168 if (!flag_reg_prefix_optional
)
3170 buf
[0] = REGISTER_PREFIX
;
3171 strcpy (buf
+ 1, regname
);
3176 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
3177 &zero_address_frag
));
3179 for (i
= 0; regname
[i
]; i
++)
3180 buf
[i
] = islower (regname
[i
]) ? toupper (regname
[i
]) : regname
[i
];
3183 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
3184 &zero_address_frag
));
3193 static const struct init_entry init_table
[] =
3248 /* control registers */
3249 { "sfc", SFC
}, /* Source Function Code */
3251 { "dfc", DFC
}, /* Destination Function Code */
3253 { "cacr", CACR
}, /* Cache Control Register */
3254 { "caar", CAAR
}, /* Cache Address Register */
3256 { "usp", USP
}, /* User Stack Pointer */
3257 { "vbr", VBR
}, /* Vector Base Register */
3258 { "msp", MSP
}, /* Master Stack Pointer */
3259 { "isp", ISP
}, /* Interrupt Stack Pointer */
3261 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0 */
3262 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1 */
3263 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0 */
3264 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1 */
3266 /* 68ec040 versions of same */
3267 { "iacr0", ITT0
}, /* Instruction Access Control Register 0 */
3268 { "iacr1", ITT1
}, /* Instruction Access Control Register 0 */
3269 { "dacr0", DTT0
}, /* Data Access Control Register 0 */
3270 { "dacr1", DTT1
}, /* Data Access Control Register 0 */
3272 /* mcf5200 versions of same. The ColdFire programmer's reference
3273 manual indicated that the order is 2,3,0,1, but Ken Rose
3274 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3275 { "acr0", ITT0
}, /* Access Control Unit 0 */
3276 { "acr1", ITT1
}, /* Access Control Unit 1 */
3277 { "acr2", DTT0
}, /* Access Control Unit 2 */
3278 { "acr3", DTT1
}, /* Access Control Unit 3 */
3280 { "tc", TC
}, /* MMU Translation Control Register */
3283 { "mmusr", MMUSR
}, /* MMU Status Register */
3284 { "srp", SRP
}, /* User Root Pointer */
3285 { "urp", URP
}, /* Supervisor Root Pointer */
3290 { "rombar", ROMBAR
}, /* ROM Base Address Register */
3291 { "rambar0", RAMBAR0
}, /* ROM Base Address Register */
3292 { "rambar1", RAMBAR1
}, /* ROM Base Address Register */
3293 { "mbar", MBAR
}, /* Module Base Address Register */
3294 /* end of control registers */
3328 /* 68ec030 versions of same */
3331 /* 68ec030 access control unit, identical to 030 MMU status reg */
3334 /* Suppressed data and address registers. */
3359 for (i
= 0; init_table
[i
].name
; i
++)
3360 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
3363 static int no_68851
, no_68881
;
3366 /* a.out machine type. Default to 68020. */
3367 int m68k_aout_machtype
= 2;
3379 int shorts_this_frag
;
3382 /* In MRI mode, the instruction and operands are separated by a
3383 space. Anything following the operands is a comment. The label
3384 has already been removed. */
3392 for (s
= str
; *s
!= '\0'; s
++)
3394 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
3412 inquote
= ! inquote
;
3417 memset ((char *) (&the_ins
), '\0', sizeof (the_ins
));
3422 for (n
= 0; n
< the_ins
.numargs
; n
++)
3423 if (the_ins
.operands
[n
].error
)
3425 er
= the_ins
.operands
[n
].error
;
3431 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
3435 /* If there is a current label, record that it marks an instruction. */
3436 if (current_label
!= NULL
)
3438 current_label
->text
= 1;
3439 current_label
= NULL
;
3442 if (the_ins
.nfrag
== 0)
3444 /* No frag hacking involved; just put it out */
3445 toP
= frag_more (2 * the_ins
.numo
);
3446 fromP
= &the_ins
.opcode
[0];
3447 for (m
= the_ins
.numo
; m
; --m
)
3449 md_number_to_chars (toP
, (long) (*fromP
), 2);
3453 /* put out symbol-dependent info */
3454 for (m
= 0; m
< the_ins
.nrel
; m
++)
3456 switch (the_ins
.reloc
[m
].wid
)
3475 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3476 the_ins
.reloc
[m
].wid
);
3479 fixP
= fix_new_exp (frag_now
,
3480 ((toP
- frag_now
->fr_literal
)
3481 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3483 &the_ins
.reloc
[m
].exp
,
3484 the_ins
.reloc
[m
].pcrel
,
3485 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
3486 the_ins
.reloc
[m
].pic_reloc
));
3487 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3488 if (the_ins
.reloc
[m
].wid
== 'B')
3489 fixP
->fx_signed
= 1;
3494 /* There's some frag hacking */
3495 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
3500 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
3502 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3503 toP
= frag_more (wid
);
3505 shorts_this_frag
= 0;
3506 for (m
= wid
/ 2; m
; --m
)
3508 md_number_to_chars (toP
, (long) (*fromP
), 2);
3513 for (m
= 0; m
< the_ins
.nrel
; m
++)
3515 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
3517 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
3520 wid
= the_ins
.reloc
[m
].wid
;
3523 the_ins
.reloc
[m
].wid
= 0;
3524 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3526 fixP
= fix_new_exp (frag_now
,
3527 ((toP
- frag_now
->fr_literal
)
3528 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3530 &the_ins
.reloc
[m
].exp
,
3531 the_ins
.reloc
[m
].pcrel
,
3532 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
3533 the_ins
.reloc
[m
].pic_reloc
));
3534 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3536 (void) frag_var (rs_machine_dependent
, 10, 0,
3537 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
3538 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
3540 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3541 shorts_this_frag
= 0;
3544 toP
= frag_more (n
* sizeof (short));
3547 md_number_to_chars (toP
, (long) (*fromP
), 2);
3553 for (m
= 0; m
< the_ins
.nrel
; m
++)
3557 wid
= the_ins
.reloc
[m
].wid
;
3560 the_ins
.reloc
[m
].wid
= 0;
3561 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3563 fixP
= fix_new_exp (frag_now
,
3564 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
3565 - shorts_this_frag
* 2),
3567 &the_ins
.reloc
[m
].exp
,
3568 the_ins
.reloc
[m
].pcrel
,
3569 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
3570 the_ins
.reloc
[m
].pic_reloc
));
3571 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3579 * md_begin -- set up hash tables with 68000 instructions.
3580 * similar to what the vax assembler does. ---phr
3582 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3583 a copy of it at runtime, adding in the information we want but isn't
3584 there. I think it'd be better to have an awk script hack the table
3585 at compile time. Or even just xstr the table and use it as-is. But
3586 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3589 register const struct m68k_opcode
*ins
;
3590 register struct m68k_incant
*hack
, *slak
;
3591 register const char *retval
= 0; /* empty string, or error msg text */
3592 register unsigned int i
;
3597 flag_reg_prefix_optional
= 1;
3599 if (! m68k_rel32_from_cmdline
)
3603 op_hash
= hash_new ();
3605 obstack_begin (&robyn
, 4000);
3606 for (i
= 0; i
< m68k_numopcodes
; i
++)
3608 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3611 ins
= &m68k_opcodes
[i
];
3612 /* We *could* ignore insns that don't match our arch here
3613 but just leaving them out of the hash. */
3614 slak
->m_operands
= ins
->args
;
3615 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
3616 slak
->m_arch
= ins
->arch
;
3617 slak
->m_opcode
= ins
->opcode
;
3618 /* This is kludgey */
3619 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
3620 if (i
+ 1 != m68k_numopcodes
3621 && !strcmp (ins
->name
, m68k_opcodes
[i
+ 1].name
))
3623 slak
->m_next
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3628 slak
= slak
->m_next
;
3632 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
3634 as_fatal (_("Internal Error: Can't hash %s: %s"), ins
->name
, retval
);
3637 for (i
= 0; i
< m68k_numaliases
; i
++)
3639 const char *name
= m68k_opcode_aliases
[i
].primary
;
3640 const char *alias
= m68k_opcode_aliases
[i
].alias
;
3641 PTR val
= hash_find (op_hash
, name
);
3643 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
3644 retval
= hash_insert (op_hash
, alias
, val
);
3646 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
3649 /* In MRI mode, all unsized branches are variable sized. Normally,
3650 they are word sized. */
3653 static struct m68k_opcode_alias mri_aliases
[] =
3673 for (i
= 0; i
< sizeof mri_aliases
/ sizeof mri_aliases
[0]; i
++)
3675 const char *name
= mri_aliases
[i
].primary
;
3676 const char *alias
= mri_aliases
[i
].alias
;
3677 PTR val
= hash_find (op_hash
, name
);
3679 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
3680 retval
= hash_jam (op_hash
, alias
, val
);
3682 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
3686 for (i
= 0; i
< sizeof (mklower_table
); i
++)
3687 mklower_table
[i
] = (isupper (c
= (char) i
)) ? tolower (c
) : c
;
3689 for (i
= 0; i
< sizeof (notend_table
); i
++)
3691 notend_table
[i
] = 0;
3692 alt_notend_table
[i
] = 0;
3694 notend_table
[','] = 1;
3695 notend_table
['{'] = 1;
3696 notend_table
['}'] = 1;
3697 alt_notend_table
['a'] = 1;
3698 alt_notend_table
['A'] = 1;
3699 alt_notend_table
['d'] = 1;
3700 alt_notend_table
['D'] = 1;
3701 alt_notend_table
['#'] = 1;
3702 alt_notend_table
['&'] = 1;
3703 alt_notend_table
['f'] = 1;
3704 alt_notend_table
['F'] = 1;
3705 #ifdef REGISTER_PREFIX
3706 alt_notend_table
[REGISTER_PREFIX
] = 1;
3709 /* We need to put '(' in alt_notend_table to handle
3710 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3712 alt_notend_table
['('] = 1;
3714 /* We need to put '@' in alt_notend_table to handle
3715 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3717 alt_notend_table
['@'] = 1;
3719 /* We need to put digits in alt_notend_table to handle
3720 bfextu %d0{24:1},%d0
3722 alt_notend_table
['0'] = 1;
3723 alt_notend_table
['1'] = 1;
3724 alt_notend_table
['2'] = 1;
3725 alt_notend_table
['3'] = 1;
3726 alt_notend_table
['4'] = 1;
3727 alt_notend_table
['5'] = 1;
3728 alt_notend_table
['6'] = 1;
3729 alt_notend_table
['7'] = 1;
3730 alt_notend_table
['8'] = 1;
3731 alt_notend_table
['9'] = 1;
3733 #ifndef MIT_SYNTAX_ONLY
3734 /* Insert pseudo ops, these have to go into the opcode table since
3735 gas expects pseudo ops to start with a dot */
3738 while (mote_pseudo_table
[n
].poc_name
)
3740 hack
= (struct m68k_incant
*)
3741 obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3742 hash_insert (op_hash
,
3743 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
3744 hack
->m_operands
= 0;
3754 record_alignment (text_section
, 2);
3755 record_alignment (data_section
, 2);
3756 record_alignment (bss_section
, 2);
3761 select_control_regs ()
3763 /* Note which set of "movec" control registers is available. */
3764 switch (cpu_of_arch (current_architecture
))
3767 control_regs
= m68000_control_regs
;
3770 control_regs
= m68010_control_regs
;
3774 control_regs
= m68020_control_regs
;
3777 control_regs
= m68040_control_regs
;
3780 control_regs
= m68060_control_regs
;
3783 control_regs
= cpu32_control_regs
;
3786 control_regs
= mcf5200_control_regs
;
3794 m68k_init_after_args ()
3796 if (cpu_of_arch (current_architecture
) == 0)
3799 const char *default_cpu
= TARGET_CPU
;
3801 if (*default_cpu
== 'm')
3803 for (i
= 0; i
< n_archs
; i
++)
3804 if (strcasecmp (default_cpu
, archs
[i
].name
) == 0)
3808 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU
);
3809 current_architecture
|= m68020
;
3812 current_architecture
|= archs
[i
].arch
;
3814 /* Permit m68881 specification with all cpus; those that can't work
3815 with a coprocessor could be doing emulation. */
3816 if (current_architecture
& m68851
)
3818 if (current_architecture
& m68040
)
3820 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
3823 /* What other incompatibilities could we check for? */
3825 /* Toss in some default assumptions about coprocessors. */
3827 && (cpu_of_arch (current_architecture
)
3828 /* Can CPU32 have a 68881 coprocessor?? */
3829 & (m68020
| m68030
| cpu32
)))
3831 current_architecture
|= m68881
;
3834 && (cpu_of_arch (current_architecture
) & m68020up
) != 0
3835 && (cpu_of_arch (current_architecture
) & m68040up
) == 0)
3837 current_architecture
|= m68851
;
3839 if (no_68881
&& (current_architecture
& m68881
))
3840 as_bad (_("options for 68881 and no-68881 both given"));
3841 if (no_68851
&& (current_architecture
& m68851
))
3842 as_bad (_("options for 68851 and no-68851 both given"));
3845 /* Work out the magic number. This isn't very general. */
3846 if (current_architecture
& m68000
)
3847 m68k_aout_machtype
= 0;
3848 else if (current_architecture
& m68010
)
3849 m68k_aout_machtype
= 1;
3850 else if (current_architecture
& m68020
)
3851 m68k_aout_machtype
= 2;
3853 m68k_aout_machtype
= 2;
3856 /* Note which set of "movec" control registers is available. */
3857 select_control_regs ();
3859 if (cpu_of_arch (current_architecture
) < m68020
3860 || cpu_of_arch (current_architecture
) == mcf5200
)
3861 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
3864 /* This is called when a label is defined. */
3867 m68k_frob_label (sym
)
3870 struct label_line
*n
;
3872 n
= (struct label_line
*) xmalloc (sizeof *n
);
3875 as_where (&n
->file
, &n
->line
);
3881 /* This is called when a value that is not an instruction is emitted. */
3884 m68k_flush_pending_output ()
3886 current_label
= NULL
;
3889 /* This is called at the end of the assembly, when the final value of
3890 the label is known. We warn if this is a text symbol aligned at an
3894 m68k_frob_symbol (sym
)
3897 if (S_GET_SEGMENT (sym
) == reg_section
3898 && (int) S_GET_VALUE (sym
) < 0)
3900 S_SET_SEGMENT (sym
, absolute_section
);
3901 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
3903 else if ((S_GET_VALUE (sym
) & 1) != 0)
3905 struct label_line
*l
;
3907 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3909 if (l
->label
== sym
)
3912 as_warn_where (l
->file
, l
->line
,
3913 _("text label `%s' aligned to odd boundary"),
3921 /* This is called if we go in or out of MRI mode because of the .mri
3925 m68k_mri_mode_change (on
)
3930 if (! flag_reg_prefix_optional
)
3932 flag_reg_prefix_optional
= 1;
3933 #ifdef REGISTER_PREFIX
3938 if (! m68k_rel32_from_cmdline
)
3943 if (! reg_prefix_optional_seen
)
3945 #ifdef REGISTER_PREFIX_OPTIONAL
3946 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
3948 flag_reg_prefix_optional
= 0;
3950 #ifdef REGISTER_PREFIX
3955 if (! m68k_rel32_from_cmdline
)
3960 /* Equal to MAX_PRECISION in atof-ieee.c */
3961 #define MAX_LITTLENUMS 6
3963 /* Turn a string in input_line_pointer into a floating point constant
3964 of type type, and store the appropriate bytes in *litP. The number
3965 of LITTLENUMS emitted is stored in *sizeP . An error message is
3966 returned, or NULL on OK. */
3969 md_atof (type
, litP
, sizeP
)
3975 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3976 LITTLENUM_TYPE
*wordP
;
4007 return _("Bad call to MD_ATOF()");
4009 t
= atof_ieee (input_line_pointer
, type
, words
);
4011 input_line_pointer
= t
;
4013 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4014 for (wordP
= words
; prec
--;)
4016 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
4017 litP
+= sizeof (LITTLENUM_TYPE
);
4023 md_number_to_chars (buf
, val
, n
)
4028 number_to_chars_bigendian (buf
, val
, n
);
4032 md_apply_fix_2 (fixP
, val
)
4036 addressT upper_limit
;
4037 offsetT lower_limit
;
4039 /* This is unnecessary but it convinces the native rs6000 compiler
4040 to generate the code we want. */
4041 char *buf
= fixP
->fx_frag
->fr_literal
;
4042 buf
+= fixP
->fx_where
;
4043 /* end ibm compiler workaround */
4045 if (val
& 0x80000000)
4046 val
|= ~(addressT
)0x7fffffff;
4053 memset (buf
, 0, fixP
->fx_size
);
4054 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc */
4056 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4057 && !S_IS_DEFINED (fixP
->fx_addsy
)
4058 && !S_IS_WEAK (fixP
->fx_addsy
))
4059 S_SET_WEAK (fixP
->fx_addsy
);
4064 #ifdef BFD_ASSEMBLER
4065 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4066 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4070 switch (fixP
->fx_size
)
4072 /* The cast to offsetT below are necessary to make code correct for
4073 machines where ints are smaller than offsetT */
4077 lower_limit
= - (offsetT
) 0x80;
4080 *buf
++ = (val
>> 8);
4082 upper_limit
= 0x7fff;
4083 lower_limit
= - (offsetT
) 0x8000;
4086 *buf
++ = (val
>> 24);
4087 *buf
++ = (val
>> 16);
4088 *buf
++ = (val
>> 8);
4090 upper_limit
= 0x7fffffff;
4091 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* avoid constant overflow */
4094 BAD_CASE (fixP
->fx_size
);
4097 /* Fix up a negative reloc. */
4098 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4100 fixP
->fx_addsy
= fixP
->fx_subsy
;
4101 fixP
->fx_subsy
= NULL
;
4105 /* For non-pc-relative values, it's conceivable we might get something
4106 like "0xff" for a byte field. So extend the upper part of the range
4107 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4108 so that we can do any range checking at all. */
4109 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
4110 upper_limit
= upper_limit
* 2 + 1;
4112 if ((addressT
) val
> upper_limit
4113 && (val
> 0 || val
< lower_limit
))
4114 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("value out of range"));
4116 /* A one byte PC-relative reloc means a short branch. We can't use
4117 a short branch with a value of 0 or -1, because those indicate
4118 different opcodes (branches with longer offsets). fixup_segment
4119 in write.c may have clobbered fx_pcrel, so we need to examine the
4122 #ifdef BFD_ASSEMBLER
4123 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
4126 && fixP
->fx_size
== 1
4127 && (fixP
->fx_addsy
== NULL
4128 || S_IS_DEFINED (fixP
->fx_addsy
))
4129 && (val
== 0 || val
== -1))
4130 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("invalid byte branch offset"));
4133 #ifdef BFD_ASSEMBLER
4135 md_apply_fix (fixP
, valp
)
4139 md_apply_fix_2 (fixP
, (addressT
) *valp
);
4143 void md_apply_fix (fixP
, val
)
4147 md_apply_fix_2 (fixP
, (addressT
) val
);
4151 /* *fragP has been relaxed to its final size, and now needs to have
4152 the bytes inside it modified to conform to the new size There is UGLY
4156 md_convert_frag_1 (fragP
)
4157 register fragS
*fragP
;
4163 /* Address in object code of the displacement. */
4164 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4166 /* Address in gas core of the place to store the displacement. */
4167 /* This convinces the native rs6000 compiler to generate the code we
4169 register char *buffer_address
= fragP
->fr_literal
;
4170 buffer_address
+= fragP
->fr_fix
;
4171 /* end ibm compiler workaround */
4173 /* The displacement of the address, from current location. */
4174 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4175 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4177 #ifdef BFD_ASSEMBLER
4178 disp
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
4181 switch (fragP
->fr_subtype
)
4183 case TAB (BCC68000
, BYTE
):
4184 case TAB (ABRANCH
, BYTE
):
4185 know (issbyte (disp
));
4187 as_bad (_("short branch with zero offset: use :w"));
4188 fragP
->fr_opcode
[1] = disp
;
4191 case TAB (DBCC
, SHORT
):
4192 know (issword (disp
));
4195 case TAB (BCC68000
, SHORT
):
4196 case TAB (ABRANCH
, SHORT
):
4197 know (issword (disp
));
4198 fragP
->fr_opcode
[1] = 0x00;
4201 case TAB (ABRANCH
, LONG
):
4202 if (!HAVE_LONG_BRANCH(current_architecture
))
4204 if (fragP
->fr_opcode
[0] == 0x61)
4207 fragP
->fr_opcode
[0] = 0x4E;
4208 fragP
->fr_opcode
[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4222 else if (fragP
->fr_opcode
[0] == 0x60)
4224 fragP
->fr_opcode
[0] = 0x4E;
4225 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4226 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4227 fragP
->fr_offset
, 0, NO_RELOC
);
4233 as_bad (_("Long branch offset not supported."));
4238 fragP
->fr_opcode
[1] = (char) 0xff;
4242 case TAB (BCC68000
, LONG
):
4243 /* only Bcc 68000 instructions can come here */
4244 /* change bcc into b!cc/jmp absl long */
4245 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
4246 fragP
->fr_opcode
[1] = 0x6;/* branch offset = 6 */
4248 /* JF: these used to be fr_opcode[2,3], but they may be in a
4249 different frag, in which case refering to them is a no-no.
4250 Only fr_opcode[0,1] are guaranteed to work. */
4251 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4252 *buffer_address
++ = (char) 0xf9;
4253 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4254 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4255 fragP
->fr_offset
, 0, NO_RELOC
);
4259 case TAB (DBCC
, LONG
):
4260 /* only DBcc 68000 instructions can come here */
4261 /* change dbcc into dbcc/jmp absl long */
4262 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4263 *buffer_address
++ = 0x00; /* branch offset = 4 */
4264 *buffer_address
++ = 0x04;
4265 *buffer_address
++ = 0x60; /* put in bra pc+6 */
4266 *buffer_address
++ = 0x06;
4267 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4268 *buffer_address
++ = (char) 0xf9;
4270 fragP
->fr_fix
+= 6; /* account for bra/jmp instructions */
4271 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4272 fragP
->fr_offset
, 0, NO_RELOC
);
4276 case TAB (FBRANCH
, SHORT
):
4277 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4280 case TAB (FBRANCH
, LONG
):
4281 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit */
4284 case TAB (PCREL
, SHORT
):
4287 case TAB (PCREL
, LONG
):
4288 /* The thing to do here is force it to ABSOLUTE LONG, since
4289 PCREL is really trying to shorten an ABSOLUTE address anyway */
4290 /* JF FOO This code has not been tested */
4291 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4293 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
4294 as_bad (_("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx"),
4295 (unsigned) fragP
->fr_opcode
[0],
4296 (unsigned long) fragP
->fr_address
);
4297 fragP
->fr_opcode
[1] &= ~0x3F;
4298 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
4302 case TAB (PCLEA
, SHORT
):
4303 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4304 fragP
->fr_offset
, 1, NO_RELOC
);
4305 fragP
->fr_opcode
[1] &= ~0x3F;
4306 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
4309 case TAB (PCLEA
, LONG
):
4310 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
) + 2, 4, fragP
->fr_symbol
,
4311 fragP
->fr_offset
, 1, NO_RELOC
);
4312 fixP
->fx_pcrel_adjust
= 2;
4313 /* Already set to mode 7.3; this indicates: PC indirect with
4314 suppressed index, 32-bit displacement. */
4315 *buffer_address
++ = 0x01;
4316 *buffer_address
++ = 0x70;
4321 case TAB (PCINDEX
, BYTE
):
4323 if (!issbyte (disp
))
4325 as_bad (_("displacement doesn't fit in one byte"));
4328 assert (fragP
->fr_fix
>= 2);
4329 buffer_address
[-2] &= ~1;
4330 buffer_address
[-1] = disp
;
4333 case TAB (PCINDEX
, SHORT
):
4335 assert (issword (disp
));
4336 assert (fragP
->fr_fix
>= 2);
4337 buffer_address
[-2] |= 0x1;
4338 buffer_address
[-1] = 0x20;
4339 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4340 fragP
->fr_offset
, (fragP
->fr_opcode
[1] & 077) == 073,
4342 fixP
->fx_pcrel_adjust
= 2;
4345 case TAB (PCINDEX
, LONG
):
4347 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4348 fragP
->fr_offset
, (fragP
->fr_opcode
[1] & 077) == 073,
4350 fixP
->fx_pcrel_adjust
= 2;
4351 assert (fragP
->fr_fix
>= 2);
4352 buffer_address
[-2] |= 0x1;
4353 buffer_address
[-1] = 0x30;
4360 md_number_to_chars (buffer_address
, (long) disp
, (int) ext
);
4361 fragP
->fr_fix
+= ext
;
4365 #ifndef BFD_ASSEMBLER
4368 md_convert_frag (headers
, sec
, fragP
)
4369 object_headers
*headers
;
4373 md_convert_frag_1 (fragP
);
4379 md_convert_frag (abfd
, sec
, fragP
)
4384 md_convert_frag_1 (fragP
);
4388 /* Force truly undefined symbols to their maximum size, and generally set up
4389 the frag list to be relaxed
4392 md_estimate_size_before_relax (fragP
, segment
)
4393 register fragS
*fragP
;
4397 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
4399 old_fix
= fragP
->fr_fix
;
4401 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4402 switch (fragP
->fr_subtype
)
4405 case TAB (ABRANCH
, SZ_UNDEF
):
4407 if ((fragP
->fr_symbol
!= NULL
) /* Not absolute */
4408 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4409 && relaxable_symbol (fragP
->fr_symbol
))
4411 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4414 else if ((fragP
->fr_symbol
== 0) || !HAVE_LONG_BRANCH(current_architecture
))
4416 /* On 68000, or for absolute value, switch to abs long */
4417 /* FIXME, we should check abs val, pick short or long */
4418 if (fragP
->fr_opcode
[0] == 0x61)
4420 fragP
->fr_opcode
[0] = 0x4E;
4421 fragP
->fr_opcode
[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4422 fix_new (fragP
, fragP
->fr_fix
, 4,
4423 fragP
->fr_symbol
, fragP
->fr_offset
, 0, NO_RELOC
);
4427 else if (fragP
->fr_opcode
[0] == 0x60)
4429 fragP
->fr_opcode
[0] = 0x4E;
4430 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4431 fix_new (fragP
, fragP
->fr_fix
, 4,
4432 fragP
->fr_symbol
, fragP
->fr_offset
, 0, NO_RELOC
);
4438 as_warn (_("Long branch offset to extern symbol not supported."));
4442 { /* Symbol is still undefined. Make it simple */
4443 fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4444 fragP
->fr_offset
, 1, NO_RELOC
);
4446 fragP
->fr_opcode
[1] = (char) 0xff;
4452 } /* case TAB(ABRANCH,SZ_UNDEF) */
4454 case TAB (FBRANCH
, SZ_UNDEF
):
4456 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4457 && relaxable_symbol (fragP
->fr_symbol
))
4460 fragP
->fr_subtype
= TAB (FBRANCH
, SHORT
);
4465 fix_new (fragP
, (int) fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4466 fragP
->fr_offset
, 1, NO_RELOC
);
4468 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit */
4472 } /* TAB(FBRANCH,SZ_UNDEF) */
4474 case TAB (PCREL
, SZ_UNDEF
):
4476 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4477 && relaxable_symbol (fragP
->fr_symbol
))
4479 || cpu_of_arch (current_architecture
) < m68020
4480 || cpu_of_arch (current_architecture
) == mcf5200
)
4482 fragP
->fr_subtype
= TAB (PCREL
, SHORT
);
4487 fragP
->fr_subtype
= TAB (PCREL
, LONG
);
4491 } /* TAB(PCREL,SZ_UNDEF) */
4493 case TAB (BCC68000
, SZ_UNDEF
):
4495 if ((fragP
->fr_symbol
!= NULL
)
4496 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4497 && relaxable_symbol (fragP
->fr_symbol
))
4499 fragP
->fr_subtype
= TAB (BCC68000
, BYTE
);
4502 /* only Bcc 68000 instructions can come here */
4503 /* change bcc into b!cc/jmp absl long */
4504 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
4505 if (flag_short_refs
)
4507 fragP
->fr_opcode
[1] = 0x04; /* branch offset = 6 */
4508 /* JF: these were fr_opcode[2,3] */
4509 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
4510 buffer_address
[1] = (char) 0xf8;
4511 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4512 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4513 fragP
->fr_offset
, 0, NO_RELOC
);
4518 fragP
->fr_opcode
[1] = 0x06; /* branch offset = 6 */
4519 /* JF: these were fr_opcode[2,3] */
4520 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
4521 buffer_address
[1] = (char) 0xf9;
4522 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4523 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4524 fragP
->fr_offset
, 0, NO_RELOC
);
4529 } /* case TAB(BCC68000,SZ_UNDEF) */
4531 case TAB (DBCC
, SZ_UNDEF
):
4533 if (fragP
->fr_symbol
!= NULL
4534 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4535 && relaxable_symbol (fragP
->fr_symbol
))
4537 fragP
->fr_subtype
= TAB (DBCC
, SHORT
);
4541 /* only DBcc 68000 instructions can come here */
4542 /* change dbcc into dbcc/jmp absl long */
4543 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4544 buffer_address
[0] = 0x00; /* branch offset = 4 */
4545 buffer_address
[1] = 0x04;
4546 buffer_address
[2] = 0x60; /* put in bra pc + ... */
4548 if (flag_short_refs
)
4550 /* JF: these were fr_opcode[5-7] */
4551 buffer_address
[3] = 0x04; /* plus 4 */
4552 buffer_address
[4] = 0x4e; /* Put in Jump Word */
4553 buffer_address
[5] = (char) 0xf8;
4554 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
4555 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4556 fragP
->fr_offset
, 0, NO_RELOC
);
4561 /* JF: these were fr_opcode[5-7] */
4562 buffer_address
[3] = 0x06; /* Plus 6 */
4563 buffer_address
[4] = 0x4e; /* put in jmp long (0x4ef9) */
4564 buffer_address
[5] = (char) 0xf9;
4565 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
4566 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4567 fragP
->fr_offset
, 0, NO_RELOC
);
4573 } /* case TAB(DBCC,SZ_UNDEF) */
4575 case TAB (PCLEA
, SZ_UNDEF
):
4577 if (((S_GET_SEGMENT (fragP
->fr_symbol
)) == segment
4578 && relaxable_symbol (fragP
->fr_symbol
))
4580 || cpu_of_arch (current_architecture
) < m68020
4581 || cpu_of_arch (current_architecture
) == mcf5200
)
4583 fragP
->fr_subtype
= TAB (PCLEA
, SHORT
);
4588 fragP
->fr_subtype
= TAB (PCLEA
, LONG
);
4592 } /* TAB(PCLEA,SZ_UNDEF) */
4594 case TAB (PCINDEX
, SZ_UNDEF
):
4595 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4596 && relaxable_symbol (fragP
->fr_symbol
))
4597 || cpu_of_arch (current_architecture
) < m68020
4598 || cpu_of_arch (current_architecture
) == mcf5200
)
4600 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
4604 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
4613 /* now that SZ_UNDEF are taken care of, check others */
4614 switch (fragP
->fr_subtype
)
4616 case TAB (BCC68000
, BYTE
):
4617 case TAB (ABRANCH
, BYTE
):
4618 /* We can't do a short jump to the next instruction, so in that
4619 case we force word mode. At this point S_GET_VALUE should
4620 return the offset of the symbol within its frag. If the
4621 symbol is at the start of a frag, and it is the next frag
4622 with any data in it (usually this is just the next frag, but
4623 assembler listings may introduce empty frags), we must use
4625 if (fragP
->fr_symbol
&& S_GET_VALUE (fragP
->fr_symbol
) == 0)
4629 for (l
= fragP
->fr_next
;
4630 l
!= fragP
->fr_symbol
->sy_frag
;
4632 if (l
->fr_fix
+ l
->fr_var
!= 0)
4634 if (l
== fragP
->fr_symbol
->sy_frag
)
4636 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4644 return fragP
->fr_var
+ fragP
->fr_fix
- old_fix
;
4647 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4648 /* the bit-field entries in the relocation_info struct plays hell
4649 with the byte-order problems of cross-assembly. So as a hack,
4650 I added this mach. dependent ri twiddler. Ugly, but it gets
4652 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4653 are symbolnum, most sig. byte first. Last byte is broken up with
4654 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4655 nibble as nuthin. (on Sun 3 at least) */
4656 /* Translate the internal relocation information into target-specific
4660 md_ri_to_chars (the_bytes
, ri
)
4662 struct reloc_info_generic
*ri
;
4665 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
4666 /* now the fun stuff */
4667 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
4668 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
4669 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
4670 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80) | ((ri
->r_length
<< 5) & 0x60) |
4671 ((ri
->r_extern
<< 4) & 0x10));
4674 #endif /* comment */
4676 #ifndef BFD_ASSEMBLER
4678 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4681 relax_addressT segment_address_in_file
;
4684 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4685 * Out: GNU LD relocation length code: 0, 1, or 2.
4688 static CONST
unsigned char nbytes_r_length
[] = {42, 0, 1, 42, 2};
4691 know (fixP
->fx_addsy
!= NULL
);
4693 md_number_to_chars (where
,
4694 fixP
->fx_frag
->fr_address
+ fixP
->fx_where
- segment_address_in_file
,
4697 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4698 ? S_GET_TYPE (fixP
->fx_addsy
)
4699 : fixP
->fx_addsy
->sy_number
);
4701 where
[4] = (r_symbolnum
>> 16) & 0x0ff;
4702 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4703 where
[6] = r_symbolnum
& 0x0ff;
4704 where
[7] = (((fixP
->fx_pcrel
<< 7) & 0x80) | ((nbytes_r_length
[fixP
->fx_size
] << 5) & 0x60) |
4705 (((!S_IS_DEFINED (fixP
->fx_addsy
)) << 4) & 0x10));
4709 #endif /* OBJ_AOUT or OBJ_BOUT */
4711 #ifndef WORKING_DOT_WORD
4712 CONST
int md_short_jump_size
= 4;
4713 CONST
int md_long_jump_size
= 6;
4716 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4718 addressT from_addr
, to_addr
;
4724 offset
= to_addr
- (from_addr
+ 2);
4726 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
4727 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
4731 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4733 addressT from_addr
, to_addr
;
4739 if (!HAVE_LONG_BRANCH(current_architecture
))
4741 offset
= to_addr
- S_GET_VALUE (to_symbol
);
4742 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
4743 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4744 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
4749 offset
= to_addr
- (from_addr
+ 2);
4750 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
4751 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4757 /* Different values of OK tell what its OK to return. Things that
4758 aren't OK are an error (what a shock, no?)
4761 10: Absolute 1:8 only
4762 20: Absolute 0:7 only
4763 30: absolute 0:15 only
4764 40: Absolute 0:31 only
4765 50: absolute 0:127 only
4766 55: absolute -64:63 only
4767 60: absolute -128:127 only
4768 70: absolute 0:4095 only
4775 struct m68k_exp
*exp
;
4778 if (exp
->exp
.X_op
== O_absent
)
4780 /* Do the same thing the VAX asm does */
4781 op (exp
) = O_constant
;
4787 as_warn (_("expression out of range: defaulting to 1"));
4791 else if (exp
->exp
.X_op
== O_constant
)
4796 if (offs (exp
) < 1 || offs (exp
) > 8)
4798 as_warn (_("expression out of range: defaulting to 1"));
4803 if (offs (exp
) < 0 || offs (exp
) > 7)
4807 if (offs (exp
) < 0 || offs (exp
) > 15)
4811 if (offs (exp
) < 0 || offs (exp
) > 32)
4815 if (offs (exp
) < 0 || offs (exp
) > 127)
4819 if (offs (exp
) < -64 || offs (exp
) > 63)
4823 if (offs (exp
) < -128 || offs (exp
) > 127)
4827 if (offs (exp
) < 0 || offs (exp
) > 4095)
4830 as_warn (_("expression out of range: defaulting to 0"));
4838 else if (exp
->exp
.X_op
== O_big
)
4840 if (offs (exp
) <= 0 /* flonum */
4841 && (ok
== 80 /* no bignums */
4842 || (ok
> 10 /* small-int ranges including 0 ok */
4843 /* If we have a flonum zero, a zero integer should
4844 do as well (e.g., in moveq). */
4845 && generic_floating_point_number
.exponent
== 0
4846 && generic_floating_point_number
.low
[0] == 0)))
4848 /* HACK! Turn it into a long */
4849 LITTLENUM_TYPE words
[6];
4851 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
4852 op (exp
) = O_constant
;
4855 offs (exp
) = words
[1] | (words
[0] << 16);
4859 op (exp
) = O_constant
;
4862 offs (exp
) = (ok
== 10) ? 1 : 0;
4863 as_warn (_("Can't deal with expression; defaulting to %ld"),
4869 if (ok
>= 10 && ok
<= 70)
4871 op (exp
) = O_constant
;
4874 offs (exp
) = (ok
== 10) ? 1 : 0;
4875 as_warn (_("Can't deal with expression; defaulting to %ld"),
4880 if (exp
->size
!= SIZE_UNSPEC
)
4888 if (!isbyte (offs (exp
)))
4889 as_warn (_("expression doesn't fit in BYTE"));
4892 if (!isword (offs (exp
)))
4893 as_warn (_("expression doesn't fit in WORD"));
4901 /* These are the back-ends for the various machine dependent pseudo-ops. */
4907 subseg_set (data_section
, 1);
4908 demand_empty_rest_of_line ();
4915 subseg_set (data_section
, 2);
4916 demand_empty_rest_of_line ();
4923 /* We don't support putting frags in the BSS segment, we fake it
4924 by marking in_bss, then looking at s_skip for clues. */
4926 subseg_set (bss_section
, 0);
4927 demand_empty_rest_of_line ();
4935 register long temp_fill
;
4937 temp
= 1; /* JF should be 2? */
4938 temp_fill
= get_absolute_expression ();
4939 if (!need_pass_2
) /* Never make frag if expect extra pass. */
4940 frag_align (temp
, (int) temp_fill
, 0);
4941 demand_empty_rest_of_line ();
4942 record_alignment (now_seg
, temp
);
4949 demand_empty_rest_of_line ();
4952 /* Pseudo-ops handled for MRI compatibility. */
4954 /* This function returns non-zero if the argument is a conditional
4955 pseudo-op. This is called when checking whether a pending
4956 alignment is needed. */
4959 m68k_conditional_pseudoop (pop
)
4962 return (pop
->poc_handler
== s_mri_if
4963 || pop
->poc_handler
== s_mri_else
);
4966 /* Handle an MRI style chip specification. */
4975 s
= input_line_pointer
;
4976 /* We can't use get_symbol_end since the processor names are not proper
4978 while (is_part_of_name (c
= *input_line_pointer
++))
4980 *--input_line_pointer
= 0;
4981 for (i
= 0; i
< n_archs
; i
++)
4982 if (strcasecmp (s
, archs
[i
].name
) == 0)
4986 as_bad (_("%s: unrecognized processor name"), s
);
4987 *input_line_pointer
= c
;
4988 ignore_rest_of_line ();
4991 *input_line_pointer
= c
;
4993 if (*input_line_pointer
== '/')
4994 current_architecture
= 0;
4996 current_architecture
&= m68881
| m68851
;
4997 current_architecture
|= archs
[i
].arch
;
4999 while (*input_line_pointer
== '/')
5001 ++input_line_pointer
;
5002 s
= input_line_pointer
;
5003 /* We can't use get_symbol_end since the processor names are not
5005 while (is_part_of_name (c
= *input_line_pointer
++))
5007 *--input_line_pointer
= 0;
5008 if (strcmp (s
, "68881") == 0)
5009 current_architecture
|= m68881
;
5010 else if (strcmp (s
, "68851") == 0)
5011 current_architecture
|= m68851
;
5012 *input_line_pointer
= c
;
5015 /* Update info about available control registers. */
5016 select_control_regs ();
5019 /* The MRI CHIP pseudo-op. */
5029 stop
= mri_comment_field (&stopc
);
5032 mri_comment_end (stop
, stopc
);
5033 demand_empty_rest_of_line ();
5036 /* The MRI FOPT pseudo-op. */
5044 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
5048 input_line_pointer
+= 3;
5049 temp
= get_absolute_expression ();
5050 if (temp
< 0 || temp
> 7)
5051 as_bad (_("bad coprocessor id"));
5053 m68k_float_copnum
= COP0
+ temp
;
5057 as_bad (_("unrecognized fopt option"));
5058 ignore_rest_of_line ();
5062 demand_empty_rest_of_line ();
5065 /* The structure used to handle the MRI OPT pseudo-op. */
5069 /* The name of the option. */
5072 /* If this is not NULL, just call this function. The first argument
5073 is the ARG field of this structure, the second argument is
5074 whether the option was negated. */
5075 void (*pfn
) PARAMS ((int arg
, int on
));
5077 /* If this is not NULL, and the PFN field is NULL, set the variable
5078 this points to. Set it to the ARG field if the option was not
5079 negated, and the NOTARG field otherwise. */
5082 /* The value to pass to PFN or to assign to *PVAR. */
5085 /* The value to assign to *PVAR if the option is negated. If PFN is
5086 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5087 the option may not be negated. */
5091 /* The table used to handle the MRI OPT pseudo-op. */
5093 static void skip_to_comma
PARAMS ((int, int));
5094 static void opt_nest
PARAMS ((int, int));
5095 static void opt_chip
PARAMS ((int, int));
5096 static void opt_list
PARAMS ((int, int));
5097 static void opt_list_symbols
PARAMS ((int, int));
5099 static const struct opt_action opt_table
[] =
5101 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5103 /* We do relaxing, so there is little use for these options. */
5104 { "b", 0, 0, 0, 0 },
5105 { "brs", 0, 0, 0, 0 },
5106 { "brb", 0, 0, 0, 0 },
5107 { "brl", 0, 0, 0, 0 },
5108 { "brw", 0, 0, 0, 0 },
5110 { "c", 0, 0, 0, 0 },
5111 { "cex", 0, 0, 0, 0 },
5112 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5113 { "cl", 0, 0, 0, 0 },
5114 { "cre", 0, 0, 0, 0 },
5115 { "d", 0, &flag_keep_locals
, 1, 0 },
5116 { "e", 0, 0, 0, 0 },
5117 { "f", 0, &flag_short_refs
, 1, 0 },
5118 { "frs", 0, &flag_short_refs
, 1, 0 },
5119 { "frl", 0, &flag_short_refs
, 0, 1 },
5120 { "g", 0, 0, 0, 0 },
5121 { "i", 0, 0, 0, 0 },
5122 { "m", 0, 0, 0, 0 },
5123 { "mex", 0, 0, 0, 0 },
5124 { "mc", 0, 0, 0, 0 },
5125 { "md", 0, 0, 0, 0 },
5126 { "nest", opt_nest
, 0, 0, 0 },
5127 { "next", skip_to_comma
, 0, 0, 0 },
5128 { "o", 0, 0, 0, 0 },
5129 { "old", 0, 0, 0, 0 },
5130 { "op", skip_to_comma
, 0, 0, 0 },
5131 { "pco", 0, 0, 0, 0 },
5132 { "p", opt_chip
, 0, 0, 0 },
5133 { "pcr", 0, 0, 0, 0 },
5134 { "pcs", 0, 0, 0, 0 },
5135 { "r", 0, 0, 0, 0 },
5136 { "quick", 0, &m68k_quick
, 1, 0 },
5137 { "rel32", 0, &m68k_rel32
, 1, 0 },
5138 { "s", opt_list
, 0, 0, 0 },
5139 { "t", opt_list_symbols
, 0, 0, 0 },
5140 { "w", 0, &flag_no_warnings
, 0, 1 },
5144 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5146 /* The MRI OPT pseudo-op. */
5158 const struct opt_action
*o
;
5163 if (*input_line_pointer
== '-')
5165 ++input_line_pointer
;
5168 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5170 input_line_pointer
+= 2;
5174 s
= input_line_pointer
;
5175 c
= get_symbol_end ();
5177 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5179 if (strcasecmp (s
, o
->name
) == 0)
5183 /* Restore input_line_pointer now in case the option
5185 *input_line_pointer
= c
;
5186 (*o
->pfn
) (o
->arg
, t
);
5188 else if (o
->pvar
!= NULL
)
5190 if (! t
&& o
->arg
== o
->notarg
)
5191 as_bad (_("option `%s' may not be negated"), s
);
5192 *input_line_pointer
= c
;
5193 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5196 *input_line_pointer
= c
;
5202 as_bad (_("option `%s' not recognized"), s
);
5203 *input_line_pointer
= c
;
5206 while (*input_line_pointer
++ == ',');
5208 /* Move back to terminating character. */
5209 --input_line_pointer
;
5210 demand_empty_rest_of_line ();
5213 /* Skip ahead to a comma. This is used for OPT options which we do
5214 not suppor tand which take arguments. */
5217 skip_to_comma (arg
, on
)
5221 while (*input_line_pointer
!= ','
5222 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5223 ++input_line_pointer
;
5226 /* Handle the OPT NEST=depth option. */
5233 if (*input_line_pointer
!= '=')
5235 as_bad (_("bad format of OPT NEST=depth"));
5239 ++input_line_pointer
;
5240 max_macro_nest
= get_absolute_expression ();
5243 /* Handle the OPT P=chip option. */
5250 if (*input_line_pointer
!= '=')
5252 /* This is just OPT P, which we do not support. */
5256 ++input_line_pointer
;
5260 /* Handle the OPT S option. */
5270 /* Handle the OPT T option. */
5273 opt_list_symbols (arg
, on
)
5278 listing
|= LISTING_SYMBOLS
;
5280 listing
&=~ LISTING_SYMBOLS
;
5283 /* Handle the MRI REG pseudo-op. */
5296 if (line_label
== NULL
)
5298 as_bad (_("missing label"));
5299 ignore_rest_of_line ();
5304 stop
= mri_comment_field (&stopc
);
5308 s
= input_line_pointer
;
5309 while (isalnum ((unsigned char) *input_line_pointer
)
5310 #ifdef REGISTER_PREFIX
5311 || *input_line_pointer
== REGISTER_PREFIX
5313 || *input_line_pointer
== '/'
5314 || *input_line_pointer
== '-')
5315 ++input_line_pointer
;
5316 c
= *input_line_pointer
;
5317 *input_line_pointer
= '\0';
5319 if (m68k_ip_op (s
, &rop
) != 0)
5321 if (rop
.error
== NULL
)
5322 as_bad (_("bad register list"));
5324 as_bad (_("bad register list: %s"), rop
.error
);
5325 *input_line_pointer
= c
;
5326 ignore_rest_of_line ();
5330 *input_line_pointer
= c
;
5332 if (rop
.mode
== REGLST
)
5334 else if (rop
.mode
== DREG
)
5335 mask
= 1 << (rop
.reg
- DATA0
);
5336 else if (rop
.mode
== AREG
)
5337 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
5338 else if (rop
.mode
== FPREG
)
5339 mask
= 1 << (rop
.reg
- FP0
+ 16);
5340 else if (rop
.mode
== CONTROL
5343 else if (rop
.mode
== CONTROL
5346 else if (rop
.mode
== CONTROL
5351 as_bad (_("bad register list"));
5352 ignore_rest_of_line ();
5356 S_SET_SEGMENT (line_label
, reg_section
);
5357 S_SET_VALUE (line_label
, ~mask
);
5358 line_label
->sy_frag
= &zero_address_frag
;
5361 mri_comment_end (stop
, stopc
);
5363 demand_empty_rest_of_line ();
5366 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5370 struct save_opts
*next
;
5372 int symbols_case_sensitive
;
5380 /* FIXME: We don't save OPT S. */
5383 /* This variable holds the stack of saved options. */
5385 static struct save_opts
*save_stack
;
5387 /* The MRI SAVE pseudo-op. */
5393 struct save_opts
*s
;
5395 s
= (struct save_opts
*) xmalloc (sizeof (struct save_opts
));
5396 s
->abspcadd
= m68k_abspcadd
;
5397 s
->symbols_case_sensitive
= symbols_case_sensitive
;
5398 s
->keep_locals
= flag_keep_locals
;
5399 s
->short_refs
= flag_short_refs
;
5400 s
->architecture
= current_architecture
;
5401 s
->quick
= m68k_quick
;
5402 s
->rel32
= m68k_rel32
;
5403 s
->listing
= listing
;
5404 s
->no_warnings
= flag_no_warnings
;
5406 s
->next
= save_stack
;
5409 demand_empty_rest_of_line ();
5412 /* The MRI RESTORE pseudo-op. */
5418 struct save_opts
*s
;
5420 if (save_stack
== NULL
)
5422 as_bad (_("restore without save"));
5423 ignore_rest_of_line ();
5428 save_stack
= s
->next
;
5430 m68k_abspcadd
= s
->abspcadd
;
5431 symbols_case_sensitive
= s
->symbols_case_sensitive
;
5432 flag_keep_locals
= s
->keep_locals
;
5433 flag_short_refs
= s
->short_refs
;
5434 current_architecture
= s
->architecture
;
5435 m68k_quick
= s
->quick
;
5436 m68k_rel32
= s
->rel32
;
5437 listing
= s
->listing
;
5438 flag_no_warnings
= s
->no_warnings
;
5442 demand_empty_rest_of_line ();
5445 /* Types of MRI structured control directives. */
5447 enum mri_control_type
5455 /* This structure is used to stack the MRI structured control
5458 struct mri_control_info
5460 /* The directive within which this one is enclosed. */
5461 struct mri_control_info
*outer
;
5463 /* The type of directive. */
5464 enum mri_control_type type
;
5466 /* Whether an ELSE has been in an IF. */
5469 /* The add or sub statement at the end of a FOR. */
5472 /* The label of the top of a FOR or REPEAT loop. */
5475 /* The label to jump to for the next iteration, or the else
5476 expression of a conditional. */
5479 /* The label to jump to to break out of the loop, or the label past
5480 the end of a conditional. */
5484 /* The stack of MRI structured control directives. */
5486 static struct mri_control_info
*mri_control_stack
;
5488 /* The current MRI structured control directive index number, used to
5489 generate label names. */
5491 static int mri_control_index
;
5493 /* Some function prototypes. */
5495 static void mri_assemble
PARAMS ((char *));
5496 static char *mri_control_label
PARAMS ((void));
5497 static struct mri_control_info
*push_mri_control
5498 PARAMS ((enum mri_control_type
));
5499 static void pop_mri_control
PARAMS ((void));
5500 static int parse_mri_condition
PARAMS ((int *));
5501 static int parse_mri_control_operand
5502 PARAMS ((int *, char **, char **, char **, char **));
5503 static int swap_mri_condition
PARAMS ((int));
5504 static int reverse_mri_condition
PARAMS ((int));
5505 static void build_mri_control_operand
5506 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5507 const char *, int));
5508 static void parse_mri_control_expression
5509 PARAMS ((char *, int, const char *, const char *, int));
5511 /* Assemble an instruction for an MRI structured control directive. */
5519 /* md_assemble expects the opcode to be in lower case. */
5520 for (s
= str
; *s
!= ' ' && *s
!= '\0'; s
++)
5522 if (isupper ((unsigned char) *s
))
5523 *s
= tolower ((unsigned char) *s
);
5529 /* Generate a new MRI label structured control directive label name. */
5532 mri_control_label ()
5536 n
= (char *) xmalloc (20);
5537 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
5538 ++mri_control_index
;
5542 /* Create a new MRI structured control directive. */
5544 static struct mri_control_info
*
5545 push_mri_control (type
)
5546 enum mri_control_type type
;
5548 struct mri_control_info
*n
;
5550 n
= (struct mri_control_info
*) xmalloc (sizeof (struct mri_control_info
));
5554 if (type
== mri_if
|| type
== mri_while
)
5557 n
->top
= mri_control_label ();
5558 n
->next
= mri_control_label ();
5559 n
->bottom
= mri_control_label ();
5561 n
->outer
= mri_control_stack
;
5562 mri_control_stack
= n
;
5567 /* Pop off the stack of MRI structured control directives. */
5572 struct mri_control_info
*n
;
5574 n
= mri_control_stack
;
5575 mri_control_stack
= n
->outer
;
5583 /* Recognize a condition code in an MRI structured control expression. */
5586 parse_mri_condition (pcc
)
5591 know (*input_line_pointer
== '<');
5593 ++input_line_pointer
;
5594 c1
= *input_line_pointer
++;
5595 c2
= *input_line_pointer
++;
5597 if (*input_line_pointer
!= '>')
5599 as_bad (_("syntax error in structured control directive"));
5603 ++input_line_pointer
;
5611 *pcc
= (c1
<< 8) | c2
;
5616 /* Parse a single operand in an MRI structured control expression. */
5619 parse_mri_control_operand (pcc
, leftstart
, leftstop
, rightstart
, rightstop
)
5636 if (*input_line_pointer
== '<')
5638 /* It's just a condition code. */
5639 return parse_mri_condition (pcc
);
5642 /* Look ahead for the condition code. */
5643 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5645 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
5650 as_bad (_("missing condition code in structured control directive"));
5654 *leftstart
= input_line_pointer
;
5656 if (*leftstop
> *leftstart
5657 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
5660 input_line_pointer
= s
;
5661 if (! parse_mri_condition (pcc
))
5664 /* Look ahead for AND or OR or end of line. */
5665 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5667 if ((strncasecmp (s
, "AND", 3) == 0
5668 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
5669 || (strncasecmp (s
, "OR", 2) == 0
5670 && (s
[2] == '.' || ! is_part_of_name (s
[2]))))
5674 *rightstart
= input_line_pointer
;
5676 if (*rightstop
> *rightstart
5677 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
5680 input_line_pointer
= s
;
5685 #define MCC(b1, b2) (((b1) << 8) | (b2))
5687 /* Swap the sense of a condition. This changes the condition so that
5688 it generates the same result when the operands are swapped. */
5691 swap_mri_condition (cc
)
5696 case MCC ('h', 'i'): return MCC ('c', 's');
5697 case MCC ('l', 's'): return MCC ('c', 'c');
5698 case MCC ('c', 'c'): return MCC ('l', 's');
5699 case MCC ('c', 's'): return MCC ('h', 'i');
5700 case MCC ('p', 'l'): return MCC ('m', 'i');
5701 case MCC ('m', 'i'): return MCC ('p', 'l');
5702 case MCC ('g', 'e'): return MCC ('l', 'e');
5703 case MCC ('l', 't'): return MCC ('g', 't');
5704 case MCC ('g', 't'): return MCC ('l', 't');
5705 case MCC ('l', 'e'): return MCC ('g', 'e');
5710 /* Reverse the sense of a condition. */
5713 reverse_mri_condition (cc
)
5718 case MCC ('h', 'i'): return MCC ('l', 's');
5719 case MCC ('l', 's'): return MCC ('h', 'i');
5720 case MCC ('c', 'c'): return MCC ('c', 's');
5721 case MCC ('c', 's'): return MCC ('c', 'c');
5722 case MCC ('n', 'e'): return MCC ('e', 'q');
5723 case MCC ('e', 'q'): return MCC ('n', 'e');
5724 case MCC ('v', 'c'): return MCC ('v', 's');
5725 case MCC ('v', 's'): return MCC ('v', 'c');
5726 case MCC ('p', 'l'): return MCC ('m', 'i');
5727 case MCC ('m', 'i'): return MCC ('p', 'l');
5728 case MCC ('g', 'e'): return MCC ('l', 't');
5729 case MCC ('l', 't'): return MCC ('g', 'e');
5730 case MCC ('g', 't'): return MCC ('l', 'e');
5731 case MCC ('l', 'e'): return MCC ('g', 't');
5736 /* Build an MRI structured control expression. This generates test
5737 and branch instructions. It goes to TRUELAB if the condition is
5738 true, and to FALSELAB if the condition is false. Exactly one of
5739 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5740 is the size qualifier for the expression. EXTENT is the size to
5741 use for the branch. */
5744 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5745 rightstop
, truelab
, falselab
, extent
)
5752 const char *truelab
;
5753 const char *falselab
;
5759 if (leftstart
!= NULL
)
5761 struct m68k_op leftop
, rightop
;
5764 /* Swap the compare operands, if necessary, to produce a legal
5765 m68k compare instruction. Comparing a register operand with
5766 a non-register operand requires the register to be on the
5767 right (cmp, cmpa). Comparing an immediate value with
5768 anything requires the immediate value to be on the left
5773 (void) m68k_ip_op (leftstart
, &leftop
);
5778 (void) m68k_ip_op (rightstart
, &rightop
);
5781 if (rightop
.mode
== IMMED
5782 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
5783 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
5787 cc
= swap_mri_condition (cc
);
5789 leftstart
= rightstart
;
5792 leftstop
= rightstop
;
5797 if (truelab
== NULL
)
5799 cc
= reverse_mri_condition (cc
);
5803 if (leftstart
!= NULL
)
5805 buf
= (char *) xmalloc (20
5806 + (leftstop
- leftstart
)
5807 + (rightstop
- rightstart
));
5815 memcpy (s
, leftstart
, leftstop
- leftstart
);
5816 s
+= leftstop
- leftstart
;
5818 memcpy (s
, rightstart
, rightstop
- rightstart
);
5819 s
+= rightstop
- rightstart
;
5825 buf
= (char *) xmalloc (20 + strlen (truelab
));
5833 strcpy (s
, truelab
);
5838 /* Parse an MRI structured control expression. This generates test
5839 and branch instructions. STOP is where the expression ends. It
5840 goes to TRUELAB if the condition is true, and to FALSELAB if the
5841 condition is false. Exactly one of TRUELAB and FALSELAB will be
5842 NULL, meaning to fall through. QUAL is the size qualifier for the
5843 expression. EXTENT is the size to use for the branch. */
5846 parse_mri_control_expression (stop
, qual
, truelab
, falselab
, extent
)
5849 const char *truelab
;
5850 const char *falselab
;
5863 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
5864 &rightstart
, &rightstop
))
5870 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
5874 if (falselab
!= NULL
)
5877 flab
= mri_control_label ();
5879 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5880 rightstop
, (const char *) NULL
, flab
, extent
);
5882 input_line_pointer
+= 3;
5883 if (*input_line_pointer
!= '.'
5884 || input_line_pointer
[1] == '\0')
5888 qual
= input_line_pointer
[1];
5889 input_line_pointer
+= 2;
5892 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
5893 &rightstart
, &rightstop
))
5899 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5900 rightstop
, truelab
, falselab
, extent
);
5902 if (falselab
== NULL
)
5905 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
5909 if (truelab
!= NULL
)
5912 tlab
= mri_control_label ();
5914 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5915 rightstop
, tlab
, (const char *) NULL
, extent
);
5917 input_line_pointer
+= 2;
5918 if (*input_line_pointer
!= '.'
5919 || input_line_pointer
[1] == '\0')
5923 qual
= input_line_pointer
[1];
5924 input_line_pointer
+= 2;
5927 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
5928 &rightstart
, &rightstop
))
5934 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5935 rightstop
, truelab
, falselab
, extent
);
5937 if (truelab
== NULL
)
5942 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5943 rightstop
, truelab
, falselab
, extent
);
5947 if (input_line_pointer
!= stop
)
5948 as_bad (_("syntax error in structured control directive"));
5951 /* Handle the MRI IF pseudo-op. This may be a structured control
5952 directive, or it may be a regular assembler conditional, depending
5961 struct mri_control_info
*n
;
5963 /* A structured control directive must end with THEN with an
5964 optional qualifier. */
5965 s
= input_line_pointer
;
5966 while (! is_end_of_line
[(unsigned char) *s
]
5967 && (! flag_mri
|| *s
!= '*'))
5970 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
5973 if (s
- input_line_pointer
> 1
5977 if (s
- input_line_pointer
< 3
5978 || strncasecmp (s
- 3, "THEN", 4) != 0)
5982 as_bad (_("missing then"));
5983 ignore_rest_of_line ();
5987 /* It's a conditional. */
5992 /* Since this might be a conditional if, this pseudo-op will be
5993 called even if we are supported to be ignoring input. Double
5994 check now. Clobber *input_line_pointer so that ignore_input
5995 thinks that this is not a special pseudo-op. */
5996 c
= *input_line_pointer
;
5997 *input_line_pointer
= 0;
5998 if (ignore_input ())
6000 *input_line_pointer
= c
;
6001 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6002 ++input_line_pointer
;
6003 demand_empty_rest_of_line ();
6006 *input_line_pointer
= c
;
6008 n
= push_mri_control (mri_if
);
6010 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
6011 n
->next
, s
[1] == '.' ? s
[2] : '\0');
6014 input_line_pointer
= s
+ 3;
6016 input_line_pointer
= s
+ 1;
6020 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6021 ++input_line_pointer
;
6024 demand_empty_rest_of_line ();
6027 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6028 structured IF, associate the ELSE with the IF. Otherwise, assume
6029 it is a conditional else. */
6040 && (mri_control_stack
== NULL
6041 || mri_control_stack
->type
!= mri_if
6042 || mri_control_stack
->else_seen
))
6048 c
= *input_line_pointer
;
6049 *input_line_pointer
= 0;
6050 if (ignore_input ())
6052 *input_line_pointer
= c
;
6053 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6054 ++input_line_pointer
;
6055 demand_empty_rest_of_line ();
6058 *input_line_pointer
= c
;
6060 if (mri_control_stack
== NULL
6061 || mri_control_stack
->type
!= mri_if
6062 || mri_control_stack
->else_seen
)
6064 as_bad (_("else without matching if"));
6065 ignore_rest_of_line ();
6069 mri_control_stack
->else_seen
= 1;
6071 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->bottom
));
6074 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6078 colon (mri_control_stack
->next
);
6082 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6083 ++input_line_pointer
;
6086 demand_empty_rest_of_line ();
6089 /* Handle the MRI ENDI pseudo-op. */
6095 if (mri_control_stack
== NULL
6096 || mri_control_stack
->type
!= mri_if
)
6098 as_bad (_("endi without matching if"));
6099 ignore_rest_of_line ();
6103 /* ignore_input will not return true for ENDI, so we don't need to
6104 worry about checking it again here. */
6106 if (! mri_control_stack
->else_seen
)
6107 colon (mri_control_stack
->next
);
6108 colon (mri_control_stack
->bottom
);
6114 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6115 ++input_line_pointer
;
6118 demand_empty_rest_of_line ();
6121 /* Handle the MRI BREAK pseudo-op. */
6124 s_mri_break (extent
)
6127 struct mri_control_info
*n
;
6131 n
= mri_control_stack
;
6133 && n
->type
!= mri_for
6134 && n
->type
!= mri_repeat
6135 && n
->type
!= mri_while
)
6139 as_bad (_("break outside of structured loop"));
6140 ignore_rest_of_line ();
6144 buf
= (char *) xmalloc (20 + strlen (n
->bottom
));
6147 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6153 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6154 ++input_line_pointer
;
6157 demand_empty_rest_of_line ();
6160 /* Handle the MRI NEXT pseudo-op. */
6166 struct mri_control_info
*n
;
6170 n
= mri_control_stack
;
6172 && n
->type
!= mri_for
6173 && n
->type
!= mri_repeat
6174 && n
->type
!= mri_while
)
6178 as_bad (_("next outside of structured loop"));
6179 ignore_rest_of_line ();
6183 buf
= (char *) xmalloc (20 + strlen (n
->next
));
6186 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6192 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6193 ++input_line_pointer
;
6196 demand_empty_rest_of_line ();
6199 /* Handle the MRI FOR pseudo-op. */
6205 const char *varstart
, *varstop
;
6206 const char *initstart
, *initstop
;
6207 const char *endstart
, *endstop
;
6208 const char *bystart
, *bystop
;
6212 struct mri_control_info
*n
;
6218 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6222 varstart
= input_line_pointer
;
6224 /* Look for the '='. */
6225 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6226 && *input_line_pointer
!= '=')
6227 ++input_line_pointer
;
6228 if (*input_line_pointer
!= '=')
6230 as_bad (_("missing ="));
6231 ignore_rest_of_line ();
6235 varstop
= input_line_pointer
;
6236 if (varstop
> varstart
6237 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6240 ++input_line_pointer
;
6242 initstart
= input_line_pointer
;
6244 /* Look for TO or DOWNTO. */
6247 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6249 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6250 && ! is_part_of_name (input_line_pointer
[2]))
6252 initstop
= input_line_pointer
;
6253 input_line_pointer
+= 2;
6256 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6257 && ! is_part_of_name (input_line_pointer
[6]))
6259 initstop
= input_line_pointer
;
6261 input_line_pointer
+= 6;
6264 ++input_line_pointer
;
6266 if (initstop
== NULL
)
6268 as_bad (_("missing to or downto"));
6269 ignore_rest_of_line ();
6272 if (initstop
> initstart
6273 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6277 endstart
= input_line_pointer
;
6279 /* Look for BY or DO. */
6282 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6284 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
6285 && ! is_part_of_name (input_line_pointer
[2]))
6287 endstop
= input_line_pointer
;
6289 input_line_pointer
+= 2;
6292 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6293 && (input_line_pointer
[2] == '.'
6294 || ! is_part_of_name (input_line_pointer
[2])))
6296 endstop
= input_line_pointer
;
6297 input_line_pointer
+= 2;
6300 ++input_line_pointer
;
6302 if (endstop
== NULL
)
6304 as_bad (_("missing do"));
6305 ignore_rest_of_line ();
6308 if (endstop
> endstart
6309 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
6315 bystop
= bystart
+ 2;
6320 bystart
= input_line_pointer
;
6324 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6326 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6327 && (input_line_pointer
[2] == '.'
6328 || ! is_part_of_name (input_line_pointer
[2])))
6330 bystop
= input_line_pointer
;
6331 input_line_pointer
+= 2;
6334 ++input_line_pointer
;
6338 as_bad (_("missing do"));
6339 ignore_rest_of_line ();
6342 if (bystop
> bystart
6343 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
6347 if (*input_line_pointer
!= '.')
6351 extent
= input_line_pointer
[1];
6352 input_line_pointer
+= 2;
6355 /* We have fully parsed the FOR operands. Now build the loop. */
6357 n
= push_mri_control (mri_for
);
6359 buf
= (char *) xmalloc (50 + (input_line_pointer
- varstart
));
6370 memcpy (s
, initstart
, initstop
- initstart
);
6371 s
+= initstop
- initstart
;
6373 memcpy (s
, varstart
, varstop
- varstart
);
6374 s
+= varstop
- varstart
;
6388 memcpy (s
, endstart
, endstop
- endstart
);
6389 s
+= endstop
- endstart
;
6391 memcpy (s
, varstart
, varstop
- varstart
);
6392 s
+= varstop
- varstart
;
6400 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
6402 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
6405 /* Put together the add or sub instruction used by ENDF. */
6415 memcpy (s
, bystart
, bystop
- bystart
);
6416 s
+= bystop
- bystart
;
6418 memcpy (s
, varstart
, varstop
- varstart
);
6419 s
+= varstop
- varstart
;
6425 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6426 ++input_line_pointer
;
6429 demand_empty_rest_of_line ();
6432 /* Handle the MRI ENDF pseudo-op. */
6438 if (mri_control_stack
== NULL
6439 || mri_control_stack
->type
!= mri_for
)
6441 as_bad (_("endf without for"));
6442 ignore_rest_of_line ();
6446 colon (mri_control_stack
->next
);
6448 mri_assemble (mri_control_stack
->incr
);
6450 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
6451 mri_assemble (mri_control_stack
->incr
);
6453 free (mri_control_stack
->incr
);
6455 colon (mri_control_stack
->bottom
);
6461 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6462 ++input_line_pointer
;
6465 demand_empty_rest_of_line ();
6468 /* Handle the MRI REPEAT pseudo-op. */
6471 s_mri_repeat (ignore
)
6474 struct mri_control_info
*n
;
6476 n
= push_mri_control (mri_repeat
);
6480 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6481 ++input_line_pointer
;
6483 demand_empty_rest_of_line ();
6486 /* Handle the MRI UNTIL pseudo-op. */
6494 if (mri_control_stack
== NULL
6495 || mri_control_stack
->type
!= mri_repeat
)
6497 as_bad (_("until without repeat"));
6498 ignore_rest_of_line ();
6502 colon (mri_control_stack
->next
);
6504 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
6507 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
6508 mri_control_stack
->top
, '\0');
6510 colon (mri_control_stack
->bottom
);
6512 input_line_pointer
= s
;
6518 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6519 ++input_line_pointer
;
6522 demand_empty_rest_of_line ();
6525 /* Handle the MRI WHILE pseudo-op. */
6533 struct mri_control_info
*n
;
6535 s
= input_line_pointer
;
6536 while (! is_end_of_line
[(unsigned char) *s
]
6537 && (! flag_mri
|| *s
!= '*'))
6540 while (*s
== ' ' || *s
== '\t')
6542 if (s
- input_line_pointer
> 1
6545 if (s
- input_line_pointer
< 2
6546 || strncasecmp (s
- 1, "DO", 2) != 0)
6548 as_bad (_("missing do"));
6549 ignore_rest_of_line ();
6553 n
= push_mri_control (mri_while
);
6557 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
6558 s
[1] == '.' ? s
[2] : '\0');
6560 input_line_pointer
= s
+ 1;
6561 if (*input_line_pointer
== '.')
6562 input_line_pointer
+= 2;
6566 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6567 ++input_line_pointer
;
6570 demand_empty_rest_of_line ();
6573 /* Handle the MRI ENDW pseudo-op. */
6581 if (mri_control_stack
== NULL
6582 || mri_control_stack
->type
!= mri_while
)
6584 as_bad (_("endw without while"));
6585 ignore_rest_of_line ();
6589 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->next
));
6590 sprintf (buf
, "bra %s", mri_control_stack
->next
);
6594 colon (mri_control_stack
->bottom
);
6600 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6601 ++input_line_pointer
;
6604 demand_empty_rest_of_line ();
6609 * Invocation line includes a switch not recognized by the base assembler.
6610 * See if it's a processor-specific option. These are:
6612 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6613 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6614 * Select the architecture. Instructions or features not
6615 * supported by the selected architecture cause fatal
6616 * errors. More than one may be specified. The default is
6617 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6618 * for -m68000, and -m68882 is a synonym for -m68881.
6619 * -[A]m[c]no-68851, -[A]m[c]no-68881
6620 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6621 * so don't use or document it, but that's the way the parsing
6624 * -pic Indicates PIC.
6625 * -k Indicates PIC. (Sun 3 only.)
6628 * Permit `|' to be used in expressions.
6633 CONST
char *md_shortopts
= "lSA:m:kQ:V";
6635 CONST
char *md_shortopts
= "lSA:m:k";
6638 struct option md_longopts
[] = {
6639 #define OPTION_PIC (OPTION_MD_BASE)
6640 {"pic", no_argument
, NULL
, OPTION_PIC
},
6641 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6642 {"register-prefix-optional", no_argument
, NULL
,
6643 OPTION_REGISTER_PREFIX_OPTIONAL
},
6644 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6645 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
6646 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6647 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
6648 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6649 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
6650 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6651 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
6652 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6653 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
6654 {NULL
, no_argument
, NULL
, 0}
6656 size_t md_longopts_size
= sizeof(md_longopts
);
6659 md_parse_option (c
, arg
)
6665 case 'l': /* -l means keep external to 2 bit offset
6666 rather than 16 bit one */
6667 flag_short_refs
= 1;
6670 case 'S': /* -S means that jbsr's always turn into
6672 flag_long_jumps
= 1;
6678 /* intentional fall-through */
6681 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
6685 const char *oarg
= arg
;
6691 if (arg
[0] == 'c' && arg
[1] == '6')
6694 for (i
= 0; i
< n_archs
; i
++)
6695 if (!strcmp (arg
, archs
[i
].name
))
6700 as_bad (_("unrecognized option `%s'"), oarg
);
6703 arch
= archs
[i
].arch
;
6706 else if (arch
== m68851
)
6715 if (arg
[0] == 'c' && arg
[1] == '6')
6718 for (i
= 0; i
< n_archs
; i
++)
6719 if (!strcmp (arg
, archs
[i
].name
))
6721 unsigned long arch
= archs
[i
].arch
;
6722 if (cpu_of_arch (arch
))
6723 /* It's a cpu spec. */
6725 current_architecture
&= ~m68000up
;
6726 current_architecture
|= arch
;
6728 else if (arch
== m68881
)
6730 current_architecture
|= m68881
;
6733 else if (arch
== m68851
)
6735 current_architecture
|= m68851
;
6745 as_bad (_("unrecognized architecture specification `%s'"), arg
);
6754 break; /* -pic, Position Independent Code */
6756 case OPTION_REGISTER_PREFIX_OPTIONAL
:
6757 flag_reg_prefix_optional
= 1;
6758 reg_prefix_optional_seen
= 1;
6761 /* -V: SVR4 argument to print version ID. */
6763 print_version_id ();
6766 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6767 should be emitted or not. FIXME: Not implemented. */
6771 case OPTION_BITWISE_OR
:
6776 n
= (char *) xmalloc (strlen (m68k_comment_chars
) + 1);
6778 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
6782 m68k_comment_chars
= n
;
6786 case OPTION_BASE_SIZE_DEFAULT_16
:
6787 m68k_index_width_default
= SIZE_WORD
;
6790 case OPTION_BASE_SIZE_DEFAULT_32
:
6791 m68k_index_width_default
= SIZE_LONG
;
6794 case OPTION_DISP_SIZE_DEFAULT_16
:
6796 m68k_rel32_from_cmdline
= 1;
6799 case OPTION_DISP_SIZE_DEFAULT_32
:
6801 m68k_rel32_from_cmdline
= 1;
6812 md_show_usage (stream
)
6815 fprintf(stream
, _("\
6817 -l use 1 word for refs to undefined symbols [default 2]\n\
6818 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6819 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6820 | -mcpu32 | -m5200\n\
6821 specify variant of 680X0 architecture [default 68020]\n\
6822 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6823 target has/lacks floating-point coprocessor\n\
6824 [default yes for 68020, 68030, and cpu32]\n"));
6825 fprintf(stream
, _("\
6826 -m68851 | -mno-68851\n\
6827 target has/lacks memory-management unit coprocessor\n\
6828 [default yes for 68020 and up]\n\
6829 -pic, -k generate position independent code\n\
6830 -S turn jbsr into jsr\n\
6831 --register-prefix-optional\n\
6832 recognize register names without prefix character\n\
6833 --bitwise-or do not treat `|' as a comment character\n"));
6834 fprintf (stream
, _("\
6835 --base-size-default-16 base reg without size is 16 bits\n\
6836 --base-size-default-32 base reg without size is 32 bits (default)\n\
6837 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6838 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6843 /* TEST2: Test md_assemble() */
6844 /* Warning, this routine probably doesn't work anymore */
6848 struct m68k_it the_ins
;
6856 if (!gets (buf
) || !*buf
)
6858 if (buf
[0] == '|' || buf
[1] == '.')
6860 for (cp
= buf
; *cp
; cp
++)
6865 memset (&the_ins
, '\0', sizeof (the_ins
));
6866 m68k_ip (&the_ins
, buf
);
6869 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
6873 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
6874 for (n
= 0; n
< the_ins
.numo
; n
++)
6875 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
6877 print_the_insn (&the_ins
.opcode
[0], stdout
);
6878 (void) putchar ('\n');
6880 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
6882 if (the_ins
.operands
[n
].error
)
6884 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
6887 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
, the_ins
.operands
[n
].reg
);
6888 if (the_ins
.operands
[n
].b_const
)
6889 printf ("Constant: '%.*s', ", 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
, the_ins
.operands
[n
].b_const
);
6890 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
, the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
6891 if (the_ins
.operands
[n
].b_iadd
)
6892 printf ("Iadd: '%.*s',", 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
, the_ins
.operands
[n
].b_iadd
);
6893 (void) putchar ('\n');
6905 while (*str
&& *str
!= ' ')
6907 if (str
[-1] == ':' || str
[1] == '=')
6914 /* Possible states for relaxation:
6916 0 0 branch offset byte (bra, etc)
6920 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6924 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6931 /* We have no need to default values of symbols. */
6935 md_undefined_symbol (name
)
6941 /* Round up a section size to the appropriate boundary. */
6943 md_section_align (segment
, size
)
6948 #ifdef BFD_ASSEMBLER
6949 /* For a.out, force the section size to be aligned. If we don't do
6950 this, BFD will align it for us, but it will not write out the
6951 final bytes of the section. This may be a bug in BFD, but it is
6952 easier to fix it here since that is how the other a.out targets
6956 align
= bfd_get_section_alignment (stdoutput
, segment
);
6957 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
6964 /* Exactly what point is a PC-relative offset relative TO?
6965 On the 68k, it is relative to the address of the first extension
6966 word. The difference between the addresses of the offset and the
6967 first extension word is stored in fx_pcrel_adjust. */
6969 md_pcrel_from (fixP
)
6974 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6976 adjust
= fixP
->fx_pcrel_adjust
;
6979 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
6982 #ifndef BFD_ASSEMBLER
6987 tc_coff_symbol_emit_hook (ignore
)
6993 tc_coff_sizemachdep (frag
)
6996 switch (frag
->fr_subtype
& 0x3)
7013 void m68k_elf_final_processing()
7015 /* Set file-specific flags if this is a cpu32 processor */
7016 if (cpu_of_arch (current_architecture
) & cpu32
)
7017 elf_elfheader (stdoutput
)->e_flags
|= EF_CPU32
;
7020 /* end of tc-m68k.c */