1 /* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
2 slow to compile, easy to find file.
4 Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
29 /* note that this file includes real declarations and thus can only be included by one source file per executable. */
30 #include "opcode/m68k.h"
33 /* This variable contains the value to write out at the beginning of
34 the a.out file. The 2<<16 means that this is a 68020 file instead
35 of an old-style 68000 file */
37 long omagic
= 2<<16|OMAGIC
; /* Magic byte for header file */
42 /* This array holds the chars that always start a comment. If the
43 pre-processor is disabled, these aren't very useful */
44 const char comment_chars
[] = "|";
46 /* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49 /* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52 /* Also note that comments like this one will always work. */
53 const char line_comment_chars
[] = "#";
55 const char line_separator_chars
[] = "";
57 /* Chars that can be used to separate mant from exp in floating point nums */
58 const char EXP_CHARS
[] = "eE";
60 /* Chars that mean this number is a floating point constant */
64 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
66 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
67 changed in read.c . Ideally it shouldn't have to know about it at all,
68 but nothing is ideal around here.
71 int md_reloc_size
= 8; /* Size of relocation record */
73 /* Its an arbitrary name: This means I don't approve of it */
74 /* See flames below */
75 static struct obstack robyn
;
77 #define TAB(x,y) (((x)<<2)+(y))
78 #define TABTYPE(xy) ((xy) >> 2)
91 /* Operands we can parse: (And associated modes)
97 reg: address or data register
98 areg: address register
99 apc: address register, PC, ZPC or empty string
100 num: 16 or 32 bit num
102 sz: w or l if omitted, l assumed
103 scale: 1 2 4 or 8 if omitted, 1 assumed
105 7.4 IMMED #num --> NUM
106 0.? DREG dreg --> dreg
107 1.? AREG areg --> areg
108 2.? AINDR areg@ --> *(areg)
109 3.? AINC areg@+ --> *(areg++)
110 4.? ADEC areg@- --> *(--areg)
111 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
112 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
113 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
114 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
115 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
116 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
117 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
118 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
119 7.0 ABSL num:sz --> *(num)
120 num --> *(num) (sz L assumed)
121 *** MSCR otherreg --> Magic
123 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
124 ?.? DINDR dreg@ --> (dreg) -- cas2 only
134 a1@(5,d2:w:1) @(45,d6:l:4)
139 #name@(numw) -->turn into PC rel mode
140 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
167 short e_siz
; /* 0== default 1==short/byte 2==word 3==long */
170 /* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
171 8-15==addr reg for operands that take both types */
174 DATA
= 1, /* 1- 8 == data registers 0-7 */
194 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
199 FPREG
, /* Eight FP registers */
208 COPNUM
= (FPREG
+8), /* Co-processor #1-#8 */
217 PC
, /* Program counter */
218 ZPC
, /* Hack for Program space, but 0 addressing */
220 CCR
, /* Condition code Reg */
222 /* These have to be in order for the movec instruction to work. */
223 USP
, /* User Stack Pointer */
224 ISP
, /* Interrupt stack pointer */
239 /* end of movec ordering constraints */
245 DRP
, /* 68851 or 68030 MMU regs */
269 PSR
, /* aka MMUSR on 68030 (but not MMUSR on 68040)
270 and ACUSR on 68ec030 */
273 IC
, /* instruction cache token */
274 DC
, /* data cache token */
275 NC
, /* no cache token */
276 BC
, /* both caches token */
278 TT0
, /* 68030 access control unit regs */
282 /* Internal form of an operand. */
284 char *error
; /* Couldn't parse it */
285 enum operand_type mode
; /* What mode this instruction is in. */
286 enum _register reg
; /* Base register */
287 struct m68k_exp
*con1
;
288 int ireg
; /* Index register */
289 int isiz
; /* 0==unspec 1==byte(?) 2==short 3==long */
290 int imul
; /* Multipy ireg by this (1,2,4,or 8) */
291 struct m68k_exp
*con2
;
294 /* internal form of a 68020 instruction */
297 char *args
; /* list of opcode info */
300 int numo
; /* Number of shorts in opcode */
303 struct m68k_op operands
[6];
305 int nexp
; /* number of exprs in use */
306 struct m68k_exp exprs
[4];
308 int nfrag
; /* Number of frags we have to produce */
310 int fragoff
; /* Where in the current opcode[] the frag ends */
316 int nrel
; /* Num of reloc strucs in use */
324 } reloc
[5]; /* Five is enough??? */
327 #define cpu_of_arch(x) ((x) & m68000up)
328 #define float_of_arch(x) ((x) & mfloat)
329 #define mmu_of_arch(x) ((x) & mmmu)
331 static struct m68k_it the_ins
; /* the instruction being assembled */
333 /* Macros for adding things to the m68k_it struct */
335 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
337 /* Like addword, but goes BEFORE general operands */
338 #define insop(w) {int z;\
339 for(z=the_ins.numo;z>opcode->m_codenum;--z)\
340 the_ins.opcode[z]=the_ins.opcode[z-1];\
341 for(z=0;z<the_ins.nrel;z++)\
342 the_ins.reloc[z].n+=2;\
343 the_ins.opcode[opcode->m_codenum]=w;\
348 #define add_exp(beg,end) (\
349 the_ins.exprs[the_ins.nexp].e_beg=beg,\
350 the_ins.exprs[the_ins.nexp].e_end=end,\
351 &the_ins.exprs[the_ins.nexp++]\
355 /* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/
356 #define add_fix(width,exp,pc_rel) {\
357 the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \
358 (((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\
359 the_ins.reloc[the_ins.nrel].add=adds((exp));\
360 the_ins.reloc[the_ins.nrel].sub=subs((exp));\
361 the_ins.reloc[the_ins.nrel].off=offs((exp));\
362 the_ins.reloc[the_ins.nrel].wid=width;\
363 the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\
366 #define add_frag(add,off,type) {\
367 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\
368 the_ins.fragb[the_ins.nfrag].fadd=add;\
369 the_ins.fragb[the_ins.nfrag].foff=off;\
370 the_ins.fragb[the_ins.nfrag++].fragty=type;\
373 #define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
375 #define seg(exp) ((exp)->e_exp.X_seg)
376 #define adds(exp) ((exp)->e_exp.X_add_symbol)
377 #define subs(exp) ((exp)->e_exp.X_subtract_symbol)
378 #define offs(exp) ((exp)->e_exp.X_add_number)
383 unsigned long m_opcode
;
387 struct m68k_incant
*m_next
;
392 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
393 #define gettwo(x) (((x)->m_opcode)&0xffff)
398 static char *crack_operand(char *str
, struct m68k_op
*opP
);
399 static int get_num(struct m68k_exp
*exp
, int ok
);
400 static int get_regs(int i
, char *str
, struct m68k_op
*opP
);
401 static int reverse_16_bits(int in
);
402 static int reverse_8_bits(int in
);
403 static int try_index(char **s
, struct m68k_op
*opP
);
404 static void install_gen_operand(int mode
, int val
);
405 static void install_operand(int mode
, int val
);
406 static void s_bss(void);
407 static void s_data1(void);
408 static void s_data2(void);
409 static void s_even(void);
410 static void s_proc(void);
412 #else /* not __STDC__ */
414 static char *crack_operand();
415 static int get_num();
416 static int get_regs();
417 static int reverse_16_bits();
418 static int reverse_8_bits();
419 static int try_index();
420 static void install_gen_operand();
421 static void install_operand();
423 void s_align_bytes();
424 static void s_data1();
425 static void s_data2();
426 static void s_even();
427 static void s_proc();
429 #endif /* not __STDC__ */
431 static int current_architecture
= 0;
433 /* BCC68000 is for patching in an extra jmp instruction for long offsets
434 on the 68000. The 68000 doesn't support long branches with branchs */
436 /* This table desribes how you change sizes for the various types of variable
437 size expressions. This version only supports two kinds. */
439 /* Note that calls to frag_var need to specify the maximum expansion needed */
440 /* This is currently 10 bytes for DBCC */
443 How far Forward this mode will reach:
444 How far Backward this mode will reach:
445 How many bytes this mode will add to the size of the frag
446 Which mode to go to if the offset won't fit in this one
450 { 1, 1, 0, 0 }, /* First entries aren't used */
451 { 1, 1, 0, 0 }, /* For no good reason except */
452 { 1, 1, 0, 0 }, /* that the VAX doesn't either */
455 { (127), (-128), 0, TAB(ABRANCH
,SHORT
)},
456 { (32767), (-32768), 2, TAB(ABRANCH
,LONG
) },
460 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
461 { (32767), (-32768), 2, TAB(FBRANCH
,LONG
)},
465 { 1, 1, 0, 0 }, /* PCREL doesn't come BYTE */
466 { (32767), (-32768), 2, TAB(PCREL
,LONG
)},
470 { (127), (-128), 0, TAB(BCC68000
,SHORT
)},
471 { (32767), (-32768), 2, TAB(BCC68000
,LONG
) },
472 { 0, 0, 6, 0 }, /* jmp long space */
475 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
476 { (32767), (-32768), 2, TAB(DBCC
,LONG
) },
477 { 0, 0, 10, 0 }, /* bra/jmp long space */
480 { 1, 1, 0, 0 }, /* PCLEA doesn't come BYTE */
481 { 32767, -32768, 2, TAB(PCLEA
,LONG
) },
487 /* These are the machine dependent pseudo-ops. These are included so
488 the assembler can work on the output from the SUN C compiler, which
492 /* This table describes all the machine specific pseudo-ops the assembler
493 has to support. The fields are:
494 pseudo-op name without dot
495 function to call to execute this pseudo-op
496 Integer arg to pass to the function
498 const pseudo_typeS md_pseudo_table
[] = {
499 { "data1", s_data1
, 0 },
500 { "data2", s_data2
, 0 },
502 { "even", s_even
, 0 },
503 { "skip", s_space
, 0 },
504 { "proc", s_proc
, 0 },
506 { "align", s_align_bytes
, 0 },
512 /* The mote pseudo ops are put into the opcode table, since they
513 don't start with a . they look like opcodes to gas.
515 extern void obj_coff_section();
517 const pseudo_typeS mote_pseudo_table
[] =
525 { "ds.l", s_space
,4},
527 { "ds.w", s_space
,2},
528 { "ds.b", s_space
,1},
530 { "xdef", s_globl
, 0},
531 { "align", s_align_ptwo
, 0},
533 { "sect", obj_coff_section
,0},
534 { "section", obj_coff_section
,0},
539 /* #define isbyte(x) ((x)>=-128 && (x)<=127) */
540 /* #define isword(x) ((x)>=-32768 && (x)<=32767) */
542 #define issbyte(x) ((x)>=-128 && (x)<=127)
543 #define isubyte(x) ((x)>=0 && (x)<=255)
544 #define issword(x) ((x)>=-32768 && (x)<=32767)
545 #define isuword(x) ((x)>=0 && (x)<=65535)
547 #define isbyte(x) ((x)>=-128 && (x)<=255)
548 #define isword(x) ((x)>=-32768 && (x)<=65535)
549 #define islong(x) (1)
551 extern char *input_line_pointer
;
558 /* JF these tables here are for speed at the expense of size */
559 /* You can replace them with the #if 0 versions if you really
560 need space and don't mind it running a bit slower */
562 static char mklower_table
[256];
563 #define mklower(c) (mklower_table[(unsigned char)(c)])
564 static char notend_table
[256];
565 static char alt_notend_table
[256];
566 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
567 alt_notend_table[(unsigned char)(s[1])])))
570 #define mklower(c) (isupper(c) ? tolower(c) : c)
574 /* JF modified this to handle cases where the first part of a symbol name
575 looks like a register */
578 * m68k_reg_parse() := if it looks like a register, return it's token &
579 * advance the pointer.
588 #ifdef REGISTER_PREFIX
589 if (*start
== REGISTER_PREFIX
)
593 if (isalpha(*start
) && is_name_beginner(*start
))
600 while (isalpha(c
) || isdigit(c
) || c
== '_')
606 symbolP
= symbol_find(start
);
609 if (symbolP
&& S_GET_SEGMENT(symbolP
) == SEG_REGISTER
)
612 return S_GET_VALUE(symbolP
);
620 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
621 #define SKIP_W() { ss++; if(*ss==' ') ss++;}
623 /* Parse an index specification using Motorola syntax. */
626 try_moto_index(s
,opP
)
636 i
=m68k_reg_parse(&ss
);
637 if(!(i
>=DATA
+0 && i
<=ADDR
+7)) { /* if i is not DATA or ADDR reg */
638 opP
->error
="Invalid index register";
652 opP
->error
="Missing . in index register";
657 if(mklower(*ss
)=='w') opP
->isiz
=2;
658 else if(mklower(*ss
)=='l') opP
->isiz
=3;
660 opP
->error
="Size spec not .W or .L";
665 if(*ss
=='.' || *ss
=='*') {
675 opP
->error
="index multiplier not 1, 2, 4 or 8";
682 opP
->error
="Missing )";
693 * try_index := data_or_address_register + ')' + SKIP_W
694 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
696 * multiplier := <empty>
697 * | ':' + multiplier_number
700 * multiplier_number := '1' | '2' | '4' | '8' ;
702 * size_spec := 'l' | 'L' | 'w' | 'W' ;
704 * SKIP_W := <empty> | ' ' ;
708 static int try_index(s
,opP
)
717 i
=m68k_reg_parse(&ss
);
718 if(!(i
>=DATA
+0 && i
<=ADDR
+7)) { /* if i is not DATA or ADDR reg */
732 opP
->error
="Missing : in index register";
747 opP
->error
="Index register size spec not :w or :l";
759 if (cpu_of_arch(current_architecture
) < m68020
) {
760 opP
->error
="no index scaling in pre-68020's";
767 opP
->error
="index multiplier not 1, 2, 4 or 8";
774 opP
->error
="Missing )";
783 /* Ian Taylor expanded this function to accept both MIT and Motorola
784 syntax. I removed the old comment, since it was wrong. The syntax
785 this accepted even before my changes was complex and undocumented.
786 I mainly added a large case when the operand string does not
787 contain an '@', since the Motorola syntax does not use the '@'
793 register struct m68k_op
*opP
;
802 } /* Find the beginning of the string */
805 opP
->error
="Missing operand";
809 for(strend
= str
; *strend
; strend
++)
815 opP
->con1
=add_exp(str
,strend
);
818 } /* Guess what: A constant. Shar and enjoy */
820 i
= m68k_reg_parse(&str
);
823 if(*str
=='/' || *str
=='-') {
824 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
826 return get_regs(i
,str
,opP
);
830 /* "Rn" Register Direct mode */
831 if(i
>=DATA
+0 && i
<=DATA
+7)
833 else if(i
>=ADDR
+0 && i
<=ADDR
+7)
844 if ((stmp
=strchr(str
,'@')) != 0) {
845 opP
->con1
=add_exp(str
,stmp
-1);
851 if ((current_architecture
& m68020up
) == 0) {
853 } /* if target is not a '20 or better */
856 if(*stmp
++!='(' || *strend
--!=')') {
857 opP
->error
="Malformed operand";
860 i
=try_index(&stmp
,opP
);
861 opP
->con2
=add_exp(stmp
,strend
);
869 } /* if there's an '@' */
871 #ifndef MIT_SYNTAX_ONLY
872 /* The operand has no '@'. Try to parse it using
874 /* Logic of the parsing switch(*str):
878 REG AREG or DREG or MSCR 3 or 2 or 13
879 REG- or REG/ REGLST 14
884 (EXPR,REG,INDX) AINDX 8
887 EXP2(REG,INDX) AINDX 8
890 REG means truth(m68k_reg_parse(&str))
891 INDX means truth(try_moto_index(&str,opP))
893 EXP2 means not REG and not '(' and not '-('
898 i
=m68k_reg_parse(&str
);
899 if((i
<ADDR
+0 || i
>ADDR
+7)
900 && (i
<DATA
+0 || i
>DATA
+7
901 || *str
!= ')' || str
[1] != '0')
902 && i
!=PC
&& i
!=ZPC
&& i
!=FAIL
) {
903 /* Can't indirect off non address regs */
904 opP
->error
="Invalid indirect register";
912 /* "(An)" Address Register Indirect mode
913 or "(Dn)" for cas2. */
914 if (i
>=DATA
+0 && i
<=DATA
+7)
922 /* "(An)+" Register Indirect w Postincrement */
927 opP
->error
="Junk after indirect";
932 i
=try_moto_index(&str
,opP
);
933 if(i
==FAIL
) return FAIL
;
934 /* "(An,Rn)" Register Indirect with Index mode*/
939 opP
->error
="Bad indirect syntax";
944 /* "(EXPR,..." , a displacement */
948 if(stmp
=index(str
,',')) {
949 opP
->con1
=add_exp(str
,stmp
-1);
952 i
=m68k_reg_parse(&str
);
953 if((i
<ADDR
+0 || i
>ADDR
+7) && i
!=PC
&& i
!=ZPC
) {
954 /* Can't indirect off non address regs */
955 opP
->error
="Invalid indirect register";
961 /* "(d,An)" Register Indirect w Displacement */
967 i
=try_moto_index(&str
,opP
);
968 if(i
==FAIL
) return FAIL
;
969 /* "(d,An,Rn)" Register Indirect with Index */
974 opP
->error
="Bad indirect syntax";
979 opP
->error
="Invalid register";
985 opP
->con1
= add_exp(str
-1,strend
);
994 i
=m68k_reg_parse(&str
);
995 if((i
<ADDR
+0 || i
>ADDR
+7) && i
!=PC
&& i
!=ZPC
&& i
!=FAIL
) {
996 /* Can't indirect off non address regs */
997 opP
->error
="Invalid indirect register";
1005 /* "-(An)" Register Indirect with Predecrement */
1009 opP
->error
="Junk after indirect";
1012 opP
->error
="Bad indirect syntax";
1016 opP
->con1
= add_exp(str
-2,strend
);
1019 /* if '-' but not "-(', do nothing */
1022 /* whether *str=='-' or not */
1024 /* "EXP2" or "EXP2(REG..." */
1027 if(stmp
=index(str
,'(')) {
1030 opP
->con1
=add_exp(str
,stmp
-1);
1032 i
=m68k_reg_parse(&str
);
1033 if((i
<ADDR
+0 || i
>ADDR
+7) && i
!=PC
1034 && i
!=ZPC
&& i
!=FAIL
) {
1035 /* Can't indirect off non address regs */
1036 opP
->error
="Invalid indirect register";
1042 /* "d(An)" Register Indirect w Displacement */
1048 i
=try_moto_index(&str
,opP
);
1049 if(i
==FAIL
) return FAIL
;
1050 /* "d(An,Rn)" Register Indirect with Index */
1055 opP
->error
="Bad indirect syntax";
1061 opP
->con1
= add_exp(ostr
,strend
);
1066 /* "EXP2" Absolute */
1069 if(strend
[-1]=='.' || strend
[-1]==':') {
1070 /* mode ==foo.[wl] */
1084 opP
->con1
=add_exp(str
,strend
);
1089 #else /* defined (MIT_SYNTAX_ONLY) */
1091 opP
->con1
=add_exp(str
,strend
);
1093 #endif /* defined (MIT_SYNTAX_ONLY) */
1098 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1099 if((i
<ADDR
+0 || i
>ADDR
+7) && i
!=PC
&& i
!=ZPC
&& i
!=FAIL
1100 && (str
[1] != '\0' || i
<DATA
+0 || i
>DATA
+7)) {
1101 opP
->error
="Invalid indirect register";
1109 if (i
<DATA
+0 || i
>DATA
+7)
1124 opP
->error
="Junk after indirect";
1127 /* Some kind of indexing involved. Lets find out how bad it is */
1128 i
=try_index(&str
,opP
);
1129 /* Didn't start with an index reg, maybe its offset or offset,reg */
1137 opP
->error
="Missing )";
1139 case ',': i
=0; break;
1140 case '(': i
++; break;
1141 case ')': --i
; break;
1144 /* if(str[-3]==':') {
1161 opP->error="Specified size isn't :w or :l";
1164 opP->con1=add_exp(beg_str,str-4);
1165 opP->con1->e_siz=siz;
1167 opP
->con1
=add_exp(beg_str
,str
-2);
1168 /* Should be offset,reg */
1170 i
=try_index(&str
,opP
);
1172 opP
->error
="Malformed index reg";
1177 /* We've now got offset) offset,reg) or reg) */
1180 /* Th-the-thats all folks */
1181 if (opP
->reg
== FAIL
) opP
->mode
= AINDX
; /* Other form of indirect */
1182 else if(opP
->ireg
== FAIL
) opP
->mode
= AOFF
;
1183 else opP
->mode
= AINDX
;
1186 /* Next thing had better be another @ */
1188 if (str
[1] == '(') {
1198 if ((current_architecture
& m68020up
) == 0) {
1200 } /* if target is not a '20 or better */
1203 if(opP
->ireg
!= FAIL
) {
1206 i
= try_index(&str
, opP
);
1208 opP
->error
= "Two index registers! not allowed!";
1212 i
= try_index(&str
, opP
);
1224 opP
->error
="Missing )";
1227 case ',': i
=0; break;
1228 case '(': i
++; break;
1229 case ')': --i
; break;
1233 opP
->con2
=add_exp(beg_str
,str
-2);
1235 if (str
[-1] == ',') {
1236 if (opP
->ireg
!= FAIL
) {
1237 opP
->error
= "Can't have two index regs";
1241 i
= try_index(&str
, opP
);
1244 opP
->error
= "malformed index reg";
1249 } else if (opP
->ireg
!= FAIL
) {
1259 opP
->error
="Junk after indirect";
1263 } /* m68k_ip_op() */
1268 short tc_coff_fix2rtype(fixP
)
1271 return (fixP
->fx_pcrel
?
1272 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
1273 fixP
->fx_size
== 2 ? R_PCRWORD
:
1275 (fixP
->fx_size
== 1 ? R_RELBYTE
:
1276 fixP
->fx_size
== 2 ? R_RELWORD
:
1284 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1288 struct m68k_op thark
;
1293 memset(&thark
, '\0', sizeof(thark
));
1294 if(!m68k_ip_op(buf
,&thark
)) printf("FAIL:");
1296 printf("op1 error %s in %s\n",thark
.error
,buf
);
1297 printf("mode %d, reg %d, ",thark
.mode
,thark
.reg
);
1299 printf("Constant: '%.*s',",1+thark
.e_const
-thark
.b_const
,thark
.b_const
);
1300 printf("ireg %d, isiz %d, imul %d ",thark
.ireg
,thark
.isiz
,thark
.imul
);
1302 printf("Iadd: '%.*s'",1+thark
.e_iadd
-thark
.b_iadd
,thark
.b_iadd
);
1311 static struct hash_control
* op_hash
= NULL
; /* handle of the OPCODE hash table
1312 NULL means any use before m68k_ip_begin()
1319 * This converts a string into a 68k instruction.
1320 * The string must be a bare single instruction in sun format
1321 * with RMS-style 68020 indirects
1324 * It provides some error messages: at most one fatal error message (which
1325 * stops the scan) and at most one warning message for each operand.
1326 * The 68k instruction is returned in exploded form, since we have no
1327 * knowledge of how you parse (or evaluate) your expressions.
1328 * We do however strip off and decode addressing modes and operation
1331 * This function's value is a string. If it is not "" then an internal
1332 * logic error was found: read this code to assign meaning to the string.
1333 * No argument string should generate such an error string:
1334 * it means a bug in our code, not in the user's text.
1336 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1340 /* JF this function no longer returns a useful value. Sorry */
1341 void m68k_ip (instring
)
1345 register struct m68k_op
*opP
;
1346 register struct m68k_incant
*opcode
;
1348 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1349 char *pdot
, *pdotmove
;
1354 char *crack_operand();
1355 LITTLENUM_TYPE words
[6];
1356 LITTLENUM_TYPE
*wordp
;
1357 unsigned long ok_arch
= 0;
1359 if (*instring
== ' ')
1360 instring
++; /* skip leading whitespace */
1362 /* Scan up to end of operation-code, which MUST end in end-of-string
1363 or exactly 1 space. */
1365 for (p
= instring
; *p
!= '\0'; p
++) {
1372 if (p
== instring
) {
1373 the_ins
.error
= "No operator";
1374 the_ins
.opcode
[0] = NULL
;
1375 /* the_ins.numo=1; */
1379 /* p now points to the end of the opcode name, probably whitespace.
1380 make sure the name is null terminated by clobbering the whitespace,
1381 look it up in the hash table, then fix it back.
1382 Remove a dot, first, since the opcode tables have none. */
1384 for (pdotmove
=pdot
; pdotmove
<p
; pdotmove
++)
1385 *pdotmove
=pdotmove
[1];
1391 opcode
= (struct m68k_incant
*)hash_find (op_hash
, instring
);
1395 for (pdotmove
=p
; pdotmove
>pdot
; pdotmove
--)
1396 *pdotmove
=pdotmove
[-1];
1401 if (opcode
== NULL
) {
1402 the_ins
.error
= "Unknown operator";
1403 the_ins
.opcode
[0] = NULL
;
1404 /* the_ins.numo=1; */
1408 /* found a legitimate opcode, start matching operands */
1409 while (*p
== ' ') ++p
;
1412 if (opcode
->m_operands
== 0) {
1413 char *old
= input_line_pointer
;
1415 input_line_pointer
= p
;
1416 /* Ahh - it's a motorola style psuedo op */
1417 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1418 ( mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1419 input_line_pointer
= old
;
1425 for(opP
= &the_ins
.operands
[0]; *p
; opP
++) {
1427 p
= crack_operand(p
, opP
);
1430 the_ins
.error
=opP
->error
;
1435 opsfound
= opP
- &the_ins
.operands
[0];
1437 /* This ugly hack is to support the floating pt opcodes in their standard form */
1438 /* Essentially, we fake a first enty of type COP#1 */
1439 if (opcode
->m_operands
[0]=='I') {
1442 for(n
=opsfound
;n
>0;--n
)
1443 the_ins
.operands
[n
]=the_ins
.operands
[n
-1];
1445 memset((char *)(&the_ins
.operands
[0]), '\0', sizeof(the_ins
.operands
[0]));
1446 the_ins
.operands
[0].mode
=MSCR
;
1447 the_ins
.operands
[0].reg
=COPNUM
; /* COP #1 */
1451 /* We've got the operands. Find an opcode that'll accept them */
1452 for (losing
= 0; ; ) {
1453 /* if we didn't get the right number of ops,
1454 or we have no common model with this pattern
1455 then reject this pattern. */
1457 if (opsfound
!= opcode
->m_opnum
1458 || ((opcode
->m_arch
& current_architecture
) == 0))
1461 ok_arch
|= opcode
->m_arch
;
1464 for (s
=opcode
->m_operands
, opP
= &the_ins
.operands
[0]; *s
&& !losing
; s
+= 2, opP
++) {
1465 /* Warning: this switch is huge! */
1466 /* I've tried to organize the cases into this order:
1467 non-alpha first, then alpha by letter. lower-case goes directly
1468 before uppercase counterpart. */
1469 /* Code with multiple case ...: gets sorted by the lowest case ...
1470 it belongs to. I hope this makes sense. */
1473 if (opP
->mode
== MSCR
|| opP
->mode
== IMMED
1474 || opP
->mode
== DREG
|| opP
->mode
== AREG
1475 || opP
->mode
== AINC
|| opP
->mode
== ADEC
1476 || opP
->mode
== REGLST
)
1481 switch (opP
->mode
) {
1482 case MSCR
: case IMMED
: case DREG
: case AREG
:
1483 case AINC
: case REGLST
: case AINDR
:
1489 if(opP
->mode
!=IMMED
)
1494 t
=get_num(opP
->con1
,80);
1495 if(s
[1]=='b' && !isbyte(t
))
1497 else if(s
[1]=='w' && !isword(t
))
1504 if(opP
->mode
!=IMMED
)
1509 if(opP
->mode
==MSCR
|| opP
->mode
==AREG
||
1510 opP
->mode
==IMMED
|| opP
->reg
==PC
|| opP
->reg
==ZPC
|| opP
->mode
==REGLST
)
1515 if(opP
->mode
==MSCR
|| opP
->reg
==PC
||
1516 opP
->reg
==ZPC
|| opP
->mode
==REGLST
)
1522 if(opP
->mode
==MSCR
|| opP
->mode
==DREG
||
1523 opP
->mode
==AREG
|| opP
->mode
==IMMED
|| opP
->reg
==PC
|| opP
->reg
==ZPC
||
1524 opP
->mode
==AINC
|| opP
->mode
==ADEC
|| opP
->mode
==REGLST
)
1529 if(opP
->mode
==MSCR
|| opP
->mode
==REGLST
)
1544 if(opP
->mode
==MSCR
|| opP
->mode
==AREG
||
1545 opP
->mode
==AINC
|| opP
->mode
==ADEC
|| opP
->mode
==IMMED
|| opP
->mode
==REGLST
)
1550 if(opP
->mode
==MSCR
|| opP
->mode
==AREG
|| opP
->mode
==REGLST
)
1555 if(opP
->mode
==MSCR
|| opP
->mode
==AREG
||
1556 opP
->mode
==AINC
|| opP
->mode
==ADEC
|| opP
->mode
==IMMED
|| opP
->reg
==PC
||
1557 opP
->reg
==ZPC
|| opP
->mode
==REGLST
)
1562 if(opP
->mode
==MSCR
|| opP
->mode
==AREG
||
1563 opP
->mode
==IMMED
|| opP
->mode
==REGLST
)
1567 case '~': /* For now! (JF FOO is this right?) */
1568 if(opP
->mode
==MSCR
|| opP
->mode
==DREG
||
1569 opP
->mode
==AREG
|| opP
->mode
==IMMED
|| opP
->reg
==PC
|| opP
->reg
==ZPC
|| opP
->mode
==REGLST
)
1574 if (opP
->mode
!= MSCR
|| (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1583 if (opP
->mode
!= AINDR
) {
1585 } /* if not address register indirect */
1588 if(opP
->mode
!=ABSL
|| (flagseen
['S'] && instring
[0] == 'j'
1589 && instring
[1] == 'b'
1590 && instring
[2] == 's'
1591 && instring
[3] == 'r'))
1596 if(opP
->mode
!=MSCR
|| opP
->reg
!=CCR
)
1600 case 'd': /* FOO This mode is a KLUDGE!! */
1601 if(opP
->mode
!=AOFF
&& (opP
->mode
!=ABSL
||
1602 opP
->con1
->e_beg
[0]!='(' || opP
->con1
->e_end
[0]!=')'))
1612 if(opP
->mode
!=MSCR
|| opP
->reg
<(FPREG
+0) || opP
->reg
>(FPREG
+7))
1617 if(opP
->mode
!=MSCR
|| opP
->reg
<COPNUM
||
1623 if (opP
->mode
!= MSCR
1626 || cpu_of_arch(current_architecture
) < m68010
/* before 68010 had none */
1627 || (cpu_of_arch(current_architecture
) < m68020
1631 && opP
->reg
!= VBR
) /* 68010's had only these */
1632 || (cpu_of_arch(current_architecture
) < m68040
1640 && opP
->reg
!= ISP
) /* 680[23]0's have only these */
1641 || (cpu_of_arch(current_architecture
) == m68040
/* 68040 has all but this */
1642 && opP
->reg
== CAAR
)) {
1644 } /* doesn't cut it */
1648 if(opP
->mode
!=IMMED
)
1654 if(opP
->mode
==DREG
|| opP
->mode
==AREG
|| opP
->mode
==FPREG
) {
1659 opP
->reg
=1<<(opP
->reg
-DATA
);
1661 } else if(opP
->mode
!=REGLST
) {
1663 } else if(s
[1]=='8' && opP
->reg
&0x0FFffFF)
1665 else if(s
[1]=='3' && opP
->reg
&0x7000000)
1670 if(opP
->mode
!=IMMED
)
1675 t
=get_num(opP
->con1
,80);
1676 if(!issbyte(t
) || isvar(opP
->con1
))
1682 if(opP
->mode
!=DREG
&& opP
->mode
!=IMMED
)
1687 if(opP
->mode
!=IMMED
)
1692 t
=get_num(opP
->con1
,80);
1693 if(t
<1 || t
>8 || isvar(opP
->con1
))
1699 if(opP
->mode
!=DREG
&& opP
->mode
!=AREG
)
1704 if (opP
->mode
!=AINDR
&& opP
->mode
!=DINDR
)
1709 if(opP
->mode
!=MSCR
|| !(opP
->reg
==FPI
|| opP
->reg
==FPS
|| opP
->reg
==FPC
))
1714 if(opP
->mode
!=MSCR
|| opP
->reg
!=SR
)
1719 if (opP
->mode
!= IMMED
)
1723 long t
= get_num (opP
->con1
, 80);
1724 if (t
< 0 || t
> 7 || isvar (opP
->con1
))
1730 if(opP
->mode
!=MSCR
|| opP
->reg
!=USP
)
1734 /* JF these are out of order. We could put them
1735 in order if we were willing to put up with
1736 bunches of #ifdef m68851s in the code.
1738 Don't forget that you need these operands
1739 to use 68030 MMU instructions. */
1741 /* Memory addressing mode used by pflushr */
1743 if(opP
->mode
==MSCR
|| opP
->mode
==DREG
||
1744 opP
->mode
==AREG
|| opP
->mode
==REGLST
)
1749 if (opP
->mode
!= MSCR
|| (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1754 if (opP
->mode
!= MSCR
1755 || (opP
->reg
!= TC
&& opP
->reg
!= CAL
1756 && opP
->reg
!= VAL
&& opP
->reg
!= SCC
&& opP
->reg
!= AC
))
1761 if (opP
->reg
!= VAL
)
1766 if (opP
->mode
!= MSCR
1767 || (opP
->reg
!= DRP
&& opP
->reg
!= SRP
1768 && opP
->reg
!= CRP
))
1773 if (opP
->mode
!= MSCR
||
1774 (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+7) &&
1775 !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+7)))
1780 if (opP
->reg
!= PSR
)
1785 if (opP
->reg
!= PCSR
)
1793 && opP
->reg
!= BC
) {
1795 } /* not a cache specifier. */
1799 if (opP
->mode
!= ABSL
) {
1801 } /* not absolute */
1805 as_fatal("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
1806 *s
, __LINE__
, __FILE__
);
1807 } /* switch on type of operand */
1811 } /* for each operand */
1812 } /* if immediately wrong */
1818 opcode
= opcode
->m_next
;
1822 && !(ok_arch
& current_architecture
))
1826 strcpy (buf
, "invalid instruction for this architecture; needs ");
1827 cp
= buf
+ strlen (buf
);
1831 strcpy (cp
, "fpu (68040 or 68881/68882)");
1834 strcpy (cp
, "mmu (68030 or 68851)");
1837 strcpy (cp
, "68020 or higher");
1840 strcpy (cp
, "68000 or higher");
1843 strcpy (cp
, "68010 or higher");
1847 int got_one
= 0, idx
;
1848 const static struct {
1861 for (idx
= 0; idx
< sizeof (archs
)/sizeof (archs
[0]); idx
++)
1863 if (archs
[idx
].arch
& ok_arch
)
1867 strcpy (cp
, " or ");
1871 strcpy (cp
, archs
[idx
].name
);
1883 the_ins
.error
= "operands mismatch";
1885 } /* Fell off the end */
1890 /* now assemble it */
1892 the_ins
.args
=opcode
->m_operands
;
1893 the_ins
.numargs
=opcode
->m_opnum
;
1894 the_ins
.numo
=opcode
->m_codenum
;
1895 the_ins
.opcode
[0]=getone(opcode
);
1896 the_ins
.opcode
[1]=gettwo(opcode
);
1898 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++) {
1899 /* This switch is a doozy.
1900 Watch the first step; its a big one! */
1919 tmpreg
=0x3c; /* 7.4 */
1920 if (strchr("bwl",s
[1])) nextword
=get_num(opP
->con1
,80);
1921 else nextword
=nextword
=get_num(opP
->con1
,0);
1922 if(isvar(opP
->con1
))
1923 add_fix(s
[1],opP
->con1
,0);
1926 if(!isbyte(nextword
))
1927 opP
->error
="operand out of range";
1932 if(!isword(nextword
))
1933 opP
->error
="operand out of range";
1938 addword(nextword
>>16);
1960 as_fatal("Internal error: Can't decode %c%c in line %s of file \"%s\"",
1961 *s
, s
[1], __LINE__
, __FILE__
);
1966 /* We gotta put out some float */
1967 if(seg(opP
->con1
)!=SEG_BIG
) {
1968 int_to_gen(nextword
);
1969 gen_to_words(words
,baseo
,(long int)outro
);
1970 for(wordp
=words
;baseo
--;wordp
++)
1974 if(offs(opP
->con1
)>0) {
1975 if(offs(opP
->con1
)>baseo
) {
1976 as_warn("Bignum too big for %c format; truncated",s
[1]);
1977 offs(opP
->con1
)=baseo
;
1979 baseo
-=offs(opP
->con1
);
1980 for(wordp
=generic_bignum
+offs(opP
->con1
)-1;offs(opP
->con1
)--;--wordp
)
1986 gen_to_words(words
,baseo
,(long)outro
);
1987 for (wordp
=words
;baseo
--;wordp
++)
1991 tmpreg
=opP
->reg
-DATA
; /* 0.dreg */
1994 tmpreg
=0x08+opP
->reg
-ADDR
; /* 1.areg */
1997 tmpreg
=0x10+opP
->reg
-ADDR
; /* 2.areg */
2000 tmpreg
=0x20+opP
->reg
-ADDR
; /* 4.areg */
2003 tmpreg
=0x18+opP
->reg
-ADDR
; /* 3.areg */
2007 nextword
=get_num(opP
->con1
,80);
2008 /* Force into index mode. Hope this works */
2010 /* We do the first bit for 32-bit displacements,
2011 and the second bit for 16 bit ones. It is
2012 possible that we should make the default be
2013 WORD instead of LONG, but I think that'd
2014 break GCC, so we put up with a little
2015 inefficiency for the sake of working output.
2018 if( !issword(nextword
)
2019 || ( isvar(opP
->con1
)
2020 && ( ( opP
->con1
->e_siz
==0
2021 && flagseen
['l']==0)
2022 || opP
->con1
->e_siz
==3))) {
2025 tmpreg
=0x3B; /* 7.3 */
2027 tmpreg
=0x30+opP
->reg
-ADDR
; /* 6.areg */
2028 if(isvar(opP
->con1
)) {
2030 add_frag(adds(opP
->con1
),
2032 TAB(PCLEA
,SZ_UNDEF
));
2036 add_fix('l',opP
->con1
,0);
2040 addword(nextword
>>16);
2043 tmpreg
=0x3A; /* 7.2 */
2045 tmpreg
=0x28+opP
->reg
-ADDR
; /* 5.areg */
2047 if(isvar(opP
->con1
)) {
2049 add_fix('w',opP
->con1
,1);
2051 add_fix('w',opP
->con1
,0);
2060 know(current_architecture
& m68020up
);
2061 /* intentional fall-through */
2064 baseo
=get_num(opP
->con1
,80);
2065 outro
=get_num(opP
->con2
,80);
2066 /* Figure out the 'addressing mode' */
2067 /* Also turn on the BASE_DISABLE bit, if needed */
2068 if(opP
->reg
==PC
|| opP
->reg
==ZPC
) {
2069 tmpreg
=0x3b; /* 7.3 */
2072 } else if(opP
->reg
==FAIL
) {
2074 tmpreg
=0x30; /* 6.garbage */
2075 } else tmpreg
=0x30+opP
->reg
-ADDR
; /* 6.areg */
2077 siz1
= (opP
->con1
) ? opP
->con1
->e_siz
: 0;
2078 siz2
= (opP
->con2
) ? opP
->con2
->e_siz
: 0;
2080 /* Index register stuff */
2081 if(opP
->ireg
>=DATA
+0 && opP
->ireg
<=ADDR
+7) {
2082 nextword
|=(opP
->ireg
-DATA
)<<12;
2084 if(opP
->isiz
==0 || opP
->isiz
==3)
2088 case 2: nextword
|=0x200; break;
2089 case 4: nextword
|=0x400; break;
2090 case 8: nextword
|=0x600; break;
2091 default: as_fatal("failed sanity check.");
2094 GET US OUT OF HERE! */
2096 /* Must be INDEX, with an index
2097 register. Address register
2098 cannot be ZERO-PC, and either
2099 :b was forced, or we know
2101 if( opP
->mode
==AINDX
2106 && !isvar(opP
->con1
)))) {
2107 nextword
+=baseo
&0xff;
2109 if(isvar(opP
->con1
))
2110 add_fix('B',opP
->con1
,0);
2114 nextword
|=0x40; /* No index reg */
2116 /* It aint simple */
2118 /* If the guy specified a width, we assume that
2119 it is wide enough. Maybe it isn't. If so, we lose
2123 if(isvar(opP
->con1
) || !issword(baseo
)) {
2134 as_warn("Byte dispacement won't work. Defaulting to :w");
2143 /* Figure out innner displacement stuff */
2144 if(opP
->mode
!=AINDX
) {
2147 if(isvar(opP
->con2
) || !issword(outro
)) {
2158 as_warn("Byte dispacement won't work. Defaulting to :w");
2166 if(opP
->mode
==APODX
) nextword
|=0x04;
2167 else if(opP
->mode
==AMIND
) nextword
|=0x40;
2171 if(isvar(opP
->con1
)) {
2172 if(opP
->reg
==PC
|| opP
->reg
==ZPC
) {
2173 add_fix(siz1
==3 ? 'l' : 'w',opP
->con1
,1);
2174 opP
->con1
->e_exp
.X_add_number
+=6;
2176 add_fix(siz1
==3 ? 'l' : 'w',opP
->con1
,0);
2183 if(isvar(opP
->con2
)) {
2184 if(opP
->reg
==PC
|| opP
->reg
==ZPC
) {
2185 add_fix(siz2
==3 ? 'l' : 'w',opP
->con2
,1);
2186 opP
->con1
->e_exp
.X_add_number
+=6;
2188 add_fix(siz2
==3 ? 'l' : 'w',opP
->con2
,0);
2198 nextword
=get_num(opP
->con1
,80);
2199 switch(opP
->con1
->e_siz
) {
2201 as_warn("Unknown size for absolute reference");
2203 if(!isvar(opP
->con1
) && issword(offs(opP
->con1
))) {
2204 tmpreg
=0x38; /* 7.0 */
2208 /* Don't generate pc relative code
2209 on 68010 and 68000 */
2212 && seg(opP
->con1
) == SEG_TEXT
2213 && now_seg
== SEG_TEXT
2214 && cpu_of_arch(current_architecture
) >= m68020
2216 && !strchr("~%&$?", s
[0])) {
2217 tmpreg
=0x3A; /* 7.2 */
2218 add_frag(adds(opP
->con1
),
2220 TAB(PCREL
,SZ_UNDEF
));
2223 case 3: /* Fall through into long */
2224 if(isvar(opP
->con1
))
2225 add_fix('l',opP
->con1
,0);
2227 tmpreg
=0x39; /* 7.1 mode */
2228 addword(nextword
>>16);
2233 if(isvar(opP
->con1
))
2234 add_fix('w',opP
->con1
,0);
2236 tmpreg
=0x38; /* 7.0 mode */
2242 as_bad("invalid indirect register");
2246 as_bad("unknown/incorrect operand");
2249 install_gen_operand(s
[1],tmpreg
);
2254 switch(s
[1]) { /* JF: I hate floating point! */
2269 tmpreg
=get_num(opP
->con1
,tmpreg
);
2270 if(isvar(opP
->con1
))
2271 add_fix(s
[1],opP
->con1
,0);
2273 case 'b': /* Danger: These do no check for
2274 certain types of overflow.
2277 opP
->error
="out of range";
2279 if(isvar(opP
->con1
))
2280 the_ins
.reloc
[the_ins
.nrel
-1].n
=(opcode
->m_codenum
)*2;
2284 opP
->error
="out of range";
2286 if(isvar(opP
->con1
))
2287 the_ins
.reloc
[the_ins
.nrel
-1].n
=(opcode
->m_codenum
)*2;
2290 insop(tmpreg
); /* Because of the way insop works, we put these two out backwards */
2292 if(isvar(opP
->con1
))
2293 the_ins
.reloc
[the_ins
.nrel
-1].n
=(opcode
->m_codenum
)*2;
2299 install_operand(s
[1],tmpreg
);
2302 as_fatal("Internal error: Unknown mode #%c in line %s of file \"%s\"", s
[1], __LINE__
, __FILE__
);
2310 install_operand(s
[1],opP
->reg
-ADDR
);
2314 tmpreg
=get_num(opP
->con1
,80);
2317 /* Needs no offsetting */
2318 add_fix('B',opP
->con1
,1);
2321 /* Offset the displacement to be relative to byte disp location */
2322 opP
->con1
->e_exp
.X_add_number
+=2;
2323 add_fix('w',opP
->con1
,1);
2328 if (cpu_of_arch(current_architecture
) < m68020
) /* 68000 or 010 */
2329 as_warn("Can't use long branches on 68000/68010");
2330 the_ins
.opcode
[the_ins
.numo
-1]|=0xff;
2331 /* Offset the displacement to be relative to byte disp location */
2332 opP
->con1
->e_exp
.X_add_number
+=4;
2333 add_fix('l',opP
->con1
,1);
2338 if(subs(opP
->con1
)) /* We can't relax it */
2341 /* This could either be a symbol, or an
2342 absolute address. No matter, the
2343 frag hacking will finger it out.
2344 Not quite: it can't switch from
2345 BRANCH to BCC68000 for the case
2346 where opnd is absolute (it needs
2347 to use the 68000 hack since no
2348 conditional abs jumps). */
2349 if (((cpu_of_arch(current_architecture
) < m68020
) || (0==adds(opP
->con1
)))
2350 && (the_ins
.opcode
[0] >= 0x6200)
2351 && (the_ins
.opcode
[0] <= 0x6f00)) {
2352 add_frag(adds(opP
->con1
),offs(opP
->con1
),TAB(BCC68000
,SZ_UNDEF
));
2354 add_frag(adds(opP
->con1
),offs(opP
->con1
),TAB(ABRANCH
,SZ_UNDEF
));
2358 if(isvar(opP
->con1
)) {
2359 /* check for DBcc instruction */
2360 if ((the_ins
.opcode
[0] & 0xf0f8) ==0x50c8) {
2361 /* size varies if patch */
2362 /* needed for long form */
2363 add_frag(adds(opP
->con1
),offs(opP
->con1
),TAB(DBCC
,SZ_UNDEF
));
2368 opP
->con1
->e_exp
.X_add_number
+=2;
2369 add_fix('w',opP
->con1
,1);
2373 case 'C': /* Fixed size LONG coproc branches */
2374 the_ins
.opcode
[the_ins
.numo
-1]|=0x40;
2375 /* Offset the displacement to be relative to byte disp location */
2376 /* Coproc branches don't have a byte disp option, but they are
2377 compatible with the ordinary branches, which do... */
2378 opP
->con1
->e_exp
.X_add_number
+=4;
2379 add_fix('l',opP
->con1
,1);
2383 case 'c': /* Var size Coprocesssor branches */
2384 if(subs(opP
->con1
)) {
2385 add_fix('l',opP
->con1
,1);
2386 add_frag((symbolS
*)0,(long)0,TAB(FBRANCH
,LONG
));
2387 } else if(adds(opP
->con1
)) {
2388 add_frag(adds(opP
->con1
),offs(opP
->con1
),TAB(FBRANCH
,SZ_UNDEF
));
2390 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2391 the_ins
.opcode
[the_ins
.numo
-1]|=0x40;
2392 add_fix('l',opP
->con1
,1);
2398 as_fatal("Internal error: operand type B%c unknown in line %s of file \"%s\"",
2399 s
[1], __LINE__
, __FILE__
);
2403 case 'C': /* Ignore it */
2406 case 'd': /* JF this is a kludge */
2407 if(opP
->mode
==AOFF
) {
2408 install_operand('s',opP
->reg
-ADDR
);
2412 tmpP
=opP
->con1
->e_end
-2;
2414 opP
->con1
->e_end
-=4; /* point to the , */
2415 baseo
=m68k_reg_parse(&tmpP
);
2416 if(baseo
<ADDR
+0 || baseo
>ADDR
+7) {
2417 as_bad("Unknown address reg, using A0");
2420 install_operand('s',baseo
);
2422 tmpreg
=get_num(opP
->con1
,80);
2423 if(!issword(tmpreg
)) {
2424 as_warn("Expression out of range, using 0");
2431 install_operand(s
[1],opP
->reg
-DATA
);
2435 install_operand(s
[1],opP
->reg
-FPREG
);
2439 tmpreg
=1+opP
->reg
-COPNUM
;
2442 install_operand(s
[1],tmpreg
);
2445 case 'J': /* JF foo */
2447 case SFC
: tmpreg
=0x000; break;
2448 case DFC
: tmpreg
=0x001; break;
2449 case CACR
: tmpreg
=0x002; break;
2450 case TC
: tmpreg
=0x003; break;
2451 case ITT0
: tmpreg
=0x004; break;
2452 case ITT1
: tmpreg
=0x005; break;
2453 case DTT0
: tmpreg
=0x006; break;
2454 case DTT1
: tmpreg
=0x007; break;
2456 case USP
: tmpreg
=0x800; break;
2457 case VBR
: tmpreg
=0x801; break;
2458 case CAAR
: tmpreg
=0x802; break;
2459 case MSP
: tmpreg
=0x803; break;
2460 case ISP
: tmpreg
=0x804; break;
2461 case MMUSR
: tmpreg
=0x805; break;
2462 case URP
: tmpreg
=0x806; break;
2463 case SRP
: tmpreg
=0x807; break;
2465 as_fatal("failed sanity check.");
2467 install_operand(s
[1],tmpreg
);
2471 tmpreg
=get_num(opP
->con1
,55);
2472 install_operand(s
[1],tmpreg
&0x7f);
2478 if(tmpreg
&0x7FF0000)
2479 as_bad("Floating point register in register list");
2480 insop(reverse_16_bits(tmpreg
));
2482 if(tmpreg
&0x700FFFF)
2483 as_bad("Wrong register in floating-point reglist");
2484 install_operand(s
[1],reverse_8_bits(tmpreg
>>16));
2491 if(tmpreg
&0x7FF0000)
2492 as_bad("Floating point register in register list");
2494 } else if(s
[1]=='8') {
2495 if(tmpreg
&0x0FFFFFF)
2496 as_bad("incorrect register in reglist");
2497 install_operand(s
[1],tmpreg
>>24);
2499 if(tmpreg
&0x700FFFF)
2500 as_bad("wrong register in floating-point reglist");
2502 install_operand(s
[1],tmpreg
>>16);
2507 install_operand(s
[1],get_num(opP
->con1
,60));
2511 tmpreg
= (opP
->mode
==DREG
)
2512 ? 0x20+opP
->reg
-DATA
2513 : (get_num(opP
->con1
,40)&0x1F);
2514 install_operand(s
[1],tmpreg
);
2518 tmpreg
=get_num(opP
->con1
,10);
2521 install_operand(s
[1],tmpreg
);
2526 /* This depends on the fact that ADDR registers are
2527 eight more than their corresponding DATA regs, so
2528 the result will have the ADDR_REG bit set */
2529 install_operand(s
[1],opP
->reg
-DATA
);
2533 if(opP
->reg
==FPI
) tmpreg
=0x1;
2534 else if(opP
->reg
==FPS
) tmpreg
=0x2;
2535 else if(opP
->reg
==FPC
) tmpreg
=0x4;
2536 else as_fatal("failed sanity check.");
2537 install_operand(s
[1],tmpreg
);
2540 case 'S': /* Ignore it */
2544 install_operand(s
[1],get_num(opP
->con1
,30));
2547 case 'U': /* Ignore it */
2552 case NC
: tmpreg
= 0; break;
2553 case DC
: tmpreg
= 1; break;
2554 case IC
: tmpreg
= 2; break;
2555 case BC
: tmpreg
= 3; break;
2557 as_fatal("failed sanity check");
2558 } /* switch on cache token */
2559 install_operand(s
[1], tmpreg
);
2562 /* JF: These are out of order, I fear. */
2572 as_fatal("failed sanity check.");
2574 install_operand(s
[1],tmpreg
);
2595 as_fatal("failed sanity check.");
2597 install_operand(s
[1],tmpreg
);
2601 if (opP
->reg
== VAL
)
2603 as_fatal("failed sanity check.");
2618 as_fatal("failed sanity check.");
2620 install_operand(s
[1],tmpreg
);
2625 case BAD
: case BAD
+1: case BAD
+2: case BAD
+3:
2626 case BAD
+4: case BAD
+5: case BAD
+6: case BAD
+7:
2627 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
2630 case BAC
: case BAC
+1: case BAC
+2: case BAC
+3:
2631 case BAC
+4: case BAC
+5: case BAC
+6: case BAC
+7:
2632 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
2636 as_fatal("failed sanity check.");
2638 install_operand(s
[1], tmpreg
);
2641 know(opP
->reg
== PSR
);
2644 know(opP
->reg
== PCSR
);
2657 as_fatal ("failed sanity check");
2659 install_operand (s
[1], tmpreg
);
2662 tmpreg
= get_num (opP
->con1
, 20);
2663 install_operand (s
[1], tmpreg
);
2665 case '_': /* used only for move16 absolute 32-bit address */
2666 tmpreg
=get_num(opP
->con1
,80);
2667 addword (tmpreg
>> 16);
2668 addword (tmpreg
& 0xFFFF);
2671 as_fatal("Internal error: Operand type %c unknown in line %d of file \"%s\"",
2672 s
[0], __LINE__
, __FILE__
);
2676 /* By the time whe get here (FINALLY) the_ins contains the complete
2677 instruction, ready to be emitted. . . */
2681 * get_regs := '/' + ?
2682 * | '-' + <register>
2683 * | '-' + <register> + ?
2688 * The idea here must be to scan in a set of registers but I don't
2689 * understand it. Looks awfully sloppy to me but I don't have any doc on
2696 static int get_regs(i
,str
,opP
)
2698 struct m68k_op
*opP
;
2701 /* 26, 25, 24, 23-16, 15-8, 0-7 */
2702 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
2703 unsigned long cur_regs
= 0;
2707 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
2708 else if(x==FPS) cur_regs|=(1<<25);\
2709 else if(x==FPC) cur_regs|=(1<<26);\
2710 else cur_regs|=(1<<(x-1)); }
2717 } else if(*str
=='-') {
2719 reg2
=m68k_reg_parse(&str
);
2720 if(reg2
<DATA
|| reg2
>=FPREG
+8 || reg1
==FPI
|| reg1
==FPS
|| reg1
==FPC
) {
2721 opP
->error
="unknown register in register list";
2730 } else if(*str
=='\0') {
2734 opP
->error
="unknow character in register list";
2737 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
2740 reg1
=m68k_reg_parse(&str
);
2741 if((reg1
<DATA
|| reg1
>=FPREG
+8) && !(reg1
==FPI
|| reg1
==FPS
|| reg1
==FPC
)) {
2742 opP
->error
="unknown register in register list";
2750 static int reverse_16_bits(in
)
2756 static int mask
[16] = {
2757 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2758 0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000
2765 } /* reverse_16_bits() */
2767 static int reverse_8_bits(in
)
2773 static int mask
[8] = {
2774 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2782 } /* reverse_8_bits() */
2784 static void install_operand(mode
,val
)
2790 the_ins
.opcode
[0]|=val
& 0xFF; /* JF FF is for M kludge */
2793 the_ins
.opcode
[0]|=val
<<9;
2796 the_ins
.opcode
[1]|=val
<<12;
2799 the_ins
.opcode
[1]|=val
<<6;
2802 the_ins
.opcode
[1]|=val
;
2805 the_ins
.opcode
[2]|=val
<<12;
2808 the_ins
.opcode
[2]|=val
<<6;
2811 /* DANGER! This is a hack to force cas2l and cas2w cmds
2812 to be three words long! */
2814 the_ins
.opcode
[2]|=val
;
2817 the_ins
.opcode
[1]|=val
<<7;
2820 the_ins
.opcode
[1]|=val
<<10;
2824 the_ins
.opcode
[1]|=val
<<5;
2829 the_ins
.opcode
[1]|=(val
<<10)|(val
<<7);
2832 the_ins
.opcode
[1]|=(val
<<12)|val
;
2835 the_ins
.opcode
[0]|=val
=0xff;
2838 the_ins
.opcode
[0]|=val
<<9;
2841 the_ins
.opcode
[1]|=val
;
2844 the_ins
.opcode
[1]|=val
;
2845 the_ins
.numo
++; /* What a hack */
2848 the_ins
.opcode
[1]|=val
<<4;
2855 the_ins
.opcode
[0] |= (val
<< 6);
2858 the_ins
.opcode
[1] = (val
>> 16);
2859 the_ins
.opcode
[2] = val
& 0xffff;
2863 as_fatal("failed sanity check.");
2865 } /* install_operand() */
2867 static void install_gen_operand(mode
,val
)
2873 the_ins
.opcode
[0]|=val
;
2876 /* This is a kludge!!! */
2877 the_ins
.opcode
[0]|=(val
&0x07)<<9|(val
&0x38)<<3;
2886 the_ins
.opcode
[0]|=val
;
2888 /* more stuff goes here */
2890 as_fatal("failed sanity check.");
2892 } /* install_gen_operand() */
2895 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2896 * then deal with the bitfield hack.
2899 static char *crack_operand(str
,opP
)
2901 register struct m68k_op
*opP
;
2903 register int parens
;
2905 register char *beg_str
;
2911 for(parens
=0;*str
&& (parens
>0 || notend(str
));str
++) {
2912 if(*str
=='(') parens
++;
2913 else if(*str
==')') {
2914 if(!parens
) { /* ERROR */
2915 opP
->error
="Extra )";
2921 if(!*str
&& parens
) { /* ERROR */
2922 opP
->error
="Missing )";
2927 if(m68k_ip_op(beg_str
,opP
)==FAIL
) {
2933 c
= *++str
; /* JF bitfield hack */
2937 as_bad("Missing operand");
2942 /* See the comment up above where the #define notend(... is */
2947 if(*s
==',') return 0;
2948 if(*s
=='{' || *s
=='}')
2950 if(*s
!=':') return 1;
2951 /* This kludge here is for the division cmd, which is a kludge */
2952 if(index("aAdD#",s
[1])) return 0;
2957 /* This is the guts of the machine-dependent assembler. STR points to a
2958 machine dependent instruction. This function is supposed to emit
2959 the frags/bytes it assembles to.
2963 insert_reg(regname
, regnum
)
2969 symbol_table_insert(symbol_new(regname
, SEG_REGISTER
, regnum
, &zero_address_frag
));
2971 for (i
= 0; regname
[i
]; i
++)
2972 buf
[i
] = islower (regname
[i
]) ? toupper (regname
[i
]) : regname
[i
];
2975 symbol_table_insert(symbol_new(buf
, SEG_REGISTER
, regnum
, &zero_address_frag
));
2978 static const struct {
3082 /* 68ec030 versions of same */
3085 /* 68ec030 access control unit, identical to 030 MMU status reg */
3097 for (i
= 0; init_table
[i
].name
; i
++)
3098 insert_reg(init_table
[i
].name
, init_table
[i
].number
);
3101 static int no_68851
, no_68881
;
3112 int shorts_this_frag
;
3113 static int done_first_time
;
3115 if (!done_first_time
)
3117 done_first_time
= 1;
3119 if (cpu_of_arch (current_architecture
) == 0)
3126 if (strcmp (TARGET_CPU
, "m68000") == 0)
3128 else if (strcmp (TARGET_CPU
, "m68010") == 0)
3130 else if (strcmp (TARGET_CPU
, "m68020") == 0
3131 || strcmp (TARGET_CPU
, "m68k") == 0)
3133 else if (strcmp (TARGET_CPU
, "m68030") == 0)
3135 else if (strcmp (TARGET_CPU
, "m68040") == 0)
3137 else if (strcmp (TARGET_CPU
, "cpu32") == 0)
3143 current_architecture
|= cpu_type
;
3145 if (current_architecture
& m68881
)
3147 if (current_architecture
& m68000
)
3148 as_bad ("incompatible processors 68000 and 68881/2 specified");
3149 if (current_architecture
& m68010
)
3150 as_bad ("incompatible processors 68010 and 68881/2 specified");
3151 if (current_architecture
& m68040
)
3152 as_bad ("incompatible processors 68040 and 68881/2 specified");
3154 /* What other incompatibilities ought we to check for? */
3156 /* Toss in some default assumptions about coprocessors. */
3158 && (cpu_of_arch (current_architecture
)
3159 /* Can CPU32 have a 68881 coprocessor?? */
3160 & (m68020
| m68030
| cpu32
)))
3162 current_architecture
|= m68881
;
3165 && (cpu_of_arch (current_architecture
) & m68020up
) != 0)
3167 current_architecture
|= m68851
;
3169 if (no_68881
&& (current_architecture
& m68881
))
3170 as_bad ("options for 68881 and no-68881 both given");
3171 if (no_68851
&& (current_architecture
& m68851
))
3172 as_bad ("options for 68851 and no-68851 both given");
3173 done_first_time
= 1;
3176 memset((char *)(&the_ins
), '\0', sizeof(the_ins
)); /* JF for paranoia sake */
3180 for(n
=the_ins
.numargs
;n
;--n
)
3181 if(the_ins
.operands
[n
].error
) {
3182 er
=the_ins
.operands
[n
].error
;
3187 as_bad("%s -- statement `%s' ignored",er
,str
);
3191 if(the_ins
.nfrag
==0) { /* No frag hacking involved; just put it out */
3192 toP
=frag_more(2*the_ins
.numo
);
3193 fromP
= &the_ins
.opcode
[0];
3194 for(m
=the_ins
.numo
;m
;--m
) {
3195 md_number_to_chars(toP
,(long)(*fromP
),2);
3199 /* put out symbol-dependent info */
3200 for(m
=0;m
<the_ins
.nrel
;m
++) {
3201 switch(the_ins
.reloc
[m
].wid
) {
3218 as_fatal("Don't know how to figure width of %c in md_assemble()",the_ins
.reloc
[m
].wid
);
3222 (toP
-frag_now
->fr_literal
)-the_ins
.numo
*2+the_ins
.reloc
[m
].n
,
3224 the_ins
.reloc
[m
].add
,
3225 the_ins
.reloc
[m
].sub
,
3226 the_ins
.reloc
[m
].off
,
3227 the_ins
.reloc
[m
].pcrel
,
3233 /* There's some frag hacking */
3234 for(n
=0,fromP
= &the_ins
.opcode
[0];n
<the_ins
.nfrag
;n
++) {
3237 if(n
==0) wid
=2*the_ins
.fragb
[n
].fragoff
;
3238 else wid
=2*(the_ins
.numo
-the_ins
.fragb
[n
-1].fragoff
);
3242 for(m
=wid
/2;m
;--m
) {
3243 md_number_to_chars(toP
,(long)(*fromP
),2);
3248 for(m
=0;m
<the_ins
.nrel
;m
++) {
3249 if((the_ins
.reloc
[m
].n
)>= 2*shorts_this_frag
/* 2*the_ins.fragb[n].fragoff */) {
3250 the_ins
.reloc
[m
].n
-= 2*shorts_this_frag
/* 2*the_ins.fragb[n].fragoff */;
3253 wid
=the_ins
.reloc
[m
].wid
;
3256 the_ins
.reloc
[m
].wid
=0;
3257 wid
= (wid
=='b') ? 1 : (wid
=='w') ? 2 : (wid
=='l') ? 4 : 4000;
3260 (toP
-frag_now
->fr_literal
)-the_ins
.numo
*2+the_ins
.reloc
[m
].n
,
3262 the_ins
.reloc
[m
].add
,
3263 the_ins
.reloc
[m
].sub
,
3264 the_ins
.reloc
[m
].off
,
3265 the_ins
.reloc
[m
].pcrel
,
3268 /* know(the_ins.fragb[n].fadd); */
3269 (void)frag_var(rs_machine_dependent
,10,0,(relax_substateT
)(the_ins
.fragb
[n
].fragty
),
3270 the_ins
.fragb
[n
].fadd
,the_ins
.fragb
[n
].foff
,to_beg_P
);
3272 n
=(the_ins
.numo
-the_ins
.fragb
[n
-1].fragoff
);
3275 toP
=frag_more(n
*sizeof(short));
3277 md_number_to_chars(toP
,(long)(*fromP
),2);
3283 for(m
=0;m
<the_ins
.nrel
;m
++) {
3286 wid
=the_ins
.reloc
[m
].wid
;
3289 the_ins
.reloc
[m
].wid
=0;
3290 wid
= (wid
=='b') ? 1 : (wid
=='w') ? 2 : (wid
=='l') ? 4 : 4000;
3293 (the_ins
.reloc
[m
].n
+ toP
-frag_now
->fr_literal
)-/* the_ins.numo */ shorts_this_frag
*2,
3295 the_ins
.reloc
[m
].add
,
3296 the_ins
.reloc
[m
].sub
,
3297 the_ins
.reloc
[m
].off
,
3298 the_ins
.reloc
[m
].pcrel
,
3309 * md_begin -- set up hash tables with 68000 instructions.
3310 * similar to what the vax assembler does. ---phr
3312 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3313 a copy of it at runtime, adding in the information we want but isn't
3314 there. I think it'd be better to have an awk script hack the table
3315 at compile time. Or even just xstr the table and use it as-is. But
3316 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3319 register const struct m68k_opcode
*ins
;
3320 register struct m68k_incant
*hack
,
3322 register char *retval
= 0; /* empty string, or error msg text */
3323 register unsigned int i
;
3326 if ((op_hash
= hash_new()) == NULL
)
3327 as_fatal("Virtual memory exhausted");
3329 obstack_begin(&robyn
,4000);
3330 for (ins
= m68k_opcodes
; ins
< endop
; ins
++) {
3331 hack
=slak
=(struct m68k_incant
*)obstack_alloc(&robyn
,sizeof(struct m68k_incant
));
3333 /* we *could* ignore insns that don't match our
3334 arch here but just leaving them out of the
3336 slak
->m_operands
=ins
->args
;
3337 slak
->m_opnum
=strlen(slak
->m_operands
)/2;
3338 slak
->m_arch
= ins
->arch
;
3339 slak
->m_opcode
=ins
->opcode
;
3340 /* This is kludgey */
3341 slak
->m_codenum
=((ins
->match
)&0xffffL
) ? 2 : 1;
3342 if((ins
+1)!=endop
&& !strcmp(ins
->name
,(ins
+1)->name
)) {
3343 slak
->m_next
=(struct m68k_incant
*) obstack_alloc(&robyn
,sizeof(struct m68k_incant
));
3350 retval
= hash_insert (op_hash
, ins
->name
,(char *)hack
);
3351 /* Didn't his mommy tell him about null pointers? */
3352 if(retval
&& *retval
)
3353 as_bad("Internal Error: Can't hash %s: %s",ins
->name
,retval
);
3356 for (i
= 0; i
< sizeof(mklower_table
) ; i
++)
3357 mklower_table
[i
] = (isupper(c
= (char) i
)) ? tolower(c
) : c
;
3359 for (i
= 0 ; i
< sizeof(notend_table
) ; i
++) {
3360 notend_table
[i
] = 0;
3361 alt_notend_table
[i
] = 0;
3363 notend_table
[','] = 1;
3364 notend_table
['{'] = 1;
3365 notend_table
['}'] = 1;
3366 alt_notend_table
['a'] = 1;
3367 alt_notend_table
['A'] = 1;
3368 alt_notend_table
['d'] = 1;
3369 alt_notend_table
['D'] = 1;
3370 alt_notend_table
['#'] = 1;
3371 alt_notend_table
['f'] = 1;
3372 alt_notend_table
['F'] = 1;
3373 #ifdef REGISTER_PREFIX
3374 alt_notend_table
[REGISTER_PREFIX
] = 1;
3377 #ifndef MIT_SYNTAX_ONLY
3378 /* Insert pseudo ops, these have to go into the opcode table since
3379 gas expects pseudo ops to start with a dot */
3382 while (mote_pseudo_table
[n
].poc_name
)
3384 hack
=(struct m68k_incant
*)
3385 obstack_alloc(&robyn
,sizeof(struct m68k_incant
));
3386 hash_insert(op_hash
,
3387 mote_pseudo_table
[n
].poc_name
, (char *)hack
);
3388 hack
->m_operands
= 0;
3399 #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
3400 || (*s == ':' && strchr("aAdD#", s[1]))) \
3404 /* This funciton is called once, before the assembler exits. It is
3405 supposed to do any final cleanup for this part of the assembler.
3412 /* Equal to MAX_PRECISION in atof-ieee.c */
3413 #define MAX_LITTLENUMS 6
3415 /* Turn a string in input_line_pointer into a floating point constant of type
3416 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3417 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
3420 md_atof(type
,litP
,sizeP
)
3426 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3427 LITTLENUM_TYPE
*wordP
;
3458 return "Bad call to MD_ATOF()";
3460 t
=atof_ieee(input_line_pointer
,type
,words
);
3462 input_line_pointer
=t
;
3464 *sizeP
=prec
* sizeof(LITTLENUM_TYPE
);
3465 for(wordP
=words
;prec
--;) {
3466 md_number_to_chars(litP
,(long)(*wordP
++),sizeof(LITTLENUM_TYPE
));
3467 litP
+=sizeof(LITTLENUM_TYPE
);
3469 return ""; /* Someone should teach Dean about null pointers */
3472 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3473 for use in the a.out file, and stores them in the array pointed to by buf.
3474 This knows about the endian-ness of the target machine and does
3475 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3476 2 (short) and 4 (long) Floating numbers are put out as a series of
3477 LITTLENUMS (shorts, here at least)
3480 md_number_to_chars(buf
,val
,n
)
3500 as_fatal("failed sanity check.");
3505 md_apply_fix(fixP
, val
)
3509 #ifdef IBM_COMPILER_SUX
3510 /* This is unnecessary but it convinces the native rs6000
3511 compiler to generate the code we want. */
3512 char *buf
= fixP
->fx_frag
->fr_literal
;
3513 buf
+= fixP
->fx_where
;
3514 #else /* IBM_COMPILER_SUX */
3515 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3516 #endif /* IBM_COMPILER_SUX */
3518 switch(fixP
->fx_size
) {
3533 BAD_CASE (fixP
->fx_size
);
3538 /* *fragP has been relaxed to its final size, and now needs to have
3539 the bytes inside it modified to conform to the new size There is UGLY
3543 md_convert_frag(headers
, fragP
)
3544 object_headers
*headers
;
3545 register fragS
*fragP
;
3550 /* Address in object code of the displacement. */
3551 register int object_address
= fragP
-> fr_fix
+ fragP
-> fr_address
;
3553 #ifdef IBM_COMPILER_SUX
3554 /* This is wrong but it convinces the native rs6000 compiler to
3555 generate the code we want. */
3556 register char *buffer_address
= fragP
-> fr_literal
;
3557 buffer_address
+= fragP
-> fr_fix
;
3558 #else /* IBM_COMPILER_SUX */
3559 /* Address in gas core of the place to store the displacement. */
3560 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
3561 #endif /* IBM_COMPILER_SUX */
3563 /* No longer true: know(fragP->fr_symbol); */
3565 /* The displacement of the address, from current location. */
3566 disp
= fragP
->fr_symbol
? S_GET_VALUE(fragP
->fr_symbol
) : 0;
3567 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
3569 switch(fragP
->fr_subtype
) {
3570 case TAB(BCC68000
,BYTE
):
3571 case TAB(ABRANCH
,BYTE
):
3572 know(issbyte(disp
));
3574 as_bad("short branch with zero offset: use :w");
3575 fragP
->fr_opcode
[1]=disp
;
3578 case TAB(DBCC
,SHORT
):
3579 know(issword(disp
));
3582 case TAB(BCC68000
,SHORT
):
3583 case TAB(ABRANCH
,SHORT
):
3584 know(issword(disp
));
3585 fragP
->fr_opcode
[1]=0x00;
3588 case TAB(ABRANCH
,LONG
):
3589 if (cpu_of_arch(current_architecture
) < m68020
) {
3590 if (fragP
->fr_opcode
[0]==0x61) {
3591 fragP
->fr_opcode
[0]= 0x4E;
3592 fragP
->fr_opcode
[1]= 0xB9; /* JBSR with ABSL LONG offset */
3593 subseg_change(SEG_TEXT
, 0);
3606 } else if (fragP
->fr_opcode
[0]==0x60) {
3607 fragP
->fr_opcode
[0]= 0x4E;
3608 fragP
->fr_opcode
[1]= 0xF9; /* JMP with ABSL LONG offset */
3609 subseg_change(SEG_TEXT
, 0);
3610 fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0, fragP
->fr_offset
,0,
3615 as_bad("Long branch offset not supported.");
3618 fragP
->fr_opcode
[1]=0xff;
3622 case TAB(BCC68000
,LONG
):
3623 /* only Bcc 68000 instructions can come here */
3624 /* change bcc into b!cc/jmp absl long */
3625 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
3626 fragP
->fr_opcode
[1] = 0x6; /* branch offset = 6 */
3628 /* JF: these used to be fr_opcode[2,3], but they may be in a
3629 different frag, in which case refering to them is a no-no.
3630 Only fr_opcode[0,1] are guaranteed to work. */
3631 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
3632 *buffer_address
++ = 0xf9;
3633 fragP
->fr_fix
+= 2; /* account for jmp instruction */
3634 subseg_change(SEG_TEXT
,0);
3635 fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
3641 case TAB(DBCC
,LONG
):
3642 /* only DBcc 68000 instructions can come here */
3643 /* change dbcc into dbcc/jmp absl long */
3644 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3645 *buffer_address
++ = 0x00; /* branch offset = 4 */
3646 *buffer_address
++ = 0x04;
3647 *buffer_address
++ = 0x60; /* put in bra pc+6 */
3648 *buffer_address
++ = 0x06;
3649 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
3650 *buffer_address
++ = 0xf9;
3652 fragP
->fr_fix
+= 6; /* account for bra/jmp instructions */
3653 subseg_change(SEG_TEXT
,0);
3654 fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
3660 case TAB(FBRANCH
,SHORT
):
3661 know((fragP
->fr_opcode
[1]&0x40)==0);
3664 case TAB(FBRANCH
,LONG
):
3665 fragP
->fr_opcode
[1]|=0x40; /* Turn on LONG bit */
3668 case TAB(PCREL
,SHORT
):
3671 case TAB(PCREL
,LONG
):
3672 /* The thing to do here is force it to ABSOLUTE LONG, since
3673 PCREL is really trying to shorten an ABSOLUTE address anyway */
3674 /* JF FOO This code has not been tested */
3675 subseg_change(SEG_TEXT
,0);
3676 fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0, NO_RELOC
);
3677 if((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
3678 as_bad("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
3679 fragP
->fr_opcode
[0],fragP
->fr_address
);
3680 fragP
->fr_opcode
[1]&= ~0x3F;
3681 fragP
->fr_opcode
[1]|=0x39; /* Mode 7.1 */
3683 /* md_number_to_chars(buffer_address,
3684 (long)(fragP->fr_symbol->sy_value + fragP->fr_offset),
3688 case TAB(PCLEA
,SHORT
):
3689 subseg_change(SEG_TEXT
,0);
3690 fix_new(fragP
,(int)(fragP
->fr_fix
),2,fragP
->fr_symbol
,(symbolS
*)0,fragP
->fr_offset
,1,
3692 fragP
->fr_opcode
[1] &= ~0x3F;
3693 fragP
->fr_opcode
[1] |= 0x3A;
3696 case TAB(PCLEA
,LONG
):
3697 subseg_change(SEG_TEXT
,0);
3698 fix_new(fragP
,(int)(fragP
->fr_fix
)+2,4,fragP
->fr_symbol
,(symbolS
*)0,fragP
->fr_offset
+2,1,
3700 *buffer_address
++ = 0x01;
3701 *buffer_address
++ = 0x70;
3703 /* buffer_address+=2; */
3707 } /* switch on subtype */
3710 md_number_to_chars(buffer_address
, (long) disp
, (int) ext
);
3711 fragP
->fr_fix
+= ext
;
3712 /* H_SET_TEXT_SIZE(headers, H_GET_TEXT_SIZE(headers) + ext); */
3713 } /* if extending */
3716 } /* md_convert_frag() */
3718 /* Force truly undefined symbols to their maximum size, and generally set up
3719 the frag list to be relaxed
3721 int md_estimate_size_before_relax(fragP
, segment
)
3722 register fragS
*fragP
;
3726 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
3728 old_fix
= fragP
->fr_fix
;
3730 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3731 switch (fragP
->fr_subtype
) {
3733 case TAB(ABRANCH
,SZ_UNDEF
): {
3734 if((fragP
->fr_symbol
!= NULL
) /* Not absolute */
3735 && S_GET_SEGMENT(fragP
->fr_symbol
) == segment
) {
3736 fragP
->fr_subtype
=TAB(TABTYPE(fragP
->fr_subtype
),BYTE
);
3738 } else if((fragP
->fr_symbol
== 0) || (cpu_of_arch(current_architecture
) < m68020
)) {
3739 /* On 68000, or for absolute value, switch to abs long */
3740 /* FIXME, we should check abs val, pick short or long */
3741 if(fragP
->fr_opcode
[0]==0x61) {
3742 fragP
->fr_opcode
[0]= 0x4E;
3743 fragP
->fr_opcode
[1]= 0xB9; /* JBSR with ABSL LONG offset */
3744 subseg_change(SEG_TEXT
, 0);
3745 fix_new(fragP
, fragP
->fr_fix
, 4,
3746 fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0, NO_RELOC
);
3749 } else if(fragP
->fr_opcode
[0]==0x60) {
3750 fragP
->fr_opcode
[0]= 0x4E;
3751 fragP
->fr_opcode
[1]= 0xF9; /* JMP with ABSL LONG offset */
3752 subseg_change(SEG_TEXT
, 0);
3753 fix_new(fragP
, fragP
->fr_fix
, 4,
3754 fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0, NO_RELOC
);
3758 as_warn("Long branch offset to extern symbol not supported.");
3760 } else { /* Symbol is still undefined. Make it simple */
3761 fix_new(fragP
, (int)(fragP
->fr_fix
), 4, fragP
->fr_symbol
,
3762 (symbolS
*)0, fragP
->fr_offset
+4, 1, NO_RELOC
);
3764 fragP
->fr_opcode
[1]=0xff;
3770 } /* case TAB(ABRANCH,SZ_UNDEF) */
3772 case TAB(FBRANCH
,SZ_UNDEF
): {
3773 if(S_GET_SEGMENT(fragP
->fr_symbol
) == segment
|| flagseen
['l']) {
3774 fragP
->fr_subtype
= TAB(FBRANCH
,SHORT
);
3777 fragP
->fr_subtype
= TAB(FBRANCH
,LONG
);
3781 } /* TAB(FBRANCH,SZ_UNDEF) */
3783 case TAB(PCREL
,SZ_UNDEF
): {
3784 if(S_GET_SEGMENT(fragP
->fr_symbol
) == segment
|| flagseen
['l']) {
3785 fragP
->fr_subtype
= TAB(PCREL
,SHORT
);
3788 fragP
->fr_subtype
= TAB(PCREL
,LONG
);
3792 } /* TAB(PCREL,SZ_UNDEF) */
3794 case TAB(BCC68000
,SZ_UNDEF
): {
3795 if((fragP
->fr_symbol
!= NULL
)
3796 && S_GET_SEGMENT(fragP
->fr_symbol
) == segment
) {
3797 fragP
->fr_subtype
=TAB(BCC68000
,BYTE
);
3800 /* only Bcc 68000 instructions can come here */
3801 /* change bcc into b!cc/jmp absl long */
3802 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
3804 fragP
->fr_opcode
[1] = 0x04; /* branch offset = 6 */
3805 /* JF: these were fr_opcode[2,3] */
3806 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
3807 buffer_address
[1] = 0xf8;
3808 fragP
->fr_fix
+= 2; /* account for jmp instruction */
3809 subseg_change(SEG_TEXT
,0);
3810 fix_new(fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, 0,
3811 fragP
->fr_offset
, 0, NO_RELOC
);
3814 fragP
->fr_opcode
[1] = 0x06; /* branch offset = 6 */
3815 /* JF: these were fr_opcode[2,3] */
3816 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
3817 buffer_address
[1] = 0xf9;
3818 fragP
->fr_fix
+= 2; /* account for jmp instruction */
3819 subseg_change(SEG_TEXT
,0);
3820 fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
3821 fragP
->fr_offset
, 0, NO_RELOC
);
3826 } /* case TAB(BCC68000,SZ_UNDEF) */
3828 case TAB(DBCC
,SZ_UNDEF
): {
3829 if (fragP
->fr_symbol
!= NULL
&& S_GET_SEGMENT(fragP
->fr_symbol
) == segment
) {
3830 fragP
->fr_subtype
=TAB(DBCC
,SHORT
);
3834 /* only DBcc 68000 instructions can come here */
3835 /* change dbcc into dbcc/jmp absl long */
3836 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3837 buffer_address
[0] = 0x00; /* branch offset = 4 */
3838 buffer_address
[1] = 0x04;
3839 buffer_address
[2] = 0x60; /* put in bra pc + ... */
3842 /* JF: these were fr_opcode[5-7] */
3843 buffer_address
[3] = 0x04; /* plus 4 */
3844 buffer_address
[4] = 0x4e;/* Put in Jump Word */
3845 buffer_address
[5] = 0xf8;
3846 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
3847 subseg_change(SEG_TEXT
,0);
3848 fix_new(fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, 0,
3851 fragP
->fr_offset
, 0, NO_RELOC
);
3854 /* JF: these were fr_opcode[5-7] */
3855 buffer_address
[3] = 0x06; /* Plus 6 */
3856 buffer_address
[4] = 0x4e; /* put in jmp long (0x4ef9) */
3857 buffer_address
[5] = 0xf9;
3858 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
3859 subseg_change(SEG_TEXT
,0);
3860 fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
3861 fragP
->fr_offset
, 0, NO_RELOC
);
3867 } /* case TAB(DBCC,SZ_UNDEF) */
3869 case TAB(PCLEA
,SZ_UNDEF
): {
3870 if ((S_GET_SEGMENT(fragP
->fr_symbol
))==segment
|| flagseen
['l']) {
3871 fragP
->fr_subtype
=TAB(PCLEA
,SHORT
);
3874 fragP
->fr_subtype
=TAB(PCLEA
,LONG
);
3878 } /* TAB(PCLEA,SZ_UNDEF) */
3883 } /* switch on subtype looking for SZ_UNDEF's. */
3885 /* now that SZ_UNDEF are taken care of, check others */
3886 switch (fragP
->fr_subtype
) {
3887 case TAB(BCC68000
,BYTE
):
3888 case TAB(ABRANCH
,BYTE
):
3889 /* We can't do a short jump to the next instruction,
3890 so we force word mode. */
3891 if (fragP
->fr_symbol
&& S_GET_VALUE(fragP
->fr_symbol
)==0 &&
3892 fragP
->fr_symbol
->sy_frag
==fragP
->fr_next
) {
3893 fragP
->fr_subtype
=TAB(TABTYPE(fragP
->fr_subtype
),SHORT
);
3900 return fragP
->fr_var
+ fragP
->fr_fix
- old_fix
;
3903 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3904 /* the bit-field entries in the relocation_info struct plays hell
3905 with the byte-order problems of cross-assembly. So as a hack,
3906 I added this mach. dependent ri twiddler. Ugly, but it gets
3908 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3909 are symbolnum, most sig. byte first. Last byte is broken up with
3910 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3911 nibble as nuthin. (on Sun 3 at least) */
3912 /* Translate the internal relocation information into target-specific
3916 md_ri_to_chars(the_bytes
, ri
)
3918 struct reloc_info_generic
*ri
;
3921 md_number_to_chars(the_bytes
, ri
->r_address
, 4);
3922 /* now the fun stuff */
3923 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
3924 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
3925 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
3926 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80) | ((ri
->r_length
<< 5) & 0x60) |
3927 ((ri
->r_extern
<< 4) & 0x10));
3929 #endif /* comment */
3931 void tc_aout_fix_to_chars(where
, fixP
, segment_address_in_file
)
3934 relax_addressT segment_address_in_file
;
3937 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3938 * Out: GNU LD relocation length code: 0, 1, or 2.
3941 static unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
3944 know(fixP
->fx_addsy
!= NULL
);
3946 md_number_to_chars(where
,
3947 fixP
->fx_frag
->fr_address
+ fixP
->fx_where
- segment_address_in_file
,
3950 r_symbolnum
= (S_IS_DEFINED(fixP
->fx_addsy
)
3951 ? S_GET_TYPE(fixP
->fx_addsy
)
3952 : fixP
->fx_addsy
->sy_number
);
3954 where
[4] = (r_symbolnum
>> 16) & 0x0ff;
3955 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
3956 where
[6] = r_symbolnum
& 0x0ff;
3957 where
[7] = (((fixP
->fx_pcrel
<< 7) & 0x80) | ((nbytes_r_length
[fixP
->fx_size
] << 5) & 0x60) |
3958 (((!S_IS_DEFINED(fixP
->fx_addsy
)) << 4) & 0x10));
3961 } /* tc_aout_fix_to_chars() */
3963 #endif /* OBJ_AOUT or OBJ_BOUT */
3965 #ifndef WORKING_DOT_WORD
3966 const int md_short_jump_size
= 4;
3967 const int md_long_jump_size
= 6;
3970 md_create_short_jump(ptr
,from_addr
,to_addr
,frag
,to_symbol
)
3979 offset
= to_addr
- (from_addr
+2);
3981 md_number_to_chars(ptr
,(long)0x6000,2);
3982 md_number_to_chars(ptr
+2,(long)offset
,2);
3986 md_create_long_jump(ptr
,from_addr
,to_addr
,frag
,to_symbol
)
3995 if (cpu_of_arch(current_architecture
) < m68020
) {
3996 offset
=to_addr
-S_GET_VALUE(to_symbol
);
3997 md_number_to_chars(ptr
,(long)0x4EF9,2);
3998 md_number_to_chars(ptr
+2,(long)offset
,4);
3999 fix_new(frag
,(ptr
+2)-frag
->fr_literal
,4,to_symbol
,(symbolS
*)0,(long)0,0,
4002 offset
=to_addr
- (from_addr
+2);
4003 md_number_to_chars(ptr
,(long)0x60ff,2);
4004 md_number_to_chars(ptr
+2,(long)offset
,4);
4009 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
4012 10: Absolute 1:8 only
4013 20: Absolute 0:7 only
4014 30: absolute 0:15 only
4015 40: Absolute 0:31 only
4016 50: absolute 0:127 only
4017 55: absolute -64:63 only
4018 60: absolute -128:127 only
4019 70: absolute 0:4095 only
4024 static int get_num(exp
,ok
)
4025 struct m68k_exp
*exp
;
4033 if(*exp
->e_beg
=='0') {
4034 if(exp
->e_beg
[1]=='x')
4035 sscanf(exp
->e_beg
+2,"%x",&l
);
4037 sscanf(exp
->e_beg
+1,"%O",&l
);
4040 return atol(exp
->e_beg
);
4046 /* Can't do anything */
4049 if(!exp
->e_beg
|| !exp
->e_end
) {
4050 seg(exp
)=SEG_ABSOLUTE
;
4053 offs(exp
)= (ok
==10) ? 1 : 0;
4054 as_warn("Null expression defaults to %ld",offs(exp
));
4059 if(/* ok!=80 && */ (exp
->e_end
[-1]==':' || exp
->e_end
[-1]=='.')
4060 && (exp
->e_end
-exp
->e_beg
)>=2) {
4061 switch(exp
->e_end
[0]) {
4080 if (exp
->e_end
[-1] == ':')
4081 as_bad("Unknown size for expression \"%c\"",exp
->e_end
[0]);
4085 c_save
=exp
->e_end
[1];
4087 save_in
=input_line_pointer
;
4088 input_line_pointer
=exp
->e_beg
;
4089 switch(expression(&(exp
->e_exp
))) {
4091 seg(exp
)=SEG_ABSOLUTE
;
4094 offs(exp
)= (ok
==10) ? 1 : 0;
4095 as_warn("Unknown expression: '%s' defaulting to %d",exp
->e_beg
,offs(exp
));
4099 /* Do the same thing the VAX asm does */
4100 seg(exp
)=SEG_ABSOLUTE
;
4105 as_warn("expression out of range: defaulting to 1");
4112 if(offs(exp
)<1 || offs(exp
)>8) {
4113 as_warn("expression out of range: defaulting to 1");
4118 if(offs(exp
)<0 || offs(exp
)>7)
4122 if(offs(exp
)<0 || offs(exp
)>15)
4126 if(offs(exp
)<0 || offs(exp
)>32)
4130 if(offs(exp
)<0 || offs(exp
)>127)
4134 if(offs(exp
)<-64 || offs(exp
)>63)
4138 if(offs(exp
)<-128 || offs(exp
)>127)
4142 if(offs(exp
)<0 || offs(exp
)>4095) {
4144 as_warn("expression out of range: defaulting to 0");
4153 if (offs (exp
) < 0 /* flonum */
4154 && (ok
== 80 /* no bignums */
4155 || (ok
> 10 /* small-int ranges including 0 ok */
4156 /* If we have a flonum zero, a zero integer should
4157 do as well (e.g., in moveq). */
4158 && generic_floating_point_number
.exponent
== 0
4159 && generic_floating_point_number
.low
[0] == 0)))
4161 /* HACK! Turn it into a long */
4162 LITTLENUM_TYPE words
[6];
4164 gen_to_words(words
,2,8L);/* These numbers are magic! */
4165 seg(exp
)=SEG_ABSOLUTE
;
4168 offs(exp
)=words
[1]|(words
[0]<<16);
4171 seg(exp
)=SEG_ABSOLUTE
;
4174 offs(exp
)= (ok
==10) ? 1 : 0;
4175 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp
->e_beg
,offs(exp
));
4183 case SEG_DIFFERENCE
:
4184 if(ok
>=10 && ok
<=70) {
4185 seg(exp
)=SEG_ABSOLUTE
;
4188 offs(exp
)= (ok
==10) ? 1 : 0;
4189 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp
->e_beg
,offs(exp
));
4195 if(input_line_pointer
!=exp
->e_end
+1)
4196 as_bad("Ignoring junk after expression");
4197 exp
->e_end
[1]=c_save
;
4198 input_line_pointer
=save_in
;
4200 switch(exp
->e_siz
) {
4202 if(!isbyte(offs(exp
)))
4203 as_warn("expression doesn't fit in BYTE");
4206 if(!isword(offs(exp
)))
4207 as_warn("expression doesn't fit in WORD");
4215 /* These are the back-ends for the various machine dependent pseudo-ops. */
4216 void demand_empty_rest_of_line(); /* Hate those extra verbose names */
4218 static void s_data1() {
4219 subseg_new(SEG_DATA
,1);
4220 demand_empty_rest_of_line();
4223 static void s_data2() {
4224 subseg_new(SEG_DATA
,2);
4225 demand_empty_rest_of_line();
4230 /* We don't support putting frags in the BSS segment, we fake it
4231 by marking in_bss, then looking at s_skip for clues */
4233 subseg_new(SEG_BSS
, 0);
4234 demand_empty_rest_of_line();
4237 static void s_even() {
4239 register long temp_fill
;
4241 temp
= 1; /* JF should be 2? */
4242 temp_fill
= get_absolute_expression ();
4243 if ( ! need_pass_2
) /* Never make frag if expect extra pass. */
4244 frag_align (temp
, (int)temp_fill
);
4245 demand_empty_rest_of_line();
4248 static void s_proc() {
4249 demand_empty_rest_of_line();
4252 /* s_space is defined in read.c .skip is simply an alias to it. */
4256 * Invocation line includes a switch not recognized by the base assembler.
4257 * See if it's a processor-specific option. These are:
4259 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4260 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4261 * Select the architecture. Instructions or features not
4262 * supported by the selected architecture cause fatal
4263 * errors. More than one may be specified. The default is
4264 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4265 * for -m68000, and -m68882 is a synonym for -m68881.
4266 * -[A]m[c]no-68851, -[A]m[c]no-68881
4267 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4268 * so don't use or document it, but that's the way the parsing
4271 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4272 * (e.g. m68020) also requests that float instructions be included. This
4273 * is the default setup, mostly to avoid hassling users. A better
4274 * rearrangement of this structure would be to add an option to DENY
4275 * floating point opcodes, for people who want to really know there's none
4276 * of that funny floaty stuff going on. FIXME-later.
4278 #ifndef MAYBE_FLOAT_TOO
4279 #define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */
4282 int md_parse_option(argP
,cntP
,vecP
)
4288 case 'l': /* -l means keep external to 2 bit offset
4289 rather than 16 bit one */
4292 case 'S': /* -S means that jbsr's always turn into jsr's. */
4297 /* intentional fall-through */
4303 } /* allow an optional "c" */
4305 if (!strcmp(*argP
, "68000")
4306 || !strcmp(*argP
, "68008")) {
4307 current_architecture
|= m68000
;
4308 } else if (!strcmp(*argP
, "68010")) {
4310 omagic
= 1<<16|OMAGIC
;
4312 current_architecture
|= m68010
;
4314 } else if (!strcmp(*argP
, "68020")) {
4315 current_architecture
|= m68020
| MAYBE_FLOAT_TOO
;
4317 } else if (!strcmp(*argP
, "68030")) {
4318 current_architecture
|= m68030
| MAYBE_FLOAT_TOO
;
4320 } else if (!strcmp(*argP
, "68040")) {
4321 current_architecture
|= m68040
| MAYBE_FLOAT_TOO
;
4324 } else if (!strcmp(*argP
, "68881")) {
4325 current_architecture
|= m68881
;
4327 } else if (!strcmp(*argP
, "68882")) {
4328 current_architecture
|= m68882
;
4329 #endif /* NO_68881 */
4330 /* Even if we aren't configured to support the processor,
4331 it should still be possible to assert that the user
4332 doesn't have it... */
4333 } else if (!strcmp (*argP
, "no-68881")
4334 || !strcmp (*argP
, "no-68882")) {
4337 } else if (!strcmp(*argP
,"68851")) {
4338 current_architecture
|= m68851
;
4339 #endif /* NO_68851 */
4340 } else if (!strcmp (*argP
, "no-68851")) {
4342 } else if (!strcmp (*argP
, "pu32")) { /* "-mcpu32" */
4343 current_architecture
|= cpu32
;
4345 as_warn("Unknown architecture, \"%s\". option ignored", *argP
);
4346 } /* switch on architecture */
4348 while(**argP
) (*argP
)++;
4353 if (!strcmp(*argP
,"pic")) {
4355 break; /* -pic, Position Independent Code */
4369 /* TEST2: Test md_assemble() */
4370 /* Warning, this routine probably doesn't work anymore */
4374 struct m68k_it the_ins
;
4381 if(!gets(buf
) || !*buf
)
4383 if(buf
[0]=='|' || buf
[1]=='.')
4385 for(cp
=buf
;*cp
;cp
++)
4390 memset(&the_ins
, '\0', sizeof(the_ins
));
4391 m68k_ip(&the_ins
,buf
);
4393 printf("Error %s in %s\n",the_ins
.error
,buf
);
4395 printf("Opcode(%d.%s): ",the_ins
.numo
,the_ins
.args
);
4396 for(n
=0;n
<the_ins
.numo
;n
++)
4397 printf(" 0x%x",the_ins
.opcode
[n
]&0xffff);
4399 print_the_insn(&the_ins
.opcode
[0],stdout
);
4400 (void)putchar('\n');
4402 for(n
=0;n
<strlen(the_ins
.args
)/2;n
++) {
4403 if(the_ins
.operands
[n
].error
) {
4404 printf("op%d Error %s in %s\n",n
,the_ins
.operands
[n
].error
,buf
);
4407 printf("mode %d, reg %d, ",the_ins
.operands
[n
].mode
,the_ins
.operands
[n
].reg
);
4408 if(the_ins
.operands
[n
].b_const
)
4409 printf("Constant: '%.*s', ",1+the_ins
.operands
[n
].e_const
-the_ins
.operands
[n
].b_const
,the_ins
.operands
[n
].b_const
);
4410 printf("ireg %d, isiz %d, imul %d, ",the_ins
.operands
[n
].ireg
,the_ins
.operands
[n
].isiz
,the_ins
.operands
[n
].imul
);
4411 if(the_ins
.operands
[n
].b_iadd
)
4412 printf("Iadd: '%.*s',",1+the_ins
.operands
[n
].e_iadd
-the_ins
.operands
[n
].b_iadd
,the_ins
.operands
[n
].b_iadd
);
4413 (void)putchar('\n');
4425 while(*str
&& *str
!=' ')
4427 if(str
[-1]==':' || str
[1]=='=')
4434 /* Possible states for relaxation:
4436 0 0 branch offset byte (bra, etc)
4440 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4444 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4463 extern fragS
*text_frag_root
;
4465 for(fragP
=text_frag_root
;fragP
;fragP
=fragP
->fr_next
) {
4466 printf("addr %lu next 0x%x fix %ld var %ld symbol 0x%x offset %ld\n",
4467 fragP
->fr_address
,fragP
->fr_next
,fragP
->fr_fix
,fragP
->fr_var
,fragP
->fr_symbol
,fragP
->fr_offset
);
4468 printf("opcode 0x%x type %d subtype %d\n\n",fragP
->fr_opcode
,fragP
->fr_type
,fragP
->fr_subtype
);
4480 fputs("Internal error:",stderr
);
4481 _doprnt(format
,&args
,stderr
);
4482 (void)putc('\n',stderr
);
4488 /* We have no need to default values of symbols. */
4492 md_undefined_symbol (name
)
4498 /* Parse an operand that is machine-specific.
4499 We just return without modifying the expression if we have nothing
4504 md_operand (expressionP
)
4505 expressionS
*expressionP
;
4509 /* Round up a section size to the appropriate boundary. */
4511 md_section_align (segment
, size
)
4515 return size
; /* Byte alignment is fine */
4518 /* Exactly what point is a PC-relative offset relative TO?
4519 On the 68k, they're relative to the address of the offset, plus
4520 its size. (??? Is this right? FIXME-SOON!) */
4522 md_pcrel_from (fixP
)
4525 return(fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
);
4529 tc_coff_symbol_emit_hook ()
4534 tc_coff_sizemachdep(frag
)
4537 switch (frag
->fr_subtype
& 0x3)
4539 case BYTE
: return 1;
4540 case SHORT
: return 2;
4541 case LONG
: return 4;
4553 /* end of tc-m68k.c */