projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
* tc-m68k.c (try_index): Error if index scaling specified and
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
2 slow to compile, easy to find file.
3
4 Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21
22 #include <ctype.h>
23 #define NO_RELOC 0
24 #include "as.h"
25
26 #include "obstack.h"
27
28 /* note that this file includes real declarations and thus can only be included by one source file per executable. */
29 #include "opcode/m68k.h"
30 #ifdef TE_SUN
31 /* This variable contains the value to write out at the beginning of
32 the a.out file. The 2<<16 means that this is a 68020 file instead
33 of an old-style 68000 file */
34
35 long omagic = 2<<16|OMAGIC; /* Magic byte for header file */
36 #else
37 long omagic = OMAGIC;
38 #endif
39
40 /* This array holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful */
42 const char comment_chars[] = "|";
43
44 /* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47 /* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
49 #NO_APP at the beginning of its output. */
50 /* Also note that comments like this one will always work. */
51 const char line_comment_chars[] = "#";
52
53 /* Chars that can be used to separate mant from exp in floating point nums */
54 const char EXP_CHARS[] = "eE";
55
56 /* Chars that mean this number is a floating point constant */
57 /* As in 0f12.456 */
58 /* or 0d1.2345e12 */
59
60 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
61
62 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
63 changed in read.c . Ideally it shouldn't have to know about it at all,
64 but nothing is ideal around here.
65 */
66
67 int md_reloc_size = 8; /* Size of relocation record */
68
69 /* Its an arbitrary name: This means I don't approve of it */
70 /* See flames below */
71 static struct obstack robyn;
72
73 #define TAB(x,y) (((x)<<2)+(y))
74 #define TABTYPE(xy) ((xy) >> 2)
75 #define BYTE 0
76 #define SHORT 1
77 #define LONG 2
78 #define SZ_UNDEF 3
79
80 #define BRANCH 1
81 #define FBRANCH 2
82 #define PCREL 3
83 #define BCC68000 4
84 #define DBCC 5
85 #define PCLEA 6
86
87 /* Operands we can parse: (And associated modes)
88
89 numb: 8 bit num
90 numw: 16 bit num
91 numl: 32 bit num
92 dreg: data reg 0-7
93 reg: address or data register
94 areg: address register
95 apc: address register, PC, ZPC or empty string
96 num: 16 or 32 bit num
97 num2: like num
98 sz: w or l if omitted, l assumed
99 scale: 1 2 4 or 8 if omitted, 1 assumed
100
101 7.4 IMMED #num --> NUM
102 0.? DREG dreg --> dreg
103 1.? AREG areg --> areg
104 2.? AINDR areg@ --> *(areg)
105 3.? AINC areg@+ --> *(areg++)
106 4.? ADEC areg@- --> *(--areg)
107 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
108 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
109 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
110 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
111 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
112 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
113 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
114 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
115 7.0 ABSL num:sz --> *(num)
116 num --> *(num) (sz L assumed)
117 *** MSCR otherreg --> Magic
118 With -l option
119 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
120
121 examples:
122 #foo #0x35 #12
123 d2
124 a4
125 a3@
126 a5@+
127 a6@-
128 a2@(12) pc@(14)
129 a1@(5,d2:w:1) @(45,d6:l:4)
130 pc@(a2) @(d4)
131 etc . . .
132
133
134 #name@(numw) -->turn into PC rel mode
135 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
136
137 */
138
139 enum operand_type {
140 IMMED = 1,
141 DREG,
142 AREG,
143 AINDR,
144 ADEC,
145 AINC,
146 AOFF,
147 AINDX,
148 APODX,
149 AMIND,
150 APRDX,
151 ABSL,
152 MSCR,
153 REGLST,
154 };
155
156
157 struct m68k_exp {
158 char *e_beg;
159 char *e_end;
160 expressionS e_exp;
161 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
162 };
163
164 /* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
165 8-15==addr reg for operands that take both types */
166
167 enum _register {
168 DATA = 1, /* 1- 8 == data registers 0-7 */
169 DATA0 = DATA,
170 DATA1,
171 DATA2,
172 DATA3,
173 DATA4,
174 DATA5,
175 DATA6,
176 DATA7,
177
178 ADDR,
179 ADDR0 = ADDR,
180 ADDR1,
181 ADDR2,
182 ADDR3,
183 ADDR4,
184 ADDR5,
185 ADDR6,
186 ADDR7,
187
188 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
189 /* I think. . . */
190
191 SP = ADDR7,
192
193 FPREG, /* Eight FP registers */
194 FP0 = FPREG,
195 FP1,
196 FP2,
197 FP3,
198 FP4,
199 FP5,
200 FP6,
201 FP7,
202 COPNUM = (FPREG+8), /* Co-processor #1-#8 */
203 COP0 = COPNUM,
204 COP1,
205 COP2,
206 COP3,
207 COP4,
208 COP5,
209 COP6,
210 COP7,
211 PC, /* Program counter */
212 ZPC, /* Hack for Program space, but 0 addressing */
213 SR, /* Status Reg */
214 CCR, /* Condition code Reg */
215
216 /* These have to be in order for the movec instruction to work. */
217 USP, /* User Stack Pointer */
218 ISP, /* Interrupt stack pointer */
219 SFC,
220 DFC,
221 CACR,
222 VBR,
223 CAAR,
224 MSP,
225 ITT0,
226 ITT1,
227 DTT0,
228 DTT1,
229 MMUSR,
230 TC,
231 SRP,
232 URP,
233 /* end of movec ordering constraints */
234
235 FPI,
236 FPS,
237 FPC,
238
239 DRP,
240 CRP,
241 CAL,
242 VAL,
243 SCC,
244 AC,
245 BAD,
246 BAD0 = BAD,
247 BAD1,
248 BAD2,
249 BAD3,
250 BAD4,
251 BAD5,
252 BAD6,
253 BAD7,
254 BAC,
255 BAC0 = BAC,
256 BAC1,
257 BAC2,
258 BAC3,
259 BAC4,
260 BAC5,
261 BAC6,
262 BAC7,
263 PSR,
264 PCSR,
265
266 IC, /* instruction cache token */
267 DC, /* data cache token */
268 NC, /* no cache token */
269 BC, /* both caches token */
270
271 };
272
273 /* Internal form of an operand. */
274 struct m68k_op {
275 char *error; /* Couldn't parse it */
276 enum operand_type mode; /* What mode this instruction is in. */
277 enum _register reg; /* Base register */
278 struct m68k_exp *con1;
279 int ireg; /* Index register */
280 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
281 int imul; /* Multipy ireg by this (1,2,4,or 8) */
282 struct m68k_exp *con2;
283 };
284
285 /* internal form of a 68020 instruction */
286 struct m68k_it {
287 char *error;
288 char *args; /* list of opcode info */
289 int numargs;
290
291 int numo; /* Number of shorts in opcode */
292 short opcode[11];
293
294 struct m68k_op operands[6];
295
296 int nexp; /* number of exprs in use */
297 struct m68k_exp exprs[4];
298
299 int nfrag; /* Number of frags we have to produce */
300 struct {
301 int fragoff; /* Where in the current opcode[] the frag ends */
302 symbolS *fadd;
303 long foff;
304 int fragty;
305 } fragb[4];
306
307 int nrel; /* Num of reloc strucs in use */
308 struct {
309 int n;
310 symbolS *add,
311 *sub;
312 long off;
313 char wid;
314 char pcrel;
315 } reloc[5]; /* Five is enough??? */
316 };
317
318 #define cpu_of_arch(x) ((x) & m68000up)
319 #define float_of_arch(x) ((x) & mfloat)
320 #define mmu_of_arch(x) ((x) & mmmu)
321
322 static struct m68k_it the_ins; /* the instruction being assembled */
323
324 /* Macros for adding things to the m68k_it struct */
325
326 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
327
328 /* Like addword, but goes BEFORE general operands */
329 #define insop(w) {int z;\
330 for(z=the_ins.numo;z>opcode->m_codenum;--z)\
331 the_ins.opcode[z]=the_ins.opcode[z-1];\
332 for(z=0;z<the_ins.nrel;z++)\
333 the_ins.reloc[z].n+=2;\
334 the_ins.opcode[opcode->m_codenum]=w;\
335 the_ins.numo++;\
336 }
337
338
339 #define add_exp(beg,end) (\
340 the_ins.exprs[the_ins.nexp].e_beg=beg,\
341 the_ins.exprs[the_ins.nexp].e_end=end,\
342 &the_ins.exprs[the_ins.nexp++]\
343 )
344
345
346 /* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/
347 #define add_fix(width,exp,pc_rel) {\
348 the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \
349 (((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\
350 the_ins.reloc[the_ins.nrel].add=adds((exp));\
351 the_ins.reloc[the_ins.nrel].sub=subs((exp));\
352 the_ins.reloc[the_ins.nrel].off=offs((exp));\
353 the_ins.reloc[the_ins.nrel].wid=width;\
354 the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\
355 }
356
357 #define add_frag(add,off,type) {\
358 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\
359 the_ins.fragb[the_ins.nfrag].fadd=add;\
360 the_ins.fragb[the_ins.nfrag].foff=off;\
361 the_ins.fragb[the_ins.nfrag++].fragty=type;\
362 }
363
364 #define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
365
366 #define seg(exp) ((exp)->e_exp.X_seg)
367 #define adds(exp) ((exp)->e_exp.X_add_symbol)
368 #define subs(exp) ((exp)->e_exp.X_subtract_symbol)
369 #define offs(exp) ((exp)->e_exp.X_add_number)
370
371
372 struct m68k_incant {
373 char *m_operands;
374 unsigned long m_opcode;
375 short m_opnum;
376 short m_codenum;
377 enum m68k_architecture m_arch;
378 struct m68k_incant *m_next;
379 };
380
381 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
382 #define gettwo(x) (((x)->m_opcode)&0xffff)
383
384
385 #if __STDC__ == 1
386
387 static char *crack_operand(char *str, struct m68k_op *opP);
388 static int get_num(struct m68k_exp *exp, int ok);
389 static int get_regs(int i, char *str, struct m68k_op *opP);
390 static int reverse_16_bits(int in);
391 static int reverse_8_bits(int in);
392 static int try_index(char **s, struct m68k_op *opP);
393 static void install_gen_operand(int mode, int val);
394 static void install_operand(int mode, int val);
395 void s_bss(void);
396 static void s_data1(void);
397 static void s_data2(void);
398 static void s_even(void);
399 static void s_proc(void);
400
401 #else /* not __STDC__ */
402
403 static char *crack_operand();
404 static int get_num();
405 static int get_regs();
406 static int reverse_16_bits();
407 static int reverse_8_bits();
408 static int try_index();
409 static void install_gen_operand();
410 static void install_operand();
411 void s_bss();
412 static void s_data1();
413 static void s_data2();
414 static void s_even();
415 static void s_proc();
416
417 #endif /* not __STDC__ */
418
419 static enum m68k_architecture current_architecture = 0;
420
421 /* BCC68000 is for patching in an extra jmp instruction for long offsets
422 on the 68000. The 68000 doesn't support long branches with branchs */
423
424 /* This table desribes how you change sizes for the various types of variable
425 size expressions. This version only supports two kinds. */
426
427 /* Note that calls to frag_var need to specify the maximum expansion needed */
428 /* This is currently 10 bytes for DBCC */
429
430 /* The fields are:
431 How far Forward this mode will reach:
432 How far Backward this mode will reach:
433 How many bytes this mode will add to the size of the frag
434 Which mode to go to if the offset won't fit in this one
435 */
436 const relax_typeS
437 md_relax_table[] = {
438 { 1, 1, 0, 0 }, /* First entries aren't used */
439 { 1, 1, 0, 0 }, /* For no good reason except */
440 { 1, 1, 0, 0 }, /* that the VAX doesn't either */
441 { 1, 1, 0, 0 },
442
443 { (127), (-128), 0, TAB(BRANCH,SHORT)},
444 { (32767), (-32768), 2, TAB(BRANCH,LONG) },
445 { 0, 0, 4, 0 },
446 { 1, 1, 0, 0 },
447
448 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
449 { (32767), (-32768), 2, TAB(FBRANCH,LONG)},
450 { 0, 0, 4, 0 },
451 { 1, 1, 0, 0 },
452
453 { 1, 1, 0, 0 }, /* PCREL doesn't come BYTE */
454 { (32767), (-32768), 2, TAB(PCREL,LONG)},
455 { 0, 0, 4, 0 },
456 { 1, 1, 0, 0 },
457
458 { (127), (-128), 0, TAB(BCC68000,SHORT)},
459 { (32767), (-32768), 2, TAB(BCC68000,LONG) },
460 { 0, 0, 6, 0 }, /* jmp long space */
461 { 1, 1, 0, 0 },
462
463 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
464 { (32767), (-32768), 2, TAB(DBCC,LONG) },
465 { 0, 0, 10, 0 }, /* bra/jmp long space */
466 { 1, 1, 0, 0 },
467
468 { 1, 1, 0, 0 }, /* PCLEA doesn't come BYTE */
469 { 32767, -32768, 2, TAB(PCLEA,LONG) },
470 { 0, 0, 6, 0 },
471 { 1, 1, 0, 0 },
472
473 };
474
475 /* These are the machine dependent pseudo-ops. These are included so
476 the assembler can work on the output from the SUN C compiler, which
477 generates these.
478 */
479
480 /* This table describes all the machine specific pseudo-ops the assembler
481 has to support. The fields are:
482 pseudo-op name without dot
483 function to call to execute this pseudo-op
484 Integer arg to pass to the function
485 */
486 const pseudo_typeS md_pseudo_table[] = {
487 { "data1", s_data1, 0 },
488 { "data2", s_data2, 0 },
489 { "bss", s_bss, 0 },
490 { "even", s_even, 0 },
491 { "skip", s_space, 0 },
492 { "proc", s_proc, 0 },
493 { 0, 0, 0 }
494 };
495
496
497 /* #define isbyte(x) ((x)>=-128 && (x)<=127) */
498 /* #define isword(x) ((x)>=-32768 && (x)<=32767) */
499
500 #define issbyte(x) ((x)>=-128 && (x)<=127)
501 #define isubyte(x) ((x)>=0 && (x)<=255)
502 #define issword(x) ((x)>=-32768 && (x)<=32767)
503 #define isuword(x) ((x)>=0 && (x)<=65535)
504
505 #define isbyte(x) ((x)>=-128 && (x)<=255)
506 #define isword(x) ((x)>=-32768 && (x)<=65535)
507 #define islong(x) (1)
508
509 extern char *input_line_pointer;
510
511 enum {
512 FAIL = 0,
513 OK = 1,
514 };
515
516 /* JF these tables here are for speed at the expense of size */
517 /* You can replace them with the #if 0 versions if you really
518 need space and don't mind it running a bit slower */
519
520 static char mklower_table[256];
521 #define mklower(c) (mklower_table[(unsigned char)(c)])
522 static char notend_table[256];
523 static char alt_notend_table[256];
524 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
525 alt_notend_table[(unsigned char)(s[1])])))
526
527 #if 0
528 #define mklower(c) (isupper(c) ? tolower(c) : c)
529 #endif
530
531
532 /* JF modified this to handle cases where the first part of a symbol name
533 looks like a register */
534
535 /*
536 * m68k_reg_parse() := if it looks like a register, return it's token &
537 * advance the pointer.
538 */
539
540 enum _register m68k_reg_parse(ccp)
541 register char **ccp;
542 {
543 char *start = *ccp;
544
545 if (isalpha(*start) && is_name_beginner(*start))
546 {
547 char c;
548 char *p = start;
549 symbolS *symbolP;
550
551 while (is_part_of_name(c = *p++))
552 ;
553 * -- p = 0;
554 symbolP = symbol_find(start);
555 *p = c;
556
557 if (symbolP && S_GET_SEGMENT(symbolP) == SEG_REGISTER)
558 {
559 *ccp = p;
560 return S_GET_VALUE(symbolP);
561 }
562 }
563 return FAIL;
564
565
566 }
567
568 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
569
570 /*
571 * m68k_ip_op := '#' + <anything>
572 * | <register> + range_sep + get_regs
573 * ;
574 *
575 * range_sep := '/' | '-' ;
576 *
577 * SKIP_WHITE := <empty> | ' ' ;
578 *
579 */
580
581 int
582 m68k_ip_op(str,opP)
583 char *str;
584 register struct m68k_op *opP;
585 {
586 char *strend;
587 long i;
588 char *parse_index();
589 int needp;
590 if (*str==' ') {
591 str++;
592 } /* Find the beginning of the string */
593
594 if(!*str) {
595 opP->error="Missing operand";
596 return FAIL;
597 } /* Out of gas */
598
599 for(strend = str; *strend; strend++) ;;
600
601 --strend;
602
603 if(*str=='#') {
604 str++;
605 opP->con1=add_exp(str,strend);
606 opP->mode=IMMED;
607 return OK;
608 } /* Guess what: A constant. Shar and enjoy */
609
610 i = m68k_reg_parse(&str);
611
612 /* is a register, is exactly a register, and is followed by '@' */
613
614 if((i==FAIL || *str!='\0') && *str!='@') {
615 char *stmp;
616
617 if(i!=FAIL && (*str=='/' || *str=='-')) {
618 opP->mode=REGLST;
619 return(get_regs(i,str,opP));
620 }
621 if ((stmp=strchr(str,'@')) != '\0') {
622 opP->con1=add_exp(str,stmp-1);
623 if(stmp==strend) {
624 opP->mode=AINDX;
625 return(OK);
626 }
627
628 if ((current_architecture & m68020up) == 0) {
629 return(FAIL);
630 } /* if target is not a '20 or better */
631
632 stmp++;
633 if(*stmp++!='(' || *strend--!=')') {
634 opP->error="Malformed operand";
635 return(FAIL);
636 }
637 i=try_index(&stmp,opP);
638 opP->con2=add_exp(stmp,strend);
639
640 if (i == FAIL) {
641 opP->mode=AMIND;
642 } else {
643 opP->mode=APODX;
644 }
645 return(OK);
646 } /* if there's an '@' */
647 opP->mode = ABSL;
648 opP->con1 = add_exp(str,strend);
649 return(OK);
650 } /* not a register, not exactly a register, or no '@' */
651
652 opP->reg=i;
653
654 if (*str=='\0') {
655 if(i>=DATA+0 && i<=DATA+7)
656 opP->mode=DREG;
657 else if(i>=ADDR+0 && i<=ADDR+7)
658 opP->mode=AREG;
659 else
660 opP->mode=MSCR;
661 return OK;
662 }
663
664 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL) { /* Can't indirect off non address regs */
665 opP->error="Invalid indirect register";
666 return FAIL;
667 }
668 know(*str == '@');
669
670 str++;
671 switch(*str) {
672 case '\0':
673 opP->mode=AINDR;
674 return OK;
675 case '-':
676 opP->mode=ADEC;
677 return OK;
678 case '+':
679 opP->mode=AINC;
680 return OK;
681 case '(':
682 str++;
683 break;
684 default:
685 opP->error="Junk after indirect";
686 return FAIL;
687 }
688 /* Some kind of indexing involved. Lets find out how bad it is */
689 i=try_index(&str,opP);
690 /* Didn't start with an index reg, maybe its offset or offset,reg */
691 if(i==FAIL) {
692 char *beg_str;
693
694 beg_str=str;
695 for(i=1;i;) {
696 switch(*str++) {
697 case '\0':
698 opP->error="Missing )";
699 return FAIL;
700 case ',': i=0; break;
701 case '(': i++; break;
702 case ')': --i; break;
703 }
704 }
705 /* if(str[-3]==':') {
706 int siz;
707
708 switch(str[-2]) {
709 case 'b':
710 case 'B':
711 siz=1;
712 break;
713 case 'w':
714 case 'W':
715 siz=2;
716 break;
717 case 'l':
718 case 'L':
719 siz=3;
720 break;
721 default:
722 opP->error="Specified size isn't :w or :l";
723 return FAIL;
724 }
725 opP->con1=add_exp(beg_str,str-4);
726 opP->con1->e_siz=siz;
727 } else */
728 opP->con1=add_exp(beg_str,str-2);
729 /* Should be offset,reg */
730 if(str[-1]==',') {
731 i=try_index(&str,opP);
732 if(i==FAIL) {
733 opP->error="Malformed index reg";
734 return FAIL;
735 }
736 }
737 }
738 /* We've now got offset) offset,reg) or reg) */
739
740 if (*str == '\0') {
741 /* Th-the-thats all folks */
742 if (opP->reg == FAIL) opP->mode = AINDX; /* Other form of indirect */
743 else if(opP->ireg == FAIL) opP->mode = AOFF;
744 else opP->mode = AINDX;
745 return(OK);
746 }
747 /* Next thing had better be another @ */
748 if (*str == '@') {
749 if (str[1] == '(') {
750 needp = 1;
751 str+=2;
752 }
753 else {
754 needp = 0;
755 str++;
756 }
757 }
758
759 if ((current_architecture & m68020up) == 0) {
760 return(FAIL);
761 } /* if target is not a '20 or better */
762
763
764 if(opP->ireg != FAIL) {
765 opP->mode = APRDX;
766
767 i = try_index(&str, opP);
768 if (i != FAIL) {
769 opP->error = "Two index registers! not allowed!";
770 return(FAIL);
771 }
772 } else {
773 i = try_index(&str, opP);
774 }
775
776 if (i == FAIL) {
777 char *beg_str;
778
779 beg_str = str;
780
781 for (i = 1; i; ) {
782 switch(*str++) {
783 case '\0':
784 if (needp)
785 opP->error="Missing )";
786 return(FAIL);
787 break;
788 case ',': i=0; break;
789 case '(': i++; break;
790 case ')': --i; break;
791 }
792 }
793
794 opP->con2=add_exp(beg_str,str-2);
795
796 if (str[-1] == ',') {
797 if (opP->ireg != FAIL) {
798 opP->error = "Can't have two index regs";
799 return(FAIL);
800 }
801
802 i = try_index(&str, opP);
803
804 if (i == FAIL) {
805 opP->error = "malformed index reg";
806 return(FAIL);
807 }
808
809 opP->mode = APODX;
810 } else if (opP->ireg != FAIL) {
811 opP->mode = APRDX;
812 } else {
813 opP->mode = AMIND;
814 }
815 } else {
816 opP->mode = APODX;
817 }
818
819 if(*str!='\0') {
820 opP->error="Junk after indirect";
821 return FAIL;
822 }
823 return(OK);
824 } /* m68k_ip_op() */
825
826 /*
827 *
828 * try_index := data_or_address_register + ')' + SKIP_W
829 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
830 *
831 * multiplier := <empty>
832 * | ':' + multiplier_number
833 * ;
834 *
835 * multiplier_number := '1' | '2' | '4' | '8' ;
836 *
837 * size_spec := 'l' | 'L' | 'w' | 'W' ;
838 *
839 * SKIP_W := <empty> | ' ' ;
840 *
841 */
842
843 static int try_index(s,opP)
844 char **s;
845 struct m68k_op *opP;
846 {
847 register int i;
848 char *ss;
849 #define SKIP_W() { ss++; if (*ss==' ') ss++;}
850
851 ss= *s;
852 /* SKIP_W(); */
853 i=m68k_reg_parse(&ss);
854 if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */
855 *s=ss;
856 return FAIL;
857 }
858 opP->ireg=i;
859 /* SKIP_W(); */
860 if(*ss==')') {
861 opP->isiz=0;
862 opP->imul=1;
863 SKIP_W();
864 *s=ss;
865 return OK;
866 }
867 if(*ss!=':') {
868 opP->error="Missing : in index register";
869 *s=ss;
870 return FAIL;
871 }
872 SKIP_W();
873 switch(*ss) {
874 case 'w':
875 case 'W':
876 opP->isiz=2;
877 break;
878 case 'l':
879 case 'L':
880 opP->isiz=3;
881 break;
882 default:
883 opP->error="Index register size spec not :w or :l";
884 *s=ss;
885 return FAIL;
886 }
887 SKIP_W();
888 if(*ss==':') {
889 SKIP_W();
890 switch(*ss) {
891 case '1':
892 case '2':
893 case '4':
894 case '8':
895 if (cpu_of_arch(current_architecture) < m68020) {
896 opP->error="no index scaling in pre-68020's";
897 *s=ss;
898 return FAIL;
899 }
900 opP->imul= *ss-'0';
901 break;
902 default:
903 opP->error="index multiplier not 1, 2, 4 or 8";
904 *s=ss;
905 return FAIL;
906 }
907 SKIP_W();
908 } else opP->imul=1;
909 if(*ss!=')') {
910 opP->error="Missing )";
911 *s=ss;
912 return FAIL;
913 }
914 SKIP_W();
915 *s=ss;
916 return OK;
917 } /* try_index() */
918
919 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
920 main()
921 {
922 char buf[128];
923 struct m68k_op thark;
924
925 for(;;) {
926 if(!gets(buf))
927 break;
928 memset(&thark, '\0', sizeof(thark));
929 if(!m68k_ip_op(buf,&thark)) printf("FAIL:");
930 if(thark.error)
931 printf("op1 error %s in %s\n",thark.error,buf);
932 printf("mode %d, reg %d, ",thark.mode,thark.reg);
933 if(thark.b_const)
934 printf("Constant: '%.*s',",1+thark.e_const-thark.b_const,thark.b_const);
935 printf("ireg %d, isiz %d, imul %d ",thark.ireg,thark.isiz,thark.imul);
936 if(thark.b_iadd)
937 printf("Iadd: '%.*s'",1+thark.e_iadd-thark.b_iadd,thark.b_iadd);
938 printf("\n");
939 }
940 exit(0);
941 }
942
943 #endif
944
945
946 static struct hash_control* op_hash = NULL; /* handle of the OPCODE hash table
947 NULL means any use before m68k_ip_begin()
948 will crash */
949
950 \f
951 /*
952 * m 6 8 k _ i p ( )
953 *
954 * This converts a string into a 68k instruction.
955 * The string must be a bare single instruction in sun format
956 * with RMS-style 68020 indirects
957 * (example: )
958 *
959 * It provides some error messages: at most one fatal error message (which
960 * stops the scan) and at most one warning message for each operand.
961 * The 68k instruction is returned in exploded form, since we have no
962 * knowledge of how you parse (or evaluate) your expressions.
963 * We do however strip off and decode addressing modes and operation
964 * mnemonic.
965 *
966 * This function's value is a string. If it is not "" then an internal
967 * logic error was found: read this code to assign meaning to the string.
968 * No argument string should generate such an error string:
969 * it means a bug in our code, not in the user's text.
970 *
971 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
972 * this function.
973 */
974
975 /* JF this function no longer returns a useful value. Sorry */
976 void m68k_ip (instring)
977 char *instring;
978 {
979 register char *p;
980 register struct m68k_op *opP;
981 register struct m68k_incant *opcode;
982 register char *s;
983 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
984 int siz1, siz2;
985 char c;
986 int losing;
987 int opsfound;
988 char *crack_operand();
989 LITTLENUM_TYPE words[6];
990 LITTLENUM_TYPE *wordp;
991
992 if (*instring == ' ')
993 instring++; /* skip leading whitespace */
994
995 /* Scan up to end of operation-code, which MUST end in end-of-string
996 or exactly 1 space. */
997 for (p = instring; *p != '\0'; p++)
998 if (*p == ' ')
999 break;
1000
1001
1002 if (p == instring) {
1003 the_ins.error = "No operator";
1004 the_ins.opcode[0] = NULL;
1005 /* the_ins.numo=1; */
1006 return;
1007 }
1008
1009 /* p now points to the end of the opcode name, probably whitespace.
1010 make sure the name is null terminated by clobbering the whitespace,
1011 look it up in the hash table, then fix it back. */
1012 c = *p;
1013 *p = '\0';
1014 opcode = (struct m68k_incant *)hash_find (op_hash, instring);
1015 *p = c;
1016
1017 if (opcode == NULL) {
1018 the_ins.error = "Unknown operator";
1019 the_ins.opcode[0] = NULL;
1020 /* the_ins.numo=1; */
1021 return;
1022 }
1023
1024 /* found a legitimate opcode, start matching operands */
1025 while (*p == ' ') ++p;
1026
1027 for(opP = &the_ins.operands[0]; *p; opP++) {
1028
1029 p = crack_operand(p, opP);
1030
1031 if (opP->error) {
1032 the_ins.error=opP->error;
1033 return;
1034 }
1035 }
1036
1037 opsfound = opP - &the_ins.operands[0];
1038
1039 /* This ugly hack is to support the floating pt opcodes in their standard form */
1040 /* Essentially, we fake a first enty of type COP#1 */
1041 if (opcode->m_operands[0]=='I') {
1042 int n;
1043
1044 for(n=opsfound;n>0;--n)
1045 the_ins.operands[n]=the_ins.operands[n-1];
1046
1047 /* memcpy((char *)(&the_ins.operands[1]), (char *)(&the_ins.operands[0]), opsfound*sizeof(the_ins.operands[0])); */
1048 memset((char *)(&the_ins.operands[0]), '\0', sizeof(the_ins.operands[0]));
1049 the_ins.operands[0].mode=MSCR;
1050 the_ins.operands[0].reg=COPNUM; /* COP #1 */
1051 opsfound++;
1052 }
1053
1054 /* We've got the operands. Find an opcode that'll accept them */
1055 for (losing = 0; ; ) {
1056 /* if we didn't get the right number of ops,
1057 or we have no common model with this pattern
1058 then reject this pattern. */
1059
1060 if (opsfound != opcode->m_opnum
1061 || ((opcode->m_arch & current_architecture) == 0)) {
1062
1063 ++losing;
1064
1065 } else {
1066 for (s=opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++) {
1067 /* Warning: this switch is huge! */
1068 /* I've tried to organize the cases into this order:
1069 non-alpha first, then alpha by letter. lower-case goes directly
1070 before uppercase counterpart. */
1071 /* Code with multiple case ...: gets sorted by the lowest case ...
1072 it belongs to. I hope this makes sense. */
1073 switch(*s) {
1074 case '!':
1075 if (opP->mode == MSCR || opP->mode == IMMED
1076 || opP->mode == DREG || opP->mode == AREG
1077 || opP->mode == AINC || opP->mode == ADEC
1078 || opP->mode == REGLST)
1079 losing++;
1080 break;
1081
1082 case '#':
1083 if(opP->mode!=IMMED)
1084 losing++;
1085 else {
1086 long t;
1087
1088 t=get_num(opP->con1,80);
1089 if(s[1]=='b' && !isbyte(t))
1090 losing++;
1091 else if(s[1]=='w' && !isword(t))
1092 losing++;
1093 }
1094 break;
1095
1096 case '^':
1097 case 'T':
1098 if(opP->mode!=IMMED)
1099 losing++;
1100 break;
1101
1102 case '$':
1103 if(opP->mode==MSCR || opP->mode==AREG ||
1104 opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1105 losing++;
1106 break;
1107
1108 case '%':
1109 if(opP->mode==MSCR || opP->reg==PC ||
1110 opP->reg==ZPC || opP->mode==REGLST)
1111 losing++;
1112 break;
1113
1114
1115 case '&':
1116 if(opP->mode==MSCR || opP->mode==DREG ||
1117 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC ||
1118 opP->mode==AINC || opP->mode==ADEC || opP->mode==REGLST)
1119 losing++;
1120 break;
1121
1122 case '*':
1123 if(opP->mode==MSCR || opP->mode==REGLST)
1124 losing++;
1125 break;
1126
1127 case '+':
1128 if(opP->mode!=AINC)
1129 losing++;
1130 break;
1131
1132 case '-':
1133 if(opP->mode!=ADEC)
1134 losing++;
1135 break;
1136
1137 case '/':
1138 if(opP->mode==MSCR || opP->mode==AREG ||
1139 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->mode==REGLST)
1140 losing++;
1141 break;
1142
1143 case ';':
1144 if(opP->mode==MSCR || opP->mode==AREG || opP->mode==REGLST)
1145 losing++;
1146 break;
1147
1148 case '?':
1149 if(opP->mode==MSCR || opP->mode==AREG ||
1150 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->reg==PC ||
1151 opP->reg==ZPC || opP->mode==REGLST)
1152 losing++;
1153 break;
1154
1155 case '@':
1156 if(opP->mode==MSCR || opP->mode==AREG ||
1157 opP->mode==IMMED || opP->mode==REGLST)
1158 losing++;
1159 break;
1160
1161 case '~': /* For now! (JF FOO is this right?) */
1162 if(opP->mode==MSCR || opP->mode==DREG ||
1163 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1164 losing++;
1165 break;
1166
1167 case 'A':
1168 if(opP->mode!=AREG)
1169 losing++;
1170 break;
1171 case 'a':
1172 if (opP->mode != AINDR) {
1173 ++losing;
1174 } /* if not address register indirect */
1175 break;
1176 case 'B': /* FOO */
1177 if(opP->mode!=ABSL || (flagseen['S'] && instring[0] == 'j'
1178 && instring[1] == 'b'
1179 && instring[2] == 's'
1180 && instring[3] == 'r'))
1181 losing++;
1182 break;
1183
1184 case 'C':
1185 if(opP->mode!=MSCR || opP->reg!=CCR)
1186 losing++;
1187 break;
1188
1189 case 'd': /* FOO This mode is a KLUDGE!! */
1190 if(opP->mode!=AOFF && (opP->mode!=ABSL ||
1191 opP->con1->e_beg[0]!='(' || opP->con1->e_end[0]!=')'))
1192 losing++;
1193 break;
1194
1195 case 'D':
1196 if(opP->mode!=DREG)
1197 losing++;
1198 break;
1199
1200 case 'F':
1201 if(opP->mode!=MSCR || opP->reg<(FPREG+0) || opP->reg>(FPREG+7))
1202 losing++;
1203 break;
1204
1205 case 'I':
1206 if(opP->mode!=MSCR || opP->reg<COPNUM ||
1207 opP->reg>=COPNUM+7)
1208 losing++;
1209 break;
1210
1211 case 'J':
1212 if (opP->mode != MSCR
1213 || opP->reg < USP
1214 || opP->reg > URP
1215 || cpu_of_arch(current_architecture) < m68010 /* before 68010 had none */
1216 || (cpu_of_arch(current_architecture) < m68020
1217 && opP->reg != SFC
1218 && opP->reg != DFC
1219 && opP->reg != USP
1220 && opP->reg != VBR) /* 68010's had only these */
1221 || (cpu_of_arch(current_architecture) < m68040
1222 && opP->reg != SFC
1223 && opP->reg != DFC
1224 && opP->reg != USP
1225 && opP->reg != VBR
1226 && opP->reg != CACR
1227 && opP->reg != CAAR
1228 && opP->reg != MSP
1229 && opP->reg != ISP) /* 680[23]0's have only these */
1230 || (cpu_of_arch(current_architecture) == m68040 /* 68040 has all but this */
1231 && opP->reg == CAAR)) {
1232 losing++;
1233 } /* doesn't cut it */
1234 break;
1235
1236 case 'k':
1237 if(opP->mode!=IMMED)
1238 losing++;
1239 break;
1240
1241 case 'l':
1242 case 'L':
1243 if(opP->mode==DREG || opP->mode==AREG || opP->mode==FPREG) {
1244 if(s[1]=='8')
1245 losing++;
1246 else {
1247 opP->mode=REGLST;
1248 opP->reg=1<<(opP->reg-DATA);
1249 }
1250 } else if(opP->mode!=REGLST) {
1251 losing++;
1252 } else if(s[1]=='8' && opP->reg&0x0FFffFF)
1253 losing++;
1254 else if(s[1]=='3' && opP->reg&0x7000000)
1255 losing++;
1256 break;
1257
1258 case 'M':
1259 if(opP->mode!=IMMED)
1260 losing++;
1261 else {
1262 long t;
1263
1264 t=get_num(opP->con1,80);
1265 if(!issbyte(t) || isvar(opP->con1))
1266 losing++;
1267 }
1268 break;
1269
1270 case 'O':
1271 if(opP->mode!=DREG && opP->mode!=IMMED)
1272 losing++;
1273 break;
1274
1275 case 'Q':
1276 if(opP->mode!=IMMED)
1277 losing++;
1278 else {
1279 long t;
1280
1281 t=get_num(opP->con1,80);
1282 if(t<1 || t>8 || isvar(opP->con1))
1283 losing++;
1284 }
1285 break;
1286
1287 case 'R':
1288 if(opP->mode!=DREG && opP->mode!=AREG)
1289 losing++;
1290 break;
1291
1292 case 's':
1293 if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC))
1294 losing++;
1295 break;
1296
1297 case 'S':
1298 if(opP->mode!=MSCR || opP->reg!=SR)
1299 losing++;
1300 break;
1301
1302 case 'U':
1303 if(opP->mode!=MSCR || opP->reg!=USP)
1304 losing++;
1305 break;
1306
1307 /* JF these are out of order. We could put them
1308 in order if we were willing to put up with
1309 bunches of #ifdef m68851s in the code */
1310 #ifndef NO_68851
1311 /* Memory addressing mode used by pflushr */
1312 case '|':
1313 if(opP->mode==MSCR || opP->mode==DREG ||
1314 opP->mode==AREG || opP->mode==REGLST)
1315 losing++;
1316 break;
1317
1318 case 'f':
1319 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
1320 losing++;
1321 break;
1322
1323 case 'P':
1324 if (opP->mode != MSCR || (opP->reg != TC && opP->reg != CAL &&
1325 opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
1326 losing++;
1327 break;
1328
1329 case 'V':
1330 if (opP->reg != VAL)
1331 losing++;
1332 break;
1333
1334 case 'W':
1335 if (opP->mode != MSCR || (opP->reg != DRP && opP->reg != SRP &&
1336 opP->reg != CRP))
1337 losing++;
1338 break;
1339
1340 case 'X':
1341 if (opP->mode != MSCR ||
1342 (!(opP->reg >= BAD && opP->reg <= BAD+7) &&
1343 !(opP->reg >= BAC && opP->reg <= BAC+7)))
1344 losing++;
1345 break;
1346
1347 case 'Y':
1348 if (opP->reg != PSR)
1349 losing++;
1350 break;
1351
1352 case 'Z':
1353 if (opP->reg != PCSR)
1354 losing++;
1355 break;
1356 #endif
1357 case 'c':
1358 if (opP->reg != NC
1359 && opP->reg != IC
1360 && opP->reg != DC
1361 && opP->reg != BC) {
1362 losing++;
1363 } /* not a cache specifier. */
1364 break;
1365
1366 case '_':
1367 if (opP->mode != ABSL) {
1368 ++losing;
1369 } /* not absolute */
1370 break;
1371
1372 default:
1373 as_fatal("Internal error: Operand mode %c unknown in line %s of file \"%s\"",
1374 *s, __LINE__, __FILE__);
1375 } /* switch on type of operand */
1376
1377 if (losing) break;
1378 } /* for each operand */
1379 } /* if immediately wrong */
1380
1381 if (!losing) {
1382 break;
1383 } /* got it. */
1384
1385 opcode = opcode->m_next;
1386
1387 if (!opcode) {
1388 the_ins.error = "instruction/operands mismatch or invalid\n instruction for this architecture";
1389 return;
1390 } /* Fell off the end */
1391
1392 losing = 0;
1393 }
1394
1395 /* now assemble it */
1396
1397 the_ins.args=opcode->m_operands;
1398 the_ins.numargs=opcode->m_opnum;
1399 the_ins.numo=opcode->m_codenum;
1400 the_ins.opcode[0]=getone(opcode);
1401 the_ins.opcode[1]=gettwo(opcode);
1402
1403 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) {
1404 /* This switch is a doozy.
1405 Watch the first step; its a big one! */
1406 switch(s[0]) {
1407
1408 case '*':
1409 case '~':
1410 case '%':
1411 case ';':
1412 case '@':
1413 case '!':
1414 case '&':
1415 case '$':
1416 case '?':
1417 case '/':
1418 #ifndef NO_68851
1419 case '|':
1420 #endif
1421 switch(opP->mode) {
1422 case IMMED:
1423 tmpreg=0x3c; /* 7.4 */
1424 if (strchr("bwl",s[1])) nextword=get_num(opP->con1,80);
1425 else nextword=nextword=get_num(opP->con1,0);
1426 if(isvar(opP->con1))
1427 add_fix(s[1],opP->con1,0);
1428 switch(s[1]) {
1429 case 'b':
1430 if(!isbyte(nextword))
1431 opP->error="operand out of range";
1432 addword(nextword);
1433 baseo=0;
1434 break;
1435 case 'w':
1436 if(!isword(nextword))
1437 opP->error="operand out of range";
1438 addword(nextword);
1439 baseo=0;
1440 break;
1441 case 'l':
1442 addword(nextword>>16);
1443 addword(nextword);
1444 baseo=0;
1445 break;
1446
1447 case 'f':
1448 baseo=2;
1449 outro=8;
1450 break;
1451 case 'F':
1452 baseo=4;
1453 outro=11;
1454 break;
1455 case 'x':
1456 baseo=6;
1457 outro=15;
1458 break;
1459 case 'p':
1460 baseo=6;
1461 outro= -1;
1462 break;
1463 default:
1464 as_fatal("Internal error: Can't decode %c%c in line %s of file \"%s\"",
1465 *s, s[1], __LINE__, __FILE__);
1466 }
1467 if(!baseo)
1468 break;
1469
1470 /* We gotta put out some float */
1471 if(seg(opP->con1)!=SEG_BIG) {
1472 int_to_gen(nextword);
1473 gen_to_words(words,baseo,(long int)outro);
1474 for(wordp=words;baseo--;wordp++)
1475 addword(*wordp);
1476 break;
1477 } /* Its BIG */
1478 if(offs(opP->con1)>0) {
1479 as_warn("Bignum assumed to be binary bit-pattern");
1480 if(offs(opP->con1)>baseo) {
1481 as_warn("Bignum too big for %c format; truncated",s[1]);
1482 offs(opP->con1)=baseo;
1483 }
1484 baseo-=offs(opP->con1);
1485 for(wordp=generic_bignum+offs(opP->con1)-1;offs(opP->con1)--;--wordp)
1486 addword(*wordp);
1487 while(baseo--)
1488 addword(0);
1489 break;
1490 }
1491 gen_to_words(words,baseo,(long)outro);
1492 for (wordp=words;baseo--;wordp++)
1493 addword(*wordp);
1494 break;
1495 case DREG:
1496 tmpreg=opP->reg-DATA; /* 0.dreg */
1497 break;
1498 case AREG:
1499 tmpreg=0x08+opP->reg-ADDR; /* 1.areg */
1500 break;
1501 case AINDR:
1502 tmpreg=0x10+opP->reg-ADDR; /* 2.areg */
1503 break;
1504 case ADEC:
1505 tmpreg=0x20+opP->reg-ADDR; /* 4.areg */
1506 break;
1507 case AINC:
1508 tmpreg=0x18+opP->reg-ADDR; /* 3.areg */
1509 break;
1510 case AOFF:
1511
1512 nextword=get_num(opP->con1,80);
1513 /* Force into index mode. Hope this works */
1514
1515 /* We do the first bit for 32-bit displacements,
1516 and the second bit for 16 bit ones. It is
1517 possible that we should make the default be
1518 WORD instead of LONG, but I think that'd
1519 break GCC, so we put up with a little
1520 inefficiency for the sake of working output.
1521 */
1522
1523 if( !issword(nextword)
1524 || ( isvar(opP->con1)
1525 && ( ( opP->con1->e_siz==0
1526 && flagseen['l']==0)
1527 || opP->con1->e_siz==3))) {
1528
1529 if(opP->reg==PC)
1530 tmpreg=0x3B; /* 7.3 */
1531 else
1532 tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
1533 if(isvar(opP->con1)) {
1534 if(opP->reg==PC) {
1535 add_frag(adds(opP->con1),
1536 offs(opP->con1),
1537 TAB(PCLEA,SZ_UNDEF));
1538 break;
1539 } else {
1540 addword(0x0170);
1541 add_fix('l',opP->con1,1);
1542 }
1543 } else
1544 addword(0x0170);
1545 addword(nextword>>16);
1546 } else {
1547 if(opP->reg==PC)
1548 tmpreg=0x3A; /* 7.2 */
1549 else
1550 tmpreg=0x28+opP->reg-ADDR; /* 5.areg */
1551
1552 if(isvar(opP->con1)) {
1553 if(opP->reg==PC) {
1554 add_fix('w',opP->con1,1);
1555 } else
1556 add_fix('w',opP->con1,0);
1557 }
1558 }
1559 addword(nextword);
1560 break;
1561
1562 case APODX:
1563 case AMIND:
1564 case APRDX:
1565 know(current_architecture & m68020up);
1566 /* intentional fall-through */
1567 case AINDX:
1568 nextword=0;
1569 baseo=get_num(opP->con1,80);
1570 outro=get_num(opP->con2,80);
1571 /* Figure out the 'addressing mode' */
1572 /* Also turn on the BASE_DISABLE bit, if needed */
1573 if(opP->reg==PC || opP->reg==ZPC) {
1574 tmpreg=0x3b; /* 7.3 */
1575 if(opP->reg==ZPC)
1576 nextword|=0x80;
1577 } else if(opP->reg==FAIL) {
1578 nextword|=0x80;
1579 tmpreg=0x30; /* 6.garbage */
1580 } else tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
1581
1582 siz1= (opP->con1) ? opP->con1->e_siz : 0;
1583 siz2= (opP->con2) ? opP->con2->e_siz : 0;
1584
1585 /* Index register stuff */
1586 if(opP->ireg>=DATA+0 && opP->ireg<=ADDR+7) {
1587 nextword|=(opP->ireg-DATA)<<12;
1588
1589 if(opP->isiz==0 || opP->isiz==3)
1590 nextword|=0x800;
1591 switch(opP->imul) {
1592 case 1: break;
1593 case 2: nextword|=0x200; break;
1594 case 4: nextword|=0x400; break;
1595 case 8: nextword|=0x600; break;
1596 default: as_fatal("failed sanity check.");
1597 }
1598 /* IF its simple,
1599 GET US OUT OF HERE! */
1600
1601 /* Must be INDEX, with an index
1602 register. Address register
1603 cannot be ZERO-PC, and either
1604 :b was forced, or we know
1605 it will fit */
1606 if( opP->mode==AINDX
1607 && opP->reg!=FAIL
1608 && opP->reg!=ZPC
1609 && ( siz1==1
1610 || ( issbyte(baseo)
1611 && !isvar(opP->con1)))) {
1612 nextword +=baseo&0xff;
1613 addword(nextword);
1614 if(isvar(opP->con1))
1615 add_fix('B',opP->con1,0);
1616 break;
1617 }
1618 } else
1619 nextword|=0x40; /* No index reg */
1620
1621 /* It aint simple */
1622 nextword|=0x100;
1623 /* If the guy specified a width, we assume that
1624 it is wide enough. Maybe it isn't. If so, we lose
1625 */
1626 switch(siz1) {
1627 case 0:
1628 if(isvar(opP->con1) || !issword(baseo)) {
1629 siz1=3;
1630 nextword|=0x30;
1631 } else if(baseo==0)
1632 nextword|=0x10;
1633 else {
1634 nextword|=0x20;
1635 siz1=2;
1636 }
1637 break;
1638 case 1:
1639 as_warn("Byte dispacement won't work. Defaulting to :w");
1640 case 2:
1641 nextword|=0x20;
1642 break;
1643 case 3:
1644 nextword|=0x30;
1645 break;
1646 }
1647
1648 /* Figure out innner displacement stuff */
1649 if(opP->mode!=AINDX) {
1650 switch(siz2) {
1651 case 0:
1652 if(isvar(opP->con2) || !issword(outro)) {
1653 siz2=3;
1654 nextword|=0x3;
1655 } else if(outro==0)
1656 nextword|=0x1;
1657 else {
1658 nextword|=0x2;
1659 siz2=2;
1660 }
1661 break;
1662 case 1:
1663 as_warn("Byte dispacement won't work. Defaulting to :w");
1664 case 2:
1665 nextword|=0x2;
1666 break;
1667 case 3:
1668 nextword|=0x3;
1669 break;
1670 }
1671 if(opP->mode==APODX) nextword|=0x04;
1672 else if(opP->mode==AMIND) nextword|=0x40;
1673 }
1674 addword(nextword);
1675
1676 if(isvar(opP->con1)) {
1677 if(opP->reg==PC || opP->reg==ZPC) {
1678 add_fix(siz1==3 ? 'l' : 'w',opP->con1,1);
1679 opP->con1->e_exp.X_add_number+=6;
1680 } else
1681 add_fix(siz1==3 ? 'l' : 'w',opP->con1,0);
1682 }
1683 if(siz1==3)
1684 addword(baseo>>16);
1685 if(siz1)
1686 addword(baseo);
1687
1688 if(isvar(opP->con2)) {
1689 if(opP->reg==PC || opP->reg==ZPC) {
1690 add_fix(siz2==3 ? 'l' : 'w',opP->con2,1);
1691 opP->con1->e_exp.X_add_number+=6;
1692 } else
1693 add_fix(siz2==3 ? 'l' : 'w',opP->con2,0);
1694 }
1695 if(siz2==3)
1696 addword(outro>>16);
1697 if(siz2)
1698 addword(outro);
1699
1700 break;
1701
1702 case ABSL:
1703 nextword=get_num(opP->con1,80);
1704 switch(opP->con1->e_siz) {
1705 default:
1706 as_warn("Unknown size for absolute reference");
1707 case 0:
1708 if(!isvar(opP->con1) && issword(offs(opP->con1))) {
1709 tmpreg=0x38; /* 7.0 */
1710 addword(nextword);
1711 break;
1712 }
1713 /* Don't generate pc relative code
1714 on 68010 and 68000 */
1715 if(isvar(opP->con1)
1716 && !subs(opP->con1)
1717 && seg(opP->con1) == SEG_TEXT
1718 && now_seg == SEG_TEXT
1719 && cpu_of_arch(current_architecture) >= m68020
1720 && !flagseen['S']
1721 && !strchr("~%&$?", s[0])) {
1722 tmpreg=0x3A; /* 7.2 */
1723 add_frag(adds(opP->con1),
1724 offs(opP->con1),
1725 TAB(PCREL,SZ_UNDEF));
1726 break;
1727 }
1728 case 3: /* Fall through into long */
1729 if(isvar(opP->con1))
1730 add_fix('l',opP->con1,0);
1731
1732 tmpreg=0x39; /* 7.1 mode */
1733 addword(nextword>>16);
1734 addword(nextword);
1735 break;
1736
1737 case 2: /* Word */
1738 if(isvar(opP->con1))
1739 add_fix('w',opP->con1,0);
1740
1741 tmpreg=0x38; /* 7.0 mode */
1742 addword(nextword);
1743 break;
1744 }
1745 break;
1746 case MSCR:
1747 default:
1748 as_bad("unknown/incorrect operand");
1749 /* abort(); */
1750 }
1751 install_gen_operand(s[1],tmpreg);
1752 break;
1753
1754 case '#':
1755 case '^':
1756 switch(s[1]) { /* JF: I hate floating point! */
1757 case 'j':
1758 tmpreg=70;
1759 break;
1760 case '8':
1761 tmpreg=20;
1762 break;
1763 case 'C':
1764 tmpreg=50;
1765 break;
1766 case '3':
1767 default:
1768 tmpreg=80;
1769 break;
1770 }
1771 tmpreg=get_num(opP->con1,tmpreg);
1772 if(isvar(opP->con1))
1773 add_fix(s[1],opP->con1,0);
1774 switch(s[1]) {
1775 case 'b': /* Danger: These do no check for
1776 certain types of overflow.
1777 user beware! */
1778 if(!isbyte(tmpreg))
1779 opP->error="out of range";
1780 insop(tmpreg);
1781 if(isvar(opP->con1))
1782 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
1783 break;
1784 case 'w':
1785 if(!isword(tmpreg))
1786 opP->error="out of range";
1787 insop(tmpreg);
1788 if(isvar(opP->con1))
1789 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
1790 break;
1791 case 'l':
1792 insop(tmpreg); /* Because of the way insop works, we put these two out backwards */
1793 insop(tmpreg>>16);
1794 if(isvar(opP->con1))
1795 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
1796 break;
1797 case '3':
1798 tmpreg&=0xFF;
1799 case '8':
1800 case 'C':
1801 install_operand(s[1],tmpreg);
1802 break;
1803 default:
1804 as_fatal("Internal error: Unknown mode #%c in line %s of file \"%s\"", s[1], __LINE__, __FILE__);
1805 }
1806 break;
1807
1808 case '+':
1809 case '-':
1810 case 'A':
1811 case 'a':
1812 install_operand(s[1],opP->reg-ADDR);
1813 break;
1814
1815 case 'B':
1816 tmpreg=get_num(opP->con1,80);
1817 switch(s[1]) {
1818 case 'B':
1819 /* Needs no offsetting */
1820 add_fix('B',opP->con1,1);
1821 break;
1822 case 'W':
1823 /* Offset the displacement to be relative to byte disp location */
1824 opP->con1->e_exp.X_add_number+=2;
1825 add_fix('w',opP->con1,1);
1826 addword(0);
1827 break;
1828 case 'L':
1829 long_branch:
1830 if (cpu_of_arch(current_architecture) < m68020) /* 68000 or 010 */
1831 as_warn("Can't use long branches on 68000/68010");
1832 the_ins.opcode[the_ins.numo-1]|=0xff;
1833 /* Offset the displacement to be relative to byte disp location */
1834 opP->con1->e_exp.X_add_number+=4;
1835 add_fix('l',opP->con1,1);
1836 addword(0);
1837 addword(0);
1838 break;
1839 case 'g':
1840 if(subs(opP->con1)) /* We can't relax it */
1841 goto long_branch;
1842
1843 /* This could either be a symbol, or an
1844 absolute address. No matter, the
1845 frag hacking will finger it out.
1846 Not quite: it can't switch from
1847 BRANCH to BCC68000 for the case
1848 where opnd is absolute (it needs
1849 to use the 68000 hack since no
1850 conditional abs jumps). */
1851 if (((cpu_of_arch(current_architecture) < m68020) || (0==adds(opP->con1)))
1852 && (the_ins.opcode[0] >= 0x6200)
1853 && (the_ins.opcode[0] <= 0x6f00)) {
1854 add_frag(adds(opP->con1),offs(opP->con1),TAB(BCC68000,SZ_UNDEF));
1855 } else {
1856 add_frag(adds(opP->con1),offs(opP->con1),TAB(BRANCH,SZ_UNDEF));
1857 }
1858 break;
1859 case 'w':
1860 if(isvar(opP->con1)) {
1861 /* check for DBcc instruction */
1862 if ((the_ins.opcode[0] & 0xf0f8) ==0x50c8) {
1863 /* size varies if patch */
1864 /* needed for long form */
1865 add_frag(adds(opP->con1),offs(opP->con1),TAB(DBCC,SZ_UNDEF));
1866 break;
1867 }
1868
1869 /* Don't ask! */
1870 opP->con1->e_exp.X_add_number+=2;
1871 add_fix('w',opP->con1,1);
1872 }
1873 addword(0);
1874 break;
1875 case 'C': /* Fixed size LONG coproc branches */
1876 the_ins.opcode[the_ins.numo-1]|=0x40;
1877 /* Offset the displacement to be relative to byte disp location */
1878 /* Coproc branches don't have a byte disp option, but they are
1879 compatible with the ordinary branches, which do... */
1880 opP->con1->e_exp.X_add_number+=4;
1881 add_fix('l',opP->con1,1);
1882 addword(0);
1883 addword(0);
1884 break;
1885 case 'c': /* Var size Coprocesssor branches */
1886 if(subs(opP->con1)) {
1887 add_fix('l',opP->con1,1);
1888 add_frag((symbolS *)0,(long)0,TAB(FBRANCH,LONG));
1889 } else if(adds(opP->con1)) {
1890 add_frag(adds(opP->con1),offs(opP->con1),TAB(FBRANCH,SZ_UNDEF));
1891 } else {
1892 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
1893 the_ins.opcode[the_ins.numo-1]|=0x40;
1894 add_fix('l',opP->con1,1);
1895 addword(0);
1896 addword(4);
1897 }
1898 break;
1899 default:
1900 as_fatal("Internal error: operand type B%c unknown in line %s of file \"%s\"",
1901 s[1], __LINE__, __FILE__);
1902 }
1903 break;
1904
1905 case 'C': /* Ignore it */
1906 break;
1907
1908 case 'd': /* JF this is a kludge */
1909 if(opP->mode==AOFF) {
1910 install_operand('s',opP->reg-ADDR);
1911 } else {
1912 char *tmpP;
1913
1914 tmpP=opP->con1->e_end-2;
1915 opP->con1->e_beg++;
1916 opP->con1->e_end-=4; /* point to the , */
1917 baseo=m68k_reg_parse(&tmpP);
1918 if(baseo<ADDR+0 || baseo>ADDR+7) {
1919 as_bad("Unknown address reg, using A0");
1920 baseo=0;
1921 } else baseo-=ADDR;
1922 install_operand('s',baseo);
1923 }
1924 tmpreg=get_num(opP->con1,80);
1925 if(!issword(tmpreg)) {
1926 as_warn("Expression out of range, using 0");
1927 tmpreg=0;
1928 }
1929 addword(tmpreg);
1930 break;
1931
1932 case 'D':
1933 install_operand(s[1],opP->reg-DATA);
1934 break;
1935
1936 case 'F':
1937 install_operand(s[1],opP->reg-FPREG);
1938 break;
1939
1940 case 'I':
1941 tmpreg=1+opP->reg-COPNUM;
1942 if(tmpreg==8)
1943 tmpreg=0;
1944 install_operand(s[1],tmpreg);
1945 break;
1946
1947 case 'J': /* JF foo */
1948 switch(opP->reg) {
1949 case SFC: tmpreg=0x000; break;
1950 case DFC: tmpreg=0x001; break;
1951 case CACR: tmpreg=0x002; break;
1952 case TC: tmpreg=0x003; break;
1953 case ITT0: tmpreg=0x004; break;
1954 case ITT1: tmpreg=0x005; break;
1955 case DTT0: tmpreg=0x006; break;
1956 case DTT1: tmpreg=0x007; break;
1957
1958 case USP: tmpreg=0x800; break;
1959 case VBR: tmpreg=0x801; break;
1960 case CAAR: tmpreg=0x802; break;
1961 case MSP: tmpreg=0x803; break;
1962 case ISP: tmpreg=0x804; break;
1963 case MMUSR: tmpreg=0x805; break;
1964 case URP: tmpreg=0x806; break;
1965 case SRP: tmpreg=0x807; break;
1966 default:
1967 as_fatal("failed sanity check.");
1968 }
1969 install_operand(s[1],tmpreg);
1970 break;
1971
1972 case 'k':
1973 tmpreg=get_num(opP->con1,55);
1974 install_operand(s[1],tmpreg&0x7f);
1975 break;
1976
1977 case 'l':
1978 tmpreg=opP->reg;
1979 if(s[1]=='w') {
1980 if(tmpreg&0x7FF0000)
1981 as_bad("Floating point register in register list");
1982 insop(reverse_16_bits(tmpreg));
1983 } else {
1984 if(tmpreg&0x700FFFF)
1985 as_bad("Wrong register in floating-point reglist");
1986 install_operand(s[1],reverse_8_bits(tmpreg>>16));
1987 }
1988 break;
1989
1990 case 'L':
1991 tmpreg=opP->reg;
1992 if(s[1]=='w') {
1993 if(tmpreg&0x7FF0000)
1994 as_bad("Floating point register in register list");
1995 insop(tmpreg);
1996 } else if(s[1]=='8') {
1997 if(tmpreg&0x0FFFFFF)
1998 as_bad("incorrect register in reglist");
1999 install_operand(s[1],tmpreg>>24);
2000 } else {
2001 if(tmpreg&0x700FFFF)
2002 as_bad("wrong register in floating-point reglist");
2003 else
2004 install_operand(s[1],tmpreg>>16);
2005 }
2006 break;
2007
2008 case 'M':
2009 install_operand(s[1],get_num(opP->con1,60));
2010 break;
2011
2012 case 'O':
2013 tmpreg= (opP->mode==DREG)
2014 ? 0x20+opP->reg-DATA
2015 : (get_num(opP->con1,40)&0x1F);
2016 install_operand(s[1],tmpreg);
2017 break;
2018
2019 case 'Q':
2020 tmpreg=get_num(opP->con1,10);
2021 if(tmpreg==8)
2022 tmpreg=0;
2023 install_operand(s[1],tmpreg);
2024 break;
2025
2026 case 'R':
2027 /* This depends on the fact that ADDR registers are
2028 eight more than their corresponding DATA regs, so
2029 the result will have the ADDR_REG bit set */
2030 install_operand(s[1],opP->reg-DATA);
2031 break;
2032
2033 case 's':
2034 if(opP->reg==FPI) tmpreg=0x1;
2035 else if(opP->reg==FPS) tmpreg=0x2;
2036 else if(opP->reg==FPC) tmpreg=0x4;
2037 else as_fatal("failed sanity check.");
2038 install_operand(s[1],tmpreg);
2039 break;
2040
2041 case 'S': /* Ignore it */
2042 break;
2043
2044 case 'T':
2045 install_operand(s[1],get_num(opP->con1,30));
2046 break;
2047
2048 case 'U': /* Ignore it */
2049 break;
2050
2051 case 'c':
2052 switch (opP->reg) {
2053 case NC: tmpreg = 0; break;
2054 case DC: tmpreg = 1; break;
2055 case IC: tmpreg = 2; break;
2056 case BC: tmpreg = 3; break;
2057 default:
2058 as_fatal("failed sanity check");
2059 } /* switch on cache token */
2060 install_operand(s[1], tmpreg);
2061 break;
2062 #ifndef NO_68851
2063 /* JF: These are out of order, I fear. */
2064 case 'f':
2065 switch (opP->reg) {
2066 case SFC:
2067 tmpreg=0;
2068 break;
2069 case DFC:
2070 tmpreg=1;
2071 break;
2072 default:
2073 as_fatal("failed sanity check.");
2074 }
2075 install_operand(s[1],tmpreg);
2076 break;
2077
2078 case 'P':
2079 switch(opP->reg) {
2080 case TC:
2081 tmpreg=0;
2082 break;
2083 case CAL:
2084 tmpreg=4;
2085 break;
2086 case VAL:
2087 tmpreg=5;
2088 break;
2089 case SCC:
2090 tmpreg=6;
2091 break;
2092 case AC:
2093 tmpreg=7;
2094 break;
2095 default:
2096 as_fatal("failed sanity check.");
2097 }
2098 install_operand(s[1],tmpreg);
2099 break;
2100
2101 case 'V':
2102 if (opP->reg == VAL)
2103 break;
2104 as_fatal("failed sanity check.");
2105
2106 case 'W':
2107 switch(opP->reg) {
2108
2109 case DRP:
2110 tmpreg=1;
2111 break;
2112 case SRP:
2113 tmpreg=2;
2114 break;
2115 case CRP:
2116 tmpreg=3;
2117 break;
2118 default:
2119 as_fatal("failed sanity check.");
2120 }
2121 install_operand(s[1],tmpreg);
2122 break;
2123
2124 case 'X':
2125 switch (opP->reg) {
2126 case BAD: case BAD+1: case BAD+2: case BAD+3:
2127 case BAD+4: case BAD+5: case BAD+6: case BAD+7:
2128 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2129 break;
2130
2131 case BAC: case BAC+1: case BAC+2: case BAC+3:
2132 case BAC+4: case BAC+5: case BAC+6: case BAC+7:
2133 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2134 break;
2135
2136 default:
2137 as_fatal("failed sanity check.");
2138 }
2139 install_operand(s[1], tmpreg);
2140 break;
2141 case 'Y':
2142 know(opP->reg == PSR);
2143 break;
2144 case 'Z':
2145 know(opP->reg == PCSR);
2146 break;
2147 #endif /* m68851 */
2148 case '_':
2149 tmpreg=get_num(opP->con1,80);
2150 install_operand(s[1], tmpreg);
2151 break;
2152 default:
2153 as_fatal("Internal error: Operand type %c unknown in line %s of file \"%s\"", s[0], __LINE__, __FILE__);
2154 }
2155 }
2156 /* By the time whe get here (FINALLY) the_ins contains the complete
2157 instruction, ready to be emitted. . . */
2158 } /* m68k_ip() */
2159
2160 /*
2161 * get_regs := '/' + ?
2162 * | '-' + <register>
2163 * | '-' + <register> + ?
2164 * | <empty>
2165 * ;
2166 *
2167
2168 * The idea here must be to scan in a set of registers but I don't
2169 * understand it. Looks awfully sloppy to me but I don't have any doc on
2170 * this format so...
2171
2172 *
2173 *
2174 */
2175
2176 static int get_regs(i,str,opP)
2177 int i;
2178 struct m68k_op *opP;
2179 char *str;
2180 {
2181 /* 26, 25, 24, 23-16, 15-8, 0-7 */
2182 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
2183 unsigned long cur_regs = 0;
2184 int reg1,
2185 reg2;
2186
2187 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
2188 else if(x==FPS) cur_regs|=(1<<25);\
2189 else if(x==FPC) cur_regs|=(1<<26);\
2190 else cur_regs|=(1<<(x-1)); }
2191
2192 reg1=i;
2193 for(;;) {
2194 if(*str=='/') {
2195 ADD_REG(reg1);
2196 str++;
2197 } else if(*str=='-') {
2198 str++;
2199 reg2=m68k_reg_parse(&str);
2200 if(reg2<DATA || reg2>=FPREG+8 || reg1==FPI || reg1==FPS || reg1==FPC) {
2201 opP->error="unknown register in register list";
2202 return FAIL;
2203 }
2204 while(reg1<=reg2) {
2205 ADD_REG(reg1);
2206 reg1++;
2207 }
2208 if(*str=='\0')
2209 break;
2210 } else if(*str=='\0') {
2211 ADD_REG(reg1);
2212 break;
2213 } else {
2214 opP->error="unknow character in register list";
2215 return FAIL;
2216 }
2217 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
2218 if (*str=='/')
2219 str ++;
2220 reg1=m68k_reg_parse(&str);
2221 if((reg1<DATA || reg1>=FPREG+8) && !(reg1==FPI || reg1==FPS || reg1==FPC)) {
2222 opP->error="unknown register in register list";
2223 return FAIL;
2224 }
2225 }
2226 opP->reg=cur_regs;
2227 return OK;
2228 } /* get_regs() */
2229
2230 static int reverse_16_bits(in)
2231 int in;
2232 {
2233 int out=0;
2234 int n;
2235
2236 static int mask[16] = {
2237 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2238 0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000
2239 };
2240 for(n=0;n<16;n++) {
2241 if(in&mask[n])
2242 out|=mask[15-n];
2243 }
2244 return out;
2245 } /* reverse_16_bits() */
2246
2247 static int reverse_8_bits(in)
2248 int in;
2249 {
2250 int out=0;
2251 int n;
2252
2253 static int mask[8] = {
2254 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2255 };
2256
2257 for(n=0;n<8;n++) {
2258 if(in&mask[n])
2259 out|=mask[7-n];
2260 }
2261 return out;
2262 } /* reverse_8_bits() */
2263
2264 static void install_operand(mode,val)
2265 int mode;
2266 int val;
2267 {
2268 switch(mode) {
2269 case 's':
2270 the_ins.opcode[0]|=val & 0xFF; /* JF FF is for M kludge */
2271 break;
2272 case 'd':
2273 the_ins.opcode[0]|=val<<9;
2274 break;
2275 case '1':
2276 the_ins.opcode[1]|=val<<12;
2277 break;
2278 case '2':
2279 the_ins.opcode[1]|=val<<6;
2280 break;
2281 case '3':
2282 the_ins.opcode[1]|=val;
2283 break;
2284 case '4':
2285 the_ins.opcode[2]|=val<<12;
2286 break;
2287 case '5':
2288 the_ins.opcode[2]|=val<<6;
2289 break;
2290 case '6':
2291 /* DANGER! This is a hack to force cas2l and cas2w cmds
2292 to be three words long! */
2293 the_ins.numo++;
2294 the_ins.opcode[2]|=val;
2295 break;
2296 case '7':
2297 the_ins.opcode[1]|=val<<7;
2298 break;
2299 case '8':
2300 the_ins.opcode[1]|=val<<10;
2301 break;
2302 #ifndef NO_68851
2303 case '9':
2304 the_ins.opcode[1]|=val<<5;
2305 break;
2306 #endif
2307
2308 case 't':
2309 the_ins.opcode[1]|=(val<<10)|(val<<7);
2310 break;
2311 case 'D':
2312 the_ins.opcode[1]|=(val<<12)|val;
2313 break;
2314 case 'g':
2315 the_ins.opcode[0]|=val=0xff;
2316 break;
2317 case 'i':
2318 the_ins.opcode[0]|=val<<9;
2319 break;
2320 case 'C':
2321 the_ins.opcode[1]|=val;
2322 break;
2323 case 'j':
2324 the_ins.opcode[1]|=val;
2325 the_ins.numo++; /* What a hack */
2326 break;
2327 case 'k':
2328 the_ins.opcode[1]|=val<<4;
2329 break;
2330 case 'b':
2331 case 'w':
2332 case 'l':
2333 break;
2334 case 'e':
2335 the_ins.opcode[0] |= (val << 6);
2336 break;
2337 case 'L':
2338 the_ins.opcode[1] = (val >> 16);
2339 the_ins.opcode[2] = val & 0xffff;
2340 break;
2341 case 'c':
2342 default:
2343 as_fatal("failed sanity check.");
2344 }
2345 } /* install_operand() */
2346
2347 static void install_gen_operand(mode,val)
2348 int mode;
2349 int val;
2350 {
2351 switch(mode) {
2352 case 's':
2353 the_ins.opcode[0]|=val;
2354 break;
2355 case 'd':
2356 /* This is a kludge!!! */
2357 the_ins.opcode[0]|=(val&0x07)<<9|(val&0x38)<<3;
2358 break;
2359 case 'b':
2360 case 'w':
2361 case 'l':
2362 case 'f':
2363 case 'F':
2364 case 'x':
2365 case 'p':
2366 the_ins.opcode[0]|=val;
2367 break;
2368 /* more stuff goes here */
2369 default:
2370 as_fatal("failed sanity check.");
2371 }
2372 } /* install_gen_operand() */
2373
2374 /*
2375 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2376 * then deal with the bitfield hack.
2377 */
2378
2379 static char *crack_operand(str,opP)
2380 register char *str;
2381 register struct m68k_op *opP;
2382 {
2383 register int parens;
2384 register int c;
2385 register char *beg_str;
2386
2387 if(!str) {
2388 return str;
2389 }
2390 beg_str=str;
2391 for(parens=0;*str && (parens>0 || notend(str));str++) {
2392 if(*str=='(') parens++;
2393 else if(*str==')') {
2394 if(!parens) { /* ERROR */
2395 opP->error="Extra )";
2396 return str;
2397 }
2398 --parens;
2399 }
2400 }
2401 if(!*str && parens) { /* ERROR */
2402 opP->error="Missing )";
2403 return str;
2404 }
2405 c= *str;
2406 *str='\0';
2407 if(m68k_ip_op(beg_str,opP)==FAIL) {
2408 *str=c;
2409 return str;
2410 }
2411 *str=c;
2412 if(c=='}')
2413 c= *++str; /* JF bitfield hack */
2414 if(c) {
2415 c= *++str;
2416 if(!c)
2417 as_bad("Missing operand");
2418 }
2419 return str;
2420 }
2421
2422 /* See the comment up above where the #define notend(... is */
2423 #if 0
2424 notend(s)
2425 char *s;
2426 {
2427 if(*s==',') return 0;
2428 if(*s=='{' || *s=='}')
2429 return 0;
2430 if(*s!=':') return 1;
2431 /* This kludge here is for the division cmd, which is a kludge */
2432 if(index("aAdD#",s[1])) return 0;
2433 return 1;
2434 }
2435 #endif
2436
2437 /* This is the guts of the machine-dependent assembler. STR points to a
2438 machine dependent instruction. This function is supposed to emit
2439 the frags/bytes it assembles to.
2440 */
2441
2442 void
2443 insert_reg(regname, regnum)
2444 char *regname;
2445 int regnum;
2446 {
2447 char buf[100];
2448 int i;
2449 symbol_table_insert(symbol_new(regname, SEG_REGISTER, regnum, &zero_address_frag));
2450
2451 for (i = 0; regname[i]; i++)
2452 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2453 buf[i] = '\0';
2454
2455 symbol_table_insert(symbol_new(buf, SEG_REGISTER, regnum, &zero_address_frag));
2456 }
2457
2458 static struct {
2459 char *name;
2460 int number;
2461 } init_table[] =
2462 {
2463 "d0", DATA0,
2464 "d1", DATA1,
2465 "d2", DATA2,
2466 "d3", DATA3,
2467 "d4", DATA4,
2468 "d5", DATA5,
2469 "d6", DATA6,
2470 "d7", DATA7,
2471 "a0", ADDR0,
2472 "a1", ADDR1,
2473 "a2", ADDR2,
2474 "a3", ADDR3,
2475 "a4", ADDR4,
2476 "a5", ADDR5,
2477 "a6", ADDR6,
2478 "fp", ADDR6,
2479 "a7", ADDR7,
2480 "sp", ADDR7,
2481 "fp0", FP0,
2482 "fp1", FP1,
2483 "fp2", FP2,
2484 "fp3", FP3,
2485 "fp4", FP4,
2486 "fp5", FP5,
2487 "fp6", FP6,
2488 "fp7", FP7,
2489 "fpi", FPI,
2490 "fpiar", FPI,
2491 "fpc", FPI,
2492 "fps", FPS,
2493 "fpsr", FPS,
2494 "fpc", FPC,
2495 "fpcr", FPC,
2496
2497 "cop0", COP0,
2498 "cop1", COP1,
2499 "cop2", COP2,
2500 "cop3", COP3,
2501 "cop4", COP4,
2502 "cop5", COP5,
2503 "cop6", COP6,
2504 "cop7", COP7,
2505 "pc", PC,
2506 "zpc", ZPC,
2507 "sr", SR,
2508
2509 "ccr", CCR,
2510 "cc", CCR,
2511
2512 "usp", USP,
2513 "isp", ISP,
2514 "sfc", SFC,
2515 "dfc", DFC,
2516 "cacr", CACR,
2517 "caar", CAAR,
2518
2519 "vbr", VBR,
2520
2521 "msp", MSP,
2522 "itt0", ITT0,
2523 "itt1", ITT1,
2524 "dtt0", DTT0,
2525 "dtt1", DTT1,
2526 "mmusr", MMUSR,
2527 "tc", TC,
2528 "srp", SRP,
2529 "urp", URP,
2530
2531 #ifndef NO_68851
2532 "ac", AC,
2533 "bc", BC,
2534 "cal", CAL,
2535 "crp", CRP,
2536 "drp", DRP,
2537 "pcsr", PCSR,
2538 "psr", PSR,
2539 "scc", SCC,
2540 "val", VAL,
2541 "bad0", BAD0,
2542 "bad1", BAD1,
2543 "bad2", BAD2,
2544 "bad3", BAD3,
2545 "bad4", BAD4,
2546 "bad5", BAD5,
2547 "bad6", BAD6,
2548 "bad7", BAD7,
2549 "bac0", BAC0,
2550 "bac1", BAC1,
2551 "bac2", BAC2,
2552 "bac3", BAC3,
2553 "bac4", BAC4,
2554 "bac5", BAC5,
2555 "bac6", BAC6,
2556 "bac7", BAC7,
2557 #endif
2558
2559 "ic", IC,
2560 "dc", DC,
2561 "nc", NC,
2562
2563 0,
2564
2565 };
2566
2567
2568 void
2569 init_regtable()
2570 {
2571 int i;
2572 for (i = 0; init_table[i].name; i++)
2573 {
2574 insert_reg(init_table[i].name, init_table[i].number);
2575 }
2576 }
2577
2578
2579 void
2580 md_assemble(str)
2581 char *str;
2582 {
2583 char *er;
2584 short *fromP;
2585 char *toP = NULL;
2586 int m,n = 0;
2587 char *to_beg_P;
2588 int shorts_this_frag;
2589
2590
2591 if (current_architecture == 0)
2592 current_architecture = (m68020
2593 #ifndef NO_68881
2594 | m68881
2595 #endif
2596 #ifndef NO_68851
2597 | m68851
2598 #endif
2599 );
2600 /* If only float and mmu were specified, default cpu. */
2601 else if (cpu_of_arch (current_architecture) == 0)
2602 current_architecture |= m68020;
2603
2604 memset((char *)(&the_ins), '\0', sizeof(the_ins)); /* JF for paranoia sake */
2605 m68k_ip(str);
2606 er=the_ins.error;
2607 if(!er) {
2608 for(n=the_ins.numargs;n;--n)
2609 if(the_ins.operands[n].error) {
2610 er=the_ins.operands[n].error;
2611 break;
2612 }
2613 }
2614 if(er) {
2615 as_bad("%s -- statement `%s' ignored",er,str);
2616 return;
2617 }
2618
2619 if(the_ins.nfrag==0) { /* No frag hacking involved; just put it out */
2620 toP=frag_more(2*the_ins.numo);
2621 fromP= &the_ins.opcode[0];
2622 for(m=the_ins.numo;m;--m) {
2623 md_number_to_chars(toP,(long)(*fromP),2);
2624 toP+=2;
2625 fromP++;
2626 }
2627 /* put out symbol-dependent info */
2628 for(m=0;m<the_ins.nrel;m++) {
2629 switch(the_ins.reloc[m].wid) {
2630 case 'B':
2631 n=1;
2632 break;
2633 case 'b':
2634 n=1;
2635 break;
2636 case '3':
2637 n=2;
2638 break;
2639 case 'w':
2640 n=2;
2641 break;
2642 case 'l':
2643 n=4;
2644 break;
2645 default:
2646 as_fatal("Don't know how to figure width of %c in md_assemble()",the_ins.reloc[m].wid);
2647 }
2648
2649 fix_new(frag_now,
2650 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
2651 n,
2652 the_ins.reloc[m].add,
2653 the_ins.reloc[m].sub,
2654 the_ins.reloc[m].off,
2655 the_ins.reloc[m].pcrel,
2656 NO_RELOC);
2657 }
2658 return;
2659 }
2660
2661 /* There's some frag hacking */
2662 for(n=0,fromP= &the_ins.opcode[0];n<the_ins.nfrag;n++) {
2663 int wid;
2664
2665 if(n==0) wid=2*the_ins.fragb[n].fragoff;
2666 else wid=2*(the_ins.numo-the_ins.fragb[n-1].fragoff);
2667 toP=frag_more(wid);
2668 to_beg_P=toP;
2669 shorts_this_frag=0;
2670 for(m=wid/2;m;--m) {
2671 md_number_to_chars(toP,(long)(*fromP),2);
2672 toP+=2;
2673 fromP++;
2674 shorts_this_frag++;
2675 }
2676 for(m=0;m<the_ins.nrel;m++) {
2677 if((the_ins.reloc[m].n)>= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */) {
2678 the_ins.reloc[m].n-= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */;
2679 break;
2680 }
2681 wid=the_ins.reloc[m].wid;
2682 if(wid==0)
2683 continue;
2684 the_ins.reloc[m].wid=0;
2685 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
2686
2687 fix_new(frag_now,
2688 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
2689 wid,
2690 the_ins.reloc[m].add,
2691 the_ins.reloc[m].sub,
2692 the_ins.reloc[m].off,
2693 the_ins.reloc[m].pcrel,
2694 NO_RELOC);
2695 }
2696 /* know(the_ins.fragb[n].fadd); */
2697 (void)frag_var(rs_machine_dependent,10,0,(relax_substateT)(the_ins.fragb[n].fragty),
2698 the_ins.fragb[n].fadd,the_ins.fragb[n].foff,to_beg_P);
2699 }
2700 n=(the_ins.numo-the_ins.fragb[n-1].fragoff);
2701 shorts_this_frag=0;
2702 if(n) {
2703 toP=frag_more(n*sizeof(short));
2704 while(n--) {
2705 md_number_to_chars(toP,(long)(*fromP),2);
2706 toP+=2;
2707 fromP++;
2708 shorts_this_frag++;
2709 }
2710 }
2711 for(m=0;m<the_ins.nrel;m++) {
2712 int wid;
2713
2714 wid=the_ins.reloc[m].wid;
2715 if(wid==0)
2716 continue;
2717 the_ins.reloc[m].wid=0;
2718 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
2719
2720 fix_new(frag_now,
2721 (the_ins.reloc[m].n + toP-frag_now->fr_literal)-/* the_ins.numo */ shorts_this_frag*2,
2722 wid,
2723 the_ins.reloc[m].add,
2724 the_ins.reloc[m].sub,
2725 the_ins.reloc[m].off,
2726 the_ins.reloc[m].pcrel,
2727 NO_RELOC);
2728 }
2729 }
2730
2731
2732
2733
2734
2735 void
2736 md_begin()
2737 {
2738 /*
2739 * md_begin -- set up hash tables with 68000 instructions.
2740 * similar to what the vax assembler does. ---phr
2741 */
2742 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
2743 a copy of it at runtime, adding in the information we want but isn't
2744 there. I think it'd be better to have an awk script hack the table
2745 at compile time. Or even just xstr the table and use it as-is. But
2746 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
2747 names. */
2748
2749 register const struct m68k_opcode *ins;
2750 register struct m68k_incant *hack,
2751 *slak;
2752 register char *retval = 0; /* empty string, or error msg text */
2753 register unsigned int i;
2754 register char c;
2755
2756 if ((op_hash = hash_new()) == NULL)
2757 as_fatal("Virtual memory exhausted");
2758
2759 obstack_begin(&robyn,4000);
2760 for (ins = m68k_opcodes; ins < endop; ins++) {
2761 hack=slak=(struct m68k_incant *)obstack_alloc(&robyn,sizeof(struct m68k_incant));
2762 do {
2763 /* we *could* ignore insns that don't match our
2764 arch here but just leaving them out of the
2765 hash. */
2766 slak->m_operands=ins->args;
2767 slak->m_opnum=strlen(slak->m_operands)/2;
2768 slak->m_arch = ins->arch;
2769 slak->m_opcode=ins->opcode;
2770 /* This is kludgey */
2771 slak->m_codenum=((ins->match)&0xffffL) ? 2 : 1;
2772 if((ins+1)!=endop && !strcmp(ins->name,(ins+1)->name)) {
2773 slak->m_next=(struct m68k_incant *) obstack_alloc(&robyn,sizeof(struct m68k_incant));
2774 ins++;
2775 } else
2776 slak->m_next=0;
2777 slak=slak->m_next;
2778 } while(slak);
2779
2780 retval = hash_insert (op_hash, ins->name,(char *)hack);
2781 /* Didn't his mommy tell him about null pointers? */
2782 if(retval && *retval)
2783 as_fatal("Internal Error: Can't hash %s: %s",ins->name,retval);
2784 }
2785
2786 for (i = 0; i < sizeof(mklower_table) ; i++)
2787 mklower_table[i] = (isupper(c = (char) i)) ? tolower(c) : c;
2788
2789 for (i = 0 ; i < sizeof(notend_table) ; i++) {
2790 notend_table[i] = 0;
2791 alt_notend_table[i] = 0;
2792 }
2793 notend_table[','] = 1;
2794 notend_table['{'] = 1;
2795 notend_table['}'] = 1;
2796 alt_notend_table['a'] = 1;
2797 alt_notend_table['A'] = 1;
2798 alt_notend_table['d'] = 1;
2799 alt_notend_table['D'] = 1;
2800 alt_notend_table['#'] = 1;
2801 alt_notend_table['f'] = 1;
2802 alt_notend_table['F'] = 1;
2803 #ifdef REGISTER_PREFIX
2804 alt_notend_table[REGISTER_PREFIX] = 1;
2805 #endif
2806
2807 init_regtable();
2808 }
2809
2810 #if 0
2811 #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
2812 || (*s == ':' && strchr("aAdD#", s[1]))) \
2813 ? 0 : 1)
2814 #endif
2815
2816 /* This funciton is called once, before the assembler exits. It is
2817 supposed to do any final cleanup for this part of the assembler.
2818 */
2819 void
2820 md_end()
2821 {
2822 }
2823
2824 /* Equal to MAX_PRECISION in atof-ieee.c */
2825 #define MAX_LITTLENUMS 6
2826
2827 /* Turn a string in input_line_pointer into a floating point constant of type
2828 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2829 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2830 */
2831 char *
2832 md_atof(type,litP,sizeP)
2833 char type;
2834 char *litP;
2835 int *sizeP;
2836 {
2837 int prec;
2838 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2839 LITTLENUM_TYPE *wordP;
2840 char *t;
2841 char *atof_ieee();
2842
2843 switch(type) {
2844 case 'f':
2845 case 'F':
2846 case 's':
2847 case 'S':
2848 prec = 2;
2849 break;
2850
2851 case 'd':
2852 case 'D':
2853 case 'r':
2854 case 'R':
2855 prec = 4;
2856 break;
2857
2858 case 'x':
2859 case 'X':
2860 prec = 6;
2861 break;
2862
2863 case 'p':
2864 case 'P':
2865 prec = 6;
2866 break;
2867
2868 default:
2869 *sizeP=0;
2870 return "Bad call to MD_ATOF()";
2871 }
2872 t=atof_ieee(input_line_pointer,type,words);
2873 if(t)
2874 input_line_pointer=t;
2875
2876 *sizeP=prec * sizeof(LITTLENUM_TYPE);
2877 for(wordP=words;prec--;) {
2878 md_number_to_chars(litP,(long)(*wordP++),sizeof(LITTLENUM_TYPE));
2879 litP+=sizeof(LITTLENUM_TYPE);
2880 }
2881 return ""; /* Someone should teach Dean about null pointers */
2882 }
2883
2884 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
2885 for use in the a.out file, and stores them in the array pointed to by buf.
2886 This knows about the endian-ness of the target machine and does
2887 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
2888 2 (short) and 4 (long) Floating numbers are put out as a series of
2889 LITTLENUMS (shorts, here at least)
2890 */
2891 void
2892 md_number_to_chars(buf,val,n)
2893 char *buf;
2894 long val;
2895 int n;
2896 {
2897 switch(n) {
2898 case 1:
2899 *buf++=val;
2900 break;
2901 case 2:
2902 *buf++=(val>>8);
2903 *buf++=val;
2904 break;
2905 case 4:
2906 *buf++=(val>>24);
2907 *buf++=(val>>16);
2908 *buf++=(val>>8);
2909 *buf++=val;
2910 break;
2911 default:
2912 as_fatal("failed sanity check.");
2913 }
2914 }
2915
2916 void
2917 md_apply_fix(fixP, val)
2918 fixS *fixP;
2919 long val;
2920 {
2921 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2922
2923 switch(fixP->fx_size) {
2924 case 1:
2925 *buf++=val;
2926 break;
2927 case 2:
2928 *buf++=(val>>8);
2929 *buf++=val;
2930 break;
2931 case 4:
2932 *buf++=(val>>24);
2933 *buf++=(val>>16);
2934 *buf++=(val>>8);
2935 *buf++=val;
2936 break;
2937 default:
2938 BAD_CASE (fixP->fx_size);
2939 }
2940 }
2941
2942
2943 /* *fragP has been relaxed to its final size, and now needs to have
2944 the bytes inside it modified to conform to the new size There is UGLY
2945 MAGIC here. ..
2946 */
2947 void
2948 md_convert_frag(headers, fragP)
2949 object_headers *headers;
2950 register fragS *fragP;
2951 {
2952 long disp;
2953 long ext = 0;
2954
2955 /* Address in object code of the displacement. */
2956 register int object_address = fragP -> fr_fix + fragP -> fr_address;
2957
2958 #ifdef IBM_COMPILER_SUX
2959 /* This is wrong but it convinces the native rs6000 compiler to
2960 generate the code we want. */
2961 register char *buffer_address = fragP -> fr_literal;
2962 buffer_address += fragP -> fr_fix;
2963 #else /* IBM_COMPILER_SUX */
2964 /* Address in gas core of the place to store the displacement. */
2965 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
2966 #endif /* IBM_COMPILER_SUX */
2967
2968 /* No longer true: know(fragP->fr_symbol); */
2969
2970 /* The displacement of the address, from current location. */
2971 disp = fragP->fr_symbol ? S_GET_VALUE(fragP->fr_symbol) : 0;
2972 disp = (disp + fragP->fr_offset) - object_address;
2973
2974 switch(fragP->fr_subtype) {
2975 case TAB(BCC68000,BYTE):
2976 case TAB(BRANCH,BYTE):
2977 know(issbyte(disp));
2978 if(disp==0)
2979 as_bad("short branch with zero offset: use :w");
2980 fragP->fr_opcode[1]=disp;
2981 ext=0;
2982 break;
2983 case TAB(DBCC,SHORT):
2984 know(issword(disp));
2985 ext=2;
2986 break;
2987 case TAB(BCC68000,SHORT):
2988 case TAB(BRANCH,SHORT):
2989 know(issword(disp));
2990 fragP->fr_opcode[1]=0x00;
2991 ext=2;
2992 break;
2993 case TAB(BRANCH,LONG):
2994 if (cpu_of_arch(current_architecture) < m68020) {
2995 if (fragP->fr_opcode[0]==0x61) {
2996 fragP->fr_opcode[0]= 0x4E;
2997 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
2998 subseg_change(SEG_TEXT, 0);
2999
3000 fix_new(fragP,
3001 fragP->fr_fix,
3002 4,
3003 fragP->fr_symbol,
3004 0,
3005 fragP->fr_offset,
3006 0,
3007 NO_RELOC);
3008
3009 fragP->fr_fix+=4;
3010 ext=0;
3011 } else if (fragP->fr_opcode[0]==0x60) {
3012 fragP->fr_opcode[0]= 0x4E;
3013 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3014 subseg_change(SEG_TEXT, 0);
3015 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset,0,
3016 NO_RELOC);
3017 fragP->fr_fix+=4;
3018 ext=0;
3019 } else {
3020 as_bad("Long branch offset not supported.");
3021 }
3022 } else {
3023 fragP->fr_opcode[1]=0xff;
3024 ext=4;
3025 }
3026 break;
3027 case TAB(BCC68000,LONG):
3028 /* only Bcc 68000 instructions can come here */
3029 /* change bcc into b!cc/jmp absl long */
3030 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3031 fragP->fr_opcode[1] = 0x6; /* branch offset = 6 */
3032
3033 /* JF: these used to be fr_opcode[2,3], but they may be in a
3034 different frag, in which case refering to them is a no-no.
3035 Only fr_opcode[0,1] are guaranteed to work. */
3036 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3037 *buffer_address++ = 0xf9;
3038 fragP->fr_fix += 2; /* account for jmp instruction */
3039 subseg_change(SEG_TEXT,0);
3040 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3041 fragP->fr_offset,0,
3042 NO_RELOC);
3043 fragP->fr_fix += 4;
3044 ext=0;
3045 break;
3046 case TAB(DBCC,LONG):
3047 /* only DBcc 68000 instructions can come here */
3048 /* change dbcc into dbcc/jmp absl long */
3049 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3050 *buffer_address++ = 0x00; /* branch offset = 4 */
3051 *buffer_address++ = 0x04;
3052 *buffer_address++ = 0x60; /* put in bra pc+6 */
3053 *buffer_address++ = 0x06;
3054 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3055 *buffer_address++ = 0xf9;
3056
3057 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3058 subseg_change(SEG_TEXT,0);
3059 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3060 fragP->fr_offset,0,
3061 NO_RELOC);
3062 fragP->fr_fix += 4;
3063 ext=0;
3064 break;
3065 case TAB(FBRANCH,SHORT):
3066 know((fragP->fr_opcode[1]&0x40)==0);
3067 ext=2;
3068 break;
3069 case TAB(FBRANCH,LONG):
3070 fragP->fr_opcode[1]|=0x40; /* Turn on LONG bit */
3071 ext=4;
3072 break;
3073 case TAB(PCREL,SHORT):
3074 ext=2;
3075 break;
3076 case TAB(PCREL,LONG):
3077 /* The thing to do here is force it to ABSOLUTE LONG, since
3078 PCREL is really trying to shorten an ABSOLUTE address anyway */
3079 /* JF FOO This code has not been tested */
3080 subseg_change(SEG_TEXT,0);
3081 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3082 if((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3083 as_bad("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
3084 fragP->fr_opcode[0],fragP->fr_address);
3085 fragP->fr_opcode[1]&= ~0x3F;
3086 fragP->fr_opcode[1]|=0x39; /* Mode 7.1 */
3087 fragP->fr_fix+=4;
3088 /* md_number_to_chars(buffer_address,
3089 (long)(fragP->fr_symbol->sy_value + fragP->fr_offset),
3090 4); */
3091 ext=0;
3092 break;
3093 case TAB(PCLEA,SHORT):
3094 subseg_change(SEG_TEXT,0);
3095 fix_new(fragP,(int)(fragP->fr_fix),2,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset,1,
3096 NO_RELOC);
3097 fragP->fr_opcode[1] &= ~0x3F;
3098 fragP->fr_opcode[1] |= 0x3A;
3099 ext=2;
3100 break;
3101 case TAB(PCLEA,LONG):
3102 subseg_change(SEG_TEXT,0);
3103 fix_new(fragP,(int)(fragP->fr_fix)+2,4,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset+2,1,
3104 NO_RELOC);
3105 *buffer_address++ = 0x01;
3106 *buffer_address++ = 0x70;
3107 fragP->fr_fix+=2;
3108 /* buffer_address+=2; */
3109 ext=4;
3110 break;
3111
3112 } /* switch on subtype */
3113
3114 if (ext) {
3115 md_number_to_chars(buffer_address, (long) disp, (int) ext);
3116 fragP->fr_fix += ext;
3117 /* H_SET_TEXT_SIZE(headers, H_GET_TEXT_SIZE(headers) + ext); */
3118 } /* if extending */
3119
3120 return;
3121 } /* md_convert_frag() */
3122
3123 /* Force truly undefined symbols to their maximum size, and generally set up
3124 the frag list to be relaxed
3125 */
3126 int md_estimate_size_before_relax(fragP, segment)
3127 register fragS *fragP;
3128 segT segment;
3129 {
3130 int old_fix;
3131 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3132
3133 old_fix = fragP->fr_fix;
3134
3135 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3136 switch (fragP->fr_subtype) {
3137
3138 case TAB(BRANCH,SZ_UNDEF): {
3139 if((fragP->fr_symbol != NULL) /* Not absolute */
3140 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3141 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),BYTE);
3142 break;
3143 } else if((fragP->fr_symbol == 0) || (cpu_of_arch(current_architecture) < m68020)) {
3144 /* On 68000, or for absolute value, switch to abs long */
3145 /* FIXME, we should check abs val, pick short or long */
3146 if(fragP->fr_opcode[0]==0x61) {
3147 fragP->fr_opcode[0]= 0x4E;
3148 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3149 subseg_change(SEG_TEXT, 0);
3150 fix_new(fragP, fragP->fr_fix, 4,
3151 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3152 fragP->fr_fix+=4;
3153 frag_wane(fragP);
3154 } else if(fragP->fr_opcode[0]==0x60) {
3155 fragP->fr_opcode[0]= 0x4E;
3156 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3157 subseg_change(SEG_TEXT, 0);
3158 fix_new(fragP, fragP->fr_fix, 4,
3159 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3160 fragP->fr_fix+=4;
3161 frag_wane(fragP);
3162 } else {
3163 as_warn("Long branch offset to extern symbol not supported.");
3164 }
3165 } else { /* Symbol is still undefined. Make it simple */
3166 fix_new(fragP, (int)(fragP->fr_fix), 4, fragP->fr_symbol,
3167 (symbolS *)0, fragP->fr_offset+4, 1, NO_RELOC);
3168 fragP->fr_fix+=4;
3169 fragP->fr_opcode[1]=0xff;
3170 frag_wane(fragP);
3171 break;
3172 }
3173
3174 break;
3175 } /* case TAB(BRANCH,SZ_UNDEF) */
3176
3177 case TAB(FBRANCH,SZ_UNDEF): {
3178 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3179 fragP->fr_subtype = TAB(FBRANCH,SHORT);
3180 fragP->fr_var += 2;
3181 } else {
3182 fragP->fr_subtype = TAB(FBRANCH,LONG);
3183 fragP->fr_var += 4;
3184 }
3185 break;
3186 } /* TAB(FBRANCH,SZ_UNDEF) */
3187
3188 case TAB(PCREL,SZ_UNDEF): {
3189 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3190 fragP->fr_subtype = TAB(PCREL,SHORT);
3191 fragP->fr_var += 2;
3192 } else {
3193 fragP->fr_subtype = TAB(PCREL,LONG);
3194 fragP->fr_var += 4;
3195 }
3196 break;
3197 } /* TAB(PCREL,SZ_UNDEF) */
3198
3199 case TAB(BCC68000,SZ_UNDEF): {
3200 if((fragP->fr_symbol != NULL)
3201 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3202 fragP->fr_subtype=TAB(BCC68000,BYTE);
3203 break;
3204 }
3205 /* only Bcc 68000 instructions can come here */
3206 /* change bcc into b!cc/jmp absl long */
3207 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3208 if(flagseen['l']) {
3209 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3210 /* JF: these were fr_opcode[2,3] */
3211 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3212 buffer_address[1] = 0xf8;
3213 fragP->fr_fix += 2; /* account for jmp instruction */
3214 subseg_change(SEG_TEXT,0);
3215 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
3216 fragP->fr_offset, 0, NO_RELOC);
3217 fragP->fr_fix += 2;
3218 } else {
3219 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3220 /* JF: these were fr_opcode[2,3] */
3221 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3222 buffer_address[1] = 0xf9;
3223 fragP->fr_fix += 2; /* account for jmp instruction */
3224 subseg_change(SEG_TEXT,0);
3225 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3226 fragP->fr_offset, 0, NO_RELOC);
3227 fragP->fr_fix += 4;
3228 }
3229 frag_wane(fragP);
3230 break;
3231 } /* case TAB(BCC68000,SZ_UNDEF) */
3232
3233 case TAB(DBCC,SZ_UNDEF): {
3234 if (fragP->fr_symbol != NULL && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3235 fragP->fr_subtype=TAB(DBCC,SHORT);
3236 fragP->fr_var+=2;
3237 break;
3238 }
3239 /* only DBcc 68000 instructions can come here */
3240 /* change dbcc into dbcc/jmp absl long */
3241 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3242 buffer_address[0] = 0x00; /* branch offset = 4 */
3243 buffer_address[1] = 0x04;
3244 buffer_address[2] = 0x60; /* put in bra pc + ... */
3245
3246 if(flagseen['l']) {
3247 /* JF: these were fr_opcode[5-7] */
3248 buffer_address[3] = 0x04; /* plus 4 */
3249 buffer_address[4] = 0x4e;/* Put in Jump Word */
3250 buffer_address[5] = 0xf8;
3251 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3252 subseg_change(SEG_TEXT,0);
3253 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
3254
3255
3256 fragP->fr_offset, 0, NO_RELOC);
3257 fragP->fr_fix += 2;
3258 } else {
3259 /* JF: these were fr_opcode[5-7] */
3260 buffer_address[3] = 0x06; /* Plus 6 */
3261 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3262 buffer_address[5] = 0xf9;
3263 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3264 subseg_change(SEG_TEXT,0);
3265 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3266 fragP->fr_offset, 0, NO_RELOC);
3267 fragP->fr_fix += 4;
3268 }
3269
3270 frag_wane(fragP);
3271 break;
3272 } /* case TAB(DBCC,SZ_UNDEF) */
3273
3274 case TAB(PCLEA,SZ_UNDEF): {
3275 if ((S_GET_SEGMENT(fragP->fr_symbol))==segment || flagseen['l']) {
3276 fragP->fr_subtype=TAB(PCLEA,SHORT);
3277 fragP->fr_var+=2;
3278 } else {
3279 fragP->fr_subtype=TAB(PCLEA,LONG);
3280 fragP->fr_var+=6;
3281 }
3282 break;
3283 } /* TAB(PCLEA,SZ_UNDEF) */
3284
3285 default:
3286 break;
3287
3288 } /* switch on subtype looking for SZ_UNDEF's. */
3289
3290 /* now that SZ_UNDEF are taken care of, check others */
3291 switch (fragP->fr_subtype) {
3292 case TAB(BCC68000,BYTE):
3293 case TAB(BRANCH,BYTE):
3294 /* We can't do a short jump to the next instruction,
3295 so we force word mode. */
3296 if (fragP->fr_symbol && S_GET_VALUE(fragP->fr_symbol)==0 &&
3297 fragP->fr_symbol->sy_frag==fragP->fr_next) {
3298 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),SHORT);
3299 fragP->fr_var+=2;
3300 }
3301 break;
3302 default:
3303 break;
3304 }
3305 return fragP->fr_var + fragP->fr_fix - old_fix;
3306 }
3307
3308 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3309 /* the bit-field entries in the relocation_info struct plays hell
3310 with the byte-order problems of cross-assembly. So as a hack,
3311 I added this mach. dependent ri twiddler. Ugly, but it gets
3312 you there. -KWK */
3313 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3314 are symbolnum, most sig. byte first. Last byte is broken up with
3315 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3316 nibble as nuthin. (on Sun 3 at least) */
3317 /* Translate the internal relocation information into target-specific
3318 format. */
3319 #ifdef comment
3320 void
3321 md_ri_to_chars(the_bytes, ri)
3322 char *the_bytes;
3323 struct reloc_info_generic *ri;
3324 {
3325 /* this is easy */
3326 md_number_to_chars(the_bytes, ri->r_address, 4);
3327 /* now the fun stuff */
3328 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3329 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3330 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3331 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3332 ((ri->r_extern << 4) & 0x10));
3333 }
3334 #endif /* comment */
3335
3336 void tc_aout_fix_to_chars(where, fixP, segment_address_in_file)
3337 char *where;
3338 fixS *fixP;
3339 relax_addressT segment_address_in_file;
3340 {
3341 /*
3342 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3343 * Out: GNU LD relocation length code: 0, 1, or 2.
3344 */
3345
3346 static unsigned char nbytes_r_length [] = { 42, 0, 1, 42, 2 };
3347 long r_symbolnum;
3348
3349 know(fixP->fx_addsy != NULL);
3350
3351 md_number_to_chars(where,
3352 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3353 4);
3354
3355 r_symbolnum = (S_IS_DEFINED(fixP->fx_addsy)
3356 ? S_GET_TYPE(fixP->fx_addsy)
3357 : fixP->fx_addsy->sy_number);
3358
3359 where[4] = (r_symbolnum >> 16) & 0x0ff;
3360 where[5] = (r_symbolnum >> 8) & 0x0ff;
3361 where[6] = r_symbolnum & 0x0ff;
3362 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3363 (((!S_IS_DEFINED(fixP->fx_addsy)) << 4) & 0x10));
3364
3365 return;
3366 } /* tc_aout_fix_to_chars() */
3367
3368 #endif /* OBJ_AOUT or OBJ_BOUT */
3369
3370 #ifndef WORKING_DOT_WORD
3371 const int md_short_jump_size = 4;
3372 const int md_long_jump_size = 6;
3373
3374 void
3375 md_create_short_jump(ptr,from_addr,to_addr,frag,to_symbol)
3376 char *ptr;
3377 long from_addr,
3378 to_addr;
3379 fragS *frag;
3380 symbolS *to_symbol;
3381 {
3382 long offset;
3383
3384 offset = to_addr - (from_addr+2);
3385
3386 md_number_to_chars(ptr ,(long)0x6000,2);
3387 md_number_to_chars(ptr+2,(long)offset,2);
3388 }
3389
3390 void
3391 md_create_long_jump(ptr,from_addr,to_addr,frag,to_symbol)
3392 char *ptr;
3393 long from_addr,
3394 to_addr;
3395 fragS *frag;
3396 symbolS *to_symbol;
3397 {
3398 long offset;
3399
3400 if (cpu_of_arch(current_architecture) < m68020) {
3401 offset=to_addr-S_GET_VALUE(to_symbol);
3402 md_number_to_chars(ptr ,(long)0x4EF9,2);
3403 md_number_to_chars(ptr+2,(long)offset,4);
3404 fix_new(frag,(ptr+2)-frag->fr_literal,4,to_symbol,(symbolS *)0,(long)0,0,
3405 NO_RELOC);
3406 } else {
3407 offset=to_addr - (from_addr+2);
3408 md_number_to_chars(ptr ,(long)0x60ff,2);
3409 md_number_to_chars(ptr+2,(long)offset,4);
3410 }
3411 }
3412
3413 #endif
3414 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
3415
3416 0: Everything is OK
3417 10: Absolute 1:8 only
3418 20: Absolute 0:7 only
3419 30: absolute 0:15 only
3420 40: Absolute 0:31 only
3421 50: absolute 0:127 only
3422 55: absolute -64:63 only
3423 60: absolute -128:127 only
3424 70: absolute 0:4095 only
3425 80: No bignums
3426
3427 */
3428
3429 static int get_num(exp,ok)
3430 struct m68k_exp *exp;
3431 int ok;
3432 {
3433 #ifdef TEST2
3434 long l = 0;
3435
3436 if(!exp->e_beg)
3437 return 0;
3438 if(*exp->e_beg=='0') {
3439 if(exp->e_beg[1]=='x')
3440 sscanf(exp->e_beg+2,"%x",&l);
3441 else
3442 sscanf(exp->e_beg+1,"%O",&l);
3443 return l;
3444 }
3445 return atol(exp->e_beg);
3446 #else
3447 char *save_in;
3448 char c_save;
3449
3450 if(!exp) {
3451 /* Can't do anything */
3452 return 0;
3453 }
3454 if(!exp->e_beg || !exp->e_end) {
3455 seg(exp)=SEG_ABSOLUTE;
3456 adds(exp)=0;
3457 subs(exp)=0;
3458 offs(exp)= (ok==10) ? 1 : 0;
3459 as_warn("Null expression defaults to %ld",offs(exp));
3460 return 0;
3461 }
3462
3463 exp->e_siz=0;
3464 if(/* ok!=80 && */exp->e_end[-1]==':' && (exp->e_end-exp->e_beg)>=2) {
3465 switch(exp->e_end[0]) {
3466 case 's':
3467 case 'S':
3468 case 'b':
3469 case 'B':
3470 exp->e_siz=1;
3471 break;
3472 case 'w':
3473 case 'W':
3474 exp->e_siz=2;
3475 break;
3476 case 'l':
3477 case 'L':
3478 exp->e_siz=3;
3479 break;
3480 default:
3481 as_bad("Unknown size for expression \"%c\"",exp->e_end[0]);
3482 }
3483 exp->e_end-=2;
3484 }
3485 c_save=exp->e_end[1];
3486 exp->e_end[1]='\0';
3487 save_in=input_line_pointer;
3488 input_line_pointer=exp->e_beg;
3489 switch(expression(&(exp->e_exp))) {
3490 case SEG_PASS1:
3491 seg(exp)=SEG_ABSOLUTE;
3492 adds(exp)=0;
3493 subs(exp)=0;
3494 offs(exp)= (ok==10) ? 1 : 0;
3495 as_warn("Unknown expression: '%s' defaulting to %d",exp->e_beg,offs(exp));
3496 break;
3497
3498 case SEG_ABSENT:
3499 /* Do the same thing the VAX asm does */
3500 seg(exp)=SEG_ABSOLUTE;
3501 adds(exp)=0;
3502 subs(exp)=0;
3503 offs(exp)=0;
3504 if(ok==10) {
3505 as_warn("expression out of range: defaulting to 1");
3506 offs(exp)=1;
3507 }
3508 break;
3509 case SEG_ABSOLUTE:
3510 switch(ok) {
3511 case 10:
3512 if(offs(exp)<1 || offs(exp)>8) {
3513 as_warn("expression out of range: defaulting to 1");
3514 offs(exp)=1;
3515 }
3516 break;
3517 case 20:
3518 if(offs(exp)<0 || offs(exp)>7)
3519 goto outrange;
3520 break;
3521 case 30:
3522 if(offs(exp)<0 || offs(exp)>15)
3523 goto outrange;
3524 break;
3525 case 40:
3526 if(offs(exp)<0 || offs(exp)>32)
3527 goto outrange;
3528 break;
3529 case 50:
3530 if(offs(exp)<0 || offs(exp)>127)
3531 goto outrange;
3532 break;
3533 case 55:
3534 if(offs(exp)<-64 || offs(exp)>63)
3535 goto outrange;
3536 break;
3537 case 60:
3538 if(offs(exp)<-128 || offs(exp)>127)
3539 goto outrange;
3540 break;
3541 case 70:
3542 if(offs(exp)<0 || offs(exp)>4095) {
3543 outrange:
3544 as_warn("expression out of range: defaulting to 0");
3545 offs(exp)=0;
3546 }
3547 break;
3548 default:
3549 break;
3550 }
3551 break;
3552 case SEG_TEXT:
3553 case SEG_DATA:
3554 case SEG_BSS:
3555 case SEG_UNKNOWN:
3556 case SEG_DIFFERENCE:
3557 if(ok>=10 && ok<=70) {
3558 seg(exp)=SEG_ABSOLUTE;
3559 adds(exp)=0;
3560 subs(exp)=0;
3561 offs(exp)= (ok==10) ? 1 : 0;
3562 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
3563 }
3564 break;
3565 case SEG_BIG:
3566 if(ok==80 && offs(exp)<0) { /* HACK! Turn it into a long */
3567 LITTLENUM_TYPE words[6];
3568
3569 gen_to_words(words,2,8L);/* These numbers are magic! */
3570 seg(exp)=SEG_ABSOLUTE;
3571 adds(exp)=0;
3572 subs(exp)=0;
3573 offs(exp)=words[1]|(words[0]<<16);
3574 } else if(ok!=0) {
3575 seg(exp)=SEG_ABSOLUTE;
3576 adds(exp)=0;
3577 subs(exp)=0;
3578 offs(exp)= (ok==10) ? 1 : 0;
3579 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
3580 }
3581 break;
3582 default:
3583 as_fatal("failed sanity check.");
3584 }
3585 if(input_line_pointer!=exp->e_end+1)
3586 as_bad("Ignoring junk after expression");
3587 exp->e_end[1]=c_save;
3588 input_line_pointer=save_in;
3589 if(exp->e_siz) {
3590 switch(exp->e_siz) {
3591 case 1:
3592 if(!isbyte(offs(exp)))
3593 as_warn("expression doesn't fit in BYTE");
3594 break;
3595 case 2:
3596 if(!isword(offs(exp)))
3597 as_warn("expression doesn't fit in WORD");
3598 break;
3599 }
3600 }
3601 return offs(exp);
3602 #endif
3603 } /* get_num() */
3604
3605 /* These are the back-ends for the various machine dependent pseudo-ops. */
3606 void demand_empty_rest_of_line(); /* Hate those extra verbose names */
3607
3608 static void s_data1() {
3609 subseg_new(SEG_DATA,1);
3610 demand_empty_rest_of_line();
3611 } /* s_data1() */
3612
3613 static void s_data2() {
3614 subseg_new(SEG_DATA,2);
3615 demand_empty_rest_of_line();
3616 } /* s_data2() */
3617
3618 static void s_bss()
3619 {
3620 /* We don't support putting frags in the BSS segment, we fake it
3621 by marking in_bss, then looking at s_skip for clues */
3622
3623 subseg_new(SEG_BSS, 0);
3624 demand_empty_rest_of_line();
3625 } /* s_bss() */
3626
3627 static void s_even() {
3628 register int temp;
3629 register long temp_fill;
3630
3631 temp = 1; /* JF should be 2? */
3632 temp_fill = get_absolute_expression ();
3633 if ( ! need_pass_2 ) /* Never make frag if expect extra pass. */
3634 frag_align (temp, (int)temp_fill);
3635 demand_empty_rest_of_line();
3636 } /* s_even() */
3637
3638 static void s_proc() {
3639 demand_empty_rest_of_line();
3640 } /* s_proc() */
3641
3642 /* s_space is defined in read.c .skip is simply an alias to it. */
3643
3644 /*
3645 * md_parse_option
3646 * Invocation line includes a switch not recognized by the base assembler.
3647 * See if it's a processor-specific option. These are:
3648 *
3649 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
3650 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
3651 * Select the architecture. Instructions or features not
3652 * supported by the selected architecture cause fatal
3653 * errors. More than one may be specified. The default is
3654 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
3655 * for -m68000, and -m68882 is a synonym for -m68881.
3656 *
3657 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
3658 * (e.g. m68020) also requests that float instructions be included. This
3659 * is the default setup, mostly to avoid hassling users. A better
3660 * rearrangement of this structure would be to add an option to DENY
3661 * floating point opcodes, for people who want to really know there's none
3662 * of that funny floaty stuff going on. FIXME-later.
3663 */
3664 #ifndef MAYBE_FLOAT_TOO
3665 #define MAYBE_FLOAT_TOO m68881
3666 #endif
3667
3668 int md_parse_option(argP,cntP,vecP)
3669 char **argP;
3670 int *cntP;
3671 char ***vecP;
3672 {
3673 switch(**argP) {
3674 case 'l': /* -l means keep external to 2 bit offset
3675 rather than 16 bit one */
3676 break;
3677
3678 case 'S': /* -S means that jbsr's always turn into jsr's. */
3679 break;
3680
3681 case 'A':
3682 (*argP)++;
3683 /* intentional fall-through */
3684 case 'm':
3685 (*argP)++;
3686
3687 if (**argP=='c') {
3688 (*argP)++;
3689 } /* allow an optional "c" */
3690
3691 if (!strcmp(*argP, "68000")
3692 || !strcmp(*argP, "68008")) {
3693 current_architecture |= m68000;
3694 } else if (!strcmp(*argP, "68010")) {
3695 #ifdef TE_SUN
3696 omagic= 1<<16|OMAGIC;
3697 #endif
3698 current_architecture |= m68010;
3699
3700 } else if (!strcmp(*argP, "68020")) {
3701 current_architecture |= m68020 | MAYBE_FLOAT_TOO;
3702
3703 } else if (!strcmp(*argP, "68030")) {
3704 current_architecture |= m68030 | MAYBE_FLOAT_TOO;
3705
3706 } else if (!strcmp(*argP, "68040")) {
3707 current_architecture |= m68040 | MAYBE_FLOAT_TOO;
3708
3709 #ifndef NO_68881
3710 } else if (!strcmp(*argP, "68881")) {
3711 current_architecture |= m68881;
3712
3713 } else if (!strcmp(*argP, "68882")) {
3714 current_architecture |= m68882;
3715
3716 #endif /* NO_68881 */
3717 #ifndef NO_68851
3718 } else if (!strcmp(*argP,"68851")) {
3719 current_architecture |= m68851;
3720
3721 #endif /* NO_68851 */
3722 } else {
3723 as_warn("Unknown architecture, \"%s\". option ignored", *argP);
3724 } /* switch on architecture */
3725
3726 while(**argP) (*argP)++;
3727
3728 break;
3729
3730 case 'p':
3731 if (!strcmp(*argP,"pic")) {
3732 (*argP) += 3;
3733 break; /* -pic, Position Independent Code */
3734 } else {
3735 return(0);
3736 } /* pic or not */
3737
3738 default:
3739 return 0;
3740 }
3741 return 1;
3742 }
3743
3744
3745 #ifdef TEST2
3746
3747 /* TEST2: Test md_assemble() */
3748 /* Warning, this routine probably doesn't work anymore */
3749
3750 main()
3751 {
3752 struct m68k_it the_ins;
3753 char buf[120];
3754 char *cp;
3755 int n;
3756
3757 m68k_ip_begin();
3758 for(;;) {
3759 if(!gets(buf) || !*buf)
3760 break;
3761 if(buf[0]=='|' || buf[1]=='.')
3762 continue;
3763 for(cp=buf;*cp;cp++)
3764 if(*cp=='\t')
3765 *cp=' ';
3766 if(is_label(buf))
3767 continue;
3768 memset(&the_ins, '\0', sizeof(the_ins));
3769 m68k_ip(&the_ins,buf);
3770 if(the_ins.error) {
3771 printf("Error %s in %s\n",the_ins.error,buf);
3772 } else {
3773 printf("Opcode(%d.%s): ",the_ins.numo,the_ins.args);
3774 for(n=0;n<the_ins.numo;n++)
3775 printf(" 0x%x",the_ins.opcode[n]&0xffff);
3776 printf(" ");
3777 print_the_insn(&the_ins.opcode[0],stdout);
3778 (void)putchar('\n');
3779 }
3780 for(n=0;n<strlen(the_ins.args)/2;n++) {
3781 if(the_ins.operands[n].error) {
3782 printf("op%d Error %s in %s\n",n,the_ins.operands[n].error,buf);
3783 continue;
3784 }
3785 printf("mode %d, reg %d, ",the_ins.operands[n].mode,the_ins.operands[n].reg);
3786 if(the_ins.operands[n].b_const)
3787 printf("Constant: '%.*s', ",1+the_ins.operands[n].e_const-the_ins.operands[n].b_const,the_ins.operands[n].b_const);
3788 printf("ireg %d, isiz %d, imul %d, ",the_ins.operands[n].ireg,the_ins.operands[n].isiz,the_ins.operands[n].imul);
3789 if(the_ins.operands[n].b_iadd)
3790 printf("Iadd: '%.*s',",1+the_ins.operands[n].e_iadd-the_ins.operands[n].b_iadd,the_ins.operands[n].b_iadd);
3791 (void)putchar('\n');
3792 }
3793 }
3794 m68k_ip_end();
3795 return 0;
3796 }
3797
3798 is_label(str)
3799 char *str;
3800 {
3801 while(*str==' ')
3802 str++;
3803 while(*str && *str!=' ')
3804 str++;
3805 if(str[-1]==':' || str[1]=='=')
3806 return 1;
3807 return 0;
3808 }
3809
3810 #endif
3811
3812 /* Possible states for relaxation:
3813
3814 0 0 branch offset byte (bra, etc)
3815 0 1 word
3816 0 2 long
3817
3818 1 0 indexed offsets byte a0@(32,d4:w:1) etc
3819 1 1 word
3820 1 2 long
3821
3822 2 0 two-offset index word-word a0@(32,d4)@(45) etc
3823 2 1 word-long
3824 2 2 long-word
3825 2 3 long-long
3826
3827 */
3828
3829
3830
3831 #ifdef DONTDEF
3832 abort()
3833 {
3834 printf("ABORT!\n");
3835 exit(12);
3836 }
3837
3838 print_frags()
3839 {
3840 fragS *fragP;
3841 extern fragS *text_frag_root;
3842
3843 for(fragP=text_frag_root;fragP;fragP=fragP->fr_next) {
3844 printf("addr %lu next 0x%x fix %ld var %ld symbol 0x%x offset %ld\n",
3845 fragP->fr_address,fragP->fr_next,fragP->fr_fix,fragP->fr_var,fragP->fr_symbol,fragP->fr_offset);
3846 printf("opcode 0x%x type %d subtype %d\n\n",fragP->fr_opcode,fragP->fr_type,fragP->fr_subtype);
3847 }
3848 fflush(stdout);
3849 return 0;
3850 }
3851 #endif
3852
3853 #ifdef DONTDEF
3854 /*VARARGS1*/
3855 panic(format,args)
3856 char *format;
3857 {
3858 fputs("Internal error:",stderr);
3859 _doprnt(format,&args,stderr);
3860 (void)putc('\n',stderr);
3861 as_where();
3862 abort();
3863 }
3864 #endif
3865
3866 /* We have no need to default values of symbols. */
3867
3868 /* ARGSUSED */
3869 symbolS *
3870 md_undefined_symbol (name)
3871 char *name;
3872 {
3873 return 0;
3874 }
3875
3876 /* Parse an operand that is machine-specific.
3877 We just return without modifying the expression if we have nothing
3878 to do. */
3879
3880 /* ARGSUSED */
3881 void
3882 md_operand (expressionP)
3883 expressionS *expressionP;
3884 {
3885 }
3886
3887 /* Round up a section size to the appropriate boundary. */
3888 long
3889 md_section_align (segment, size)
3890 segT segment;
3891 long size;
3892 {
3893 return size; /* Byte alignment is fine */
3894 }
3895
3896 /* Exactly what point is a PC-relative offset relative TO?
3897 On the 68k, they're relative to the address of the offset, plus
3898 its size. (??? Is this right? FIXME-SOON!) */
3899 long
3900 md_pcrel_from (fixP)
3901 fixS *fixP;
3902 {
3903 return(fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address);
3904 }
3905
3906 /*
3907 * Local Variables:
3908 * comment-column: 0
3909 * fill-column: 131
3910 * End:
3911 */
3912
3913 /* end of tc-m68k.c */
GDB Binutils - Deliverables
This page took 0.111452 seconds and 4 git commands to generate.