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2001-05-25 H.J. Lu <hjl@gnu.org>
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001
4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23 #include <ctype.h>
24 #include "as.h"
25 #include "obstack.h"
26 #include "subsegs.h"
27
28 #include "opcode/m68k.h"
29 #include "m68k-parse.h"
30
31 #if defined (OBJ_ELF)
32 #include "elf/m68k.h"
33 #endif
34
35 /* This string holds the chars that always start a comment. If the
36 pre-processor is disabled, these aren't very useful. The macro
37 tc_comment_chars points to this. We use this, rather than the
38 usual comment_chars, so that the --bitwise-or option will work. */
39 #if defined (TE_SVR4) || defined (TE_DELTA)
40 const char *m68k_comment_chars = "|#";
41 #else
42 const char *m68k_comment_chars = "|";
43 #endif
44
45 /* This array holds the chars that only start a comment at the beginning of
46 a line. If the line seems to have the form '# 123 filename'
47 .line and .file directives will appear in the pre-processed output */
48 /* Note that input_file.c hand checks for '#' at the beginning of the
49 first line of the input file. This is because the compiler outputs
50 #NO_APP at the beginning of its output. */
51 /* Also note that comments like this one will always work. */
52 const char line_comment_chars[] = "#*";
53
54 const char line_separator_chars[] = ";";
55
56 /* Chars that can be used to separate mant from exp in floating point nums */
57 CONST char EXP_CHARS[] = "eE";
58
59 /* Chars that mean this number is a floating point constant, as
60 in "0f12.456" or "0d1.2345e12". */
61
62 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
63
64 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
65 changed in read.c . Ideally it shouldn't have to know about it at all,
66 but nothing is ideal around here. */
67
68 const int md_reloc_size = 8; /* Size of relocation record */
69
70 /* Are we trying to generate PIC code? If so, absolute references
71 ought to be made into linkage table references or pc-relative
72 references. Not implemented. For ELF there are other means
73 to denote pic relocations. */
74 int flag_want_pic;
75
76 static int flag_short_refs; /* -l option */
77 static int flag_long_jumps; /* -S option */
78 static int flag_keep_pcrel; /* --pcrel option. */
79
80 #ifdef REGISTER_PREFIX_OPTIONAL
81 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
82 #else
83 int flag_reg_prefix_optional;
84 #endif
85
86 /* Whether --register-prefix-optional was used on the command line. */
87 static int reg_prefix_optional_seen;
88
89 /* The floating point coprocessor to use by default. */
90 static enum m68k_register m68k_float_copnum = COP1;
91
92 /* If this is non-zero, then references to number(%pc) will be taken
93 to refer to number, rather than to %pc + number. */
94 static int m68k_abspcadd;
95
96 /* If this is non-zero, then the quick forms of the move, add, and sub
97 instructions are used when possible. */
98 static int m68k_quick = 1;
99
100 /* If this is non-zero, then if the size is not specified for a base
101 or outer displacement, the assembler assumes that the size should
102 be 32 bits. */
103 static int m68k_rel32 = 1;
104
105 /* This is non-zero if m68k_rel32 was set from the command line. */
106 static int m68k_rel32_from_cmdline;
107
108 /* The default width to use for an index register when using a base
109 displacement. */
110 static enum m68k_size m68k_index_width_default = SIZE_LONG;
111
112 /* We want to warn if any text labels are misaligned. In order to get
113 the right line number, we need to record the line number for each
114 label. */
115
116 struct label_line
117 {
118 struct label_line *next;
119 symbolS *label;
120 char *file;
121 unsigned int line;
122 int text;
123 };
124
125 /* The list of labels. */
126
127 static struct label_line *labels;
128
129 /* The current label. */
130
131 static struct label_line *current_label;
132
133 /* Its an arbitrary name: This means I don't approve of it */
134 /* See flames below */
135 static struct obstack robyn;
136
137 struct m68k_incant
138 {
139 const char *m_operands;
140 unsigned long m_opcode;
141 short m_opnum;
142 short m_codenum;
143 int m_arch;
144 struct m68k_incant *m_next;
145 };
146
147 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
148 #define gettwo(x) (((x)->m_opcode)&0xffff)
149
150 static const enum m68k_register m68000_control_regs[] = { 0 };
151 static const enum m68k_register m68010_control_regs[] = {
152 SFC, DFC, USP, VBR,
153 0
154 };
155 static const enum m68k_register m68020_control_regs[] = {
156 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
157 0
158 };
159 static const enum m68k_register m68040_control_regs[] = {
160 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
161 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
162 0
163 };
164 static const enum m68k_register m68060_control_regs[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
166 USP, VBR, URP, SRP, PCR,
167 0
168 };
169 static const enum m68k_register mcf_control_regs[] = {
170 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
171 RAMBAR0, RAMBAR1, MBAR,
172 0
173 };
174 #define cpu32_control_regs m68010_control_regs
175
176 static const enum m68k_register *control_regs;
177
178 /* internal form of a 68020 instruction */
179 struct m68k_it
180 {
181 const char *error;
182 const char *args; /* list of opcode info */
183 int numargs;
184
185 int numo; /* Number of shorts in opcode */
186 short opcode[11];
187
188 struct m68k_op operands[6];
189
190 int nexp; /* number of exprs in use */
191 struct m68k_exp exprs[4];
192
193 int nfrag; /* Number of frags we have to produce */
194 struct
195 {
196 int fragoff; /* Where in the current opcode the frag ends */
197 symbolS *fadd;
198 offsetT foff;
199 int fragty;
200 }
201 fragb[4];
202
203 int nrel; /* Num of reloc strucs in use */
204 struct
205 {
206 int n;
207 expressionS exp;
208 char wid;
209 char pcrel;
210 /* In a pc relative address the difference between the address
211 of the offset and the address that the offset is relative
212 to. This depends on the addressing mode. Basically this
213 is the value to put in the offset field to address the
214 first byte of the offset, without regarding the special
215 significance of some values (in the branch instruction, for
216 example). */
217 int pcrel_fix;
218 #ifdef OBJ_ELF
219 /* Whether this expression needs special pic relocation, and if
220 so, which. */
221 enum pic_relocation pic_reloc;
222 #endif
223 }
224 reloc[5]; /* Five is enough??? */
225 };
226
227 #define cpu_of_arch(x) ((x) & (m68000up|mcf))
228 #define float_of_arch(x) ((x) & mfloat)
229 #define mmu_of_arch(x) ((x) & mmmu)
230 #define arch_coldfire_p(x) (((x) & mcf) != 0)
231
232 /* Macros for determining if cpu supports a specific addressing mode */
233 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
234
235 static struct m68k_it the_ins; /* the instruction being assembled */
236
237 #define op(ex) ((ex)->exp.X_op)
238 #define adds(ex) ((ex)->exp.X_add_symbol)
239 #define subs(ex) ((ex)->exp.X_op_symbol)
240 #define offs(ex) ((ex)->exp.X_add_number)
241
242 /* Macros for adding things to the m68k_it struct */
243
244 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
245
246 /* Static functions. */
247
248 static void insop PARAMS ((int, const struct m68k_incant *));
249 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
250 static void add_frag PARAMS ((symbolS *, offsetT, int));
251
252 /* Like addword, but goes BEFORE general operands */
253 static void
254 insop (w, opcode)
255 int w;
256 const struct m68k_incant *opcode;
257 {
258 int z;
259 for(z=the_ins.numo;z>opcode->m_codenum;--z)
260 the_ins.opcode[z]=the_ins.opcode[z-1];
261 for(z=0;z<the_ins.nrel;z++)
262 the_ins.reloc[z].n+=2;
263 for (z = 0; z < the_ins.nfrag; z++)
264 the_ins.fragb[z].fragoff++;
265 the_ins.opcode[opcode->m_codenum]=w;
266 the_ins.numo++;
267 }
268
269 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
270 Blecch. */
271 static void
272 add_fix (width, exp, pc_rel, pc_fix)
273 int width;
274 struct m68k_exp *exp;
275 int pc_rel;
276 int pc_fix;
277 {
278 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
279 ? (the_ins.numo*2-1)
280 : (((width)=='b')
281 ? (the_ins.numo*2+1)
282 : (the_ins.numo*2)));
283 the_ins.reloc[the_ins.nrel].exp = exp->exp;
284 the_ins.reloc[the_ins.nrel].wid = width;
285 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
286 #ifdef OBJ_ELF
287 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
288 #endif
289 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
290 }
291
292 /* Cause an extra frag to be generated here, inserting up to 10 bytes
293 (that value is chosen in the frag_var call in md_assemble). TYPE
294 is the subtype of the frag to be generated; its primary type is
295 rs_machine_dependent.
296
297 The TYPE parameter is also used by md_convert_frag_1 and
298 md_estimate_size_before_relax. The appropriate type of fixup will
299 be emitted by md_convert_frag_1.
300
301 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
302 static void
303 add_frag (add, off, type)
304 symbolS *add;
305 offsetT off;
306 int type;
307 {
308 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
309 the_ins.fragb[the_ins.nfrag].fadd=add;
310 the_ins.fragb[the_ins.nfrag].foff=off;
311 the_ins.fragb[the_ins.nfrag++].fragty=type;
312 }
313
314 #define isvar(ex) \
315 (op (ex) != O_constant && op (ex) != O_big)
316
317 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
318 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
319 static void m68k_ip PARAMS ((char *));
320 static void insert_reg PARAMS ((const char *, int));
321 static void select_control_regs PARAMS ((void));
322 static void init_regtable PARAMS ((void));
323 static int reverse_16_bits PARAMS ((int in));
324 static int reverse_8_bits PARAMS ((int in));
325 static void install_gen_operand PARAMS ((int mode, int val));
326 static void install_operand PARAMS ((int mode, int val));
327 static void s_bss PARAMS ((int));
328 static void s_data1 PARAMS ((int));
329 static void s_data2 PARAMS ((int));
330 static void s_even PARAMS ((int));
331 static void s_proc PARAMS ((int));
332 static void mri_chip PARAMS ((void));
333 static void s_chip PARAMS ((int));
334 static void s_fopt PARAMS ((int));
335 static void s_opt PARAMS ((int));
336 static void s_reg PARAMS ((int));
337 static void s_restore PARAMS ((int));
338 static void s_save PARAMS ((int));
339 static void s_mri_if PARAMS ((int));
340 static void s_mri_else PARAMS ((int));
341 static void s_mri_endi PARAMS ((int));
342 static void s_mri_break PARAMS ((int));
343 static void s_mri_next PARAMS ((int));
344 static void s_mri_for PARAMS ((int));
345 static void s_mri_endf PARAMS ((int));
346 static void s_mri_repeat PARAMS ((int));
347 static void s_mri_until PARAMS ((int));
348 static void s_mri_while PARAMS ((int));
349 static void s_mri_endw PARAMS ((int));
350 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
351 static void md_convert_frag_1 PARAMS ((fragS *));
352
353 static int current_architecture;
354
355 struct m68k_cpu
356 {
357 unsigned long arch;
358 const char *name;
359 int alias;
360 };
361
362 static const struct m68k_cpu archs[] =
363 {
364 { m68000, "68000", 0 },
365 { m68010, "68010", 0 },
366 { m68020, "68020", 0 },
367 { m68030, "68030", 0 },
368 { m68040, "68040", 0 },
369 { m68060, "68060", 0 },
370 { cpu32, "cpu32", 0 },
371 { m68881, "68881", 0 },
372 { m68851, "68851", 0 },
373 { mcf5200, "5200", 0 },
374 { mcf5206e, "5206e", 0 },
375 { mcf5307, "5307", 0},
376 { mcf5407, "5407", 0},
377 /* Aliases (effectively, so far as gas is concerned) for the above
378 cpus. */
379 { m68020, "68k", 1 },
380 { m68000, "68008", 1 },
381 { m68000, "68302", 1 },
382 { m68000, "68306", 1 },
383 { m68000, "68307", 1 },
384 { m68000, "68322", 1 },
385 { m68000, "68356", 1 },
386 { m68000, "68ec000", 1 },
387 { m68000, "68hc000", 1 },
388 { m68000, "68hc001", 1 },
389 { m68020, "68ec020", 1 },
390 { m68030, "68ec030", 1 },
391 { m68040, "68ec040", 1 },
392 { m68060, "68ec060", 1 },
393 { cpu32, "68330", 1 },
394 { cpu32, "68331", 1 },
395 { cpu32, "68332", 1 },
396 { cpu32, "68333", 1 },
397 { cpu32, "68334", 1 },
398 { cpu32, "68336", 1 },
399 { cpu32, "68340", 1 },
400 { cpu32, "68341", 1 },
401 { cpu32, "68349", 1 },
402 { cpu32, "68360", 1 },
403 { m68881, "68882", 1 },
404 { mcf5200, "5202", 1 },
405 { mcf5200, "5204", 1 },
406 { mcf5200, "5206", 1 },
407 };
408
409 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
410
411 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
412 architecture and we have a lot of relaxation modes. */
413
414 /* Macros used in the relaxation code. */
415 #define TAB(x,y) (((x) << 2) + (y))
416 #define TABTYPE(x) ((x) >> 2)
417
418 /* Relaxation states. */
419 #define BYTE 0
420 #define SHORT 1
421 #define LONG 2
422 #define SZ_UNDEF 3
423
424 /* Here are all the relaxation modes we support. First we can relax ordinary
425 branches. On 68020 and higher and on CPU32 all branch instructions take
426 three forms, so on these CPUs all branches always remain as such. When we
427 have to expand to the LONG form on a 68000, though, we substitute an
428 absolute jump instead. This is a direct replacement for unconditional
429 branches and a branch over a jump for conditional branches. However, if the
430 user requires PIC and disables this with --pcrel, we can only relax between
431 BYTE and SHORT forms, punting if that isn't enough. This gives us four
432 different relaxation modes for branches: */
433
434 #define BRANCHBWL 1 /* branch byte, word, or long */
435 #define BRABSJUNC 2 /* absolute jump for LONG, unconditional */
436 #define BRABSJCOND 3 /* absolute jump for LONG, conditional */
437 #define BRANCHBW 4 /* branch byte or word */
438
439 /* We also relax coprocessor branches and DBcc's. All CPUs that support
440 coprocessor branches support them in word and long forms, so we have only
441 one relaxation mode for them. DBcc's are word only on all CPUs. We can
442 relax them to the LONG form with a branch-around sequence. This sequence
443 can use a long branch (if available) or an absolute jump (if acceptable).
444 This gives us two relaxation modes. If long branches are not available and
445 absolute jumps are not acceptable, we don't relax DBcc's. */
446
447 #define FBRANCH 5 /* coprocessor branch */
448 #define DBCCLBR 6 /* DBcc relaxable with a long branch */
449 #define DBCCABSJ 7 /* DBcc relaxable with an absolute jump */
450
451 /* That's all for instruction relaxation. However, we also relax PC-relative
452 operands. Specifically, we have three operand relaxation modes. On the
453 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
454 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
455 two. Also PC+displacement+index operands in their simple form (with a non-
456 suppressed index without memory indirection) are supported on all CPUs, but
457 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
458 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
459 form of the PC+displacement+index operand. Finally, some absolute operands
460 can be relaxed down to 16-bit PC-relative. */
461
462 #define PCREL1632 8 /* 16-bit or 32-bit PC-relative */
463 #define PCINDEX 9 /* PC+displacement+index */
464 #define ABSTOPCREL 10 /* absolute relax down to 16-bit PC-relative */
465
466 /* Note that calls to frag_var need to specify the maximum expansion
467 needed; this is currently 10 bytes for DBCC. */
468
469 /* The fields are:
470 How far Forward this mode will reach:
471 How far Backward this mode will reach:
472 How many bytes this mode will add to the size of the frag
473 Which mode to go to if the offset won't fit in this one
474 */
475 relax_typeS md_relax_table[] =
476 {
477 {1, 1, 0, 0}, /* First entries aren't used */
478 {1, 1, 0, 0}, /* For no good reason except */
479 {1, 1, 0, 0}, /* that the VAX doesn't either */
480 {1, 1, 0, 0},
481
482 {(127), (-128), 0, TAB (BRANCHBWL, SHORT)},
483 {(32767), (-32768), 2, TAB (BRANCHBWL, LONG)},
484 {0, 0, 4, 0},
485 {1, 1, 0, 0},
486
487 {(127), (-128), 0, TAB (BRABSJUNC, SHORT)},
488 {(32767), (-32768), 2, TAB (BRABSJUNC, LONG)},
489 {0, 0, 4, 0},
490 {1, 1, 0, 0},
491
492 {(127), (-128), 0, TAB (BRABSJCOND, SHORT)},
493 {(32767), (-32768), 2, TAB (BRABSJCOND, LONG)},
494 {0, 0, 6, 0},
495 {1, 1, 0, 0},
496
497 {(127), (-128), 0, TAB (BRANCHBW, SHORT)},
498 {0, 0, 2, 0},
499 {1, 1, 0, 0},
500 {1, 1, 0, 0},
501
502 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
503 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
504 {0, 0, 4, 0},
505 {1, 1, 0, 0},
506
507 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
508 {(32767), (-32768), 2, TAB (DBCCLBR, LONG)},
509 {0, 0, 10, 0},
510 {1, 1, 0, 0},
511
512 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
513 {(32767), (-32768), 2, TAB (DBCCABSJ, LONG)},
514 {0, 0, 10, 0},
515 {1, 1, 0, 0},
516
517 {1, 1, 0, 0}, /* PCREL1632 doesn't come BYTE */
518 {32767, -32768, 2, TAB (PCREL1632, LONG)},
519 {0, 0, 6, 0},
520 {1, 1, 0, 0},
521
522 {125, -130, 0, TAB (PCINDEX, SHORT)},
523 {32765, -32770, 2, TAB (PCINDEX, LONG)},
524 {0, 0, 4, 0},
525 {1, 1, 0, 0},
526
527 {1, 1, 0, 0}, /* ABSTOPCREL doesn't come BYTE */
528 {(32767), (-32768), 2, TAB (ABSTOPCREL, LONG)},
529 {0, 0, 4, 0},
530 {1, 1, 0, 0},
531 };
532
533 /* These are the machine dependent pseudo-ops. These are included so
534 the assembler can work on the output from the SUN C compiler, which
535 generates these.
536 */
537
538 /* This table describes all the machine specific pseudo-ops the assembler
539 has to support. The fields are:
540 pseudo-op name without dot
541 function to call to execute this pseudo-op
542 Integer arg to pass to the function
543 */
544 const pseudo_typeS md_pseudo_table[] =
545 {
546 {"data1", s_data1, 0},
547 {"data2", s_data2, 0},
548 {"bss", s_bss, 0},
549 {"even", s_even, 0},
550 {"skip", s_space, 0},
551 {"proc", s_proc, 0},
552 #if defined (TE_SUN3) || defined (OBJ_ELF)
553 {"align", s_align_bytes, 0},
554 #endif
555 #ifdef OBJ_ELF
556 {"swbeg", s_ignore, 0},
557 #endif
558 {"extend", float_cons, 'x'},
559 {"ldouble", float_cons, 'x'},
560
561 /* The following pseudo-ops are supported for MRI compatibility. */
562 {"chip", s_chip, 0},
563 {"comline", s_space, 1},
564 {"fopt", s_fopt, 0},
565 {"mask2", s_ignore, 0},
566 {"opt", s_opt, 0},
567 {"reg", s_reg, 0},
568 {"restore", s_restore, 0},
569 {"save", s_save, 0},
570
571 {"if", s_mri_if, 0},
572 {"if.b", s_mri_if, 'b'},
573 {"if.w", s_mri_if, 'w'},
574 {"if.l", s_mri_if, 'l'},
575 {"else", s_mri_else, 0},
576 {"else.s", s_mri_else, 's'},
577 {"else.l", s_mri_else, 'l'},
578 {"endi", s_mri_endi, 0},
579 {"break", s_mri_break, 0},
580 {"break.s", s_mri_break, 's'},
581 {"break.l", s_mri_break, 'l'},
582 {"next", s_mri_next, 0},
583 {"next.s", s_mri_next, 's'},
584 {"next.l", s_mri_next, 'l'},
585 {"for", s_mri_for, 0},
586 {"for.b", s_mri_for, 'b'},
587 {"for.w", s_mri_for, 'w'},
588 {"for.l", s_mri_for, 'l'},
589 {"endf", s_mri_endf, 0},
590 {"repeat", s_mri_repeat, 0},
591 {"until", s_mri_until, 0},
592 {"until.b", s_mri_until, 'b'},
593 {"until.w", s_mri_until, 'w'},
594 {"until.l", s_mri_until, 'l'},
595 {"while", s_mri_while, 0},
596 {"while.b", s_mri_while, 'b'},
597 {"while.w", s_mri_while, 'w'},
598 {"while.l", s_mri_while, 'l'},
599 {"endw", s_mri_endw, 0},
600
601 {0, 0, 0}
602 };
603
604 /* The mote pseudo ops are put into the opcode table, since they
605 don't start with a . they look like opcodes to gas.
606 */
607
608 #ifdef M68KCOFF
609 extern void obj_coff_section PARAMS ((int));
610 #endif
611
612 CONST pseudo_typeS mote_pseudo_table[] =
613 {
614
615 {"dcl", cons, 4},
616 {"dc", cons, 2},
617 {"dcw", cons, 2},
618 {"dcb", cons, 1},
619
620 {"dsl", s_space, 4},
621 {"ds", s_space, 2},
622 {"dsw", s_space, 2},
623 {"dsb", s_space, 1},
624
625 {"xdef", s_globl, 0},
626 #ifdef OBJ_ELF
627 {"align", s_align_bytes, 0},
628 #else
629 {"align", s_align_ptwo, 0},
630 #endif
631 #ifdef M68KCOFF
632 {"sect", obj_coff_section, 0},
633 {"section", obj_coff_section, 0},
634 #endif
635 {0, 0, 0}
636 };
637
638 #define issbyte(x) ((x)>=-128 && (x)<=127)
639 #define isubyte(x) ((x)>=0 && (x)<=255)
640 #define issword(x) ((x)>=-32768 && (x)<=32767)
641 #define isuword(x) ((x)>=0 && (x)<=65535)
642
643 #define isbyte(x) ((x)>= -255 && (x)<=255)
644 #define isword(x) ((x)>=-65536 && (x)<=65535)
645 #define islong(x) (1)
646
647 extern char *input_line_pointer;
648
649 static char mklower_table[256];
650 #define mklower(c) (mklower_table[(unsigned char) (c)])
651 static char notend_table[256];
652 static char alt_notend_table[256];
653 #define notend(s) \
654 (! (notend_table[(unsigned char) *s] \
655 || (*s == ':' \
656 && alt_notend_table[(unsigned char) s[1]])))
657
658 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
659
660 #ifdef NO_PCREL_RELOCS
661
662 int
663 make_pcrel_absolute(fixP, add_number)
664 fixS *fixP;
665 long *add_number;
666 {
667 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
668
669 /* rewrite the PC relative instructions to absolute address ones.
670 * these are rumoured to be faster, and the apollo linker refuses
671 * to deal with the PC relative relocations.
672 */
673 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
674 {
675 opcode[0] = 0x4e;
676 opcode[1] = 0xf9;
677 }
678 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
679 {
680 opcode[0] = 0x4e;
681 opcode[1] = 0xb9;
682 }
683 else
684 as_fatal (_("Unknown PC relative instruction"));
685 *add_number -= 4;
686 return 0;
687 }
688
689 #endif /* NO_PCREL_RELOCS */
690
691 short
692 tc_coff_fix2rtype (fixP)
693 fixS *fixP;
694 {
695 if (fixP->fx_tcbit && fixP->fx_size == 4)
696 return R_RELLONG_NEG;
697 #ifdef NO_PCREL_RELOCS
698 know (fixP->fx_pcrel == 0);
699 return (fixP->fx_size == 1 ? R_RELBYTE
700 : fixP->fx_size == 2 ? R_DIR16
701 : R_DIR32);
702 #else
703 return (fixP->fx_pcrel ?
704 (fixP->fx_size == 1 ? R_PCRBYTE :
705 fixP->fx_size == 2 ? R_PCRWORD :
706 R_PCRLONG) :
707 (fixP->fx_size == 1 ? R_RELBYTE :
708 fixP->fx_size == 2 ? R_RELWORD :
709 R_RELLONG));
710 #endif
711 }
712
713 #endif
714
715 #ifdef OBJ_ELF
716
717 /* Return zero if the reference to SYMBOL from within the same segment may
718 be relaxed. */
719
720 /* On an ELF system, we can't relax an externally visible symbol,
721 because it may be overridden by a shared library. However, if
722 TARGET_OS is "elf", then we presume that we are assembling for an
723 embedded system, in which case we don't have to worry about shared
724 libraries, and we can relax any external sym. */
725
726 #define relaxable_symbol(symbol) \
727 (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \
728 || S_IS_WEAK (symbol)))
729
730 /* Compute the relocation code for a fixup of SIZE bytes, using pc
731 relative relocation if PCREL is non-zero. PIC says whether a special
732 pic relocation was requested. */
733
734 static bfd_reloc_code_real_type get_reloc_code
735 PARAMS ((int, int, enum pic_relocation));
736
737 static bfd_reloc_code_real_type
738 get_reloc_code (size, pcrel, pic)
739 int size;
740 int pcrel;
741 enum pic_relocation pic;
742 {
743 switch (pic)
744 {
745 case pic_got_pcrel:
746 switch (size)
747 {
748 case 1:
749 return BFD_RELOC_8_GOT_PCREL;
750 case 2:
751 return BFD_RELOC_16_GOT_PCREL;
752 case 4:
753 return BFD_RELOC_32_GOT_PCREL;
754 }
755 break;
756
757 case pic_got_off:
758 switch (size)
759 {
760 case 1:
761 return BFD_RELOC_8_GOTOFF;
762 case 2:
763 return BFD_RELOC_16_GOTOFF;
764 case 4:
765 return BFD_RELOC_32_GOTOFF;
766 }
767 break;
768
769 case pic_plt_pcrel:
770 switch (size)
771 {
772 case 1:
773 return BFD_RELOC_8_PLT_PCREL;
774 case 2:
775 return BFD_RELOC_16_PLT_PCREL;
776 case 4:
777 return BFD_RELOC_32_PLT_PCREL;
778 }
779 break;
780
781 case pic_plt_off:
782 switch (size)
783 {
784 case 1:
785 return BFD_RELOC_8_PLTOFF;
786 case 2:
787 return BFD_RELOC_16_PLTOFF;
788 case 4:
789 return BFD_RELOC_32_PLTOFF;
790 }
791 break;
792
793 case pic_none:
794 if (pcrel)
795 {
796 switch (size)
797 {
798 case 1:
799 return BFD_RELOC_8_PCREL;
800 case 2:
801 return BFD_RELOC_16_PCREL;
802 case 4:
803 return BFD_RELOC_32_PCREL;
804 }
805 }
806 else
807 {
808 switch (size)
809 {
810 case 1:
811 return BFD_RELOC_8;
812 case 2:
813 return BFD_RELOC_16;
814 case 4:
815 return BFD_RELOC_32;
816 }
817 }
818 }
819
820 if (pcrel)
821 {
822 if (pic == pic_none)
823 as_bad (_("Can not do %d byte pc-relative relocation"), size);
824 else
825 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
826 }
827 else
828 {
829 if (pic == pic_none)
830 as_bad (_("Can not do %d byte relocation"), size);
831 else
832 as_bad (_("Can not do %d byte pic relocation"), size);
833 }
834
835 return BFD_RELOC_NONE;
836 }
837
838 /* Here we decide which fixups can be adjusted to make them relative
839 to the beginning of the section instead of the symbol. Basically
840 we need to make sure that the dynamic relocations are done
841 correctly, so in some cases we force the original symbol to be
842 used. */
843 int
844 tc_m68k_fix_adjustable (fixP)
845 fixS *fixP;
846 {
847 /* Prevent all adjustments to global symbols. */
848 if (! relaxable_symbol (fixP->fx_addsy))
849 return 0;
850
851 /* adjust_reloc_syms doesn't know about the GOT */
852 switch (fixP->fx_r_type)
853 {
854 case BFD_RELOC_8_GOT_PCREL:
855 case BFD_RELOC_16_GOT_PCREL:
856 case BFD_RELOC_32_GOT_PCREL:
857 case BFD_RELOC_8_GOTOFF:
858 case BFD_RELOC_16_GOTOFF:
859 case BFD_RELOC_32_GOTOFF:
860 case BFD_RELOC_8_PLT_PCREL:
861 case BFD_RELOC_16_PLT_PCREL:
862 case BFD_RELOC_32_PLT_PCREL:
863 case BFD_RELOC_8_PLTOFF:
864 case BFD_RELOC_16_PLTOFF:
865 case BFD_RELOC_32_PLTOFF:
866 return 0;
867
868 case BFD_RELOC_VTABLE_INHERIT:
869 case BFD_RELOC_VTABLE_ENTRY:
870 return 0;
871
872 default:
873 return 1;
874 }
875 }
876
877 #else /* !OBJ_ELF */
878
879 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
880
881 #define relaxable_symbol(symbol) 1
882
883 #endif /* OBJ_ELF */
884
885 #ifdef BFD_ASSEMBLER
886
887 arelent *
888 tc_gen_reloc (section, fixp)
889 asection *section;
890 fixS *fixp;
891 {
892 arelent *reloc;
893 bfd_reloc_code_real_type code;
894
895 /* If the tcbit is set, then this was a fixup of a negative value
896 that was never resolved. We do not have a reloc to handle this,
897 so just return. We assume that other code will have detected this
898 situation and produced a helpful error message, so we just tell the
899 user that the reloc cannot be produced. */
900 if (fixp->fx_tcbit)
901 {
902 if (fixp->fx_addsy)
903 as_bad (_("Unable to produce reloc against symbol '%s'"),
904 S_GET_NAME (fixp->fx_addsy));
905 return NULL;
906 }
907
908 if (fixp->fx_r_type != BFD_RELOC_NONE)
909 {
910 code = fixp->fx_r_type;
911
912 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
913 that fixup_segment converted a non-PC relative reloc into a
914 PC relative reloc. In such a case, we need to convert the
915 reloc code. */
916 if (fixp->fx_pcrel)
917 {
918 switch (code)
919 {
920 case BFD_RELOC_8:
921 code = BFD_RELOC_8_PCREL;
922 break;
923 case BFD_RELOC_16:
924 code = BFD_RELOC_16_PCREL;
925 break;
926 case BFD_RELOC_32:
927 code = BFD_RELOC_32_PCREL;
928 break;
929 case BFD_RELOC_8_PCREL:
930 case BFD_RELOC_16_PCREL:
931 case BFD_RELOC_32_PCREL:
932 case BFD_RELOC_8_GOT_PCREL:
933 case BFD_RELOC_16_GOT_PCREL:
934 case BFD_RELOC_32_GOT_PCREL:
935 case BFD_RELOC_8_GOTOFF:
936 case BFD_RELOC_16_GOTOFF:
937 case BFD_RELOC_32_GOTOFF:
938 case BFD_RELOC_8_PLT_PCREL:
939 case BFD_RELOC_16_PLT_PCREL:
940 case BFD_RELOC_32_PLT_PCREL:
941 case BFD_RELOC_8_PLTOFF:
942 case BFD_RELOC_16_PLTOFF:
943 case BFD_RELOC_32_PLTOFF:
944 break;
945 default:
946 as_bad_where (fixp->fx_file, fixp->fx_line,
947 _("Cannot make %s relocation PC relative"),
948 bfd_get_reloc_code_name (code));
949 }
950 }
951 }
952 else
953 {
954 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
955 switch (F (fixp->fx_size, fixp->fx_pcrel))
956 {
957 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
958 MAP (1, 0, BFD_RELOC_8);
959 MAP (2, 0, BFD_RELOC_16);
960 MAP (4, 0, BFD_RELOC_32);
961 MAP (1, 1, BFD_RELOC_8_PCREL);
962 MAP (2, 1, BFD_RELOC_16_PCREL);
963 MAP (4, 1, BFD_RELOC_32_PCREL);
964 default:
965 abort ();
966 }
967 }
968 #undef F
969 #undef MAP
970
971 reloc = (arelent *) xmalloc (sizeof (arelent));
972 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
973 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
974 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
975 #ifndef OBJ_ELF
976 if (fixp->fx_pcrel)
977 reloc->addend = fixp->fx_addnumber;
978 else
979 reloc->addend = 0;
980 #else
981 if (!fixp->fx_pcrel)
982 reloc->addend = fixp->fx_addnumber;
983 else
984 reloc->addend = (section->vma
985 /* Explicit sign extension in case char is
986 unsigned. */
987 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
988 + fixp->fx_addnumber
989 + md_pcrel_from (fixp));
990 #endif
991
992 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
993 assert (reloc->howto != 0);
994
995 return reloc;
996 }
997
998 #endif /* BFD_ASSEMBLER */
999
1000 /* Handle of the OPCODE hash table. NULL means any use before
1001 m68k_ip_begin() will crash. */
1002 static struct hash_control *op_hash;
1003 \f
1004 /* Assemble an m68k instruction. */
1005
1006 static void
1007 m68k_ip (instring)
1008 char *instring;
1009 {
1010 register char *p;
1011 register struct m68k_op *opP;
1012 register const struct m68k_incant *opcode;
1013 register const char *s;
1014 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1015 char *pdot, *pdotmove;
1016 enum m68k_size siz1, siz2;
1017 char c;
1018 int losing;
1019 int opsfound;
1020 LITTLENUM_TYPE words[6];
1021 LITTLENUM_TYPE *wordp;
1022 unsigned long ok_arch = 0;
1023
1024 if (*instring == ' ')
1025 instring++; /* skip leading whitespace */
1026
1027 /* Scan up to end of operation-code, which MUST end in end-of-string
1028 or exactly 1 space. */
1029 pdot = 0;
1030 for (p = instring; *p != '\0'; p++)
1031 {
1032 if (*p == ' ')
1033 break;
1034 if (*p == '.')
1035 pdot = p;
1036 }
1037
1038 if (p == instring)
1039 {
1040 the_ins.error = _("No operator");
1041 return;
1042 }
1043
1044 /* p now points to the end of the opcode name, probably whitespace.
1045 Make sure the name is null terminated by clobbering the
1046 whitespace, look it up in the hash table, then fix it back.
1047 Remove a dot, first, since the opcode tables have none. */
1048 if (pdot != NULL)
1049 {
1050 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1051 *pdotmove = pdotmove[1];
1052 p--;
1053 }
1054
1055 c = *p;
1056 *p = '\0';
1057 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1058 *p = c;
1059
1060 if (pdot != NULL)
1061 {
1062 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1063 *pdotmove = pdotmove[-1];
1064 *pdot = '.';
1065 ++p;
1066 }
1067
1068 if (opcode == NULL)
1069 {
1070 the_ins.error = _("Unknown operator");
1071 return;
1072 }
1073
1074 /* found a legitimate opcode, start matching operands */
1075 while (*p == ' ')
1076 ++p;
1077
1078 if (opcode->m_operands == 0)
1079 {
1080 char *old = input_line_pointer;
1081 *old = '\n';
1082 input_line_pointer = p;
1083 /* Ahh - it's a motorola style psuedo op */
1084 mote_pseudo_table[opcode->m_opnum].poc_handler
1085 (mote_pseudo_table[opcode->m_opnum].poc_val);
1086 input_line_pointer = old;
1087 *old = 0;
1088
1089 return;
1090 }
1091
1092 if (flag_mri && opcode->m_opnum == 0)
1093 {
1094 /* In MRI mode, random garbage is allowed after an instruction
1095 which accepts no operands. */
1096 the_ins.args = opcode->m_operands;
1097 the_ins.numargs = opcode->m_opnum;
1098 the_ins.numo = opcode->m_codenum;
1099 the_ins.opcode[0] = getone (opcode);
1100 the_ins.opcode[1] = gettwo (opcode);
1101 return;
1102 }
1103
1104 for (opP = &the_ins.operands[0]; *p; opP++)
1105 {
1106 p = crack_operand (p, opP);
1107
1108 if (opP->error)
1109 {
1110 the_ins.error = opP->error;
1111 return;
1112 }
1113 }
1114
1115 opsfound = opP - &the_ins.operands[0];
1116
1117 /* This ugly hack is to support the floating pt opcodes in their
1118 standard form. Essentially, we fake a first enty of type COP#1 */
1119 if (opcode->m_operands[0] == 'I')
1120 {
1121 int n;
1122
1123 for (n = opsfound; n > 0; --n)
1124 the_ins.operands[n] = the_ins.operands[n - 1];
1125
1126 memset ((char *) (&the_ins.operands[0]), '\0',
1127 sizeof (the_ins.operands[0]));
1128 the_ins.operands[0].mode = CONTROL;
1129 the_ins.operands[0].reg = m68k_float_copnum;
1130 opsfound++;
1131 }
1132
1133 /* We've got the operands. Find an opcode that'll accept them */
1134 for (losing = 0;;)
1135 {
1136 /* If we didn't get the right number of ops, or we have no
1137 common model with this pattern then reject this pattern. */
1138
1139 ok_arch |= opcode->m_arch;
1140 if (opsfound != opcode->m_opnum
1141 || ((opcode->m_arch & current_architecture) == 0))
1142 ++losing;
1143 else
1144 {
1145 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1146 *s && !losing;
1147 s += 2, opP++)
1148 {
1149 /* Warning: this switch is huge! */
1150 /* I've tried to organize the cases into this order:
1151 non-alpha first, then alpha by letter. Lower-case
1152 goes directly before uppercase counterpart. */
1153 /* Code with multiple case ...: gets sorted by the lowest
1154 case ... it belongs to. I hope this makes sense. */
1155 switch (*s)
1156 {
1157 case '!':
1158 switch (opP->mode)
1159 {
1160 case IMMED:
1161 case DREG:
1162 case AREG:
1163 case FPREG:
1164 case CONTROL:
1165 case AINC:
1166 case ADEC:
1167 case REGLST:
1168 losing++;
1169 break;
1170 default:
1171 break;
1172 }
1173 break;
1174
1175 case '<':
1176 switch (opP->mode)
1177 {
1178 case DREG:
1179 case AREG:
1180 case FPREG:
1181 case CONTROL:
1182 case IMMED:
1183 case ADEC:
1184 case REGLST:
1185 losing++;
1186 break;
1187 default:
1188 break;
1189 }
1190 break;
1191
1192 case '>':
1193 switch (opP->mode)
1194 {
1195 case DREG:
1196 case AREG:
1197 case FPREG:
1198 case CONTROL:
1199 case IMMED:
1200 case AINC:
1201 case REGLST:
1202 losing++;
1203 break;
1204 case ABSL:
1205 break;
1206 default:
1207 if (opP->reg == PC
1208 || opP->reg == ZPC)
1209 losing++;
1210 break;
1211 }
1212 break;
1213
1214 case 'm':
1215 switch (opP->mode)
1216 {
1217 case DREG:
1218 case AREG:
1219 case AINDR:
1220 case AINC:
1221 case ADEC:
1222 break;
1223 default:
1224 losing++;
1225 }
1226 break;
1227
1228 case 'n':
1229 switch (opP->mode)
1230 {
1231 case DISP:
1232 break;
1233 default:
1234 losing++;
1235 }
1236 break;
1237
1238 case 'o':
1239 switch (opP->mode)
1240 {
1241 case BASE:
1242 case ABSL:
1243 case IMMED:
1244 break;
1245 default:
1246 losing++;
1247 }
1248 break;
1249
1250 case 'p':
1251 switch (opP->mode)
1252 {
1253 case DREG:
1254 case AREG:
1255 case AINDR:
1256 case AINC:
1257 case ADEC:
1258 break;
1259 case DISP:
1260 if (opP->reg == PC || opP->reg == ZPC)
1261 losing++;
1262 break;
1263 default:
1264 losing++;
1265 }
1266 break;
1267
1268 case 'q':
1269 switch (opP->mode)
1270 {
1271 case DREG:
1272 case AINDR:
1273 case AINC:
1274 case ADEC:
1275 break;
1276 case DISP:
1277 if (opP->reg == PC || opP->reg == ZPC)
1278 losing++;
1279 break;
1280 default:
1281 losing++;
1282 break;
1283 }
1284 break;
1285
1286 case 'v':
1287 switch (opP->mode)
1288 {
1289 case DREG:
1290 case AINDR:
1291 case AINC:
1292 case ADEC:
1293 case ABSL:
1294 break;
1295 case DISP:
1296 if (opP->reg == PC || opP->reg == ZPC)
1297 losing++;
1298 break;
1299 default:
1300 losing++;
1301 break;
1302 }
1303 break;
1304
1305 case '#':
1306 if (opP->mode != IMMED)
1307 losing++;
1308 else if (s[1] == 'b'
1309 && ! isvar (&opP->disp)
1310 && (opP->disp.exp.X_op != O_constant
1311 || ! isbyte (opP->disp.exp.X_add_number)))
1312 losing++;
1313 else if (s[1] == 'B'
1314 && ! isvar (&opP->disp)
1315 && (opP->disp.exp.X_op != O_constant
1316 || ! issbyte (opP->disp.exp.X_add_number)))
1317 losing++;
1318 else if (s[1] == 'w'
1319 && ! isvar (&opP->disp)
1320 && (opP->disp.exp.X_op != O_constant
1321 || ! isword (opP->disp.exp.X_add_number)))
1322 losing++;
1323 else if (s[1] == 'W'
1324 && ! isvar (&opP->disp)
1325 && (opP->disp.exp.X_op != O_constant
1326 || ! issword (opP->disp.exp.X_add_number)))
1327 losing++;
1328 break;
1329
1330 case '^':
1331 case 'T':
1332 if (opP->mode != IMMED)
1333 losing++;
1334 break;
1335
1336 case '$':
1337 if (opP->mode == AREG
1338 || opP->mode == CONTROL
1339 || opP->mode == FPREG
1340 || opP->mode == IMMED
1341 || opP->mode == REGLST
1342 || (opP->mode != ABSL
1343 && (opP->reg == PC
1344 || opP->reg == ZPC)))
1345 losing++;
1346 break;
1347
1348 case '%':
1349 if (opP->mode == CONTROL
1350 || opP->mode == FPREG
1351 || opP->mode == REGLST
1352 || opP->mode == IMMED
1353 || (opP->mode != ABSL
1354 && (opP->reg == PC
1355 || opP->reg == ZPC)))
1356 losing++;
1357 break;
1358
1359 case '&':
1360 switch (opP->mode)
1361 {
1362 case DREG:
1363 case AREG:
1364 case FPREG:
1365 case CONTROL:
1366 case IMMED:
1367 case AINC:
1368 case ADEC:
1369 case REGLST:
1370 losing++;
1371 break;
1372 case ABSL:
1373 break;
1374 default:
1375 if (opP->reg == PC
1376 || opP->reg == ZPC)
1377 losing++;
1378 break;
1379 }
1380 break;
1381
1382 case '*':
1383 if (opP->mode == CONTROL
1384 || opP->mode == FPREG
1385 || opP->mode == REGLST)
1386 losing++;
1387 break;
1388
1389 case '+':
1390 if (opP->mode != AINC)
1391 losing++;
1392 break;
1393
1394 case '-':
1395 if (opP->mode != ADEC)
1396 losing++;
1397 break;
1398
1399 case '/':
1400 switch (opP->mode)
1401 {
1402 case AREG:
1403 case CONTROL:
1404 case FPREG:
1405 case AINC:
1406 case ADEC:
1407 case IMMED:
1408 case REGLST:
1409 losing++;
1410 break;
1411 default:
1412 break;
1413 }
1414 break;
1415
1416 case ';':
1417 switch (opP->mode)
1418 {
1419 case AREG:
1420 case CONTROL:
1421 case FPREG:
1422 case REGLST:
1423 losing++;
1424 break;
1425 default:
1426 break;
1427 }
1428 break;
1429
1430 case '?':
1431 switch (opP->mode)
1432 {
1433 case AREG:
1434 case CONTROL:
1435 case FPREG:
1436 case AINC:
1437 case ADEC:
1438 case IMMED:
1439 case REGLST:
1440 losing++;
1441 break;
1442 case ABSL:
1443 break;
1444 default:
1445 if (opP->reg == PC || opP->reg == ZPC)
1446 losing++;
1447 break;
1448 }
1449 break;
1450
1451 case '@':
1452 switch (opP->mode)
1453 {
1454 case AREG:
1455 case CONTROL:
1456 case FPREG:
1457 case IMMED:
1458 case REGLST:
1459 losing++;
1460 break;
1461 default:
1462 break;
1463 }
1464 break;
1465
1466 case '~': /* For now! (JF FOO is this right?) */
1467 switch (opP->mode)
1468 {
1469 case DREG:
1470 case AREG:
1471 case CONTROL:
1472 case FPREG:
1473 case IMMED:
1474 case REGLST:
1475 losing++;
1476 break;
1477 case ABSL:
1478 break;
1479 default:
1480 if (opP->reg == PC
1481 || opP->reg == ZPC)
1482 losing++;
1483 break;
1484 }
1485 break;
1486
1487 case '3':
1488 if (opP->mode != CONTROL
1489 || (opP->reg != TT0 && opP->reg != TT1))
1490 losing++;
1491 break;
1492
1493 case 'A':
1494 if (opP->mode != AREG)
1495 losing++;
1496 break;
1497
1498 case 'a':
1499 if (opP->mode != AINDR)
1500 ++losing;
1501 break;
1502
1503 case 'B': /* FOO */
1504 if (opP->mode != ABSL
1505 || (flag_long_jumps
1506 && strncmp (instring, "jbsr", 4) == 0))
1507 losing++;
1508 break;
1509
1510 case 'C':
1511 if (opP->mode != CONTROL || opP->reg != CCR)
1512 losing++;
1513 break;
1514
1515 case 'd':
1516 if (opP->mode != DISP
1517 || opP->reg < ADDR0
1518 || opP->reg > ADDR7)
1519 losing++;
1520 break;
1521
1522 case 'D':
1523 if (opP->mode != DREG)
1524 losing++;
1525 break;
1526
1527 case 'E':
1528 if (opP->reg != ACC)
1529 losing++;
1530 break;
1531
1532 case 'F':
1533 if (opP->mode != FPREG)
1534 losing++;
1535 break;
1536
1537 case 'G':
1538 if (opP->reg != MACSR)
1539 losing++;
1540 break;
1541
1542 case 'H':
1543 if (opP->reg != MASK)
1544 losing++;
1545 break;
1546
1547 case 'I':
1548 if (opP->mode != CONTROL
1549 || opP->reg < COP0
1550 || opP->reg > COP7)
1551 losing++;
1552 break;
1553
1554 case 'J':
1555 if (opP->mode != CONTROL
1556 || opP->reg < USP
1557 || opP->reg > last_movec_reg)
1558 losing++;
1559 else
1560 {
1561 const enum m68k_register *rp;
1562 for (rp = control_regs; *rp; rp++)
1563 if (*rp == opP->reg)
1564 break;
1565 if (*rp == 0)
1566 losing++;
1567 }
1568 break;
1569
1570 case 'k':
1571 if (opP->mode != IMMED)
1572 losing++;
1573 break;
1574
1575 case 'l':
1576 case 'L':
1577 if (opP->mode == DREG
1578 || opP->mode == AREG
1579 || opP->mode == FPREG)
1580 {
1581 if (s[1] == '8')
1582 losing++;
1583 else
1584 {
1585 switch (opP->mode)
1586 {
1587 case DREG:
1588 opP->mask = 1 << (opP->reg - DATA0);
1589 break;
1590 case AREG:
1591 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1592 break;
1593 case FPREG:
1594 opP->mask = 1 << (opP->reg - FP0 + 16);
1595 break;
1596 default:
1597 abort ();
1598 }
1599 opP->mode = REGLST;
1600 }
1601 }
1602 else if (opP->mode == CONTROL)
1603 {
1604 if (s[1] != '8')
1605 losing++;
1606 else
1607 {
1608 switch (opP->reg)
1609 {
1610 case FPI:
1611 opP->mask = 1 << 24;
1612 break;
1613 case FPS:
1614 opP->mask = 1 << 25;
1615 break;
1616 case FPC:
1617 opP->mask = 1 << 26;
1618 break;
1619 default:
1620 losing++;
1621 break;
1622 }
1623 opP->mode = REGLST;
1624 }
1625 }
1626 else if (opP->mode != REGLST)
1627 losing++;
1628 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1629 losing++;
1630 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1631 losing++;
1632 break;
1633
1634 case 'M':
1635 if (opP->mode != IMMED)
1636 losing++;
1637 else if (opP->disp.exp.X_op != O_constant
1638 || ! issbyte (opP->disp.exp.X_add_number))
1639 losing++;
1640 else if (! m68k_quick
1641 && instring[3] != 'q'
1642 && instring[4] != 'q')
1643 losing++;
1644 break;
1645
1646 case 'O':
1647 if (opP->mode != DREG
1648 && opP->mode != IMMED
1649 && opP->mode != ABSL)
1650 losing++;
1651 break;
1652
1653 case 'Q':
1654 if (opP->mode != IMMED)
1655 losing++;
1656 else if (opP->disp.exp.X_op != O_constant
1657 || opP->disp.exp.X_add_number < 1
1658 || opP->disp.exp.X_add_number > 8)
1659 losing++;
1660 else if (! m68k_quick
1661 && (strncmp (instring, "add", 3) == 0
1662 || strncmp (instring, "sub", 3) == 0)
1663 && instring[3] != 'q')
1664 losing++;
1665 break;
1666
1667 case 'R':
1668 if (opP->mode != DREG && opP->mode != AREG)
1669 losing++;
1670 break;
1671
1672 case 'r':
1673 if (opP->mode != AINDR
1674 && (opP->mode != BASE
1675 || (opP->reg != 0
1676 && opP->reg != ZADDR0)
1677 || opP->disp.exp.X_op != O_absent
1678 || ((opP->index.reg < DATA0
1679 || opP->index.reg > DATA7)
1680 && (opP->index.reg < ADDR0
1681 || opP->index.reg > ADDR7))
1682 || opP->index.size != SIZE_UNSPEC
1683 || opP->index.scale != 1))
1684 losing++;
1685 break;
1686
1687 case 's':
1688 if (opP->mode != CONTROL
1689 || ! (opP->reg == FPI
1690 || opP->reg == FPS
1691 || opP->reg == FPC))
1692 losing++;
1693 break;
1694
1695 case 'S':
1696 if (opP->mode != CONTROL || opP->reg != SR)
1697 losing++;
1698 break;
1699
1700 case 't':
1701 if (opP->mode != IMMED)
1702 losing++;
1703 else if (opP->disp.exp.X_op != O_constant
1704 || opP->disp.exp.X_add_number < 0
1705 || opP->disp.exp.X_add_number > 7)
1706 losing++;
1707 break;
1708
1709 case 'U':
1710 if (opP->mode != CONTROL || opP->reg != USP)
1711 losing++;
1712 break;
1713
1714 /* JF these are out of order. We could put them
1715 in order if we were willing to put up with
1716 bunches of #ifdef m68851s in the code.
1717
1718 Don't forget that you need these operands
1719 to use 68030 MMU instructions. */
1720 #ifndef NO_68851
1721 /* Memory addressing mode used by pflushr */
1722 case '|':
1723 if (opP->mode == CONTROL
1724 || opP->mode == FPREG
1725 || opP->mode == DREG
1726 || opP->mode == AREG
1727 || opP->mode == REGLST)
1728 losing++;
1729 /* We should accept immediate operands, but they
1730 supposedly have to be quad word, and we don't
1731 handle that. I would like to see what a Motorola
1732 assembler does before doing something here. */
1733 if (opP->mode == IMMED)
1734 losing++;
1735 break;
1736
1737 case 'f':
1738 if (opP->mode != CONTROL
1739 || (opP->reg != SFC && opP->reg != DFC))
1740 losing++;
1741 break;
1742
1743 case '0':
1744 if (opP->mode != CONTROL || opP->reg != TC)
1745 losing++;
1746 break;
1747
1748 case '1':
1749 if (opP->mode != CONTROL || opP->reg != AC)
1750 losing++;
1751 break;
1752
1753 case '2':
1754 if (opP->mode != CONTROL
1755 || (opP->reg != CAL
1756 && opP->reg != VAL
1757 && opP->reg != SCC))
1758 losing++;
1759 break;
1760
1761 case 'V':
1762 if (opP->mode != CONTROL
1763 || opP->reg != VAL)
1764 losing++;
1765 break;
1766
1767 case 'W':
1768 if (opP->mode != CONTROL
1769 || (opP->reg != DRP
1770 && opP->reg != SRP
1771 && opP->reg != CRP))
1772 losing++;
1773 break;
1774
1775 case 'X':
1776 if (opP->mode != CONTROL
1777 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1778 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1779 losing++;
1780 break;
1781
1782 case 'Y':
1783 if (opP->mode != CONTROL || opP->reg != PSR)
1784 losing++;
1785 break;
1786
1787 case 'Z':
1788 if (opP->mode != CONTROL || opP->reg != PCSR)
1789 losing++;
1790 break;
1791 #endif
1792 case 'c':
1793 if (opP->mode != CONTROL
1794 || (opP->reg != NC
1795 && opP->reg != IC
1796 && opP->reg != DC
1797 && opP->reg != BC))
1798 {
1799 losing++;
1800 } /* not a cache specifier. */
1801 break;
1802
1803 case '_':
1804 if (opP->mode != ABSL)
1805 ++losing;
1806 break;
1807
1808 case 'u':
1809 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1810 losing++;
1811 /* FIXME: kludge instead of fixing parser:
1812 upper/lower registers are *not* CONTROL
1813 registers, but ordinary ones. */
1814 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1815 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1816 opP->mode = DREG;
1817 else
1818 opP->mode = AREG;
1819 break;
1820
1821 default:
1822 abort ();
1823 } /* switch on type of operand */
1824
1825 if (losing)
1826 break;
1827 } /* for each operand */
1828 } /* if immediately wrong */
1829
1830 if (!losing)
1831 {
1832 break;
1833 } /* got it. */
1834
1835 opcode = opcode->m_next;
1836
1837 if (!opcode)
1838 {
1839 if (ok_arch
1840 && !(ok_arch & current_architecture))
1841 {
1842 char buf[200], *cp;
1843
1844 strcpy (buf,
1845 _("invalid instruction for this architecture; needs "));
1846 cp = buf + strlen (buf);
1847 switch (ok_arch)
1848 {
1849 case mfloat:
1850 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1851 break;
1852 case mmmu:
1853 strcpy (cp, _("mmu (68030 or 68851)"));
1854 break;
1855 case m68020up:
1856 strcpy (cp, _("68020 or higher"));
1857 break;
1858 case m68000up:
1859 strcpy (cp, _("68000 or higher"));
1860 break;
1861 case m68010up:
1862 strcpy (cp, _("68010 or higher"));
1863 break;
1864 default:
1865 {
1866 int got_one = 0, idx;
1867 for (idx = 0;
1868 idx < (int) (sizeof (archs) / sizeof (archs[0]));
1869 idx++)
1870 {
1871 if ((archs[idx].arch & ok_arch)
1872 && ! archs[idx].alias)
1873 {
1874 if (got_one)
1875 {
1876 strcpy (cp, " or ");
1877 cp += strlen (cp);
1878 }
1879 got_one = 1;
1880 strcpy (cp, archs[idx].name);
1881 cp += strlen (cp);
1882 }
1883 }
1884 }
1885 }
1886 cp = xmalloc (strlen (buf) + 1);
1887 strcpy (cp, buf);
1888 the_ins.error = cp;
1889 }
1890 else
1891 the_ins.error = _("operands mismatch");
1892 return;
1893 } /* Fell off the end */
1894
1895 losing = 0;
1896 }
1897
1898 /* now assemble it */
1899
1900 the_ins.args = opcode->m_operands;
1901 the_ins.numargs = opcode->m_opnum;
1902 the_ins.numo = opcode->m_codenum;
1903 the_ins.opcode[0] = getone (opcode);
1904 the_ins.opcode[1] = gettwo (opcode);
1905
1906 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1907 {
1908 /* This switch is a doozy.
1909 Watch the first step; its a big one! */
1910 switch (s[0])
1911 {
1912
1913 case '*':
1914 case '~':
1915 case '%':
1916 case ';':
1917 case '@':
1918 case '!':
1919 case '&':
1920 case '$':
1921 case '?':
1922 case '/':
1923 case '<':
1924 case '>':
1925 case 'm':
1926 case 'n':
1927 case 'o':
1928 case 'p':
1929 case 'q':
1930 case 'v':
1931 #ifndef NO_68851
1932 case '|':
1933 #endif
1934 switch (opP->mode)
1935 {
1936 case IMMED:
1937 tmpreg = 0x3c; /* 7.4 */
1938 if (strchr ("bwl", s[1]))
1939 nextword = get_num (&opP->disp, 80);
1940 else
1941 nextword = get_num (&opP->disp, 0);
1942 if (isvar (&opP->disp))
1943 add_fix (s[1], &opP->disp, 0, 0);
1944 switch (s[1])
1945 {
1946 case 'b':
1947 if (!isbyte (nextword))
1948 opP->error = _("operand out of range");
1949 addword (nextword);
1950 baseo = 0;
1951 break;
1952 case 'w':
1953 if (!isword (nextword))
1954 opP->error = _("operand out of range");
1955 addword (nextword);
1956 baseo = 0;
1957 break;
1958 case 'W':
1959 if (!issword (nextword))
1960 opP->error = _("operand out of range");
1961 addword (nextword);
1962 baseo = 0;
1963 break;
1964 case 'l':
1965 addword (nextword >> 16);
1966 addword (nextword);
1967 baseo = 0;
1968 break;
1969
1970 case 'f':
1971 baseo = 2;
1972 outro = 8;
1973 break;
1974 case 'F':
1975 baseo = 4;
1976 outro = 11;
1977 break;
1978 case 'x':
1979 baseo = 6;
1980 outro = 15;
1981 break;
1982 case 'p':
1983 baseo = 6;
1984 outro = -1;
1985 break;
1986 default:
1987 abort ();
1988 }
1989 if (!baseo)
1990 break;
1991
1992 /* We gotta put out some float */
1993 if (op (&opP->disp) != O_big)
1994 {
1995 valueT val;
1996 int gencnt;
1997
1998 /* Can other cases happen here? */
1999 if (op (&opP->disp) != O_constant)
2000 abort ();
2001
2002 val = (valueT) offs (&opP->disp);
2003 gencnt = 0;
2004 do
2005 {
2006 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2007 val >>= LITTLENUM_NUMBER_OF_BITS;
2008 ++gencnt;
2009 }
2010 while (val != 0);
2011 offs (&opP->disp) = gencnt;
2012 }
2013 if (offs (&opP->disp) > 0)
2014 {
2015 if (offs (&opP->disp) > baseo)
2016 {
2017 as_warn (_("Bignum too big for %c format; truncated"),
2018 s[1]);
2019 offs (&opP->disp) = baseo;
2020 }
2021 baseo -= offs (&opP->disp);
2022 while (baseo--)
2023 addword (0);
2024 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2025 offs (&opP->disp)--;
2026 --wordp)
2027 addword (*wordp);
2028 break;
2029 }
2030 gen_to_words (words, baseo, (long) outro);
2031 for (wordp = words; baseo--; wordp++)
2032 addword (*wordp);
2033 break;
2034 case DREG:
2035 tmpreg = opP->reg - DATA; /* 0.dreg */
2036 break;
2037 case AREG:
2038 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2039 break;
2040 case AINDR:
2041 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2042 break;
2043 case ADEC:
2044 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2045 break;
2046 case AINC:
2047 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2048 break;
2049 case DISP:
2050
2051 nextword = get_num (&opP->disp, 80);
2052
2053 if (opP->reg == PC
2054 && ! isvar (&opP->disp)
2055 && m68k_abspcadd)
2056 {
2057 opP->disp.exp.X_op = O_symbol;
2058 #ifndef BFD_ASSEMBLER
2059 opP->disp.exp.X_add_symbol = &abs_symbol;
2060 #else
2061 opP->disp.exp.X_add_symbol =
2062 section_symbol (absolute_section);
2063 #endif
2064 }
2065
2066 /* Force into index mode. Hope this works */
2067
2068 /* We do the first bit for 32-bit displacements, and the
2069 second bit for 16 bit ones. It is possible that we
2070 should make the default be WORD instead of LONG, but
2071 I think that'd break GCC, so we put up with a little
2072 inefficiency for the sake of working output. */
2073
2074 if (!issword (nextword)
2075 || (isvar (&opP->disp)
2076 && ((opP->disp.size == SIZE_UNSPEC
2077 && flag_short_refs == 0
2078 && cpu_of_arch (current_architecture) >= m68020
2079 && ! arch_coldfire_p (current_architecture))
2080 || opP->disp.size == SIZE_LONG)))
2081 {
2082 if (cpu_of_arch (current_architecture) < m68020
2083 || arch_coldfire_p (current_architecture))
2084 opP->error =
2085 _("displacement too large for this architecture; needs 68020 or higher");
2086 if (opP->reg == PC)
2087 tmpreg = 0x3B; /* 7.3 */
2088 else
2089 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2090 if (isvar (&opP->disp))
2091 {
2092 if (opP->reg == PC)
2093 {
2094 if (opP->disp.size == SIZE_LONG
2095 #ifdef OBJ_ELF
2096 /* If the displacement needs pic
2097 relocation it cannot be relaxed. */
2098 || opP->disp.pic_reloc != pic_none
2099 #endif
2100 )
2101 {
2102 addword (0x0170);
2103 add_fix ('l', &opP->disp, 1, 2);
2104 }
2105 else
2106 {
2107 add_frag (adds (&opP->disp),
2108 offs (&opP->disp),
2109 TAB (PCREL1632, SZ_UNDEF));
2110 break;
2111 }
2112 }
2113 else
2114 {
2115 addword (0x0170);
2116 add_fix ('l', &opP->disp, 0, 0);
2117 }
2118 }
2119 else
2120 addword (0x0170);
2121 addword (nextword >> 16);
2122 }
2123 else
2124 {
2125 if (opP->reg == PC)
2126 tmpreg = 0x3A; /* 7.2 */
2127 else
2128 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2129
2130 if (isvar (&opP->disp))
2131 {
2132 if (opP->reg == PC)
2133 {
2134 add_fix ('w', &opP->disp, 1, 0);
2135 }
2136 else
2137 add_fix ('w', &opP->disp, 0, 0);
2138 }
2139 }
2140 addword (nextword);
2141 break;
2142
2143 case POST:
2144 case PRE:
2145 case BASE:
2146 nextword = 0;
2147 baseo = get_num (&opP->disp, 80);
2148 if (opP->mode == POST || opP->mode == PRE)
2149 outro = get_num (&opP->odisp, 80);
2150 /* Figure out the `addressing mode'.
2151 Also turn on the BASE_DISABLE bit, if needed. */
2152 if (opP->reg == PC || opP->reg == ZPC)
2153 {
2154 tmpreg = 0x3b; /* 7.3 */
2155 if (opP->reg == ZPC)
2156 nextword |= 0x80;
2157 }
2158 else if (opP->reg == 0)
2159 {
2160 nextword |= 0x80;
2161 tmpreg = 0x30; /* 6.garbage */
2162 }
2163 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2164 {
2165 nextword |= 0x80;
2166 tmpreg = 0x30 + opP->reg - ZADDR0;
2167 }
2168 else
2169 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2170
2171 siz1 = opP->disp.size;
2172 if (opP->mode == POST || opP->mode == PRE)
2173 siz2 = opP->odisp.size;
2174 else
2175 siz2 = SIZE_UNSPEC;
2176
2177 /* Index register stuff */
2178 if (opP->index.reg != 0
2179 && opP->index.reg >= DATA
2180 && opP->index.reg <= ADDR7)
2181 {
2182 nextword |= (opP->index.reg - DATA) << 12;
2183
2184 if (opP->index.size == SIZE_LONG
2185 || (opP->index.size == SIZE_UNSPEC
2186 && m68k_index_width_default == SIZE_LONG))
2187 nextword |= 0x800;
2188
2189 if ((opP->index.scale != 1
2190 && cpu_of_arch (current_architecture) < m68020)
2191 || (opP->index.scale == 8
2192 && arch_coldfire_p (current_architecture)))
2193 {
2194 opP->error =
2195 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2196 }
2197
2198 if (arch_coldfire_p (current_architecture)
2199 && opP->index.size == SIZE_WORD)
2200 opP->error = _("invalid index size for coldfire");
2201
2202 switch (opP->index.scale)
2203 {
2204 case 1:
2205 break;
2206 case 2:
2207 nextword |= 0x200;
2208 break;
2209 case 4:
2210 nextword |= 0x400;
2211 break;
2212 case 8:
2213 nextword |= 0x600;
2214 break;
2215 default:
2216 abort ();
2217 }
2218 /* IF its simple,
2219 GET US OUT OF HERE! */
2220
2221 /* Must be INDEX, with an index register. Address
2222 register cannot be ZERO-PC, and either :b was
2223 forced, or we know it will fit. For a 68000 or
2224 68010, force this mode anyways, because the
2225 larger modes aren't supported. */
2226 if (opP->mode == BASE
2227 && ((opP->reg >= ADDR0
2228 && opP->reg <= ADDR7)
2229 || opP->reg == PC))
2230 {
2231 if (siz1 == SIZE_BYTE
2232 || cpu_of_arch (current_architecture) < m68020
2233 || arch_coldfire_p (current_architecture)
2234 || (siz1 == SIZE_UNSPEC
2235 && ! isvar (&opP->disp)
2236 && issbyte (baseo)))
2237 {
2238 nextword += baseo & 0xff;
2239 addword (nextword);
2240 if (isvar (&opP->disp))
2241 {
2242 /* Do a byte relocation. If it doesn't
2243 fit (possible on m68000) let the
2244 fixup processing complain later. */
2245 if (opP->reg == PC)
2246 add_fix ('B', &opP->disp, 1, 1);
2247 else
2248 add_fix ('B', &opP->disp, 0, 0);
2249 }
2250 else if (siz1 != SIZE_BYTE)
2251 {
2252 if (siz1 != SIZE_UNSPEC)
2253 as_warn (_("Forcing byte displacement"));
2254 if (! issbyte (baseo))
2255 opP->error = _("byte displacement out of range");
2256 }
2257
2258 break;
2259 }
2260 else if (siz1 == SIZE_UNSPEC
2261 && opP->reg == PC
2262 && isvar (&opP->disp)
2263 && subs (&opP->disp) == NULL
2264 #ifdef OBJ_ELF
2265 /* If the displacement needs pic
2266 relocation it cannot be relaxed. */
2267 && opP->disp.pic_reloc == pic_none
2268 #endif
2269 )
2270 {
2271 /* The code in md_convert_frag_1 needs to be
2272 able to adjust nextword. Call frag_grow
2273 to ensure that we have enough space in
2274 the frag obstack to make all the bytes
2275 contiguous. */
2276 frag_grow (14);
2277 nextword += baseo & 0xff;
2278 addword (nextword);
2279 add_frag (adds (&opP->disp), offs (&opP->disp),
2280 TAB (PCINDEX, SZ_UNDEF));
2281
2282 break;
2283 }
2284 }
2285 }
2286 else
2287 {
2288 nextword |= 0x40; /* No index reg */
2289 if (opP->index.reg >= ZDATA0
2290 && opP->index.reg <= ZDATA7)
2291 nextword |= (opP->index.reg - ZDATA0) << 12;
2292 else if (opP->index.reg >= ZADDR0
2293 || opP->index.reg <= ZADDR7)
2294 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2295 }
2296
2297 /* It isn't simple. */
2298
2299 if (cpu_of_arch (current_architecture) < m68020
2300 || arch_coldfire_p (current_architecture))
2301 opP->error =
2302 _("invalid operand mode for this architecture; needs 68020 or higher");
2303
2304 nextword |= 0x100;
2305 /* If the guy specified a width, we assume that it is
2306 wide enough. Maybe it isn't. If so, we lose. */
2307 switch (siz1)
2308 {
2309 case SIZE_UNSPEC:
2310 if (isvar (&opP->disp)
2311 ? m68k_rel32
2312 : ! issword (baseo))
2313 {
2314 siz1 = SIZE_LONG;
2315 nextword |= 0x30;
2316 }
2317 else if (! isvar (&opP->disp) && baseo == 0)
2318 nextword |= 0x10;
2319 else
2320 {
2321 nextword |= 0x20;
2322 siz1 = SIZE_WORD;
2323 }
2324 break;
2325 case SIZE_BYTE:
2326 as_warn (_(":b not permitted; defaulting to :w"));
2327 /* Fall through. */
2328 case SIZE_WORD:
2329 nextword |= 0x20;
2330 break;
2331 case SIZE_LONG:
2332 nextword |= 0x30;
2333 break;
2334 }
2335
2336 /* Figure out innner displacement stuff */
2337 if (opP->mode == POST || opP->mode == PRE)
2338 {
2339 if (cpu_of_arch (current_architecture) & cpu32)
2340 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2341 switch (siz2)
2342 {
2343 case SIZE_UNSPEC:
2344 if (isvar (&opP->odisp)
2345 ? m68k_rel32
2346 : ! issword (outro))
2347 {
2348 siz2 = SIZE_LONG;
2349 nextword |= 0x3;
2350 }
2351 else if (! isvar (&opP->odisp) && outro == 0)
2352 nextword |= 0x1;
2353 else
2354 {
2355 nextword |= 0x2;
2356 siz2 = SIZE_WORD;
2357 }
2358 break;
2359 case 1:
2360 as_warn (_(":b not permitted; defaulting to :w"));
2361 /* Fall through. */
2362 case 2:
2363 nextword |= 0x2;
2364 break;
2365 case 3:
2366 nextword |= 0x3;
2367 break;
2368 }
2369 if (opP->mode == POST
2370 && (nextword & 0x40) == 0)
2371 nextword |= 0x04;
2372 }
2373 addword (nextword);
2374
2375 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2376 {
2377 if (opP->reg == PC || opP->reg == ZPC)
2378 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2379 else
2380 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2381 }
2382 if (siz1 == SIZE_LONG)
2383 addword (baseo >> 16);
2384 if (siz1 != SIZE_UNSPEC)
2385 addword (baseo);
2386
2387 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2388 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2389 if (siz2 == SIZE_LONG)
2390 addword (outro >> 16);
2391 if (siz2 != SIZE_UNSPEC)
2392 addword (outro);
2393
2394 break;
2395
2396 case ABSL:
2397 nextword = get_num (&opP->disp, 80);
2398 switch (opP->disp.size)
2399 {
2400 default:
2401 abort ();
2402 case SIZE_UNSPEC:
2403 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2404 {
2405 tmpreg = 0x38; /* 7.0 */
2406 addword (nextword);
2407 break;
2408 }
2409 if (isvar (&opP->disp)
2410 && !subs (&opP->disp)
2411 && adds (&opP->disp)
2412 #ifdef OBJ_ELF
2413 /* If the displacement needs pic relocation it
2414 cannot be relaxed. */
2415 && opP->disp.pic_reloc == pic_none
2416 #endif
2417 && !flag_long_jumps
2418 && !strchr ("~%&$?", s[0]))
2419 {
2420 tmpreg = 0x3A; /* 7.2 */
2421 add_frag (adds (&opP->disp),
2422 offs (&opP->disp),
2423 TAB (ABSTOPCREL, SZ_UNDEF));
2424 break;
2425 }
2426 /* Fall through into long */
2427 case SIZE_LONG:
2428 if (isvar (&opP->disp))
2429 add_fix ('l', &opP->disp, 0, 0);
2430
2431 tmpreg = 0x39;/* 7.1 mode */
2432 addword (nextword >> 16);
2433 addword (nextword);
2434 break;
2435
2436 case SIZE_BYTE:
2437 as_bad (_("unsupported byte value; use a different suffix"));
2438 /* Fall through. */
2439 case SIZE_WORD: /* Word */
2440 if (isvar (&opP->disp))
2441 add_fix ('w', &opP->disp, 0, 0);
2442
2443 tmpreg = 0x38;/* 7.0 mode */
2444 addword (nextword);
2445 break;
2446 }
2447 break;
2448 case CONTROL:
2449 case FPREG:
2450 default:
2451 as_bad (_("unknown/incorrect operand"));
2452 /* abort (); */
2453 }
2454 install_gen_operand (s[1], tmpreg);
2455 break;
2456
2457 case '#':
2458 case '^':
2459 switch (s[1])
2460 { /* JF: I hate floating point! */
2461 case 'j':
2462 tmpreg = 70;
2463 break;
2464 case '8':
2465 tmpreg = 20;
2466 break;
2467 case 'C':
2468 tmpreg = 50;
2469 break;
2470 case '3':
2471 default:
2472 tmpreg = 80;
2473 break;
2474 }
2475 tmpreg = get_num (&opP->disp, tmpreg);
2476 if (isvar (&opP->disp))
2477 add_fix (s[1], &opP->disp, 0, 0);
2478 switch (s[1])
2479 {
2480 case 'b': /* Danger: These do no check for
2481 certain types of overflow.
2482 user beware! */
2483 if (!isbyte (tmpreg))
2484 opP->error = _("out of range");
2485 insop (tmpreg, opcode);
2486 if (isvar (&opP->disp))
2487 the_ins.reloc[the_ins.nrel - 1].n =
2488 (opcode->m_codenum) * 2 + 1;
2489 break;
2490 case 'B':
2491 if (!issbyte (tmpreg))
2492 opP->error = _("out of range");
2493 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2494 if (isvar (&opP->disp))
2495 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2496 break;
2497 case 'w':
2498 if (!isword (tmpreg))
2499 opP->error = _("out of range");
2500 insop (tmpreg, opcode);
2501 if (isvar (&opP->disp))
2502 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2503 break;
2504 case 'W':
2505 if (!issword (tmpreg))
2506 opP->error = _("out of range");
2507 insop (tmpreg, opcode);
2508 if (isvar (&opP->disp))
2509 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2510 break;
2511 case 'l':
2512 /* Because of the way insop works, we put these two out
2513 backwards. */
2514 insop (tmpreg, opcode);
2515 insop (tmpreg >> 16, opcode);
2516 if (isvar (&opP->disp))
2517 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2518 break;
2519 case '3':
2520 tmpreg &= 0xFF;
2521 case '8':
2522 case 'C':
2523 case 'j':
2524 install_operand (s[1], tmpreg);
2525 break;
2526 default:
2527 abort ();
2528 }
2529 break;
2530
2531 case '+':
2532 case '-':
2533 case 'A':
2534 case 'a':
2535 install_operand (s[1], opP->reg - ADDR);
2536 break;
2537
2538 case 'B':
2539 tmpreg = get_num (&opP->disp, 80);
2540 switch (s[1])
2541 {
2542 case 'B':
2543 add_fix ('B', &opP->disp, 1, -1);
2544 break;
2545 case 'W':
2546 add_fix ('w', &opP->disp, 1, 0);
2547 addword (0);
2548 break;
2549 case 'L':
2550 long_branch:
2551 if (! HAVE_LONG_BRANCH (current_architecture))
2552 as_warn (_("Can't use long branches on 68000/68010/5200"));
2553 the_ins.opcode[0] |= 0xff;
2554 add_fix ('l', &opP->disp, 1, 0);
2555 addword (0);
2556 addword (0);
2557 break;
2558 case 'g':
2559 if (subs (&opP->disp)) /* We can't relax it */
2560 goto long_branch;
2561
2562 #ifdef OBJ_ELF
2563 /* If the displacement needs pic relocation it cannot be
2564 relaxed. */
2565 if (opP->disp.pic_reloc != pic_none)
2566 goto long_branch;
2567 #endif
2568 /* This could either be a symbol, or an absolute
2569 address. If it's an absolute address, turn it into
2570 an absolute jump right here and keep it out of the
2571 relaxer. */
2572 if (adds (&opP->disp) == 0)
2573 {
2574 if (the_ins.opcode[0] == 0x6000) /* jbra */
2575 the_ins.opcode[0] = 0x4EF1;
2576 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2577 the_ins.opcode[0] = 0x4EB1;
2578 else /* jCC */
2579 {
2580 the_ins.opcode[0] ^= 0x0100;
2581 the_ins.opcode[0] |= 0x0006;
2582 addword (0x4EF1);
2583 }
2584 add_fix ('l', &opP->disp, 0, 0);
2585 addword (0);
2586 addword (0);
2587 break;
2588 }
2589
2590 /* Now we know it's going into the relaxer. Now figure
2591 out which mode. We try in this order of preference:
2592 long branch, absolute jump, byte/word branches only. */
2593 if (HAVE_LONG_BRANCH (current_architecture))
2594 add_frag (adds (&opP->disp), offs (&opP->disp),
2595 TAB (BRANCHBWL, SZ_UNDEF));
2596 else if (! flag_keep_pcrel)
2597 {
2598 if ((the_ins.opcode[0] == 0x6000)
2599 || (the_ins.opcode[0] == 0x6100))
2600 add_frag (adds (&opP->disp), offs (&opP->disp),
2601 TAB (BRABSJUNC, SZ_UNDEF));
2602 else
2603 add_frag (adds (&opP->disp), offs (&opP->disp),
2604 TAB (BRABSJCOND, SZ_UNDEF));
2605 }
2606 else
2607 add_frag (adds (&opP->disp), offs (&opP->disp),
2608 TAB (BRANCHBW, SZ_UNDEF));
2609 break;
2610 case 'w':
2611 if (isvar (&opP->disp))
2612 {
2613 /* Check for DBcc instructions. We can relax them,
2614 but only if we have long branches and/or absolute
2615 jumps. */
2616 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2617 && (HAVE_LONG_BRANCH (current_architecture)
2618 || (! flag_keep_pcrel)))
2619 {
2620 if (HAVE_LONG_BRANCH (current_architecture))
2621 add_frag (adds (&opP->disp), offs (&opP->disp),
2622 TAB (DBCCLBR, SZ_UNDEF));
2623 else
2624 add_frag (adds (&opP->disp), offs (&opP->disp),
2625 TAB (DBCCABSJ, SZ_UNDEF));
2626 break;
2627 }
2628 add_fix ('w', &opP->disp, 1, 0);
2629 }
2630 addword (0);
2631 break;
2632 case 'C': /* Fixed size LONG coproc branches */
2633 add_fix ('l', &opP->disp, 1, 0);
2634 addword (0);
2635 addword (0);
2636 break;
2637 case 'c': /* Var size Coprocesssor branches */
2638 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2639 {
2640 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2641 add_fix ('l', &opP->disp, 1, 0);
2642 addword (0);
2643 addword (0);
2644 }
2645 else
2646 add_frag (adds (&opP->disp), offs (&opP->disp),
2647 TAB (FBRANCH, SZ_UNDEF));
2648 break;
2649 default:
2650 abort ();
2651 }
2652 break;
2653
2654 case 'C': /* Ignore it */
2655 break;
2656
2657 case 'd': /* JF this is a kludge */
2658 install_operand ('s', opP->reg - ADDR);
2659 tmpreg = get_num (&opP->disp, 80);
2660 if (!issword (tmpreg))
2661 {
2662 as_warn (_("Expression out of range, using 0"));
2663 tmpreg = 0;
2664 }
2665 addword (tmpreg);
2666 break;
2667
2668 case 'D':
2669 install_operand (s[1], opP->reg - DATA);
2670 break;
2671
2672 case 'E': /* Ignore it */
2673 break;
2674
2675 case 'F':
2676 install_operand (s[1], opP->reg - FP0);
2677 break;
2678
2679 case 'G': /* Ignore it */
2680 case 'H':
2681 break;
2682
2683 case 'I':
2684 tmpreg = opP->reg - COP0;
2685 install_operand (s[1], tmpreg);
2686 break;
2687
2688 case 'J': /* JF foo */
2689 switch (opP->reg)
2690 {
2691 case SFC:
2692 tmpreg = 0x000;
2693 break;
2694 case DFC:
2695 tmpreg = 0x001;
2696 break;
2697 case CACR:
2698 tmpreg = 0x002;
2699 break;
2700 case TC:
2701 tmpreg = 0x003;
2702 break;
2703 case ITT0:
2704 tmpreg = 0x004;
2705 break;
2706 case ITT1:
2707 tmpreg = 0x005;
2708 break;
2709 case DTT0:
2710 tmpreg = 0x006;
2711 break;
2712 case DTT1:
2713 tmpreg = 0x007;
2714 break;
2715 case BUSCR:
2716 tmpreg = 0x008;
2717 break;
2718
2719 case USP:
2720 tmpreg = 0x800;
2721 break;
2722 case VBR:
2723 tmpreg = 0x801;
2724 break;
2725 case CAAR:
2726 tmpreg = 0x802;
2727 break;
2728 case MSP:
2729 tmpreg = 0x803;
2730 break;
2731 case ISP:
2732 tmpreg = 0x804;
2733 break;
2734 case MMUSR:
2735 tmpreg = 0x805;
2736 break;
2737 case URP:
2738 tmpreg = 0x806;
2739 break;
2740 case SRP:
2741 tmpreg = 0x807;
2742 break;
2743 case PCR:
2744 tmpreg = 0x808;
2745 break;
2746 case ROMBAR:
2747 tmpreg = 0xC00;
2748 break;
2749 case RAMBAR0:
2750 tmpreg = 0xC04;
2751 break;
2752 case RAMBAR1:
2753 tmpreg = 0xC05;
2754 break;
2755 case MBAR:
2756 tmpreg = 0xC0F;
2757 break;
2758 default:
2759 abort ();
2760 }
2761 install_operand (s[1], tmpreg);
2762 break;
2763
2764 case 'k':
2765 tmpreg = get_num (&opP->disp, 55);
2766 install_operand (s[1], tmpreg & 0x7f);
2767 break;
2768
2769 case 'l':
2770 tmpreg = opP->mask;
2771 if (s[1] == 'w')
2772 {
2773 if (tmpreg & 0x7FF0000)
2774 as_bad (_("Floating point register in register list"));
2775 insop (reverse_16_bits (tmpreg), opcode);
2776 }
2777 else
2778 {
2779 if (tmpreg & 0x700FFFF)
2780 as_bad (_("Wrong register in floating-point reglist"));
2781 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2782 }
2783 break;
2784
2785 case 'L':
2786 tmpreg = opP->mask;
2787 if (s[1] == 'w')
2788 {
2789 if (tmpreg & 0x7FF0000)
2790 as_bad (_("Floating point register in register list"));
2791 insop (tmpreg, opcode);
2792 }
2793 else if (s[1] == '8')
2794 {
2795 if (tmpreg & 0x0FFFFFF)
2796 as_bad (_("incorrect register in reglist"));
2797 install_operand (s[1], tmpreg >> 24);
2798 }
2799 else
2800 {
2801 if (tmpreg & 0x700FFFF)
2802 as_bad (_("wrong register in floating-point reglist"));
2803 else
2804 install_operand (s[1], tmpreg >> 16);
2805 }
2806 break;
2807
2808 case 'M':
2809 install_operand (s[1], get_num (&opP->disp, 60));
2810 break;
2811
2812 case 'O':
2813 tmpreg = ((opP->mode == DREG)
2814 ? 0x20 + (int) (opP->reg - DATA)
2815 : (get_num (&opP->disp, 40) & 0x1F));
2816 install_operand (s[1], tmpreg);
2817 break;
2818
2819 case 'Q':
2820 tmpreg = get_num (&opP->disp, 10);
2821 if (tmpreg == 8)
2822 tmpreg = 0;
2823 install_operand (s[1], tmpreg);
2824 break;
2825
2826 case 'R':
2827 /* This depends on the fact that ADDR registers are eight
2828 more than their corresponding DATA regs, so the result
2829 will have the ADDR_REG bit set */
2830 install_operand (s[1], opP->reg - DATA);
2831 break;
2832
2833 case 'r':
2834 if (opP->mode == AINDR)
2835 install_operand (s[1], opP->reg - DATA);
2836 else
2837 install_operand (s[1], opP->index.reg - DATA);
2838 break;
2839
2840 case 's':
2841 if (opP->reg == FPI)
2842 tmpreg = 0x1;
2843 else if (opP->reg == FPS)
2844 tmpreg = 0x2;
2845 else if (opP->reg == FPC)
2846 tmpreg = 0x4;
2847 else
2848 abort ();
2849 install_operand (s[1], tmpreg);
2850 break;
2851
2852 case 'S': /* Ignore it */
2853 break;
2854
2855 case 'T':
2856 install_operand (s[1], get_num (&opP->disp, 30));
2857 break;
2858
2859 case 'U': /* Ignore it */
2860 break;
2861
2862 case 'c':
2863 switch (opP->reg)
2864 {
2865 case NC:
2866 tmpreg = 0;
2867 break;
2868 case DC:
2869 tmpreg = 1;
2870 break;
2871 case IC:
2872 tmpreg = 2;
2873 break;
2874 case BC:
2875 tmpreg = 3;
2876 break;
2877 default:
2878 as_fatal (_("failed sanity check"));
2879 } /* switch on cache token */
2880 install_operand (s[1], tmpreg);
2881 break;
2882 #ifndef NO_68851
2883 /* JF: These are out of order, I fear. */
2884 case 'f':
2885 switch (opP->reg)
2886 {
2887 case SFC:
2888 tmpreg = 0;
2889 break;
2890 case DFC:
2891 tmpreg = 1;
2892 break;
2893 default:
2894 abort ();
2895 }
2896 install_operand (s[1], tmpreg);
2897 break;
2898
2899 case '0':
2900 case '1':
2901 case '2':
2902 switch (opP->reg)
2903 {
2904 case TC:
2905 tmpreg = 0;
2906 break;
2907 case CAL:
2908 tmpreg = 4;
2909 break;
2910 case VAL:
2911 tmpreg = 5;
2912 break;
2913 case SCC:
2914 tmpreg = 6;
2915 break;
2916 case AC:
2917 tmpreg = 7;
2918 break;
2919 default:
2920 abort ();
2921 }
2922 install_operand (s[1], tmpreg);
2923 break;
2924
2925 case 'V':
2926 if (opP->reg == VAL)
2927 break;
2928 abort ();
2929
2930 case 'W':
2931 switch (opP->reg)
2932 {
2933 case DRP:
2934 tmpreg = 1;
2935 break;
2936 case SRP:
2937 tmpreg = 2;
2938 break;
2939 case CRP:
2940 tmpreg = 3;
2941 break;
2942 default:
2943 abort ();
2944 }
2945 install_operand (s[1], tmpreg);
2946 break;
2947
2948 case 'X':
2949 switch (opP->reg)
2950 {
2951 case BAD:
2952 case BAD + 1:
2953 case BAD + 2:
2954 case BAD + 3:
2955 case BAD + 4:
2956 case BAD + 5:
2957 case BAD + 6:
2958 case BAD + 7:
2959 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2960 break;
2961
2962 case BAC:
2963 case BAC + 1:
2964 case BAC + 2:
2965 case BAC + 3:
2966 case BAC + 4:
2967 case BAC + 5:
2968 case BAC + 6:
2969 case BAC + 7:
2970 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2971 break;
2972
2973 default:
2974 abort ();
2975 }
2976 install_operand (s[1], tmpreg);
2977 break;
2978 case 'Y':
2979 know (opP->reg == PSR);
2980 break;
2981 case 'Z':
2982 know (opP->reg == PCSR);
2983 break;
2984 #endif /* m68851 */
2985 case '3':
2986 switch (opP->reg)
2987 {
2988 case TT0:
2989 tmpreg = 2;
2990 break;
2991 case TT1:
2992 tmpreg = 3;
2993 break;
2994 default:
2995 abort ();
2996 }
2997 install_operand (s[1], tmpreg);
2998 break;
2999 case 't':
3000 tmpreg = get_num (&opP->disp, 20);
3001 install_operand (s[1], tmpreg);
3002 break;
3003 case '_': /* used only for move16 absolute 32-bit address */
3004 if (isvar (&opP->disp))
3005 add_fix ('l', &opP->disp, 0, 0);
3006 tmpreg = get_num (&opP->disp, 80);
3007 addword (tmpreg >> 16);
3008 addword (tmpreg & 0xFFFF);
3009 break;
3010 case 'u':
3011 install_operand (s[1], opP->reg - DATA0L);
3012 opP->reg -= (DATA0L);
3013 opP->reg &= 0x0F; /* remove upper/lower bit */
3014 break;
3015 default:
3016 abort ();
3017 }
3018 }
3019
3020 /* By the time whe get here (FINALLY) the_ins contains the complete
3021 instruction, ready to be emitted. . . */
3022 }
3023
3024 static int
3025 reverse_16_bits (in)
3026 int in;
3027 {
3028 int out = 0;
3029 int n;
3030
3031 static int mask[16] =
3032 {
3033 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3034 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3035 };
3036 for (n = 0; n < 16; n++)
3037 {
3038 if (in & mask[n])
3039 out |= mask[15 - n];
3040 }
3041 return out;
3042 } /* reverse_16_bits() */
3043
3044 static int
3045 reverse_8_bits (in)
3046 int in;
3047 {
3048 int out = 0;
3049 int n;
3050
3051 static int mask[8] =
3052 {
3053 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3054 };
3055
3056 for (n = 0; n < 8; n++)
3057 {
3058 if (in & mask[n])
3059 out |= mask[7 - n];
3060 }
3061 return out;
3062 } /* reverse_8_bits() */
3063
3064 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3065 (that value is chosen in the frag_var call in md_assemble). TYPE
3066 is the subtype of the frag to be generated; its primary type is
3067 rs_machine_dependent.
3068
3069 The TYPE parameter is also used by md_convert_frag_1 and
3070 md_estimate_size_before_relax. The appropriate type of fixup will
3071 be emitted by md_convert_frag_1.
3072
3073 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3074 static void
3075 install_operand (mode, val)
3076 int mode;
3077 int val;
3078 {
3079 switch (mode)
3080 {
3081 case 's':
3082 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3083 break;
3084 case 'd':
3085 the_ins.opcode[0] |= val << 9;
3086 break;
3087 case '1':
3088 the_ins.opcode[1] |= val << 12;
3089 break;
3090 case '2':
3091 the_ins.opcode[1] |= val << 6;
3092 break;
3093 case '3':
3094 the_ins.opcode[1] |= val;
3095 break;
3096 case '4':
3097 the_ins.opcode[2] |= val << 12;
3098 break;
3099 case '5':
3100 the_ins.opcode[2] |= val << 6;
3101 break;
3102 case '6':
3103 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3104 three words long! */
3105 the_ins.numo++;
3106 the_ins.opcode[2] |= val;
3107 break;
3108 case '7':
3109 the_ins.opcode[1] |= val << 7;
3110 break;
3111 case '8':
3112 the_ins.opcode[1] |= val << 10;
3113 break;
3114 #ifndef NO_68851
3115 case '9':
3116 the_ins.opcode[1] |= val << 5;
3117 break;
3118 #endif
3119
3120 case 't':
3121 the_ins.opcode[1] |= (val << 10) | (val << 7);
3122 break;
3123 case 'D':
3124 the_ins.opcode[1] |= (val << 12) | val;
3125 break;
3126 case 'g':
3127 the_ins.opcode[0] |= val = 0xff;
3128 break;
3129 case 'i':
3130 the_ins.opcode[0] |= val << 9;
3131 break;
3132 case 'C':
3133 the_ins.opcode[1] |= val;
3134 break;
3135 case 'j':
3136 the_ins.opcode[1] |= val;
3137 the_ins.numo++; /* What a hack */
3138 break;
3139 case 'k':
3140 the_ins.opcode[1] |= val << 4;
3141 break;
3142 case 'b':
3143 case 'w':
3144 case 'W':
3145 case 'l':
3146 break;
3147 case 'e':
3148 the_ins.opcode[0] |= (val << 6);
3149 break;
3150 case 'L':
3151 the_ins.opcode[1] = (val >> 16);
3152 the_ins.opcode[2] = val & 0xffff;
3153 break;
3154 case 'm':
3155 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3156 the_ins.opcode[0] |= ((val & 0x7) << 9);
3157 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3158 break;
3159 case 'n':
3160 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3161 the_ins.opcode[0] |= ((val & 0x7) << 9);
3162 break;
3163 case 'o':
3164 the_ins.opcode[1] |= val << 12;
3165 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3166 break;
3167 case 'M':
3168 the_ins.opcode[0] |= (val & 0xF);
3169 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3170 break;
3171 case 'N':
3172 the_ins.opcode[1] |= (val & 0xF);
3173 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3174 break;
3175 case 'h':
3176 the_ins.opcode[1] |= ((val != 1) << 10);
3177 break;
3178 case 'c':
3179 default:
3180 as_fatal (_("failed sanity check."));
3181 }
3182 } /* install_operand() */
3183
3184 static void
3185 install_gen_operand (mode, val)
3186 int mode;
3187 int val;
3188 {
3189 switch (mode)
3190 {
3191 case 's':
3192 the_ins.opcode[0] |= val;
3193 break;
3194 case 'd':
3195 /* This is a kludge!!! */
3196 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3197 break;
3198 case 'b':
3199 case 'w':
3200 case 'l':
3201 case 'f':
3202 case 'F':
3203 case 'x':
3204 case 'p':
3205 the_ins.opcode[0] |= val;
3206 break;
3207 /* more stuff goes here */
3208 default:
3209 as_fatal (_("failed sanity check."));
3210 }
3211 } /* install_gen_operand() */
3212
3213 /*
3214 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3215 * then deal with the bitfield hack.
3216 */
3217
3218 static char *
3219 crack_operand (str, opP)
3220 register char *str;
3221 register struct m68k_op *opP;
3222 {
3223 register int parens;
3224 register int c;
3225 register char *beg_str;
3226 int inquote = 0;
3227
3228 if (!str)
3229 {
3230 return str;
3231 }
3232 beg_str = str;
3233 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3234 {
3235 if (! inquote)
3236 {
3237 if (*str == '(')
3238 parens++;
3239 else if (*str == ')')
3240 {
3241 if (!parens)
3242 { /* ERROR */
3243 opP->error = _("Extra )");
3244 return str;
3245 }
3246 --parens;
3247 }
3248 }
3249 if (flag_mri && *str == '\'')
3250 inquote = ! inquote;
3251 }
3252 if (!*str && parens)
3253 { /* ERROR */
3254 opP->error = _("Missing )");
3255 return str;
3256 }
3257 c = *str;
3258 *str = '\0';
3259 if (m68k_ip_op (beg_str, opP) != 0)
3260 {
3261 *str = c;
3262 return str;
3263 }
3264 *str = c;
3265 if (c == '}')
3266 c = *++str; /* JF bitfield hack */
3267 if (c)
3268 {
3269 c = *++str;
3270 if (!c)
3271 as_bad (_("Missing operand"));
3272 }
3273
3274 /* Detect MRI REG symbols and convert them to REGLSTs. */
3275 if (opP->mode == CONTROL && (int)opP->reg < 0)
3276 {
3277 opP->mode = REGLST;
3278 opP->mask = ~(int)opP->reg;
3279 opP->reg = 0;
3280 }
3281
3282 return str;
3283 }
3284
3285 /* This is the guts of the machine-dependent assembler. STR points to a
3286 machine dependent instruction. This function is supposed to emit
3287 the frags/bytes it assembles to.
3288 */
3289
3290 static void
3291 insert_reg (regname, regnum)
3292 const char *regname;
3293 int regnum;
3294 {
3295 char buf[100];
3296 int i;
3297
3298 #ifdef REGISTER_PREFIX
3299 if (!flag_reg_prefix_optional)
3300 {
3301 buf[0] = REGISTER_PREFIX;
3302 strcpy (buf + 1, regname);
3303 regname = buf;
3304 }
3305 #endif
3306
3307 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3308 &zero_address_frag));
3309
3310 for (i = 0; regname[i]; i++)
3311 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3312 buf[i] = '\0';
3313
3314 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3315 &zero_address_frag));
3316 }
3317
3318 struct init_entry
3319 {
3320 const char *name;
3321 int number;
3322 };
3323
3324 static const struct init_entry init_table[] =
3325 {
3326 { "d0", DATA0 },
3327 { "d1", DATA1 },
3328 { "d2", DATA2 },
3329 { "d3", DATA3 },
3330 { "d4", DATA4 },
3331 { "d5", DATA5 },
3332 { "d6", DATA6 },
3333 { "d7", DATA7 },
3334 { "a0", ADDR0 },
3335 { "a1", ADDR1 },
3336 { "a2", ADDR2 },
3337 { "a3", ADDR3 },
3338 { "a4", ADDR4 },
3339 { "a5", ADDR5 },
3340 { "a6", ADDR6 },
3341 { "fp", ADDR6 },
3342 { "a7", ADDR7 },
3343 { "sp", ADDR7 },
3344 { "ssp", ADDR7 },
3345 { "fp0", FP0 },
3346 { "fp1", FP1 },
3347 { "fp2", FP2 },
3348 { "fp3", FP3 },
3349 { "fp4", FP4 },
3350 { "fp5", FP5 },
3351 { "fp6", FP6 },
3352 { "fp7", FP7 },
3353 { "fpi", FPI },
3354 { "fpiar", FPI },
3355 { "fpc", FPI },
3356 { "fps", FPS },
3357 { "fpsr", FPS },
3358 { "fpc", FPC },
3359 { "fpcr", FPC },
3360 { "control", FPC },
3361 { "status", FPS },
3362 { "iaddr", FPI },
3363
3364 { "cop0", COP0 },
3365 { "cop1", COP1 },
3366 { "cop2", COP2 },
3367 { "cop3", COP3 },
3368 { "cop4", COP4 },
3369 { "cop5", COP5 },
3370 { "cop6", COP6 },
3371 { "cop7", COP7 },
3372 { "pc", PC },
3373 { "zpc", ZPC },
3374 { "sr", SR },
3375
3376 { "ccr", CCR },
3377 { "cc", CCR },
3378
3379 { "acc", ACC },
3380 { "macsr", MACSR },
3381 { "mask", MASK },
3382
3383 /* control registers */
3384 { "sfc", SFC }, /* Source Function Code */
3385 { "sfcr", SFC },
3386 { "dfc", DFC }, /* Destination Function Code */
3387 { "dfcr", DFC },
3388 { "cacr", CACR }, /* Cache Control Register */
3389 { "caar", CAAR }, /* Cache Address Register */
3390
3391 { "usp", USP }, /* User Stack Pointer */
3392 { "vbr", VBR }, /* Vector Base Register */
3393 { "msp", MSP }, /* Master Stack Pointer */
3394 { "isp", ISP }, /* Interrupt Stack Pointer */
3395
3396 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3397 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3398 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3399 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3400
3401 /* 68ec040 versions of same */
3402 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3403 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3404 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3405 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3406
3407 /* mcf5200 versions of same. The ColdFire programmer's reference
3408 manual indicated that the order is 2,3,0,1, but Ken Rose
3409 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3410 { "acr0", ITT0 }, /* Access Control Unit 0 */
3411 { "acr1", ITT1 }, /* Access Control Unit 1 */
3412 { "acr2", DTT0 }, /* Access Control Unit 2 */
3413 { "acr3", DTT1 }, /* Access Control Unit 3 */
3414
3415 { "tc", TC }, /* MMU Translation Control Register */
3416 { "tcr", TC },
3417
3418 { "mmusr", MMUSR }, /* MMU Status Register */
3419 { "srp", SRP }, /* User Root Pointer */
3420 { "urp", URP }, /* Supervisor Root Pointer */
3421
3422 { "buscr", BUSCR },
3423 { "pcr", PCR },
3424
3425 { "rombar", ROMBAR }, /* ROM Base Address Register */
3426 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3427 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3428 { "mbar", MBAR }, /* Module Base Address Register */
3429 /* end of control registers */
3430
3431 { "ac", AC },
3432 { "bc", BC },
3433 { "cal", CAL },
3434 { "crp", CRP },
3435 { "drp", DRP },
3436 { "pcsr", PCSR },
3437 { "psr", PSR },
3438 { "scc", SCC },
3439 { "val", VAL },
3440 { "bad0", BAD0 },
3441 { "bad1", BAD1 },
3442 { "bad2", BAD2 },
3443 { "bad3", BAD3 },
3444 { "bad4", BAD4 },
3445 { "bad5", BAD5 },
3446 { "bad6", BAD6 },
3447 { "bad7", BAD7 },
3448 { "bac0", BAC0 },
3449 { "bac1", BAC1 },
3450 { "bac2", BAC2 },
3451 { "bac3", BAC3 },
3452 { "bac4", BAC4 },
3453 { "bac5", BAC5 },
3454 { "bac6", BAC6 },
3455 { "bac7", BAC7 },
3456
3457 { "ic", IC },
3458 { "dc", DC },
3459 { "nc", NC },
3460
3461 { "tt0", TT0 },
3462 { "tt1", TT1 },
3463 /* 68ec030 versions of same */
3464 { "ac0", TT0 },
3465 { "ac1", TT1 },
3466 /* 68ec030 access control unit, identical to 030 MMU status reg */
3467 { "acusr", PSR },
3468
3469 /* Suppressed data and address registers. */
3470 { "zd0", ZDATA0 },
3471 { "zd1", ZDATA1 },
3472 { "zd2", ZDATA2 },
3473 { "zd3", ZDATA3 },
3474 { "zd4", ZDATA4 },
3475 { "zd5", ZDATA5 },
3476 { "zd6", ZDATA6 },
3477 { "zd7", ZDATA7 },
3478 { "za0", ZADDR0 },
3479 { "za1", ZADDR1 },
3480 { "za2", ZADDR2 },
3481 { "za3", ZADDR3 },
3482 { "za4", ZADDR4 },
3483 { "za5", ZADDR5 },
3484 { "za6", ZADDR6 },
3485 { "za7", ZADDR7 },
3486
3487 /* Upper and lower data and address registers, used by macw and msacw. */
3488 { "d0l", DATA0L },
3489 { "d1l", DATA1L },
3490 { "d2l", DATA2L },
3491 { "d3l", DATA3L },
3492 { "d4l", DATA4L },
3493 { "d5l", DATA5L },
3494 { "d6l", DATA6L },
3495 { "d7l", DATA7L },
3496
3497 { "a0l", ADDR0L },
3498 { "a1l", ADDR1L },
3499 { "a2l", ADDR2L },
3500 { "a3l", ADDR3L },
3501 { "a4l", ADDR4L },
3502 { "a5l", ADDR5L },
3503 { "a6l", ADDR6L },
3504 { "a7l", ADDR7L },
3505
3506 { "d0u", DATA0U },
3507 { "d1u", DATA1U },
3508 { "d2u", DATA2U },
3509 { "d3u", DATA3U },
3510 { "d4u", DATA4U },
3511 { "d5u", DATA5U },
3512 { "d6u", DATA6U },
3513 { "d7u", DATA7U },
3514
3515 { "a0u", ADDR0U },
3516 { "a1u", ADDR1U },
3517 { "a2u", ADDR2U },
3518 { "a3u", ADDR3U },
3519 { "a4u", ADDR4U },
3520 { "a5u", ADDR5U },
3521 { "a6u", ADDR6U },
3522 { "a7u", ADDR7U },
3523
3524 { 0, 0 }
3525 };
3526
3527 static void
3528 init_regtable ()
3529 {
3530 int i;
3531 for (i = 0; init_table[i].name; i++)
3532 insert_reg (init_table[i].name, init_table[i].number);
3533 }
3534
3535 static int no_68851, no_68881;
3536
3537 #ifdef OBJ_AOUT
3538 /* a.out machine type. Default to 68020. */
3539 int m68k_aout_machtype = 2;
3540 #endif
3541
3542 void
3543 md_assemble (str)
3544 char *str;
3545 {
3546 const char *er;
3547 short *fromP;
3548 char *toP = NULL;
3549 int m, n = 0;
3550 char *to_beg_P;
3551 int shorts_this_frag;
3552 fixS *fixP;
3553
3554 /* In MRI mode, the instruction and operands are separated by a
3555 space. Anything following the operands is a comment. The label
3556 has already been removed. */
3557 if (flag_mri)
3558 {
3559 char *s;
3560 int fields = 0;
3561 int infield = 0;
3562 int inquote = 0;
3563
3564 for (s = str; *s != '\0'; s++)
3565 {
3566 if ((*s == ' ' || *s == '\t') && ! inquote)
3567 {
3568 if (infield)
3569 {
3570 ++fields;
3571 if (fields >= 2)
3572 {
3573 *s = '\0';
3574 break;
3575 }
3576 infield = 0;
3577 }
3578 }
3579 else
3580 {
3581 if (! infield)
3582 infield = 1;
3583 if (*s == '\'')
3584 inquote = ! inquote;
3585 }
3586 }
3587 }
3588
3589 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3590 m68k_ip (str);
3591 er = the_ins.error;
3592 if (!er)
3593 {
3594 for (n = 0; n < the_ins.numargs; n++)
3595 if (the_ins.operands[n].error)
3596 {
3597 er = the_ins.operands[n].error;
3598 break;
3599 }
3600 }
3601 if (er)
3602 {
3603 as_bad (_("%s -- statement `%s' ignored"), er, str);
3604 return;
3605 }
3606
3607 /* If there is a current label, record that it marks an instruction. */
3608 if (current_label != NULL)
3609 {
3610 current_label->text = 1;
3611 current_label = NULL;
3612 }
3613
3614 if (the_ins.nfrag == 0)
3615 {
3616 /* No frag hacking involved; just put it out */
3617 toP = frag_more (2 * the_ins.numo);
3618 fromP = &the_ins.opcode[0];
3619 for (m = the_ins.numo; m; --m)
3620 {
3621 md_number_to_chars (toP, (long) (*fromP), 2);
3622 toP += 2;
3623 fromP++;
3624 }
3625 /* put out symbol-dependent info */
3626 for (m = 0; m < the_ins.nrel; m++)
3627 {
3628 switch (the_ins.reloc[m].wid)
3629 {
3630 case 'B':
3631 n = 1;
3632 break;
3633 case 'b':
3634 n = 1;
3635 break;
3636 case '3':
3637 n = 1;
3638 break;
3639 case 'w':
3640 case 'W':
3641 n = 2;
3642 break;
3643 case 'l':
3644 n = 4;
3645 break;
3646 default:
3647 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3648 the_ins.reloc[m].wid);
3649 }
3650
3651 fixP = fix_new_exp (frag_now,
3652 ((toP - frag_now->fr_literal)
3653 - the_ins.numo * 2 + the_ins.reloc[m].n),
3654 n,
3655 &the_ins.reloc[m].exp,
3656 the_ins.reloc[m].pcrel,
3657 get_reloc_code (n, the_ins.reloc[m].pcrel,
3658 the_ins.reloc[m].pic_reloc));
3659 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3660 if (the_ins.reloc[m].wid == 'B')
3661 fixP->fx_signed = 1;
3662 }
3663 return;
3664 }
3665
3666 /* There's some frag hacking */
3667 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3668 {
3669 int wid;
3670
3671 if (n == 0)
3672 wid = 2 * the_ins.fragb[n].fragoff;
3673 else
3674 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3675 toP = frag_more (wid);
3676 to_beg_P = toP;
3677 shorts_this_frag = 0;
3678 for (m = wid / 2; m; --m)
3679 {
3680 md_number_to_chars (toP, (long) (*fromP), 2);
3681 toP += 2;
3682 fromP++;
3683 shorts_this_frag++;
3684 }
3685 for (m = 0; m < the_ins.nrel; m++)
3686 {
3687 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3688 {
3689 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3690 break;
3691 }
3692 wid = the_ins.reloc[m].wid;
3693 if (wid == 0)
3694 continue;
3695 the_ins.reloc[m].wid = 0;
3696 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3697
3698 fixP = fix_new_exp (frag_now,
3699 ((toP - frag_now->fr_literal)
3700 - the_ins.numo * 2 + the_ins.reloc[m].n),
3701 wid,
3702 &the_ins.reloc[m].exp,
3703 the_ins.reloc[m].pcrel,
3704 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3705 the_ins.reloc[m].pic_reloc));
3706 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3707 }
3708 (void) frag_var (rs_machine_dependent, 10, 0,
3709 (relax_substateT) (the_ins.fragb[n].fragty),
3710 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3711 }
3712 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3713 shorts_this_frag = 0;
3714 if (n)
3715 {
3716 toP = frag_more (n * sizeof (short));
3717 while (n--)
3718 {
3719 md_number_to_chars (toP, (long) (*fromP), 2);
3720 toP += 2;
3721 fromP++;
3722 shorts_this_frag++;
3723 }
3724 }
3725 for (m = 0; m < the_ins.nrel; m++)
3726 {
3727 int wid;
3728
3729 wid = the_ins.reloc[m].wid;
3730 if (wid == 0)
3731 continue;
3732 the_ins.reloc[m].wid = 0;
3733 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3734
3735 fixP = fix_new_exp (frag_now,
3736 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3737 - shorts_this_frag * 2),
3738 wid,
3739 &the_ins.reloc[m].exp,
3740 the_ins.reloc[m].pcrel,
3741 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3742 the_ins.reloc[m].pic_reloc));
3743 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3744 }
3745 }
3746
3747 void
3748 md_begin ()
3749 {
3750 /*
3751 * md_begin -- set up hash tables with 68000 instructions.
3752 * similar to what the vax assembler does. ---phr
3753 */
3754 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3755 a copy of it at runtime, adding in the information we want but isn't
3756 there. I think it'd be better to have an awk script hack the table
3757 at compile time. Or even just xstr the table and use it as-is. But
3758 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3759 names. */
3760
3761 register const struct m68k_opcode *ins;
3762 register struct m68k_incant *hack, *slak;
3763 register const char *retval = 0; /* empty string, or error msg text */
3764 register int i;
3765 register char c;
3766
3767 if (flag_mri)
3768 {
3769 flag_reg_prefix_optional = 1;
3770 m68k_abspcadd = 1;
3771 if (! m68k_rel32_from_cmdline)
3772 m68k_rel32 = 0;
3773 }
3774
3775 op_hash = hash_new ();
3776
3777 obstack_begin (&robyn, 4000);
3778 for (i = 0; i < m68k_numopcodes; i++)
3779 {
3780 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3781 do
3782 {
3783 ins = &m68k_opcodes[i];
3784 /* We *could* ignore insns that don't match our arch here
3785 but just leaving them out of the hash. */
3786 slak->m_operands = ins->args;
3787 slak->m_opnum = strlen (slak->m_operands) / 2;
3788 slak->m_arch = ins->arch;
3789 slak->m_opcode = ins->opcode;
3790 /* This is kludgey */
3791 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3792 if (i + 1 != m68k_numopcodes
3793 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3794 {
3795 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3796 i++;
3797 }
3798 else
3799 slak->m_next = 0;
3800 slak = slak->m_next;
3801 }
3802 while (slak);
3803
3804 retval = hash_insert (op_hash, ins->name, (char *) hack);
3805 if (retval)
3806 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3807 }
3808
3809 for (i = 0; i < m68k_numaliases; i++)
3810 {
3811 const char *name = m68k_opcode_aliases[i].primary;
3812 const char *alias = m68k_opcode_aliases[i].alias;
3813 PTR val = hash_find (op_hash, name);
3814 if (!val)
3815 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3816 retval = hash_insert (op_hash, alias, val);
3817 if (retval)
3818 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3819 }
3820
3821 /* In MRI mode, all unsized branches are variable sized. Normally,
3822 they are word sized. */
3823 if (flag_mri)
3824 {
3825 static struct m68k_opcode_alias mri_aliases[] =
3826 {
3827 { "bhi", "jhi", },
3828 { "bls", "jls", },
3829 { "bcc", "jcc", },
3830 { "bcs", "jcs", },
3831 { "bne", "jne", },
3832 { "beq", "jeq", },
3833 { "bvc", "jvc", },
3834 { "bvs", "jvs", },
3835 { "bpl", "jpl", },
3836 { "bmi", "jmi", },
3837 { "bge", "jge", },
3838 { "blt", "jlt", },
3839 { "bgt", "jgt", },
3840 { "ble", "jle", },
3841 { "bra", "jra", },
3842 { "bsr", "jbsr", },
3843 };
3844
3845 for (i = 0;
3846 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3847 i++)
3848 {
3849 const char *name = mri_aliases[i].primary;
3850 const char *alias = mri_aliases[i].alias;
3851 PTR val = hash_find (op_hash, name);
3852 if (!val)
3853 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3854 retval = hash_jam (op_hash, alias, val);
3855 if (retval)
3856 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3857 }
3858 }
3859
3860 for (i = 0; i < (int) sizeof (mklower_table); i++)
3861 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3862
3863 for (i = 0; i < (int) sizeof (notend_table); i++)
3864 {
3865 notend_table[i] = 0;
3866 alt_notend_table[i] = 0;
3867 }
3868 notend_table[','] = 1;
3869 notend_table['{'] = 1;
3870 notend_table['}'] = 1;
3871 alt_notend_table['a'] = 1;
3872 alt_notend_table['A'] = 1;
3873 alt_notend_table['d'] = 1;
3874 alt_notend_table['D'] = 1;
3875 alt_notend_table['#'] = 1;
3876 alt_notend_table['&'] = 1;
3877 alt_notend_table['f'] = 1;
3878 alt_notend_table['F'] = 1;
3879 #ifdef REGISTER_PREFIX
3880 alt_notend_table[REGISTER_PREFIX] = 1;
3881 #endif
3882
3883 /* We need to put '(' in alt_notend_table to handle
3884 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3885 */
3886 alt_notend_table['('] = 1;
3887
3888 /* We need to put '@' in alt_notend_table to handle
3889 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3890 */
3891 alt_notend_table['@'] = 1;
3892
3893 /* We need to put digits in alt_notend_table to handle
3894 bfextu %d0{24:1},%d0
3895 */
3896 alt_notend_table['0'] = 1;
3897 alt_notend_table['1'] = 1;
3898 alt_notend_table['2'] = 1;
3899 alt_notend_table['3'] = 1;
3900 alt_notend_table['4'] = 1;
3901 alt_notend_table['5'] = 1;
3902 alt_notend_table['6'] = 1;
3903 alt_notend_table['7'] = 1;
3904 alt_notend_table['8'] = 1;
3905 alt_notend_table['9'] = 1;
3906
3907 #ifndef MIT_SYNTAX_ONLY
3908 /* Insert pseudo ops, these have to go into the opcode table since
3909 gas expects pseudo ops to start with a dot */
3910 {
3911 int n = 0;
3912 while (mote_pseudo_table[n].poc_name)
3913 {
3914 hack = (struct m68k_incant *)
3915 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3916 hash_insert (op_hash,
3917 mote_pseudo_table[n].poc_name, (char *) hack);
3918 hack->m_operands = 0;
3919 hack->m_opnum = n;
3920 n++;
3921 }
3922 }
3923 #endif
3924
3925 init_regtable ();
3926
3927 #ifdef OBJ_ELF
3928 record_alignment (text_section, 2);
3929 record_alignment (data_section, 2);
3930 record_alignment (bss_section, 2);
3931 #endif
3932 }
3933
3934 static void
3935 select_control_regs ()
3936 {
3937 /* Note which set of "movec" control registers is available. */
3938 switch (cpu_of_arch (current_architecture))
3939 {
3940 case m68000:
3941 control_regs = m68000_control_regs;
3942 break;
3943 case m68010:
3944 control_regs = m68010_control_regs;
3945 break;
3946 case m68020:
3947 case m68030:
3948 control_regs = m68020_control_regs;
3949 break;
3950 case m68040:
3951 control_regs = m68040_control_regs;
3952 break;
3953 case m68060:
3954 control_regs = m68060_control_regs;
3955 break;
3956 case cpu32:
3957 control_regs = cpu32_control_regs;
3958 break;
3959 case mcf5200:
3960 case mcf5206e:
3961 case mcf5307:
3962 case mcf5407:
3963 control_regs = mcf_control_regs;
3964 break;
3965 default:
3966 abort ();
3967 }
3968 }
3969
3970 void
3971 m68k_init_after_args ()
3972 {
3973 if (cpu_of_arch (current_architecture) == 0)
3974 {
3975 int i;
3976 const char *default_cpu = TARGET_CPU;
3977
3978 if (*default_cpu == 'm')
3979 default_cpu++;
3980 for (i = 0; i < n_archs; i++)
3981 if (strcasecmp (default_cpu, archs[i].name) == 0)
3982 break;
3983 if (i == n_archs)
3984 {
3985 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3986 current_architecture |= m68020;
3987 }
3988 else
3989 current_architecture |= archs[i].arch;
3990 }
3991 /* Permit m68881 specification with all cpus; those that can't work
3992 with a coprocessor could be doing emulation. */
3993 if (current_architecture & m68851)
3994 {
3995 if (current_architecture & m68040)
3996 {
3997 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
3998 }
3999 }
4000 /* What other incompatibilities could we check for? */
4001
4002 /* Toss in some default assumptions about coprocessors. */
4003 if (!no_68881
4004 && (cpu_of_arch (current_architecture)
4005 /* Can CPU32 have a 68881 coprocessor?? */
4006 & (m68020 | m68030 | cpu32)))
4007 {
4008 current_architecture |= m68881;
4009 }
4010 if (!no_68851
4011 && (cpu_of_arch (current_architecture) & m68020up) != 0
4012 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4013 {
4014 current_architecture |= m68851;
4015 }
4016 if (no_68881 && (current_architecture & m68881))
4017 as_bad (_("options for 68881 and no-68881 both given"));
4018 if (no_68851 && (current_architecture & m68851))
4019 as_bad (_("options for 68851 and no-68851 both given"));
4020
4021 #ifdef OBJ_AOUT
4022 /* Work out the magic number. This isn't very general. */
4023 if (current_architecture & m68000)
4024 m68k_aout_machtype = 0;
4025 else if (current_architecture & m68010)
4026 m68k_aout_machtype = 1;
4027 else if (current_architecture & m68020)
4028 m68k_aout_machtype = 2;
4029 else
4030 m68k_aout_machtype = 2;
4031 #endif
4032
4033 /* Note which set of "movec" control registers is available. */
4034 select_control_regs ();
4035
4036 if (cpu_of_arch (current_architecture) < m68020
4037 || arch_coldfire_p (current_architecture))
4038 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4039 }
4040 \f
4041 /* This is called when a label is defined. */
4042
4043 void
4044 m68k_frob_label (sym)
4045 symbolS *sym;
4046 {
4047 struct label_line *n;
4048
4049 n = (struct label_line *) xmalloc (sizeof *n);
4050 n->next = labels;
4051 n->label = sym;
4052 as_where (&n->file, &n->line);
4053 n->text = 0;
4054 labels = n;
4055 current_label = n;
4056 }
4057
4058 /* This is called when a value that is not an instruction is emitted. */
4059
4060 void
4061 m68k_flush_pending_output ()
4062 {
4063 current_label = NULL;
4064 }
4065
4066 /* This is called at the end of the assembly, when the final value of
4067 the label is known. We warn if this is a text symbol aligned at an
4068 odd location. */
4069
4070 void
4071 m68k_frob_symbol (sym)
4072 symbolS *sym;
4073 {
4074 if (S_GET_SEGMENT (sym) == reg_section
4075 && (int) S_GET_VALUE (sym) < 0)
4076 {
4077 S_SET_SEGMENT (sym, absolute_section);
4078 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4079 }
4080 else if ((S_GET_VALUE (sym) & 1) != 0)
4081 {
4082 struct label_line *l;
4083
4084 for (l = labels; l != NULL; l = l->next)
4085 {
4086 if (l->label == sym)
4087 {
4088 if (l->text)
4089 as_warn_where (l->file, l->line,
4090 _("text label `%s' aligned to odd boundary"),
4091 S_GET_NAME (sym));
4092 break;
4093 }
4094 }
4095 }
4096 }
4097 \f
4098 /* This is called if we go in or out of MRI mode because of the .mri
4099 pseudo-op. */
4100
4101 void
4102 m68k_mri_mode_change (on)
4103 int on;
4104 {
4105 if (on)
4106 {
4107 if (! flag_reg_prefix_optional)
4108 {
4109 flag_reg_prefix_optional = 1;
4110 #ifdef REGISTER_PREFIX
4111 init_regtable ();
4112 #endif
4113 }
4114 m68k_abspcadd = 1;
4115 if (! m68k_rel32_from_cmdline)
4116 m68k_rel32 = 0;
4117 }
4118 else
4119 {
4120 if (! reg_prefix_optional_seen)
4121 {
4122 #ifdef REGISTER_PREFIX_OPTIONAL
4123 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4124 #else
4125 flag_reg_prefix_optional = 0;
4126 #endif
4127 #ifdef REGISTER_PREFIX
4128 init_regtable ();
4129 #endif
4130 }
4131 m68k_abspcadd = 0;
4132 if (! m68k_rel32_from_cmdline)
4133 m68k_rel32 = 1;
4134 }
4135 }
4136
4137 /* Equal to MAX_PRECISION in atof-ieee.c */
4138 #define MAX_LITTLENUMS 6
4139
4140 /* Turn a string in input_line_pointer into a floating point constant
4141 of type TYPE, and store the appropriate bytes in *LITP. The number
4142 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4143 returned, or NULL on OK. */
4144
4145 char *
4146 md_atof (type, litP, sizeP)
4147 char type;
4148 char *litP;
4149 int *sizeP;
4150 {
4151 int prec;
4152 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4153 LITTLENUM_TYPE *wordP;
4154 char *t;
4155
4156 switch (type)
4157 {
4158 case 'f':
4159 case 'F':
4160 case 's':
4161 case 'S':
4162 prec = 2;
4163 break;
4164
4165 case 'd':
4166 case 'D':
4167 case 'r':
4168 case 'R':
4169 prec = 4;
4170 break;
4171
4172 case 'x':
4173 case 'X':
4174 prec = 6;
4175 break;
4176
4177 case 'p':
4178 case 'P':
4179 prec = 6;
4180 break;
4181
4182 default:
4183 *sizeP = 0;
4184 return _("Bad call to MD_ATOF()");
4185 }
4186 t = atof_ieee (input_line_pointer, type, words);
4187 if (t)
4188 input_line_pointer = t;
4189
4190 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4191 for (wordP = words; prec--;)
4192 {
4193 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4194 litP += sizeof (LITTLENUM_TYPE);
4195 }
4196 return 0;
4197 }
4198
4199 void
4200 md_number_to_chars (buf, val, n)
4201 char *buf;
4202 valueT val;
4203 int n;
4204 {
4205 number_to_chars_bigendian (buf, val, n);
4206 }
4207
4208 static void
4209 md_apply_fix_2 (fixP, val)
4210 fixS *fixP;
4211 offsetT val;
4212 {
4213 addressT upper_limit;
4214 offsetT lower_limit;
4215
4216 /* This is unnecessary but it convinces the native rs6000 compiler
4217 to generate the code we want. */
4218 char *buf = fixP->fx_frag->fr_literal;
4219 buf += fixP->fx_where;
4220 /* end ibm compiler workaround */
4221
4222 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
4223
4224 #ifdef OBJ_ELF
4225 if (fixP->fx_addsy)
4226 {
4227 memset (buf, 0, fixP->fx_size);
4228 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4229
4230 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4231 && !S_IS_DEFINED (fixP->fx_addsy)
4232 && !S_IS_WEAK (fixP->fx_addsy))
4233 S_SET_WEAK (fixP->fx_addsy);
4234 return;
4235 }
4236 #endif
4237
4238 #ifdef BFD_ASSEMBLER
4239 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4240 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4241 return;
4242 #endif
4243
4244 switch (fixP->fx_size)
4245 {
4246 /* The cast to offsetT below are necessary to make code correct for
4247 machines where ints are smaller than offsetT */
4248 case 1:
4249 *buf++ = val;
4250 upper_limit = 0x7f;
4251 lower_limit = - (offsetT) 0x80;
4252 break;
4253 case 2:
4254 *buf++ = (val >> 8);
4255 *buf++ = val;
4256 upper_limit = 0x7fff;
4257 lower_limit = - (offsetT) 0x8000;
4258 break;
4259 case 4:
4260 *buf++ = (val >> 24);
4261 *buf++ = (val >> 16);
4262 *buf++ = (val >> 8);
4263 *buf++ = val;
4264 upper_limit = 0x7fffffff;
4265 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4266 break;
4267 default:
4268 BAD_CASE (fixP->fx_size);
4269 }
4270
4271 /* Fix up a negative reloc. */
4272 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4273 {
4274 fixP->fx_addsy = fixP->fx_subsy;
4275 fixP->fx_subsy = NULL;
4276 fixP->fx_tcbit = 1;
4277 }
4278
4279 /* For non-pc-relative values, it's conceivable we might get something
4280 like "0xff" for a byte field. So extend the upper part of the range
4281 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4282 so that we can do any range checking at all. */
4283 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4284 upper_limit = upper_limit * 2 + 1;
4285
4286 if ((addressT) val > upper_limit
4287 && (val > 0 || val < lower_limit))
4288 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4289
4290 /* A one byte PC-relative reloc means a short branch. We can't use
4291 a short branch with a value of 0 or -1, because those indicate
4292 different opcodes (branches with longer offsets). fixup_segment
4293 in write.c may have clobbered fx_pcrel, so we need to examine the
4294 reloc type. */
4295 if ((fixP->fx_pcrel
4296 #ifdef BFD_ASSEMBLER
4297 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4298 #endif
4299 )
4300 && fixP->fx_size == 1
4301 && (fixP->fx_addsy == NULL
4302 || S_IS_DEFINED (fixP->fx_addsy))
4303 && (val == 0 || val == -1))
4304 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4305 }
4306
4307 #ifdef BFD_ASSEMBLER
4308 int
4309 md_apply_fix (fixP, valp)
4310 fixS *fixP;
4311 valueT *valp;
4312 {
4313 md_apply_fix_2 (fixP, (addressT) *valp);
4314 return 1;
4315 }
4316 #else
4317 void md_apply_fix (fixP, val)
4318 fixS *fixP;
4319 long val;
4320 {
4321 md_apply_fix_2 (fixP, (addressT) val);
4322 }
4323 #endif
4324
4325 /* *fragP has been relaxed to its final size, and now needs to have
4326 the bytes inside it modified to conform to the new size There is UGLY
4327 MAGIC here. ..
4328 */
4329 static void
4330 md_convert_frag_1 (fragP)
4331 register fragS *fragP;
4332 {
4333 long disp;
4334 fixS *fixP;
4335
4336 /* Address in object code of the displacement. */
4337 register int object_address = fragP->fr_fix + fragP->fr_address;
4338
4339 /* Address in gas core of the place to store the displacement. */
4340 /* This convinces the native rs6000 compiler to generate the code we
4341 want. */
4342 register char *buffer_address = fragP->fr_literal;
4343 buffer_address += fragP->fr_fix;
4344 /* end ibm compiler workaround */
4345
4346 /* The displacement of the address, from current location. */
4347 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4348 disp = (disp + fragP->fr_offset) - object_address;
4349
4350 #ifdef BFD_ASSEMBLER
4351 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
4352 #endif
4353
4354 switch (fragP->fr_subtype)
4355 {
4356 case TAB (BRANCHBWL, BYTE):
4357 case TAB (BRABSJUNC, BYTE):
4358 case TAB (BRABSJCOND, BYTE):
4359 case TAB (BRANCHBW, BYTE):
4360 know (issbyte (disp));
4361 if (disp == 0)
4362 as_bad (_("short branch with zero offset: use :w"));
4363 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4364 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4365 fixP->fx_pcrel_adjust = -1;
4366 break;
4367 case TAB (BRANCHBWL, SHORT):
4368 case TAB (BRABSJUNC, SHORT):
4369 case TAB (BRABSJCOND, SHORT):
4370 case TAB (BRANCHBW, SHORT):
4371 fragP->fr_opcode[1] = 0x00;
4372 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4373 1, RELAX_RELOC_PC16);
4374 fragP->fr_fix += 2;
4375 break;
4376 case TAB (BRANCHBWL, LONG):
4377 fragP->fr_opcode[1] = (char) 0xFF;
4378 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4379 1, RELAX_RELOC_PC32);
4380 fragP->fr_fix += 4;
4381 break;
4382 case TAB (BRABSJUNC, LONG):
4383 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4384 {
4385 fragP->fr_opcode[0] = 0x4E;
4386 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4387 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4388 0, RELAX_RELOC_ABS32);
4389 fragP->fr_fix += 4;
4390 }
4391 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4392 {
4393 fragP->fr_opcode[0] = 0x4E;
4394 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4395 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4396 0, RELAX_RELOC_ABS32);
4397 fragP->fr_fix += 4;
4398 }
4399 else
4400 {
4401 /* This cannot happen, because jbsr and jbra are the only two
4402 unconditional branches. */
4403 abort ();
4404 }
4405 break;
4406 case TAB (BRABSJCOND, LONG):
4407 /* Only Bcc 68000 instructions can come here. */
4408 /* Change bcc into b!cc/jmp absl long. */
4409
4410 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4411 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4412
4413 /* JF: these used to be fr_opcode[2,3], but they may be in a
4414 different frag, in which case refering to them is a no-no.
4415 Only fr_opcode[0,1] are guaranteed to work. */
4416 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4417 *buffer_address++ = (char) 0xf9;
4418 fragP->fr_fix += 2; /* account for jmp instruction */
4419 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4420 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4421 fragP->fr_fix += 4;
4422 break;
4423 case TAB (FBRANCH, SHORT):
4424 know ((fragP->fr_opcode[1] & 0x40) == 0);
4425 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4426 1, RELAX_RELOC_PC16);
4427 fragP->fr_fix += 2;
4428 break;
4429 case TAB (FBRANCH, LONG):
4430 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4431 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4432 1, RELAX_RELOC_PC32);
4433 fragP->fr_fix += 4;
4434 break;
4435 case TAB (DBCCLBR, SHORT):
4436 case TAB (DBCCABSJ, SHORT):
4437 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4438 1, RELAX_RELOC_PC16);
4439 fragP->fr_fix += 2;
4440 break;
4441 case TAB (DBCCLBR, LONG):
4442 /* only DBcc instructions can come here */
4443 /* Change dbcc into dbcc/bral. */
4444
4445 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4446 *buffer_address++ = 0x00; /* branch offset = 4 */
4447 *buffer_address++ = 0x04;
4448 *buffer_address++ = 0x60; /* put in bra pc+6 */
4449 *buffer_address++ = 0x06;
4450 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4451 *buffer_address++ = (char) 0xff;
4452
4453 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4454 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4455 RELAX_RELOC_PC32);
4456 fragP->fr_fix += 4;
4457 break;
4458 case TAB (DBCCABSJ, LONG):
4459 /* only DBcc instructions can come here */
4460 /* Change dbcc into dbcc/jmp. */
4461
4462 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4463 *buffer_address++ = 0x00; /* branch offset = 4 */
4464 *buffer_address++ = 0x04;
4465 *buffer_address++ = 0x60; /* put in bra pc+6 */
4466 *buffer_address++ = 0x06;
4467 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4468 *buffer_address++ = (char) 0xf9;
4469
4470 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4471 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4472 RELAX_RELOC_ABS32);
4473 fragP->fr_fix += 4;
4474 break;
4475 case TAB (PCREL1632, SHORT):
4476 fragP->fr_opcode[1] &= ~0x3F;
4477 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4478 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4479 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4480 fragP->fr_fix += 2;
4481 break;
4482 case TAB (PCREL1632, LONG):
4483 /* Already set to mode 7.3; this indicates: PC indirect with
4484 suppressed index, 32-bit displacement. */
4485 *buffer_address++ = 0x01;
4486 *buffer_address++ = 0x70;
4487 fragP->fr_fix += 2;
4488 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4489 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4490 fixP->fx_pcrel_adjust = 2;
4491 fragP->fr_fix += 4;
4492 break;
4493 case TAB (PCINDEX, BYTE):
4494 assert (fragP->fr_fix >= 2);
4495 buffer_address[-2] &= ~1;
4496 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4497 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4498 fixP->fx_pcrel_adjust = 1;
4499 break;
4500 case TAB (PCINDEX, SHORT):
4501 assert (fragP->fr_fix >= 2);
4502 buffer_address[-2] |= 0x1;
4503 buffer_address[-1] = 0x20;
4504 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4505 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4506 fixP->fx_pcrel_adjust = 2;
4507 fragP->fr_fix += 2;
4508 break;
4509 case TAB (PCINDEX, LONG):
4510 assert (fragP->fr_fix >= 2);
4511 buffer_address[-2] |= 0x1;
4512 buffer_address[-1] = 0x30;
4513 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4514 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4515 fixP->fx_pcrel_adjust = 2;
4516 fragP->fr_fix += 4;
4517 break;
4518 case TAB (ABSTOPCREL, SHORT):
4519 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4520 1, RELAX_RELOC_PC16);
4521 fragP->fr_fix += 2;
4522 break;
4523 case TAB (ABSTOPCREL, LONG):
4524 /* The thing to do here is force it to ABSOLUTE LONG, since
4525 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4526 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4527 abort ();
4528 fragP->fr_opcode[1] &= ~0x3F;
4529 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4530 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4531 0, RELAX_RELOC_ABS32);
4532 fragP->fr_fix += 4;
4533 break;
4534 }
4535 }
4536
4537 #ifndef BFD_ASSEMBLER
4538
4539 void
4540 md_convert_frag (headers, sec, fragP)
4541 object_headers *headers ATTRIBUTE_UNUSED;
4542 segT sec ATTRIBUTE_UNUSED;
4543 fragS *fragP;
4544 {
4545 md_convert_frag_1 (fragP);
4546 }
4547
4548 #else
4549
4550 void
4551 md_convert_frag (abfd, sec, fragP)
4552 bfd *abfd ATTRIBUTE_UNUSED;
4553 segT sec ATTRIBUTE_UNUSED;
4554 fragS *fragP;
4555 {
4556 md_convert_frag_1 (fragP);
4557 }
4558 #endif
4559
4560 /* Force truly undefined symbols to their maximum size, and generally set up
4561 the frag list to be relaxed
4562 */
4563 int
4564 md_estimate_size_before_relax (fragP, segment)
4565 register fragS *fragP;
4566 segT segment;
4567 {
4568 int old_fix;
4569
4570 old_fix = fragP->fr_fix;
4571
4572 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4573 switch (fragP->fr_subtype)
4574 {
4575 case TAB (BRANCHBWL, SZ_UNDEF):
4576 case TAB (BRABSJUNC, SZ_UNDEF):
4577 case TAB (BRABSJCOND, SZ_UNDEF):
4578 {
4579 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4580 && relaxable_symbol (fragP->fr_symbol))
4581 {
4582 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4583 }
4584 else if (flag_short_refs)
4585 {
4586 /* Symbol is undefined and we want short ref. */
4587 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4588 }
4589 else
4590 {
4591 /* Symbol is still undefined. Make it LONG. */
4592 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4593 }
4594 break;
4595 }
4596
4597 case TAB (BRANCHBW, SZ_UNDEF):
4598 {
4599 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4600 && relaxable_symbol (fragP->fr_symbol))
4601 {
4602 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4603 }
4604 else
4605 {
4606 /* Symbol is undefined and we don't have long branches. */
4607 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4608 }
4609 break;
4610 }
4611
4612 case TAB (FBRANCH, SZ_UNDEF):
4613 case TAB (DBCCLBR, SZ_UNDEF):
4614 case TAB (DBCCABSJ, SZ_UNDEF):
4615 case TAB (PCREL1632, SZ_UNDEF):
4616 {
4617 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4618 && relaxable_symbol (fragP->fr_symbol))
4619 || flag_short_refs)
4620 {
4621 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4622 }
4623 else
4624 {
4625 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4626 }
4627 break;
4628 }
4629
4630 case TAB (PCINDEX, SZ_UNDEF):
4631 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4632 && relaxable_symbol (fragP->fr_symbol)))
4633 {
4634 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4635 }
4636 else
4637 {
4638 fragP->fr_subtype = TAB (PCINDEX, LONG);
4639 }
4640 break;
4641
4642 case TAB (ABSTOPCREL, SZ_UNDEF):
4643 {
4644 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4645 && relaxable_symbol (fragP->fr_symbol)))
4646 {
4647 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4648 }
4649 else
4650 {
4651 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4652 }
4653 break;
4654 }
4655
4656 default:
4657 break;
4658 }
4659
4660 /* Now that SZ_UNDEF are taken care of, check others. */
4661 switch (fragP->fr_subtype)
4662 {
4663 case TAB (BRANCHBWL, BYTE):
4664 case TAB (BRABSJUNC, BYTE):
4665 case TAB (BRABSJCOND, BYTE):
4666 case TAB (BRANCHBW, BYTE):
4667 /* We can't do a short jump to the next instruction, so in that
4668 case we force word mode. At this point S_GET_VALUE should
4669 return the offset of the symbol within its frag. If the
4670 symbol is at the start of a frag, and it is the next frag
4671 with any data in it (usually this is just the next frag, but
4672 assembler listings may introduce empty frags), we must use
4673 word mode. */
4674 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4675 {
4676 fragS *stop;
4677 fragS *l;
4678
4679 stop = symbol_get_frag (fragP->fr_symbol);
4680 for (l = fragP->fr_next; l != stop; l = l->fr_next)
4681 if (l->fr_fix + l->fr_var != 0)
4682 break;
4683 if (l == stop)
4684 {
4685 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4686 }
4687 }
4688 break;
4689 default:
4690 break;
4691 }
4692 fragP->fr_var = md_relax_table[fragP->fr_subtype].rlx_length;
4693 return fragP->fr_var + fragP->fr_fix - old_fix;
4694 }
4695
4696 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4697 /* the bit-field entries in the relocation_info struct plays hell
4698 with the byte-order problems of cross-assembly. So as a hack,
4699 I added this mach. dependent ri twiddler. Ugly, but it gets
4700 you there. -KWK */
4701 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4702 are symbolnum, most sig. byte first. Last byte is broken up with
4703 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4704 nibble as nuthin. (on Sun 3 at least) */
4705 /* Translate the internal relocation information into target-specific
4706 format. */
4707 #ifdef comment
4708 void
4709 md_ri_to_chars (the_bytes, ri)
4710 char *the_bytes;
4711 struct reloc_info_generic *ri;
4712 {
4713 /* this is easy */
4714 md_number_to_chars (the_bytes, ri->r_address, 4);
4715 /* now the fun stuff */
4716 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4717 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4718 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4719 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4720 ((ri->r_extern << 4) & 0x10));
4721 }
4722
4723 #endif /* comment */
4724
4725 #ifndef BFD_ASSEMBLER
4726 void
4727 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4728 char *where;
4729 fixS *fixP;
4730 relax_addressT segment_address_in_file;
4731 {
4732 /*
4733 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4734 * Out: GNU LD relocation length code: 0, 1, or 2.
4735 */
4736
4737 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4738 long r_symbolnum;
4739
4740 know (fixP->fx_addsy != NULL);
4741
4742 md_number_to_chars (where,
4743 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4744 4);
4745
4746 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4747 ? S_GET_TYPE (fixP->fx_addsy)
4748 : fixP->fx_addsy->sy_number);
4749
4750 where[4] = (r_symbolnum >> 16) & 0x0ff;
4751 where[5] = (r_symbolnum >> 8) & 0x0ff;
4752 where[6] = r_symbolnum & 0x0ff;
4753 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4754 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4755 }
4756 #endif
4757
4758 #endif /* OBJ_AOUT or OBJ_BOUT */
4759
4760 #ifndef WORKING_DOT_WORD
4761 CONST int md_short_jump_size = 4;
4762 CONST int md_long_jump_size = 6;
4763
4764 void
4765 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4766 char *ptr;
4767 addressT from_addr, to_addr;
4768 fragS *frag ATTRIBUTE_UNUSED;
4769 symbolS *to_symbol ATTRIBUTE_UNUSED;
4770 {
4771 valueT offset;
4772
4773 offset = to_addr - (from_addr + 2);
4774
4775 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4776 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4777 }
4778
4779 void
4780 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4781 char *ptr;
4782 addressT from_addr, to_addr;
4783 fragS *frag;
4784 symbolS *to_symbol;
4785 {
4786 valueT offset;
4787
4788 if (!HAVE_LONG_BRANCH(current_architecture))
4789 {
4790 offset = to_addr - S_GET_VALUE (to_symbol);
4791 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4792 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4793 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4794 0, NO_RELOC);
4795 }
4796 else
4797 {
4798 offset = to_addr - (from_addr + 2);
4799 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4800 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4801 }
4802 }
4803
4804 #endif
4805
4806 /* Different values of OK tell what its OK to return. Things that
4807 aren't OK are an error (what a shock, no?)
4808
4809 0: Everything is OK
4810 10: Absolute 1:8 only
4811 20: Absolute 0:7 only
4812 30: absolute 0:15 only
4813 40: Absolute 0:31 only
4814 50: absolute 0:127 only
4815 55: absolute -64:63 only
4816 60: absolute -128:127 only
4817 70: absolute 0:4095 only
4818 80: No bignums
4819
4820 */
4821
4822 static int
4823 get_num (exp, ok)
4824 struct m68k_exp *exp;
4825 int ok;
4826 {
4827 if (exp->exp.X_op == O_absent)
4828 {
4829 /* Do the same thing the VAX asm does */
4830 op (exp) = O_constant;
4831 adds (exp) = 0;
4832 subs (exp) = 0;
4833 offs (exp) = 0;
4834 if (ok == 10)
4835 {
4836 as_warn (_("expression out of range: defaulting to 1"));
4837 offs (exp) = 1;
4838 }
4839 }
4840 else if (exp->exp.X_op == O_constant)
4841 {
4842 switch (ok)
4843 {
4844 case 10:
4845 if (offs (exp) < 1 || offs (exp) > 8)
4846 {
4847 as_warn (_("expression out of range: defaulting to 1"));
4848 offs (exp) = 1;
4849 }
4850 break;
4851 case 20:
4852 if (offs (exp) < 0 || offs (exp) > 7)
4853 goto outrange;
4854 break;
4855 case 30:
4856 if (offs (exp) < 0 || offs (exp) > 15)
4857 goto outrange;
4858 break;
4859 case 40:
4860 if (offs (exp) < 0 || offs (exp) > 32)
4861 goto outrange;
4862 break;
4863 case 50:
4864 if (offs (exp) < 0 || offs (exp) > 127)
4865 goto outrange;
4866 break;
4867 case 55:
4868 if (offs (exp) < -64 || offs (exp) > 63)
4869 goto outrange;
4870 break;
4871 case 60:
4872 if (offs (exp) < -128 || offs (exp) > 127)
4873 goto outrange;
4874 break;
4875 case 70:
4876 if (offs (exp) < 0 || offs (exp) > 4095)
4877 {
4878 outrange:
4879 as_warn (_("expression out of range: defaulting to 0"));
4880 offs (exp) = 0;
4881 }
4882 break;
4883 default:
4884 break;
4885 }
4886 }
4887 else if (exp->exp.X_op == O_big)
4888 {
4889 if (offs (exp) <= 0 /* flonum */
4890 && (ok == 80 /* no bignums */
4891 || (ok > 10 /* small-int ranges including 0 ok */
4892 /* If we have a flonum zero, a zero integer should
4893 do as well (e.g., in moveq). */
4894 && generic_floating_point_number.exponent == 0
4895 && generic_floating_point_number.low[0] == 0)))
4896 {
4897 /* HACK! Turn it into a long */
4898 LITTLENUM_TYPE words[6];
4899
4900 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4901 op (exp) = O_constant;
4902 adds (exp) = 0;
4903 subs (exp) = 0;
4904 offs (exp) = words[1] | (words[0] << 16);
4905 }
4906 else if (ok != 0)
4907 {
4908 op (exp) = O_constant;
4909 adds (exp) = 0;
4910 subs (exp) = 0;
4911 offs (exp) = (ok == 10) ? 1 : 0;
4912 as_warn (_("Can't deal with expression; defaulting to %ld"),
4913 offs (exp));
4914 }
4915 }
4916 else
4917 {
4918 if (ok >= 10 && ok <= 70)
4919 {
4920 op (exp) = O_constant;
4921 adds (exp) = 0;
4922 subs (exp) = 0;
4923 offs (exp) = (ok == 10) ? 1 : 0;
4924 as_warn (_("Can't deal with expression; defaulting to %ld"),
4925 offs (exp));
4926 }
4927 }
4928
4929 if (exp->size != SIZE_UNSPEC)
4930 {
4931 switch (exp->size)
4932 {
4933 case SIZE_UNSPEC:
4934 case SIZE_LONG:
4935 break;
4936 case SIZE_BYTE:
4937 if (!isbyte (offs (exp)))
4938 as_warn (_("expression doesn't fit in BYTE"));
4939 break;
4940 case SIZE_WORD:
4941 if (!isword (offs (exp)))
4942 as_warn (_("expression doesn't fit in WORD"));
4943 break;
4944 }
4945 }
4946
4947 return offs (exp);
4948 }
4949
4950 /* These are the back-ends for the various machine dependent pseudo-ops. */
4951
4952 static void
4953 s_data1 (ignore)
4954 int ignore ATTRIBUTE_UNUSED;
4955 {
4956 subseg_set (data_section, 1);
4957 demand_empty_rest_of_line ();
4958 }
4959
4960 static void
4961 s_data2 (ignore)
4962 int ignore ATTRIBUTE_UNUSED;
4963 {
4964 subseg_set (data_section, 2);
4965 demand_empty_rest_of_line ();
4966 }
4967
4968 static void
4969 s_bss (ignore)
4970 int ignore ATTRIBUTE_UNUSED;
4971 {
4972 /* We don't support putting frags in the BSS segment, we fake it
4973 by marking in_bss, then looking at s_skip for clues. */
4974
4975 subseg_set (bss_section, 0);
4976 demand_empty_rest_of_line ();
4977 }
4978
4979 static void
4980 s_even (ignore)
4981 int ignore ATTRIBUTE_UNUSED;
4982 {
4983 register int temp;
4984 register long temp_fill;
4985
4986 temp = 1; /* JF should be 2? */
4987 temp_fill = get_absolute_expression ();
4988 if (!need_pass_2) /* Never make frag if expect extra pass. */
4989 frag_align (temp, (int) temp_fill, 0);
4990 demand_empty_rest_of_line ();
4991 record_alignment (now_seg, temp);
4992 }
4993
4994 static void
4995 s_proc (ignore)
4996 int ignore ATTRIBUTE_UNUSED;
4997 {
4998 demand_empty_rest_of_line ();
4999 }
5000 \f
5001 /* Pseudo-ops handled for MRI compatibility. */
5002
5003 /* This function returns non-zero if the argument is a conditional
5004 pseudo-op. This is called when checking whether a pending
5005 alignment is needed. */
5006
5007 int
5008 m68k_conditional_pseudoop (pop)
5009 pseudo_typeS *pop;
5010 {
5011 return (pop->poc_handler == s_mri_if
5012 || pop->poc_handler == s_mri_else);
5013 }
5014
5015 /* Handle an MRI style chip specification. */
5016
5017 static void
5018 mri_chip ()
5019 {
5020 char *s;
5021 char c;
5022 int i;
5023
5024 s = input_line_pointer;
5025 /* We can't use get_symbol_end since the processor names are not proper
5026 symbols. */
5027 while (is_part_of_name (c = *input_line_pointer++))
5028 ;
5029 *--input_line_pointer = 0;
5030 for (i = 0; i < n_archs; i++)
5031 if (strcasecmp (s, archs[i].name) == 0)
5032 break;
5033 if (i >= n_archs)
5034 {
5035 as_bad (_("%s: unrecognized processor name"), s);
5036 *input_line_pointer = c;
5037 ignore_rest_of_line ();
5038 return;
5039 }
5040 *input_line_pointer = c;
5041
5042 if (*input_line_pointer == '/')
5043 current_architecture = 0;
5044 else
5045 current_architecture &= m68881 | m68851;
5046 current_architecture |= archs[i].arch;
5047
5048 while (*input_line_pointer == '/')
5049 {
5050 ++input_line_pointer;
5051 s = input_line_pointer;
5052 /* We can't use get_symbol_end since the processor names are not
5053 proper symbols. */
5054 while (is_part_of_name (c = *input_line_pointer++))
5055 ;
5056 *--input_line_pointer = 0;
5057 if (strcmp (s, "68881") == 0)
5058 current_architecture |= m68881;
5059 else if (strcmp (s, "68851") == 0)
5060 current_architecture |= m68851;
5061 *input_line_pointer = c;
5062 }
5063
5064 /* Update info about available control registers. */
5065 select_control_regs ();
5066 }
5067
5068 /* The MRI CHIP pseudo-op. */
5069
5070 static void
5071 s_chip (ignore)
5072 int ignore ATTRIBUTE_UNUSED;
5073 {
5074 char *stop = NULL;
5075 char stopc;
5076
5077 if (flag_mri)
5078 stop = mri_comment_field (&stopc);
5079 mri_chip ();
5080 if (flag_mri)
5081 mri_comment_end (stop, stopc);
5082 demand_empty_rest_of_line ();
5083 }
5084
5085 /* The MRI FOPT pseudo-op. */
5086
5087 static void
5088 s_fopt (ignore)
5089 int ignore ATTRIBUTE_UNUSED;
5090 {
5091 SKIP_WHITESPACE ();
5092
5093 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5094 {
5095 int temp;
5096
5097 input_line_pointer += 3;
5098 temp = get_absolute_expression ();
5099 if (temp < 0 || temp > 7)
5100 as_bad (_("bad coprocessor id"));
5101 else
5102 m68k_float_copnum = COP0 + temp;
5103 }
5104 else
5105 {
5106 as_bad (_("unrecognized fopt option"));
5107 ignore_rest_of_line ();
5108 return;
5109 }
5110
5111 demand_empty_rest_of_line ();
5112 }
5113
5114 /* The structure used to handle the MRI OPT pseudo-op. */
5115
5116 struct opt_action
5117 {
5118 /* The name of the option. */
5119 const char *name;
5120
5121 /* If this is not NULL, just call this function. The first argument
5122 is the ARG field of this structure, the second argument is
5123 whether the option was negated. */
5124 void (*pfn) PARAMS ((int arg, int on));
5125
5126 /* If this is not NULL, and the PFN field is NULL, set the variable
5127 this points to. Set it to the ARG field if the option was not
5128 negated, and the NOTARG field otherwise. */
5129 int *pvar;
5130
5131 /* The value to pass to PFN or to assign to *PVAR. */
5132 int arg;
5133
5134 /* The value to assign to *PVAR if the option is negated. If PFN is
5135 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5136 the option may not be negated. */
5137 int notarg;
5138 };
5139
5140 /* The table used to handle the MRI OPT pseudo-op. */
5141
5142 static void skip_to_comma PARAMS ((int, int));
5143 static void opt_nest PARAMS ((int, int));
5144 static void opt_chip PARAMS ((int, int));
5145 static void opt_list PARAMS ((int, int));
5146 static void opt_list_symbols PARAMS ((int, int));
5147
5148 static const struct opt_action opt_table[] =
5149 {
5150 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5151
5152 /* We do relaxing, so there is little use for these options. */
5153 { "b", 0, 0, 0, 0 },
5154 { "brs", 0, 0, 0, 0 },
5155 { "brb", 0, 0, 0, 0 },
5156 { "brl", 0, 0, 0, 0 },
5157 { "brw", 0, 0, 0, 0 },
5158
5159 { "c", 0, 0, 0, 0 },
5160 { "cex", 0, 0, 0, 0 },
5161 { "case", 0, &symbols_case_sensitive, 1, 0 },
5162 { "cl", 0, 0, 0, 0 },
5163 { "cre", 0, 0, 0, 0 },
5164 { "d", 0, &flag_keep_locals, 1, 0 },
5165 { "e", 0, 0, 0, 0 },
5166 { "f", 0, &flag_short_refs, 1, 0 },
5167 { "frs", 0, &flag_short_refs, 1, 0 },
5168 { "frl", 0, &flag_short_refs, 0, 1 },
5169 { "g", 0, 0, 0, 0 },
5170 { "i", 0, 0, 0, 0 },
5171 { "m", 0, 0, 0, 0 },
5172 { "mex", 0, 0, 0, 0 },
5173 { "mc", 0, 0, 0, 0 },
5174 { "md", 0, 0, 0, 0 },
5175 { "nest", opt_nest, 0, 0, 0 },
5176 { "next", skip_to_comma, 0, 0, 0 },
5177 { "o", 0, 0, 0, 0 },
5178 { "old", 0, 0, 0, 0 },
5179 { "op", skip_to_comma, 0, 0, 0 },
5180 { "pco", 0, 0, 0, 0 },
5181 { "p", opt_chip, 0, 0, 0 },
5182 { "pcr", 0, 0, 0, 0 },
5183 { "pcs", 0, 0, 0, 0 },
5184 { "r", 0, 0, 0, 0 },
5185 { "quick", 0, &m68k_quick, 1, 0 },
5186 { "rel32", 0, &m68k_rel32, 1, 0 },
5187 { "s", opt_list, 0, 0, 0 },
5188 { "t", opt_list_symbols, 0, 0, 0 },
5189 { "w", 0, &flag_no_warnings, 0, 1 },
5190 { "x", 0, 0, 0, 0 }
5191 };
5192
5193 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5194
5195 /* The MRI OPT pseudo-op. */
5196
5197 static void
5198 s_opt (ignore)
5199 int ignore ATTRIBUTE_UNUSED;
5200 {
5201 do
5202 {
5203 int t;
5204 char *s;
5205 char c;
5206 int i;
5207 const struct opt_action *o;
5208
5209 SKIP_WHITESPACE ();
5210
5211 t = 1;
5212 if (*input_line_pointer == '-')
5213 {
5214 ++input_line_pointer;
5215 t = 0;
5216 }
5217 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5218 {
5219 input_line_pointer += 2;
5220 t = 0;
5221 }
5222
5223 s = input_line_pointer;
5224 c = get_symbol_end ();
5225
5226 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5227 {
5228 if (strcasecmp (s, o->name) == 0)
5229 {
5230 if (o->pfn)
5231 {
5232 /* Restore input_line_pointer now in case the option
5233 takes arguments. */
5234 *input_line_pointer = c;
5235 (*o->pfn) (o->arg, t);
5236 }
5237 else if (o->pvar != NULL)
5238 {
5239 if (! t && o->arg == o->notarg)
5240 as_bad (_("option `%s' may not be negated"), s);
5241 *input_line_pointer = c;
5242 *o->pvar = t ? o->arg : o->notarg;
5243 }
5244 else
5245 *input_line_pointer = c;
5246 break;
5247 }
5248 }
5249 if (i >= OPTCOUNT)
5250 {
5251 as_bad (_("option `%s' not recognized"), s);
5252 *input_line_pointer = c;
5253 }
5254 }
5255 while (*input_line_pointer++ == ',');
5256
5257 /* Move back to terminating character. */
5258 --input_line_pointer;
5259 demand_empty_rest_of_line ();
5260 }
5261
5262 /* Skip ahead to a comma. This is used for OPT options which we do
5263 not suppor tand which take arguments. */
5264
5265 static void
5266 skip_to_comma (arg, on)
5267 int arg ATTRIBUTE_UNUSED;
5268 int on ATTRIBUTE_UNUSED;
5269 {
5270 while (*input_line_pointer != ','
5271 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5272 ++input_line_pointer;
5273 }
5274
5275 /* Handle the OPT NEST=depth option. */
5276
5277 static void
5278 opt_nest (arg, on)
5279 int arg ATTRIBUTE_UNUSED;
5280 int on ATTRIBUTE_UNUSED;
5281 {
5282 if (*input_line_pointer != '=')
5283 {
5284 as_bad (_("bad format of OPT NEST=depth"));
5285 return;
5286 }
5287
5288 ++input_line_pointer;
5289 max_macro_nest = get_absolute_expression ();
5290 }
5291
5292 /* Handle the OPT P=chip option. */
5293
5294 static void
5295 opt_chip (arg, on)
5296 int arg ATTRIBUTE_UNUSED;
5297 int on ATTRIBUTE_UNUSED;
5298 {
5299 if (*input_line_pointer != '=')
5300 {
5301 /* This is just OPT P, which we do not support. */
5302 return;
5303 }
5304
5305 ++input_line_pointer;
5306 mri_chip ();
5307 }
5308
5309 /* Handle the OPT S option. */
5310
5311 static void
5312 opt_list (arg, on)
5313 int arg ATTRIBUTE_UNUSED;
5314 int on;
5315 {
5316 listing_list (on);
5317 }
5318
5319 /* Handle the OPT T option. */
5320
5321 static void
5322 opt_list_symbols (arg, on)
5323 int arg ATTRIBUTE_UNUSED;
5324 int on;
5325 {
5326 if (on)
5327 listing |= LISTING_SYMBOLS;
5328 else
5329 listing &=~ LISTING_SYMBOLS;
5330 }
5331
5332 /* Handle the MRI REG pseudo-op. */
5333
5334 static void
5335 s_reg (ignore)
5336 int ignore ATTRIBUTE_UNUSED;
5337 {
5338 char *s;
5339 int c;
5340 struct m68k_op rop;
5341 int mask;
5342 char *stop = NULL;
5343 char stopc;
5344
5345 if (line_label == NULL)
5346 {
5347 as_bad (_("missing label"));
5348 ignore_rest_of_line ();
5349 return;
5350 }
5351
5352 if (flag_mri)
5353 stop = mri_comment_field (&stopc);
5354
5355 SKIP_WHITESPACE ();
5356
5357 s = input_line_pointer;
5358 while (isalnum ((unsigned char) *input_line_pointer)
5359 #ifdef REGISTER_PREFIX
5360 || *input_line_pointer == REGISTER_PREFIX
5361 #endif
5362 || *input_line_pointer == '/'
5363 || *input_line_pointer == '-')
5364 ++input_line_pointer;
5365 c = *input_line_pointer;
5366 *input_line_pointer = '\0';
5367
5368 if (m68k_ip_op (s, &rop) != 0)
5369 {
5370 if (rop.error == NULL)
5371 as_bad (_("bad register list"));
5372 else
5373 as_bad (_("bad register list: %s"), rop.error);
5374 *input_line_pointer = c;
5375 ignore_rest_of_line ();
5376 return;
5377 }
5378
5379 *input_line_pointer = c;
5380
5381 if (rop.mode == REGLST)
5382 mask = rop.mask;
5383 else if (rop.mode == DREG)
5384 mask = 1 << (rop.reg - DATA0);
5385 else if (rop.mode == AREG)
5386 mask = 1 << (rop.reg - ADDR0 + 8);
5387 else if (rop.mode == FPREG)
5388 mask = 1 << (rop.reg - FP0 + 16);
5389 else if (rop.mode == CONTROL
5390 && rop.reg == FPI)
5391 mask = 1 << 24;
5392 else if (rop.mode == CONTROL
5393 && rop.reg == FPS)
5394 mask = 1 << 25;
5395 else if (rop.mode == CONTROL
5396 && rop.reg == FPC)
5397 mask = 1 << 26;
5398 else
5399 {
5400 as_bad (_("bad register list"));
5401 ignore_rest_of_line ();
5402 return;
5403 }
5404
5405 S_SET_SEGMENT (line_label, reg_section);
5406 S_SET_VALUE (line_label, ~mask);
5407 symbol_set_frag (line_label, &zero_address_frag);
5408
5409 if (flag_mri)
5410 mri_comment_end (stop, stopc);
5411
5412 demand_empty_rest_of_line ();
5413 }
5414
5415 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5416
5417 struct save_opts
5418 {
5419 struct save_opts *next;
5420 int abspcadd;
5421 int symbols_case_sensitive;
5422 int keep_locals;
5423 int short_refs;
5424 int architecture;
5425 int quick;
5426 int rel32;
5427 int listing;
5428 int no_warnings;
5429 /* FIXME: We don't save OPT S. */
5430 };
5431
5432 /* This variable holds the stack of saved options. */
5433
5434 static struct save_opts *save_stack;
5435
5436 /* The MRI SAVE pseudo-op. */
5437
5438 static void
5439 s_save (ignore)
5440 int ignore ATTRIBUTE_UNUSED;
5441 {
5442 struct save_opts *s;
5443
5444 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5445 s->abspcadd = m68k_abspcadd;
5446 s->symbols_case_sensitive = symbols_case_sensitive;
5447 s->keep_locals = flag_keep_locals;
5448 s->short_refs = flag_short_refs;
5449 s->architecture = current_architecture;
5450 s->quick = m68k_quick;
5451 s->rel32 = m68k_rel32;
5452 s->listing = listing;
5453 s->no_warnings = flag_no_warnings;
5454
5455 s->next = save_stack;
5456 save_stack = s;
5457
5458 demand_empty_rest_of_line ();
5459 }
5460
5461 /* The MRI RESTORE pseudo-op. */
5462
5463 static void
5464 s_restore (ignore)
5465 int ignore ATTRIBUTE_UNUSED;
5466 {
5467 struct save_opts *s;
5468
5469 if (save_stack == NULL)
5470 {
5471 as_bad (_("restore without save"));
5472 ignore_rest_of_line ();
5473 return;
5474 }
5475
5476 s = save_stack;
5477 save_stack = s->next;
5478
5479 m68k_abspcadd = s->abspcadd;
5480 symbols_case_sensitive = s->symbols_case_sensitive;
5481 flag_keep_locals = s->keep_locals;
5482 flag_short_refs = s->short_refs;
5483 current_architecture = s->architecture;
5484 m68k_quick = s->quick;
5485 m68k_rel32 = s->rel32;
5486 listing = s->listing;
5487 flag_no_warnings = s->no_warnings;
5488
5489 free (s);
5490
5491 demand_empty_rest_of_line ();
5492 }
5493
5494 /* Types of MRI structured control directives. */
5495
5496 enum mri_control_type
5497 {
5498 mri_for,
5499 mri_if,
5500 mri_repeat,
5501 mri_while
5502 };
5503
5504 /* This structure is used to stack the MRI structured control
5505 directives. */
5506
5507 struct mri_control_info
5508 {
5509 /* The directive within which this one is enclosed. */
5510 struct mri_control_info *outer;
5511
5512 /* The type of directive. */
5513 enum mri_control_type type;
5514
5515 /* Whether an ELSE has been in an IF. */
5516 int else_seen;
5517
5518 /* The add or sub statement at the end of a FOR. */
5519 char *incr;
5520
5521 /* The label of the top of a FOR or REPEAT loop. */
5522 char *top;
5523
5524 /* The label to jump to for the next iteration, or the else
5525 expression of a conditional. */
5526 char *next;
5527
5528 /* The label to jump to to break out of the loop, or the label past
5529 the end of a conditional. */
5530 char *bottom;
5531 };
5532
5533 /* The stack of MRI structured control directives. */
5534
5535 static struct mri_control_info *mri_control_stack;
5536
5537 /* The current MRI structured control directive index number, used to
5538 generate label names. */
5539
5540 static int mri_control_index;
5541
5542 /* Some function prototypes. */
5543
5544 static void mri_assemble PARAMS ((char *));
5545 static char *mri_control_label PARAMS ((void));
5546 static struct mri_control_info *push_mri_control
5547 PARAMS ((enum mri_control_type));
5548 static void pop_mri_control PARAMS ((void));
5549 static int parse_mri_condition PARAMS ((int *));
5550 static int parse_mri_control_operand
5551 PARAMS ((int *, char **, char **, char **, char **));
5552 static int swap_mri_condition PARAMS ((int));
5553 static int reverse_mri_condition PARAMS ((int));
5554 static void build_mri_control_operand
5555 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5556 const char *, int));
5557 static void parse_mri_control_expression
5558 PARAMS ((char *, int, const char *, const char *, int));
5559
5560 /* Assemble an instruction for an MRI structured control directive. */
5561
5562 static void
5563 mri_assemble (str)
5564 char *str;
5565 {
5566 char *s;
5567
5568 /* md_assemble expects the opcode to be in lower case. */
5569 for (s = str; *s != ' ' && *s != '\0'; s++)
5570 {
5571 if (isupper ((unsigned char) *s))
5572 *s = tolower ((unsigned char) *s);
5573 }
5574
5575 md_assemble (str);
5576 }
5577
5578 /* Generate a new MRI label structured control directive label name. */
5579
5580 static char *
5581 mri_control_label ()
5582 {
5583 char *n;
5584
5585 n = (char *) xmalloc (20);
5586 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5587 ++mri_control_index;
5588 return n;
5589 }
5590
5591 /* Create a new MRI structured control directive. */
5592
5593 static struct mri_control_info *
5594 push_mri_control (type)
5595 enum mri_control_type type;
5596 {
5597 struct mri_control_info *n;
5598
5599 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5600
5601 n->type = type;
5602 n->else_seen = 0;
5603 if (type == mri_if || type == mri_while)
5604 n->top = NULL;
5605 else
5606 n->top = mri_control_label ();
5607 n->next = mri_control_label ();
5608 n->bottom = mri_control_label ();
5609
5610 n->outer = mri_control_stack;
5611 mri_control_stack = n;
5612
5613 return n;
5614 }
5615
5616 /* Pop off the stack of MRI structured control directives. */
5617
5618 static void
5619 pop_mri_control ()
5620 {
5621 struct mri_control_info *n;
5622
5623 n = mri_control_stack;
5624 mri_control_stack = n->outer;
5625 if (n->top != NULL)
5626 free (n->top);
5627 free (n->next);
5628 free (n->bottom);
5629 free (n);
5630 }
5631
5632 /* Recognize a condition code in an MRI structured control expression. */
5633
5634 static int
5635 parse_mri_condition (pcc)
5636 int *pcc;
5637 {
5638 char c1, c2;
5639
5640 know (*input_line_pointer == '<');
5641
5642 ++input_line_pointer;
5643 c1 = *input_line_pointer++;
5644 c2 = *input_line_pointer++;
5645
5646 if (*input_line_pointer != '>')
5647 {
5648 as_bad (_("syntax error in structured control directive"));
5649 return 0;
5650 }
5651
5652 ++input_line_pointer;
5653 SKIP_WHITESPACE ();
5654
5655 if (isupper (c1))
5656 c1 = tolower (c1);
5657 if (isupper (c2))
5658 c2 = tolower (c2);
5659
5660 *pcc = (c1 << 8) | c2;
5661
5662 return 1;
5663 }
5664
5665 /* Parse a single operand in an MRI structured control expression. */
5666
5667 static int
5668 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5669 int *pcc;
5670 char **leftstart;
5671 char **leftstop;
5672 char **rightstart;
5673 char **rightstop;
5674 {
5675 char *s;
5676
5677 SKIP_WHITESPACE ();
5678
5679 *pcc = -1;
5680 *leftstart = NULL;
5681 *leftstop = NULL;
5682 *rightstart = NULL;
5683 *rightstop = NULL;
5684
5685 if (*input_line_pointer == '<')
5686 {
5687 /* It's just a condition code. */
5688 return parse_mri_condition (pcc);
5689 }
5690
5691 /* Look ahead for the condition code. */
5692 for (s = input_line_pointer; *s != '\0'; ++s)
5693 {
5694 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5695 break;
5696 }
5697 if (*s == '\0')
5698 {
5699 as_bad (_("missing condition code in structured control directive"));
5700 return 0;
5701 }
5702
5703 *leftstart = input_line_pointer;
5704 *leftstop = s;
5705 if (*leftstop > *leftstart
5706 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5707 --*leftstop;
5708
5709 input_line_pointer = s;
5710 if (! parse_mri_condition (pcc))
5711 return 0;
5712
5713 /* Look ahead for AND or OR or end of line. */
5714 for (s = input_line_pointer; *s != '\0'; ++s)
5715 {
5716 if ((strncasecmp (s, "AND", 3) == 0
5717 && (s[3] == '.' || ! is_part_of_name (s[3])))
5718 || (strncasecmp (s, "OR", 2) == 0
5719 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5720 break;
5721 }
5722
5723 *rightstart = input_line_pointer;
5724 *rightstop = s;
5725 if (*rightstop > *rightstart
5726 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5727 --*rightstop;
5728
5729 input_line_pointer = s;
5730
5731 return 1;
5732 }
5733
5734 #define MCC(b1, b2) (((b1) << 8) | (b2))
5735
5736 /* Swap the sense of a condition. This changes the condition so that
5737 it generates the same result when the operands are swapped. */
5738
5739 static int
5740 swap_mri_condition (cc)
5741 int cc;
5742 {
5743 switch (cc)
5744 {
5745 case MCC ('h', 'i'): return MCC ('c', 's');
5746 case MCC ('l', 's'): return MCC ('c', 'c');
5747 case MCC ('c', 'c'): return MCC ('l', 's');
5748 case MCC ('c', 's'): return MCC ('h', 'i');
5749 case MCC ('p', 'l'): return MCC ('m', 'i');
5750 case MCC ('m', 'i'): return MCC ('p', 'l');
5751 case MCC ('g', 'e'): return MCC ('l', 'e');
5752 case MCC ('l', 't'): return MCC ('g', 't');
5753 case MCC ('g', 't'): return MCC ('l', 't');
5754 case MCC ('l', 'e'): return MCC ('g', 'e');
5755 }
5756 return cc;
5757 }
5758
5759 /* Reverse the sense of a condition. */
5760
5761 static int
5762 reverse_mri_condition (cc)
5763 int cc;
5764 {
5765 switch (cc)
5766 {
5767 case MCC ('h', 'i'): return MCC ('l', 's');
5768 case MCC ('l', 's'): return MCC ('h', 'i');
5769 case MCC ('c', 'c'): return MCC ('c', 's');
5770 case MCC ('c', 's'): return MCC ('c', 'c');
5771 case MCC ('n', 'e'): return MCC ('e', 'q');
5772 case MCC ('e', 'q'): return MCC ('n', 'e');
5773 case MCC ('v', 'c'): return MCC ('v', 's');
5774 case MCC ('v', 's'): return MCC ('v', 'c');
5775 case MCC ('p', 'l'): return MCC ('m', 'i');
5776 case MCC ('m', 'i'): return MCC ('p', 'l');
5777 case MCC ('g', 'e'): return MCC ('l', 't');
5778 case MCC ('l', 't'): return MCC ('g', 'e');
5779 case MCC ('g', 't'): return MCC ('l', 'e');
5780 case MCC ('l', 'e'): return MCC ('g', 't');
5781 }
5782 return cc;
5783 }
5784
5785 /* Build an MRI structured control expression. This generates test
5786 and branch instructions. It goes to TRUELAB if the condition is
5787 true, and to FALSELAB if the condition is false. Exactly one of
5788 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5789 is the size qualifier for the expression. EXTENT is the size to
5790 use for the branch. */
5791
5792 static void
5793 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5794 rightstop, truelab, falselab, extent)
5795 int qual;
5796 int cc;
5797 char *leftstart;
5798 char *leftstop;
5799 char *rightstart;
5800 char *rightstop;
5801 const char *truelab;
5802 const char *falselab;
5803 int extent;
5804 {
5805 char *buf;
5806 char *s;
5807
5808 if (leftstart != NULL)
5809 {
5810 struct m68k_op leftop, rightop;
5811 char c;
5812
5813 /* Swap the compare operands, if necessary, to produce a legal
5814 m68k compare instruction. Comparing a register operand with
5815 a non-register operand requires the register to be on the
5816 right (cmp, cmpa). Comparing an immediate value with
5817 anything requires the immediate value to be on the left
5818 (cmpi). */
5819
5820 c = *leftstop;
5821 *leftstop = '\0';
5822 (void) m68k_ip_op (leftstart, &leftop);
5823 *leftstop = c;
5824
5825 c = *rightstop;
5826 *rightstop = '\0';
5827 (void) m68k_ip_op (rightstart, &rightop);
5828 *rightstop = c;
5829
5830 if (rightop.mode == IMMED
5831 || ((leftop.mode == DREG || leftop.mode == AREG)
5832 && (rightop.mode != DREG && rightop.mode != AREG)))
5833 {
5834 char *temp;
5835
5836 cc = swap_mri_condition (cc);
5837 temp = leftstart;
5838 leftstart = rightstart;
5839 rightstart = temp;
5840 temp = leftstop;
5841 leftstop = rightstop;
5842 rightstop = temp;
5843 }
5844 }
5845
5846 if (truelab == NULL)
5847 {
5848 cc = reverse_mri_condition (cc);
5849 truelab = falselab;
5850 }
5851
5852 if (leftstart != NULL)
5853 {
5854 buf = (char *) xmalloc (20
5855 + (leftstop - leftstart)
5856 + (rightstop - rightstart));
5857 s = buf;
5858 *s++ = 'c';
5859 *s++ = 'm';
5860 *s++ = 'p';
5861 if (qual != '\0')
5862 *s++ = qual;
5863 *s++ = ' ';
5864 memcpy (s, leftstart, leftstop - leftstart);
5865 s += leftstop - leftstart;
5866 *s++ = ',';
5867 memcpy (s, rightstart, rightstop - rightstart);
5868 s += rightstop - rightstart;
5869 *s = '\0';
5870 mri_assemble (buf);
5871 free (buf);
5872 }
5873
5874 buf = (char *) xmalloc (20 + strlen (truelab));
5875 s = buf;
5876 *s++ = 'b';
5877 *s++ = cc >> 8;
5878 *s++ = cc & 0xff;
5879 if (extent != '\0')
5880 *s++ = extent;
5881 *s++ = ' ';
5882 strcpy (s, truelab);
5883 mri_assemble (buf);
5884 free (buf);
5885 }
5886
5887 /* Parse an MRI structured control expression. This generates test
5888 and branch instructions. STOP is where the expression ends. It
5889 goes to TRUELAB if the condition is true, and to FALSELAB if the
5890 condition is false. Exactly one of TRUELAB and FALSELAB will be
5891 NULL, meaning to fall through. QUAL is the size qualifier for the
5892 expression. EXTENT is the size to use for the branch. */
5893
5894 static void
5895 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5896 char *stop;
5897 int qual;
5898 const char *truelab;
5899 const char *falselab;
5900 int extent;
5901 {
5902 int c;
5903 int cc;
5904 char *leftstart;
5905 char *leftstop;
5906 char *rightstart;
5907 char *rightstop;
5908
5909 c = *stop;
5910 *stop = '\0';
5911
5912 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5913 &rightstart, &rightstop))
5914 {
5915 *stop = c;
5916 return;
5917 }
5918
5919 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5920 {
5921 const char *flab;
5922
5923 if (falselab != NULL)
5924 flab = falselab;
5925 else
5926 flab = mri_control_label ();
5927
5928 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5929 rightstop, (const char *) NULL, flab, extent);
5930
5931 input_line_pointer += 3;
5932 if (*input_line_pointer != '.'
5933 || input_line_pointer[1] == '\0')
5934 qual = '\0';
5935 else
5936 {
5937 qual = input_line_pointer[1];
5938 input_line_pointer += 2;
5939 }
5940
5941 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5942 &rightstart, &rightstop))
5943 {
5944 *stop = c;
5945 return;
5946 }
5947
5948 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5949 rightstop, truelab, falselab, extent);
5950
5951 if (falselab == NULL)
5952 colon (flab);
5953 }
5954 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5955 {
5956 const char *tlab;
5957
5958 if (truelab != NULL)
5959 tlab = truelab;
5960 else
5961 tlab = mri_control_label ();
5962
5963 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5964 rightstop, tlab, (const char *) NULL, extent);
5965
5966 input_line_pointer += 2;
5967 if (*input_line_pointer != '.'
5968 || input_line_pointer[1] == '\0')
5969 qual = '\0';
5970 else
5971 {
5972 qual = input_line_pointer[1];
5973 input_line_pointer += 2;
5974 }
5975
5976 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5977 &rightstart, &rightstop))
5978 {
5979 *stop = c;
5980 return;
5981 }
5982
5983 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5984 rightstop, truelab, falselab, extent);
5985
5986 if (truelab == NULL)
5987 colon (tlab);
5988 }
5989 else
5990 {
5991 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5992 rightstop, truelab, falselab, extent);
5993 }
5994
5995 *stop = c;
5996 if (input_line_pointer != stop)
5997 as_bad (_("syntax error in structured control directive"));
5998 }
5999
6000 /* Handle the MRI IF pseudo-op. This may be a structured control
6001 directive, or it may be a regular assembler conditional, depending
6002 on its operands. */
6003
6004 static void
6005 s_mri_if (qual)
6006 int qual;
6007 {
6008 char *s;
6009 int c;
6010 struct mri_control_info *n;
6011
6012 /* A structured control directive must end with THEN with an
6013 optional qualifier. */
6014 s = input_line_pointer;
6015 while (! is_end_of_line[(unsigned char) *s]
6016 && (! flag_mri || *s != '*'))
6017 ++s;
6018 --s;
6019 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6020 --s;
6021
6022 if (s - input_line_pointer > 1
6023 && s[-1] == '.')
6024 s -= 2;
6025
6026 if (s - input_line_pointer < 3
6027 || strncasecmp (s - 3, "THEN", 4) != 0)
6028 {
6029 if (qual != '\0')
6030 {
6031 as_bad (_("missing then"));
6032 ignore_rest_of_line ();
6033 return;
6034 }
6035
6036 /* It's a conditional. */
6037 s_if (O_ne);
6038 return;
6039 }
6040
6041 /* Since this might be a conditional if, this pseudo-op will be
6042 called even if we are supported to be ignoring input. Double
6043 check now. Clobber *input_line_pointer so that ignore_input
6044 thinks that this is not a special pseudo-op. */
6045 c = *input_line_pointer;
6046 *input_line_pointer = 0;
6047 if (ignore_input ())
6048 {
6049 *input_line_pointer = c;
6050 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6051 ++input_line_pointer;
6052 demand_empty_rest_of_line ();
6053 return;
6054 }
6055 *input_line_pointer = c;
6056
6057 n = push_mri_control (mri_if);
6058
6059 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6060 n->next, s[1] == '.' ? s[2] : '\0');
6061
6062 if (s[1] == '.')
6063 input_line_pointer = s + 3;
6064 else
6065 input_line_pointer = s + 1;
6066
6067 if (flag_mri)
6068 {
6069 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6070 ++input_line_pointer;
6071 }
6072
6073 demand_empty_rest_of_line ();
6074 }
6075
6076 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6077 structured IF, associate the ELSE with the IF. Otherwise, assume
6078 it is a conditional else. */
6079
6080 static void
6081 s_mri_else (qual)
6082 int qual;
6083 {
6084 int c;
6085 char *buf;
6086 char q[2];
6087
6088 if (qual == '\0'
6089 && (mri_control_stack == NULL
6090 || mri_control_stack->type != mri_if
6091 || mri_control_stack->else_seen))
6092 {
6093 s_else (0);
6094 return;
6095 }
6096
6097 c = *input_line_pointer;
6098 *input_line_pointer = 0;
6099 if (ignore_input ())
6100 {
6101 *input_line_pointer = c;
6102 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6103 ++input_line_pointer;
6104 demand_empty_rest_of_line ();
6105 return;
6106 }
6107 *input_line_pointer = c;
6108
6109 if (mri_control_stack == NULL
6110 || mri_control_stack->type != mri_if
6111 || mri_control_stack->else_seen)
6112 {
6113 as_bad (_("else without matching if"));
6114 ignore_rest_of_line ();
6115 return;
6116 }
6117
6118 mri_control_stack->else_seen = 1;
6119
6120 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6121 q[0] = qual;
6122 q[1] = '\0';
6123 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6124 mri_assemble (buf);
6125 free (buf);
6126
6127 colon (mri_control_stack->next);
6128
6129 if (flag_mri)
6130 {
6131 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6132 ++input_line_pointer;
6133 }
6134
6135 demand_empty_rest_of_line ();
6136 }
6137
6138 /* Handle the MRI ENDI pseudo-op. */
6139
6140 static void
6141 s_mri_endi (ignore)
6142 int ignore ATTRIBUTE_UNUSED;
6143 {
6144 if (mri_control_stack == NULL
6145 || mri_control_stack->type != mri_if)
6146 {
6147 as_bad (_("endi without matching if"));
6148 ignore_rest_of_line ();
6149 return;
6150 }
6151
6152 /* ignore_input will not return true for ENDI, so we don't need to
6153 worry about checking it again here. */
6154
6155 if (! mri_control_stack->else_seen)
6156 colon (mri_control_stack->next);
6157 colon (mri_control_stack->bottom);
6158
6159 pop_mri_control ();
6160
6161 if (flag_mri)
6162 {
6163 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6164 ++input_line_pointer;
6165 }
6166
6167 demand_empty_rest_of_line ();
6168 }
6169
6170 /* Handle the MRI BREAK pseudo-op. */
6171
6172 static void
6173 s_mri_break (extent)
6174 int extent;
6175 {
6176 struct mri_control_info *n;
6177 char *buf;
6178 char ex[2];
6179
6180 n = mri_control_stack;
6181 while (n != NULL
6182 && n->type != mri_for
6183 && n->type != mri_repeat
6184 && n->type != mri_while)
6185 n = n->outer;
6186 if (n == NULL)
6187 {
6188 as_bad (_("break outside of structured loop"));
6189 ignore_rest_of_line ();
6190 return;
6191 }
6192
6193 buf = (char *) xmalloc (20 + strlen (n->bottom));
6194 ex[0] = extent;
6195 ex[1] = '\0';
6196 sprintf (buf, "bra%s %s", ex, n->bottom);
6197 mri_assemble (buf);
6198 free (buf);
6199
6200 if (flag_mri)
6201 {
6202 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6203 ++input_line_pointer;
6204 }
6205
6206 demand_empty_rest_of_line ();
6207 }
6208
6209 /* Handle the MRI NEXT pseudo-op. */
6210
6211 static void
6212 s_mri_next (extent)
6213 int extent;
6214 {
6215 struct mri_control_info *n;
6216 char *buf;
6217 char ex[2];
6218
6219 n = mri_control_stack;
6220 while (n != NULL
6221 && n->type != mri_for
6222 && n->type != mri_repeat
6223 && n->type != mri_while)
6224 n = n->outer;
6225 if (n == NULL)
6226 {
6227 as_bad (_("next outside of structured loop"));
6228 ignore_rest_of_line ();
6229 return;
6230 }
6231
6232 buf = (char *) xmalloc (20 + strlen (n->next));
6233 ex[0] = extent;
6234 ex[1] = '\0';
6235 sprintf (buf, "bra%s %s", ex, n->next);
6236 mri_assemble (buf);
6237 free (buf);
6238
6239 if (flag_mri)
6240 {
6241 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6242 ++input_line_pointer;
6243 }
6244
6245 demand_empty_rest_of_line ();
6246 }
6247
6248 /* Handle the MRI FOR pseudo-op. */
6249
6250 static void
6251 s_mri_for (qual)
6252 int qual;
6253 {
6254 const char *varstart, *varstop;
6255 const char *initstart, *initstop;
6256 const char *endstart, *endstop;
6257 const char *bystart, *bystop;
6258 int up;
6259 int by;
6260 int extent;
6261 struct mri_control_info *n;
6262 char *buf;
6263 char *s;
6264 char ex[2];
6265
6266 /* The syntax is
6267 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6268 */
6269
6270 SKIP_WHITESPACE ();
6271 varstart = input_line_pointer;
6272
6273 /* Look for the '='. */
6274 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6275 && *input_line_pointer != '=')
6276 ++input_line_pointer;
6277 if (*input_line_pointer != '=')
6278 {
6279 as_bad (_("missing ="));
6280 ignore_rest_of_line ();
6281 return;
6282 }
6283
6284 varstop = input_line_pointer;
6285 if (varstop > varstart
6286 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6287 --varstop;
6288
6289 ++input_line_pointer;
6290
6291 initstart = input_line_pointer;
6292
6293 /* Look for TO or DOWNTO. */
6294 up = 1;
6295 initstop = NULL;
6296 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6297 {
6298 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6299 && ! is_part_of_name (input_line_pointer[2]))
6300 {
6301 initstop = input_line_pointer;
6302 input_line_pointer += 2;
6303 break;
6304 }
6305 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6306 && ! is_part_of_name (input_line_pointer[6]))
6307 {
6308 initstop = input_line_pointer;
6309 up = 0;
6310 input_line_pointer += 6;
6311 break;
6312 }
6313 ++input_line_pointer;
6314 }
6315 if (initstop == NULL)
6316 {
6317 as_bad (_("missing to or downto"));
6318 ignore_rest_of_line ();
6319 return;
6320 }
6321 if (initstop > initstart
6322 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6323 --initstop;
6324
6325 SKIP_WHITESPACE ();
6326 endstart = input_line_pointer;
6327
6328 /* Look for BY or DO. */
6329 by = 0;
6330 endstop = NULL;
6331 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6332 {
6333 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6334 && ! is_part_of_name (input_line_pointer[2]))
6335 {
6336 endstop = input_line_pointer;
6337 by = 1;
6338 input_line_pointer += 2;
6339 break;
6340 }
6341 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6342 && (input_line_pointer[2] == '.'
6343 || ! is_part_of_name (input_line_pointer[2])))
6344 {
6345 endstop = input_line_pointer;
6346 input_line_pointer += 2;
6347 break;
6348 }
6349 ++input_line_pointer;
6350 }
6351 if (endstop == NULL)
6352 {
6353 as_bad (_("missing do"));
6354 ignore_rest_of_line ();
6355 return;
6356 }
6357 if (endstop > endstart
6358 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6359 --endstop;
6360
6361 if (! by)
6362 {
6363 bystart = "#1";
6364 bystop = bystart + 2;
6365 }
6366 else
6367 {
6368 SKIP_WHITESPACE ();
6369 bystart = input_line_pointer;
6370
6371 /* Look for DO. */
6372 bystop = NULL;
6373 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6374 {
6375 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6376 && (input_line_pointer[2] == '.'
6377 || ! is_part_of_name (input_line_pointer[2])))
6378 {
6379 bystop = input_line_pointer;
6380 input_line_pointer += 2;
6381 break;
6382 }
6383 ++input_line_pointer;
6384 }
6385 if (bystop == NULL)
6386 {
6387 as_bad (_("missing do"));
6388 ignore_rest_of_line ();
6389 return;
6390 }
6391 if (bystop > bystart
6392 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6393 --bystop;
6394 }
6395
6396 if (*input_line_pointer != '.')
6397 extent = '\0';
6398 else
6399 {
6400 extent = input_line_pointer[1];
6401 input_line_pointer += 2;
6402 }
6403
6404 /* We have fully parsed the FOR operands. Now build the loop. */
6405
6406 n = push_mri_control (mri_for);
6407
6408 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6409
6410 /* move init,var */
6411 s = buf;
6412 *s++ = 'm';
6413 *s++ = 'o';
6414 *s++ = 'v';
6415 *s++ = 'e';
6416 if (qual != '\0')
6417 *s++ = qual;
6418 *s++ = ' ';
6419 memcpy (s, initstart, initstop - initstart);
6420 s += initstop - initstart;
6421 *s++ = ',';
6422 memcpy (s, varstart, varstop - varstart);
6423 s += varstop - varstart;
6424 *s = '\0';
6425 mri_assemble (buf);
6426
6427 colon (n->top);
6428
6429 /* cmp end,var */
6430 s = buf;
6431 *s++ = 'c';
6432 *s++ = 'm';
6433 *s++ = 'p';
6434 if (qual != '\0')
6435 *s++ = qual;
6436 *s++ = ' ';
6437 memcpy (s, endstart, endstop - endstart);
6438 s += endstop - endstart;
6439 *s++ = ',';
6440 memcpy (s, varstart, varstop - varstart);
6441 s += varstop - varstart;
6442 *s = '\0';
6443 mri_assemble (buf);
6444
6445 /* bcc bottom */
6446 ex[0] = extent;
6447 ex[1] = '\0';
6448 if (up)
6449 sprintf (buf, "blt%s %s", ex, n->bottom);
6450 else
6451 sprintf (buf, "bgt%s %s", ex, n->bottom);
6452 mri_assemble (buf);
6453
6454 /* Put together the add or sub instruction used by ENDF. */
6455 s = buf;
6456 if (up)
6457 strcpy (s, "add");
6458 else
6459 strcpy (s, "sub");
6460 s += 3;
6461 if (qual != '\0')
6462 *s++ = qual;
6463 *s++ = ' ';
6464 memcpy (s, bystart, bystop - bystart);
6465 s += bystop - bystart;
6466 *s++ = ',';
6467 memcpy (s, varstart, varstop - varstart);
6468 s += varstop - varstart;
6469 *s = '\0';
6470 n->incr = buf;
6471
6472 if (flag_mri)
6473 {
6474 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6475 ++input_line_pointer;
6476 }
6477
6478 demand_empty_rest_of_line ();
6479 }
6480
6481 /* Handle the MRI ENDF pseudo-op. */
6482
6483 static void
6484 s_mri_endf (ignore)
6485 int ignore ATTRIBUTE_UNUSED;
6486 {
6487 if (mri_control_stack == NULL
6488 || mri_control_stack->type != mri_for)
6489 {
6490 as_bad (_("endf without for"));
6491 ignore_rest_of_line ();
6492 return;
6493 }
6494
6495 colon (mri_control_stack->next);
6496
6497 mri_assemble (mri_control_stack->incr);
6498
6499 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6500 mri_assemble (mri_control_stack->incr);
6501
6502 free (mri_control_stack->incr);
6503
6504 colon (mri_control_stack->bottom);
6505
6506 pop_mri_control ();
6507
6508 if (flag_mri)
6509 {
6510 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6511 ++input_line_pointer;
6512 }
6513
6514 demand_empty_rest_of_line ();
6515 }
6516
6517 /* Handle the MRI REPEAT pseudo-op. */
6518
6519 static void
6520 s_mri_repeat (ignore)
6521 int ignore ATTRIBUTE_UNUSED;
6522 {
6523 struct mri_control_info *n;
6524
6525 n = push_mri_control (mri_repeat);
6526 colon (n->top);
6527 if (flag_mri)
6528 {
6529 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6530 ++input_line_pointer;
6531 }
6532 demand_empty_rest_of_line ();
6533 }
6534
6535 /* Handle the MRI UNTIL pseudo-op. */
6536
6537 static void
6538 s_mri_until (qual)
6539 int qual;
6540 {
6541 char *s;
6542
6543 if (mri_control_stack == NULL
6544 || mri_control_stack->type != mri_repeat)
6545 {
6546 as_bad (_("until without repeat"));
6547 ignore_rest_of_line ();
6548 return;
6549 }
6550
6551 colon (mri_control_stack->next);
6552
6553 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6554 ;
6555
6556 parse_mri_control_expression (s, qual, (const char *) NULL,
6557 mri_control_stack->top, '\0');
6558
6559 colon (mri_control_stack->bottom);
6560
6561 input_line_pointer = s;
6562
6563 pop_mri_control ();
6564
6565 if (flag_mri)
6566 {
6567 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6568 ++input_line_pointer;
6569 }
6570
6571 demand_empty_rest_of_line ();
6572 }
6573
6574 /* Handle the MRI WHILE pseudo-op. */
6575
6576 static void
6577 s_mri_while (qual)
6578 int qual;
6579 {
6580 char *s;
6581
6582 struct mri_control_info *n;
6583
6584 s = input_line_pointer;
6585 while (! is_end_of_line[(unsigned char) *s]
6586 && (! flag_mri || *s != '*'))
6587 s++;
6588 --s;
6589 while (*s == ' ' || *s == '\t')
6590 --s;
6591 if (s - input_line_pointer > 1
6592 && s[-1] == '.')
6593 s -= 2;
6594 if (s - input_line_pointer < 2
6595 || strncasecmp (s - 1, "DO", 2) != 0)
6596 {
6597 as_bad (_("missing do"));
6598 ignore_rest_of_line ();
6599 return;
6600 }
6601
6602 n = push_mri_control (mri_while);
6603
6604 colon (n->next);
6605
6606 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6607 s[1] == '.' ? s[2] : '\0');
6608
6609 input_line_pointer = s + 1;
6610 if (*input_line_pointer == '.')
6611 input_line_pointer += 2;
6612
6613 if (flag_mri)
6614 {
6615 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6616 ++input_line_pointer;
6617 }
6618
6619 demand_empty_rest_of_line ();
6620 }
6621
6622 /* Handle the MRI ENDW pseudo-op. */
6623
6624 static void
6625 s_mri_endw (ignore)
6626 int ignore ATTRIBUTE_UNUSED;
6627 {
6628 char *buf;
6629
6630 if (mri_control_stack == NULL
6631 || mri_control_stack->type != mri_while)
6632 {
6633 as_bad (_("endw without while"));
6634 ignore_rest_of_line ();
6635 return;
6636 }
6637
6638 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6639 sprintf (buf, "bra %s", mri_control_stack->next);
6640 mri_assemble (buf);
6641 free (buf);
6642
6643 colon (mri_control_stack->bottom);
6644
6645 pop_mri_control ();
6646
6647 if (flag_mri)
6648 {
6649 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6650 ++input_line_pointer;
6651 }
6652
6653 demand_empty_rest_of_line ();
6654 }
6655 \f
6656 /*
6657 * md_parse_option
6658 * Invocation line includes a switch not recognized by the base assembler.
6659 * See if it's a processor-specific option. These are:
6660 *
6661 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6662 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6663 * Select the architecture. Instructions or features not
6664 * supported by the selected architecture cause fatal
6665 * errors. More than one may be specified. The default is
6666 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6667 * for -m68000, and -m68882 is a synonym for -m68881.
6668 * -[A]m[c]no-68851, -[A]m[c]no-68881
6669 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6670 * so don't use or document it, but that's the way the parsing
6671 * works).
6672 *
6673 * -pic Indicates PIC.
6674 * -k Indicates PIC. (Sun 3 only.)
6675 * --pcrel Never turn PC-relative branches into absolute jumps.
6676 *
6677 * --bitwise-or
6678 * Permit `|' to be used in expressions.
6679 *
6680 */
6681
6682 #ifdef OBJ_ELF
6683 CONST char *md_shortopts = "lSA:m:kQ:V";
6684 #else
6685 CONST char *md_shortopts = "lSA:m:k";
6686 #endif
6687
6688 struct option md_longopts[] = {
6689 #define OPTION_PIC (OPTION_MD_BASE)
6690 {"pic", no_argument, NULL, OPTION_PIC},
6691 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6692 {"register-prefix-optional", no_argument, NULL,
6693 OPTION_REGISTER_PREFIX_OPTIONAL},
6694 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6695 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6696 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6697 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6698 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6699 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6700 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6701 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6702 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6703 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6704 #define OPTION_PCREL (OPTION_MD_BASE + 7)
6705 {"pcrel", no_argument, NULL, OPTION_PCREL},
6706 {NULL, no_argument, NULL, 0}
6707 };
6708 size_t md_longopts_size = sizeof (md_longopts);
6709
6710 int
6711 md_parse_option (c, arg)
6712 int c;
6713 char *arg;
6714 {
6715 switch (c)
6716 {
6717 case 'l': /* -l means keep external to 2 bit offset
6718 rather than 16 bit one */
6719 flag_short_refs = 1;
6720 break;
6721
6722 case 'S': /* -S means that jbsr's always turn into
6723 jsr's. */
6724 flag_long_jumps = 1;
6725 break;
6726
6727 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6728 branches into absolute jumps. */
6729 flag_keep_pcrel = 1;
6730 break;
6731
6732 case 'A':
6733 if (*arg == 'm')
6734 arg++;
6735 /* intentional fall-through */
6736 case 'm':
6737
6738 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6739 {
6740 int i;
6741 unsigned long arch;
6742 const char *oarg = arg;
6743
6744 arg += 3;
6745 if (*arg == 'm')
6746 {
6747 arg++;
6748 if (arg[0] == 'c' && arg[1] == '6')
6749 arg++;
6750 }
6751 for (i = 0; i < n_archs; i++)
6752 if (!strcmp (arg, archs[i].name))
6753 break;
6754 if (i == n_archs)
6755 {
6756 unknown:
6757 as_bad (_("unrecognized option `%s'"), oarg);
6758 return 0;
6759 }
6760 arch = archs[i].arch;
6761 if (arch == m68881)
6762 no_68881 = 1;
6763 else if (arch == m68851)
6764 no_68851 = 1;
6765 else
6766 goto unknown;
6767 }
6768 else
6769 {
6770 int i;
6771
6772 if (arg[0] == 'c' && arg[1] == '6')
6773 arg++;
6774
6775 for (i = 0; i < n_archs; i++)
6776 if (!strcmp (arg, archs[i].name))
6777 {
6778 unsigned long arch = archs[i].arch;
6779 if (cpu_of_arch (arch))
6780 /* It's a cpu spec. */
6781 {
6782 current_architecture &= ~m68000up;
6783 current_architecture |= arch;
6784 }
6785 else if (arch == m68881)
6786 {
6787 current_architecture |= m68881;
6788 no_68881 = 0;
6789 }
6790 else if (arch == m68851)
6791 {
6792 current_architecture |= m68851;
6793 no_68851 = 0;
6794 }
6795 else
6796 /* ??? */
6797 abort ();
6798 break;
6799 }
6800 if (i == n_archs)
6801 {
6802 as_bad (_("unrecognized architecture specification `%s'"), arg);
6803 return 0;
6804 }
6805 }
6806 break;
6807
6808 case OPTION_PIC:
6809 case 'k':
6810 flag_want_pic = 1;
6811 break; /* -pic, Position Independent Code */
6812
6813 case OPTION_REGISTER_PREFIX_OPTIONAL:
6814 flag_reg_prefix_optional = 1;
6815 reg_prefix_optional_seen = 1;
6816 break;
6817
6818 /* -V: SVR4 argument to print version ID. */
6819 case 'V':
6820 print_version_id ();
6821 break;
6822
6823 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6824 should be emitted or not. FIXME: Not implemented. */
6825 case 'Q':
6826 break;
6827
6828 case OPTION_BITWISE_OR:
6829 {
6830 char *n, *t;
6831 const char *s;
6832
6833 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6834 t = n;
6835 for (s = m68k_comment_chars; *s != '\0'; s++)
6836 if (*s != '|')
6837 *t++ = *s;
6838 *t = '\0';
6839 m68k_comment_chars = n;
6840 }
6841 break;
6842
6843 case OPTION_BASE_SIZE_DEFAULT_16:
6844 m68k_index_width_default = SIZE_WORD;
6845 break;
6846
6847 case OPTION_BASE_SIZE_DEFAULT_32:
6848 m68k_index_width_default = SIZE_LONG;
6849 break;
6850
6851 case OPTION_DISP_SIZE_DEFAULT_16:
6852 m68k_rel32 = 0;
6853 m68k_rel32_from_cmdline = 1;
6854 break;
6855
6856 case OPTION_DISP_SIZE_DEFAULT_32:
6857 m68k_rel32 = 1;
6858 m68k_rel32_from_cmdline = 1;
6859 break;
6860
6861 default:
6862 return 0;
6863 }
6864
6865 return 1;
6866 }
6867
6868 void
6869 md_show_usage (stream)
6870 FILE *stream;
6871 {
6872 fprintf (stream, _("\
6873 680X0 options:\n\
6874 -l use 1 word for refs to undefined symbols [default 2]\n\
6875 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6876 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6877 | -mcpu32 | -m5200\n\
6878 specify variant of 680X0 architecture [default 68020]\n\
6879 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6880 target has/lacks floating-point coprocessor\n\
6881 [default yes for 68020, 68030, and cpu32]\n"));
6882 fprintf (stream, _("\
6883 -m68851 | -mno-68851\n\
6884 target has/lacks memory-management unit coprocessor\n\
6885 [default yes for 68020 and up]\n\
6886 -pic, -k generate position independent code\n\
6887 -S turn jbsr into jsr\n\
6888 --pcrel never turn PC-relative branches into absolute jumps\n\
6889 --register-prefix-optional\n\
6890 recognize register names without prefix character\n\
6891 --bitwise-or do not treat `|' as a comment character\n"));
6892 fprintf (stream, _("\
6893 --base-size-default-16 base reg without size is 16 bits\n\
6894 --base-size-default-32 base reg without size is 32 bits (default)\n\
6895 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6896 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6897 }
6898 \f
6899 #ifdef TEST2
6900
6901 /* TEST2: Test md_assemble() */
6902 /* Warning, this routine probably doesn't work anymore */
6903
6904 main ()
6905 {
6906 struct m68k_it the_ins;
6907 char buf[120];
6908 char *cp;
6909 int n;
6910
6911 m68k_ip_begin ();
6912 for (;;)
6913 {
6914 if (!gets (buf) || !*buf)
6915 break;
6916 if (buf[0] == '|' || buf[1] == '.')
6917 continue;
6918 for (cp = buf; *cp; cp++)
6919 if (*cp == '\t')
6920 *cp = ' ';
6921 if (is_label (buf))
6922 continue;
6923 memset (&the_ins, '\0', sizeof (the_ins));
6924 m68k_ip (&the_ins, buf);
6925 if (the_ins.error)
6926 {
6927 printf (_("Error %s in %s\n"), the_ins.error, buf);
6928 }
6929 else
6930 {
6931 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
6932 for (n = 0; n < the_ins.numo; n++)
6933 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6934 printf (" ");
6935 print_the_insn (&the_ins.opcode[0], stdout);
6936 (void) putchar ('\n');
6937 }
6938 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6939 {
6940 if (the_ins.operands[n].error)
6941 {
6942 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6943 continue;
6944 }
6945 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6946 if (the_ins.operands[n].b_const)
6947 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6948 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6949 if (the_ins.operands[n].b_iadd)
6950 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6951 (void) putchar ('\n');
6952 }
6953 }
6954 m68k_ip_end ();
6955 return 0;
6956 }
6957
6958 is_label (str)
6959 char *str;
6960 {
6961 while (*str == ' ')
6962 str++;
6963 while (*str && *str != ' ')
6964 str++;
6965 if (str[-1] == ':' || str[1] == '=')
6966 return 1;
6967 return 0;
6968 }
6969
6970 #endif
6971
6972 /* Possible states for relaxation:
6973
6974 0 0 branch offset byte (bra, etc)
6975 0 1 word
6976 0 2 long
6977
6978 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6979 1 1 word
6980 1 2 long
6981
6982 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6983 2 1 word-long
6984 2 2 long-word
6985 2 3 long-long
6986
6987 */
6988
6989 /* We have no need to default values of symbols. */
6990
6991 symbolS *
6992 md_undefined_symbol (name)
6993 char *name ATTRIBUTE_UNUSED;
6994 {
6995 return 0;
6996 }
6997
6998 /* Round up a section size to the appropriate boundary. */
6999 valueT
7000 md_section_align (segment, size)
7001 segT segment ATTRIBUTE_UNUSED;
7002 valueT size;
7003 {
7004 #ifdef OBJ_AOUT
7005 #ifdef BFD_ASSEMBLER
7006 /* For a.out, force the section size to be aligned. If we don't do
7007 this, BFD will align it for us, but it will not write out the
7008 final bytes of the section. This may be a bug in BFD, but it is
7009 easier to fix it here since that is how the other a.out targets
7010 work. */
7011 int align;
7012
7013 align = bfd_get_section_alignment (stdoutput, segment);
7014 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7015 #endif
7016 #endif
7017
7018 return size;
7019 }
7020
7021 /* Exactly what point is a PC-relative offset relative TO?
7022 On the 68k, it is relative to the address of the first extension
7023 word. The difference between the addresses of the offset and the
7024 first extension word is stored in fx_pcrel_adjust. */
7025 long
7026 md_pcrel_from (fixP)
7027 fixS *fixP;
7028 {
7029 int adjust;
7030
7031 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7032 sign extend the value here. */
7033 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7034 if (adjust == 64)
7035 adjust = -1;
7036 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7037 }
7038
7039 #ifndef BFD_ASSEMBLER
7040 #ifdef OBJ_COFF
7041
7042 void
7043 tc_coff_symbol_emit_hook (ignore)
7044 symbolS *ignore ATTRIBUTE_UNUSED;
7045 {
7046 }
7047
7048 int
7049 tc_coff_sizemachdep (frag)
7050 fragS *frag;
7051 {
7052 switch (frag->fr_subtype & 0x3)
7053 {
7054 case BYTE:
7055 return 1;
7056 case SHORT:
7057 return 2;
7058 case LONG:
7059 return 4;
7060 default:
7061 abort ();
7062 return 0;
7063 }
7064 }
7065
7066 #endif
7067 #endif
7068 #ifdef OBJ_ELF
7069 void m68k_elf_final_processing()
7070 {
7071 /* Set file-specific flags if this is a cpu32 processor */
7072 if (cpu_of_arch (current_architecture) & cpu32)
7073 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7074 }
7075 #endif
GDB Binutils - Deliverables
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