1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
36 /* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40 #if defined (TE_SVR4) || defined (TE_DELTA)
41 const char *m68k_comment_chars
= "|#";
43 const char *m68k_comment_chars
= "|";
46 /* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49 /* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52 /* Also note that comments like this one will always work. */
53 const char line_comment_chars
[] = "#*";
55 const char line_separator_chars
[] = ";";
57 /* Chars that can be used to separate mant from exp in floating point nums. */
58 const char EXP_CHARS
[] = "eE";
60 /* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
63 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
65 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
69 const int md_reloc_size
= 8; /* Size of relocation record. */
71 /* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
73 references. Not implemented. For ELF there are other means
74 to denote pic relocations. */
77 static int flag_short_refs
; /* -l option. */
78 static int flag_long_jumps
; /* -S option. */
79 static int flag_keep_pcrel
; /* --pcrel option. */
81 #ifdef REGISTER_PREFIX_OPTIONAL
82 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
84 int flag_reg_prefix_optional
;
87 /* Whether --register-prefix-optional was used on the command line. */
88 static int reg_prefix_optional_seen
;
90 /* The floating point coprocessor to use by default. */
91 static enum m68k_register m68k_float_copnum
= COP1
;
93 /* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95 static int m68k_abspcadd
;
97 /* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99 static int m68k_quick
= 1;
101 /* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
104 static int m68k_rel32
= 1;
106 /* This is non-zero if m68k_rel32 was set from the command line. */
107 static int m68k_rel32_from_cmdline
;
109 /* The default width to use for an index register when using a base
111 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
113 /* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
118 struct label_line
*next
;
125 /* The list of labels. */
127 static struct label_line
*labels
;
129 /* The current label. */
131 static struct label_line
*current_label
;
133 /* Its an arbitrary name: This means I don't approve of it.
135 static struct obstack robyn
;
139 const char *m_operands
;
140 unsigned long m_opcode
;
144 struct m68k_incant
*m_next
;
147 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
148 #define gettwo(x) (((x)->m_opcode)&0xffff)
150 static const enum m68k_register m68000_control_regs
[] = { 0 };
151 static const enum m68k_register m68010_control_regs
[] = {
155 static const enum m68k_register m68020_control_regs
[] = {
156 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
159 static const enum m68k_register m68040_control_regs
[] = {
160 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
161 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
164 static const enum m68k_register m68060_control_regs
[] = {
165 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
166 USP
, VBR
, URP
, SRP
, PCR
,
169 static const enum m68k_register mcf_control_regs
[] = {
170 CACR
, TC
, ACR0
, ACR1
, ACR2
, ACR3
, VBR
, ROMBAR
,
171 RAMBAR0
, RAMBAR1
, MBAR
,
174 static const enum m68k_register mcf528x_control_regs
[] = {
175 CACR
, ACR0
, ACR1
, VBR
, FLASHBAR
, RAMBAR
,
178 static const enum m68k_register mcfv4e_control_regs
[] = {
179 CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
, VBR
, PC
, ROMBAR
,
180 ROMBAR1
, RAMBAR0
, RAMBAR1
, MPCR
, EDRAMBAR
, SECMBAR
, MBAR
, MBAR0
, MBAR1
,
181 PCR1U0
, PCR1L0
, PCR1U1
, PCR1L1
, PCR2U0
, PCR2L0
, PCR2U1
, PCR2L1
,
182 PCR3U0
, PCR3L0
, PCR3U1
, PCR3L1
,
185 #define cpu32_control_regs m68010_control_regs
187 static const enum m68k_register
*control_regs
;
189 /* Internal form of a 68020 instruction. */
193 const char *args
; /* List of opcode info. */
196 int numo
; /* Number of shorts in opcode. */
199 struct m68k_op operands
[6];
201 int nexp
; /* Number of exprs in use. */
202 struct m68k_exp exprs
[4];
204 int nfrag
; /* Number of frags we have to produce. */
207 int fragoff
; /* Where in the current opcode the frag ends. */
214 int nrel
; /* Num of reloc strucs in use. */
221 /* In a pc relative address the difference between the address
222 of the offset and the address that the offset is relative
223 to. This depends on the addressing mode. Basically this
224 is the value to put in the offset field to address the
225 first byte of the offset, without regarding the special
226 significance of some values (in the branch instruction, for
230 /* Whether this expression needs special pic relocation, and if
232 enum pic_relocation pic_reloc
;
235 reloc
[5]; /* Five is enough??? */
238 #define cpu_of_arch(x) ((x) & (m68000up | mcf))
239 #define float_of_arch(x) ((x) & mfloat)
240 #define mmu_of_arch(x) ((x) & mmmu)
241 #define arch_coldfire_p(x) ((x) & mcf)
242 #define arch_coldfire_v4e_p(x) ((x) & mcfv4e)
244 /* Macros for determining if cpu supports a specific addressing mode. */
245 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407|mcfv4e))
247 static struct m68k_it the_ins
; /* The instruction being assembled. */
249 #define op(ex) ((ex)->exp.X_op)
250 #define adds(ex) ((ex)->exp.X_add_symbol)
251 #define subs(ex) ((ex)->exp.X_op_symbol)
252 #define offs(ex) ((ex)->exp.X_add_number)
254 /* Macros for adding things to the m68k_it struct. */
255 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
257 /* Static functions. */
258 static void insop
PARAMS ((int, const struct m68k_incant
*));
259 static void add_fix
PARAMS ((int, struct m68k_exp
*, int, int));
260 static void add_frag
PARAMS ((symbolS
*, offsetT
, int));
262 /* Like addword, but goes BEFORE general operands. */
267 const struct m68k_incant
*opcode
;
270 for (z
= the_ins
.numo
; z
> opcode
->m_codenum
; --z
)
271 the_ins
.opcode
[z
] = the_ins
.opcode
[z
- 1];
272 for (z
= 0; z
< the_ins
.nrel
; z
++)
273 the_ins
.reloc
[z
].n
+= 2;
274 for (z
= 0; z
< the_ins
.nfrag
; z
++)
275 the_ins
.fragb
[z
].fragoff
++;
276 the_ins
.opcode
[opcode
->m_codenum
] = w
;
280 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
283 add_fix (width
, exp
, pc_rel
, pc_fix
)
285 struct m68k_exp
*exp
;
289 the_ins
.reloc
[the_ins
.nrel
].n
= ((width
== 'B' || width
== '3')
293 : (the_ins
.numo
*2)));
294 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
295 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
296 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
298 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
300 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
303 /* Cause an extra frag to be generated here, inserting up to 10 bytes
304 (that value is chosen in the frag_var call in md_assemble). TYPE
305 is the subtype of the frag to be generated; its primary type is
306 rs_machine_dependent.
308 The TYPE parameter is also used by md_convert_frag_1 and
309 md_estimate_size_before_relax. The appropriate type of fixup will
310 be emitted by md_convert_frag_1.
312 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
314 add_frag (add
, off
, type
)
319 the_ins
.fragb
[the_ins
.nfrag
].fragoff
= the_ins
.numo
;
320 the_ins
.fragb
[the_ins
.nfrag
].fadd
= add
;
321 the_ins
.fragb
[the_ins
.nfrag
].foff
= off
;
322 the_ins
.fragb
[the_ins
.nfrag
++].fragty
= type
;
326 (op (ex) != O_constant && op (ex) != O_big)
328 static char *crack_operand
PARAMS ((char *str
, struct m68k_op
*opP
));
329 static int get_num
PARAMS ((struct m68k_exp
*exp
, int ok
));
330 static void m68k_ip
PARAMS ((char *));
331 static void insert_reg
PARAMS ((const char *, int));
332 static void select_control_regs
PARAMS ((void));
333 static void init_regtable
PARAMS ((void));
334 static int reverse_16_bits
PARAMS ((int in
));
335 static int reverse_8_bits
PARAMS ((int in
));
336 static void install_gen_operand
PARAMS ((int mode
, int val
));
337 static void install_operand
PARAMS ((int mode
, int val
));
338 static void s_bss
PARAMS ((int));
339 static void s_data1
PARAMS ((int));
340 static void s_data2
PARAMS ((int));
341 static void s_even
PARAMS ((int));
342 static void s_proc
PARAMS ((int));
343 static void mri_chip
PARAMS ((void));
344 static void s_chip
PARAMS ((int));
345 static void s_fopt
PARAMS ((int));
346 static void s_opt
PARAMS ((int));
347 static void s_reg
PARAMS ((int));
348 static void s_restore
PARAMS ((int));
349 static void s_save
PARAMS ((int));
350 static void s_mri_if
PARAMS ((int));
351 static void s_mri_else
PARAMS ((int));
352 static void s_mri_endi
PARAMS ((int));
353 static void s_mri_break
PARAMS ((int));
354 static void s_mri_next
PARAMS ((int));
355 static void s_mri_for
PARAMS ((int));
356 static void s_mri_endf
PARAMS ((int));
357 static void s_mri_repeat
PARAMS ((int));
358 static void s_mri_until
PARAMS ((int));
359 static void s_mri_while
PARAMS ((int));
360 static void s_mri_endw
PARAMS ((int));
361 static void md_convert_frag_1
PARAMS ((fragS
*));
363 static int current_architecture
;
372 static const struct m68k_cpu archs
[] =
374 { m68000
, "68000", 0 },
375 { m68010
, "68010", 0 },
376 { m68020
, "68020", 0 },
377 { m68030
, "68030", 0 },
378 { m68040
, "68040", 0 },
379 { m68060
, "68060", 0 },
380 { cpu32
, "cpu32", 0 },
381 { m68881
, "68881", 0 },
382 { m68851
, "68851", 0 },
383 { mcf5200
, "5200", 0 },
384 { mcf5206e
, "5206e", 0 },
385 { mcf528x
|mcfmac
, "528x", 0 },
386 { mcf5307
|mcfmac
, "5307", 0 },
387 { mcf5407
|mcfmac
, "5407", 0 },
388 { mcfv4e
|mcfemac
, "cfv4e", 0 },
389 /* Aliases (effectively, so far as gas is concerned) for the above
391 { m68020
, "68k", 1 },
392 { m68000
, "68008", 1 },
393 { m68000
, "68302", 1 },
394 { m68000
, "68306", 1 },
395 { m68000
, "68307", 1 },
396 { m68000
, "68322", 1 },
397 { m68000
, "68356", 1 },
398 { m68000
, "68ec000", 1 },
399 { m68000
, "68hc000", 1 },
400 { m68000
, "68hc001", 1 },
401 { m68020
, "68ec020", 1 },
402 { m68030
, "68ec030", 1 },
403 { m68040
, "68ec040", 1 },
404 { m68060
, "68ec060", 1 },
405 { cpu32
, "68330", 1 },
406 { cpu32
, "68331", 1 },
407 { cpu32
, "68332", 1 },
408 { cpu32
, "68333", 1 },
409 { cpu32
, "68334", 1 },
410 { cpu32
, "68336", 1 },
411 { cpu32
, "68340", 1 },
412 { cpu32
, "68341", 1 },
413 { cpu32
, "68349", 1 },
414 { cpu32
, "68360", 1 },
415 { m68881
, "68882", 1 },
416 { mcf5200
, "5202", 1 },
417 { mcf5200
, "5204", 1 },
418 { mcf5200
, "5206", 1 },
419 { mcf5407
|mcfmac
, "cfv4", 1 },
422 static const int n_archs
= sizeof (archs
) / sizeof (archs
[0]);
424 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
425 architecture and we have a lot of relaxation modes. */
427 /* Macros used in the relaxation code. */
428 #define TAB(x,y) (((x) << 2) + (y))
429 #define TABTYPE(x) ((x) >> 2)
431 /* Relaxation states. */
437 /* Here are all the relaxation modes we support. First we can relax ordinary
438 branches. On 68020 and higher and on CPU32 all branch instructions take
439 three forms, so on these CPUs all branches always remain as such. When we
440 have to expand to the LONG form on a 68000, though, we substitute an
441 absolute jump instead. This is a direct replacement for unconditional
442 branches and a branch over a jump for conditional branches. However, if the
443 user requires PIC and disables this with --pcrel, we can only relax between
444 BYTE and SHORT forms, punting if that isn't enough. This gives us four
445 different relaxation modes for branches: */
447 #define BRANCHBWL 0 /* Branch byte, word, or long. */
448 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
449 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
450 #define BRANCHBW 3 /* Branch byte or word. */
452 /* We also relax coprocessor branches and DBcc's. All CPUs that support
453 coprocessor branches support them in word and long forms, so we have only
454 one relaxation mode for them. DBcc's are word only on all CPUs. We can
455 relax them to the LONG form with a branch-around sequence. This sequence
456 can use a long branch (if available) or an absolute jump (if acceptable).
457 This gives us two relaxation modes. If long branches are not available and
458 absolute jumps are not acceptable, we don't relax DBcc's. */
460 #define FBRANCH 4 /* Coprocessor branch. */
461 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
462 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
464 /* That's all for instruction relaxation. However, we also relax PC-relative
465 operands. Specifically, we have three operand relaxation modes. On the
466 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
467 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
468 two. Also PC+displacement+index operands in their simple form (with a non-
469 suppressed index without memory indirection) are supported on all CPUs, but
470 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
471 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
472 form of the PC+displacement+index operand. Finally, some absolute operands
473 can be relaxed down to 16-bit PC-relative. */
475 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
476 #define PCINDEX 8 /* PC + displacement + index. */
477 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
479 /* Note that calls to frag_var need to specify the maximum expansion
480 needed; this is currently 10 bytes for DBCC. */
483 How far Forward this mode will reach:
484 How far Backward this mode will reach:
485 How many bytes this mode will add to the size of the frag
486 Which mode to go to if the offset won't fit in this one
488 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
489 relax_typeS md_relax_table
[] =
491 { 127, -128, 0, TAB (BRANCHBWL
, SHORT
) },
492 { 32767, -32768, 2, TAB (BRANCHBWL
, LONG
) },
496 { 127, -128, 0, TAB (BRABSJUNC
, SHORT
) },
497 { 32767, -32768, 2, TAB (BRABSJUNC
, LONG
) },
501 { 127, -128, 0, TAB (BRABSJCOND
, SHORT
) },
502 { 32767, -32768, 2, TAB (BRABSJCOND
, LONG
) },
506 { 127, -128, 0, TAB (BRANCHBW
, SHORT
) },
511 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
512 { 32767, -32768, 2, TAB (FBRANCH
, LONG
) },
516 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
517 { 32767, -32768, 2, TAB (DBCCLBR
, LONG
) },
521 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
522 { 32767, -32768, 2, TAB (DBCCABSJ
, LONG
) },
526 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
527 { 32767, -32768, 2, TAB (PCREL1632
, LONG
) },
531 { 125, -130, 0, TAB (PCINDEX
, SHORT
) },
532 { 32765, -32770, 2, TAB (PCINDEX
, LONG
) },
536 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
537 { 32767, -32768, 2, TAB (ABSTOPCREL
, LONG
) },
542 /* These are the machine dependent pseudo-ops. These are included so
543 the assembler can work on the output from the SUN C compiler, which
546 /* This table describes all the machine specific pseudo-ops the assembler
547 has to support. The fields are:
548 pseudo-op name without dot
549 function to call to execute this pseudo-op
550 Integer arg to pass to the function. */
551 const pseudo_typeS md_pseudo_table
[] =
553 {"data1", s_data1
, 0},
554 {"data2", s_data2
, 0},
557 {"skip", s_space
, 0},
559 #if defined (TE_SUN3) || defined (OBJ_ELF)
560 {"align", s_align_bytes
, 0},
563 {"swbeg", s_ignore
, 0},
565 {"extend", float_cons
, 'x'},
566 {"ldouble", float_cons
, 'x'},
568 /* The following pseudo-ops are supported for MRI compatibility. */
570 {"comline", s_space
, 1},
572 {"mask2", s_ignore
, 0},
575 {"restore", s_restore
, 0},
579 {"if.b", s_mri_if
, 'b'},
580 {"if.w", s_mri_if
, 'w'},
581 {"if.l", s_mri_if
, 'l'},
582 {"else", s_mri_else
, 0},
583 {"else.s", s_mri_else
, 's'},
584 {"else.l", s_mri_else
, 'l'},
585 {"endi", s_mri_endi
, 0},
586 {"break", s_mri_break
, 0},
587 {"break.s", s_mri_break
, 's'},
588 {"break.l", s_mri_break
, 'l'},
589 {"next", s_mri_next
, 0},
590 {"next.s", s_mri_next
, 's'},
591 {"next.l", s_mri_next
, 'l'},
592 {"for", s_mri_for
, 0},
593 {"for.b", s_mri_for
, 'b'},
594 {"for.w", s_mri_for
, 'w'},
595 {"for.l", s_mri_for
, 'l'},
596 {"endf", s_mri_endf
, 0},
597 {"repeat", s_mri_repeat
, 0},
598 {"until", s_mri_until
, 0},
599 {"until.b", s_mri_until
, 'b'},
600 {"until.w", s_mri_until
, 'w'},
601 {"until.l", s_mri_until
, 'l'},
602 {"while", s_mri_while
, 0},
603 {"while.b", s_mri_while
, 'b'},
604 {"while.w", s_mri_while
, 'w'},
605 {"while.l", s_mri_while
, 'l'},
606 {"endw", s_mri_endw
, 0},
611 /* The mote pseudo ops are put into the opcode table, since they
612 don't start with a . they look like opcodes to gas.
616 extern void obj_coff_section
PARAMS ((int));
619 const pseudo_typeS mote_pseudo_table
[] =
632 {"xdef", s_globl
, 0},
634 {"align", s_align_bytes
, 0},
636 {"align", s_align_ptwo
, 0},
639 {"sect", obj_coff_section
, 0},
640 {"section", obj_coff_section
, 0},
645 #define issbyte(x) ((x)>=-128 && (x)<=127)
646 #define isubyte(x) ((x)>=0 && (x)<=255)
647 #define issword(x) ((x)>=-32768 && (x)<=32767)
648 #define isuword(x) ((x)>=0 && (x)<=65535)
650 #define isbyte(x) ((x)>= -255 && (x)<=255)
651 #define isword(x) ((x)>=-65536 && (x)<=65535)
652 #define islong(x) (1)
654 extern char *input_line_pointer
;
656 static char notend_table
[256];
657 static char alt_notend_table
[256];
659 (! (notend_table[(unsigned char) *s] \
661 && alt_notend_table[(unsigned char) s[1]])))
663 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
665 #ifdef NO_PCREL_RELOCS
668 make_pcrel_absolute(fixP
, add_number
)
672 register unsigned char *opcode
= fixP
->fx_frag
->fr_opcode
;
674 /* Rewrite the PC relative instructions to absolute address ones.
675 these are rumored to be faster, and the apollo linker refuses
676 to deal with the PC relative relocations. */
677 if (opcode
[0] == 0x60 && opcode
[1] == 0xff) /* BRA -> JMP. */
680 as_fatal(_("Tried to convert PC relative branch to absolute jump"));
684 else if (opcode
[0] == 0x61 && opcode
[1] == 0xff) /* BSR -> JSR. */
687 as_fatal(_("Tried to convert PC relative BSR to absolute JSR"));
692 as_fatal (_("Unknown PC relative instruction"));
697 #endif /* NO_PCREL_RELOCS */
700 tc_coff_fix2rtype (fixP
)
703 if (fixP
->fx_tcbit
&& fixP
->fx_size
== 4)
704 return R_RELLONG_NEG
;
705 #ifdef NO_PCREL_RELOCS
706 know (fixP
->fx_pcrel
== 0);
707 return (fixP
->fx_size
== 1 ? R_RELBYTE
708 : fixP
->fx_size
== 2 ? R_DIR16
711 return (fixP
->fx_pcrel
?
712 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
713 fixP
->fx_size
== 2 ? R_PCRWORD
:
715 (fixP
->fx_size
== 1 ? R_RELBYTE
:
716 fixP
->fx_size
== 2 ? R_RELWORD
:
725 /* Return zero if the reference to SYMBOL from within the same segment may
728 /* On an ELF system, we can't relax an externally visible symbol,
729 because it may be overridden by a shared library. However, if
730 TARGET_OS is "elf", then we presume that we are assembling for an
731 embedded system, in which case we don't have to worry about shared
732 libraries, and we can relax any external sym. */
734 #define relaxable_symbol(symbol) \
735 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
736 || S_IS_WEAK (symbol)))
738 /* Compute the relocation code for a fixup of SIZE bytes, using pc
739 relative relocation if PCREL is non-zero. PIC says whether a special
740 pic relocation was requested. */
742 static bfd_reloc_code_real_type get_reloc_code
743 PARAMS ((int, int, enum pic_relocation
));
745 static bfd_reloc_code_real_type
746 get_reloc_code (size
, pcrel
, pic
)
749 enum pic_relocation pic
;
757 return BFD_RELOC_8_GOT_PCREL
;
759 return BFD_RELOC_16_GOT_PCREL
;
761 return BFD_RELOC_32_GOT_PCREL
;
769 return BFD_RELOC_8_GOTOFF
;
771 return BFD_RELOC_16_GOTOFF
;
773 return BFD_RELOC_32_GOTOFF
;
781 return BFD_RELOC_8_PLT_PCREL
;
783 return BFD_RELOC_16_PLT_PCREL
;
785 return BFD_RELOC_32_PLT_PCREL
;
793 return BFD_RELOC_8_PLTOFF
;
795 return BFD_RELOC_16_PLTOFF
;
797 return BFD_RELOC_32_PLTOFF
;
807 return BFD_RELOC_8_PCREL
;
809 return BFD_RELOC_16_PCREL
;
811 return BFD_RELOC_32_PCREL
;
831 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
833 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
838 as_bad (_("Can not do %d byte relocation"), size
);
840 as_bad (_("Can not do %d byte pic relocation"), size
);
843 return BFD_RELOC_NONE
;
846 /* Here we decide which fixups can be adjusted to make them relative
847 to the beginning of the section instead of the symbol. Basically
848 we need to make sure that the dynamic relocations are done
849 correctly, so in some cases we force the original symbol to be
852 tc_m68k_fix_adjustable (fixP
)
855 /* Adjust_reloc_syms doesn't know about the GOT. */
856 switch (fixP
->fx_r_type
)
858 case BFD_RELOC_8_GOT_PCREL
:
859 case BFD_RELOC_16_GOT_PCREL
:
860 case BFD_RELOC_32_GOT_PCREL
:
861 case BFD_RELOC_8_GOTOFF
:
862 case BFD_RELOC_16_GOTOFF
:
863 case BFD_RELOC_32_GOTOFF
:
864 case BFD_RELOC_8_PLT_PCREL
:
865 case BFD_RELOC_16_PLT_PCREL
:
866 case BFD_RELOC_32_PLT_PCREL
:
867 case BFD_RELOC_8_PLTOFF
:
868 case BFD_RELOC_16_PLTOFF
:
869 case BFD_RELOC_32_PLTOFF
:
872 case BFD_RELOC_VTABLE_INHERIT
:
873 case BFD_RELOC_VTABLE_ENTRY
:
883 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
885 #define relaxable_symbol(symbol) 1
892 tc_gen_reloc (section
, fixp
)
893 asection
*section ATTRIBUTE_UNUSED
;
897 bfd_reloc_code_real_type code
;
899 /* If the tcbit is set, then this was a fixup of a negative value
900 that was never resolved. We do not have a reloc to handle this,
901 so just return. We assume that other code will have detected this
902 situation and produced a helpful error message, so we just tell the
903 user that the reloc cannot be produced. */
907 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
908 _("Unable to produce reloc against symbol '%s'"),
909 S_GET_NAME (fixp
->fx_addsy
));
913 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
915 code
= fixp
->fx_r_type
;
917 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
918 that fixup_segment converted a non-PC relative reloc into a
919 PC relative reloc. In such a case, we need to convert the
926 code
= BFD_RELOC_8_PCREL
;
929 code
= BFD_RELOC_16_PCREL
;
932 code
= BFD_RELOC_32_PCREL
;
934 case BFD_RELOC_8_PCREL
:
935 case BFD_RELOC_16_PCREL
:
936 case BFD_RELOC_32_PCREL
:
937 case BFD_RELOC_8_GOT_PCREL
:
938 case BFD_RELOC_16_GOT_PCREL
:
939 case BFD_RELOC_32_GOT_PCREL
:
940 case BFD_RELOC_8_GOTOFF
:
941 case BFD_RELOC_16_GOTOFF
:
942 case BFD_RELOC_32_GOTOFF
:
943 case BFD_RELOC_8_PLT_PCREL
:
944 case BFD_RELOC_16_PLT_PCREL
:
945 case BFD_RELOC_32_PLT_PCREL
:
946 case BFD_RELOC_8_PLTOFF
:
947 case BFD_RELOC_16_PLTOFF
:
948 case BFD_RELOC_32_PLTOFF
:
951 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
952 _("Cannot make %s relocation PC relative"),
953 bfd_get_reloc_code_name (code
));
959 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
960 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
962 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
963 MAP (1, 0, BFD_RELOC_8
);
964 MAP (2, 0, BFD_RELOC_16
);
965 MAP (4, 0, BFD_RELOC_32
);
966 MAP (1, 1, BFD_RELOC_8_PCREL
);
967 MAP (2, 1, BFD_RELOC_16_PCREL
);
968 MAP (4, 1, BFD_RELOC_32_PCREL
);
976 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
977 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
978 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
979 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
982 reloc
->addend
= fixp
->fx_addnumber
;
987 reloc
->addend
= fixp
->fx_addnumber
;
989 reloc
->addend
= (section
->vma
990 /* Explicit sign extension in case char is
992 + ((fixp
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80
994 + md_pcrel_from (fixp
));
997 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
998 assert (reloc
->howto
!= 0);
1003 #endif /* BFD_ASSEMBLER */
1005 /* Handle of the OPCODE hash table. NULL means any use before
1006 m68k_ip_begin() will crash. */
1007 static struct hash_control
*op_hash
;
1009 /* Assemble an m68k instruction. */
1016 register struct m68k_op
*opP
;
1017 register const struct m68k_incant
*opcode
;
1018 register const char *s
;
1019 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1020 char *pdot
, *pdotmove
;
1021 enum m68k_size siz1
, siz2
;
1025 LITTLENUM_TYPE words
[6];
1026 LITTLENUM_TYPE
*wordp
;
1027 unsigned long ok_arch
= 0;
1029 if (*instring
== ' ')
1030 instring
++; /* Skip leading whitespace. */
1032 /* Scan up to end of operation-code, which MUST end in end-of-string
1033 or exactly 1 space. */
1035 for (p
= instring
; *p
!= '\0'; p
++)
1045 the_ins
.error
= _("No operator");
1049 /* p now points to the end of the opcode name, probably whitespace.
1050 Make sure the name is null terminated by clobbering the
1051 whitespace, look it up in the hash table, then fix it back.
1052 Remove a dot, first, since the opcode tables have none. */
1055 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1056 *pdotmove
= pdotmove
[1];
1062 opcode
= (const struct m68k_incant
*) hash_find (op_hash
, instring
);
1067 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1068 *pdotmove
= pdotmove
[-1];
1075 the_ins
.error
= _("Unknown operator");
1079 /* Found a legitimate opcode, start matching operands. */
1083 if (opcode
->m_operands
== 0)
1085 char *old
= input_line_pointer
;
1087 input_line_pointer
= p
;
1088 /* Ahh - it's a motorola style psuedo op. */
1089 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1090 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1091 input_line_pointer
= old
;
1097 if (flag_mri
&& opcode
->m_opnum
== 0)
1099 /* In MRI mode, random garbage is allowed after an instruction
1100 which accepts no operands. */
1101 the_ins
.args
= opcode
->m_operands
;
1102 the_ins
.numargs
= opcode
->m_opnum
;
1103 the_ins
.numo
= opcode
->m_codenum
;
1104 the_ins
.opcode
[0] = getone (opcode
);
1105 the_ins
.opcode
[1] = gettwo (opcode
);
1109 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1111 p
= crack_operand (p
, opP
);
1115 the_ins
.error
= opP
->error
;
1120 opsfound
= opP
- &the_ins
.operands
[0];
1122 /* This ugly hack is to support the floating pt opcodes in their
1123 standard form. Essentially, we fake a first enty of type COP#1 */
1124 if (opcode
->m_operands
[0] == 'I')
1128 for (n
= opsfound
; n
> 0; --n
)
1129 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1131 memset ((char *) (&the_ins
.operands
[0]), '\0',
1132 sizeof (the_ins
.operands
[0]));
1133 the_ins
.operands
[0].mode
= CONTROL
;
1134 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1138 /* We've got the operands. Find an opcode that'll accept them. */
1141 /* If we didn't get the right number of ops, or we have no
1142 common model with this pattern then reject this pattern. */
1144 ok_arch
|= opcode
->m_arch
;
1145 if (opsfound
!= opcode
->m_opnum
1146 || ((opcode
->m_arch
& current_architecture
) == 0))
1150 for (s
= opcode
->m_operands
, opP
= &the_ins
.operands
[0];
1154 /* Warning: this switch is huge! */
1155 /* I've tried to organize the cases into this order:
1156 non-alpha first, then alpha by letter. Lower-case
1157 goes directly before uppercase counterpart. */
1158 /* Code with multiple case ...: gets sorted by the lowest
1159 case ... it belongs to. I hope this makes sense. */
1265 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1282 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1301 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1311 if (opP
->mode
!= IMMED
)
1313 else if (s
[1] == 'b'
1314 && ! isvar (&opP
->disp
)
1315 && (opP
->disp
.exp
.X_op
!= O_constant
1316 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1318 else if (s
[1] == 'B'
1319 && ! isvar (&opP
->disp
)
1320 && (opP
->disp
.exp
.X_op
!= O_constant
1321 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1323 else if (s
[1] == 'w'
1324 && ! isvar (&opP
->disp
)
1325 && (opP
->disp
.exp
.X_op
!= O_constant
1326 || ! isword (opP
->disp
.exp
.X_add_number
)))
1328 else if (s
[1] == 'W'
1329 && ! isvar (&opP
->disp
)
1330 && (opP
->disp
.exp
.X_op
!= O_constant
1331 || ! issword (opP
->disp
.exp
.X_add_number
)))
1337 if (opP
->mode
!= IMMED
)
1342 if (opP
->mode
== AREG
1343 || opP
->mode
== CONTROL
1344 || opP
->mode
== FPREG
1345 || opP
->mode
== IMMED
1346 || opP
->mode
== REGLST
1347 || (opP
->mode
!= ABSL
1349 || opP
->reg
== ZPC
)))
1354 if (opP
->mode
== CONTROL
1355 || opP
->mode
== FPREG
1356 || opP
->mode
== REGLST
1357 || opP
->mode
== IMMED
1358 || (opP
->mode
!= ABSL
1360 || opP
->reg
== ZPC
)))
1388 if (opP
->mode
== CONTROL
1389 || opP
->mode
== FPREG
1390 || opP
->mode
== REGLST
)
1395 if (opP
->mode
!= AINC
)
1400 if (opP
->mode
!= ADEC
)
1450 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1471 case '~': /* For now! (JF FOO is this right?) */
1493 if (opP
->mode
!= CONTROL
1494 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1499 if (opP
->mode
!= AREG
)
1504 if (opP
->mode
!= AINDR
)
1509 if (opP
->mode
!= AINDR
&& opP
->mode
!= AINC
&& opP
->mode
!= ADEC
1510 && (opP
->mode
!= DISP
1512 || opP
->reg
> ADDR7
))
1517 if (opP
->mode
!= ABSL
1519 && strncmp (instring
, "jbsr", 4) == 0))
1542 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1547 if (opP
->mode
!= DISP
1549 || opP
->reg
> ADDR7
)
1554 if (opP
->mode
!= DREG
)
1559 if (opP
->reg
!= ACC
)
1564 if (opP
->reg
!= ACC
&& opP
->reg
!= ACC1
1565 && opP
->reg
!= ACC2
&& opP
->reg
!= ACC3
)
1570 if (opP
->mode
!= FPREG
)
1575 if (opP
->reg
!= MACSR
)
1580 if (opP
->reg
!= ACCEXT01
&& opP
->reg
!= ACCEXT23
)
1585 if (opP
->reg
!= MASK
)
1590 if (opP
->mode
!= CONTROL
1597 if (opP
->mode
!= LSH
&& opP
->mode
!= RSH
)
1602 if (opP
->mode
!= CONTROL
1604 || opP
->reg
> last_movec_reg
)
1608 const enum m68k_register
*rp
;
1609 for (rp
= control_regs
; *rp
; rp
++)
1610 if (*rp
== opP
->reg
)
1618 if (opP
->mode
!= IMMED
)
1624 if (opP
->mode
== DREG
1625 || opP
->mode
== AREG
1626 || opP
->mode
== FPREG
)
1635 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1638 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1641 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1649 else if (opP
->mode
== CONTROL
)
1658 opP
->mask
= 1 << 24;
1661 opP
->mask
= 1 << 25;
1664 opP
->mask
= 1 << 26;
1673 else if (opP
->mode
!= REGLST
)
1675 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
1677 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
1682 if (opP
->mode
!= IMMED
)
1684 else if (opP
->disp
.exp
.X_op
!= O_constant
1685 || ! issbyte (opP
->disp
.exp
.X_add_number
))
1687 else if (! m68k_quick
1688 && instring
[3] != 'q'
1689 && instring
[4] != 'q')
1694 if (opP
->mode
!= DREG
1695 && opP
->mode
!= IMMED
1696 && opP
->mode
!= ABSL
)
1701 if (opP
->mode
!= IMMED
)
1703 else if (opP
->disp
.exp
.X_op
!= O_constant
1704 || opP
->disp
.exp
.X_add_number
< 1
1705 || opP
->disp
.exp
.X_add_number
> 8)
1707 else if (! m68k_quick
1708 && (strncmp (instring
, "add", 3) == 0
1709 || strncmp (instring
, "sub", 3) == 0)
1710 && instring
[3] != 'q')
1715 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1720 if (opP
->mode
!= AINDR
1721 && (opP
->mode
!= BASE
1723 && opP
->reg
!= ZADDR0
)
1724 || opP
->disp
.exp
.X_op
!= O_absent
1725 || ((opP
->index
.reg
< DATA0
1726 || opP
->index
.reg
> DATA7
)
1727 && (opP
->index
.reg
< ADDR0
1728 || opP
->index
.reg
> ADDR7
))
1729 || opP
->index
.size
!= SIZE_UNSPEC
1730 || opP
->index
.scale
!= 1))
1735 if (opP
->mode
!= CONTROL
1736 || ! (opP
->reg
== FPI
1738 || opP
->reg
== FPC
))
1743 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
1748 if (opP
->mode
!= IMMED
)
1750 else if (opP
->disp
.exp
.X_op
!= O_constant
1751 || opP
->disp
.exp
.X_add_number
< 0
1752 || opP
->disp
.exp
.X_add_number
> 7)
1757 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
1762 if (opP
->mode
!= IMMED
)
1764 else if (opP
->disp
.exp
.X_op
!= O_constant
1765 || opP
->disp
.exp
.X_add_number
< -1
1766 || opP
->disp
.exp
.X_add_number
> 7
1767 || opP
->disp
.exp
.X_add_number
== 0)
1771 /* JF these are out of order. We could put them
1772 in order if we were willing to put up with
1773 bunches of #ifdef m68851s in the code.
1775 Don't forget that you need these operands
1776 to use 68030 MMU instructions. */
1778 /* Memory addressing mode used by pflushr. */
1780 if (opP
->mode
== CONTROL
1781 || opP
->mode
== FPREG
1782 || opP
->mode
== DREG
1783 || opP
->mode
== AREG
1784 || opP
->mode
== REGLST
)
1786 /* We should accept immediate operands, but they
1787 supposedly have to be quad word, and we don't
1788 handle that. I would like to see what a Motorola
1789 assembler does before doing something here. */
1790 if (opP
->mode
== IMMED
)
1795 if (opP
->mode
!= CONTROL
1796 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1801 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
1806 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
1811 if (opP
->mode
!= CONTROL
1814 && opP
->reg
!= SCC
))
1819 if (opP
->mode
!= CONTROL
1825 if (opP
->mode
!= CONTROL
1828 && opP
->reg
!= CRP
))
1852 if (opP
->mode
!= CONTROL
1853 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
1854 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
1859 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
1864 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
1869 if (opP
->mode
!= CONTROL
1878 if (opP
->mode
!= ABSL
)
1883 if (opP
->reg
< DATA0L
|| opP
->reg
> ADDR7U
)
1885 /* FIXME: kludge instead of fixing parser:
1886 upper/lower registers are *not* CONTROL
1887 registers, but ordinary ones. */
1888 if ((opP
->reg
>= DATA0L
&& opP
->reg
<= DATA7L
)
1889 || (opP
->reg
>= DATA0U
&& opP
->reg
<= DATA7U
))
1896 if (!(opP
->mode
== AINDR
1897 || (opP
->mode
== DISP
&& !(opP
->reg
== PC
||
1903 if (!(opP
->mode
== AINDR
|| opP
->mode
== DISP
))
1919 opcode
= opcode
->m_next
;
1924 && !(ok_arch
& current_architecture
))
1929 _("invalid instruction for this architecture; needs "));
1930 cp
= buf
+ strlen (buf
);
1934 strcpy (cp
, _("ColdFire fpu (cfv4e)"));
1937 strcpy (cp
, _("fpu (68040, 68060 or 68881/68882)"));
1940 strcpy (cp
, _("mmu (68030 or 68851)"));
1943 strcpy (cp
, _("68020 or higher"));
1946 strcpy (cp
, _("68000 or higher"));
1949 strcpy (cp
, _("68010 or higher"));
1953 int got_one
= 0, idx
;
1955 idx
< (int) (sizeof (archs
) / sizeof (archs
[0]));
1958 if ((archs
[idx
].arch
& ok_arch
)
1959 && ! archs
[idx
].alias
)
1963 strcpy (cp
, " or ");
1967 strcpy (cp
, archs
[idx
].name
);
1973 cp
= xmalloc (strlen (buf
) + 1);
1978 the_ins
.error
= _("operands mismatch");
1985 /* Now assemble it. */
1986 the_ins
.args
= opcode
->m_operands
;
1987 the_ins
.numargs
= opcode
->m_opnum
;
1988 the_ins
.numo
= opcode
->m_codenum
;
1989 the_ins
.opcode
[0] = getone (opcode
);
1990 the_ins
.opcode
[1] = gettwo (opcode
);
1992 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
1994 /* This switch is a doozy.
1995 Watch the first step; its a big one! */
2028 tmpreg
= 0x3c; /* 7.4 */
2029 if (strchr ("bwl", s
[1]))
2030 nextword
= get_num (&opP
->disp
, 90);
2032 nextword
= get_num (&opP
->disp
, 0);
2033 if (isvar (&opP
->disp
))
2034 add_fix (s
[1], &opP
->disp
, 0, 0);
2038 if (!isbyte (nextword
))
2039 opP
->error
= _("operand out of range");
2044 if (!isword (nextword
))
2045 opP
->error
= _("operand out of range");
2050 if (!issword (nextword
))
2051 opP
->error
= _("operand out of range");
2056 addword (nextword
>> 16);
2083 /* We gotta put out some float. */
2084 if (op (&opP
->disp
) != O_big
)
2089 /* Can other cases happen here? */
2090 if (op (&opP
->disp
) != O_constant
)
2093 val
= (valueT
) offs (&opP
->disp
);
2097 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2098 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2102 offs (&opP
->disp
) = gencnt
;
2104 if (offs (&opP
->disp
) > 0)
2106 if (offs (&opP
->disp
) > baseo
)
2108 as_warn (_("Bignum too big for %c format; truncated"),
2110 offs (&opP
->disp
) = baseo
;
2112 baseo
-= offs (&opP
->disp
);
2115 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
2116 offs (&opP
->disp
)--;
2121 gen_to_words (words
, baseo
, (long) outro
);
2122 for (wordp
= words
; baseo
--; wordp
++)
2126 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2129 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2132 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2135 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2138 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2142 nextword
= get_num (&opP
->disp
, 90);
2145 && ! isvar (&opP
->disp
)
2148 opP
->disp
.exp
.X_op
= O_symbol
;
2149 #ifndef BFD_ASSEMBLER
2150 opP
->disp
.exp
.X_add_symbol
= &abs_symbol
;
2152 opP
->disp
.exp
.X_add_symbol
=
2153 section_symbol (absolute_section
);
2157 /* Force into index mode. Hope this works. */
2159 /* We do the first bit for 32-bit displacements, and the
2160 second bit for 16 bit ones. It is possible that we
2161 should make the default be WORD instead of LONG, but
2162 I think that'd break GCC, so we put up with a little
2163 inefficiency for the sake of working output. */
2165 if (!issword (nextword
)
2166 || (isvar (&opP
->disp
)
2167 && ((opP
->disp
.size
== SIZE_UNSPEC
2168 && flag_short_refs
== 0
2169 && cpu_of_arch (current_architecture
) >= m68020
2170 && ! arch_coldfire_p (current_architecture
))
2171 || opP
->disp
.size
== SIZE_LONG
)))
2173 if (cpu_of_arch (current_architecture
) < m68020
2174 || arch_coldfire_p (current_architecture
))
2176 _("displacement too large for this architecture; needs 68020 or higher");
2178 tmpreg
= 0x3B; /* 7.3 */
2180 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2181 if (isvar (&opP
->disp
))
2185 if (opP
->disp
.size
== SIZE_LONG
2187 /* If the displacement needs pic
2188 relocation it cannot be relaxed. */
2189 || opP
->disp
.pic_reloc
!= pic_none
2194 add_fix ('l', &opP
->disp
, 1, 2);
2198 add_frag (adds (&opP
->disp
),
2200 TAB (PCREL1632
, SZ_UNDEF
));
2207 add_fix ('l', &opP
->disp
, 0, 0);
2212 addword (nextword
>> 16);
2217 tmpreg
= 0x3A; /* 7.2 */
2219 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2221 if (isvar (&opP
->disp
))
2225 add_fix ('w', &opP
->disp
, 1, 0);
2228 add_fix ('w', &opP
->disp
, 0, 0);
2238 baseo
= get_num (&opP
->disp
, 90);
2239 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2240 outro
= get_num (&opP
->odisp
, 90);
2241 /* Figure out the `addressing mode'.
2242 Also turn on the BASE_DISABLE bit, if needed. */
2243 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2245 tmpreg
= 0x3b; /* 7.3 */
2246 if (opP
->reg
== ZPC
)
2249 else if (opP
->reg
== 0)
2252 tmpreg
= 0x30; /* 6.garbage */
2254 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2257 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2260 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2262 siz1
= opP
->disp
.size
;
2263 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2264 siz2
= opP
->odisp
.size
;
2268 /* Index register stuff. */
2269 if (opP
->index
.reg
!= 0
2270 && opP
->index
.reg
>= DATA
2271 && opP
->index
.reg
<= ADDR7
)
2273 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2275 if (opP
->index
.size
== SIZE_LONG
2276 || (opP
->index
.size
== SIZE_UNSPEC
2277 && m68k_index_width_default
== SIZE_LONG
))
2280 if ((opP
->index
.scale
!= 1
2281 && cpu_of_arch (current_architecture
) < m68020
)
2282 || (opP
->index
.scale
== 8
2283 && (arch_coldfire_p (current_architecture
)
2284 && !arch_coldfire_v4e_p(current_architecture
))))
2287 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2290 if (arch_coldfire_p (current_architecture
)
2291 && opP
->index
.size
== SIZE_WORD
)
2292 opP
->error
= _("invalid index size for coldfire");
2294 switch (opP
->index
.scale
)
2311 GET US OUT OF HERE! */
2313 /* Must be INDEX, with an index register. Address
2314 register cannot be ZERO-PC, and either :b was
2315 forced, or we know it will fit. For a 68000 or
2316 68010, force this mode anyways, because the
2317 larger modes aren't supported. */
2318 if (opP
->mode
== BASE
2319 && ((opP
->reg
>= ADDR0
2320 && opP
->reg
<= ADDR7
)
2323 if (siz1
== SIZE_BYTE
2324 || cpu_of_arch (current_architecture
) < m68020
2325 || arch_coldfire_p (current_architecture
)
2326 || (siz1
== SIZE_UNSPEC
2327 && ! isvar (&opP
->disp
)
2328 && issbyte (baseo
)))
2330 nextword
+= baseo
& 0xff;
2332 if (isvar (&opP
->disp
))
2334 /* Do a byte relocation. If it doesn't
2335 fit (possible on m68000) let the
2336 fixup processing complain later. */
2338 add_fix ('B', &opP
->disp
, 1, 1);
2340 add_fix ('B', &opP
->disp
, 0, 0);
2342 else if (siz1
!= SIZE_BYTE
)
2344 if (siz1
!= SIZE_UNSPEC
)
2345 as_warn (_("Forcing byte displacement"));
2346 if (! issbyte (baseo
))
2347 opP
->error
= _("byte displacement out of range");
2352 else if (siz1
== SIZE_UNSPEC
2354 && isvar (&opP
->disp
)
2355 && subs (&opP
->disp
) == NULL
2357 /* If the displacement needs pic
2358 relocation it cannot be relaxed. */
2359 && opP
->disp
.pic_reloc
== pic_none
2363 /* The code in md_convert_frag_1 needs to be
2364 able to adjust nextword. Call frag_grow
2365 to ensure that we have enough space in
2366 the frag obstack to make all the bytes
2369 nextword
+= baseo
& 0xff;
2371 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2372 TAB (PCINDEX
, SZ_UNDEF
));
2380 nextword
|= 0x40; /* No index reg. */
2381 if (opP
->index
.reg
>= ZDATA0
2382 && opP
->index
.reg
<= ZDATA7
)
2383 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2384 else if (opP
->index
.reg
>= ZADDR0
2385 || opP
->index
.reg
<= ZADDR7
)
2386 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2389 /* It isn't simple. */
2391 if (cpu_of_arch (current_architecture
) < m68020
2392 || arch_coldfire_p (current_architecture
))
2394 _("invalid operand mode for this architecture; needs 68020 or higher");
2397 /* If the guy specified a width, we assume that it is
2398 wide enough. Maybe it isn't. If so, we lose. */
2402 if (isvar (&opP
->disp
)
2404 : ! issword (baseo
))
2409 else if (! isvar (&opP
->disp
) && baseo
== 0)
2418 as_warn (_(":b not permitted; defaulting to :w"));
2428 /* Figure out inner displacement stuff. */
2429 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2431 if (cpu_of_arch (current_architecture
) & cpu32
)
2432 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2436 if (isvar (&opP
->odisp
)
2438 : ! issword (outro
))
2443 else if (! isvar (&opP
->odisp
) && outro
== 0)
2452 as_warn (_(":b not permitted; defaulting to :w"));
2461 if (opP
->mode
== POST
2462 && (nextword
& 0x40) == 0)
2467 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2469 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2470 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2472 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2474 if (siz1
== SIZE_LONG
)
2475 addword (baseo
>> 16);
2476 if (siz1
!= SIZE_UNSPEC
)
2479 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2480 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2481 if (siz2
== SIZE_LONG
)
2482 addword (outro
>> 16);
2483 if (siz2
!= SIZE_UNSPEC
)
2489 nextword
= get_num (&opP
->disp
, 90);
2490 switch (opP
->disp
.size
)
2495 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2497 tmpreg
= 0x38; /* 7.0 */
2501 if (isvar (&opP
->disp
)
2502 && !subs (&opP
->disp
)
2503 && adds (&opP
->disp
)
2505 /* If the displacement needs pic relocation it
2506 cannot be relaxed. */
2507 && opP
->disp
.pic_reloc
== pic_none
2510 && !strchr ("~%&$?", s
[0]))
2512 tmpreg
= 0x3A; /* 7.2 */
2513 add_frag (adds (&opP
->disp
),
2515 TAB (ABSTOPCREL
, SZ_UNDEF
));
2518 /* Fall through into long. */
2520 if (isvar (&opP
->disp
))
2521 add_fix ('l', &opP
->disp
, 0, 0);
2523 tmpreg
= 0x39;/* 7.1 mode */
2524 addword (nextword
>> 16);
2529 as_bad (_("unsupported byte value; use a different suffix"));
2533 if (isvar (&opP
->disp
))
2534 add_fix ('w', &opP
->disp
, 0, 0);
2536 tmpreg
= 0x38;/* 7.0 mode */
2544 as_bad (_("unknown/incorrect operand"));
2548 /* If s[0] is '4', then this is for the mac instructions
2549 that can have a trailing_ampersand set. If so, set 0x100
2550 bit on tmpreg so install_gen_operand can check for it and
2551 set the appropriate bit (word2, bit 5). */
2554 if (opP
->trailing_ampersand
)
2557 install_gen_operand (s
[1], tmpreg
);
2563 { /* JF: I hate floating point! */
2578 tmpreg
= get_num (&opP
->disp
, tmpreg
);
2579 if (isvar (&opP
->disp
))
2580 add_fix (s
[1], &opP
->disp
, 0, 0);
2583 case 'b': /* Danger: These do no check for
2584 certain types of overflow.
2586 if (!isbyte (tmpreg
))
2587 opP
->error
= _("out of range");
2588 insop (tmpreg
, opcode
);
2589 if (isvar (&opP
->disp
))
2590 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
2591 (opcode
->m_codenum
) * 2 + 1;
2594 if (!issbyte (tmpreg
))
2595 opP
->error
= _("out of range");
2596 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
2597 if (isvar (&opP
->disp
))
2598 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
2601 if (!isword (tmpreg
))
2602 opP
->error
= _("out of range");
2603 insop (tmpreg
, opcode
);
2604 if (isvar (&opP
->disp
))
2605 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2608 if (!issword (tmpreg
))
2609 opP
->error
= _("out of range");
2610 insop (tmpreg
, opcode
);
2611 if (isvar (&opP
->disp
))
2612 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2615 /* Because of the way insop works, we put these two out
2617 insop (tmpreg
, opcode
);
2618 insop (tmpreg
>> 16, opcode
);
2619 if (isvar (&opP
->disp
))
2620 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2627 install_operand (s
[1], tmpreg
);
2638 install_operand (s
[1], opP
->reg
- ADDR
);
2642 tmpreg
= get_num (&opP
->disp
, 90);
2646 add_fix ('B', &opP
->disp
, 1, -1);
2649 add_fix ('w', &opP
->disp
, 1, 0);
2654 if (! HAVE_LONG_BRANCH (current_architecture
))
2655 as_warn (_("Can't use long branches on 68000/68010/5200"));
2656 the_ins
.opcode
[0] |= 0xff;
2657 add_fix ('l', &opP
->disp
, 1, 0);
2662 if (subs (&opP
->disp
)) /* We can't relax it. */
2666 /* If the displacement needs pic relocation it cannot be
2668 if (opP
->disp
.pic_reloc
!= pic_none
)
2671 /* This could either be a symbol, or an absolute
2672 address. If it's an absolute address, turn it into
2673 an absolute jump right here and keep it out of the
2675 if (adds (&opP
->disp
) == 0)
2677 if (the_ins
.opcode
[0] == 0x6000) /* jbra */
2678 the_ins
.opcode
[0] = 0x4EF9;
2679 else if (the_ins
.opcode
[0] == 0x6100) /* jbsr */
2680 the_ins
.opcode
[0] = 0x4EB9;
2683 the_ins
.opcode
[0] ^= 0x0100;
2684 the_ins
.opcode
[0] |= 0x0006;
2687 add_fix ('l', &opP
->disp
, 0, 0);
2693 /* Now we know it's going into the relaxer. Now figure
2694 out which mode. We try in this order of preference:
2695 long branch, absolute jump, byte/word branches only. */
2696 if (HAVE_LONG_BRANCH (current_architecture
))
2697 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2698 TAB (BRANCHBWL
, SZ_UNDEF
));
2699 else if (! flag_keep_pcrel
)
2701 if ((the_ins
.opcode
[0] == 0x6000)
2702 || (the_ins
.opcode
[0] == 0x6100))
2703 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2704 TAB (BRABSJUNC
, SZ_UNDEF
));
2706 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2707 TAB (BRABSJCOND
, SZ_UNDEF
));
2710 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2711 TAB (BRANCHBW
, SZ_UNDEF
));
2714 if (isvar (&opP
->disp
))
2716 /* Check for DBcc instructions. We can relax them,
2717 but only if we have long branches and/or absolute
2719 if (((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2720 && (HAVE_LONG_BRANCH (current_architecture
)
2721 || (! flag_keep_pcrel
)))
2723 if (HAVE_LONG_BRANCH (current_architecture
))
2724 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2725 TAB (DBCCLBR
, SZ_UNDEF
));
2727 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2728 TAB (DBCCABSJ
, SZ_UNDEF
));
2731 add_fix ('w', &opP
->disp
, 1, 0);
2735 case 'C': /* Fixed size LONG coproc branches. */
2736 add_fix ('l', &opP
->disp
, 1, 0);
2740 case 'c': /* Var size Coprocesssor branches. */
2741 if (subs (&opP
->disp
) || (adds (&opP
->disp
) == 0))
2743 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2744 add_fix ('l', &opP
->disp
, 1, 0);
2749 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2750 TAB (FBRANCH
, SZ_UNDEF
));
2757 case 'C': /* Ignore it. */
2760 case 'd': /* JF this is a kludge. */
2761 install_operand ('s', opP
->reg
- ADDR
);
2762 tmpreg
= get_num (&opP
->disp
, 90);
2763 if (!issword (tmpreg
))
2765 as_warn (_("Expression out of range, using 0"));
2772 install_operand (s
[1], opP
->reg
- DATA
);
2775 case 'e': /* EMAC ACCx, reg/reg. */
2776 install_operand (s
[1], opP
->reg
- ACC
);
2779 case 'E': /* Ignore it. */
2783 install_operand (s
[1], opP
->reg
- FP0
);
2786 case 'g': /* EMAC ACCEXTx. */
2787 install_operand (s
[1], opP
->reg
- ACCEXT01
);
2790 case 'G': /* Ignore it. */
2795 tmpreg
= opP
->reg
- COP0
;
2796 install_operand (s
[1], tmpreg
);
2799 case 'i': /* MAC/EMAC scale factor. */
2800 install_operand (s
[1], opP
->mode
== LSH
? 0x1 : 0x3);
2803 case 'J': /* JF foo. */
2932 install_operand (s
[1], tmpreg
);
2936 tmpreg
= get_num (&opP
->disp
, 55);
2937 install_operand (s
[1], tmpreg
& 0x7f);
2944 if (tmpreg
& 0x7FF0000)
2945 as_bad (_("Floating point register in register list"));
2946 insop (reverse_16_bits (tmpreg
), opcode
);
2950 if (tmpreg
& 0x700FFFF)
2951 as_bad (_("Wrong register in floating-point reglist"));
2952 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
2960 if (tmpreg
& 0x7FF0000)
2961 as_bad (_("Floating point register in register list"));
2962 insop (tmpreg
, opcode
);
2964 else if (s
[1] == '8')
2966 if (tmpreg
& 0x0FFFFFF)
2967 as_bad (_("incorrect register in reglist"));
2968 install_operand (s
[1], tmpreg
>> 24);
2972 if (tmpreg
& 0x700FFFF)
2973 as_bad (_("wrong register in floating-point reglist"));
2975 install_operand (s
[1], tmpreg
>> 16);
2980 install_operand (s
[1], get_num (&opP
->disp
, 60));
2984 tmpreg
= ((opP
->mode
== DREG
)
2985 ? 0x20 + (int) (opP
->reg
- DATA
)
2986 : (get_num (&opP
->disp
, 40) & 0x1F));
2987 install_operand (s
[1], tmpreg
);
2991 tmpreg
= get_num (&opP
->disp
, 10);
2994 install_operand (s
[1], tmpreg
);
2998 /* This depends on the fact that ADDR registers are eight
2999 more than their corresponding DATA regs, so the result
3000 will have the ADDR_REG bit set. */
3001 install_operand (s
[1], opP
->reg
- DATA
);
3005 if (opP
->mode
== AINDR
)
3006 install_operand (s
[1], opP
->reg
- DATA
);
3008 install_operand (s
[1], opP
->index
.reg
- DATA
);
3012 if (opP
->reg
== FPI
)
3014 else if (opP
->reg
== FPS
)
3016 else if (opP
->reg
== FPC
)
3020 install_operand (s
[1], tmpreg
);
3023 case 'S': /* Ignore it. */
3027 install_operand (s
[1], get_num (&opP
->disp
, 30));
3030 case 'U': /* Ignore it. */
3049 as_fatal (_("failed sanity check"));
3050 } /* switch on cache token. */
3051 install_operand (s
[1], tmpreg
);
3054 /* JF: These are out of order, I fear. */
3067 install_operand (s
[1], tmpreg
);
3093 install_operand (s
[1], tmpreg
);
3097 if (opP
->reg
== VAL
)
3116 install_operand (s
[1], tmpreg
);
3130 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3141 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3147 install_operand (s
[1], tmpreg
);
3150 know (opP
->reg
== PSR
);
3153 know (opP
->reg
== PCSR
);
3168 install_operand (s
[1], tmpreg
);
3171 tmpreg
= get_num (&opP
->disp
, 20);
3172 install_operand (s
[1], tmpreg
);
3174 case '_': /* used only for move16 absolute 32-bit address. */
3175 if (isvar (&opP
->disp
))
3176 add_fix ('l', &opP
->disp
, 0, 0);
3177 tmpreg
= get_num (&opP
->disp
, 90);
3178 addword (tmpreg
>> 16);
3179 addword (tmpreg
& 0xFFFF);
3182 install_operand (s
[1], opP
->reg
- DATA0L
);
3183 opP
->reg
-= (DATA0L
);
3184 opP
->reg
&= 0x0F; /* remove upper/lower bit. */
3187 tmpreg
= get_num (&opP
->disp
, 80);
3190 install_operand (s
[1], tmpreg
);
3197 /* By the time whe get here (FINALLY) the_ins contains the complete
3198 instruction, ready to be emitted. . . */
3202 reverse_16_bits (in
)
3208 static int mask
[16] =
3210 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3211 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3213 for (n
= 0; n
< 16; n
++)
3216 out
|= mask
[15 - n
];
3219 } /* reverse_16_bits() */
3228 static int mask
[8] =
3230 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3233 for (n
= 0; n
< 8; n
++)
3239 } /* reverse_8_bits() */
3241 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3242 (that value is chosen in the frag_var call in md_assemble). TYPE
3243 is the subtype of the frag to be generated; its primary type is
3244 rs_machine_dependent.
3246 The TYPE parameter is also used by md_convert_frag_1 and
3247 md_estimate_size_before_relax. The appropriate type of fixup will
3248 be emitted by md_convert_frag_1.
3250 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3252 install_operand (mode
, val
)
3259 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge. */
3262 the_ins
.opcode
[0] |= val
<< 9;
3265 the_ins
.opcode
[1] |= val
<< 12;
3268 the_ins
.opcode
[1] |= val
<< 6;
3271 the_ins
.opcode
[1] |= val
;
3274 the_ins
.opcode
[2] |= val
<< 12;
3277 the_ins
.opcode
[2] |= val
<< 6;
3280 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3281 three words long! */
3283 the_ins
.opcode
[2] |= val
;
3286 the_ins
.opcode
[1] |= val
<< 7;
3289 the_ins
.opcode
[1] |= val
<< 10;
3293 the_ins
.opcode
[1] |= val
<< 5;
3298 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3301 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3304 the_ins
.opcode
[0] |= val
= 0xff;
3307 the_ins
.opcode
[0] |= val
<< 9;
3310 the_ins
.opcode
[1] |= val
;
3313 the_ins
.opcode
[1] |= val
;
3314 the_ins
.numo
++; /* What a hack. */
3317 the_ins
.opcode
[1] |= val
<< 4;
3325 the_ins
.opcode
[0] |= (val
<< 6);
3328 the_ins
.opcode
[1] = (val
>> 16);
3329 the_ins
.opcode
[2] = val
& 0xffff;
3332 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3333 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3334 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3336 case 'n': /* MAC/EMAC Rx on !load. */
3337 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3338 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3339 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3341 case 'o': /* MAC/EMAC Rx on load. */
3342 the_ins
.opcode
[1] |= val
<< 12;
3343 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3345 case 'M': /* MAC/EMAC Ry on !load. */
3346 the_ins
.opcode
[0] |= (val
& 0xF);
3347 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3349 case 'N': /* MAC/EMAC Ry on load. */
3350 the_ins
.opcode
[1] |= (val
& 0xF);
3351 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3354 the_ins
.opcode
[1] |= ((val
!= 1) << 10);
3357 the_ins
.opcode
[0] |= ((val
& 0x3) << 9);
3360 the_ins
.opcode
[0] |= ((val
& 0x3) << 0);
3363 the_ins
.opcode
[0] |= ((~val
& 0x1) << 7);
3364 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3367 the_ins
.opcode
[0] |= ((val
& 0x1) << 7);
3368 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3371 the_ins
.opcode
[1] |= ((val
& 0x3) << 9);
3374 the_ins
.opcode
[0] |= (val
& 0x1) <<10;
3378 as_fatal (_("failed sanity check."));
3380 } /* install_operand() */
3383 install_gen_operand (mode
, val
)
3389 case '/': /* Special for mask loads for mac/msac insns with
3390 possible mask; trailing_ampersend set in bit 8. */
3391 the_ins
.opcode
[0] |= (val
& 0x3f);
3392 the_ins
.opcode
[1] |= (((val
& 0x100) >> 8) << 5);
3395 the_ins
.opcode
[0] |= val
;
3398 /* This is a kludge!!! */
3399 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3408 the_ins
.opcode
[0] |= val
;
3410 /* more stuff goes here. */
3412 as_fatal (_("failed sanity check."));
3414 } /* install_gen_operand() */
3417 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3418 * then deal with the bitfield hack.
3422 crack_operand (str
, opP
)
3424 register struct m68k_op
*opP
;
3426 register int parens
;
3428 register char *beg_str
;
3436 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3442 else if (*str
== ')')
3446 opP
->error
= _("Extra )");
3452 if (flag_mri
&& *str
== '\'')
3453 inquote
= ! inquote
;
3455 if (!*str
&& parens
)
3457 opP
->error
= _("Missing )");
3462 if (m68k_ip_op (beg_str
, opP
) != 0)
3469 c
= *++str
; /* JF bitfield hack. */
3474 as_bad (_("Missing operand"));
3477 /* Detect MRI REG symbols and convert them to REGLSTs. */
3478 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
3481 opP
->mask
= ~(int)opP
->reg
;
3488 /* This is the guts of the machine-dependent assembler. STR points to a
3489 machine dependent instruction. This function is supposed to emit
3490 the frags/bytes it assembles to.
3494 insert_reg (regname
, regnum
)
3495 const char *regname
;
3501 #ifdef REGISTER_PREFIX
3502 if (!flag_reg_prefix_optional
)
3504 buf
[0] = REGISTER_PREFIX
;
3505 strcpy (buf
+ 1, regname
);
3510 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
3511 &zero_address_frag
));
3513 for (i
= 0; regname
[i
]; i
++)
3514 buf
[i
] = TOUPPER (regname
[i
]);
3517 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
3518 &zero_address_frag
));
3527 static const struct init_entry init_table
[] =
3587 { "accext01", ACCEXT01
},
3588 { "accext23", ACCEXT23
},
3592 /* Control registers. */
3593 { "sfc", SFC
}, /* Source Function Code. */
3595 { "dfc", DFC
}, /* Destination Function Code. */
3597 { "cacr", CACR
}, /* Cache Control Register. */
3598 { "caar", CAAR
}, /* Cache Address Register. */
3600 { "usp", USP
}, /* User Stack Pointer. */
3601 { "vbr", VBR
}, /* Vector Base Register. */
3602 { "msp", MSP
}, /* Master Stack Pointer. */
3603 { "isp", ISP
}, /* Interrupt Stack Pointer. */
3605 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0. */
3606 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1. */
3607 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0. */
3608 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1. */
3610 /* 68ec040 versions of same */
3611 { "iacr0", ITT0
}, /* Instruction Access Control Register 0. */
3612 { "iacr1", ITT1
}, /* Instruction Access Control Register 0. */
3613 { "dacr0", DTT0
}, /* Data Access Control Register 0. */
3614 { "dacr1", DTT1
}, /* Data Access Control Register 0. */
3616 /* mcf5200 versions of same. The ColdFire programmer's reference
3617 manual indicated that the order is 2,3,0,1, but Ken Rose
3618 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3619 { "acr0", ACR0
}, /* Access Control Unit 0. */
3620 { "acr1", ACR1
}, /* Access Control Unit 1. */
3621 { "acr2", ACR2
}, /* Access Control Unit 2. */
3622 { "acr3", ACR3
}, /* Access Control Unit 3. */
3624 { "tc", TC
}, /* MMU Translation Control Register. */
3627 { "mmusr", MMUSR
}, /* MMU Status Register. */
3628 { "srp", SRP
}, /* User Root Pointer. */
3629 { "urp", URP
}, /* Supervisor Root Pointer. */
3634 { "rombar", ROMBAR
}, /* ROM Base Address Register. */
3635 { "rambar0", RAMBAR0
}, /* ROM Base Address Register. */
3636 { "rambar1", RAMBAR1
}, /* ROM Base Address Register. */
3637 { "mbar", MBAR
}, /* Module Base Address Register. */
3639 { "mbar0", MBAR0
}, /* mcfv4e registers. */
3640 { "mbar1", MBAR1
}, /* mcfv4e registers. */
3641 { "rombar0", ROMBAR
}, /* mcfv4e registers. */
3642 { "rombar1", ROMBAR1
}, /* mcfv4e registers. */
3643 { "mpcr", MPCR
}, /* mcfv4e registers. */
3644 { "edrambar", EDRAMBAR
}, /* mcfv4e registers. */
3645 { "secmbar", SECMBAR
}, /* mcfv4e registers. */
3646 { "asid", TC
}, /* mcfv4e registers. */
3647 { "mmubar", BUSCR
}, /* mcfv4e registers. */
3648 { "pcr1u0", PCR1U0
}, /* mcfv4e registers. */
3649 { "pcr1l0", PCR1L0
}, /* mcfv4e registers. */
3650 { "pcr2u0", PCR2U0
}, /* mcfv4e registers. */
3651 { "pcr2l0", PCR2L0
}, /* mcfv4e registers. */
3652 { "pcr3u0", PCR3U0
}, /* mcfv4e registers. */
3653 { "pcr3l0", PCR3L0
}, /* mcfv4e registers. */
3654 { "pcr1u1", PCR1U1
}, /* mcfv4e registers. */
3655 { "pcr1l1", PCR1L1
}, /* mcfv4e registers. */
3656 { "pcr2u1", PCR2U1
}, /* mcfv4e registers. */
3657 { "pcr2l1", PCR2L1
}, /* mcfv4e registers. */
3658 { "pcr3u1", PCR3U1
}, /* mcfv4e registers. */
3659 { "pcr3l1", PCR3L1
}, /* mcfv4e registers. */
3661 { "flashbar", FLASHBAR
}, /* mcf528x registers. */
3662 { "rambar", RAMBAR
}, /* mcf528x registers. */
3663 /* End of control registers. */
3697 /* 68ec030 versions of same. */
3700 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3703 /* Suppressed data and address registers. */
3721 /* Upper and lower data and address registers, used by macw and msacw. */
3765 for (i
= 0; init_table
[i
].name
; i
++)
3766 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
3769 static int no_68851
, no_68881
;
3772 /* a.out machine type. Default to 68020. */
3773 int m68k_aout_machtype
= 2;
3785 int shorts_this_frag
;
3788 /* In MRI mode, the instruction and operands are separated by a
3789 space. Anything following the operands is a comment. The label
3790 has already been removed. */
3798 for (s
= str
; *s
!= '\0'; s
++)
3800 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
3818 inquote
= ! inquote
;
3823 memset ((char *) (&the_ins
), '\0', sizeof (the_ins
));
3828 for (n
= 0; n
< the_ins
.numargs
; n
++)
3829 if (the_ins
.operands
[n
].error
)
3831 er
= the_ins
.operands
[n
].error
;
3837 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
3841 /* If there is a current label, record that it marks an instruction. */
3842 if (current_label
!= NULL
)
3844 current_label
->text
= 1;
3845 current_label
= NULL
;
3849 /* Tie dwarf2 debug info to the address at the start of the insn. */
3850 dwarf2_emit_insn (0);
3853 if (the_ins
.nfrag
== 0)
3855 /* No frag hacking involved; just put it out. */
3856 toP
= frag_more (2 * the_ins
.numo
);
3857 fromP
= &the_ins
.opcode
[0];
3858 for (m
= the_ins
.numo
; m
; --m
)
3860 md_number_to_chars (toP
, (long) (*fromP
), 2);
3864 /* Put out symbol-dependent info. */
3865 for (m
= 0; m
< the_ins
.nrel
; m
++)
3867 switch (the_ins
.reloc
[m
].wid
)
3886 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3887 the_ins
.reloc
[m
].wid
);
3890 fixP
= fix_new_exp (frag_now
,
3891 ((toP
- frag_now
->fr_literal
)
3892 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3894 &the_ins
.reloc
[m
].exp
,
3895 the_ins
.reloc
[m
].pcrel
,
3896 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
3897 the_ins
.reloc
[m
].pic_reloc
));
3898 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3899 if (the_ins
.reloc
[m
].wid
== 'B')
3900 fixP
->fx_signed
= 1;
3905 /* There's some frag hacking. */
3907 /* Calculate the max frag size. */
3910 wid
= 2 * the_ins
.fragb
[0].fragoff
;
3911 for (n
= 1; n
< the_ins
.nfrag
; n
++)
3912 wid
+= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3913 /* frag_var part. */
3915 /* Make sure the whole insn fits in one chunk, in particular that
3916 the var part is attached, as we access one byte before the
3917 variable frag for byte branches. */
3921 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
3926 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
3928 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3929 toP
= frag_more (wid
);
3931 shorts_this_frag
= 0;
3932 for (m
= wid
/ 2; m
; --m
)
3934 md_number_to_chars (toP
, (long) (*fromP
), 2);
3939 for (m
= 0; m
< the_ins
.nrel
; m
++)
3941 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
3943 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
3946 wid
= the_ins
.reloc
[m
].wid
;
3949 the_ins
.reloc
[m
].wid
= 0;
3950 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3952 fixP
= fix_new_exp (frag_now
,
3953 ((toP
- frag_now
->fr_literal
)
3954 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3956 &the_ins
.reloc
[m
].exp
,
3957 the_ins
.reloc
[m
].pcrel
,
3958 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
3959 the_ins
.reloc
[m
].pic_reloc
));
3960 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3962 (void) frag_var (rs_machine_dependent
, 10, 0,
3963 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
3964 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
3966 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3967 shorts_this_frag
= 0;
3970 toP
= frag_more (n
* sizeof (short));
3973 md_number_to_chars (toP
, (long) (*fromP
), 2);
3979 for (m
= 0; m
< the_ins
.nrel
; m
++)
3983 wid
= the_ins
.reloc
[m
].wid
;
3986 the_ins
.reloc
[m
].wid
= 0;
3987 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3989 fixP
= fix_new_exp (frag_now
,
3990 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
3991 - shorts_this_frag
* 2),
3993 &the_ins
.reloc
[m
].exp
,
3994 the_ins
.reloc
[m
].pcrel
,
3995 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
3996 the_ins
.reloc
[m
].pic_reloc
));
3997 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4005 * md_begin -- set up hash tables with 68000 instructions.
4006 * similar to what the vax assembler does. ---phr
4008 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4009 a copy of it at runtime, adding in the information we want but isn't
4010 there. I think it'd be better to have an awk script hack the table
4011 at compile time. Or even just xstr the table and use it as-is. But
4012 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4015 const struct m68k_opcode
*ins
;
4016 struct m68k_incant
*hack
, *slak
;
4017 const char *retval
= 0; /* Empty string, or error msg text. */
4022 flag_reg_prefix_optional
= 1;
4024 if (! m68k_rel32_from_cmdline
)
4028 op_hash
= hash_new ();
4030 obstack_begin (&robyn
, 4000);
4031 for (i
= 0; i
< m68k_numopcodes
; i
++)
4033 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4036 ins
= &m68k_opcodes
[i
];
4037 /* We *could* ignore insns that don't match our arch here
4038 but just leaving them out of the hash. */
4039 slak
->m_operands
= ins
->args
;
4040 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
4041 slak
->m_arch
= ins
->arch
;
4042 slak
->m_opcode
= ins
->opcode
;
4043 /* This is kludgey. */
4044 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
4045 if (i
+ 1 != m68k_numopcodes
4046 && !strcmp (ins
->name
, m68k_opcodes
[i
+ 1].name
))
4048 slak
->m_next
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4053 slak
= slak
->m_next
;
4057 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
4059 as_fatal (_("Internal Error: Can't hash %s: %s"), ins
->name
, retval
);
4062 for (i
= 0; i
< m68k_numaliases
; i
++)
4064 const char *name
= m68k_opcode_aliases
[i
].primary
;
4065 const char *alias
= m68k_opcode_aliases
[i
].alias
;
4066 PTR val
= hash_find (op_hash
, name
);
4068 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4069 retval
= hash_insert (op_hash
, alias
, val
);
4071 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4074 /* In MRI mode, all unsized branches are variable sized. Normally,
4075 they are word sized. */
4078 static struct m68k_opcode_alias mri_aliases
[] =
4099 i
< (int) (sizeof mri_aliases
/ sizeof mri_aliases
[0]);
4102 const char *name
= mri_aliases
[i
].primary
;
4103 const char *alias
= mri_aliases
[i
].alias
;
4104 PTR val
= hash_find (op_hash
, name
);
4106 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4107 retval
= hash_jam (op_hash
, alias
, val
);
4109 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4113 for (i
= 0; i
< (int) sizeof (notend_table
); i
++)
4115 notend_table
[i
] = 0;
4116 alt_notend_table
[i
] = 0;
4118 notend_table
[','] = 1;
4119 notend_table
['{'] = 1;
4120 notend_table
['}'] = 1;
4121 alt_notend_table
['a'] = 1;
4122 alt_notend_table
['A'] = 1;
4123 alt_notend_table
['d'] = 1;
4124 alt_notend_table
['D'] = 1;
4125 alt_notend_table
['#'] = 1;
4126 alt_notend_table
['&'] = 1;
4127 alt_notend_table
['f'] = 1;
4128 alt_notend_table
['F'] = 1;
4129 #ifdef REGISTER_PREFIX
4130 alt_notend_table
[REGISTER_PREFIX
] = 1;
4133 /* We need to put '(' in alt_notend_table to handle
4134 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
4136 alt_notend_table
['('] = 1;
4138 /* We need to put '@' in alt_notend_table to handle
4139 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
4141 alt_notend_table
['@'] = 1;
4143 /* We need to put digits in alt_notend_table to handle
4144 bfextu %d0{24:1},%d0
4146 alt_notend_table
['0'] = 1;
4147 alt_notend_table
['1'] = 1;
4148 alt_notend_table
['2'] = 1;
4149 alt_notend_table
['3'] = 1;
4150 alt_notend_table
['4'] = 1;
4151 alt_notend_table
['5'] = 1;
4152 alt_notend_table
['6'] = 1;
4153 alt_notend_table
['7'] = 1;
4154 alt_notend_table
['8'] = 1;
4155 alt_notend_table
['9'] = 1;
4157 #ifndef MIT_SYNTAX_ONLY
4158 /* Insert pseudo ops, these have to go into the opcode table since
4159 gas expects pseudo ops to start with a dot. */
4162 while (mote_pseudo_table
[n
].poc_name
)
4164 hack
= (struct m68k_incant
*)
4165 obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4166 hash_insert (op_hash
,
4167 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
4168 hack
->m_operands
= 0;
4178 record_alignment (text_section
, 2);
4179 record_alignment (data_section
, 2);
4180 record_alignment (bss_section
, 2);
4185 select_control_regs ()
4187 /* Note which set of "movec" control registers is available. */
4188 switch (cpu_of_arch (current_architecture
))
4191 as_warn (_("architecture not yet selected: defaulting to 68020"));
4192 control_regs
= m68020_control_regs
;
4196 control_regs
= m68000_control_regs
;
4199 control_regs
= m68010_control_regs
;
4203 control_regs
= m68020_control_regs
;
4206 control_regs
= m68040_control_regs
;
4209 control_regs
= m68060_control_regs
;
4212 control_regs
= cpu32_control_regs
;
4218 control_regs
= mcf_control_regs
;
4221 control_regs
= mcf528x_control_regs
;
4224 control_regs
= mcfv4e_control_regs
;
4232 m68k_init_after_args ()
4234 if (cpu_of_arch (current_architecture
) == 0)
4237 const char *default_cpu
= TARGET_CPU
;
4239 if (*default_cpu
== 'm')
4241 for (i
= 0; i
< n_archs
; i
++)
4242 if (strcasecmp (default_cpu
, archs
[i
].name
) == 0)
4246 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU
);
4247 current_architecture
|= m68020
;
4250 current_architecture
|= archs
[i
].arch
;
4252 /* Permit m68881 specification with all cpus; those that can't work
4253 with a coprocessor could be doing emulation. */
4254 if (current_architecture
& m68851
)
4256 if (current_architecture
& m68040
)
4258 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4261 /* What other incompatibilities could we check for? */
4263 /* Toss in some default assumptions about coprocessors. */
4265 && (cpu_of_arch (current_architecture
)
4266 /* Can CPU32 have a 68881 coprocessor?? */
4267 & (m68020
| m68030
| cpu32
)))
4269 current_architecture
|= m68881
;
4272 && (cpu_of_arch (current_architecture
) & m68020up
) != 0
4273 && (cpu_of_arch (current_architecture
) & m68040up
) == 0)
4275 current_architecture
|= m68851
;
4277 if (no_68881
&& (current_architecture
& m68881
))
4278 as_bad (_("options for 68881 and no-68881 both given"));
4279 if (no_68851
&& (current_architecture
& m68851
))
4280 as_bad (_("options for 68851 and no-68851 both given"));
4283 /* Work out the magic number. This isn't very general. */
4284 if (current_architecture
& m68000
)
4285 m68k_aout_machtype
= 0;
4286 else if (current_architecture
& m68010
)
4287 m68k_aout_machtype
= 1;
4288 else if (current_architecture
& m68020
)
4289 m68k_aout_machtype
= 2;
4291 m68k_aout_machtype
= 2;
4294 /* Note which set of "movec" control registers is available. */
4295 select_control_regs ();
4297 if (cpu_of_arch (current_architecture
) < m68020
4298 || arch_coldfire_p (current_architecture
))
4299 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
4302 /* This is called when a label is defined. */
4305 m68k_frob_label (sym
)
4308 struct label_line
*n
;
4310 n
= (struct label_line
*) xmalloc (sizeof *n
);
4313 as_where (&n
->file
, &n
->line
);
4319 /* This is called when a value that is not an instruction is emitted. */
4322 m68k_flush_pending_output ()
4324 current_label
= NULL
;
4327 /* This is called at the end of the assembly, when the final value of
4328 the label is known. We warn if this is a text symbol aligned at an
4332 m68k_frob_symbol (sym
)
4335 if (S_GET_SEGMENT (sym
) == reg_section
4336 && (int) S_GET_VALUE (sym
) < 0)
4338 S_SET_SEGMENT (sym
, absolute_section
);
4339 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
4341 else if ((S_GET_VALUE (sym
) & 1) != 0)
4343 struct label_line
*l
;
4345 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4347 if (l
->label
== sym
)
4350 as_warn_where (l
->file
, l
->line
,
4351 _("text label `%s' aligned to odd boundary"),
4359 /* This is called if we go in or out of MRI mode because of the .mri
4363 m68k_mri_mode_change (on
)
4368 if (! flag_reg_prefix_optional
)
4370 flag_reg_prefix_optional
= 1;
4371 #ifdef REGISTER_PREFIX
4376 if (! m68k_rel32_from_cmdline
)
4381 if (! reg_prefix_optional_seen
)
4383 #ifdef REGISTER_PREFIX_OPTIONAL
4384 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
4386 flag_reg_prefix_optional
= 0;
4388 #ifdef REGISTER_PREFIX
4393 if (! m68k_rel32_from_cmdline
)
4398 /* Equal to MAX_PRECISION in atof-ieee.c. */
4399 #define MAX_LITTLENUMS 6
4401 /* Turn a string in input_line_pointer into a floating point constant
4402 of type TYPE, and store the appropriate bytes in *LITP. The number
4403 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4404 returned, or NULL on OK. */
4407 md_atof (type
, litP
, sizeP
)
4413 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4414 LITTLENUM_TYPE
*wordP
;
4445 return _("Bad call to MD_ATOF()");
4447 t
= atof_ieee (input_line_pointer
, type
, words
);
4449 input_line_pointer
= t
;
4451 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4452 for (wordP
= words
; prec
--;)
4454 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
4455 litP
+= sizeof (LITTLENUM_TYPE
);
4461 md_number_to_chars (buf
, val
, n
)
4466 number_to_chars_bigendian (buf
, val
, n
);
4470 md_apply_fix3 (fixP
, valP
, seg
)
4473 segT seg ATTRIBUTE_UNUSED
;
4475 offsetT val
= *valP
;
4476 addressT upper_limit
;
4477 offsetT lower_limit
;
4479 /* This is unnecessary but it convinces the native rs6000 compiler
4480 to generate the code we want. */
4481 char *buf
= fixP
->fx_frag
->fr_literal
;
4482 buf
+= fixP
->fx_where
;
4483 /* End ibm compiler workaround. */
4485 val
= ((val
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4487 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4493 memset (buf
, 0, fixP
->fx_size
);
4494 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4496 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4497 && !S_IS_DEFINED (fixP
->fx_addsy
)
4498 && !S_IS_WEAK (fixP
->fx_addsy
))
4499 S_SET_WEAK (fixP
->fx_addsy
);
4504 #ifdef BFD_ASSEMBLER
4505 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4506 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4510 switch (fixP
->fx_size
)
4512 /* The cast to offsetT below are necessary to make code
4513 correct for machines where ints are smaller than offsetT. */
4517 lower_limit
= - (offsetT
) 0x80;
4520 *buf
++ = (val
>> 8);
4522 upper_limit
= 0x7fff;
4523 lower_limit
= - (offsetT
) 0x8000;
4526 *buf
++ = (val
>> 24);
4527 *buf
++ = (val
>> 16);
4528 *buf
++ = (val
>> 8);
4530 upper_limit
= 0x7fffffff;
4531 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* Avoid constant overflow. */
4534 BAD_CASE (fixP
->fx_size
);
4537 /* Fix up a negative reloc. */
4538 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4540 fixP
->fx_addsy
= fixP
->fx_subsy
;
4541 fixP
->fx_subsy
= NULL
;
4545 /* For non-pc-relative values, it's conceivable we might get something
4546 like "0xff" for a byte field. So extend the upper part of the range
4547 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4548 so that we can do any range checking at all. */
4549 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
4550 upper_limit
= upper_limit
* 2 + 1;
4552 if ((addressT
) val
> upper_limit
4553 && (val
> 0 || val
< lower_limit
))
4554 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("value out of range"));
4556 /* A one byte PC-relative reloc means a short branch. We can't use
4557 a short branch with a value of 0 or -1, because those indicate
4558 different opcodes (branches with longer offsets). fixup_segment
4559 in write.c may have clobbered fx_pcrel, so we need to examine the
4562 #ifdef BFD_ASSEMBLER
4563 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
4566 && fixP
->fx_size
== 1
4567 && (fixP
->fx_addsy
== NULL
4568 || S_IS_DEFINED (fixP
->fx_addsy
))
4569 && (val
== 0 || val
== -1))
4570 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("invalid byte branch offset"));
4573 /* *fragP has been relaxed to its final size, and now needs to have
4574 the bytes inside it modified to conform to the new size There is UGLY
4578 md_convert_frag_1 (fragP
)
4579 register fragS
*fragP
;
4584 /* Address in object code of the displacement. */
4585 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4587 /* Address in gas core of the place to store the displacement. */
4588 /* This convinces the native rs6000 compiler to generate the code we
4590 register char *buffer_address
= fragP
->fr_literal
;
4591 buffer_address
+= fragP
->fr_fix
;
4592 /* End ibm compiler workaround. */
4594 /* The displacement of the address, from current location. */
4595 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4596 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4598 switch (fragP
->fr_subtype
)
4600 case TAB (BRANCHBWL
, BYTE
):
4601 case TAB (BRABSJUNC
, BYTE
):
4602 case TAB (BRABSJCOND
, BYTE
):
4603 case TAB (BRANCHBW
, BYTE
):
4604 know (issbyte (disp
));
4606 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4607 _("short branch with zero offset: use :w"));
4608 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4609 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4610 fixP
->fx_pcrel_adjust
= -1;
4612 case TAB (BRANCHBWL
, SHORT
):
4613 case TAB (BRABSJUNC
, SHORT
):
4614 case TAB (BRABSJCOND
, SHORT
):
4615 case TAB (BRANCHBW
, SHORT
):
4616 fragP
->fr_opcode
[1] = 0x00;
4617 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4618 1, RELAX_RELOC_PC16
);
4621 case TAB (BRANCHBWL
, LONG
):
4622 fragP
->fr_opcode
[1] = (char) 0xFF;
4623 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4624 1, RELAX_RELOC_PC32
);
4627 case TAB (BRABSJUNC
, LONG
):
4628 if (fragP
->fr_opcode
[0] == 0x61) /* jbsr */
4630 if (flag_keep_pcrel
)
4631 as_fatal(_("Tried to convert PC relative BSR to absolute JSR"));
4632 fragP
->fr_opcode
[0] = 0x4E;
4633 fragP
->fr_opcode
[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4634 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4635 0, RELAX_RELOC_ABS32
);
4638 else if (fragP
->fr_opcode
[0] == 0x60) /* jbra */
4640 if (flag_keep_pcrel
)
4641 as_fatal(_("Tried to convert PC relative branch to absolute jump"));
4642 fragP
->fr_opcode
[0] = 0x4E;
4643 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4644 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4645 0, RELAX_RELOC_ABS32
);
4650 /* This cannot happen, because jbsr and jbra are the only two
4651 unconditional branches. */
4655 case TAB (BRABSJCOND
, LONG
):
4656 if (flag_keep_pcrel
)
4657 as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
4659 /* Only Bcc 68000 instructions can come here
4660 Change bcc into b!cc/jmp absl long. */
4661 fragP
->fr_opcode
[0] ^= 0x01; /* Invert bcc. */
4662 fragP
->fr_opcode
[1] = 0x06; /* Branch offset = 6. */
4664 /* JF: these used to be fr_opcode[2,3], but they may be in a
4665 different frag, in which case referring to them is a no-no.
4666 Only fr_opcode[0,1] are guaranteed to work. */
4667 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4668 *buffer_address
++ = (char) 0xf9;
4669 fragP
->fr_fix
+= 2; /* Account for jmp instruction. */
4670 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4671 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
4674 case TAB (FBRANCH
, SHORT
):
4675 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4676 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4677 1, RELAX_RELOC_PC16
);
4680 case TAB (FBRANCH
, LONG
):
4681 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit. */
4682 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4683 1, RELAX_RELOC_PC32
);
4686 case TAB (DBCCLBR
, SHORT
):
4687 case TAB (DBCCABSJ
, SHORT
):
4688 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4689 1, RELAX_RELOC_PC16
);
4692 case TAB (DBCCLBR
, LONG
):
4693 /* Only DBcc instructions can come here.
4694 Change dbcc into dbcc/bral.
4695 JF: these used to be fr_opcode[2-7], but that's wrong. */
4696 if (flag_keep_pcrel
)
4697 as_fatal(_("Tried to convert DBcc to absolute jump"));
4699 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4700 *buffer_address
++ = 0x04;
4701 *buffer_address
++ = 0x60; /* Put in bra pc+6. */
4702 *buffer_address
++ = 0x06;
4703 *buffer_address
++ = 0x60; /* Put in bral (0x60ff). */
4704 *buffer_address
++ = (char) 0xff;
4706 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4707 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 1,
4711 case TAB (DBCCABSJ
, LONG
):
4712 /* Only DBcc instructions can come here.
4713 Change dbcc into dbcc/jmp.
4714 JF: these used to be fr_opcode[2-7], but that's wrong. */
4715 if (flag_keep_pcrel
)
4716 as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
4718 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4719 *buffer_address
++ = 0x04;
4720 *buffer_address
++ = 0x60; /* Put in bra pc + 6. */
4721 *buffer_address
++ = 0x06;
4722 *buffer_address
++ = 0x4e; /* Put in jmp long (0x4ef9). */
4723 *buffer_address
++ = (char) 0xf9;
4725 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4726 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 0,
4730 case TAB (PCREL1632
, SHORT
):
4731 fragP
->fr_opcode
[1] &= ~0x3F;
4732 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
4733 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4734 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4737 case TAB (PCREL1632
, LONG
):
4738 /* Already set to mode 7.3; this indicates: PC indirect with
4739 suppressed index, 32-bit displacement. */
4740 *buffer_address
++ = 0x01;
4741 *buffer_address
++ = 0x70;
4743 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4744 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4745 fixP
->fx_pcrel_adjust
= 2;
4748 case TAB (PCINDEX
, BYTE
):
4749 assert (fragP
->fr_fix
>= 2);
4750 buffer_address
[-2] &= ~1;
4751 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4752 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4753 fixP
->fx_pcrel_adjust
= 1;
4755 case TAB (PCINDEX
, SHORT
):
4756 assert (fragP
->fr_fix
>= 2);
4757 buffer_address
[-2] |= 0x1;
4758 buffer_address
[-1] = 0x20;
4759 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4760 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4761 fixP
->fx_pcrel_adjust
= 2;
4764 case TAB (PCINDEX
, LONG
):
4765 assert (fragP
->fr_fix
>= 2);
4766 buffer_address
[-2] |= 0x1;
4767 buffer_address
[-1] = 0x30;
4768 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4769 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4770 fixP
->fx_pcrel_adjust
= 2;
4773 case TAB (ABSTOPCREL
, SHORT
):
4774 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4775 1, RELAX_RELOC_PC16
);
4778 case TAB (ABSTOPCREL
, LONG
):
4779 if (flag_keep_pcrel
)
4780 as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
4781 /* The thing to do here is force it to ABSOLUTE LONG, since
4782 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4783 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
4785 fragP
->fr_opcode
[1] &= ~0x3F;
4786 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
4787 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4788 0, RELAX_RELOC_ABS32
);
4794 #ifndef BFD_ASSEMBLER
4797 md_convert_frag (headers
, sec
, fragP
)
4798 object_headers
*headers ATTRIBUTE_UNUSED
;
4799 segT sec ATTRIBUTE_UNUSED
;
4802 md_convert_frag_1 (fragP
);
4808 md_convert_frag (abfd
, sec
, fragP
)
4809 bfd
*abfd ATTRIBUTE_UNUSED
;
4810 segT sec ATTRIBUTE_UNUSED
;
4813 md_convert_frag_1 (fragP
);
4817 /* Force truly undefined symbols to their maximum size, and generally set up
4818 the frag list to be relaxed
4821 md_estimate_size_before_relax (fragP
, segment
)
4822 register fragS
*fragP
;
4825 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4826 switch (fragP
->fr_subtype
)
4828 case TAB (BRANCHBWL
, SZ_UNDEF
):
4829 case TAB (BRABSJUNC
, SZ_UNDEF
):
4830 case TAB (BRABSJCOND
, SZ_UNDEF
):
4832 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4833 && relaxable_symbol (fragP
->fr_symbol
))
4835 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4837 else if (flag_short_refs
)
4839 /* Symbol is undefined and we want short ref. */
4840 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4844 /* Symbol is still undefined. Make it LONG. */
4845 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
4850 case TAB (BRANCHBW
, SZ_UNDEF
):
4852 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4853 && relaxable_symbol (fragP
->fr_symbol
))
4855 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4859 /* Symbol is undefined and we don't have long branches. */
4860 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4865 case TAB (FBRANCH
, SZ_UNDEF
):
4866 case TAB (DBCCLBR
, SZ_UNDEF
):
4867 case TAB (DBCCABSJ
, SZ_UNDEF
):
4868 case TAB (PCREL1632
, SZ_UNDEF
):
4870 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4871 && relaxable_symbol (fragP
->fr_symbol
))
4874 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4878 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
4883 case TAB (PCINDEX
, SZ_UNDEF
):
4884 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4885 && relaxable_symbol (fragP
->fr_symbol
)))
4887 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
4891 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
4895 case TAB (ABSTOPCREL
, SZ_UNDEF
):
4897 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4898 && relaxable_symbol (fragP
->fr_symbol
)))
4900 fragP
->fr_subtype
= TAB (ABSTOPCREL
, SHORT
);
4904 fragP
->fr_subtype
= TAB (ABSTOPCREL
, LONG
);
4913 /* Now that SZ_UNDEF are taken care of, check others. */
4914 switch (fragP
->fr_subtype
)
4916 case TAB (BRANCHBWL
, BYTE
):
4917 case TAB (BRABSJUNC
, BYTE
):
4918 case TAB (BRABSJCOND
, BYTE
):
4919 case TAB (BRANCHBW
, BYTE
):
4920 /* We can't do a short jump to the next instruction, so in that
4921 case we force word mode. If the symbol is at the start of a
4922 frag, and it is the next frag with any data in it (usually
4923 this is just the next frag, but assembler listings may
4924 introduce empty frags), we must use word mode. */
4925 if (fragP
->fr_symbol
)
4929 sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
4930 if (S_GET_VALUE (fragP
->fr_symbol
) == sym_frag
->fr_address
)
4934 for (l
= fragP
->fr_next
; l
&& l
!= sym_frag
; l
= l
->fr_next
)
4938 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4945 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4948 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4949 /* the bit-field entries in the relocation_info struct plays hell
4950 with the byte-order problems of cross-assembly. So as a hack,
4951 I added this mach. dependent ri twiddler. Ugly, but it gets
4953 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4954 are symbolnum, most sig. byte first. Last byte is broken up with
4955 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4956 nibble as nuthin. (on Sun 3 at least) */
4957 /* Translate the internal relocation information into target-specific
4961 md_ri_to_chars (the_bytes
, ri
)
4963 struct reloc_info_generic
*ri
;
4966 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
4967 /* Now the fun stuff. */
4968 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
4969 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
4970 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
4971 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80) | ((ri
->r_length
<< 5) & 0x60) |
4972 ((ri
->r_extern
<< 4) & 0x10));
4977 #ifndef BFD_ASSEMBLER
4979 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4982 relax_addressT segment_address_in_file
;
4985 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4986 * Out: GNU LD relocation length code: 0, 1, or 2.
4989 static const unsigned char nbytes_r_length
[] = {42, 0, 1, 42, 2};
4992 know (fixP
->fx_addsy
!= NULL
);
4994 md_number_to_chars (where
,
4995 fixP
->fx_frag
->fr_address
+ fixP
->fx_where
- segment_address_in_file
,
4998 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4999 ? S_GET_TYPE (fixP
->fx_addsy
)
5000 : fixP
->fx_addsy
->sy_number
);
5002 where
[4] = (r_symbolnum
>> 16) & 0x0ff;
5003 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
5004 where
[6] = r_symbolnum
& 0x0ff;
5005 where
[7] = (((fixP
->fx_pcrel
<< 7) & 0x80) | ((nbytes_r_length
[fixP
->fx_size
] << 5) & 0x60) |
5006 (((!S_IS_DEFINED (fixP
->fx_addsy
)) << 4) & 0x10));
5010 #endif /* OBJ_AOUT or OBJ_BOUT */
5012 #ifndef WORKING_DOT_WORD
5013 const int md_short_jump_size
= 4;
5014 const int md_long_jump_size
= 6;
5017 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5019 addressT from_addr
, to_addr
;
5020 fragS
*frag ATTRIBUTE_UNUSED
;
5021 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5025 offset
= to_addr
- (from_addr
+ 2);
5027 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
5028 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
5032 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5034 addressT from_addr
, to_addr
;
5040 if (!HAVE_LONG_BRANCH(current_architecture
))
5042 if (flag_keep_pcrel
)
5043 as_fatal(_("Tried to convert PC relative branch to absolute jump"));
5044 offset
= to_addr
- S_GET_VALUE (to_symbol
);
5045 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
5046 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5047 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
5052 offset
= to_addr
- (from_addr
+ 2);
5053 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
5054 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5060 /* Different values of OK tell what its OK to return. Things that
5061 aren't OK are an error (what a shock, no?)
5064 10: Absolute 1:8 only
5065 20: Absolute 0:7 only
5066 30: absolute 0:15 only
5067 40: Absolute 0:31 only
5068 50: absolute 0:127 only
5069 55: absolute -64:63 only
5070 60: absolute -128:127 only
5071 70: absolute 0:4095 only
5072 80: absolute -1, 1:7 only
5077 struct m68k_exp
*exp
;
5080 if (exp
->exp
.X_op
== O_absent
)
5082 /* Do the same thing the VAX asm does. */
5083 op (exp
) = O_constant
;
5089 as_warn (_("expression out of range: defaulting to 1"));
5093 else if (exp
->exp
.X_op
== O_constant
)
5098 if (offs (exp
) < 1 || offs (exp
) > 8)
5100 as_warn (_("expression out of range: defaulting to 1"));
5105 if (offs (exp
) < 0 || offs (exp
) > 7)
5109 if (offs (exp
) < 0 || offs (exp
) > 15)
5113 if (offs (exp
) < 0 || offs (exp
) > 32)
5117 if (offs (exp
) < 0 || offs (exp
) > 127)
5121 if (offs (exp
) < -64 || offs (exp
) > 63)
5125 if (offs (exp
) < -128 || offs (exp
) > 127)
5129 if (offs (exp
) < 0 || offs (exp
) > 4095)
5132 as_warn (_("expression out of range: defaulting to 0"));
5141 as_warn (_("expression out of range: defaulting to 1"));
5149 else if (exp
->exp
.X_op
== O_big
)
5151 if (offs (exp
) <= 0 /* flonum. */
5152 && (ok
== 90 /* no bignums */
5153 || (ok
> 10 /* Small-int ranges including 0 ok. */
5154 /* If we have a flonum zero, a zero integer should
5155 do as well (e.g., in moveq). */
5156 && generic_floating_point_number
.exponent
== 0
5157 && generic_floating_point_number
.low
[0] == 0)))
5159 /* HACK! Turn it into a long. */
5160 LITTLENUM_TYPE words
[6];
5162 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
5163 op (exp
) = O_constant
;
5166 offs (exp
) = words
[1] | (words
[0] << 16);
5170 op (exp
) = O_constant
;
5173 offs (exp
) = (ok
== 10) ? 1 : 0;
5174 as_warn (_("Can't deal with expression; defaulting to %ld"),
5180 if (ok
>= 10 && ok
<= 80)
5182 op (exp
) = O_constant
;
5185 offs (exp
) = (ok
== 10) ? 1 : 0;
5186 as_warn (_("Can't deal with expression; defaulting to %ld"),
5191 if (exp
->size
!= SIZE_UNSPEC
)
5199 if (!isbyte (offs (exp
)))
5200 as_warn (_("expression doesn't fit in BYTE"));
5203 if (!isword (offs (exp
)))
5204 as_warn (_("expression doesn't fit in WORD"));
5212 /* These are the back-ends for the various machine dependent pseudo-ops. */
5216 int ignore ATTRIBUTE_UNUSED
;
5218 subseg_set (data_section
, 1);
5219 demand_empty_rest_of_line ();
5224 int ignore ATTRIBUTE_UNUSED
;
5226 subseg_set (data_section
, 2);
5227 demand_empty_rest_of_line ();
5232 int ignore ATTRIBUTE_UNUSED
;
5234 /* We don't support putting frags in the BSS segment, we fake it
5235 by marking in_bss, then looking at s_skip for clues. */
5237 subseg_set (bss_section
, 0);
5238 demand_empty_rest_of_line ();
5243 int ignore ATTRIBUTE_UNUSED
;
5246 register long temp_fill
;
5248 temp
= 1; /* JF should be 2? */
5249 temp_fill
= get_absolute_expression ();
5250 if (!need_pass_2
) /* Never make frag if expect extra pass. */
5251 frag_align (temp
, (int) temp_fill
, 0);
5252 demand_empty_rest_of_line ();
5253 record_alignment (now_seg
, temp
);
5258 int ignore ATTRIBUTE_UNUSED
;
5260 demand_empty_rest_of_line ();
5263 /* Pseudo-ops handled for MRI compatibility. */
5265 /* This function returns non-zero if the argument is a conditional
5266 pseudo-op. This is called when checking whether a pending
5267 alignment is needed. */
5270 m68k_conditional_pseudoop (pop
)
5273 return (pop
->poc_handler
== s_mri_if
5274 || pop
->poc_handler
== s_mri_else
);
5277 /* Handle an MRI style chip specification. */
5286 s
= input_line_pointer
;
5287 /* We can't use get_symbol_end since the processor names are not proper
5289 while (is_part_of_name (c
= *input_line_pointer
++))
5291 *--input_line_pointer
= 0;
5292 for (i
= 0; i
< n_archs
; i
++)
5293 if (strcasecmp (s
, archs
[i
].name
) == 0)
5297 as_bad (_("%s: unrecognized processor name"), s
);
5298 *input_line_pointer
= c
;
5299 ignore_rest_of_line ();
5302 *input_line_pointer
= c
;
5304 if (*input_line_pointer
== '/')
5305 current_architecture
= 0;
5307 current_architecture
&= m68881
| m68851
;
5308 current_architecture
|= archs
[i
].arch
;
5310 while (*input_line_pointer
== '/')
5312 ++input_line_pointer
;
5313 s
= input_line_pointer
;
5314 /* We can't use get_symbol_end since the processor names are not
5316 while (is_part_of_name (c
= *input_line_pointer
++))
5318 *--input_line_pointer
= 0;
5319 if (strcmp (s
, "68881") == 0)
5320 current_architecture
|= m68881
;
5321 else if (strcmp (s
, "68851") == 0)
5322 current_architecture
|= m68851
;
5323 *input_line_pointer
= c
;
5326 /* Update info about available control registers. */
5327 select_control_regs ();
5330 /* The MRI CHIP pseudo-op. */
5334 int ignore ATTRIBUTE_UNUSED
;
5340 stop
= mri_comment_field (&stopc
);
5343 mri_comment_end (stop
, stopc
);
5344 demand_empty_rest_of_line ();
5347 /* The MRI FOPT pseudo-op. */
5351 int ignore ATTRIBUTE_UNUSED
;
5355 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
5359 input_line_pointer
+= 3;
5360 temp
= get_absolute_expression ();
5361 if (temp
< 0 || temp
> 7)
5362 as_bad (_("bad coprocessor id"));
5364 m68k_float_copnum
= COP0
+ temp
;
5368 as_bad (_("unrecognized fopt option"));
5369 ignore_rest_of_line ();
5373 demand_empty_rest_of_line ();
5376 /* The structure used to handle the MRI OPT pseudo-op. */
5380 /* The name of the option. */
5383 /* If this is not NULL, just call this function. The first argument
5384 is the ARG field of this structure, the second argument is
5385 whether the option was negated. */
5386 void (*pfn
) PARAMS ((int arg
, int on
));
5388 /* If this is not NULL, and the PFN field is NULL, set the variable
5389 this points to. Set it to the ARG field if the option was not
5390 negated, and the NOTARG field otherwise. */
5393 /* The value to pass to PFN or to assign to *PVAR. */
5396 /* The value to assign to *PVAR if the option is negated. If PFN is
5397 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5398 the option may not be negated. */
5402 /* The table used to handle the MRI OPT pseudo-op. */
5404 static void skip_to_comma
PARAMS ((int, int));
5405 static void opt_nest
PARAMS ((int, int));
5406 static void opt_chip
PARAMS ((int, int));
5407 static void opt_list
PARAMS ((int, int));
5408 static void opt_list_symbols
PARAMS ((int, int));
5410 static const struct opt_action opt_table
[] =
5412 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5414 /* We do relaxing, so there is little use for these options. */
5415 { "b", 0, 0, 0, 0 },
5416 { "brs", 0, 0, 0, 0 },
5417 { "brb", 0, 0, 0, 0 },
5418 { "brl", 0, 0, 0, 0 },
5419 { "brw", 0, 0, 0, 0 },
5421 { "c", 0, 0, 0, 0 },
5422 { "cex", 0, 0, 0, 0 },
5423 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5424 { "cl", 0, 0, 0, 0 },
5425 { "cre", 0, 0, 0, 0 },
5426 { "d", 0, &flag_keep_locals
, 1, 0 },
5427 { "e", 0, 0, 0, 0 },
5428 { "f", 0, &flag_short_refs
, 1, 0 },
5429 { "frs", 0, &flag_short_refs
, 1, 0 },
5430 { "frl", 0, &flag_short_refs
, 0, 1 },
5431 { "g", 0, 0, 0, 0 },
5432 { "i", 0, 0, 0, 0 },
5433 { "m", 0, 0, 0, 0 },
5434 { "mex", 0, 0, 0, 0 },
5435 { "mc", 0, 0, 0, 0 },
5436 { "md", 0, 0, 0, 0 },
5437 { "nest", opt_nest
, 0, 0, 0 },
5438 { "next", skip_to_comma
, 0, 0, 0 },
5439 { "o", 0, 0, 0, 0 },
5440 { "old", 0, 0, 0, 0 },
5441 { "op", skip_to_comma
, 0, 0, 0 },
5442 { "pco", 0, 0, 0, 0 },
5443 { "p", opt_chip
, 0, 0, 0 },
5444 { "pcr", 0, 0, 0, 0 },
5445 { "pcs", 0, 0, 0, 0 },
5446 { "r", 0, 0, 0, 0 },
5447 { "quick", 0, &m68k_quick
, 1, 0 },
5448 { "rel32", 0, &m68k_rel32
, 1, 0 },
5449 { "s", opt_list
, 0, 0, 0 },
5450 { "t", opt_list_symbols
, 0, 0, 0 },
5451 { "w", 0, &flag_no_warnings
, 0, 1 },
5455 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5457 /* The MRI OPT pseudo-op. */
5461 int ignore ATTRIBUTE_UNUSED
;
5469 const struct opt_action
*o
;
5474 if (*input_line_pointer
== '-')
5476 ++input_line_pointer
;
5479 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5481 input_line_pointer
+= 2;
5485 s
= input_line_pointer
;
5486 c
= get_symbol_end ();
5488 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5490 if (strcasecmp (s
, o
->name
) == 0)
5494 /* Restore input_line_pointer now in case the option
5496 *input_line_pointer
= c
;
5497 (*o
->pfn
) (o
->arg
, t
);
5499 else if (o
->pvar
!= NULL
)
5501 if (! t
&& o
->arg
== o
->notarg
)
5502 as_bad (_("option `%s' may not be negated"), s
);
5503 *input_line_pointer
= c
;
5504 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5507 *input_line_pointer
= c
;
5513 as_bad (_("option `%s' not recognized"), s
);
5514 *input_line_pointer
= c
;
5517 while (*input_line_pointer
++ == ',');
5519 /* Move back to terminating character. */
5520 --input_line_pointer
;
5521 demand_empty_rest_of_line ();
5524 /* Skip ahead to a comma. This is used for OPT options which we do
5525 not support and which take arguments. */
5528 skip_to_comma (arg
, on
)
5529 int arg ATTRIBUTE_UNUSED
;
5530 int on ATTRIBUTE_UNUSED
;
5532 while (*input_line_pointer
!= ','
5533 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5534 ++input_line_pointer
;
5537 /* Handle the OPT NEST=depth option. */
5541 int arg ATTRIBUTE_UNUSED
;
5542 int on ATTRIBUTE_UNUSED
;
5544 if (*input_line_pointer
!= '=')
5546 as_bad (_("bad format of OPT NEST=depth"));
5550 ++input_line_pointer
;
5551 max_macro_nest
= get_absolute_expression ();
5554 /* Handle the OPT P=chip option. */
5558 int arg ATTRIBUTE_UNUSED
;
5559 int on ATTRIBUTE_UNUSED
;
5561 if (*input_line_pointer
!= '=')
5563 /* This is just OPT P, which we do not support. */
5567 ++input_line_pointer
;
5571 /* Handle the OPT S option. */
5575 int arg ATTRIBUTE_UNUSED
;
5581 /* Handle the OPT T option. */
5584 opt_list_symbols (arg
, on
)
5585 int arg ATTRIBUTE_UNUSED
;
5589 listing
|= LISTING_SYMBOLS
;
5591 listing
&= ~LISTING_SYMBOLS
;
5594 /* Handle the MRI REG pseudo-op. */
5598 int ignore ATTRIBUTE_UNUSED
;
5607 if (line_label
== NULL
)
5609 as_bad (_("missing label"));
5610 ignore_rest_of_line ();
5615 stop
= mri_comment_field (&stopc
);
5619 s
= input_line_pointer
;
5620 while (ISALNUM (*input_line_pointer
)
5621 #ifdef REGISTER_PREFIX
5622 || *input_line_pointer
== REGISTER_PREFIX
5624 || *input_line_pointer
== '/'
5625 || *input_line_pointer
== '-')
5626 ++input_line_pointer
;
5627 c
= *input_line_pointer
;
5628 *input_line_pointer
= '\0';
5630 if (m68k_ip_op (s
, &rop
) != 0)
5632 if (rop
.error
== NULL
)
5633 as_bad (_("bad register list"));
5635 as_bad (_("bad register list: %s"), rop
.error
);
5636 *input_line_pointer
= c
;
5637 ignore_rest_of_line ();
5641 *input_line_pointer
= c
;
5643 if (rop
.mode
== REGLST
)
5645 else if (rop
.mode
== DREG
)
5646 mask
= 1 << (rop
.reg
- DATA0
);
5647 else if (rop
.mode
== AREG
)
5648 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
5649 else if (rop
.mode
== FPREG
)
5650 mask
= 1 << (rop
.reg
- FP0
+ 16);
5651 else if (rop
.mode
== CONTROL
5654 else if (rop
.mode
== CONTROL
5657 else if (rop
.mode
== CONTROL
5662 as_bad (_("bad register list"));
5663 ignore_rest_of_line ();
5667 S_SET_SEGMENT (line_label
, reg_section
);
5668 S_SET_VALUE (line_label
, ~mask
);
5669 symbol_set_frag (line_label
, &zero_address_frag
);
5672 mri_comment_end (stop
, stopc
);
5674 demand_empty_rest_of_line ();
5677 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5681 struct save_opts
*next
;
5683 int symbols_case_sensitive
;
5691 /* FIXME: We don't save OPT S. */
5694 /* This variable holds the stack of saved options. */
5696 static struct save_opts
*save_stack
;
5698 /* The MRI SAVE pseudo-op. */
5702 int ignore ATTRIBUTE_UNUSED
;
5704 struct save_opts
*s
;
5706 s
= (struct save_opts
*) xmalloc (sizeof (struct save_opts
));
5707 s
->abspcadd
= m68k_abspcadd
;
5708 s
->symbols_case_sensitive
= symbols_case_sensitive
;
5709 s
->keep_locals
= flag_keep_locals
;
5710 s
->short_refs
= flag_short_refs
;
5711 s
->architecture
= current_architecture
;
5712 s
->quick
= m68k_quick
;
5713 s
->rel32
= m68k_rel32
;
5714 s
->listing
= listing
;
5715 s
->no_warnings
= flag_no_warnings
;
5717 s
->next
= save_stack
;
5720 demand_empty_rest_of_line ();
5723 /* The MRI RESTORE pseudo-op. */
5727 int ignore ATTRIBUTE_UNUSED
;
5729 struct save_opts
*s
;
5731 if (save_stack
== NULL
)
5733 as_bad (_("restore without save"));
5734 ignore_rest_of_line ();
5739 save_stack
= s
->next
;
5741 m68k_abspcadd
= s
->abspcadd
;
5742 symbols_case_sensitive
= s
->symbols_case_sensitive
;
5743 flag_keep_locals
= s
->keep_locals
;
5744 flag_short_refs
= s
->short_refs
;
5745 current_architecture
= s
->architecture
;
5746 m68k_quick
= s
->quick
;
5747 m68k_rel32
= s
->rel32
;
5748 listing
= s
->listing
;
5749 flag_no_warnings
= s
->no_warnings
;
5753 demand_empty_rest_of_line ();
5756 /* Types of MRI structured control directives. */
5758 enum mri_control_type
5766 /* This structure is used to stack the MRI structured control
5769 struct mri_control_info
5771 /* The directive within which this one is enclosed. */
5772 struct mri_control_info
*outer
;
5774 /* The type of directive. */
5775 enum mri_control_type type
;
5777 /* Whether an ELSE has been in an IF. */
5780 /* The add or sub statement at the end of a FOR. */
5783 /* The label of the top of a FOR or REPEAT loop. */
5786 /* The label to jump to for the next iteration, or the else
5787 expression of a conditional. */
5790 /* The label to jump to to break out of the loop, or the label past
5791 the end of a conditional. */
5795 /* The stack of MRI structured control directives. */
5797 static struct mri_control_info
*mri_control_stack
;
5799 /* The current MRI structured control directive index number, used to
5800 generate label names. */
5802 static int mri_control_index
;
5804 /* Some function prototypes. */
5806 static void mri_assemble
PARAMS ((char *));
5807 static char *mri_control_label
PARAMS ((void));
5808 static struct mri_control_info
*push_mri_control
5809 PARAMS ((enum mri_control_type
));
5810 static void pop_mri_control
PARAMS ((void));
5811 static int parse_mri_condition
PARAMS ((int *));
5812 static int parse_mri_control_operand
5813 PARAMS ((int *, char **, char **, char **, char **));
5814 static int swap_mri_condition
PARAMS ((int));
5815 static int reverse_mri_condition
PARAMS ((int));
5816 static void build_mri_control_operand
5817 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5818 const char *, int));
5819 static void parse_mri_control_expression
5820 PARAMS ((char *, int, const char *, const char *, int));
5822 /* Assemble an instruction for an MRI structured control directive. */
5830 /* md_assemble expects the opcode to be in lower case. */
5831 for (s
= str
; *s
!= ' ' && *s
!= '\0'; s
++)
5837 /* Generate a new MRI label structured control directive label name. */
5840 mri_control_label ()
5844 n
= (char *) xmalloc (20);
5845 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
5846 ++mri_control_index
;
5850 /* Create a new MRI structured control directive. */
5852 static struct mri_control_info
*
5853 push_mri_control (type
)
5854 enum mri_control_type type
;
5856 struct mri_control_info
*n
;
5858 n
= (struct mri_control_info
*) xmalloc (sizeof (struct mri_control_info
));
5862 if (type
== mri_if
|| type
== mri_while
)
5865 n
->top
= mri_control_label ();
5866 n
->next
= mri_control_label ();
5867 n
->bottom
= mri_control_label ();
5869 n
->outer
= mri_control_stack
;
5870 mri_control_stack
= n
;
5875 /* Pop off the stack of MRI structured control directives. */
5880 struct mri_control_info
*n
;
5882 n
= mri_control_stack
;
5883 mri_control_stack
= n
->outer
;
5891 /* Recognize a condition code in an MRI structured control expression. */
5894 parse_mri_condition (pcc
)
5899 know (*input_line_pointer
== '<');
5901 ++input_line_pointer
;
5902 c1
= *input_line_pointer
++;
5903 c2
= *input_line_pointer
++;
5905 if (*input_line_pointer
!= '>')
5907 as_bad (_("syntax error in structured control directive"));
5911 ++input_line_pointer
;
5917 *pcc
= (c1
<< 8) | c2
;
5922 /* Parse a single operand in an MRI structured control expression. */
5925 parse_mri_control_operand (pcc
, leftstart
, leftstop
, rightstart
, rightstop
)
5942 if (*input_line_pointer
== '<')
5944 /* It's just a condition code. */
5945 return parse_mri_condition (pcc
);
5948 /* Look ahead for the condition code. */
5949 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5951 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
5956 as_bad (_("missing condition code in structured control directive"));
5960 *leftstart
= input_line_pointer
;
5962 if (*leftstop
> *leftstart
5963 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
5966 input_line_pointer
= s
;
5967 if (! parse_mri_condition (pcc
))
5970 /* Look ahead for AND or OR or end of line. */
5971 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5973 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5974 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5976 if ((s
== input_line_pointer
5979 && ((strncasecmp (s
, "AND", 3) == 0
5980 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
5981 || (strncasecmp (s
, "OR", 2) == 0
5982 && (s
[2] == '.' || ! is_part_of_name (s
[2])))))
5986 *rightstart
= input_line_pointer
;
5988 if (*rightstop
> *rightstart
5989 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
5992 input_line_pointer
= s
;
5997 #define MCC(b1, b2) (((b1) << 8) | (b2))
5999 /* Swap the sense of a condition. This changes the condition so that
6000 it generates the same result when the operands are swapped. */
6003 swap_mri_condition (cc
)
6008 case MCC ('h', 'i'): return MCC ('c', 's');
6009 case MCC ('l', 's'): return MCC ('c', 'c');
6010 /* <HS> is an alias for <CC>. */
6011 case MCC ('h', 's'):
6012 case MCC ('c', 'c'): return MCC ('l', 's');
6013 /* <LO> is an alias for <CS>. */
6014 case MCC ('l', 'o'):
6015 case MCC ('c', 's'): return MCC ('h', 'i');
6016 case MCC ('p', 'l'): return MCC ('m', 'i');
6017 case MCC ('m', 'i'): return MCC ('p', 'l');
6018 case MCC ('g', 'e'): return MCC ('l', 'e');
6019 case MCC ('l', 't'): return MCC ('g', 't');
6020 case MCC ('g', 't'): return MCC ('l', 't');
6021 case MCC ('l', 'e'): return MCC ('g', 'e');
6022 /* Issue a warning for conditions we can not swap. */
6023 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6024 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6025 case MCC ('v', 'c'):
6026 case MCC ('v', 's'):
6028 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6029 (char) (cc
>> 8), (char) (cc
));
6035 /* Reverse the sense of a condition. */
6038 reverse_mri_condition (cc
)
6043 case MCC ('h', 'i'): return MCC ('l', 's');
6044 case MCC ('l', 's'): return MCC ('h', 'i');
6045 /* <HS> is an alias for <CC> */
6046 case MCC ('h', 's'): return MCC ('l', 'o');
6047 case MCC ('c', 'c'): return MCC ('c', 's');
6048 /* <LO> is an alias for <CS> */
6049 case MCC ('l', 'o'): return MCC ('h', 's');
6050 case MCC ('c', 's'): return MCC ('c', 'c');
6051 case MCC ('n', 'e'): return MCC ('e', 'q');
6052 case MCC ('e', 'q'): return MCC ('n', 'e');
6053 case MCC ('v', 'c'): return MCC ('v', 's');
6054 case MCC ('v', 's'): return MCC ('v', 'c');
6055 case MCC ('p', 'l'): return MCC ('m', 'i');
6056 case MCC ('m', 'i'): return MCC ('p', 'l');
6057 case MCC ('g', 'e'): return MCC ('l', 't');
6058 case MCC ('l', 't'): return MCC ('g', 'e');
6059 case MCC ('g', 't'): return MCC ('l', 'e');
6060 case MCC ('l', 'e'): return MCC ('g', 't');
6065 /* Build an MRI structured control expression. This generates test
6066 and branch instructions. It goes to TRUELAB if the condition is
6067 true, and to FALSELAB if the condition is false. Exactly one of
6068 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6069 is the size qualifier for the expression. EXTENT is the size to
6070 use for the branch. */
6073 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6074 rightstop
, truelab
, falselab
, extent
)
6081 const char *truelab
;
6082 const char *falselab
;
6088 if (leftstart
!= NULL
)
6090 struct m68k_op leftop
, rightop
;
6093 /* Swap the compare operands, if necessary, to produce a legal
6094 m68k compare instruction. Comparing a register operand with
6095 a non-register operand requires the register to be on the
6096 right (cmp, cmpa). Comparing an immediate value with
6097 anything requires the immediate value to be on the left
6102 (void) m68k_ip_op (leftstart
, &leftop
);
6107 (void) m68k_ip_op (rightstart
, &rightop
);
6110 if (rightop
.mode
== IMMED
6111 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
6112 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
6116 /* Correct conditional handling:
6117 if #1 <lt> d0 then ;means if (1 < d0)
6123 cmp #1,d0 if we do *not* swap the operands
6124 bgt true we need the swapped condition!
6131 leftstart
= rightstart
;
6134 leftstop
= rightstop
;
6139 cc
= swap_mri_condition (cc
);
6143 if (truelab
== NULL
)
6145 cc
= reverse_mri_condition (cc
);
6149 if (leftstart
!= NULL
)
6151 buf
= (char *) xmalloc (20
6152 + (leftstop
- leftstart
)
6153 + (rightstop
- rightstart
));
6159 *s
++ = TOLOWER (qual
);
6161 memcpy (s
, leftstart
, leftstop
- leftstart
);
6162 s
+= leftstop
- leftstart
;
6164 memcpy (s
, rightstart
, rightstop
- rightstart
);
6165 s
+= rightstop
- rightstart
;
6171 buf
= (char *) xmalloc (20 + strlen (truelab
));
6177 *s
++ = TOLOWER (extent
);
6179 strcpy (s
, truelab
);
6184 /* Parse an MRI structured control expression. This generates test
6185 and branch instructions. STOP is where the expression ends. It
6186 goes to TRUELAB if the condition is true, and to FALSELAB if the
6187 condition is false. Exactly one of TRUELAB and FALSELAB will be
6188 NULL, meaning to fall through. QUAL is the size qualifier for the
6189 expression. EXTENT is the size to use for the branch. */
6192 parse_mri_control_expression (stop
, qual
, truelab
, falselab
, extent
)
6195 const char *truelab
;
6196 const char *falselab
;
6209 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6210 &rightstart
, &rightstop
))
6216 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
6220 if (falselab
!= NULL
)
6223 flab
= mri_control_label ();
6225 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6226 rightstop
, (const char *) NULL
, flab
, extent
);
6228 input_line_pointer
+= 3;
6229 if (*input_line_pointer
!= '.'
6230 || input_line_pointer
[1] == '\0')
6234 qual
= input_line_pointer
[1];
6235 input_line_pointer
+= 2;
6238 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6239 &rightstart
, &rightstop
))
6245 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6246 rightstop
, truelab
, falselab
, extent
);
6248 if (falselab
== NULL
)
6251 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
6255 if (truelab
!= NULL
)
6258 tlab
= mri_control_label ();
6260 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6261 rightstop
, tlab
, (const char *) NULL
, extent
);
6263 input_line_pointer
+= 2;
6264 if (*input_line_pointer
!= '.'
6265 || input_line_pointer
[1] == '\0')
6269 qual
= input_line_pointer
[1];
6270 input_line_pointer
+= 2;
6273 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6274 &rightstart
, &rightstop
))
6280 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6281 rightstop
, truelab
, falselab
, extent
);
6283 if (truelab
== NULL
)
6288 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6289 rightstop
, truelab
, falselab
, extent
);
6293 if (input_line_pointer
!= stop
)
6294 as_bad (_("syntax error in structured control directive"));
6297 /* Handle the MRI IF pseudo-op. This may be a structured control
6298 directive, or it may be a regular assembler conditional, depending
6307 struct mri_control_info
*n
;
6309 /* A structured control directive must end with THEN with an
6310 optional qualifier. */
6311 s
= input_line_pointer
;
6312 /* We only accept '*' as introduction of comments if preceded by white space
6313 or at first column of a line (I think this can't actually happen here?)
6314 This is important when assembling:
6315 if d0 <ne> 12(a0,d0*2) then
6316 if d0 <ne> #CONST*20 then. */
6317 while ( ! ( is_end_of_line
[(unsigned char) *s
]
6320 && ( s
== input_line_pointer
6322 || *(s
-1) == '\t'))))
6325 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
6328 if (s
- input_line_pointer
> 1
6332 if (s
- input_line_pointer
< 3
6333 || strncasecmp (s
- 3, "THEN", 4) != 0)
6337 as_bad (_("missing then"));
6338 ignore_rest_of_line ();
6342 /* It's a conditional. */
6347 /* Since this might be a conditional if, this pseudo-op will be
6348 called even if we are supported to be ignoring input. Double
6349 check now. Clobber *input_line_pointer so that ignore_input
6350 thinks that this is not a special pseudo-op. */
6351 c
= *input_line_pointer
;
6352 *input_line_pointer
= 0;
6353 if (ignore_input ())
6355 *input_line_pointer
= c
;
6356 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6357 ++input_line_pointer
;
6358 demand_empty_rest_of_line ();
6361 *input_line_pointer
= c
;
6363 n
= push_mri_control (mri_if
);
6365 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
6366 n
->next
, s
[1] == '.' ? s
[2] : '\0');
6369 input_line_pointer
= s
+ 3;
6371 input_line_pointer
= s
+ 1;
6375 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6376 ++input_line_pointer
;
6379 demand_empty_rest_of_line ();
6382 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6383 structured IF, associate the ELSE with the IF. Otherwise, assume
6384 it is a conditional else. */
6395 && (mri_control_stack
== NULL
6396 || mri_control_stack
->type
!= mri_if
6397 || mri_control_stack
->else_seen
))
6403 c
= *input_line_pointer
;
6404 *input_line_pointer
= 0;
6405 if (ignore_input ())
6407 *input_line_pointer
= c
;
6408 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6409 ++input_line_pointer
;
6410 demand_empty_rest_of_line ();
6413 *input_line_pointer
= c
;
6415 if (mri_control_stack
== NULL
6416 || mri_control_stack
->type
!= mri_if
6417 || mri_control_stack
->else_seen
)
6419 as_bad (_("else without matching if"));
6420 ignore_rest_of_line ();
6424 mri_control_stack
->else_seen
= 1;
6426 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->bottom
));
6427 q
[0] = TOLOWER (qual
);
6429 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6433 colon (mri_control_stack
->next
);
6437 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6438 ++input_line_pointer
;
6441 demand_empty_rest_of_line ();
6444 /* Handle the MRI ENDI pseudo-op. */
6448 int ignore ATTRIBUTE_UNUSED
;
6450 if (mri_control_stack
== NULL
6451 || mri_control_stack
->type
!= mri_if
)
6453 as_bad (_("endi without matching if"));
6454 ignore_rest_of_line ();
6458 /* ignore_input will not return true for ENDI, so we don't need to
6459 worry about checking it again here. */
6461 if (! mri_control_stack
->else_seen
)
6462 colon (mri_control_stack
->next
);
6463 colon (mri_control_stack
->bottom
);
6469 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6470 ++input_line_pointer
;
6473 demand_empty_rest_of_line ();
6476 /* Handle the MRI BREAK pseudo-op. */
6479 s_mri_break (extent
)
6482 struct mri_control_info
*n
;
6486 n
= mri_control_stack
;
6488 && n
->type
!= mri_for
6489 && n
->type
!= mri_repeat
6490 && n
->type
!= mri_while
)
6494 as_bad (_("break outside of structured loop"));
6495 ignore_rest_of_line ();
6499 buf
= (char *) xmalloc (20 + strlen (n
->bottom
));
6500 ex
[0] = TOLOWER (extent
);
6502 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6508 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6509 ++input_line_pointer
;
6512 demand_empty_rest_of_line ();
6515 /* Handle the MRI NEXT pseudo-op. */
6521 struct mri_control_info
*n
;
6525 n
= mri_control_stack
;
6527 && n
->type
!= mri_for
6528 && n
->type
!= mri_repeat
6529 && n
->type
!= mri_while
)
6533 as_bad (_("next outside of structured loop"));
6534 ignore_rest_of_line ();
6538 buf
= (char *) xmalloc (20 + strlen (n
->next
));
6539 ex
[0] = TOLOWER (extent
);
6541 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6547 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6548 ++input_line_pointer
;
6551 demand_empty_rest_of_line ();
6554 /* Handle the MRI FOR pseudo-op. */
6560 const char *varstart
, *varstop
;
6561 const char *initstart
, *initstop
;
6562 const char *endstart
, *endstop
;
6563 const char *bystart
, *bystop
;
6567 struct mri_control_info
*n
;
6573 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6577 varstart
= input_line_pointer
;
6579 /* Look for the '='. */
6580 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6581 && *input_line_pointer
!= '=')
6582 ++input_line_pointer
;
6583 if (*input_line_pointer
!= '=')
6585 as_bad (_("missing ="));
6586 ignore_rest_of_line ();
6590 varstop
= input_line_pointer
;
6591 if (varstop
> varstart
6592 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6595 ++input_line_pointer
;
6597 initstart
= input_line_pointer
;
6599 /* Look for TO or DOWNTO. */
6602 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6604 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6605 && ! is_part_of_name (input_line_pointer
[2]))
6607 initstop
= input_line_pointer
;
6608 input_line_pointer
+= 2;
6611 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6612 && ! is_part_of_name (input_line_pointer
[6]))
6614 initstop
= input_line_pointer
;
6616 input_line_pointer
+= 6;
6619 ++input_line_pointer
;
6621 if (initstop
== NULL
)
6623 as_bad (_("missing to or downto"));
6624 ignore_rest_of_line ();
6627 if (initstop
> initstart
6628 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6632 endstart
= input_line_pointer
;
6634 /* Look for BY or DO. */
6637 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6639 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
6640 && ! is_part_of_name (input_line_pointer
[2]))
6642 endstop
= input_line_pointer
;
6644 input_line_pointer
+= 2;
6647 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6648 && (input_line_pointer
[2] == '.'
6649 || ! is_part_of_name (input_line_pointer
[2])))
6651 endstop
= input_line_pointer
;
6652 input_line_pointer
+= 2;
6655 ++input_line_pointer
;
6657 if (endstop
== NULL
)
6659 as_bad (_("missing do"));
6660 ignore_rest_of_line ();
6663 if (endstop
> endstart
6664 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
6670 bystop
= bystart
+ 2;
6675 bystart
= input_line_pointer
;
6679 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6681 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6682 && (input_line_pointer
[2] == '.'
6683 || ! is_part_of_name (input_line_pointer
[2])))
6685 bystop
= input_line_pointer
;
6686 input_line_pointer
+= 2;
6689 ++input_line_pointer
;
6693 as_bad (_("missing do"));
6694 ignore_rest_of_line ();
6697 if (bystop
> bystart
6698 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
6702 if (*input_line_pointer
!= '.')
6706 extent
= input_line_pointer
[1];
6707 input_line_pointer
+= 2;
6710 /* We have fully parsed the FOR operands. Now build the loop. */
6711 n
= push_mri_control (mri_for
);
6713 buf
= (char *) xmalloc (50 + (input_line_pointer
- varstart
));
6715 /* Move init,var. */
6722 *s
++ = TOLOWER (qual
);
6724 memcpy (s
, initstart
, initstop
- initstart
);
6725 s
+= initstop
- initstart
;
6727 memcpy (s
, varstart
, varstop
- varstart
);
6728 s
+= varstop
- varstart
;
6740 *s
++ = TOLOWER (qual
);
6742 memcpy (s
, endstart
, endstop
- endstart
);
6743 s
+= endstop
- endstart
;
6745 memcpy (s
, varstart
, varstop
- varstart
);
6746 s
+= varstop
- varstart
;
6751 ex
[0] = TOLOWER (extent
);
6754 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
6756 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
6759 /* Put together the add or sub instruction used by ENDF. */
6767 *s
++ = TOLOWER (qual
);
6769 memcpy (s
, bystart
, bystop
- bystart
);
6770 s
+= bystop
- bystart
;
6772 memcpy (s
, varstart
, varstop
- varstart
);
6773 s
+= varstop
- varstart
;
6779 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6780 ++input_line_pointer
;
6783 demand_empty_rest_of_line ();
6786 /* Handle the MRI ENDF pseudo-op. */
6790 int ignore ATTRIBUTE_UNUSED
;
6792 if (mri_control_stack
== NULL
6793 || mri_control_stack
->type
!= mri_for
)
6795 as_bad (_("endf without for"));
6796 ignore_rest_of_line ();
6800 colon (mri_control_stack
->next
);
6802 mri_assemble (mri_control_stack
->incr
);
6804 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
6805 mri_assemble (mri_control_stack
->incr
);
6807 free (mri_control_stack
->incr
);
6809 colon (mri_control_stack
->bottom
);
6815 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6816 ++input_line_pointer
;
6819 demand_empty_rest_of_line ();
6822 /* Handle the MRI REPEAT pseudo-op. */
6825 s_mri_repeat (ignore
)
6826 int ignore ATTRIBUTE_UNUSED
;
6828 struct mri_control_info
*n
;
6830 n
= push_mri_control (mri_repeat
);
6834 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6835 ++input_line_pointer
;
6837 demand_empty_rest_of_line ();
6840 /* Handle the MRI UNTIL pseudo-op. */
6848 if (mri_control_stack
== NULL
6849 || mri_control_stack
->type
!= mri_repeat
)
6851 as_bad (_("until without repeat"));
6852 ignore_rest_of_line ();
6856 colon (mri_control_stack
->next
);
6858 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
6861 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
6862 mri_control_stack
->top
, '\0');
6864 colon (mri_control_stack
->bottom
);
6866 input_line_pointer
= s
;
6872 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6873 ++input_line_pointer
;
6876 demand_empty_rest_of_line ();
6879 /* Handle the MRI WHILE pseudo-op. */
6887 struct mri_control_info
*n
;
6889 s
= input_line_pointer
;
6890 /* We only accept '*' as introduction of comments if preceded by white space
6891 or at first column of a line (I think this can't actually happen here?)
6892 This is important when assembling:
6893 while d0 <ne> 12(a0,d0*2) do
6894 while d0 <ne> #CONST*20 do. */
6895 while (! (is_end_of_line
[(unsigned char) *s
]
6898 && (s
== input_line_pointer
6900 || *(s
-1) == '\t'))))
6903 while (*s
== ' ' || *s
== '\t')
6905 if (s
- input_line_pointer
> 1
6908 if (s
- input_line_pointer
< 2
6909 || strncasecmp (s
- 1, "DO", 2) != 0)
6911 as_bad (_("missing do"));
6912 ignore_rest_of_line ();
6916 n
= push_mri_control (mri_while
);
6920 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
6921 s
[1] == '.' ? s
[2] : '\0');
6923 input_line_pointer
= s
+ 1;
6924 if (*input_line_pointer
== '.')
6925 input_line_pointer
+= 2;
6929 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6930 ++input_line_pointer
;
6933 demand_empty_rest_of_line ();
6936 /* Handle the MRI ENDW pseudo-op. */
6940 int ignore ATTRIBUTE_UNUSED
;
6944 if (mri_control_stack
== NULL
6945 || mri_control_stack
->type
!= mri_while
)
6947 as_bad (_("endw without while"));
6948 ignore_rest_of_line ();
6952 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->next
));
6953 sprintf (buf
, "bra %s", mri_control_stack
->next
);
6957 colon (mri_control_stack
->bottom
);
6963 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6964 ++input_line_pointer
;
6967 demand_empty_rest_of_line ();
6972 * Invocation line includes a switch not recognized by the base assembler.
6973 * See if it's a processor-specific option. These are:
6975 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6976 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6977 * Select the architecture. Instructions or features not
6978 * supported by the selected architecture cause fatal
6979 * errors. More than one may be specified. The default is
6980 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6981 * for -m68000, and -m68882 is a synonym for -m68881.
6982 * -[A]m[c]no-68851, -[A]m[c]no-68881
6983 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6984 * so don't use or document it, but that's the way the parsing
6987 * -pic Indicates PIC.
6988 * -k Indicates PIC. (Sun 3 only.)
6989 * --pcrel Never turn PC-relative branches into absolute jumps.
6992 * Permit `|' to be used in expressions.
6997 const char *md_shortopts
= "lSA:m:kQ:V";
6999 const char *md_shortopts
= "lSA:m:k";
7002 struct option md_longopts
[] = {
7003 #define OPTION_PIC (OPTION_MD_BASE)
7004 {"pic", no_argument
, NULL
, OPTION_PIC
},
7005 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7006 {"register-prefix-optional", no_argument
, NULL
,
7007 OPTION_REGISTER_PREFIX_OPTIONAL
},
7008 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7009 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
7010 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7011 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
7012 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7013 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
7014 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7015 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
7016 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7017 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
7018 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7019 {"pcrel", no_argument
, NULL
, OPTION_PCREL
},
7020 {NULL
, no_argument
, NULL
, 0}
7022 size_t md_longopts_size
= sizeof (md_longopts
);
7025 md_parse_option (c
, arg
)
7031 case 'l': /* -l means keep external to 2 bit offset
7032 rather than 16 bit one. */
7033 flag_short_refs
= 1;
7036 case 'S': /* -S means that jbsr's always turn into
7038 flag_long_jumps
= 1;
7041 case OPTION_PCREL
: /* --pcrel means never turn PC-relative
7042 branches into absolute jumps. */
7043 flag_keep_pcrel
= 1;
7049 /* Intentional fall-through. */
7052 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
7056 const char *oarg
= arg
;
7062 if (arg
[0] == 'c' && arg
[1] == '6')
7065 for (i
= 0; i
< n_archs
; i
++)
7066 if (!strcmp (arg
, archs
[i
].name
))
7071 as_bad (_("unrecognized option `%s'"), oarg
);
7074 arch
= archs
[i
].arch
;
7077 else if (arch
== m68851
)
7086 if (arg
[0] == 'c' && arg
[1] == '6')
7089 for (i
= 0; i
< n_archs
; i
++)
7090 if (!strcmp (arg
, archs
[i
].name
))
7092 unsigned long arch
= archs
[i
].arch
;
7093 if (cpu_of_arch (arch
))
7094 /* It's a cpu spec. */
7096 current_architecture
&= ~m68000up
;
7097 current_architecture
|= arch
;
7099 else if (arch
== m68881
)
7101 current_architecture
|= m68881
;
7104 else if (arch
== m68851
)
7106 current_architecture
|= m68851
;
7116 as_bad (_("unrecognized architecture specification `%s'"), arg
);
7125 break; /* -pic, Position Independent Code. */
7127 case OPTION_REGISTER_PREFIX_OPTIONAL
:
7128 flag_reg_prefix_optional
= 1;
7129 reg_prefix_optional_seen
= 1;
7132 /* -V: SVR4 argument to print version ID. */
7134 print_version_id ();
7137 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7138 should be emitted or not. FIXME: Not implemented. */
7142 case OPTION_BITWISE_OR
:
7147 n
= (char *) xmalloc (strlen (m68k_comment_chars
) + 1);
7149 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
7153 m68k_comment_chars
= n
;
7157 case OPTION_BASE_SIZE_DEFAULT_16
:
7158 m68k_index_width_default
= SIZE_WORD
;
7161 case OPTION_BASE_SIZE_DEFAULT_32
:
7162 m68k_index_width_default
= SIZE_LONG
;
7165 case OPTION_DISP_SIZE_DEFAULT_16
:
7167 m68k_rel32_from_cmdline
= 1;
7170 case OPTION_DISP_SIZE_DEFAULT_32
:
7172 m68k_rel32_from_cmdline
= 1;
7183 md_show_usage (stream
)
7186 const char *default_cpu
= TARGET_CPU
;
7188 unsigned int default_arch
;
7190 /* Get the canonical name for the default target CPU. */
7191 if (*default_cpu
== 'm')
7193 for (i
= 0; i
< n_archs
; i
++)
7195 if (strcasecmp (default_cpu
, archs
[i
].name
) == 0)
7197 default_arch
= archs
[i
].arch
;
7198 for (i
= 0; i
< n_archs
; i
++)
7200 if (archs
[i
].arch
== default_arch
7203 default_cpu
= archs
[i
].name
;
7210 fprintf (stream
, _("\
7212 -l use 1 word for refs to undefined symbols [default 2]\n\
7213 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
7214 -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
7215 -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m528x | -m5307 |\n\
7216 -m5407 | -mcfv4 | -mcfv4e\n\
7217 specify variant of 680X0 architecture [default %s]\n\
7218 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
7219 target has/lacks floating-point coprocessor\n\
7220 [default yes for 68020, 68030, and cpu32]\n"),
7222 fprintf (stream
, _("\
7223 -m68851 | -mno-68851\n\
7224 target has/lacks memory-management unit coprocessor\n\
7225 [default yes for 68020 and up]\n\
7226 -pic, -k generate position independent code\n\
7227 -S turn jbsr into jsr\n\
7228 --pcrel never turn PC-relative branches into absolute jumps\n\
7229 --register-prefix-optional\n\
7230 recognize register names without prefix character\n\
7231 --bitwise-or do not treat `|' as a comment character\n"));
7232 fprintf (stream
, _("\
7233 --base-size-default-16 base reg without size is 16 bits\n\
7234 --base-size-default-32 base reg without size is 32 bits (default)\n\
7235 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7236 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7241 /* TEST2: Test md_assemble() */
7242 /* Warning, this routine probably doesn't work anymore. */
7246 struct m68k_it the_ins
;
7254 if (!gets (buf
) || !*buf
)
7256 if (buf
[0] == '|' || buf
[1] == '.')
7258 for (cp
= buf
; *cp
; cp
++)
7263 memset (&the_ins
, '\0', sizeof (the_ins
));
7264 m68k_ip (&the_ins
, buf
);
7267 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
7271 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
7272 for (n
= 0; n
< the_ins
.numo
; n
++)
7273 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
7275 print_the_insn (&the_ins
.opcode
[0], stdout
);
7276 (void) putchar ('\n');
7278 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
7280 if (the_ins
.operands
[n
].error
)
7282 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
7285 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
, the_ins
.operands
[n
].reg
);
7286 if (the_ins
.operands
[n
].b_const
)
7287 printf ("Constant: '%.*s', ", 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
, the_ins
.operands
[n
].b_const
);
7288 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
, the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
7289 if (the_ins
.operands
[n
].b_iadd
)
7290 printf ("Iadd: '%.*s',", 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
, the_ins
.operands
[n
].b_iadd
);
7291 (void) putchar ('\n');
7303 while (*str
&& *str
!= ' ')
7305 if (str
[-1] == ':' || str
[1] == '=')
7312 /* Possible states for relaxation:
7314 0 0 branch offset byte (bra, etc)
7318 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7322 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7329 /* We have no need to default values of symbols. */
7332 md_undefined_symbol (name
)
7333 char *name ATTRIBUTE_UNUSED
;
7338 /* Round up a section size to the appropriate boundary. */
7340 md_section_align (segment
, size
)
7341 segT segment ATTRIBUTE_UNUSED
;
7345 #ifdef BFD_ASSEMBLER
7346 /* For a.out, force the section size to be aligned. If we don't do
7347 this, BFD will align it for us, but it will not write out the
7348 final bytes of the section. This may be a bug in BFD, but it is
7349 easier to fix it here since that is how the other a.out targets
7353 align
= bfd_get_section_alignment (stdoutput
, segment
);
7354 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7361 /* Exactly what point is a PC-relative offset relative TO?
7362 On the 68k, it is relative to the address of the first extension
7363 word. The difference between the addresses of the offset and the
7364 first extension word is stored in fx_pcrel_adjust. */
7366 md_pcrel_from (fixP
)
7371 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7372 sign extend the value here. */
7373 adjust
= ((fixP
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80;
7376 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
7379 #ifndef BFD_ASSEMBLER
7383 tc_coff_symbol_emit_hook (ignore
)
7384 symbolS
*ignore ATTRIBUTE_UNUSED
;
7389 tc_coff_sizemachdep (frag
)
7392 switch (frag
->fr_subtype
& 0x3)
7410 m68k_elf_final_processing ()
7412 /* Set file-specific flags if this is a cpu32 processor. */
7413 if (cpu_of_arch (current_architecture
) & cpu32
)
7414 elf_elfheader (stdoutput
)->e_flags
|= EF_CPU32
;
7415 else if ((cpu_of_arch (current_architecture
) & m68000up
)
7416 && !(cpu_of_arch (current_architecture
) & m68020up
))
7417 elf_elfheader (stdoutput
)->e_flags
|= EF_M68000
;
7422 tc_m68k_regname_to_dw2regnum (const char *regname
)
7424 unsigned int regnum
;
7425 static const char *const regnames
[] =
7427 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7428 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7429 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7433 for (regnum
= 0; regnum
< ARRAY_SIZE (regnames
); regnum
++)
7434 if (strcmp (regname
, regnames
[regnum
]) == 0)
7441 tc_m68k_frame_initial_instructions (void)
7443 static int sp_regno
= -1;
7446 sp_regno
= tc_m68k_regname_to_dw2regnum ("sp");
7448 cfi_add_CFA_def_cfa (sp_regno
, -DWARF2_CIE_DATA_ALIGNMENT
);
7449 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, DWARF2_CIE_DATA_ALIGNMENT
);