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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 1998
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 #include <ctype.h>
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if defined (TE_SVR4) || defined (TE_DELTA)
35 const char *m68k_comment_chars = "|#";
36 #else
37 const char *m68k_comment_chars = "|";
38 #endif
39
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars[] = "#*";
48
49 const char line_separator_chars[] = "";
50
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST char EXP_CHARS[] = "eE";
53
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
56
57 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
58
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
62
63 const int md_reloc_size = 8; /* Size of relocation record */
64
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
69 int flag_want_pic;
70
71 static int flag_short_refs; /* -l option */
72 static int flag_long_jumps; /* -S option */
73
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
76 #else
77 int flag_reg_prefix_optional;
78 #endif
79
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen;
82
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum = COP1;
85
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd;
89
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick = 1;
93
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
96 be 32 bits. */
97 static int m68k_rel32 = 1;
98
99 /* This is non-zero if m68k_rel32 was set from the command line. */
100 static int m68k_rel32_from_cmdline;
101
102 /* The default width to use for an index register when using a base
103 displacement. */
104 static enum m68k_size m68k_index_width_default = SIZE_LONG;
105
106 /* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
108 label. */
109
110 struct label_line
111 {
112 struct label_line *next;
113 symbolS *label;
114 char *file;
115 unsigned int line;
116 int text;
117 };
118
119 /* The list of labels. */
120
121 static struct label_line *labels;
122
123 /* The current label. */
124
125 static struct label_line *current_label;
126
127 /* Its an arbitrary name: This means I don't approve of it */
128 /* See flames below */
129 static struct obstack robyn;
130
131 #define TAB(x,y) (((x)<<2)+(y))
132 #define TABTYPE(xy) ((xy) >> 2)
133 #define BYTE 0
134 #define SHORT 1
135 #define LONG 2
136 #define SZ_UNDEF 3
137 #undef BRANCH
138 /* Case `g' except when BCC68000 is applicable. */
139 #define ABRANCH 1
140 /* Coprocessor branches. */
141 #define FBRANCH 2
142 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
144 #define PCREL 3
145 /* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
150 #define BCC68000 4
151 /* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
153 #define DBCC 5
154 /* Not currently used? */
155 #define PCLEA 6
156 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
157 in 16 or 8 bits. */
158 #define PCINDEX 7
159
160 struct m68k_incant
161 {
162 const char *m_operands;
163 unsigned long m_opcode;
164 short m_opnum;
165 short m_codenum;
166 int m_arch;
167 struct m68k_incant *m_next;
168 };
169
170 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171 #define gettwo(x) (((x)->m_opcode)&0xffff)
172
173 static const enum m68k_register m68000_control_regs[] = { 0 };
174 static const enum m68k_register m68010_control_regs[] = {
175 SFC, DFC, USP, VBR,
176 0
177 };
178 static const enum m68k_register m68020_control_regs[] = {
179 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
180 0
181 };
182 static const enum m68k_register m68040_control_regs[] = {
183 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
184 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
185 0
186 };
187 static const enum m68k_register m68060_control_regs[] = {
188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
189 USP, VBR, URP, SRP, PCR,
190 0
191 };
192 static const enum m68k_register mcf5200_control_regs[] = {
193 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
194 RAMBAR0, RAMBAR1, MBAR,
195 0
196 };
197 #define cpu32_control_regs m68010_control_regs
198
199 static const enum m68k_register *control_regs;
200
201 /* internal form of a 68020 instruction */
202 struct m68k_it
203 {
204 const char *error;
205 const char *args; /* list of opcode info */
206 int numargs;
207
208 int numo; /* Number of shorts in opcode */
209 short opcode[11];
210
211 struct m68k_op operands[6];
212
213 int nexp; /* number of exprs in use */
214 struct m68k_exp exprs[4];
215
216 int nfrag; /* Number of frags we have to produce */
217 struct
218 {
219 int fragoff; /* Where in the current opcode the frag ends */
220 symbolS *fadd;
221 offsetT foff;
222 int fragty;
223 }
224 fragb[4];
225
226 int nrel; /* Num of reloc strucs in use */
227 struct
228 {
229 int n;
230 expressionS exp;
231 char wid;
232 char pcrel;
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
239 example). */
240 int pcrel_fix;
241 #ifdef OBJ_ELF
242 /* Whether this expression needs special pic relocation, and if
243 so, which. */
244 enum pic_relocation pic_reloc;
245 #endif
246 }
247 reloc[5]; /* Five is enough??? */
248 };
249
250 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
251 #define float_of_arch(x) ((x) & mfloat)
252 #define mmu_of_arch(x) ((x) & mmmu)
253
254 /* Macros for determining if cpu supports a specific addressing mode */
255 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
256
257 static struct m68k_it the_ins; /* the instruction being assembled */
258
259 #define op(ex) ((ex)->exp.X_op)
260 #define adds(ex) ((ex)->exp.X_add_symbol)
261 #define subs(ex) ((ex)->exp.X_op_symbol)
262 #define offs(ex) ((ex)->exp.X_add_number)
263
264 /* Macros for adding things to the m68k_it struct */
265
266 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
267
268 /* Static functions. */
269
270 static void insop PARAMS ((int, const struct m68k_incant *));
271 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
272 static void add_frag PARAMS ((symbolS *, offsetT, int));
273
274 /* Like addword, but goes BEFORE general operands */
275 static void
276 insop (w, opcode)
277 int w;
278 const struct m68k_incant *opcode;
279 {
280 int z;
281 for(z=the_ins.numo;z>opcode->m_codenum;--z)
282 the_ins.opcode[z]=the_ins.opcode[z-1];
283 for(z=0;z<the_ins.nrel;z++)
284 the_ins.reloc[z].n+=2;
285 for (z = 0; z < the_ins.nfrag; z++)
286 the_ins.fragb[z].fragoff++;
287 the_ins.opcode[opcode->m_codenum]=w;
288 the_ins.numo++;
289 }
290
291 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
292 Blecch. */
293 static void
294 add_fix (width, exp, pc_rel, pc_fix)
295 int width;
296 struct m68k_exp *exp;
297 int pc_rel;
298 int pc_fix;
299 {
300 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
301 ? (the_ins.numo*2-1)
302 : (((width)=='b')
303 ? (the_ins.numo*2+1)
304 : (the_ins.numo*2)));
305 the_ins.reloc[the_ins.nrel].exp = exp->exp;
306 the_ins.reloc[the_ins.nrel].wid = width;
307 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
308 #ifdef OBJ_ELF
309 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
310 #endif
311 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
312 }
313
314 /* Cause an extra frag to be generated here, inserting up to 10 bytes
315 (that value is chosen in the frag_var call in md_assemble). TYPE
316 is the subtype of the frag to be generated; its primary type is
317 rs_machine_dependent.
318
319 The TYPE parameter is also used by md_convert_frag_1 and
320 md_estimate_size_before_relax. The appropriate type of fixup will
321 be emitted by md_convert_frag_1.
322
323 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
324 static void
325 add_frag (add, off, type)
326 symbolS *add;
327 offsetT off;
328 int type;
329 {
330 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
331 the_ins.fragb[the_ins.nfrag].fadd=add;
332 the_ins.fragb[the_ins.nfrag].foff=off;
333 the_ins.fragb[the_ins.nfrag++].fragty=type;
334 }
335
336 #define isvar(ex) \
337 (op (ex) != O_constant && op (ex) != O_big)
338
339 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
340 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
341 static void m68k_ip PARAMS ((char *));
342 static void insert_reg PARAMS ((const char *, int));
343 static void select_control_regs PARAMS ((void));
344 static void init_regtable PARAMS ((void));
345 static int reverse_16_bits PARAMS ((int in));
346 static int reverse_8_bits PARAMS ((int in));
347 static void install_gen_operand PARAMS ((int mode, int val));
348 static void install_operand PARAMS ((int mode, int val));
349 static void s_bss PARAMS ((int));
350 static void s_data1 PARAMS ((int));
351 static void s_data2 PARAMS ((int));
352 static void s_even PARAMS ((int));
353 static void s_proc PARAMS ((int));
354 static void mri_chip PARAMS ((void));
355 static void s_chip PARAMS ((int));
356 static void s_fopt PARAMS ((int));
357 static void s_opt PARAMS ((int));
358 static void s_reg PARAMS ((int));
359 static void s_restore PARAMS ((int));
360 static void s_save PARAMS ((int));
361 static void s_mri_if PARAMS ((int));
362 static void s_mri_else PARAMS ((int));
363 static void s_mri_endi PARAMS ((int));
364 static void s_mri_break PARAMS ((int));
365 static void s_mri_next PARAMS ((int));
366 static void s_mri_for PARAMS ((int));
367 static void s_mri_endf PARAMS ((int));
368 static void s_mri_repeat PARAMS ((int));
369 static void s_mri_until PARAMS ((int));
370 static void s_mri_while PARAMS ((int));
371 static void s_mri_endw PARAMS ((int));
372 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
373 static void md_convert_frag_1 PARAMS ((fragS *));
374
375 static int current_architecture;
376
377 struct m68k_cpu {
378 unsigned long arch;
379 const char *name;
380 int alias;
381 };
382
383 static const struct m68k_cpu archs[] = {
384 { m68000, "68000", 0 },
385 { m68010, "68010", 0 },
386 { m68020, "68020", 0 },
387 { m68030, "68030", 0 },
388 { m68040, "68040", 0 },
389 { m68060, "68060", 0 },
390 { cpu32, "cpu32", 0 },
391 { m68881, "68881", 0 },
392 { m68851, "68851", 0 },
393 { mcf5200, "5200", 0 },
394 /* Aliases (effectively, so far as gas is concerned) for the above
395 cpus. */
396 { m68020, "68k", 1 },
397 { m68000, "68008", 1 },
398 { m68000, "68302", 1 },
399 { m68000, "68306", 1 },
400 { m68000, "68307", 1 },
401 { m68000, "68322", 1 },
402 { m68000, "68356", 1 },
403 { m68000, "68ec000", 1 },
404 { m68000, "68hc000", 1 },
405 { m68000, "68hc001", 1 },
406 { m68020, "68ec020", 1 },
407 { m68030, "68ec030", 1 },
408 { m68040, "68ec040", 1 },
409 { m68060, "68ec060", 1 },
410 { cpu32, "68330", 1 },
411 { cpu32, "68331", 1 },
412 { cpu32, "68332", 1 },
413 { cpu32, "68333", 1 },
414 { cpu32, "68334", 1 },
415 { cpu32, "68336", 1 },
416 { cpu32, "68340", 1 },
417 { cpu32, "68341", 1 },
418 { cpu32, "68349", 1 },
419 { cpu32, "68360", 1 },
420 { m68881, "68882", 1 },
421 };
422
423 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
424
425 /* BCC68000 is for patching in an extra jmp instruction for long offsets
426 on the 68000. The 68000 doesn't support long branches with branchs */
427
428 /* This table desribes how you change sizes for the various types of variable
429 size expressions. This version only supports two kinds. */
430
431 /* Note that calls to frag_var need to specify the maximum expansion
432 needed; this is currently 10 bytes for DBCC. */
433
434 /* The fields are:
435 How far Forward this mode will reach:
436 How far Backward this mode will reach:
437 How many bytes this mode will add to the size of the frag
438 Which mode to go to if the offset won't fit in this one
439 */
440 relax_typeS md_relax_table[] =
441 {
442 {1, 1, 0, 0}, /* First entries aren't used */
443 {1, 1, 0, 0}, /* For no good reason except */
444 {1, 1, 0, 0}, /* that the VAX doesn't either */
445 {1, 1, 0, 0},
446
447 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
448 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
449 {0, 0, 4, 0},
450 {1, 1, 0, 0},
451
452 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
453 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
454 {0, 0, 4, 0},
455 {1, 1, 0, 0},
456
457 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
458 {(32767), (-32768), 2, TAB (PCREL, LONG)},
459 {0, 0, 4, 0},
460 {1, 1, 0, 0},
461
462 {(127), (-128), 0, TAB (BCC68000, SHORT)},
463 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
464 {0, 0, 6, 0}, /* jmp long space */
465 {1, 1, 0, 0},
466
467 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
468 {(32767), (-32768), 2, TAB (DBCC, LONG)},
469 {0, 0, 10, 0}, /* bra/jmp long space */
470 {1, 1, 0, 0},
471
472 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
473 {32767, -32768, 2, TAB (PCLEA, LONG)},
474 {0, 0, 6, 0},
475 {1, 1, 0, 0},
476
477 /* For, e.g., jmp pcrel indexed. */
478 {125, -130, 0, TAB (PCINDEX, SHORT)},
479 {32765, -32770, 2, TAB (PCINDEX, LONG)},
480 {0, 0, 4, 0},
481 {1, 1, 0, 0},
482 };
483
484 /* These are the machine dependent pseudo-ops. These are included so
485 the assembler can work on the output from the SUN C compiler, which
486 generates these.
487 */
488
489 /* This table describes all the machine specific pseudo-ops the assembler
490 has to support. The fields are:
491 pseudo-op name without dot
492 function to call to execute this pseudo-op
493 Integer arg to pass to the function
494 */
495 const pseudo_typeS md_pseudo_table[] =
496 {
497 {"data1", s_data1, 0},
498 {"data2", s_data2, 0},
499 {"bss", s_bss, 0},
500 {"even", s_even, 0},
501 {"skip", s_space, 0},
502 {"proc", s_proc, 0},
503 #if defined (TE_SUN3) || defined (OBJ_ELF)
504 {"align", s_align_bytes, 0},
505 #endif
506 #ifdef OBJ_ELF
507 {"swbeg", s_ignore, 0},
508 #endif
509 {"extend", float_cons, 'x'},
510 {"ldouble", float_cons, 'x'},
511
512 /* The following pseudo-ops are supported for MRI compatibility. */
513 {"chip", s_chip, 0},
514 {"comline", s_space, 1},
515 {"fopt", s_fopt, 0},
516 {"mask2", s_ignore, 0},
517 {"opt", s_opt, 0},
518 {"reg", s_reg, 0},
519 {"restore", s_restore, 0},
520 {"save", s_save, 0},
521
522 {"if", s_mri_if, 0},
523 {"if.b", s_mri_if, 'b'},
524 {"if.w", s_mri_if, 'w'},
525 {"if.l", s_mri_if, 'l'},
526 {"else", s_mri_else, 0},
527 {"else.s", s_mri_else, 's'},
528 {"else.l", s_mri_else, 'l'},
529 {"endi", s_mri_endi, 0},
530 {"break", s_mri_break, 0},
531 {"break.s", s_mri_break, 's'},
532 {"break.l", s_mri_break, 'l'},
533 {"next", s_mri_next, 0},
534 {"next.s", s_mri_next, 's'},
535 {"next.l", s_mri_next, 'l'},
536 {"for", s_mri_for, 0},
537 {"for.b", s_mri_for, 'b'},
538 {"for.w", s_mri_for, 'w'},
539 {"for.l", s_mri_for, 'l'},
540 {"endf", s_mri_endf, 0},
541 {"repeat", s_mri_repeat, 0},
542 {"until", s_mri_until, 0},
543 {"until.b", s_mri_until, 'b'},
544 {"until.w", s_mri_until, 'w'},
545 {"until.l", s_mri_until, 'l'},
546 {"while", s_mri_while, 0},
547 {"while.b", s_mri_while, 'b'},
548 {"while.w", s_mri_while, 'w'},
549 {"while.l", s_mri_while, 'l'},
550 {"endw", s_mri_endw, 0},
551
552 {0, 0, 0}
553 };
554
555
556 /* The mote pseudo ops are put into the opcode table, since they
557 don't start with a . they look like opcodes to gas.
558 */
559
560 #ifdef M68KCOFF
561 extern void obj_coff_section PARAMS ((int));
562 #endif
563
564 CONST pseudo_typeS mote_pseudo_table[] =
565 {
566
567 {"dcl", cons, 4},
568 {"dc", cons, 2},
569 {"dcw", cons, 2},
570 {"dcb", cons, 1},
571
572 {"dsl", s_space, 4},
573 {"ds", s_space, 2},
574 {"dsw", s_space, 2},
575 {"dsb", s_space, 1},
576
577 {"xdef", s_globl, 0},
578 #ifdef OBJ_ELF
579 {"align", s_align_bytes, 0},
580 #else
581 {"align", s_align_ptwo, 0},
582 #endif
583 #ifdef M68KCOFF
584 {"sect", obj_coff_section, 0},
585 {"section", obj_coff_section, 0},
586 #endif
587 {0, 0, 0}
588 };
589
590 #define issbyte(x) ((x)>=-128 && (x)<=127)
591 #define isubyte(x) ((x)>=0 && (x)<=255)
592 #define issword(x) ((x)>=-32768 && (x)<=32767)
593 #define isuword(x) ((x)>=0 && (x)<=65535)
594
595 #define isbyte(x) ((x)>= -255 && (x)<=255)
596 #define isword(x) ((x)>=-65536 && (x)<=65535)
597 #define islong(x) (1)
598
599 extern char *input_line_pointer;
600
601 static char mklower_table[256];
602 #define mklower(c) (mklower_table[(unsigned char)(c)])
603 static char notend_table[256];
604 static char alt_notend_table[256];
605 #define notend(s) \
606 (! (notend_table[(unsigned char) *s] \
607 || (*s == ':' \
608 && alt_notend_table[(unsigned char) s[1]])))
609
610 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
611
612 #ifdef NO_PCREL_RELOCS
613
614 int
615 make_pcrel_absolute(fixP, add_number)
616 fixS *fixP;
617 long *add_number;
618 {
619 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
620
621 /* rewrite the PC relative instructions to absolute address ones.
622 * these are rumoured to be faster, and the apollo linker refuses
623 * to deal with the PC relative relocations.
624 */
625 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
626 {
627 opcode[0] = 0x4e;
628 opcode[1] = 0xf9;
629 }
630 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
631 {
632 opcode[0] = 0x4e;
633 opcode[1] = 0xb9;
634 }
635 else
636 as_fatal (_("Unknown PC relative instruction"));
637 *add_number -= 4;
638 return 0;
639 }
640
641 #endif /* NO_PCREL_RELOCS */
642
643 short
644 tc_coff_fix2rtype (fixP)
645 fixS *fixP;
646 {
647 if (fixP->fx_tcbit && fixP->fx_size == 4)
648 return R_RELLONG_NEG;
649 #ifdef NO_PCREL_RELOCS
650 know (fixP->fx_pcrel == 0);
651 return (fixP->fx_size == 1 ? R_RELBYTE
652 : fixP->fx_size == 2 ? R_DIR16
653 : R_DIR32);
654 #else
655 return (fixP->fx_pcrel ?
656 (fixP->fx_size == 1 ? R_PCRBYTE :
657 fixP->fx_size == 2 ? R_PCRWORD :
658 R_PCRLONG) :
659 (fixP->fx_size == 1 ? R_RELBYTE :
660 fixP->fx_size == 2 ? R_RELWORD :
661 R_RELLONG));
662 #endif
663 }
664
665 #endif
666
667 #ifdef OBJ_ELF
668
669 /* Compute the relocation code for a fixup of SIZE bytes, using pc
670 relative relocation if PCREL is non-zero. PIC says whether a special
671 pic relocation was requested. */
672
673 static bfd_reloc_code_real_type get_reloc_code
674 PARAMS ((int, int, enum pic_relocation));
675
676 static bfd_reloc_code_real_type
677 get_reloc_code (size, pcrel, pic)
678 int size;
679 int pcrel;
680 enum pic_relocation pic;
681 {
682 switch (pic)
683 {
684 case pic_got_pcrel:
685 switch (size)
686 {
687 case 1:
688 return BFD_RELOC_8_GOT_PCREL;
689 case 2:
690 return BFD_RELOC_16_GOT_PCREL;
691 case 4:
692 return BFD_RELOC_32_GOT_PCREL;
693 }
694 break;
695
696 case pic_got_off:
697 switch (size)
698 {
699 case 1:
700 return BFD_RELOC_8_GOTOFF;
701 case 2:
702 return BFD_RELOC_16_GOTOFF;
703 case 4:
704 return BFD_RELOC_32_GOTOFF;
705 }
706 break;
707
708 case pic_plt_pcrel:
709 switch (size)
710 {
711 case 1:
712 return BFD_RELOC_8_PLT_PCREL;
713 case 2:
714 return BFD_RELOC_16_PLT_PCREL;
715 case 4:
716 return BFD_RELOC_32_PLT_PCREL;
717 }
718 break;
719
720 case pic_plt_off:
721 switch (size)
722 {
723 case 1:
724 return BFD_RELOC_8_PLTOFF;
725 case 2:
726 return BFD_RELOC_16_PLTOFF;
727 case 4:
728 return BFD_RELOC_32_PLTOFF;
729 }
730 break;
731
732 case pic_none:
733 if (pcrel)
734 {
735 switch (size)
736 {
737 case 1:
738 return BFD_RELOC_8_PCREL;
739 case 2:
740 return BFD_RELOC_16_PCREL;
741 case 4:
742 return BFD_RELOC_32_PCREL;
743 }
744 }
745 else
746 {
747 switch (size)
748 {
749 case 1:
750 return BFD_RELOC_8;
751 case 2:
752 return BFD_RELOC_16;
753 case 4:
754 return BFD_RELOC_32;
755 }
756 }
757 }
758
759 if (pcrel)
760 {
761 if (pic == pic_none)
762 as_bad (_("Can not do %d byte pc-relative relocation"), size);
763 else
764 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
765 }
766 else
767 {
768 if (pic == pic_none)
769 as_bad (_("Can not do %d byte relocation"), size);
770 else
771 as_bad (_("Can not do %d byte pic relocation"), size);
772 }
773
774 return BFD_RELOC_NONE;
775 }
776
777 /* Here we decide which fixups can be adjusted to make them relative
778 to the beginning of the section instead of the symbol. Basically
779 we need to make sure that the dynamic relocations are done
780 correctly, so in some cases we force the original symbol to be
781 used. */
782 int
783 tc_m68k_fix_adjustable (fixP)
784 fixS *fixP;
785 {
786 /* Prevent all adjustments to global symbols. */
787 if (S_IS_EXTERNAL (fixP->fx_addsy))
788 return 0;
789
790 /* adjust_reloc_syms doesn't know about the GOT */
791 switch (fixP->fx_r_type)
792 {
793 case BFD_RELOC_8_GOT_PCREL:
794 case BFD_RELOC_16_GOT_PCREL:
795 case BFD_RELOC_32_GOT_PCREL:
796 case BFD_RELOC_8_GOTOFF:
797 case BFD_RELOC_16_GOTOFF:
798 case BFD_RELOC_32_GOTOFF:
799 case BFD_RELOC_8_PLT_PCREL:
800 case BFD_RELOC_16_PLT_PCREL:
801 case BFD_RELOC_32_PLT_PCREL:
802 case BFD_RELOC_8_PLTOFF:
803 case BFD_RELOC_16_PLTOFF:
804 case BFD_RELOC_32_PLTOFF:
805 return 0;
806
807 default:
808 return 1;
809 }
810 }
811
812 #else /* !OBJ_ELF */
813
814 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
815
816 #endif /* OBJ_ELF */
817
818 #ifdef BFD_ASSEMBLER
819
820 arelent *
821 tc_gen_reloc (section, fixp)
822 asection *section;
823 fixS *fixp;
824 {
825 arelent *reloc;
826 bfd_reloc_code_real_type code;
827
828 if (fixp->fx_tcbit)
829 abort ();
830
831 if (fixp->fx_r_type != BFD_RELOC_NONE)
832 {
833 code = fixp->fx_r_type;
834
835 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
836 that fixup_segment converted a non-PC relative reloc into a
837 PC relative reloc. In such a case, we need to convert the
838 reloc code. */
839 if (fixp->fx_pcrel)
840 {
841 switch (code)
842 {
843 case BFD_RELOC_8:
844 code = BFD_RELOC_8_PCREL;
845 break;
846 case BFD_RELOC_16:
847 code = BFD_RELOC_16_PCREL;
848 break;
849 case BFD_RELOC_32:
850 code = BFD_RELOC_32_PCREL;
851 break;
852 case BFD_RELOC_8_PCREL:
853 case BFD_RELOC_16_PCREL:
854 case BFD_RELOC_32_PCREL:
855 case BFD_RELOC_8_GOT_PCREL:
856 case BFD_RELOC_16_GOT_PCREL:
857 case BFD_RELOC_32_GOT_PCREL:
858 case BFD_RELOC_8_GOTOFF:
859 case BFD_RELOC_16_GOTOFF:
860 case BFD_RELOC_32_GOTOFF:
861 case BFD_RELOC_8_PLT_PCREL:
862 case BFD_RELOC_16_PLT_PCREL:
863 case BFD_RELOC_32_PLT_PCREL:
864 case BFD_RELOC_8_PLTOFF:
865 case BFD_RELOC_16_PLTOFF:
866 case BFD_RELOC_32_PLTOFF:
867 break;
868 default:
869 as_bad_where (fixp->fx_file, fixp->fx_line,
870 _("Cannot make %s relocation PC relative"),
871 bfd_get_reloc_code_name (code));
872 }
873 }
874 }
875 else
876 {
877 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
878 switch (F (fixp->fx_size, fixp->fx_pcrel))
879 {
880 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
881 MAP (1, 0, BFD_RELOC_8);
882 MAP (2, 0, BFD_RELOC_16);
883 MAP (4, 0, BFD_RELOC_32);
884 MAP (1, 1, BFD_RELOC_8_PCREL);
885 MAP (2, 1, BFD_RELOC_16_PCREL);
886 MAP (4, 1, BFD_RELOC_32_PCREL);
887 default:
888 abort ();
889 }
890 }
891 #undef F
892 #undef MAP
893
894 reloc = (arelent *) xmalloc (sizeof (arelent));
895 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
896 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
897 #ifndef OBJ_ELF
898 if (fixp->fx_pcrel)
899 reloc->addend = fixp->fx_addnumber;
900 else
901 reloc->addend = 0;
902 #else
903 if (!fixp->fx_pcrel)
904 reloc->addend = fixp->fx_addnumber;
905 else
906 reloc->addend = (section->vma
907 + (fixp->fx_pcrel_adjust == 64
908 ? -1 : fixp->fx_pcrel_adjust)
909 + fixp->fx_addnumber
910 + md_pcrel_from (fixp));
911 #endif
912
913 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
914 assert (reloc->howto != 0);
915
916 return reloc;
917 }
918
919 #endif /* BFD_ASSEMBLER */
920
921 /* Handle of the OPCODE hash table. NULL means any use before
922 m68k_ip_begin() will crash. */
923 static struct hash_control *op_hash;
924 \f
925 /* Assemble an m68k instruction. */
926
927 static void
928 m68k_ip (instring)
929 char *instring;
930 {
931 register char *p;
932 register struct m68k_op *opP;
933 register const struct m68k_incant *opcode;
934 register const char *s;
935 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
936 char *pdot, *pdotmove;
937 enum m68k_size siz1, siz2;
938 char c;
939 int losing;
940 int opsfound;
941 LITTLENUM_TYPE words[6];
942 LITTLENUM_TYPE *wordp;
943 unsigned long ok_arch = 0;
944
945 if (*instring == ' ')
946 instring++; /* skip leading whitespace */
947
948 /* Scan up to end of operation-code, which MUST end in end-of-string
949 or exactly 1 space. */
950 pdot = 0;
951 for (p = instring; *p != '\0'; p++)
952 {
953 if (*p == ' ')
954 break;
955 if (*p == '.')
956 pdot = p;
957 }
958
959 if (p == instring)
960 {
961 the_ins.error = _("No operator");
962 return;
963 }
964
965 /* p now points to the end of the opcode name, probably whitespace.
966 Make sure the name is null terminated by clobbering the
967 whitespace, look it up in the hash table, then fix it back.
968 Remove a dot, first, since the opcode tables have none. */
969 if (pdot != NULL)
970 {
971 for (pdotmove = pdot; pdotmove < p; pdotmove++)
972 *pdotmove = pdotmove[1];
973 p--;
974 }
975
976 c = *p;
977 *p = '\0';
978 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
979 *p = c;
980
981 if (pdot != NULL)
982 {
983 for (pdotmove = p; pdotmove > pdot; pdotmove--)
984 *pdotmove = pdotmove[-1];
985 *pdot = '.';
986 ++p;
987 }
988
989 if (opcode == NULL)
990 {
991 the_ins.error = _("Unknown operator");
992 return;
993 }
994
995 /* found a legitimate opcode, start matching operands */
996 while (*p == ' ')
997 ++p;
998
999 if (opcode->m_operands == 0)
1000 {
1001 char *old = input_line_pointer;
1002 *old = '\n';
1003 input_line_pointer = p;
1004 /* Ahh - it's a motorola style psuedo op */
1005 mote_pseudo_table[opcode->m_opnum].poc_handler
1006 (mote_pseudo_table[opcode->m_opnum].poc_val);
1007 input_line_pointer = old;
1008 *old = 0;
1009
1010 return;
1011 }
1012
1013 if (flag_mri && opcode->m_opnum == 0)
1014 {
1015 /* In MRI mode, random garbage is allowed after an instruction
1016 which accepts no operands. */
1017 the_ins.args = opcode->m_operands;
1018 the_ins.numargs = opcode->m_opnum;
1019 the_ins.numo = opcode->m_codenum;
1020 the_ins.opcode[0] = getone (opcode);
1021 the_ins.opcode[1] = gettwo (opcode);
1022 return;
1023 }
1024
1025 for (opP = &the_ins.operands[0]; *p; opP++)
1026 {
1027 p = crack_operand (p, opP);
1028
1029 if (opP->error)
1030 {
1031 the_ins.error = opP->error;
1032 return;
1033 }
1034 }
1035
1036 opsfound = opP - &the_ins.operands[0];
1037
1038 /* This ugly hack is to support the floating pt opcodes in their
1039 standard form. Essentially, we fake a first enty of type COP#1 */
1040 if (opcode->m_operands[0] == 'I')
1041 {
1042 int n;
1043
1044 for (n = opsfound; n > 0; --n)
1045 the_ins.operands[n] = the_ins.operands[n - 1];
1046
1047 memset ((char *) (&the_ins.operands[0]), '\0',
1048 sizeof (the_ins.operands[0]));
1049 the_ins.operands[0].mode = CONTROL;
1050 the_ins.operands[0].reg = m68k_float_copnum;
1051 opsfound++;
1052 }
1053
1054 /* We've got the operands. Find an opcode that'll accept them */
1055 for (losing = 0;;)
1056 {
1057 /* If we didn't get the right number of ops, or we have no
1058 common model with this pattern then reject this pattern. */
1059
1060 ok_arch |= opcode->m_arch;
1061 if (opsfound != opcode->m_opnum
1062 || ((opcode->m_arch & current_architecture) == 0))
1063 ++losing;
1064 else
1065 {
1066 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1067 *s && !losing;
1068 s += 2, opP++)
1069 {
1070 /* Warning: this switch is huge! */
1071 /* I've tried to organize the cases into this order:
1072 non-alpha first, then alpha by letter. Lower-case
1073 goes directly before uppercase counterpart. */
1074 /* Code with multiple case ...: gets sorted by the lowest
1075 case ... it belongs to. I hope this makes sense. */
1076 switch (*s)
1077 {
1078 case '!':
1079 switch (opP->mode)
1080 {
1081 case IMMED:
1082 case DREG:
1083 case AREG:
1084 case FPREG:
1085 case CONTROL:
1086 case AINC:
1087 case ADEC:
1088 case REGLST:
1089 losing++;
1090 break;
1091 default:
1092 break;
1093 }
1094 break;
1095
1096 case '<':
1097 switch (opP->mode)
1098 {
1099 case DREG:
1100 case AREG:
1101 case FPREG:
1102 case CONTROL:
1103 case IMMED:
1104 case ADEC:
1105 case REGLST:
1106 losing++;
1107 break;
1108 default:
1109 break;
1110 }
1111 break;
1112
1113 case '>':
1114 switch (opP->mode)
1115 {
1116 case DREG:
1117 case AREG:
1118 case FPREG:
1119 case CONTROL:
1120 case IMMED:
1121 case AINC:
1122 case REGLST:
1123 losing++;
1124 break;
1125 case ABSL:
1126 break;
1127 default:
1128 if (opP->reg == PC
1129 || opP->reg == ZPC)
1130 losing++;
1131 break;
1132 }
1133 break;
1134
1135 case 'm':
1136 switch (opP->mode)
1137 {
1138 case DREG:
1139 case AREG:
1140 case AINDR:
1141 case AINC:
1142 case ADEC:
1143 break;
1144 default:
1145 losing++;
1146 }
1147 break;
1148
1149 case 'n':
1150 switch (opP->mode)
1151 {
1152 case DISP:
1153 break;
1154 default:
1155 losing++;
1156 }
1157 break;
1158
1159 case 'o':
1160 switch (opP->mode)
1161 {
1162 case BASE:
1163 case ABSL:
1164 case IMMED:
1165 break;
1166 default:
1167 losing++;
1168 }
1169 break;
1170
1171 case 'p':
1172 switch (opP->mode)
1173 {
1174 case DREG:
1175 case AREG:
1176 case AINDR:
1177 case AINC:
1178 case ADEC:
1179 break;
1180 case DISP:
1181 if (opP->reg == PC || opP->reg == ZPC)
1182 losing++;
1183 break;
1184 default:
1185 losing++;
1186 }
1187 break;
1188
1189 case 'q':
1190 switch (opP->mode)
1191 {
1192 case DREG:
1193 case AINDR:
1194 case AINC:
1195 case ADEC:
1196 break;
1197 case DISP:
1198 if (opP->reg == PC || opP->reg == ZPC)
1199 losing++;
1200 break;
1201 default:
1202 losing++;
1203 break;
1204 }
1205 break;
1206
1207 case 'v':
1208 switch (opP->mode)
1209 {
1210 case DREG:
1211 case AINDR:
1212 case AINC:
1213 case ADEC:
1214 case ABSL:
1215 break;
1216 case DISP:
1217 if (opP->reg == PC || opP->reg == ZPC)
1218 losing++;
1219 break;
1220 default:
1221 losing++;
1222 break;
1223 }
1224 break;
1225
1226 case '#':
1227 if (opP->mode != IMMED)
1228 losing++;
1229 else if (s[1] == 'b'
1230 && ! isvar (&opP->disp)
1231 && (opP->disp.exp.X_op != O_constant
1232 || ! isbyte (opP->disp.exp.X_add_number)))
1233 losing++;
1234 else if (s[1] == 'B'
1235 && ! isvar (&opP->disp)
1236 && (opP->disp.exp.X_op != O_constant
1237 || ! issbyte (opP->disp.exp.X_add_number)))
1238 losing++;
1239 else if (s[1] == 'w'
1240 && ! isvar (&opP->disp)
1241 && (opP->disp.exp.X_op != O_constant
1242 || ! isword (opP->disp.exp.X_add_number)))
1243 losing++;
1244 else if (s[1] == 'W'
1245 && ! isvar (&opP->disp)
1246 && (opP->disp.exp.X_op != O_constant
1247 || ! issword (opP->disp.exp.X_add_number)))
1248 losing++;
1249 break;
1250
1251 case '^':
1252 case 'T':
1253 if (opP->mode != IMMED)
1254 losing++;
1255 break;
1256
1257 case '$':
1258 if (opP->mode == AREG
1259 || opP->mode == CONTROL
1260 || opP->mode == FPREG
1261 || opP->mode == IMMED
1262 || opP->mode == REGLST
1263 || (opP->mode != ABSL
1264 && (opP->reg == PC
1265 || opP->reg == ZPC)))
1266 losing++;
1267 break;
1268
1269 case '%':
1270 if (opP->mode == CONTROL
1271 || opP->mode == FPREG
1272 || opP->mode == REGLST
1273 || opP->mode == IMMED
1274 || (opP->mode != ABSL
1275 && (opP->reg == PC
1276 || opP->reg == ZPC)))
1277 losing++;
1278 break;
1279
1280 case '&':
1281 switch (opP->mode)
1282 {
1283 case DREG:
1284 case AREG:
1285 case FPREG:
1286 case CONTROL:
1287 case IMMED:
1288 case AINC:
1289 case ADEC:
1290 case REGLST:
1291 losing++;
1292 break;
1293 case ABSL:
1294 break;
1295 default:
1296 if (opP->reg == PC
1297 || opP->reg == ZPC)
1298 losing++;
1299 break;
1300 }
1301 break;
1302
1303 case '*':
1304 if (opP->mode == CONTROL
1305 || opP->mode == FPREG
1306 || opP->mode == REGLST)
1307 losing++;
1308 break;
1309
1310 case '+':
1311 if (opP->mode != AINC)
1312 losing++;
1313 break;
1314
1315 case '-':
1316 if (opP->mode != ADEC)
1317 losing++;
1318 break;
1319
1320 case '/':
1321 switch (opP->mode)
1322 {
1323 case AREG:
1324 case CONTROL:
1325 case FPREG:
1326 case AINC:
1327 case ADEC:
1328 case IMMED:
1329 case REGLST:
1330 losing++;
1331 break;
1332 default:
1333 break;
1334 }
1335 break;
1336
1337 case ';':
1338 switch (opP->mode)
1339 {
1340 case AREG:
1341 case CONTROL:
1342 case FPREG:
1343 case REGLST:
1344 losing++;
1345 break;
1346 default:
1347 break;
1348 }
1349 break;
1350
1351 case '?':
1352 switch (opP->mode)
1353 {
1354 case AREG:
1355 case CONTROL:
1356 case FPREG:
1357 case AINC:
1358 case ADEC:
1359 case IMMED:
1360 case REGLST:
1361 losing++;
1362 break;
1363 case ABSL:
1364 break;
1365 default:
1366 if (opP->reg == PC || opP->reg == ZPC)
1367 losing++;
1368 break;
1369 }
1370 break;
1371
1372 case '@':
1373 switch (opP->mode)
1374 {
1375 case AREG:
1376 case CONTROL:
1377 case FPREG:
1378 case IMMED:
1379 case REGLST:
1380 losing++;
1381 break;
1382 default:
1383 break;
1384 }
1385 break;
1386
1387 case '~': /* For now! (JF FOO is this right?) */
1388 switch (opP->mode)
1389 {
1390 case DREG:
1391 case AREG:
1392 case CONTROL:
1393 case FPREG:
1394 case IMMED:
1395 case REGLST:
1396 losing++;
1397 break;
1398 case ABSL:
1399 break;
1400 default:
1401 if (opP->reg == PC
1402 || opP->reg == ZPC)
1403 losing++;
1404 break;
1405 }
1406 break;
1407
1408 case '3':
1409 if (opP->mode != CONTROL
1410 || (opP->reg != TT0 && opP->reg != TT1))
1411 losing++;
1412 break;
1413
1414 case 'A':
1415 if (opP->mode != AREG)
1416 losing++;
1417 break;
1418
1419 case 'a':
1420 if (opP->mode != AINDR)
1421 ++losing;
1422 break;
1423
1424 case 'B': /* FOO */
1425 if (opP->mode != ABSL
1426 || (flag_long_jumps
1427 && strncmp (instring, "jbsr", 4) == 0))
1428 losing++;
1429 break;
1430
1431 case 'C':
1432 if (opP->mode != CONTROL || opP->reg != CCR)
1433 losing++;
1434 break;
1435
1436 case 'd':
1437 if (opP->mode != DISP
1438 || opP->reg < ADDR0
1439 || opP->reg > ADDR7)
1440 losing++;
1441 break;
1442
1443 case 'D':
1444 if (opP->mode != DREG)
1445 losing++;
1446 break;
1447
1448 case 'F':
1449 if (opP->mode != FPREG)
1450 losing++;
1451 break;
1452
1453 case 'I':
1454 if (opP->mode != CONTROL
1455 || opP->reg < COP0
1456 || opP->reg > COP7)
1457 losing++;
1458 break;
1459
1460 case 'J':
1461 if (opP->mode != CONTROL
1462 || opP->reg < USP
1463 || opP->reg > last_movec_reg)
1464 losing++;
1465 else
1466 {
1467 const enum m68k_register *rp;
1468 for (rp = control_regs; *rp; rp++)
1469 if (*rp == opP->reg)
1470 break;
1471 if (*rp == 0)
1472 losing++;
1473 }
1474 break;
1475
1476 case 'k':
1477 if (opP->mode != IMMED)
1478 losing++;
1479 break;
1480
1481 case 'l':
1482 case 'L':
1483 if (opP->mode == DREG
1484 || opP->mode == AREG
1485 || opP->mode == FPREG)
1486 {
1487 if (s[1] == '8')
1488 losing++;
1489 else
1490 {
1491 switch (opP->mode)
1492 {
1493 case DREG:
1494 opP->mask = 1 << (opP->reg - DATA0);
1495 break;
1496 case AREG:
1497 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1498 break;
1499 case FPREG:
1500 opP->mask = 1 << (opP->reg - FP0 + 16);
1501 break;
1502 default:
1503 abort ();
1504 }
1505 opP->mode = REGLST;
1506 }
1507 }
1508 else if (opP->mode == CONTROL)
1509 {
1510 if (s[1] != '8')
1511 losing++;
1512 else
1513 {
1514 switch (opP->reg)
1515 {
1516 case FPI:
1517 opP->mask = 1 << 24;
1518 break;
1519 case FPS:
1520 opP->mask = 1 << 25;
1521 break;
1522 case FPC:
1523 opP->mask = 1 << 26;
1524 break;
1525 default:
1526 losing++;
1527 break;
1528 }
1529 opP->mode = REGLST;
1530 }
1531 }
1532 else if (opP->mode != REGLST)
1533 losing++;
1534 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1535 losing++;
1536 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1537 losing++;
1538 break;
1539
1540 case 'M':
1541 if (opP->mode != IMMED)
1542 losing++;
1543 else if (opP->disp.exp.X_op != O_constant
1544 || ! issbyte (opP->disp.exp.X_add_number))
1545 losing++;
1546 else if (! m68k_quick
1547 && instring[3] != 'q'
1548 && instring[4] != 'q')
1549 losing++;
1550 break;
1551
1552 case 'O':
1553 if (opP->mode != DREG
1554 && opP->mode != IMMED
1555 && opP->mode != ABSL)
1556 losing++;
1557 break;
1558
1559 case 'Q':
1560 if (opP->mode != IMMED)
1561 losing++;
1562 else if (opP->disp.exp.X_op != O_constant
1563 || opP->disp.exp.X_add_number < 1
1564 || opP->disp.exp.X_add_number > 8)
1565 losing++;
1566 else if (! m68k_quick
1567 && (strncmp (instring, "add", 3) == 0
1568 || strncmp (instring, "sub", 3) == 0)
1569 && instring[3] != 'q')
1570 losing++;
1571 break;
1572
1573 case 'R':
1574 if (opP->mode != DREG && opP->mode != AREG)
1575 losing++;
1576 break;
1577
1578 case 'r':
1579 if (opP->mode != AINDR
1580 && (opP->mode != BASE
1581 || (opP->reg != 0
1582 && opP->reg != ZADDR0)
1583 || opP->disp.exp.X_op != O_absent
1584 || ((opP->index.reg < DATA0
1585 || opP->index.reg > DATA7)
1586 && (opP->index.reg < ADDR0
1587 || opP->index.reg > ADDR7))
1588 || opP->index.size != SIZE_UNSPEC
1589 || opP->index.scale != 1))
1590 losing++;
1591 break;
1592
1593 case 's':
1594 if (opP->mode != CONTROL
1595 || ! (opP->reg == FPI
1596 || opP->reg == FPS
1597 || opP->reg == FPC))
1598 losing++;
1599 break;
1600
1601 case 'S':
1602 if (opP->mode != CONTROL || opP->reg != SR)
1603 losing++;
1604 break;
1605
1606 case 't':
1607 if (opP->mode != IMMED)
1608 losing++;
1609 else if (opP->disp.exp.X_op != O_constant
1610 || opP->disp.exp.X_add_number < 0
1611 || opP->disp.exp.X_add_number > 7)
1612 losing++;
1613 break;
1614
1615 case 'U':
1616 if (opP->mode != CONTROL || opP->reg != USP)
1617 losing++;
1618 break;
1619
1620 /* JF these are out of order. We could put them
1621 in order if we were willing to put up with
1622 bunches of #ifdef m68851s in the code.
1623
1624 Don't forget that you need these operands
1625 to use 68030 MMU instructions. */
1626 #ifndef NO_68851
1627 /* Memory addressing mode used by pflushr */
1628 case '|':
1629 if (opP->mode == CONTROL
1630 || opP->mode == FPREG
1631 || opP->mode == DREG
1632 || opP->mode == AREG
1633 || opP->mode == REGLST)
1634 losing++;
1635 /* We should accept immediate operands, but they
1636 supposedly have to be quad word, and we don't
1637 handle that. I would like to see what a Motorola
1638 assembler does before doing something here. */
1639 if (opP->mode == IMMED)
1640 losing++;
1641 break;
1642
1643 case 'f':
1644 if (opP->mode != CONTROL
1645 || (opP->reg != SFC && opP->reg != DFC))
1646 losing++;
1647 break;
1648
1649 case '0':
1650 if (opP->mode != CONTROL || opP->reg != TC)
1651 losing++;
1652 break;
1653
1654 case '1':
1655 if (opP->mode != CONTROL || opP->reg != AC)
1656 losing++;
1657 break;
1658
1659 case '2':
1660 if (opP->mode != CONTROL
1661 || (opP->reg != CAL
1662 && opP->reg != VAL
1663 && opP->reg != SCC))
1664 losing++;
1665 break;
1666
1667 case 'V':
1668 if (opP->mode != CONTROL
1669 || opP->reg != VAL)
1670 losing++;
1671 break;
1672
1673 case 'W':
1674 if (opP->mode != CONTROL
1675 || (opP->reg != DRP
1676 && opP->reg != SRP
1677 && opP->reg != CRP))
1678 losing++;
1679 break;
1680
1681 case 'X':
1682 if (opP->mode != CONTROL
1683 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1684 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1685 losing++;
1686 break;
1687
1688 case 'Y':
1689 if (opP->mode != CONTROL || opP->reg != PSR)
1690 losing++;
1691 break;
1692
1693 case 'Z':
1694 if (opP->mode != CONTROL || opP->reg != PCSR)
1695 losing++;
1696 break;
1697 #endif
1698 case 'c':
1699 if (opP->mode != CONTROL
1700 || (opP->reg != NC
1701 && opP->reg != IC
1702 && opP->reg != DC
1703 && opP->reg != BC))
1704 {
1705 losing++;
1706 } /* not a cache specifier. */
1707 break;
1708
1709 case '_':
1710 if (opP->mode != ABSL)
1711 ++losing;
1712 break;
1713
1714 default:
1715 abort ();
1716 } /* switch on type of operand */
1717
1718 if (losing)
1719 break;
1720 } /* for each operand */
1721 } /* if immediately wrong */
1722
1723 if (!losing)
1724 {
1725 break;
1726 } /* got it. */
1727
1728 opcode = opcode->m_next;
1729
1730 if (!opcode)
1731 {
1732 if (ok_arch
1733 && !(ok_arch & current_architecture))
1734 {
1735 char buf[200], *cp;
1736
1737 strcpy (buf,
1738 _("invalid instruction for this architecture; needs "));
1739 cp = buf + strlen (buf);
1740 switch (ok_arch)
1741 {
1742 case mfloat:
1743 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1744 break;
1745 case mmmu:
1746 strcpy (cp, _("mmu (68030 or 68851)"));
1747 break;
1748 case m68020up:
1749 strcpy (cp, _("68020 or higher"));
1750 break;
1751 case m68000up:
1752 strcpy (cp, _("68000 or higher"));
1753 break;
1754 case m68010up:
1755 strcpy (cp, _("68010 or higher"));
1756 break;
1757 default:
1758 {
1759 int got_one = 0, idx;
1760 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1761 idx++)
1762 {
1763 if ((archs[idx].arch & ok_arch)
1764 && ! archs[idx].alias)
1765 {
1766 if (got_one)
1767 {
1768 strcpy (cp, " or ");
1769 cp += strlen (cp);
1770 }
1771 got_one = 1;
1772 strcpy (cp, archs[idx].name);
1773 cp += strlen (cp);
1774 }
1775 }
1776 }
1777 }
1778 cp = xmalloc (strlen (buf) + 1);
1779 strcpy (cp, buf);
1780 the_ins.error = cp;
1781 }
1782 else
1783 the_ins.error = _("operands mismatch");
1784 return;
1785 } /* Fell off the end */
1786
1787 losing = 0;
1788 }
1789
1790 /* now assemble it */
1791
1792 the_ins.args = opcode->m_operands;
1793 the_ins.numargs = opcode->m_opnum;
1794 the_ins.numo = opcode->m_codenum;
1795 the_ins.opcode[0] = getone (opcode);
1796 the_ins.opcode[1] = gettwo (opcode);
1797
1798 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1799 {
1800 /* This switch is a doozy.
1801 Watch the first step; its a big one! */
1802 switch (s[0])
1803 {
1804
1805 case '*':
1806 case '~':
1807 case '%':
1808 case ';':
1809 case '@':
1810 case '!':
1811 case '&':
1812 case '$':
1813 case '?':
1814 case '/':
1815 case '<':
1816 case '>':
1817 case 'm':
1818 case 'n':
1819 case 'o':
1820 case 'p':
1821 case 'q':
1822 case 'v':
1823 #ifndef NO_68851
1824 case '|':
1825 #endif
1826 switch (opP->mode)
1827 {
1828 case IMMED:
1829 tmpreg = 0x3c; /* 7.4 */
1830 if (strchr ("bwl", s[1]))
1831 nextword = get_num (&opP->disp, 80);
1832 else
1833 nextword = get_num (&opP->disp, 0);
1834 if (isvar (&opP->disp))
1835 add_fix (s[1], &opP->disp, 0, 0);
1836 switch (s[1])
1837 {
1838 case 'b':
1839 if (!isbyte (nextword))
1840 opP->error = _("operand out of range");
1841 addword (nextword);
1842 baseo = 0;
1843 break;
1844 case 'w':
1845 if (!isword (nextword))
1846 opP->error = _("operand out of range");
1847 addword (nextword);
1848 baseo = 0;
1849 break;
1850 case 'W':
1851 if (!issword (nextword))
1852 opP->error = _("operand out of range");
1853 addword (nextword);
1854 baseo = 0;
1855 break;
1856 case 'l':
1857 addword (nextword >> 16);
1858 addword (nextword);
1859 baseo = 0;
1860 break;
1861
1862 case 'f':
1863 baseo = 2;
1864 outro = 8;
1865 break;
1866 case 'F':
1867 baseo = 4;
1868 outro = 11;
1869 break;
1870 case 'x':
1871 baseo = 6;
1872 outro = 15;
1873 break;
1874 case 'p':
1875 baseo = 6;
1876 outro = -1;
1877 break;
1878 default:
1879 abort ();
1880 }
1881 if (!baseo)
1882 break;
1883
1884 /* We gotta put out some float */
1885 if (op (&opP->disp) != O_big)
1886 {
1887 valueT val;
1888 int gencnt;
1889
1890 /* Can other cases happen here? */
1891 if (op (&opP->disp) != O_constant)
1892 abort ();
1893
1894 val = (valueT) offs (&opP->disp);
1895 gencnt = 0;
1896 do
1897 {
1898 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1899 val >>= LITTLENUM_NUMBER_OF_BITS;
1900 ++gencnt;
1901 }
1902 while (val != 0);
1903 offs (&opP->disp) = gencnt;
1904 }
1905 if (offs (&opP->disp) > 0)
1906 {
1907 if (offs (&opP->disp) > baseo)
1908 {
1909 as_warn (_("Bignum too big for %c format; truncated"),
1910 s[1]);
1911 offs (&opP->disp) = baseo;
1912 }
1913 baseo -= offs (&opP->disp);
1914 while (baseo--)
1915 addword (0);
1916 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1917 offs (&opP->disp)--;
1918 --wordp)
1919 addword (*wordp);
1920 break;
1921 }
1922 gen_to_words (words, baseo, (long) outro);
1923 for (wordp = words; baseo--; wordp++)
1924 addword (*wordp);
1925 break;
1926 case DREG:
1927 tmpreg = opP->reg - DATA; /* 0.dreg */
1928 break;
1929 case AREG:
1930 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1931 break;
1932 case AINDR:
1933 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1934 break;
1935 case ADEC:
1936 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1937 break;
1938 case AINC:
1939 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1940 break;
1941 case DISP:
1942
1943 nextword = get_num (&opP->disp, 80);
1944
1945 if (opP->reg == PC
1946 && ! isvar (&opP->disp)
1947 && m68k_abspcadd)
1948 {
1949 opP->disp.exp.X_op = O_symbol;
1950 #ifndef BFD_ASSEMBLER
1951 opP->disp.exp.X_add_symbol = &abs_symbol;
1952 #else
1953 opP->disp.exp.X_add_symbol =
1954 section_symbol (absolute_section);
1955 #endif
1956 }
1957
1958 /* Force into index mode. Hope this works */
1959
1960 /* We do the first bit for 32-bit displacements, and the
1961 second bit for 16 bit ones. It is possible that we
1962 should make the default be WORD instead of LONG, but
1963 I think that'd break GCC, so we put up with a little
1964 inefficiency for the sake of working output. */
1965
1966 if (!issword (nextword)
1967 || (isvar (&opP->disp)
1968 && ((opP->disp.size == SIZE_UNSPEC
1969 && flag_short_refs == 0
1970 && cpu_of_arch (current_architecture) >= m68020
1971 && cpu_of_arch (current_architecture) != mcf5200)
1972 || opP->disp.size == SIZE_LONG)))
1973 {
1974 if (cpu_of_arch (current_architecture) < m68020
1975 || cpu_of_arch (current_architecture) == mcf5200)
1976 opP->error =
1977 _("displacement too large for this architecture; needs 68020 or higher");
1978 if (opP->reg == PC)
1979 tmpreg = 0x3B; /* 7.3 */
1980 else
1981 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1982 if (isvar (&opP->disp))
1983 {
1984 if (opP->reg == PC)
1985 {
1986 if (opP->disp.size == SIZE_LONG
1987 #ifdef OBJ_ELF
1988 /* If the displacement needs pic
1989 relocation it cannot be relaxed. */
1990 || opP->disp.pic_reloc != pic_none
1991 #endif
1992 )
1993 {
1994 addword (0x0170);
1995 add_fix ('l', &opP->disp, 1, 2);
1996 }
1997 else
1998 {
1999 add_frag (adds (&opP->disp),
2000 offs (&opP->disp),
2001 TAB (PCLEA, SZ_UNDEF));
2002 break;
2003 }
2004 }
2005 else
2006 {
2007 addword (0x0170);
2008 add_fix ('l', &opP->disp, 0, 0);
2009 }
2010 }
2011 else
2012 addword (0x0170);
2013 addword (nextword >> 16);
2014 }
2015 else
2016 {
2017 if (opP->reg == PC)
2018 tmpreg = 0x3A; /* 7.2 */
2019 else
2020 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2021
2022 if (isvar (&opP->disp))
2023 {
2024 if (opP->reg == PC)
2025 {
2026 add_fix ('w', &opP->disp, 1, 0);
2027 }
2028 else
2029 add_fix ('w', &opP->disp, 0, 0);
2030 }
2031 }
2032 addword (nextword);
2033 break;
2034
2035 case POST:
2036 case PRE:
2037 case BASE:
2038 nextword = 0;
2039 baseo = get_num (&opP->disp, 80);
2040 if (opP->mode == POST || opP->mode == PRE)
2041 outro = get_num (&opP->odisp, 80);
2042 /* Figure out the `addressing mode'.
2043 Also turn on the BASE_DISABLE bit, if needed. */
2044 if (opP->reg == PC || opP->reg == ZPC)
2045 {
2046 tmpreg = 0x3b; /* 7.3 */
2047 if (opP->reg == ZPC)
2048 nextword |= 0x80;
2049 }
2050 else if (opP->reg == 0)
2051 {
2052 nextword |= 0x80;
2053 tmpreg = 0x30; /* 6.garbage */
2054 }
2055 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2056 {
2057 nextword |= 0x80;
2058 tmpreg = 0x30 + opP->reg - ZADDR0;
2059 }
2060 else
2061 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2062
2063 siz1 = opP->disp.size;
2064 if (opP->mode == POST || opP->mode == PRE)
2065 siz2 = opP->odisp.size;
2066 else
2067 siz2 = SIZE_UNSPEC;
2068
2069 /* Index register stuff */
2070 if (opP->index.reg != 0
2071 && opP->index.reg >= DATA
2072 && opP->index.reg <= ADDR7)
2073 {
2074 nextword |= (opP->index.reg - DATA) << 12;
2075
2076 if (opP->index.size == SIZE_LONG
2077 || (opP->index.size == SIZE_UNSPEC
2078 && m68k_index_width_default == SIZE_LONG))
2079 nextword |= 0x800;
2080
2081 if ((opP->index.scale != 1
2082 && cpu_of_arch (current_architecture) < m68020)
2083 || (opP->index.scale == 8
2084 && current_architecture == mcf5200))
2085 {
2086 opP->error =
2087 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2088 }
2089
2090 switch (opP->index.scale)
2091 {
2092 case 1:
2093 break;
2094 case 2:
2095 nextword |= 0x200;
2096 break;
2097 case 4:
2098 nextword |= 0x400;
2099 break;
2100 case 8:
2101 nextword |= 0x600;
2102 break;
2103 default:
2104 abort ();
2105 }
2106 /* IF its simple,
2107 GET US OUT OF HERE! */
2108
2109 /* Must be INDEX, with an index register. Address
2110 register cannot be ZERO-PC, and either :b was
2111 forced, or we know it will fit. For a 68000 or
2112 68010, force this mode anyways, because the
2113 larger modes aren't supported. */
2114 if (opP->mode == BASE
2115 && ((opP->reg >= ADDR0
2116 && opP->reg <= ADDR7)
2117 || opP->reg == PC))
2118 {
2119 if (siz1 == SIZE_BYTE
2120 || cpu_of_arch (current_architecture) < m68020
2121 || cpu_of_arch (current_architecture) == mcf5200
2122 || (siz1 == SIZE_UNSPEC
2123 && ! isvar (&opP->disp)
2124 && issbyte (baseo)))
2125 {
2126 nextword += baseo & 0xff;
2127 addword (nextword);
2128 if (isvar (&opP->disp))
2129 {
2130 /* Do a byte relocation. If it doesn't
2131 fit (possible on m68000) let the
2132 fixup processing complain later. */
2133 if (opP->reg == PC)
2134 add_fix ('B', &opP->disp, 1, 1);
2135 else
2136 add_fix ('B', &opP->disp, 0, 0);
2137 }
2138 else if (siz1 != SIZE_BYTE)
2139 {
2140 if (siz1 != SIZE_UNSPEC)
2141 as_warn (_("Forcing byte displacement"));
2142 if (! issbyte (baseo))
2143 opP->error = _("byte displacement out of range");
2144 }
2145
2146 break;
2147 }
2148 else if (siz1 == SIZE_UNSPEC
2149 && opP->reg == PC
2150 && isvar (&opP->disp)
2151 && subs (&opP->disp) == NULL
2152 #ifdef OBJ_ELF
2153 /* If the displacement needs pic
2154 relocation it cannot be relaxed. */
2155 && opP->disp.pic_reloc == pic_none
2156 #endif
2157 )
2158 {
2159 /* The code in md_convert_frag_1 needs to be
2160 able to adjust nextword. Call frag_grow
2161 to ensure that we have enough space in
2162 the frag obstack to make all the bytes
2163 contiguous. */
2164 frag_grow (14);
2165 nextword += baseo & 0xff;
2166 addword (nextword);
2167 add_frag (adds (&opP->disp), offs (&opP->disp),
2168 TAB (PCINDEX, SZ_UNDEF));
2169
2170 break;
2171 }
2172 }
2173 }
2174 else
2175 {
2176 nextword |= 0x40; /* No index reg */
2177 if (opP->index.reg >= ZDATA0
2178 && opP->index.reg <= ZDATA7)
2179 nextword |= (opP->index.reg - ZDATA0) << 12;
2180 else if (opP->index.reg >= ZADDR0
2181 || opP->index.reg <= ZADDR7)
2182 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2183 }
2184
2185 /* It isn't simple. */
2186
2187 if (cpu_of_arch (current_architecture) < m68020
2188 || cpu_of_arch (current_architecture) == mcf5200)
2189 opP->error =
2190 _("invalid operand mode for this architecture; needs 68020 or higher");
2191
2192 nextword |= 0x100;
2193 /* If the guy specified a width, we assume that it is
2194 wide enough. Maybe it isn't. If so, we lose. */
2195 switch (siz1)
2196 {
2197 case SIZE_UNSPEC:
2198 if (isvar (&opP->disp)
2199 ? m68k_rel32
2200 : ! issword (baseo))
2201 {
2202 siz1 = SIZE_LONG;
2203 nextword |= 0x30;
2204 }
2205 else if (! isvar (&opP->disp) && baseo == 0)
2206 nextword |= 0x10;
2207 else
2208 {
2209 nextword |= 0x20;
2210 siz1 = SIZE_WORD;
2211 }
2212 break;
2213 case SIZE_BYTE:
2214 as_warn (_(":b not permitted; defaulting to :w"));
2215 /* Fall through. */
2216 case SIZE_WORD:
2217 nextword |= 0x20;
2218 break;
2219 case SIZE_LONG:
2220 nextword |= 0x30;
2221 break;
2222 }
2223
2224 /* Figure out innner displacement stuff */
2225 if (opP->mode == POST || opP->mode == PRE)
2226 {
2227 if (cpu_of_arch (current_architecture) & cpu32)
2228 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2229 switch (siz2)
2230 {
2231 case SIZE_UNSPEC:
2232 if (isvar (&opP->odisp)
2233 ? m68k_rel32
2234 : ! issword (outro))
2235 {
2236 siz2 = SIZE_LONG;
2237 nextword |= 0x3;
2238 }
2239 else if (! isvar (&opP->odisp) && outro == 0)
2240 nextword |= 0x1;
2241 else
2242 {
2243 nextword |= 0x2;
2244 siz2 = SIZE_WORD;
2245 }
2246 break;
2247 case 1:
2248 as_warn (_(":b not permitted; defaulting to :w"));
2249 /* Fall through. */
2250 case 2:
2251 nextword |= 0x2;
2252 break;
2253 case 3:
2254 nextword |= 0x3;
2255 break;
2256 }
2257 if (opP->mode == POST
2258 && (nextword & 0x40) == 0)
2259 nextword |= 0x04;
2260 }
2261 addword (nextword);
2262
2263 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2264 {
2265 if (opP->reg == PC || opP->reg == ZPC)
2266 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2267 else
2268 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2269 }
2270 if (siz1 == SIZE_LONG)
2271 addword (baseo >> 16);
2272 if (siz1 != SIZE_UNSPEC)
2273 addword (baseo);
2274
2275 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2276 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2277 if (siz2 == SIZE_LONG)
2278 addword (outro >> 16);
2279 if (siz2 != SIZE_UNSPEC)
2280 addword (outro);
2281
2282 break;
2283
2284 case ABSL:
2285 nextword = get_num (&opP->disp, 80);
2286 switch (opP->disp.size)
2287 {
2288 default:
2289 abort ();
2290 case SIZE_UNSPEC:
2291 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2292 {
2293 tmpreg = 0x38; /* 7.0 */
2294 addword (nextword);
2295 break;
2296 }
2297 /* Don't generate pc relative code on 68010 and
2298 68000. */
2299 if (isvar (&opP->disp)
2300 && !subs (&opP->disp)
2301 && adds (&opP->disp)
2302 #ifdef OBJ_ELF
2303 /* If the displacement needs pic relocation it
2304 cannot be relaxed. */
2305 && opP->disp.pic_reloc == pic_none
2306 #endif
2307 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2308 && HAVE_LONG_BRANCH(current_architecture)
2309 && !flag_long_jumps
2310 && !strchr ("~%&$?", s[0]))
2311 {
2312 tmpreg = 0x3A; /* 7.2 */
2313 add_frag (adds (&opP->disp),
2314 offs (&opP->disp),
2315 TAB (PCREL, SZ_UNDEF));
2316 break;
2317 }
2318 /* Fall through into long */
2319 case SIZE_LONG:
2320 if (isvar (&opP->disp))
2321 add_fix ('l', &opP->disp, 0, 0);
2322
2323 tmpreg = 0x39;/* 7.1 mode */
2324 addword (nextword >> 16);
2325 addword (nextword);
2326 break;
2327
2328 case SIZE_BYTE:
2329 as_bad (_("unsupported byte value; use a different suffix"));
2330 /* Fall through. */
2331 case SIZE_WORD: /* Word */
2332 if (isvar (&opP->disp))
2333 add_fix ('w', &opP->disp, 0, 0);
2334
2335 tmpreg = 0x38;/* 7.0 mode */
2336 addword (nextword);
2337 break;
2338 }
2339 break;
2340 case CONTROL:
2341 case FPREG:
2342 default:
2343 as_bad (_("unknown/incorrect operand"));
2344 /* abort(); */
2345 }
2346 install_gen_operand (s[1], tmpreg);
2347 break;
2348
2349 case '#':
2350 case '^':
2351 switch (s[1])
2352 { /* JF: I hate floating point! */
2353 case 'j':
2354 tmpreg = 70;
2355 break;
2356 case '8':
2357 tmpreg = 20;
2358 break;
2359 case 'C':
2360 tmpreg = 50;
2361 break;
2362 case '3':
2363 default:
2364 tmpreg = 80;
2365 break;
2366 }
2367 tmpreg = get_num (&opP->disp, tmpreg);
2368 if (isvar (&opP->disp))
2369 add_fix (s[1], &opP->disp, 0, 0);
2370 switch (s[1])
2371 {
2372 case 'b': /* Danger: These do no check for
2373 certain types of overflow.
2374 user beware! */
2375 if (!isbyte (tmpreg))
2376 opP->error = _("out of range");
2377 insop (tmpreg, opcode);
2378 if (isvar (&opP->disp))
2379 the_ins.reloc[the_ins.nrel - 1].n =
2380 (opcode->m_codenum) * 2 + 1;
2381 break;
2382 case 'B':
2383 if (!issbyte (tmpreg))
2384 opP->error = _("out of range");
2385 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2386 if (isvar (&opP->disp))
2387 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2388 break;
2389 case 'w':
2390 if (!isword (tmpreg))
2391 opP->error = _("out of range");
2392 insop (tmpreg, opcode);
2393 if (isvar (&opP->disp))
2394 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2395 break;
2396 case 'W':
2397 if (!issword (tmpreg))
2398 opP->error = _("out of range");
2399 insop (tmpreg, opcode);
2400 if (isvar (&opP->disp))
2401 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2402 break;
2403 case 'l':
2404 /* Because of the way insop works, we put these two out
2405 backwards. */
2406 insop (tmpreg, opcode);
2407 insop (tmpreg >> 16, opcode);
2408 if (isvar (&opP->disp))
2409 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2410 break;
2411 case '3':
2412 tmpreg &= 0xFF;
2413 case '8':
2414 case 'C':
2415 case 'j':
2416 install_operand (s[1], tmpreg);
2417 break;
2418 default:
2419 abort ();
2420 }
2421 break;
2422
2423 case '+':
2424 case '-':
2425 case 'A':
2426 case 'a':
2427 install_operand (s[1], opP->reg - ADDR);
2428 break;
2429
2430 case 'B':
2431 tmpreg = get_num (&opP->disp, 80);
2432 switch (s[1])
2433 {
2434 case 'B':
2435 /* The pc_fix argument winds up in fx_pcrel_adjust,
2436 which is a char, and may therefore be unsigned. We
2437 want to pass -1, but we pass 64 instead, and convert
2438 back in md_pcrel_from. */
2439 add_fix ('B', &opP->disp, 1, 64);
2440 break;
2441 case 'W':
2442 add_fix ('w', &opP->disp, 1, 0);
2443 addword (0);
2444 break;
2445 case 'L':
2446 long_branch:
2447 if (!HAVE_LONG_BRANCH(current_architecture))
2448 as_warn (_("Can't use long branches on 68000/68010/5200"));
2449 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2450 add_fix ('l', &opP->disp, 1, 0);
2451 addword (0);
2452 addword (0);
2453 break;
2454 case 'g':
2455 if (subs (&opP->disp)) /* We can't relax it */
2456 goto long_branch;
2457
2458 #ifdef OBJ_ELF
2459 /* If the displacement needs pic relocation it cannot be
2460 relaxed. */
2461 if (opP->disp.pic_reloc != pic_none)
2462 goto long_branch;
2463 #endif
2464
2465 /* This could either be a symbol, or an absolute
2466 address. No matter, the frag hacking will finger it
2467 out. Not quite: it can't switch from BRANCH to
2468 BCC68000 for the case where opnd is absolute (it
2469 needs to use the 68000 hack since no conditional abs
2470 jumps). */
2471 if (( !HAVE_LONG_BRANCH(current_architecture)
2472 || (0 == adds (&opP->disp)))
2473 && (the_ins.opcode[0] >= 0x6200)
2474 && (the_ins.opcode[0] <= 0x6f00))
2475 add_frag (adds (&opP->disp), offs (&opP->disp),
2476 TAB (BCC68000, SZ_UNDEF));
2477 else
2478 add_frag (adds (&opP->disp), offs (&opP->disp),
2479 TAB (ABRANCH, SZ_UNDEF));
2480 break;
2481 case 'w':
2482 if (isvar (&opP->disp))
2483 {
2484 #if 1
2485 /* check for DBcc instruction */
2486 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2487 {
2488 /* size varies if patch */
2489 /* needed for long form */
2490 add_frag (adds (&opP->disp), offs (&opP->disp),
2491 TAB (DBCC, SZ_UNDEF));
2492 break;
2493 }
2494 #endif
2495 add_fix ('w', &opP->disp, 1, 0);
2496 }
2497 addword (0);
2498 break;
2499 case 'C': /* Fixed size LONG coproc branches */
2500 add_fix ('l', &opP->disp, 1, 0);
2501 addword (0);
2502 addword (0);
2503 break;
2504 case 'c': /* Var size Coprocesssor branches */
2505 if (subs (&opP->disp))
2506 {
2507 add_fix ('l', &opP->disp, 1, 0);
2508 add_frag ((symbolS *) 0, (offsetT) 0, TAB (FBRANCH, LONG));
2509 }
2510 else if (adds (&opP->disp))
2511 add_frag (adds (&opP->disp), offs (&opP->disp),
2512 TAB (FBRANCH, SZ_UNDEF));
2513 else
2514 {
2515 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2516 TAB(FBRANCH,SHORT)); */
2517 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2518 add_fix ('l', &opP->disp, 1, 0);
2519 addword (0);
2520 addword (0);
2521 }
2522 break;
2523 default:
2524 abort ();
2525 }
2526 break;
2527
2528 case 'C': /* Ignore it */
2529 break;
2530
2531 case 'd': /* JF this is a kludge */
2532 install_operand ('s', opP->reg - ADDR);
2533 tmpreg = get_num (&opP->disp, 80);
2534 if (!issword (tmpreg))
2535 {
2536 as_warn (_("Expression out of range, using 0"));
2537 tmpreg = 0;
2538 }
2539 addword (tmpreg);
2540 break;
2541
2542 case 'D':
2543 install_operand (s[1], opP->reg - DATA);
2544 break;
2545
2546 case 'F':
2547 install_operand (s[1], opP->reg - FP0);
2548 break;
2549
2550 case 'I':
2551 tmpreg = opP->reg - COP0;
2552 install_operand (s[1], tmpreg);
2553 break;
2554
2555 case 'J': /* JF foo */
2556 switch (opP->reg)
2557 {
2558 case SFC:
2559 tmpreg = 0x000;
2560 break;
2561 case DFC:
2562 tmpreg = 0x001;
2563 break;
2564 case CACR:
2565 tmpreg = 0x002;
2566 break;
2567 case TC:
2568 tmpreg = 0x003;
2569 break;
2570 case ITT0:
2571 tmpreg = 0x004;
2572 break;
2573 case ITT1:
2574 tmpreg = 0x005;
2575 break;
2576 case DTT0:
2577 tmpreg = 0x006;
2578 break;
2579 case DTT1:
2580 tmpreg = 0x007;
2581 break;
2582 case BUSCR:
2583 tmpreg = 0x008;
2584 break;
2585
2586 case USP:
2587 tmpreg = 0x800;
2588 break;
2589 case VBR:
2590 tmpreg = 0x801;
2591 break;
2592 case CAAR:
2593 tmpreg = 0x802;
2594 break;
2595 case MSP:
2596 tmpreg = 0x803;
2597 break;
2598 case ISP:
2599 tmpreg = 0x804;
2600 break;
2601 case MMUSR:
2602 tmpreg = 0x805;
2603 break;
2604 case URP:
2605 tmpreg = 0x806;
2606 break;
2607 case SRP:
2608 tmpreg = 0x807;
2609 break;
2610 case PCR:
2611 tmpreg = 0x808;
2612 break;
2613 case ROMBAR:
2614 tmpreg = 0xC00;
2615 break;
2616 case RAMBAR0:
2617 tmpreg = 0xC04;
2618 break;
2619 case RAMBAR1:
2620 tmpreg = 0xC05;
2621 break;
2622 case MBAR:
2623 tmpreg = 0xC0F;
2624 break;
2625 default:
2626 abort ();
2627 }
2628 install_operand (s[1], tmpreg);
2629 break;
2630
2631 case 'k':
2632 tmpreg = get_num (&opP->disp, 55);
2633 install_operand (s[1], tmpreg & 0x7f);
2634 break;
2635
2636 case 'l':
2637 tmpreg = opP->mask;
2638 if (s[1] == 'w')
2639 {
2640 if (tmpreg & 0x7FF0000)
2641 as_bad (_("Floating point register in register list"));
2642 insop (reverse_16_bits (tmpreg), opcode);
2643 }
2644 else
2645 {
2646 if (tmpreg & 0x700FFFF)
2647 as_bad (_("Wrong register in floating-point reglist"));
2648 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2649 }
2650 break;
2651
2652 case 'L':
2653 tmpreg = opP->mask;
2654 if (s[1] == 'w')
2655 {
2656 if (tmpreg & 0x7FF0000)
2657 as_bad (_("Floating point register in register list"));
2658 insop (tmpreg, opcode);
2659 }
2660 else if (s[1] == '8')
2661 {
2662 if (tmpreg & 0x0FFFFFF)
2663 as_bad (_("incorrect register in reglist"));
2664 install_operand (s[1], tmpreg >> 24);
2665 }
2666 else
2667 {
2668 if (tmpreg & 0x700FFFF)
2669 as_bad (_("wrong register in floating-point reglist"));
2670 else
2671 install_operand (s[1], tmpreg >> 16);
2672 }
2673 break;
2674
2675 case 'M':
2676 install_operand (s[1], get_num (&opP->disp, 60));
2677 break;
2678
2679 case 'O':
2680 tmpreg = ((opP->mode == DREG)
2681 ? 0x20 + opP->reg - DATA
2682 : (get_num (&opP->disp, 40) & 0x1F));
2683 install_operand (s[1], tmpreg);
2684 break;
2685
2686 case 'Q':
2687 tmpreg = get_num (&opP->disp, 10);
2688 if (tmpreg == 8)
2689 tmpreg = 0;
2690 install_operand (s[1], tmpreg);
2691 break;
2692
2693 case 'R':
2694 /* This depends on the fact that ADDR registers are eight
2695 more than their corresponding DATA regs, so the result
2696 will have the ADDR_REG bit set */
2697 install_operand (s[1], opP->reg - DATA);
2698 break;
2699
2700 case 'r':
2701 if (opP->mode == AINDR)
2702 install_operand (s[1], opP->reg - DATA);
2703 else
2704 install_operand (s[1], opP->index.reg - DATA);
2705 break;
2706
2707 case 's':
2708 if (opP->reg == FPI)
2709 tmpreg = 0x1;
2710 else if (opP->reg == FPS)
2711 tmpreg = 0x2;
2712 else if (opP->reg == FPC)
2713 tmpreg = 0x4;
2714 else
2715 abort ();
2716 install_operand (s[1], tmpreg);
2717 break;
2718
2719 case 'S': /* Ignore it */
2720 break;
2721
2722 case 'T':
2723 install_operand (s[1], get_num (&opP->disp, 30));
2724 break;
2725
2726 case 'U': /* Ignore it */
2727 break;
2728
2729 case 'c':
2730 switch (opP->reg)
2731 {
2732 case NC:
2733 tmpreg = 0;
2734 break;
2735 case DC:
2736 tmpreg = 1;
2737 break;
2738 case IC:
2739 tmpreg = 2;
2740 break;
2741 case BC:
2742 tmpreg = 3;
2743 break;
2744 default:
2745 as_fatal (_("failed sanity check"));
2746 } /* switch on cache token */
2747 install_operand (s[1], tmpreg);
2748 break;
2749 #ifndef NO_68851
2750 /* JF: These are out of order, I fear. */
2751 case 'f':
2752 switch (opP->reg)
2753 {
2754 case SFC:
2755 tmpreg = 0;
2756 break;
2757 case DFC:
2758 tmpreg = 1;
2759 break;
2760 default:
2761 abort ();
2762 }
2763 install_operand (s[1], tmpreg);
2764 break;
2765
2766 case '0':
2767 case '1':
2768 case '2':
2769 switch (opP->reg)
2770 {
2771 case TC:
2772 tmpreg = 0;
2773 break;
2774 case CAL:
2775 tmpreg = 4;
2776 break;
2777 case VAL:
2778 tmpreg = 5;
2779 break;
2780 case SCC:
2781 tmpreg = 6;
2782 break;
2783 case AC:
2784 tmpreg = 7;
2785 break;
2786 default:
2787 abort ();
2788 }
2789 install_operand (s[1], tmpreg);
2790 break;
2791
2792 case 'V':
2793 if (opP->reg == VAL)
2794 break;
2795 abort ();
2796
2797 case 'W':
2798 switch (opP->reg)
2799 {
2800 case DRP:
2801 tmpreg = 1;
2802 break;
2803 case SRP:
2804 tmpreg = 2;
2805 break;
2806 case CRP:
2807 tmpreg = 3;
2808 break;
2809 default:
2810 abort ();
2811 }
2812 install_operand (s[1], tmpreg);
2813 break;
2814
2815 case 'X':
2816 switch (opP->reg)
2817 {
2818 case BAD:
2819 case BAD + 1:
2820 case BAD + 2:
2821 case BAD + 3:
2822 case BAD + 4:
2823 case BAD + 5:
2824 case BAD + 6:
2825 case BAD + 7:
2826 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2827 break;
2828
2829 case BAC:
2830 case BAC + 1:
2831 case BAC + 2:
2832 case BAC + 3:
2833 case BAC + 4:
2834 case BAC + 5:
2835 case BAC + 6:
2836 case BAC + 7:
2837 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2838 break;
2839
2840 default:
2841 abort ();
2842 }
2843 install_operand (s[1], tmpreg);
2844 break;
2845 case 'Y':
2846 know (opP->reg == PSR);
2847 break;
2848 case 'Z':
2849 know (opP->reg == PCSR);
2850 break;
2851 #endif /* m68851 */
2852 case '3':
2853 switch (opP->reg)
2854 {
2855 case TT0:
2856 tmpreg = 2;
2857 break;
2858 case TT1:
2859 tmpreg = 3;
2860 break;
2861 default:
2862 abort ();
2863 }
2864 install_operand (s[1], tmpreg);
2865 break;
2866 case 't':
2867 tmpreg = get_num (&opP->disp, 20);
2868 install_operand (s[1], tmpreg);
2869 break;
2870 case '_': /* used only for move16 absolute 32-bit address */
2871 if (isvar (&opP->disp))
2872 add_fix ('l', &opP->disp, 0, 0);
2873 tmpreg = get_num (&opP->disp, 80);
2874 addword (tmpreg >> 16);
2875 addword (tmpreg & 0xFFFF);
2876 break;
2877 default:
2878 abort ();
2879 }
2880 }
2881
2882 /* By the time whe get here (FINALLY) the_ins contains the complete
2883 instruction, ready to be emitted. . . */
2884 }
2885
2886 static int
2887 reverse_16_bits (in)
2888 int in;
2889 {
2890 int out = 0;
2891 int n;
2892
2893 static int mask[16] =
2894 {
2895 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2896 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2897 };
2898 for (n = 0; n < 16; n++)
2899 {
2900 if (in & mask[n])
2901 out |= mask[15 - n];
2902 }
2903 return out;
2904 } /* reverse_16_bits() */
2905
2906 static int
2907 reverse_8_bits (in)
2908 int in;
2909 {
2910 int out = 0;
2911 int n;
2912
2913 static int mask[8] =
2914 {
2915 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2916 };
2917
2918 for (n = 0; n < 8; n++)
2919 {
2920 if (in & mask[n])
2921 out |= mask[7 - n];
2922 }
2923 return out;
2924 } /* reverse_8_bits() */
2925
2926 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2927 (that value is chosen in the frag_var call in md_assemble). TYPE
2928 is the subtype of the frag to be generated; its primary type is
2929 rs_machine_dependent.
2930
2931 The TYPE parameter is also used by md_convert_frag_1 and
2932 md_estimate_size_before_relax. The appropriate type of fixup will
2933 be emitted by md_convert_frag_1.
2934
2935 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2936 static void
2937 install_operand (mode, val)
2938 int mode;
2939 int val;
2940 {
2941 switch (mode)
2942 {
2943 case 's':
2944 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2945 break;
2946 case 'd':
2947 the_ins.opcode[0] |= val << 9;
2948 break;
2949 case '1':
2950 the_ins.opcode[1] |= val << 12;
2951 break;
2952 case '2':
2953 the_ins.opcode[1] |= val << 6;
2954 break;
2955 case '3':
2956 the_ins.opcode[1] |= val;
2957 break;
2958 case '4':
2959 the_ins.opcode[2] |= val << 12;
2960 break;
2961 case '5':
2962 the_ins.opcode[2] |= val << 6;
2963 break;
2964 case '6':
2965 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2966 three words long! */
2967 the_ins.numo++;
2968 the_ins.opcode[2] |= val;
2969 break;
2970 case '7':
2971 the_ins.opcode[1] |= val << 7;
2972 break;
2973 case '8':
2974 the_ins.opcode[1] |= val << 10;
2975 break;
2976 #ifndef NO_68851
2977 case '9':
2978 the_ins.opcode[1] |= val << 5;
2979 break;
2980 #endif
2981
2982 case 't':
2983 the_ins.opcode[1] |= (val << 10) | (val << 7);
2984 break;
2985 case 'D':
2986 the_ins.opcode[1] |= (val << 12) | val;
2987 break;
2988 case 'g':
2989 the_ins.opcode[0] |= val = 0xff;
2990 break;
2991 case 'i':
2992 the_ins.opcode[0] |= val << 9;
2993 break;
2994 case 'C':
2995 the_ins.opcode[1] |= val;
2996 break;
2997 case 'j':
2998 the_ins.opcode[1] |= val;
2999 the_ins.numo++; /* What a hack */
3000 break;
3001 case 'k':
3002 the_ins.opcode[1] |= val << 4;
3003 break;
3004 case 'b':
3005 case 'w':
3006 case 'W':
3007 case 'l':
3008 break;
3009 case 'e':
3010 the_ins.opcode[0] |= (val << 6);
3011 break;
3012 case 'L':
3013 the_ins.opcode[1] = (val >> 16);
3014 the_ins.opcode[2] = val & 0xffff;
3015 break;
3016 case 'c':
3017 default:
3018 as_fatal (_("failed sanity check."));
3019 }
3020 } /* install_operand() */
3021
3022 static void
3023 install_gen_operand (mode, val)
3024 int mode;
3025 int val;
3026 {
3027 switch (mode)
3028 {
3029 case 's':
3030 the_ins.opcode[0] |= val;
3031 break;
3032 case 'd':
3033 /* This is a kludge!!! */
3034 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3035 break;
3036 case 'b':
3037 case 'w':
3038 case 'l':
3039 case 'f':
3040 case 'F':
3041 case 'x':
3042 case 'p':
3043 the_ins.opcode[0] |= val;
3044 break;
3045 /* more stuff goes here */
3046 default:
3047 as_fatal (_("failed sanity check."));
3048 }
3049 } /* install_gen_operand() */
3050
3051 /*
3052 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3053 * then deal with the bitfield hack.
3054 */
3055
3056 static char *
3057 crack_operand (str, opP)
3058 register char *str;
3059 register struct m68k_op *opP;
3060 {
3061 register int parens;
3062 register int c;
3063 register char *beg_str;
3064 int inquote = 0;
3065
3066 if (!str)
3067 {
3068 return str;
3069 }
3070 beg_str = str;
3071 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3072 {
3073 if (! inquote)
3074 {
3075 if (*str == '(')
3076 parens++;
3077 else if (*str == ')')
3078 {
3079 if (!parens)
3080 { /* ERROR */
3081 opP->error = _("Extra )");
3082 return str;
3083 }
3084 --parens;
3085 }
3086 }
3087 if (flag_mri && *str == '\'')
3088 inquote = ! inquote;
3089 }
3090 if (!*str && parens)
3091 { /* ERROR */
3092 opP->error = _("Missing )");
3093 return str;
3094 }
3095 c = *str;
3096 *str = '\0';
3097 if (m68k_ip_op (beg_str, opP) != 0)
3098 {
3099 *str = c;
3100 return str;
3101 }
3102 *str = c;
3103 if (c == '}')
3104 c = *++str; /* JF bitfield hack */
3105 if (c)
3106 {
3107 c = *++str;
3108 if (!c)
3109 as_bad (_("Missing operand"));
3110 }
3111
3112 /* Detect MRI REG symbols and convert them to REGLSTs. */
3113 if (opP->mode == CONTROL && (int)opP->reg < 0)
3114 {
3115 opP->mode = REGLST;
3116 opP->mask = ~(int)opP->reg;
3117 opP->reg = 0;
3118 }
3119
3120 return str;
3121 }
3122
3123 /* This is the guts of the machine-dependent assembler. STR points to a
3124 machine dependent instruction. This function is supposed to emit
3125 the frags/bytes it assembles to.
3126 */
3127
3128 static void
3129 insert_reg (regname, regnum)
3130 const char *regname;
3131 int regnum;
3132 {
3133 char buf[100];
3134 int i;
3135
3136 #ifdef REGISTER_PREFIX
3137 if (!flag_reg_prefix_optional)
3138 {
3139 buf[0] = REGISTER_PREFIX;
3140 strcpy (buf + 1, regname);
3141 regname = buf;
3142 }
3143 #endif
3144
3145 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3146 &zero_address_frag));
3147
3148 for (i = 0; regname[i]; i++)
3149 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3150 buf[i] = '\0';
3151
3152 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3153 &zero_address_frag));
3154 }
3155
3156 struct init_entry
3157 {
3158 const char *name;
3159 int number;
3160 };
3161
3162 static const struct init_entry init_table[] =
3163 {
3164 { "d0", DATA0 },
3165 { "d1", DATA1 },
3166 { "d2", DATA2 },
3167 { "d3", DATA3 },
3168 { "d4", DATA4 },
3169 { "d5", DATA5 },
3170 { "d6", DATA6 },
3171 { "d7", DATA7 },
3172 { "a0", ADDR0 },
3173 { "a1", ADDR1 },
3174 { "a2", ADDR2 },
3175 { "a3", ADDR3 },
3176 { "a4", ADDR4 },
3177 { "a5", ADDR5 },
3178 { "a6", ADDR6 },
3179 { "fp", ADDR6 },
3180 { "a7", ADDR7 },
3181 { "sp", ADDR7 },
3182 { "ssp", ADDR7 },
3183 { "fp0", FP0 },
3184 { "fp1", FP1 },
3185 { "fp2", FP2 },
3186 { "fp3", FP3 },
3187 { "fp4", FP4 },
3188 { "fp5", FP5 },
3189 { "fp6", FP6 },
3190 { "fp7", FP7 },
3191 { "fpi", FPI },
3192 { "fpiar", FPI },
3193 { "fpc", FPI },
3194 { "fps", FPS },
3195 { "fpsr", FPS },
3196 { "fpc", FPC },
3197 { "fpcr", FPC },
3198 { "control", FPC },
3199 { "status", FPS },
3200 { "iaddr", FPI },
3201
3202 { "cop0", COP0 },
3203 { "cop1", COP1 },
3204 { "cop2", COP2 },
3205 { "cop3", COP3 },
3206 { "cop4", COP4 },
3207 { "cop5", COP5 },
3208 { "cop6", COP6 },
3209 { "cop7", COP7 },
3210 { "pc", PC },
3211 { "zpc", ZPC },
3212 { "sr", SR },
3213
3214 { "ccr", CCR },
3215 { "cc", CCR },
3216
3217 /* control registers */
3218 { "sfc", SFC }, /* Source Function Code */
3219 { "sfcr", SFC },
3220 { "dfc", DFC }, /* Destination Function Code */
3221 { "dfcr", DFC },
3222 { "cacr", CACR }, /* Cache Control Register */
3223 { "caar", CAAR }, /* Cache Address Register */
3224
3225 { "usp", USP }, /* User Stack Pointer */
3226 { "vbr", VBR }, /* Vector Base Register */
3227 { "msp", MSP }, /* Master Stack Pointer */
3228 { "isp", ISP }, /* Interrupt Stack Pointer */
3229
3230 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3231 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3232 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3233 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3234
3235 /* 68ec040 versions of same */
3236 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3237 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3238 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3239 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3240
3241 /* mcf5200 versions of same. The ColdFire programmer's reference
3242 manual indicated that the order is 2,3,0,1, but Ken Rose
3243 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3244 { "acr0", ITT0 }, /* Access Control Unit 0 */
3245 { "acr1", ITT1 }, /* Access Control Unit 1 */
3246 { "acr2", DTT0 }, /* Access Control Unit 2 */
3247 { "acr3", DTT1 }, /* Access Control Unit 3 */
3248
3249 { "tc", TC }, /* MMU Translation Control Register */
3250 { "tcr", TC },
3251
3252 { "mmusr", MMUSR }, /* MMU Status Register */
3253 { "srp", SRP }, /* User Root Pointer */
3254 { "urp", URP }, /* Supervisor Root Pointer */
3255
3256 { "buscr", BUSCR },
3257 { "pcr", PCR },
3258
3259 { "rombar", ROMBAR }, /* ROM Base Address Register */
3260 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3261 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3262 { "mbar", MBAR }, /* Module Base Address Register */
3263 /* end of control registers */
3264
3265 { "ac", AC },
3266 { "bc", BC },
3267 { "cal", CAL },
3268 { "crp", CRP },
3269 { "drp", DRP },
3270 { "pcsr", PCSR },
3271 { "psr", PSR },
3272 { "scc", SCC },
3273 { "val", VAL },
3274 { "bad0", BAD0 },
3275 { "bad1", BAD1 },
3276 { "bad2", BAD2 },
3277 { "bad3", BAD3 },
3278 { "bad4", BAD4 },
3279 { "bad5", BAD5 },
3280 { "bad6", BAD6 },
3281 { "bad7", BAD7 },
3282 { "bac0", BAC0 },
3283 { "bac1", BAC1 },
3284 { "bac2", BAC2 },
3285 { "bac3", BAC3 },
3286 { "bac4", BAC4 },
3287 { "bac5", BAC5 },
3288 { "bac6", BAC6 },
3289 { "bac7", BAC7 },
3290
3291 { "ic", IC },
3292 { "dc", DC },
3293 { "nc", NC },
3294
3295 { "tt0", TT0 },
3296 { "tt1", TT1 },
3297 /* 68ec030 versions of same */
3298 { "ac0", TT0 },
3299 { "ac1", TT1 },
3300 /* 68ec030 access control unit, identical to 030 MMU status reg */
3301 { "acusr", PSR },
3302
3303 /* Suppressed data and address registers. */
3304 { "zd0", ZDATA0 },
3305 { "zd1", ZDATA1 },
3306 { "zd2", ZDATA2 },
3307 { "zd3", ZDATA3 },
3308 { "zd4", ZDATA4 },
3309 { "zd5", ZDATA5 },
3310 { "zd6", ZDATA6 },
3311 { "zd7", ZDATA7 },
3312 { "za0", ZADDR0 },
3313 { "za1", ZADDR1 },
3314 { "za2", ZADDR2 },
3315 { "za3", ZADDR3 },
3316 { "za4", ZADDR4 },
3317 { "za5", ZADDR5 },
3318 { "za6", ZADDR6 },
3319 { "za7", ZADDR7 },
3320
3321 { 0, 0 }
3322 };
3323
3324 static void
3325 init_regtable ()
3326 {
3327 int i;
3328 for (i = 0; init_table[i].name; i++)
3329 insert_reg (init_table[i].name, init_table[i].number);
3330 }
3331
3332 static int no_68851, no_68881;
3333
3334 #ifdef OBJ_AOUT
3335 /* a.out machine type. Default to 68020. */
3336 int m68k_aout_machtype = 2;
3337 #endif
3338
3339 void
3340 md_assemble (str)
3341 char *str;
3342 {
3343 const char *er;
3344 short *fromP;
3345 char *toP = NULL;
3346 int m, n = 0;
3347 char *to_beg_P;
3348 int shorts_this_frag;
3349 fixS *fixP;
3350
3351 /* In MRI mode, the instruction and operands are separated by a
3352 space. Anything following the operands is a comment. The label
3353 has already been removed. */
3354 if (flag_mri)
3355 {
3356 char *s;
3357 int fields = 0;
3358 int infield = 0;
3359 int inquote = 0;
3360
3361 for (s = str; *s != '\0'; s++)
3362 {
3363 if ((*s == ' ' || *s == '\t') && ! inquote)
3364 {
3365 if (infield)
3366 {
3367 ++fields;
3368 if (fields >= 2)
3369 {
3370 *s = '\0';
3371 break;
3372 }
3373 infield = 0;
3374 }
3375 }
3376 else
3377 {
3378 if (! infield)
3379 infield = 1;
3380 if (*s == '\'')
3381 inquote = ! inquote;
3382 }
3383 }
3384 }
3385
3386 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3387 m68k_ip (str);
3388 er = the_ins.error;
3389 if (!er)
3390 {
3391 for (n = 0; n < the_ins.numargs; n++)
3392 if (the_ins.operands[n].error)
3393 {
3394 er = the_ins.operands[n].error;
3395 break;
3396 }
3397 }
3398 if (er)
3399 {
3400 as_bad (_("%s -- statement `%s' ignored"), er, str);
3401 return;
3402 }
3403
3404 /* If there is a current label, record that it marks an instruction. */
3405 if (current_label != NULL)
3406 {
3407 current_label->text = 1;
3408 current_label = NULL;
3409 }
3410
3411 if (the_ins.nfrag == 0)
3412 {
3413 /* No frag hacking involved; just put it out */
3414 toP = frag_more (2 * the_ins.numo);
3415 fromP = &the_ins.opcode[0];
3416 for (m = the_ins.numo; m; --m)
3417 {
3418 md_number_to_chars (toP, (long) (*fromP), 2);
3419 toP += 2;
3420 fromP++;
3421 }
3422 /* put out symbol-dependent info */
3423 for (m = 0; m < the_ins.nrel; m++)
3424 {
3425 switch (the_ins.reloc[m].wid)
3426 {
3427 case 'B':
3428 n = 1;
3429 break;
3430 case 'b':
3431 n = 1;
3432 break;
3433 case '3':
3434 n = 1;
3435 break;
3436 case 'w':
3437 case 'W':
3438 n = 2;
3439 break;
3440 case 'l':
3441 n = 4;
3442 break;
3443 default:
3444 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3445 the_ins.reloc[m].wid);
3446 }
3447
3448 fixP = fix_new_exp (frag_now,
3449 ((toP - frag_now->fr_literal)
3450 - the_ins.numo * 2 + the_ins.reloc[m].n),
3451 n,
3452 &the_ins.reloc[m].exp,
3453 the_ins.reloc[m].pcrel,
3454 get_reloc_code (n, the_ins.reloc[m].pcrel,
3455 the_ins.reloc[m].pic_reloc));
3456 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3457 if (the_ins.reloc[m].wid == 'B')
3458 fixP->fx_signed = 1;
3459 }
3460 return;
3461 }
3462
3463 /* There's some frag hacking */
3464 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3465 {
3466 int wid;
3467
3468 if (n == 0)
3469 wid = 2 * the_ins.fragb[n].fragoff;
3470 else
3471 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3472 toP = frag_more (wid);
3473 to_beg_P = toP;
3474 shorts_this_frag = 0;
3475 for (m = wid / 2; m; --m)
3476 {
3477 md_number_to_chars (toP, (long) (*fromP), 2);
3478 toP += 2;
3479 fromP++;
3480 shorts_this_frag++;
3481 }
3482 for (m = 0; m < the_ins.nrel; m++)
3483 {
3484 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3485 {
3486 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3487 break;
3488 }
3489 wid = the_ins.reloc[m].wid;
3490 if (wid == 0)
3491 continue;
3492 the_ins.reloc[m].wid = 0;
3493 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3494
3495 fixP = fix_new_exp (frag_now,
3496 ((toP - frag_now->fr_literal)
3497 - the_ins.numo * 2 + the_ins.reloc[m].n),
3498 wid,
3499 &the_ins.reloc[m].exp,
3500 the_ins.reloc[m].pcrel,
3501 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3502 the_ins.reloc[m].pic_reloc));
3503 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3504 }
3505 (void) frag_var (rs_machine_dependent, 10, 0,
3506 (relax_substateT) (the_ins.fragb[n].fragty),
3507 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3508 }
3509 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3510 shorts_this_frag = 0;
3511 if (n)
3512 {
3513 toP = frag_more (n * sizeof (short));
3514 while (n--)
3515 {
3516 md_number_to_chars (toP, (long) (*fromP), 2);
3517 toP += 2;
3518 fromP++;
3519 shorts_this_frag++;
3520 }
3521 }
3522 for (m = 0; m < the_ins.nrel; m++)
3523 {
3524 int wid;
3525
3526 wid = the_ins.reloc[m].wid;
3527 if (wid == 0)
3528 continue;
3529 the_ins.reloc[m].wid = 0;
3530 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3531
3532 fixP = fix_new_exp (frag_now,
3533 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3534 - shorts_this_frag * 2),
3535 wid,
3536 &the_ins.reloc[m].exp,
3537 the_ins.reloc[m].pcrel,
3538 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3539 the_ins.reloc[m].pic_reloc));
3540 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3541 }
3542 }
3543
3544 void
3545 md_begin ()
3546 {
3547 /*
3548 * md_begin -- set up hash tables with 68000 instructions.
3549 * similar to what the vax assembler does. ---phr
3550 */
3551 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3552 a copy of it at runtime, adding in the information we want but isn't
3553 there. I think it'd be better to have an awk script hack the table
3554 at compile time. Or even just xstr the table and use it as-is. But
3555 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3556 names. */
3557
3558 register const struct m68k_opcode *ins;
3559 register struct m68k_incant *hack, *slak;
3560 register const char *retval = 0; /* empty string, or error msg text */
3561 register unsigned int i;
3562 register char c;
3563
3564 if (flag_mri)
3565 {
3566 flag_reg_prefix_optional = 1;
3567 m68k_abspcadd = 1;
3568 if (! m68k_rel32_from_cmdline)
3569 m68k_rel32 = 0;
3570 }
3571
3572 op_hash = hash_new ();
3573
3574 obstack_begin (&robyn, 4000);
3575 for (i = 0; i < m68k_numopcodes; i++)
3576 {
3577 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3578 do
3579 {
3580 ins = &m68k_opcodes[i];
3581 /* We *could* ignore insns that don't match our arch here
3582 but just leaving them out of the hash. */
3583 slak->m_operands = ins->args;
3584 slak->m_opnum = strlen (slak->m_operands) / 2;
3585 slak->m_arch = ins->arch;
3586 slak->m_opcode = ins->opcode;
3587 /* This is kludgey */
3588 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3589 if (i + 1 != m68k_numopcodes
3590 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3591 {
3592 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3593 i++;
3594 }
3595 else
3596 slak->m_next = 0;
3597 slak = slak->m_next;
3598 }
3599 while (slak);
3600
3601 retval = hash_insert (op_hash, ins->name, (char *) hack);
3602 if (retval)
3603 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3604 }
3605
3606 for (i = 0; i < m68k_numaliases; i++)
3607 {
3608 const char *name = m68k_opcode_aliases[i].primary;
3609 const char *alias = m68k_opcode_aliases[i].alias;
3610 PTR val = hash_find (op_hash, name);
3611 if (!val)
3612 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3613 retval = hash_insert (op_hash, alias, val);
3614 if (retval)
3615 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3616 }
3617
3618 /* In MRI mode, all unsized branches are variable sized. Normally,
3619 they are word sized. */
3620 if (flag_mri)
3621 {
3622 static struct m68k_opcode_alias mri_aliases[] =
3623 {
3624 { "bhi", "jhi", },
3625 { "bls", "jls", },
3626 { "bcc", "jcc", },
3627 { "bcs", "jcs", },
3628 { "bne", "jne", },
3629 { "beq", "jeq", },
3630 { "bvc", "jvc", },
3631 { "bvs", "jvs", },
3632 { "bpl", "jpl", },
3633 { "bmi", "jmi", },
3634 { "bge", "jge", },
3635 { "blt", "jlt", },
3636 { "bgt", "jgt", },
3637 { "ble", "jle", },
3638 { "bra", "jra", },
3639 { "bsr", "jbsr", },
3640 };
3641
3642 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3643 {
3644 const char *name = mri_aliases[i].primary;
3645 const char *alias = mri_aliases[i].alias;
3646 PTR val = hash_find (op_hash, name);
3647 if (!val)
3648 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3649 retval = hash_jam (op_hash, alias, val);
3650 if (retval)
3651 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3652 }
3653 }
3654
3655 for (i = 0; i < sizeof (mklower_table); i++)
3656 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3657
3658 for (i = 0; i < sizeof (notend_table); i++)
3659 {
3660 notend_table[i] = 0;
3661 alt_notend_table[i] = 0;
3662 }
3663 notend_table[','] = 1;
3664 notend_table['{'] = 1;
3665 notend_table['}'] = 1;
3666 alt_notend_table['a'] = 1;
3667 alt_notend_table['A'] = 1;
3668 alt_notend_table['d'] = 1;
3669 alt_notend_table['D'] = 1;
3670 alt_notend_table['#'] = 1;
3671 alt_notend_table['&'] = 1;
3672 alt_notend_table['f'] = 1;
3673 alt_notend_table['F'] = 1;
3674 #ifdef REGISTER_PREFIX
3675 alt_notend_table[REGISTER_PREFIX] = 1;
3676 #endif
3677
3678 /* We need to put '(' in alt_notend_table to handle
3679 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3680 */
3681 alt_notend_table['('] = 1;
3682
3683 /* We need to put '@' in alt_notend_table to handle
3684 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3685 */
3686 alt_notend_table['@'] = 1;
3687
3688 /* We need to put digits in alt_notend_table to handle
3689 bfextu %d0{24:1},%d0
3690 */
3691 alt_notend_table['0'] = 1;
3692 alt_notend_table['1'] = 1;
3693 alt_notend_table['2'] = 1;
3694 alt_notend_table['3'] = 1;
3695 alt_notend_table['4'] = 1;
3696 alt_notend_table['5'] = 1;
3697 alt_notend_table['6'] = 1;
3698 alt_notend_table['7'] = 1;
3699 alt_notend_table['8'] = 1;
3700 alt_notend_table['9'] = 1;
3701
3702 #ifndef MIT_SYNTAX_ONLY
3703 /* Insert pseudo ops, these have to go into the opcode table since
3704 gas expects pseudo ops to start with a dot */
3705 {
3706 int n = 0;
3707 while (mote_pseudo_table[n].poc_name)
3708 {
3709 hack = (struct m68k_incant *)
3710 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3711 hash_insert (op_hash,
3712 mote_pseudo_table[n].poc_name, (char *) hack);
3713 hack->m_operands = 0;
3714 hack->m_opnum = n;
3715 n++;
3716 }
3717 }
3718 #endif
3719
3720 init_regtable ();
3721
3722 #ifdef OBJ_ELF
3723 record_alignment (text_section, 2);
3724 record_alignment (data_section, 2);
3725 record_alignment (bss_section, 2);
3726 #endif
3727 }
3728
3729 static void
3730 select_control_regs ()
3731 {
3732 /* Note which set of "movec" control registers is available. */
3733 switch (cpu_of_arch (current_architecture))
3734 {
3735 case m68000:
3736 control_regs = m68000_control_regs;
3737 break;
3738 case m68010:
3739 control_regs = m68010_control_regs;
3740 break;
3741 case m68020:
3742 case m68030:
3743 control_regs = m68020_control_regs;
3744 break;
3745 case m68040:
3746 control_regs = m68040_control_regs;
3747 break;
3748 case m68060:
3749 control_regs = m68060_control_regs;
3750 break;
3751 case cpu32:
3752 control_regs = cpu32_control_regs;
3753 break;
3754 case mcf5200:
3755 control_regs = mcf5200_control_regs;
3756 break;
3757 default:
3758 abort ();
3759 }
3760 }
3761
3762 void
3763 m68k_init_after_args ()
3764 {
3765 if (cpu_of_arch (current_architecture) == 0)
3766 {
3767 int i;
3768 const char *default_cpu = TARGET_CPU;
3769
3770 if (*default_cpu == 'm')
3771 default_cpu++;
3772 for (i = 0; i < n_archs; i++)
3773 if (strcasecmp (default_cpu, archs[i].name) == 0)
3774 break;
3775 if (i == n_archs)
3776 {
3777 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3778 current_architecture |= m68020;
3779 }
3780 else
3781 current_architecture |= archs[i].arch;
3782 }
3783 /* Permit m68881 specification with all cpus; those that can't work
3784 with a coprocessor could be doing emulation. */
3785 if (current_architecture & m68851)
3786 {
3787 if (current_architecture & m68040)
3788 {
3789 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
3790 }
3791 }
3792 /* What other incompatibilities could we check for? */
3793
3794 /* Toss in some default assumptions about coprocessors. */
3795 if (!no_68881
3796 && (cpu_of_arch (current_architecture)
3797 /* Can CPU32 have a 68881 coprocessor?? */
3798 & (m68020 | m68030 | cpu32)))
3799 {
3800 current_architecture |= m68881;
3801 }
3802 if (!no_68851
3803 && (cpu_of_arch (current_architecture) & m68020up) != 0
3804 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3805 {
3806 current_architecture |= m68851;
3807 }
3808 if (no_68881 && (current_architecture & m68881))
3809 as_bad (_("options for 68881 and no-68881 both given"));
3810 if (no_68851 && (current_architecture & m68851))
3811 as_bad (_("options for 68851 and no-68851 both given"));
3812
3813 #ifdef OBJ_AOUT
3814 /* Work out the magic number. This isn't very general. */
3815 if (current_architecture & m68000)
3816 m68k_aout_machtype = 0;
3817 else if (current_architecture & m68010)
3818 m68k_aout_machtype = 1;
3819 else if (current_architecture & m68020)
3820 m68k_aout_machtype = 2;
3821 else
3822 m68k_aout_machtype = 2;
3823 #endif
3824
3825 /* Note which set of "movec" control registers is available. */
3826 select_control_regs ();
3827
3828 if (cpu_of_arch (current_architecture) < m68020
3829 || cpu_of_arch (current_architecture) == mcf5200)
3830 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3831 }
3832 \f
3833 /* This is called when a label is defined. */
3834
3835 void
3836 m68k_frob_label (sym)
3837 symbolS *sym;
3838 {
3839 struct label_line *n;
3840
3841 n = (struct label_line *) xmalloc (sizeof *n);
3842 n->next = labels;
3843 n->label = sym;
3844 as_where (&n->file, &n->line);
3845 n->text = 0;
3846 labels = n;
3847 current_label = n;
3848 }
3849
3850 /* This is called when a value that is not an instruction is emitted. */
3851
3852 void
3853 m68k_flush_pending_output ()
3854 {
3855 current_label = NULL;
3856 }
3857
3858 /* This is called at the end of the assembly, when the final value of
3859 the label is known. We warn if this is a text symbol aligned at an
3860 odd location. */
3861
3862 void
3863 m68k_frob_symbol (sym)
3864 symbolS *sym;
3865 {
3866 if (S_GET_SEGMENT (sym) == reg_section
3867 && (int) S_GET_VALUE (sym) < 0)
3868 {
3869 S_SET_SEGMENT (sym, absolute_section);
3870 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
3871 }
3872 else if ((S_GET_VALUE (sym) & 1) != 0)
3873 {
3874 struct label_line *l;
3875
3876 for (l = labels; l != NULL; l = l->next)
3877 {
3878 if (l->label == sym)
3879 {
3880 if (l->text)
3881 as_warn_where (l->file, l->line,
3882 _("text label `%s' aligned to odd boundary"),
3883 S_GET_NAME (sym));
3884 break;
3885 }
3886 }
3887 }
3888 }
3889 \f
3890 /* This is called if we go in or out of MRI mode because of the .mri
3891 pseudo-op. */
3892
3893 void
3894 m68k_mri_mode_change (on)
3895 int on;
3896 {
3897 if (on)
3898 {
3899 if (! flag_reg_prefix_optional)
3900 {
3901 flag_reg_prefix_optional = 1;
3902 #ifdef REGISTER_PREFIX
3903 init_regtable ();
3904 #endif
3905 }
3906 m68k_abspcadd = 1;
3907 if (! m68k_rel32_from_cmdline)
3908 m68k_rel32 = 0;
3909 }
3910 else
3911 {
3912 if (! reg_prefix_optional_seen)
3913 {
3914 #ifdef REGISTER_PREFIX_OPTIONAL
3915 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3916 #else
3917 flag_reg_prefix_optional = 0;
3918 #endif
3919 #ifdef REGISTER_PREFIX
3920 init_regtable ();
3921 #endif
3922 }
3923 m68k_abspcadd = 0;
3924 if (! m68k_rel32_from_cmdline)
3925 m68k_rel32 = 1;
3926 }
3927 }
3928
3929 /* Equal to MAX_PRECISION in atof-ieee.c */
3930 #define MAX_LITTLENUMS 6
3931
3932 /* Turn a string in input_line_pointer into a floating point constant
3933 of type type, and store the appropriate bytes in *litP. The number
3934 of LITTLENUMS emitted is stored in *sizeP . An error message is
3935 returned, or NULL on OK. */
3936
3937 char *
3938 md_atof (type, litP, sizeP)
3939 char type;
3940 char *litP;
3941 int *sizeP;
3942 {
3943 int prec;
3944 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3945 LITTLENUM_TYPE *wordP;
3946 char *t;
3947
3948 switch (type)
3949 {
3950 case 'f':
3951 case 'F':
3952 case 's':
3953 case 'S':
3954 prec = 2;
3955 break;
3956
3957 case 'd':
3958 case 'D':
3959 case 'r':
3960 case 'R':
3961 prec = 4;
3962 break;
3963
3964 case 'x':
3965 case 'X':
3966 prec = 6;
3967 break;
3968
3969 case 'p':
3970 case 'P':
3971 prec = 6;
3972 break;
3973
3974 default:
3975 *sizeP = 0;
3976 return _("Bad call to MD_ATOF()");
3977 }
3978 t = atof_ieee (input_line_pointer, type, words);
3979 if (t)
3980 input_line_pointer = t;
3981
3982 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3983 for (wordP = words; prec--;)
3984 {
3985 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3986 litP += sizeof (LITTLENUM_TYPE);
3987 }
3988 return 0;
3989 }
3990
3991 void
3992 md_number_to_chars (buf, val, n)
3993 char *buf;
3994 valueT val;
3995 int n;
3996 {
3997 number_to_chars_bigendian (buf, val, n);
3998 }
3999
4000 static void
4001 md_apply_fix_2 (fixP, val)
4002 fixS *fixP;
4003 offsetT val;
4004 {
4005 addressT upper_limit;
4006 offsetT lower_limit;
4007
4008 /* This is unnecessary but it convinces the native rs6000 compiler
4009 to generate the code we want. */
4010 char *buf = fixP->fx_frag->fr_literal;
4011 buf += fixP->fx_where;
4012 /* end ibm compiler workaround */
4013
4014 if (val & 0x80000000)
4015 val |= ~(addressT)0x7fffffff;
4016 else
4017 val &= 0x7fffffff;
4018
4019 #ifdef OBJ_ELF
4020 if (fixP->fx_addsy)
4021 {
4022 memset (buf, 0, fixP->fx_size);
4023 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4024 return;
4025 }
4026 #endif
4027
4028 switch (fixP->fx_size)
4029 {
4030 /* The cast to offsetT below are necessary to make code correct for
4031 machines where ints are smaller than offsetT */
4032 case 1:
4033 *buf++ = val;
4034 upper_limit = 0x7f;
4035 lower_limit = - (offsetT) 0x80;
4036 break;
4037 case 2:
4038 *buf++ = (val >> 8);
4039 *buf++ = val;
4040 upper_limit = 0x7fff;
4041 lower_limit = - (offsetT) 0x8000;
4042 break;
4043 case 4:
4044 *buf++ = (val >> 24);
4045 *buf++ = (val >> 16);
4046 *buf++ = (val >> 8);
4047 *buf++ = val;
4048 upper_limit = 0x7fffffff;
4049 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4050 break;
4051 default:
4052 BAD_CASE (fixP->fx_size);
4053 }
4054
4055 /* Fix up a negative reloc. */
4056 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4057 {
4058 fixP->fx_addsy = fixP->fx_subsy;
4059 fixP->fx_subsy = NULL;
4060 fixP->fx_tcbit = 1;
4061 }
4062
4063 /* For non-pc-relative values, it's conceivable we might get something
4064 like "0xff" for a byte field. So extend the upper part of the range
4065 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4066 so that we can do any range checking at all. */
4067 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4068 upper_limit = upper_limit * 2 + 1;
4069
4070 if ((addressT) val > upper_limit
4071 && (val > 0 || val < lower_limit))
4072 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4073
4074 /* A one byte PC-relative reloc means a short branch. We can't use
4075 a short branch with a value of 0 or -1, because those indicate
4076 different opcodes (branches with longer offsets). fixup_segment
4077 in write.c may have clobbered fx_pcrel, so we need to examine the
4078 reloc type. */
4079 if ((fixP->fx_pcrel
4080 #ifdef BFD_ASSEMBLER
4081 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4082 #endif
4083 )
4084 && fixP->fx_size == 1
4085 && (fixP->fx_addsy == NULL
4086 || S_IS_DEFINED (fixP->fx_addsy))
4087 && (val == 0 || val == -1))
4088 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4089 }
4090
4091 #ifdef BFD_ASSEMBLER
4092 int
4093 md_apply_fix (fixP, valp)
4094 fixS *fixP;
4095 valueT *valp;
4096 {
4097 md_apply_fix_2 (fixP, (addressT) *valp);
4098 return 1;
4099 }
4100 #else
4101 void md_apply_fix (fixP, val)
4102 fixS *fixP;
4103 long val;
4104 {
4105 md_apply_fix_2 (fixP, (addressT) val);
4106 }
4107 #endif
4108
4109 /* *fragP has been relaxed to its final size, and now needs to have
4110 the bytes inside it modified to conform to the new size There is UGLY
4111 MAGIC here. ..
4112 */
4113 static void
4114 md_convert_frag_1 (fragP)
4115 register fragS *fragP;
4116 {
4117 long disp;
4118 long ext = 0;
4119 fixS *fixP;
4120
4121 /* Address in object code of the displacement. */
4122 register int object_address = fragP->fr_fix + fragP->fr_address;
4123
4124 /* Address in gas core of the place to store the displacement. */
4125 /* This convinces the native rs6000 compiler to generate the code we
4126 want. */
4127 register char *buffer_address = fragP->fr_literal;
4128 buffer_address += fragP->fr_fix;
4129 /* end ibm compiler workaround */
4130
4131 /* The displacement of the address, from current location. */
4132 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4133 disp = (disp + fragP->fr_offset) - object_address;
4134
4135 #ifdef BFD_ASSEMBLER
4136 disp += fragP->fr_symbol->sy_frag->fr_address;
4137 #endif
4138
4139 switch (fragP->fr_subtype)
4140 {
4141 case TAB (BCC68000, BYTE):
4142 case TAB (ABRANCH, BYTE):
4143 know (issbyte (disp));
4144 if (disp == 0)
4145 as_bad (_("short branch with zero offset: use :w"));
4146 fragP->fr_opcode[1] = disp;
4147 ext = 0;
4148 break;
4149 case TAB (DBCC, SHORT):
4150 know (issword (disp));
4151 ext = 2;
4152 break;
4153 case TAB (BCC68000, SHORT):
4154 case TAB (ABRANCH, SHORT):
4155 know (issword (disp));
4156 fragP->fr_opcode[1] = 0x00;
4157 ext = 2;
4158 break;
4159 case TAB (ABRANCH, LONG):
4160 if (!HAVE_LONG_BRANCH(current_architecture))
4161 {
4162 if (fragP->fr_opcode[0] == 0x61)
4163 /* BSR */
4164 {
4165 fragP->fr_opcode[0] = 0x4E;
4166 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4167
4168 fix_new (fragP,
4169 fragP->fr_fix,
4170 4,
4171 fragP->fr_symbol,
4172 fragP->fr_offset,
4173 0,
4174 NO_RELOC);
4175
4176 fragP->fr_fix += 4;
4177 ext = 0;
4178 }
4179 /* BRA */
4180 else if (fragP->fr_opcode[0] == 0x60)
4181 {
4182 fragP->fr_opcode[0] = 0x4E;
4183 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4184 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4185 fragP->fr_offset, 0, NO_RELOC);
4186 fragP->fr_fix += 4;
4187 ext = 0;
4188 }
4189 else
4190 {
4191 as_bad (_("Long branch offset not supported."));
4192 }
4193 }
4194 else
4195 {
4196 fragP->fr_opcode[1] = (char) 0xff;
4197 ext = 4;
4198 }
4199 break;
4200 case TAB (BCC68000, LONG):
4201 /* only Bcc 68000 instructions can come here */
4202 /* change bcc into b!cc/jmp absl long */
4203 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4204 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4205
4206 /* JF: these used to be fr_opcode[2,3], but they may be in a
4207 different frag, in which case refering to them is a no-no.
4208 Only fr_opcode[0,1] are guaranteed to work. */
4209 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4210 *buffer_address++ = (char) 0xf9;
4211 fragP->fr_fix += 2; /* account for jmp instruction */
4212 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4213 fragP->fr_offset, 0, NO_RELOC);
4214 fragP->fr_fix += 4;
4215 ext = 0;
4216 break;
4217 case TAB (DBCC, LONG):
4218 /* only DBcc 68000 instructions can come here */
4219 /* change dbcc into dbcc/jmp absl long */
4220 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4221 *buffer_address++ = 0x00; /* branch offset = 4 */
4222 *buffer_address++ = 0x04;
4223 *buffer_address++ = 0x60; /* put in bra pc+6 */
4224 *buffer_address++ = 0x06;
4225 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4226 *buffer_address++ = (char) 0xf9;
4227
4228 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4229 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4230 fragP->fr_offset, 0, NO_RELOC);
4231 fragP->fr_fix += 4;
4232 ext = 0;
4233 break;
4234 case TAB (FBRANCH, SHORT):
4235 know ((fragP->fr_opcode[1] & 0x40) == 0);
4236 ext = 2;
4237 break;
4238 case TAB (FBRANCH, LONG):
4239 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4240 ext = 4;
4241 break;
4242 case TAB (PCREL, SHORT):
4243 ext = 2;
4244 break;
4245 case TAB (PCREL, LONG):
4246 /* The thing to do here is force it to ABSOLUTE LONG, since
4247 PCREL is really trying to shorten an ABSOLUTE address anyway */
4248 /* JF FOO This code has not been tested */
4249 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4250 0, NO_RELOC);
4251 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4252 as_bad (_("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx"),
4253 (unsigned) fragP->fr_opcode[0],
4254 (unsigned long) fragP->fr_address);
4255 fragP->fr_opcode[1] &= ~0x3F;
4256 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4257 fragP->fr_fix += 4;
4258 ext = 0;
4259 break;
4260 case TAB (PCLEA, SHORT):
4261 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4262 fragP->fr_offset, 1, NO_RELOC);
4263 fragP->fr_opcode[1] &= ~0x3F;
4264 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4265 ext = 2;
4266 break;
4267 case TAB (PCLEA, LONG):
4268 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4269 fragP->fr_offset, 1, NO_RELOC);
4270 fixP->fx_pcrel_adjust = 2;
4271 /* Already set to mode 7.3; this indicates: PC indirect with
4272 suppressed index, 32-bit displacement. */
4273 *buffer_address++ = 0x01;
4274 *buffer_address++ = 0x70;
4275 fragP->fr_fix += 2;
4276 ext = 4;
4277 break;
4278
4279 case TAB (PCINDEX, BYTE):
4280 disp += 2;
4281 if (!issbyte (disp))
4282 {
4283 as_bad (_("displacement doesn't fit in one byte"));
4284 disp = 0;
4285 }
4286 assert (fragP->fr_fix >= 2);
4287 buffer_address[-2] &= ~1;
4288 buffer_address[-1] = disp;
4289 ext = 0;
4290 break;
4291 case TAB (PCINDEX, SHORT):
4292 disp += 2;
4293 assert (issword (disp));
4294 assert (fragP->fr_fix >= 2);
4295 buffer_address[-2] |= 0x1;
4296 buffer_address[-1] = 0x20;
4297 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4298 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4299 NO_RELOC);
4300 fixP->fx_pcrel_adjust = 2;
4301 ext = 2;
4302 break;
4303 case TAB (PCINDEX, LONG):
4304 disp += 2;
4305 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4306 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4307 NO_RELOC);
4308 fixP->fx_pcrel_adjust = 2;
4309 assert (fragP->fr_fix >= 2);
4310 buffer_address[-2] |= 0x1;
4311 buffer_address[-1] = 0x30;
4312 ext = 4;
4313 break;
4314 }
4315
4316 if (ext)
4317 {
4318 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4319 fragP->fr_fix += ext;
4320 }
4321 }
4322
4323 #ifndef BFD_ASSEMBLER
4324
4325 void
4326 md_convert_frag (headers, sec, fragP)
4327 object_headers *headers;
4328 segT sec;
4329 fragS *fragP;
4330 {
4331 md_convert_frag_1 (fragP);
4332 }
4333
4334 #else
4335
4336 void
4337 md_convert_frag (abfd, sec, fragP)
4338 bfd *abfd;
4339 segT sec;
4340 fragS *fragP;
4341 {
4342 md_convert_frag_1 (fragP);
4343 }
4344 #endif
4345
4346 /* Force truly undefined symbols to their maximum size, and generally set up
4347 the frag list to be relaxed
4348 */
4349 int
4350 md_estimate_size_before_relax (fragP, segment)
4351 register fragS *fragP;
4352 segT segment;
4353 {
4354 int old_fix;
4355 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4356
4357 old_fix = fragP->fr_fix;
4358
4359 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4360 switch (fragP->fr_subtype)
4361 {
4362
4363 case TAB (ABRANCH, SZ_UNDEF):
4364 {
4365 if ((fragP->fr_symbol != NULL) /* Not absolute */
4366 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4367 {
4368 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4369 break;
4370 }
4371 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4372 {
4373 /* On 68000, or for absolute value, switch to abs long */
4374 /* FIXME, we should check abs val, pick short or long */
4375 if (fragP->fr_opcode[0] == 0x61)
4376 {
4377 fragP->fr_opcode[0] = 0x4E;
4378 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4379 fix_new (fragP, fragP->fr_fix, 4,
4380 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4381 fragP->fr_fix += 4;
4382 frag_wane (fragP);
4383 }
4384 else if (fragP->fr_opcode[0] == 0x60)
4385 {
4386 fragP->fr_opcode[0] = 0x4E;
4387 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4388 fix_new (fragP, fragP->fr_fix, 4,
4389 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4390 fragP->fr_fix += 4;
4391 frag_wane (fragP);
4392 }
4393 else
4394 {
4395 as_warn (_("Long branch offset to extern symbol not supported."));
4396 }
4397 }
4398 else
4399 { /* Symbol is still undefined. Make it simple */
4400 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4401 fragP->fr_offset, 1, NO_RELOC);
4402 fragP->fr_fix += 4;
4403 fragP->fr_opcode[1] = (char) 0xff;
4404 frag_wane (fragP);
4405 break;
4406 }
4407
4408 break;
4409 } /* case TAB(ABRANCH,SZ_UNDEF) */
4410
4411 case TAB (FBRANCH, SZ_UNDEF):
4412 {
4413 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4414 {
4415 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4416 fragP->fr_var += 2;
4417 }
4418 else
4419 {
4420 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4421 fragP->fr_offset, 1, NO_RELOC);
4422 fragP->fr_fix += 4;
4423 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4424 frag_wane (fragP);
4425 }
4426 break;
4427 } /* TAB(FBRANCH,SZ_UNDEF) */
4428
4429 case TAB (PCREL, SZ_UNDEF):
4430 {
4431 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4432 || flag_short_refs
4433 || cpu_of_arch (current_architecture) < m68020
4434 || cpu_of_arch (current_architecture) == mcf5200)
4435 {
4436 fragP->fr_subtype = TAB (PCREL, SHORT);
4437 fragP->fr_var += 2;
4438 }
4439 else
4440 {
4441 fragP->fr_subtype = TAB (PCREL, LONG);
4442 fragP->fr_var += 4;
4443 }
4444 break;
4445 } /* TAB(PCREL,SZ_UNDEF) */
4446
4447 case TAB (BCC68000, SZ_UNDEF):
4448 {
4449 if ((fragP->fr_symbol != NULL)
4450 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4451 {
4452 fragP->fr_subtype = TAB (BCC68000, BYTE);
4453 break;
4454 }
4455 /* only Bcc 68000 instructions can come here */
4456 /* change bcc into b!cc/jmp absl long */
4457 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4458 if (flag_short_refs)
4459 {
4460 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4461 /* JF: these were fr_opcode[2,3] */
4462 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4463 buffer_address[1] = (char) 0xf8;
4464 fragP->fr_fix += 2; /* account for jmp instruction */
4465 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4466 fragP->fr_offset, 0, NO_RELOC);
4467 fragP->fr_fix += 2;
4468 }
4469 else
4470 {
4471 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4472 /* JF: these were fr_opcode[2,3] */
4473 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4474 buffer_address[1] = (char) 0xf9;
4475 fragP->fr_fix += 2; /* account for jmp instruction */
4476 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4477 fragP->fr_offset, 0, NO_RELOC);
4478 fragP->fr_fix += 4;
4479 }
4480 frag_wane (fragP);
4481 break;
4482 } /* case TAB(BCC68000,SZ_UNDEF) */
4483
4484 case TAB (DBCC, SZ_UNDEF):
4485 {
4486 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4487 {
4488 fragP->fr_subtype = TAB (DBCC, SHORT);
4489 fragP->fr_var += 2;
4490 break;
4491 }
4492 /* only DBcc 68000 instructions can come here */
4493 /* change dbcc into dbcc/jmp absl long */
4494 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4495 buffer_address[0] = 0x00; /* branch offset = 4 */
4496 buffer_address[1] = 0x04;
4497 buffer_address[2] = 0x60; /* put in bra pc + ... */
4498
4499 if (flag_short_refs)
4500 {
4501 /* JF: these were fr_opcode[5-7] */
4502 buffer_address[3] = 0x04; /* plus 4 */
4503 buffer_address[4] = 0x4e; /* Put in Jump Word */
4504 buffer_address[5] = (char) 0xf8;
4505 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4506 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4507 fragP->fr_offset, 0, NO_RELOC);
4508 fragP->fr_fix += 2;
4509 }
4510 else
4511 {
4512 /* JF: these were fr_opcode[5-7] */
4513 buffer_address[3] = 0x06; /* Plus 6 */
4514 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4515 buffer_address[5] = (char) 0xf9;
4516 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4517 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4518 fragP->fr_offset, 0, NO_RELOC);
4519 fragP->fr_fix += 4;
4520 }
4521
4522 frag_wane (fragP);
4523 break;
4524 } /* case TAB(DBCC,SZ_UNDEF) */
4525
4526 case TAB (PCLEA, SZ_UNDEF):
4527 {
4528 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4529 || flag_short_refs
4530 || cpu_of_arch (current_architecture) < m68020
4531 || cpu_of_arch (current_architecture) == mcf5200)
4532 {
4533 fragP->fr_subtype = TAB (PCLEA, SHORT);
4534 fragP->fr_var += 2;
4535 }
4536 else
4537 {
4538 fragP->fr_subtype = TAB (PCLEA, LONG);
4539 fragP->fr_var += 6;
4540 }
4541 break;
4542 } /* TAB(PCLEA,SZ_UNDEF) */
4543
4544 case TAB (PCINDEX, SZ_UNDEF):
4545 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4546 || cpu_of_arch (current_architecture) < m68020
4547 || cpu_of_arch (current_architecture) == mcf5200)
4548 {
4549 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4550 }
4551 else
4552 {
4553 fragP->fr_subtype = TAB (PCINDEX, LONG);
4554 fragP->fr_var += 4;
4555 }
4556 break;
4557
4558 default:
4559 break;
4560 }
4561
4562 /* now that SZ_UNDEF are taken care of, check others */
4563 switch (fragP->fr_subtype)
4564 {
4565 case TAB (BCC68000, BYTE):
4566 case TAB (ABRANCH, BYTE):
4567 /* We can't do a short jump to the next instruction, so in that
4568 case we force word mode. At this point S_GET_VALUE should
4569 return the offset of the symbol within its frag. If the
4570 symbol is at the start of a frag, and it is the next frag
4571 with any data in it (usually this is just the next frag, but
4572 assembler listings may introduce empty frags), we must use
4573 word mode. */
4574 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4575 {
4576 fragS *l;
4577
4578 for (l = fragP->fr_next;
4579 l != fragP->fr_symbol->sy_frag;
4580 l = l->fr_next)
4581 if (l->fr_fix + l->fr_var != 0)
4582 break;
4583 if (l == fragP->fr_symbol->sy_frag)
4584 {
4585 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4586 fragP->fr_var += 2;
4587 }
4588 }
4589 break;
4590 default:
4591 break;
4592 }
4593 return fragP->fr_var + fragP->fr_fix - old_fix;
4594 }
4595
4596 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4597 /* the bit-field entries in the relocation_info struct plays hell
4598 with the byte-order problems of cross-assembly. So as a hack,
4599 I added this mach. dependent ri twiddler. Ugly, but it gets
4600 you there. -KWK */
4601 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4602 are symbolnum, most sig. byte first. Last byte is broken up with
4603 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4604 nibble as nuthin. (on Sun 3 at least) */
4605 /* Translate the internal relocation information into target-specific
4606 format. */
4607 #ifdef comment
4608 void
4609 md_ri_to_chars (the_bytes, ri)
4610 char *the_bytes;
4611 struct reloc_info_generic *ri;
4612 {
4613 /* this is easy */
4614 md_number_to_chars (the_bytes, ri->r_address, 4);
4615 /* now the fun stuff */
4616 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4617 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4618 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4619 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4620 ((ri->r_extern << 4) & 0x10));
4621 }
4622
4623 #endif /* comment */
4624
4625 #ifndef BFD_ASSEMBLER
4626 void
4627 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4628 char *where;
4629 fixS *fixP;
4630 relax_addressT segment_address_in_file;
4631 {
4632 /*
4633 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4634 * Out: GNU LD relocation length code: 0, 1, or 2.
4635 */
4636
4637 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4638 long r_symbolnum;
4639
4640 know (fixP->fx_addsy != NULL);
4641
4642 md_number_to_chars (where,
4643 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4644 4);
4645
4646 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4647 ? S_GET_TYPE (fixP->fx_addsy)
4648 : fixP->fx_addsy->sy_number);
4649
4650 where[4] = (r_symbolnum >> 16) & 0x0ff;
4651 where[5] = (r_symbolnum >> 8) & 0x0ff;
4652 where[6] = r_symbolnum & 0x0ff;
4653 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4654 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4655 }
4656 #endif
4657
4658 #endif /* OBJ_AOUT or OBJ_BOUT */
4659
4660 #ifndef WORKING_DOT_WORD
4661 CONST int md_short_jump_size = 4;
4662 CONST int md_long_jump_size = 6;
4663
4664 void
4665 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4666 char *ptr;
4667 addressT from_addr, to_addr;
4668 fragS *frag;
4669 symbolS *to_symbol;
4670 {
4671 valueT offset;
4672
4673 offset = to_addr - (from_addr + 2);
4674
4675 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4676 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4677 }
4678
4679 void
4680 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4681 char *ptr;
4682 addressT from_addr, to_addr;
4683 fragS *frag;
4684 symbolS *to_symbol;
4685 {
4686 valueT offset;
4687
4688 if (!HAVE_LONG_BRANCH(current_architecture))
4689 {
4690 offset = to_addr - S_GET_VALUE (to_symbol);
4691 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4692 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4693 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4694 0, NO_RELOC);
4695 }
4696 else
4697 {
4698 offset = to_addr - (from_addr + 2);
4699 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4700 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4701 }
4702 }
4703
4704 #endif
4705
4706 /* Different values of OK tell what its OK to return. Things that
4707 aren't OK are an error (what a shock, no?)
4708
4709 0: Everything is OK
4710 10: Absolute 1:8 only
4711 20: Absolute 0:7 only
4712 30: absolute 0:15 only
4713 40: Absolute 0:31 only
4714 50: absolute 0:127 only
4715 55: absolute -64:63 only
4716 60: absolute -128:127 only
4717 70: absolute 0:4095 only
4718 80: No bignums
4719
4720 */
4721
4722 static int
4723 get_num (exp, ok)
4724 struct m68k_exp *exp;
4725 int ok;
4726 {
4727 if (exp->exp.X_op == O_absent)
4728 {
4729 /* Do the same thing the VAX asm does */
4730 op (exp) = O_constant;
4731 adds (exp) = 0;
4732 subs (exp) = 0;
4733 offs (exp) = 0;
4734 if (ok == 10)
4735 {
4736 as_warn (_("expression out of range: defaulting to 1"));
4737 offs (exp) = 1;
4738 }
4739 }
4740 else if (exp->exp.X_op == O_constant)
4741 {
4742 switch (ok)
4743 {
4744 case 10:
4745 if (offs (exp) < 1 || offs (exp) > 8)
4746 {
4747 as_warn (_("expression out of range: defaulting to 1"));
4748 offs (exp) = 1;
4749 }
4750 break;
4751 case 20:
4752 if (offs (exp) < 0 || offs (exp) > 7)
4753 goto outrange;
4754 break;
4755 case 30:
4756 if (offs (exp) < 0 || offs (exp) > 15)
4757 goto outrange;
4758 break;
4759 case 40:
4760 if (offs (exp) < 0 || offs (exp) > 32)
4761 goto outrange;
4762 break;
4763 case 50:
4764 if (offs (exp) < 0 || offs (exp) > 127)
4765 goto outrange;
4766 break;
4767 case 55:
4768 if (offs (exp) < -64 || offs (exp) > 63)
4769 goto outrange;
4770 break;
4771 case 60:
4772 if (offs (exp) < -128 || offs (exp) > 127)
4773 goto outrange;
4774 break;
4775 case 70:
4776 if (offs (exp) < 0 || offs (exp) > 4095)
4777 {
4778 outrange:
4779 as_warn (_("expression out of range: defaulting to 0"));
4780 offs (exp) = 0;
4781 }
4782 break;
4783 default:
4784 break;
4785 }
4786 }
4787 else if (exp->exp.X_op == O_big)
4788 {
4789 if (offs (exp) <= 0 /* flonum */
4790 && (ok == 80 /* no bignums */
4791 || (ok > 10 /* small-int ranges including 0 ok */
4792 /* If we have a flonum zero, a zero integer should
4793 do as well (e.g., in moveq). */
4794 && generic_floating_point_number.exponent == 0
4795 && generic_floating_point_number.low[0] == 0)))
4796 {
4797 /* HACK! Turn it into a long */
4798 LITTLENUM_TYPE words[6];
4799
4800 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4801 op (exp) = O_constant;
4802 adds (exp) = 0;
4803 subs (exp) = 0;
4804 offs (exp) = words[1] | (words[0] << 16);
4805 }
4806 else if (ok != 0)
4807 {
4808 op (exp) = O_constant;
4809 adds (exp) = 0;
4810 subs (exp) = 0;
4811 offs (exp) = (ok == 10) ? 1 : 0;
4812 as_warn (_("Can't deal with expression; defaulting to %ld"),
4813 offs (exp));
4814 }
4815 }
4816 else
4817 {
4818 if (ok >= 10 && ok <= 70)
4819 {
4820 op (exp) = O_constant;
4821 adds (exp) = 0;
4822 subs (exp) = 0;
4823 offs (exp) = (ok == 10) ? 1 : 0;
4824 as_warn (_("Can't deal with expression; defaulting to %ld"),
4825 offs (exp));
4826 }
4827 }
4828
4829 if (exp->size != SIZE_UNSPEC)
4830 {
4831 switch (exp->size)
4832 {
4833 case SIZE_UNSPEC:
4834 case SIZE_LONG:
4835 break;
4836 case SIZE_BYTE:
4837 if (!isbyte (offs (exp)))
4838 as_warn (_("expression doesn't fit in BYTE"));
4839 break;
4840 case SIZE_WORD:
4841 if (!isword (offs (exp)))
4842 as_warn (_("expression doesn't fit in WORD"));
4843 break;
4844 }
4845 }
4846
4847 return offs (exp);
4848 }
4849
4850 /* These are the back-ends for the various machine dependent pseudo-ops. */
4851
4852 static void
4853 s_data1 (ignore)
4854 int ignore;
4855 {
4856 subseg_set (data_section, 1);
4857 demand_empty_rest_of_line ();
4858 }
4859
4860 static void
4861 s_data2 (ignore)
4862 int ignore;
4863 {
4864 subseg_set (data_section, 2);
4865 demand_empty_rest_of_line ();
4866 }
4867
4868 static void
4869 s_bss (ignore)
4870 int ignore;
4871 {
4872 /* We don't support putting frags in the BSS segment, we fake it
4873 by marking in_bss, then looking at s_skip for clues. */
4874
4875 subseg_set (bss_section, 0);
4876 demand_empty_rest_of_line ();
4877 }
4878
4879 static void
4880 s_even (ignore)
4881 int ignore;
4882 {
4883 register int temp;
4884 register long temp_fill;
4885
4886 temp = 1; /* JF should be 2? */
4887 temp_fill = get_absolute_expression ();
4888 if (!need_pass_2) /* Never make frag if expect extra pass. */
4889 frag_align (temp, (int) temp_fill, 0);
4890 demand_empty_rest_of_line ();
4891 record_alignment (now_seg, temp);
4892 }
4893
4894 static void
4895 s_proc (ignore)
4896 int ignore;
4897 {
4898 demand_empty_rest_of_line ();
4899 }
4900 \f
4901 /* Pseudo-ops handled for MRI compatibility. */
4902
4903 /* This function returns non-zero if the argument is a conditional
4904 pseudo-op. This is called when checking whether a pending
4905 alignment is needed. */
4906
4907 int
4908 m68k_conditional_pseudoop (pop)
4909 pseudo_typeS *pop;
4910 {
4911 return (pop->poc_handler == s_mri_if
4912 || pop->poc_handler == s_mri_else);
4913 }
4914
4915 /* Handle an MRI style chip specification. */
4916
4917 static void
4918 mri_chip ()
4919 {
4920 char *s;
4921 char c;
4922 int i;
4923
4924 s = input_line_pointer;
4925 /* We can't use get_symbol_end since the processor names are not proper
4926 symbols. */
4927 while (is_part_of_name (c = *input_line_pointer++))
4928 ;
4929 *--input_line_pointer = 0;
4930 for (i = 0; i < n_archs; i++)
4931 if (strcasecmp (s, archs[i].name) == 0)
4932 break;
4933 if (i >= n_archs)
4934 {
4935 as_bad (_("%s: unrecognized processor name"), s);
4936 *input_line_pointer = c;
4937 ignore_rest_of_line ();
4938 return;
4939 }
4940 *input_line_pointer = c;
4941
4942 if (*input_line_pointer == '/')
4943 current_architecture = 0;
4944 else
4945 current_architecture &= m68881 | m68851;
4946 current_architecture |= archs[i].arch;
4947
4948 while (*input_line_pointer == '/')
4949 {
4950 ++input_line_pointer;
4951 s = input_line_pointer;
4952 /* We can't use get_symbol_end since the processor names are not
4953 proper symbols. */
4954 while (is_part_of_name (c = *input_line_pointer++))
4955 ;
4956 *--input_line_pointer = 0;
4957 if (strcmp (s, "68881") == 0)
4958 current_architecture |= m68881;
4959 else if (strcmp (s, "68851") == 0)
4960 current_architecture |= m68851;
4961 *input_line_pointer = c;
4962 }
4963
4964 /* Update info about available control registers. */
4965 select_control_regs ();
4966 }
4967
4968 /* The MRI CHIP pseudo-op. */
4969
4970 static void
4971 s_chip (ignore)
4972 int ignore;
4973 {
4974 char *stop = NULL;
4975 char stopc;
4976
4977 if (flag_mri)
4978 stop = mri_comment_field (&stopc);
4979 mri_chip ();
4980 if (flag_mri)
4981 mri_comment_end (stop, stopc);
4982 demand_empty_rest_of_line ();
4983 }
4984
4985 /* The MRI FOPT pseudo-op. */
4986
4987 static void
4988 s_fopt (ignore)
4989 int ignore;
4990 {
4991 SKIP_WHITESPACE ();
4992
4993 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4994 {
4995 int temp;
4996
4997 input_line_pointer += 3;
4998 temp = get_absolute_expression ();
4999 if (temp < 0 || temp > 7)
5000 as_bad (_("bad coprocessor id"));
5001 else
5002 m68k_float_copnum = COP0 + temp;
5003 }
5004 else
5005 {
5006 as_bad (_("unrecognized fopt option"));
5007 ignore_rest_of_line ();
5008 return;
5009 }
5010
5011 demand_empty_rest_of_line ();
5012 }
5013
5014 /* The structure used to handle the MRI OPT pseudo-op. */
5015
5016 struct opt_action
5017 {
5018 /* The name of the option. */
5019 const char *name;
5020
5021 /* If this is not NULL, just call this function. The first argument
5022 is the ARG field of this structure, the second argument is
5023 whether the option was negated. */
5024 void (*pfn) PARAMS ((int arg, int on));
5025
5026 /* If this is not NULL, and the PFN field is NULL, set the variable
5027 this points to. Set it to the ARG field if the option was not
5028 negated, and the NOTARG field otherwise. */
5029 int *pvar;
5030
5031 /* The value to pass to PFN or to assign to *PVAR. */
5032 int arg;
5033
5034 /* The value to assign to *PVAR if the option is negated. If PFN is
5035 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5036 the option may not be negated. */
5037 int notarg;
5038 };
5039
5040 /* The table used to handle the MRI OPT pseudo-op. */
5041
5042 static void skip_to_comma PARAMS ((int, int));
5043 static void opt_nest PARAMS ((int, int));
5044 static void opt_chip PARAMS ((int, int));
5045 static void opt_list PARAMS ((int, int));
5046 static void opt_list_symbols PARAMS ((int, int));
5047
5048 static const struct opt_action opt_table[] =
5049 {
5050 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5051
5052 /* We do relaxing, so there is little use for these options. */
5053 { "b", 0, 0, 0, 0 },
5054 { "brs", 0, 0, 0, 0 },
5055 { "brb", 0, 0, 0, 0 },
5056 { "brl", 0, 0, 0, 0 },
5057 { "brw", 0, 0, 0, 0 },
5058
5059 { "c", 0, 0, 0, 0 },
5060 { "cex", 0, 0, 0, 0 },
5061 { "case", 0, &symbols_case_sensitive, 1, 0 },
5062 { "cl", 0, 0, 0, 0 },
5063 { "cre", 0, 0, 0, 0 },
5064 { "d", 0, &flag_keep_locals, 1, 0 },
5065 { "e", 0, 0, 0, 0 },
5066 { "f", 0, &flag_short_refs, 1, 0 },
5067 { "frs", 0, &flag_short_refs, 1, 0 },
5068 { "frl", 0, &flag_short_refs, 0, 1 },
5069 { "g", 0, 0, 0, 0 },
5070 { "i", 0, 0, 0, 0 },
5071 { "m", 0, 0, 0, 0 },
5072 { "mex", 0, 0, 0, 0 },
5073 { "mc", 0, 0, 0, 0 },
5074 { "md", 0, 0, 0, 0 },
5075 { "nest", opt_nest, 0, 0, 0 },
5076 { "next", skip_to_comma, 0, 0, 0 },
5077 { "o", 0, 0, 0, 0 },
5078 { "old", 0, 0, 0, 0 },
5079 { "op", skip_to_comma, 0, 0, 0 },
5080 { "pco", 0, 0, 0, 0 },
5081 { "p", opt_chip, 0, 0, 0 },
5082 { "pcr", 0, 0, 0, 0 },
5083 { "pcs", 0, 0, 0, 0 },
5084 { "r", 0, 0, 0, 0 },
5085 { "quick", 0, &m68k_quick, 1, 0 },
5086 { "rel32", 0, &m68k_rel32, 1, 0 },
5087 { "s", opt_list, 0, 0, 0 },
5088 { "t", opt_list_symbols, 0, 0, 0 },
5089 { "w", 0, &flag_no_warnings, 0, 1 },
5090 { "x", 0, 0, 0, 0 }
5091 };
5092
5093 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5094
5095 /* The MRI OPT pseudo-op. */
5096
5097 static void
5098 s_opt (ignore)
5099 int ignore;
5100 {
5101 do
5102 {
5103 int t;
5104 char *s;
5105 char c;
5106 int i;
5107 const struct opt_action *o;
5108
5109 SKIP_WHITESPACE ();
5110
5111 t = 1;
5112 if (*input_line_pointer == '-')
5113 {
5114 ++input_line_pointer;
5115 t = 0;
5116 }
5117 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5118 {
5119 input_line_pointer += 2;
5120 t = 0;
5121 }
5122
5123 s = input_line_pointer;
5124 c = get_symbol_end ();
5125
5126 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5127 {
5128 if (strcasecmp (s, o->name) == 0)
5129 {
5130 if (o->pfn)
5131 {
5132 /* Restore input_line_pointer now in case the option
5133 takes arguments. */
5134 *input_line_pointer = c;
5135 (*o->pfn) (o->arg, t);
5136 }
5137 else if (o->pvar != NULL)
5138 {
5139 if (! t && o->arg == o->notarg)
5140 as_bad (_("option `%s' may not be negated"), s);
5141 *input_line_pointer = c;
5142 *o->pvar = t ? o->arg : o->notarg;
5143 }
5144 else
5145 *input_line_pointer = c;
5146 break;
5147 }
5148 }
5149 if (i >= OPTCOUNT)
5150 {
5151 as_bad (_("option `%s' not recognized"), s);
5152 *input_line_pointer = c;
5153 }
5154 }
5155 while (*input_line_pointer++ == ',');
5156
5157 /* Move back to terminating character. */
5158 --input_line_pointer;
5159 demand_empty_rest_of_line ();
5160 }
5161
5162 /* Skip ahead to a comma. This is used for OPT options which we do
5163 not suppor tand which take arguments. */
5164
5165 static void
5166 skip_to_comma (arg, on)
5167 int arg;
5168 int on;
5169 {
5170 while (*input_line_pointer != ','
5171 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5172 ++input_line_pointer;
5173 }
5174
5175 /* Handle the OPT NEST=depth option. */
5176
5177 static void
5178 opt_nest (arg, on)
5179 int arg;
5180 int on;
5181 {
5182 if (*input_line_pointer != '=')
5183 {
5184 as_bad (_("bad format of OPT NEST=depth"));
5185 return;
5186 }
5187
5188 ++input_line_pointer;
5189 max_macro_nest = get_absolute_expression ();
5190 }
5191
5192 /* Handle the OPT P=chip option. */
5193
5194 static void
5195 opt_chip (arg, on)
5196 int arg;
5197 int on;
5198 {
5199 if (*input_line_pointer != '=')
5200 {
5201 /* This is just OPT P, which we do not support. */
5202 return;
5203 }
5204
5205 ++input_line_pointer;
5206 mri_chip ();
5207 }
5208
5209 /* Handle the OPT S option. */
5210
5211 static void
5212 opt_list (arg, on)
5213 int arg;
5214 int on;
5215 {
5216 listing_list (on);
5217 }
5218
5219 /* Handle the OPT T option. */
5220
5221 static void
5222 opt_list_symbols (arg, on)
5223 int arg;
5224 int on;
5225 {
5226 if (on)
5227 listing |= LISTING_SYMBOLS;
5228 else
5229 listing &=~ LISTING_SYMBOLS;
5230 }
5231
5232 /* Handle the MRI REG pseudo-op. */
5233
5234 static void
5235 s_reg (ignore)
5236 int ignore;
5237 {
5238 char *s;
5239 int c;
5240 struct m68k_op rop;
5241 int mask;
5242 char *stop = NULL;
5243 char stopc;
5244
5245 if (line_label == NULL)
5246 {
5247 as_bad (_("missing label"));
5248 ignore_rest_of_line ();
5249 return;
5250 }
5251
5252 if (flag_mri)
5253 stop = mri_comment_field (&stopc);
5254
5255 SKIP_WHITESPACE ();
5256
5257 s = input_line_pointer;
5258 while (isalnum ((unsigned char) *input_line_pointer)
5259 #ifdef REGISTER_PREFIX
5260 || *input_line_pointer == REGISTER_PREFIX
5261 #endif
5262 || *input_line_pointer == '/'
5263 || *input_line_pointer == '-')
5264 ++input_line_pointer;
5265 c = *input_line_pointer;
5266 *input_line_pointer = '\0';
5267
5268 if (m68k_ip_op (s, &rop) != 0)
5269 {
5270 if (rop.error == NULL)
5271 as_bad (_("bad register list"));
5272 else
5273 as_bad (_("bad register list: %s"), rop.error);
5274 *input_line_pointer = c;
5275 ignore_rest_of_line ();
5276 return;
5277 }
5278
5279 *input_line_pointer = c;
5280
5281 if (rop.mode == REGLST)
5282 mask = rop.mask;
5283 else if (rop.mode == DREG)
5284 mask = 1 << (rop.reg - DATA0);
5285 else if (rop.mode == AREG)
5286 mask = 1 << (rop.reg - ADDR0 + 8);
5287 else if (rop.mode == FPREG)
5288 mask = 1 << (rop.reg - FP0 + 16);
5289 else if (rop.mode == CONTROL
5290 && rop.reg == FPI)
5291 mask = 1 << 24;
5292 else if (rop.mode == CONTROL
5293 && rop.reg == FPS)
5294 mask = 1 << 25;
5295 else if (rop.mode == CONTROL
5296 && rop.reg == FPC)
5297 mask = 1 << 26;
5298 else
5299 {
5300 as_bad (_("bad register list"));
5301 ignore_rest_of_line ();
5302 return;
5303 }
5304
5305 S_SET_SEGMENT (line_label, reg_section);
5306 S_SET_VALUE (line_label, ~mask);
5307 line_label->sy_frag = &zero_address_frag;
5308
5309 if (flag_mri)
5310 mri_comment_end (stop, stopc);
5311
5312 demand_empty_rest_of_line ();
5313 }
5314
5315 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5316
5317 struct save_opts
5318 {
5319 struct save_opts *next;
5320 int abspcadd;
5321 int symbols_case_sensitive;
5322 int keep_locals;
5323 int short_refs;
5324 int architecture;
5325 int quick;
5326 int rel32;
5327 int listing;
5328 int no_warnings;
5329 /* FIXME: We don't save OPT S. */
5330 };
5331
5332 /* This variable holds the stack of saved options. */
5333
5334 static struct save_opts *save_stack;
5335
5336 /* The MRI SAVE pseudo-op. */
5337
5338 static void
5339 s_save (ignore)
5340 int ignore;
5341 {
5342 struct save_opts *s;
5343
5344 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5345 s->abspcadd = m68k_abspcadd;
5346 s->symbols_case_sensitive = symbols_case_sensitive;
5347 s->keep_locals = flag_keep_locals;
5348 s->short_refs = flag_short_refs;
5349 s->architecture = current_architecture;
5350 s->quick = m68k_quick;
5351 s->rel32 = m68k_rel32;
5352 s->listing = listing;
5353 s->no_warnings = flag_no_warnings;
5354
5355 s->next = save_stack;
5356 save_stack = s;
5357
5358 demand_empty_rest_of_line ();
5359 }
5360
5361 /* The MRI RESTORE pseudo-op. */
5362
5363 static void
5364 s_restore (ignore)
5365 int ignore;
5366 {
5367 struct save_opts *s;
5368
5369 if (save_stack == NULL)
5370 {
5371 as_bad (_("restore without save"));
5372 ignore_rest_of_line ();
5373 return;
5374 }
5375
5376 s = save_stack;
5377 save_stack = s->next;
5378
5379 m68k_abspcadd = s->abspcadd;
5380 symbols_case_sensitive = s->symbols_case_sensitive;
5381 flag_keep_locals = s->keep_locals;
5382 flag_short_refs = s->short_refs;
5383 current_architecture = s->architecture;
5384 m68k_quick = s->quick;
5385 m68k_rel32 = s->rel32;
5386 listing = s->listing;
5387 flag_no_warnings = s->no_warnings;
5388
5389 free (s);
5390
5391 demand_empty_rest_of_line ();
5392 }
5393
5394 /* Types of MRI structured control directives. */
5395
5396 enum mri_control_type
5397 {
5398 mri_for,
5399 mri_if,
5400 mri_repeat,
5401 mri_while
5402 };
5403
5404 /* This structure is used to stack the MRI structured control
5405 directives. */
5406
5407 struct mri_control_info
5408 {
5409 /* The directive within which this one is enclosed. */
5410 struct mri_control_info *outer;
5411
5412 /* The type of directive. */
5413 enum mri_control_type type;
5414
5415 /* Whether an ELSE has been in an IF. */
5416 int else_seen;
5417
5418 /* The add or sub statement at the end of a FOR. */
5419 char *incr;
5420
5421 /* The label of the top of a FOR or REPEAT loop. */
5422 char *top;
5423
5424 /* The label to jump to for the next iteration, or the else
5425 expression of a conditional. */
5426 char *next;
5427
5428 /* The label to jump to to break out of the loop, or the label past
5429 the end of a conditional. */
5430 char *bottom;
5431 };
5432
5433 /* The stack of MRI structured control directives. */
5434
5435 static struct mri_control_info *mri_control_stack;
5436
5437 /* The current MRI structured control directive index number, used to
5438 generate label names. */
5439
5440 static int mri_control_index;
5441
5442 /* Some function prototypes. */
5443
5444 static char *mri_control_label PARAMS ((void));
5445 static struct mri_control_info *push_mri_control
5446 PARAMS ((enum mri_control_type));
5447 static void pop_mri_control PARAMS ((void));
5448 static int parse_mri_condition PARAMS ((int *));
5449 static int parse_mri_control_operand
5450 PARAMS ((int *, char **, char **, char **, char **));
5451 static int swap_mri_condition PARAMS ((int));
5452 static int reverse_mri_condition PARAMS ((int));
5453 static void build_mri_control_operand
5454 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5455 const char *, int));
5456 static void parse_mri_control_expression
5457 PARAMS ((char *, int, const char *, const char *, int));
5458
5459 /* Generate a new MRI label structured control directive label name. */
5460
5461 static char *
5462 mri_control_label ()
5463 {
5464 char *n;
5465
5466 n = (char *) xmalloc (20);
5467 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5468 ++mri_control_index;
5469 return n;
5470 }
5471
5472 /* Create a new MRI structured control directive. */
5473
5474 static struct mri_control_info *
5475 push_mri_control (type)
5476 enum mri_control_type type;
5477 {
5478 struct mri_control_info *n;
5479
5480 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5481
5482 n->type = type;
5483 n->else_seen = 0;
5484 if (type == mri_if || type == mri_while)
5485 n->top = NULL;
5486 else
5487 n->top = mri_control_label ();
5488 n->next = mri_control_label ();
5489 n->bottom = mri_control_label ();
5490
5491 n->outer = mri_control_stack;
5492 mri_control_stack = n;
5493
5494 return n;
5495 }
5496
5497 /* Pop off the stack of MRI structured control directives. */
5498
5499 static void
5500 pop_mri_control ()
5501 {
5502 struct mri_control_info *n;
5503
5504 n = mri_control_stack;
5505 mri_control_stack = n->outer;
5506 if (n->top != NULL)
5507 free (n->top);
5508 free (n->next);
5509 free (n->bottom);
5510 free (n);
5511 }
5512
5513 /* Recognize a condition code in an MRI structured control expression. */
5514
5515 static int
5516 parse_mri_condition (pcc)
5517 int *pcc;
5518 {
5519 char c1, c2;
5520
5521 know (*input_line_pointer == '<');
5522
5523 ++input_line_pointer;
5524 c1 = *input_line_pointer++;
5525 c2 = *input_line_pointer++;
5526
5527 if (*input_line_pointer != '>')
5528 {
5529 as_bad (_("syntax error in structured control directive"));
5530 return 0;
5531 }
5532
5533 ++input_line_pointer;
5534 SKIP_WHITESPACE ();
5535
5536 if (isupper (c1))
5537 c1 = tolower (c1);
5538 if (isupper (c2))
5539 c2 = tolower (c2);
5540
5541 *pcc = (c1 << 8) | c2;
5542
5543 return 1;
5544 }
5545
5546 /* Parse a single operand in an MRI structured control expression. */
5547
5548 static int
5549 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5550 int *pcc;
5551 char **leftstart;
5552 char **leftstop;
5553 char **rightstart;
5554 char **rightstop;
5555 {
5556 char *s;
5557
5558 SKIP_WHITESPACE ();
5559
5560 *pcc = -1;
5561 *leftstart = NULL;
5562 *leftstop = NULL;
5563 *rightstart = NULL;
5564 *rightstop = NULL;
5565
5566 if (*input_line_pointer == '<')
5567 {
5568 /* It's just a condition code. */
5569 return parse_mri_condition (pcc);
5570 }
5571
5572 /* Look ahead for the condition code. */
5573 for (s = input_line_pointer; *s != '\0'; ++s)
5574 {
5575 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5576 break;
5577 }
5578 if (*s == '\0')
5579 {
5580 as_bad (_("missing condition code in structured control directive"));
5581 return 0;
5582 }
5583
5584 *leftstart = input_line_pointer;
5585 *leftstop = s;
5586 if (*leftstop > *leftstart
5587 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5588 --*leftstop;
5589
5590 input_line_pointer = s;
5591 if (! parse_mri_condition (pcc))
5592 return 0;
5593
5594 /* Look ahead for AND or OR or end of line. */
5595 for (s = input_line_pointer; *s != '\0'; ++s)
5596 {
5597 if ((strncasecmp (s, "AND", 3) == 0
5598 && (s[3] == '.' || ! is_part_of_name (s[3])))
5599 || (strncasecmp (s, "OR", 2) == 0
5600 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5601 break;
5602 }
5603
5604 *rightstart = input_line_pointer;
5605 *rightstop = s;
5606 if (*rightstop > *rightstart
5607 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5608 --*rightstop;
5609
5610 input_line_pointer = s;
5611
5612 return 1;
5613 }
5614
5615 #define MCC(b1, b2) (((b1) << 8) | (b2))
5616
5617 /* Swap the sense of a condition. This changes the condition so that
5618 it generates the same result when the operands are swapped. */
5619
5620 static int
5621 swap_mri_condition (cc)
5622 int cc;
5623 {
5624 switch (cc)
5625 {
5626 case MCC ('h', 'i'): return MCC ('c', 's');
5627 case MCC ('l', 's'): return MCC ('c', 'c');
5628 case MCC ('c', 'c'): return MCC ('l', 's');
5629 case MCC ('c', 's'): return MCC ('h', 'i');
5630 case MCC ('p', 'l'): return MCC ('m', 'i');
5631 case MCC ('m', 'i'): return MCC ('p', 'l');
5632 case MCC ('g', 'e'): return MCC ('l', 'e');
5633 case MCC ('l', 't'): return MCC ('g', 't');
5634 case MCC ('g', 't'): return MCC ('l', 't');
5635 case MCC ('l', 'e'): return MCC ('g', 'e');
5636 }
5637 return cc;
5638 }
5639
5640 /* Reverse the sense of a condition. */
5641
5642 static int
5643 reverse_mri_condition (cc)
5644 int cc;
5645 {
5646 switch (cc)
5647 {
5648 case MCC ('h', 'i'): return MCC ('l', 's');
5649 case MCC ('l', 's'): return MCC ('h', 'i');
5650 case MCC ('c', 'c'): return MCC ('c', 's');
5651 case MCC ('c', 's'): return MCC ('c', 'c');
5652 case MCC ('n', 'e'): return MCC ('e', 'q');
5653 case MCC ('e', 'q'): return MCC ('n', 'e');
5654 case MCC ('v', 'c'): return MCC ('v', 's');
5655 case MCC ('v', 's'): return MCC ('v', 'c');
5656 case MCC ('p', 'l'): return MCC ('m', 'i');
5657 case MCC ('m', 'i'): return MCC ('p', 'l');
5658 case MCC ('g', 'e'): return MCC ('l', 't');
5659 case MCC ('l', 't'): return MCC ('g', 'e');
5660 case MCC ('g', 't'): return MCC ('l', 'e');
5661 case MCC ('l', 'e'): return MCC ('g', 't');
5662 }
5663 return cc;
5664 }
5665
5666 /* Build an MRI structured control expression. This generates test
5667 and branch instructions. It goes to TRUELAB if the condition is
5668 true, and to FALSELAB if the condition is false. Exactly one of
5669 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5670 is the size qualifier for the expression. EXTENT is the size to
5671 use for the branch. */
5672
5673 static void
5674 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5675 rightstop, truelab, falselab, extent)
5676 int qual;
5677 int cc;
5678 char *leftstart;
5679 char *leftstop;
5680 char *rightstart;
5681 char *rightstop;
5682 const char *truelab;
5683 const char *falselab;
5684 int extent;
5685 {
5686 char *buf;
5687 char *s;
5688
5689 if (leftstart != NULL)
5690 {
5691 struct m68k_op leftop, rightop;
5692 char c;
5693
5694 /* Swap the compare operands, if necessary, to produce a legal
5695 m68k compare instruction. Comparing a register operand with
5696 a non-register operand requires the register to be on the
5697 right (cmp, cmpa). Comparing an immediate value with
5698 anything requires the immediate value to be on the left
5699 (cmpi). */
5700
5701 c = *leftstop;
5702 *leftstop = '\0';
5703 (void) m68k_ip_op (leftstart, &leftop);
5704 *leftstop = c;
5705
5706 c = *rightstop;
5707 *rightstop = '\0';
5708 (void) m68k_ip_op (rightstart, &rightop);
5709 *rightstop = c;
5710
5711 if (rightop.mode == IMMED
5712 || ((leftop.mode == DREG || leftop.mode == AREG)
5713 && (rightop.mode != DREG && rightop.mode != AREG)))
5714 {
5715 char *temp;
5716
5717 cc = swap_mri_condition (cc);
5718 temp = leftstart;
5719 leftstart = rightstart;
5720 rightstart = temp;
5721 temp = leftstop;
5722 leftstop = rightstop;
5723 rightstop = temp;
5724 }
5725 }
5726
5727 if (truelab == NULL)
5728 {
5729 cc = reverse_mri_condition (cc);
5730 truelab = falselab;
5731 }
5732
5733 if (leftstart != NULL)
5734 {
5735 buf = (char *) xmalloc (20
5736 + (leftstop - leftstart)
5737 + (rightstop - rightstart));
5738 s = buf;
5739 *s++ = 'c';
5740 *s++ = 'm';
5741 *s++ = 'p';
5742 if (qual != '\0')
5743 *s++ = qual;
5744 *s++ = ' ';
5745 memcpy (s, leftstart, leftstop - leftstart);
5746 s += leftstop - leftstart;
5747 *s++ = ',';
5748 memcpy (s, rightstart, rightstop - rightstart);
5749 s += rightstop - rightstart;
5750 *s = '\0';
5751 md_assemble (buf);
5752 free (buf);
5753 }
5754
5755 buf = (char *) xmalloc (20 + strlen (truelab));
5756 s = buf;
5757 *s++ = 'b';
5758 *s++ = cc >> 8;
5759 *s++ = cc & 0xff;
5760 if (extent != '\0')
5761 *s++ = extent;
5762 *s++ = ' ';
5763 strcpy (s, truelab);
5764 md_assemble (buf);
5765 free (buf);
5766 }
5767
5768 /* Parse an MRI structured control expression. This generates test
5769 and branch instructions. STOP is where the expression ends. It
5770 goes to TRUELAB if the condition is true, and to FALSELAB if the
5771 condition is false. Exactly one of TRUELAB and FALSELAB will be
5772 NULL, meaning to fall through. QUAL is the size qualifier for the
5773 expression. EXTENT is the size to use for the branch. */
5774
5775 static void
5776 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5777 char *stop;
5778 int qual;
5779 const char *truelab;
5780 const char *falselab;
5781 int extent;
5782 {
5783 int c;
5784 int cc;
5785 char *leftstart;
5786 char *leftstop;
5787 char *rightstart;
5788 char *rightstop;
5789
5790 c = *stop;
5791 *stop = '\0';
5792
5793 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5794 &rightstart, &rightstop))
5795 {
5796 *stop = c;
5797 return;
5798 }
5799
5800 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5801 {
5802 const char *flab;
5803
5804 if (falselab != NULL)
5805 flab = falselab;
5806 else
5807 flab = mri_control_label ();
5808
5809 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5810 rightstop, (const char *) NULL, flab, extent);
5811
5812 input_line_pointer += 3;
5813 if (*input_line_pointer != '.'
5814 || input_line_pointer[1] == '\0')
5815 qual = '\0';
5816 else
5817 {
5818 qual = input_line_pointer[1];
5819 input_line_pointer += 2;
5820 }
5821
5822 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5823 &rightstart, &rightstop))
5824 {
5825 *stop = c;
5826 return;
5827 }
5828
5829 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5830 rightstop, truelab, falselab, extent);
5831
5832 if (falselab == NULL)
5833 colon (flab);
5834 }
5835 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5836 {
5837 const char *tlab;
5838
5839 if (truelab != NULL)
5840 tlab = truelab;
5841 else
5842 tlab = mri_control_label ();
5843
5844 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5845 rightstop, tlab, (const char *) NULL, extent);
5846
5847 input_line_pointer += 2;
5848 if (*input_line_pointer != '.'
5849 || input_line_pointer[1] == '\0')
5850 qual = '\0';
5851 else
5852 {
5853 qual = input_line_pointer[1];
5854 input_line_pointer += 2;
5855 }
5856
5857 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5858 &rightstart, &rightstop))
5859 {
5860 *stop = c;
5861 return;
5862 }
5863
5864 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5865 rightstop, truelab, falselab, extent);
5866
5867 if (truelab == NULL)
5868 colon (tlab);
5869 }
5870 else
5871 {
5872 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5873 rightstop, truelab, falselab, extent);
5874 }
5875
5876 *stop = c;
5877 if (input_line_pointer != stop)
5878 as_bad (_("syntax error in structured control directive"));
5879 }
5880
5881 /* Handle the MRI IF pseudo-op. This may be a structured control
5882 directive, or it may be a regular assembler conditional, depending
5883 on its operands. */
5884
5885 static void
5886 s_mri_if (qual)
5887 int qual;
5888 {
5889 char *s;
5890 int c;
5891 struct mri_control_info *n;
5892
5893 /* A structured control directive must end with THEN with an
5894 optional qualifier. */
5895 s = input_line_pointer;
5896 while (! is_end_of_line[(unsigned char) *s]
5897 && (! flag_mri || *s != '*'))
5898 ++s;
5899 --s;
5900 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5901 --s;
5902
5903 if (s - input_line_pointer > 1
5904 && s[-1] == '.')
5905 s -= 2;
5906
5907 if (s - input_line_pointer < 3
5908 || strncasecmp (s - 3, "THEN", 4) != 0)
5909 {
5910 if (qual != '\0')
5911 {
5912 as_bad (_("missing then"));
5913 ignore_rest_of_line ();
5914 return;
5915 }
5916
5917 /* It's a conditional. */
5918 s_if (O_ne);
5919 return;
5920 }
5921
5922 /* Since this might be a conditional if, this pseudo-op will be
5923 called even if we are supported to be ignoring input. Double
5924 check now. Clobber *input_line_pointer so that ignore_input
5925 thinks that this is not a special pseudo-op. */
5926 c = *input_line_pointer;
5927 *input_line_pointer = 0;
5928 if (ignore_input ())
5929 {
5930 *input_line_pointer = c;
5931 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5932 ++input_line_pointer;
5933 demand_empty_rest_of_line ();
5934 return;
5935 }
5936 *input_line_pointer = c;
5937
5938 n = push_mri_control (mri_if);
5939
5940 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5941 n->next, s[1] == '.' ? s[2] : '\0');
5942
5943 if (s[1] == '.')
5944 input_line_pointer = s + 3;
5945 else
5946 input_line_pointer = s + 1;
5947
5948 if (flag_mri)
5949 {
5950 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5951 ++input_line_pointer;
5952 }
5953
5954 demand_empty_rest_of_line ();
5955 }
5956
5957 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5958 structured IF, associate the ELSE with the IF. Otherwise, assume
5959 it is a conditional else. */
5960
5961 static void
5962 s_mri_else (qual)
5963 int qual;
5964 {
5965 int c;
5966 char *buf;
5967 char q[2];
5968
5969 if (qual == '\0'
5970 && (mri_control_stack == NULL
5971 || mri_control_stack->type != mri_if
5972 || mri_control_stack->else_seen))
5973 {
5974 s_else (0);
5975 return;
5976 }
5977
5978 c = *input_line_pointer;
5979 *input_line_pointer = 0;
5980 if (ignore_input ())
5981 {
5982 *input_line_pointer = c;
5983 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5984 ++input_line_pointer;
5985 demand_empty_rest_of_line ();
5986 return;
5987 }
5988 *input_line_pointer = c;
5989
5990 if (mri_control_stack == NULL
5991 || mri_control_stack->type != mri_if
5992 || mri_control_stack->else_seen)
5993 {
5994 as_bad (_("else without matching if"));
5995 ignore_rest_of_line ();
5996 return;
5997 }
5998
5999 mri_control_stack->else_seen = 1;
6000
6001 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6002 q[0] = qual;
6003 q[1] = '\0';
6004 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6005 md_assemble (buf);
6006 free (buf);
6007
6008 colon (mri_control_stack->next);
6009
6010 if (flag_mri)
6011 {
6012 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6013 ++input_line_pointer;
6014 }
6015
6016 demand_empty_rest_of_line ();
6017 }
6018
6019 /* Handle the MRI ENDI pseudo-op. */
6020
6021 static void
6022 s_mri_endi (ignore)
6023 int ignore;
6024 {
6025 if (mri_control_stack == NULL
6026 || mri_control_stack->type != mri_if)
6027 {
6028 as_bad (_("endi without matching if"));
6029 ignore_rest_of_line ();
6030 return;
6031 }
6032
6033 /* ignore_input will not return true for ENDI, so we don't need to
6034 worry about checking it again here. */
6035
6036 if (! mri_control_stack->else_seen)
6037 colon (mri_control_stack->next);
6038 colon (mri_control_stack->bottom);
6039
6040 pop_mri_control ();
6041
6042 if (flag_mri)
6043 {
6044 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6045 ++input_line_pointer;
6046 }
6047
6048 demand_empty_rest_of_line ();
6049 }
6050
6051 /* Handle the MRI BREAK pseudo-op. */
6052
6053 static void
6054 s_mri_break (extent)
6055 int extent;
6056 {
6057 struct mri_control_info *n;
6058 char *buf;
6059 char ex[2];
6060
6061 n = mri_control_stack;
6062 while (n != NULL
6063 && n->type != mri_for
6064 && n->type != mri_repeat
6065 && n->type != mri_while)
6066 n = n->outer;
6067 if (n == NULL)
6068 {
6069 as_bad (_("break outside of structured loop"));
6070 ignore_rest_of_line ();
6071 return;
6072 }
6073
6074 buf = (char *) xmalloc (20 + strlen (n->bottom));
6075 ex[0] = extent;
6076 ex[1] = '\0';
6077 sprintf (buf, "bra%s %s", ex, n->bottom);
6078 md_assemble (buf);
6079 free (buf);
6080
6081 if (flag_mri)
6082 {
6083 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6084 ++input_line_pointer;
6085 }
6086
6087 demand_empty_rest_of_line ();
6088 }
6089
6090 /* Handle the MRI NEXT pseudo-op. */
6091
6092 static void
6093 s_mri_next (extent)
6094 int extent;
6095 {
6096 struct mri_control_info *n;
6097 char *buf;
6098 char ex[2];
6099
6100 n = mri_control_stack;
6101 while (n != NULL
6102 && n->type != mri_for
6103 && n->type != mri_repeat
6104 && n->type != mri_while)
6105 n = n->outer;
6106 if (n == NULL)
6107 {
6108 as_bad (_("next outside of structured loop"));
6109 ignore_rest_of_line ();
6110 return;
6111 }
6112
6113 buf = (char *) xmalloc (20 + strlen (n->next));
6114 ex[0] = extent;
6115 ex[1] = '\0';
6116 sprintf (buf, "bra%s %s", ex, n->next);
6117 md_assemble (buf);
6118 free (buf);
6119
6120 if (flag_mri)
6121 {
6122 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6123 ++input_line_pointer;
6124 }
6125
6126 demand_empty_rest_of_line ();
6127 }
6128
6129 /* Handle the MRI FOR pseudo-op. */
6130
6131 static void
6132 s_mri_for (qual)
6133 int qual;
6134 {
6135 const char *varstart, *varstop;
6136 const char *initstart, *initstop;
6137 const char *endstart, *endstop;
6138 const char *bystart, *bystop;
6139 int up;
6140 int by;
6141 int extent;
6142 struct mri_control_info *n;
6143 char *buf;
6144 char *s;
6145 char ex[2];
6146
6147 /* The syntax is
6148 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6149 */
6150
6151 SKIP_WHITESPACE ();
6152 varstart = input_line_pointer;
6153
6154 /* Look for the '='. */
6155 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6156 && *input_line_pointer != '=')
6157 ++input_line_pointer;
6158 if (*input_line_pointer != '=')
6159 {
6160 as_bad (_("missing ="));
6161 ignore_rest_of_line ();
6162 return;
6163 }
6164
6165 varstop = input_line_pointer;
6166 if (varstop > varstart
6167 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6168 --varstop;
6169
6170 ++input_line_pointer;
6171
6172 initstart = input_line_pointer;
6173
6174 /* Look for TO or DOWNTO. */
6175 up = 1;
6176 initstop = NULL;
6177 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6178 {
6179 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6180 && ! is_part_of_name (input_line_pointer[2]))
6181 {
6182 initstop = input_line_pointer;
6183 input_line_pointer += 2;
6184 break;
6185 }
6186 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6187 && ! is_part_of_name (input_line_pointer[6]))
6188 {
6189 initstop = input_line_pointer;
6190 up = 0;
6191 input_line_pointer += 6;
6192 break;
6193 }
6194 ++input_line_pointer;
6195 }
6196 if (initstop == NULL)
6197 {
6198 as_bad (_("missing to or downto"));
6199 ignore_rest_of_line ();
6200 return;
6201 }
6202 if (initstop > initstart
6203 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6204 --initstop;
6205
6206 SKIP_WHITESPACE ();
6207 endstart = input_line_pointer;
6208
6209 /* Look for BY or DO. */
6210 by = 0;
6211 endstop = NULL;
6212 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6213 {
6214 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6215 && ! is_part_of_name (input_line_pointer[2]))
6216 {
6217 endstop = input_line_pointer;
6218 by = 1;
6219 input_line_pointer += 2;
6220 break;
6221 }
6222 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6223 && (input_line_pointer[2] == '.'
6224 || ! is_part_of_name (input_line_pointer[2])))
6225 {
6226 endstop = input_line_pointer;
6227 input_line_pointer += 2;
6228 break;
6229 }
6230 ++input_line_pointer;
6231 }
6232 if (endstop == NULL)
6233 {
6234 as_bad (_("missing do"));
6235 ignore_rest_of_line ();
6236 return;
6237 }
6238 if (endstop > endstart
6239 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6240 --endstop;
6241
6242 if (! by)
6243 {
6244 bystart = "#1";
6245 bystop = bystart + 2;
6246 }
6247 else
6248 {
6249 SKIP_WHITESPACE ();
6250 bystart = input_line_pointer;
6251
6252 /* Look for DO. */
6253 bystop = NULL;
6254 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6255 {
6256 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6257 && (input_line_pointer[2] == '.'
6258 || ! is_part_of_name (input_line_pointer[2])))
6259 {
6260 bystop = input_line_pointer;
6261 input_line_pointer += 2;
6262 break;
6263 }
6264 ++input_line_pointer;
6265 }
6266 if (bystop == NULL)
6267 {
6268 as_bad (_("missing do"));
6269 ignore_rest_of_line ();
6270 return;
6271 }
6272 if (bystop > bystart
6273 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6274 --bystop;
6275 }
6276
6277 if (*input_line_pointer != '.')
6278 extent = '\0';
6279 else
6280 {
6281 extent = input_line_pointer[1];
6282 input_line_pointer += 2;
6283 }
6284
6285 /* We have fully parsed the FOR operands. Now build the loop. */
6286
6287 n = push_mri_control (mri_for);
6288
6289 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6290
6291 /* move init,var */
6292 s = buf;
6293 *s++ = 'm';
6294 *s++ = 'o';
6295 *s++ = 'v';
6296 *s++ = 'e';
6297 if (qual != '\0')
6298 *s++ = qual;
6299 *s++ = ' ';
6300 memcpy (s, initstart, initstop - initstart);
6301 s += initstop - initstart;
6302 *s++ = ',';
6303 memcpy (s, varstart, varstop - varstart);
6304 s += varstop - varstart;
6305 *s = '\0';
6306 md_assemble (buf);
6307
6308 colon (n->top);
6309
6310 /* cmp end,var */
6311 s = buf;
6312 *s++ = 'c';
6313 *s++ = 'm';
6314 *s++ = 'p';
6315 if (qual != '\0')
6316 *s++ = qual;
6317 *s++ = ' ';
6318 memcpy (s, endstart, endstop - endstart);
6319 s += endstop - endstart;
6320 *s++ = ',';
6321 memcpy (s, varstart, varstop - varstart);
6322 s += varstop - varstart;
6323 *s = '\0';
6324 md_assemble (buf);
6325
6326 /* bcc bottom */
6327 ex[0] = extent;
6328 ex[1] = '\0';
6329 if (up)
6330 sprintf (buf, "blt%s %s", ex, n->bottom);
6331 else
6332 sprintf (buf, "bgt%s %s", ex, n->bottom);
6333 md_assemble (buf);
6334
6335 /* Put together the add or sub instruction used by ENDF. */
6336 s = buf;
6337 if (up)
6338 strcpy (s, "add");
6339 else
6340 strcpy (s, "sub");
6341 s += 3;
6342 if (qual != '\0')
6343 *s++ = qual;
6344 *s++ = ' ';
6345 memcpy (s, bystart, bystop - bystart);
6346 s += bystop - bystart;
6347 *s++ = ',';
6348 memcpy (s, varstart, varstop - varstart);
6349 s += varstop - varstart;
6350 *s = '\0';
6351 n->incr = buf;
6352
6353 if (flag_mri)
6354 {
6355 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6356 ++input_line_pointer;
6357 }
6358
6359 demand_empty_rest_of_line ();
6360 }
6361
6362 /* Handle the MRI ENDF pseudo-op. */
6363
6364 static void
6365 s_mri_endf (ignore)
6366 int ignore;
6367 {
6368 if (mri_control_stack == NULL
6369 || mri_control_stack->type != mri_for)
6370 {
6371 as_bad (_("endf without for"));
6372 ignore_rest_of_line ();
6373 return;
6374 }
6375
6376 colon (mri_control_stack->next);
6377
6378 md_assemble (mri_control_stack->incr);
6379
6380 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6381 md_assemble (mri_control_stack->incr);
6382
6383 free (mri_control_stack->incr);
6384
6385 colon (mri_control_stack->bottom);
6386
6387 pop_mri_control ();
6388
6389 if (flag_mri)
6390 {
6391 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6392 ++input_line_pointer;
6393 }
6394
6395 demand_empty_rest_of_line ();
6396 }
6397
6398 /* Handle the MRI REPEAT pseudo-op. */
6399
6400 static void
6401 s_mri_repeat (ignore)
6402 int ignore;
6403 {
6404 struct mri_control_info *n;
6405
6406 n = push_mri_control (mri_repeat);
6407 colon (n->top);
6408 if (flag_mri)
6409 {
6410 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6411 ++input_line_pointer;
6412 }
6413 demand_empty_rest_of_line ();
6414 }
6415
6416 /* Handle the MRI UNTIL pseudo-op. */
6417
6418 static void
6419 s_mri_until (qual)
6420 int qual;
6421 {
6422 char *s;
6423
6424 if (mri_control_stack == NULL
6425 || mri_control_stack->type != mri_repeat)
6426 {
6427 as_bad (_("until without repeat"));
6428 ignore_rest_of_line ();
6429 return;
6430 }
6431
6432 colon (mri_control_stack->next);
6433
6434 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6435 ;
6436
6437 parse_mri_control_expression (s, qual, (const char *) NULL,
6438 mri_control_stack->top, '\0');
6439
6440 colon (mri_control_stack->bottom);
6441
6442 input_line_pointer = s;
6443
6444 pop_mri_control ();
6445
6446 if (flag_mri)
6447 {
6448 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6449 ++input_line_pointer;
6450 }
6451
6452 demand_empty_rest_of_line ();
6453 }
6454
6455 /* Handle the MRI WHILE pseudo-op. */
6456
6457 static void
6458 s_mri_while (qual)
6459 int qual;
6460 {
6461 char *s;
6462
6463 struct mri_control_info *n;
6464
6465 s = input_line_pointer;
6466 while (! is_end_of_line[(unsigned char) *s]
6467 && (! flag_mri || *s != '*'))
6468 s++;
6469 --s;
6470 while (*s == ' ' || *s == '\t')
6471 --s;
6472 if (s - input_line_pointer > 1
6473 && s[-1] == '.')
6474 s -= 2;
6475 if (s - input_line_pointer < 2
6476 || strncasecmp (s - 1, "DO", 2) != 0)
6477 {
6478 as_bad (_("missing do"));
6479 ignore_rest_of_line ();
6480 return;
6481 }
6482
6483 n = push_mri_control (mri_while);
6484
6485 colon (n->next);
6486
6487 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6488 s[1] == '.' ? s[2] : '\0');
6489
6490 input_line_pointer = s + 1;
6491 if (*input_line_pointer == '.')
6492 input_line_pointer += 2;
6493
6494 if (flag_mri)
6495 {
6496 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6497 ++input_line_pointer;
6498 }
6499
6500 demand_empty_rest_of_line ();
6501 }
6502
6503 /* Handle the MRI ENDW pseudo-op. */
6504
6505 static void
6506 s_mri_endw (ignore)
6507 int ignore;
6508 {
6509 char *buf;
6510
6511 if (mri_control_stack == NULL
6512 || mri_control_stack->type != mri_while)
6513 {
6514 as_bad (_("endw without while"));
6515 ignore_rest_of_line ();
6516 return;
6517 }
6518
6519 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6520 sprintf (buf, "bra %s", mri_control_stack->next);
6521 md_assemble (buf);
6522 free (buf);
6523
6524 colon (mri_control_stack->bottom);
6525
6526 pop_mri_control ();
6527
6528 if (flag_mri)
6529 {
6530 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6531 ++input_line_pointer;
6532 }
6533
6534 demand_empty_rest_of_line ();
6535 }
6536 \f
6537 /*
6538 * md_parse_option
6539 * Invocation line includes a switch not recognized by the base assembler.
6540 * See if it's a processor-specific option. These are:
6541 *
6542 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6543 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6544 * Select the architecture. Instructions or features not
6545 * supported by the selected architecture cause fatal
6546 * errors. More than one may be specified. The default is
6547 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6548 * for -m68000, and -m68882 is a synonym for -m68881.
6549 * -[A]m[c]no-68851, -[A]m[c]no-68881
6550 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6551 * so don't use or document it, but that's the way the parsing
6552 * works).
6553 *
6554 * -pic Indicates PIC.
6555 * -k Indicates PIC. (Sun 3 only.)
6556 *
6557 * --bitwise-or
6558 * Permit `|' to be used in expressions.
6559 *
6560 */
6561
6562 #ifdef OBJ_ELF
6563 CONST char *md_shortopts = "lSA:m:kQ:V";
6564 #else
6565 CONST char *md_shortopts = "lSA:m:k";
6566 #endif
6567
6568 struct option md_longopts[] = {
6569 #define OPTION_PIC (OPTION_MD_BASE)
6570 {"pic", no_argument, NULL, OPTION_PIC},
6571 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6572 {"register-prefix-optional", no_argument, NULL,
6573 OPTION_REGISTER_PREFIX_OPTIONAL},
6574 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6575 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6576 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6577 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6578 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6579 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6580 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6581 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6582 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6583 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6584 {NULL, no_argument, NULL, 0}
6585 };
6586 size_t md_longopts_size = sizeof(md_longopts);
6587
6588 int
6589 md_parse_option (c, arg)
6590 int c;
6591 char *arg;
6592 {
6593 switch (c)
6594 {
6595 case 'l': /* -l means keep external to 2 bit offset
6596 rather than 16 bit one */
6597 flag_short_refs = 1;
6598 break;
6599
6600 case 'S': /* -S means that jbsr's always turn into
6601 jsr's. */
6602 flag_long_jumps = 1;
6603 break;
6604
6605 case 'A':
6606 if (*arg == 'm')
6607 arg++;
6608 /* intentional fall-through */
6609 case 'm':
6610
6611 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6612 {
6613 int i;
6614 unsigned long arch;
6615 const char *oarg = arg;
6616
6617 arg += 3;
6618 if (*arg == 'm')
6619 {
6620 arg++;
6621 if (arg[0] == 'c' && arg[1] == '6')
6622 arg++;
6623 }
6624 for (i = 0; i < n_archs; i++)
6625 if (!strcmp (arg, archs[i].name))
6626 break;
6627 if (i == n_archs)
6628 {
6629 unknown:
6630 as_bad (_("unrecognized option `%s'"), oarg);
6631 return 0;
6632 }
6633 arch = archs[i].arch;
6634 if (arch == m68881)
6635 no_68881 = 1;
6636 else if (arch == m68851)
6637 no_68851 = 1;
6638 else
6639 goto unknown;
6640 }
6641 else
6642 {
6643 int i;
6644
6645 if (arg[0] == 'c' && arg[1] == '6')
6646 arg++;
6647
6648 for (i = 0; i < n_archs; i++)
6649 if (!strcmp (arg, archs[i].name))
6650 {
6651 unsigned long arch = archs[i].arch;
6652 if (cpu_of_arch (arch))
6653 /* It's a cpu spec. */
6654 {
6655 current_architecture &= ~m68000up;
6656 current_architecture |= arch;
6657 }
6658 else if (arch == m68881)
6659 {
6660 current_architecture |= m68881;
6661 no_68881 = 0;
6662 }
6663 else if (arch == m68851)
6664 {
6665 current_architecture |= m68851;
6666 no_68851 = 0;
6667 }
6668 else
6669 /* ??? */
6670 abort ();
6671 break;
6672 }
6673 if (i == n_archs)
6674 {
6675 as_bad (_("unrecognized architecture specification `%s'"), arg);
6676 return 0;
6677 }
6678 }
6679 break;
6680
6681 case OPTION_PIC:
6682 case 'k':
6683 flag_want_pic = 1;
6684 break; /* -pic, Position Independent Code */
6685
6686 case OPTION_REGISTER_PREFIX_OPTIONAL:
6687 flag_reg_prefix_optional = 1;
6688 reg_prefix_optional_seen = 1;
6689 break;
6690
6691 /* -V: SVR4 argument to print version ID. */
6692 case 'V':
6693 print_version_id ();
6694 break;
6695
6696 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6697 should be emitted or not. FIXME: Not implemented. */
6698 case 'Q':
6699 break;
6700
6701 case OPTION_BITWISE_OR:
6702 {
6703 char *n, *t;
6704 const char *s;
6705
6706 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6707 t = n;
6708 for (s = m68k_comment_chars; *s != '\0'; s++)
6709 if (*s != '|')
6710 *t++ = *s;
6711 *t = '\0';
6712 m68k_comment_chars = n;
6713 }
6714 break;
6715
6716 case OPTION_BASE_SIZE_DEFAULT_16:
6717 m68k_index_width_default = SIZE_WORD;
6718 break;
6719
6720 case OPTION_BASE_SIZE_DEFAULT_32:
6721 m68k_index_width_default = SIZE_LONG;
6722 break;
6723
6724 case OPTION_DISP_SIZE_DEFAULT_16:
6725 m68k_rel32 = 0;
6726 m68k_rel32_from_cmdline = 1;
6727 break;
6728
6729 case OPTION_DISP_SIZE_DEFAULT_32:
6730 m68k_rel32 = 1;
6731 m68k_rel32_from_cmdline = 1;
6732 break;
6733
6734 default:
6735 return 0;
6736 }
6737
6738 return 1;
6739 }
6740
6741 void
6742 md_show_usage (stream)
6743 FILE *stream;
6744 {
6745 fprintf(stream, _("\
6746 680X0 options:\n\
6747 -l use 1 word for refs to undefined symbols [default 2]\n\
6748 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6749 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6750 | -mcpu32 | -m5200\n\
6751 specify variant of 680X0 architecture [default 68020]\n\
6752 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6753 target has/lacks floating-point coprocessor\n\
6754 [default yes for 68020, 68030, and cpu32]\n"));
6755 fprintf(stream, _("\
6756 -m68851 | -mno-68851\n\
6757 target has/lacks memory-management unit coprocessor\n\
6758 [default yes for 68020 and up]\n\
6759 -pic, -k generate position independent code\n\
6760 -S turn jbsr into jsr\n\
6761 --register-prefix-optional\n\
6762 recognize register names without prefix character\n\
6763 --bitwise-or do not treat `|' as a comment character\n"));
6764 fprintf (stream, _("\
6765 --base-size-default-16 base reg without size is 16 bits\n\
6766 --base-size-default-32 base reg without size is 32 bits (default)\n\
6767 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6768 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6769 }
6770 \f
6771 #ifdef TEST2
6772
6773 /* TEST2: Test md_assemble() */
6774 /* Warning, this routine probably doesn't work anymore */
6775
6776 main ()
6777 {
6778 struct m68k_it the_ins;
6779 char buf[120];
6780 char *cp;
6781 int n;
6782
6783 m68k_ip_begin ();
6784 for (;;)
6785 {
6786 if (!gets (buf) || !*buf)
6787 break;
6788 if (buf[0] == '|' || buf[1] == '.')
6789 continue;
6790 for (cp = buf; *cp; cp++)
6791 if (*cp == '\t')
6792 *cp = ' ';
6793 if (is_label (buf))
6794 continue;
6795 memset (&the_ins, '\0', sizeof (the_ins));
6796 m68k_ip (&the_ins, buf);
6797 if (the_ins.error)
6798 {
6799 printf (_("Error %s in %s\n"), the_ins.error, buf);
6800 }
6801 else
6802 {
6803 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
6804 for (n = 0; n < the_ins.numo; n++)
6805 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6806 printf (" ");
6807 print_the_insn (&the_ins.opcode[0], stdout);
6808 (void) putchar ('\n');
6809 }
6810 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6811 {
6812 if (the_ins.operands[n].error)
6813 {
6814 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6815 continue;
6816 }
6817 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6818 if (the_ins.operands[n].b_const)
6819 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6820 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6821 if (the_ins.operands[n].b_iadd)
6822 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6823 (void) putchar ('\n');
6824 }
6825 }
6826 m68k_ip_end ();
6827 return 0;
6828 }
6829
6830 is_label (str)
6831 char *str;
6832 {
6833 while (*str == ' ')
6834 str++;
6835 while (*str && *str != ' ')
6836 str++;
6837 if (str[-1] == ':' || str[1] == '=')
6838 return 1;
6839 return 0;
6840 }
6841
6842 #endif
6843
6844 /* Possible states for relaxation:
6845
6846 0 0 branch offset byte (bra, etc)
6847 0 1 word
6848 0 2 long
6849
6850 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6851 1 1 word
6852 1 2 long
6853
6854 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6855 2 1 word-long
6856 2 2 long-word
6857 2 3 long-long
6858
6859 */
6860
6861 /* We have no need to default values of symbols. */
6862
6863 /* ARGSUSED */
6864 symbolS *
6865 md_undefined_symbol (name)
6866 char *name;
6867 {
6868 return 0;
6869 }
6870
6871 /* Round up a section size to the appropriate boundary. */
6872 valueT
6873 md_section_align (segment, size)
6874 segT segment;
6875 valueT size;
6876 {
6877 #ifdef OBJ_AOUT
6878 #ifdef BFD_ASSEMBLER
6879 /* For a.out, force the section size to be aligned. If we don't do
6880 this, BFD will align it for us, but it will not write out the
6881 final bytes of the section. This may be a bug in BFD, but it is
6882 easier to fix it here since that is how the other a.out targets
6883 work. */
6884 int align;
6885
6886 align = bfd_get_section_alignment (stdoutput, segment);
6887 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6888 #endif
6889 #endif
6890
6891 return size;
6892 }
6893
6894 /* Exactly what point is a PC-relative offset relative TO?
6895 On the 68k, it is relative to the address of the first extension
6896 word. The difference between the addresses of the offset and the
6897 first extension word is stored in fx_pcrel_adjust. */
6898 long
6899 md_pcrel_from (fixP)
6900 fixS *fixP;
6901 {
6902 int adjust;
6903
6904 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6905 -1 as 64. */
6906 adjust = fixP->fx_pcrel_adjust;
6907 if (adjust == 64)
6908 adjust = -1;
6909 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6910 }
6911
6912 #ifndef BFD_ASSEMBLER
6913 #ifdef OBJ_COFF
6914
6915 /*ARGSUSED*/
6916 void
6917 tc_coff_symbol_emit_hook (ignore)
6918 symbolS *ignore;
6919 {
6920 }
6921
6922 int
6923 tc_coff_sizemachdep (frag)
6924 fragS *frag;
6925 {
6926 switch (frag->fr_subtype & 0x3)
6927 {
6928 case BYTE:
6929 return 1;
6930 case SHORT:
6931 return 2;
6932 case LONG:
6933 return 4;
6934 default:
6935 abort ();
6936 return 0;
6937 }
6938 }
6939
6940 #endif
6941 #endif
6942
6943 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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