1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 1998
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if defined (TE_SVR4) || defined (TE_DELTA)
35 const char *m68k_comment_chars
= "|#";
37 const char *m68k_comment_chars
= "|";
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars
[] = "#*";
49 const char line_separator_chars
[] = "";
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST
char EXP_CHARS
[] = "eE";
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
57 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
63 const int md_reloc_size
= 8; /* Size of relocation record */
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
71 static int flag_short_refs
; /* -l option */
72 static int flag_long_jumps
; /* -S option */
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
77 int flag_reg_prefix_optional
;
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen
;
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum
= COP1
;
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd
;
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick
= 1;
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
97 static int m68k_rel32
= 1;
99 /* This is non-zero if m68k_rel32 was set from the command line. */
100 static int m68k_rel32_from_cmdline
;
102 /* The default width to use for an index register when using a base
104 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
106 /* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
112 struct label_line
*next
;
119 /* The list of labels. */
121 static struct label_line
*labels
;
123 /* The current label. */
125 static struct label_line
*current_label
;
127 /* Its an arbitrary name: This means I don't approve of it */
128 /* See flames below */
129 static struct obstack robyn
;
131 #define TAB(x,y) (((x)<<2)+(y))
132 #define TABTYPE(xy) ((xy) >> 2)
138 /* Case `g' except when BCC68000 is applicable. */
140 /* Coprocessor branches. */
142 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
145 /* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
151 /* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
154 /* Not currently used? */
156 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
162 const char *m_operands
;
163 unsigned long m_opcode
;
167 struct m68k_incant
*m_next
;
170 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171 #define gettwo(x) (((x)->m_opcode)&0xffff)
173 static const enum m68k_register m68000_control_regs
[] = { 0 };
174 static const enum m68k_register m68010_control_regs
[] = {
178 static const enum m68k_register m68020_control_regs
[] = {
179 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
182 static const enum m68k_register m68040_control_regs
[] = {
183 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
184 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
187 static const enum m68k_register m68060_control_regs
[] = {
188 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
189 USP
, VBR
, URP
, SRP
, PCR
,
192 static const enum m68k_register mcf5200_control_regs
[] = {
193 CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, VBR
, ROMBAR
,
194 RAMBAR0
, RAMBAR1
, MBAR
,
197 #define cpu32_control_regs m68010_control_regs
199 static const enum m68k_register
*control_regs
;
201 /* internal form of a 68020 instruction */
205 const char *args
; /* list of opcode info */
208 int numo
; /* Number of shorts in opcode */
211 struct m68k_op operands
[6];
213 int nexp
; /* number of exprs in use */
214 struct m68k_exp exprs
[4];
216 int nfrag
; /* Number of frags we have to produce */
219 int fragoff
; /* Where in the current opcode the frag ends */
226 int nrel
; /* Num of reloc strucs in use */
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
242 /* Whether this expression needs special pic relocation, and if
244 enum pic_relocation pic_reloc
;
247 reloc
[5]; /* Five is enough??? */
250 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
251 #define float_of_arch(x) ((x) & mfloat)
252 #define mmu_of_arch(x) ((x) & mmmu)
254 /* Macros for determining if cpu supports a specific addressing mode */
255 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
257 static struct m68k_it the_ins
; /* the instruction being assembled */
259 #define op(ex) ((ex)->exp.X_op)
260 #define adds(ex) ((ex)->exp.X_add_symbol)
261 #define subs(ex) ((ex)->exp.X_op_symbol)
262 #define offs(ex) ((ex)->exp.X_add_number)
264 /* Macros for adding things to the m68k_it struct */
266 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
268 /* Static functions. */
270 static void insop
PARAMS ((int, const struct m68k_incant
*));
271 static void add_fix
PARAMS ((int, struct m68k_exp
*, int, int));
272 static void add_frag
PARAMS ((symbolS
*, offsetT
, int));
274 /* Like addword, but goes BEFORE general operands */
278 const struct m68k_incant
*opcode
;
281 for(z
=the_ins
.numo
;z
>opcode
->m_codenum
;--z
)
282 the_ins
.opcode
[z
]=the_ins
.opcode
[z
-1];
283 for(z
=0;z
<the_ins
.nrel
;z
++)
284 the_ins
.reloc
[z
].n
+=2;
285 for (z
= 0; z
< the_ins
.nfrag
; z
++)
286 the_ins
.fragb
[z
].fragoff
++;
287 the_ins
.opcode
[opcode
->m_codenum
]=w
;
291 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
294 add_fix (width
, exp
, pc_rel
, pc_fix
)
296 struct m68k_exp
*exp
;
300 the_ins
.reloc
[the_ins
.nrel
].n
= ((width
== 'B' || width
== '3')
304 : (the_ins
.numo
*2)));
305 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
306 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
307 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
309 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
311 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
314 /* Cause an extra frag to be generated here, inserting up to 10 bytes
315 (that value is chosen in the frag_var call in md_assemble). TYPE
316 is the subtype of the frag to be generated; its primary type is
317 rs_machine_dependent.
319 The TYPE parameter is also used by md_convert_frag_1 and
320 md_estimate_size_before_relax. The appropriate type of fixup will
321 be emitted by md_convert_frag_1.
323 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
325 add_frag (add
, off
, type
)
330 the_ins
.fragb
[the_ins
.nfrag
].fragoff
=the_ins
.numo
;
331 the_ins
.fragb
[the_ins
.nfrag
].fadd
=add
;
332 the_ins
.fragb
[the_ins
.nfrag
].foff
=off
;
333 the_ins
.fragb
[the_ins
.nfrag
++].fragty
=type
;
337 (op (ex) != O_constant && op (ex) != O_big)
339 static char *crack_operand
PARAMS ((char *str
, struct m68k_op
*opP
));
340 static int get_num
PARAMS ((struct m68k_exp
*exp
, int ok
));
341 static void m68k_ip
PARAMS ((char *));
342 static void insert_reg
PARAMS ((const char *, int));
343 static void select_control_regs
PARAMS ((void));
344 static void init_regtable
PARAMS ((void));
345 static int reverse_16_bits
PARAMS ((int in
));
346 static int reverse_8_bits
PARAMS ((int in
));
347 static void install_gen_operand
PARAMS ((int mode
, int val
));
348 static void install_operand
PARAMS ((int mode
, int val
));
349 static void s_bss
PARAMS ((int));
350 static void s_data1
PARAMS ((int));
351 static void s_data2
PARAMS ((int));
352 static void s_even
PARAMS ((int));
353 static void s_proc
PARAMS ((int));
354 static void mri_chip
PARAMS ((void));
355 static void s_chip
PARAMS ((int));
356 static void s_fopt
PARAMS ((int));
357 static void s_opt
PARAMS ((int));
358 static void s_reg
PARAMS ((int));
359 static void s_restore
PARAMS ((int));
360 static void s_save
PARAMS ((int));
361 static void s_mri_if
PARAMS ((int));
362 static void s_mri_else
PARAMS ((int));
363 static void s_mri_endi
PARAMS ((int));
364 static void s_mri_break
PARAMS ((int));
365 static void s_mri_next
PARAMS ((int));
366 static void s_mri_for
PARAMS ((int));
367 static void s_mri_endf
PARAMS ((int));
368 static void s_mri_repeat
PARAMS ((int));
369 static void s_mri_until
PARAMS ((int));
370 static void s_mri_while
PARAMS ((int));
371 static void s_mri_endw
PARAMS ((int));
372 static void md_apply_fix_2
PARAMS ((fixS
*, offsetT
));
373 static void md_convert_frag_1
PARAMS ((fragS
*));
375 static int current_architecture
;
383 static const struct m68k_cpu archs
[] = {
384 { m68000
, "68000", 0 },
385 { m68010
, "68010", 0 },
386 { m68020
, "68020", 0 },
387 { m68030
, "68030", 0 },
388 { m68040
, "68040", 0 },
389 { m68060
, "68060", 0 },
390 { cpu32
, "cpu32", 0 },
391 { m68881
, "68881", 0 },
392 { m68851
, "68851", 0 },
393 { mcf5200
, "5200", 0 },
394 /* Aliases (effectively, so far as gas is concerned) for the above
396 { m68020
, "68k", 1 },
397 { m68000
, "68008", 1 },
398 { m68000
, "68302", 1 },
399 { m68000
, "68306", 1 },
400 { m68000
, "68307", 1 },
401 { m68000
, "68322", 1 },
402 { m68000
, "68356", 1 },
403 { m68000
, "68ec000", 1 },
404 { m68000
, "68hc000", 1 },
405 { m68000
, "68hc001", 1 },
406 { m68020
, "68ec020", 1 },
407 { m68030
, "68ec030", 1 },
408 { m68040
, "68ec040", 1 },
409 { m68060
, "68ec060", 1 },
410 { cpu32
, "68330", 1 },
411 { cpu32
, "68331", 1 },
412 { cpu32
, "68332", 1 },
413 { cpu32
, "68333", 1 },
414 { cpu32
, "68334", 1 },
415 { cpu32
, "68336", 1 },
416 { cpu32
, "68340", 1 },
417 { cpu32
, "68341", 1 },
418 { cpu32
, "68349", 1 },
419 { cpu32
, "68360", 1 },
420 { m68881
, "68882", 1 },
423 static const int n_archs
= sizeof (archs
) / sizeof (archs
[0]);
425 /* BCC68000 is for patching in an extra jmp instruction for long offsets
426 on the 68000. The 68000 doesn't support long branches with branchs */
428 /* This table desribes how you change sizes for the various types of variable
429 size expressions. This version only supports two kinds. */
431 /* Note that calls to frag_var need to specify the maximum expansion
432 needed; this is currently 10 bytes for DBCC. */
435 How far Forward this mode will reach:
436 How far Backward this mode will reach:
437 How many bytes this mode will add to the size of the frag
438 Which mode to go to if the offset won't fit in this one
440 relax_typeS md_relax_table
[] =
442 {1, 1, 0, 0}, /* First entries aren't used */
443 {1, 1, 0, 0}, /* For no good reason except */
444 {1, 1, 0, 0}, /* that the VAX doesn't either */
447 {(127), (-128), 0, TAB (ABRANCH
, SHORT
)},
448 {(32767), (-32768), 2, TAB (ABRANCH
, LONG
)},
452 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
453 {(32767), (-32768), 2, TAB (FBRANCH
, LONG
)},
457 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
458 {(32767), (-32768), 2, TAB (PCREL
, LONG
)},
462 {(127), (-128), 0, TAB (BCC68000
, SHORT
)},
463 {(32767), (-32768), 2, TAB (BCC68000
, LONG
)},
464 {0, 0, 6, 0}, /* jmp long space */
467 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
468 {(32767), (-32768), 2, TAB (DBCC
, LONG
)},
469 {0, 0, 10, 0}, /* bra/jmp long space */
472 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
473 {32767, -32768, 2, TAB (PCLEA
, LONG
)},
477 /* For, e.g., jmp pcrel indexed. */
478 {125, -130, 0, TAB (PCINDEX
, SHORT
)},
479 {32765, -32770, 2, TAB (PCINDEX
, LONG
)},
484 /* These are the machine dependent pseudo-ops. These are included so
485 the assembler can work on the output from the SUN C compiler, which
489 /* This table describes all the machine specific pseudo-ops the assembler
490 has to support. The fields are:
491 pseudo-op name without dot
492 function to call to execute this pseudo-op
493 Integer arg to pass to the function
495 const pseudo_typeS md_pseudo_table
[] =
497 {"data1", s_data1
, 0},
498 {"data2", s_data2
, 0},
501 {"skip", s_space
, 0},
503 #if defined (TE_SUN3) || defined (OBJ_ELF)
504 {"align", s_align_bytes
, 0},
507 {"swbeg", s_ignore
, 0},
509 {"extend", float_cons
, 'x'},
510 {"ldouble", float_cons
, 'x'},
512 /* The following pseudo-ops are supported for MRI compatibility. */
514 {"comline", s_space
, 1},
516 {"mask2", s_ignore
, 0},
519 {"restore", s_restore
, 0},
523 {"if.b", s_mri_if
, 'b'},
524 {"if.w", s_mri_if
, 'w'},
525 {"if.l", s_mri_if
, 'l'},
526 {"else", s_mri_else
, 0},
527 {"else.s", s_mri_else
, 's'},
528 {"else.l", s_mri_else
, 'l'},
529 {"endi", s_mri_endi
, 0},
530 {"break", s_mri_break
, 0},
531 {"break.s", s_mri_break
, 's'},
532 {"break.l", s_mri_break
, 'l'},
533 {"next", s_mri_next
, 0},
534 {"next.s", s_mri_next
, 's'},
535 {"next.l", s_mri_next
, 'l'},
536 {"for", s_mri_for
, 0},
537 {"for.b", s_mri_for
, 'b'},
538 {"for.w", s_mri_for
, 'w'},
539 {"for.l", s_mri_for
, 'l'},
540 {"endf", s_mri_endf
, 0},
541 {"repeat", s_mri_repeat
, 0},
542 {"until", s_mri_until
, 0},
543 {"until.b", s_mri_until
, 'b'},
544 {"until.w", s_mri_until
, 'w'},
545 {"until.l", s_mri_until
, 'l'},
546 {"while", s_mri_while
, 0},
547 {"while.b", s_mri_while
, 'b'},
548 {"while.w", s_mri_while
, 'w'},
549 {"while.l", s_mri_while
, 'l'},
550 {"endw", s_mri_endw
, 0},
556 /* The mote pseudo ops are put into the opcode table, since they
557 don't start with a . they look like opcodes to gas.
561 extern void obj_coff_section
PARAMS ((int));
564 CONST pseudo_typeS mote_pseudo_table
[] =
577 {"xdef", s_globl
, 0},
579 {"align", s_align_bytes
, 0},
581 {"align", s_align_ptwo
, 0},
584 {"sect", obj_coff_section
, 0},
585 {"section", obj_coff_section
, 0},
590 #define issbyte(x) ((x)>=-128 && (x)<=127)
591 #define isubyte(x) ((x)>=0 && (x)<=255)
592 #define issword(x) ((x)>=-32768 && (x)<=32767)
593 #define isuword(x) ((x)>=0 && (x)<=65535)
595 #define isbyte(x) ((x)>= -255 && (x)<=255)
596 #define isword(x) ((x)>=-65536 && (x)<=65535)
597 #define islong(x) (1)
599 extern char *input_line_pointer
;
601 static char mklower_table
[256];
602 #define mklower(c) (mklower_table[(unsigned char)(c)])
603 static char notend_table
[256];
604 static char alt_notend_table
[256];
606 (! (notend_table[(unsigned char) *s] \
608 && alt_notend_table[(unsigned char) s[1]])))
610 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
612 #ifdef NO_PCREL_RELOCS
615 make_pcrel_absolute(fixP
, add_number
)
619 register unsigned char *opcode
= fixP
->fx_frag
->fr_opcode
;
621 /* rewrite the PC relative instructions to absolute address ones.
622 * these are rumoured to be faster, and the apollo linker refuses
623 * to deal with the PC relative relocations.
625 if (opcode
[0] == 0x60 && opcode
[1] == 0xff) /* BRA -> JMP */
630 else if (opcode
[0] == 0x61 && opcode
[1] == 0xff) /* BSR -> JSR */
636 as_fatal (_("Unknown PC relative instruction"));
641 #endif /* NO_PCREL_RELOCS */
644 tc_coff_fix2rtype (fixP
)
647 if (fixP
->fx_tcbit
&& fixP
->fx_size
== 4)
648 return R_RELLONG_NEG
;
649 #ifdef NO_PCREL_RELOCS
650 know (fixP
->fx_pcrel
== 0);
651 return (fixP
->fx_size
== 1 ? R_RELBYTE
652 : fixP
->fx_size
== 2 ? R_DIR16
655 return (fixP
->fx_pcrel
?
656 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
657 fixP
->fx_size
== 2 ? R_PCRWORD
:
659 (fixP
->fx_size
== 1 ? R_RELBYTE
:
660 fixP
->fx_size
== 2 ? R_RELWORD
:
669 /* Compute the relocation code for a fixup of SIZE bytes, using pc
670 relative relocation if PCREL is non-zero. PIC says whether a special
671 pic relocation was requested. */
673 static bfd_reloc_code_real_type get_reloc_code
674 PARAMS ((int, int, enum pic_relocation
));
676 static bfd_reloc_code_real_type
677 get_reloc_code (size
, pcrel
, pic
)
680 enum pic_relocation pic
;
688 return BFD_RELOC_8_GOT_PCREL
;
690 return BFD_RELOC_16_GOT_PCREL
;
692 return BFD_RELOC_32_GOT_PCREL
;
700 return BFD_RELOC_8_GOTOFF
;
702 return BFD_RELOC_16_GOTOFF
;
704 return BFD_RELOC_32_GOTOFF
;
712 return BFD_RELOC_8_PLT_PCREL
;
714 return BFD_RELOC_16_PLT_PCREL
;
716 return BFD_RELOC_32_PLT_PCREL
;
724 return BFD_RELOC_8_PLTOFF
;
726 return BFD_RELOC_16_PLTOFF
;
728 return BFD_RELOC_32_PLTOFF
;
738 return BFD_RELOC_8_PCREL
;
740 return BFD_RELOC_16_PCREL
;
742 return BFD_RELOC_32_PCREL
;
762 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
764 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
769 as_bad (_("Can not do %d byte relocation"), size
);
771 as_bad (_("Can not do %d byte pic relocation"), size
);
774 return BFD_RELOC_NONE
;
777 /* Here we decide which fixups can be adjusted to make them relative
778 to the beginning of the section instead of the symbol. Basically
779 we need to make sure that the dynamic relocations are done
780 correctly, so in some cases we force the original symbol to be
783 tc_m68k_fix_adjustable (fixP
)
786 /* Prevent all adjustments to global symbols. */
787 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
790 /* adjust_reloc_syms doesn't know about the GOT */
791 switch (fixP
->fx_r_type
)
793 case BFD_RELOC_8_GOT_PCREL
:
794 case BFD_RELOC_16_GOT_PCREL
:
795 case BFD_RELOC_32_GOT_PCREL
:
796 case BFD_RELOC_8_GOTOFF
:
797 case BFD_RELOC_16_GOTOFF
:
798 case BFD_RELOC_32_GOTOFF
:
799 case BFD_RELOC_8_PLT_PCREL
:
800 case BFD_RELOC_16_PLT_PCREL
:
801 case BFD_RELOC_32_PLT_PCREL
:
802 case BFD_RELOC_8_PLTOFF
:
803 case BFD_RELOC_16_PLTOFF
:
804 case BFD_RELOC_32_PLTOFF
:
814 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
821 tc_gen_reloc (section
, fixp
)
826 bfd_reloc_code_real_type code
;
831 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
833 code
= fixp
->fx_r_type
;
835 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
836 that fixup_segment converted a non-PC relative reloc into a
837 PC relative reloc. In such a case, we need to convert the
844 code
= BFD_RELOC_8_PCREL
;
847 code
= BFD_RELOC_16_PCREL
;
850 code
= BFD_RELOC_32_PCREL
;
852 case BFD_RELOC_8_PCREL
:
853 case BFD_RELOC_16_PCREL
:
854 case BFD_RELOC_32_PCREL
:
855 case BFD_RELOC_8_GOT_PCREL
:
856 case BFD_RELOC_16_GOT_PCREL
:
857 case BFD_RELOC_32_GOT_PCREL
:
858 case BFD_RELOC_8_GOTOFF
:
859 case BFD_RELOC_16_GOTOFF
:
860 case BFD_RELOC_32_GOTOFF
:
861 case BFD_RELOC_8_PLT_PCREL
:
862 case BFD_RELOC_16_PLT_PCREL
:
863 case BFD_RELOC_32_PLT_PCREL
:
864 case BFD_RELOC_8_PLTOFF
:
865 case BFD_RELOC_16_PLTOFF
:
866 case BFD_RELOC_32_PLTOFF
:
869 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
870 _("Cannot make %s relocation PC relative"),
871 bfd_get_reloc_code_name (code
));
877 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
878 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
880 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
881 MAP (1, 0, BFD_RELOC_8
);
882 MAP (2, 0, BFD_RELOC_16
);
883 MAP (4, 0, BFD_RELOC_32
);
884 MAP (1, 1, BFD_RELOC_8_PCREL
);
885 MAP (2, 1, BFD_RELOC_16_PCREL
);
886 MAP (4, 1, BFD_RELOC_32_PCREL
);
894 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
895 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
896 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
899 reloc
->addend
= fixp
->fx_addnumber
;
904 reloc
->addend
= fixp
->fx_addnumber
;
906 reloc
->addend
= (section
->vma
907 + (fixp
->fx_pcrel_adjust
== 64
908 ? -1 : fixp
->fx_pcrel_adjust
)
910 + md_pcrel_from (fixp
));
913 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
914 assert (reloc
->howto
!= 0);
919 #endif /* BFD_ASSEMBLER */
921 /* Handle of the OPCODE hash table. NULL means any use before
922 m68k_ip_begin() will crash. */
923 static struct hash_control
*op_hash
;
925 /* Assemble an m68k instruction. */
932 register struct m68k_op
*opP
;
933 register const struct m68k_incant
*opcode
;
934 register const char *s
;
935 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
936 char *pdot
, *pdotmove
;
937 enum m68k_size siz1
, siz2
;
941 LITTLENUM_TYPE words
[6];
942 LITTLENUM_TYPE
*wordp
;
943 unsigned long ok_arch
= 0;
945 if (*instring
== ' ')
946 instring
++; /* skip leading whitespace */
948 /* Scan up to end of operation-code, which MUST end in end-of-string
949 or exactly 1 space. */
951 for (p
= instring
; *p
!= '\0'; p
++)
961 the_ins
.error
= _("No operator");
965 /* p now points to the end of the opcode name, probably whitespace.
966 Make sure the name is null terminated by clobbering the
967 whitespace, look it up in the hash table, then fix it back.
968 Remove a dot, first, since the opcode tables have none. */
971 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
972 *pdotmove
= pdotmove
[1];
978 opcode
= (const struct m68k_incant
*) hash_find (op_hash
, instring
);
983 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
984 *pdotmove
= pdotmove
[-1];
991 the_ins
.error
= _("Unknown operator");
995 /* found a legitimate opcode, start matching operands */
999 if (opcode
->m_operands
== 0)
1001 char *old
= input_line_pointer
;
1003 input_line_pointer
= p
;
1004 /* Ahh - it's a motorola style psuedo op */
1005 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1006 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1007 input_line_pointer
= old
;
1013 if (flag_mri
&& opcode
->m_opnum
== 0)
1015 /* In MRI mode, random garbage is allowed after an instruction
1016 which accepts no operands. */
1017 the_ins
.args
= opcode
->m_operands
;
1018 the_ins
.numargs
= opcode
->m_opnum
;
1019 the_ins
.numo
= opcode
->m_codenum
;
1020 the_ins
.opcode
[0] = getone (opcode
);
1021 the_ins
.opcode
[1] = gettwo (opcode
);
1025 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1027 p
= crack_operand (p
, opP
);
1031 the_ins
.error
= opP
->error
;
1036 opsfound
= opP
- &the_ins
.operands
[0];
1038 /* This ugly hack is to support the floating pt opcodes in their
1039 standard form. Essentially, we fake a first enty of type COP#1 */
1040 if (opcode
->m_operands
[0] == 'I')
1044 for (n
= opsfound
; n
> 0; --n
)
1045 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1047 memset ((char *) (&the_ins
.operands
[0]), '\0',
1048 sizeof (the_ins
.operands
[0]));
1049 the_ins
.operands
[0].mode
= CONTROL
;
1050 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1054 /* We've got the operands. Find an opcode that'll accept them */
1057 /* If we didn't get the right number of ops, or we have no
1058 common model with this pattern then reject this pattern. */
1060 ok_arch
|= opcode
->m_arch
;
1061 if (opsfound
!= opcode
->m_opnum
1062 || ((opcode
->m_arch
& current_architecture
) == 0))
1066 for (s
= opcode
->m_operands
, opP
= &the_ins
.operands
[0];
1070 /* Warning: this switch is huge! */
1071 /* I've tried to organize the cases into this order:
1072 non-alpha first, then alpha by letter. Lower-case
1073 goes directly before uppercase counterpart. */
1074 /* Code with multiple case ...: gets sorted by the lowest
1075 case ... it belongs to. I hope this makes sense. */
1181 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1198 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1217 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1227 if (opP
->mode
!= IMMED
)
1229 else if (s
[1] == 'b'
1230 && ! isvar (&opP
->disp
)
1231 && (opP
->disp
.exp
.X_op
!= O_constant
1232 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1234 else if (s
[1] == 'B'
1235 && ! isvar (&opP
->disp
)
1236 && (opP
->disp
.exp
.X_op
!= O_constant
1237 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1239 else if (s
[1] == 'w'
1240 && ! isvar (&opP
->disp
)
1241 && (opP
->disp
.exp
.X_op
!= O_constant
1242 || ! isword (opP
->disp
.exp
.X_add_number
)))
1244 else if (s
[1] == 'W'
1245 && ! isvar (&opP
->disp
)
1246 && (opP
->disp
.exp
.X_op
!= O_constant
1247 || ! issword (opP
->disp
.exp
.X_add_number
)))
1253 if (opP
->mode
!= IMMED
)
1258 if (opP
->mode
== AREG
1259 || opP
->mode
== CONTROL
1260 || opP
->mode
== FPREG
1261 || opP
->mode
== IMMED
1262 || opP
->mode
== REGLST
1263 || (opP
->mode
!= ABSL
1265 || opP
->reg
== ZPC
)))
1270 if (opP
->mode
== CONTROL
1271 || opP
->mode
== FPREG
1272 || opP
->mode
== REGLST
1273 || opP
->mode
== IMMED
1274 || (opP
->mode
!= ABSL
1276 || opP
->reg
== ZPC
)))
1304 if (opP
->mode
== CONTROL
1305 || opP
->mode
== FPREG
1306 || opP
->mode
== REGLST
)
1311 if (opP
->mode
!= AINC
)
1316 if (opP
->mode
!= ADEC
)
1366 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1387 case '~': /* For now! (JF FOO is this right?) */
1409 if (opP
->mode
!= CONTROL
1410 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1415 if (opP
->mode
!= AREG
)
1420 if (opP
->mode
!= AINDR
)
1425 if (opP
->mode
!= ABSL
1427 && strncmp (instring
, "jbsr", 4) == 0))
1432 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1437 if (opP
->mode
!= DISP
1439 || opP
->reg
> ADDR7
)
1444 if (opP
->mode
!= DREG
)
1449 if (opP
->mode
!= FPREG
)
1454 if (opP
->mode
!= CONTROL
1461 if (opP
->mode
!= CONTROL
1463 || opP
->reg
> last_movec_reg
)
1467 const enum m68k_register
*rp
;
1468 for (rp
= control_regs
; *rp
; rp
++)
1469 if (*rp
== opP
->reg
)
1477 if (opP
->mode
!= IMMED
)
1483 if (opP
->mode
== DREG
1484 || opP
->mode
== AREG
1485 || opP
->mode
== FPREG
)
1494 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1497 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1500 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1508 else if (opP
->mode
== CONTROL
)
1517 opP
->mask
= 1 << 24;
1520 opP
->mask
= 1 << 25;
1523 opP
->mask
= 1 << 26;
1532 else if (opP
->mode
!= REGLST
)
1534 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
1536 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
1541 if (opP
->mode
!= IMMED
)
1543 else if (opP
->disp
.exp
.X_op
!= O_constant
1544 || ! issbyte (opP
->disp
.exp
.X_add_number
))
1546 else if (! m68k_quick
1547 && instring
[3] != 'q'
1548 && instring
[4] != 'q')
1553 if (opP
->mode
!= DREG
1554 && opP
->mode
!= IMMED
1555 && opP
->mode
!= ABSL
)
1560 if (opP
->mode
!= IMMED
)
1562 else if (opP
->disp
.exp
.X_op
!= O_constant
1563 || opP
->disp
.exp
.X_add_number
< 1
1564 || opP
->disp
.exp
.X_add_number
> 8)
1566 else if (! m68k_quick
1567 && (strncmp (instring
, "add", 3) == 0
1568 || strncmp (instring
, "sub", 3) == 0)
1569 && instring
[3] != 'q')
1574 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1579 if (opP
->mode
!= AINDR
1580 && (opP
->mode
!= BASE
1582 && opP
->reg
!= ZADDR0
)
1583 || opP
->disp
.exp
.X_op
!= O_absent
1584 || ((opP
->index
.reg
< DATA0
1585 || opP
->index
.reg
> DATA7
)
1586 && (opP
->index
.reg
< ADDR0
1587 || opP
->index
.reg
> ADDR7
))
1588 || opP
->index
.size
!= SIZE_UNSPEC
1589 || opP
->index
.scale
!= 1))
1594 if (opP
->mode
!= CONTROL
1595 || ! (opP
->reg
== FPI
1597 || opP
->reg
== FPC
))
1602 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
1607 if (opP
->mode
!= IMMED
)
1609 else if (opP
->disp
.exp
.X_op
!= O_constant
1610 || opP
->disp
.exp
.X_add_number
< 0
1611 || opP
->disp
.exp
.X_add_number
> 7)
1616 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
1620 /* JF these are out of order. We could put them
1621 in order if we were willing to put up with
1622 bunches of #ifdef m68851s in the code.
1624 Don't forget that you need these operands
1625 to use 68030 MMU instructions. */
1627 /* Memory addressing mode used by pflushr */
1629 if (opP
->mode
== CONTROL
1630 || opP
->mode
== FPREG
1631 || opP
->mode
== DREG
1632 || opP
->mode
== AREG
1633 || opP
->mode
== REGLST
)
1635 /* We should accept immediate operands, but they
1636 supposedly have to be quad word, and we don't
1637 handle that. I would like to see what a Motorola
1638 assembler does before doing something here. */
1639 if (opP
->mode
== IMMED
)
1644 if (opP
->mode
!= CONTROL
1645 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1650 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
1655 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
1660 if (opP
->mode
!= CONTROL
1663 && opP
->reg
!= SCC
))
1668 if (opP
->mode
!= CONTROL
1674 if (opP
->mode
!= CONTROL
1677 && opP
->reg
!= CRP
))
1682 if (opP
->mode
!= CONTROL
1683 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
1684 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
1689 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
1694 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
1699 if (opP
->mode
!= CONTROL
1706 } /* not a cache specifier. */
1710 if (opP
->mode
!= ABSL
)
1716 } /* switch on type of operand */
1720 } /* for each operand */
1721 } /* if immediately wrong */
1728 opcode
= opcode
->m_next
;
1733 && !(ok_arch
& current_architecture
))
1738 _("invalid instruction for this architecture; needs "));
1739 cp
= buf
+ strlen (buf
);
1743 strcpy (cp
, _("fpu (68040, 68060 or 68881/68882)"));
1746 strcpy (cp
, _("mmu (68030 or 68851)"));
1749 strcpy (cp
, _("68020 or higher"));
1752 strcpy (cp
, _("68000 or higher"));
1755 strcpy (cp
, _("68010 or higher"));
1759 int got_one
= 0, idx
;
1760 for (idx
= 0; idx
< sizeof (archs
) / sizeof (archs
[0]);
1763 if ((archs
[idx
].arch
& ok_arch
)
1764 && ! archs
[idx
].alias
)
1768 strcpy (cp
, " or ");
1772 strcpy (cp
, archs
[idx
].name
);
1778 cp
= xmalloc (strlen (buf
) + 1);
1783 the_ins
.error
= _("operands mismatch");
1785 } /* Fell off the end */
1790 /* now assemble it */
1792 the_ins
.args
= opcode
->m_operands
;
1793 the_ins
.numargs
= opcode
->m_opnum
;
1794 the_ins
.numo
= opcode
->m_codenum
;
1795 the_ins
.opcode
[0] = getone (opcode
);
1796 the_ins
.opcode
[1] = gettwo (opcode
);
1798 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
1800 /* This switch is a doozy.
1801 Watch the first step; its a big one! */
1829 tmpreg
= 0x3c; /* 7.4 */
1830 if (strchr ("bwl", s
[1]))
1831 nextword
= get_num (&opP
->disp
, 80);
1833 nextword
= get_num (&opP
->disp
, 0);
1834 if (isvar (&opP
->disp
))
1835 add_fix (s
[1], &opP
->disp
, 0, 0);
1839 if (!isbyte (nextword
))
1840 opP
->error
= _("operand out of range");
1845 if (!isword (nextword
))
1846 opP
->error
= _("operand out of range");
1851 if (!issword (nextword
))
1852 opP
->error
= _("operand out of range");
1857 addword (nextword
>> 16);
1884 /* We gotta put out some float */
1885 if (op (&opP
->disp
) != O_big
)
1890 /* Can other cases happen here? */
1891 if (op (&opP
->disp
) != O_constant
)
1894 val
= (valueT
) offs (&opP
->disp
);
1898 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
1899 val
>>= LITTLENUM_NUMBER_OF_BITS
;
1903 offs (&opP
->disp
) = gencnt
;
1905 if (offs (&opP
->disp
) > 0)
1907 if (offs (&opP
->disp
) > baseo
)
1909 as_warn (_("Bignum too big for %c format; truncated"),
1911 offs (&opP
->disp
) = baseo
;
1913 baseo
-= offs (&opP
->disp
);
1916 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
1917 offs (&opP
->disp
)--;
1922 gen_to_words (words
, baseo
, (long) outro
);
1923 for (wordp
= words
; baseo
--; wordp
++)
1927 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
1930 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
1933 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
1936 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
1939 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
1943 nextword
= get_num (&opP
->disp
, 80);
1946 && ! isvar (&opP
->disp
)
1949 opP
->disp
.exp
.X_op
= O_symbol
;
1950 #ifndef BFD_ASSEMBLER
1951 opP
->disp
.exp
.X_add_symbol
= &abs_symbol
;
1953 opP
->disp
.exp
.X_add_symbol
=
1954 section_symbol (absolute_section
);
1958 /* Force into index mode. Hope this works */
1960 /* We do the first bit for 32-bit displacements, and the
1961 second bit for 16 bit ones. It is possible that we
1962 should make the default be WORD instead of LONG, but
1963 I think that'd break GCC, so we put up with a little
1964 inefficiency for the sake of working output. */
1966 if (!issword (nextword
)
1967 || (isvar (&opP
->disp
)
1968 && ((opP
->disp
.size
== SIZE_UNSPEC
1969 && flag_short_refs
== 0
1970 && cpu_of_arch (current_architecture
) >= m68020
1971 && cpu_of_arch (current_architecture
) != mcf5200
)
1972 || opP
->disp
.size
== SIZE_LONG
)))
1974 if (cpu_of_arch (current_architecture
) < m68020
1975 || cpu_of_arch (current_architecture
) == mcf5200
)
1977 _("displacement too large for this architecture; needs 68020 or higher");
1979 tmpreg
= 0x3B; /* 7.3 */
1981 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
1982 if (isvar (&opP
->disp
))
1986 if (opP
->disp
.size
== SIZE_LONG
1988 /* If the displacement needs pic
1989 relocation it cannot be relaxed. */
1990 || opP
->disp
.pic_reloc
!= pic_none
1995 add_fix ('l', &opP
->disp
, 1, 2);
1999 add_frag (adds (&opP
->disp
),
2001 TAB (PCLEA
, SZ_UNDEF
));
2008 add_fix ('l', &opP
->disp
, 0, 0);
2013 addword (nextword
>> 16);
2018 tmpreg
= 0x3A; /* 7.2 */
2020 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2022 if (isvar (&opP
->disp
))
2026 add_fix ('w', &opP
->disp
, 1, 0);
2029 add_fix ('w', &opP
->disp
, 0, 0);
2039 baseo
= get_num (&opP
->disp
, 80);
2040 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2041 outro
= get_num (&opP
->odisp
, 80);
2042 /* Figure out the `addressing mode'.
2043 Also turn on the BASE_DISABLE bit, if needed. */
2044 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2046 tmpreg
= 0x3b; /* 7.3 */
2047 if (opP
->reg
== ZPC
)
2050 else if (opP
->reg
== 0)
2053 tmpreg
= 0x30; /* 6.garbage */
2055 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2058 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2061 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2063 siz1
= opP
->disp
.size
;
2064 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2065 siz2
= opP
->odisp
.size
;
2069 /* Index register stuff */
2070 if (opP
->index
.reg
!= 0
2071 && opP
->index
.reg
>= DATA
2072 && opP
->index
.reg
<= ADDR7
)
2074 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2076 if (opP
->index
.size
== SIZE_LONG
2077 || (opP
->index
.size
== SIZE_UNSPEC
2078 && m68k_index_width_default
== SIZE_LONG
))
2081 if ((opP
->index
.scale
!= 1
2082 && cpu_of_arch (current_architecture
) < m68020
)
2083 || (opP
->index
.scale
== 8
2084 && current_architecture
== mcf5200
))
2087 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2090 switch (opP
->index
.scale
)
2107 GET US OUT OF HERE! */
2109 /* Must be INDEX, with an index register. Address
2110 register cannot be ZERO-PC, and either :b was
2111 forced, or we know it will fit. For a 68000 or
2112 68010, force this mode anyways, because the
2113 larger modes aren't supported. */
2114 if (opP
->mode
== BASE
2115 && ((opP
->reg
>= ADDR0
2116 && opP
->reg
<= ADDR7
)
2119 if (siz1
== SIZE_BYTE
2120 || cpu_of_arch (current_architecture
) < m68020
2121 || cpu_of_arch (current_architecture
) == mcf5200
2122 || (siz1
== SIZE_UNSPEC
2123 && ! isvar (&opP
->disp
)
2124 && issbyte (baseo
)))
2126 nextword
+= baseo
& 0xff;
2128 if (isvar (&opP
->disp
))
2130 /* Do a byte relocation. If it doesn't
2131 fit (possible on m68000) let the
2132 fixup processing complain later. */
2134 add_fix ('B', &opP
->disp
, 1, 1);
2136 add_fix ('B', &opP
->disp
, 0, 0);
2138 else if (siz1
!= SIZE_BYTE
)
2140 if (siz1
!= SIZE_UNSPEC
)
2141 as_warn (_("Forcing byte displacement"));
2142 if (! issbyte (baseo
))
2143 opP
->error
= _("byte displacement out of range");
2148 else if (siz1
== SIZE_UNSPEC
2150 && isvar (&opP
->disp
)
2151 && subs (&opP
->disp
) == NULL
2153 /* If the displacement needs pic
2154 relocation it cannot be relaxed. */
2155 && opP
->disp
.pic_reloc
== pic_none
2159 /* The code in md_convert_frag_1 needs to be
2160 able to adjust nextword. Call frag_grow
2161 to ensure that we have enough space in
2162 the frag obstack to make all the bytes
2165 nextword
+= baseo
& 0xff;
2167 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2168 TAB (PCINDEX
, SZ_UNDEF
));
2176 nextword
|= 0x40; /* No index reg */
2177 if (opP
->index
.reg
>= ZDATA0
2178 && opP
->index
.reg
<= ZDATA7
)
2179 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2180 else if (opP
->index
.reg
>= ZADDR0
2181 || opP
->index
.reg
<= ZADDR7
)
2182 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2185 /* It isn't simple. */
2187 if (cpu_of_arch (current_architecture
) < m68020
2188 || cpu_of_arch (current_architecture
) == mcf5200
)
2190 _("invalid operand mode for this architecture; needs 68020 or higher");
2193 /* If the guy specified a width, we assume that it is
2194 wide enough. Maybe it isn't. If so, we lose. */
2198 if (isvar (&opP
->disp
)
2200 : ! issword (baseo
))
2205 else if (! isvar (&opP
->disp
) && baseo
== 0)
2214 as_warn (_(":b not permitted; defaulting to :w"));
2224 /* Figure out innner displacement stuff */
2225 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2227 if (cpu_of_arch (current_architecture
) & cpu32
)
2228 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2232 if (isvar (&opP
->odisp
)
2234 : ! issword (outro
))
2239 else if (! isvar (&opP
->odisp
) && outro
== 0)
2248 as_warn (_(":b not permitted; defaulting to :w"));
2257 if (opP
->mode
== POST
2258 && (nextword
& 0x40) == 0)
2263 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2265 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2266 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2268 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2270 if (siz1
== SIZE_LONG
)
2271 addword (baseo
>> 16);
2272 if (siz1
!= SIZE_UNSPEC
)
2275 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2276 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2277 if (siz2
== SIZE_LONG
)
2278 addword (outro
>> 16);
2279 if (siz2
!= SIZE_UNSPEC
)
2285 nextword
= get_num (&opP
->disp
, 80);
2286 switch (opP
->disp
.size
)
2291 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2293 tmpreg
= 0x38; /* 7.0 */
2297 /* Don't generate pc relative code on 68010 and
2299 if (isvar (&opP
->disp
)
2300 && !subs (&opP
->disp
)
2301 && adds (&opP
->disp
)
2303 /* If the displacement needs pic relocation it
2304 cannot be relaxed. */
2305 && opP
->disp
.pic_reloc
== pic_none
2307 && S_GET_SEGMENT (adds (&opP
->disp
)) == now_seg
2308 && HAVE_LONG_BRANCH(current_architecture
)
2310 && !strchr ("~%&$?", s
[0]))
2312 tmpreg
= 0x3A; /* 7.2 */
2313 add_frag (adds (&opP
->disp
),
2315 TAB (PCREL
, SZ_UNDEF
));
2318 /* Fall through into long */
2320 if (isvar (&opP
->disp
))
2321 add_fix ('l', &opP
->disp
, 0, 0);
2323 tmpreg
= 0x39;/* 7.1 mode */
2324 addword (nextword
>> 16);
2329 as_bad (_("unsupported byte value; use a different suffix"));
2331 case SIZE_WORD
: /* Word */
2332 if (isvar (&opP
->disp
))
2333 add_fix ('w', &opP
->disp
, 0, 0);
2335 tmpreg
= 0x38;/* 7.0 mode */
2343 as_bad (_("unknown/incorrect operand"));
2346 install_gen_operand (s
[1], tmpreg
);
2352 { /* JF: I hate floating point! */
2367 tmpreg
= get_num (&opP
->disp
, tmpreg
);
2368 if (isvar (&opP
->disp
))
2369 add_fix (s
[1], &opP
->disp
, 0, 0);
2372 case 'b': /* Danger: These do no check for
2373 certain types of overflow.
2375 if (!isbyte (tmpreg
))
2376 opP
->error
= _("out of range");
2377 insop (tmpreg
, opcode
);
2378 if (isvar (&opP
->disp
))
2379 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
2380 (opcode
->m_codenum
) * 2 + 1;
2383 if (!issbyte (tmpreg
))
2384 opP
->error
= _("out of range");
2385 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
2386 if (isvar (&opP
->disp
))
2387 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
2390 if (!isword (tmpreg
))
2391 opP
->error
= _("out of range");
2392 insop (tmpreg
, opcode
);
2393 if (isvar (&opP
->disp
))
2394 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2397 if (!issword (tmpreg
))
2398 opP
->error
= _("out of range");
2399 insop (tmpreg
, opcode
);
2400 if (isvar (&opP
->disp
))
2401 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2404 /* Because of the way insop works, we put these two out
2406 insop (tmpreg
, opcode
);
2407 insop (tmpreg
>> 16, opcode
);
2408 if (isvar (&opP
->disp
))
2409 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2416 install_operand (s
[1], tmpreg
);
2427 install_operand (s
[1], opP
->reg
- ADDR
);
2431 tmpreg
= get_num (&opP
->disp
, 80);
2435 /* The pc_fix argument winds up in fx_pcrel_adjust,
2436 which is a char, and may therefore be unsigned. We
2437 want to pass -1, but we pass 64 instead, and convert
2438 back in md_pcrel_from. */
2439 add_fix ('B', &opP
->disp
, 1, 64);
2442 add_fix ('w', &opP
->disp
, 1, 0);
2447 if (!HAVE_LONG_BRANCH(current_architecture
))
2448 as_warn (_("Can't use long branches on 68000/68010/5200"));
2449 the_ins
.opcode
[the_ins
.numo
- 1] |= 0xff;
2450 add_fix ('l', &opP
->disp
, 1, 0);
2455 if (subs (&opP
->disp
)) /* We can't relax it */
2459 /* If the displacement needs pic relocation it cannot be
2461 if (opP
->disp
.pic_reloc
!= pic_none
)
2465 /* This could either be a symbol, or an absolute
2466 address. No matter, the frag hacking will finger it
2467 out. Not quite: it can't switch from BRANCH to
2468 BCC68000 for the case where opnd is absolute (it
2469 needs to use the 68000 hack since no conditional abs
2471 if (( !HAVE_LONG_BRANCH(current_architecture
)
2472 || (0 == adds (&opP
->disp
)))
2473 && (the_ins
.opcode
[0] >= 0x6200)
2474 && (the_ins
.opcode
[0] <= 0x6f00))
2475 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2476 TAB (BCC68000
, SZ_UNDEF
));
2478 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2479 TAB (ABRANCH
, SZ_UNDEF
));
2482 if (isvar (&opP
->disp
))
2485 /* check for DBcc instruction */
2486 if ((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2488 /* size varies if patch */
2489 /* needed for long form */
2490 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2491 TAB (DBCC
, SZ_UNDEF
));
2495 add_fix ('w', &opP
->disp
, 1, 0);
2499 case 'C': /* Fixed size LONG coproc branches */
2500 add_fix ('l', &opP
->disp
, 1, 0);
2504 case 'c': /* Var size Coprocesssor branches */
2505 if (subs (&opP
->disp
))
2507 add_fix ('l', &opP
->disp
, 1, 0);
2508 add_frag ((symbolS
*) 0, (offsetT
) 0, TAB (FBRANCH
, LONG
));
2510 else if (adds (&opP
->disp
))
2511 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2512 TAB (FBRANCH
, SZ_UNDEF
));
2515 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2516 TAB(FBRANCH,SHORT)); */
2517 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2518 add_fix ('l', &opP
->disp
, 1, 0);
2528 case 'C': /* Ignore it */
2531 case 'd': /* JF this is a kludge */
2532 install_operand ('s', opP
->reg
- ADDR
);
2533 tmpreg
= get_num (&opP
->disp
, 80);
2534 if (!issword (tmpreg
))
2536 as_warn (_("Expression out of range, using 0"));
2543 install_operand (s
[1], opP
->reg
- DATA
);
2547 install_operand (s
[1], opP
->reg
- FP0
);
2551 tmpreg
= opP
->reg
- COP0
;
2552 install_operand (s
[1], tmpreg
);
2555 case 'J': /* JF foo */
2628 install_operand (s
[1], tmpreg
);
2632 tmpreg
= get_num (&opP
->disp
, 55);
2633 install_operand (s
[1], tmpreg
& 0x7f);
2640 if (tmpreg
& 0x7FF0000)
2641 as_bad (_("Floating point register in register list"));
2642 insop (reverse_16_bits (tmpreg
), opcode
);
2646 if (tmpreg
& 0x700FFFF)
2647 as_bad (_("Wrong register in floating-point reglist"));
2648 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
2656 if (tmpreg
& 0x7FF0000)
2657 as_bad (_("Floating point register in register list"));
2658 insop (tmpreg
, opcode
);
2660 else if (s
[1] == '8')
2662 if (tmpreg
& 0x0FFFFFF)
2663 as_bad (_("incorrect register in reglist"));
2664 install_operand (s
[1], tmpreg
>> 24);
2668 if (tmpreg
& 0x700FFFF)
2669 as_bad (_("wrong register in floating-point reglist"));
2671 install_operand (s
[1], tmpreg
>> 16);
2676 install_operand (s
[1], get_num (&opP
->disp
, 60));
2680 tmpreg
= ((opP
->mode
== DREG
)
2681 ? 0x20 + opP
->reg
- DATA
2682 : (get_num (&opP
->disp
, 40) & 0x1F));
2683 install_operand (s
[1], tmpreg
);
2687 tmpreg
= get_num (&opP
->disp
, 10);
2690 install_operand (s
[1], tmpreg
);
2694 /* This depends on the fact that ADDR registers are eight
2695 more than their corresponding DATA regs, so the result
2696 will have the ADDR_REG bit set */
2697 install_operand (s
[1], opP
->reg
- DATA
);
2701 if (opP
->mode
== AINDR
)
2702 install_operand (s
[1], opP
->reg
- DATA
);
2704 install_operand (s
[1], opP
->index
.reg
- DATA
);
2708 if (opP
->reg
== FPI
)
2710 else if (opP
->reg
== FPS
)
2712 else if (opP
->reg
== FPC
)
2716 install_operand (s
[1], tmpreg
);
2719 case 'S': /* Ignore it */
2723 install_operand (s
[1], get_num (&opP
->disp
, 30));
2726 case 'U': /* Ignore it */
2745 as_fatal (_("failed sanity check"));
2746 } /* switch on cache token */
2747 install_operand (s
[1], tmpreg
);
2750 /* JF: These are out of order, I fear. */
2763 install_operand (s
[1], tmpreg
);
2789 install_operand (s
[1], tmpreg
);
2793 if (opP
->reg
== VAL
)
2812 install_operand (s
[1], tmpreg
);
2826 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
2837 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
2843 install_operand (s
[1], tmpreg
);
2846 know (opP
->reg
== PSR
);
2849 know (opP
->reg
== PCSR
);
2864 install_operand (s
[1], tmpreg
);
2867 tmpreg
= get_num (&opP
->disp
, 20);
2868 install_operand (s
[1], tmpreg
);
2870 case '_': /* used only for move16 absolute 32-bit address */
2871 if (isvar (&opP
->disp
))
2872 add_fix ('l', &opP
->disp
, 0, 0);
2873 tmpreg
= get_num (&opP
->disp
, 80);
2874 addword (tmpreg
>> 16);
2875 addword (tmpreg
& 0xFFFF);
2882 /* By the time whe get here (FINALLY) the_ins contains the complete
2883 instruction, ready to be emitted. . . */
2887 reverse_16_bits (in
)
2893 static int mask
[16] =
2895 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2896 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2898 for (n
= 0; n
< 16; n
++)
2901 out
|= mask
[15 - n
];
2904 } /* reverse_16_bits() */
2913 static int mask
[8] =
2915 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2918 for (n
= 0; n
< 8; n
++)
2924 } /* reverse_8_bits() */
2926 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2927 (that value is chosen in the frag_var call in md_assemble). TYPE
2928 is the subtype of the frag to be generated; its primary type is
2929 rs_machine_dependent.
2931 The TYPE parameter is also used by md_convert_frag_1 and
2932 md_estimate_size_before_relax. The appropriate type of fixup will
2933 be emitted by md_convert_frag_1.
2935 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2937 install_operand (mode
, val
)
2944 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge */
2947 the_ins
.opcode
[0] |= val
<< 9;
2950 the_ins
.opcode
[1] |= val
<< 12;
2953 the_ins
.opcode
[1] |= val
<< 6;
2956 the_ins
.opcode
[1] |= val
;
2959 the_ins
.opcode
[2] |= val
<< 12;
2962 the_ins
.opcode
[2] |= val
<< 6;
2965 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2966 three words long! */
2968 the_ins
.opcode
[2] |= val
;
2971 the_ins
.opcode
[1] |= val
<< 7;
2974 the_ins
.opcode
[1] |= val
<< 10;
2978 the_ins
.opcode
[1] |= val
<< 5;
2983 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
2986 the_ins
.opcode
[1] |= (val
<< 12) | val
;
2989 the_ins
.opcode
[0] |= val
= 0xff;
2992 the_ins
.opcode
[0] |= val
<< 9;
2995 the_ins
.opcode
[1] |= val
;
2998 the_ins
.opcode
[1] |= val
;
2999 the_ins
.numo
++; /* What a hack */
3002 the_ins
.opcode
[1] |= val
<< 4;
3010 the_ins
.opcode
[0] |= (val
<< 6);
3013 the_ins
.opcode
[1] = (val
>> 16);
3014 the_ins
.opcode
[2] = val
& 0xffff;
3018 as_fatal (_("failed sanity check."));
3020 } /* install_operand() */
3023 install_gen_operand (mode
, val
)
3030 the_ins
.opcode
[0] |= val
;
3033 /* This is a kludge!!! */
3034 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3043 the_ins
.opcode
[0] |= val
;
3045 /* more stuff goes here */
3047 as_fatal (_("failed sanity check."));
3049 } /* install_gen_operand() */
3052 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3053 * then deal with the bitfield hack.
3057 crack_operand (str
, opP
)
3059 register struct m68k_op
*opP
;
3061 register int parens
;
3063 register char *beg_str
;
3071 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3077 else if (*str
== ')')
3081 opP
->error
= _("Extra )");
3087 if (flag_mri
&& *str
== '\'')
3088 inquote
= ! inquote
;
3090 if (!*str
&& parens
)
3092 opP
->error
= _("Missing )");
3097 if (m68k_ip_op (beg_str
, opP
) != 0)
3104 c
= *++str
; /* JF bitfield hack */
3109 as_bad (_("Missing operand"));
3112 /* Detect MRI REG symbols and convert them to REGLSTs. */
3113 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
3116 opP
->mask
= ~(int)opP
->reg
;
3123 /* This is the guts of the machine-dependent assembler. STR points to a
3124 machine dependent instruction. This function is supposed to emit
3125 the frags/bytes it assembles to.
3129 insert_reg (regname
, regnum
)
3130 const char *regname
;
3136 #ifdef REGISTER_PREFIX
3137 if (!flag_reg_prefix_optional
)
3139 buf
[0] = REGISTER_PREFIX
;
3140 strcpy (buf
+ 1, regname
);
3145 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
3146 &zero_address_frag
));
3148 for (i
= 0; regname
[i
]; i
++)
3149 buf
[i
] = islower (regname
[i
]) ? toupper (regname
[i
]) : regname
[i
];
3152 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
3153 &zero_address_frag
));
3162 static const struct init_entry init_table
[] =
3217 /* control registers */
3218 { "sfc", SFC
}, /* Source Function Code */
3220 { "dfc", DFC
}, /* Destination Function Code */
3222 { "cacr", CACR
}, /* Cache Control Register */
3223 { "caar", CAAR
}, /* Cache Address Register */
3225 { "usp", USP
}, /* User Stack Pointer */
3226 { "vbr", VBR
}, /* Vector Base Register */
3227 { "msp", MSP
}, /* Master Stack Pointer */
3228 { "isp", ISP
}, /* Interrupt Stack Pointer */
3230 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0 */
3231 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1 */
3232 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0 */
3233 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1 */
3235 /* 68ec040 versions of same */
3236 { "iacr0", ITT0
}, /* Instruction Access Control Register 0 */
3237 { "iacr1", ITT1
}, /* Instruction Access Control Register 0 */
3238 { "dacr0", DTT0
}, /* Data Access Control Register 0 */
3239 { "dacr1", DTT1
}, /* Data Access Control Register 0 */
3241 /* mcf5200 versions of same. The ColdFire programmer's reference
3242 manual indicated that the order is 2,3,0,1, but Ken Rose
3243 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3244 { "acr0", ITT0
}, /* Access Control Unit 0 */
3245 { "acr1", ITT1
}, /* Access Control Unit 1 */
3246 { "acr2", DTT0
}, /* Access Control Unit 2 */
3247 { "acr3", DTT1
}, /* Access Control Unit 3 */
3249 { "tc", TC
}, /* MMU Translation Control Register */
3252 { "mmusr", MMUSR
}, /* MMU Status Register */
3253 { "srp", SRP
}, /* User Root Pointer */
3254 { "urp", URP
}, /* Supervisor Root Pointer */
3259 { "rombar", ROMBAR
}, /* ROM Base Address Register */
3260 { "rambar0", RAMBAR0
}, /* ROM Base Address Register */
3261 { "rambar1", RAMBAR1
}, /* ROM Base Address Register */
3262 { "mbar", MBAR
}, /* Module Base Address Register */
3263 /* end of control registers */
3297 /* 68ec030 versions of same */
3300 /* 68ec030 access control unit, identical to 030 MMU status reg */
3303 /* Suppressed data and address registers. */
3328 for (i
= 0; init_table
[i
].name
; i
++)
3329 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
3332 static int no_68851
, no_68881
;
3335 /* a.out machine type. Default to 68020. */
3336 int m68k_aout_machtype
= 2;
3348 int shorts_this_frag
;
3351 /* In MRI mode, the instruction and operands are separated by a
3352 space. Anything following the operands is a comment. The label
3353 has already been removed. */
3361 for (s
= str
; *s
!= '\0'; s
++)
3363 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
3381 inquote
= ! inquote
;
3386 memset ((char *) (&the_ins
), '\0', sizeof (the_ins
));
3391 for (n
= 0; n
< the_ins
.numargs
; n
++)
3392 if (the_ins
.operands
[n
].error
)
3394 er
= the_ins
.operands
[n
].error
;
3400 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
3404 /* If there is a current label, record that it marks an instruction. */
3405 if (current_label
!= NULL
)
3407 current_label
->text
= 1;
3408 current_label
= NULL
;
3411 if (the_ins
.nfrag
== 0)
3413 /* No frag hacking involved; just put it out */
3414 toP
= frag_more (2 * the_ins
.numo
);
3415 fromP
= &the_ins
.opcode
[0];
3416 for (m
= the_ins
.numo
; m
; --m
)
3418 md_number_to_chars (toP
, (long) (*fromP
), 2);
3422 /* put out symbol-dependent info */
3423 for (m
= 0; m
< the_ins
.nrel
; m
++)
3425 switch (the_ins
.reloc
[m
].wid
)
3444 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3445 the_ins
.reloc
[m
].wid
);
3448 fixP
= fix_new_exp (frag_now
,
3449 ((toP
- frag_now
->fr_literal
)
3450 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3452 &the_ins
.reloc
[m
].exp
,
3453 the_ins
.reloc
[m
].pcrel
,
3454 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
3455 the_ins
.reloc
[m
].pic_reloc
));
3456 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3457 if (the_ins
.reloc
[m
].wid
== 'B')
3458 fixP
->fx_signed
= 1;
3463 /* There's some frag hacking */
3464 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
3469 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
3471 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3472 toP
= frag_more (wid
);
3474 shorts_this_frag
= 0;
3475 for (m
= wid
/ 2; m
; --m
)
3477 md_number_to_chars (toP
, (long) (*fromP
), 2);
3482 for (m
= 0; m
< the_ins
.nrel
; m
++)
3484 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
3486 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
3489 wid
= the_ins
.reloc
[m
].wid
;
3492 the_ins
.reloc
[m
].wid
= 0;
3493 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3495 fixP
= fix_new_exp (frag_now
,
3496 ((toP
- frag_now
->fr_literal
)
3497 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3499 &the_ins
.reloc
[m
].exp
,
3500 the_ins
.reloc
[m
].pcrel
,
3501 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
3502 the_ins
.reloc
[m
].pic_reloc
));
3503 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3505 (void) frag_var (rs_machine_dependent
, 10, 0,
3506 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
3507 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
3509 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3510 shorts_this_frag
= 0;
3513 toP
= frag_more (n
* sizeof (short));
3516 md_number_to_chars (toP
, (long) (*fromP
), 2);
3522 for (m
= 0; m
< the_ins
.nrel
; m
++)
3526 wid
= the_ins
.reloc
[m
].wid
;
3529 the_ins
.reloc
[m
].wid
= 0;
3530 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3532 fixP
= fix_new_exp (frag_now
,
3533 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
3534 - shorts_this_frag
* 2),
3536 &the_ins
.reloc
[m
].exp
,
3537 the_ins
.reloc
[m
].pcrel
,
3538 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
3539 the_ins
.reloc
[m
].pic_reloc
));
3540 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3548 * md_begin -- set up hash tables with 68000 instructions.
3549 * similar to what the vax assembler does. ---phr
3551 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3552 a copy of it at runtime, adding in the information we want but isn't
3553 there. I think it'd be better to have an awk script hack the table
3554 at compile time. Or even just xstr the table and use it as-is. But
3555 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3558 register const struct m68k_opcode
*ins
;
3559 register struct m68k_incant
*hack
, *slak
;
3560 register const char *retval
= 0; /* empty string, or error msg text */
3561 register unsigned int i
;
3566 flag_reg_prefix_optional
= 1;
3568 if (! m68k_rel32_from_cmdline
)
3572 op_hash
= hash_new ();
3574 obstack_begin (&robyn
, 4000);
3575 for (i
= 0; i
< m68k_numopcodes
; i
++)
3577 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3580 ins
= &m68k_opcodes
[i
];
3581 /* We *could* ignore insns that don't match our arch here
3582 but just leaving them out of the hash. */
3583 slak
->m_operands
= ins
->args
;
3584 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
3585 slak
->m_arch
= ins
->arch
;
3586 slak
->m_opcode
= ins
->opcode
;
3587 /* This is kludgey */
3588 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
3589 if (i
+ 1 != m68k_numopcodes
3590 && !strcmp (ins
->name
, m68k_opcodes
[i
+ 1].name
))
3592 slak
->m_next
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3597 slak
= slak
->m_next
;
3601 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
3603 as_fatal (_("Internal Error: Can't hash %s: %s"), ins
->name
, retval
);
3606 for (i
= 0; i
< m68k_numaliases
; i
++)
3608 const char *name
= m68k_opcode_aliases
[i
].primary
;
3609 const char *alias
= m68k_opcode_aliases
[i
].alias
;
3610 PTR val
= hash_find (op_hash
, name
);
3612 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
3613 retval
= hash_insert (op_hash
, alias
, val
);
3615 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
3618 /* In MRI mode, all unsized branches are variable sized. Normally,
3619 they are word sized. */
3622 static struct m68k_opcode_alias mri_aliases
[] =
3642 for (i
= 0; i
< sizeof mri_aliases
/ sizeof mri_aliases
[0]; i
++)
3644 const char *name
= mri_aliases
[i
].primary
;
3645 const char *alias
= mri_aliases
[i
].alias
;
3646 PTR val
= hash_find (op_hash
, name
);
3648 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
3649 retval
= hash_jam (op_hash
, alias
, val
);
3651 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
3655 for (i
= 0; i
< sizeof (mklower_table
); i
++)
3656 mklower_table
[i
] = (isupper (c
= (char) i
)) ? tolower (c
) : c
;
3658 for (i
= 0; i
< sizeof (notend_table
); i
++)
3660 notend_table
[i
] = 0;
3661 alt_notend_table
[i
] = 0;
3663 notend_table
[','] = 1;
3664 notend_table
['{'] = 1;
3665 notend_table
['}'] = 1;
3666 alt_notend_table
['a'] = 1;
3667 alt_notend_table
['A'] = 1;
3668 alt_notend_table
['d'] = 1;
3669 alt_notend_table
['D'] = 1;
3670 alt_notend_table
['#'] = 1;
3671 alt_notend_table
['&'] = 1;
3672 alt_notend_table
['f'] = 1;
3673 alt_notend_table
['F'] = 1;
3674 #ifdef REGISTER_PREFIX
3675 alt_notend_table
[REGISTER_PREFIX
] = 1;
3678 /* We need to put '(' in alt_notend_table to handle
3679 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3681 alt_notend_table
['('] = 1;
3683 /* We need to put '@' in alt_notend_table to handle
3684 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3686 alt_notend_table
['@'] = 1;
3688 /* We need to put digits in alt_notend_table to handle
3689 bfextu %d0{24:1},%d0
3691 alt_notend_table
['0'] = 1;
3692 alt_notend_table
['1'] = 1;
3693 alt_notend_table
['2'] = 1;
3694 alt_notend_table
['3'] = 1;
3695 alt_notend_table
['4'] = 1;
3696 alt_notend_table
['5'] = 1;
3697 alt_notend_table
['6'] = 1;
3698 alt_notend_table
['7'] = 1;
3699 alt_notend_table
['8'] = 1;
3700 alt_notend_table
['9'] = 1;
3702 #ifndef MIT_SYNTAX_ONLY
3703 /* Insert pseudo ops, these have to go into the opcode table since
3704 gas expects pseudo ops to start with a dot */
3707 while (mote_pseudo_table
[n
].poc_name
)
3709 hack
= (struct m68k_incant
*)
3710 obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3711 hash_insert (op_hash
,
3712 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
3713 hack
->m_operands
= 0;
3723 record_alignment (text_section
, 2);
3724 record_alignment (data_section
, 2);
3725 record_alignment (bss_section
, 2);
3730 select_control_regs ()
3732 /* Note which set of "movec" control registers is available. */
3733 switch (cpu_of_arch (current_architecture
))
3736 control_regs
= m68000_control_regs
;
3739 control_regs
= m68010_control_regs
;
3743 control_regs
= m68020_control_regs
;
3746 control_regs
= m68040_control_regs
;
3749 control_regs
= m68060_control_regs
;
3752 control_regs
= cpu32_control_regs
;
3755 control_regs
= mcf5200_control_regs
;
3763 m68k_init_after_args ()
3765 if (cpu_of_arch (current_architecture
) == 0)
3768 const char *default_cpu
= TARGET_CPU
;
3770 if (*default_cpu
== 'm')
3772 for (i
= 0; i
< n_archs
; i
++)
3773 if (strcasecmp (default_cpu
, archs
[i
].name
) == 0)
3777 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU
);
3778 current_architecture
|= m68020
;
3781 current_architecture
|= archs
[i
].arch
;
3783 /* Permit m68881 specification with all cpus; those that can't work
3784 with a coprocessor could be doing emulation. */
3785 if (current_architecture
& m68851
)
3787 if (current_architecture
& m68040
)
3789 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
3792 /* What other incompatibilities could we check for? */
3794 /* Toss in some default assumptions about coprocessors. */
3796 && (cpu_of_arch (current_architecture
)
3797 /* Can CPU32 have a 68881 coprocessor?? */
3798 & (m68020
| m68030
| cpu32
)))
3800 current_architecture
|= m68881
;
3803 && (cpu_of_arch (current_architecture
) & m68020up
) != 0
3804 && (cpu_of_arch (current_architecture
) & m68040up
) == 0)
3806 current_architecture
|= m68851
;
3808 if (no_68881
&& (current_architecture
& m68881
))
3809 as_bad (_("options for 68881 and no-68881 both given"));
3810 if (no_68851
&& (current_architecture
& m68851
))
3811 as_bad (_("options for 68851 and no-68851 both given"));
3814 /* Work out the magic number. This isn't very general. */
3815 if (current_architecture
& m68000
)
3816 m68k_aout_machtype
= 0;
3817 else if (current_architecture
& m68010
)
3818 m68k_aout_machtype
= 1;
3819 else if (current_architecture
& m68020
)
3820 m68k_aout_machtype
= 2;
3822 m68k_aout_machtype
= 2;
3825 /* Note which set of "movec" control registers is available. */
3826 select_control_regs ();
3828 if (cpu_of_arch (current_architecture
) < m68020
3829 || cpu_of_arch (current_architecture
) == mcf5200
)
3830 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
3833 /* This is called when a label is defined. */
3836 m68k_frob_label (sym
)
3839 struct label_line
*n
;
3841 n
= (struct label_line
*) xmalloc (sizeof *n
);
3844 as_where (&n
->file
, &n
->line
);
3850 /* This is called when a value that is not an instruction is emitted. */
3853 m68k_flush_pending_output ()
3855 current_label
= NULL
;
3858 /* This is called at the end of the assembly, when the final value of
3859 the label is known. We warn if this is a text symbol aligned at an
3863 m68k_frob_symbol (sym
)
3866 if (S_GET_SEGMENT (sym
) == reg_section
3867 && (int) S_GET_VALUE (sym
) < 0)
3869 S_SET_SEGMENT (sym
, absolute_section
);
3870 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
3872 else if ((S_GET_VALUE (sym
) & 1) != 0)
3874 struct label_line
*l
;
3876 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3878 if (l
->label
== sym
)
3881 as_warn_where (l
->file
, l
->line
,
3882 _("text label `%s' aligned to odd boundary"),
3890 /* This is called if we go in or out of MRI mode because of the .mri
3894 m68k_mri_mode_change (on
)
3899 if (! flag_reg_prefix_optional
)
3901 flag_reg_prefix_optional
= 1;
3902 #ifdef REGISTER_PREFIX
3907 if (! m68k_rel32_from_cmdline
)
3912 if (! reg_prefix_optional_seen
)
3914 #ifdef REGISTER_PREFIX_OPTIONAL
3915 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
3917 flag_reg_prefix_optional
= 0;
3919 #ifdef REGISTER_PREFIX
3924 if (! m68k_rel32_from_cmdline
)
3929 /* Equal to MAX_PRECISION in atof-ieee.c */
3930 #define MAX_LITTLENUMS 6
3932 /* Turn a string in input_line_pointer into a floating point constant
3933 of type type, and store the appropriate bytes in *litP. The number
3934 of LITTLENUMS emitted is stored in *sizeP . An error message is
3935 returned, or NULL on OK. */
3938 md_atof (type
, litP
, sizeP
)
3944 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3945 LITTLENUM_TYPE
*wordP
;
3976 return _("Bad call to MD_ATOF()");
3978 t
= atof_ieee (input_line_pointer
, type
, words
);
3980 input_line_pointer
= t
;
3982 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
3983 for (wordP
= words
; prec
--;)
3985 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
3986 litP
+= sizeof (LITTLENUM_TYPE
);
3992 md_number_to_chars (buf
, val
, n
)
3997 number_to_chars_bigendian (buf
, val
, n
);
4001 md_apply_fix_2 (fixP
, val
)
4005 addressT upper_limit
;
4006 offsetT lower_limit
;
4008 /* This is unnecessary but it convinces the native rs6000 compiler
4009 to generate the code we want. */
4010 char *buf
= fixP
->fx_frag
->fr_literal
;
4011 buf
+= fixP
->fx_where
;
4012 /* end ibm compiler workaround */
4014 if (val
& 0x80000000)
4015 val
|= ~(addressT
)0x7fffffff;
4022 memset (buf
, 0, fixP
->fx_size
);
4023 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc */
4028 switch (fixP
->fx_size
)
4030 /* The cast to offsetT below are necessary to make code correct for
4031 machines where ints are smaller than offsetT */
4035 lower_limit
= - (offsetT
) 0x80;
4038 *buf
++ = (val
>> 8);
4040 upper_limit
= 0x7fff;
4041 lower_limit
= - (offsetT
) 0x8000;
4044 *buf
++ = (val
>> 24);
4045 *buf
++ = (val
>> 16);
4046 *buf
++ = (val
>> 8);
4048 upper_limit
= 0x7fffffff;
4049 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* avoid constant overflow */
4052 BAD_CASE (fixP
->fx_size
);
4055 /* Fix up a negative reloc. */
4056 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4058 fixP
->fx_addsy
= fixP
->fx_subsy
;
4059 fixP
->fx_subsy
= NULL
;
4063 /* For non-pc-relative values, it's conceivable we might get something
4064 like "0xff" for a byte field. So extend the upper part of the range
4065 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4066 so that we can do any range checking at all. */
4067 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
4068 upper_limit
= upper_limit
* 2 + 1;
4070 if ((addressT
) val
> upper_limit
4071 && (val
> 0 || val
< lower_limit
))
4072 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("value out of range"));
4074 /* A one byte PC-relative reloc means a short branch. We can't use
4075 a short branch with a value of 0 or -1, because those indicate
4076 different opcodes (branches with longer offsets). fixup_segment
4077 in write.c may have clobbered fx_pcrel, so we need to examine the
4080 #ifdef BFD_ASSEMBLER
4081 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
4084 && fixP
->fx_size
== 1
4085 && (fixP
->fx_addsy
== NULL
4086 || S_IS_DEFINED (fixP
->fx_addsy
))
4087 && (val
== 0 || val
== -1))
4088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("invalid byte branch offset"));
4091 #ifdef BFD_ASSEMBLER
4093 md_apply_fix (fixP
, valp
)
4097 md_apply_fix_2 (fixP
, (addressT
) *valp
);
4101 void md_apply_fix (fixP
, val
)
4105 md_apply_fix_2 (fixP
, (addressT
) val
);
4109 /* *fragP has been relaxed to its final size, and now needs to have
4110 the bytes inside it modified to conform to the new size There is UGLY
4114 md_convert_frag_1 (fragP
)
4115 register fragS
*fragP
;
4121 /* Address in object code of the displacement. */
4122 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4124 /* Address in gas core of the place to store the displacement. */
4125 /* This convinces the native rs6000 compiler to generate the code we
4127 register char *buffer_address
= fragP
->fr_literal
;
4128 buffer_address
+= fragP
->fr_fix
;
4129 /* end ibm compiler workaround */
4131 /* The displacement of the address, from current location. */
4132 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4133 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4135 #ifdef BFD_ASSEMBLER
4136 disp
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
4139 switch (fragP
->fr_subtype
)
4141 case TAB (BCC68000
, BYTE
):
4142 case TAB (ABRANCH
, BYTE
):
4143 know (issbyte (disp
));
4145 as_bad (_("short branch with zero offset: use :w"));
4146 fragP
->fr_opcode
[1] = disp
;
4149 case TAB (DBCC
, SHORT
):
4150 know (issword (disp
));
4153 case TAB (BCC68000
, SHORT
):
4154 case TAB (ABRANCH
, SHORT
):
4155 know (issword (disp
));
4156 fragP
->fr_opcode
[1] = 0x00;
4159 case TAB (ABRANCH
, LONG
):
4160 if (!HAVE_LONG_BRANCH(current_architecture
))
4162 if (fragP
->fr_opcode
[0] == 0x61)
4165 fragP
->fr_opcode
[0] = 0x4E;
4166 fragP
->fr_opcode
[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4180 else if (fragP
->fr_opcode
[0] == 0x60)
4182 fragP
->fr_opcode
[0] = 0x4E;
4183 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4184 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4185 fragP
->fr_offset
, 0, NO_RELOC
);
4191 as_bad (_("Long branch offset not supported."));
4196 fragP
->fr_opcode
[1] = (char) 0xff;
4200 case TAB (BCC68000
, LONG
):
4201 /* only Bcc 68000 instructions can come here */
4202 /* change bcc into b!cc/jmp absl long */
4203 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
4204 fragP
->fr_opcode
[1] = 0x6;/* branch offset = 6 */
4206 /* JF: these used to be fr_opcode[2,3], but they may be in a
4207 different frag, in which case refering to them is a no-no.
4208 Only fr_opcode[0,1] are guaranteed to work. */
4209 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4210 *buffer_address
++ = (char) 0xf9;
4211 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4212 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4213 fragP
->fr_offset
, 0, NO_RELOC
);
4217 case TAB (DBCC
, LONG
):
4218 /* only DBcc 68000 instructions can come here */
4219 /* change dbcc into dbcc/jmp absl long */
4220 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4221 *buffer_address
++ = 0x00; /* branch offset = 4 */
4222 *buffer_address
++ = 0x04;
4223 *buffer_address
++ = 0x60; /* put in bra pc+6 */
4224 *buffer_address
++ = 0x06;
4225 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4226 *buffer_address
++ = (char) 0xf9;
4228 fragP
->fr_fix
+= 6; /* account for bra/jmp instructions */
4229 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4230 fragP
->fr_offset
, 0, NO_RELOC
);
4234 case TAB (FBRANCH
, SHORT
):
4235 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4238 case TAB (FBRANCH
, LONG
):
4239 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit */
4242 case TAB (PCREL
, SHORT
):
4245 case TAB (PCREL
, LONG
):
4246 /* The thing to do here is force it to ABSOLUTE LONG, since
4247 PCREL is really trying to shorten an ABSOLUTE address anyway */
4248 /* JF FOO This code has not been tested */
4249 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4251 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
4252 as_bad (_("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx"),
4253 (unsigned) fragP
->fr_opcode
[0],
4254 (unsigned long) fragP
->fr_address
);
4255 fragP
->fr_opcode
[1] &= ~0x3F;
4256 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
4260 case TAB (PCLEA
, SHORT
):
4261 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4262 fragP
->fr_offset
, 1, NO_RELOC
);
4263 fragP
->fr_opcode
[1] &= ~0x3F;
4264 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
4267 case TAB (PCLEA
, LONG
):
4268 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
) + 2, 4, fragP
->fr_symbol
,
4269 fragP
->fr_offset
, 1, NO_RELOC
);
4270 fixP
->fx_pcrel_adjust
= 2;
4271 /* Already set to mode 7.3; this indicates: PC indirect with
4272 suppressed index, 32-bit displacement. */
4273 *buffer_address
++ = 0x01;
4274 *buffer_address
++ = 0x70;
4279 case TAB (PCINDEX
, BYTE
):
4281 if (!issbyte (disp
))
4283 as_bad (_("displacement doesn't fit in one byte"));
4286 assert (fragP
->fr_fix
>= 2);
4287 buffer_address
[-2] &= ~1;
4288 buffer_address
[-1] = disp
;
4291 case TAB (PCINDEX
, SHORT
):
4293 assert (issword (disp
));
4294 assert (fragP
->fr_fix
>= 2);
4295 buffer_address
[-2] |= 0x1;
4296 buffer_address
[-1] = 0x20;
4297 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4298 fragP
->fr_offset
, (fragP
->fr_opcode
[1] & 077) == 073,
4300 fixP
->fx_pcrel_adjust
= 2;
4303 case TAB (PCINDEX
, LONG
):
4305 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4306 fragP
->fr_offset
, (fragP
->fr_opcode
[1] & 077) == 073,
4308 fixP
->fx_pcrel_adjust
= 2;
4309 assert (fragP
->fr_fix
>= 2);
4310 buffer_address
[-2] |= 0x1;
4311 buffer_address
[-1] = 0x30;
4318 md_number_to_chars (buffer_address
, (long) disp
, (int) ext
);
4319 fragP
->fr_fix
+= ext
;
4323 #ifndef BFD_ASSEMBLER
4326 md_convert_frag (headers
, sec
, fragP
)
4327 object_headers
*headers
;
4331 md_convert_frag_1 (fragP
);
4337 md_convert_frag (abfd
, sec
, fragP
)
4342 md_convert_frag_1 (fragP
);
4346 /* Force truly undefined symbols to their maximum size, and generally set up
4347 the frag list to be relaxed
4350 md_estimate_size_before_relax (fragP
, segment
)
4351 register fragS
*fragP
;
4355 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
4357 old_fix
= fragP
->fr_fix
;
4359 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4360 switch (fragP
->fr_subtype
)
4363 case TAB (ABRANCH
, SZ_UNDEF
):
4365 if ((fragP
->fr_symbol
!= NULL
) /* Not absolute */
4366 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4368 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4371 else if ((fragP
->fr_symbol
== 0) || !HAVE_LONG_BRANCH(current_architecture
))
4373 /* On 68000, or for absolute value, switch to abs long */
4374 /* FIXME, we should check abs val, pick short or long */
4375 if (fragP
->fr_opcode
[0] == 0x61)
4377 fragP
->fr_opcode
[0] = 0x4E;
4378 fragP
->fr_opcode
[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4379 fix_new (fragP
, fragP
->fr_fix
, 4,
4380 fragP
->fr_symbol
, fragP
->fr_offset
, 0, NO_RELOC
);
4384 else if (fragP
->fr_opcode
[0] == 0x60)
4386 fragP
->fr_opcode
[0] = 0x4E;
4387 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4388 fix_new (fragP
, fragP
->fr_fix
, 4,
4389 fragP
->fr_symbol
, fragP
->fr_offset
, 0, NO_RELOC
);
4395 as_warn (_("Long branch offset to extern symbol not supported."));
4399 { /* Symbol is still undefined. Make it simple */
4400 fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4401 fragP
->fr_offset
, 1, NO_RELOC
);
4403 fragP
->fr_opcode
[1] = (char) 0xff;
4409 } /* case TAB(ABRANCH,SZ_UNDEF) */
4411 case TAB (FBRANCH
, SZ_UNDEF
):
4413 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
|| flag_short_refs
)
4415 fragP
->fr_subtype
= TAB (FBRANCH
, SHORT
);
4420 fix_new (fragP
, (int) fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4421 fragP
->fr_offset
, 1, NO_RELOC
);
4423 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit */
4427 } /* TAB(FBRANCH,SZ_UNDEF) */
4429 case TAB (PCREL
, SZ_UNDEF
):
4431 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4433 || cpu_of_arch (current_architecture
) < m68020
4434 || cpu_of_arch (current_architecture
) == mcf5200
)
4436 fragP
->fr_subtype
= TAB (PCREL
, SHORT
);
4441 fragP
->fr_subtype
= TAB (PCREL
, LONG
);
4445 } /* TAB(PCREL,SZ_UNDEF) */
4447 case TAB (BCC68000
, SZ_UNDEF
):
4449 if ((fragP
->fr_symbol
!= NULL
)
4450 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4452 fragP
->fr_subtype
= TAB (BCC68000
, BYTE
);
4455 /* only Bcc 68000 instructions can come here */
4456 /* change bcc into b!cc/jmp absl long */
4457 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
4458 if (flag_short_refs
)
4460 fragP
->fr_opcode
[1] = 0x04; /* branch offset = 6 */
4461 /* JF: these were fr_opcode[2,3] */
4462 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
4463 buffer_address
[1] = (char) 0xf8;
4464 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4465 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4466 fragP
->fr_offset
, 0, NO_RELOC
);
4471 fragP
->fr_opcode
[1] = 0x06; /* branch offset = 6 */
4472 /* JF: these were fr_opcode[2,3] */
4473 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
4474 buffer_address
[1] = (char) 0xf9;
4475 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4476 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4477 fragP
->fr_offset
, 0, NO_RELOC
);
4482 } /* case TAB(BCC68000,SZ_UNDEF) */
4484 case TAB (DBCC
, SZ_UNDEF
):
4486 if (fragP
->fr_symbol
!= NULL
&& S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4488 fragP
->fr_subtype
= TAB (DBCC
, SHORT
);
4492 /* only DBcc 68000 instructions can come here */
4493 /* change dbcc into dbcc/jmp absl long */
4494 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4495 buffer_address
[0] = 0x00; /* branch offset = 4 */
4496 buffer_address
[1] = 0x04;
4497 buffer_address
[2] = 0x60; /* put in bra pc + ... */
4499 if (flag_short_refs
)
4501 /* JF: these were fr_opcode[5-7] */
4502 buffer_address
[3] = 0x04; /* plus 4 */
4503 buffer_address
[4] = 0x4e; /* Put in Jump Word */
4504 buffer_address
[5] = (char) 0xf8;
4505 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
4506 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4507 fragP
->fr_offset
, 0, NO_RELOC
);
4512 /* JF: these were fr_opcode[5-7] */
4513 buffer_address
[3] = 0x06; /* Plus 6 */
4514 buffer_address
[4] = 0x4e; /* put in jmp long (0x4ef9) */
4515 buffer_address
[5] = (char) 0xf9;
4516 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
4517 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4518 fragP
->fr_offset
, 0, NO_RELOC
);
4524 } /* case TAB(DBCC,SZ_UNDEF) */
4526 case TAB (PCLEA
, SZ_UNDEF
):
4528 if ((S_GET_SEGMENT (fragP
->fr_symbol
)) == segment
4530 || cpu_of_arch (current_architecture
) < m68020
4531 || cpu_of_arch (current_architecture
) == mcf5200
)
4533 fragP
->fr_subtype
= TAB (PCLEA
, SHORT
);
4538 fragP
->fr_subtype
= TAB (PCLEA
, LONG
);
4542 } /* TAB(PCLEA,SZ_UNDEF) */
4544 case TAB (PCINDEX
, SZ_UNDEF
):
4545 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4546 || cpu_of_arch (current_architecture
) < m68020
4547 || cpu_of_arch (current_architecture
) == mcf5200
)
4549 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
4553 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
4562 /* now that SZ_UNDEF are taken care of, check others */
4563 switch (fragP
->fr_subtype
)
4565 case TAB (BCC68000
, BYTE
):
4566 case TAB (ABRANCH
, BYTE
):
4567 /* We can't do a short jump to the next instruction, so in that
4568 case we force word mode. At this point S_GET_VALUE should
4569 return the offset of the symbol within its frag. If the
4570 symbol is at the start of a frag, and it is the next frag
4571 with any data in it (usually this is just the next frag, but
4572 assembler listings may introduce empty frags), we must use
4574 if (fragP
->fr_symbol
&& S_GET_VALUE (fragP
->fr_symbol
) == 0)
4578 for (l
= fragP
->fr_next
;
4579 l
!= fragP
->fr_symbol
->sy_frag
;
4581 if (l
->fr_fix
+ l
->fr_var
!= 0)
4583 if (l
== fragP
->fr_symbol
->sy_frag
)
4585 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4593 return fragP
->fr_var
+ fragP
->fr_fix
- old_fix
;
4596 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4597 /* the bit-field entries in the relocation_info struct plays hell
4598 with the byte-order problems of cross-assembly. So as a hack,
4599 I added this mach. dependent ri twiddler. Ugly, but it gets
4601 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4602 are symbolnum, most sig. byte first. Last byte is broken up with
4603 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4604 nibble as nuthin. (on Sun 3 at least) */
4605 /* Translate the internal relocation information into target-specific
4609 md_ri_to_chars (the_bytes
, ri
)
4611 struct reloc_info_generic
*ri
;
4614 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
4615 /* now the fun stuff */
4616 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
4617 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
4618 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
4619 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80) | ((ri
->r_length
<< 5) & 0x60) |
4620 ((ri
->r_extern
<< 4) & 0x10));
4623 #endif /* comment */
4625 #ifndef BFD_ASSEMBLER
4627 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4630 relax_addressT segment_address_in_file
;
4633 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4634 * Out: GNU LD relocation length code: 0, 1, or 2.
4637 static CONST
unsigned char nbytes_r_length
[] = {42, 0, 1, 42, 2};
4640 know (fixP
->fx_addsy
!= NULL
);
4642 md_number_to_chars (where
,
4643 fixP
->fx_frag
->fr_address
+ fixP
->fx_where
- segment_address_in_file
,
4646 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4647 ? S_GET_TYPE (fixP
->fx_addsy
)
4648 : fixP
->fx_addsy
->sy_number
);
4650 where
[4] = (r_symbolnum
>> 16) & 0x0ff;
4651 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4652 where
[6] = r_symbolnum
& 0x0ff;
4653 where
[7] = (((fixP
->fx_pcrel
<< 7) & 0x80) | ((nbytes_r_length
[fixP
->fx_size
] << 5) & 0x60) |
4654 (((!S_IS_DEFINED (fixP
->fx_addsy
)) << 4) & 0x10));
4658 #endif /* OBJ_AOUT or OBJ_BOUT */
4660 #ifndef WORKING_DOT_WORD
4661 CONST
int md_short_jump_size
= 4;
4662 CONST
int md_long_jump_size
= 6;
4665 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4667 addressT from_addr
, to_addr
;
4673 offset
= to_addr
- (from_addr
+ 2);
4675 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
4676 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
4680 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4682 addressT from_addr
, to_addr
;
4688 if (!HAVE_LONG_BRANCH(current_architecture
))
4690 offset
= to_addr
- S_GET_VALUE (to_symbol
);
4691 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
4692 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4693 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
4698 offset
= to_addr
- (from_addr
+ 2);
4699 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
4700 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4706 /* Different values of OK tell what its OK to return. Things that
4707 aren't OK are an error (what a shock, no?)
4710 10: Absolute 1:8 only
4711 20: Absolute 0:7 only
4712 30: absolute 0:15 only
4713 40: Absolute 0:31 only
4714 50: absolute 0:127 only
4715 55: absolute -64:63 only
4716 60: absolute -128:127 only
4717 70: absolute 0:4095 only
4724 struct m68k_exp
*exp
;
4727 if (exp
->exp
.X_op
== O_absent
)
4729 /* Do the same thing the VAX asm does */
4730 op (exp
) = O_constant
;
4736 as_warn (_("expression out of range: defaulting to 1"));
4740 else if (exp
->exp
.X_op
== O_constant
)
4745 if (offs (exp
) < 1 || offs (exp
) > 8)
4747 as_warn (_("expression out of range: defaulting to 1"));
4752 if (offs (exp
) < 0 || offs (exp
) > 7)
4756 if (offs (exp
) < 0 || offs (exp
) > 15)
4760 if (offs (exp
) < 0 || offs (exp
) > 32)
4764 if (offs (exp
) < 0 || offs (exp
) > 127)
4768 if (offs (exp
) < -64 || offs (exp
) > 63)
4772 if (offs (exp
) < -128 || offs (exp
) > 127)
4776 if (offs (exp
) < 0 || offs (exp
) > 4095)
4779 as_warn (_("expression out of range: defaulting to 0"));
4787 else if (exp
->exp
.X_op
== O_big
)
4789 if (offs (exp
) <= 0 /* flonum */
4790 && (ok
== 80 /* no bignums */
4791 || (ok
> 10 /* small-int ranges including 0 ok */
4792 /* If we have a flonum zero, a zero integer should
4793 do as well (e.g., in moveq). */
4794 && generic_floating_point_number
.exponent
== 0
4795 && generic_floating_point_number
.low
[0] == 0)))
4797 /* HACK! Turn it into a long */
4798 LITTLENUM_TYPE words
[6];
4800 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
4801 op (exp
) = O_constant
;
4804 offs (exp
) = words
[1] | (words
[0] << 16);
4808 op (exp
) = O_constant
;
4811 offs (exp
) = (ok
== 10) ? 1 : 0;
4812 as_warn (_("Can't deal with expression; defaulting to %ld"),
4818 if (ok
>= 10 && ok
<= 70)
4820 op (exp
) = O_constant
;
4823 offs (exp
) = (ok
== 10) ? 1 : 0;
4824 as_warn (_("Can't deal with expression; defaulting to %ld"),
4829 if (exp
->size
!= SIZE_UNSPEC
)
4837 if (!isbyte (offs (exp
)))
4838 as_warn (_("expression doesn't fit in BYTE"));
4841 if (!isword (offs (exp
)))
4842 as_warn (_("expression doesn't fit in WORD"));
4850 /* These are the back-ends for the various machine dependent pseudo-ops. */
4856 subseg_set (data_section
, 1);
4857 demand_empty_rest_of_line ();
4864 subseg_set (data_section
, 2);
4865 demand_empty_rest_of_line ();
4872 /* We don't support putting frags in the BSS segment, we fake it
4873 by marking in_bss, then looking at s_skip for clues. */
4875 subseg_set (bss_section
, 0);
4876 demand_empty_rest_of_line ();
4884 register long temp_fill
;
4886 temp
= 1; /* JF should be 2? */
4887 temp_fill
= get_absolute_expression ();
4888 if (!need_pass_2
) /* Never make frag if expect extra pass. */
4889 frag_align (temp
, (int) temp_fill
, 0);
4890 demand_empty_rest_of_line ();
4891 record_alignment (now_seg
, temp
);
4898 demand_empty_rest_of_line ();
4901 /* Pseudo-ops handled for MRI compatibility. */
4903 /* This function returns non-zero if the argument is a conditional
4904 pseudo-op. This is called when checking whether a pending
4905 alignment is needed. */
4908 m68k_conditional_pseudoop (pop
)
4911 return (pop
->poc_handler
== s_mri_if
4912 || pop
->poc_handler
== s_mri_else
);
4915 /* Handle an MRI style chip specification. */
4924 s
= input_line_pointer
;
4925 /* We can't use get_symbol_end since the processor names are not proper
4927 while (is_part_of_name (c
= *input_line_pointer
++))
4929 *--input_line_pointer
= 0;
4930 for (i
= 0; i
< n_archs
; i
++)
4931 if (strcasecmp (s
, archs
[i
].name
) == 0)
4935 as_bad (_("%s: unrecognized processor name"), s
);
4936 *input_line_pointer
= c
;
4937 ignore_rest_of_line ();
4940 *input_line_pointer
= c
;
4942 if (*input_line_pointer
== '/')
4943 current_architecture
= 0;
4945 current_architecture
&= m68881
| m68851
;
4946 current_architecture
|= archs
[i
].arch
;
4948 while (*input_line_pointer
== '/')
4950 ++input_line_pointer
;
4951 s
= input_line_pointer
;
4952 /* We can't use get_symbol_end since the processor names are not
4954 while (is_part_of_name (c
= *input_line_pointer
++))
4956 *--input_line_pointer
= 0;
4957 if (strcmp (s
, "68881") == 0)
4958 current_architecture
|= m68881
;
4959 else if (strcmp (s
, "68851") == 0)
4960 current_architecture
|= m68851
;
4961 *input_line_pointer
= c
;
4964 /* Update info about available control registers. */
4965 select_control_regs ();
4968 /* The MRI CHIP pseudo-op. */
4978 stop
= mri_comment_field (&stopc
);
4981 mri_comment_end (stop
, stopc
);
4982 demand_empty_rest_of_line ();
4985 /* The MRI FOPT pseudo-op. */
4993 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
4997 input_line_pointer
+= 3;
4998 temp
= get_absolute_expression ();
4999 if (temp
< 0 || temp
> 7)
5000 as_bad (_("bad coprocessor id"));
5002 m68k_float_copnum
= COP0
+ temp
;
5006 as_bad (_("unrecognized fopt option"));
5007 ignore_rest_of_line ();
5011 demand_empty_rest_of_line ();
5014 /* The structure used to handle the MRI OPT pseudo-op. */
5018 /* The name of the option. */
5021 /* If this is not NULL, just call this function. The first argument
5022 is the ARG field of this structure, the second argument is
5023 whether the option was negated. */
5024 void (*pfn
) PARAMS ((int arg
, int on
));
5026 /* If this is not NULL, and the PFN field is NULL, set the variable
5027 this points to. Set it to the ARG field if the option was not
5028 negated, and the NOTARG field otherwise. */
5031 /* The value to pass to PFN or to assign to *PVAR. */
5034 /* The value to assign to *PVAR if the option is negated. If PFN is
5035 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5036 the option may not be negated. */
5040 /* The table used to handle the MRI OPT pseudo-op. */
5042 static void skip_to_comma
PARAMS ((int, int));
5043 static void opt_nest
PARAMS ((int, int));
5044 static void opt_chip
PARAMS ((int, int));
5045 static void opt_list
PARAMS ((int, int));
5046 static void opt_list_symbols
PARAMS ((int, int));
5048 static const struct opt_action opt_table
[] =
5050 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5052 /* We do relaxing, so there is little use for these options. */
5053 { "b", 0, 0, 0, 0 },
5054 { "brs", 0, 0, 0, 0 },
5055 { "brb", 0, 0, 0, 0 },
5056 { "brl", 0, 0, 0, 0 },
5057 { "brw", 0, 0, 0, 0 },
5059 { "c", 0, 0, 0, 0 },
5060 { "cex", 0, 0, 0, 0 },
5061 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5062 { "cl", 0, 0, 0, 0 },
5063 { "cre", 0, 0, 0, 0 },
5064 { "d", 0, &flag_keep_locals
, 1, 0 },
5065 { "e", 0, 0, 0, 0 },
5066 { "f", 0, &flag_short_refs
, 1, 0 },
5067 { "frs", 0, &flag_short_refs
, 1, 0 },
5068 { "frl", 0, &flag_short_refs
, 0, 1 },
5069 { "g", 0, 0, 0, 0 },
5070 { "i", 0, 0, 0, 0 },
5071 { "m", 0, 0, 0, 0 },
5072 { "mex", 0, 0, 0, 0 },
5073 { "mc", 0, 0, 0, 0 },
5074 { "md", 0, 0, 0, 0 },
5075 { "nest", opt_nest
, 0, 0, 0 },
5076 { "next", skip_to_comma
, 0, 0, 0 },
5077 { "o", 0, 0, 0, 0 },
5078 { "old", 0, 0, 0, 0 },
5079 { "op", skip_to_comma
, 0, 0, 0 },
5080 { "pco", 0, 0, 0, 0 },
5081 { "p", opt_chip
, 0, 0, 0 },
5082 { "pcr", 0, 0, 0, 0 },
5083 { "pcs", 0, 0, 0, 0 },
5084 { "r", 0, 0, 0, 0 },
5085 { "quick", 0, &m68k_quick
, 1, 0 },
5086 { "rel32", 0, &m68k_rel32
, 1, 0 },
5087 { "s", opt_list
, 0, 0, 0 },
5088 { "t", opt_list_symbols
, 0, 0, 0 },
5089 { "w", 0, &flag_no_warnings
, 0, 1 },
5093 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5095 /* The MRI OPT pseudo-op. */
5107 const struct opt_action
*o
;
5112 if (*input_line_pointer
== '-')
5114 ++input_line_pointer
;
5117 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5119 input_line_pointer
+= 2;
5123 s
= input_line_pointer
;
5124 c
= get_symbol_end ();
5126 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5128 if (strcasecmp (s
, o
->name
) == 0)
5132 /* Restore input_line_pointer now in case the option
5134 *input_line_pointer
= c
;
5135 (*o
->pfn
) (o
->arg
, t
);
5137 else if (o
->pvar
!= NULL
)
5139 if (! t
&& o
->arg
== o
->notarg
)
5140 as_bad (_("option `%s' may not be negated"), s
);
5141 *input_line_pointer
= c
;
5142 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5145 *input_line_pointer
= c
;
5151 as_bad (_("option `%s' not recognized"), s
);
5152 *input_line_pointer
= c
;
5155 while (*input_line_pointer
++ == ',');
5157 /* Move back to terminating character. */
5158 --input_line_pointer
;
5159 demand_empty_rest_of_line ();
5162 /* Skip ahead to a comma. This is used for OPT options which we do
5163 not suppor tand which take arguments. */
5166 skip_to_comma (arg
, on
)
5170 while (*input_line_pointer
!= ','
5171 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5172 ++input_line_pointer
;
5175 /* Handle the OPT NEST=depth option. */
5182 if (*input_line_pointer
!= '=')
5184 as_bad (_("bad format of OPT NEST=depth"));
5188 ++input_line_pointer
;
5189 max_macro_nest
= get_absolute_expression ();
5192 /* Handle the OPT P=chip option. */
5199 if (*input_line_pointer
!= '=')
5201 /* This is just OPT P, which we do not support. */
5205 ++input_line_pointer
;
5209 /* Handle the OPT S option. */
5219 /* Handle the OPT T option. */
5222 opt_list_symbols (arg
, on
)
5227 listing
|= LISTING_SYMBOLS
;
5229 listing
&=~ LISTING_SYMBOLS
;
5232 /* Handle the MRI REG pseudo-op. */
5245 if (line_label
== NULL
)
5247 as_bad (_("missing label"));
5248 ignore_rest_of_line ();
5253 stop
= mri_comment_field (&stopc
);
5257 s
= input_line_pointer
;
5258 while (isalnum ((unsigned char) *input_line_pointer
)
5259 #ifdef REGISTER_PREFIX
5260 || *input_line_pointer
== REGISTER_PREFIX
5262 || *input_line_pointer
== '/'
5263 || *input_line_pointer
== '-')
5264 ++input_line_pointer
;
5265 c
= *input_line_pointer
;
5266 *input_line_pointer
= '\0';
5268 if (m68k_ip_op (s
, &rop
) != 0)
5270 if (rop
.error
== NULL
)
5271 as_bad (_("bad register list"));
5273 as_bad (_("bad register list: %s"), rop
.error
);
5274 *input_line_pointer
= c
;
5275 ignore_rest_of_line ();
5279 *input_line_pointer
= c
;
5281 if (rop
.mode
== REGLST
)
5283 else if (rop
.mode
== DREG
)
5284 mask
= 1 << (rop
.reg
- DATA0
);
5285 else if (rop
.mode
== AREG
)
5286 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
5287 else if (rop
.mode
== FPREG
)
5288 mask
= 1 << (rop
.reg
- FP0
+ 16);
5289 else if (rop
.mode
== CONTROL
5292 else if (rop
.mode
== CONTROL
5295 else if (rop
.mode
== CONTROL
5300 as_bad (_("bad register list"));
5301 ignore_rest_of_line ();
5305 S_SET_SEGMENT (line_label
, reg_section
);
5306 S_SET_VALUE (line_label
, ~mask
);
5307 line_label
->sy_frag
= &zero_address_frag
;
5310 mri_comment_end (stop
, stopc
);
5312 demand_empty_rest_of_line ();
5315 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5319 struct save_opts
*next
;
5321 int symbols_case_sensitive
;
5329 /* FIXME: We don't save OPT S. */
5332 /* This variable holds the stack of saved options. */
5334 static struct save_opts
*save_stack
;
5336 /* The MRI SAVE pseudo-op. */
5342 struct save_opts
*s
;
5344 s
= (struct save_opts
*) xmalloc (sizeof (struct save_opts
));
5345 s
->abspcadd
= m68k_abspcadd
;
5346 s
->symbols_case_sensitive
= symbols_case_sensitive
;
5347 s
->keep_locals
= flag_keep_locals
;
5348 s
->short_refs
= flag_short_refs
;
5349 s
->architecture
= current_architecture
;
5350 s
->quick
= m68k_quick
;
5351 s
->rel32
= m68k_rel32
;
5352 s
->listing
= listing
;
5353 s
->no_warnings
= flag_no_warnings
;
5355 s
->next
= save_stack
;
5358 demand_empty_rest_of_line ();
5361 /* The MRI RESTORE pseudo-op. */
5367 struct save_opts
*s
;
5369 if (save_stack
== NULL
)
5371 as_bad (_("restore without save"));
5372 ignore_rest_of_line ();
5377 save_stack
= s
->next
;
5379 m68k_abspcadd
= s
->abspcadd
;
5380 symbols_case_sensitive
= s
->symbols_case_sensitive
;
5381 flag_keep_locals
= s
->keep_locals
;
5382 flag_short_refs
= s
->short_refs
;
5383 current_architecture
= s
->architecture
;
5384 m68k_quick
= s
->quick
;
5385 m68k_rel32
= s
->rel32
;
5386 listing
= s
->listing
;
5387 flag_no_warnings
= s
->no_warnings
;
5391 demand_empty_rest_of_line ();
5394 /* Types of MRI structured control directives. */
5396 enum mri_control_type
5404 /* This structure is used to stack the MRI structured control
5407 struct mri_control_info
5409 /* The directive within which this one is enclosed. */
5410 struct mri_control_info
*outer
;
5412 /* The type of directive. */
5413 enum mri_control_type type
;
5415 /* Whether an ELSE has been in an IF. */
5418 /* The add or sub statement at the end of a FOR. */
5421 /* The label of the top of a FOR or REPEAT loop. */
5424 /* The label to jump to for the next iteration, or the else
5425 expression of a conditional. */
5428 /* The label to jump to to break out of the loop, or the label past
5429 the end of a conditional. */
5433 /* The stack of MRI structured control directives. */
5435 static struct mri_control_info
*mri_control_stack
;
5437 /* The current MRI structured control directive index number, used to
5438 generate label names. */
5440 static int mri_control_index
;
5442 /* Some function prototypes. */
5444 static char *mri_control_label
PARAMS ((void));
5445 static struct mri_control_info
*push_mri_control
5446 PARAMS ((enum mri_control_type
));
5447 static void pop_mri_control
PARAMS ((void));
5448 static int parse_mri_condition
PARAMS ((int *));
5449 static int parse_mri_control_operand
5450 PARAMS ((int *, char **, char **, char **, char **));
5451 static int swap_mri_condition
PARAMS ((int));
5452 static int reverse_mri_condition
PARAMS ((int));
5453 static void build_mri_control_operand
5454 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5455 const char *, int));
5456 static void parse_mri_control_expression
5457 PARAMS ((char *, int, const char *, const char *, int));
5459 /* Generate a new MRI label structured control directive label name. */
5462 mri_control_label ()
5466 n
= (char *) xmalloc (20);
5467 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
5468 ++mri_control_index
;
5472 /* Create a new MRI structured control directive. */
5474 static struct mri_control_info
*
5475 push_mri_control (type
)
5476 enum mri_control_type type
;
5478 struct mri_control_info
*n
;
5480 n
= (struct mri_control_info
*) xmalloc (sizeof (struct mri_control_info
));
5484 if (type
== mri_if
|| type
== mri_while
)
5487 n
->top
= mri_control_label ();
5488 n
->next
= mri_control_label ();
5489 n
->bottom
= mri_control_label ();
5491 n
->outer
= mri_control_stack
;
5492 mri_control_stack
= n
;
5497 /* Pop off the stack of MRI structured control directives. */
5502 struct mri_control_info
*n
;
5504 n
= mri_control_stack
;
5505 mri_control_stack
= n
->outer
;
5513 /* Recognize a condition code in an MRI structured control expression. */
5516 parse_mri_condition (pcc
)
5521 know (*input_line_pointer
== '<');
5523 ++input_line_pointer
;
5524 c1
= *input_line_pointer
++;
5525 c2
= *input_line_pointer
++;
5527 if (*input_line_pointer
!= '>')
5529 as_bad (_("syntax error in structured control directive"));
5533 ++input_line_pointer
;
5541 *pcc
= (c1
<< 8) | c2
;
5546 /* Parse a single operand in an MRI structured control expression. */
5549 parse_mri_control_operand (pcc
, leftstart
, leftstop
, rightstart
, rightstop
)
5566 if (*input_line_pointer
== '<')
5568 /* It's just a condition code. */
5569 return parse_mri_condition (pcc
);
5572 /* Look ahead for the condition code. */
5573 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5575 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
5580 as_bad (_("missing condition code in structured control directive"));
5584 *leftstart
= input_line_pointer
;
5586 if (*leftstop
> *leftstart
5587 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
5590 input_line_pointer
= s
;
5591 if (! parse_mri_condition (pcc
))
5594 /* Look ahead for AND or OR or end of line. */
5595 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5597 if ((strncasecmp (s
, "AND", 3) == 0
5598 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
5599 || (strncasecmp (s
, "OR", 2) == 0
5600 && (s
[2] == '.' || ! is_part_of_name (s
[2]))))
5604 *rightstart
= input_line_pointer
;
5606 if (*rightstop
> *rightstart
5607 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
5610 input_line_pointer
= s
;
5615 #define MCC(b1, b2) (((b1) << 8) | (b2))
5617 /* Swap the sense of a condition. This changes the condition so that
5618 it generates the same result when the operands are swapped. */
5621 swap_mri_condition (cc
)
5626 case MCC ('h', 'i'): return MCC ('c', 's');
5627 case MCC ('l', 's'): return MCC ('c', 'c');
5628 case MCC ('c', 'c'): return MCC ('l', 's');
5629 case MCC ('c', 's'): return MCC ('h', 'i');
5630 case MCC ('p', 'l'): return MCC ('m', 'i');
5631 case MCC ('m', 'i'): return MCC ('p', 'l');
5632 case MCC ('g', 'e'): return MCC ('l', 'e');
5633 case MCC ('l', 't'): return MCC ('g', 't');
5634 case MCC ('g', 't'): return MCC ('l', 't');
5635 case MCC ('l', 'e'): return MCC ('g', 'e');
5640 /* Reverse the sense of a condition. */
5643 reverse_mri_condition (cc
)
5648 case MCC ('h', 'i'): return MCC ('l', 's');
5649 case MCC ('l', 's'): return MCC ('h', 'i');
5650 case MCC ('c', 'c'): return MCC ('c', 's');
5651 case MCC ('c', 's'): return MCC ('c', 'c');
5652 case MCC ('n', 'e'): return MCC ('e', 'q');
5653 case MCC ('e', 'q'): return MCC ('n', 'e');
5654 case MCC ('v', 'c'): return MCC ('v', 's');
5655 case MCC ('v', 's'): return MCC ('v', 'c');
5656 case MCC ('p', 'l'): return MCC ('m', 'i');
5657 case MCC ('m', 'i'): return MCC ('p', 'l');
5658 case MCC ('g', 'e'): return MCC ('l', 't');
5659 case MCC ('l', 't'): return MCC ('g', 'e');
5660 case MCC ('g', 't'): return MCC ('l', 'e');
5661 case MCC ('l', 'e'): return MCC ('g', 't');
5666 /* Build an MRI structured control expression. This generates test
5667 and branch instructions. It goes to TRUELAB if the condition is
5668 true, and to FALSELAB if the condition is false. Exactly one of
5669 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5670 is the size qualifier for the expression. EXTENT is the size to
5671 use for the branch. */
5674 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5675 rightstop
, truelab
, falselab
, extent
)
5682 const char *truelab
;
5683 const char *falselab
;
5689 if (leftstart
!= NULL
)
5691 struct m68k_op leftop
, rightop
;
5694 /* Swap the compare operands, if necessary, to produce a legal
5695 m68k compare instruction. Comparing a register operand with
5696 a non-register operand requires the register to be on the
5697 right (cmp, cmpa). Comparing an immediate value with
5698 anything requires the immediate value to be on the left
5703 (void) m68k_ip_op (leftstart
, &leftop
);
5708 (void) m68k_ip_op (rightstart
, &rightop
);
5711 if (rightop
.mode
== IMMED
5712 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
5713 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
5717 cc
= swap_mri_condition (cc
);
5719 leftstart
= rightstart
;
5722 leftstop
= rightstop
;
5727 if (truelab
== NULL
)
5729 cc
= reverse_mri_condition (cc
);
5733 if (leftstart
!= NULL
)
5735 buf
= (char *) xmalloc (20
5736 + (leftstop
- leftstart
)
5737 + (rightstop
- rightstart
));
5745 memcpy (s
, leftstart
, leftstop
- leftstart
);
5746 s
+= leftstop
- leftstart
;
5748 memcpy (s
, rightstart
, rightstop
- rightstart
);
5749 s
+= rightstop
- rightstart
;
5755 buf
= (char *) xmalloc (20 + strlen (truelab
));
5763 strcpy (s
, truelab
);
5768 /* Parse an MRI structured control expression. This generates test
5769 and branch instructions. STOP is where the expression ends. It
5770 goes to TRUELAB if the condition is true, and to FALSELAB if the
5771 condition is false. Exactly one of TRUELAB and FALSELAB will be
5772 NULL, meaning to fall through. QUAL is the size qualifier for the
5773 expression. EXTENT is the size to use for the branch. */
5776 parse_mri_control_expression (stop
, qual
, truelab
, falselab
, extent
)
5779 const char *truelab
;
5780 const char *falselab
;
5793 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
5794 &rightstart
, &rightstop
))
5800 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
5804 if (falselab
!= NULL
)
5807 flab
= mri_control_label ();
5809 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5810 rightstop
, (const char *) NULL
, flab
, extent
);
5812 input_line_pointer
+= 3;
5813 if (*input_line_pointer
!= '.'
5814 || input_line_pointer
[1] == '\0')
5818 qual
= input_line_pointer
[1];
5819 input_line_pointer
+= 2;
5822 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
5823 &rightstart
, &rightstop
))
5829 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5830 rightstop
, truelab
, falselab
, extent
);
5832 if (falselab
== NULL
)
5835 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
5839 if (truelab
!= NULL
)
5842 tlab
= mri_control_label ();
5844 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5845 rightstop
, tlab
, (const char *) NULL
, extent
);
5847 input_line_pointer
+= 2;
5848 if (*input_line_pointer
!= '.'
5849 || input_line_pointer
[1] == '\0')
5853 qual
= input_line_pointer
[1];
5854 input_line_pointer
+= 2;
5857 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
5858 &rightstart
, &rightstop
))
5864 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5865 rightstop
, truelab
, falselab
, extent
);
5867 if (truelab
== NULL
)
5872 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5873 rightstop
, truelab
, falselab
, extent
);
5877 if (input_line_pointer
!= stop
)
5878 as_bad (_("syntax error in structured control directive"));
5881 /* Handle the MRI IF pseudo-op. This may be a structured control
5882 directive, or it may be a regular assembler conditional, depending
5891 struct mri_control_info
*n
;
5893 /* A structured control directive must end with THEN with an
5894 optional qualifier. */
5895 s
= input_line_pointer
;
5896 while (! is_end_of_line
[(unsigned char) *s
]
5897 && (! flag_mri
|| *s
!= '*'))
5900 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
5903 if (s
- input_line_pointer
> 1
5907 if (s
- input_line_pointer
< 3
5908 || strncasecmp (s
- 3, "THEN", 4) != 0)
5912 as_bad (_("missing then"));
5913 ignore_rest_of_line ();
5917 /* It's a conditional. */
5922 /* Since this might be a conditional if, this pseudo-op will be
5923 called even if we are supported to be ignoring input. Double
5924 check now. Clobber *input_line_pointer so that ignore_input
5925 thinks that this is not a special pseudo-op. */
5926 c
= *input_line_pointer
;
5927 *input_line_pointer
= 0;
5928 if (ignore_input ())
5930 *input_line_pointer
= c
;
5931 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5932 ++input_line_pointer
;
5933 demand_empty_rest_of_line ();
5936 *input_line_pointer
= c
;
5938 n
= push_mri_control (mri_if
);
5940 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
5941 n
->next
, s
[1] == '.' ? s
[2] : '\0');
5944 input_line_pointer
= s
+ 3;
5946 input_line_pointer
= s
+ 1;
5950 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5951 ++input_line_pointer
;
5954 demand_empty_rest_of_line ();
5957 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5958 structured IF, associate the ELSE with the IF. Otherwise, assume
5959 it is a conditional else. */
5970 && (mri_control_stack
== NULL
5971 || mri_control_stack
->type
!= mri_if
5972 || mri_control_stack
->else_seen
))
5978 c
= *input_line_pointer
;
5979 *input_line_pointer
= 0;
5980 if (ignore_input ())
5982 *input_line_pointer
= c
;
5983 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5984 ++input_line_pointer
;
5985 demand_empty_rest_of_line ();
5988 *input_line_pointer
= c
;
5990 if (mri_control_stack
== NULL
5991 || mri_control_stack
->type
!= mri_if
5992 || mri_control_stack
->else_seen
)
5994 as_bad (_("else without matching if"));
5995 ignore_rest_of_line ();
5999 mri_control_stack
->else_seen
= 1;
6001 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->bottom
));
6004 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6008 colon (mri_control_stack
->next
);
6012 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6013 ++input_line_pointer
;
6016 demand_empty_rest_of_line ();
6019 /* Handle the MRI ENDI pseudo-op. */
6025 if (mri_control_stack
== NULL
6026 || mri_control_stack
->type
!= mri_if
)
6028 as_bad (_("endi without matching if"));
6029 ignore_rest_of_line ();
6033 /* ignore_input will not return true for ENDI, so we don't need to
6034 worry about checking it again here. */
6036 if (! mri_control_stack
->else_seen
)
6037 colon (mri_control_stack
->next
);
6038 colon (mri_control_stack
->bottom
);
6044 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6045 ++input_line_pointer
;
6048 demand_empty_rest_of_line ();
6051 /* Handle the MRI BREAK pseudo-op. */
6054 s_mri_break (extent
)
6057 struct mri_control_info
*n
;
6061 n
= mri_control_stack
;
6063 && n
->type
!= mri_for
6064 && n
->type
!= mri_repeat
6065 && n
->type
!= mri_while
)
6069 as_bad (_("break outside of structured loop"));
6070 ignore_rest_of_line ();
6074 buf
= (char *) xmalloc (20 + strlen (n
->bottom
));
6077 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6083 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6084 ++input_line_pointer
;
6087 demand_empty_rest_of_line ();
6090 /* Handle the MRI NEXT pseudo-op. */
6096 struct mri_control_info
*n
;
6100 n
= mri_control_stack
;
6102 && n
->type
!= mri_for
6103 && n
->type
!= mri_repeat
6104 && n
->type
!= mri_while
)
6108 as_bad (_("next outside of structured loop"));
6109 ignore_rest_of_line ();
6113 buf
= (char *) xmalloc (20 + strlen (n
->next
));
6116 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6122 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6123 ++input_line_pointer
;
6126 demand_empty_rest_of_line ();
6129 /* Handle the MRI FOR pseudo-op. */
6135 const char *varstart
, *varstop
;
6136 const char *initstart
, *initstop
;
6137 const char *endstart
, *endstop
;
6138 const char *bystart
, *bystop
;
6142 struct mri_control_info
*n
;
6148 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6152 varstart
= input_line_pointer
;
6154 /* Look for the '='. */
6155 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6156 && *input_line_pointer
!= '=')
6157 ++input_line_pointer
;
6158 if (*input_line_pointer
!= '=')
6160 as_bad (_("missing ="));
6161 ignore_rest_of_line ();
6165 varstop
= input_line_pointer
;
6166 if (varstop
> varstart
6167 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6170 ++input_line_pointer
;
6172 initstart
= input_line_pointer
;
6174 /* Look for TO or DOWNTO. */
6177 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6179 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6180 && ! is_part_of_name (input_line_pointer
[2]))
6182 initstop
= input_line_pointer
;
6183 input_line_pointer
+= 2;
6186 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6187 && ! is_part_of_name (input_line_pointer
[6]))
6189 initstop
= input_line_pointer
;
6191 input_line_pointer
+= 6;
6194 ++input_line_pointer
;
6196 if (initstop
== NULL
)
6198 as_bad (_("missing to or downto"));
6199 ignore_rest_of_line ();
6202 if (initstop
> initstart
6203 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6207 endstart
= input_line_pointer
;
6209 /* Look for BY or DO. */
6212 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6214 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
6215 && ! is_part_of_name (input_line_pointer
[2]))
6217 endstop
= input_line_pointer
;
6219 input_line_pointer
+= 2;
6222 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6223 && (input_line_pointer
[2] == '.'
6224 || ! is_part_of_name (input_line_pointer
[2])))
6226 endstop
= input_line_pointer
;
6227 input_line_pointer
+= 2;
6230 ++input_line_pointer
;
6232 if (endstop
== NULL
)
6234 as_bad (_("missing do"));
6235 ignore_rest_of_line ();
6238 if (endstop
> endstart
6239 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
6245 bystop
= bystart
+ 2;
6250 bystart
= input_line_pointer
;
6254 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6256 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6257 && (input_line_pointer
[2] == '.'
6258 || ! is_part_of_name (input_line_pointer
[2])))
6260 bystop
= input_line_pointer
;
6261 input_line_pointer
+= 2;
6264 ++input_line_pointer
;
6268 as_bad (_("missing do"));
6269 ignore_rest_of_line ();
6272 if (bystop
> bystart
6273 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
6277 if (*input_line_pointer
!= '.')
6281 extent
= input_line_pointer
[1];
6282 input_line_pointer
+= 2;
6285 /* We have fully parsed the FOR operands. Now build the loop. */
6287 n
= push_mri_control (mri_for
);
6289 buf
= (char *) xmalloc (50 + (input_line_pointer
- varstart
));
6300 memcpy (s
, initstart
, initstop
- initstart
);
6301 s
+= initstop
- initstart
;
6303 memcpy (s
, varstart
, varstop
- varstart
);
6304 s
+= varstop
- varstart
;
6318 memcpy (s
, endstart
, endstop
- endstart
);
6319 s
+= endstop
- endstart
;
6321 memcpy (s
, varstart
, varstop
- varstart
);
6322 s
+= varstop
- varstart
;
6330 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
6332 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
6335 /* Put together the add or sub instruction used by ENDF. */
6345 memcpy (s
, bystart
, bystop
- bystart
);
6346 s
+= bystop
- bystart
;
6348 memcpy (s
, varstart
, varstop
- varstart
);
6349 s
+= varstop
- varstart
;
6355 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6356 ++input_line_pointer
;
6359 demand_empty_rest_of_line ();
6362 /* Handle the MRI ENDF pseudo-op. */
6368 if (mri_control_stack
== NULL
6369 || mri_control_stack
->type
!= mri_for
)
6371 as_bad (_("endf without for"));
6372 ignore_rest_of_line ();
6376 colon (mri_control_stack
->next
);
6378 md_assemble (mri_control_stack
->incr
);
6380 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
6381 md_assemble (mri_control_stack
->incr
);
6383 free (mri_control_stack
->incr
);
6385 colon (mri_control_stack
->bottom
);
6391 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6392 ++input_line_pointer
;
6395 demand_empty_rest_of_line ();
6398 /* Handle the MRI REPEAT pseudo-op. */
6401 s_mri_repeat (ignore
)
6404 struct mri_control_info
*n
;
6406 n
= push_mri_control (mri_repeat
);
6410 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6411 ++input_line_pointer
;
6413 demand_empty_rest_of_line ();
6416 /* Handle the MRI UNTIL pseudo-op. */
6424 if (mri_control_stack
== NULL
6425 || mri_control_stack
->type
!= mri_repeat
)
6427 as_bad (_("until without repeat"));
6428 ignore_rest_of_line ();
6432 colon (mri_control_stack
->next
);
6434 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
6437 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
6438 mri_control_stack
->top
, '\0');
6440 colon (mri_control_stack
->bottom
);
6442 input_line_pointer
= s
;
6448 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6449 ++input_line_pointer
;
6452 demand_empty_rest_of_line ();
6455 /* Handle the MRI WHILE pseudo-op. */
6463 struct mri_control_info
*n
;
6465 s
= input_line_pointer
;
6466 while (! is_end_of_line
[(unsigned char) *s
]
6467 && (! flag_mri
|| *s
!= '*'))
6470 while (*s
== ' ' || *s
== '\t')
6472 if (s
- input_line_pointer
> 1
6475 if (s
- input_line_pointer
< 2
6476 || strncasecmp (s
- 1, "DO", 2) != 0)
6478 as_bad (_("missing do"));
6479 ignore_rest_of_line ();
6483 n
= push_mri_control (mri_while
);
6487 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
6488 s
[1] == '.' ? s
[2] : '\0');
6490 input_line_pointer
= s
+ 1;
6491 if (*input_line_pointer
== '.')
6492 input_line_pointer
+= 2;
6496 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6497 ++input_line_pointer
;
6500 demand_empty_rest_of_line ();
6503 /* Handle the MRI ENDW pseudo-op. */
6511 if (mri_control_stack
== NULL
6512 || mri_control_stack
->type
!= mri_while
)
6514 as_bad (_("endw without while"));
6515 ignore_rest_of_line ();
6519 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->next
));
6520 sprintf (buf
, "bra %s", mri_control_stack
->next
);
6524 colon (mri_control_stack
->bottom
);
6530 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6531 ++input_line_pointer
;
6534 demand_empty_rest_of_line ();
6539 * Invocation line includes a switch not recognized by the base assembler.
6540 * See if it's a processor-specific option. These are:
6542 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6543 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6544 * Select the architecture. Instructions or features not
6545 * supported by the selected architecture cause fatal
6546 * errors. More than one may be specified. The default is
6547 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6548 * for -m68000, and -m68882 is a synonym for -m68881.
6549 * -[A]m[c]no-68851, -[A]m[c]no-68881
6550 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6551 * so don't use or document it, but that's the way the parsing
6554 * -pic Indicates PIC.
6555 * -k Indicates PIC. (Sun 3 only.)
6558 * Permit `|' to be used in expressions.
6563 CONST
char *md_shortopts
= "lSA:m:kQ:V";
6565 CONST
char *md_shortopts
= "lSA:m:k";
6568 struct option md_longopts
[] = {
6569 #define OPTION_PIC (OPTION_MD_BASE)
6570 {"pic", no_argument
, NULL
, OPTION_PIC
},
6571 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6572 {"register-prefix-optional", no_argument
, NULL
,
6573 OPTION_REGISTER_PREFIX_OPTIONAL
},
6574 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6575 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
6576 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6577 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
6578 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6579 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
6580 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6581 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
6582 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6583 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
6584 {NULL
, no_argument
, NULL
, 0}
6586 size_t md_longopts_size
= sizeof(md_longopts
);
6589 md_parse_option (c
, arg
)
6595 case 'l': /* -l means keep external to 2 bit offset
6596 rather than 16 bit one */
6597 flag_short_refs
= 1;
6600 case 'S': /* -S means that jbsr's always turn into
6602 flag_long_jumps
= 1;
6608 /* intentional fall-through */
6611 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
6615 const char *oarg
= arg
;
6621 if (arg
[0] == 'c' && arg
[1] == '6')
6624 for (i
= 0; i
< n_archs
; i
++)
6625 if (!strcmp (arg
, archs
[i
].name
))
6630 as_bad (_("unrecognized option `%s'"), oarg
);
6633 arch
= archs
[i
].arch
;
6636 else if (arch
== m68851
)
6645 if (arg
[0] == 'c' && arg
[1] == '6')
6648 for (i
= 0; i
< n_archs
; i
++)
6649 if (!strcmp (arg
, archs
[i
].name
))
6651 unsigned long arch
= archs
[i
].arch
;
6652 if (cpu_of_arch (arch
))
6653 /* It's a cpu spec. */
6655 current_architecture
&= ~m68000up
;
6656 current_architecture
|= arch
;
6658 else if (arch
== m68881
)
6660 current_architecture
|= m68881
;
6663 else if (arch
== m68851
)
6665 current_architecture
|= m68851
;
6675 as_bad (_("unrecognized architecture specification `%s'"), arg
);
6684 break; /* -pic, Position Independent Code */
6686 case OPTION_REGISTER_PREFIX_OPTIONAL
:
6687 flag_reg_prefix_optional
= 1;
6688 reg_prefix_optional_seen
= 1;
6691 /* -V: SVR4 argument to print version ID. */
6693 print_version_id ();
6696 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6697 should be emitted or not. FIXME: Not implemented. */
6701 case OPTION_BITWISE_OR
:
6706 n
= (char *) xmalloc (strlen (m68k_comment_chars
) + 1);
6708 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
6712 m68k_comment_chars
= n
;
6716 case OPTION_BASE_SIZE_DEFAULT_16
:
6717 m68k_index_width_default
= SIZE_WORD
;
6720 case OPTION_BASE_SIZE_DEFAULT_32
:
6721 m68k_index_width_default
= SIZE_LONG
;
6724 case OPTION_DISP_SIZE_DEFAULT_16
:
6726 m68k_rel32_from_cmdline
= 1;
6729 case OPTION_DISP_SIZE_DEFAULT_32
:
6731 m68k_rel32_from_cmdline
= 1;
6742 md_show_usage (stream
)
6745 fprintf(stream
, _("\
6747 -l use 1 word for refs to undefined symbols [default 2]\n\
6748 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6749 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6750 | -mcpu32 | -m5200\n\
6751 specify variant of 680X0 architecture [default 68020]\n\
6752 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6753 target has/lacks floating-point coprocessor\n\
6754 [default yes for 68020, 68030, and cpu32]\n"));
6755 fprintf(stream
, _("\
6756 -m68851 | -mno-68851\n\
6757 target has/lacks memory-management unit coprocessor\n\
6758 [default yes for 68020 and up]\n\
6759 -pic, -k generate position independent code\n\
6760 -S turn jbsr into jsr\n\
6761 --register-prefix-optional\n\
6762 recognize register names without prefix character\n\
6763 --bitwise-or do not treat `|' as a comment character\n"));
6764 fprintf (stream
, _("\
6765 --base-size-default-16 base reg without size is 16 bits\n\
6766 --base-size-default-32 base reg without size is 32 bits (default)\n\
6767 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6768 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6773 /* TEST2: Test md_assemble() */
6774 /* Warning, this routine probably doesn't work anymore */
6778 struct m68k_it the_ins
;
6786 if (!gets (buf
) || !*buf
)
6788 if (buf
[0] == '|' || buf
[1] == '.')
6790 for (cp
= buf
; *cp
; cp
++)
6795 memset (&the_ins
, '\0', sizeof (the_ins
));
6796 m68k_ip (&the_ins
, buf
);
6799 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
6803 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
6804 for (n
= 0; n
< the_ins
.numo
; n
++)
6805 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
6807 print_the_insn (&the_ins
.opcode
[0], stdout
);
6808 (void) putchar ('\n');
6810 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
6812 if (the_ins
.operands
[n
].error
)
6814 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
6817 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
, the_ins
.operands
[n
].reg
);
6818 if (the_ins
.operands
[n
].b_const
)
6819 printf ("Constant: '%.*s', ", 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
, the_ins
.operands
[n
].b_const
);
6820 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
, the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
6821 if (the_ins
.operands
[n
].b_iadd
)
6822 printf ("Iadd: '%.*s',", 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
, the_ins
.operands
[n
].b_iadd
);
6823 (void) putchar ('\n');
6835 while (*str
&& *str
!= ' ')
6837 if (str
[-1] == ':' || str
[1] == '=')
6844 /* Possible states for relaxation:
6846 0 0 branch offset byte (bra, etc)
6850 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6854 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6861 /* We have no need to default values of symbols. */
6865 md_undefined_symbol (name
)
6871 /* Round up a section size to the appropriate boundary. */
6873 md_section_align (segment
, size
)
6878 #ifdef BFD_ASSEMBLER
6879 /* For a.out, force the section size to be aligned. If we don't do
6880 this, BFD will align it for us, but it will not write out the
6881 final bytes of the section. This may be a bug in BFD, but it is
6882 easier to fix it here since that is how the other a.out targets
6886 align
= bfd_get_section_alignment (stdoutput
, segment
);
6887 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
6894 /* Exactly what point is a PC-relative offset relative TO?
6895 On the 68k, it is relative to the address of the first extension
6896 word. The difference between the addresses of the offset and the
6897 first extension word is stored in fx_pcrel_adjust. */
6899 md_pcrel_from (fixP
)
6904 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6906 adjust
= fixP
->fx_pcrel_adjust
;
6909 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
6912 #ifndef BFD_ASSEMBLER
6917 tc_coff_symbol_emit_hook (ignore
)
6923 tc_coff_sizemachdep (frag
)
6926 switch (frag
->fr_subtype
& 0x3)
6943 /* end of tc-m68k.c */