1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars
= "|#";
47 const char *m68k_comment_chars
= "|";
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars
[] = "#*";
59 const char line_separator_chars
[] = ";";
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS
[] = "eE";
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
67 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
79 static int flag_short_refs
; /* -l option. */
80 static int flag_long_jumps
; /* -S option. */
81 static int flag_keep_pcrel
; /* --pcrel option. */
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
86 int flag_reg_prefix_optional
;
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen
;
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum
= COP1
;
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd
;
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick
= 1;
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
106 static int m68k_rel32
= 1;
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline
;
111 /* The default width to use for an index register when using a base
113 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
120 struct label_line
*next
;
127 /* The list of labels. */
129 static struct label_line
*labels
;
131 /* The current label. */
133 static struct label_line
*current_label
;
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode
const ** m68k_sorted_opcodes
;
138 /* Its an arbitrary name: This means I don't approve of it.
140 static struct obstack robyn
;
144 const char *m_operands
;
145 unsigned long m_opcode
;
149 struct m68k_incant
*m_next
;
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
155 static const enum m68k_register m68000_ctrl
[] = { 0 };
156 static const enum m68k_register m68010_ctrl
[] = {
160 static const enum m68k_register m68020_ctrl
[] = {
161 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
164 static const enum m68k_register m68040_ctrl
[] = {
165 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
166 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
169 static const enum m68k_register m68060_ctrl
[] = {
170 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
171 USP
, VBR
, URP
, SRP
, PCR
,
174 static const enum m68k_register mcf_ctrl
[] = {
175 CACR
, TC
, ACR0
, ACR1
, ACR2
, ACR3
, VBR
, ROMBAR
,
176 RAMBAR0
, RAMBAR1
, MBAR
,
179 static const enum m68k_register mcf5208_ctrl
[] = {
180 CACR
, ACR0
, ACR1
, VBR
, RAMBAR1
,
183 static const enum m68k_register mcf5210a_ctrl
[] = {
184 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR
, MBAR
,
187 static const enum m68k_register mcf5213_ctrl
[] = {
188 VBR
, RAMBAR
, FLASHBAR
,
191 static const enum m68k_register mcf5216_ctrl
[] = {
192 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
,
195 static const enum m68k_register mcf52235_ctrl
[] = {
196 VBR
, FLASHBAR
, RAMBAR
,
199 static const enum m68k_register mcf5225_ctrl
[] = {
200 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, MBAR
,
203 static const enum m68k_register mcf5235_ctrl
[] = {
204 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
207 static const enum m68k_register mcf5249_ctrl
[] = {
208 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, MBAR
, MBAR2
,
211 static const enum m68k_register mcf5250_ctrl
[] = {
215 static const enum m68k_register mcf5271_ctrl
[] = {
216 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
219 static const enum m68k_register mcf5272_ctrl
[] = {
220 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR
, MBAR
,
223 static const enum m68k_register mcf5275_ctrl
[] = {
224 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
227 static const enum m68k_register mcf5282_ctrl
[] = {
228 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
,
231 static const enum m68k_register mcf5329_ctrl
[] = {
232 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
235 static const enum m68k_register mcf5373_ctrl
[] = {
236 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
,
239 static const enum m68k_register mcfv4e_ctrl
[] = {
240 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
241 VBR
, PC
, ROMBAR0
, ROMBAR1
, RAMBAR0
, RAMBAR1
,
243 MPCR
/* Multiprocessor Control register */,
244 EDRAMBAR
/* Embedded DRAM Base Address Register */,
245 /* Permutation control registers. */
246 PCR1U0
, PCR1L0
, PCR1U1
, PCR1L1
, PCR2U0
, PCR2L0
, PCR2U1
, PCR2L1
,
247 PCR3U0
, PCR3L0
, PCR3U1
, PCR3L1
,
249 TC
/* ASID */, BUSCR
/* MMUBAR */,
250 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
251 MBAR1
/* MBAR */, MBAR2
/* SECMBAR */, MBAR0
/* SECMBAR */,
252 ROMBAR
/* ROMBAR0 */,
255 static const enum m68k_register mcf5475_ctrl
[] = {
256 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
257 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
259 TC
/* ASID */, BUSCR
/* MMUBAR */,
260 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
261 MBAR1
/* MBAR */, ROMBAR
/* ROMBAR0 */,
264 static const enum m68k_register mcf5485_ctrl
[] = {
265 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
266 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
268 TC
/* ASID */, BUSCR
/* MMUBAR */,
269 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
270 MBAR1
/* MBAR */, ROMBAR
/* ROMBAR0 */,
273 static const enum m68k_register fido_ctrl
[] = {
274 SFC
, DFC
, USP
, VBR
, CAC
, MBB
,
277 #define cpu32_ctrl m68010_ctrl
279 static const enum m68k_register
*control_regs
;
281 /* Internal form of a 68020 instruction. */
285 const char *args
; /* List of opcode info. */
288 int numo
; /* Number of shorts in opcode. */
291 struct m68k_op operands
[6];
293 int nexp
; /* Number of exprs in use. */
294 struct m68k_exp exprs
[4];
296 int nfrag
; /* Number of frags we have to produce. */
299 int fragoff
; /* Where in the current opcode the frag ends. */
306 int nrel
; /* Num of reloc strucs in use. */
313 /* In a pc relative address the difference between the address
314 of the offset and the address that the offset is relative
315 to. This depends on the addressing mode. Basically this
316 is the value to put in the offset field to address the
317 first byte of the offset, without regarding the special
318 significance of some values (in the branch instruction, for
322 /* Whether this expression needs special pic relocation, and if
324 enum pic_relocation pic_reloc
;
327 reloc
[5]; /* Five is enough??? */
330 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
331 #define float_of_arch(x) ((x) & mfloat)
332 #define mmu_of_arch(x) ((x) & mmmu)
333 #define arch_coldfire_p(x) ((x) & mcfisa_a)
334 #define arch_coldfire_fpu(x) ((x) & cfloat)
336 /* Macros for determining if cpu supports a specific addressing mode. */
337 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
339 static struct m68k_it the_ins
; /* The instruction being assembled. */
341 #define op(ex) ((ex)->exp.X_op)
342 #define adds(ex) ((ex)->exp.X_add_symbol)
343 #define subs(ex) ((ex)->exp.X_op_symbol)
344 #define offs(ex) ((ex)->exp.X_add_number)
346 /* Macros for adding things to the m68k_it struct. */
347 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
349 /* Like addword, but goes BEFORE general operands. */
352 insop (int w
, const struct m68k_incant
*opcode
)
355 for (z
= the_ins
.numo
; z
> opcode
->m_codenum
; --z
)
356 the_ins
.opcode
[z
] = the_ins
.opcode
[z
- 1];
357 for (z
= 0; z
< the_ins
.nrel
; z
++)
358 the_ins
.reloc
[z
].n
+= 2;
359 for (z
= 0; z
< the_ins
.nfrag
; z
++)
360 the_ins
.fragb
[z
].fragoff
++;
361 the_ins
.opcode
[opcode
->m_codenum
] = w
;
365 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
368 add_fix (int width
, struct m68k_exp
*exp
, int pc_rel
, int pc_fix
)
370 the_ins
.reloc
[the_ins
.nrel
].n
= (width
== 'B' || width
== '3'
371 ? the_ins
.numo
* 2 - 1
373 ? the_ins
.numo
* 2 + 1
374 : the_ins
.numo
* 2));
375 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
376 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
377 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
379 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
381 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
384 /* Cause an extra frag to be generated here, inserting up to 10 bytes
385 (that value is chosen in the frag_var call in md_assemble). TYPE
386 is the subtype of the frag to be generated; its primary type is
387 rs_machine_dependent.
389 The TYPE parameter is also used by md_convert_frag_1 and
390 md_estimate_size_before_relax. The appropriate type of fixup will
391 be emitted by md_convert_frag_1.
393 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
395 add_frag (symbolS
*add
, offsetT off
, int type
)
397 the_ins
.fragb
[the_ins
.nfrag
].fragoff
= the_ins
.numo
;
398 the_ins
.fragb
[the_ins
.nfrag
].fadd
= add
;
399 the_ins
.fragb
[the_ins
.nfrag
].foff
= off
;
400 the_ins
.fragb
[the_ins
.nfrag
++].fragty
= type
;
404 (op (ex) != O_constant && op (ex) != O_big)
406 static char *crack_operand (char *str
, struct m68k_op
*opP
);
407 static int get_num (struct m68k_exp
*exp
, int ok
);
408 static int reverse_16_bits (int in
);
409 static int reverse_8_bits (int in
);
410 static void install_gen_operand (int mode
, int val
);
411 static void install_operand (int mode
, int val
);
412 static void s_bss (int);
413 static void s_data1 (int);
414 static void s_data2 (int);
415 static void s_even (int);
416 static void s_proc (int);
417 static void s_chip (int);
418 static void s_fopt (int);
419 static void s_opt (int);
420 static void s_reg (int);
421 static void s_restore (int);
422 static void s_save (int);
423 static void s_mri_if (int);
424 static void s_mri_else (int);
425 static void s_mri_endi (int);
426 static void s_mri_break (int);
427 static void s_mri_next (int);
428 static void s_mri_for (int);
429 static void s_mri_endf (int);
430 static void s_mri_repeat (int);
431 static void s_mri_until (int);
432 static void s_mri_while (int);
433 static void s_mri_endw (int);
434 static void s_m68k_cpu (int);
435 static void s_m68k_arch (int);
439 unsigned long arch
; /* Architecture features. */
440 const enum m68k_register
*control_regs
; /* Control regs on chip */
441 const char *name
; /* Name */
442 int alias
; /* Alias for a cannonical name. If 1, then
443 succeeds canonical name, if -1 then
444 succeeds canonical name, if <-1 ||>1 this is a
445 deprecated name, and the next/previous name
449 /* We hold flags for features explicitly enabled and explicitly
451 static int current_architecture
;
452 static int not_current_architecture
;
453 static const struct m68k_cpu
*selected_arch
;
454 static const struct m68k_cpu
*selected_cpu
;
455 static int initialized
;
457 /* Architecture models. */
458 static const struct m68k_cpu m68k_archs
[] =
460 {m68000
, m68000_ctrl
, "68000", 0},
461 {m68010
, m68010_ctrl
, "68010", 0},
462 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
463 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
464 {m68040
, m68040_ctrl
, "68040", 0},
465 {m68060
, m68060_ctrl
, "68060", 0},
466 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
467 {fido_a
, fido_ctrl
, "fidoa", 0},
468 {mcfisa_a
|mcfhwdiv
, NULL
, "isaa", 0},
469 {mcfisa_a
|mcfhwdiv
|mcfisa_aa
|mcfusp
, NULL
, "isaaplus", 0},
470 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfusp
, NULL
, "isab", 0},
471 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfmac
|mcfusp
, mcf_ctrl
, "cfv4", 0},
472 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "cfv4e", 0},
476 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
478 static const struct m68k_cpu m68k_extensions
[] =
480 {m68851
, NULL
, "68851", -1},
481 {m68881
, NULL
, "68881", -1},
482 {m68881
, NULL
, "68882", -1},
484 {cfloat
|m68881
, NULL
, "float", 0},
486 {mcfhwdiv
, NULL
, "div", 1},
487 {mcfusp
, NULL
, "usp", 1},
488 {mcfmac
, NULL
, "mac", 1},
489 {mcfemac
, NULL
, "emac", 1},
495 static const struct m68k_cpu m68k_cpus
[] =
497 {m68000
, m68000_ctrl
, "68000", 0},
498 {m68000
, m68000_ctrl
, "68ec000", 1},
499 {m68000
, m68000_ctrl
, "68hc000", 1},
500 {m68000
, m68000_ctrl
, "68hc001", 1},
501 {m68000
, m68000_ctrl
, "68008", 1},
502 {m68000
, m68000_ctrl
, "68302", 1},
503 {m68000
, m68000_ctrl
, "68306", 1},
504 {m68000
, m68000_ctrl
, "68307", 1},
505 {m68000
, m68000_ctrl
, "68322", 1},
506 {m68000
, m68000_ctrl
, "68356", 1},
507 {m68010
, m68010_ctrl
, "68010", 0},
508 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
509 {m68020
|m68881
|m68851
, m68020_ctrl
, "68k", 1},
510 {m68020
|m68881
|m68851
, m68020_ctrl
, "68ec020", 1},
511 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
512 {m68030
|m68881
|m68851
, m68020_ctrl
, "68ec030", 1},
513 {m68040
, m68040_ctrl
, "68040", 0},
514 {m68040
, m68040_ctrl
, "68ec040", 1},
515 {m68060
, m68060_ctrl
, "68060", 0},
516 {m68060
, m68060_ctrl
, "68ec060", 1},
518 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
519 {cpu32
|m68881
, cpu32_ctrl
, "68330", 1},
520 {cpu32
|m68881
, cpu32_ctrl
, "68331", 1},
521 {cpu32
|m68881
, cpu32_ctrl
, "68332", 1},
522 {cpu32
|m68881
, cpu32_ctrl
, "68333", 1},
523 {cpu32
|m68881
, cpu32_ctrl
, "68334", 1},
524 {cpu32
|m68881
, cpu32_ctrl
, "68336", 1},
525 {cpu32
|m68881
, cpu32_ctrl
, "68340", 1},
526 {cpu32
|m68881
, cpu32_ctrl
, "68341", 1},
527 {cpu32
|m68881
, cpu32_ctrl
, "68349", 1},
528 {cpu32
|m68881
, cpu32_ctrl
, "68360", 1},
530 {mcfisa_a
, mcf_ctrl
, "5200", 0},
531 {mcfisa_a
, mcf_ctrl
, "5202", 1},
532 {mcfisa_a
, mcf_ctrl
, "5204", 1},
533 {mcfisa_a
, mcf_ctrl
, "5206", 1},
535 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf_ctrl
, "5206e", 0},
537 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5207", -1},
538 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5208", 0},
540 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5210a", 0},
541 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5211a", 1},
543 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5211", -1},
544 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5212", -1},
545 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5213", 0},
547 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5214", -1},
548 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5216", 0},
549 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "521x", 2},
551 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52230", -1},
552 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52233", -1},
553 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52234", -1},
554 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52235", 0},
556 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5224", -1},
557 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5225", 0},
559 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5232", -1},
560 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5233", -1},
561 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5234", -1},
562 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5235", -1},
563 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "523x", 0},
565 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5249_ctrl
, "5249", 0},
566 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5250_ctrl
, "5250", 0},
568 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5270", -1},
569 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5271", 0},
571 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5272_ctrl
, "5272", 0},
573 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5274", -1},
574 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5275", 0},
576 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5280", -1},
577 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5281", -1},
578 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5282", -1},
579 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "528x", 0},
581 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf_ctrl
, "5307", 0},
583 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5327", -1},
584 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5328", -1},
585 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5329", -1},
586 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "532x", 0},
588 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5372", -1},
589 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5373", -1},
590 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "537x", 0},
592 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfmac
, mcf_ctrl
, "5407",0},
594 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5470", -1},
595 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5471", -1},
596 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5472", -1},
597 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5473", -1},
598 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5474", -1},
599 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5475", -1},
600 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "547x", 0},
602 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5480", -1},
603 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5481", -1},
604 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5482", -1},
605 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5483", -1},
606 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5484", -1},
607 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5485", -1},
608 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "548x", 0},
610 {fido_a
, fido_ctrl
, "fidoa", 0},
611 {fido_a
, fido_ctrl
, "fido", 1},
616 static const struct m68k_cpu
*m68k_lookup_cpu
617 (const char *, const struct m68k_cpu
*, int, int *);
618 static int m68k_set_arch (const char *, int, int);
619 static int m68k_set_cpu (const char *, int, int);
620 static int m68k_set_extension (const char *, int, int);
621 static void m68k_init_arch (void);
623 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
624 architecture and we have a lot of relaxation modes. */
626 /* Macros used in the relaxation code. */
627 #define TAB(x,y) (((x) << 2) + (y))
628 #define TABTYPE(x) ((x) >> 2)
630 /* Relaxation states. */
636 /* Here are all the relaxation modes we support. First we can relax ordinary
637 branches. On 68020 and higher and on CPU32 all branch instructions take
638 three forms, so on these CPUs all branches always remain as such. When we
639 have to expand to the LONG form on a 68000, though, we substitute an
640 absolute jump instead. This is a direct replacement for unconditional
641 branches and a branch over a jump for conditional branches. However, if the
642 user requires PIC and disables this with --pcrel, we can only relax between
643 BYTE and SHORT forms, punting if that isn't enough. This gives us four
644 different relaxation modes for branches: */
646 #define BRANCHBWL 0 /* Branch byte, word, or long. */
647 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
648 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
649 #define BRANCHBW 3 /* Branch byte or word. */
651 /* We also relax coprocessor branches and DBcc's. All CPUs that support
652 coprocessor branches support them in word and long forms, so we have only
653 one relaxation mode for them. DBcc's are word only on all CPUs. We can
654 relax them to the LONG form with a branch-around sequence. This sequence
655 can use a long branch (if available) or an absolute jump (if acceptable).
656 This gives us two relaxation modes. If long branches are not available and
657 absolute jumps are not acceptable, we don't relax DBcc's. */
659 #define FBRANCH 4 /* Coprocessor branch. */
660 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
661 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
663 /* That's all for instruction relaxation. However, we also relax PC-relative
664 operands. Specifically, we have three operand relaxation modes. On the
665 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
666 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
667 two. Also PC+displacement+index operands in their simple form (with a non-
668 suppressed index without memory indirection) are supported on all CPUs, but
669 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
670 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
671 form of the PC+displacement+index operand. Finally, some absolute operands
672 can be relaxed down to 16-bit PC-relative. */
674 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
675 #define PCINDEX 8 /* PC + displacement + index. */
676 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
678 /* Note that calls to frag_var need to specify the maximum expansion
679 needed; this is currently 10 bytes for DBCC. */
682 How far Forward this mode will reach:
683 How far Backward this mode will reach:
684 How many bytes this mode will add to the size of the frag
685 Which mode to go to if the offset won't fit in this one
687 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
688 relax_typeS md_relax_table
[] =
690 { 127, -128, 0, TAB (BRANCHBWL
, SHORT
) },
691 { 32767, -32768, 2, TAB (BRANCHBWL
, LONG
) },
695 { 127, -128, 0, TAB (BRABSJUNC
, SHORT
) },
696 { 32767, -32768, 2, TAB (BRABSJUNC
, LONG
) },
700 { 127, -128, 0, TAB (BRABSJCOND
, SHORT
) },
701 { 32767, -32768, 2, TAB (BRABSJCOND
, LONG
) },
705 { 127, -128, 0, TAB (BRANCHBW
, SHORT
) },
710 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
711 { 32767, -32768, 2, TAB (FBRANCH
, LONG
) },
715 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
716 { 32767, -32768, 2, TAB (DBCCLBR
, LONG
) },
720 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
721 { 32767, -32768, 2, TAB (DBCCABSJ
, LONG
) },
725 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
726 { 32767, -32768, 2, TAB (PCREL1632
, LONG
) },
730 { 125, -130, 0, TAB (PCINDEX
, SHORT
) },
731 { 32765, -32770, 2, TAB (PCINDEX
, LONG
) },
735 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
736 { 32767, -32768, 2, TAB (ABSTOPCREL
, LONG
) },
741 /* These are the machine dependent pseudo-ops. These are included so
742 the assembler can work on the output from the SUN C compiler, which
745 /* This table describes all the machine specific pseudo-ops the assembler
746 has to support. The fields are:
747 pseudo-op name without dot
748 function to call to execute this pseudo-op
749 Integer arg to pass to the function. */
750 const pseudo_typeS md_pseudo_table
[] =
752 {"data1", s_data1
, 0},
753 {"data2", s_data2
, 0},
756 {"skip", s_space
, 0},
758 #if defined (TE_SUN3) || defined (OBJ_ELF)
759 {"align", s_align_bytes
, 0},
762 {"swbeg", s_ignore
, 0},
764 {"extend", float_cons
, 'x'},
765 {"ldouble", float_cons
, 'x'},
767 {"arch", s_m68k_arch
, 0},
768 {"cpu", s_m68k_cpu
, 0},
770 /* The following pseudo-ops are supported for MRI compatibility. */
772 {"comline", s_space
, 1},
774 {"mask2", s_ignore
, 0},
777 {"restore", s_restore
, 0},
781 {"if.b", s_mri_if
, 'b'},
782 {"if.w", s_mri_if
, 'w'},
783 {"if.l", s_mri_if
, 'l'},
784 {"else", s_mri_else
, 0},
785 {"else.s", s_mri_else
, 's'},
786 {"else.l", s_mri_else
, 'l'},
787 {"endi", s_mri_endi
, 0},
788 {"break", s_mri_break
, 0},
789 {"break.s", s_mri_break
, 's'},
790 {"break.l", s_mri_break
, 'l'},
791 {"next", s_mri_next
, 0},
792 {"next.s", s_mri_next
, 's'},
793 {"next.l", s_mri_next
, 'l'},
794 {"for", s_mri_for
, 0},
795 {"for.b", s_mri_for
, 'b'},
796 {"for.w", s_mri_for
, 'w'},
797 {"for.l", s_mri_for
, 'l'},
798 {"endf", s_mri_endf
, 0},
799 {"repeat", s_mri_repeat
, 0},
800 {"until", s_mri_until
, 0},
801 {"until.b", s_mri_until
, 'b'},
802 {"until.w", s_mri_until
, 'w'},
803 {"until.l", s_mri_until
, 'l'},
804 {"while", s_mri_while
, 0},
805 {"while.b", s_mri_while
, 'b'},
806 {"while.w", s_mri_while
, 'w'},
807 {"while.l", s_mri_while
, 'l'},
808 {"endw", s_mri_endw
, 0},
813 /* The mote pseudo ops are put into the opcode table, since they
814 don't start with a . they look like opcodes to gas. */
816 const pseudo_typeS mote_pseudo_table
[] =
829 {"xdef", s_globl
, 0},
831 {"align", s_align_bytes
, 0},
833 {"align", s_align_ptwo
, 0},
836 {"sect", obj_coff_section
, 0},
837 {"section", obj_coff_section
, 0},
842 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
843 gives identical results to a 32-bit host. */
844 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
845 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
847 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
848 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
849 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
850 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
852 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
853 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
854 #define islong(x) (1)
856 static char notend_table
[256];
857 static char alt_notend_table
[256];
859 (! (notend_table[(unsigned char) *s] \
861 && alt_notend_table[(unsigned char) s[1]])))
865 /* Return zero if the reference to SYMBOL from within the same segment may
868 /* On an ELF system, we can't relax an externally visible symbol,
869 because it may be overridden by a shared library. However, if
870 TARGET_OS is "elf", then we presume that we are assembling for an
871 embedded system, in which case we don't have to worry about shared
872 libraries, and we can relax any external sym. */
874 #define relaxable_symbol(symbol) \
875 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
876 || S_IS_WEAK (symbol)))
878 /* Compute the relocation code for a fixup of SIZE bytes, using pc
879 relative relocation if PCREL is non-zero. PIC says whether a special
880 pic relocation was requested. */
882 static bfd_reloc_code_real_type
883 get_reloc_code (int size
, int pcrel
, enum pic_relocation pic
)
891 return BFD_RELOC_8_GOT_PCREL
;
893 return BFD_RELOC_16_GOT_PCREL
;
895 return BFD_RELOC_32_GOT_PCREL
;
903 return BFD_RELOC_8_GOTOFF
;
905 return BFD_RELOC_16_GOTOFF
;
907 return BFD_RELOC_32_GOTOFF
;
915 return BFD_RELOC_8_PLT_PCREL
;
917 return BFD_RELOC_16_PLT_PCREL
;
919 return BFD_RELOC_32_PLT_PCREL
;
927 return BFD_RELOC_8_PLTOFF
;
929 return BFD_RELOC_16_PLTOFF
;
931 return BFD_RELOC_32_PLTOFF
;
941 return BFD_RELOC_8_PCREL
;
943 return BFD_RELOC_16_PCREL
;
945 return BFD_RELOC_32_PCREL
;
965 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
967 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
972 as_bad (_("Can not do %d byte relocation"), size
);
974 as_bad (_("Can not do %d byte pic relocation"), size
);
977 return BFD_RELOC_NONE
;
980 /* Here we decide which fixups can be adjusted to make them relative
981 to the beginning of the section instead of the symbol. Basically
982 we need to make sure that the dynamic relocations are done
983 correctly, so in some cases we force the original symbol to be
986 tc_m68k_fix_adjustable (fixS
*fixP
)
988 /* Adjust_reloc_syms doesn't know about the GOT. */
989 switch (fixP
->fx_r_type
)
991 case BFD_RELOC_8_GOT_PCREL
:
992 case BFD_RELOC_16_GOT_PCREL
:
993 case BFD_RELOC_32_GOT_PCREL
:
994 case BFD_RELOC_8_GOTOFF
:
995 case BFD_RELOC_16_GOTOFF
:
996 case BFD_RELOC_32_GOTOFF
:
997 case BFD_RELOC_8_PLT_PCREL
:
998 case BFD_RELOC_16_PLT_PCREL
:
999 case BFD_RELOC_32_PLT_PCREL
:
1000 case BFD_RELOC_8_PLTOFF
:
1001 case BFD_RELOC_16_PLTOFF
:
1002 case BFD_RELOC_32_PLTOFF
:
1005 case BFD_RELOC_VTABLE_INHERIT
:
1006 case BFD_RELOC_VTABLE_ENTRY
:
1014 #else /* !OBJ_ELF */
1016 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1018 #define relaxable_symbol(symbol) 1
1020 #endif /* OBJ_ELF */
1023 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
1026 bfd_reloc_code_real_type code
;
1028 /* If the tcbit is set, then this was a fixup of a negative value
1029 that was never resolved. We do not have a reloc to handle this,
1030 so just return. We assume that other code will have detected this
1031 situation and produced a helpful error message, so we just tell the
1032 user that the reloc cannot be produced. */
1036 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1037 _("Unable to produce reloc against symbol '%s'"),
1038 S_GET_NAME (fixp
->fx_addsy
));
1042 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
1044 code
= fixp
->fx_r_type
;
1046 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1047 that fixup_segment converted a non-PC relative reloc into a
1048 PC relative reloc. In such a case, we need to convert the
1055 code
= BFD_RELOC_8_PCREL
;
1058 code
= BFD_RELOC_16_PCREL
;
1061 code
= BFD_RELOC_32_PCREL
;
1063 case BFD_RELOC_8_PCREL
:
1064 case BFD_RELOC_16_PCREL
:
1065 case BFD_RELOC_32_PCREL
:
1066 case BFD_RELOC_8_GOT_PCREL
:
1067 case BFD_RELOC_16_GOT_PCREL
:
1068 case BFD_RELOC_32_GOT_PCREL
:
1069 case BFD_RELOC_8_GOTOFF
:
1070 case BFD_RELOC_16_GOTOFF
:
1071 case BFD_RELOC_32_GOTOFF
:
1072 case BFD_RELOC_8_PLT_PCREL
:
1073 case BFD_RELOC_16_PLT_PCREL
:
1074 case BFD_RELOC_32_PLT_PCREL
:
1075 case BFD_RELOC_8_PLTOFF
:
1076 case BFD_RELOC_16_PLTOFF
:
1077 case BFD_RELOC_32_PLTOFF
:
1080 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1081 _("Cannot make %s relocation PC relative"),
1082 bfd_get_reloc_code_name (code
));
1088 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1089 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
1091 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1092 MAP (1, 0, BFD_RELOC_8
);
1093 MAP (2, 0, BFD_RELOC_16
);
1094 MAP (4, 0, BFD_RELOC_32
);
1095 MAP (1, 1, BFD_RELOC_8_PCREL
);
1096 MAP (2, 1, BFD_RELOC_16_PCREL
);
1097 MAP (4, 1, BFD_RELOC_32_PCREL
);
1105 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1106 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1107 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1108 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1111 reloc
->addend
= fixp
->fx_addnumber
;
1115 if (!fixp
->fx_pcrel
)
1116 reloc
->addend
= fixp
->fx_addnumber
;
1118 reloc
->addend
= (section
->vma
1119 /* Explicit sign extension in case char is
1121 + ((fixp
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80
1122 + fixp
->fx_addnumber
1123 + md_pcrel_from (fixp
));
1126 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1127 assert (reloc
->howto
!= 0);
1132 /* Handle of the OPCODE hash table. NULL means any use before
1133 m68k_ip_begin() will crash. */
1134 static struct hash_control
*op_hash
;
1136 /* Assemble an m68k instruction. */
1139 m68k_ip (char *instring
)
1142 register struct m68k_op
*opP
;
1143 register const struct m68k_incant
*opcode
;
1144 register const char *s
;
1145 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1146 char *pdot
, *pdotmove
;
1147 enum m68k_size siz1
, siz2
;
1151 struct m68k_op operands_backup
[6];
1152 LITTLENUM_TYPE words
[6];
1153 LITTLENUM_TYPE
*wordp
;
1154 unsigned long ok_arch
= 0;
1156 if (*instring
== ' ')
1157 instring
++; /* Skip leading whitespace. */
1159 /* Scan up to end of operation-code, which MUST end in end-of-string
1160 or exactly 1 space. */
1162 for (p
= instring
; *p
!= '\0'; p
++)
1172 the_ins
.error
= _("No operator");
1176 /* p now points to the end of the opcode name, probably whitespace.
1177 Make sure the name is null terminated by clobbering the
1178 whitespace, look it up in the hash table, then fix it back.
1179 Remove a dot, first, since the opcode tables have none. */
1182 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1183 *pdotmove
= pdotmove
[1];
1189 opcode
= (const struct m68k_incant
*) hash_find (op_hash
, instring
);
1194 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1195 *pdotmove
= pdotmove
[-1];
1202 the_ins
.error
= _("Unknown operator");
1206 /* Found a legitimate opcode, start matching operands. */
1210 if (opcode
->m_operands
== 0)
1212 char *old
= input_line_pointer
;
1214 input_line_pointer
= p
;
1215 /* Ahh - it's a motorola style psuedo op. */
1216 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1217 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1218 input_line_pointer
= old
;
1224 if (flag_mri
&& opcode
->m_opnum
== 0)
1226 /* In MRI mode, random garbage is allowed after an instruction
1227 which accepts no operands. */
1228 the_ins
.args
= opcode
->m_operands
;
1229 the_ins
.numargs
= opcode
->m_opnum
;
1230 the_ins
.numo
= opcode
->m_codenum
;
1231 the_ins
.opcode
[0] = getone (opcode
);
1232 the_ins
.opcode
[1] = gettwo (opcode
);
1236 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1238 p
= crack_operand (p
, opP
);
1242 the_ins
.error
= opP
->error
;
1247 opsfound
= opP
- &the_ins
.operands
[0];
1249 /* This ugly hack is to support the floating pt opcodes in their
1250 standard form. Essentially, we fake a first enty of type COP#1 */
1251 if (opcode
->m_operands
[0] == 'I')
1255 for (n
= opsfound
; n
> 0; --n
)
1256 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1258 memset (&the_ins
.operands
[0], '\0', sizeof (the_ins
.operands
[0]));
1259 the_ins
.operands
[0].mode
= CONTROL
;
1260 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1264 /* We've got the operands. Find an opcode that'll accept them. */
1267 /* If we didn't get the right number of ops, or we have no
1268 common model with this pattern then reject this pattern. */
1270 ok_arch
|= opcode
->m_arch
;
1271 if (opsfound
!= opcode
->m_opnum
1272 || ((opcode
->m_arch
& current_architecture
) == 0))
1278 /* Make a copy of the operands of this insn so that
1279 we can modify them safely, should we want to. */
1280 assert (opsfound
<= (int) ARRAY_SIZE (operands_backup
));
1281 for (i
= 0; i
< opsfound
; i
++)
1282 operands_backup
[i
] = the_ins
.operands
[i
];
1284 for (s
= opcode
->m_operands
, opP
= &operands_backup
[0];
1288 /* Warning: this switch is huge! */
1289 /* I've tried to organize the cases into this order:
1290 non-alpha first, then alpha by letter. Lower-case
1291 goes directly before uppercase counterpart. */
1292 /* Code with multiple case ...: gets sorted by the lowest
1293 case ... it belongs to. I hope this makes sense. */
1399 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1416 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1435 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1445 if (opP
->mode
!= IMMED
)
1447 else if (s
[1] == 'b'
1448 && ! isvar (&opP
->disp
)
1449 && (opP
->disp
.exp
.X_op
!= O_constant
1450 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1452 else if (s
[1] == 'B'
1453 && ! isvar (&opP
->disp
)
1454 && (opP
->disp
.exp
.X_op
!= O_constant
1455 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1457 else if (s
[1] == 'w'
1458 && ! isvar (&opP
->disp
)
1459 && (opP
->disp
.exp
.X_op
!= O_constant
1460 || ! isword (opP
->disp
.exp
.X_add_number
)))
1462 else if (s
[1] == 'W'
1463 && ! isvar (&opP
->disp
)
1464 && (opP
->disp
.exp
.X_op
!= O_constant
1465 || ! issword (opP
->disp
.exp
.X_add_number
)))
1471 if (opP
->mode
!= IMMED
)
1476 if (opP
->mode
== AREG
1477 || opP
->mode
== CONTROL
1478 || opP
->mode
== FPREG
1479 || opP
->mode
== IMMED
1480 || opP
->mode
== REGLST
1481 || (opP
->mode
!= ABSL
1483 || opP
->reg
== ZPC
)))
1488 if (opP
->mode
== CONTROL
1489 || opP
->mode
== FPREG
1490 || opP
->mode
== REGLST
1491 || opP
->mode
== IMMED
1492 || (opP
->mode
!= ABSL
1494 || opP
->reg
== ZPC
)))
1522 if (opP
->mode
== CONTROL
1523 || opP
->mode
== FPREG
1524 || opP
->mode
== REGLST
)
1529 if (opP
->mode
!= AINC
)
1534 if (opP
->mode
!= ADEC
)
1584 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1605 case '~': /* For now! (JF FOO is this right?) */
1627 if (opP
->mode
!= CONTROL
1628 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1633 if (opP
->mode
!= AREG
)
1638 if (opP
->mode
!= AINDR
)
1643 if (opP
->mode
!= AINDR
&& opP
->mode
!= AINC
&& opP
->mode
!= ADEC
1644 && (opP
->mode
!= DISP
1646 || opP
->reg
> ADDR7
))
1651 if (opP
->mode
!= ABSL
1653 && strncmp (instring
, "jbsr", 4) == 0))
1676 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1681 if (opP
->mode
!= DISP
1683 || opP
->reg
> ADDR7
)
1688 if (opP
->mode
!= DREG
)
1693 if (opP
->reg
!= ACC
)
1698 if (opP
->reg
!= ACC
&& opP
->reg
!= ACC1
1699 && opP
->reg
!= ACC2
&& opP
->reg
!= ACC3
)
1704 if (opP
->mode
!= FPREG
)
1709 if (opP
->reg
!= MACSR
)
1714 if (opP
->reg
!= ACCEXT01
&& opP
->reg
!= ACCEXT23
)
1719 if (opP
->reg
!= MASK
)
1724 if (opP
->mode
!= CONTROL
1731 if (opP
->mode
!= LSH
&& opP
->mode
!= RSH
)
1736 if (opP
->mode
!= CONTROL
1738 || opP
->reg
> last_movec_reg
1743 const enum m68k_register
*rp
;
1745 for (rp
= control_regs
; *rp
; rp
++)
1746 if (*rp
== opP
->reg
)
1754 if (opP
->mode
!= IMMED
)
1760 if (opP
->mode
== DREG
1761 || opP
->mode
== AREG
1762 || opP
->mode
== FPREG
)
1771 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1774 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1777 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1785 else if (opP
->mode
== CONTROL
)
1794 opP
->mask
= 1 << 24;
1797 opP
->mask
= 1 << 25;
1800 opP
->mask
= 1 << 26;
1809 else if (opP
->mode
!= REGLST
)
1811 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
1813 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
1818 if (opP
->mode
!= IMMED
)
1820 else if (opP
->disp
.exp
.X_op
!= O_constant
1821 || ! issbyte (opP
->disp
.exp
.X_add_number
))
1823 else if (! m68k_quick
1824 && instring
[3] != 'q'
1825 && instring
[4] != 'q')
1830 if (opP
->mode
!= DREG
1831 && opP
->mode
!= IMMED
1832 && opP
->mode
!= ABSL
)
1837 if (opP
->mode
!= IMMED
)
1839 else if (opP
->disp
.exp
.X_op
!= O_constant
1840 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
1842 else if (! m68k_quick
1843 && (strncmp (instring
, "add", 3) == 0
1844 || strncmp (instring
, "sub", 3) == 0)
1845 && instring
[3] != 'q')
1850 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1855 if (opP
->mode
!= AINDR
1856 && (opP
->mode
!= BASE
1858 && opP
->reg
!= ZADDR0
)
1859 || opP
->disp
.exp
.X_op
!= O_absent
1860 || ((opP
->index
.reg
< DATA0
1861 || opP
->index
.reg
> DATA7
)
1862 && (opP
->index
.reg
< ADDR0
1863 || opP
->index
.reg
> ADDR7
))
1864 || opP
->index
.size
!= SIZE_UNSPEC
1865 || opP
->index
.scale
!= 1))
1870 if (opP
->mode
!= CONTROL
1871 || ! (opP
->reg
== FPI
1873 || opP
->reg
== FPC
))
1878 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
1883 if (opP
->mode
!= IMMED
)
1885 else if (opP
->disp
.exp
.X_op
!= O_constant
1886 || TRUNC (opP
->disp
.exp
.X_add_number
) > 7)
1891 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
1896 if (opP
->mode
!= IMMED
)
1898 else if (opP
->disp
.exp
.X_op
!= O_constant
1899 || (TRUNC (opP
->disp
.exp
.X_add_number
) != 0xffffffff
1900 && TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 6))
1904 /* JF these are out of order. We could put them
1905 in order if we were willing to put up with
1906 bunches of #ifdef m68851s in the code.
1908 Don't forget that you need these operands
1909 to use 68030 MMU instructions. */
1911 /* Memory addressing mode used by pflushr. */
1913 if (opP
->mode
== CONTROL
1914 || opP
->mode
== FPREG
1915 || opP
->mode
== DREG
1916 || opP
->mode
== AREG
1917 || opP
->mode
== REGLST
)
1919 /* We should accept immediate operands, but they
1920 supposedly have to be quad word, and we don't
1921 handle that. I would like to see what a Motorola
1922 assembler does before doing something here. */
1923 if (opP
->mode
== IMMED
)
1928 if (opP
->mode
!= CONTROL
1929 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1934 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
1939 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
1944 if (opP
->mode
!= CONTROL
1947 && opP
->reg
!= SCC
))
1952 if (opP
->mode
!= CONTROL
1958 if (opP
->mode
!= CONTROL
1961 && opP
->reg
!= CRP
))
1985 if (opP
->mode
!= CONTROL
1986 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
1987 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
1992 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
1997 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
2002 if (opP
->mode
!= CONTROL
2011 if (opP
->mode
!= ABSL
)
2016 if (opP
->reg
< DATA0L
|| opP
->reg
> ADDR7U
)
2018 /* FIXME: kludge instead of fixing parser:
2019 upper/lower registers are *not* CONTROL
2020 registers, but ordinary ones. */
2021 if ((opP
->reg
>= DATA0L
&& opP
->reg
<= DATA7L
)
2022 || (opP
->reg
>= DATA0U
&& opP
->reg
<= DATA7U
))
2029 if (!(opP
->mode
== AINDR
2030 || (opP
->mode
== DISP
2031 && !(opP
->reg
== PC
|| opP
->reg
== ZPC
))))
2036 if (!(opP
->mode
== AINDR
|| opP
->mode
== DISP
))
2048 /* Since we have found the correct instruction, copy
2049 in the modifications that we may have made. */
2051 for (i
= 0; i
< opsfound
; i
++)
2052 the_ins
.operands
[i
] = operands_backup
[i
];
2058 opcode
= opcode
->m_next
;
2063 && !(ok_arch
& current_architecture
))
2065 const struct m68k_cpu
*cpu
;
2068 char *buf
= xmalloc (space
+ 1);
2072 the_ins
.error
= buf
;
2073 /* Make sure there's a NUL at the end of the buffer -- strncpy
2074 won't write one when it runs out of buffer */
2076 #define APPEND(STRING) \
2077 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2079 APPEND (_("invalid instruction for this architecture; needs "));
2083 APPEND (_("ColdFire ISA_A"));
2086 APPEND (_("ColdFire hardware divide"));
2089 APPEND (_("ColdFire ISA_A+"));
2092 APPEND (_("ColdFire ISA_B"));
2095 APPEND (_("ColdFire fpu"));
2098 APPEND (_("M68K fpu"));
2101 APPEND (_("M68K mmu"));
2104 APPEND (_("68020 or higher"));
2107 APPEND (_("68000 or higher"));
2110 APPEND (_("68010 or higher"));
2118 for (cpu
= m68k_cpus
; cpu
->name
; cpu
++)
2119 if (!cpu
->alias
&& (cpu
->arch
& ok_arch
))
2121 const struct m68k_cpu
*alias
;
2122 int seen_master
= 0;
2128 for (alias
= cpu
; alias
!= m68k_cpus
; alias
--)
2129 if (alias
[-1].alias
>= 0)
2131 for (; !seen_master
|| alias
->alias
> 0; alias
++)
2141 APPEND (alias
->name
);
2154 /* we ran out of space, so replace the end of the list
2159 strcpy (buf
, " ...");
2163 the_ins
.error
= _("operands mismatch");
2170 /* Now assemble it. */
2171 the_ins
.args
= opcode
->m_operands
;
2172 the_ins
.numargs
= opcode
->m_opnum
;
2173 the_ins
.numo
= opcode
->m_codenum
;
2174 the_ins
.opcode
[0] = getone (opcode
);
2175 the_ins
.opcode
[1] = gettwo (opcode
);
2177 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2179 /* This switch is a doozy.
2180 Watch the first step; its a big one! */
2213 tmpreg
= 0x3c; /* 7.4 */
2214 if (strchr ("bwl", s
[1]))
2215 nextword
= get_num (&opP
->disp
, 90);
2217 nextword
= get_num (&opP
->disp
, 0);
2218 if (isvar (&opP
->disp
))
2219 add_fix (s
[1], &opP
->disp
, 0, 0);
2223 if (!isbyte (nextword
))
2224 opP
->error
= _("operand out of range");
2229 if (!isword (nextword
))
2230 opP
->error
= _("operand out of range");
2235 if (!issword (nextword
))
2236 opP
->error
= _("operand out of range");
2241 addword (nextword
>> 16);
2268 /* We gotta put out some float. */
2269 if (op (&opP
->disp
) != O_big
)
2274 /* Can other cases happen here? */
2275 if (op (&opP
->disp
) != O_constant
)
2278 val
= (valueT
) offs (&opP
->disp
);
2282 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2283 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2287 offs (&opP
->disp
) = gencnt
;
2289 if (offs (&opP
->disp
) > 0)
2291 if (offs (&opP
->disp
) > baseo
)
2293 as_warn (_("Bignum too big for %c format; truncated"),
2295 offs (&opP
->disp
) = baseo
;
2297 baseo
-= offs (&opP
->disp
);
2300 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
2301 offs (&opP
->disp
)--;
2306 gen_to_words (words
, baseo
, (long) outro
);
2307 for (wordp
= words
; baseo
--; wordp
++)
2311 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2314 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2317 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2320 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2323 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2327 nextword
= get_num (&opP
->disp
, 90);
2329 /* Convert mode 5 addressing with a zero offset into
2330 mode 2 addressing to reduce the instruction size by a
2332 if (! isvar (&opP
->disp
)
2334 && (opP
->disp
.size
== SIZE_UNSPEC
)
2335 && (opP
->reg
>= ADDR0
)
2336 && (opP
->reg
<= ADDR7
))
2338 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2343 && ! isvar (&opP
->disp
)
2346 opP
->disp
.exp
.X_op
= O_symbol
;
2347 opP
->disp
.exp
.X_add_symbol
=
2348 section_symbol (absolute_section
);
2351 /* Force into index mode. Hope this works. */
2353 /* We do the first bit for 32-bit displacements, and the
2354 second bit for 16 bit ones. It is possible that we
2355 should make the default be WORD instead of LONG, but
2356 I think that'd break GCC, so we put up with a little
2357 inefficiency for the sake of working output. */
2359 if (!issword (nextword
)
2360 || (isvar (&opP
->disp
)
2361 && ((opP
->disp
.size
== SIZE_UNSPEC
2362 && flag_short_refs
== 0
2363 && cpu_of_arch (current_architecture
) >= m68020
2364 && ! arch_coldfire_p (current_architecture
))
2365 || opP
->disp
.size
== SIZE_LONG
)))
2367 if (cpu_of_arch (current_architecture
) < m68020
2368 || arch_coldfire_p (current_architecture
))
2370 _("displacement too large for this architecture; needs 68020 or higher");
2372 tmpreg
= 0x3B; /* 7.3 */
2374 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2375 if (isvar (&opP
->disp
))
2379 if (opP
->disp
.size
== SIZE_LONG
2381 /* If the displacement needs pic
2382 relocation it cannot be relaxed. */
2383 || opP
->disp
.pic_reloc
!= pic_none
2388 add_fix ('l', &opP
->disp
, 1, 2);
2392 add_frag (adds (&opP
->disp
),
2393 SEXT (offs (&opP
->disp
)),
2394 TAB (PCREL1632
, SZ_UNDEF
));
2401 add_fix ('l', &opP
->disp
, 0, 0);
2406 addword (nextword
>> 16);
2411 tmpreg
= 0x3A; /* 7.2 */
2413 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2415 if (isvar (&opP
->disp
))
2419 add_fix ('w', &opP
->disp
, 1, 0);
2422 add_fix ('w', &opP
->disp
, 0, 0);
2432 baseo
= get_num (&opP
->disp
, 90);
2433 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2434 outro
= get_num (&opP
->odisp
, 90);
2435 /* Figure out the `addressing mode'.
2436 Also turn on the BASE_DISABLE bit, if needed. */
2437 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2439 tmpreg
= 0x3b; /* 7.3 */
2440 if (opP
->reg
== ZPC
)
2443 else if (opP
->reg
== 0)
2446 tmpreg
= 0x30; /* 6.garbage */
2448 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2451 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2454 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2456 siz1
= opP
->disp
.size
;
2457 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2458 siz2
= opP
->odisp
.size
;
2462 /* Index register stuff. */
2463 if (opP
->index
.reg
!= 0
2464 && opP
->index
.reg
>= DATA
2465 && opP
->index
.reg
<= ADDR7
)
2467 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2469 if (opP
->index
.size
== SIZE_LONG
2470 || (opP
->index
.size
== SIZE_UNSPEC
2471 && m68k_index_width_default
== SIZE_LONG
))
2474 if ((opP
->index
.scale
!= 1
2475 && cpu_of_arch (current_architecture
) < m68020
)
2476 || (opP
->index
.scale
== 8
2477 && (arch_coldfire_p (current_architecture
)
2478 && !arch_coldfire_fpu (current_architecture
))))
2481 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2484 if (arch_coldfire_p (current_architecture
)
2485 && opP
->index
.size
== SIZE_WORD
)
2486 opP
->error
= _("invalid index size for coldfire");
2488 switch (opP
->index
.scale
)
2505 GET US OUT OF HERE! */
2507 /* Must be INDEX, with an index register. Address
2508 register cannot be ZERO-PC, and either :b was
2509 forced, or we know it will fit. For a 68000 or
2510 68010, force this mode anyways, because the
2511 larger modes aren't supported. */
2512 if (opP
->mode
== BASE
2513 && ((opP
->reg
>= ADDR0
2514 && opP
->reg
<= ADDR7
)
2517 if (siz1
== SIZE_BYTE
2518 || cpu_of_arch (current_architecture
) < m68020
2519 || arch_coldfire_p (current_architecture
)
2520 || (siz1
== SIZE_UNSPEC
2521 && ! isvar (&opP
->disp
)
2522 && issbyte (baseo
)))
2524 nextword
+= baseo
& 0xff;
2526 if (isvar (&opP
->disp
))
2528 /* Do a byte relocation. If it doesn't
2529 fit (possible on m68000) let the
2530 fixup processing complain later. */
2532 add_fix ('B', &opP
->disp
, 1, 1);
2534 add_fix ('B', &opP
->disp
, 0, 0);
2536 else if (siz1
!= SIZE_BYTE
)
2538 if (siz1
!= SIZE_UNSPEC
)
2539 as_warn (_("Forcing byte displacement"));
2540 if (! issbyte (baseo
))
2541 opP
->error
= _("byte displacement out of range");
2546 else if (siz1
== SIZE_UNSPEC
2548 && isvar (&opP
->disp
)
2549 && subs (&opP
->disp
) == NULL
2551 /* If the displacement needs pic
2552 relocation it cannot be relaxed. */
2553 && opP
->disp
.pic_reloc
== pic_none
2557 /* The code in md_convert_frag_1 needs to be
2558 able to adjust nextword. Call frag_grow
2559 to ensure that we have enough space in
2560 the frag obstack to make all the bytes
2563 nextword
+= baseo
& 0xff;
2565 add_frag (adds (&opP
->disp
),
2566 SEXT (offs (&opP
->disp
)),
2567 TAB (PCINDEX
, SZ_UNDEF
));
2575 nextword
|= 0x40; /* No index reg. */
2576 if (opP
->index
.reg
>= ZDATA0
2577 && opP
->index
.reg
<= ZDATA7
)
2578 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2579 else if (opP
->index
.reg
>= ZADDR0
2580 || opP
->index
.reg
<= ZADDR7
)
2581 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2584 /* It isn't simple. */
2586 if (cpu_of_arch (current_architecture
) < m68020
2587 || arch_coldfire_p (current_architecture
))
2589 _("invalid operand mode for this architecture; needs 68020 or higher");
2592 /* If the guy specified a width, we assume that it is
2593 wide enough. Maybe it isn't. If so, we lose. */
2597 if (isvar (&opP
->disp
)
2599 : ! issword (baseo
))
2604 else if (! isvar (&opP
->disp
) && baseo
== 0)
2613 as_warn (_(":b not permitted; defaulting to :w"));
2623 /* Figure out inner displacement stuff. */
2624 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2626 if (cpu_of_arch (current_architecture
) & cpu32
)
2627 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2631 if (isvar (&opP
->odisp
)
2633 : ! issword (outro
))
2638 else if (! isvar (&opP
->odisp
) && outro
== 0)
2647 as_warn (_(":b not permitted; defaulting to :w"));
2656 if (opP
->mode
== POST
2657 && (nextword
& 0x40) == 0)
2662 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2664 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2665 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2667 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2669 if (siz1
== SIZE_LONG
)
2670 addword (baseo
>> 16);
2671 if (siz1
!= SIZE_UNSPEC
)
2674 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2675 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2676 if (siz2
== SIZE_LONG
)
2677 addword (outro
>> 16);
2678 if (siz2
!= SIZE_UNSPEC
)
2684 nextword
= get_num (&opP
->disp
, 90);
2685 switch (opP
->disp
.size
)
2690 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2692 tmpreg
= 0x38; /* 7.0 */
2696 if (isvar (&opP
->disp
)
2697 && !subs (&opP
->disp
)
2698 && adds (&opP
->disp
)
2700 /* If the displacement needs pic relocation it
2701 cannot be relaxed. */
2702 && opP
->disp
.pic_reloc
== pic_none
2705 && !strchr ("~%&$?", s
[0]))
2707 tmpreg
= 0x3A; /* 7.2 */
2708 add_frag (adds (&opP
->disp
),
2709 SEXT (offs (&opP
->disp
)),
2710 TAB (ABSTOPCREL
, SZ_UNDEF
));
2713 /* Fall through into long. */
2715 if (isvar (&opP
->disp
))
2716 add_fix ('l', &opP
->disp
, 0, 0);
2718 tmpreg
= 0x39;/* 7.1 mode */
2719 addword (nextword
>> 16);
2724 as_bad (_("unsupported byte value; use a different suffix"));
2728 if (isvar (&opP
->disp
))
2729 add_fix ('w', &opP
->disp
, 0, 0);
2731 tmpreg
= 0x38;/* 7.0 mode */
2739 as_bad (_("unknown/incorrect operand"));
2743 /* If s[0] is '4', then this is for the mac instructions
2744 that can have a trailing_ampersand set. If so, set 0x100
2745 bit on tmpreg so install_gen_operand can check for it and
2746 set the appropriate bit (word2, bit 5). */
2749 if (opP
->trailing_ampersand
)
2752 install_gen_operand (s
[1], tmpreg
);
2758 { /* JF: I hate floating point! */
2773 tmpreg
= get_num (&opP
->disp
, tmpreg
);
2774 if (isvar (&opP
->disp
))
2775 add_fix (s
[1], &opP
->disp
, 0, 0);
2778 case 'b': /* Danger: These do no check for
2779 certain types of overflow.
2781 if (!isbyte (tmpreg
))
2782 opP
->error
= _("out of range");
2783 insop (tmpreg
, opcode
);
2784 if (isvar (&opP
->disp
))
2785 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
2786 (opcode
->m_codenum
) * 2 + 1;
2789 if (!issbyte (tmpreg
))
2790 opP
->error
= _("out of range");
2791 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
2792 if (isvar (&opP
->disp
))
2793 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
2796 if (!isword (tmpreg
))
2797 opP
->error
= _("out of range");
2798 insop (tmpreg
, opcode
);
2799 if (isvar (&opP
->disp
))
2800 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2803 if (!issword (tmpreg
))
2804 opP
->error
= _("out of range");
2805 insop (tmpreg
, opcode
);
2806 if (isvar (&opP
->disp
))
2807 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2810 /* Because of the way insop works, we put these two out
2812 insop (tmpreg
, opcode
);
2813 insop (tmpreg
>> 16, opcode
);
2814 if (isvar (&opP
->disp
))
2815 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2822 install_operand (s
[1], tmpreg
);
2833 install_operand (s
[1], opP
->reg
- ADDR
);
2837 tmpreg
= get_num (&opP
->disp
, 90);
2841 add_fix ('B', &opP
->disp
, 1, -1);
2844 add_fix ('w', &opP
->disp
, 1, 0);
2849 if (! HAVE_LONG_BRANCH (current_architecture
))
2850 as_warn (_("Can't use long branches on 68000/68010/5200"));
2851 the_ins
.opcode
[0] |= 0xff;
2852 add_fix ('l', &opP
->disp
, 1, 0);
2857 if (subs (&opP
->disp
)) /* We can't relax it. */
2861 /* If the displacement needs pic relocation it cannot be
2863 if (opP
->disp
.pic_reloc
!= pic_none
)
2866 /* This could either be a symbol, or an absolute
2867 address. If it's an absolute address, turn it into
2868 an absolute jump right here and keep it out of the
2870 if (adds (&opP
->disp
) == 0)
2872 if (the_ins
.opcode
[0] == 0x6000) /* jbra */
2873 the_ins
.opcode
[0] = 0x4EF9;
2874 else if (the_ins
.opcode
[0] == 0x6100) /* jbsr */
2875 the_ins
.opcode
[0] = 0x4EB9;
2878 the_ins
.opcode
[0] ^= 0x0100;
2879 the_ins
.opcode
[0] |= 0x0006;
2882 add_fix ('l', &opP
->disp
, 0, 0);
2888 /* Now we know it's going into the relaxer. Now figure
2889 out which mode. We try in this order of preference:
2890 long branch, absolute jump, byte/word branches only. */
2891 if (HAVE_LONG_BRANCH (current_architecture
))
2892 add_frag (adds (&opP
->disp
),
2893 SEXT (offs (&opP
->disp
)),
2894 TAB (BRANCHBWL
, SZ_UNDEF
));
2895 else if (! flag_keep_pcrel
)
2897 if ((the_ins
.opcode
[0] == 0x6000)
2898 || (the_ins
.opcode
[0] == 0x6100))
2899 add_frag (adds (&opP
->disp
),
2900 SEXT (offs (&opP
->disp
)),
2901 TAB (BRABSJUNC
, SZ_UNDEF
));
2903 add_frag (adds (&opP
->disp
),
2904 SEXT (offs (&opP
->disp
)),
2905 TAB (BRABSJCOND
, SZ_UNDEF
));
2908 add_frag (adds (&opP
->disp
),
2909 SEXT (offs (&opP
->disp
)),
2910 TAB (BRANCHBW
, SZ_UNDEF
));
2913 if (isvar (&opP
->disp
))
2915 /* Check for DBcc instructions. We can relax them,
2916 but only if we have long branches and/or absolute
2918 if (((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2919 && (HAVE_LONG_BRANCH (current_architecture
)
2920 || (! flag_keep_pcrel
)))
2922 if (HAVE_LONG_BRANCH (current_architecture
))
2923 add_frag (adds (&opP
->disp
),
2924 SEXT (offs (&opP
->disp
)),
2925 TAB (DBCCLBR
, SZ_UNDEF
));
2927 add_frag (adds (&opP
->disp
),
2928 SEXT (offs (&opP
->disp
)),
2929 TAB (DBCCABSJ
, SZ_UNDEF
));
2932 add_fix ('w', &opP
->disp
, 1, 0);
2936 case 'C': /* Fixed size LONG coproc branches. */
2937 add_fix ('l', &opP
->disp
, 1, 0);
2941 case 'c': /* Var size Coprocesssor branches. */
2942 if (subs (&opP
->disp
) || (adds (&opP
->disp
) == 0))
2944 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2945 add_fix ('l', &opP
->disp
, 1, 0);
2950 add_frag (adds (&opP
->disp
),
2951 SEXT (offs (&opP
->disp
)),
2952 TAB (FBRANCH
, SZ_UNDEF
));
2959 case 'C': /* Ignore it. */
2962 case 'd': /* JF this is a kludge. */
2963 install_operand ('s', opP
->reg
- ADDR
);
2964 tmpreg
= get_num (&opP
->disp
, 90);
2965 if (!issword (tmpreg
))
2967 as_warn (_("Expression out of range, using 0"));
2974 install_operand (s
[1], opP
->reg
- DATA
);
2977 case 'e': /* EMAC ACCx, reg/reg. */
2978 install_operand (s
[1], opP
->reg
- ACC
);
2981 case 'E': /* Ignore it. */
2985 install_operand (s
[1], opP
->reg
- FP0
);
2988 case 'g': /* EMAC ACCEXTx. */
2989 install_operand (s
[1], opP
->reg
- ACCEXT01
);
2992 case 'G': /* Ignore it. */
2997 tmpreg
= opP
->reg
- COP0
;
2998 install_operand (s
[1], tmpreg
);
3001 case 'i': /* MAC/EMAC scale factor. */
3002 install_operand (s
[1], opP
->mode
== LSH
? 0x1 : 0x3);
3005 case 'J': /* JF foo. */
3144 install_operand (s
[1], tmpreg
);
3148 tmpreg
= get_num (&opP
->disp
, 55);
3149 install_operand (s
[1], tmpreg
& 0x7f);
3156 if (tmpreg
& 0x7FF0000)
3157 as_bad (_("Floating point register in register list"));
3158 insop (reverse_16_bits (tmpreg
), opcode
);
3162 if (tmpreg
& 0x700FFFF)
3163 as_bad (_("Wrong register in floating-point reglist"));
3164 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
3172 if (tmpreg
& 0x7FF0000)
3173 as_bad (_("Floating point register in register list"));
3174 insop (tmpreg
, opcode
);
3176 else if (s
[1] == '8')
3178 if (tmpreg
& 0x0FFFFFF)
3179 as_bad (_("incorrect register in reglist"));
3180 install_operand (s
[1], tmpreg
>> 24);
3184 if (tmpreg
& 0x700FFFF)
3185 as_bad (_("wrong register in floating-point reglist"));
3187 install_operand (s
[1], tmpreg
>> 16);
3192 install_operand (s
[1], get_num (&opP
->disp
, 60));
3196 tmpreg
= ((opP
->mode
== DREG
)
3197 ? 0x20 + (int) (opP
->reg
- DATA
)
3198 : (get_num (&opP
->disp
, 40) & 0x1F));
3199 install_operand (s
[1], tmpreg
);
3203 tmpreg
= get_num (&opP
->disp
, 10);
3206 install_operand (s
[1], tmpreg
);
3210 /* This depends on the fact that ADDR registers are eight
3211 more than their corresponding DATA regs, so the result
3212 will have the ADDR_REG bit set. */
3213 install_operand (s
[1], opP
->reg
- DATA
);
3217 if (opP
->mode
== AINDR
)
3218 install_operand (s
[1], opP
->reg
- DATA
);
3220 install_operand (s
[1], opP
->index
.reg
- DATA
);
3224 if (opP
->reg
== FPI
)
3226 else if (opP
->reg
== FPS
)
3228 else if (opP
->reg
== FPC
)
3232 install_operand (s
[1], tmpreg
);
3235 case 'S': /* Ignore it. */
3239 install_operand (s
[1], get_num (&opP
->disp
, 30));
3242 case 'U': /* Ignore it. */
3261 as_fatal (_("failed sanity check"));
3262 } /* switch on cache token. */
3263 install_operand (s
[1], tmpreg
);
3266 /* JF: These are out of order, I fear. */
3279 install_operand (s
[1], tmpreg
);
3305 install_operand (s
[1], tmpreg
);
3309 if (opP
->reg
== VAL
)
3328 install_operand (s
[1], tmpreg
);
3342 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3353 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3359 install_operand (s
[1], tmpreg
);
3362 know (opP
->reg
== PSR
);
3365 know (opP
->reg
== PCSR
);
3380 install_operand (s
[1], tmpreg
);
3383 tmpreg
= get_num (&opP
->disp
, 20);
3384 install_operand (s
[1], tmpreg
);
3386 case '_': /* used only for move16 absolute 32-bit address. */
3387 if (isvar (&opP
->disp
))
3388 add_fix ('l', &opP
->disp
, 0, 0);
3389 tmpreg
= get_num (&opP
->disp
, 90);
3390 addword (tmpreg
>> 16);
3391 addword (tmpreg
& 0xFFFF);
3394 install_operand (s
[1], opP
->reg
- DATA0L
);
3395 opP
->reg
-= (DATA0L
);
3396 opP
->reg
&= 0x0F; /* remove upper/lower bit. */
3399 tmpreg
= get_num (&opP
->disp
, 80);
3402 install_operand (s
[1], tmpreg
);
3409 /* By the time whe get here (FINALLY) the_ins contains the complete
3410 instruction, ready to be emitted. . . */
3414 reverse_16_bits (int in
)
3419 static int mask
[16] =
3421 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3422 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3424 for (n
= 0; n
< 16; n
++)
3427 out
|= mask
[15 - n
];
3430 } /* reverse_16_bits() */
3433 reverse_8_bits (int in
)
3438 static int mask
[8] =
3440 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3443 for (n
= 0; n
< 8; n
++)
3449 } /* reverse_8_bits() */
3451 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3452 (that value is chosen in the frag_var call in md_assemble). TYPE
3453 is the subtype of the frag to be generated; its primary type is
3454 rs_machine_dependent.
3456 The TYPE parameter is also used by md_convert_frag_1 and
3457 md_estimate_size_before_relax. The appropriate type of fixup will
3458 be emitted by md_convert_frag_1.
3460 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3462 install_operand (int mode
, int val
)
3467 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge. */
3470 the_ins
.opcode
[0] |= val
<< 9;
3473 the_ins
.opcode
[1] |= val
<< 12;
3476 the_ins
.opcode
[1] |= val
<< 6;
3479 the_ins
.opcode
[1] |= val
;
3482 the_ins
.opcode
[2] |= val
<< 12;
3485 the_ins
.opcode
[2] |= val
<< 6;
3488 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3489 three words long! */
3491 the_ins
.opcode
[2] |= val
;
3494 the_ins
.opcode
[1] |= val
<< 7;
3497 the_ins
.opcode
[1] |= val
<< 10;
3501 the_ins
.opcode
[1] |= val
<< 5;
3506 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3509 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3512 the_ins
.opcode
[0] |= val
= 0xff;
3515 the_ins
.opcode
[0] |= val
<< 9;
3518 the_ins
.opcode
[1] |= val
;
3521 the_ins
.opcode
[1] |= val
;
3522 the_ins
.numo
++; /* What a hack. */
3525 the_ins
.opcode
[1] |= val
<< 4;
3533 the_ins
.opcode
[0] |= (val
<< 6);
3536 the_ins
.opcode
[1] = (val
>> 16);
3537 the_ins
.opcode
[2] = val
& 0xffff;
3540 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3541 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3542 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3544 case 'n': /* MAC/EMAC Rx on !load. */
3545 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3546 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3547 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3549 case 'o': /* MAC/EMAC Rx on load. */
3550 the_ins
.opcode
[1] |= val
<< 12;
3551 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3553 case 'M': /* MAC/EMAC Ry on !load. */
3554 the_ins
.opcode
[0] |= (val
& 0xF);
3555 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3557 case 'N': /* MAC/EMAC Ry on load. */
3558 the_ins
.opcode
[1] |= (val
& 0xF);
3559 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3562 the_ins
.opcode
[1] |= ((val
!= 1) << 10);
3565 the_ins
.opcode
[0] |= ((val
& 0x3) << 9);
3568 the_ins
.opcode
[0] |= ((val
& 0x3) << 0);
3570 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3571 the_ins
.opcode
[0] |= ((~val
& 0x1) << 7);
3572 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3574 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3575 the_ins
.opcode
[0] |= ((val
& 0x1) << 7);
3576 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3579 the_ins
.opcode
[1] |= ((val
& 0x3) << 9);
3582 the_ins
.opcode
[0] |= (val
& 0x1) <<10;
3586 as_fatal (_("failed sanity check."));
3591 install_gen_operand (int mode
, int val
)
3595 case '/': /* Special for mask loads for mac/msac insns with
3596 possible mask; trailing_ampersend set in bit 8. */
3597 the_ins
.opcode
[0] |= (val
& 0x3f);
3598 the_ins
.opcode
[1] |= (((val
& 0x100) >> 8) << 5);
3601 the_ins
.opcode
[0] |= val
;
3604 /* This is a kludge!!! */
3605 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3614 the_ins
.opcode
[0] |= val
;
3616 /* more stuff goes here. */
3618 as_fatal (_("failed sanity check."));
3622 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3623 then deal with the bitfield hack. */
3626 crack_operand (char *str
, struct m68k_op
*opP
)
3628 register int parens
;
3630 register char *beg_str
;
3638 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3644 else if (*str
== ')')
3648 opP
->error
= _("Extra )");
3654 if (flag_mri
&& *str
== '\'')
3655 inquote
= ! inquote
;
3657 if (!*str
&& parens
)
3659 opP
->error
= _("Missing )");
3664 if (m68k_ip_op (beg_str
, opP
) != 0)
3671 c
= *++str
; /* JF bitfield hack. */
3676 as_bad (_("Missing operand"));
3679 /* Detect MRI REG symbols and convert them to REGLSTs. */
3680 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
3683 opP
->mask
= ~(int)opP
->reg
;
3690 /* This is the guts of the machine-dependent assembler. STR points to a
3691 machine dependent instruction. This function is supposed to emit
3692 the frags/bytes it assembles to.
3696 insert_reg (const char *regname
, int regnum
)
3701 #ifdef REGISTER_PREFIX
3702 if (!flag_reg_prefix_optional
)
3704 buf
[0] = REGISTER_PREFIX
;
3705 strcpy (buf
+ 1, regname
);
3710 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
3711 &zero_address_frag
));
3713 for (i
= 0; regname
[i
]; i
++)
3714 buf
[i
] = TOUPPER (regname
[i
]);
3717 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
3718 &zero_address_frag
));
3727 static const struct init_entry init_table
[] =
3787 { "accext01", ACCEXT01
},
3788 { "accext23", ACCEXT23
},
3792 /* Control registers. */
3793 { "sfc", SFC
}, /* Source Function Code. */
3795 { "dfc", DFC
}, /* Destination Function Code. */
3797 { "cacr", CACR
}, /* Cache Control Register. */
3798 { "caar", CAAR
}, /* Cache Address Register. */
3800 { "usp", USP
}, /* User Stack Pointer. */
3801 { "vbr", VBR
}, /* Vector Base Register. */
3802 { "msp", MSP
}, /* Master Stack Pointer. */
3803 { "isp", ISP
}, /* Interrupt Stack Pointer. */
3805 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0. */
3806 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1. */
3807 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0. */
3808 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1. */
3810 /* 68ec040 versions of same */
3811 { "iacr0", ITT0
}, /* Instruction Access Control Register 0. */
3812 { "iacr1", ITT1
}, /* Instruction Access Control Register 0. */
3813 { "dacr0", DTT0
}, /* Data Access Control Register 0. */
3814 { "dacr1", DTT1
}, /* Data Access Control Register 0. */
3816 /* Coldfire versions of same. The ColdFire programmer's reference
3817 manual indicated that the order is 2,3,0,1, but Ken Rose
3818 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3819 { "acr0", ACR0
}, /* Access Control Unit 0. */
3820 { "acr1", ACR1
}, /* Access Control Unit 1. */
3821 { "acr2", ACR2
}, /* Access Control Unit 2. */
3822 { "acr3", ACR3
}, /* Access Control Unit 3. */
3824 { "tc", TC
}, /* MMU Translation Control Register. */
3828 { "mmusr", MMUSR
}, /* MMU Status Register. */
3829 { "srp", SRP
}, /* User Root Pointer. */
3830 { "urp", URP
}, /* Supervisor Root Pointer. */
3833 { "mmubar", MMUBAR
},
3836 { "rombar", ROMBAR
}, /* ROM Base Address Register. */
3837 { "rambar0", RAMBAR0
}, /* ROM Base Address Register. */
3838 { "rambar1", RAMBAR1
}, /* ROM Base Address Register. */
3839 { "mbar", MBAR
}, /* Module Base Address Register. */
3841 { "mbar0", MBAR0
}, /* mcfv4e registers. */
3842 { "mbar1", MBAR1
}, /* mcfv4e registers. */
3843 { "rombar0", ROMBAR0
}, /* mcfv4e registers. */
3844 { "rombar1", ROMBAR1
}, /* mcfv4e registers. */
3845 { "mpcr", MPCR
}, /* mcfv4e registers. */
3846 { "edrambar", EDRAMBAR
}, /* mcfv4e registers. */
3847 { "secmbar", SECMBAR
}, /* mcfv4e registers. */
3848 { "asid", TC
}, /* mcfv4e registers. */
3849 { "mmubar", BUSCR
}, /* mcfv4e registers. */
3850 { "pcr1u0", PCR1U0
}, /* mcfv4e registers. */
3851 { "pcr1l0", PCR1L0
}, /* mcfv4e registers. */
3852 { "pcr2u0", PCR2U0
}, /* mcfv4e registers. */
3853 { "pcr2l0", PCR2L0
}, /* mcfv4e registers. */
3854 { "pcr3u0", PCR3U0
}, /* mcfv4e registers. */
3855 { "pcr3l0", PCR3L0
}, /* mcfv4e registers. */
3856 { "pcr1u1", PCR1U1
}, /* mcfv4e registers. */
3857 { "pcr1l1", PCR1L1
}, /* mcfv4e registers. */
3858 { "pcr2u1", PCR2U1
}, /* mcfv4e registers. */
3859 { "pcr2l1", PCR2L1
}, /* mcfv4e registers. */
3860 { "pcr3u1", PCR3U1
}, /* mcfv4e registers. */
3861 { "pcr3l1", PCR3L1
}, /* mcfv4e registers. */
3863 { "flashbar", FLASHBAR
}, /* mcf528x registers. */
3864 { "rambar", RAMBAR
}, /* mcf528x registers. */
3866 { "mbar2", MBAR2
}, /* mcf5249 registers. */
3868 { "cac", CAC
}, /* fido registers. */
3869 { "mbb", MBB
}, /* fido registers. */
3870 /* End of control registers. */
3904 /* 68ec030 versions of same. */
3907 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3910 /* Suppressed data and address registers. */
3928 /* Upper and lower data and address registers, used by macw and msacw. */
3969 init_regtable (void)
3972 for (i
= 0; init_table
[i
].name
; i
++)
3973 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
3977 md_assemble (char *str
)
3984 int shorts_this_frag
;
3987 if (!selected_cpu
&& !selected_arch
)
3989 /* We've not selected an architecture yet. Set the default
3990 now. We do this lazily so that an initial .cpu or .arch directive
3992 if (!m68k_set_cpu (TARGET_CPU
, 1, 1))
3993 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU
);
3998 /* In MRI mode, the instruction and operands are separated by a
3999 space. Anything following the operands is a comment. The label
4000 has already been removed. */
4008 for (s
= str
; *s
!= '\0'; s
++)
4010 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
4028 inquote
= ! inquote
;
4033 memset (&the_ins
, '\0', sizeof (the_ins
));
4038 for (n
= 0; n
< the_ins
.numargs
; n
++)
4039 if (the_ins
.operands
[n
].error
)
4041 er
= the_ins
.operands
[n
].error
;
4047 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
4051 /* If there is a current label, record that it marks an instruction. */
4052 if (current_label
!= NULL
)
4054 current_label
->text
= 1;
4055 current_label
= NULL
;
4059 /* Tie dwarf2 debug info to the address at the start of the insn. */
4060 dwarf2_emit_insn (0);
4063 if (the_ins
.nfrag
== 0)
4065 /* No frag hacking involved; just put it out. */
4066 toP
= frag_more (2 * the_ins
.numo
);
4067 fromP
= &the_ins
.opcode
[0];
4068 for (m
= the_ins
.numo
; m
; --m
)
4070 md_number_to_chars (toP
, (long) (*fromP
), 2);
4074 /* Put out symbol-dependent info. */
4075 for (m
= 0; m
< the_ins
.nrel
; m
++)
4077 switch (the_ins
.reloc
[m
].wid
)
4096 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4097 the_ins
.reloc
[m
].wid
);
4100 fixP
= fix_new_exp (frag_now
,
4101 ((toP
- frag_now
->fr_literal
)
4102 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4104 &the_ins
.reloc
[m
].exp
,
4105 the_ins
.reloc
[m
].pcrel
,
4106 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
4107 the_ins
.reloc
[m
].pic_reloc
));
4108 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4109 if (the_ins
.reloc
[m
].wid
== 'B')
4110 fixP
->fx_signed
= 1;
4115 /* There's some frag hacking. */
4117 /* Calculate the max frag size. */
4120 wid
= 2 * the_ins
.fragb
[0].fragoff
;
4121 for (n
= 1; n
< the_ins
.nfrag
; n
++)
4122 wid
+= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4123 /* frag_var part. */
4125 /* Make sure the whole insn fits in one chunk, in particular that
4126 the var part is attached, as we access one byte before the
4127 variable frag for byte branches. */
4131 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
4136 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
4138 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4139 toP
= frag_more (wid
);
4141 shorts_this_frag
= 0;
4142 for (m
= wid
/ 2; m
; --m
)
4144 md_number_to_chars (toP
, (long) (*fromP
), 2);
4149 for (m
= 0; m
< the_ins
.nrel
; m
++)
4151 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
4153 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
4156 wid
= the_ins
.reloc
[m
].wid
;
4159 the_ins
.reloc
[m
].wid
= 0;
4160 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4162 fixP
= fix_new_exp (frag_now
,
4163 ((toP
- frag_now
->fr_literal
)
4164 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4166 &the_ins
.reloc
[m
].exp
,
4167 the_ins
.reloc
[m
].pcrel
,
4168 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4169 the_ins
.reloc
[m
].pic_reloc
));
4170 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4172 (void) frag_var (rs_machine_dependent
, 10, 0,
4173 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
4174 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
4176 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4177 shorts_this_frag
= 0;
4180 toP
= frag_more (n
* 2);
4183 md_number_to_chars (toP
, (long) (*fromP
), 2);
4189 for (m
= 0; m
< the_ins
.nrel
; m
++)
4193 wid
= the_ins
.reloc
[m
].wid
;
4196 the_ins
.reloc
[m
].wid
= 0;
4197 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4199 fixP
= fix_new_exp (frag_now
,
4200 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
4201 - shorts_this_frag
* 2),
4203 &the_ins
.reloc
[m
].exp
,
4204 the_ins
.reloc
[m
].pcrel
,
4205 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4206 the_ins
.reloc
[m
].pic_reloc
));
4207 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4211 /* Comparison function used by qsort to rank the opcode entries by name. */
4214 m68k_compare_opcode (const void * v1
, const void * v2
)
4216 struct m68k_opcode
* op1
, * op2
;
4222 op1
= *(struct m68k_opcode
**) v1
;
4223 op2
= *(struct m68k_opcode
**) v2
;
4225 /* Compare the two names. If different, return the comparison.
4226 If the same, return the order they are in the opcode table. */
4227 ret
= strcmp (op1
->name
, op2
->name
);
4238 const struct m68k_opcode
*ins
;
4239 struct m68k_incant
*hack
, *slak
;
4240 const char *retval
= 0; /* Empty string, or error msg text. */
4243 /* Set up hash tables with 68000 instructions.
4244 similar to what the vax assembler does. */
4245 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4246 a copy of it at runtime, adding in the information we want but isn't
4247 there. I think it'd be better to have an awk script hack the table
4248 at compile time. Or even just xstr the table and use it as-is. But
4249 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4254 flag_reg_prefix_optional
= 1;
4256 if (! m68k_rel32_from_cmdline
)
4260 /* First sort the opcode table into alphabetical order to seperate
4261 the order that the assembler wants to see the opcodes from the
4262 order that the disassembler wants to see them. */
4263 m68k_sorted_opcodes
= xmalloc (m68k_numopcodes
* sizeof (* m68k_sorted_opcodes
));
4264 if (!m68k_sorted_opcodes
)
4265 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4266 m68k_numopcodes
* ((int) sizeof (* m68k_sorted_opcodes
)));
4268 for (i
= m68k_numopcodes
; i
--;)
4269 m68k_sorted_opcodes
[i
] = m68k_opcodes
+ i
;
4271 qsort (m68k_sorted_opcodes
, m68k_numopcodes
,
4272 sizeof (m68k_sorted_opcodes
[0]), m68k_compare_opcode
);
4274 op_hash
= hash_new ();
4276 obstack_begin (&robyn
, 4000);
4277 for (i
= 0; i
< m68k_numopcodes
; i
++)
4279 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4282 ins
= m68k_sorted_opcodes
[i
];
4284 /* We *could* ignore insns that don't match our
4285 arch here by just leaving them out of the hash. */
4286 slak
->m_operands
= ins
->args
;
4287 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
4288 slak
->m_arch
= ins
->arch
;
4289 slak
->m_opcode
= ins
->opcode
;
4290 /* This is kludgey. */
4291 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
4292 if (i
+ 1 != m68k_numopcodes
4293 && !strcmp (ins
->name
, m68k_sorted_opcodes
[i
+ 1]->name
))
4295 slak
->m_next
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4300 slak
= slak
->m_next
;
4304 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
4306 as_fatal (_("Internal Error: Can't hash %s: %s"), ins
->name
, retval
);
4309 for (i
= 0; i
< m68k_numaliases
; i
++)
4311 const char *name
= m68k_opcode_aliases
[i
].primary
;
4312 const char *alias
= m68k_opcode_aliases
[i
].alias
;
4313 PTR val
= hash_find (op_hash
, name
);
4316 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4317 retval
= hash_insert (op_hash
, alias
, val
);
4319 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4322 /* In MRI mode, all unsized branches are variable sized. Normally,
4323 they are word sized. */
4326 static struct m68k_opcode_alias mri_aliases
[] =
4347 i
< (int) (sizeof mri_aliases
/ sizeof mri_aliases
[0]);
4350 const char *name
= mri_aliases
[i
].primary
;
4351 const char *alias
= mri_aliases
[i
].alias
;
4352 PTR val
= hash_find (op_hash
, name
);
4355 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4356 retval
= hash_jam (op_hash
, alias
, val
);
4358 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4362 for (i
= 0; i
< (int) sizeof (notend_table
); i
++)
4364 notend_table
[i
] = 0;
4365 alt_notend_table
[i
] = 0;
4368 notend_table
[','] = 1;
4369 notend_table
['{'] = 1;
4370 notend_table
['}'] = 1;
4371 alt_notend_table
['a'] = 1;
4372 alt_notend_table
['A'] = 1;
4373 alt_notend_table
['d'] = 1;
4374 alt_notend_table
['D'] = 1;
4375 alt_notend_table
['#'] = 1;
4376 alt_notend_table
['&'] = 1;
4377 alt_notend_table
['f'] = 1;
4378 alt_notend_table
['F'] = 1;
4379 #ifdef REGISTER_PREFIX
4380 alt_notend_table
[REGISTER_PREFIX
] = 1;
4383 /* We need to put '(' in alt_notend_table to handle
4384 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4385 alt_notend_table
['('] = 1;
4387 /* We need to put '@' in alt_notend_table to handle
4388 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4389 alt_notend_table
['@'] = 1;
4391 /* We need to put digits in alt_notend_table to handle
4392 bfextu %d0{24:1},%d0 */
4393 alt_notend_table
['0'] = 1;
4394 alt_notend_table
['1'] = 1;
4395 alt_notend_table
['2'] = 1;
4396 alt_notend_table
['3'] = 1;
4397 alt_notend_table
['4'] = 1;
4398 alt_notend_table
['5'] = 1;
4399 alt_notend_table
['6'] = 1;
4400 alt_notend_table
['7'] = 1;
4401 alt_notend_table
['8'] = 1;
4402 alt_notend_table
['9'] = 1;
4404 #ifndef MIT_SYNTAX_ONLY
4405 /* Insert pseudo ops, these have to go into the opcode table since
4406 gas expects pseudo ops to start with a dot. */
4410 while (mote_pseudo_table
[n
].poc_name
)
4412 hack
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4413 hash_insert (op_hash
,
4414 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
4415 hack
->m_operands
= 0;
4425 record_alignment (text_section
, 2);
4426 record_alignment (data_section
, 2);
4427 record_alignment (bss_section
, 2);
4432 /* This is called when a label is defined. */
4435 m68k_frob_label (symbolS
*sym
)
4437 struct label_line
*n
;
4439 n
= (struct label_line
*) xmalloc (sizeof *n
);
4442 as_where (&n
->file
, &n
->line
);
4448 dwarf2_emit_label (sym
);
4452 /* This is called when a value that is not an instruction is emitted. */
4455 m68k_flush_pending_output (void)
4457 current_label
= NULL
;
4460 /* This is called at the end of the assembly, when the final value of
4461 the label is known. We warn if this is a text symbol aligned at an
4465 m68k_frob_symbol (symbolS
*sym
)
4467 if (S_GET_SEGMENT (sym
) == reg_section
4468 && (int) S_GET_VALUE (sym
) < 0)
4470 S_SET_SEGMENT (sym
, absolute_section
);
4471 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
4473 else if ((S_GET_VALUE (sym
) & 1) != 0)
4475 struct label_line
*l
;
4477 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4479 if (l
->label
== sym
)
4482 as_warn_where (l
->file
, l
->line
,
4483 _("text label `%s' aligned to odd boundary"),
4491 /* This is called if we go in or out of MRI mode because of the .mri
4495 m68k_mri_mode_change (int on
)
4499 if (! flag_reg_prefix_optional
)
4501 flag_reg_prefix_optional
= 1;
4502 #ifdef REGISTER_PREFIX
4507 if (! m68k_rel32_from_cmdline
)
4512 if (! reg_prefix_optional_seen
)
4514 #ifdef REGISTER_PREFIX_OPTIONAL
4515 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
4517 flag_reg_prefix_optional
= 0;
4519 #ifdef REGISTER_PREFIX
4524 if (! m68k_rel32_from_cmdline
)
4529 /* Equal to MAX_PRECISION in atof-ieee.c. */
4530 #define MAX_LITTLENUMS 6
4532 /* Turn a string in input_line_pointer into a floating point constant
4533 of type TYPE, and store the appropriate bytes in *LITP. The number
4534 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4535 returned, or NULL on OK. */
4538 md_atof (int type
, char *litP
, int *sizeP
)
4541 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4542 LITTLENUM_TYPE
*wordP
;
4573 return _("Bad call to MD_ATOF()");
4575 t
= atof_ieee (input_line_pointer
, type
, words
);
4577 input_line_pointer
= t
;
4579 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4580 for (wordP
= words
; prec
--;)
4582 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
4583 litP
+= sizeof (LITTLENUM_TYPE
);
4589 md_number_to_chars (char *buf
, valueT val
, int n
)
4591 number_to_chars_bigendian (buf
, val
, n
);
4595 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4597 offsetT val
= *valP
;
4598 addressT upper_limit
;
4599 offsetT lower_limit
;
4601 /* This is unnecessary but it convinces the native rs6000 compiler
4602 to generate the code we want. */
4603 char *buf
= fixP
->fx_frag
->fr_literal
;
4604 buf
+= fixP
->fx_where
;
4605 /* End ibm compiler workaround. */
4609 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4615 memset (buf
, 0, fixP
->fx_size
);
4616 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4618 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4619 && !S_IS_DEFINED (fixP
->fx_addsy
)
4620 && !S_IS_WEAK (fixP
->fx_addsy
))
4621 S_SET_WEAK (fixP
->fx_addsy
);
4626 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4627 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4630 switch (fixP
->fx_size
)
4632 /* The cast to offsetT below are necessary to make code
4633 correct for machines where ints are smaller than offsetT. */
4637 lower_limit
= - (offsetT
) 0x80;
4640 *buf
++ = (val
>> 8);
4642 upper_limit
= 0x7fff;
4643 lower_limit
= - (offsetT
) 0x8000;
4646 *buf
++ = (val
>> 24);
4647 *buf
++ = (val
>> 16);
4648 *buf
++ = (val
>> 8);
4650 upper_limit
= 0x7fffffff;
4651 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* Avoid constant overflow. */
4654 BAD_CASE (fixP
->fx_size
);
4657 /* Fix up a negative reloc. */
4658 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4660 fixP
->fx_addsy
= fixP
->fx_subsy
;
4661 fixP
->fx_subsy
= NULL
;
4665 /* For non-pc-relative values, it's conceivable we might get something
4666 like "0xff" for a byte field. So extend the upper part of the range
4667 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4668 so that we can do any range checking at all. */
4669 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
4670 upper_limit
= upper_limit
* 2 + 1;
4672 if ((addressT
) val
> upper_limit
4673 && (val
> 0 || val
< lower_limit
))
4674 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("value out of range"));
4676 /* A one byte PC-relative reloc means a short branch. We can't use
4677 a short branch with a value of 0 or -1, because those indicate
4678 different opcodes (branches with longer offsets). fixup_segment
4679 in write.c may have clobbered fx_pcrel, so we need to examine the
4682 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4683 && fixP
->fx_size
== 1
4684 && (fixP
->fx_addsy
== NULL
4685 || S_IS_DEFINED (fixP
->fx_addsy
))
4686 && (val
== 0 || val
== -1))
4687 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("invalid byte branch offset"));
4690 /* *fragP has been relaxed to its final size, and now needs to have
4691 the bytes inside it modified to conform to the new size There is UGLY
4695 md_convert_frag_1 (fragS
*fragP
)
4700 /* Address in object code of the displacement. */
4701 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4703 /* Address in gas core of the place to store the displacement. */
4704 /* This convinces the native rs6000 compiler to generate the code we
4706 register char *buffer_address
= fragP
->fr_literal
;
4707 buffer_address
+= fragP
->fr_fix
;
4708 /* End ibm compiler workaround. */
4710 /* The displacement of the address, from current location. */
4711 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4712 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4714 switch (fragP
->fr_subtype
)
4716 case TAB (BRANCHBWL
, BYTE
):
4717 case TAB (BRABSJUNC
, BYTE
):
4718 case TAB (BRABSJCOND
, BYTE
):
4719 case TAB (BRANCHBW
, BYTE
):
4720 know (issbyte (disp
));
4722 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4723 _("short branch with zero offset: use :w"));
4724 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4725 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4726 fixP
->fx_pcrel_adjust
= -1;
4728 case TAB (BRANCHBWL
, SHORT
):
4729 case TAB (BRABSJUNC
, SHORT
):
4730 case TAB (BRABSJCOND
, SHORT
):
4731 case TAB (BRANCHBW
, SHORT
):
4732 fragP
->fr_opcode
[1] = 0x00;
4733 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4734 1, RELAX_RELOC_PC16
);
4737 case TAB (BRANCHBWL
, LONG
):
4738 fragP
->fr_opcode
[1] = (char) 0xFF;
4739 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4740 1, RELAX_RELOC_PC32
);
4743 case TAB (BRABSJUNC
, LONG
):
4744 if (fragP
->fr_opcode
[0] == 0x61) /* jbsr */
4746 if (flag_keep_pcrel
)
4747 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4748 fragP
->fr_opcode
[0] = 0x4E;
4749 fragP
->fr_opcode
[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4750 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4751 0, RELAX_RELOC_ABS32
);
4754 else if (fragP
->fr_opcode
[0] == 0x60) /* jbra */
4756 if (flag_keep_pcrel
)
4757 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4758 fragP
->fr_opcode
[0] = 0x4E;
4759 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4760 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4761 0, RELAX_RELOC_ABS32
);
4766 /* This cannot happen, because jbsr and jbra are the only two
4767 unconditional branches. */
4771 case TAB (BRABSJCOND
, LONG
):
4772 if (flag_keep_pcrel
)
4773 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4775 /* Only Bcc 68000 instructions can come here
4776 Change bcc into b!cc/jmp absl long. */
4777 fragP
->fr_opcode
[0] ^= 0x01; /* Invert bcc. */
4778 fragP
->fr_opcode
[1] = 0x06; /* Branch offset = 6. */
4780 /* JF: these used to be fr_opcode[2,3], but they may be in a
4781 different frag, in which case referring to them is a no-no.
4782 Only fr_opcode[0,1] are guaranteed to work. */
4783 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4784 *buffer_address
++ = (char) 0xf9;
4785 fragP
->fr_fix
+= 2; /* Account for jmp instruction. */
4786 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4787 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
4790 case TAB (FBRANCH
, SHORT
):
4791 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4792 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4793 1, RELAX_RELOC_PC16
);
4796 case TAB (FBRANCH
, LONG
):
4797 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit. */
4798 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4799 1, RELAX_RELOC_PC32
);
4802 case TAB (DBCCLBR
, SHORT
):
4803 case TAB (DBCCABSJ
, SHORT
):
4804 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4805 1, RELAX_RELOC_PC16
);
4808 case TAB (DBCCLBR
, LONG
):
4809 /* Only DBcc instructions can come here.
4810 Change dbcc into dbcc/bral.
4811 JF: these used to be fr_opcode[2-7], but that's wrong. */
4812 if (flag_keep_pcrel
)
4813 as_fatal (_("Tried to convert DBcc to absolute jump"));
4815 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4816 *buffer_address
++ = 0x04;
4817 *buffer_address
++ = 0x60; /* Put in bra pc+6. */
4818 *buffer_address
++ = 0x06;
4819 *buffer_address
++ = 0x60; /* Put in bral (0x60ff). */
4820 *buffer_address
++ = (char) 0xff;
4822 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4823 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 1,
4827 case TAB (DBCCABSJ
, LONG
):
4828 /* Only DBcc instructions can come here.
4829 Change dbcc into dbcc/jmp.
4830 JF: these used to be fr_opcode[2-7], but that's wrong. */
4831 if (flag_keep_pcrel
)
4832 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4834 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4835 *buffer_address
++ = 0x04;
4836 *buffer_address
++ = 0x60; /* Put in bra pc + 6. */
4837 *buffer_address
++ = 0x06;
4838 *buffer_address
++ = 0x4e; /* Put in jmp long (0x4ef9). */
4839 *buffer_address
++ = (char) 0xf9;
4841 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4842 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 0,
4846 case TAB (PCREL1632
, SHORT
):
4847 fragP
->fr_opcode
[1] &= ~0x3F;
4848 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
4849 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4850 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4853 case TAB (PCREL1632
, LONG
):
4854 /* Already set to mode 7.3; this indicates: PC indirect with
4855 suppressed index, 32-bit displacement. */
4856 *buffer_address
++ = 0x01;
4857 *buffer_address
++ = 0x70;
4859 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4860 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4861 fixP
->fx_pcrel_adjust
= 2;
4864 case TAB (PCINDEX
, BYTE
):
4865 assert (fragP
->fr_fix
>= 2);
4866 buffer_address
[-2] &= ~1;
4867 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4868 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4869 fixP
->fx_pcrel_adjust
= 1;
4871 case TAB (PCINDEX
, SHORT
):
4872 assert (fragP
->fr_fix
>= 2);
4873 buffer_address
[-2] |= 0x1;
4874 buffer_address
[-1] = 0x20;
4875 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4876 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4877 fixP
->fx_pcrel_adjust
= 2;
4880 case TAB (PCINDEX
, LONG
):
4881 assert (fragP
->fr_fix
>= 2);
4882 buffer_address
[-2] |= 0x1;
4883 buffer_address
[-1] = 0x30;
4884 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4885 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4886 fixP
->fx_pcrel_adjust
= 2;
4889 case TAB (ABSTOPCREL
, SHORT
):
4890 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4891 1, RELAX_RELOC_PC16
);
4894 case TAB (ABSTOPCREL
, LONG
):
4895 if (flag_keep_pcrel
)
4896 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4897 /* The thing to do here is force it to ABSOLUTE LONG, since
4898 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4899 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
4901 fragP
->fr_opcode
[1] &= ~0x3F;
4902 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
4903 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4904 0, RELAX_RELOC_ABS32
);
4911 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
4912 segT sec ATTRIBUTE_UNUSED
,
4915 md_convert_frag_1 (fragP
);
4918 /* Force truly undefined symbols to their maximum size, and generally set up
4919 the frag list to be relaxed
4922 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
4924 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4925 switch (fragP
->fr_subtype
)
4927 case TAB (BRANCHBWL
, SZ_UNDEF
):
4928 case TAB (BRABSJUNC
, SZ_UNDEF
):
4929 case TAB (BRABSJCOND
, SZ_UNDEF
):
4931 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4932 && relaxable_symbol (fragP
->fr_symbol
))
4934 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4936 else if (flag_short_refs
)
4938 /* Symbol is undefined and we want short ref. */
4939 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4943 /* Symbol is still undefined. Make it LONG. */
4944 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
4949 case TAB (BRANCHBW
, SZ_UNDEF
):
4951 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4952 && relaxable_symbol (fragP
->fr_symbol
))
4954 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4958 /* Symbol is undefined and we don't have long branches. */
4959 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4964 case TAB (FBRANCH
, SZ_UNDEF
):
4965 case TAB (DBCCLBR
, SZ_UNDEF
):
4966 case TAB (DBCCABSJ
, SZ_UNDEF
):
4967 case TAB (PCREL1632
, SZ_UNDEF
):
4969 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4970 && relaxable_symbol (fragP
->fr_symbol
))
4973 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4977 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
4982 case TAB (PCINDEX
, SZ_UNDEF
):
4983 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4984 && relaxable_symbol (fragP
->fr_symbol
)))
4986 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
4990 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
4994 case TAB (ABSTOPCREL
, SZ_UNDEF
):
4996 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4997 && relaxable_symbol (fragP
->fr_symbol
)))
4999 fragP
->fr_subtype
= TAB (ABSTOPCREL
, SHORT
);
5003 fragP
->fr_subtype
= TAB (ABSTOPCREL
, LONG
);
5012 /* Now that SZ_UNDEF are taken care of, check others. */
5013 switch (fragP
->fr_subtype
)
5015 case TAB (BRANCHBWL
, BYTE
):
5016 case TAB (BRABSJUNC
, BYTE
):
5017 case TAB (BRABSJCOND
, BYTE
):
5018 case TAB (BRANCHBW
, BYTE
):
5019 /* We can't do a short jump to the next instruction, so in that
5020 case we force word mode. If the symbol is at the start of a
5021 frag, and it is the next frag with any data in it (usually
5022 this is just the next frag, but assembler listings may
5023 introduce empty frags), we must use word mode. */
5024 if (fragP
->fr_symbol
)
5028 sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
5029 if (S_GET_VALUE (fragP
->fr_symbol
) == sym_frag
->fr_address
)
5033 for (l
= fragP
->fr_next
; l
&& l
!= sym_frag
; l
= l
->fr_next
)
5037 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5044 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5047 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5048 /* the bit-field entries in the relocation_info struct plays hell
5049 with the byte-order problems of cross-assembly. So as a hack,
5050 I added this mach. dependent ri twiddler. Ugly, but it gets
5052 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5053 are symbolnum, most sig. byte first. Last byte is broken up with
5054 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5055 nibble as nuthin. (on Sun 3 at least) */
5056 /* Translate the internal relocation information into target-specific
5060 md_ri_to_chars (char *the_bytes
, struct reloc_info_generic
*ri
)
5063 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
5064 /* Now the fun stuff. */
5065 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
5066 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
5067 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
5068 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80)
5069 | ((ri
->r_length
<< 5) & 0x60)
5070 | ((ri
->r_extern
<< 4) & 0x10));
5075 #endif /* OBJ_AOUT or OBJ_BOUT */
5077 #ifndef WORKING_DOT_WORD
5078 int md_short_jump_size
= 4;
5079 int md_long_jump_size
= 6;
5082 md_create_short_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5083 fragS
*frag ATTRIBUTE_UNUSED
,
5084 symbolS
*to_symbol ATTRIBUTE_UNUSED
)
5088 offset
= to_addr
- (from_addr
+ 2);
5090 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
5091 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
5095 md_create_long_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5096 fragS
*frag
, symbolS
*to_symbol
)
5100 if (!HAVE_LONG_BRANCH (current_architecture
))
5102 if (flag_keep_pcrel
)
5103 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5104 offset
= to_addr
- S_GET_VALUE (to_symbol
);
5105 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
5106 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5107 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
5112 offset
= to_addr
- (from_addr
+ 2);
5113 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
5114 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5120 /* Different values of OK tell what its OK to return. Things that
5121 aren't OK are an error (what a shock, no?)
5124 10: Absolute 1:8 only
5125 20: Absolute 0:7 only
5126 30: absolute 0:15 only
5127 40: Absolute 0:31 only
5128 50: absolute 0:127 only
5129 55: absolute -64:63 only
5130 60: absolute -128:127 only
5131 70: absolute 0:4095 only
5132 80: absolute -1, 1:7 only
5136 get_num (struct m68k_exp
*exp
, int ok
)
5138 if (exp
->exp
.X_op
== O_absent
)
5140 /* Do the same thing the VAX asm does. */
5141 op (exp
) = O_constant
;
5147 as_warn (_("expression out of range: defaulting to 1"));
5151 else if (exp
->exp
.X_op
== O_constant
)
5156 if ((valueT
) TRUNC (offs (exp
)) - 1 > 7)
5158 as_warn (_("expression out of range: defaulting to 1"));
5163 if ((valueT
) TRUNC (offs (exp
)) > 7)
5167 if ((valueT
) TRUNC (offs (exp
)) > 15)
5171 if ((valueT
) TRUNC (offs (exp
)) > 32)
5175 if ((valueT
) TRUNC (offs (exp
)) > 127)
5179 if ((valueT
) SEXT (offs (exp
)) + 64 > 127)
5183 if ((valueT
) SEXT (offs (exp
)) + 128 > 255)
5187 if ((valueT
) TRUNC (offs (exp
)) > 4095)
5190 as_warn (_("expression out of range: defaulting to 0"));
5195 if ((valueT
) TRUNC (offs (exp
)) != 0xffffffff
5196 && (valueT
) TRUNC (offs (exp
)) - 1 > 6)
5198 as_warn (_("expression out of range: defaulting to 1"));
5206 else if (exp
->exp
.X_op
== O_big
)
5208 if (offs (exp
) <= 0 /* flonum. */
5209 && (ok
== 90 /* no bignums */
5210 || (ok
> 10 /* Small-int ranges including 0 ok. */
5211 /* If we have a flonum zero, a zero integer should
5212 do as well (e.g., in moveq). */
5213 && generic_floating_point_number
.exponent
== 0
5214 && generic_floating_point_number
.low
[0] == 0)))
5216 /* HACK! Turn it into a long. */
5217 LITTLENUM_TYPE words
[6];
5219 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
5220 op (exp
) = O_constant
;
5223 offs (exp
) = words
[1] | (words
[0] << 16);
5227 op (exp
) = O_constant
;
5230 offs (exp
) = (ok
== 10) ? 1 : 0;
5231 as_warn (_("Can't deal with expression; defaulting to %ld"),
5237 if (ok
>= 10 && ok
<= 80)
5239 op (exp
) = O_constant
;
5242 offs (exp
) = (ok
== 10) ? 1 : 0;
5243 as_warn (_("Can't deal with expression; defaulting to %ld"),
5248 if (exp
->size
!= SIZE_UNSPEC
)
5256 if (!isbyte (offs (exp
)))
5257 as_warn (_("expression doesn't fit in BYTE"));
5260 if (!isword (offs (exp
)))
5261 as_warn (_("expression doesn't fit in WORD"));
5269 /* These are the back-ends for the various machine dependent pseudo-ops. */
5272 s_data1 (int ignore ATTRIBUTE_UNUSED
)
5274 subseg_set (data_section
, 1);
5275 demand_empty_rest_of_line ();
5279 s_data2 (int ignore ATTRIBUTE_UNUSED
)
5281 subseg_set (data_section
, 2);
5282 demand_empty_rest_of_line ();
5286 s_bss (int ignore ATTRIBUTE_UNUSED
)
5288 /* We don't support putting frags in the BSS segment, we fake it
5289 by marking in_bss, then looking at s_skip for clues. */
5291 subseg_set (bss_section
, 0);
5292 demand_empty_rest_of_line ();
5296 s_even (int ignore ATTRIBUTE_UNUSED
)
5299 register long temp_fill
;
5301 temp
= 1; /* JF should be 2? */
5302 temp_fill
= get_absolute_expression ();
5303 if (!need_pass_2
) /* Never make frag if expect extra pass. */
5304 frag_align (temp
, (int) temp_fill
, 0);
5305 demand_empty_rest_of_line ();
5306 record_alignment (now_seg
, temp
);
5310 s_proc (int ignore ATTRIBUTE_UNUSED
)
5312 demand_empty_rest_of_line ();
5315 /* Pseudo-ops handled for MRI compatibility. */
5317 /* This function returns non-zero if the argument is a conditional
5318 pseudo-op. This is called when checking whether a pending
5319 alignment is needed. */
5322 m68k_conditional_pseudoop (pseudo_typeS
*pop
)
5324 return (pop
->poc_handler
== s_mri_if
5325 || pop
->poc_handler
== s_mri_else
);
5328 /* Handle an MRI style chip specification. */
5337 s
= input_line_pointer
;
5338 /* We can't use get_symbol_end since the processor names are not proper
5340 while (is_part_of_name (c
= *input_line_pointer
++))
5342 *--input_line_pointer
= 0;
5343 for (i
= 0; m68k_cpus
[i
].name
; i
++)
5344 if (strcasecmp (s
, m68k_cpus
[i
].name
) == 0)
5346 if (!m68k_cpus
[i
].name
)
5348 as_bad (_("%s: unrecognized processor name"), s
);
5349 *input_line_pointer
= c
;
5350 ignore_rest_of_line ();
5353 *input_line_pointer
= c
;
5355 if (*input_line_pointer
== '/')
5356 current_architecture
= 0;
5358 current_architecture
&= m68881
| m68851
;
5359 current_architecture
|= m68k_cpus
[i
].arch
& ~(m68881
| m68851
);
5360 control_regs
= m68k_cpus
[i
].control_regs
;
5362 while (*input_line_pointer
== '/')
5364 ++input_line_pointer
;
5365 s
= input_line_pointer
;
5366 /* We can't use get_symbol_end since the processor names are not
5368 while (is_part_of_name (c
= *input_line_pointer
++))
5370 *--input_line_pointer
= 0;
5371 if (strcmp (s
, "68881") == 0)
5372 current_architecture
|= m68881
;
5373 else if (strcmp (s
, "68851") == 0)
5374 current_architecture
|= m68851
;
5375 *input_line_pointer
= c
;
5379 /* The MRI CHIP pseudo-op. */
5382 s_chip (int ignore ATTRIBUTE_UNUSED
)
5388 stop
= mri_comment_field (&stopc
);
5391 mri_comment_end (stop
, stopc
);
5392 demand_empty_rest_of_line ();
5395 /* The MRI FOPT pseudo-op. */
5398 s_fopt (int ignore ATTRIBUTE_UNUSED
)
5402 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
5406 input_line_pointer
+= 3;
5407 temp
= get_absolute_expression ();
5408 if (temp
< 0 || temp
> 7)
5409 as_bad (_("bad coprocessor id"));
5411 m68k_float_copnum
= COP0
+ temp
;
5415 as_bad (_("unrecognized fopt option"));
5416 ignore_rest_of_line ();
5420 demand_empty_rest_of_line ();
5423 /* The structure used to handle the MRI OPT pseudo-op. */
5427 /* The name of the option. */
5430 /* If this is not NULL, just call this function. The first argument
5431 is the ARG field of this structure, the second argument is
5432 whether the option was negated. */
5433 void (*pfn
) (int arg
, int on
);
5435 /* If this is not NULL, and the PFN field is NULL, set the variable
5436 this points to. Set it to the ARG field if the option was not
5437 negated, and the NOTARG field otherwise. */
5440 /* The value to pass to PFN or to assign to *PVAR. */
5443 /* The value to assign to *PVAR if the option is negated. If PFN is
5444 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5445 the option may not be negated. */
5449 /* The table used to handle the MRI OPT pseudo-op. */
5451 static void skip_to_comma (int, int);
5452 static void opt_nest (int, int);
5453 static void opt_chip (int, int);
5454 static void opt_list (int, int);
5455 static void opt_list_symbols (int, int);
5457 static const struct opt_action opt_table
[] =
5459 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5461 /* We do relaxing, so there is little use for these options. */
5462 { "b", 0, 0, 0, 0 },
5463 { "brs", 0, 0, 0, 0 },
5464 { "brb", 0, 0, 0, 0 },
5465 { "brl", 0, 0, 0, 0 },
5466 { "brw", 0, 0, 0, 0 },
5468 { "c", 0, 0, 0, 0 },
5469 { "cex", 0, 0, 0, 0 },
5470 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5471 { "cl", 0, 0, 0, 0 },
5472 { "cre", 0, 0, 0, 0 },
5473 { "d", 0, &flag_keep_locals
, 1, 0 },
5474 { "e", 0, 0, 0, 0 },
5475 { "f", 0, &flag_short_refs
, 1, 0 },
5476 { "frs", 0, &flag_short_refs
, 1, 0 },
5477 { "frl", 0, &flag_short_refs
, 0, 1 },
5478 { "g", 0, 0, 0, 0 },
5479 { "i", 0, 0, 0, 0 },
5480 { "m", 0, 0, 0, 0 },
5481 { "mex", 0, 0, 0, 0 },
5482 { "mc", 0, 0, 0, 0 },
5483 { "md", 0, 0, 0, 0 },
5484 { "nest", opt_nest
, 0, 0, 0 },
5485 { "next", skip_to_comma
, 0, 0, 0 },
5486 { "o", 0, 0, 0, 0 },
5487 { "old", 0, 0, 0, 0 },
5488 { "op", skip_to_comma
, 0, 0, 0 },
5489 { "pco", 0, 0, 0, 0 },
5490 { "p", opt_chip
, 0, 0, 0 },
5491 { "pcr", 0, 0, 0, 0 },
5492 { "pcs", 0, 0, 0, 0 },
5493 { "r", 0, 0, 0, 0 },
5494 { "quick", 0, &m68k_quick
, 1, 0 },
5495 { "rel32", 0, &m68k_rel32
, 1, 0 },
5496 { "s", opt_list
, 0, 0, 0 },
5497 { "t", opt_list_symbols
, 0, 0, 0 },
5498 { "w", 0, &flag_no_warnings
, 0, 1 },
5502 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5504 /* The MRI OPT pseudo-op. */
5507 s_opt (int ignore ATTRIBUTE_UNUSED
)
5515 const struct opt_action
*o
;
5520 if (*input_line_pointer
== '-')
5522 ++input_line_pointer
;
5525 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5527 input_line_pointer
+= 2;
5531 s
= input_line_pointer
;
5532 c
= get_symbol_end ();
5534 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5536 if (strcasecmp (s
, o
->name
) == 0)
5540 /* Restore input_line_pointer now in case the option
5542 *input_line_pointer
= c
;
5543 (*o
->pfn
) (o
->arg
, t
);
5545 else if (o
->pvar
!= NULL
)
5547 if (! t
&& o
->arg
== o
->notarg
)
5548 as_bad (_("option `%s' may not be negated"), s
);
5549 *input_line_pointer
= c
;
5550 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5553 *input_line_pointer
= c
;
5559 as_bad (_("option `%s' not recognized"), s
);
5560 *input_line_pointer
= c
;
5563 while (*input_line_pointer
++ == ',');
5565 /* Move back to terminating character. */
5566 --input_line_pointer
;
5567 demand_empty_rest_of_line ();
5570 /* Skip ahead to a comma. This is used for OPT options which we do
5571 not support and which take arguments. */
5574 skip_to_comma (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5576 while (*input_line_pointer
!= ','
5577 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5578 ++input_line_pointer
;
5581 /* Handle the OPT NEST=depth option. */
5584 opt_nest (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5586 if (*input_line_pointer
!= '=')
5588 as_bad (_("bad format of OPT NEST=depth"));
5592 ++input_line_pointer
;
5593 max_macro_nest
= get_absolute_expression ();
5596 /* Handle the OPT P=chip option. */
5599 opt_chip (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5601 if (*input_line_pointer
!= '=')
5603 /* This is just OPT P, which we do not support. */
5607 ++input_line_pointer
;
5611 /* Handle the OPT S option. */
5614 opt_list (int arg ATTRIBUTE_UNUSED
, int on
)
5619 /* Handle the OPT T option. */
5622 opt_list_symbols (int arg ATTRIBUTE_UNUSED
, int on
)
5625 listing
|= LISTING_SYMBOLS
;
5627 listing
&= ~LISTING_SYMBOLS
;
5630 /* Handle the MRI REG pseudo-op. */
5633 s_reg (int ignore ATTRIBUTE_UNUSED
)
5642 if (line_label
== NULL
)
5644 as_bad (_("missing label"));
5645 ignore_rest_of_line ();
5650 stop
= mri_comment_field (&stopc
);
5654 s
= input_line_pointer
;
5655 while (ISALNUM (*input_line_pointer
)
5656 #ifdef REGISTER_PREFIX
5657 || *input_line_pointer
== REGISTER_PREFIX
5659 || *input_line_pointer
== '/'
5660 || *input_line_pointer
== '-')
5661 ++input_line_pointer
;
5662 c
= *input_line_pointer
;
5663 *input_line_pointer
= '\0';
5665 if (m68k_ip_op (s
, &rop
) != 0)
5667 if (rop
.error
== NULL
)
5668 as_bad (_("bad register list"));
5670 as_bad (_("bad register list: %s"), rop
.error
);
5671 *input_line_pointer
= c
;
5672 ignore_rest_of_line ();
5676 *input_line_pointer
= c
;
5678 if (rop
.mode
== REGLST
)
5680 else if (rop
.mode
== DREG
)
5681 mask
= 1 << (rop
.reg
- DATA0
);
5682 else if (rop
.mode
== AREG
)
5683 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
5684 else if (rop
.mode
== FPREG
)
5685 mask
= 1 << (rop
.reg
- FP0
+ 16);
5686 else if (rop
.mode
== CONTROL
5689 else if (rop
.mode
== CONTROL
5692 else if (rop
.mode
== CONTROL
5697 as_bad (_("bad register list"));
5698 ignore_rest_of_line ();
5702 S_SET_SEGMENT (line_label
, reg_section
);
5703 S_SET_VALUE (line_label
, ~mask
);
5704 symbol_set_frag (line_label
, &zero_address_frag
);
5707 mri_comment_end (stop
, stopc
);
5709 demand_empty_rest_of_line ();
5712 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5716 struct save_opts
*next
;
5718 int symbols_case_sensitive
;
5722 const enum m68k_register
*control_regs
;
5727 /* FIXME: We don't save OPT S. */
5730 /* This variable holds the stack of saved options. */
5732 static struct save_opts
*save_stack
;
5734 /* The MRI SAVE pseudo-op. */
5737 s_save (int ignore ATTRIBUTE_UNUSED
)
5739 struct save_opts
*s
;
5741 s
= (struct save_opts
*) xmalloc (sizeof (struct save_opts
));
5742 s
->abspcadd
= m68k_abspcadd
;
5743 s
->symbols_case_sensitive
= symbols_case_sensitive
;
5744 s
->keep_locals
= flag_keep_locals
;
5745 s
->short_refs
= flag_short_refs
;
5746 s
->architecture
= current_architecture
;
5747 s
->control_regs
= control_regs
;
5748 s
->quick
= m68k_quick
;
5749 s
->rel32
= m68k_rel32
;
5750 s
->listing
= listing
;
5751 s
->no_warnings
= flag_no_warnings
;
5753 s
->next
= save_stack
;
5756 demand_empty_rest_of_line ();
5759 /* The MRI RESTORE pseudo-op. */
5762 s_restore (int ignore ATTRIBUTE_UNUSED
)
5764 struct save_opts
*s
;
5766 if (save_stack
== NULL
)
5768 as_bad (_("restore without save"));
5769 ignore_rest_of_line ();
5774 save_stack
= s
->next
;
5776 m68k_abspcadd
= s
->abspcadd
;
5777 symbols_case_sensitive
= s
->symbols_case_sensitive
;
5778 flag_keep_locals
= s
->keep_locals
;
5779 flag_short_refs
= s
->short_refs
;
5780 current_architecture
= s
->architecture
;
5781 control_regs
= s
->control_regs
;
5782 m68k_quick
= s
->quick
;
5783 m68k_rel32
= s
->rel32
;
5784 listing
= s
->listing
;
5785 flag_no_warnings
= s
->no_warnings
;
5789 demand_empty_rest_of_line ();
5792 /* Types of MRI structured control directives. */
5794 enum mri_control_type
5802 /* This structure is used to stack the MRI structured control
5805 struct mri_control_info
5807 /* The directive within which this one is enclosed. */
5808 struct mri_control_info
*outer
;
5810 /* The type of directive. */
5811 enum mri_control_type type
;
5813 /* Whether an ELSE has been in an IF. */
5816 /* The add or sub statement at the end of a FOR. */
5819 /* The label of the top of a FOR or REPEAT loop. */
5822 /* The label to jump to for the next iteration, or the else
5823 expression of a conditional. */
5826 /* The label to jump to to break out of the loop, or the label past
5827 the end of a conditional. */
5831 /* The stack of MRI structured control directives. */
5833 static struct mri_control_info
*mri_control_stack
;
5835 /* The current MRI structured control directive index number, used to
5836 generate label names. */
5838 static int mri_control_index
;
5840 /* Assemble an instruction for an MRI structured control directive. */
5843 mri_assemble (char *str
)
5847 /* md_assemble expects the opcode to be in lower case. */
5848 for (s
= str
; *s
!= ' ' && *s
!= '\0'; s
++)
5854 /* Generate a new MRI label structured control directive label name. */
5857 mri_control_label (void)
5861 n
= (char *) xmalloc (20);
5862 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
5863 ++mri_control_index
;
5867 /* Create a new MRI structured control directive. */
5869 static struct mri_control_info
*
5870 push_mri_control (enum mri_control_type type
)
5872 struct mri_control_info
*n
;
5874 n
= (struct mri_control_info
*) xmalloc (sizeof (struct mri_control_info
));
5878 if (type
== mri_if
|| type
== mri_while
)
5881 n
->top
= mri_control_label ();
5882 n
->next
= mri_control_label ();
5883 n
->bottom
= mri_control_label ();
5885 n
->outer
= mri_control_stack
;
5886 mri_control_stack
= n
;
5891 /* Pop off the stack of MRI structured control directives. */
5894 pop_mri_control (void)
5896 struct mri_control_info
*n
;
5898 n
= mri_control_stack
;
5899 mri_control_stack
= n
->outer
;
5907 /* Recognize a condition code in an MRI structured control expression. */
5910 parse_mri_condition (int *pcc
)
5914 know (*input_line_pointer
== '<');
5916 ++input_line_pointer
;
5917 c1
= *input_line_pointer
++;
5918 c2
= *input_line_pointer
++;
5920 if (*input_line_pointer
!= '>')
5922 as_bad (_("syntax error in structured control directive"));
5926 ++input_line_pointer
;
5932 *pcc
= (c1
<< 8) | c2
;
5937 /* Parse a single operand in an MRI structured control expression. */
5940 parse_mri_control_operand (int *pcc
, char **leftstart
, char **leftstop
,
5941 char **rightstart
, char **rightstop
)
5953 if (*input_line_pointer
== '<')
5955 /* It's just a condition code. */
5956 return parse_mri_condition (pcc
);
5959 /* Look ahead for the condition code. */
5960 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5962 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
5967 as_bad (_("missing condition code in structured control directive"));
5971 *leftstart
= input_line_pointer
;
5973 if (*leftstop
> *leftstart
5974 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
5977 input_line_pointer
= s
;
5978 if (! parse_mri_condition (pcc
))
5981 /* Look ahead for AND or OR or end of line. */
5982 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5984 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5985 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5987 if ((s
== input_line_pointer
5990 && ((strncasecmp (s
, "AND", 3) == 0
5991 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
5992 || (strncasecmp (s
, "OR", 2) == 0
5993 && (s
[2] == '.' || ! is_part_of_name (s
[2])))))
5997 *rightstart
= input_line_pointer
;
5999 if (*rightstop
> *rightstart
6000 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
6003 input_line_pointer
= s
;
6008 #define MCC(b1, b2) (((b1) << 8) | (b2))
6010 /* Swap the sense of a condition. This changes the condition so that
6011 it generates the same result when the operands are swapped. */
6014 swap_mri_condition (int cc
)
6018 case MCC ('h', 'i'): return MCC ('c', 's');
6019 case MCC ('l', 's'): return MCC ('c', 'c');
6020 /* <HS> is an alias for <CC>. */
6021 case MCC ('h', 's'):
6022 case MCC ('c', 'c'): return MCC ('l', 's');
6023 /* <LO> is an alias for <CS>. */
6024 case MCC ('l', 'o'):
6025 case MCC ('c', 's'): return MCC ('h', 'i');
6026 case MCC ('p', 'l'): return MCC ('m', 'i');
6027 case MCC ('m', 'i'): return MCC ('p', 'l');
6028 case MCC ('g', 'e'): return MCC ('l', 'e');
6029 case MCC ('l', 't'): return MCC ('g', 't');
6030 case MCC ('g', 't'): return MCC ('l', 't');
6031 case MCC ('l', 'e'): return MCC ('g', 'e');
6032 /* Issue a warning for conditions we can not swap. */
6033 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6034 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6035 case MCC ('v', 'c'):
6036 case MCC ('v', 's'):
6038 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6039 (char) (cc
>> 8), (char) (cc
));
6045 /* Reverse the sense of a condition. */
6048 reverse_mri_condition (int cc
)
6052 case MCC ('h', 'i'): return MCC ('l', 's');
6053 case MCC ('l', 's'): return MCC ('h', 'i');
6054 /* <HS> is an alias for <CC> */
6055 case MCC ('h', 's'): return MCC ('l', 'o');
6056 case MCC ('c', 'c'): return MCC ('c', 's');
6057 /* <LO> is an alias for <CS> */
6058 case MCC ('l', 'o'): return MCC ('h', 's');
6059 case MCC ('c', 's'): return MCC ('c', 'c');
6060 case MCC ('n', 'e'): return MCC ('e', 'q');
6061 case MCC ('e', 'q'): return MCC ('n', 'e');
6062 case MCC ('v', 'c'): return MCC ('v', 's');
6063 case MCC ('v', 's'): return MCC ('v', 'c');
6064 case MCC ('p', 'l'): return MCC ('m', 'i');
6065 case MCC ('m', 'i'): return MCC ('p', 'l');
6066 case MCC ('g', 'e'): return MCC ('l', 't');
6067 case MCC ('l', 't'): return MCC ('g', 'e');
6068 case MCC ('g', 't'): return MCC ('l', 'e');
6069 case MCC ('l', 'e'): return MCC ('g', 't');
6074 /* Build an MRI structured control expression. This generates test
6075 and branch instructions. It goes to TRUELAB if the condition is
6076 true, and to FALSELAB if the condition is false. Exactly one of
6077 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6078 is the size qualifier for the expression. EXTENT is the size to
6079 use for the branch. */
6082 build_mri_control_operand (int qual
, int cc
, char *leftstart
, char *leftstop
,
6083 char *rightstart
, char *rightstop
,
6084 const char *truelab
, const char *falselab
,
6090 if (leftstart
!= NULL
)
6092 struct m68k_op leftop
, rightop
;
6095 /* Swap the compare operands, if necessary, to produce a legal
6096 m68k compare instruction. Comparing a register operand with
6097 a non-register operand requires the register to be on the
6098 right (cmp, cmpa). Comparing an immediate value with
6099 anything requires the immediate value to be on the left
6104 (void) m68k_ip_op (leftstart
, &leftop
);
6109 (void) m68k_ip_op (rightstart
, &rightop
);
6112 if (rightop
.mode
== IMMED
6113 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
6114 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
6118 /* Correct conditional handling:
6119 if #1 <lt> d0 then ;means if (1 < d0)
6125 cmp #1,d0 if we do *not* swap the operands
6126 bgt true we need the swapped condition!
6133 leftstart
= rightstart
;
6136 leftstop
= rightstop
;
6141 cc
= swap_mri_condition (cc
);
6145 if (truelab
== NULL
)
6147 cc
= reverse_mri_condition (cc
);
6151 if (leftstart
!= NULL
)
6153 buf
= (char *) xmalloc (20
6154 + (leftstop
- leftstart
)
6155 + (rightstop
- rightstart
));
6161 *s
++ = TOLOWER (qual
);
6163 memcpy (s
, leftstart
, leftstop
- leftstart
);
6164 s
+= leftstop
- leftstart
;
6166 memcpy (s
, rightstart
, rightstop
- rightstart
);
6167 s
+= rightstop
- rightstart
;
6173 buf
= (char *) xmalloc (20 + strlen (truelab
));
6179 *s
++ = TOLOWER (extent
);
6181 strcpy (s
, truelab
);
6186 /* Parse an MRI structured control expression. This generates test
6187 and branch instructions. STOP is where the expression ends. It
6188 goes to TRUELAB if the condition is true, and to FALSELAB if the
6189 condition is false. Exactly one of TRUELAB and FALSELAB will be
6190 NULL, meaning to fall through. QUAL is the size qualifier for the
6191 expression. EXTENT is the size to use for the branch. */
6194 parse_mri_control_expression (char *stop
, int qual
, const char *truelab
,
6195 const char *falselab
, int extent
)
6207 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6208 &rightstart
, &rightstop
))
6214 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
6218 if (falselab
!= NULL
)
6221 flab
= mri_control_label ();
6223 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6224 rightstop
, (const char *) NULL
, flab
, extent
);
6226 input_line_pointer
+= 3;
6227 if (*input_line_pointer
!= '.'
6228 || input_line_pointer
[1] == '\0')
6232 qual
= input_line_pointer
[1];
6233 input_line_pointer
+= 2;
6236 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6237 &rightstart
, &rightstop
))
6243 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6244 rightstop
, truelab
, falselab
, extent
);
6246 if (falselab
== NULL
)
6249 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
6253 if (truelab
!= NULL
)
6256 tlab
= mri_control_label ();
6258 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6259 rightstop
, tlab
, (const char *) NULL
, extent
);
6261 input_line_pointer
+= 2;
6262 if (*input_line_pointer
!= '.'
6263 || input_line_pointer
[1] == '\0')
6267 qual
= input_line_pointer
[1];
6268 input_line_pointer
+= 2;
6271 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6272 &rightstart
, &rightstop
))
6278 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6279 rightstop
, truelab
, falselab
, extent
);
6281 if (truelab
== NULL
)
6286 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6287 rightstop
, truelab
, falselab
, extent
);
6291 if (input_line_pointer
!= stop
)
6292 as_bad (_("syntax error in structured control directive"));
6295 /* Handle the MRI IF pseudo-op. This may be a structured control
6296 directive, or it may be a regular assembler conditional, depending
6304 struct mri_control_info
*n
;
6306 /* A structured control directive must end with THEN with an
6307 optional qualifier. */
6308 s
= input_line_pointer
;
6309 /* We only accept '*' as introduction of comments if preceded by white space
6310 or at first column of a line (I think this can't actually happen here?)
6311 This is important when assembling:
6312 if d0 <ne> 12(a0,d0*2) then
6313 if d0 <ne> #CONST*20 then. */
6314 while (! (is_end_of_line
[(unsigned char) *s
]
6317 && (s
== input_line_pointer
6319 || *(s
-1) == '\t'))))
6322 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
6325 if (s
- input_line_pointer
> 1
6329 if (s
- input_line_pointer
< 3
6330 || strncasecmp (s
- 3, "THEN", 4) != 0)
6334 as_bad (_("missing then"));
6335 ignore_rest_of_line ();
6339 /* It's a conditional. */
6344 /* Since this might be a conditional if, this pseudo-op will be
6345 called even if we are supported to be ignoring input. Double
6346 check now. Clobber *input_line_pointer so that ignore_input
6347 thinks that this is not a special pseudo-op. */
6348 c
= *input_line_pointer
;
6349 *input_line_pointer
= 0;
6350 if (ignore_input ())
6352 *input_line_pointer
= c
;
6353 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6354 ++input_line_pointer
;
6355 demand_empty_rest_of_line ();
6358 *input_line_pointer
= c
;
6360 n
= push_mri_control (mri_if
);
6362 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
6363 n
->next
, s
[1] == '.' ? s
[2] : '\0');
6366 input_line_pointer
= s
+ 3;
6368 input_line_pointer
= s
+ 1;
6372 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6373 ++input_line_pointer
;
6376 demand_empty_rest_of_line ();
6379 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6380 structured IF, associate the ELSE with the IF. Otherwise, assume
6381 it is a conditional else. */
6384 s_mri_else (int qual
)
6391 && (mri_control_stack
== NULL
6392 || mri_control_stack
->type
!= mri_if
6393 || mri_control_stack
->else_seen
))
6399 c
= *input_line_pointer
;
6400 *input_line_pointer
= 0;
6401 if (ignore_input ())
6403 *input_line_pointer
= c
;
6404 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6405 ++input_line_pointer
;
6406 demand_empty_rest_of_line ();
6409 *input_line_pointer
= c
;
6411 if (mri_control_stack
== NULL
6412 || mri_control_stack
->type
!= mri_if
6413 || mri_control_stack
->else_seen
)
6415 as_bad (_("else without matching if"));
6416 ignore_rest_of_line ();
6420 mri_control_stack
->else_seen
= 1;
6422 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->bottom
));
6423 q
[0] = TOLOWER (qual
);
6425 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6429 colon (mri_control_stack
->next
);
6433 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6434 ++input_line_pointer
;
6437 demand_empty_rest_of_line ();
6440 /* Handle the MRI ENDI pseudo-op. */
6443 s_mri_endi (int ignore ATTRIBUTE_UNUSED
)
6445 if (mri_control_stack
== NULL
6446 || mri_control_stack
->type
!= mri_if
)
6448 as_bad (_("endi without matching if"));
6449 ignore_rest_of_line ();
6453 /* ignore_input will not return true for ENDI, so we don't need to
6454 worry about checking it again here. */
6456 if (! mri_control_stack
->else_seen
)
6457 colon (mri_control_stack
->next
);
6458 colon (mri_control_stack
->bottom
);
6464 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6465 ++input_line_pointer
;
6468 demand_empty_rest_of_line ();
6471 /* Handle the MRI BREAK pseudo-op. */
6474 s_mri_break (int extent
)
6476 struct mri_control_info
*n
;
6480 n
= mri_control_stack
;
6482 && n
->type
!= mri_for
6483 && n
->type
!= mri_repeat
6484 && n
->type
!= mri_while
)
6488 as_bad (_("break outside of structured loop"));
6489 ignore_rest_of_line ();
6493 buf
= (char *) xmalloc (20 + strlen (n
->bottom
));
6494 ex
[0] = TOLOWER (extent
);
6496 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6502 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6503 ++input_line_pointer
;
6506 demand_empty_rest_of_line ();
6509 /* Handle the MRI NEXT pseudo-op. */
6512 s_mri_next (int extent
)
6514 struct mri_control_info
*n
;
6518 n
= mri_control_stack
;
6520 && n
->type
!= mri_for
6521 && n
->type
!= mri_repeat
6522 && n
->type
!= mri_while
)
6526 as_bad (_("next outside of structured loop"));
6527 ignore_rest_of_line ();
6531 buf
= (char *) xmalloc (20 + strlen (n
->next
));
6532 ex
[0] = TOLOWER (extent
);
6534 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6540 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6541 ++input_line_pointer
;
6544 demand_empty_rest_of_line ();
6547 /* Handle the MRI FOR pseudo-op. */
6550 s_mri_for (int qual
)
6552 const char *varstart
, *varstop
;
6553 const char *initstart
, *initstop
;
6554 const char *endstart
, *endstop
;
6555 const char *bystart
, *bystop
;
6559 struct mri_control_info
*n
;
6565 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6569 varstart
= input_line_pointer
;
6571 /* Look for the '='. */
6572 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6573 && *input_line_pointer
!= '=')
6574 ++input_line_pointer
;
6575 if (*input_line_pointer
!= '=')
6577 as_bad (_("missing ="));
6578 ignore_rest_of_line ();
6582 varstop
= input_line_pointer
;
6583 if (varstop
> varstart
6584 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6587 ++input_line_pointer
;
6589 initstart
= input_line_pointer
;
6591 /* Look for TO or DOWNTO. */
6594 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6596 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6597 && ! is_part_of_name (input_line_pointer
[2]))
6599 initstop
= input_line_pointer
;
6600 input_line_pointer
+= 2;
6603 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6604 && ! is_part_of_name (input_line_pointer
[6]))
6606 initstop
= input_line_pointer
;
6608 input_line_pointer
+= 6;
6611 ++input_line_pointer
;
6613 if (initstop
== NULL
)
6615 as_bad (_("missing to or downto"));
6616 ignore_rest_of_line ();
6619 if (initstop
> initstart
6620 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6624 endstart
= input_line_pointer
;
6626 /* Look for BY or DO. */
6629 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6631 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
6632 && ! is_part_of_name (input_line_pointer
[2]))
6634 endstop
= input_line_pointer
;
6636 input_line_pointer
+= 2;
6639 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6640 && (input_line_pointer
[2] == '.'
6641 || ! is_part_of_name (input_line_pointer
[2])))
6643 endstop
= input_line_pointer
;
6644 input_line_pointer
+= 2;
6647 ++input_line_pointer
;
6649 if (endstop
== NULL
)
6651 as_bad (_("missing do"));
6652 ignore_rest_of_line ();
6655 if (endstop
> endstart
6656 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
6662 bystop
= bystart
+ 2;
6667 bystart
= input_line_pointer
;
6671 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6673 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6674 && (input_line_pointer
[2] == '.'
6675 || ! is_part_of_name (input_line_pointer
[2])))
6677 bystop
= input_line_pointer
;
6678 input_line_pointer
+= 2;
6681 ++input_line_pointer
;
6685 as_bad (_("missing do"));
6686 ignore_rest_of_line ();
6689 if (bystop
> bystart
6690 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
6694 if (*input_line_pointer
!= '.')
6698 extent
= input_line_pointer
[1];
6699 input_line_pointer
+= 2;
6702 /* We have fully parsed the FOR operands. Now build the loop. */
6703 n
= push_mri_control (mri_for
);
6705 buf
= (char *) xmalloc (50 + (input_line_pointer
- varstart
));
6707 /* Move init,var. */
6714 *s
++ = TOLOWER (qual
);
6716 memcpy (s
, initstart
, initstop
- initstart
);
6717 s
+= initstop
- initstart
;
6719 memcpy (s
, varstart
, varstop
- varstart
);
6720 s
+= varstop
- varstart
;
6732 *s
++ = TOLOWER (qual
);
6734 memcpy (s
, endstart
, endstop
- endstart
);
6735 s
+= endstop
- endstart
;
6737 memcpy (s
, varstart
, varstop
- varstart
);
6738 s
+= varstop
- varstart
;
6743 ex
[0] = TOLOWER (extent
);
6746 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
6748 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
6751 /* Put together the add or sub instruction used by ENDF. */
6759 *s
++ = TOLOWER (qual
);
6761 memcpy (s
, bystart
, bystop
- bystart
);
6762 s
+= bystop
- bystart
;
6764 memcpy (s
, varstart
, varstop
- varstart
);
6765 s
+= varstop
- varstart
;
6771 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6772 ++input_line_pointer
;
6775 demand_empty_rest_of_line ();
6778 /* Handle the MRI ENDF pseudo-op. */
6781 s_mri_endf (int ignore ATTRIBUTE_UNUSED
)
6783 if (mri_control_stack
== NULL
6784 || mri_control_stack
->type
!= mri_for
)
6786 as_bad (_("endf without for"));
6787 ignore_rest_of_line ();
6791 colon (mri_control_stack
->next
);
6793 mri_assemble (mri_control_stack
->incr
);
6795 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
6796 mri_assemble (mri_control_stack
->incr
);
6798 free (mri_control_stack
->incr
);
6800 colon (mri_control_stack
->bottom
);
6806 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6807 ++input_line_pointer
;
6810 demand_empty_rest_of_line ();
6813 /* Handle the MRI REPEAT pseudo-op. */
6816 s_mri_repeat (int ignore ATTRIBUTE_UNUSED
)
6818 struct mri_control_info
*n
;
6820 n
= push_mri_control (mri_repeat
);
6824 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6825 ++input_line_pointer
;
6827 demand_empty_rest_of_line ();
6830 /* Handle the MRI UNTIL pseudo-op. */
6833 s_mri_until (int qual
)
6837 if (mri_control_stack
== NULL
6838 || mri_control_stack
->type
!= mri_repeat
)
6840 as_bad (_("until without repeat"));
6841 ignore_rest_of_line ();
6845 colon (mri_control_stack
->next
);
6847 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
6850 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
6851 mri_control_stack
->top
, '\0');
6853 colon (mri_control_stack
->bottom
);
6855 input_line_pointer
= s
;
6861 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6862 ++input_line_pointer
;
6865 demand_empty_rest_of_line ();
6868 /* Handle the MRI WHILE pseudo-op. */
6871 s_mri_while (int qual
)
6875 struct mri_control_info
*n
;
6877 s
= input_line_pointer
;
6878 /* We only accept '*' as introduction of comments if preceded by white space
6879 or at first column of a line (I think this can't actually happen here?)
6880 This is important when assembling:
6881 while d0 <ne> 12(a0,d0*2) do
6882 while d0 <ne> #CONST*20 do. */
6883 while (! (is_end_of_line
[(unsigned char) *s
]
6886 && (s
== input_line_pointer
6888 || *(s
-1) == '\t'))))
6891 while (*s
== ' ' || *s
== '\t')
6893 if (s
- input_line_pointer
> 1
6896 if (s
- input_line_pointer
< 2
6897 || strncasecmp (s
- 1, "DO", 2) != 0)
6899 as_bad (_("missing do"));
6900 ignore_rest_of_line ();
6904 n
= push_mri_control (mri_while
);
6908 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
6909 s
[1] == '.' ? s
[2] : '\0');
6911 input_line_pointer
= s
+ 1;
6912 if (*input_line_pointer
== '.')
6913 input_line_pointer
+= 2;
6917 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6918 ++input_line_pointer
;
6921 demand_empty_rest_of_line ();
6924 /* Handle the MRI ENDW pseudo-op. */
6927 s_mri_endw (int ignore ATTRIBUTE_UNUSED
)
6931 if (mri_control_stack
== NULL
6932 || mri_control_stack
->type
!= mri_while
)
6934 as_bad (_("endw without while"));
6935 ignore_rest_of_line ();
6939 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->next
));
6940 sprintf (buf
, "bra %s", mri_control_stack
->next
);
6944 colon (mri_control_stack
->bottom
);
6950 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6951 ++input_line_pointer
;
6954 demand_empty_rest_of_line ();
6957 /* Parse a .cpu directive. */
6960 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED
)
6967 as_bad (_("already assembled instructions"));
6968 ignore_rest_of_line ();
6972 name
= input_line_pointer
;
6973 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
6974 input_line_pointer
++;
6975 saved_char
= *input_line_pointer
;
6976 *input_line_pointer
= 0;
6978 m68k_set_cpu (name
, 1, 0);
6980 *input_line_pointer
= saved_char
;
6981 demand_empty_rest_of_line ();
6985 /* Parse a .arch directive. */
6988 s_m68k_arch (int ignored ATTRIBUTE_UNUSED
)
6995 as_bad (_("already assembled instructions"));
6996 ignore_rest_of_line ();
7000 name
= input_line_pointer
;
7001 while (*input_line_pointer
&& *input_line_pointer
!= ','
7002 && !ISSPACE (*input_line_pointer
))
7003 input_line_pointer
++;
7004 saved_char
= *input_line_pointer
;
7005 *input_line_pointer
= 0;
7007 if (m68k_set_arch (name
, 1, 0))
7009 /* Scan extensions. */
7012 *input_line_pointer
++ = saved_char
;
7013 if (!*input_line_pointer
|| ISSPACE (*input_line_pointer
))
7015 name
= input_line_pointer
;
7016 while (*input_line_pointer
&& *input_line_pointer
!= ','
7017 && !ISSPACE (*input_line_pointer
))
7018 input_line_pointer
++;
7019 saved_char
= *input_line_pointer
;
7020 *input_line_pointer
= 0;
7022 while (m68k_set_extension (name
, 1, 0));
7025 *input_line_pointer
= saved_char
;
7026 demand_empty_rest_of_line ();
7030 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7031 if none is found, the caller is responsible for emitting an error
7032 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7033 cpu name, if it begins with a '6' (possibly skipping an intervening
7034 'c'. We also allow a 'c' in the same place. if NEGATED is
7035 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7036 the option is indeed negated. */
7038 static const struct m68k_cpu
*
7039 m68k_lookup_cpu (const char *arg
, const struct m68k_cpu
*table
,
7040 int allow_m
, int *negated
)
7042 /* allow negated value? */
7047 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
7054 /* Remove 'm' or 'mc' prefix from 68k variants. */
7061 else if (arg
[1] == 'c' && arg
[2] == '6')
7065 else if (arg
[0] == 'c' && arg
[1] == '6')
7068 for (; table
->name
; table
++)
7069 if (!strcmp (arg
, table
->name
))
7071 if (table
->alias
< -1 || table
->alias
> 1)
7072 as_bad (_("`%s' is deprecated, use `%s'"),
7073 table
->name
, table
[table
->alias
< 0 ? 1 : -1].name
);
7079 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7082 m68k_set_cpu (char const *name
, int allow_m
, int silent
)
7084 const struct m68k_cpu
*cpu
;
7086 cpu
= m68k_lookup_cpu (name
, m68k_cpus
, allow_m
, NULL
);
7091 as_bad (_("cpu `%s' unrecognized"), name
);
7095 if (selected_cpu
&& selected_cpu
!= cpu
)
7097 as_bad (_("already selected `%s' processor"),
7098 selected_cpu
->name
);
7105 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7108 m68k_set_arch (char const *name
, int allow_m
, int silent
)
7110 const struct m68k_cpu
*arch
;
7112 arch
= m68k_lookup_cpu (name
, m68k_archs
, allow_m
, NULL
);
7117 as_bad (_("architecture `%s' unrecognized"), name
);
7121 if (selected_arch
&& selected_arch
!= arch
)
7123 as_bad (_("already selected `%s' architecture"),
7124 selected_arch
->name
);
7128 selected_arch
= arch
;
7132 /* Set the architecture extension, issuing errors if it is
7133 unrecognized, or invalid */
7136 m68k_set_extension (char const *name
, int allow_m
, int silent
)
7139 const struct m68k_cpu
*ext
;
7141 ext
= m68k_lookup_cpu (name
, m68k_extensions
, allow_m
, &negated
);
7146 as_bad (_("extension `%s' unrecognized"), name
);
7151 not_current_architecture
|= ext
->arch
;
7153 current_architecture
|= ext
->arch
;
7158 Invocation line includes a switch not recognized by the base assembler.
7162 const char *md_shortopts
= "lSA:m:kQ:V";
7164 const char *md_shortopts
= "lSA:m:k";
7167 struct option md_longopts
[] = {
7168 #define OPTION_PIC (OPTION_MD_BASE)
7169 {"pic", no_argument
, NULL
, OPTION_PIC
},
7170 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7171 {"register-prefix-optional", no_argument
, NULL
,
7172 OPTION_REGISTER_PREFIX_OPTIONAL
},
7173 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7174 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
7175 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7176 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
7177 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7178 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
7179 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7180 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
7181 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7182 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
7183 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7184 {"pcrel", no_argument
, NULL
, OPTION_PCREL
},
7185 {NULL
, no_argument
, NULL
, 0}
7187 size_t md_longopts_size
= sizeof (md_longopts
);
7190 md_parse_option (int c
, char *arg
)
7194 case 'l': /* -l means keep external to 2 bit offset
7195 rather than 16 bit one. */
7196 flag_short_refs
= 1;
7199 case 'S': /* -S means that jbsr's always turn into
7201 flag_long_jumps
= 1;
7204 case OPTION_PCREL
: /* --pcrel means never turn PC-relative
7205 branches into absolute jumps. */
7206 flag_keep_pcrel
= 1;
7212 break; /* -pic, Position Independent Code. */
7214 case OPTION_REGISTER_PREFIX_OPTIONAL
:
7215 flag_reg_prefix_optional
= 1;
7216 reg_prefix_optional_seen
= 1;
7219 /* -V: SVR4 argument to print version ID. */
7221 print_version_id ();
7224 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7225 should be emitted or not. FIXME: Not implemented. */
7229 case OPTION_BITWISE_OR
:
7234 n
= (char *) xmalloc (strlen (m68k_comment_chars
) + 1);
7236 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
7240 m68k_comment_chars
= n
;
7244 case OPTION_BASE_SIZE_DEFAULT_16
:
7245 m68k_index_width_default
= SIZE_WORD
;
7248 case OPTION_BASE_SIZE_DEFAULT_32
:
7249 m68k_index_width_default
= SIZE_LONG
;
7252 case OPTION_DISP_SIZE_DEFAULT_16
:
7254 m68k_rel32_from_cmdline
= 1;
7257 case OPTION_DISP_SIZE_DEFAULT_32
:
7259 m68k_rel32_from_cmdline
= 1;
7264 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7267 /* Intentional fall-through. */
7269 if (!strncmp (arg
, "arch=", 5))
7270 m68k_set_arch (arg
+ 5, 1, 0);
7271 else if (!strncmp (arg
, "cpu=", 4))
7272 m68k_set_cpu (arg
+ 4, 1, 0);
7273 else if (m68k_set_extension (arg
, 0, 1))
7275 else if (m68k_set_arch (arg
, 0, 1))
7277 else if (m68k_set_cpu (arg
, 0, 1))
7290 /* Setup tables from the selected arch and/or cpu */
7293 m68k_init_arch (void)
7295 if (not_current_architecture
& current_architecture
)
7297 as_bad (_("architecture features both enabled and disabled"));
7298 not_current_architecture
&= ~current_architecture
;
7302 current_architecture
|= selected_arch
->arch
;
7303 control_regs
= selected_arch
->control_regs
;
7306 current_architecture
|= selected_cpu
->arch
;
7308 current_architecture
&= ~not_current_architecture
;
7310 if ((current_architecture
& (cfloat
| m68881
)) == (cfloat
| m68881
))
7312 /* Determine which float is really meant. */
7313 if (current_architecture
& (m68k_mask
& ~m68881
))
7314 current_architecture
^= cfloat
;
7316 current_architecture
^= m68881
;
7321 control_regs
= selected_cpu
->control_regs
;
7322 if (current_architecture
& ~selected_cpu
->arch
)
7324 as_bad (_("selected processor does not have all features of selected architecture"));
7325 current_architecture
7326 = selected_cpu
->arch
& ~not_current_architecture
;
7330 if ((current_architecture
& m68k_mask
)
7331 && (current_architecture
& ~m68k_mask
))
7333 as_bad (_ ("m68k and cf features both selected"));
7334 if (current_architecture
& m68k_mask
)
7335 current_architecture
&= m68k_mask
;
7337 current_architecture
&= ~m68k_mask
;
7340 /* Permit m68881 specification with all cpus; those that can't work
7341 with a coprocessor could be doing emulation. */
7342 if (current_architecture
& m68851
)
7344 if (current_architecture
& m68040
)
7345 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7347 /* What other incompatibilities could we check for? */
7349 if (cpu_of_arch (current_architecture
) < m68020
7350 || arch_coldfire_p (current_architecture
))
7351 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
7357 md_show_usage (FILE *stream
)
7359 const char *default_cpu
= TARGET_CPU
;
7361 unsigned int default_arch
;
7363 /* Get the canonical name for the default target CPU. */
7364 if (*default_cpu
== 'm')
7366 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7368 if (strcasecmp (default_cpu
, m68k_cpus
[i
].name
) == 0)
7370 default_arch
= m68k_cpus
[i
].arch
;
7371 while (m68k_cpus
[i
].alias
> 0)
7373 while (m68k_cpus
[i
].alias
< 0)
7375 default_cpu
= m68k_cpus
[i
].name
;
7379 fprintf (stream
, _("\
7380 -march=<arch> set architecture\n\
7381 -mcpu=<cpu> set cpu [default %s]\n\
7383 for (i
= 0; m68k_extensions
[i
].name
; i
++)
7384 fprintf (stream
, _("\
7385 -m[no-]%-16s enable/disable%s architecture extension\n\
7386 "), m68k_extensions
[i
].name
,
7387 m68k_extensions
[i
].alias
> 0 ? " ColdFire"
7388 : m68k_extensions
[i
].alias
< 0 ? " m68k" : "");
7390 fprintf (stream
, _("\
7391 -l use 1 word for refs to undefined symbols [default 2]\n\
7392 -pic, -k generate position independent code\n\
7393 -S turn jbsr into jsr\n\
7394 --pcrel never turn PC-relative branches into absolute jumps\n\
7395 --register-prefix-optional\n\
7396 recognize register names without prefix character\n\
7397 --bitwise-or do not treat `|' as a comment character\n\
7398 --base-size-default-16 base reg without size is 16 bits\n\
7399 --base-size-default-32 base reg without size is 32 bits (default)\n\
7400 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7401 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7404 fprintf (stream
, _("Architecture variants are: "));
7405 for (i
= 0; m68k_archs
[i
].name
; i
++)
7408 fprintf (stream
, " | ");
7409 fprintf (stream
, m68k_archs
[i
].name
);
7411 fprintf (stream
, "\n");
7413 fprintf (stream
, _("Processor variants are: "));
7414 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7417 fprintf (stream
, " | ");
7418 fprintf (stream
, m68k_cpus
[i
].name
);
7420 fprintf (stream
, _("\n"));
7425 /* TEST2: Test md_assemble() */
7426 /* Warning, this routine probably doesn't work anymore. */
7430 struct m68k_it the_ins
;
7438 if (!gets (buf
) || !*buf
)
7440 if (buf
[0] == '|' || buf
[1] == '.')
7442 for (cp
= buf
; *cp
; cp
++)
7447 memset (&the_ins
, '\0', sizeof (the_ins
));
7448 m68k_ip (&the_ins
, buf
);
7451 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
7455 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
7456 for (n
= 0; n
< the_ins
.numo
; n
++)
7457 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
7459 print_the_insn (&the_ins
.opcode
[0], stdout
);
7460 (void) putchar ('\n');
7462 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
7464 if (the_ins
.operands
[n
].error
)
7466 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
7469 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
,
7470 the_ins
.operands
[n
].reg
);
7471 if (the_ins
.operands
[n
].b_const
)
7472 printf ("Constant: '%.*s', ",
7473 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
,
7474 the_ins
.operands
[n
].b_const
);
7475 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
,
7476 the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
7477 if (the_ins
.operands
[n
].b_iadd
)
7478 printf ("Iadd: '%.*s',",
7479 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
,
7480 the_ins
.operands
[n
].b_iadd
);
7489 is_label (char *str
)
7493 while (*str
&& *str
!= ' ')
7495 if (str
[-1] == ':' || str
[1] == '=')
7502 /* Possible states for relaxation:
7504 0 0 branch offset byte (bra, etc)
7508 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7512 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7519 /* We have no need to default values of symbols. */
7522 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7527 /* Round up a section size to the appropriate boundary. */
7529 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7532 /* For a.out, force the section size to be aligned. If we don't do
7533 this, BFD will align it for us, but it will not write out the
7534 final bytes of the section. This may be a bug in BFD, but it is
7535 easier to fix it here since that is how the other a.out targets
7539 align
= bfd_get_section_alignment (stdoutput
, segment
);
7540 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7546 /* Exactly what point is a PC-relative offset relative TO?
7547 On the 68k, it is relative to the address of the first extension
7548 word. The difference between the addresses of the offset and the
7549 first extension word is stored in fx_pcrel_adjust. */
7551 md_pcrel_from (fixS
*fixP
)
7555 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7556 sign extend the value here. */
7557 adjust
= ((fixP
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80;
7560 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
7565 m68k_elf_final_processing (void)
7569 if (arch_coldfire_fpu (current_architecture
))
7570 flags
|= EF_M68K_CFV4E
;
7571 /* Set file-specific flags if this is a cpu32 processor. */
7572 if (cpu_of_arch (current_architecture
) & cpu32
)
7573 flags
|= EF_M68K_CPU32
;
7574 else if (cpu_of_arch (current_architecture
) & fido_a
)
7575 flags
|= EF_M68K_FIDO
;
7576 else if ((cpu_of_arch (current_architecture
) & m68000up
)
7577 && !(cpu_of_arch (current_architecture
) & m68020up
))
7578 flags
|= EF_M68K_M68000
;
7580 if (current_architecture
& mcfisa_a
)
7582 static const unsigned isa_features
[][2] =
7584 {EF_M68K_CF_ISA_A_NODIV
, mcfisa_a
},
7585 {EF_M68K_CF_ISA_A
, mcfisa_a
|mcfhwdiv
},
7586 {EF_M68K_CF_ISA_A_PLUS
,mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfusp
},
7587 {EF_M68K_CF_ISA_B_NOUSP
,mcfisa_a
|mcfisa_b
|mcfhwdiv
},
7588 {EF_M68K_CF_ISA_B
, mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfusp
},
7591 static const unsigned mac_features
[][2] =
7593 {EF_M68K_CF_MAC
, mcfmac
},
7594 {EF_M68K_CF_EMAC
, mcfemac
},
7600 pattern
= (current_architecture
7601 & (mcfisa_a
|mcfisa_aa
|mcfisa_b
|mcfhwdiv
|mcfusp
));
7602 for (ix
= 0; isa_features
[ix
][1]; ix
++)
7604 if (pattern
== isa_features
[ix
][1])
7606 flags
|= isa_features
[ix
][0];
7610 if (!isa_features
[ix
][1])
7613 as_warn (_("Not a defined coldfire architecture"));
7617 if (current_architecture
& cfloat
)
7618 flags
|= EF_M68K_CF_FLOAT
| EF_M68K_CFV4E
;
7620 pattern
= current_architecture
& (mcfmac
|mcfemac
);
7623 for (ix
= 0; mac_features
[ix
][1]; ix
++)
7625 if (pattern
== mac_features
[ix
][1])
7627 flags
|= mac_features
[ix
][0];
7631 if (!mac_features
[ix
][1])
7636 elf_elfheader (stdoutput
)->e_flags
|= flags
;
7641 tc_m68k_regname_to_dw2regnum (char *regname
)
7643 unsigned int regnum
;
7644 static const char *const regnames
[] =
7646 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7647 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7648 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7652 for (regnum
= 0; regnum
< ARRAY_SIZE (regnames
); regnum
++)
7653 if (strcmp (regname
, regnames
[regnum
]) == 0)
7660 tc_m68k_frame_initial_instructions (void)
7662 static int sp_regno
= -1;
7665 sp_regno
= tc_m68k_regname_to_dw2regnum ("sp");
7667 cfi_add_CFA_def_cfa (sp_regno
, -DWARF2_CIE_DATA_ALIGNMENT
);
7668 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, DWARF2_CIE_DATA_ALIGNMENT
);