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* config/atof-vax.c (md_atof): Fix comparison inside know().
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
177 0
178 };
179 static const enum m68k_register mcf5206_ctrl[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
181 0
182 };
183 static const enum m68k_register mcf5208_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
185 0
186 };
187 static const enum m68k_register mcf5210a_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
189 0
190 };
191 static const enum m68k_register mcf5213_ctrl[] = {
192 VBR, RAMBAR, RAMBAR1, FLASHBAR,
193 0
194 };
195 static const enum m68k_register mcf5216_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
197 0
198 };
199 static const enum m68k_register mcf52223_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
201 0
202 };
203 static const enum m68k_register mcf52235_ctrl[] = {
204 VBR, FLASHBAR, RAMBAR, RAMBAR1,
205 0
206 };
207 static const enum m68k_register mcf5225_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
209 0
210 };
211 static const enum m68k_register mcf5235_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
213 0
214 };
215 static const enum m68k_register mcf5249_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
217 0
218 };
219 static const enum m68k_register mcf5250_ctrl[] = {
220 VBR,
221 0
222 };
223 static const enum m68k_register mcf5253_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR,
225 0
226 };
227 static const enum m68k_register mcf5271_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
229 0
230 };
231 static const enum m68k_register mcf5272_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
233 0
234 };
235 static const enum m68k_register mcf5275_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
237 0
238 };
239 static const enum m68k_register mcf5282_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
241 0
242 };
243 static const enum m68k_register mcf5307_ctrl[] = {
244 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
245 0
246 };
247 static const enum m68k_register mcf5329_ctrl[] = {
248 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
249 0
250 };
251 static const enum m68k_register mcf5373_ctrl[] = {
252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
253 0
254 };
255 static const enum m68k_register mcfv4e_ctrl[] = {
256 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
257 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
258 MBAR, SECMBAR,
259 MPCR /* Multiprocessor Control register */,
260 EDRAMBAR /* Embedded DRAM Base Address Register */,
261 /* Permutation control registers. */
262 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
263 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
264 /* Legacy names */
265 TC /* ASID */, BUSCR /* MMUBAR */,
266 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
267 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
268 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
269 0
270 };
271 static const enum m68k_register mcf5475_ctrl[] = {
272 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
273 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
274 /* Legacy names */
275 TC /* ASID */, BUSCR /* MMUBAR */,
276 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
277 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
278 0
279 };
280 static const enum m68k_register mcf5485_ctrl[] = {
281 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
282 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
283 /* Legacy names */
284 TC /* ASID */, BUSCR /* MMUBAR */,
285 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
286 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
287 0
288 };
289 static const enum m68k_register fido_ctrl[] = {
290 SFC, DFC, USP, VBR, CAC, MBB,
291 0
292 };
293 #define cpu32_ctrl m68010_ctrl
294
295 static const enum m68k_register *control_regs;
296
297 /* Internal form of a 68020 instruction. */
298 struct m68k_it
299 {
300 const char *error;
301 const char *args; /* List of opcode info. */
302 int numargs;
303
304 int numo; /* Number of shorts in opcode. */
305 short opcode[11];
306
307 struct m68k_op operands[6];
308
309 int nexp; /* Number of exprs in use. */
310 struct m68k_exp exprs[4];
311
312 int nfrag; /* Number of frags we have to produce. */
313 struct
314 {
315 int fragoff; /* Where in the current opcode the frag ends. */
316 symbolS *fadd;
317 offsetT foff;
318 int fragty;
319 }
320 fragb[4];
321
322 int nrel; /* Num of reloc strucs in use. */
323 struct
324 {
325 int n;
326 expressionS exp;
327 char wid;
328 char pcrel;
329 /* In a pc relative address the difference between the address
330 of the offset and the address that the offset is relative
331 to. This depends on the addressing mode. Basically this
332 is the value to put in the offset field to address the
333 first byte of the offset, without regarding the special
334 significance of some values (in the branch instruction, for
335 example). */
336 int pcrel_fix;
337 #ifdef OBJ_ELF
338 /* Whether this expression needs special pic relocation, and if
339 so, which. */
340 enum pic_relocation pic_reloc;
341 #endif
342 }
343 reloc[5]; /* Five is enough??? */
344 };
345
346 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
347 #define float_of_arch(x) ((x) & mfloat)
348 #define mmu_of_arch(x) ((x) & mmmu)
349 #define arch_coldfire_p(x) ((x) & mcfisa_a)
350 #define arch_coldfire_fpu(x) ((x) & cfloat)
351
352 /* Macros for determining if cpu supports a specific addressing mode. */
353 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
354
355 static struct m68k_it the_ins; /* The instruction being assembled. */
356
357 #define op(ex) ((ex)->exp.X_op)
358 #define adds(ex) ((ex)->exp.X_add_symbol)
359 #define subs(ex) ((ex)->exp.X_op_symbol)
360 #define offs(ex) ((ex)->exp.X_add_number)
361
362 /* Macros for adding things to the m68k_it struct. */
363 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
364
365 /* Like addword, but goes BEFORE general operands. */
366
367 static void
368 insop (int w, const struct m68k_incant *opcode)
369 {
370 int z;
371 for (z = the_ins.numo; z > opcode->m_codenum; --z)
372 the_ins.opcode[z] = the_ins.opcode[z - 1];
373 for (z = 0; z < the_ins.nrel; z++)
374 the_ins.reloc[z].n += 2;
375 for (z = 0; z < the_ins.nfrag; z++)
376 the_ins.fragb[z].fragoff++;
377 the_ins.opcode[opcode->m_codenum] = w;
378 the_ins.numo++;
379 }
380
381 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
382 Blecch. */
383 static void
384 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
385 {
386 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
387 ? the_ins.numo * 2 - 1
388 : (width == 'b'
389 ? the_ins.numo * 2 + 1
390 : the_ins.numo * 2));
391 the_ins.reloc[the_ins.nrel].exp = exp->exp;
392 the_ins.reloc[the_ins.nrel].wid = width;
393 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
394 #ifdef OBJ_ELF
395 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
396 #endif
397 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
398 }
399
400 /* Cause an extra frag to be generated here, inserting up to 10 bytes
401 (that value is chosen in the frag_var call in md_assemble). TYPE
402 is the subtype of the frag to be generated; its primary type is
403 rs_machine_dependent.
404
405 The TYPE parameter is also used by md_convert_frag_1 and
406 md_estimate_size_before_relax. The appropriate type of fixup will
407 be emitted by md_convert_frag_1.
408
409 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
410 static void
411 add_frag (symbolS *add, offsetT off, int type)
412 {
413 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
414 the_ins.fragb[the_ins.nfrag].fadd = add;
415 the_ins.fragb[the_ins.nfrag].foff = off;
416 the_ins.fragb[the_ins.nfrag++].fragty = type;
417 }
418
419 #define isvar(ex) \
420 (op (ex) != O_constant && op (ex) != O_big)
421
422 static char *crack_operand (char *str, struct m68k_op *opP);
423 static int get_num (struct m68k_exp *exp, int ok);
424 static int reverse_16_bits (int in);
425 static int reverse_8_bits (int in);
426 static void install_gen_operand (int mode, int val);
427 static void install_operand (int mode, int val);
428 static void s_bss (int);
429 static void s_data1 (int);
430 static void s_data2 (int);
431 static void s_even (int);
432 static void s_proc (int);
433 static void s_chip (int);
434 static void s_fopt (int);
435 static void s_opt (int);
436 static void s_reg (int);
437 static void s_restore (int);
438 static void s_save (int);
439 static void s_mri_if (int);
440 static void s_mri_else (int);
441 static void s_mri_endi (int);
442 static void s_mri_break (int);
443 static void s_mri_next (int);
444 static void s_mri_for (int);
445 static void s_mri_endf (int);
446 static void s_mri_repeat (int);
447 static void s_mri_until (int);
448 static void s_mri_while (int);
449 static void s_mri_endw (int);
450 static void s_m68k_cpu (int);
451 static void s_m68k_arch (int);
452
453 struct m68k_cpu
454 {
455 unsigned long arch; /* Architecture features. */
456 const enum m68k_register *control_regs; /* Control regs on chip */
457 const char *name; /* Name */
458 int alias; /* Alias for a cannonical name. If 1, then
459 succeeds canonical name, if -1 then
460 succeeds canonical name, if <-1 ||>1 this is a
461 deprecated name, and the next/previous name
462 should be used. */
463 };
464
465 /* We hold flags for features explicitly enabled and explicitly
466 disabled. */
467 static int current_architecture;
468 static int not_current_architecture;
469 static const struct m68k_cpu *selected_arch;
470 static const struct m68k_cpu *selected_cpu;
471 static int initialized;
472
473 /* Architecture models. */
474 static const struct m68k_cpu m68k_archs[] =
475 {
476 {m68000, m68000_ctrl, "68000", 0},
477 {m68010, m68010_ctrl, "68010", 0},
478 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
479 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
480 {m68040, m68040_ctrl, "68040", 0},
481 {m68060, m68060_ctrl, "68060", 0},
482 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
483 {fido_a, fido_ctrl, "fidoa", 0},
484 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
485 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
486 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
487 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
488 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
489 {0,0,NULL, 0}
490 };
491
492 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
493 for either. */
494 static const struct m68k_cpu m68k_extensions[] =
495 {
496 {m68851, NULL, "68851", -1},
497 {m68881, NULL, "68881", -1},
498 {m68881, NULL, "68882", -1},
499
500 {cfloat|m68881, NULL, "float", 0},
501
502 {mcfhwdiv, NULL, "div", 1},
503 {mcfusp, NULL, "usp", 1},
504 {mcfmac, NULL, "mac", 1},
505 {mcfemac, NULL, "emac", 1},
506
507 {0,NULL,NULL, 0}
508 };
509
510 /* Processor list */
511 static const struct m68k_cpu m68k_cpus[] =
512 {
513 {m68000, m68000_ctrl, "68000", 0},
514 {m68000, m68000_ctrl, "68ec000", 1},
515 {m68000, m68000_ctrl, "68hc000", 1},
516 {m68000, m68000_ctrl, "68hc001", 1},
517 {m68000, m68000_ctrl, "68008", 1},
518 {m68000, m68000_ctrl, "68302", 1},
519 {m68000, m68000_ctrl, "68306", 1},
520 {m68000, m68000_ctrl, "68307", 1},
521 {m68000, m68000_ctrl, "68322", 1},
522 {m68000, m68000_ctrl, "68356", 1},
523 {m68010, m68010_ctrl, "68010", 0},
524 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
525 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
526 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
527 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
528 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
529 {m68040, m68040_ctrl, "68040", 0},
530 {m68040, m68040_ctrl, "68ec040", 1},
531 {m68060, m68060_ctrl, "68060", 0},
532 {m68060, m68060_ctrl, "68ec060", 1},
533
534 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
535 {cpu32|m68881, cpu32_ctrl, "68330", 1},
536 {cpu32|m68881, cpu32_ctrl, "68331", 1},
537 {cpu32|m68881, cpu32_ctrl, "68332", 1},
538 {cpu32|m68881, cpu32_ctrl, "68333", 1},
539 {cpu32|m68881, cpu32_ctrl, "68334", 1},
540 {cpu32|m68881, cpu32_ctrl, "68336", 1},
541 {cpu32|m68881, cpu32_ctrl, "68340", 1},
542 {cpu32|m68881, cpu32_ctrl, "68341", 1},
543 {cpu32|m68881, cpu32_ctrl, "68349", 1},
544 {cpu32|m68881, cpu32_ctrl, "68360", 1},
545
546 {mcfisa_a, mcf_ctrl, "5200", 0},
547 {mcfisa_a, mcf_ctrl, "5202", 1},
548 {mcfisa_a, mcf_ctrl, "5204", 1},
549 {mcfisa_a, mcf5206_ctrl, "5206", 1},
550
551 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
552
553 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
554 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
555
556 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
557 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
558
559 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
560 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
561 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
562
563 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
564 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
565 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
566
567 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
568 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
569
570 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
571 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
572 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
573 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
574
575 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
576 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
577
578 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
579 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
580 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
581 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
582 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
583
584 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
585 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
586 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
587
588 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
590
591 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
592
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
594 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
595
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
599 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
600
601 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
602
603 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
604 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
607
608 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
609 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
610 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
611
612 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
613
614 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
615 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
616 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
617 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
618 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
619 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
620 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
621
622 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
623 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
624 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
625 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
626 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
627 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
628 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
629
630 {fido_a, fido_ctrl, "fidoa", 0},
631 {fido_a, fido_ctrl, "fido", 1},
632
633 {0,NULL,NULL, 0}
634 };
635
636 static const struct m68k_cpu *m68k_lookup_cpu
637 (const char *, const struct m68k_cpu *, int, int *);
638 static int m68k_set_arch (const char *, int, int);
639 static int m68k_set_cpu (const char *, int, int);
640 static int m68k_set_extension (const char *, int, int);
641 static void m68k_init_arch (void);
642
643 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
644 architecture and we have a lot of relaxation modes. */
645
646 /* Macros used in the relaxation code. */
647 #define TAB(x,y) (((x) << 2) + (y))
648 #define TABTYPE(x) ((x) >> 2)
649
650 /* Relaxation states. */
651 #define BYTE 0
652 #define SHORT 1
653 #define LONG 2
654 #define SZ_UNDEF 3
655
656 /* Here are all the relaxation modes we support. First we can relax ordinary
657 branches. On 68020 and higher and on CPU32 all branch instructions take
658 three forms, so on these CPUs all branches always remain as such. When we
659 have to expand to the LONG form on a 68000, though, we substitute an
660 absolute jump instead. This is a direct replacement for unconditional
661 branches and a branch over a jump for conditional branches. However, if the
662 user requires PIC and disables this with --pcrel, we can only relax between
663 BYTE and SHORT forms, punting if that isn't enough. This gives us four
664 different relaxation modes for branches: */
665
666 #define BRANCHBWL 0 /* Branch byte, word, or long. */
667 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
668 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
669 #define BRANCHBW 3 /* Branch byte or word. */
670
671 /* We also relax coprocessor branches and DBcc's. All CPUs that support
672 coprocessor branches support them in word and long forms, so we have only
673 one relaxation mode for them. DBcc's are word only on all CPUs. We can
674 relax them to the LONG form with a branch-around sequence. This sequence
675 can use a long branch (if available) or an absolute jump (if acceptable).
676 This gives us two relaxation modes. If long branches are not available and
677 absolute jumps are not acceptable, we don't relax DBcc's. */
678
679 #define FBRANCH 4 /* Coprocessor branch. */
680 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
681 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
682
683 /* That's all for instruction relaxation. However, we also relax PC-relative
684 operands. Specifically, we have three operand relaxation modes. On the
685 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
686 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
687 two. Also PC+displacement+index operands in their simple form (with a non-
688 suppressed index without memory indirection) are supported on all CPUs, but
689 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
690 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
691 form of the PC+displacement+index operand. Finally, some absolute operands
692 can be relaxed down to 16-bit PC-relative. */
693
694 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
695 #define PCINDEX 8 /* PC + displacement + index. */
696 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
697
698 /* Note that calls to frag_var need to specify the maximum expansion
699 needed; this is currently 10 bytes for DBCC. */
700
701 /* The fields are:
702 How far Forward this mode will reach:
703 How far Backward this mode will reach:
704 How many bytes this mode will add to the size of the frag
705 Which mode to go to if the offset won't fit in this one
706
707 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
708 relax_typeS md_relax_table[] =
709 {
710 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
711 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
712 { 0, 0, 4, 0 },
713 { 1, 1, 0, 0 },
714
715 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
716 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
717 { 0, 0, 4, 0 },
718 { 1, 1, 0, 0 },
719
720 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
721 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
722 { 0, 0, 6, 0 },
723 { 1, 1, 0, 0 },
724
725 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
726 { 0, 0, 2, 0 },
727 { 1, 1, 0, 0 },
728 { 1, 1, 0, 0 },
729
730 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
731 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
732 { 0, 0, 4, 0 },
733 { 1, 1, 0, 0 },
734
735 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
736 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
737 { 0, 0, 10, 0 },
738 { 1, 1, 0, 0 },
739
740 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
741 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
742 { 0, 0, 10, 0 },
743 { 1, 1, 0, 0 },
744
745 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
746 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
747 { 0, 0, 6, 0 },
748 { 1, 1, 0, 0 },
749
750 { 125, -130, 0, TAB (PCINDEX, SHORT) },
751 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
752 { 0, 0, 4, 0 },
753 { 1, 1, 0, 0 },
754
755 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
756 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
757 { 0, 0, 4, 0 },
758 { 1, 1, 0, 0 },
759 };
760
761 /* These are the machine dependent pseudo-ops. These are included so
762 the assembler can work on the output from the SUN C compiler, which
763 generates these. */
764
765 /* This table describes all the machine specific pseudo-ops the assembler
766 has to support. The fields are:
767 pseudo-op name without dot
768 function to call to execute this pseudo-op
769 Integer arg to pass to the function. */
770 const pseudo_typeS md_pseudo_table[] =
771 {
772 {"data1", s_data1, 0},
773 {"data2", s_data2, 0},
774 {"bss", s_bss, 0},
775 {"even", s_even, 0},
776 {"skip", s_space, 0},
777 {"proc", s_proc, 0},
778 #if defined (TE_SUN3) || defined (OBJ_ELF)
779 {"align", s_align_bytes, 0},
780 #endif
781 #ifdef OBJ_ELF
782 {"swbeg", s_ignore, 0},
783 #endif
784 {"extend", float_cons, 'x'},
785 {"ldouble", float_cons, 'x'},
786
787 {"arch", s_m68k_arch, 0},
788 {"cpu", s_m68k_cpu, 0},
789
790 /* The following pseudo-ops are supported for MRI compatibility. */
791 {"chip", s_chip, 0},
792 {"comline", s_space, 1},
793 {"fopt", s_fopt, 0},
794 {"mask2", s_ignore, 0},
795 {"opt", s_opt, 0},
796 {"reg", s_reg, 0},
797 {"restore", s_restore, 0},
798 {"save", s_save, 0},
799
800 {"if", s_mri_if, 0},
801 {"if.b", s_mri_if, 'b'},
802 {"if.w", s_mri_if, 'w'},
803 {"if.l", s_mri_if, 'l'},
804 {"else", s_mri_else, 0},
805 {"else.s", s_mri_else, 's'},
806 {"else.l", s_mri_else, 'l'},
807 {"endi", s_mri_endi, 0},
808 {"break", s_mri_break, 0},
809 {"break.s", s_mri_break, 's'},
810 {"break.l", s_mri_break, 'l'},
811 {"next", s_mri_next, 0},
812 {"next.s", s_mri_next, 's'},
813 {"next.l", s_mri_next, 'l'},
814 {"for", s_mri_for, 0},
815 {"for.b", s_mri_for, 'b'},
816 {"for.w", s_mri_for, 'w'},
817 {"for.l", s_mri_for, 'l'},
818 {"endf", s_mri_endf, 0},
819 {"repeat", s_mri_repeat, 0},
820 {"until", s_mri_until, 0},
821 {"until.b", s_mri_until, 'b'},
822 {"until.w", s_mri_until, 'w'},
823 {"until.l", s_mri_until, 'l'},
824 {"while", s_mri_while, 0},
825 {"while.b", s_mri_while, 'b'},
826 {"while.w", s_mri_while, 'w'},
827 {"while.l", s_mri_while, 'l'},
828 {"endw", s_mri_endw, 0},
829
830 {0, 0, 0}
831 };
832
833 /* The mote pseudo ops are put into the opcode table, since they
834 don't start with a . they look like opcodes to gas. */
835
836 const pseudo_typeS mote_pseudo_table[] =
837 {
838
839 {"dcl", cons, 4},
840 {"dc", cons, 2},
841 {"dcw", cons, 2},
842 {"dcb", cons, 1},
843
844 {"dsl", s_space, 4},
845 {"ds", s_space, 2},
846 {"dsw", s_space, 2},
847 {"dsb", s_space, 1},
848
849 {"xdef", s_globl, 0},
850 #ifdef OBJ_ELF
851 {"align", s_align_bytes, 0},
852 #else
853 {"align", s_align_ptwo, 0},
854 #endif
855 #ifdef M68KCOFF
856 {"sect", obj_coff_section, 0},
857 {"section", obj_coff_section, 0},
858 #endif
859 {0, 0, 0}
860 };
861
862 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
863 gives identical results to a 32-bit host. */
864 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
865 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
866
867 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
868 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
869 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
870 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
871
872 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
873 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
874 #define islong(x) (1)
875
876 static char notend_table[256];
877 static char alt_notend_table[256];
878 #define notend(s) \
879 (! (notend_table[(unsigned char) *s] \
880 || (*s == ':' \
881 && alt_notend_table[(unsigned char) s[1]])))
882
883 #ifdef OBJ_ELF
884
885 /* Return zero if the reference to SYMBOL from within the same segment may
886 be relaxed. */
887
888 /* On an ELF system, we can't relax an externally visible symbol,
889 because it may be overridden by a shared library. However, if
890 TARGET_OS is "elf", then we presume that we are assembling for an
891 embedded system, in which case we don't have to worry about shared
892 libraries, and we can relax any external sym. */
893
894 #define relaxable_symbol(symbol) \
895 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
896 || S_IS_WEAK (symbol)))
897
898 /* Compute the relocation code for a fixup of SIZE bytes, using pc
899 relative relocation if PCREL is non-zero. PIC says whether a special
900 pic relocation was requested. */
901
902 static bfd_reloc_code_real_type
903 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
904 {
905 switch (pic)
906 {
907 case pic_got_pcrel:
908 switch (size)
909 {
910 case 1:
911 return BFD_RELOC_8_GOT_PCREL;
912 case 2:
913 return BFD_RELOC_16_GOT_PCREL;
914 case 4:
915 return BFD_RELOC_32_GOT_PCREL;
916 }
917 break;
918
919 case pic_got_off:
920 switch (size)
921 {
922 case 1:
923 return BFD_RELOC_8_GOTOFF;
924 case 2:
925 return BFD_RELOC_16_GOTOFF;
926 case 4:
927 return BFD_RELOC_32_GOTOFF;
928 }
929 break;
930
931 case pic_plt_pcrel:
932 switch (size)
933 {
934 case 1:
935 return BFD_RELOC_8_PLT_PCREL;
936 case 2:
937 return BFD_RELOC_16_PLT_PCREL;
938 case 4:
939 return BFD_RELOC_32_PLT_PCREL;
940 }
941 break;
942
943 case pic_plt_off:
944 switch (size)
945 {
946 case 1:
947 return BFD_RELOC_8_PLTOFF;
948 case 2:
949 return BFD_RELOC_16_PLTOFF;
950 case 4:
951 return BFD_RELOC_32_PLTOFF;
952 }
953 break;
954
955 case pic_none:
956 if (pcrel)
957 {
958 switch (size)
959 {
960 case 1:
961 return BFD_RELOC_8_PCREL;
962 case 2:
963 return BFD_RELOC_16_PCREL;
964 case 4:
965 return BFD_RELOC_32_PCREL;
966 }
967 }
968 else
969 {
970 switch (size)
971 {
972 case 1:
973 return BFD_RELOC_8;
974 case 2:
975 return BFD_RELOC_16;
976 case 4:
977 return BFD_RELOC_32;
978 }
979 }
980 }
981
982 if (pcrel)
983 {
984 if (pic == pic_none)
985 as_bad (_("Can not do %d byte pc-relative relocation"), size);
986 else
987 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
988 }
989 else
990 {
991 if (pic == pic_none)
992 as_bad (_("Can not do %d byte relocation"), size);
993 else
994 as_bad (_("Can not do %d byte pic relocation"), size);
995 }
996
997 return BFD_RELOC_NONE;
998 }
999
1000 /* Here we decide which fixups can be adjusted to make them relative
1001 to the beginning of the section instead of the symbol. Basically
1002 we need to make sure that the dynamic relocations are done
1003 correctly, so in some cases we force the original symbol to be
1004 used. */
1005 int
1006 tc_m68k_fix_adjustable (fixS *fixP)
1007 {
1008 /* Adjust_reloc_syms doesn't know about the GOT. */
1009 switch (fixP->fx_r_type)
1010 {
1011 case BFD_RELOC_8_GOT_PCREL:
1012 case BFD_RELOC_16_GOT_PCREL:
1013 case BFD_RELOC_32_GOT_PCREL:
1014 case BFD_RELOC_8_GOTOFF:
1015 case BFD_RELOC_16_GOTOFF:
1016 case BFD_RELOC_32_GOTOFF:
1017 case BFD_RELOC_8_PLT_PCREL:
1018 case BFD_RELOC_16_PLT_PCREL:
1019 case BFD_RELOC_32_PLT_PCREL:
1020 case BFD_RELOC_8_PLTOFF:
1021 case BFD_RELOC_16_PLTOFF:
1022 case BFD_RELOC_32_PLTOFF:
1023 return 0;
1024
1025 case BFD_RELOC_VTABLE_INHERIT:
1026 case BFD_RELOC_VTABLE_ENTRY:
1027 return 0;
1028
1029 default:
1030 return 1;
1031 }
1032 }
1033
1034 #else /* !OBJ_ELF */
1035
1036 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1037
1038 #define relaxable_symbol(symbol) 1
1039
1040 #endif /* OBJ_ELF */
1041
1042 arelent *
1043 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1044 {
1045 arelent *reloc;
1046 bfd_reloc_code_real_type code;
1047
1048 /* If the tcbit is set, then this was a fixup of a negative value
1049 that was never resolved. We do not have a reloc to handle this,
1050 so just return. We assume that other code will have detected this
1051 situation and produced a helpful error message, so we just tell the
1052 user that the reloc cannot be produced. */
1053 if (fixp->fx_tcbit)
1054 {
1055 if (fixp->fx_addsy)
1056 as_bad_where (fixp->fx_file, fixp->fx_line,
1057 _("Unable to produce reloc against symbol '%s'"),
1058 S_GET_NAME (fixp->fx_addsy));
1059 return NULL;
1060 }
1061
1062 if (fixp->fx_r_type != BFD_RELOC_NONE)
1063 {
1064 code = fixp->fx_r_type;
1065
1066 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1067 that fixup_segment converted a non-PC relative reloc into a
1068 PC relative reloc. In such a case, we need to convert the
1069 reloc code. */
1070 if (fixp->fx_pcrel)
1071 {
1072 switch (code)
1073 {
1074 case BFD_RELOC_8:
1075 code = BFD_RELOC_8_PCREL;
1076 break;
1077 case BFD_RELOC_16:
1078 code = BFD_RELOC_16_PCREL;
1079 break;
1080 case BFD_RELOC_32:
1081 code = BFD_RELOC_32_PCREL;
1082 break;
1083 case BFD_RELOC_8_PCREL:
1084 case BFD_RELOC_16_PCREL:
1085 case BFD_RELOC_32_PCREL:
1086 case BFD_RELOC_8_GOT_PCREL:
1087 case BFD_RELOC_16_GOT_PCREL:
1088 case BFD_RELOC_32_GOT_PCREL:
1089 case BFD_RELOC_8_GOTOFF:
1090 case BFD_RELOC_16_GOTOFF:
1091 case BFD_RELOC_32_GOTOFF:
1092 case BFD_RELOC_8_PLT_PCREL:
1093 case BFD_RELOC_16_PLT_PCREL:
1094 case BFD_RELOC_32_PLT_PCREL:
1095 case BFD_RELOC_8_PLTOFF:
1096 case BFD_RELOC_16_PLTOFF:
1097 case BFD_RELOC_32_PLTOFF:
1098 break;
1099 default:
1100 as_bad_where (fixp->fx_file, fixp->fx_line,
1101 _("Cannot make %s relocation PC relative"),
1102 bfd_get_reloc_code_name (code));
1103 }
1104 }
1105 }
1106 else
1107 {
1108 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1109 switch (F (fixp->fx_size, fixp->fx_pcrel))
1110 {
1111 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1112 MAP (1, 0, BFD_RELOC_8);
1113 MAP (2, 0, BFD_RELOC_16);
1114 MAP (4, 0, BFD_RELOC_32);
1115 MAP (1, 1, BFD_RELOC_8_PCREL);
1116 MAP (2, 1, BFD_RELOC_16_PCREL);
1117 MAP (4, 1, BFD_RELOC_32_PCREL);
1118 default:
1119 abort ();
1120 }
1121 }
1122 #undef F
1123 #undef MAP
1124
1125 reloc = (arelent *) xmalloc (sizeof (arelent));
1126 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1127 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1128 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1129 #ifndef OBJ_ELF
1130 if (fixp->fx_pcrel)
1131 reloc->addend = fixp->fx_addnumber;
1132 else
1133 reloc->addend = 0;
1134 #else
1135 if (!fixp->fx_pcrel)
1136 reloc->addend = fixp->fx_addnumber;
1137 else
1138 reloc->addend = (section->vma
1139 /* Explicit sign extension in case char is
1140 unsigned. */
1141 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1142 + fixp->fx_addnumber
1143 + md_pcrel_from (fixp));
1144 #endif
1145
1146 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1147 assert (reloc->howto != 0);
1148
1149 return reloc;
1150 }
1151
1152 /* Handle of the OPCODE hash table. NULL means any use before
1153 m68k_ip_begin() will crash. */
1154 static struct hash_control *op_hash;
1155 \f
1156 /* Assemble an m68k instruction. */
1157
1158 static void
1159 m68k_ip (char *instring)
1160 {
1161 register char *p;
1162 register struct m68k_op *opP;
1163 register const struct m68k_incant *opcode;
1164 register const char *s;
1165 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1166 char *pdot, *pdotmove;
1167 enum m68k_size siz1, siz2;
1168 char c;
1169 int losing;
1170 int opsfound;
1171 struct m68k_op operands_backup[6];
1172 LITTLENUM_TYPE words[6];
1173 LITTLENUM_TYPE *wordp;
1174 unsigned long ok_arch = 0;
1175
1176 if (*instring == ' ')
1177 instring++; /* Skip leading whitespace. */
1178
1179 /* Scan up to end of operation-code, which MUST end in end-of-string
1180 or exactly 1 space. */
1181 pdot = 0;
1182 for (p = instring; *p != '\0'; p++)
1183 {
1184 if (*p == ' ')
1185 break;
1186 if (*p == '.')
1187 pdot = p;
1188 }
1189
1190 if (p == instring)
1191 {
1192 the_ins.error = _("No operator");
1193 return;
1194 }
1195
1196 /* p now points to the end of the opcode name, probably whitespace.
1197 Make sure the name is null terminated by clobbering the
1198 whitespace, look it up in the hash table, then fix it back.
1199 Remove a dot, first, since the opcode tables have none. */
1200 if (pdot != NULL)
1201 {
1202 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1203 *pdotmove = pdotmove[1];
1204 p--;
1205 }
1206
1207 c = *p;
1208 *p = '\0';
1209 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1210 *p = c;
1211
1212 if (pdot != NULL)
1213 {
1214 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1215 *pdotmove = pdotmove[-1];
1216 *pdot = '.';
1217 ++p;
1218 }
1219
1220 if (opcode == NULL)
1221 {
1222 the_ins.error = _("Unknown operator");
1223 return;
1224 }
1225
1226 /* Found a legitimate opcode, start matching operands. */
1227 while (*p == ' ')
1228 ++p;
1229
1230 if (opcode->m_operands == 0)
1231 {
1232 char *old = input_line_pointer;
1233 *old = '\n';
1234 input_line_pointer = p;
1235 /* Ahh - it's a motorola style psuedo op. */
1236 mote_pseudo_table[opcode->m_opnum].poc_handler
1237 (mote_pseudo_table[opcode->m_opnum].poc_val);
1238 input_line_pointer = old;
1239 *old = 0;
1240
1241 return;
1242 }
1243
1244 if (flag_mri && opcode->m_opnum == 0)
1245 {
1246 /* In MRI mode, random garbage is allowed after an instruction
1247 which accepts no operands. */
1248 the_ins.args = opcode->m_operands;
1249 the_ins.numargs = opcode->m_opnum;
1250 the_ins.numo = opcode->m_codenum;
1251 the_ins.opcode[0] = getone (opcode);
1252 the_ins.opcode[1] = gettwo (opcode);
1253 return;
1254 }
1255
1256 for (opP = &the_ins.operands[0]; *p; opP++)
1257 {
1258 p = crack_operand (p, opP);
1259
1260 if (opP->error)
1261 {
1262 the_ins.error = opP->error;
1263 return;
1264 }
1265 }
1266
1267 opsfound = opP - &the_ins.operands[0];
1268
1269 /* This ugly hack is to support the floating pt opcodes in their
1270 standard form. Essentially, we fake a first enty of type COP#1 */
1271 if (opcode->m_operands[0] == 'I')
1272 {
1273 int n;
1274
1275 for (n = opsfound; n > 0; --n)
1276 the_ins.operands[n] = the_ins.operands[n - 1];
1277
1278 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1279 the_ins.operands[0].mode = CONTROL;
1280 the_ins.operands[0].reg = m68k_float_copnum;
1281 opsfound++;
1282 }
1283
1284 /* We've got the operands. Find an opcode that'll accept them. */
1285 for (losing = 0;;)
1286 {
1287 /* If we didn't get the right number of ops, or we have no
1288 common model with this pattern then reject this pattern. */
1289
1290 ok_arch |= opcode->m_arch;
1291 if (opsfound != opcode->m_opnum
1292 || ((opcode->m_arch & current_architecture) == 0))
1293 ++losing;
1294 else
1295 {
1296 int i;
1297
1298 /* Make a copy of the operands of this insn so that
1299 we can modify them safely, should we want to. */
1300 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1301 for (i = 0; i < opsfound; i++)
1302 operands_backup[i] = the_ins.operands[i];
1303
1304 for (s = opcode->m_operands, opP = &operands_backup[0];
1305 *s && !losing;
1306 s += 2, opP++)
1307 {
1308 /* Warning: this switch is huge! */
1309 /* I've tried to organize the cases into this order:
1310 non-alpha first, then alpha by letter. Lower-case
1311 goes directly before uppercase counterpart. */
1312 /* Code with multiple case ...: gets sorted by the lowest
1313 case ... it belongs to. I hope this makes sense. */
1314 switch (*s)
1315 {
1316 case '!':
1317 switch (opP->mode)
1318 {
1319 case IMMED:
1320 case DREG:
1321 case AREG:
1322 case FPREG:
1323 case CONTROL:
1324 case AINC:
1325 case ADEC:
1326 case REGLST:
1327 losing++;
1328 break;
1329 default:
1330 break;
1331 }
1332 break;
1333
1334 case '<':
1335 switch (opP->mode)
1336 {
1337 case DREG:
1338 case AREG:
1339 case FPREG:
1340 case CONTROL:
1341 case IMMED:
1342 case ADEC:
1343 case REGLST:
1344 losing++;
1345 break;
1346 default:
1347 break;
1348 }
1349 break;
1350
1351 case '>':
1352 switch (opP->mode)
1353 {
1354 case DREG:
1355 case AREG:
1356 case FPREG:
1357 case CONTROL:
1358 case IMMED:
1359 case AINC:
1360 case REGLST:
1361 losing++;
1362 break;
1363 case ABSL:
1364 break;
1365 default:
1366 if (opP->reg == PC
1367 || opP->reg == ZPC)
1368 losing++;
1369 break;
1370 }
1371 break;
1372
1373 case 'm':
1374 switch (opP->mode)
1375 {
1376 case DREG:
1377 case AREG:
1378 case AINDR:
1379 case AINC:
1380 case ADEC:
1381 break;
1382 default:
1383 losing++;
1384 }
1385 break;
1386
1387 case 'n':
1388 switch (opP->mode)
1389 {
1390 case DISP:
1391 break;
1392 default:
1393 losing++;
1394 }
1395 break;
1396
1397 case 'o':
1398 switch (opP->mode)
1399 {
1400 case BASE:
1401 case ABSL:
1402 case IMMED:
1403 break;
1404 default:
1405 losing++;
1406 }
1407 break;
1408
1409 case 'p':
1410 switch (opP->mode)
1411 {
1412 case DREG:
1413 case AREG:
1414 case AINDR:
1415 case AINC:
1416 case ADEC:
1417 break;
1418 case DISP:
1419 if (opP->reg == PC || opP->reg == ZPC)
1420 losing++;
1421 break;
1422 default:
1423 losing++;
1424 }
1425 break;
1426
1427 case 'q':
1428 switch (opP->mode)
1429 {
1430 case DREG:
1431 case AINDR:
1432 case AINC:
1433 case ADEC:
1434 break;
1435 case DISP:
1436 if (opP->reg == PC || opP->reg == ZPC)
1437 losing++;
1438 break;
1439 default:
1440 losing++;
1441 break;
1442 }
1443 break;
1444
1445 case 'v':
1446 switch (opP->mode)
1447 {
1448 case DREG:
1449 case AINDR:
1450 case AINC:
1451 case ADEC:
1452 case ABSL:
1453 break;
1454 case DISP:
1455 if (opP->reg == PC || opP->reg == ZPC)
1456 losing++;
1457 break;
1458 default:
1459 losing++;
1460 break;
1461 }
1462 break;
1463
1464 case '#':
1465 if (opP->mode != IMMED)
1466 losing++;
1467 else if (s[1] == 'b'
1468 && ! isvar (&opP->disp)
1469 && (opP->disp.exp.X_op != O_constant
1470 || ! isbyte (opP->disp.exp.X_add_number)))
1471 losing++;
1472 else if (s[1] == 'B'
1473 && ! isvar (&opP->disp)
1474 && (opP->disp.exp.X_op != O_constant
1475 || ! issbyte (opP->disp.exp.X_add_number)))
1476 losing++;
1477 else if (s[1] == 'w'
1478 && ! isvar (&opP->disp)
1479 && (opP->disp.exp.X_op != O_constant
1480 || ! isword (opP->disp.exp.X_add_number)))
1481 losing++;
1482 else if (s[1] == 'W'
1483 && ! isvar (&opP->disp)
1484 && (opP->disp.exp.X_op != O_constant
1485 || ! issword (opP->disp.exp.X_add_number)))
1486 losing++;
1487 break;
1488
1489 case '^':
1490 case 'T':
1491 if (opP->mode != IMMED)
1492 losing++;
1493 break;
1494
1495 case '$':
1496 if (opP->mode == AREG
1497 || opP->mode == CONTROL
1498 || opP->mode == FPREG
1499 || opP->mode == IMMED
1500 || opP->mode == REGLST
1501 || (opP->mode != ABSL
1502 && (opP->reg == PC
1503 || opP->reg == ZPC)))
1504 losing++;
1505 break;
1506
1507 case '%':
1508 if (opP->mode == CONTROL
1509 || opP->mode == FPREG
1510 || opP->mode == REGLST
1511 || opP->mode == IMMED
1512 || (opP->mode != ABSL
1513 && (opP->reg == PC
1514 || opP->reg == ZPC)))
1515 losing++;
1516 break;
1517
1518 case '&':
1519 switch (opP->mode)
1520 {
1521 case DREG:
1522 case AREG:
1523 case FPREG:
1524 case CONTROL:
1525 case IMMED:
1526 case AINC:
1527 case ADEC:
1528 case REGLST:
1529 losing++;
1530 break;
1531 case ABSL:
1532 break;
1533 default:
1534 if (opP->reg == PC
1535 || opP->reg == ZPC)
1536 losing++;
1537 break;
1538 }
1539 break;
1540
1541 case '*':
1542 if (opP->mode == CONTROL
1543 || opP->mode == FPREG
1544 || opP->mode == REGLST)
1545 losing++;
1546 break;
1547
1548 case '+':
1549 if (opP->mode != AINC)
1550 losing++;
1551 break;
1552
1553 case '-':
1554 if (opP->mode != ADEC)
1555 losing++;
1556 break;
1557
1558 case '/':
1559 switch (opP->mode)
1560 {
1561 case AREG:
1562 case CONTROL:
1563 case FPREG:
1564 case AINC:
1565 case ADEC:
1566 case IMMED:
1567 case REGLST:
1568 losing++;
1569 break;
1570 default:
1571 break;
1572 }
1573 break;
1574
1575 case ';':
1576 switch (opP->mode)
1577 {
1578 case AREG:
1579 case CONTROL:
1580 case FPREG:
1581 case REGLST:
1582 losing++;
1583 break;
1584 default:
1585 break;
1586 }
1587 break;
1588
1589 case '?':
1590 switch (opP->mode)
1591 {
1592 case AREG:
1593 case CONTROL:
1594 case FPREG:
1595 case AINC:
1596 case ADEC:
1597 case IMMED:
1598 case REGLST:
1599 losing++;
1600 break;
1601 case ABSL:
1602 break;
1603 default:
1604 if (opP->reg == PC || opP->reg == ZPC)
1605 losing++;
1606 break;
1607 }
1608 break;
1609
1610 case '@':
1611 switch (opP->mode)
1612 {
1613 case AREG:
1614 case CONTROL:
1615 case FPREG:
1616 case IMMED:
1617 case REGLST:
1618 losing++;
1619 break;
1620 default:
1621 break;
1622 }
1623 break;
1624
1625 case '~': /* For now! (JF FOO is this right?) */
1626 switch (opP->mode)
1627 {
1628 case DREG:
1629 case AREG:
1630 case CONTROL:
1631 case FPREG:
1632 case IMMED:
1633 case REGLST:
1634 losing++;
1635 break;
1636 case ABSL:
1637 break;
1638 default:
1639 if (opP->reg == PC
1640 || opP->reg == ZPC)
1641 losing++;
1642 break;
1643 }
1644 break;
1645
1646 case '3':
1647 if (opP->mode != CONTROL
1648 || (opP->reg != TT0 && opP->reg != TT1))
1649 losing++;
1650 break;
1651
1652 case 'A':
1653 if (opP->mode != AREG)
1654 losing++;
1655 break;
1656
1657 case 'a':
1658 if (opP->mode != AINDR)
1659 ++losing;
1660 break;
1661
1662 case '4':
1663 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1664 && (opP->mode != DISP
1665 || opP->reg < ADDR0
1666 || opP->reg > ADDR7))
1667 ++losing;
1668 break;
1669
1670 case 'B': /* FOO */
1671 if (opP->mode != ABSL
1672 || (flag_long_jumps
1673 && strncmp (instring, "jbsr", 4) == 0))
1674 losing++;
1675 break;
1676
1677 case 'b':
1678 switch (opP->mode)
1679 {
1680 case IMMED:
1681 case ABSL:
1682 case AREG:
1683 case FPREG:
1684 case CONTROL:
1685 case POST:
1686 case PRE:
1687 case REGLST:
1688 losing++;
1689 break;
1690 default:
1691 break;
1692 }
1693 break;
1694
1695 case 'C':
1696 if (opP->mode != CONTROL || opP->reg != CCR)
1697 losing++;
1698 break;
1699
1700 case 'd':
1701 if (opP->mode != DISP
1702 || opP->reg < ADDR0
1703 || opP->reg > ADDR7)
1704 losing++;
1705 break;
1706
1707 case 'D':
1708 if (opP->mode != DREG)
1709 losing++;
1710 break;
1711
1712 case 'E':
1713 if (opP->reg != ACC)
1714 losing++;
1715 break;
1716
1717 case 'e':
1718 if (opP->reg != ACC && opP->reg != ACC1
1719 && opP->reg != ACC2 && opP->reg != ACC3)
1720 losing++;
1721 break;
1722
1723 case 'F':
1724 if (opP->mode != FPREG)
1725 losing++;
1726 break;
1727
1728 case 'G':
1729 if (opP->reg != MACSR)
1730 losing++;
1731 break;
1732
1733 case 'g':
1734 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1735 losing++;
1736 break;
1737
1738 case 'H':
1739 if (opP->reg != MASK)
1740 losing++;
1741 break;
1742
1743 case 'I':
1744 if (opP->mode != CONTROL
1745 || opP->reg < COP0
1746 || opP->reg > COP7)
1747 losing++;
1748 break;
1749
1750 case 'i':
1751 if (opP->mode != LSH && opP->mode != RSH)
1752 losing++;
1753 break;
1754
1755 case 'J':
1756 if (opP->mode != CONTROL
1757 || opP->reg < USP
1758 || opP->reg > last_movec_reg
1759 || !control_regs)
1760 losing++;
1761 else
1762 {
1763 const enum m68k_register *rp;
1764
1765 for (rp = control_regs; *rp; rp++)
1766 {
1767 if (*rp == opP->reg)
1768 break;
1769 /* In most CPUs RAMBAR refers to control reg
1770 c05 (RAMBAR1), but a few CPUs have it
1771 refer to c04 (RAMBAR0). */
1772 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1773 {
1774 opP->reg = RAMBAR_ALT;
1775 break;
1776 }
1777 }
1778 if (*rp == 0)
1779 losing++;
1780 }
1781 break;
1782
1783 case 'k':
1784 if (opP->mode != IMMED)
1785 losing++;
1786 break;
1787
1788 case 'l':
1789 case 'L':
1790 if (opP->mode == DREG
1791 || opP->mode == AREG
1792 || opP->mode == FPREG)
1793 {
1794 if (s[1] == '8')
1795 losing++;
1796 else
1797 {
1798 switch (opP->mode)
1799 {
1800 case DREG:
1801 opP->mask = 1 << (opP->reg - DATA0);
1802 break;
1803 case AREG:
1804 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1805 break;
1806 case FPREG:
1807 opP->mask = 1 << (opP->reg - FP0 + 16);
1808 break;
1809 default:
1810 abort ();
1811 }
1812 opP->mode = REGLST;
1813 }
1814 }
1815 else if (opP->mode == CONTROL)
1816 {
1817 if (s[1] != '8')
1818 losing++;
1819 else
1820 {
1821 switch (opP->reg)
1822 {
1823 case FPI:
1824 opP->mask = 1 << 24;
1825 break;
1826 case FPS:
1827 opP->mask = 1 << 25;
1828 break;
1829 case FPC:
1830 opP->mask = 1 << 26;
1831 break;
1832 default:
1833 losing++;
1834 break;
1835 }
1836 opP->mode = REGLST;
1837 }
1838 }
1839 else if (opP->mode != REGLST)
1840 losing++;
1841 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1842 losing++;
1843 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1844 losing++;
1845 break;
1846
1847 case 'M':
1848 if (opP->mode != IMMED)
1849 losing++;
1850 else if (opP->disp.exp.X_op != O_constant
1851 || ! issbyte (opP->disp.exp.X_add_number))
1852 losing++;
1853 else if (! m68k_quick
1854 && instring[3] != 'q'
1855 && instring[4] != 'q')
1856 losing++;
1857 break;
1858
1859 case 'O':
1860 if (opP->mode != DREG
1861 && opP->mode != IMMED
1862 && opP->mode != ABSL)
1863 losing++;
1864 break;
1865
1866 case 'Q':
1867 if (opP->mode != IMMED)
1868 losing++;
1869 else if (opP->disp.exp.X_op != O_constant
1870 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1871 losing++;
1872 else if (! m68k_quick
1873 && (strncmp (instring, "add", 3) == 0
1874 || strncmp (instring, "sub", 3) == 0)
1875 && instring[3] != 'q')
1876 losing++;
1877 break;
1878
1879 case 'R':
1880 if (opP->mode != DREG && opP->mode != AREG)
1881 losing++;
1882 break;
1883
1884 case 'r':
1885 if (opP->mode != AINDR
1886 && (opP->mode != BASE
1887 || (opP->reg != 0
1888 && opP->reg != ZADDR0)
1889 || opP->disp.exp.X_op != O_absent
1890 || ((opP->index.reg < DATA0
1891 || opP->index.reg > DATA7)
1892 && (opP->index.reg < ADDR0
1893 || opP->index.reg > ADDR7))
1894 || opP->index.size != SIZE_UNSPEC
1895 || opP->index.scale != 1))
1896 losing++;
1897 break;
1898
1899 case 's':
1900 if (opP->mode != CONTROL
1901 || ! (opP->reg == FPI
1902 || opP->reg == FPS
1903 || opP->reg == FPC))
1904 losing++;
1905 break;
1906
1907 case 'S':
1908 if (opP->mode != CONTROL || opP->reg != SR)
1909 losing++;
1910 break;
1911
1912 case 't':
1913 if (opP->mode != IMMED)
1914 losing++;
1915 else if (opP->disp.exp.X_op != O_constant
1916 || TRUNC (opP->disp.exp.X_add_number) > 7)
1917 losing++;
1918 break;
1919
1920 case 'U':
1921 if (opP->mode != CONTROL || opP->reg != USP)
1922 losing++;
1923 break;
1924
1925 case 'x':
1926 if (opP->mode != IMMED)
1927 losing++;
1928 else if (opP->disp.exp.X_op != O_constant
1929 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1930 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1931 losing++;
1932 break;
1933
1934 /* JF these are out of order. We could put them
1935 in order if we were willing to put up with
1936 bunches of #ifdef m68851s in the code.
1937
1938 Don't forget that you need these operands
1939 to use 68030 MMU instructions. */
1940 #ifndef NO_68851
1941 /* Memory addressing mode used by pflushr. */
1942 case '|':
1943 if (opP->mode == CONTROL
1944 || opP->mode == FPREG
1945 || opP->mode == DREG
1946 || opP->mode == AREG
1947 || opP->mode == REGLST)
1948 losing++;
1949 /* We should accept immediate operands, but they
1950 supposedly have to be quad word, and we don't
1951 handle that. I would like to see what a Motorola
1952 assembler does before doing something here. */
1953 if (opP->mode == IMMED)
1954 losing++;
1955 break;
1956
1957 case 'f':
1958 if (opP->mode != CONTROL
1959 || (opP->reg != SFC && opP->reg != DFC))
1960 losing++;
1961 break;
1962
1963 case '0':
1964 if (opP->mode != CONTROL || opP->reg != TC)
1965 losing++;
1966 break;
1967
1968 case '1':
1969 if (opP->mode != CONTROL || opP->reg != AC)
1970 losing++;
1971 break;
1972
1973 case '2':
1974 if (opP->mode != CONTROL
1975 || (opP->reg != CAL
1976 && opP->reg != VAL
1977 && opP->reg != SCC))
1978 losing++;
1979 break;
1980
1981 case 'V':
1982 if (opP->mode != CONTROL
1983 || opP->reg != VAL)
1984 losing++;
1985 break;
1986
1987 case 'W':
1988 if (opP->mode != CONTROL
1989 || (opP->reg != DRP
1990 && opP->reg != SRP
1991 && opP->reg != CRP))
1992 losing++;
1993 break;
1994
1995 case 'w':
1996 switch (opP->mode)
1997 {
1998 case IMMED:
1999 case ABSL:
2000 case AREG:
2001 case DREG:
2002 case FPREG:
2003 case CONTROL:
2004 case POST:
2005 case PRE:
2006 case REGLST:
2007 losing++;
2008 break;
2009 default:
2010 break;
2011 }
2012 break;
2013
2014 case 'X':
2015 if (opP->mode != CONTROL
2016 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2017 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2018 losing++;
2019 break;
2020
2021 case 'Y':
2022 if (opP->mode != CONTROL || opP->reg != PSR)
2023 losing++;
2024 break;
2025
2026 case 'Z':
2027 if (opP->mode != CONTROL || opP->reg != PCSR)
2028 losing++;
2029 break;
2030 #endif
2031 case 'c':
2032 if (opP->mode != CONTROL
2033 || (opP->reg != NC
2034 && opP->reg != IC
2035 && opP->reg != DC
2036 && opP->reg != BC))
2037 losing++;
2038 break;
2039
2040 case '_':
2041 if (opP->mode != ABSL)
2042 ++losing;
2043 break;
2044
2045 case 'u':
2046 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2047 losing++;
2048 /* FIXME: kludge instead of fixing parser:
2049 upper/lower registers are *not* CONTROL
2050 registers, but ordinary ones. */
2051 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2052 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2053 opP->mode = DREG;
2054 else
2055 opP->mode = AREG;
2056 break;
2057
2058 case 'y':
2059 if (!(opP->mode == AINDR
2060 || (opP->mode == DISP
2061 && !(opP->reg == PC || opP->reg == ZPC))))
2062 losing++;
2063 break;
2064
2065 case 'z':
2066 if (!(opP->mode == AINDR || opP->mode == DISP))
2067 losing++;
2068 break;
2069
2070 default:
2071 abort ();
2072 }
2073
2074 if (losing)
2075 break;
2076 }
2077
2078 /* Since we have found the correct instruction, copy
2079 in the modifications that we may have made. */
2080 if (!losing)
2081 for (i = 0; i < opsfound; i++)
2082 the_ins.operands[i] = operands_backup[i];
2083 }
2084
2085 if (!losing)
2086 break;
2087
2088 opcode = opcode->m_next;
2089
2090 if (!opcode)
2091 {
2092 if (ok_arch
2093 && !(ok_arch & current_architecture))
2094 {
2095 const struct m68k_cpu *cpu;
2096 int any = 0;
2097 size_t space = 400;
2098 char *buf = xmalloc (space + 1);
2099 size_t len;
2100 int paren = 1;
2101
2102 the_ins.error = buf;
2103 /* Make sure there's a NUL at the end of the buffer -- strncpy
2104 won't write one when it runs out of buffer */
2105 buf[space] = 0;
2106 #define APPEND(STRING) \
2107 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2108
2109 APPEND (_("invalid instruction for this architecture; needs "));
2110 switch (ok_arch)
2111 {
2112 case mcfisa_a:
2113 APPEND (_("ColdFire ISA_A"));
2114 break;
2115 case mcfhwdiv:
2116 APPEND (_("ColdFire hardware divide"));
2117 break;
2118 case mcfisa_aa:
2119 APPEND (_("ColdFire ISA_A+"));
2120 break;
2121 case mcfisa_b:
2122 APPEND (_("ColdFire ISA_B"));
2123 break;
2124 case cfloat:
2125 APPEND (_("ColdFire fpu"));
2126 break;
2127 case mfloat:
2128 APPEND (_("M68K fpu"));
2129 break;
2130 case mmmu:
2131 APPEND (_("M68K mmu"));
2132 break;
2133 case m68020up:
2134 APPEND (_("68020 or higher"));
2135 break;
2136 case m68000up:
2137 APPEND (_("68000 or higher"));
2138 break;
2139 case m68010up:
2140 APPEND (_("68010 or higher"));
2141 break;
2142 default:
2143 paren = 0;
2144 }
2145 if (paren)
2146 APPEND (" (");
2147
2148 for (cpu = m68k_cpus; cpu->name; cpu++)
2149 if (!cpu->alias && (cpu->arch & ok_arch))
2150 {
2151 const struct m68k_cpu *alias;
2152 int seen_master = 0;
2153
2154 if (any)
2155 APPEND (", ");
2156 any = 0;
2157 APPEND (cpu->name);
2158 for (alias = cpu; alias != m68k_cpus; alias--)
2159 if (alias[-1].alias >= 0)
2160 break;
2161 for (; !seen_master || alias->alias > 0; alias++)
2162 {
2163 if (!alias->alias)
2164 seen_master = 1;
2165 else
2166 {
2167 if (any)
2168 APPEND (", ");
2169 else
2170 APPEND (" [");
2171 APPEND (alias->name);
2172 any = 1;
2173 }
2174 }
2175 if (any)
2176 APPEND ("]");
2177 any = 1;
2178 }
2179 if (paren)
2180 APPEND (")");
2181 #undef APPEND
2182 if (!space)
2183 {
2184 /* we ran out of space, so replace the end of the list
2185 with ellipsis. */
2186 buf -= 4;
2187 while (*buf != ' ')
2188 buf--;
2189 strcpy (buf, " ...");
2190 }
2191 }
2192 else
2193 the_ins.error = _("operands mismatch");
2194 return;
2195 }
2196
2197 losing = 0;
2198 }
2199
2200 /* Now assemble it. */
2201 the_ins.args = opcode->m_operands;
2202 the_ins.numargs = opcode->m_opnum;
2203 the_ins.numo = opcode->m_codenum;
2204 the_ins.opcode[0] = getone (opcode);
2205 the_ins.opcode[1] = gettwo (opcode);
2206
2207 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2208 {
2209 /* This switch is a doozy.
2210 Watch the first step; its a big one! */
2211 switch (s[0])
2212 {
2213
2214 case '*':
2215 case '~':
2216 case '%':
2217 case ';':
2218 case '@':
2219 case '!':
2220 case '&':
2221 case '$':
2222 case '?':
2223 case '/':
2224 case '<':
2225 case '>':
2226 case 'b':
2227 case 'm':
2228 case 'n':
2229 case 'o':
2230 case 'p':
2231 case 'q':
2232 case 'v':
2233 case 'w':
2234 case 'y':
2235 case 'z':
2236 case '4':
2237 #ifndef NO_68851
2238 case '|':
2239 #endif
2240 switch (opP->mode)
2241 {
2242 case IMMED:
2243 tmpreg = 0x3c; /* 7.4 */
2244 if (strchr ("bwl", s[1]))
2245 nextword = get_num (&opP->disp, 90);
2246 else
2247 nextword = get_num (&opP->disp, 0);
2248 if (isvar (&opP->disp))
2249 add_fix (s[1], &opP->disp, 0, 0);
2250 switch (s[1])
2251 {
2252 case 'b':
2253 if (!isbyte (nextword))
2254 opP->error = _("operand out of range");
2255 addword (nextword);
2256 baseo = 0;
2257 break;
2258 case 'w':
2259 if (!isword (nextword))
2260 opP->error = _("operand out of range");
2261 addword (nextword);
2262 baseo = 0;
2263 break;
2264 case 'W':
2265 if (!issword (nextword))
2266 opP->error = _("operand out of range");
2267 addword (nextword);
2268 baseo = 0;
2269 break;
2270 case 'l':
2271 addword (nextword >> 16);
2272 addword (nextword);
2273 baseo = 0;
2274 break;
2275
2276 case 'f':
2277 baseo = 2;
2278 outro = 8;
2279 break;
2280 case 'F':
2281 baseo = 4;
2282 outro = 11;
2283 break;
2284 case 'x':
2285 baseo = 6;
2286 outro = 15;
2287 break;
2288 case 'p':
2289 baseo = 6;
2290 outro = -1;
2291 break;
2292 default:
2293 abort ();
2294 }
2295 if (!baseo)
2296 break;
2297
2298 /* We gotta put out some float. */
2299 if (op (&opP->disp) != O_big)
2300 {
2301 valueT val;
2302 int gencnt;
2303
2304 /* Can other cases happen here? */
2305 if (op (&opP->disp) != O_constant)
2306 abort ();
2307
2308 val = (valueT) offs (&opP->disp);
2309 gencnt = 0;
2310 do
2311 {
2312 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2313 val >>= LITTLENUM_NUMBER_OF_BITS;
2314 ++gencnt;
2315 }
2316 while (val != 0);
2317 offs (&opP->disp) = gencnt;
2318 }
2319 if (offs (&opP->disp) > 0)
2320 {
2321 if (offs (&opP->disp) > baseo)
2322 {
2323 as_warn (_("Bignum too big for %c format; truncated"),
2324 s[1]);
2325 offs (&opP->disp) = baseo;
2326 }
2327 baseo -= offs (&opP->disp);
2328 while (baseo--)
2329 addword (0);
2330 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2331 offs (&opP->disp)--;
2332 --wordp)
2333 addword (*wordp);
2334 break;
2335 }
2336 gen_to_words (words, baseo, (long) outro);
2337 for (wordp = words; baseo--; wordp++)
2338 addword (*wordp);
2339 break;
2340 case DREG:
2341 tmpreg = opP->reg - DATA; /* 0.dreg */
2342 break;
2343 case AREG:
2344 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2345 break;
2346 case AINDR:
2347 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2348 break;
2349 case ADEC:
2350 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2351 break;
2352 case AINC:
2353 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2354 break;
2355 case DISP:
2356
2357 nextword = get_num (&opP->disp, 90);
2358
2359 /* Convert mode 5 addressing with a zero offset into
2360 mode 2 addressing to reduce the instruction size by a
2361 word. */
2362 if (! isvar (&opP->disp)
2363 && (nextword == 0)
2364 && (opP->disp.size == SIZE_UNSPEC)
2365 && (opP->reg >= ADDR0)
2366 && (opP->reg <= ADDR7))
2367 {
2368 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2369 break;
2370 }
2371
2372 if (opP->reg == PC
2373 && ! isvar (&opP->disp)
2374 && m68k_abspcadd)
2375 {
2376 opP->disp.exp.X_op = O_symbol;
2377 opP->disp.exp.X_add_symbol =
2378 section_symbol (absolute_section);
2379 }
2380
2381 /* Force into index mode. Hope this works. */
2382
2383 /* We do the first bit for 32-bit displacements, and the
2384 second bit for 16 bit ones. It is possible that we
2385 should make the default be WORD instead of LONG, but
2386 I think that'd break GCC, so we put up with a little
2387 inefficiency for the sake of working output. */
2388
2389 if (!issword (nextword)
2390 || (isvar (&opP->disp)
2391 && ((opP->disp.size == SIZE_UNSPEC
2392 && flag_short_refs == 0
2393 && cpu_of_arch (current_architecture) >= m68020
2394 && ! arch_coldfire_p (current_architecture))
2395 || opP->disp.size == SIZE_LONG)))
2396 {
2397 if (cpu_of_arch (current_architecture) < m68020
2398 || arch_coldfire_p (current_architecture))
2399 opP->error =
2400 _("displacement too large for this architecture; needs 68020 or higher");
2401 if (opP->reg == PC)
2402 tmpreg = 0x3B; /* 7.3 */
2403 else
2404 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2405 if (isvar (&opP->disp))
2406 {
2407 if (opP->reg == PC)
2408 {
2409 if (opP->disp.size == SIZE_LONG
2410 #ifdef OBJ_ELF
2411 /* If the displacement needs pic
2412 relocation it cannot be relaxed. */
2413 || opP->disp.pic_reloc != pic_none
2414 #endif
2415 )
2416 {
2417 addword (0x0170);
2418 add_fix ('l', &opP->disp, 1, 2);
2419 }
2420 else
2421 {
2422 add_frag (adds (&opP->disp),
2423 SEXT (offs (&opP->disp)),
2424 TAB (PCREL1632, SZ_UNDEF));
2425 break;
2426 }
2427 }
2428 else
2429 {
2430 addword (0x0170);
2431 add_fix ('l', &opP->disp, 0, 0);
2432 }
2433 }
2434 else
2435 addword (0x0170);
2436 addword (nextword >> 16);
2437 }
2438 else
2439 {
2440 if (opP->reg == PC)
2441 tmpreg = 0x3A; /* 7.2 */
2442 else
2443 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2444
2445 if (isvar (&opP->disp))
2446 {
2447 if (opP->reg == PC)
2448 {
2449 add_fix ('w', &opP->disp, 1, 0);
2450 }
2451 else
2452 add_fix ('w', &opP->disp, 0, 0);
2453 }
2454 }
2455 addword (nextword);
2456 break;
2457
2458 case POST:
2459 case PRE:
2460 case BASE:
2461 nextword = 0;
2462 baseo = get_num (&opP->disp, 90);
2463 if (opP->mode == POST || opP->mode == PRE)
2464 outro = get_num (&opP->odisp, 90);
2465 /* Figure out the `addressing mode'.
2466 Also turn on the BASE_DISABLE bit, if needed. */
2467 if (opP->reg == PC || opP->reg == ZPC)
2468 {
2469 tmpreg = 0x3b; /* 7.3 */
2470 if (opP->reg == ZPC)
2471 nextword |= 0x80;
2472 }
2473 else if (opP->reg == 0)
2474 {
2475 nextword |= 0x80;
2476 tmpreg = 0x30; /* 6.garbage */
2477 }
2478 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2479 {
2480 nextword |= 0x80;
2481 tmpreg = 0x30 + opP->reg - ZADDR0;
2482 }
2483 else
2484 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2485
2486 siz1 = opP->disp.size;
2487 if (opP->mode == POST || opP->mode == PRE)
2488 siz2 = opP->odisp.size;
2489 else
2490 siz2 = SIZE_UNSPEC;
2491
2492 /* Index register stuff. */
2493 if (opP->index.reg != 0
2494 && opP->index.reg >= DATA
2495 && opP->index.reg <= ADDR7)
2496 {
2497 nextword |= (opP->index.reg - DATA) << 12;
2498
2499 if (opP->index.size == SIZE_LONG
2500 || (opP->index.size == SIZE_UNSPEC
2501 && m68k_index_width_default == SIZE_LONG))
2502 nextword |= 0x800;
2503
2504 if ((opP->index.scale != 1
2505 && cpu_of_arch (current_architecture) < m68020)
2506 || (opP->index.scale == 8
2507 && (arch_coldfire_p (current_architecture)
2508 && !arch_coldfire_fpu (current_architecture))))
2509 {
2510 opP->error =
2511 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2512 }
2513
2514 if (arch_coldfire_p (current_architecture)
2515 && opP->index.size == SIZE_WORD)
2516 opP->error = _("invalid index size for coldfire");
2517
2518 switch (opP->index.scale)
2519 {
2520 case 1:
2521 break;
2522 case 2:
2523 nextword |= 0x200;
2524 break;
2525 case 4:
2526 nextword |= 0x400;
2527 break;
2528 case 8:
2529 nextword |= 0x600;
2530 break;
2531 default:
2532 abort ();
2533 }
2534 /* IF its simple,
2535 GET US OUT OF HERE! */
2536
2537 /* Must be INDEX, with an index register. Address
2538 register cannot be ZERO-PC, and either :b was
2539 forced, or we know it will fit. For a 68000 or
2540 68010, force this mode anyways, because the
2541 larger modes aren't supported. */
2542 if (opP->mode == BASE
2543 && ((opP->reg >= ADDR0
2544 && opP->reg <= ADDR7)
2545 || opP->reg == PC))
2546 {
2547 if (siz1 == SIZE_BYTE
2548 || cpu_of_arch (current_architecture) < m68020
2549 || arch_coldfire_p (current_architecture)
2550 || (siz1 == SIZE_UNSPEC
2551 && ! isvar (&opP->disp)
2552 && issbyte (baseo)))
2553 {
2554 nextword += baseo & 0xff;
2555 addword (nextword);
2556 if (isvar (&opP->disp))
2557 {
2558 /* Do a byte relocation. If it doesn't
2559 fit (possible on m68000) let the
2560 fixup processing complain later. */
2561 if (opP->reg == PC)
2562 add_fix ('B', &opP->disp, 1, 1);
2563 else
2564 add_fix ('B', &opP->disp, 0, 0);
2565 }
2566 else if (siz1 != SIZE_BYTE)
2567 {
2568 if (siz1 != SIZE_UNSPEC)
2569 as_warn (_("Forcing byte displacement"));
2570 if (! issbyte (baseo))
2571 opP->error = _("byte displacement out of range");
2572 }
2573
2574 break;
2575 }
2576 else if (siz1 == SIZE_UNSPEC
2577 && opP->reg == PC
2578 && isvar (&opP->disp)
2579 && subs (&opP->disp) == NULL
2580 #ifdef OBJ_ELF
2581 /* If the displacement needs pic
2582 relocation it cannot be relaxed. */
2583 && opP->disp.pic_reloc == pic_none
2584 #endif
2585 )
2586 {
2587 /* The code in md_convert_frag_1 needs to be
2588 able to adjust nextword. Call frag_grow
2589 to ensure that we have enough space in
2590 the frag obstack to make all the bytes
2591 contiguous. */
2592 frag_grow (14);
2593 nextword += baseo & 0xff;
2594 addword (nextword);
2595 add_frag (adds (&opP->disp),
2596 SEXT (offs (&opP->disp)),
2597 TAB (PCINDEX, SZ_UNDEF));
2598
2599 break;
2600 }
2601 }
2602 }
2603 else
2604 {
2605 nextword |= 0x40; /* No index reg. */
2606 if (opP->index.reg >= ZDATA0
2607 && opP->index.reg <= ZDATA7)
2608 nextword |= (opP->index.reg - ZDATA0) << 12;
2609 else if (opP->index.reg >= ZADDR0
2610 || opP->index.reg <= ZADDR7)
2611 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2612 }
2613
2614 /* It isn't simple. */
2615
2616 if (cpu_of_arch (current_architecture) < m68020
2617 || arch_coldfire_p (current_architecture))
2618 opP->error =
2619 _("invalid operand mode for this architecture; needs 68020 or higher");
2620
2621 nextword |= 0x100;
2622 /* If the guy specified a width, we assume that it is
2623 wide enough. Maybe it isn't. If so, we lose. */
2624 switch (siz1)
2625 {
2626 case SIZE_UNSPEC:
2627 if (isvar (&opP->disp)
2628 ? m68k_rel32
2629 : ! issword (baseo))
2630 {
2631 siz1 = SIZE_LONG;
2632 nextword |= 0x30;
2633 }
2634 else if (! isvar (&opP->disp) && baseo == 0)
2635 nextword |= 0x10;
2636 else
2637 {
2638 nextword |= 0x20;
2639 siz1 = SIZE_WORD;
2640 }
2641 break;
2642 case SIZE_BYTE:
2643 as_warn (_(":b not permitted; defaulting to :w"));
2644 /* Fall through. */
2645 case SIZE_WORD:
2646 nextword |= 0x20;
2647 break;
2648 case SIZE_LONG:
2649 nextword |= 0x30;
2650 break;
2651 }
2652
2653 /* Figure out inner displacement stuff. */
2654 if (opP->mode == POST || opP->mode == PRE)
2655 {
2656 if (cpu_of_arch (current_architecture) & cpu32)
2657 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2658 switch (siz2)
2659 {
2660 case SIZE_UNSPEC:
2661 if (isvar (&opP->odisp)
2662 ? m68k_rel32
2663 : ! issword (outro))
2664 {
2665 siz2 = SIZE_LONG;
2666 nextword |= 0x3;
2667 }
2668 else if (! isvar (&opP->odisp) && outro == 0)
2669 nextword |= 0x1;
2670 else
2671 {
2672 nextword |= 0x2;
2673 siz2 = SIZE_WORD;
2674 }
2675 break;
2676 case 1:
2677 as_warn (_(":b not permitted; defaulting to :w"));
2678 /* Fall through. */
2679 case 2:
2680 nextword |= 0x2;
2681 break;
2682 case 3:
2683 nextword |= 0x3;
2684 break;
2685 }
2686 if (opP->mode == POST
2687 && (nextword & 0x40) == 0)
2688 nextword |= 0x04;
2689 }
2690 addword (nextword);
2691
2692 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2693 {
2694 if (opP->reg == PC || opP->reg == ZPC)
2695 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2696 else
2697 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2698 }
2699 if (siz1 == SIZE_LONG)
2700 addword (baseo >> 16);
2701 if (siz1 != SIZE_UNSPEC)
2702 addword (baseo);
2703
2704 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2705 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2706 if (siz2 == SIZE_LONG)
2707 addword (outro >> 16);
2708 if (siz2 != SIZE_UNSPEC)
2709 addword (outro);
2710
2711 break;
2712
2713 case ABSL:
2714 nextword = get_num (&opP->disp, 90);
2715 switch (opP->disp.size)
2716 {
2717 default:
2718 abort ();
2719 case SIZE_UNSPEC:
2720 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2721 {
2722 tmpreg = 0x38; /* 7.0 */
2723 addword (nextword);
2724 break;
2725 }
2726 if (isvar (&opP->disp)
2727 && !subs (&opP->disp)
2728 && adds (&opP->disp)
2729 #ifdef OBJ_ELF
2730 /* If the displacement needs pic relocation it
2731 cannot be relaxed. */
2732 && opP->disp.pic_reloc == pic_none
2733 #endif
2734 && !flag_long_jumps
2735 && !strchr ("~%&$?", s[0]))
2736 {
2737 tmpreg = 0x3A; /* 7.2 */
2738 add_frag (adds (&opP->disp),
2739 SEXT (offs (&opP->disp)),
2740 TAB (ABSTOPCREL, SZ_UNDEF));
2741 break;
2742 }
2743 /* Fall through into long. */
2744 case SIZE_LONG:
2745 if (isvar (&opP->disp))
2746 add_fix ('l', &opP->disp, 0, 0);
2747
2748 tmpreg = 0x39;/* 7.1 mode */
2749 addword (nextword >> 16);
2750 addword (nextword);
2751 break;
2752
2753 case SIZE_BYTE:
2754 as_bad (_("unsupported byte value; use a different suffix"));
2755 /* Fall through. */
2756
2757 case SIZE_WORD:
2758 if (isvar (&opP->disp))
2759 add_fix ('w', &opP->disp, 0, 0);
2760
2761 tmpreg = 0x38;/* 7.0 mode */
2762 addword (nextword);
2763 break;
2764 }
2765 break;
2766 case CONTROL:
2767 case FPREG:
2768 default:
2769 as_bad (_("unknown/incorrect operand"));
2770 /* abort (); */
2771 }
2772
2773 /* If s[0] is '4', then this is for the mac instructions
2774 that can have a trailing_ampersand set. If so, set 0x100
2775 bit on tmpreg so install_gen_operand can check for it and
2776 set the appropriate bit (word2, bit 5). */
2777 if (s[0] == '4')
2778 {
2779 if (opP->trailing_ampersand)
2780 tmpreg |= 0x100;
2781 }
2782 install_gen_operand (s[1], tmpreg);
2783 break;
2784
2785 case '#':
2786 case '^':
2787 switch (s[1])
2788 { /* JF: I hate floating point! */
2789 case 'j':
2790 tmpreg = 70;
2791 break;
2792 case '8':
2793 tmpreg = 20;
2794 break;
2795 case 'C':
2796 tmpreg = 50;
2797 break;
2798 case '3':
2799 default:
2800 tmpreg = 90;
2801 break;
2802 }
2803 tmpreg = get_num (&opP->disp, tmpreg);
2804 if (isvar (&opP->disp))
2805 add_fix (s[1], &opP->disp, 0, 0);
2806 switch (s[1])
2807 {
2808 case 'b': /* Danger: These do no check for
2809 certain types of overflow.
2810 user beware! */
2811 if (!isbyte (tmpreg))
2812 opP->error = _("out of range");
2813 insop (tmpreg, opcode);
2814 if (isvar (&opP->disp))
2815 the_ins.reloc[the_ins.nrel - 1].n =
2816 (opcode->m_codenum) * 2 + 1;
2817 break;
2818 case 'B':
2819 if (!issbyte (tmpreg))
2820 opP->error = _("out of range");
2821 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2822 if (isvar (&opP->disp))
2823 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2824 break;
2825 case 'w':
2826 if (!isword (tmpreg))
2827 opP->error = _("out of range");
2828 insop (tmpreg, opcode);
2829 if (isvar (&opP->disp))
2830 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2831 break;
2832 case 'W':
2833 if (!issword (tmpreg))
2834 opP->error = _("out of range");
2835 insop (tmpreg, opcode);
2836 if (isvar (&opP->disp))
2837 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2838 break;
2839 case 'l':
2840 /* Because of the way insop works, we put these two out
2841 backwards. */
2842 insop (tmpreg, opcode);
2843 insop (tmpreg >> 16, opcode);
2844 if (isvar (&opP->disp))
2845 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2846 break;
2847 case '3':
2848 tmpreg &= 0xFF;
2849 case '8':
2850 case 'C':
2851 case 'j':
2852 install_operand (s[1], tmpreg);
2853 break;
2854 default:
2855 abort ();
2856 }
2857 break;
2858
2859 case '+':
2860 case '-':
2861 case 'A':
2862 case 'a':
2863 install_operand (s[1], opP->reg - ADDR);
2864 break;
2865
2866 case 'B':
2867 tmpreg = get_num (&opP->disp, 90);
2868 switch (s[1])
2869 {
2870 case 'B':
2871 add_fix ('B', &opP->disp, 1, -1);
2872 break;
2873 case 'W':
2874 add_fix ('w', &opP->disp, 1, 0);
2875 addword (0);
2876 break;
2877 case 'L':
2878 long_branch:
2879 if (! HAVE_LONG_BRANCH (current_architecture))
2880 as_warn (_("Can't use long branches on 68000/68010/5200"));
2881 the_ins.opcode[0] |= 0xff;
2882 add_fix ('l', &opP->disp, 1, 0);
2883 addword (0);
2884 addword (0);
2885 break;
2886 case 'g':
2887 if (subs (&opP->disp)) /* We can't relax it. */
2888 goto long_branch;
2889
2890 #ifdef OBJ_ELF
2891 /* If the displacement needs pic relocation it cannot be
2892 relaxed. */
2893 if (opP->disp.pic_reloc != pic_none)
2894 goto long_branch;
2895 #endif
2896 /* This could either be a symbol, or an absolute
2897 address. If it's an absolute address, turn it into
2898 an absolute jump right here and keep it out of the
2899 relaxer. */
2900 if (adds (&opP->disp) == 0)
2901 {
2902 if (the_ins.opcode[0] == 0x6000) /* jbra */
2903 the_ins.opcode[0] = 0x4EF9;
2904 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2905 the_ins.opcode[0] = 0x4EB9;
2906 else /* jCC */
2907 {
2908 the_ins.opcode[0] ^= 0x0100;
2909 the_ins.opcode[0] |= 0x0006;
2910 addword (0x4EF9);
2911 }
2912 add_fix ('l', &opP->disp, 0, 0);
2913 addword (0);
2914 addword (0);
2915 break;
2916 }
2917
2918 /* Now we know it's going into the relaxer. Now figure
2919 out which mode. We try in this order of preference:
2920 long branch, absolute jump, byte/word branches only. */
2921 if (HAVE_LONG_BRANCH (current_architecture))
2922 add_frag (adds (&opP->disp),
2923 SEXT (offs (&opP->disp)),
2924 TAB (BRANCHBWL, SZ_UNDEF));
2925 else if (! flag_keep_pcrel)
2926 {
2927 if ((the_ins.opcode[0] == 0x6000)
2928 || (the_ins.opcode[0] == 0x6100))
2929 add_frag (adds (&opP->disp),
2930 SEXT (offs (&opP->disp)),
2931 TAB (BRABSJUNC, SZ_UNDEF));
2932 else
2933 add_frag (adds (&opP->disp),
2934 SEXT (offs (&opP->disp)),
2935 TAB (BRABSJCOND, SZ_UNDEF));
2936 }
2937 else
2938 add_frag (adds (&opP->disp),
2939 SEXT (offs (&opP->disp)),
2940 TAB (BRANCHBW, SZ_UNDEF));
2941 break;
2942 case 'w':
2943 if (isvar (&opP->disp))
2944 {
2945 /* Check for DBcc instructions. We can relax them,
2946 but only if we have long branches and/or absolute
2947 jumps. */
2948 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2949 && (HAVE_LONG_BRANCH (current_architecture)
2950 || (! flag_keep_pcrel)))
2951 {
2952 if (HAVE_LONG_BRANCH (current_architecture))
2953 add_frag (adds (&opP->disp),
2954 SEXT (offs (&opP->disp)),
2955 TAB (DBCCLBR, SZ_UNDEF));
2956 else
2957 add_frag (adds (&opP->disp),
2958 SEXT (offs (&opP->disp)),
2959 TAB (DBCCABSJ, SZ_UNDEF));
2960 break;
2961 }
2962 add_fix ('w', &opP->disp, 1, 0);
2963 }
2964 addword (0);
2965 break;
2966 case 'C': /* Fixed size LONG coproc branches. */
2967 add_fix ('l', &opP->disp, 1, 0);
2968 addword (0);
2969 addword (0);
2970 break;
2971 case 'c': /* Var size Coprocesssor branches. */
2972 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2973 {
2974 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2975 add_fix ('l', &opP->disp, 1, 0);
2976 addword (0);
2977 addword (0);
2978 }
2979 else
2980 add_frag (adds (&opP->disp),
2981 SEXT (offs (&opP->disp)),
2982 TAB (FBRANCH, SZ_UNDEF));
2983 break;
2984 default:
2985 abort ();
2986 }
2987 break;
2988
2989 case 'C': /* Ignore it. */
2990 break;
2991
2992 case 'd': /* JF this is a kludge. */
2993 install_operand ('s', opP->reg - ADDR);
2994 tmpreg = get_num (&opP->disp, 90);
2995 if (!issword (tmpreg))
2996 {
2997 as_warn (_("Expression out of range, using 0"));
2998 tmpreg = 0;
2999 }
3000 addword (tmpreg);
3001 break;
3002
3003 case 'D':
3004 install_operand (s[1], opP->reg - DATA);
3005 break;
3006
3007 case 'e': /* EMAC ACCx, reg/reg. */
3008 install_operand (s[1], opP->reg - ACC);
3009 break;
3010
3011 case 'E': /* Ignore it. */
3012 break;
3013
3014 case 'F':
3015 install_operand (s[1], opP->reg - FP0);
3016 break;
3017
3018 case 'g': /* EMAC ACCEXTx. */
3019 install_operand (s[1], opP->reg - ACCEXT01);
3020 break;
3021
3022 case 'G': /* Ignore it. */
3023 case 'H':
3024 break;
3025
3026 case 'I':
3027 tmpreg = opP->reg - COP0;
3028 install_operand (s[1], tmpreg);
3029 break;
3030
3031 case 'i': /* MAC/EMAC scale factor. */
3032 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3033 break;
3034
3035 case 'J': /* JF foo. */
3036 switch (opP->reg)
3037 {
3038 case SFC:
3039 tmpreg = 0x000;
3040 break;
3041 case DFC:
3042 tmpreg = 0x001;
3043 break;
3044 case CACR:
3045 tmpreg = 0x002;
3046 break;
3047 case TC:
3048 case ASID:
3049 tmpreg = 0x003;
3050 break;
3051 case ACR0:
3052 case ITT0:
3053 tmpreg = 0x004;
3054 break;
3055 case ACR1:
3056 case ITT1:
3057 tmpreg = 0x005;
3058 break;
3059 case ACR2:
3060 case DTT0:
3061 tmpreg = 0x006;
3062 break;
3063 case ACR3:
3064 case DTT1:
3065 tmpreg = 0x007;
3066 break;
3067 case BUSCR:
3068 case MMUBAR:
3069 tmpreg = 0x008;
3070 break;
3071
3072 case USP:
3073 tmpreg = 0x800;
3074 break;
3075 case VBR:
3076 tmpreg = 0x801;
3077 break;
3078 case CAAR:
3079 tmpreg = 0x802;
3080 break;
3081 case MSP:
3082 tmpreg = 0x803;
3083 break;
3084 case ISP:
3085 tmpreg = 0x804;
3086 break;
3087 case MMUSR:
3088 tmpreg = 0x805;
3089 break;
3090 case URP:
3091 tmpreg = 0x806;
3092 break;
3093 case SRP:
3094 tmpreg = 0x807;
3095 break;
3096 case PCR:
3097 tmpreg = 0x808;
3098 break;
3099 case ROMBAR:
3100 case ROMBAR0:
3101 tmpreg = 0xC00;
3102 break;
3103 case ROMBAR1:
3104 tmpreg = 0xC01;
3105 break;
3106 case FLASHBAR:
3107 case RAMBAR0:
3108 case RAMBAR_ALT:
3109 tmpreg = 0xC04;
3110 break;
3111 case RAMBAR:
3112 case RAMBAR1:
3113 tmpreg = 0xC05;
3114 break;
3115 case MPCR:
3116 tmpreg = 0xC0C;
3117 break;
3118 case EDRAMBAR:
3119 tmpreg = 0xC0D;
3120 break;
3121 case MBAR0:
3122 case MBAR2:
3123 case SECMBAR:
3124 tmpreg = 0xC0E;
3125 break;
3126 case MBAR1:
3127 case MBAR:
3128 tmpreg = 0xC0F;
3129 break;
3130 case PCR1U0:
3131 tmpreg = 0xD02;
3132 break;
3133 case PCR1L0:
3134 tmpreg = 0xD03;
3135 break;
3136 case PCR2U0:
3137 tmpreg = 0xD04;
3138 break;
3139 case PCR2L0:
3140 tmpreg = 0xD05;
3141 break;
3142 case PCR3U0:
3143 tmpreg = 0xD06;
3144 break;
3145 case PCR3L0:
3146 tmpreg = 0xD07;
3147 break;
3148 case PCR1L1:
3149 tmpreg = 0xD0A;
3150 break;
3151 case PCR1U1:
3152 tmpreg = 0xD0B;
3153 break;
3154 case PCR2L1:
3155 tmpreg = 0xD0C;
3156 break;
3157 case PCR2U1:
3158 tmpreg = 0xD0D;
3159 break;
3160 case PCR3L1:
3161 tmpreg = 0xD0E;
3162 break;
3163 case PCR3U1:
3164 tmpreg = 0xD0F;
3165 break;
3166 case CAC:
3167 tmpreg = 0xFFE;
3168 break;
3169 case MBB:
3170 tmpreg = 0xFFF;
3171 break;
3172 default:
3173 abort ();
3174 }
3175 install_operand (s[1], tmpreg);
3176 break;
3177
3178 case 'k':
3179 tmpreg = get_num (&opP->disp, 55);
3180 install_operand (s[1], tmpreg & 0x7f);
3181 break;
3182
3183 case 'l':
3184 tmpreg = opP->mask;
3185 if (s[1] == 'w')
3186 {
3187 if (tmpreg & 0x7FF0000)
3188 as_bad (_("Floating point register in register list"));
3189 insop (reverse_16_bits (tmpreg), opcode);
3190 }
3191 else
3192 {
3193 if (tmpreg & 0x700FFFF)
3194 as_bad (_("Wrong register in floating-point reglist"));
3195 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3196 }
3197 break;
3198
3199 case 'L':
3200 tmpreg = opP->mask;
3201 if (s[1] == 'w')
3202 {
3203 if (tmpreg & 0x7FF0000)
3204 as_bad (_("Floating point register in register list"));
3205 insop (tmpreg, opcode);
3206 }
3207 else if (s[1] == '8')
3208 {
3209 if (tmpreg & 0x0FFFFFF)
3210 as_bad (_("incorrect register in reglist"));
3211 install_operand (s[1], tmpreg >> 24);
3212 }
3213 else
3214 {
3215 if (tmpreg & 0x700FFFF)
3216 as_bad (_("wrong register in floating-point reglist"));
3217 else
3218 install_operand (s[1], tmpreg >> 16);
3219 }
3220 break;
3221
3222 case 'M':
3223 install_operand (s[1], get_num (&opP->disp, 60));
3224 break;
3225
3226 case 'O':
3227 tmpreg = ((opP->mode == DREG)
3228 ? 0x20 + (int) (opP->reg - DATA)
3229 : (get_num (&opP->disp, 40) & 0x1F));
3230 install_operand (s[1], tmpreg);
3231 break;
3232
3233 case 'Q':
3234 tmpreg = get_num (&opP->disp, 10);
3235 if (tmpreg == 8)
3236 tmpreg = 0;
3237 install_operand (s[1], tmpreg);
3238 break;
3239
3240 case 'R':
3241 /* This depends on the fact that ADDR registers are eight
3242 more than their corresponding DATA regs, so the result
3243 will have the ADDR_REG bit set. */
3244 install_operand (s[1], opP->reg - DATA);
3245 break;
3246
3247 case 'r':
3248 if (opP->mode == AINDR)
3249 install_operand (s[1], opP->reg - DATA);
3250 else
3251 install_operand (s[1], opP->index.reg - DATA);
3252 break;
3253
3254 case 's':
3255 if (opP->reg == FPI)
3256 tmpreg = 0x1;
3257 else if (opP->reg == FPS)
3258 tmpreg = 0x2;
3259 else if (opP->reg == FPC)
3260 tmpreg = 0x4;
3261 else
3262 abort ();
3263 install_operand (s[1], tmpreg);
3264 break;
3265
3266 case 'S': /* Ignore it. */
3267 break;
3268
3269 case 'T':
3270 install_operand (s[1], get_num (&opP->disp, 30));
3271 break;
3272
3273 case 'U': /* Ignore it. */
3274 break;
3275
3276 case 'c':
3277 switch (opP->reg)
3278 {
3279 case NC:
3280 tmpreg = 0;
3281 break;
3282 case DC:
3283 tmpreg = 1;
3284 break;
3285 case IC:
3286 tmpreg = 2;
3287 break;
3288 case BC:
3289 tmpreg = 3;
3290 break;
3291 default:
3292 as_fatal (_("failed sanity check"));
3293 } /* switch on cache token. */
3294 install_operand (s[1], tmpreg);
3295 break;
3296 #ifndef NO_68851
3297 /* JF: These are out of order, I fear. */
3298 case 'f':
3299 switch (opP->reg)
3300 {
3301 case SFC:
3302 tmpreg = 0;
3303 break;
3304 case DFC:
3305 tmpreg = 1;
3306 break;
3307 default:
3308 abort ();
3309 }
3310 install_operand (s[1], tmpreg);
3311 break;
3312
3313 case '0':
3314 case '1':
3315 case '2':
3316 switch (opP->reg)
3317 {
3318 case TC:
3319 tmpreg = 0;
3320 break;
3321 case CAL:
3322 tmpreg = 4;
3323 break;
3324 case VAL:
3325 tmpreg = 5;
3326 break;
3327 case SCC:
3328 tmpreg = 6;
3329 break;
3330 case AC:
3331 tmpreg = 7;
3332 break;
3333 default:
3334 abort ();
3335 }
3336 install_operand (s[1], tmpreg);
3337 break;
3338
3339 case 'V':
3340 if (opP->reg == VAL)
3341 break;
3342 abort ();
3343
3344 case 'W':
3345 switch (opP->reg)
3346 {
3347 case DRP:
3348 tmpreg = 1;
3349 break;
3350 case SRP:
3351 tmpreg = 2;
3352 break;
3353 case CRP:
3354 tmpreg = 3;
3355 break;
3356 default:
3357 abort ();
3358 }
3359 install_operand (s[1], tmpreg);
3360 break;
3361
3362 case 'X':
3363 switch (opP->reg)
3364 {
3365 case BAD:
3366 case BAD + 1:
3367 case BAD + 2:
3368 case BAD + 3:
3369 case BAD + 4:
3370 case BAD + 5:
3371 case BAD + 6:
3372 case BAD + 7:
3373 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3374 break;
3375
3376 case BAC:
3377 case BAC + 1:
3378 case BAC + 2:
3379 case BAC + 3:
3380 case BAC + 4:
3381 case BAC + 5:
3382 case BAC + 6:
3383 case BAC + 7:
3384 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3385 break;
3386
3387 default:
3388 abort ();
3389 }
3390 install_operand (s[1], tmpreg);
3391 break;
3392 case 'Y':
3393 know (opP->reg == PSR);
3394 break;
3395 case 'Z':
3396 know (opP->reg == PCSR);
3397 break;
3398 #endif /* m68851 */
3399 case '3':
3400 switch (opP->reg)
3401 {
3402 case TT0:
3403 tmpreg = 2;
3404 break;
3405 case TT1:
3406 tmpreg = 3;
3407 break;
3408 default:
3409 abort ();
3410 }
3411 install_operand (s[1], tmpreg);
3412 break;
3413 case 't':
3414 tmpreg = get_num (&opP->disp, 20);
3415 install_operand (s[1], tmpreg);
3416 break;
3417 case '_': /* used only for move16 absolute 32-bit address. */
3418 if (isvar (&opP->disp))
3419 add_fix ('l', &opP->disp, 0, 0);
3420 tmpreg = get_num (&opP->disp, 90);
3421 addword (tmpreg >> 16);
3422 addword (tmpreg & 0xFFFF);
3423 break;
3424 case 'u':
3425 install_operand (s[1], opP->reg - DATA0L);
3426 opP->reg -= (DATA0L);
3427 opP->reg &= 0x0F; /* remove upper/lower bit. */
3428 break;
3429 case 'x':
3430 tmpreg = get_num (&opP->disp, 80);
3431 if (tmpreg == -1)
3432 tmpreg = 0;
3433 install_operand (s[1], tmpreg);
3434 break;
3435 default:
3436 abort ();
3437 }
3438 }
3439
3440 /* By the time whe get here (FINALLY) the_ins contains the complete
3441 instruction, ready to be emitted. . . */
3442 }
3443
3444 static int
3445 reverse_16_bits (int in)
3446 {
3447 int out = 0;
3448 int n;
3449
3450 static int mask[16] =
3451 {
3452 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3453 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3454 };
3455 for (n = 0; n < 16; n++)
3456 {
3457 if (in & mask[n])
3458 out |= mask[15 - n];
3459 }
3460 return out;
3461 } /* reverse_16_bits() */
3462
3463 static int
3464 reverse_8_bits (int in)
3465 {
3466 int out = 0;
3467 int n;
3468
3469 static int mask[8] =
3470 {
3471 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3472 };
3473
3474 for (n = 0; n < 8; n++)
3475 {
3476 if (in & mask[n])
3477 out |= mask[7 - n];
3478 }
3479 return out;
3480 } /* reverse_8_bits() */
3481
3482 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3483 (that value is chosen in the frag_var call in md_assemble). TYPE
3484 is the subtype of the frag to be generated; its primary type is
3485 rs_machine_dependent.
3486
3487 The TYPE parameter is also used by md_convert_frag_1 and
3488 md_estimate_size_before_relax. The appropriate type of fixup will
3489 be emitted by md_convert_frag_1.
3490
3491 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3492 static void
3493 install_operand (int mode, int val)
3494 {
3495 switch (mode)
3496 {
3497 case 's':
3498 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3499 break;
3500 case 'd':
3501 the_ins.opcode[0] |= val << 9;
3502 break;
3503 case '1':
3504 the_ins.opcode[1] |= val << 12;
3505 break;
3506 case '2':
3507 the_ins.opcode[1] |= val << 6;
3508 break;
3509 case '3':
3510 the_ins.opcode[1] |= val;
3511 break;
3512 case '4':
3513 the_ins.opcode[2] |= val << 12;
3514 break;
3515 case '5':
3516 the_ins.opcode[2] |= val << 6;
3517 break;
3518 case '6':
3519 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3520 three words long! */
3521 the_ins.numo++;
3522 the_ins.opcode[2] |= val;
3523 break;
3524 case '7':
3525 the_ins.opcode[1] |= val << 7;
3526 break;
3527 case '8':
3528 the_ins.opcode[1] |= val << 10;
3529 break;
3530 #ifndef NO_68851
3531 case '9':
3532 the_ins.opcode[1] |= val << 5;
3533 break;
3534 #endif
3535
3536 case 't':
3537 the_ins.opcode[1] |= (val << 10) | (val << 7);
3538 break;
3539 case 'D':
3540 the_ins.opcode[1] |= (val << 12) | val;
3541 break;
3542 case 'g':
3543 the_ins.opcode[0] |= val = 0xff;
3544 break;
3545 case 'i':
3546 the_ins.opcode[0] |= val << 9;
3547 break;
3548 case 'C':
3549 the_ins.opcode[1] |= val;
3550 break;
3551 case 'j':
3552 the_ins.opcode[1] |= val;
3553 the_ins.numo++; /* What a hack. */
3554 break;
3555 case 'k':
3556 the_ins.opcode[1] |= val << 4;
3557 break;
3558 case 'b':
3559 case 'w':
3560 case 'W':
3561 case 'l':
3562 break;
3563 case 'e':
3564 the_ins.opcode[0] |= (val << 6);
3565 break;
3566 case 'L':
3567 the_ins.opcode[1] = (val >> 16);
3568 the_ins.opcode[2] = val & 0xffff;
3569 break;
3570 case 'm':
3571 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3572 the_ins.opcode[0] |= ((val & 0x7) << 9);
3573 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3574 break;
3575 case 'n': /* MAC/EMAC Rx on !load. */
3576 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3577 the_ins.opcode[0] |= ((val & 0x7) << 9);
3578 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3579 break;
3580 case 'o': /* MAC/EMAC Rx on load. */
3581 the_ins.opcode[1] |= val << 12;
3582 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3583 break;
3584 case 'M': /* MAC/EMAC Ry on !load. */
3585 the_ins.opcode[0] |= (val & 0xF);
3586 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3587 break;
3588 case 'N': /* MAC/EMAC Ry on load. */
3589 the_ins.opcode[1] |= (val & 0xF);
3590 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3591 break;
3592 case 'h':
3593 the_ins.opcode[1] |= ((val != 1) << 10);
3594 break;
3595 case 'F':
3596 the_ins.opcode[0] |= ((val & 0x3) << 9);
3597 break;
3598 case 'f':
3599 the_ins.opcode[0] |= ((val & 0x3) << 0);
3600 break;
3601 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3602 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3603 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3604 break;
3605 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3606 the_ins.opcode[0] |= ((val & 0x1) << 7);
3607 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3608 break;
3609 case 'I':
3610 the_ins.opcode[1] |= ((val & 0x3) << 9);
3611 break;
3612 case ']':
3613 the_ins.opcode[0] |= (val & 0x1) <<10;
3614 break;
3615 case 'c':
3616 default:
3617 as_fatal (_("failed sanity check."));
3618 }
3619 }
3620
3621 static void
3622 install_gen_operand (int mode, int val)
3623 {
3624 switch (mode)
3625 {
3626 case '/': /* Special for mask loads for mac/msac insns with
3627 possible mask; trailing_ampersend set in bit 8. */
3628 the_ins.opcode[0] |= (val & 0x3f);
3629 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3630 break;
3631 case 's':
3632 the_ins.opcode[0] |= val;
3633 break;
3634 case 'd':
3635 /* This is a kludge!!! */
3636 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3637 break;
3638 case 'b':
3639 case 'w':
3640 case 'l':
3641 case 'f':
3642 case 'F':
3643 case 'x':
3644 case 'p':
3645 the_ins.opcode[0] |= val;
3646 break;
3647 /* more stuff goes here. */
3648 default:
3649 as_fatal (_("failed sanity check."));
3650 }
3651 }
3652
3653 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3654 then deal with the bitfield hack. */
3655
3656 static char *
3657 crack_operand (char *str, struct m68k_op *opP)
3658 {
3659 register int parens;
3660 register int c;
3661 register char *beg_str;
3662 int inquote = 0;
3663
3664 if (!str)
3665 {
3666 return str;
3667 }
3668 beg_str = str;
3669 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3670 {
3671 if (! inquote)
3672 {
3673 if (*str == '(')
3674 parens++;
3675 else if (*str == ')')
3676 {
3677 if (!parens)
3678 { /* ERROR. */
3679 opP->error = _("Extra )");
3680 return str;
3681 }
3682 --parens;
3683 }
3684 }
3685 if (flag_mri && *str == '\'')
3686 inquote = ! inquote;
3687 }
3688 if (!*str && parens)
3689 { /* ERROR. */
3690 opP->error = _("Missing )");
3691 return str;
3692 }
3693 c = *str;
3694 *str = '\0';
3695 if (m68k_ip_op (beg_str, opP) != 0)
3696 {
3697 *str = c;
3698 return str;
3699 }
3700 *str = c;
3701 if (c == '}')
3702 c = *++str; /* JF bitfield hack. */
3703 if (c)
3704 {
3705 c = *++str;
3706 if (!c)
3707 as_bad (_("Missing operand"));
3708 }
3709
3710 /* Detect MRI REG symbols and convert them to REGLSTs. */
3711 if (opP->mode == CONTROL && (int)opP->reg < 0)
3712 {
3713 opP->mode = REGLST;
3714 opP->mask = ~(int)opP->reg;
3715 opP->reg = 0;
3716 }
3717
3718 return str;
3719 }
3720
3721 /* This is the guts of the machine-dependent assembler. STR points to a
3722 machine dependent instruction. This function is supposed to emit
3723 the frags/bytes it assembles to.
3724 */
3725
3726 static void
3727 insert_reg (const char *regname, int regnum)
3728 {
3729 char buf[100];
3730 int i;
3731
3732 #ifdef REGISTER_PREFIX
3733 if (!flag_reg_prefix_optional)
3734 {
3735 buf[0] = REGISTER_PREFIX;
3736 strcpy (buf + 1, regname);
3737 regname = buf;
3738 }
3739 #endif
3740
3741 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3742 &zero_address_frag));
3743
3744 for (i = 0; regname[i]; i++)
3745 buf[i] = TOUPPER (regname[i]);
3746 buf[i] = '\0';
3747
3748 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3749 &zero_address_frag));
3750 }
3751
3752 struct init_entry
3753 {
3754 const char *name;
3755 int number;
3756 };
3757
3758 static const struct init_entry init_table[] =
3759 {
3760 { "d0", DATA0 },
3761 { "d1", DATA1 },
3762 { "d2", DATA2 },
3763 { "d3", DATA3 },
3764 { "d4", DATA4 },
3765 { "d5", DATA5 },
3766 { "d6", DATA6 },
3767 { "d7", DATA7 },
3768 { "a0", ADDR0 },
3769 { "a1", ADDR1 },
3770 { "a2", ADDR2 },
3771 { "a3", ADDR3 },
3772 { "a4", ADDR4 },
3773 { "a5", ADDR5 },
3774 { "a6", ADDR6 },
3775 { "fp", ADDR6 },
3776 { "a7", ADDR7 },
3777 { "sp", ADDR7 },
3778 { "ssp", ADDR7 },
3779 { "fp0", FP0 },
3780 { "fp1", FP1 },
3781 { "fp2", FP2 },
3782 { "fp3", FP3 },
3783 { "fp4", FP4 },
3784 { "fp5", FP5 },
3785 { "fp6", FP6 },
3786 { "fp7", FP7 },
3787 { "fpi", FPI },
3788 { "fpiar", FPI },
3789 { "fpc", FPI },
3790 { "fps", FPS },
3791 { "fpsr", FPS },
3792 { "fpc", FPC },
3793 { "fpcr", FPC },
3794 { "control", FPC },
3795 { "status", FPS },
3796 { "iaddr", FPI },
3797
3798 { "cop0", COP0 },
3799 { "cop1", COP1 },
3800 { "cop2", COP2 },
3801 { "cop3", COP3 },
3802 { "cop4", COP4 },
3803 { "cop5", COP5 },
3804 { "cop6", COP6 },
3805 { "cop7", COP7 },
3806 { "pc", PC },
3807 { "zpc", ZPC },
3808 { "sr", SR },
3809
3810 { "ccr", CCR },
3811 { "cc", CCR },
3812
3813 { "acc", ACC },
3814 { "acc0", ACC },
3815 { "acc1", ACC1 },
3816 { "acc2", ACC2 },
3817 { "acc3", ACC3 },
3818 { "accext01", ACCEXT01 },
3819 { "accext23", ACCEXT23 },
3820 { "macsr", MACSR },
3821 { "mask", MASK },
3822
3823 /* Control registers. */
3824 { "sfc", SFC }, /* Source Function Code. */
3825 { "sfcr", SFC },
3826 { "dfc", DFC }, /* Destination Function Code. */
3827 { "dfcr", DFC },
3828 { "cacr", CACR }, /* Cache Control Register. */
3829 { "caar", CAAR }, /* Cache Address Register. */
3830
3831 { "usp", USP }, /* User Stack Pointer. */
3832 { "vbr", VBR }, /* Vector Base Register. */
3833 { "msp", MSP }, /* Master Stack Pointer. */
3834 { "isp", ISP }, /* Interrupt Stack Pointer. */
3835
3836 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3837 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3838 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3839 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3840
3841 /* 68ec040 versions of same */
3842 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3843 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3844 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3845 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3846
3847 /* Coldfire versions of same. The ColdFire programmer's reference
3848 manual indicated that the order is 2,3,0,1, but Ken Rose
3849 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3850 { "acr0", ACR0 }, /* Access Control Unit 0. */
3851 { "acr1", ACR1 }, /* Access Control Unit 1. */
3852 { "acr2", ACR2 }, /* Access Control Unit 2. */
3853 { "acr3", ACR3 }, /* Access Control Unit 3. */
3854
3855 { "tc", TC }, /* MMU Translation Control Register. */
3856 { "tcr", TC },
3857 { "asid", ASID },
3858
3859 { "mmusr", MMUSR }, /* MMU Status Register. */
3860 { "srp", SRP }, /* User Root Pointer. */
3861 { "urp", URP }, /* Supervisor Root Pointer. */
3862
3863 { "buscr", BUSCR },
3864 { "mmubar", MMUBAR },
3865 { "pcr", PCR },
3866
3867 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3868 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3869 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3870 { "mbar", MBAR }, /* Module Base Address Register. */
3871
3872 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3873 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3874 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3875 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3876 { "mpcr", MPCR }, /* mcfv4e registers. */
3877 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3878 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3879 { "asid", TC }, /* mcfv4e registers. */
3880 { "mmubar", BUSCR }, /* mcfv4e registers. */
3881 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3882 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3883 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3884 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3885 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3886 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3887 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3888 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3889 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3890 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3891 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3892 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3893
3894 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3895 { "rambar", RAMBAR }, /* mcf528x registers. */
3896
3897 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3898
3899 { "cac", CAC }, /* fido registers. */
3900 { "mbb", MBB }, /* fido registers. */
3901 /* End of control registers. */
3902
3903 { "ac", AC },
3904 { "bc", BC },
3905 { "cal", CAL },
3906 { "crp", CRP },
3907 { "drp", DRP },
3908 { "pcsr", PCSR },
3909 { "psr", PSR },
3910 { "scc", SCC },
3911 { "val", VAL },
3912 { "bad0", BAD0 },
3913 { "bad1", BAD1 },
3914 { "bad2", BAD2 },
3915 { "bad3", BAD3 },
3916 { "bad4", BAD4 },
3917 { "bad5", BAD5 },
3918 { "bad6", BAD6 },
3919 { "bad7", BAD7 },
3920 { "bac0", BAC0 },
3921 { "bac1", BAC1 },
3922 { "bac2", BAC2 },
3923 { "bac3", BAC3 },
3924 { "bac4", BAC4 },
3925 { "bac5", BAC5 },
3926 { "bac6", BAC6 },
3927 { "bac7", BAC7 },
3928
3929 { "ic", IC },
3930 { "dc", DC },
3931 { "nc", NC },
3932
3933 { "tt0", TT0 },
3934 { "tt1", TT1 },
3935 /* 68ec030 versions of same. */
3936 { "ac0", TT0 },
3937 { "ac1", TT1 },
3938 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3939 { "acusr", PSR },
3940
3941 /* Suppressed data and address registers. */
3942 { "zd0", ZDATA0 },
3943 { "zd1", ZDATA1 },
3944 { "zd2", ZDATA2 },
3945 { "zd3", ZDATA3 },
3946 { "zd4", ZDATA4 },
3947 { "zd5", ZDATA5 },
3948 { "zd6", ZDATA6 },
3949 { "zd7", ZDATA7 },
3950 { "za0", ZADDR0 },
3951 { "za1", ZADDR1 },
3952 { "za2", ZADDR2 },
3953 { "za3", ZADDR3 },
3954 { "za4", ZADDR4 },
3955 { "za5", ZADDR5 },
3956 { "za6", ZADDR6 },
3957 { "za7", ZADDR7 },
3958
3959 /* Upper and lower data and address registers, used by macw and msacw. */
3960 { "d0l", DATA0L },
3961 { "d1l", DATA1L },
3962 { "d2l", DATA2L },
3963 { "d3l", DATA3L },
3964 { "d4l", DATA4L },
3965 { "d5l", DATA5L },
3966 { "d6l", DATA6L },
3967 { "d7l", DATA7L },
3968
3969 { "a0l", ADDR0L },
3970 { "a1l", ADDR1L },
3971 { "a2l", ADDR2L },
3972 { "a3l", ADDR3L },
3973 { "a4l", ADDR4L },
3974 { "a5l", ADDR5L },
3975 { "a6l", ADDR6L },
3976 { "a7l", ADDR7L },
3977
3978 { "d0u", DATA0U },
3979 { "d1u", DATA1U },
3980 { "d2u", DATA2U },
3981 { "d3u", DATA3U },
3982 { "d4u", DATA4U },
3983 { "d5u", DATA5U },
3984 { "d6u", DATA6U },
3985 { "d7u", DATA7U },
3986
3987 { "a0u", ADDR0U },
3988 { "a1u", ADDR1U },
3989 { "a2u", ADDR2U },
3990 { "a3u", ADDR3U },
3991 { "a4u", ADDR4U },
3992 { "a5u", ADDR5U },
3993 { "a6u", ADDR6U },
3994 { "a7u", ADDR7U },
3995
3996 { 0, 0 }
3997 };
3998
3999 static void
4000 init_regtable (void)
4001 {
4002 int i;
4003 for (i = 0; init_table[i].name; i++)
4004 insert_reg (init_table[i].name, init_table[i].number);
4005 }
4006
4007 void
4008 md_assemble (char *str)
4009 {
4010 const char *er;
4011 short *fromP;
4012 char *toP = NULL;
4013 int m, n = 0;
4014 char *to_beg_P;
4015 int shorts_this_frag;
4016 fixS *fixP;
4017
4018 if (!selected_cpu && !selected_arch)
4019 {
4020 /* We've not selected an architecture yet. Set the default
4021 now. We do this lazily so that an initial .cpu or .arch directive
4022 can specify. */
4023 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4024 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4025 }
4026 if (!initialized)
4027 m68k_init_arch ();
4028
4029 /* In MRI mode, the instruction and operands are separated by a
4030 space. Anything following the operands is a comment. The label
4031 has already been removed. */
4032 if (flag_mri)
4033 {
4034 char *s;
4035 int fields = 0;
4036 int infield = 0;
4037 int inquote = 0;
4038
4039 for (s = str; *s != '\0'; s++)
4040 {
4041 if ((*s == ' ' || *s == '\t') && ! inquote)
4042 {
4043 if (infield)
4044 {
4045 ++fields;
4046 if (fields >= 2)
4047 {
4048 *s = '\0';
4049 break;
4050 }
4051 infield = 0;
4052 }
4053 }
4054 else
4055 {
4056 if (! infield)
4057 infield = 1;
4058 if (*s == '\'')
4059 inquote = ! inquote;
4060 }
4061 }
4062 }
4063
4064 memset (&the_ins, '\0', sizeof (the_ins));
4065 m68k_ip (str);
4066 er = the_ins.error;
4067 if (!er)
4068 {
4069 for (n = 0; n < the_ins.numargs; n++)
4070 if (the_ins.operands[n].error)
4071 {
4072 er = the_ins.operands[n].error;
4073 break;
4074 }
4075 }
4076 if (er)
4077 {
4078 as_bad (_("%s -- statement `%s' ignored"), er, str);
4079 return;
4080 }
4081
4082 /* If there is a current label, record that it marks an instruction. */
4083 if (current_label != NULL)
4084 {
4085 current_label->text = 1;
4086 current_label = NULL;
4087 }
4088
4089 #ifdef OBJ_ELF
4090 /* Tie dwarf2 debug info to the address at the start of the insn. */
4091 dwarf2_emit_insn (0);
4092 #endif
4093
4094 if (the_ins.nfrag == 0)
4095 {
4096 /* No frag hacking involved; just put it out. */
4097 toP = frag_more (2 * the_ins.numo);
4098 fromP = &the_ins.opcode[0];
4099 for (m = the_ins.numo; m; --m)
4100 {
4101 md_number_to_chars (toP, (long) (*fromP), 2);
4102 toP += 2;
4103 fromP++;
4104 }
4105 /* Put out symbol-dependent info. */
4106 for (m = 0; m < the_ins.nrel; m++)
4107 {
4108 switch (the_ins.reloc[m].wid)
4109 {
4110 case 'B':
4111 n = 1;
4112 break;
4113 case 'b':
4114 n = 1;
4115 break;
4116 case '3':
4117 n = 1;
4118 break;
4119 case 'w':
4120 case 'W':
4121 n = 2;
4122 break;
4123 case 'l':
4124 n = 4;
4125 break;
4126 default:
4127 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4128 the_ins.reloc[m].wid);
4129 }
4130
4131 fixP = fix_new_exp (frag_now,
4132 ((toP - frag_now->fr_literal)
4133 - the_ins.numo * 2 + the_ins.reloc[m].n),
4134 n,
4135 &the_ins.reloc[m].exp,
4136 the_ins.reloc[m].pcrel,
4137 get_reloc_code (n, the_ins.reloc[m].pcrel,
4138 the_ins.reloc[m].pic_reloc));
4139 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4140 if (the_ins.reloc[m].wid == 'B')
4141 fixP->fx_signed = 1;
4142 }
4143 return;
4144 }
4145
4146 /* There's some frag hacking. */
4147 {
4148 /* Calculate the max frag size. */
4149 int wid;
4150
4151 wid = 2 * the_ins.fragb[0].fragoff;
4152 for (n = 1; n < the_ins.nfrag; n++)
4153 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4154 /* frag_var part. */
4155 wid += 10;
4156 /* Make sure the whole insn fits in one chunk, in particular that
4157 the var part is attached, as we access one byte before the
4158 variable frag for byte branches. */
4159 frag_grow (wid);
4160 }
4161
4162 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4163 {
4164 int wid;
4165
4166 if (n == 0)
4167 wid = 2 * the_ins.fragb[n].fragoff;
4168 else
4169 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4170 toP = frag_more (wid);
4171 to_beg_P = toP;
4172 shorts_this_frag = 0;
4173 for (m = wid / 2; m; --m)
4174 {
4175 md_number_to_chars (toP, (long) (*fromP), 2);
4176 toP += 2;
4177 fromP++;
4178 shorts_this_frag++;
4179 }
4180 for (m = 0; m < the_ins.nrel; m++)
4181 {
4182 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4183 {
4184 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4185 break;
4186 }
4187 wid = the_ins.reloc[m].wid;
4188 if (wid == 0)
4189 continue;
4190 the_ins.reloc[m].wid = 0;
4191 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4192
4193 fixP = fix_new_exp (frag_now,
4194 ((toP - frag_now->fr_literal)
4195 - the_ins.numo * 2 + the_ins.reloc[m].n),
4196 wid,
4197 &the_ins.reloc[m].exp,
4198 the_ins.reloc[m].pcrel,
4199 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4200 the_ins.reloc[m].pic_reloc));
4201 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4202 }
4203 (void) frag_var (rs_machine_dependent, 10, 0,
4204 (relax_substateT) (the_ins.fragb[n].fragty),
4205 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4206 }
4207 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4208 shorts_this_frag = 0;
4209 if (n)
4210 {
4211 toP = frag_more (n * 2);
4212 while (n--)
4213 {
4214 md_number_to_chars (toP, (long) (*fromP), 2);
4215 toP += 2;
4216 fromP++;
4217 shorts_this_frag++;
4218 }
4219 }
4220 for (m = 0; m < the_ins.nrel; m++)
4221 {
4222 int wid;
4223
4224 wid = the_ins.reloc[m].wid;
4225 if (wid == 0)
4226 continue;
4227 the_ins.reloc[m].wid = 0;
4228 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4229
4230 fixP = fix_new_exp (frag_now,
4231 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4232 - shorts_this_frag * 2),
4233 wid,
4234 &the_ins.reloc[m].exp,
4235 the_ins.reloc[m].pcrel,
4236 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4237 the_ins.reloc[m].pic_reloc));
4238 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4239 }
4240 }
4241
4242 /* Comparison function used by qsort to rank the opcode entries by name. */
4243
4244 static int
4245 m68k_compare_opcode (const void * v1, const void * v2)
4246 {
4247 struct m68k_opcode * op1, * op2;
4248 int ret;
4249
4250 if (v1 == v2)
4251 return 0;
4252
4253 op1 = *(struct m68k_opcode **) v1;
4254 op2 = *(struct m68k_opcode **) v2;
4255
4256 /* Compare the two names. If different, return the comparison.
4257 If the same, return the order they are in the opcode table. */
4258 ret = strcmp (op1->name, op2->name);
4259 if (ret)
4260 return ret;
4261 if (op1 < op2)
4262 return -1;
4263 return 1;
4264 }
4265
4266 void
4267 md_begin (void)
4268 {
4269 const struct m68k_opcode *ins;
4270 struct m68k_incant *hack, *slak;
4271 const char *retval = 0; /* Empty string, or error msg text. */
4272 int i;
4273
4274 /* Set up hash tables with 68000 instructions.
4275 similar to what the vax assembler does. */
4276 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4277 a copy of it at runtime, adding in the information we want but isn't
4278 there. I think it'd be better to have an awk script hack the table
4279 at compile time. Or even just xstr the table and use it as-is. But
4280 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4281 names. */
4282
4283 if (flag_mri)
4284 {
4285 flag_reg_prefix_optional = 1;
4286 m68k_abspcadd = 1;
4287 if (! m68k_rel32_from_cmdline)
4288 m68k_rel32 = 0;
4289 }
4290
4291 /* First sort the opcode table into alphabetical order to seperate
4292 the order that the assembler wants to see the opcodes from the
4293 order that the disassembler wants to see them. */
4294 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4295 if (!m68k_sorted_opcodes)
4296 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4297 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4298
4299 for (i = m68k_numopcodes; i--;)
4300 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4301
4302 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4303 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4304
4305 op_hash = hash_new ();
4306
4307 obstack_begin (&robyn, 4000);
4308 for (i = 0; i < m68k_numopcodes; i++)
4309 {
4310 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4311 do
4312 {
4313 ins = m68k_sorted_opcodes[i];
4314
4315 /* We *could* ignore insns that don't match our
4316 arch here by just leaving them out of the hash. */
4317 slak->m_operands = ins->args;
4318 slak->m_opnum = strlen (slak->m_operands) / 2;
4319 slak->m_arch = ins->arch;
4320 slak->m_opcode = ins->opcode;
4321 /* This is kludgey. */
4322 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4323 if (i + 1 != m68k_numopcodes
4324 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4325 {
4326 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4327 i++;
4328 }
4329 else
4330 slak->m_next = 0;
4331 slak = slak->m_next;
4332 }
4333 while (slak);
4334
4335 retval = hash_insert (op_hash, ins->name, (char *) hack);
4336 if (retval)
4337 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4338 }
4339
4340 for (i = 0; i < m68k_numaliases; i++)
4341 {
4342 const char *name = m68k_opcode_aliases[i].primary;
4343 const char *alias = m68k_opcode_aliases[i].alias;
4344 PTR val = hash_find (op_hash, name);
4345
4346 if (!val)
4347 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4348 retval = hash_insert (op_hash, alias, val);
4349 if (retval)
4350 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4351 }
4352
4353 /* In MRI mode, all unsized branches are variable sized. Normally,
4354 they are word sized. */
4355 if (flag_mri)
4356 {
4357 static struct m68k_opcode_alias mri_aliases[] =
4358 {
4359 { "bhi", "jhi", },
4360 { "bls", "jls", },
4361 { "bcc", "jcc", },
4362 { "bcs", "jcs", },
4363 { "bne", "jne", },
4364 { "beq", "jeq", },
4365 { "bvc", "jvc", },
4366 { "bvs", "jvs", },
4367 { "bpl", "jpl", },
4368 { "bmi", "jmi", },
4369 { "bge", "jge", },
4370 { "blt", "jlt", },
4371 { "bgt", "jgt", },
4372 { "ble", "jle", },
4373 { "bra", "jra", },
4374 { "bsr", "jbsr", },
4375 };
4376
4377 for (i = 0;
4378 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4379 i++)
4380 {
4381 const char *name = mri_aliases[i].primary;
4382 const char *alias = mri_aliases[i].alias;
4383 PTR val = hash_find (op_hash, name);
4384
4385 if (!val)
4386 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4387 retval = hash_jam (op_hash, alias, val);
4388 if (retval)
4389 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4390 }
4391 }
4392
4393 for (i = 0; i < (int) sizeof (notend_table); i++)
4394 {
4395 notend_table[i] = 0;
4396 alt_notend_table[i] = 0;
4397 }
4398
4399 notend_table[','] = 1;
4400 notend_table['{'] = 1;
4401 notend_table['}'] = 1;
4402 alt_notend_table['a'] = 1;
4403 alt_notend_table['A'] = 1;
4404 alt_notend_table['d'] = 1;
4405 alt_notend_table['D'] = 1;
4406 alt_notend_table['#'] = 1;
4407 alt_notend_table['&'] = 1;
4408 alt_notend_table['f'] = 1;
4409 alt_notend_table['F'] = 1;
4410 #ifdef REGISTER_PREFIX
4411 alt_notend_table[REGISTER_PREFIX] = 1;
4412 #endif
4413
4414 /* We need to put '(' in alt_notend_table to handle
4415 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4416 alt_notend_table['('] = 1;
4417
4418 /* We need to put '@' in alt_notend_table to handle
4419 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4420 alt_notend_table['@'] = 1;
4421
4422 /* We need to put digits in alt_notend_table to handle
4423 bfextu %d0{24:1},%d0 */
4424 alt_notend_table['0'] = 1;
4425 alt_notend_table['1'] = 1;
4426 alt_notend_table['2'] = 1;
4427 alt_notend_table['3'] = 1;
4428 alt_notend_table['4'] = 1;
4429 alt_notend_table['5'] = 1;
4430 alt_notend_table['6'] = 1;
4431 alt_notend_table['7'] = 1;
4432 alt_notend_table['8'] = 1;
4433 alt_notend_table['9'] = 1;
4434
4435 #ifndef MIT_SYNTAX_ONLY
4436 /* Insert pseudo ops, these have to go into the opcode table since
4437 gas expects pseudo ops to start with a dot. */
4438 {
4439 int n = 0;
4440
4441 while (mote_pseudo_table[n].poc_name)
4442 {
4443 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4444 hash_insert (op_hash,
4445 mote_pseudo_table[n].poc_name, (char *) hack);
4446 hack->m_operands = 0;
4447 hack->m_opnum = n;
4448 n++;
4449 }
4450 }
4451 #endif
4452
4453 init_regtable ();
4454
4455 #ifdef OBJ_ELF
4456 record_alignment (text_section, 2);
4457 record_alignment (data_section, 2);
4458 record_alignment (bss_section, 2);
4459 #endif
4460 }
4461
4462 \f
4463 /* This is called when a label is defined. */
4464
4465 void
4466 m68k_frob_label (symbolS *sym)
4467 {
4468 struct label_line *n;
4469
4470 n = (struct label_line *) xmalloc (sizeof *n);
4471 n->next = labels;
4472 n->label = sym;
4473 as_where (&n->file, &n->line);
4474 n->text = 0;
4475 labels = n;
4476 current_label = n;
4477
4478 #ifdef OBJ_ELF
4479 dwarf2_emit_label (sym);
4480 #endif
4481 }
4482
4483 /* This is called when a value that is not an instruction is emitted. */
4484
4485 void
4486 m68k_flush_pending_output (void)
4487 {
4488 current_label = NULL;
4489 }
4490
4491 /* This is called at the end of the assembly, when the final value of
4492 the label is known. We warn if this is a text symbol aligned at an
4493 odd location. */
4494
4495 void
4496 m68k_frob_symbol (symbolS *sym)
4497 {
4498 if (S_GET_SEGMENT (sym) == reg_section
4499 && (int) S_GET_VALUE (sym) < 0)
4500 {
4501 S_SET_SEGMENT (sym, absolute_section);
4502 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4503 }
4504 else if ((S_GET_VALUE (sym) & 1) != 0)
4505 {
4506 struct label_line *l;
4507
4508 for (l = labels; l != NULL; l = l->next)
4509 {
4510 if (l->label == sym)
4511 {
4512 if (l->text)
4513 as_warn_where (l->file, l->line,
4514 _("text label `%s' aligned to odd boundary"),
4515 S_GET_NAME (sym));
4516 break;
4517 }
4518 }
4519 }
4520 }
4521 \f
4522 /* This is called if we go in or out of MRI mode because of the .mri
4523 pseudo-op. */
4524
4525 void
4526 m68k_mri_mode_change (int on)
4527 {
4528 if (on)
4529 {
4530 if (! flag_reg_prefix_optional)
4531 {
4532 flag_reg_prefix_optional = 1;
4533 #ifdef REGISTER_PREFIX
4534 init_regtable ();
4535 #endif
4536 }
4537 m68k_abspcadd = 1;
4538 if (! m68k_rel32_from_cmdline)
4539 m68k_rel32 = 0;
4540 }
4541 else
4542 {
4543 if (! reg_prefix_optional_seen)
4544 {
4545 #ifdef REGISTER_PREFIX_OPTIONAL
4546 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4547 #else
4548 flag_reg_prefix_optional = 0;
4549 #endif
4550 #ifdef REGISTER_PREFIX
4551 init_regtable ();
4552 #endif
4553 }
4554 m68k_abspcadd = 0;
4555 if (! m68k_rel32_from_cmdline)
4556 m68k_rel32 = 1;
4557 }
4558 }
4559
4560 /* Equal to MAX_PRECISION in atof-ieee.c. */
4561 #define MAX_LITTLENUMS 6
4562
4563 /* Turn a string in input_line_pointer into a floating point constant
4564 of type TYPE, and store the appropriate bytes in *LITP. The number
4565 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4566 returned, or NULL on OK. */
4567
4568 char *
4569 md_atof (int type, char *litP, int *sizeP)
4570 {
4571 int prec;
4572 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4573 LITTLENUM_TYPE *wordP;
4574 char *t;
4575
4576 switch (type)
4577 {
4578 case 'f':
4579 case 'F':
4580 case 's':
4581 case 'S':
4582 prec = 2;
4583 break;
4584
4585 case 'd':
4586 case 'D':
4587 case 'r':
4588 case 'R':
4589 prec = 4;
4590 break;
4591
4592 case 'x':
4593 case 'X':
4594 prec = 6;
4595 break;
4596
4597 case 'p':
4598 case 'P':
4599 prec = 6;
4600 break;
4601
4602 default:
4603 *sizeP = 0;
4604 return _("Bad call to MD_ATOF()");
4605 }
4606 t = atof_ieee (input_line_pointer, type, words);
4607 if (t)
4608 input_line_pointer = t;
4609
4610 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4611 for (wordP = words; prec--;)
4612 {
4613 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4614 litP += sizeof (LITTLENUM_TYPE);
4615 }
4616 return 0;
4617 }
4618
4619 void
4620 md_number_to_chars (char *buf, valueT val, int n)
4621 {
4622 number_to_chars_bigendian (buf, val, n);
4623 }
4624
4625 void
4626 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4627 {
4628 offsetT val = *valP;
4629 addressT upper_limit;
4630 offsetT lower_limit;
4631
4632 /* This is unnecessary but it convinces the native rs6000 compiler
4633 to generate the code we want. */
4634 char *buf = fixP->fx_frag->fr_literal;
4635 buf += fixP->fx_where;
4636 /* End ibm compiler workaround. */
4637
4638 val = SEXT (val);
4639
4640 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4641 fixP->fx_done = 1;
4642
4643 #ifdef OBJ_ELF
4644 if (fixP->fx_addsy)
4645 {
4646 memset (buf, 0, fixP->fx_size);
4647 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4648
4649 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4650 && !S_IS_DEFINED (fixP->fx_addsy)
4651 && !S_IS_WEAK (fixP->fx_addsy))
4652 S_SET_WEAK (fixP->fx_addsy);
4653 return;
4654 }
4655 #endif
4656
4657 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4658 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4659 return;
4660
4661 switch (fixP->fx_size)
4662 {
4663 /* The cast to offsetT below are necessary to make code
4664 correct for machines where ints are smaller than offsetT. */
4665 case 1:
4666 *buf++ = val;
4667 upper_limit = 0x7f;
4668 lower_limit = - (offsetT) 0x80;
4669 break;
4670 case 2:
4671 *buf++ = (val >> 8);
4672 *buf++ = val;
4673 upper_limit = 0x7fff;
4674 lower_limit = - (offsetT) 0x8000;
4675 break;
4676 case 4:
4677 *buf++ = (val >> 24);
4678 *buf++ = (val >> 16);
4679 *buf++ = (val >> 8);
4680 *buf++ = val;
4681 upper_limit = 0x7fffffff;
4682 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4683 break;
4684 default:
4685 BAD_CASE (fixP->fx_size);
4686 }
4687
4688 /* Fix up a negative reloc. */
4689 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4690 {
4691 fixP->fx_addsy = fixP->fx_subsy;
4692 fixP->fx_subsy = NULL;
4693 fixP->fx_tcbit = 1;
4694 }
4695
4696 /* For non-pc-relative values, it's conceivable we might get something
4697 like "0xff" for a byte field. So extend the upper part of the range
4698 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4699 so that we can do any range checking at all. */
4700 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4701 upper_limit = upper_limit * 2 + 1;
4702
4703 if ((addressT) val > upper_limit
4704 && (val > 0 || val < lower_limit))
4705 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4706
4707 /* A one byte PC-relative reloc means a short branch. We can't use
4708 a short branch with a value of 0 or -1, because those indicate
4709 different opcodes (branches with longer offsets). fixup_segment
4710 in write.c may have clobbered fx_pcrel, so we need to examine the
4711 reloc type. */
4712 if ((fixP->fx_pcrel
4713 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4714 && fixP->fx_size == 1
4715 && (fixP->fx_addsy == NULL
4716 || S_IS_DEFINED (fixP->fx_addsy))
4717 && (val == 0 || val == -1))
4718 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4719 }
4720
4721 /* *fragP has been relaxed to its final size, and now needs to have
4722 the bytes inside it modified to conform to the new size There is UGLY
4723 MAGIC here. ..
4724 */
4725 static void
4726 md_convert_frag_1 (fragS *fragP)
4727 {
4728 long disp;
4729 fixS *fixP;
4730
4731 /* Address in object code of the displacement. */
4732 register int object_address = fragP->fr_fix + fragP->fr_address;
4733
4734 /* Address in gas core of the place to store the displacement. */
4735 /* This convinces the native rs6000 compiler to generate the code we
4736 want. */
4737 register char *buffer_address = fragP->fr_literal;
4738 buffer_address += fragP->fr_fix;
4739 /* End ibm compiler workaround. */
4740
4741 /* The displacement of the address, from current location. */
4742 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4743 disp = (disp + fragP->fr_offset) - object_address;
4744
4745 switch (fragP->fr_subtype)
4746 {
4747 case TAB (BRANCHBWL, BYTE):
4748 case TAB (BRABSJUNC, BYTE):
4749 case TAB (BRABSJCOND, BYTE):
4750 case TAB (BRANCHBW, BYTE):
4751 know (issbyte (disp));
4752 if (disp == 0)
4753 as_bad_where (fragP->fr_file, fragP->fr_line,
4754 _("short branch with zero offset: use :w"));
4755 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4756 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4757 fixP->fx_pcrel_adjust = -1;
4758 break;
4759 case TAB (BRANCHBWL, SHORT):
4760 case TAB (BRABSJUNC, SHORT):
4761 case TAB (BRABSJCOND, SHORT):
4762 case TAB (BRANCHBW, SHORT):
4763 fragP->fr_opcode[1] = 0x00;
4764 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4765 1, RELAX_RELOC_PC16);
4766 fragP->fr_fix += 2;
4767 break;
4768 case TAB (BRANCHBWL, LONG):
4769 fragP->fr_opcode[1] = (char) 0xFF;
4770 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4771 1, RELAX_RELOC_PC32);
4772 fragP->fr_fix += 4;
4773 break;
4774 case TAB (BRABSJUNC, LONG):
4775 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4776 {
4777 if (flag_keep_pcrel)
4778 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4779 fragP->fr_opcode[0] = 0x4E;
4780 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4781 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4782 0, RELAX_RELOC_ABS32);
4783 fragP->fr_fix += 4;
4784 }
4785 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4786 {
4787 if (flag_keep_pcrel)
4788 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4789 fragP->fr_opcode[0] = 0x4E;
4790 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4791 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4792 0, RELAX_RELOC_ABS32);
4793 fragP->fr_fix += 4;
4794 }
4795 else
4796 {
4797 /* This cannot happen, because jbsr and jbra are the only two
4798 unconditional branches. */
4799 abort ();
4800 }
4801 break;
4802 case TAB (BRABSJCOND, LONG):
4803 if (flag_keep_pcrel)
4804 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4805
4806 /* Only Bcc 68000 instructions can come here
4807 Change bcc into b!cc/jmp absl long. */
4808 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4809 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4810
4811 /* JF: these used to be fr_opcode[2,3], but they may be in a
4812 different frag, in which case referring to them is a no-no.
4813 Only fr_opcode[0,1] are guaranteed to work. */
4814 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4815 *buffer_address++ = (char) 0xf9;
4816 fragP->fr_fix += 2; /* Account for jmp instruction. */
4817 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4818 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4819 fragP->fr_fix += 4;
4820 break;
4821 case TAB (FBRANCH, SHORT):
4822 know ((fragP->fr_opcode[1] & 0x40) == 0);
4823 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4824 1, RELAX_RELOC_PC16);
4825 fragP->fr_fix += 2;
4826 break;
4827 case TAB (FBRANCH, LONG):
4828 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4829 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4830 1, RELAX_RELOC_PC32);
4831 fragP->fr_fix += 4;
4832 break;
4833 case TAB (DBCCLBR, SHORT):
4834 case TAB (DBCCABSJ, SHORT):
4835 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4836 1, RELAX_RELOC_PC16);
4837 fragP->fr_fix += 2;
4838 break;
4839 case TAB (DBCCLBR, LONG):
4840 /* Only DBcc instructions can come here.
4841 Change dbcc into dbcc/bral.
4842 JF: these used to be fr_opcode[2-7], but that's wrong. */
4843 if (flag_keep_pcrel)
4844 as_fatal (_("Tried to convert DBcc to absolute jump"));
4845
4846 *buffer_address++ = 0x00; /* Branch offset = 4. */
4847 *buffer_address++ = 0x04;
4848 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4849 *buffer_address++ = 0x06;
4850 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4851 *buffer_address++ = (char) 0xff;
4852
4853 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4854 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4855 RELAX_RELOC_PC32);
4856 fragP->fr_fix += 4;
4857 break;
4858 case TAB (DBCCABSJ, LONG):
4859 /* Only DBcc instructions can come here.
4860 Change dbcc into dbcc/jmp.
4861 JF: these used to be fr_opcode[2-7], but that's wrong. */
4862 if (flag_keep_pcrel)
4863 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4864
4865 *buffer_address++ = 0x00; /* Branch offset = 4. */
4866 *buffer_address++ = 0x04;
4867 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4868 *buffer_address++ = 0x06;
4869 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4870 *buffer_address++ = (char) 0xf9;
4871
4872 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4873 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4874 RELAX_RELOC_ABS32);
4875 fragP->fr_fix += 4;
4876 break;
4877 case TAB (PCREL1632, SHORT):
4878 fragP->fr_opcode[1] &= ~0x3F;
4879 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4880 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4881 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4882 fragP->fr_fix += 2;
4883 break;
4884 case TAB (PCREL1632, LONG):
4885 /* Already set to mode 7.3; this indicates: PC indirect with
4886 suppressed index, 32-bit displacement. */
4887 *buffer_address++ = 0x01;
4888 *buffer_address++ = 0x70;
4889 fragP->fr_fix += 2;
4890 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4891 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4892 fixP->fx_pcrel_adjust = 2;
4893 fragP->fr_fix += 4;
4894 break;
4895 case TAB (PCINDEX, BYTE):
4896 assert (fragP->fr_fix >= 2);
4897 buffer_address[-2] &= ~1;
4898 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4899 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4900 fixP->fx_pcrel_adjust = 1;
4901 break;
4902 case TAB (PCINDEX, SHORT):
4903 assert (fragP->fr_fix >= 2);
4904 buffer_address[-2] |= 0x1;
4905 buffer_address[-1] = 0x20;
4906 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4907 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4908 fixP->fx_pcrel_adjust = 2;
4909 fragP->fr_fix += 2;
4910 break;
4911 case TAB (PCINDEX, LONG):
4912 assert (fragP->fr_fix >= 2);
4913 buffer_address[-2] |= 0x1;
4914 buffer_address[-1] = 0x30;
4915 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4916 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4917 fixP->fx_pcrel_adjust = 2;
4918 fragP->fr_fix += 4;
4919 break;
4920 case TAB (ABSTOPCREL, SHORT):
4921 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4922 1, RELAX_RELOC_PC16);
4923 fragP->fr_fix += 2;
4924 break;
4925 case TAB (ABSTOPCREL, LONG):
4926 if (flag_keep_pcrel)
4927 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4928 /* The thing to do here is force it to ABSOLUTE LONG, since
4929 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4930 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4931 abort ();
4932 fragP->fr_opcode[1] &= ~0x3F;
4933 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4934 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4935 0, RELAX_RELOC_ABS32);
4936 fragP->fr_fix += 4;
4937 break;
4938 }
4939 }
4940
4941 void
4942 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4943 segT sec ATTRIBUTE_UNUSED,
4944 fragS *fragP)
4945 {
4946 md_convert_frag_1 (fragP);
4947 }
4948
4949 /* Force truly undefined symbols to their maximum size, and generally set up
4950 the frag list to be relaxed
4951 */
4952 int
4953 md_estimate_size_before_relax (fragS *fragP, segT segment)
4954 {
4955 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4956 switch (fragP->fr_subtype)
4957 {
4958 case TAB (BRANCHBWL, SZ_UNDEF):
4959 case TAB (BRABSJUNC, SZ_UNDEF):
4960 case TAB (BRABSJCOND, SZ_UNDEF):
4961 {
4962 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4963 && relaxable_symbol (fragP->fr_symbol))
4964 {
4965 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4966 }
4967 else if (flag_short_refs)
4968 {
4969 /* Symbol is undefined and we want short ref. */
4970 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4971 }
4972 else
4973 {
4974 /* Symbol is still undefined. Make it LONG. */
4975 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4976 }
4977 break;
4978 }
4979
4980 case TAB (BRANCHBW, SZ_UNDEF):
4981 {
4982 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4983 && relaxable_symbol (fragP->fr_symbol))
4984 {
4985 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4986 }
4987 else
4988 {
4989 /* Symbol is undefined and we don't have long branches. */
4990 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4991 }
4992 break;
4993 }
4994
4995 case TAB (FBRANCH, SZ_UNDEF):
4996 case TAB (DBCCLBR, SZ_UNDEF):
4997 case TAB (DBCCABSJ, SZ_UNDEF):
4998 case TAB (PCREL1632, SZ_UNDEF):
4999 {
5000 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5001 && relaxable_symbol (fragP->fr_symbol))
5002 || flag_short_refs)
5003 {
5004 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5005 }
5006 else
5007 {
5008 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5009 }
5010 break;
5011 }
5012
5013 case TAB (PCINDEX, SZ_UNDEF):
5014 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5015 && relaxable_symbol (fragP->fr_symbol)))
5016 {
5017 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5018 }
5019 else
5020 {
5021 fragP->fr_subtype = TAB (PCINDEX, LONG);
5022 }
5023 break;
5024
5025 case TAB (ABSTOPCREL, SZ_UNDEF):
5026 {
5027 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5028 && relaxable_symbol (fragP->fr_symbol)))
5029 {
5030 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5031 }
5032 else
5033 {
5034 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5035 }
5036 break;
5037 }
5038
5039 default:
5040 break;
5041 }
5042
5043 /* Now that SZ_UNDEF are taken care of, check others. */
5044 switch (fragP->fr_subtype)
5045 {
5046 case TAB (BRANCHBWL, BYTE):
5047 case TAB (BRABSJUNC, BYTE):
5048 case TAB (BRABSJCOND, BYTE):
5049 case TAB (BRANCHBW, BYTE):
5050 /* We can't do a short jump to the next instruction, so in that
5051 case we force word mode. If the symbol is at the start of a
5052 frag, and it is the next frag with any data in it (usually
5053 this is just the next frag, but assembler listings may
5054 introduce empty frags), we must use word mode. */
5055 if (fragP->fr_symbol)
5056 {
5057 fragS *sym_frag;
5058
5059 sym_frag = symbol_get_frag (fragP->fr_symbol);
5060 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5061 {
5062 fragS *l;
5063
5064 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5065 if (l->fr_fix != 0)
5066 break;
5067 if (l == sym_frag)
5068 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5069 }
5070 }
5071 break;
5072 default:
5073 break;
5074 }
5075 return md_relax_table[fragP->fr_subtype].rlx_length;
5076 }
5077
5078 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5079 /* the bit-field entries in the relocation_info struct plays hell
5080 with the byte-order problems of cross-assembly. So as a hack,
5081 I added this mach. dependent ri twiddler. Ugly, but it gets
5082 you there. -KWK */
5083 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5084 are symbolnum, most sig. byte first. Last byte is broken up with
5085 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5086 nibble as nuthin. (on Sun 3 at least) */
5087 /* Translate the internal relocation information into target-specific
5088 format. */
5089 #ifdef comment
5090 void
5091 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5092 {
5093 /* This is easy. */
5094 md_number_to_chars (the_bytes, ri->r_address, 4);
5095 /* Now the fun stuff. */
5096 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5097 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5098 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5099 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5100 | ((ri->r_length << 5) & 0x60)
5101 | ((ri->r_extern << 4) & 0x10));
5102 }
5103
5104 #endif
5105
5106 #endif /* OBJ_AOUT or OBJ_BOUT */
5107
5108 #ifndef WORKING_DOT_WORD
5109 int md_short_jump_size = 4;
5110 int md_long_jump_size = 6;
5111
5112 void
5113 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5114 fragS *frag ATTRIBUTE_UNUSED,
5115 symbolS *to_symbol ATTRIBUTE_UNUSED)
5116 {
5117 valueT offset;
5118
5119 offset = to_addr - (from_addr + 2);
5120
5121 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5122 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5123 }
5124
5125 void
5126 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5127 fragS *frag, symbolS *to_symbol)
5128 {
5129 valueT offset;
5130
5131 if (!HAVE_LONG_BRANCH (current_architecture))
5132 {
5133 if (flag_keep_pcrel)
5134 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5135 offset = to_addr - S_GET_VALUE (to_symbol);
5136 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5137 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5138 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5139 0, NO_RELOC);
5140 }
5141 else
5142 {
5143 offset = to_addr - (from_addr + 2);
5144 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5145 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5146 }
5147 }
5148
5149 #endif
5150
5151 /* Different values of OK tell what its OK to return. Things that
5152 aren't OK are an error (what a shock, no?)
5153
5154 0: Everything is OK
5155 10: Absolute 1:8 only
5156 20: Absolute 0:7 only
5157 30: absolute 0:15 only
5158 40: Absolute 0:31 only
5159 50: absolute 0:127 only
5160 55: absolute -64:63 only
5161 60: absolute -128:127 only
5162 70: absolute 0:4095 only
5163 80: absolute -1, 1:7 only
5164 90: No bignums. */
5165
5166 static int
5167 get_num (struct m68k_exp *exp, int ok)
5168 {
5169 if (exp->exp.X_op == O_absent)
5170 {
5171 /* Do the same thing the VAX asm does. */
5172 op (exp) = O_constant;
5173 adds (exp) = 0;
5174 subs (exp) = 0;
5175 offs (exp) = 0;
5176 if (ok == 10)
5177 {
5178 as_warn (_("expression out of range: defaulting to 1"));
5179 offs (exp) = 1;
5180 }
5181 }
5182 else if (exp->exp.X_op == O_constant)
5183 {
5184 switch (ok)
5185 {
5186 case 10:
5187 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5188 {
5189 as_warn (_("expression out of range: defaulting to 1"));
5190 offs (exp) = 1;
5191 }
5192 break;
5193 case 20:
5194 if ((valueT) TRUNC (offs (exp)) > 7)
5195 goto outrange;
5196 break;
5197 case 30:
5198 if ((valueT) TRUNC (offs (exp)) > 15)
5199 goto outrange;
5200 break;
5201 case 40:
5202 if ((valueT) TRUNC (offs (exp)) > 32)
5203 goto outrange;
5204 break;
5205 case 50:
5206 if ((valueT) TRUNC (offs (exp)) > 127)
5207 goto outrange;
5208 break;
5209 case 55:
5210 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5211 goto outrange;
5212 break;
5213 case 60:
5214 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5215 goto outrange;
5216 break;
5217 case 70:
5218 if ((valueT) TRUNC (offs (exp)) > 4095)
5219 {
5220 outrange:
5221 as_warn (_("expression out of range: defaulting to 0"));
5222 offs (exp) = 0;
5223 }
5224 break;
5225 case 80:
5226 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5227 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5228 {
5229 as_warn (_("expression out of range: defaulting to 1"));
5230 offs (exp) = 1;
5231 }
5232 break;
5233 default:
5234 break;
5235 }
5236 }
5237 else if (exp->exp.X_op == O_big)
5238 {
5239 if (offs (exp) <= 0 /* flonum. */
5240 && (ok == 90 /* no bignums */
5241 || (ok > 10 /* Small-int ranges including 0 ok. */
5242 /* If we have a flonum zero, a zero integer should
5243 do as well (e.g., in moveq). */
5244 && generic_floating_point_number.exponent == 0
5245 && generic_floating_point_number.low[0] == 0)))
5246 {
5247 /* HACK! Turn it into a long. */
5248 LITTLENUM_TYPE words[6];
5249
5250 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5251 op (exp) = O_constant;
5252 adds (exp) = 0;
5253 subs (exp) = 0;
5254 offs (exp) = words[1] | (words[0] << 16);
5255 }
5256 else if (ok != 0)
5257 {
5258 op (exp) = O_constant;
5259 adds (exp) = 0;
5260 subs (exp) = 0;
5261 offs (exp) = (ok == 10) ? 1 : 0;
5262 as_warn (_("Can't deal with expression; defaulting to %ld"),
5263 (long) offs (exp));
5264 }
5265 }
5266 else
5267 {
5268 if (ok >= 10 && ok <= 80)
5269 {
5270 op (exp) = O_constant;
5271 adds (exp) = 0;
5272 subs (exp) = 0;
5273 offs (exp) = (ok == 10) ? 1 : 0;
5274 as_warn (_("Can't deal with expression; defaulting to %ld"),
5275 (long) offs (exp));
5276 }
5277 }
5278
5279 if (exp->size != SIZE_UNSPEC)
5280 {
5281 switch (exp->size)
5282 {
5283 case SIZE_UNSPEC:
5284 case SIZE_LONG:
5285 break;
5286 case SIZE_BYTE:
5287 if (!isbyte (offs (exp)))
5288 as_warn (_("expression doesn't fit in BYTE"));
5289 break;
5290 case SIZE_WORD:
5291 if (!isword (offs (exp)))
5292 as_warn (_("expression doesn't fit in WORD"));
5293 break;
5294 }
5295 }
5296
5297 return offs (exp);
5298 }
5299
5300 /* These are the back-ends for the various machine dependent pseudo-ops. */
5301
5302 static void
5303 s_data1 (int ignore ATTRIBUTE_UNUSED)
5304 {
5305 subseg_set (data_section, 1);
5306 demand_empty_rest_of_line ();
5307 }
5308
5309 static void
5310 s_data2 (int ignore ATTRIBUTE_UNUSED)
5311 {
5312 subseg_set (data_section, 2);
5313 demand_empty_rest_of_line ();
5314 }
5315
5316 static void
5317 s_bss (int ignore ATTRIBUTE_UNUSED)
5318 {
5319 /* We don't support putting frags in the BSS segment, we fake it
5320 by marking in_bss, then looking at s_skip for clues. */
5321
5322 subseg_set (bss_section, 0);
5323 demand_empty_rest_of_line ();
5324 }
5325
5326 static void
5327 s_even (int ignore ATTRIBUTE_UNUSED)
5328 {
5329 register int temp;
5330 register long temp_fill;
5331
5332 temp = 1; /* JF should be 2? */
5333 temp_fill = get_absolute_expression ();
5334 if (!need_pass_2) /* Never make frag if expect extra pass. */
5335 frag_align (temp, (int) temp_fill, 0);
5336 demand_empty_rest_of_line ();
5337 record_alignment (now_seg, temp);
5338 }
5339
5340 static void
5341 s_proc (int ignore ATTRIBUTE_UNUSED)
5342 {
5343 demand_empty_rest_of_line ();
5344 }
5345 \f
5346 /* Pseudo-ops handled for MRI compatibility. */
5347
5348 /* This function returns non-zero if the argument is a conditional
5349 pseudo-op. This is called when checking whether a pending
5350 alignment is needed. */
5351
5352 int
5353 m68k_conditional_pseudoop (pseudo_typeS *pop)
5354 {
5355 return (pop->poc_handler == s_mri_if
5356 || pop->poc_handler == s_mri_else);
5357 }
5358
5359 /* Handle an MRI style chip specification. */
5360
5361 static void
5362 mri_chip (void)
5363 {
5364 char *s;
5365 char c;
5366 int i;
5367
5368 s = input_line_pointer;
5369 /* We can't use get_symbol_end since the processor names are not proper
5370 symbols. */
5371 while (is_part_of_name (c = *input_line_pointer++))
5372 ;
5373 *--input_line_pointer = 0;
5374 for (i = 0; m68k_cpus[i].name; i++)
5375 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5376 break;
5377 if (!m68k_cpus[i].name)
5378 {
5379 as_bad (_("%s: unrecognized processor name"), s);
5380 *input_line_pointer = c;
5381 ignore_rest_of_line ();
5382 return;
5383 }
5384 *input_line_pointer = c;
5385
5386 if (*input_line_pointer == '/')
5387 current_architecture = 0;
5388 else
5389 current_architecture &= m68881 | m68851;
5390 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5391 control_regs = m68k_cpus[i].control_regs;
5392
5393 while (*input_line_pointer == '/')
5394 {
5395 ++input_line_pointer;
5396 s = input_line_pointer;
5397 /* We can't use get_symbol_end since the processor names are not
5398 proper symbols. */
5399 while (is_part_of_name (c = *input_line_pointer++))
5400 ;
5401 *--input_line_pointer = 0;
5402 if (strcmp (s, "68881") == 0)
5403 current_architecture |= m68881;
5404 else if (strcmp (s, "68851") == 0)
5405 current_architecture |= m68851;
5406 *input_line_pointer = c;
5407 }
5408 }
5409
5410 /* The MRI CHIP pseudo-op. */
5411
5412 static void
5413 s_chip (int ignore ATTRIBUTE_UNUSED)
5414 {
5415 char *stop = NULL;
5416 char stopc;
5417
5418 if (flag_mri)
5419 stop = mri_comment_field (&stopc);
5420 mri_chip ();
5421 if (flag_mri)
5422 mri_comment_end (stop, stopc);
5423 demand_empty_rest_of_line ();
5424 }
5425
5426 /* The MRI FOPT pseudo-op. */
5427
5428 static void
5429 s_fopt (int ignore ATTRIBUTE_UNUSED)
5430 {
5431 SKIP_WHITESPACE ();
5432
5433 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5434 {
5435 int temp;
5436
5437 input_line_pointer += 3;
5438 temp = get_absolute_expression ();
5439 if (temp < 0 || temp > 7)
5440 as_bad (_("bad coprocessor id"));
5441 else
5442 m68k_float_copnum = COP0 + temp;
5443 }
5444 else
5445 {
5446 as_bad (_("unrecognized fopt option"));
5447 ignore_rest_of_line ();
5448 return;
5449 }
5450
5451 demand_empty_rest_of_line ();
5452 }
5453
5454 /* The structure used to handle the MRI OPT pseudo-op. */
5455
5456 struct opt_action
5457 {
5458 /* The name of the option. */
5459 const char *name;
5460
5461 /* If this is not NULL, just call this function. The first argument
5462 is the ARG field of this structure, the second argument is
5463 whether the option was negated. */
5464 void (*pfn) (int arg, int on);
5465
5466 /* If this is not NULL, and the PFN field is NULL, set the variable
5467 this points to. Set it to the ARG field if the option was not
5468 negated, and the NOTARG field otherwise. */
5469 int *pvar;
5470
5471 /* The value to pass to PFN or to assign to *PVAR. */
5472 int arg;
5473
5474 /* The value to assign to *PVAR if the option is negated. If PFN is
5475 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5476 the option may not be negated. */
5477 int notarg;
5478 };
5479
5480 /* The table used to handle the MRI OPT pseudo-op. */
5481
5482 static void skip_to_comma (int, int);
5483 static void opt_nest (int, int);
5484 static void opt_chip (int, int);
5485 static void opt_list (int, int);
5486 static void opt_list_symbols (int, int);
5487
5488 static const struct opt_action opt_table[] =
5489 {
5490 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5491
5492 /* We do relaxing, so there is little use for these options. */
5493 { "b", 0, 0, 0, 0 },
5494 { "brs", 0, 0, 0, 0 },
5495 { "brb", 0, 0, 0, 0 },
5496 { "brl", 0, 0, 0, 0 },
5497 { "brw", 0, 0, 0, 0 },
5498
5499 { "c", 0, 0, 0, 0 },
5500 { "cex", 0, 0, 0, 0 },
5501 { "case", 0, &symbols_case_sensitive, 1, 0 },
5502 { "cl", 0, 0, 0, 0 },
5503 { "cre", 0, 0, 0, 0 },
5504 { "d", 0, &flag_keep_locals, 1, 0 },
5505 { "e", 0, 0, 0, 0 },
5506 { "f", 0, &flag_short_refs, 1, 0 },
5507 { "frs", 0, &flag_short_refs, 1, 0 },
5508 { "frl", 0, &flag_short_refs, 0, 1 },
5509 { "g", 0, 0, 0, 0 },
5510 { "i", 0, 0, 0, 0 },
5511 { "m", 0, 0, 0, 0 },
5512 { "mex", 0, 0, 0, 0 },
5513 { "mc", 0, 0, 0, 0 },
5514 { "md", 0, 0, 0, 0 },
5515 { "nest", opt_nest, 0, 0, 0 },
5516 { "next", skip_to_comma, 0, 0, 0 },
5517 { "o", 0, 0, 0, 0 },
5518 { "old", 0, 0, 0, 0 },
5519 { "op", skip_to_comma, 0, 0, 0 },
5520 { "pco", 0, 0, 0, 0 },
5521 { "p", opt_chip, 0, 0, 0 },
5522 { "pcr", 0, 0, 0, 0 },
5523 { "pcs", 0, 0, 0, 0 },
5524 { "r", 0, 0, 0, 0 },
5525 { "quick", 0, &m68k_quick, 1, 0 },
5526 { "rel32", 0, &m68k_rel32, 1, 0 },
5527 { "s", opt_list, 0, 0, 0 },
5528 { "t", opt_list_symbols, 0, 0, 0 },
5529 { "w", 0, &flag_no_warnings, 0, 1 },
5530 { "x", 0, 0, 0, 0 }
5531 };
5532
5533 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5534
5535 /* The MRI OPT pseudo-op. */
5536
5537 static void
5538 s_opt (int ignore ATTRIBUTE_UNUSED)
5539 {
5540 do
5541 {
5542 int t;
5543 char *s;
5544 char c;
5545 int i;
5546 const struct opt_action *o;
5547
5548 SKIP_WHITESPACE ();
5549
5550 t = 1;
5551 if (*input_line_pointer == '-')
5552 {
5553 ++input_line_pointer;
5554 t = 0;
5555 }
5556 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5557 {
5558 input_line_pointer += 2;
5559 t = 0;
5560 }
5561
5562 s = input_line_pointer;
5563 c = get_symbol_end ();
5564
5565 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5566 {
5567 if (strcasecmp (s, o->name) == 0)
5568 {
5569 if (o->pfn)
5570 {
5571 /* Restore input_line_pointer now in case the option
5572 takes arguments. */
5573 *input_line_pointer = c;
5574 (*o->pfn) (o->arg, t);
5575 }
5576 else if (o->pvar != NULL)
5577 {
5578 if (! t && o->arg == o->notarg)
5579 as_bad (_("option `%s' may not be negated"), s);
5580 *input_line_pointer = c;
5581 *o->pvar = t ? o->arg : o->notarg;
5582 }
5583 else
5584 *input_line_pointer = c;
5585 break;
5586 }
5587 }
5588 if (i >= OPTCOUNT)
5589 {
5590 as_bad (_("option `%s' not recognized"), s);
5591 *input_line_pointer = c;
5592 }
5593 }
5594 while (*input_line_pointer++ == ',');
5595
5596 /* Move back to terminating character. */
5597 --input_line_pointer;
5598 demand_empty_rest_of_line ();
5599 }
5600
5601 /* Skip ahead to a comma. This is used for OPT options which we do
5602 not support and which take arguments. */
5603
5604 static void
5605 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5606 {
5607 while (*input_line_pointer != ','
5608 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5609 ++input_line_pointer;
5610 }
5611
5612 /* Handle the OPT NEST=depth option. */
5613
5614 static void
5615 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5616 {
5617 if (*input_line_pointer != '=')
5618 {
5619 as_bad (_("bad format of OPT NEST=depth"));
5620 return;
5621 }
5622
5623 ++input_line_pointer;
5624 max_macro_nest = get_absolute_expression ();
5625 }
5626
5627 /* Handle the OPT P=chip option. */
5628
5629 static void
5630 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5631 {
5632 if (*input_line_pointer != '=')
5633 {
5634 /* This is just OPT P, which we do not support. */
5635 return;
5636 }
5637
5638 ++input_line_pointer;
5639 mri_chip ();
5640 }
5641
5642 /* Handle the OPT S option. */
5643
5644 static void
5645 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5646 {
5647 listing_list (on);
5648 }
5649
5650 /* Handle the OPT T option. */
5651
5652 static void
5653 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5654 {
5655 if (on)
5656 listing |= LISTING_SYMBOLS;
5657 else
5658 listing &= ~LISTING_SYMBOLS;
5659 }
5660
5661 /* Handle the MRI REG pseudo-op. */
5662
5663 static void
5664 s_reg (int ignore ATTRIBUTE_UNUSED)
5665 {
5666 char *s;
5667 int c;
5668 struct m68k_op rop;
5669 int mask;
5670 char *stop = NULL;
5671 char stopc;
5672
5673 if (line_label == NULL)
5674 {
5675 as_bad (_("missing label"));
5676 ignore_rest_of_line ();
5677 return;
5678 }
5679
5680 if (flag_mri)
5681 stop = mri_comment_field (&stopc);
5682
5683 SKIP_WHITESPACE ();
5684
5685 s = input_line_pointer;
5686 while (ISALNUM (*input_line_pointer)
5687 #ifdef REGISTER_PREFIX
5688 || *input_line_pointer == REGISTER_PREFIX
5689 #endif
5690 || *input_line_pointer == '/'
5691 || *input_line_pointer == '-')
5692 ++input_line_pointer;
5693 c = *input_line_pointer;
5694 *input_line_pointer = '\0';
5695
5696 if (m68k_ip_op (s, &rop) != 0)
5697 {
5698 if (rop.error == NULL)
5699 as_bad (_("bad register list"));
5700 else
5701 as_bad (_("bad register list: %s"), rop.error);
5702 *input_line_pointer = c;
5703 ignore_rest_of_line ();
5704 return;
5705 }
5706
5707 *input_line_pointer = c;
5708
5709 if (rop.mode == REGLST)
5710 mask = rop.mask;
5711 else if (rop.mode == DREG)
5712 mask = 1 << (rop.reg - DATA0);
5713 else if (rop.mode == AREG)
5714 mask = 1 << (rop.reg - ADDR0 + 8);
5715 else if (rop.mode == FPREG)
5716 mask = 1 << (rop.reg - FP0 + 16);
5717 else if (rop.mode == CONTROL
5718 && rop.reg == FPI)
5719 mask = 1 << 24;
5720 else if (rop.mode == CONTROL
5721 && rop.reg == FPS)
5722 mask = 1 << 25;
5723 else if (rop.mode == CONTROL
5724 && rop.reg == FPC)
5725 mask = 1 << 26;
5726 else
5727 {
5728 as_bad (_("bad register list"));
5729 ignore_rest_of_line ();
5730 return;
5731 }
5732
5733 S_SET_SEGMENT (line_label, reg_section);
5734 S_SET_VALUE (line_label, ~mask);
5735 symbol_set_frag (line_label, &zero_address_frag);
5736
5737 if (flag_mri)
5738 mri_comment_end (stop, stopc);
5739
5740 demand_empty_rest_of_line ();
5741 }
5742
5743 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5744
5745 struct save_opts
5746 {
5747 struct save_opts *next;
5748 int abspcadd;
5749 int symbols_case_sensitive;
5750 int keep_locals;
5751 int short_refs;
5752 int architecture;
5753 const enum m68k_register *control_regs;
5754 int quick;
5755 int rel32;
5756 int listing;
5757 int no_warnings;
5758 /* FIXME: We don't save OPT S. */
5759 };
5760
5761 /* This variable holds the stack of saved options. */
5762
5763 static struct save_opts *save_stack;
5764
5765 /* The MRI SAVE pseudo-op. */
5766
5767 static void
5768 s_save (int ignore ATTRIBUTE_UNUSED)
5769 {
5770 struct save_opts *s;
5771
5772 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5773 s->abspcadd = m68k_abspcadd;
5774 s->symbols_case_sensitive = symbols_case_sensitive;
5775 s->keep_locals = flag_keep_locals;
5776 s->short_refs = flag_short_refs;
5777 s->architecture = current_architecture;
5778 s->control_regs = control_regs;
5779 s->quick = m68k_quick;
5780 s->rel32 = m68k_rel32;
5781 s->listing = listing;
5782 s->no_warnings = flag_no_warnings;
5783
5784 s->next = save_stack;
5785 save_stack = s;
5786
5787 demand_empty_rest_of_line ();
5788 }
5789
5790 /* The MRI RESTORE pseudo-op. */
5791
5792 static void
5793 s_restore (int ignore ATTRIBUTE_UNUSED)
5794 {
5795 struct save_opts *s;
5796
5797 if (save_stack == NULL)
5798 {
5799 as_bad (_("restore without save"));
5800 ignore_rest_of_line ();
5801 return;
5802 }
5803
5804 s = save_stack;
5805 save_stack = s->next;
5806
5807 m68k_abspcadd = s->abspcadd;
5808 symbols_case_sensitive = s->symbols_case_sensitive;
5809 flag_keep_locals = s->keep_locals;
5810 flag_short_refs = s->short_refs;
5811 current_architecture = s->architecture;
5812 control_regs = s->control_regs;
5813 m68k_quick = s->quick;
5814 m68k_rel32 = s->rel32;
5815 listing = s->listing;
5816 flag_no_warnings = s->no_warnings;
5817
5818 free (s);
5819
5820 demand_empty_rest_of_line ();
5821 }
5822
5823 /* Types of MRI structured control directives. */
5824
5825 enum mri_control_type
5826 {
5827 mri_for,
5828 mri_if,
5829 mri_repeat,
5830 mri_while
5831 };
5832
5833 /* This structure is used to stack the MRI structured control
5834 directives. */
5835
5836 struct mri_control_info
5837 {
5838 /* The directive within which this one is enclosed. */
5839 struct mri_control_info *outer;
5840
5841 /* The type of directive. */
5842 enum mri_control_type type;
5843
5844 /* Whether an ELSE has been in an IF. */
5845 int else_seen;
5846
5847 /* The add or sub statement at the end of a FOR. */
5848 char *incr;
5849
5850 /* The label of the top of a FOR or REPEAT loop. */
5851 char *top;
5852
5853 /* The label to jump to for the next iteration, or the else
5854 expression of a conditional. */
5855 char *next;
5856
5857 /* The label to jump to to break out of the loop, or the label past
5858 the end of a conditional. */
5859 char *bottom;
5860 };
5861
5862 /* The stack of MRI structured control directives. */
5863
5864 static struct mri_control_info *mri_control_stack;
5865
5866 /* The current MRI structured control directive index number, used to
5867 generate label names. */
5868
5869 static int mri_control_index;
5870
5871 /* Assemble an instruction for an MRI structured control directive. */
5872
5873 static void
5874 mri_assemble (char *str)
5875 {
5876 char *s;
5877
5878 /* md_assemble expects the opcode to be in lower case. */
5879 for (s = str; *s != ' ' && *s != '\0'; s++)
5880 *s = TOLOWER (*s);
5881
5882 md_assemble (str);
5883 }
5884
5885 /* Generate a new MRI label structured control directive label name. */
5886
5887 static char *
5888 mri_control_label (void)
5889 {
5890 char *n;
5891
5892 n = (char *) xmalloc (20);
5893 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5894 ++mri_control_index;
5895 return n;
5896 }
5897
5898 /* Create a new MRI structured control directive. */
5899
5900 static struct mri_control_info *
5901 push_mri_control (enum mri_control_type type)
5902 {
5903 struct mri_control_info *n;
5904
5905 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5906
5907 n->type = type;
5908 n->else_seen = 0;
5909 if (type == mri_if || type == mri_while)
5910 n->top = NULL;
5911 else
5912 n->top = mri_control_label ();
5913 n->next = mri_control_label ();
5914 n->bottom = mri_control_label ();
5915
5916 n->outer = mri_control_stack;
5917 mri_control_stack = n;
5918
5919 return n;
5920 }
5921
5922 /* Pop off the stack of MRI structured control directives. */
5923
5924 static void
5925 pop_mri_control (void)
5926 {
5927 struct mri_control_info *n;
5928
5929 n = mri_control_stack;
5930 mri_control_stack = n->outer;
5931 if (n->top != NULL)
5932 free (n->top);
5933 free (n->next);
5934 free (n->bottom);
5935 free (n);
5936 }
5937
5938 /* Recognize a condition code in an MRI structured control expression. */
5939
5940 static int
5941 parse_mri_condition (int *pcc)
5942 {
5943 char c1, c2;
5944
5945 know (*input_line_pointer == '<');
5946
5947 ++input_line_pointer;
5948 c1 = *input_line_pointer++;
5949 c2 = *input_line_pointer++;
5950
5951 if (*input_line_pointer != '>')
5952 {
5953 as_bad (_("syntax error in structured control directive"));
5954 return 0;
5955 }
5956
5957 ++input_line_pointer;
5958 SKIP_WHITESPACE ();
5959
5960 c1 = TOLOWER (c1);
5961 c2 = TOLOWER (c2);
5962
5963 *pcc = (c1 << 8) | c2;
5964
5965 return 1;
5966 }
5967
5968 /* Parse a single operand in an MRI structured control expression. */
5969
5970 static int
5971 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5972 char **rightstart, char **rightstop)
5973 {
5974 char *s;
5975
5976 SKIP_WHITESPACE ();
5977
5978 *pcc = -1;
5979 *leftstart = NULL;
5980 *leftstop = NULL;
5981 *rightstart = NULL;
5982 *rightstop = NULL;
5983
5984 if (*input_line_pointer == '<')
5985 {
5986 /* It's just a condition code. */
5987 return parse_mri_condition (pcc);
5988 }
5989
5990 /* Look ahead for the condition code. */
5991 for (s = input_line_pointer; *s != '\0'; ++s)
5992 {
5993 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5994 break;
5995 }
5996 if (*s == '\0')
5997 {
5998 as_bad (_("missing condition code in structured control directive"));
5999 return 0;
6000 }
6001
6002 *leftstart = input_line_pointer;
6003 *leftstop = s;
6004 if (*leftstop > *leftstart
6005 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6006 --*leftstop;
6007
6008 input_line_pointer = s;
6009 if (! parse_mri_condition (pcc))
6010 return 0;
6011
6012 /* Look ahead for AND or OR or end of line. */
6013 for (s = input_line_pointer; *s != '\0'; ++s)
6014 {
6015 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6016 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6017 ^^^ ^^ */
6018 if ((s == input_line_pointer
6019 || *(s-1) == ' '
6020 || *(s-1) == '\t')
6021 && ((strncasecmp (s, "AND", 3) == 0
6022 && (s[3] == '.' || ! is_part_of_name (s[3])))
6023 || (strncasecmp (s, "OR", 2) == 0
6024 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6025 break;
6026 }
6027
6028 *rightstart = input_line_pointer;
6029 *rightstop = s;
6030 if (*rightstop > *rightstart
6031 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6032 --*rightstop;
6033
6034 input_line_pointer = s;
6035
6036 return 1;
6037 }
6038
6039 #define MCC(b1, b2) (((b1) << 8) | (b2))
6040
6041 /* Swap the sense of a condition. This changes the condition so that
6042 it generates the same result when the operands are swapped. */
6043
6044 static int
6045 swap_mri_condition (int cc)
6046 {
6047 switch (cc)
6048 {
6049 case MCC ('h', 'i'): return MCC ('c', 's');
6050 case MCC ('l', 's'): return MCC ('c', 'c');
6051 /* <HS> is an alias for <CC>. */
6052 case MCC ('h', 's'):
6053 case MCC ('c', 'c'): return MCC ('l', 's');
6054 /* <LO> is an alias for <CS>. */
6055 case MCC ('l', 'o'):
6056 case MCC ('c', 's'): return MCC ('h', 'i');
6057 case MCC ('p', 'l'): return MCC ('m', 'i');
6058 case MCC ('m', 'i'): return MCC ('p', 'l');
6059 case MCC ('g', 'e'): return MCC ('l', 'e');
6060 case MCC ('l', 't'): return MCC ('g', 't');
6061 case MCC ('g', 't'): return MCC ('l', 't');
6062 case MCC ('l', 'e'): return MCC ('g', 'e');
6063 /* Issue a warning for conditions we can not swap. */
6064 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6065 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6066 case MCC ('v', 'c'):
6067 case MCC ('v', 's'):
6068 default :
6069 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6070 (char) (cc >> 8), (char) (cc));
6071 break;
6072 }
6073 return cc;
6074 }
6075
6076 /* Reverse the sense of a condition. */
6077
6078 static int
6079 reverse_mri_condition (int cc)
6080 {
6081 switch (cc)
6082 {
6083 case MCC ('h', 'i'): return MCC ('l', 's');
6084 case MCC ('l', 's'): return MCC ('h', 'i');
6085 /* <HS> is an alias for <CC> */
6086 case MCC ('h', 's'): return MCC ('l', 'o');
6087 case MCC ('c', 'c'): return MCC ('c', 's');
6088 /* <LO> is an alias for <CS> */
6089 case MCC ('l', 'o'): return MCC ('h', 's');
6090 case MCC ('c', 's'): return MCC ('c', 'c');
6091 case MCC ('n', 'e'): return MCC ('e', 'q');
6092 case MCC ('e', 'q'): return MCC ('n', 'e');
6093 case MCC ('v', 'c'): return MCC ('v', 's');
6094 case MCC ('v', 's'): return MCC ('v', 'c');
6095 case MCC ('p', 'l'): return MCC ('m', 'i');
6096 case MCC ('m', 'i'): return MCC ('p', 'l');
6097 case MCC ('g', 'e'): return MCC ('l', 't');
6098 case MCC ('l', 't'): return MCC ('g', 'e');
6099 case MCC ('g', 't'): return MCC ('l', 'e');
6100 case MCC ('l', 'e'): return MCC ('g', 't');
6101 }
6102 return cc;
6103 }
6104
6105 /* Build an MRI structured control expression. This generates test
6106 and branch instructions. It goes to TRUELAB if the condition is
6107 true, and to FALSELAB if the condition is false. Exactly one of
6108 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6109 is the size qualifier for the expression. EXTENT is the size to
6110 use for the branch. */
6111
6112 static void
6113 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6114 char *rightstart, char *rightstop,
6115 const char *truelab, const char *falselab,
6116 int extent)
6117 {
6118 char *buf;
6119 char *s;
6120
6121 if (leftstart != NULL)
6122 {
6123 struct m68k_op leftop, rightop;
6124 char c;
6125
6126 /* Swap the compare operands, if necessary, to produce a legal
6127 m68k compare instruction. Comparing a register operand with
6128 a non-register operand requires the register to be on the
6129 right (cmp, cmpa). Comparing an immediate value with
6130 anything requires the immediate value to be on the left
6131 (cmpi). */
6132
6133 c = *leftstop;
6134 *leftstop = '\0';
6135 (void) m68k_ip_op (leftstart, &leftop);
6136 *leftstop = c;
6137
6138 c = *rightstop;
6139 *rightstop = '\0';
6140 (void) m68k_ip_op (rightstart, &rightop);
6141 *rightstop = c;
6142
6143 if (rightop.mode == IMMED
6144 || ((leftop.mode == DREG || leftop.mode == AREG)
6145 && (rightop.mode != DREG && rightop.mode != AREG)))
6146 {
6147 char *temp;
6148
6149 /* Correct conditional handling:
6150 if #1 <lt> d0 then ;means if (1 < d0)
6151 ...
6152 endi
6153
6154 should assemble to:
6155
6156 cmp #1,d0 if we do *not* swap the operands
6157 bgt true we need the swapped condition!
6158 ble false
6159 true:
6160 ...
6161 false:
6162 */
6163 temp = leftstart;
6164 leftstart = rightstart;
6165 rightstart = temp;
6166 temp = leftstop;
6167 leftstop = rightstop;
6168 rightstop = temp;
6169 }
6170 else
6171 {
6172 cc = swap_mri_condition (cc);
6173 }
6174 }
6175
6176 if (truelab == NULL)
6177 {
6178 cc = reverse_mri_condition (cc);
6179 truelab = falselab;
6180 }
6181
6182 if (leftstart != NULL)
6183 {
6184 buf = (char *) xmalloc (20
6185 + (leftstop - leftstart)
6186 + (rightstop - rightstart));
6187 s = buf;
6188 *s++ = 'c';
6189 *s++ = 'm';
6190 *s++ = 'p';
6191 if (qual != '\0')
6192 *s++ = TOLOWER (qual);
6193 *s++ = ' ';
6194 memcpy (s, leftstart, leftstop - leftstart);
6195 s += leftstop - leftstart;
6196 *s++ = ',';
6197 memcpy (s, rightstart, rightstop - rightstart);
6198 s += rightstop - rightstart;
6199 *s = '\0';
6200 mri_assemble (buf);
6201 free (buf);
6202 }
6203
6204 buf = (char *) xmalloc (20 + strlen (truelab));
6205 s = buf;
6206 *s++ = 'b';
6207 *s++ = cc >> 8;
6208 *s++ = cc & 0xff;
6209 if (extent != '\0')
6210 *s++ = TOLOWER (extent);
6211 *s++ = ' ';
6212 strcpy (s, truelab);
6213 mri_assemble (buf);
6214 free (buf);
6215 }
6216
6217 /* Parse an MRI structured control expression. This generates test
6218 and branch instructions. STOP is where the expression ends. It
6219 goes to TRUELAB if the condition is true, and to FALSELAB if the
6220 condition is false. Exactly one of TRUELAB and FALSELAB will be
6221 NULL, meaning to fall through. QUAL is the size qualifier for the
6222 expression. EXTENT is the size to use for the branch. */
6223
6224 static void
6225 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6226 const char *falselab, int extent)
6227 {
6228 int c;
6229 int cc;
6230 char *leftstart;
6231 char *leftstop;
6232 char *rightstart;
6233 char *rightstop;
6234
6235 c = *stop;
6236 *stop = '\0';
6237
6238 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6239 &rightstart, &rightstop))
6240 {
6241 *stop = c;
6242 return;
6243 }
6244
6245 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6246 {
6247 const char *flab;
6248
6249 if (falselab != NULL)
6250 flab = falselab;
6251 else
6252 flab = mri_control_label ();
6253
6254 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6255 rightstop, (const char *) NULL, flab, extent);
6256
6257 input_line_pointer += 3;
6258 if (*input_line_pointer != '.'
6259 || input_line_pointer[1] == '\0')
6260 qual = '\0';
6261 else
6262 {
6263 qual = input_line_pointer[1];
6264 input_line_pointer += 2;
6265 }
6266
6267 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6268 &rightstart, &rightstop))
6269 {
6270 *stop = c;
6271 return;
6272 }
6273
6274 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6275 rightstop, truelab, falselab, extent);
6276
6277 if (falselab == NULL)
6278 colon (flab);
6279 }
6280 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6281 {
6282 const char *tlab;
6283
6284 if (truelab != NULL)
6285 tlab = truelab;
6286 else
6287 tlab = mri_control_label ();
6288
6289 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6290 rightstop, tlab, (const char *) NULL, extent);
6291
6292 input_line_pointer += 2;
6293 if (*input_line_pointer != '.'
6294 || input_line_pointer[1] == '\0')
6295 qual = '\0';
6296 else
6297 {
6298 qual = input_line_pointer[1];
6299 input_line_pointer += 2;
6300 }
6301
6302 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6303 &rightstart, &rightstop))
6304 {
6305 *stop = c;
6306 return;
6307 }
6308
6309 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6310 rightstop, truelab, falselab, extent);
6311
6312 if (truelab == NULL)
6313 colon (tlab);
6314 }
6315 else
6316 {
6317 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6318 rightstop, truelab, falselab, extent);
6319 }
6320
6321 *stop = c;
6322 if (input_line_pointer != stop)
6323 as_bad (_("syntax error in structured control directive"));
6324 }
6325
6326 /* Handle the MRI IF pseudo-op. This may be a structured control
6327 directive, or it may be a regular assembler conditional, depending
6328 on its operands. */
6329
6330 static void
6331 s_mri_if (int qual)
6332 {
6333 char *s;
6334 int c;
6335 struct mri_control_info *n;
6336
6337 /* A structured control directive must end with THEN with an
6338 optional qualifier. */
6339 s = input_line_pointer;
6340 /* We only accept '*' as introduction of comments if preceded by white space
6341 or at first column of a line (I think this can't actually happen here?)
6342 This is important when assembling:
6343 if d0 <ne> 12(a0,d0*2) then
6344 if d0 <ne> #CONST*20 then. */
6345 while (! (is_end_of_line[(unsigned char) *s]
6346 || (flag_mri
6347 && *s == '*'
6348 && (s == input_line_pointer
6349 || *(s-1) == ' '
6350 || *(s-1) == '\t'))))
6351 ++s;
6352 --s;
6353 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6354 --s;
6355
6356 if (s - input_line_pointer > 1
6357 && s[-1] == '.')
6358 s -= 2;
6359
6360 if (s - input_line_pointer < 3
6361 || strncasecmp (s - 3, "THEN", 4) != 0)
6362 {
6363 if (qual != '\0')
6364 {
6365 as_bad (_("missing then"));
6366 ignore_rest_of_line ();
6367 return;
6368 }
6369
6370 /* It's a conditional. */
6371 s_if (O_ne);
6372 return;
6373 }
6374
6375 /* Since this might be a conditional if, this pseudo-op will be
6376 called even if we are supported to be ignoring input. Double
6377 check now. Clobber *input_line_pointer so that ignore_input
6378 thinks that this is not a special pseudo-op. */
6379 c = *input_line_pointer;
6380 *input_line_pointer = 0;
6381 if (ignore_input ())
6382 {
6383 *input_line_pointer = c;
6384 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6385 ++input_line_pointer;
6386 demand_empty_rest_of_line ();
6387 return;
6388 }
6389 *input_line_pointer = c;
6390
6391 n = push_mri_control (mri_if);
6392
6393 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6394 n->next, s[1] == '.' ? s[2] : '\0');
6395
6396 if (s[1] == '.')
6397 input_line_pointer = s + 3;
6398 else
6399 input_line_pointer = s + 1;
6400
6401 if (flag_mri)
6402 {
6403 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6404 ++input_line_pointer;
6405 }
6406
6407 demand_empty_rest_of_line ();
6408 }
6409
6410 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6411 structured IF, associate the ELSE with the IF. Otherwise, assume
6412 it is a conditional else. */
6413
6414 static void
6415 s_mri_else (int qual)
6416 {
6417 int c;
6418 char *buf;
6419 char q[2];
6420
6421 if (qual == '\0'
6422 && (mri_control_stack == NULL
6423 || mri_control_stack->type != mri_if
6424 || mri_control_stack->else_seen))
6425 {
6426 s_else (0);
6427 return;
6428 }
6429
6430 c = *input_line_pointer;
6431 *input_line_pointer = 0;
6432 if (ignore_input ())
6433 {
6434 *input_line_pointer = c;
6435 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6436 ++input_line_pointer;
6437 demand_empty_rest_of_line ();
6438 return;
6439 }
6440 *input_line_pointer = c;
6441
6442 if (mri_control_stack == NULL
6443 || mri_control_stack->type != mri_if
6444 || mri_control_stack->else_seen)
6445 {
6446 as_bad (_("else without matching if"));
6447 ignore_rest_of_line ();
6448 return;
6449 }
6450
6451 mri_control_stack->else_seen = 1;
6452
6453 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6454 q[0] = TOLOWER (qual);
6455 q[1] = '\0';
6456 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6457 mri_assemble (buf);
6458 free (buf);
6459
6460 colon (mri_control_stack->next);
6461
6462 if (flag_mri)
6463 {
6464 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6465 ++input_line_pointer;
6466 }
6467
6468 demand_empty_rest_of_line ();
6469 }
6470
6471 /* Handle the MRI ENDI pseudo-op. */
6472
6473 static void
6474 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6475 {
6476 if (mri_control_stack == NULL
6477 || mri_control_stack->type != mri_if)
6478 {
6479 as_bad (_("endi without matching if"));
6480 ignore_rest_of_line ();
6481 return;
6482 }
6483
6484 /* ignore_input will not return true for ENDI, so we don't need to
6485 worry about checking it again here. */
6486
6487 if (! mri_control_stack->else_seen)
6488 colon (mri_control_stack->next);
6489 colon (mri_control_stack->bottom);
6490
6491 pop_mri_control ();
6492
6493 if (flag_mri)
6494 {
6495 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6496 ++input_line_pointer;
6497 }
6498
6499 demand_empty_rest_of_line ();
6500 }
6501
6502 /* Handle the MRI BREAK pseudo-op. */
6503
6504 static void
6505 s_mri_break (int extent)
6506 {
6507 struct mri_control_info *n;
6508 char *buf;
6509 char ex[2];
6510
6511 n = mri_control_stack;
6512 while (n != NULL
6513 && n->type != mri_for
6514 && n->type != mri_repeat
6515 && n->type != mri_while)
6516 n = n->outer;
6517 if (n == NULL)
6518 {
6519 as_bad (_("break outside of structured loop"));
6520 ignore_rest_of_line ();
6521 return;
6522 }
6523
6524 buf = (char *) xmalloc (20 + strlen (n->bottom));
6525 ex[0] = TOLOWER (extent);
6526 ex[1] = '\0';
6527 sprintf (buf, "bra%s %s", ex, n->bottom);
6528 mri_assemble (buf);
6529 free (buf);
6530
6531 if (flag_mri)
6532 {
6533 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6534 ++input_line_pointer;
6535 }
6536
6537 demand_empty_rest_of_line ();
6538 }
6539
6540 /* Handle the MRI NEXT pseudo-op. */
6541
6542 static void
6543 s_mri_next (int extent)
6544 {
6545 struct mri_control_info *n;
6546 char *buf;
6547 char ex[2];
6548
6549 n = mri_control_stack;
6550 while (n != NULL
6551 && n->type != mri_for
6552 && n->type != mri_repeat
6553 && n->type != mri_while)
6554 n = n->outer;
6555 if (n == NULL)
6556 {
6557 as_bad (_("next outside of structured loop"));
6558 ignore_rest_of_line ();
6559 return;
6560 }
6561
6562 buf = (char *) xmalloc (20 + strlen (n->next));
6563 ex[0] = TOLOWER (extent);
6564 ex[1] = '\0';
6565 sprintf (buf, "bra%s %s", ex, n->next);
6566 mri_assemble (buf);
6567 free (buf);
6568
6569 if (flag_mri)
6570 {
6571 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6572 ++input_line_pointer;
6573 }
6574
6575 demand_empty_rest_of_line ();
6576 }
6577
6578 /* Handle the MRI FOR pseudo-op. */
6579
6580 static void
6581 s_mri_for (int qual)
6582 {
6583 const char *varstart, *varstop;
6584 const char *initstart, *initstop;
6585 const char *endstart, *endstop;
6586 const char *bystart, *bystop;
6587 int up;
6588 int by;
6589 int extent;
6590 struct mri_control_info *n;
6591 char *buf;
6592 char *s;
6593 char ex[2];
6594
6595 /* The syntax is
6596 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6597 */
6598
6599 SKIP_WHITESPACE ();
6600 varstart = input_line_pointer;
6601
6602 /* Look for the '='. */
6603 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6604 && *input_line_pointer != '=')
6605 ++input_line_pointer;
6606 if (*input_line_pointer != '=')
6607 {
6608 as_bad (_("missing ="));
6609 ignore_rest_of_line ();
6610 return;
6611 }
6612
6613 varstop = input_line_pointer;
6614 if (varstop > varstart
6615 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6616 --varstop;
6617
6618 ++input_line_pointer;
6619
6620 initstart = input_line_pointer;
6621
6622 /* Look for TO or DOWNTO. */
6623 up = 1;
6624 initstop = NULL;
6625 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6626 {
6627 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6628 && ! is_part_of_name (input_line_pointer[2]))
6629 {
6630 initstop = input_line_pointer;
6631 input_line_pointer += 2;
6632 break;
6633 }
6634 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6635 && ! is_part_of_name (input_line_pointer[6]))
6636 {
6637 initstop = input_line_pointer;
6638 up = 0;
6639 input_line_pointer += 6;
6640 break;
6641 }
6642 ++input_line_pointer;
6643 }
6644 if (initstop == NULL)
6645 {
6646 as_bad (_("missing to or downto"));
6647 ignore_rest_of_line ();
6648 return;
6649 }
6650 if (initstop > initstart
6651 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6652 --initstop;
6653
6654 SKIP_WHITESPACE ();
6655 endstart = input_line_pointer;
6656
6657 /* Look for BY or DO. */
6658 by = 0;
6659 endstop = NULL;
6660 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6661 {
6662 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6663 && ! is_part_of_name (input_line_pointer[2]))
6664 {
6665 endstop = input_line_pointer;
6666 by = 1;
6667 input_line_pointer += 2;
6668 break;
6669 }
6670 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6671 && (input_line_pointer[2] == '.'
6672 || ! is_part_of_name (input_line_pointer[2])))
6673 {
6674 endstop = input_line_pointer;
6675 input_line_pointer += 2;
6676 break;
6677 }
6678 ++input_line_pointer;
6679 }
6680 if (endstop == NULL)
6681 {
6682 as_bad (_("missing do"));
6683 ignore_rest_of_line ();
6684 return;
6685 }
6686 if (endstop > endstart
6687 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6688 --endstop;
6689
6690 if (! by)
6691 {
6692 bystart = "#1";
6693 bystop = bystart + 2;
6694 }
6695 else
6696 {
6697 SKIP_WHITESPACE ();
6698 bystart = input_line_pointer;
6699
6700 /* Look for DO. */
6701 bystop = NULL;
6702 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6703 {
6704 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6705 && (input_line_pointer[2] == '.'
6706 || ! is_part_of_name (input_line_pointer[2])))
6707 {
6708 bystop = input_line_pointer;
6709 input_line_pointer += 2;
6710 break;
6711 }
6712 ++input_line_pointer;
6713 }
6714 if (bystop == NULL)
6715 {
6716 as_bad (_("missing do"));
6717 ignore_rest_of_line ();
6718 return;
6719 }
6720 if (bystop > bystart
6721 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6722 --bystop;
6723 }
6724
6725 if (*input_line_pointer != '.')
6726 extent = '\0';
6727 else
6728 {
6729 extent = input_line_pointer[1];
6730 input_line_pointer += 2;
6731 }
6732
6733 /* We have fully parsed the FOR operands. Now build the loop. */
6734 n = push_mri_control (mri_for);
6735
6736 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6737
6738 /* Move init,var. */
6739 s = buf;
6740 *s++ = 'm';
6741 *s++ = 'o';
6742 *s++ = 'v';
6743 *s++ = 'e';
6744 if (qual != '\0')
6745 *s++ = TOLOWER (qual);
6746 *s++ = ' ';
6747 memcpy (s, initstart, initstop - initstart);
6748 s += initstop - initstart;
6749 *s++ = ',';
6750 memcpy (s, varstart, varstop - varstart);
6751 s += varstop - varstart;
6752 *s = '\0';
6753 mri_assemble (buf);
6754
6755 colon (n->top);
6756
6757 /* cmp end,var. */
6758 s = buf;
6759 *s++ = 'c';
6760 *s++ = 'm';
6761 *s++ = 'p';
6762 if (qual != '\0')
6763 *s++ = TOLOWER (qual);
6764 *s++ = ' ';
6765 memcpy (s, endstart, endstop - endstart);
6766 s += endstop - endstart;
6767 *s++ = ',';
6768 memcpy (s, varstart, varstop - varstart);
6769 s += varstop - varstart;
6770 *s = '\0';
6771 mri_assemble (buf);
6772
6773 /* bcc bottom. */
6774 ex[0] = TOLOWER (extent);
6775 ex[1] = '\0';
6776 if (up)
6777 sprintf (buf, "blt%s %s", ex, n->bottom);
6778 else
6779 sprintf (buf, "bgt%s %s", ex, n->bottom);
6780 mri_assemble (buf);
6781
6782 /* Put together the add or sub instruction used by ENDF. */
6783 s = buf;
6784 if (up)
6785 strcpy (s, "add");
6786 else
6787 strcpy (s, "sub");
6788 s += 3;
6789 if (qual != '\0')
6790 *s++ = TOLOWER (qual);
6791 *s++ = ' ';
6792 memcpy (s, bystart, bystop - bystart);
6793 s += bystop - bystart;
6794 *s++ = ',';
6795 memcpy (s, varstart, varstop - varstart);
6796 s += varstop - varstart;
6797 *s = '\0';
6798 n->incr = buf;
6799
6800 if (flag_mri)
6801 {
6802 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6803 ++input_line_pointer;
6804 }
6805
6806 demand_empty_rest_of_line ();
6807 }
6808
6809 /* Handle the MRI ENDF pseudo-op. */
6810
6811 static void
6812 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6813 {
6814 if (mri_control_stack == NULL
6815 || mri_control_stack->type != mri_for)
6816 {
6817 as_bad (_("endf without for"));
6818 ignore_rest_of_line ();
6819 return;
6820 }
6821
6822 colon (mri_control_stack->next);
6823
6824 mri_assemble (mri_control_stack->incr);
6825
6826 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6827 mri_assemble (mri_control_stack->incr);
6828
6829 free (mri_control_stack->incr);
6830
6831 colon (mri_control_stack->bottom);
6832
6833 pop_mri_control ();
6834
6835 if (flag_mri)
6836 {
6837 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6838 ++input_line_pointer;
6839 }
6840
6841 demand_empty_rest_of_line ();
6842 }
6843
6844 /* Handle the MRI REPEAT pseudo-op. */
6845
6846 static void
6847 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6848 {
6849 struct mri_control_info *n;
6850
6851 n = push_mri_control (mri_repeat);
6852 colon (n->top);
6853 if (flag_mri)
6854 {
6855 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6856 ++input_line_pointer;
6857 }
6858 demand_empty_rest_of_line ();
6859 }
6860
6861 /* Handle the MRI UNTIL pseudo-op. */
6862
6863 static void
6864 s_mri_until (int qual)
6865 {
6866 char *s;
6867
6868 if (mri_control_stack == NULL
6869 || mri_control_stack->type != mri_repeat)
6870 {
6871 as_bad (_("until without repeat"));
6872 ignore_rest_of_line ();
6873 return;
6874 }
6875
6876 colon (mri_control_stack->next);
6877
6878 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6879 ;
6880
6881 parse_mri_control_expression (s, qual, (const char *) NULL,
6882 mri_control_stack->top, '\0');
6883
6884 colon (mri_control_stack->bottom);
6885
6886 input_line_pointer = s;
6887
6888 pop_mri_control ();
6889
6890 if (flag_mri)
6891 {
6892 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6893 ++input_line_pointer;
6894 }
6895
6896 demand_empty_rest_of_line ();
6897 }
6898
6899 /* Handle the MRI WHILE pseudo-op. */
6900
6901 static void
6902 s_mri_while (int qual)
6903 {
6904 char *s;
6905
6906 struct mri_control_info *n;
6907
6908 s = input_line_pointer;
6909 /* We only accept '*' as introduction of comments if preceded by white space
6910 or at first column of a line (I think this can't actually happen here?)
6911 This is important when assembling:
6912 while d0 <ne> 12(a0,d0*2) do
6913 while d0 <ne> #CONST*20 do. */
6914 while (! (is_end_of_line[(unsigned char) *s]
6915 || (flag_mri
6916 && *s == '*'
6917 && (s == input_line_pointer
6918 || *(s-1) == ' '
6919 || *(s-1) == '\t'))))
6920 s++;
6921 --s;
6922 while (*s == ' ' || *s == '\t')
6923 --s;
6924 if (s - input_line_pointer > 1
6925 && s[-1] == '.')
6926 s -= 2;
6927 if (s - input_line_pointer < 2
6928 || strncasecmp (s - 1, "DO", 2) != 0)
6929 {
6930 as_bad (_("missing do"));
6931 ignore_rest_of_line ();
6932 return;
6933 }
6934
6935 n = push_mri_control (mri_while);
6936
6937 colon (n->next);
6938
6939 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6940 s[1] == '.' ? s[2] : '\0');
6941
6942 input_line_pointer = s + 1;
6943 if (*input_line_pointer == '.')
6944 input_line_pointer += 2;
6945
6946 if (flag_mri)
6947 {
6948 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6949 ++input_line_pointer;
6950 }
6951
6952 demand_empty_rest_of_line ();
6953 }
6954
6955 /* Handle the MRI ENDW pseudo-op. */
6956
6957 static void
6958 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
6959 {
6960 char *buf;
6961
6962 if (mri_control_stack == NULL
6963 || mri_control_stack->type != mri_while)
6964 {
6965 as_bad (_("endw without while"));
6966 ignore_rest_of_line ();
6967 return;
6968 }
6969
6970 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6971 sprintf (buf, "bra %s", mri_control_stack->next);
6972 mri_assemble (buf);
6973 free (buf);
6974
6975 colon (mri_control_stack->bottom);
6976
6977 pop_mri_control ();
6978
6979 if (flag_mri)
6980 {
6981 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6982 ++input_line_pointer;
6983 }
6984
6985 demand_empty_rest_of_line ();
6986 }
6987 \f
6988 /* Parse a .cpu directive. */
6989
6990 static void
6991 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6992 {
6993 char saved_char;
6994 char *name;
6995
6996 if (initialized)
6997 {
6998 as_bad (_("already assembled instructions"));
6999 ignore_rest_of_line ();
7000 return;
7001 }
7002
7003 name = input_line_pointer;
7004 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7005 input_line_pointer++;
7006 saved_char = *input_line_pointer;
7007 *input_line_pointer = 0;
7008
7009 m68k_set_cpu (name, 1, 0);
7010
7011 *input_line_pointer = saved_char;
7012 demand_empty_rest_of_line ();
7013 return;
7014 }
7015
7016 /* Parse a .arch directive. */
7017
7018 static void
7019 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7020 {
7021 char saved_char;
7022 char *name;
7023
7024 if (initialized)
7025 {
7026 as_bad (_("already assembled instructions"));
7027 ignore_rest_of_line ();
7028 return;
7029 }
7030
7031 name = input_line_pointer;
7032 while (*input_line_pointer && *input_line_pointer != ','
7033 && !ISSPACE (*input_line_pointer))
7034 input_line_pointer++;
7035 saved_char = *input_line_pointer;
7036 *input_line_pointer = 0;
7037
7038 if (m68k_set_arch (name, 1, 0))
7039 {
7040 /* Scan extensions. */
7041 do
7042 {
7043 *input_line_pointer++ = saved_char;
7044 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7045 break;
7046 name = input_line_pointer;
7047 while (*input_line_pointer && *input_line_pointer != ','
7048 && !ISSPACE (*input_line_pointer))
7049 input_line_pointer++;
7050 saved_char = *input_line_pointer;
7051 *input_line_pointer = 0;
7052 }
7053 while (m68k_set_extension (name, 1, 0));
7054 }
7055
7056 *input_line_pointer = saved_char;
7057 demand_empty_rest_of_line ();
7058 return;
7059 }
7060 \f
7061 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7062 if none is found, the caller is responsible for emitting an error
7063 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7064 cpu name, if it begins with a '6' (possibly skipping an intervening
7065 'c'. We also allow a 'c' in the same place. if NEGATED is
7066 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7067 the option is indeed negated. */
7068
7069 static const struct m68k_cpu *
7070 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7071 int allow_m, int *negated)
7072 {
7073 /* allow negated value? */
7074 if (negated)
7075 {
7076 *negated = 0;
7077
7078 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7079 {
7080 arg += 3;
7081 *negated = 1;
7082 }
7083 }
7084
7085 /* Remove 'm' or 'mc' prefix from 68k variants. */
7086 if (allow_m)
7087 {
7088 if (arg[0] == 'm')
7089 {
7090 if (arg[1] == '6')
7091 arg += 1;
7092 else if (arg[1] == 'c' && arg[2] == '6')
7093 arg += 2;
7094 }
7095 }
7096 else if (arg[0] == 'c' && arg[1] == '6')
7097 arg += 1;
7098
7099 for (; table->name; table++)
7100 if (!strcmp (arg, table->name))
7101 {
7102 if (table->alias < -1 || table->alias > 1)
7103 as_bad (_("`%s' is deprecated, use `%s'"),
7104 table->name, table[table->alias < 0 ? 1 : -1].name);
7105 return table;
7106 }
7107 return 0;
7108 }
7109
7110 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7111
7112 static int
7113 m68k_set_cpu (char const *name, int allow_m, int silent)
7114 {
7115 const struct m68k_cpu *cpu;
7116
7117 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7118
7119 if (!cpu)
7120 {
7121 if (!silent)
7122 as_bad (_("cpu `%s' unrecognized"), name);
7123 return 0;
7124 }
7125
7126 if (selected_cpu && selected_cpu != cpu)
7127 {
7128 as_bad (_("already selected `%s' processor"),
7129 selected_cpu->name);
7130 return 0;
7131 }
7132 selected_cpu = cpu;
7133 return 1;
7134 }
7135
7136 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7137
7138 static int
7139 m68k_set_arch (char const *name, int allow_m, int silent)
7140 {
7141 const struct m68k_cpu *arch;
7142
7143 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7144
7145 if (!arch)
7146 {
7147 if (!silent)
7148 as_bad (_("architecture `%s' unrecognized"), name);
7149 return 0;
7150 }
7151
7152 if (selected_arch && selected_arch != arch)
7153 {
7154 as_bad (_("already selected `%s' architecture"),
7155 selected_arch->name);
7156 return 0;
7157 }
7158
7159 selected_arch = arch;
7160 return 1;
7161 }
7162
7163 /* Set the architecture extension, issuing errors if it is
7164 unrecognized, or invalid */
7165
7166 static int
7167 m68k_set_extension (char const *name, int allow_m, int silent)
7168 {
7169 int negated;
7170 const struct m68k_cpu *ext;
7171
7172 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7173
7174 if (!ext)
7175 {
7176 if (!silent)
7177 as_bad (_("extension `%s' unrecognized"), name);
7178 return 0;
7179 }
7180
7181 if (negated)
7182 not_current_architecture |= ext->arch;
7183 else
7184 current_architecture |= ext->arch;
7185 return 1;
7186 }
7187
7188 /* md_parse_option
7189 Invocation line includes a switch not recognized by the base assembler.
7190 */
7191
7192 #ifdef OBJ_ELF
7193 const char *md_shortopts = "lSA:m:kQ:V";
7194 #else
7195 const char *md_shortopts = "lSA:m:k";
7196 #endif
7197
7198 struct option md_longopts[] = {
7199 #define OPTION_PIC (OPTION_MD_BASE)
7200 {"pic", no_argument, NULL, OPTION_PIC},
7201 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7202 {"register-prefix-optional", no_argument, NULL,
7203 OPTION_REGISTER_PREFIX_OPTIONAL},
7204 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7205 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7206 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7207 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7208 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7209 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7210 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7211 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7212 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7213 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7214 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7215 {"pcrel", no_argument, NULL, OPTION_PCREL},
7216 {NULL, no_argument, NULL, 0}
7217 };
7218 size_t md_longopts_size = sizeof (md_longopts);
7219
7220 int
7221 md_parse_option (int c, char *arg)
7222 {
7223 switch (c)
7224 {
7225 case 'l': /* -l means keep external to 2 bit offset
7226 rather than 16 bit one. */
7227 flag_short_refs = 1;
7228 break;
7229
7230 case 'S': /* -S means that jbsr's always turn into
7231 jsr's. */
7232 flag_long_jumps = 1;
7233 break;
7234
7235 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7236 branches into absolute jumps. */
7237 flag_keep_pcrel = 1;
7238 break;
7239
7240 case OPTION_PIC:
7241 case 'k':
7242 flag_want_pic = 1;
7243 break; /* -pic, Position Independent Code. */
7244
7245 case OPTION_REGISTER_PREFIX_OPTIONAL:
7246 flag_reg_prefix_optional = 1;
7247 reg_prefix_optional_seen = 1;
7248 break;
7249
7250 /* -V: SVR4 argument to print version ID. */
7251 case 'V':
7252 print_version_id ();
7253 break;
7254
7255 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7256 should be emitted or not. FIXME: Not implemented. */
7257 case 'Q':
7258 break;
7259
7260 case OPTION_BITWISE_OR:
7261 {
7262 char *n, *t;
7263 const char *s;
7264
7265 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7266 t = n;
7267 for (s = m68k_comment_chars; *s != '\0'; s++)
7268 if (*s != '|')
7269 *t++ = *s;
7270 *t = '\0';
7271 m68k_comment_chars = n;
7272 }
7273 break;
7274
7275 case OPTION_BASE_SIZE_DEFAULT_16:
7276 m68k_index_width_default = SIZE_WORD;
7277 break;
7278
7279 case OPTION_BASE_SIZE_DEFAULT_32:
7280 m68k_index_width_default = SIZE_LONG;
7281 break;
7282
7283 case OPTION_DISP_SIZE_DEFAULT_16:
7284 m68k_rel32 = 0;
7285 m68k_rel32_from_cmdline = 1;
7286 break;
7287
7288 case OPTION_DISP_SIZE_DEFAULT_32:
7289 m68k_rel32 = 1;
7290 m68k_rel32_from_cmdline = 1;
7291 break;
7292
7293 case 'A':
7294 #if WARN_DEPRECATED
7295 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7296 arg, arg));
7297 #endif
7298 /* Intentional fall-through. */
7299 case 'm':
7300 if (!strncmp (arg, "arch=", 5))
7301 m68k_set_arch (arg + 5, 1, 0);
7302 else if (!strncmp (arg, "cpu=", 4))
7303 m68k_set_cpu (arg + 4, 1, 0);
7304 else if (m68k_set_extension (arg, 0, 1))
7305 ;
7306 else if (m68k_set_arch (arg, 0, 1))
7307 ;
7308 else if (m68k_set_cpu (arg, 0, 1))
7309 ;
7310 else
7311 return 0;
7312 break;
7313
7314 default:
7315 return 0;
7316 }
7317
7318 return 1;
7319 }
7320
7321 /* Setup tables from the selected arch and/or cpu */
7322
7323 static void
7324 m68k_init_arch (void)
7325 {
7326 if (not_current_architecture & current_architecture)
7327 {
7328 as_bad (_("architecture features both enabled and disabled"));
7329 not_current_architecture &= ~current_architecture;
7330 }
7331 if (selected_arch)
7332 {
7333 current_architecture |= selected_arch->arch;
7334 control_regs = selected_arch->control_regs;
7335 }
7336 else
7337 current_architecture |= selected_cpu->arch;
7338
7339 current_architecture &= ~not_current_architecture;
7340
7341 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7342 {
7343 /* Determine which float is really meant. */
7344 if (current_architecture & (m68k_mask & ~m68881))
7345 current_architecture ^= cfloat;
7346 else
7347 current_architecture ^= m68881;
7348 }
7349
7350 if (selected_cpu)
7351 {
7352 control_regs = selected_cpu->control_regs;
7353 if (current_architecture & ~selected_cpu->arch)
7354 {
7355 as_bad (_("selected processor does not have all features of selected architecture"));
7356 current_architecture
7357 = selected_cpu->arch & ~not_current_architecture;
7358 }
7359 }
7360
7361 if ((current_architecture & m68k_mask)
7362 && (current_architecture & ~m68k_mask))
7363 {
7364 as_bad (_ ("m68k and cf features both selected"));
7365 if (current_architecture & m68k_mask)
7366 current_architecture &= m68k_mask;
7367 else
7368 current_architecture &= ~m68k_mask;
7369 }
7370
7371 /* Permit m68881 specification with all cpus; those that can't work
7372 with a coprocessor could be doing emulation. */
7373 if (current_architecture & m68851)
7374 {
7375 if (current_architecture & m68040)
7376 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7377 }
7378 /* What other incompatibilities could we check for? */
7379
7380 if (cpu_of_arch (current_architecture) < m68020
7381 || arch_coldfire_p (current_architecture))
7382 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7383
7384 initialized = 1;
7385 }
7386
7387 void
7388 md_show_usage (FILE *stream)
7389 {
7390 const char *default_cpu = TARGET_CPU;
7391 int i;
7392 unsigned int default_arch;
7393
7394 /* Get the canonical name for the default target CPU. */
7395 if (*default_cpu == 'm')
7396 default_cpu++;
7397 for (i = 0; m68k_cpus[i].name; i++)
7398 {
7399 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7400 {
7401 default_arch = m68k_cpus[i].arch;
7402 while (m68k_cpus[i].alias > 0)
7403 i--;
7404 while (m68k_cpus[i].alias < 0)
7405 i++;
7406 default_cpu = m68k_cpus[i].name;
7407 }
7408 }
7409
7410 fprintf (stream, _("\
7411 -march=<arch> set architecture\n\
7412 -mcpu=<cpu> set cpu [default %s]\n\
7413 "), default_cpu);
7414 for (i = 0; m68k_extensions[i].name; i++)
7415 fprintf (stream, _("\
7416 -m[no-]%-16s enable/disable%s architecture extension\n\
7417 "), m68k_extensions[i].name,
7418 m68k_extensions[i].alias > 0 ? " ColdFire"
7419 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7420
7421 fprintf (stream, _("\
7422 -l use 1 word for refs to undefined symbols [default 2]\n\
7423 -pic, -k generate position independent code\n\
7424 -S turn jbsr into jsr\n\
7425 --pcrel never turn PC-relative branches into absolute jumps\n\
7426 --register-prefix-optional\n\
7427 recognize register names without prefix character\n\
7428 --bitwise-or do not treat `|' as a comment character\n\
7429 --base-size-default-16 base reg without size is 16 bits\n\
7430 --base-size-default-32 base reg without size is 32 bits (default)\n\
7431 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7432 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7433 "));
7434
7435 fprintf (stream, _("Architecture variants are: "));
7436 for (i = 0; m68k_archs[i].name; i++)
7437 {
7438 if (i)
7439 fprintf (stream, " | ");
7440 fprintf (stream, m68k_archs[i].name);
7441 }
7442 fprintf (stream, "\n");
7443
7444 fprintf (stream, _("Processor variants are: "));
7445 for (i = 0; m68k_cpus[i].name; i++)
7446 {
7447 if (i)
7448 fprintf (stream, " | ");
7449 fprintf (stream, m68k_cpus[i].name);
7450 }
7451 fprintf (stream, _("\n"));
7452 }
7453 \f
7454 #ifdef TEST2
7455
7456 /* TEST2: Test md_assemble() */
7457 /* Warning, this routine probably doesn't work anymore. */
7458 int
7459 main (void)
7460 {
7461 struct m68k_it the_ins;
7462 char buf[120];
7463 char *cp;
7464 int n;
7465
7466 m68k_ip_begin ();
7467 for (;;)
7468 {
7469 if (!gets (buf) || !*buf)
7470 break;
7471 if (buf[0] == '|' || buf[1] == '.')
7472 continue;
7473 for (cp = buf; *cp; cp++)
7474 if (*cp == '\t')
7475 *cp = ' ';
7476 if (is_label (buf))
7477 continue;
7478 memset (&the_ins, '\0', sizeof (the_ins));
7479 m68k_ip (&the_ins, buf);
7480 if (the_ins.error)
7481 {
7482 printf (_("Error %s in %s\n"), the_ins.error, buf);
7483 }
7484 else
7485 {
7486 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7487 for (n = 0; n < the_ins.numo; n++)
7488 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7489 printf (" ");
7490 print_the_insn (&the_ins.opcode[0], stdout);
7491 (void) putchar ('\n');
7492 }
7493 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7494 {
7495 if (the_ins.operands[n].error)
7496 {
7497 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7498 continue;
7499 }
7500 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7501 the_ins.operands[n].reg);
7502 if (the_ins.operands[n].b_const)
7503 printf ("Constant: '%.*s', ",
7504 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7505 the_ins.operands[n].b_const);
7506 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7507 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7508 if (the_ins.operands[n].b_iadd)
7509 printf ("Iadd: '%.*s',",
7510 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7511 the_ins.operands[n].b_iadd);
7512 putchar ('\n');
7513 }
7514 }
7515 m68k_ip_end ();
7516 return 0;
7517 }
7518
7519 int
7520 is_label (char *str)
7521 {
7522 while (*str == ' ')
7523 str++;
7524 while (*str && *str != ' ')
7525 str++;
7526 if (str[-1] == ':' || str[1] == '=')
7527 return 1;
7528 return 0;
7529 }
7530
7531 #endif
7532
7533 /* Possible states for relaxation:
7534
7535 0 0 branch offset byte (bra, etc)
7536 0 1 word
7537 0 2 long
7538
7539 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7540 1 1 word
7541 1 2 long
7542
7543 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7544 2 1 word-long
7545 2 2 long-word
7546 2 3 long-long
7547
7548 */
7549
7550 /* We have no need to default values of symbols. */
7551
7552 symbolS *
7553 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7554 {
7555 return 0;
7556 }
7557
7558 /* Round up a section size to the appropriate boundary. */
7559 valueT
7560 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7561 {
7562 #ifdef OBJ_AOUT
7563 /* For a.out, force the section size to be aligned. If we don't do
7564 this, BFD will align it for us, but it will not write out the
7565 final bytes of the section. This may be a bug in BFD, but it is
7566 easier to fix it here since that is how the other a.out targets
7567 work. */
7568 int align;
7569
7570 align = bfd_get_section_alignment (stdoutput, segment);
7571 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7572 #endif
7573
7574 return size;
7575 }
7576
7577 /* Exactly what point is a PC-relative offset relative TO?
7578 On the 68k, it is relative to the address of the first extension
7579 word. The difference between the addresses of the offset and the
7580 first extension word is stored in fx_pcrel_adjust. */
7581 long
7582 md_pcrel_from (fixS *fixP)
7583 {
7584 int adjust;
7585
7586 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7587 sign extend the value here. */
7588 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7589 if (adjust == 64)
7590 adjust = -1;
7591 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7592 }
7593
7594 #ifdef OBJ_ELF
7595 void
7596 m68k_elf_final_processing (void)
7597 {
7598 unsigned flags = 0;
7599
7600 if (arch_coldfire_fpu (current_architecture))
7601 flags |= EF_M68K_CFV4E;
7602 /* Set file-specific flags if this is a cpu32 processor. */
7603 if (cpu_of_arch (current_architecture) & cpu32)
7604 flags |= EF_M68K_CPU32;
7605 else if (cpu_of_arch (current_architecture) & fido_a)
7606 flags |= EF_M68K_FIDO;
7607 else if ((cpu_of_arch (current_architecture) & m68000up)
7608 && !(cpu_of_arch (current_architecture) & m68020up))
7609 flags |= EF_M68K_M68000;
7610
7611 if (current_architecture & mcfisa_a)
7612 {
7613 static const unsigned isa_features[][2] =
7614 {
7615 {EF_M68K_CF_ISA_A_NODIV, mcfisa_a},
7616 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7617 {EF_M68K_CF_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7618 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7619 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7620 {0,0},
7621 };
7622 static const unsigned mac_features[][2] =
7623 {
7624 {EF_M68K_CF_MAC, mcfmac},
7625 {EF_M68K_CF_EMAC, mcfemac},
7626 {0,0},
7627 };
7628 unsigned ix;
7629 unsigned pattern;
7630
7631 pattern = (current_architecture
7632 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7633 for (ix = 0; isa_features[ix][1]; ix++)
7634 {
7635 if (pattern == isa_features[ix][1])
7636 {
7637 flags |= isa_features[ix][0];
7638 break;
7639 }
7640 }
7641 if (!isa_features[ix][1])
7642 {
7643 cf_bad:
7644 as_warn (_("Not a defined coldfire architecture"));
7645 }
7646 else
7647 {
7648 if (current_architecture & cfloat)
7649 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7650
7651 pattern = current_architecture & (mcfmac|mcfemac);
7652 if (pattern)
7653 {
7654 for (ix = 0; mac_features[ix][1]; ix++)
7655 {
7656 if (pattern == mac_features[ix][1])
7657 {
7658 flags |= mac_features[ix][0];
7659 break;
7660 }
7661 }
7662 if (!mac_features[ix][1])
7663 goto cf_bad;
7664 }
7665 }
7666 }
7667 elf_elfheader (stdoutput)->e_flags |= flags;
7668 }
7669 #endif
7670
7671 int
7672 tc_m68k_regname_to_dw2regnum (char *regname)
7673 {
7674 unsigned int regnum;
7675 static const char *const regnames[] =
7676 {
7677 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7678 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7679 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7680 "pc"
7681 };
7682
7683 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7684 if (strcmp (regname, regnames[regnum]) == 0)
7685 return regnum;
7686
7687 return -1;
7688 }
7689
7690 void
7691 tc_m68k_frame_initial_instructions (void)
7692 {
7693 static int sp_regno = -1;
7694
7695 if (sp_regno < 0)
7696 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7697
7698 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7699 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7700 }
GDB Binutils - Deliverables
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