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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
20
21 #include <ctype.h>
22 #include "as.h"
23 #include "obstack.h"
24 #include "subsegs.h"
25
26 #include "opcode/m68k.h"
27 #include "m68k-parse.h"
28
29 /* This array holds the chars that always start a comment. If the
30 pre-processor is disabled, these aren't very useful */
31 #if (defined (OBJ_ELF) && ! defined (TE_PSOS) && ! defined (TE_LINUX)) || defined (TE_DELTA)
32 const char comment_chars[] = "|#";
33 #else
34 const char comment_chars[] = "|";
35 #endif
36
37 /* This array holds the chars that only start a comment at the beginning of
38 a line. If the line seems to have the form '# 123 filename'
39 .line and .file directives will appear in the pre-processed output */
40 /* Note that input_file.c hand checks for '#' at the beginning of the
41 first line of the input file. This is because the compiler outputs
42 #NO_APP at the beginning of its output. */
43 /* Also note that comments like this one will always work. */
44 const char line_comment_chars[] = "#";
45
46 const char line_separator_chars[] = "";
47
48 /* Chars that can be used to separate mant from exp in floating point nums */
49 CONST char EXP_CHARS[] = "eE";
50
51 /* Chars that mean this number is a floating point constant, as
52 in "0f12.456" or "0d1.2345e12". */
53
54 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
55
56 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
57 changed in read.c . Ideally it shouldn't have to know about it at all,
58 but nothing is ideal around here. */
59
60 const int md_reloc_size = 8; /* Size of relocation record */
61
62 /* Are we trying to generate PIC code? If so, absolute references
63 ought to be made into linkage table references or pc-relative
64 references. Not implemented. For ELF there are other means
65 to denote pic relocations. */
66 int flag_want_pic;
67
68 static int flag_short_refs; /* -l option */
69 static int flag_long_jumps; /* -S option */
70
71 #ifdef REGISTER_PREFIX_OPTIONAL
72 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
73 #else
74 int flag_reg_prefix_optional;
75 #endif
76
77 /* Whether --register-prefix-optional was used on the command line. */
78 static int reg_prefix_optional_seen;
79
80 /* The floating point coprocessor to use by default. */
81 static enum m68k_register m68k_float_copnum = COP1;
82
83 /* If this is non-zero, then references to number(%pc) will be taken
84 to refer to number, rather than to %pc + number. */
85 static int m68k_abspcadd;
86
87 /* If this is non-zero, then the quick forms of the move, add, and sub
88 instructions are used when possible. */
89 static int m68k_quick = 1;
90
91 /* If this is non-zero, then if the size is not specified for a base
92 or outer displacement, the assembler assumes that the size should
93 be 32 bits. */
94 static int m68k_rel32 = 1;
95
96 /* Its an arbitrary name: This means I don't approve of it */
97 /* See flames below */
98 static struct obstack robyn;
99
100 #define TAB(x,y) (((x)<<2)+(y))
101 #define TABTYPE(xy) ((xy) >> 2)
102 #define BYTE 0
103 #define SHORT 1
104 #define LONG 2
105 #define SZ_UNDEF 3
106 #undef BRANCH
107 /* Case `g' except when BCC68000 is applicable. */
108 #define ABRANCH 1
109 /* Coprocessor branches. */
110 #define FBRANCH 2
111 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
112 supported on all cpus. Widens to 32-bit absolute. */
113 #define PCREL 3
114 /* For inserting an extra jmp instruction with long offset on 68000,
115 for expanding conditional branches. (Not bsr or bra.) Since the
116 68000 doesn't support 32-bit displacements for conditional
117 branches, we fake it by reversing the condition and branching
118 around a jmp with an absolute long operand. */
119 #define BCC68000 4
120 /* For the DBcc "instructions". If the displacement requires 32 bits,
121 the branch-around-a-jump game is played here too. */
122 #define DBCC 5
123 /* Not currently used? */
124 #define PCLEA 6
125 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
126 in 16 or 8 bits. */
127 #define PCINDEX 7
128
129 struct m68k_incant
130 {
131 const char *m_operands;
132 unsigned long m_opcode;
133 short m_opnum;
134 short m_codenum;
135 int m_arch;
136 struct m68k_incant *m_next;
137 };
138
139 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
140 #define gettwo(x) (((x)->m_opcode)&0xffff)
141
142 static const enum m68k_register m68000_control_regs[] = { 0 };
143 static const enum m68k_register m68010_control_regs[] = {
144 SFC, DFC, USP, VBR,
145 0
146 };
147 static const enum m68k_register m68020_control_regs[] = {
148 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
149 0
150 };
151 static const enum m68k_register m68040_control_regs[] = {
152 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
153 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
154 0
155 };
156 static const enum m68k_register m68060_control_regs[] = {
157 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
158 USP, VBR, URP, SRP, PCR,
159 0
160 };
161 #define cpu32_control_regs m68010_control_regs
162
163 static const enum m68k_register *control_regs;
164
165 /* internal form of a 68020 instruction */
166 struct m68k_it
167 {
168 const char *error;
169 const char *args; /* list of opcode info */
170 int numargs;
171
172 int numo; /* Number of shorts in opcode */
173 short opcode[11];
174
175 struct m68k_op operands[6];
176
177 int nexp; /* number of exprs in use */
178 struct m68k_exp exprs[4];
179
180 int nfrag; /* Number of frags we have to produce */
181 struct
182 {
183 int fragoff; /* Where in the current opcode the frag ends */
184 symbolS *fadd;
185 long foff;
186 int fragty;
187 }
188 fragb[4];
189
190 int nrel; /* Num of reloc strucs in use */
191 struct
192 {
193 int n;
194 expressionS exp;
195 char wid;
196 char pcrel;
197 /* In a pc relative address the difference between the address
198 of the offset and the address that the offset is relative
199 to. This depends on the addressing mode. Basically this
200 is the value to put in the offset field to address the
201 first byte of the offset, without regarding the special
202 significance of some values (in the branch instruction, for
203 example). */
204 int pcrel_fix;
205 #ifdef OBJ_ELF
206 /* Whether this expression needs special pic relocation, and if
207 so, which. */
208 enum pic_relocation pic_reloc;
209 #endif
210 }
211 reloc[5]; /* Five is enough??? */
212 };
213
214 #define cpu_of_arch(x) ((x) & m68000up)
215 #define float_of_arch(x) ((x) & mfloat)
216 #define mmu_of_arch(x) ((x) & mmmu)
217
218 static struct m68k_it the_ins; /* the instruction being assembled */
219
220 #define op(ex) ((ex)->exp.X_op)
221 #define adds(ex) ((ex)->exp.X_add_symbol)
222 #define subs(ex) ((ex)->exp.X_op_symbol)
223 #define offs(ex) ((ex)->exp.X_add_number)
224
225 /* Macros for adding things to the m68k_it struct */
226
227 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
228
229 /* Like addword, but goes BEFORE general operands */
230 static void
231 insop (w, opcode)
232 int w;
233 struct m68k_incant *opcode;
234 {
235 int z;
236 for(z=the_ins.numo;z>opcode->m_codenum;--z)
237 the_ins.opcode[z]=the_ins.opcode[z-1];
238 for(z=0;z<the_ins.nrel;z++)
239 the_ins.reloc[z].n+=2;
240 for (z = 0; z < the_ins.nfrag; z++)
241 the_ins.fragb[z].fragoff++;
242 the_ins.opcode[opcode->m_codenum]=w;
243 the_ins.numo++;
244 }
245
246 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
247 Blecch. */
248 static void
249 add_fix (width, exp, pc_rel, pc_fix)
250 char width;
251 struct m68k_exp *exp;
252 int pc_rel;
253 int pc_fix;
254 {
255 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
256 ? (the_ins.numo*2-1)
257 : (((width)=='b')
258 ? (the_ins.numo*2+1)
259 : (the_ins.numo*2)));
260 the_ins.reloc[the_ins.nrel].exp = exp->exp;
261 the_ins.reloc[the_ins.nrel].wid = width;
262 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
263 #ifdef OBJ_ELF
264 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
265 #endif
266 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
267 }
268
269 /* Cause an extra frag to be generated here, inserting up to 10 bytes
270 (that value is chosen in the frag_var call in md_assemble). TYPE
271 is the subtype of the frag to be generated; its primary type is
272 rs_machine_dependent.
273
274 The TYPE parameter is also used by md_convert_frag_1 and
275 md_estimate_size_before_relax. The appropriate type of fixup will
276 be emitted by md_convert_frag_1.
277
278 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
279 static void
280 add_frag(add,off,type)
281 symbolS *add;
282 long off;
283 int type;
284 {
285 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
286 the_ins.fragb[the_ins.nfrag].fadd=add;
287 the_ins.fragb[the_ins.nfrag].foff=off;
288 the_ins.fragb[the_ins.nfrag++].fragty=type;
289 }
290
291 #define isvar(ex) \
292 (op (ex) != O_constant && op (ex) != O_big)
293
294 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
295 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
296 static int reverse_16_bits PARAMS ((int in));
297 static int reverse_8_bits PARAMS ((int in));
298 static void install_gen_operand PARAMS ((int mode, int val));
299 static void install_operand PARAMS ((int mode, int val));
300 static void s_bss PARAMS ((int));
301 static void s_data1 PARAMS ((int));
302 static void s_data2 PARAMS ((int));
303 static void s_even PARAMS ((int));
304 static void s_proc PARAMS ((int));
305 static void mri_chip PARAMS ((void));
306 static void s_chip PARAMS ((int));
307 static void s_fopt PARAMS ((int));
308 static void s_opt PARAMS ((int));
309 static void s_reg PARAMS ((int));
310 static void s_restore PARAMS ((int));
311 static void s_save PARAMS ((int));
312 static void s_mri_if PARAMS ((int));
313 static void s_mri_else PARAMS ((int));
314 static void s_mri_endi PARAMS ((int));
315 static void s_mri_break PARAMS ((int));
316 static void s_mri_next PARAMS ((int));
317 static void s_mri_for PARAMS ((int));
318 static void s_mri_endf PARAMS ((int));
319 static void s_mri_repeat PARAMS ((int));
320 static void s_mri_until PARAMS ((int));
321 static void s_mri_while PARAMS ((int));
322 static void s_mri_endw PARAMS ((int));
323
324 static int current_architecture;
325
326 struct m68k_cpu {
327 unsigned long arch;
328 const char *name;
329 int alias;
330 };
331
332 static const struct m68k_cpu archs[] = {
333 { m68000, "68000", 0 },
334 { m68010, "68010", 0 },
335 { m68020, "68020", 0 },
336 { m68030, "68030", 0 },
337 { m68040, "68040", 0 },
338 { m68060, "68060", 0 },
339 { cpu32, "cpu32", 0 },
340 { m68881, "68881", 0 },
341 { m68851, "68851", 0 },
342 /* Aliases (effectively, so far as gas is concerned) for the above
343 cpus. */
344 { m68020, "68k", 1 },
345 { m68000, "68302", 1 },
346 { m68000, "68008", 1 },
347 { m68000, "68ec000", 1 },
348 { m68000, "68hc000", 1 },
349 { m68000, "68hc001", 1 },
350 { m68020, "68ec020", 1 },
351 { m68030, "68ec030", 1 },
352 { m68040, "68ec040", 1 },
353 { cpu32, "68330", 1 },
354 { cpu32, "68331", 1 },
355 { cpu32, "68332", 1 },
356 { cpu32, "68333", 1 },
357 { cpu32, "68340", 1 },
358 { cpu32, "68360", 1 },
359 { m68881, "68882", 1 },
360 };
361
362 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
363
364 /* BCC68000 is for patching in an extra jmp instruction for long offsets
365 on the 68000. The 68000 doesn't support long branches with branchs */
366
367 /* This table desribes how you change sizes for the various types of variable
368 size expressions. This version only supports two kinds. */
369
370 /* Note that calls to frag_var need to specify the maximum expansion
371 needed; this is currently 10 bytes for DBCC. */
372
373 /* The fields are:
374 How far Forward this mode will reach:
375 How far Backward this mode will reach:
376 How many bytes this mode will add to the size of the frag
377 Which mode to go to if the offset won't fit in this one
378 */
379 relax_typeS md_relax_table[] =
380 {
381 {1, 1, 0, 0}, /* First entries aren't used */
382 {1, 1, 0, 0}, /* For no good reason except */
383 {1, 1, 0, 0}, /* that the VAX doesn't either */
384 {1, 1, 0, 0},
385
386 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
387 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
388 {0, 0, 4, 0},
389 {1, 1, 0, 0},
390
391 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
392 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
393 {0, 0, 4, 0},
394 {1, 1, 0, 0},
395
396 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
397 {(32767), (-32768), 2, TAB (PCREL, LONG)},
398 {0, 0, 4, 0},
399 {1, 1, 0, 0},
400
401 {(127), (-128), 0, TAB (BCC68000, SHORT)},
402 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
403 {0, 0, 6, 0}, /* jmp long space */
404 {1, 1, 0, 0},
405
406 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
407 {(32767), (-32768), 2, TAB (DBCC, LONG)},
408 {0, 0, 10, 0}, /* bra/jmp long space */
409 {1, 1, 0, 0},
410
411 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
412 {32767, -32768, 2, TAB (PCLEA, LONG)},
413 {0, 0, 6, 0},
414 {1, 1, 0, 0},
415
416 /* For, e.g., jmp pcrel indexed. */
417 {125, -130, 0, TAB (PCINDEX, SHORT)},
418 {32765, -32770, 2, TAB (PCINDEX, LONG)},
419 {0, 0, 4, 0},
420 {1, 1, 0, 0},
421 };
422
423 /* These are the machine dependent pseudo-ops. These are included so
424 the assembler can work on the output from the SUN C compiler, which
425 generates these.
426 */
427
428 /* This table describes all the machine specific pseudo-ops the assembler
429 has to support. The fields are:
430 pseudo-op name without dot
431 function to call to execute this pseudo-op
432 Integer arg to pass to the function
433 */
434 const pseudo_typeS md_pseudo_table[] =
435 {
436 {"data1", s_data1, 0},
437 {"data2", s_data2, 0},
438 {"bss", s_bss, 0},
439 {"even", s_even, 0},
440 {"skip", s_space, 0},
441 {"proc", s_proc, 0},
442 #if defined (TE_SUN3) || defined (OBJ_ELF)
443 {"align", s_align_bytes, 0},
444 #endif
445 #ifdef OBJ_ELF
446 {"swbeg", s_ignore, 0},
447 #endif
448 {"extend", float_cons, 'x'},
449 {"ldouble", float_cons, 'x'},
450
451 /* The following pseudo-ops are supported for MRI compatibility. */
452 {"chip", s_chip, 0},
453 {"comline", s_space, 1},
454 {"fopt", s_fopt, 0},
455 {"mask2", s_ignore, 0},
456 {"opt", s_opt, 0},
457 {"reg", s_reg, 0},
458 {"restore", s_restore, 0},
459 {"save", s_save, 0},
460
461 {"if", s_mri_if, 0},
462 {"if.b", s_mri_if, 'b'},
463 {"if.w", s_mri_if, 'w'},
464 {"if.l", s_mri_if, 'l'},
465 {"else", s_mri_else, 0},
466 {"else.s", s_mri_else, 's'},
467 {"else.l", s_mri_else, 'l'},
468 {"endi", s_mri_endi, 0},
469 {"break", s_mri_break, 0},
470 {"break.s", s_mri_break, 's'},
471 {"break.l", s_mri_break, 'l'},
472 {"next", s_mri_next, 0},
473 {"next.s", s_mri_next, 's'},
474 {"next.l", s_mri_next, 'l'},
475 {"for", s_mri_for, 0},
476 {"for.b", s_mri_for, 'b'},
477 {"for.w", s_mri_for, 'w'},
478 {"for.l", s_mri_for, 'l'},
479 {"endf", s_mri_endf, 0},
480 {"repeat", s_mri_repeat, 0},
481 {"until", s_mri_until, 0},
482 {"until.b", s_mri_until, 'b'},
483 {"until.w", s_mri_until, 'w'},
484 {"until.l", s_mri_until, 'l'},
485 {"while", s_mri_while, 0},
486 {"while.b", s_mri_while, 'b'},
487 {"while.w", s_mri_while, 'w'},
488 {"while.l", s_mri_while, 'l'},
489 {"endw", s_mri_endw, 0},
490
491 {0, 0, 0}
492 };
493
494
495 /* The mote pseudo ops are put into the opcode table, since they
496 don't start with a . they look like opcodes to gas.
497 */
498 extern void obj_coff_section ();
499
500 CONST pseudo_typeS mote_pseudo_table[] =
501 {
502
503 {"dcl", cons, 4},
504 {"dc", cons, 2},
505 {"dcw", cons, 2},
506 {"dcb", cons, 1},
507
508 {"dsl", s_space, 4},
509 {"ds", s_space, 2},
510 {"dsw", s_space, 2},
511 {"dsb", s_space, 1},
512
513 {"xdef", s_globl, 0},
514 #ifdef OBJ_ELF
515 {"align", s_align_bytes, 0},
516 #else
517 {"align", s_align_ptwo, 0},
518 #endif
519 #ifdef M68KCOFF
520 {"sect", obj_coff_section, 0},
521 {"section", obj_coff_section, 0},
522 #endif
523 {0, 0, 0}
524 };
525
526 #define issbyte(x) ((x)>=-128 && (x)<=127)
527 #define isubyte(x) ((x)>=0 && (x)<=255)
528 #define issword(x) ((x)>=-32768 && (x)<=32767)
529 #define isuword(x) ((x)>=0 && (x)<=65535)
530
531 #define isbyte(x) ((x)>= -255 && (x)<=255)
532 #define isword(x) ((x)>=-65536 && (x)<=65535)
533 #define islong(x) (1)
534
535 extern char *input_line_pointer;
536
537 static char mklower_table[256];
538 #define mklower(c) (mklower_table[(unsigned char)(c)])
539 static char notend_table[256];
540 static char alt_notend_table[256];
541 #define notend(s) \
542 (! (notend_table[(unsigned char) *s] \
543 || (*s == ':' \
544 && alt_notend_table[(unsigned char) s[1]])))
545
546 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
547
548 #ifdef NO_PCREL_RELOCS
549
550 int
551 make_pcrel_absolute(fixP, add_number)
552 fixS *fixP;
553 long *add_number;
554 {
555 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
556
557 /* rewrite the PC relative instructions to absolute address ones.
558 * these are rumoured to be faster, and the apollo linker refuses
559 * to deal with the PC relative relocations.
560 */
561 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
562 {
563 opcode[0] = 0x4e;
564 opcode[1] = 0xf9;
565 }
566 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
567 {
568 opcode[0] = 0x4e;
569 opcode[1] = 0xb9;
570 }
571 else
572 as_fatal ("Unknown PC relative instruction");
573 *add_number -= 4;
574 return 0;
575 }
576
577 #endif /* NO_PCREL_RELOCS */
578
579 short
580 tc_coff_fix2rtype (fixP)
581 fixS *fixP;
582 {
583 if (fixP->fx_tcbit && fixP->fx_size == 4)
584 return R_RELLONG_NEG;
585 #ifdef NO_PCREL_RELOCS
586 know (fixP->fx_pcrel == 0);
587 return (fixP->fx_size == 1 ? R_RELBYTE
588 : fixP->fx_size == 2 ? R_DIR16
589 : R_DIR32);
590 #else
591 return (fixP->fx_pcrel ?
592 (fixP->fx_size == 1 ? R_PCRBYTE :
593 fixP->fx_size == 2 ? R_PCRWORD :
594 R_PCRLONG) :
595 (fixP->fx_size == 1 ? R_RELBYTE :
596 fixP->fx_size == 2 ? R_RELWORD :
597 R_RELLONG));
598 #endif
599 }
600
601 #endif
602
603 #ifdef OBJ_ELF
604
605 /* Compute the relocation code for a fixup of SIZE bytes, using pc
606 relative relocation if PCREL is non-zero. PIC says whether a special
607 pic relocation was requested. */
608
609 static bfd_reloc_code_real_type get_reloc_code
610 PARAMS ((int, int, enum pic_relocation));
611
612 static bfd_reloc_code_real_type
613 get_reloc_code (size, pcrel, pic)
614 int size;
615 int pcrel;
616 enum pic_relocation pic;
617 {
618 switch (pic)
619 {
620 case pic_got_pcrel:
621 switch (size)
622 {
623 case 1:
624 return BFD_RELOC_8_GOT_PCREL;
625 case 2:
626 return BFD_RELOC_16_GOT_PCREL;
627 case 4:
628 return BFD_RELOC_32_GOT_PCREL;
629 }
630 break;
631
632 case pic_got_off:
633 switch (size)
634 {
635 case 1:
636 return BFD_RELOC_8_GOTOFF;
637 case 2:
638 return BFD_RELOC_16_GOTOFF;
639 case 4:
640 return BFD_RELOC_32_GOTOFF;
641 }
642 break;
643
644 case pic_plt_pcrel:
645 switch (size)
646 {
647 case 1:
648 return BFD_RELOC_8_PLT_PCREL;
649 case 2:
650 return BFD_RELOC_16_PLT_PCREL;
651 case 4:
652 return BFD_RELOC_32_PLT_PCREL;
653 }
654 break;
655
656 case pic_plt_off:
657 switch (size)
658 {
659 case 1:
660 return BFD_RELOC_8_PLTOFF;
661 case 2:
662 return BFD_RELOC_16_PLTOFF;
663 case 4:
664 return BFD_RELOC_32_PLTOFF;
665 }
666 break;
667
668 case pic_none:
669 if (pcrel)
670 {
671 switch (size)
672 {
673 case 1:
674 return BFD_RELOC_8_PCREL;
675 case 2:
676 return BFD_RELOC_16_PCREL;
677 case 4:
678 return BFD_RELOC_32_PCREL;
679 }
680 }
681 else
682 {
683 switch (size)
684 {
685 case 1:
686 return BFD_RELOC_8;
687 case 2:
688 return BFD_RELOC_16;
689 case 4:
690 return BFD_RELOC_32;
691 }
692 }
693 }
694
695 as_bad ("Can not do %d byte %s%srelocation", size,
696 pcrel ? "pc-relative " : "",
697 pic == pic_none ? "" : "pic ");
698 return BFD_RELOC_NONE;
699 }
700
701 /* Here we decide which fixups can be adjusted to make them relative
702 to the beginning of the section instead of the symbol. Basically
703 we need to make sure that the dynamic relocations are done
704 correctly, so in some cases we force the original symbol to be
705 used. */
706 int
707 tc_m68k_fix_adjustable (fixP)
708 fixS *fixP;
709 {
710 /* Prevent all adjustments to global symbols. */
711 if (S_IS_EXTERNAL (fixP->fx_addsy))
712 return 0;
713
714 /* adjust_reloc_syms doesn't know about the GOT */
715 switch (fixP->fx_r_type)
716 {
717 case BFD_RELOC_8_GOT_PCREL:
718 case BFD_RELOC_16_GOT_PCREL:
719 case BFD_RELOC_32_GOT_PCREL:
720 case BFD_RELOC_8_GOTOFF:
721 case BFD_RELOC_16_GOTOFF:
722 case BFD_RELOC_32_GOTOFF:
723 case BFD_RELOC_8_PLT_PCREL:
724 case BFD_RELOC_16_PLT_PCREL:
725 case BFD_RELOC_32_PLT_PCREL:
726 case BFD_RELOC_8_PLTOFF:
727 case BFD_RELOC_16_PLTOFF:
728 case BFD_RELOC_32_PLTOFF:
729 return 0;
730
731 default:
732 return 1;
733 }
734 }
735
736 #else /* !OBJ_ELF */
737
738 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
739
740 #endif /* OBJ_ELF */
741
742 #ifdef BFD_ASSEMBLER
743
744 arelent *
745 tc_gen_reloc (section, fixp)
746 asection *section;
747 fixS *fixp;
748 {
749 arelent *reloc;
750 bfd_reloc_code_real_type code;
751
752 if (fixp->fx_tcbit)
753 abort ();
754
755 if (fixp->fx_r_type != BFD_RELOC_NONE)
756 code = fixp->fx_r_type;
757 else
758 {
759 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
760 switch (F (fixp->fx_size, fixp->fx_pcrel))
761 {
762 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
763 MAP (1, 0, BFD_RELOC_8);
764 MAP (2, 0, BFD_RELOC_16);
765 MAP (4, 0, BFD_RELOC_32);
766 MAP (1, 1, BFD_RELOC_8_PCREL);
767 MAP (2, 1, BFD_RELOC_16_PCREL);
768 MAP (4, 1, BFD_RELOC_32_PCREL);
769 default:
770 abort ();
771 }
772 }
773 #undef F
774 #undef MAP
775
776 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
777 assert (reloc != 0);
778 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
779 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
780 #ifndef OBJ_ELF
781 if (fixp->fx_pcrel)
782 reloc->addend = fixp->fx_addnumber;
783 else
784 reloc->addend = 0;
785 #else
786 if (!fixp->fx_pcrel)
787 reloc->addend = fixp->fx_addnumber;
788 else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
789 reloc->addend = (section->vma
790 + (fixp->fx_pcrel_adjust == 64
791 ? -1 : fixp->fx_pcrel_adjust)
792 + fixp->fx_addnumber
793 + md_pcrel_from (fixp));
794 else
795 reloc->addend = (fixp->fx_offset
796 + (fixp->fx_pcrel_adjust == 64
797 ? -1 : fixp->fx_pcrel_adjust));
798 #endif
799
800 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
801 assert (reloc->howto != 0);
802
803 return reloc;
804 }
805
806 #endif /* BFD_ASSEMBLER */
807
808 /* Handle of the OPCODE hash table. NULL means any use before
809 m68k_ip_begin() will crash. */
810 static struct hash_control *op_hash;
811 \f
812 /* Assemble an m68k instruction. */
813
814 void
815 m68k_ip (instring)
816 char *instring;
817 {
818 register char *p;
819 register struct m68k_op *opP;
820 register struct m68k_incant *opcode;
821 register const char *s;
822 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
823 char *pdot, *pdotmove;
824 enum m68k_size siz1, siz2;
825 char c;
826 int losing;
827 int opsfound;
828 char *crack_operand ();
829 LITTLENUM_TYPE words[6];
830 LITTLENUM_TYPE *wordp;
831 unsigned long ok_arch = 0;
832
833 if (*instring == ' ')
834 instring++; /* skip leading whitespace */
835
836 /* Scan up to end of operation-code, which MUST end in end-of-string
837 or exactly 1 space. */
838 pdot = 0;
839 for (p = instring; *p != '\0'; p++)
840 {
841 if (*p == ' ')
842 break;
843 if (*p == '.')
844 pdot = p;
845 }
846
847 if (p == instring)
848 {
849 the_ins.error = "No operator";
850 return;
851 }
852
853 /* p now points to the end of the opcode name, probably whitespace.
854 Make sure the name is null terminated by clobbering the
855 whitespace, look it up in the hash table, then fix it back.
856 Remove a dot, first, since the opcode tables have none. */
857 if (pdot != NULL)
858 {
859 for (pdotmove = pdot; pdotmove < p; pdotmove++)
860 *pdotmove = pdotmove[1];
861 p--;
862 }
863
864 c = *p;
865 *p = '\0';
866 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
867 *p = c;
868
869 if (pdot != NULL)
870 {
871 for (pdotmove = p; pdotmove > pdot; pdotmove--)
872 *pdotmove = pdotmove[-1];
873 *pdot = '.';
874 ++p;
875 }
876
877 if (opcode == NULL)
878 {
879 the_ins.error = "Unknown operator";
880 return;
881 }
882
883 /* found a legitimate opcode, start matching operands */
884 while (*p == ' ')
885 ++p;
886
887 if (opcode->m_operands == 0)
888 {
889 char *old = input_line_pointer;
890 *old = '\n';
891 input_line_pointer = p;
892 /* Ahh - it's a motorola style psuedo op */
893 mote_pseudo_table[opcode->m_opnum].poc_handler
894 (mote_pseudo_table[opcode->m_opnum].poc_val);
895 input_line_pointer = old;
896 *old = 0;
897
898 return;
899 }
900
901 if (flag_mri && opcode->m_opnum == 0)
902 {
903 /* In MRI mode, random garbage is allowed after an instruction
904 which accepts no operands. */
905 the_ins.args = opcode->m_operands;
906 the_ins.numargs = opcode->m_opnum;
907 the_ins.numo = opcode->m_codenum;
908 the_ins.opcode[0] = getone (opcode);
909 the_ins.opcode[1] = gettwo (opcode);
910 return;
911 }
912
913 for (opP = &the_ins.operands[0]; *p; opP++)
914 {
915 p = crack_operand (p, opP);
916
917 if (opP->error)
918 {
919 the_ins.error = opP->error;
920 return;
921 }
922 }
923
924 opsfound = opP - &the_ins.operands[0];
925
926 /* This ugly hack is to support the floating pt opcodes in their
927 standard form. Essentially, we fake a first enty of type COP#1 */
928 if (opcode->m_operands[0] == 'I')
929 {
930 int n;
931
932 for (n = opsfound; n > 0; --n)
933 the_ins.operands[n] = the_ins.operands[n - 1];
934
935 memset ((char *) (&the_ins.operands[0]), '\0',
936 sizeof (the_ins.operands[0]));
937 the_ins.operands[0].mode = CONTROL;
938 the_ins.operands[0].reg = m68k_float_copnum;
939 opsfound++;
940 }
941
942 /* We've got the operands. Find an opcode that'll accept them */
943 for (losing = 0;;)
944 {
945 /* If we didn't get the right number of ops, or we have no
946 common model with this pattern then reject this pattern. */
947
948 if (opsfound != opcode->m_opnum
949 || ((opcode->m_arch & current_architecture) == 0))
950 {
951 ++losing;
952 ok_arch |= opcode->m_arch;
953 }
954 else
955 {
956 for (s = opcode->m_operands, opP = &the_ins.operands[0];
957 *s && !losing;
958 s += 2, opP++)
959 {
960 /* Warning: this switch is huge! */
961 /* I've tried to organize the cases into this order:
962 non-alpha first, then alpha by letter. Lower-case
963 goes directly before uppercase counterpart. */
964 /* Code with multiple case ...: gets sorted by the lowest
965 case ... it belongs to. I hope this makes sense. */
966 switch (*s)
967 {
968 case '!':
969 switch (opP->mode)
970 {
971 case IMMED:
972 case DREG:
973 case AREG:
974 case FPREG:
975 case CONTROL:
976 case AINC:
977 case ADEC:
978 case REGLST:
979 losing++;
980 break;
981 default:
982 break;
983 }
984 break;
985
986 case '`':
987 switch (opP->mode)
988 {
989 case IMMED:
990 case DREG:
991 case AREG:
992 case FPREG:
993 case CONTROL:
994 case AINC:
995 case REGLST:
996 case AINDR:
997 losing++;
998 break;
999 default:
1000 break;
1001 }
1002 break;
1003
1004 case '#':
1005 if (opP->mode != IMMED)
1006 losing++;
1007 else if (s[1] == 'b'
1008 && ! isvar (&opP->disp)
1009 && (opP->disp.exp.X_op != O_constant
1010 || ! isbyte (opP->disp.exp.X_add_number)))
1011 losing++;
1012 else if (s[1] == 'w'
1013 && ! isvar (&opP->disp)
1014 && (opP->disp.exp.X_op != O_constant
1015 || ! isword (opP->disp.exp.X_add_number)))
1016 losing++;
1017 else if (s[1] == 'W'
1018 && ! isvar (&opP->disp)
1019 && (opP->disp.exp.X_op != O_constant
1020 || ! issword (opP->disp.exp.X_add_number)))
1021 losing++;
1022 break;
1023
1024 case '^':
1025 case 'T':
1026 if (opP->mode != IMMED)
1027 losing++;
1028 break;
1029
1030 case '$':
1031 if (opP->mode == AREG
1032 || opP->mode == CONTROL
1033 || opP->mode == FPREG
1034 || opP->mode == IMMED
1035 || opP->mode == REGLST
1036 || (opP->mode != ABSL
1037 && (opP->reg == PC
1038 || opP->reg == ZPC)))
1039 losing++;
1040 break;
1041
1042 case '%':
1043 if (opP->mode == CONTROL
1044 || opP->mode == FPREG
1045 || opP->mode == REGLST
1046 || opP->mode == IMMED
1047 || (opP->mode != ABSL
1048 && (opP->reg == PC
1049 || opP->reg == ZPC)))
1050 losing++;
1051 break;
1052
1053 case '&':
1054 switch (opP->mode)
1055 {
1056 case DREG:
1057 case AREG:
1058 case FPREG:
1059 case CONTROL:
1060 case IMMED:
1061 case AINC:
1062 case ADEC:
1063 case REGLST:
1064 losing++;
1065 break;
1066 case ABSL:
1067 break;
1068 default:
1069 if (opP->reg == PC
1070 || opP->reg == ZPC)
1071 losing++;
1072 break;
1073 }
1074 break;
1075
1076 case '*':
1077 if (opP->mode == CONTROL
1078 || opP->mode == FPREG
1079 || opP->mode == REGLST)
1080 losing++;
1081 break;
1082
1083 case '+':
1084 if (opP->mode != AINC)
1085 losing++;
1086 break;
1087
1088 case '-':
1089 if (opP->mode != ADEC)
1090 losing++;
1091 break;
1092
1093 case '/':
1094 switch (opP->mode)
1095 {
1096 case AREG:
1097 case CONTROL:
1098 case FPREG:
1099 case AINC:
1100 case ADEC:
1101 case IMMED:
1102 case REGLST:
1103 losing++;
1104 break;
1105 default:
1106 break;
1107 }
1108 break;
1109
1110 case ';':
1111 switch (opP->mode)
1112 {
1113 case AREG:
1114 case CONTROL:
1115 case FPREG:
1116 case REGLST:
1117 losing++;
1118 break;
1119 default:
1120 break;
1121 }
1122 break;
1123
1124 case '?':
1125 switch (opP->mode)
1126 {
1127 case AREG:
1128 case CONTROL:
1129 case FPREG:
1130 case AINC:
1131 case ADEC:
1132 case IMMED:
1133 case REGLST:
1134 losing++;
1135 break;
1136 case ABSL:
1137 break;
1138 default:
1139 if (opP->reg == PC || opP->reg == ZPC)
1140 losing++;
1141 break;
1142 }
1143 break;
1144
1145 case '@':
1146 switch (opP->mode)
1147 {
1148 case AREG:
1149 case CONTROL:
1150 case FPREG:
1151 case IMMED:
1152 case REGLST:
1153 losing++;
1154 break;
1155 default:
1156 break;
1157 }
1158 break;
1159
1160 case '~': /* For now! (JF FOO is this right?) */
1161 switch (opP->mode)
1162 {
1163 case DREG:
1164 case AREG:
1165 case CONTROL:
1166 case FPREG:
1167 case IMMED:
1168 case REGLST:
1169 losing++;
1170 break;
1171 case ABSL:
1172 break;
1173 default:
1174 if (opP->reg == PC
1175 || opP->reg == ZPC)
1176 losing++;
1177 break;
1178 }
1179 break;
1180
1181 case '3':
1182 if (opP->mode != CONTROL
1183 || (opP->reg != TT0 && opP->reg != TT1))
1184 losing++;
1185 break;
1186
1187 case 'A':
1188 if (opP->mode != AREG)
1189 losing++;
1190 break;
1191
1192 case 'a':
1193 if (opP->mode != AINDR)
1194 ++losing;
1195 break;
1196
1197 case 'B': /* FOO */
1198 if (opP->mode != ABSL
1199 || (flag_long_jumps
1200 && strncmp (instring, "jbsr", 4) == 0))
1201 losing++;
1202 break;
1203
1204 case 'C':
1205 if (opP->mode != CONTROL || opP->reg != CCR)
1206 losing++;
1207 break;
1208
1209 case 'd':
1210 if (opP->mode != DISP
1211 || opP->reg < ADDR0
1212 || opP->reg > ADDR7)
1213 losing++;
1214 break;
1215
1216 case 'D':
1217 if (opP->mode != DREG)
1218 losing++;
1219 break;
1220
1221 case 'F':
1222 if (opP->mode != FPREG)
1223 losing++;
1224 break;
1225
1226 case 'I':
1227 if (opP->mode != CONTROL
1228 || opP->reg < COP0
1229 || opP->reg > COP7)
1230 losing++;
1231 break;
1232
1233 case 'J':
1234 if (opP->mode != CONTROL
1235 || opP->reg < USP
1236 || opP->reg > last_movec_reg)
1237 losing++;
1238 else
1239 {
1240 const enum m68k_register *rp;
1241 for (rp = control_regs; *rp; rp++)
1242 if (*rp == opP->reg)
1243 break;
1244 if (*rp == 0)
1245 losing++;
1246 }
1247 break;
1248
1249 case 'k':
1250 if (opP->mode != IMMED)
1251 losing++;
1252 break;
1253
1254 case 'l':
1255 case 'L':
1256 if (opP->mode == DREG
1257 || opP->mode == AREG
1258 || opP->mode == FPREG)
1259 {
1260 if (s[1] == '8')
1261 losing++;
1262 else
1263 {
1264 switch (opP->mode)
1265 {
1266 case DREG:
1267 opP->mask = 1 << (opP->reg - DATA0);
1268 break;
1269 case AREG:
1270 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1271 break;
1272 case FPREG:
1273 opP->mask = 1 << (opP->reg - FP0 + 16);
1274 break;
1275 default:
1276 abort ();
1277 }
1278 opP->mode = REGLST;
1279 }
1280 }
1281 else if (opP->mode == CONTROL)
1282 {
1283 if (s[1] != '8')
1284 losing++;
1285 else
1286 {
1287 switch (opP->reg)
1288 {
1289 case FPI:
1290 opP->mask = 1 << 24;
1291 break;
1292 case FPS:
1293 opP->mask = 1 << 25;
1294 break;
1295 case FPC:
1296 opP->mask = 1 << 26;
1297 break;
1298 default:
1299 losing++;
1300 break;
1301 }
1302 opP->mode = REGLST;
1303 }
1304 }
1305 else if (opP->mode == ABSL
1306 && opP->disp.size == SIZE_UNSPEC
1307 && opP->disp.exp.X_op == O_constant)
1308 {
1309 /* This is what the MRI REG pseudo-op generates. */
1310 opP->mode = REGLST;
1311 opP->mask = opP->disp.exp.X_add_number;
1312 }
1313 else if (opP->mode != REGLST)
1314 losing++;
1315 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1316 losing++;
1317 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1318 losing++;
1319 break;
1320
1321 case 'M':
1322 if (opP->mode != IMMED)
1323 losing++;
1324 else if (opP->disp.exp.X_op != O_constant
1325 || ! issbyte (opP->disp.exp.X_add_number))
1326 losing++;
1327 else if (! m68k_quick
1328 && instring[3] != 'q'
1329 && instring[4] != 'q')
1330 losing++;
1331 break;
1332
1333 case 'O':
1334 if (opP->mode != DREG && opP->mode != IMMED)
1335 losing++;
1336 break;
1337
1338 case 'Q':
1339 if (opP->mode != IMMED)
1340 losing++;
1341 else if (opP->disp.exp.X_op != O_constant
1342 || opP->disp.exp.X_add_number < 1
1343 || opP->disp.exp.X_add_number > 8)
1344 losing++;
1345 else if (! m68k_quick
1346 && (strncmp (instring, "add", 3) == 0
1347 || strncmp (instring, "sub", 3) == 0)
1348 && instring[3] != 'q')
1349 losing++;
1350 break;
1351
1352 case 'R':
1353 if (opP->mode != DREG && opP->mode != AREG)
1354 losing++;
1355 break;
1356
1357 case 'r':
1358 if (opP->mode != AINDR
1359 && (opP->mode != BASE
1360 || (opP->reg != 0
1361 && opP->reg != ZADDR0)
1362 || opP->disp.exp.X_op != O_absent
1363 || ((opP->index.reg < DATA0
1364 || opP->index.reg > DATA7)
1365 && (opP->index.reg < ADDR0
1366 || opP->index.reg > ADDR7))
1367 || opP->index.size != SIZE_UNSPEC
1368 || opP->index.scale != 1))
1369 losing++;
1370 break;
1371
1372 case 's':
1373 if (opP->mode != CONTROL
1374 || ! (opP->reg == FPI
1375 || opP->reg == FPS
1376 || opP->reg == FPC))
1377 losing++;
1378 break;
1379
1380 case 'S':
1381 if (opP->mode != CONTROL || opP->reg != SR)
1382 losing++;
1383 break;
1384
1385 case 't':
1386 if (opP->mode != IMMED)
1387 losing++;
1388 else if (opP->disp.exp.X_op != O_constant
1389 || opP->disp.exp.X_add_number < 0
1390 || opP->disp.exp.X_add_number > 7)
1391 losing++;
1392 break;
1393
1394 case 'U':
1395 if (opP->mode != CONTROL || opP->reg != USP)
1396 losing++;
1397 break;
1398
1399 /* JF these are out of order. We could put them
1400 in order if we were willing to put up with
1401 bunches of #ifdef m68851s in the code.
1402
1403 Don't forget that you need these operands
1404 to use 68030 MMU instructions. */
1405 #ifndef NO_68851
1406 /* Memory addressing mode used by pflushr */
1407 case '|':
1408 if (opP->mode == CONTROL
1409 || opP->mode == FPREG
1410 || opP->mode == DREG
1411 || opP->mode == AREG
1412 || opP->mode == REGLST)
1413 losing++;
1414 /* We should accept immediate operands, but they
1415 supposedly have to be quad word, and we don't
1416 handle that. I would like to see what a Motorola
1417 assembler does before doing something here. */
1418 if (opP->mode == IMMED)
1419 losing++;
1420 break;
1421
1422 case 'f':
1423 if (opP->mode != CONTROL
1424 || (opP->reg != SFC && opP->reg != DFC))
1425 losing++;
1426 break;
1427
1428 case '0':
1429 if (opP->mode != CONTROL || opP->reg != TC)
1430 losing++;
1431 break;
1432
1433 case '1':
1434 if (opP->mode != CONTROL || opP->reg != AC)
1435 losing++;
1436 break;
1437
1438 case '2':
1439 if (opP->mode != CONTROL
1440 || (opP->reg != CAL
1441 && opP->reg != VAL
1442 && opP->reg != SCC))
1443 losing++;
1444 break;
1445
1446 case 'V':
1447 if (opP->mode != CONTROL
1448 || opP->reg != VAL)
1449 losing++;
1450 break;
1451
1452 case 'W':
1453 if (opP->mode != CONTROL
1454 || (opP->reg != DRP
1455 && opP->reg != SRP
1456 && opP->reg != CRP))
1457 losing++;
1458 break;
1459
1460 case 'X':
1461 if (opP->mode != CONTROL
1462 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1463 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1464 losing++;
1465 break;
1466
1467 case 'Y':
1468 if (opP->mode != CONTROL || opP->reg != PSR)
1469 losing++;
1470 break;
1471
1472 case 'Z':
1473 if (opP->mode != CONTROL || opP->reg != PCSR)
1474 losing++;
1475 break;
1476 #endif
1477 case 'c':
1478 if (opP->mode != CONTROL
1479 || (opP->reg != NC
1480 && opP->reg != IC
1481 && opP->reg != DC
1482 && opP->reg != BC))
1483 {
1484 losing++;
1485 } /* not a cache specifier. */
1486 break;
1487
1488 case '_':
1489 if (opP->mode != ABSL)
1490 ++losing;
1491 break;
1492
1493 default:
1494 abort ();
1495 } /* switch on type of operand */
1496
1497 if (losing)
1498 break;
1499 } /* for each operand */
1500 } /* if immediately wrong */
1501
1502 if (!losing)
1503 {
1504 break;
1505 } /* got it. */
1506
1507 opcode = opcode->m_next;
1508
1509 if (!opcode)
1510 {
1511 if (ok_arch
1512 && !(ok_arch & current_architecture))
1513 {
1514 char buf[200], *cp;
1515 int len;
1516 strcpy (buf,
1517 "invalid instruction for this architecture; needs ");
1518 cp = buf + strlen (buf);
1519 switch (ok_arch)
1520 {
1521 case mfloat:
1522 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1523 break;
1524 case mmmu:
1525 strcpy (cp, "mmu (68030 or 68851)");
1526 break;
1527 case m68020up:
1528 strcpy (cp, "68020 or higher");
1529 break;
1530 case m68000up:
1531 strcpy (cp, "68000 or higher");
1532 break;
1533 case m68010up:
1534 strcpy (cp, "68010 or higher");
1535 break;
1536 default:
1537 {
1538 int got_one = 0, idx;
1539 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1540 idx++)
1541 {
1542 if ((archs[idx].arch & ok_arch)
1543 && ! archs[idx].alias)
1544 {
1545 if (got_one)
1546 {
1547 strcpy (cp, " or ");
1548 cp += strlen (cp);
1549 }
1550 got_one = 1;
1551 strcpy (cp, archs[idx].name);
1552 cp += strlen (cp);
1553 }
1554 }
1555 }
1556 }
1557 len = cp - buf + 1;
1558 cp = malloc (len);
1559 strcpy (cp, buf);
1560 the_ins.error = cp;
1561 }
1562 else
1563 the_ins.error = "operands mismatch";
1564 return;
1565 } /* Fell off the end */
1566
1567 losing = 0;
1568 }
1569
1570 /* now assemble it */
1571
1572 the_ins.args = opcode->m_operands;
1573 the_ins.numargs = opcode->m_opnum;
1574 the_ins.numo = opcode->m_codenum;
1575 the_ins.opcode[0] = getone (opcode);
1576 the_ins.opcode[1] = gettwo (opcode);
1577
1578 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1579 {
1580 /* This switch is a doozy.
1581 Watch the first step; its a big one! */
1582 switch (s[0])
1583 {
1584
1585 case '*':
1586 case '~':
1587 case '%':
1588 case ';':
1589 case '@':
1590 case '!':
1591 case '&':
1592 case '$':
1593 case '?':
1594 case '/':
1595 case '`':
1596 #ifndef NO_68851
1597 case '|':
1598 #endif
1599 switch (opP->mode)
1600 {
1601 case IMMED:
1602 tmpreg = 0x3c; /* 7.4 */
1603 if (strchr ("bwl", s[1]))
1604 nextword = get_num (&opP->disp, 80);
1605 else
1606 nextword = get_num (&opP->disp, 0);
1607 if (isvar (&opP->disp))
1608 add_fix (s[1], &opP->disp, 0, 0);
1609 switch (s[1])
1610 {
1611 case 'b':
1612 if (!isbyte (nextword))
1613 opP->error = "operand out of range";
1614 addword (nextword);
1615 baseo = 0;
1616 break;
1617 case 'w':
1618 if (!isword (nextword))
1619 opP->error = "operand out of range";
1620 addword (nextword);
1621 baseo = 0;
1622 break;
1623 case 'W':
1624 if (!issword (nextword))
1625 opP->error = "operand out of range";
1626 addword (nextword);
1627 baseo = 0;
1628 break;
1629 case 'l':
1630 addword (nextword >> 16);
1631 addword (nextword);
1632 baseo = 0;
1633 break;
1634
1635 case 'f':
1636 baseo = 2;
1637 outro = 8;
1638 break;
1639 case 'F':
1640 baseo = 4;
1641 outro = 11;
1642 break;
1643 case 'x':
1644 baseo = 6;
1645 outro = 15;
1646 break;
1647 case 'p':
1648 baseo = 6;
1649 outro = -1;
1650 break;
1651 default:
1652 abort ();
1653 }
1654 if (!baseo)
1655 break;
1656
1657 /* We gotta put out some float */
1658 if (op (&opP->disp) != O_big)
1659 {
1660 valueT val;
1661 int gencnt;
1662
1663 /* Can other cases happen here? */
1664 if (op (&opP->disp) != O_constant)
1665 abort ();
1666
1667 val = (valueT) offs (&opP->disp);
1668 gencnt = 0;
1669 do
1670 {
1671 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1672 val >>= LITTLENUM_NUMBER_OF_BITS;
1673 ++gencnt;
1674 }
1675 while (val != 0);
1676 offs (&opP->disp) = gencnt;
1677 }
1678 if (offs (&opP->disp) > 0)
1679 {
1680 if (offs (&opP->disp) > baseo)
1681 {
1682 as_warn ("Bignum too big for %c format; truncated",
1683 s[1]);
1684 offs (&opP->disp) = baseo;
1685 }
1686 baseo -= offs (&opP->disp);
1687 while (baseo--)
1688 addword (0);
1689 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1690 offs (&opP->disp)--;
1691 --wordp)
1692 addword (*wordp);
1693 break;
1694 }
1695 gen_to_words (words, baseo, (long) outro);
1696 for (wordp = words; baseo--; wordp++)
1697 addword (*wordp);
1698 break;
1699 case DREG:
1700 tmpreg = opP->reg - DATA; /* 0.dreg */
1701 break;
1702 case AREG:
1703 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1704 break;
1705 case AINDR:
1706 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1707 break;
1708 case ADEC:
1709 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1710 break;
1711 case AINC:
1712 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1713 break;
1714 case DISP:
1715
1716 nextword = get_num (&opP->disp, 80);
1717
1718 if (opP->reg == PC
1719 && ! isvar (&opP->disp)
1720 && m68k_abspcadd)
1721 {
1722 opP->disp.exp.X_op = O_symbol;
1723 #ifndef BFD_ASSEMBLER
1724 opP->disp.exp.X_add_symbol = &abs_symbol;
1725 #else
1726 opP->disp.exp.X_add_symbol =
1727 section_symbol (absolute_section);
1728 #endif
1729 }
1730
1731 /* Force into index mode. Hope this works */
1732
1733 /* We do the first bit for 32-bit displacements, and the
1734 second bit for 16 bit ones. It is possible that we
1735 should make the default be WORD instead of LONG, but
1736 I think that'd break GCC, so we put up with a little
1737 inefficiency for the sake of working output. */
1738
1739 if (!issword (nextword)
1740 || (isvar (&opP->disp)
1741 && ((opP->disp.size == SIZE_UNSPEC
1742 && flag_short_refs == 0
1743 && cpu_of_arch (current_architecture) >= m68020)
1744 || opP->disp.size == SIZE_LONG)))
1745 {
1746 if (cpu_of_arch (current_architecture) < m68020)
1747 opP->error =
1748 "displacement too large for this architecture; needs 68020 or higher";
1749 if (opP->reg == PC)
1750 tmpreg = 0x3B; /* 7.3 */
1751 else
1752 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1753 if (isvar (&opP->disp))
1754 {
1755 if (opP->reg == PC)
1756 {
1757 if (opP->disp.size == SIZE_LONG
1758 #ifdef OBJ_ELF
1759 /* If the displacement needs pic
1760 relocation it cannot be relaxed. */
1761 || opP->disp.pic_reloc != pic_none
1762 #endif
1763 )
1764 {
1765 addword (0x0170);
1766 add_fix ('l', &opP->disp, 1, 2);
1767 }
1768 else
1769 {
1770 add_frag (adds (&opP->disp),
1771 offs (&opP->disp),
1772 TAB (PCLEA, SZ_UNDEF));
1773 break;
1774 }
1775 }
1776 else
1777 {
1778 addword (0x0170);
1779 add_fix ('l', &opP->disp, 0, 0);
1780 }
1781 }
1782 else
1783 addword (0x0170);
1784 addword (nextword >> 16);
1785 }
1786 else
1787 {
1788 if (opP->reg == PC)
1789 tmpreg = 0x3A; /* 7.2 */
1790 else
1791 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1792
1793 if (isvar (&opP->disp))
1794 {
1795 if (opP->reg == PC)
1796 {
1797 add_fix ('w', &opP->disp, 1, 0);
1798 }
1799 else
1800 add_fix ('w', &opP->disp, 0, 0);
1801 }
1802 }
1803 addword (nextword);
1804 break;
1805
1806 case POST:
1807 case PRE:
1808 case BASE:
1809 nextword = 0;
1810 baseo = get_num (&opP->disp, 80);
1811 if (opP->mode == POST || opP->mode == PRE)
1812 outro = get_num (&opP->odisp, 80);
1813 /* Figure out the `addressing mode'.
1814 Also turn on the BASE_DISABLE bit, if needed. */
1815 if (opP->reg == PC || opP->reg == ZPC)
1816 {
1817 tmpreg = 0x3b; /* 7.3 */
1818 if (opP->reg == ZPC)
1819 nextword |= 0x80;
1820 }
1821 else if (opP->reg == 0)
1822 {
1823 nextword |= 0x80;
1824 tmpreg = 0x30; /* 6.garbage */
1825 }
1826 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1827 {
1828 nextword |= 0x80;
1829 tmpreg = 0x30 + opP->reg - ZADDR0;
1830 }
1831 else
1832 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1833
1834 siz1 = opP->disp.size;
1835 if (opP->mode == POST || opP->mode == PRE)
1836 siz2 = opP->odisp.size;
1837 else
1838 siz2 = SIZE_UNSPEC;
1839
1840 /* Index register stuff */
1841 if (opP->index.reg != 0
1842 && opP->index.reg >= DATA
1843 && opP->index.reg <= ADDR7)
1844 {
1845 nextword |= (opP->index.reg - DATA) << 12;
1846
1847 if (opP->index.size == SIZE_UNSPEC
1848 || opP->index.size == SIZE_LONG)
1849 nextword |= 0x800;
1850
1851 if (cpu_of_arch (current_architecture) < m68020)
1852 {
1853 if (opP->index.scale != 1)
1854 {
1855 opP->error =
1856 "scale factor invalid on this architecture; needs 68020 or higher";
1857 }
1858 }
1859
1860 switch (opP->index.scale)
1861 {
1862 case 1:
1863 break;
1864 case 2:
1865 nextword |= 0x200;
1866 break;
1867 case 4:
1868 nextword |= 0x400;
1869 break;
1870 case 8:
1871 nextword |= 0x600;
1872 break;
1873 default:
1874 abort ();
1875 }
1876 /* IF its simple,
1877 GET US OUT OF HERE! */
1878
1879 /* Must be INDEX, with an index register. Address
1880 register cannot be ZERO-PC, and either :b was
1881 forced, or we know it will fit. For a 68000 or
1882 68010, force this mode anyways, because the
1883 larger modes aren't supported. */
1884 if (opP->mode == BASE
1885 && ((opP->reg >= ADDR0
1886 && opP->reg <= ADDR7)
1887 || opP->reg == PC))
1888 {
1889 if (siz1 == SIZE_BYTE
1890 || cpu_of_arch (current_architecture) < m68020
1891 || (siz1 == SIZE_UNSPEC
1892 && ! isvar (&opP->disp)
1893 && issbyte (baseo)))
1894 {
1895 nextword += baseo & 0xff;
1896 addword (nextword);
1897 if (isvar (&opP->disp))
1898 {
1899 /* Do a byte relocation. If it doesn't
1900 fit (possible on m68000) let the
1901 fixup processing complain later. */
1902 if (opP->reg == PC)
1903 add_fix ('B', &opP->disp, 1, 1);
1904 else
1905 add_fix ('B', &opP->disp, 0, 0);
1906 }
1907 else if (siz1 != SIZE_BYTE)
1908 {
1909 if (siz1 != SIZE_UNSPEC)
1910 as_warn ("Forcing byte displacement");
1911 if (! issbyte (baseo))
1912 opP->error = "byte displacement out of range";
1913 }
1914
1915 break;
1916 }
1917 else if (siz1 == SIZE_UNSPEC
1918 && opP->reg == PC
1919 && isvar (&opP->disp)
1920 && subs (&opP->disp) == NULL
1921 #ifdef OBJ_ELF
1922 /* If the displacement needs pic
1923 relocation it cannot be relaxed. */
1924 && opP->disp.pic_reloc == pic_none
1925 #endif
1926 )
1927 {
1928 nextword += baseo & 0xff;
1929 addword (nextword);
1930 add_frag (adds (&opP->disp), offs (&opP->disp),
1931 TAB (PCINDEX, SZ_UNDEF));
1932
1933 break;
1934 }
1935 }
1936 }
1937 else
1938 {
1939 nextword |= 0x40; /* No index reg */
1940 if (opP->index.reg >= ZDATA0
1941 && opP->index.reg <= ZDATA7)
1942 nextword |= (opP->index.reg - ZDATA0) << 12;
1943 else if (opP->index.reg >= ZADDR0
1944 || opP->index.reg <= ZADDR7)
1945 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1946 }
1947
1948 /* It isn't simple. */
1949
1950 if (cpu_of_arch (current_architecture) < m68020)
1951 opP->error =
1952 "invalid operand mode for this architecture; needs 68020 or higher";
1953
1954 nextword |= 0x100;
1955 /* If the guy specified a width, we assume that it is
1956 wide enough. Maybe it isn't. If so, we lose. */
1957 switch (siz1)
1958 {
1959 case SIZE_UNSPEC:
1960 if (isvar (&opP->disp)
1961 ? m68k_rel32
1962 : ! issword (baseo))
1963 {
1964 siz1 = SIZE_LONG;
1965 nextword |= 0x30;
1966 }
1967 else if (! isvar (&opP->disp) && baseo == 0)
1968 nextword |= 0x10;
1969 else
1970 {
1971 nextword |= 0x20;
1972 siz1 = SIZE_WORD;
1973 }
1974 break;
1975 case SIZE_BYTE:
1976 as_warn (":b not permitted; defaulting to :w");
1977 /* Fall through. */
1978 case SIZE_WORD:
1979 nextword |= 0x20;
1980 break;
1981 case SIZE_LONG:
1982 nextword |= 0x30;
1983 break;
1984 }
1985
1986 /* Figure out innner displacement stuff */
1987 if (opP->mode == POST || opP->mode == PRE)
1988 {
1989 switch (siz2)
1990 {
1991 case SIZE_UNSPEC:
1992 if (isvar (&opP->odisp)
1993 ? m68k_rel32
1994 : ! issword (outro))
1995 {
1996 siz2 = SIZE_LONG;
1997 nextword |= 0x3;
1998 }
1999 else if (! isvar (&opP->odisp) && outro == 0)
2000 nextword |= 0x1;
2001 else
2002 {
2003 nextword |= 0x2;
2004 siz2 = SIZE_WORD;
2005 }
2006 break;
2007 case 1:
2008 as_warn (":b not permitted; defaulting to :w");
2009 /* Fall through. */
2010 case 2:
2011 nextword |= 0x2;
2012 break;
2013 case 3:
2014 nextword |= 0x3;
2015 break;
2016 }
2017 if (opP->mode == POST
2018 && (nextword & 0x40) == 0)
2019 nextword |= 0x04;
2020 }
2021 addword (nextword);
2022
2023 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2024 {
2025 if (opP->reg == PC || opP->reg == ZPC)
2026 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2027 else
2028 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2029 }
2030 if (siz1 == SIZE_LONG)
2031 addword (baseo >> 16);
2032 if (siz1 != SIZE_UNSPEC)
2033 addword (baseo);
2034
2035 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2036 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2037 if (siz2 == SIZE_LONG)
2038 addword (outro >> 16);
2039 if (siz2 != SIZE_UNSPEC)
2040 addword (outro);
2041
2042 break;
2043
2044 case ABSL:
2045 nextword = get_num (&opP->disp, 80);
2046 switch (opP->disp.size)
2047 {
2048 default:
2049 abort ();
2050 case SIZE_UNSPEC:
2051 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2052 {
2053 tmpreg = 0x38; /* 7.0 */
2054 addword (nextword);
2055 break;
2056 }
2057 /* Don't generate pc relative code on 68010 and
2058 68000. */
2059 if (isvar (&opP->disp)
2060 && !subs (&opP->disp)
2061 && adds (&opP->disp)
2062 #ifdef OBJ_ELF
2063 /* If the displacement needs pic relocation it
2064 cannot be relaxed. */
2065 && opP->disp.pic_reloc == pic_none
2066 #endif
2067 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2068 && cpu_of_arch (current_architecture) >= m68020
2069 && !flag_long_jumps
2070 && !strchr ("~%&$?", s[0]))
2071 {
2072 tmpreg = 0x3A; /* 7.2 */
2073 add_frag (adds (&opP->disp),
2074 offs (&opP->disp),
2075 TAB (PCREL, SZ_UNDEF));
2076 break;
2077 }
2078 /* Fall through into long */
2079 case SIZE_LONG:
2080 if (isvar (&opP->disp))
2081 add_fix ('l', &opP->disp, 0, 0);
2082
2083 tmpreg = 0x39;/* 7.1 mode */
2084 addword (nextword >> 16);
2085 addword (nextword);
2086 break;
2087
2088 case SIZE_WORD: /* Word */
2089 if (isvar (&opP->disp))
2090 add_fix ('w', &opP->disp, 0, 0);
2091
2092 tmpreg = 0x38;/* 7.0 mode */
2093 addword (nextword);
2094 break;
2095 }
2096 break;
2097 case CONTROL:
2098 case FPREG:
2099 default:
2100 as_bad ("unknown/incorrect operand");
2101 /* abort(); */
2102 }
2103 install_gen_operand (s[1], tmpreg);
2104 break;
2105
2106 case '#':
2107 case '^':
2108 switch (s[1])
2109 { /* JF: I hate floating point! */
2110 case 'j':
2111 tmpreg = 70;
2112 break;
2113 case '8':
2114 tmpreg = 20;
2115 break;
2116 case 'C':
2117 tmpreg = 50;
2118 break;
2119 case '3':
2120 default:
2121 tmpreg = 80;
2122 break;
2123 }
2124 tmpreg = get_num (&opP->disp, tmpreg);
2125 if (isvar (&opP->disp))
2126 add_fix (s[1], &opP->disp, 0, 0);
2127 switch (s[1])
2128 {
2129 case 'b': /* Danger: These do no check for
2130 certain types of overflow.
2131 user beware! */
2132 if (!isbyte (tmpreg))
2133 opP->error = "out of range";
2134 insop (tmpreg, opcode);
2135 if (isvar (&opP->disp))
2136 the_ins.reloc[the_ins.nrel - 1].n =
2137 (opcode->m_codenum) * 2 + 1;
2138 break;
2139 case 'w':
2140 if (!isword (tmpreg))
2141 opP->error = "out of range";
2142 insop (tmpreg, opcode);
2143 if (isvar (&opP->disp))
2144 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2145 break;
2146 case 'W':
2147 if (!issword (tmpreg))
2148 opP->error = "out of range";
2149 insop (tmpreg, opcode);
2150 if (isvar (&opP->disp))
2151 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2152 break;
2153 case 'l':
2154 /* Because of the way insop works, we put these two out
2155 backwards. */
2156 insop (tmpreg, opcode);
2157 insop (tmpreg >> 16, opcode);
2158 if (isvar (&opP->disp))
2159 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2160 break;
2161 case '3':
2162 tmpreg &= 0xFF;
2163 case '8':
2164 case 'C':
2165 install_operand (s[1], tmpreg);
2166 break;
2167 default:
2168 abort ();
2169 }
2170 break;
2171
2172 case '+':
2173 case '-':
2174 case 'A':
2175 case 'a':
2176 install_operand (s[1], opP->reg - ADDR);
2177 break;
2178
2179 case 'B':
2180 tmpreg = get_num (&opP->disp, 80);
2181 switch (s[1])
2182 {
2183 case 'B':
2184 /* The pc_fix argument winds up in fx_pcrel_adjust,
2185 which is a char, and may therefore be unsigned. We
2186 want to pass -1, but we pass 64 instead, and convert
2187 back in md_pcrel_from. */
2188 add_fix ('B', &opP->disp, 1, 64);
2189 break;
2190 case 'W':
2191 add_fix ('w', &opP->disp, 1, 0);
2192 addword (0);
2193 break;
2194 case 'L':
2195 long_branch:
2196 if (cpu_of_arch (current_architecture) < m68020)
2197 as_warn ("Can't use long branches on 68000/68010");
2198 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2199 add_fix ('l', &opP->disp, 1, 0);
2200 addword (0);
2201 addword (0);
2202 break;
2203 case 'g':
2204 if (subs (&opP->disp)) /* We can't relax it */
2205 goto long_branch;
2206
2207 #ifdef OBJ_ELF
2208 /* If the displacement needs pic relocation it cannot be
2209 relaxed. */
2210 if (opP->disp.pic_reloc != pic_none)
2211 goto long_branch;
2212 #endif
2213
2214 /* This could either be a symbol, or an absolute
2215 address. No matter, the frag hacking will finger it
2216 out. Not quite: it can't switch from BRANCH to
2217 BCC68000 for the case where opnd is absolute (it
2218 needs to use the 68000 hack since no conditional abs
2219 jumps). */
2220 if (((cpu_of_arch (current_architecture) < m68020)
2221 || (0 == adds (&opP->disp)))
2222 && (the_ins.opcode[0] >= 0x6200)
2223 && (the_ins.opcode[0] <= 0x6f00))
2224 add_frag (adds (&opP->disp), offs (&opP->disp),
2225 TAB (BCC68000, SZ_UNDEF));
2226 else
2227 add_frag (adds (&opP->disp), offs (&opP->disp),
2228 TAB (ABRANCH, SZ_UNDEF));
2229 break;
2230 case 'w':
2231 if (isvar (&opP->disp))
2232 {
2233 #if 1
2234 /* check for DBcc instruction */
2235 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2236 {
2237 /* size varies if patch */
2238 /* needed for long form */
2239 add_frag (adds (&opP->disp), offs (&opP->disp),
2240 TAB (DBCC, SZ_UNDEF));
2241 break;
2242 }
2243 #endif
2244 add_fix ('w', &opP->disp, 1, 0);
2245 }
2246 addword (0);
2247 break;
2248 case 'C': /* Fixed size LONG coproc branches */
2249 add_fix ('l', &opP->disp, 1, 0);
2250 addword (0);
2251 addword (0);
2252 break;
2253 case 'c': /* Var size Coprocesssor branches */
2254 if (subs (&opP->disp))
2255 {
2256 add_fix ('l', &opP->disp, 1, 0);
2257 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2258 }
2259 else if (adds (&opP->disp))
2260 add_frag (adds (&opP->disp), offs (&opP->disp),
2261 TAB (FBRANCH, SZ_UNDEF));
2262 else
2263 {
2264 /* add_frag((symbolS *) 0, offs(&opP->disp),
2265 TAB(FBRANCH,SHORT)); */
2266 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2267 add_fix ('l', &opP->disp, 1, 0);
2268 addword (0);
2269 addword (0);
2270 }
2271 break;
2272 default:
2273 abort ();
2274 }
2275 break;
2276
2277 case 'C': /* Ignore it */
2278 break;
2279
2280 case 'd': /* JF this is a kludge */
2281 install_operand ('s', opP->reg - ADDR);
2282 tmpreg = get_num (&opP->disp, 80);
2283 if (!issword (tmpreg))
2284 {
2285 as_warn ("Expression out of range, using 0");
2286 tmpreg = 0;
2287 }
2288 addword (tmpreg);
2289 break;
2290
2291 case 'D':
2292 install_operand (s[1], opP->reg - DATA);
2293 break;
2294
2295 case 'F':
2296 install_operand (s[1], opP->reg - FP0);
2297 break;
2298
2299 case 'I':
2300 tmpreg = opP->reg - COP0;
2301 install_operand (s[1], tmpreg);
2302 break;
2303
2304 case 'J': /* JF foo */
2305 switch (opP->reg)
2306 {
2307 case SFC:
2308 tmpreg = 0x000;
2309 break;
2310 case DFC:
2311 tmpreg = 0x001;
2312 break;
2313 case CACR:
2314 tmpreg = 0x002;
2315 break;
2316 case TC:
2317 tmpreg = 0x003;
2318 break;
2319 case ITT0:
2320 tmpreg = 0x004;
2321 break;
2322 case ITT1:
2323 tmpreg = 0x005;
2324 break;
2325 case DTT0:
2326 tmpreg = 0x006;
2327 break;
2328 case DTT1:
2329 tmpreg = 0x007;
2330 break;
2331 case BUSCR:
2332 tmpreg = 0x008;
2333 break;
2334
2335 case USP:
2336 tmpreg = 0x800;
2337 break;
2338 case VBR:
2339 tmpreg = 0x801;
2340 break;
2341 case CAAR:
2342 tmpreg = 0x802;
2343 break;
2344 case MSP:
2345 tmpreg = 0x803;
2346 break;
2347 case ISP:
2348 tmpreg = 0x804;
2349 break;
2350 case MMUSR:
2351 tmpreg = 0x805;
2352 break;
2353 case URP:
2354 tmpreg = 0x806;
2355 break;
2356 case SRP:
2357 tmpreg = 0x807;
2358 break;
2359 case PCR:
2360 tmpreg = 0x808;
2361 break;
2362 default:
2363 abort ();
2364 }
2365 install_operand (s[1], tmpreg);
2366 break;
2367
2368 case 'k':
2369 tmpreg = get_num (&opP->disp, 55);
2370 install_operand (s[1], tmpreg & 0x7f);
2371 break;
2372
2373 case 'l':
2374 tmpreg = opP->mask;
2375 if (s[1] == 'w')
2376 {
2377 if (tmpreg & 0x7FF0000)
2378 as_bad ("Floating point register in register list");
2379 insop (reverse_16_bits (tmpreg), opcode);
2380 }
2381 else
2382 {
2383 if (tmpreg & 0x700FFFF)
2384 as_bad ("Wrong register in floating-point reglist");
2385 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2386 }
2387 break;
2388
2389 case 'L':
2390 tmpreg = opP->mask;
2391 if (s[1] == 'w')
2392 {
2393 if (tmpreg & 0x7FF0000)
2394 as_bad ("Floating point register in register list");
2395 insop (tmpreg, opcode);
2396 }
2397 else if (s[1] == '8')
2398 {
2399 if (tmpreg & 0x0FFFFFF)
2400 as_bad ("incorrect register in reglist");
2401 install_operand (s[1], tmpreg >> 24);
2402 }
2403 else
2404 {
2405 if (tmpreg & 0x700FFFF)
2406 as_bad ("wrong register in floating-point reglist");
2407 else
2408 install_operand (s[1], tmpreg >> 16);
2409 }
2410 break;
2411
2412 case 'M':
2413 install_operand (s[1], get_num (&opP->disp, 60));
2414 break;
2415
2416 case 'O':
2417 tmpreg = ((opP->mode == DREG)
2418 ? 0x20 + opP->reg - DATA
2419 : (get_num (&opP->disp, 40) & 0x1F));
2420 install_operand (s[1], tmpreg);
2421 break;
2422
2423 case 'Q':
2424 tmpreg = get_num (&opP->disp, 10);
2425 if (tmpreg == 8)
2426 tmpreg = 0;
2427 install_operand (s[1], tmpreg);
2428 break;
2429
2430 case 'R':
2431 /* This depends on the fact that ADDR registers are eight
2432 more than their corresponding DATA regs, so the result
2433 will have the ADDR_REG bit set */
2434 install_operand (s[1], opP->reg - DATA);
2435 break;
2436
2437 case 'r':
2438 if (opP->mode == AINDR)
2439 install_operand (s[1], opP->reg - DATA);
2440 else
2441 install_operand (s[1], opP->index.reg - DATA);
2442 break;
2443
2444 case 's':
2445 if (opP->reg == FPI)
2446 tmpreg = 0x1;
2447 else if (opP->reg == FPS)
2448 tmpreg = 0x2;
2449 else if (opP->reg == FPC)
2450 tmpreg = 0x4;
2451 else
2452 abort ();
2453 install_operand (s[1], tmpreg);
2454 break;
2455
2456 case 'S': /* Ignore it */
2457 break;
2458
2459 case 'T':
2460 install_operand (s[1], get_num (&opP->disp, 30));
2461 break;
2462
2463 case 'U': /* Ignore it */
2464 break;
2465
2466 case 'c':
2467 switch (opP->reg)
2468 {
2469 case NC:
2470 tmpreg = 0;
2471 break;
2472 case DC:
2473 tmpreg = 1;
2474 break;
2475 case IC:
2476 tmpreg = 2;
2477 break;
2478 case BC:
2479 tmpreg = 3;
2480 break;
2481 default:
2482 as_fatal ("failed sanity check");
2483 } /* switch on cache token */
2484 install_operand (s[1], tmpreg);
2485 break;
2486 #ifndef NO_68851
2487 /* JF: These are out of order, I fear. */
2488 case 'f':
2489 switch (opP->reg)
2490 {
2491 case SFC:
2492 tmpreg = 0;
2493 break;
2494 case DFC:
2495 tmpreg = 1;
2496 break;
2497 default:
2498 abort ();
2499 }
2500 install_operand (s[1], tmpreg);
2501 break;
2502
2503 case '0':
2504 case '1':
2505 case '2':
2506 switch (opP->reg)
2507 {
2508 case TC:
2509 tmpreg = 0;
2510 break;
2511 case CAL:
2512 tmpreg = 4;
2513 break;
2514 case VAL:
2515 tmpreg = 5;
2516 break;
2517 case SCC:
2518 tmpreg = 6;
2519 break;
2520 case AC:
2521 tmpreg = 7;
2522 break;
2523 default:
2524 abort ();
2525 }
2526 install_operand (s[1], tmpreg);
2527 break;
2528
2529 case 'V':
2530 if (opP->reg == VAL)
2531 break;
2532 abort ();
2533
2534 case 'W':
2535 switch (opP->reg)
2536 {
2537 case DRP:
2538 tmpreg = 1;
2539 break;
2540 case SRP:
2541 tmpreg = 2;
2542 break;
2543 case CRP:
2544 tmpreg = 3;
2545 break;
2546 default:
2547 abort ();
2548 }
2549 install_operand (s[1], tmpreg);
2550 break;
2551
2552 case 'X':
2553 switch (opP->reg)
2554 {
2555 case BAD:
2556 case BAD + 1:
2557 case BAD + 2:
2558 case BAD + 3:
2559 case BAD + 4:
2560 case BAD + 5:
2561 case BAD + 6:
2562 case BAD + 7:
2563 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2564 break;
2565
2566 case BAC:
2567 case BAC + 1:
2568 case BAC + 2:
2569 case BAC + 3:
2570 case BAC + 4:
2571 case BAC + 5:
2572 case BAC + 6:
2573 case BAC + 7:
2574 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2575 break;
2576
2577 default:
2578 abort ();
2579 }
2580 install_operand (s[1], tmpreg);
2581 break;
2582 case 'Y':
2583 know (opP->reg == PSR);
2584 break;
2585 case 'Z':
2586 know (opP->reg == PCSR);
2587 break;
2588 #endif /* m68851 */
2589 case '3':
2590 switch (opP->reg)
2591 {
2592 case TT0:
2593 tmpreg = 2;
2594 break;
2595 case TT1:
2596 tmpreg = 3;
2597 break;
2598 default:
2599 abort ();
2600 }
2601 install_operand (s[1], tmpreg);
2602 break;
2603 case 't':
2604 tmpreg = get_num (&opP->disp, 20);
2605 install_operand (s[1], tmpreg);
2606 break;
2607 case '_': /* used only for move16 absolute 32-bit address */
2608 tmpreg = get_num (&opP->disp, 80);
2609 addword (tmpreg >> 16);
2610 addword (tmpreg & 0xFFFF);
2611 break;
2612 default:
2613 abort ();
2614 }
2615 }
2616
2617 /* By the time whe get here (FINALLY) the_ins contains the complete
2618 instruction, ready to be emitted. . . */
2619 }
2620
2621 static int
2622 reverse_16_bits (in)
2623 int in;
2624 {
2625 int out = 0;
2626 int n;
2627
2628 static int mask[16] =
2629 {
2630 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2631 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2632 };
2633 for (n = 0; n < 16; n++)
2634 {
2635 if (in & mask[n])
2636 out |= mask[15 - n];
2637 }
2638 return out;
2639 } /* reverse_16_bits() */
2640
2641 static int
2642 reverse_8_bits (in)
2643 int in;
2644 {
2645 int out = 0;
2646 int n;
2647
2648 static int mask[8] =
2649 {
2650 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2651 };
2652
2653 for (n = 0; n < 8; n++)
2654 {
2655 if (in & mask[n])
2656 out |= mask[7 - n];
2657 }
2658 return out;
2659 } /* reverse_8_bits() */
2660
2661 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2662 (that value is chosen in the frag_var call in md_assemble). TYPE
2663 is the subtype of the frag to be generated; its primary type is
2664 rs_machine_dependent.
2665
2666 The TYPE parameter is also used by md_convert_frag_1 and
2667 md_estimate_size_before_relax. The appropriate type of fixup will
2668 be emitted by md_convert_frag_1.
2669
2670 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2671 static void
2672 install_operand (mode, val)
2673 int mode;
2674 int val;
2675 {
2676 switch (mode)
2677 {
2678 case 's':
2679 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2680 break;
2681 case 'd':
2682 the_ins.opcode[0] |= val << 9;
2683 break;
2684 case '1':
2685 the_ins.opcode[1] |= val << 12;
2686 break;
2687 case '2':
2688 the_ins.opcode[1] |= val << 6;
2689 break;
2690 case '3':
2691 the_ins.opcode[1] |= val;
2692 break;
2693 case '4':
2694 the_ins.opcode[2] |= val << 12;
2695 break;
2696 case '5':
2697 the_ins.opcode[2] |= val << 6;
2698 break;
2699 case '6':
2700 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2701 three words long! */
2702 the_ins.numo++;
2703 the_ins.opcode[2] |= val;
2704 break;
2705 case '7':
2706 the_ins.opcode[1] |= val << 7;
2707 break;
2708 case '8':
2709 the_ins.opcode[1] |= val << 10;
2710 break;
2711 #ifndef NO_68851
2712 case '9':
2713 the_ins.opcode[1] |= val << 5;
2714 break;
2715 #endif
2716
2717 case 't':
2718 the_ins.opcode[1] |= (val << 10) | (val << 7);
2719 break;
2720 case 'D':
2721 the_ins.opcode[1] |= (val << 12) | val;
2722 break;
2723 case 'g':
2724 the_ins.opcode[0] |= val = 0xff;
2725 break;
2726 case 'i':
2727 the_ins.opcode[0] |= val << 9;
2728 break;
2729 case 'C':
2730 the_ins.opcode[1] |= val;
2731 break;
2732 case 'j':
2733 the_ins.opcode[1] |= val;
2734 the_ins.numo++; /* What a hack */
2735 break;
2736 case 'k':
2737 the_ins.opcode[1] |= val << 4;
2738 break;
2739 case 'b':
2740 case 'w':
2741 case 'W':
2742 case 'l':
2743 break;
2744 case 'e':
2745 the_ins.opcode[0] |= (val << 6);
2746 break;
2747 case 'L':
2748 the_ins.opcode[1] = (val >> 16);
2749 the_ins.opcode[2] = val & 0xffff;
2750 break;
2751 case 'c':
2752 default:
2753 as_fatal ("failed sanity check.");
2754 }
2755 } /* install_operand() */
2756
2757 static void
2758 install_gen_operand (mode, val)
2759 int mode;
2760 int val;
2761 {
2762 switch (mode)
2763 {
2764 case 's':
2765 the_ins.opcode[0] |= val;
2766 break;
2767 case 'd':
2768 /* This is a kludge!!! */
2769 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2770 break;
2771 case 'b':
2772 case 'w':
2773 case 'l':
2774 case 'f':
2775 case 'F':
2776 case 'x':
2777 case 'p':
2778 the_ins.opcode[0] |= val;
2779 break;
2780 /* more stuff goes here */
2781 default:
2782 as_fatal ("failed sanity check.");
2783 }
2784 } /* install_gen_operand() */
2785
2786 /*
2787 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2788 * then deal with the bitfield hack.
2789 */
2790
2791 static char *
2792 crack_operand (str, opP)
2793 register char *str;
2794 register struct m68k_op *opP;
2795 {
2796 register int parens;
2797 register int c;
2798 register char *beg_str;
2799 int inquote = 0;
2800
2801 if (!str)
2802 {
2803 return str;
2804 }
2805 beg_str = str;
2806 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
2807 {
2808 if (! inquote)
2809 {
2810 if (*str == '(')
2811 parens++;
2812 else if (*str == ')')
2813 {
2814 if (!parens)
2815 { /* ERROR */
2816 opP->error = "Extra )";
2817 return str;
2818 }
2819 --parens;
2820 }
2821 }
2822 if (flag_mri && *str == '\'')
2823 inquote = ! inquote;
2824 }
2825 if (!*str && parens)
2826 { /* ERROR */
2827 opP->error = "Missing )";
2828 return str;
2829 }
2830 c = *str;
2831 *str = '\0';
2832 if (m68k_ip_op (beg_str, opP) != 0)
2833 {
2834 *str = c;
2835 return str;
2836 }
2837 *str = c;
2838 if (c == '}')
2839 c = *++str; /* JF bitfield hack */
2840 if (c)
2841 {
2842 c = *++str;
2843 if (!c)
2844 as_bad ("Missing operand");
2845 }
2846 return str;
2847 }
2848
2849 /* This is the guts of the machine-dependent assembler. STR points to a
2850 machine dependent instruction. This function is supposed to emit
2851 the frags/bytes it assembles to.
2852 */
2853
2854 void
2855 insert_reg (regname, regnum)
2856 char *regname;
2857 int regnum;
2858 {
2859 char buf[100];
2860 int i;
2861
2862 #ifdef REGISTER_PREFIX
2863 if (!flag_reg_prefix_optional)
2864 {
2865 buf[0] = REGISTER_PREFIX;
2866 strcpy (buf + 1, regname);
2867 regname = buf;
2868 }
2869 #endif
2870
2871 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2872 &zero_address_frag));
2873
2874 for (i = 0; regname[i]; i++)
2875 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2876 buf[i] = '\0';
2877
2878 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2879 &zero_address_frag));
2880 }
2881
2882 struct init_entry
2883 {
2884 const char *name;
2885 int number;
2886 };
2887
2888 static const struct init_entry init_table[] =
2889 {
2890 { "d0", DATA0 },
2891 { "d1", DATA1 },
2892 { "d2", DATA2 },
2893 { "d3", DATA3 },
2894 { "d4", DATA4 },
2895 { "d5", DATA5 },
2896 { "d6", DATA6 },
2897 { "d7", DATA7 },
2898 { "a0", ADDR0 },
2899 { "a1", ADDR1 },
2900 { "a2", ADDR2 },
2901 { "a3", ADDR3 },
2902 { "a4", ADDR4 },
2903 { "a5", ADDR5 },
2904 { "a6", ADDR6 },
2905 { "fp", ADDR6 },
2906 { "a7", ADDR7 },
2907 { "sp", ADDR7 },
2908 { "ssp", ADDR7 },
2909 { "fp0", FP0 },
2910 { "fp1", FP1 },
2911 { "fp2", FP2 },
2912 { "fp3", FP3 },
2913 { "fp4", FP4 },
2914 { "fp5", FP5 },
2915 { "fp6", FP6 },
2916 { "fp7", FP7 },
2917 { "fpi", FPI },
2918 { "fpiar", FPI },
2919 { "fpc", FPI },
2920 { "fps", FPS },
2921 { "fpsr", FPS },
2922 { "fpc", FPC },
2923 { "fpcr", FPC },
2924 { "control", FPC },
2925 { "status", FPS },
2926 { "iaddr", FPI },
2927
2928 { "cop0", COP0 },
2929 { "cop1", COP1 },
2930 { "cop2", COP2 },
2931 { "cop3", COP3 },
2932 { "cop4", COP4 },
2933 { "cop5", COP5 },
2934 { "cop6", COP6 },
2935 { "cop7", COP7 },
2936 { "pc", PC },
2937 { "zpc", ZPC },
2938 { "sr", SR },
2939
2940 { "ccr", CCR },
2941 { "cc", CCR },
2942
2943 { "usp", USP },
2944 { "isp", ISP },
2945 { "sfc", SFC },
2946 { "sfcr", SFC },
2947 { "dfc", DFC },
2948 { "dfcr", DFC },
2949 { "cacr", CACR },
2950 { "caar", CAAR },
2951
2952 { "vbr", VBR },
2953
2954 { "msp", MSP },
2955 { "itt0", ITT0 },
2956 { "itt1", ITT1 },
2957 { "dtt0", DTT0 },
2958 { "dtt1", DTT1 },
2959 { "mmusr", MMUSR },
2960 { "tc", TC },
2961 { "srp", SRP },
2962 { "urp", URP },
2963 { "buscr", BUSCR },
2964 { "pcr", PCR },
2965
2966 { "ac", AC },
2967 { "bc", BC },
2968 { "cal", CAL },
2969 { "crp", CRP },
2970 { "drp", DRP },
2971 { "pcsr", PCSR },
2972 { "psr", PSR },
2973 { "scc", SCC },
2974 { "val", VAL },
2975 { "bad0", BAD0 },
2976 { "bad1", BAD1 },
2977 { "bad2", BAD2 },
2978 { "bad3", BAD3 },
2979 { "bad4", BAD4 },
2980 { "bad5", BAD5 },
2981 { "bad6", BAD6 },
2982 { "bad7", BAD7 },
2983 { "bac0", BAC0 },
2984 { "bac1", BAC1 },
2985 { "bac2", BAC2 },
2986 { "bac3", BAC3 },
2987 { "bac4", BAC4 },
2988 { "bac5", BAC5 },
2989 { "bac6", BAC6 },
2990 { "bac7", BAC7 },
2991
2992 { "ic", IC },
2993 { "dc", DC },
2994 { "nc", NC },
2995
2996 { "tt0", TT0 },
2997 { "tt1", TT1 },
2998 /* 68ec030 versions of same */
2999 { "ac0", TT0 },
3000 { "ac1", TT1 },
3001 /* 68ec030 access control unit, identical to 030 MMU status reg */
3002 { "acusr", PSR },
3003
3004 /* Suppressed data and address registers. */
3005 { "zd0", ZDATA0 },
3006 { "zd1", ZDATA1 },
3007 { "zd2", ZDATA2 },
3008 { "zd3", ZDATA3 },
3009 { "zd4", ZDATA4 },
3010 { "zd5", ZDATA5 },
3011 { "zd6", ZDATA6 },
3012 { "zd7", ZDATA7 },
3013 { "za0", ZADDR0 },
3014 { "za1", ZADDR1 },
3015 { "za2", ZADDR2 },
3016 { "za3", ZADDR3 },
3017 { "za4", ZADDR4 },
3018 { "za5", ZADDR5 },
3019 { "za6", ZADDR6 },
3020 { "za7", ZADDR7 },
3021
3022 { 0, 0 }
3023 };
3024
3025 void
3026 init_regtable ()
3027 {
3028 int i;
3029 for (i = 0; init_table[i].name; i++)
3030 insert_reg (init_table[i].name, init_table[i].number);
3031 }
3032
3033 static int no_68851, no_68881;
3034
3035 #ifdef OBJ_AOUT
3036 /* a.out machine type. Default to 68020. */
3037 int m68k_aout_machtype = 2;
3038 #endif
3039
3040 void
3041 md_assemble (str)
3042 char *str;
3043 {
3044 const char *er;
3045 short *fromP;
3046 char *toP = NULL;
3047 int m, n = 0;
3048 char *to_beg_P;
3049 int shorts_this_frag;
3050 fixS *fixP;
3051
3052 /* In MRI mode, the instruction and operands are separated by a
3053 space. Anything following the operands is a comment. The label
3054 has already been removed. */
3055 if (flag_mri)
3056 {
3057 char *s;
3058 int fields = 0;
3059 int infield = 0;
3060 int inquote = 0;
3061
3062 for (s = str; *s != '\0'; s++)
3063 {
3064 if ((*s == ' ' || *s == '\t') && ! inquote)
3065 {
3066 if (infield)
3067 {
3068 ++fields;
3069 if (fields >= 2)
3070 {
3071 *s = '\0';
3072 break;
3073 }
3074 infield = 0;
3075 }
3076 }
3077 else
3078 {
3079 if (! infield)
3080 infield = 1;
3081 if (*s == '\'')
3082 inquote = ! inquote;
3083 }
3084 }
3085 }
3086
3087 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3088 m68k_ip (str);
3089 er = the_ins.error;
3090 if (!er)
3091 {
3092 for (n = 0; n < the_ins.numargs; n++)
3093 if (the_ins.operands[n].error)
3094 {
3095 er = the_ins.operands[n].error;
3096 break;
3097 }
3098 }
3099 if (er)
3100 {
3101 as_bad ("%s -- statement `%s' ignored", er, str);
3102 return;
3103 }
3104
3105 if (the_ins.nfrag == 0)
3106 {
3107 /* No frag hacking involved; just put it out */
3108 toP = frag_more (2 * the_ins.numo);
3109 fromP = &the_ins.opcode[0];
3110 for (m = the_ins.numo; m; --m)
3111 {
3112 md_number_to_chars (toP, (long) (*fromP), 2);
3113 toP += 2;
3114 fromP++;
3115 }
3116 /* put out symbol-dependent info */
3117 for (m = 0; m < the_ins.nrel; m++)
3118 {
3119 switch (the_ins.reloc[m].wid)
3120 {
3121 case 'B':
3122 n = 1;
3123 break;
3124 case 'b':
3125 n = 1;
3126 break;
3127 case '3':
3128 n = 2;
3129 break;
3130 case 'w':
3131 n = 2;
3132 break;
3133 case 'l':
3134 n = 4;
3135 break;
3136 default:
3137 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3138 the_ins.reloc[m].wid);
3139 }
3140
3141 fixP = fix_new_exp (frag_now,
3142 ((toP - frag_now->fr_literal)
3143 - the_ins.numo * 2 + the_ins.reloc[m].n),
3144 n,
3145 &the_ins.reloc[m].exp,
3146 the_ins.reloc[m].pcrel,
3147 get_reloc_code (n, the_ins.reloc[m].pcrel,
3148 the_ins.reloc[m].pic_reloc));
3149 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3150 }
3151 return;
3152 }
3153
3154 /* There's some frag hacking */
3155 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3156 {
3157 int wid;
3158
3159 if (n == 0)
3160 wid = 2 * the_ins.fragb[n].fragoff;
3161 else
3162 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3163 toP = frag_more (wid);
3164 to_beg_P = toP;
3165 shorts_this_frag = 0;
3166 for (m = wid / 2; m; --m)
3167 {
3168 md_number_to_chars (toP, (long) (*fromP), 2);
3169 toP += 2;
3170 fromP++;
3171 shorts_this_frag++;
3172 }
3173 for (m = 0; m < the_ins.nrel; m++)
3174 {
3175 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3176 {
3177 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3178 break;
3179 }
3180 wid = the_ins.reloc[m].wid;
3181 if (wid == 0)
3182 continue;
3183 the_ins.reloc[m].wid = 0;
3184 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3185
3186 fixP = fix_new_exp (frag_now,
3187 ((toP - frag_now->fr_literal)
3188 - the_ins.numo * 2 + the_ins.reloc[m].n),
3189 wid,
3190 &the_ins.reloc[m].exp,
3191 the_ins.reloc[m].pcrel,
3192 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3193 the_ins.reloc[m].pic_reloc));
3194 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3195 }
3196 (void) frag_var (rs_machine_dependent, 10, 0,
3197 (relax_substateT) (the_ins.fragb[n].fragty),
3198 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3199 }
3200 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3201 shorts_this_frag = 0;
3202 if (n)
3203 {
3204 toP = frag_more (n * sizeof (short));
3205 while (n--)
3206 {
3207 md_number_to_chars (toP, (long) (*fromP), 2);
3208 toP += 2;
3209 fromP++;
3210 shorts_this_frag++;
3211 }
3212 }
3213 for (m = 0; m < the_ins.nrel; m++)
3214 {
3215 int wid;
3216
3217 wid = the_ins.reloc[m].wid;
3218 if (wid == 0)
3219 continue;
3220 the_ins.reloc[m].wid = 0;
3221 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3222
3223 fixP = fix_new_exp (frag_now,
3224 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3225 - shorts_this_frag * 2),
3226 wid,
3227 &the_ins.reloc[m].exp,
3228 the_ins.reloc[m].pcrel,
3229 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3230 the_ins.reloc[m].pic_reloc));
3231 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3232 }
3233 }
3234
3235 void
3236 md_begin ()
3237 {
3238 /*
3239 * md_begin -- set up hash tables with 68000 instructions.
3240 * similar to what the vax assembler does. ---phr
3241 */
3242 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3243 a copy of it at runtime, adding in the information we want but isn't
3244 there. I think it'd be better to have an awk script hack the table
3245 at compile time. Or even just xstr the table and use it as-is. But
3246 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3247 names. */
3248
3249 register const struct m68k_opcode *ins;
3250 register struct m68k_incant *hack, *slak;
3251 register const char *retval = 0; /* empty string, or error msg text */
3252 register unsigned int i;
3253 register char c;
3254
3255 if (flag_mri)
3256 {
3257 flag_reg_prefix_optional = 1;
3258 m68k_abspcadd = 1;
3259 m68k_rel32 = 0;
3260 }
3261
3262 op_hash = hash_new ();
3263
3264 obstack_begin (&robyn, 4000);
3265 for (i = 0; i < m68k_numopcodes; i++)
3266 {
3267 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3268 do
3269 {
3270 ins = &m68k_opcodes[i];
3271 /* We *could* ignore insns that don't match our arch here
3272 but just leaving them out of the hash. */
3273 slak->m_operands = ins->args;
3274 slak->m_opnum = strlen (slak->m_operands) / 2;
3275 slak->m_arch = ins->arch;
3276 slak->m_opcode = ins->opcode;
3277 /* This is kludgey */
3278 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3279 if (i + 1 != m68k_numopcodes
3280 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3281 {
3282 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3283 i++;
3284 }
3285 else
3286 slak->m_next = 0;
3287 slak = slak->m_next;
3288 }
3289 while (slak);
3290
3291 retval = hash_insert (op_hash, ins->name, (char *) hack);
3292 if (retval)
3293 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3294 }
3295
3296 for (i = 0; i < m68k_numaliases; i++)
3297 {
3298 const char *name = m68k_opcode_aliases[i].primary;
3299 const char *alias = m68k_opcode_aliases[i].alias;
3300 PTR val = hash_find (op_hash, name);
3301 if (!val)
3302 as_fatal ("Internal Error: Can't find %s in hash table", name);
3303 retval = hash_insert (op_hash, alias, val);
3304 if (retval)
3305 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3306 }
3307
3308 /* In MRI mode, all unsized branches are variable sized. Normally,
3309 they are word sized. */
3310 if (flag_mri)
3311 {
3312 static struct m68k_opcode_alias mri_aliases[] =
3313 {
3314 { "bhi", "jhi", },
3315 { "bls", "jls", },
3316 { "bcc", "jcc", },
3317 { "bcs", "jcs", },
3318 { "bne", "jne", },
3319 { "beq", "jeq", },
3320 { "bvc", "jvc", },
3321 { "bvs", "jvs", },
3322 { "bpl", "jpl", },
3323 { "bmi", "jmi", },
3324 { "bge", "jge", },
3325 { "blt", "jlt", },
3326 { "bgt", "jgt", },
3327 { "ble", "jle", },
3328 { "bra", "jra", },
3329 { "bsr", "jbsr", },
3330 };
3331
3332 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3333 {
3334 const char *name = mri_aliases[i].primary;
3335 const char *alias = mri_aliases[i].alias;
3336 PTR val = hash_find (op_hash, name);
3337 if (!val)
3338 as_fatal ("Internal Error: Can't find %s in hash table", name);
3339 retval = hash_jam (op_hash, alias, val);
3340 if (retval)
3341 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3342 }
3343 }
3344
3345 for (i = 0; i < sizeof (mklower_table); i++)
3346 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3347
3348 for (i = 0; i < sizeof (notend_table); i++)
3349 {
3350 notend_table[i] = 0;
3351 alt_notend_table[i] = 0;
3352 }
3353 notend_table[','] = 1;
3354 notend_table['{'] = 1;
3355 notend_table['}'] = 1;
3356 alt_notend_table['a'] = 1;
3357 alt_notend_table['A'] = 1;
3358 alt_notend_table['d'] = 1;
3359 alt_notend_table['D'] = 1;
3360 alt_notend_table['#'] = 1;
3361 alt_notend_table['&'] = 1;
3362 alt_notend_table['f'] = 1;
3363 alt_notend_table['F'] = 1;
3364 #ifdef REGISTER_PREFIX
3365 alt_notend_table[REGISTER_PREFIX] = 1;
3366 #endif
3367
3368 /* We need to put '(' in alt_notend_table to handle
3369 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3370 */
3371 alt_notend_table['('] = 1;
3372
3373 /* We need to put '@' in alt_notend_table to handle
3374 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3375 */
3376 alt_notend_table['@'] = 1;
3377
3378 #ifndef MIT_SYNTAX_ONLY
3379 /* Insert pseudo ops, these have to go into the opcode table since
3380 gas expects pseudo ops to start with a dot */
3381 {
3382 int n = 0;
3383 while (mote_pseudo_table[n].poc_name)
3384 {
3385 hack = (struct m68k_incant *)
3386 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3387 hash_insert (op_hash,
3388 mote_pseudo_table[n].poc_name, (char *) hack);
3389 hack->m_operands = 0;
3390 hack->m_opnum = n;
3391 n++;
3392 }
3393 }
3394 #endif
3395
3396 init_regtable ();
3397
3398 #ifdef OBJ_ELF
3399 record_alignment (text_section, 2);
3400 record_alignment (data_section, 2);
3401 record_alignment (bss_section, 2);
3402 #endif
3403 }
3404
3405 void
3406 m68k_init_after_args ()
3407 {
3408 if (cpu_of_arch (current_architecture) == 0)
3409 {
3410 int i;
3411 const char *default_cpu = TARGET_CPU;
3412
3413 if (*default_cpu == 'm')
3414 default_cpu++;
3415 for (i = 0; i < n_archs; i++)
3416 if (strcasecmp (default_cpu, archs[i].name) == 0)
3417 break;
3418 if (i == n_archs)
3419 {
3420 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3421 current_architecture |= m68020;
3422 }
3423 else
3424 current_architecture |= archs[i].arch;
3425 }
3426 /* Permit m68881 specification with all cpus; those that can't work
3427 with a coprocessor could be doing emulation. */
3428 if (current_architecture & m68851)
3429 {
3430 if (current_architecture & m68040)
3431 {
3432 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3433 }
3434 }
3435 /* What other incompatibilities could we check for? */
3436
3437 /* Toss in some default assumptions about coprocessors. */
3438 if (!no_68881
3439 && (cpu_of_arch (current_architecture)
3440 /* Can CPU32 have a 68881 coprocessor?? */
3441 & (m68020 | m68030 | cpu32)))
3442 {
3443 current_architecture |= m68881;
3444 }
3445 if (!no_68851
3446 && (cpu_of_arch (current_architecture) & m68020up) != 0
3447 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3448 {
3449 current_architecture |= m68851;
3450 }
3451 if (no_68881 && (current_architecture & m68881))
3452 as_bad ("options for 68881 and no-68881 both given");
3453 if (no_68851 && (current_architecture & m68851))
3454 as_bad ("options for 68851 and no-68851 both given");
3455
3456 #ifdef OBJ_AOUT
3457 /* Work out the magic number. This isn't very general. */
3458 if (current_architecture & m68000)
3459 m68k_aout_machtype = 0;
3460 else if (current_architecture & m68010)
3461 m68k_aout_machtype = 1;
3462 else if (current_architecture & m68020)
3463 m68k_aout_machtype = 2;
3464 else
3465 m68k_aout_machtype = 2;
3466 #endif
3467
3468 /* Note which set of "movec" control registers is available. */
3469 switch (cpu_of_arch (current_architecture))
3470 {
3471 case m68000:
3472 control_regs = m68000_control_regs;
3473 break;
3474 case m68010:
3475 control_regs = m68010_control_regs;
3476 break;
3477 case m68020:
3478 case m68030:
3479 control_regs = m68020_control_regs;
3480 break;
3481 case m68040:
3482 control_regs = m68040_control_regs;
3483 break;
3484 case m68060:
3485 control_regs = m68060_control_regs;
3486 break;
3487 case cpu32:
3488 control_regs = cpu32_control_regs;
3489 break;
3490 default:
3491 abort ();
3492 }
3493
3494 if (cpu_of_arch (current_architecture) < m68020)
3495 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3496 }
3497
3498 /* This is called if we go in or out of MRI mode because of the .mri
3499 pseudo-op. */
3500
3501 void
3502 m68k_mri_mode_change (on)
3503 int on;
3504 {
3505 if (on)
3506 {
3507 if (! flag_reg_prefix_optional)
3508 {
3509 flag_reg_prefix_optional = 1;
3510 #ifdef REGISTER_PREFIX
3511 init_regtable ();
3512 #endif
3513 }
3514 m68k_abspcadd = 1;
3515 m68k_rel32 = 0;
3516 }
3517 else
3518 {
3519 if (! reg_prefix_optional_seen)
3520 {
3521 #ifdef REGISTER_PREFIX_OPTIONAL
3522 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3523 #else
3524 flag_reg_prefix_optional = 0;
3525 #endif
3526 #ifdef REGISTER_PREFIX
3527 init_regtable ();
3528 #endif
3529 }
3530 m68k_abspcadd = 0;
3531 m68k_rel32 = 1;
3532 }
3533 }
3534
3535 /* Equal to MAX_PRECISION in atof-ieee.c */
3536 #define MAX_LITTLENUMS 6
3537
3538 /* Turn a string in input_line_pointer into a floating point constant
3539 of type type, and store the appropriate bytes in *litP. The number
3540 of LITTLENUMS emitted is stored in *sizeP . An error message is
3541 returned, or NULL on OK. */
3542
3543 char *
3544 md_atof (type, litP, sizeP)
3545 char type;
3546 char *litP;
3547 int *sizeP;
3548 {
3549 int prec;
3550 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3551 LITTLENUM_TYPE *wordP;
3552 char *t;
3553 char *atof_ieee ();
3554
3555 switch (type)
3556 {
3557 case 'f':
3558 case 'F':
3559 case 's':
3560 case 'S':
3561 prec = 2;
3562 break;
3563
3564 case 'd':
3565 case 'D':
3566 case 'r':
3567 case 'R':
3568 prec = 4;
3569 break;
3570
3571 case 'x':
3572 case 'X':
3573 prec = 6;
3574 break;
3575
3576 case 'p':
3577 case 'P':
3578 prec = 6;
3579 break;
3580
3581 default:
3582 *sizeP = 0;
3583 return "Bad call to MD_ATOF()";
3584 }
3585 t = atof_ieee (input_line_pointer, type, words);
3586 if (t)
3587 input_line_pointer = t;
3588
3589 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3590 for (wordP = words; prec--;)
3591 {
3592 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3593 litP += sizeof (LITTLENUM_TYPE);
3594 }
3595 return 0;
3596 }
3597
3598 void
3599 md_number_to_chars (buf, val, n)
3600 char *buf;
3601 valueT val;
3602 int n;
3603 {
3604 number_to_chars_bigendian (buf, val, n);
3605 }
3606
3607 static void
3608 md_apply_fix_2 (fixP, val)
3609 fixS *fixP;
3610 offsetT val;
3611 {
3612 addressT upper_limit;
3613 offsetT lower_limit;
3614
3615 /* This is unnecessary but it convinces the native rs6000 compiler
3616 to generate the code we want. */
3617 char *buf = fixP->fx_frag->fr_literal;
3618 buf += fixP->fx_where;
3619 /* end ibm compiler workaround */
3620
3621 if (val & 0x80000000)
3622 val |= ~(addressT)0x7fffffff;
3623 else
3624 val &= 0x7fffffff;
3625
3626 #ifdef OBJ_ELF
3627 if (fixP->fx_addsy)
3628 {
3629 memset (buf, 0, fixP->fx_size);
3630 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3631 return;
3632 }
3633 #endif
3634
3635 switch (fixP->fx_size)
3636 {
3637 /* The cast to offsetT below are necessary to make code correct for
3638 machines where ints are smaller than offsetT */
3639 case 1:
3640 *buf++ = val;
3641 upper_limit = 0x7f;
3642 lower_limit = - (offsetT) 0x80;
3643 break;
3644 case 2:
3645 *buf++ = (val >> 8);
3646 *buf++ = val;
3647 upper_limit = 0x7fff;
3648 lower_limit = - (offsetT) 0x8000;
3649 break;
3650 case 4:
3651 *buf++ = (val >> 24);
3652 *buf++ = (val >> 16);
3653 *buf++ = (val >> 8);
3654 *buf++ = val;
3655 upper_limit = 0x7fffffff;
3656 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3657 break;
3658 default:
3659 BAD_CASE (fixP->fx_size);
3660 }
3661
3662 /* Fix up a negative reloc. */
3663 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3664 {
3665 fixP->fx_addsy = fixP->fx_subsy;
3666 fixP->fx_subsy = NULL;
3667 fixP->fx_tcbit = 1;
3668 }
3669
3670 /* For non-pc-relative values, it's conceivable we might get something
3671 like "0xff" for a byte field. So extend the upper part of the range
3672 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3673 so that we can do any range checking at all. */
3674 if (!fixP->fx_pcrel)
3675 upper_limit = upper_limit * 2 + 1;
3676
3677 if ((addressT) val > upper_limit
3678 && (val > 0 || val < lower_limit))
3679 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3680
3681 /* A one byte PC-relative reloc means a short branch. We can't use
3682 a short branch with a value of 0 or -1, because those indicate
3683 different opcodes (branches with longer offsets). */
3684 if (fixP->fx_pcrel
3685 && fixP->fx_size == 1
3686 && (fixP->fx_addsy == NULL
3687 || S_IS_DEFINED (fixP->fx_addsy))
3688 && (val == 0 || val == -1))
3689 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3690 }
3691
3692 #ifdef BFD_ASSEMBLER
3693 int
3694 md_apply_fix (fixP, valp)
3695 fixS *fixP;
3696 valueT *valp;
3697 {
3698 md_apply_fix_2 (fixP, (addressT) *valp);
3699 return 1;
3700 }
3701 #else
3702 void md_apply_fix (fixP, val)
3703 fixS *fixP;
3704 long val;
3705 {
3706 md_apply_fix_2 (fixP, (addressT) val);
3707 }
3708 #endif
3709
3710 /* *fragP has been relaxed to its final size, and now needs to have
3711 the bytes inside it modified to conform to the new size There is UGLY
3712 MAGIC here. ..
3713 */
3714 void
3715 md_convert_frag_1 (fragP)
3716 register fragS *fragP;
3717 {
3718 long disp;
3719 long ext = 0;
3720 fixS *fixP;
3721
3722 /* Address in object code of the displacement. */
3723 register int object_address = fragP->fr_fix + fragP->fr_address;
3724
3725 /* Address in gas core of the place to store the displacement. */
3726 /* This convinces the native rs6000 compiler to generate the code we
3727 want. */
3728 register char *buffer_address = fragP->fr_literal;
3729 buffer_address += fragP->fr_fix;
3730 /* end ibm compiler workaround */
3731
3732 /* The displacement of the address, from current location. */
3733 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3734 disp = (disp + fragP->fr_offset) - object_address;
3735
3736 #ifdef BFD_ASSEMBLER
3737 disp += fragP->fr_symbol->sy_frag->fr_address;
3738 #endif
3739
3740 switch (fragP->fr_subtype)
3741 {
3742 case TAB (BCC68000, BYTE):
3743 case TAB (ABRANCH, BYTE):
3744 know (issbyte (disp));
3745 if (disp == 0)
3746 as_bad ("short branch with zero offset: use :w");
3747 fragP->fr_opcode[1] = disp;
3748 ext = 0;
3749 break;
3750 case TAB (DBCC, SHORT):
3751 know (issword (disp));
3752 ext = 2;
3753 break;
3754 case TAB (BCC68000, SHORT):
3755 case TAB (ABRANCH, SHORT):
3756 know (issword (disp));
3757 fragP->fr_opcode[1] = 0x00;
3758 ext = 2;
3759 break;
3760 case TAB (ABRANCH, LONG):
3761 if (cpu_of_arch (current_architecture) < m68020)
3762 {
3763 if (fragP->fr_opcode[0] == 0x61)
3764 /* BSR */
3765 {
3766 fragP->fr_opcode[0] = 0x4E;
3767 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3768
3769 fix_new (fragP,
3770 fragP->fr_fix,
3771 4,
3772 fragP->fr_symbol,
3773 fragP->fr_offset,
3774 0,
3775 NO_RELOC);
3776
3777 fragP->fr_fix += 4;
3778 ext = 0;
3779 }
3780 /* BRA */
3781 else if (fragP->fr_opcode[0] == 0x60)
3782 {
3783 fragP->fr_opcode[0] = 0x4E;
3784 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3785 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3786 fragP->fr_offset, 0, NO_RELOC);
3787 fragP->fr_fix += 4;
3788 ext = 0;
3789 }
3790 else
3791 {
3792 as_bad ("Long branch offset not supported.");
3793 }
3794 }
3795 else
3796 {
3797 fragP->fr_opcode[1] = (char) 0xff;
3798 ext = 4;
3799 }
3800 break;
3801 case TAB (BCC68000, LONG):
3802 /* only Bcc 68000 instructions can come here */
3803 /* change bcc into b!cc/jmp absl long */
3804 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3805 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3806
3807 /* JF: these used to be fr_opcode[2,3], but they may be in a
3808 different frag, in which case refering to them is a no-no.
3809 Only fr_opcode[0,1] are guaranteed to work. */
3810 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3811 *buffer_address++ = (char) 0xf9;
3812 fragP->fr_fix += 2; /* account for jmp instruction */
3813 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3814 fragP->fr_offset, 0, NO_RELOC);
3815 fragP->fr_fix += 4;
3816 ext = 0;
3817 break;
3818 case TAB (DBCC, LONG):
3819 /* only DBcc 68000 instructions can come here */
3820 /* change dbcc into dbcc/jmp absl long */
3821 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3822 *buffer_address++ = 0x00; /* branch offset = 4 */
3823 *buffer_address++ = 0x04;
3824 *buffer_address++ = 0x60; /* put in bra pc+6 */
3825 *buffer_address++ = 0x06;
3826 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3827 *buffer_address++ = (char) 0xf9;
3828
3829 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3830 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3831 fragP->fr_offset, 0, NO_RELOC);
3832 fragP->fr_fix += 4;
3833 ext = 0;
3834 break;
3835 case TAB (FBRANCH, SHORT):
3836 know ((fragP->fr_opcode[1] & 0x40) == 0);
3837 ext = 2;
3838 break;
3839 case TAB (FBRANCH, LONG):
3840 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3841 ext = 4;
3842 break;
3843 case TAB (PCREL, SHORT):
3844 ext = 2;
3845 break;
3846 case TAB (PCREL, LONG):
3847 /* The thing to do here is force it to ABSOLUTE LONG, since
3848 PCREL is really trying to shorten an ABSOLUTE address anyway */
3849 /* JF FOO This code has not been tested */
3850 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3851 0, NO_RELOC);
3852 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3853 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3854 (unsigned) fragP->fr_opcode[0],
3855 (unsigned long) fragP->fr_address);
3856 fragP->fr_opcode[1] &= ~0x3F;
3857 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3858 fragP->fr_fix += 4;
3859 ext = 0;
3860 break;
3861 case TAB (PCLEA, SHORT):
3862 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3863 fragP->fr_offset, 1, NO_RELOC);
3864 fragP->fr_opcode[1] &= ~0x3F;
3865 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3866 ext = 2;
3867 break;
3868 case TAB (PCLEA, LONG):
3869 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3870 fragP->fr_offset, 1, NO_RELOC);
3871 fixP->fx_pcrel_adjust = 2;
3872 /* Already set to mode 7.3; this indicates: PC indirect with
3873 suppressed index, 32-bit displacement. */
3874 *buffer_address++ = 0x01;
3875 *buffer_address++ = 0x70;
3876 fragP->fr_fix += 2;
3877 ext = 4;
3878 break;
3879
3880 case TAB (PCINDEX, BYTE):
3881 disp += 2;
3882 if (!issbyte (disp))
3883 {
3884 as_bad ("displacement doesn't fit in one byte");
3885 disp = 0;
3886 }
3887 assert (fragP->fr_fix >= 2);
3888 buffer_address[-2] &= ~1;
3889 buffer_address[-1] = disp;
3890 ext = 0;
3891 break;
3892 case TAB (PCINDEX, SHORT):
3893 disp += 2;
3894 assert (issword (disp));
3895 assert (fragP->fr_fix >= 2);
3896 buffer_address[-2] |= 0x1;
3897 buffer_address[-1] = 0x20;
3898 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3899 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3900 NO_RELOC);
3901 fixP->fx_pcrel_adjust = 2;
3902 ext = 2;
3903 break;
3904 case TAB (PCINDEX, LONG):
3905 disp += 2;
3906 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3907 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3908 NO_RELOC);
3909 fixP->fx_pcrel_adjust = 2;
3910 assert (fragP->fr_fix >= 2);
3911 buffer_address[-2] |= 0x1;
3912 buffer_address[-1] = 0x30;
3913 ext = 4;
3914 break;
3915 }
3916
3917 if (ext)
3918 {
3919 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3920 fragP->fr_fix += ext;
3921 }
3922 }
3923
3924 #ifndef BFD_ASSEMBLER
3925
3926 void
3927 md_convert_frag (headers, sec, fragP)
3928 object_headers *headers;
3929 segT sec;
3930 fragS *fragP;
3931 {
3932 md_convert_frag_1 (fragP);
3933 }
3934
3935 #else
3936
3937 void
3938 md_convert_frag (abfd, sec, fragP)
3939 bfd *abfd;
3940 segT sec;
3941 fragS *fragP;
3942 {
3943 md_convert_frag_1 (fragP);
3944 }
3945 #endif
3946
3947 /* Force truly undefined symbols to their maximum size, and generally set up
3948 the frag list to be relaxed
3949 */
3950 int
3951 md_estimate_size_before_relax (fragP, segment)
3952 register fragS *fragP;
3953 segT segment;
3954 {
3955 int old_fix;
3956 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3957
3958 old_fix = fragP->fr_fix;
3959
3960 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3961 switch (fragP->fr_subtype)
3962 {
3963
3964 case TAB (ABRANCH, SZ_UNDEF):
3965 {
3966 if ((fragP->fr_symbol != NULL) /* Not absolute */
3967 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3968 {
3969 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3970 break;
3971 }
3972 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3973 {
3974 /* On 68000, or for absolute value, switch to abs long */
3975 /* FIXME, we should check abs val, pick short or long */
3976 if (fragP->fr_opcode[0] == 0x61)
3977 {
3978 fragP->fr_opcode[0] = 0x4E;
3979 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3980 fix_new (fragP, fragP->fr_fix, 4,
3981 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3982 fragP->fr_fix += 4;
3983 frag_wane (fragP);
3984 }
3985 else if (fragP->fr_opcode[0] == 0x60)
3986 {
3987 fragP->fr_opcode[0] = 0x4E;
3988 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3989 fix_new (fragP, fragP->fr_fix, 4,
3990 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3991 fragP->fr_fix += 4;
3992 frag_wane (fragP);
3993 }
3994 else
3995 {
3996 as_warn ("Long branch offset to extern symbol not supported.");
3997 }
3998 }
3999 else
4000 { /* Symbol is still undefined. Make it simple */
4001 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4002 fragP->fr_offset, 1, NO_RELOC);
4003 fragP->fr_fix += 4;
4004 fragP->fr_opcode[1] = (char) 0xff;
4005 frag_wane (fragP);
4006 break;
4007 }
4008
4009 break;
4010 } /* case TAB(ABRANCH,SZ_UNDEF) */
4011
4012 case TAB (FBRANCH, SZ_UNDEF):
4013 {
4014 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4015 {
4016 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4017 fragP->fr_var += 2;
4018 }
4019 else
4020 {
4021 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4022 fragP->fr_offset, 1, NO_RELOC);
4023 fragP->fr_fix += 4;
4024 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4025 frag_wane (fragP);
4026 }
4027 break;
4028 } /* TAB(FBRANCH,SZ_UNDEF) */
4029
4030 case TAB (PCREL, SZ_UNDEF):
4031 {
4032 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4033 || flag_short_refs
4034 || cpu_of_arch (current_architecture) < m68020)
4035 {
4036 fragP->fr_subtype = TAB (PCREL, SHORT);
4037 fragP->fr_var += 2;
4038 }
4039 else
4040 {
4041 fragP->fr_subtype = TAB (PCREL, LONG);
4042 fragP->fr_var += 4;
4043 }
4044 break;
4045 } /* TAB(PCREL,SZ_UNDEF) */
4046
4047 case TAB (BCC68000, SZ_UNDEF):
4048 {
4049 if ((fragP->fr_symbol != NULL)
4050 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4051 {
4052 fragP->fr_subtype = TAB (BCC68000, BYTE);
4053 break;
4054 }
4055 /* only Bcc 68000 instructions can come here */
4056 /* change bcc into b!cc/jmp absl long */
4057 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4058 if (flag_short_refs)
4059 {
4060 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4061 /* JF: these were fr_opcode[2,3] */
4062 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4063 buffer_address[1] = (char) 0xf8;
4064 fragP->fr_fix += 2; /* account for jmp instruction */
4065 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4066 fragP->fr_offset, 0, NO_RELOC);
4067 fragP->fr_fix += 2;
4068 }
4069 else
4070 {
4071 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4072 /* JF: these were fr_opcode[2,3] */
4073 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4074 buffer_address[1] = (char) 0xf9;
4075 fragP->fr_fix += 2; /* account for jmp instruction */
4076 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4077 fragP->fr_offset, 0, NO_RELOC);
4078 fragP->fr_fix += 4;
4079 }
4080 frag_wane (fragP);
4081 break;
4082 } /* case TAB(BCC68000,SZ_UNDEF) */
4083
4084 case TAB (DBCC, SZ_UNDEF):
4085 {
4086 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4087 {
4088 fragP->fr_subtype = TAB (DBCC, SHORT);
4089 fragP->fr_var += 2;
4090 break;
4091 }
4092 /* only DBcc 68000 instructions can come here */
4093 /* change dbcc into dbcc/jmp absl long */
4094 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4095 buffer_address[0] = 0x00; /* branch offset = 4 */
4096 buffer_address[1] = 0x04;
4097 buffer_address[2] = 0x60; /* put in bra pc + ... */
4098
4099 if (flag_short_refs)
4100 {
4101 /* JF: these were fr_opcode[5-7] */
4102 buffer_address[3] = 0x04; /* plus 4 */
4103 buffer_address[4] = 0x4e; /* Put in Jump Word */
4104 buffer_address[5] = (char) 0xf8;
4105 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4106 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4107 fragP->fr_offset, 0, NO_RELOC);
4108 fragP->fr_fix += 2;
4109 }
4110 else
4111 {
4112 /* JF: these were fr_opcode[5-7] */
4113 buffer_address[3] = 0x06; /* Plus 6 */
4114 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4115 buffer_address[5] = (char) 0xf9;
4116 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4117 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4118 fragP->fr_offset, 0, NO_RELOC);
4119 fragP->fr_fix += 4;
4120 }
4121
4122 frag_wane (fragP);
4123 break;
4124 } /* case TAB(DBCC,SZ_UNDEF) */
4125
4126 case TAB (PCLEA, SZ_UNDEF):
4127 {
4128 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4129 || flag_short_refs
4130 || cpu_of_arch (current_architecture) < m68020)
4131 {
4132 fragP->fr_subtype = TAB (PCLEA, SHORT);
4133 fragP->fr_var += 2;
4134 }
4135 else
4136 {
4137 fragP->fr_subtype = TAB (PCLEA, LONG);
4138 fragP->fr_var += 6;
4139 }
4140 break;
4141 } /* TAB(PCLEA,SZ_UNDEF) */
4142
4143 case TAB (PCINDEX, SZ_UNDEF):
4144 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4145 || cpu_of_arch (current_architecture) < m68020)
4146 {
4147 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4148 }
4149 else
4150 {
4151 fragP->fr_subtype = TAB (PCINDEX, LONG);
4152 fragP->fr_var += 4;
4153 }
4154 break;
4155
4156 default:
4157 break;
4158 }
4159
4160 /* now that SZ_UNDEF are taken care of, check others */
4161 switch (fragP->fr_subtype)
4162 {
4163 case TAB (BCC68000, BYTE):
4164 case TAB (ABRANCH, BYTE):
4165 /* We can't do a short jump to the next instruction, so in that
4166 case we force word mode. At this point S_GET_VALUE should
4167 return the offset of the symbol within its frag. If the
4168 symbol is at the start of a frag, and it is the next frag
4169 with any data in it (usually this is just the next frag, but
4170 assembler listings may introduce empty frags), we must use
4171 word mode. */
4172 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4173 {
4174 fragS *l;
4175
4176 for (l = fragP->fr_next;
4177 l != fragP->fr_symbol->sy_frag;
4178 l = l->fr_next)
4179 if (l->fr_fix + l->fr_var != 0)
4180 break;
4181 if (l == fragP->fr_symbol->sy_frag)
4182 {
4183 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4184 fragP->fr_var += 2;
4185 }
4186 }
4187 break;
4188 default:
4189 break;
4190 }
4191 return fragP->fr_var + fragP->fr_fix - old_fix;
4192 }
4193
4194 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4195 /* the bit-field entries in the relocation_info struct plays hell
4196 with the byte-order problems of cross-assembly. So as a hack,
4197 I added this mach. dependent ri twiddler. Ugly, but it gets
4198 you there. -KWK */
4199 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4200 are symbolnum, most sig. byte first. Last byte is broken up with
4201 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4202 nibble as nuthin. (on Sun 3 at least) */
4203 /* Translate the internal relocation information into target-specific
4204 format. */
4205 #ifdef comment
4206 void
4207 md_ri_to_chars (the_bytes, ri)
4208 char *the_bytes;
4209 struct reloc_info_generic *ri;
4210 {
4211 /* this is easy */
4212 md_number_to_chars (the_bytes, ri->r_address, 4);
4213 /* now the fun stuff */
4214 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4215 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4216 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4217 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4218 ((ri->r_extern << 4) & 0x10));
4219 }
4220
4221 #endif /* comment */
4222
4223 #ifndef BFD_ASSEMBLER
4224 void
4225 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4226 char *where;
4227 fixS *fixP;
4228 relax_addressT segment_address_in_file;
4229 {
4230 /*
4231 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4232 * Out: GNU LD relocation length code: 0, 1, or 2.
4233 */
4234
4235 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4236 long r_symbolnum;
4237
4238 know (fixP->fx_addsy != NULL);
4239
4240 md_number_to_chars (where,
4241 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4242 4);
4243
4244 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4245 ? S_GET_TYPE (fixP->fx_addsy)
4246 : fixP->fx_addsy->sy_number);
4247
4248 where[4] = (r_symbolnum >> 16) & 0x0ff;
4249 where[5] = (r_symbolnum >> 8) & 0x0ff;
4250 where[6] = r_symbolnum & 0x0ff;
4251 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4252 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4253 }
4254 #endif
4255
4256 #endif /* OBJ_AOUT or OBJ_BOUT */
4257
4258 #ifndef WORKING_DOT_WORD
4259 CONST int md_short_jump_size = 4;
4260 CONST int md_long_jump_size = 6;
4261
4262 void
4263 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4264 char *ptr;
4265 addressT from_addr, to_addr;
4266 fragS *frag;
4267 symbolS *to_symbol;
4268 {
4269 valueT offset;
4270
4271 offset = to_addr - (from_addr + 2);
4272
4273 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4274 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4275 }
4276
4277 void
4278 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4279 char *ptr;
4280 addressT from_addr, to_addr;
4281 fragS *frag;
4282 symbolS *to_symbol;
4283 {
4284 valueT offset;
4285
4286 if (cpu_of_arch (current_architecture) < m68020)
4287 {
4288 offset = to_addr - S_GET_VALUE (to_symbol);
4289 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4290 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4291 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4292 0, NO_RELOC);
4293 }
4294 else
4295 {
4296 offset = to_addr - (from_addr + 2);
4297 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4298 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4299 }
4300 }
4301
4302 #endif
4303
4304 /* Different values of OK tell what its OK to return. Things that
4305 aren't OK are an error (what a shock, no?)
4306
4307 0: Everything is OK
4308 10: Absolute 1:8 only
4309 20: Absolute 0:7 only
4310 30: absolute 0:15 only
4311 40: Absolute 0:31 only
4312 50: absolute 0:127 only
4313 55: absolute -64:63 only
4314 60: absolute -128:127 only
4315 70: absolute 0:4095 only
4316 80: No bignums
4317
4318 */
4319
4320 static int
4321 get_num (exp, ok)
4322 struct m68k_exp *exp;
4323 int ok;
4324 {
4325 if (exp->exp.X_op == O_absent)
4326 {
4327 /* Do the same thing the VAX asm does */
4328 op (exp) = O_constant;
4329 adds (exp) = 0;
4330 subs (exp) = 0;
4331 offs (exp) = 0;
4332 if (ok == 10)
4333 {
4334 as_warn ("expression out of range: defaulting to 1");
4335 offs (exp) = 1;
4336 }
4337 }
4338 else if (exp->exp.X_op == O_constant)
4339 {
4340 switch (ok)
4341 {
4342 case 10:
4343 if (offs (exp) < 1 || offs (exp) > 8)
4344 {
4345 as_warn ("expression out of range: defaulting to 1");
4346 offs (exp) = 1;
4347 }
4348 break;
4349 case 20:
4350 if (offs (exp) < 0 || offs (exp) > 7)
4351 goto outrange;
4352 break;
4353 case 30:
4354 if (offs (exp) < 0 || offs (exp) > 15)
4355 goto outrange;
4356 break;
4357 case 40:
4358 if (offs (exp) < 0 || offs (exp) > 32)
4359 goto outrange;
4360 break;
4361 case 50:
4362 if (offs (exp) < 0 || offs (exp) > 127)
4363 goto outrange;
4364 break;
4365 case 55:
4366 if (offs (exp) < -64 || offs (exp) > 63)
4367 goto outrange;
4368 break;
4369 case 60:
4370 if (offs (exp) < -128 || offs (exp) > 127)
4371 goto outrange;
4372 break;
4373 case 70:
4374 if (offs (exp) < 0 || offs (exp) > 4095)
4375 {
4376 outrange:
4377 as_warn ("expression out of range: defaulting to 0");
4378 offs (exp) = 0;
4379 }
4380 break;
4381 default:
4382 break;
4383 }
4384 }
4385 else if (exp->exp.X_op == O_big)
4386 {
4387 if (offs (exp) <= 0 /* flonum */
4388 && (ok == 80 /* no bignums */
4389 || (ok > 10 /* small-int ranges including 0 ok */
4390 /* If we have a flonum zero, a zero integer should
4391 do as well (e.g., in moveq). */
4392 && generic_floating_point_number.exponent == 0
4393 && generic_floating_point_number.low[0] == 0)))
4394 {
4395 /* HACK! Turn it into a long */
4396 LITTLENUM_TYPE words[6];
4397
4398 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4399 op (exp) = O_constant;
4400 adds (exp) = 0;
4401 subs (exp) = 0;
4402 offs (exp) = words[1] | (words[0] << 16);
4403 }
4404 else if (ok != 0)
4405 {
4406 op (exp) = O_constant;
4407 adds (exp) = 0;
4408 subs (exp) = 0;
4409 offs (exp) = (ok == 10) ? 1 : 0;
4410 as_warn ("Can't deal with expression; defaulting to %ld",
4411 offs (exp));
4412 }
4413 }
4414 else
4415 {
4416 if (ok >= 10 && ok <= 70)
4417 {
4418 op (exp) = O_constant;
4419 adds (exp) = 0;
4420 subs (exp) = 0;
4421 offs (exp) = (ok == 10) ? 1 : 0;
4422 as_warn ("Can't deal with expression; defaulting to %ld",
4423 offs (exp));
4424 }
4425 }
4426
4427 if (exp->size != SIZE_UNSPEC)
4428 {
4429 switch (exp->size)
4430 {
4431 case SIZE_UNSPEC:
4432 case SIZE_LONG:
4433 break;
4434 case SIZE_BYTE:
4435 if (!isbyte (offs (exp)))
4436 as_warn ("expression doesn't fit in BYTE");
4437 break;
4438 case SIZE_WORD:
4439 if (!isword (offs (exp)))
4440 as_warn ("expression doesn't fit in WORD");
4441 break;
4442 }
4443 }
4444
4445 return offs (exp);
4446 }
4447
4448 /* These are the back-ends for the various machine dependent pseudo-ops. */
4449 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4450
4451 static void
4452 s_data1 (ignore)
4453 int ignore;
4454 {
4455 subseg_set (data_section, 1);
4456 demand_empty_rest_of_line ();
4457 }
4458
4459 static void
4460 s_data2 (ignore)
4461 int ignore;
4462 {
4463 subseg_set (data_section, 2);
4464 demand_empty_rest_of_line ();
4465 }
4466
4467 static void
4468 s_bss (ignore)
4469 int ignore;
4470 {
4471 /* We don't support putting frags in the BSS segment, we fake it
4472 by marking in_bss, then looking at s_skip for clues. */
4473
4474 subseg_set (bss_section, 0);
4475 demand_empty_rest_of_line ();
4476 }
4477
4478 static void
4479 s_even (ignore)
4480 int ignore;
4481 {
4482 register int temp;
4483 register long temp_fill;
4484
4485 temp = 1; /* JF should be 2? */
4486 temp_fill = get_absolute_expression ();
4487 if (!need_pass_2) /* Never make frag if expect extra pass. */
4488 frag_align (temp, (int) temp_fill);
4489 demand_empty_rest_of_line ();
4490 }
4491
4492 static void
4493 s_proc (ignore)
4494 int ignore;
4495 {
4496 demand_empty_rest_of_line ();
4497 }
4498 \f
4499 /* Pseudo-ops handled for MRI compatibility. */
4500
4501 /* Handle an MRI style chip specification. */
4502
4503 static void
4504 mri_chip ()
4505 {
4506 char *s;
4507 char c;
4508 int i;
4509
4510 s = input_line_pointer;
4511 c = get_symbol_end ();
4512 for (i = 0; i < n_archs; i++)
4513 if (strcasecmp (s, archs[i].name) == 0)
4514 break;
4515 if (i >= n_archs)
4516 {
4517 as_bad ("%s: unrecognized processor name", s);
4518 *input_line_pointer = c;
4519 ignore_rest_of_line ();
4520 return;
4521 }
4522 *input_line_pointer = c;
4523
4524 if (*input_line_pointer == '/')
4525 current_architecture = 0;
4526 else
4527 current_architecture &= m68881 | m68851;
4528 current_architecture |= archs[i].arch;
4529
4530 while (*input_line_pointer == '/')
4531 {
4532 ++input_line_pointer;
4533 s = input_line_pointer;
4534 c = get_symbol_end ();
4535 if (strcmp (s, "68881") == 0)
4536 current_architecture |= m68881;
4537 else if (strcmp (s, "68851") == 0)
4538 current_architecture |= m68851;
4539 *input_line_pointer = c;
4540 }
4541 }
4542
4543 /* The MRI CHIP pseudo-op. */
4544
4545 static void
4546 s_chip (ignore)
4547 int ignore;
4548 {
4549 char *stop = NULL;
4550 char stopc;
4551
4552 if (flag_mri)
4553 stop = mri_comment_field (&stopc);
4554 mri_chip ();
4555 if (flag_mri)
4556 mri_comment_end (stop, stopc);
4557 demand_empty_rest_of_line ();
4558 }
4559
4560 /* The MRI FOPT pseudo-op. */
4561
4562 static void
4563 s_fopt (ignore)
4564 int ignore;
4565 {
4566 SKIP_WHITESPACE ();
4567
4568 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4569 {
4570 int temp;
4571
4572 input_line_pointer += 3;
4573 temp = get_absolute_expression ();
4574 if (temp < 0 || temp > 7)
4575 as_bad ("bad coprocessor id");
4576 else
4577 m68k_float_copnum = COP0 + temp;
4578 }
4579 else
4580 {
4581 as_bad ("unrecognized fopt option");
4582 ignore_rest_of_line ();
4583 return;
4584 }
4585
4586 demand_empty_rest_of_line ();
4587 }
4588
4589 /* The structure used to handle the MRI OPT pseudo-op. */
4590
4591 struct opt_action
4592 {
4593 /* The name of the option. */
4594 const char *name;
4595
4596 /* If this is not NULL, just call this function. The first argument
4597 is the ARG field of this structure, the second argument is
4598 whether the option was negated. */
4599 void (*pfn) PARAMS ((int arg, int on));
4600
4601 /* If this is not NULL, and the PFN field is NULL, set the variable
4602 this points to. Set it to the ARG field if the option was not
4603 negated, and the NOTARG field otherwise. */
4604 int *pvar;
4605
4606 /* The value to pass to PFN or to assign to *PVAR. */
4607 int arg;
4608
4609 /* The value to assign to *PVAR if the option is negated. If PFN is
4610 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4611 the option may not be negated. */
4612 int notarg;
4613 };
4614
4615 /* The table used to handle the MRI OPT pseudo-op. */
4616
4617 static void skip_to_comma PARAMS ((int, int));
4618 static void opt_nest PARAMS ((int, int));
4619 static void opt_chip PARAMS ((int, int));
4620 static void opt_list PARAMS ((int, int));
4621 static void opt_list_symbols PARAMS ((int, int));
4622
4623 static const struct opt_action opt_table[] =
4624 {
4625 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4626
4627 /* We do relaxing, so there is little use for these options. */
4628 { "b", 0, 0, 0, 0 },
4629 { "brs", 0, 0, 0, 0 },
4630 { "brb", 0, 0, 0, 0 },
4631 { "brl", 0, 0, 0, 0 },
4632 { "brw", 0, 0, 0, 0 },
4633
4634 { "c", 0, 0, 0, 0 },
4635 { "cex", 0, 0, 0, 0 },
4636 { "case", 0, &symbols_case_sensitive, 1, 0 },
4637 { "cl", 0, 0, 0, 0 },
4638 { "cre", 0, 0, 0, 0 },
4639 { "d", 0, &flag_keep_locals, 1, 0 },
4640 { "e", 0, 0, 0, 0 },
4641 { "f", 0, &flag_short_refs, 1, 0 },
4642 { "frs", 0, &flag_short_refs, 1, 0 },
4643 { "frl", 0, &flag_short_refs, 0, 1 },
4644 { "g", 0, 0, 0, 0 },
4645 { "i", 0, 0, 0, 0 },
4646 { "m", 0, 0, 0, 0 },
4647 { "mex", 0, 0, 0, 0 },
4648 { "mc", 0, 0, 0, 0 },
4649 { "md", 0, 0, 0, 0 },
4650 { "nest", opt_nest, 0, 0, 0 },
4651 { "next", skip_to_comma, 0, 0, 0 },
4652 { "o", 0, 0, 0, 0 },
4653 { "old", 0, 0, 0, 0 },
4654 { "op", skip_to_comma, 0, 0, 0 },
4655 { "pco", 0, 0, 0, 0 },
4656 { "p", opt_chip, 0, 0, 0 },
4657 { "pcr", 0, 0, 0, 0 },
4658 { "pcs", 0, 0, 0, 0 },
4659 { "r", 0, 0, 0, 0 },
4660 { "quick", 0, &m68k_quick, 1, 0 },
4661 { "rel32", 0, &m68k_rel32, 1, 0 },
4662 { "s", opt_list, 0, 0, 0 },
4663 { "t", opt_list_symbols, 0, 0, 0 },
4664 { "w", 0, &flag_no_warnings, 0, 1 },
4665 { "x", 0, 0, 0, 0 }
4666 };
4667
4668 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4669
4670 /* The MRI OPT pseudo-op. */
4671
4672 static void
4673 s_opt (ignore)
4674 int ignore;
4675 {
4676 do
4677 {
4678 int t;
4679 char *s;
4680 char c;
4681 int i;
4682 const struct opt_action *o;
4683
4684 SKIP_WHITESPACE ();
4685
4686 t = 1;
4687 if (*input_line_pointer == '-')
4688 {
4689 ++input_line_pointer;
4690 t = 0;
4691 }
4692 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4693 {
4694 input_line_pointer += 2;
4695 t = 0;
4696 }
4697
4698 s = input_line_pointer;
4699 c = get_symbol_end ();
4700
4701 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4702 {
4703 if (strcasecmp (s, o->name) == 0)
4704 {
4705 if (o->pfn)
4706 {
4707 /* Restore input_line_pointer now in case the option
4708 takes arguments. */
4709 *input_line_pointer = c;
4710 (*o->pfn) (o->arg, t);
4711 }
4712 else if (o->pvar != NULL)
4713 {
4714 if (! t && o->arg == o->notarg)
4715 as_bad ("option `%s' may not be negated", s);
4716 *input_line_pointer = c;
4717 *o->pvar = t ? o->arg : o->notarg;
4718 }
4719 else
4720 *input_line_pointer = c;
4721 break;
4722 }
4723 }
4724 if (i >= OPTCOUNT)
4725 {
4726 as_bad ("option `%s' not recognized", s);
4727 *input_line_pointer = c;
4728 }
4729 }
4730 while (*input_line_pointer++ == ',');
4731
4732 /* Move back to terminating character. */
4733 --input_line_pointer;
4734 demand_empty_rest_of_line ();
4735 }
4736
4737 /* Skip ahead to a comma. This is used for OPT options which we do
4738 not suppor tand which take arguments. */
4739
4740 static void
4741 skip_to_comma (arg, on)
4742 int arg;
4743 int on;
4744 {
4745 while (*input_line_pointer != ','
4746 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4747 ++input_line_pointer;
4748 }
4749
4750 /* Handle the OPT NEST=depth option. */
4751
4752 static void
4753 opt_nest (arg, on)
4754 int arg;
4755 int on;
4756 {
4757 if (*input_line_pointer != '=')
4758 {
4759 as_bad ("bad format of OPT NEST=depth");
4760 return;
4761 }
4762
4763 ++input_line_pointer;
4764 max_macro_nest = get_absolute_expression ();
4765 }
4766
4767 /* Handle the OPT P=chip option. */
4768
4769 static void
4770 opt_chip (arg, on)
4771 int arg;
4772 int on;
4773 {
4774 if (*input_line_pointer != '=')
4775 {
4776 /* This is just OPT P, which we do not support. */
4777 return;
4778 }
4779
4780 ++input_line_pointer;
4781 mri_chip ();
4782 }
4783
4784 /* Handle the OPT S option. */
4785
4786 static void
4787 opt_list (arg, on)
4788 int arg;
4789 int on;
4790 {
4791 listing_list (on);
4792 }
4793
4794 /* Handle the OPT T option. */
4795
4796 static void
4797 opt_list_symbols (arg, on)
4798 int arg;
4799 int on;
4800 {
4801 if (on)
4802 listing |= LISTING_SYMBOLS;
4803 else
4804 listing &=~ LISTING_SYMBOLS;
4805 }
4806
4807 /* Handle the MRI REG pseudo-op. */
4808
4809 static void
4810 s_reg (ignore)
4811 int ignore;
4812 {
4813 char *s;
4814 int c;
4815 struct m68k_op rop;
4816 unsigned long mask;
4817 char *stop = NULL;
4818 char stopc;
4819
4820 if (line_label == NULL)
4821 {
4822 as_bad ("missing label");
4823 ignore_rest_of_line ();
4824 return;
4825 }
4826
4827 if (flag_mri)
4828 stop = mri_comment_field (&stopc);
4829
4830 SKIP_WHITESPACE ();
4831
4832 s = input_line_pointer;
4833 while (isalnum ((unsigned char) *input_line_pointer)
4834 #ifdef REGISTER_PREFIX
4835 || *input_line_pointer == REGISTER_PREFIX
4836 #endif
4837 || *input_line_pointer == '/'
4838 || *input_line_pointer == '-')
4839 ++input_line_pointer;
4840 c = *input_line_pointer;
4841 *input_line_pointer = '\0';
4842
4843 if (m68k_ip_op (s, &rop) != 0)
4844 {
4845 if (rop.error == NULL)
4846 as_bad ("bad register list");
4847 else
4848 as_bad ("bad register list: %s", rop.error);
4849 *input_line_pointer = c;
4850 ignore_rest_of_line ();
4851 return;
4852 }
4853
4854 *input_line_pointer = c;
4855
4856 if (rop.mode == REGLST)
4857 mask = rop.mask;
4858 else if (rop.mode == DREG)
4859 mask = 1 << (rop.reg - DATA0);
4860 else if (rop.mode == AREG)
4861 mask = 1 << (rop.reg - ADDR0 + 8);
4862 else if (rop.mode == FPREG)
4863 mask = 1 << (rop.reg - FP0 + 16);
4864 else if (rop.mode == CONTROL
4865 && rop.reg == FPI)
4866 mask = 1 << 24;
4867 else if (rop.mode == CONTROL
4868 && rop.reg == FPS)
4869 mask = 1 << 25;
4870 else if (rop.mode == CONTROL
4871 && rop.reg == FPC)
4872 mask = 1 << 26;
4873 else
4874 {
4875 as_bad ("bad register list");
4876 ignore_rest_of_line ();
4877 return;
4878 }
4879
4880 S_SET_SEGMENT (line_label, absolute_section);
4881 S_SET_VALUE (line_label, mask);
4882 line_label->sy_frag = &zero_address_frag;
4883
4884 if (flag_mri)
4885 mri_comment_end (stop, stopc);
4886
4887 demand_empty_rest_of_line ();
4888 }
4889
4890 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4891
4892 struct save_opts
4893 {
4894 struct save_opts *next;
4895 int abspcadd;
4896 int symbols_case_sensitive;
4897 int keep_locals;
4898 int short_refs;
4899 int architecture;
4900 int quick;
4901 int rel32;
4902 int listing;
4903 int no_warnings;
4904 /* FIXME: We don't save OPT S. */
4905 };
4906
4907 /* This variable holds the stack of saved options. */
4908
4909 static struct save_opts *save_stack;
4910
4911 /* The MRI SAVE pseudo-op. */
4912
4913 static void
4914 s_save (ignore)
4915 int ignore;
4916 {
4917 struct save_opts *s;
4918
4919 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
4920 s->abspcadd = m68k_abspcadd;
4921 s->symbols_case_sensitive = symbols_case_sensitive;
4922 s->keep_locals = flag_keep_locals;
4923 s->short_refs = flag_short_refs;
4924 s->architecture = current_architecture;
4925 s->quick = m68k_quick;
4926 s->rel32 = m68k_rel32;
4927 s->listing = listing;
4928 s->no_warnings = flag_no_warnings;
4929
4930 s->next = save_stack;
4931 save_stack = s;
4932
4933 demand_empty_rest_of_line ();
4934 }
4935
4936 /* The MRI RESTORE pseudo-op. */
4937
4938 static void
4939 s_restore (ignore)
4940 int ignore;
4941 {
4942 struct save_opts *s;
4943
4944 if (save_stack == NULL)
4945 {
4946 as_bad ("restore without save");
4947 ignore_rest_of_line ();
4948 return;
4949 }
4950
4951 s = save_stack;
4952 save_stack = s->next;
4953
4954 m68k_abspcadd = s->abspcadd;
4955 symbols_case_sensitive = s->symbols_case_sensitive;
4956 flag_keep_locals = s->keep_locals;
4957 flag_short_refs = s->short_refs;
4958 current_architecture = s->architecture;
4959 m68k_quick = s->quick;
4960 m68k_rel32 = s->rel32;
4961 listing = s->listing;
4962 flag_no_warnings = s->no_warnings;
4963
4964 free (s);
4965
4966 demand_empty_rest_of_line ();
4967 }
4968
4969 /* Types of MRI structured control directives. */
4970
4971 enum mri_control_type
4972 {
4973 mri_for,
4974 mri_if,
4975 mri_repeat,
4976 mri_while
4977 };
4978
4979 /* This structure is used to stack the MRI structured control
4980 directives. */
4981
4982 struct mri_control_info
4983 {
4984 /* The directive within which this one is enclosed. */
4985 struct mri_control_info *outer;
4986
4987 /* The type of directive. */
4988 enum mri_control_type type;
4989
4990 /* Whether an ELSE has been in an IF. */
4991 int else_seen;
4992
4993 /* The add or sub statement at the end of a FOR. */
4994 char *incr;
4995
4996 /* The label of the top of a FOR or REPEAT loop. */
4997 char *top;
4998
4999 /* The label to jump to for the next iteration, or the else
5000 expression of a conditional. */
5001 char *next;
5002
5003 /* The label to jump to to break out of the loop, or the label past
5004 the end of a conditional. */
5005 char *bottom;
5006 };
5007
5008 /* The stack of MRI structured control directives. */
5009
5010 static struct mri_control_info *mri_control_stack;
5011
5012 /* The current MRI structured control directive index number, used to
5013 generate label names. */
5014
5015 static int mri_control_index;
5016
5017 /* Some function prototypes. */
5018
5019 static char *mri_control_label PARAMS ((void));
5020 static struct mri_control_info *push_mri_control
5021 PARAMS ((enum mri_control_type));
5022 static void pop_mri_control PARAMS ((void));
5023 static int parse_mri_condition PARAMS ((int *));
5024 static int parse_mri_control_operand
5025 PARAMS ((int *, char **, char **, char **, char **));
5026 static int swap_mri_condition PARAMS ((int));
5027 static int reverse_mri_condition PARAMS ((int));
5028 static void build_mri_control_operand
5029 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5030 const char *, int));
5031 static void parse_mri_control_expression
5032 PARAMS ((char *, int, const char *, const char *, int));
5033
5034 /* Generate a new MRI label structured control directive label name. */
5035
5036 static char *
5037 mri_control_label ()
5038 {
5039 char *n;
5040
5041 n = (char *) xmalloc (20);
5042 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5043 ++mri_control_index;
5044 return n;
5045 }
5046
5047 /* Create a new MRI structured control directive. */
5048
5049 static struct mri_control_info *
5050 push_mri_control (type)
5051 enum mri_control_type type;
5052 {
5053 struct mri_control_info *n;
5054
5055 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5056
5057 n->type = type;
5058 n->else_seen = 0;
5059 if (type == mri_if || type == mri_while)
5060 n->top = NULL;
5061 else
5062 n->top = mri_control_label ();
5063 n->next = mri_control_label ();
5064 n->bottom = mri_control_label ();
5065
5066 n->outer = mri_control_stack;
5067 mri_control_stack = n;
5068
5069 return n;
5070 }
5071
5072 /* Pop off the stack of MRI structured control directives. */
5073
5074 static void
5075 pop_mri_control ()
5076 {
5077 struct mri_control_info *n;
5078
5079 n = mri_control_stack;
5080 mri_control_stack = n->outer;
5081 if (n->top != NULL)
5082 free (n->top);
5083 free (n->next);
5084 free (n->bottom);
5085 free (n);
5086 }
5087
5088 /* Recognize a condition code in an MRI structured control expression. */
5089
5090 static int
5091 parse_mri_condition (pcc)
5092 int *pcc;
5093 {
5094 char c1, c2;
5095
5096 know (*input_line_pointer == '<');
5097
5098 ++input_line_pointer;
5099 c1 = *input_line_pointer++;
5100 c2 = *input_line_pointer++;
5101
5102 if (*input_line_pointer != '>')
5103 {
5104 as_bad ("syntax error in structured control directive");
5105 return 0;
5106 }
5107
5108 ++input_line_pointer;
5109 SKIP_WHITESPACE ();
5110
5111 if (isupper (c1))
5112 c1 = tolower (c1);
5113 if (isupper (c2))
5114 c2 = tolower (c2);
5115
5116 *pcc = (c1 << 8) | c2;
5117
5118 return 1;
5119 }
5120
5121 /* Parse a single operand in an MRI structured control expression. */
5122
5123 static int
5124 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5125 int *pcc;
5126 char **leftstart;
5127 char **leftstop;
5128 char **rightstart;
5129 char **rightstop;
5130 {
5131 char *s;
5132
5133 SKIP_WHITESPACE ();
5134
5135 *pcc = -1;
5136 *leftstart = NULL;
5137 *leftstop = NULL;
5138 *rightstart = NULL;
5139 *rightstop = NULL;
5140
5141 if (*input_line_pointer == '<')
5142 {
5143 /* It's just a condition code. */
5144 return parse_mri_condition (pcc);
5145 }
5146
5147 /* Look ahead for the condition code. */
5148 for (s = input_line_pointer; *s != '\0'; ++s)
5149 {
5150 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5151 break;
5152 }
5153 if (*s == '\0')
5154 {
5155 as_bad ("missing condition code in structured control directive");
5156 return 0;
5157 }
5158
5159 *leftstart = input_line_pointer;
5160 *leftstop = s;
5161 if (*leftstop > *leftstart
5162 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5163 --*leftstop;
5164
5165 input_line_pointer = s;
5166 if (! parse_mri_condition (pcc))
5167 return 0;
5168
5169 /* Look ahead for AND or OR or end of line. */
5170 for (s = input_line_pointer; *s != '\0'; ++s)
5171 {
5172 if ((strncasecmp (s, "AND", 3) == 0
5173 && (s[3] == '.' || ! is_part_of_name (s[3])))
5174 || (strncasecmp (s, "OR", 2) == 0
5175 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5176 break;
5177 }
5178
5179 *rightstart = input_line_pointer;
5180 *rightstop = s;
5181 if (*rightstop > *rightstart
5182 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5183 --*rightstop;
5184
5185 input_line_pointer = s;
5186
5187 return 1;
5188 }
5189
5190 #define MCC(b1, b2) (((b1) << 8) | (b2))
5191
5192 /* Swap the sense of a condition. This changes the condition so that
5193 it generates the same result when the operands are swapped. */
5194
5195 static int
5196 swap_mri_condition (cc)
5197 int cc;
5198 {
5199 switch (cc)
5200 {
5201 case MCC ('h', 'i'): return MCC ('c', 's');
5202 case MCC ('l', 's'): return MCC ('c', 'c');
5203 case MCC ('c', 'c'): return MCC ('l', 's');
5204 case MCC ('c', 's'): return MCC ('h', 'i');
5205 case MCC ('p', 'l'): return MCC ('m', 'i');
5206 case MCC ('m', 'i'): return MCC ('p', 'l');
5207 case MCC ('g', 'e'): return MCC ('l', 'e');
5208 case MCC ('l', 't'): return MCC ('g', 't');
5209 case MCC ('g', 't'): return MCC ('l', 't');
5210 case MCC ('l', 'e'): return MCC ('g', 'e');
5211 }
5212 return cc;
5213 }
5214
5215 /* Reverse the sense of a condition. */
5216
5217 static int
5218 reverse_mri_condition (cc)
5219 int cc;
5220 {
5221 switch (cc)
5222 {
5223 case MCC ('h', 'i'): return MCC ('l', 's');
5224 case MCC ('l', 's'): return MCC ('h', 'i');
5225 case MCC ('c', 'c'): return MCC ('c', 's');
5226 case MCC ('c', 's'): return MCC ('c', 'c');
5227 case MCC ('n', 'e'): return MCC ('e', 'q');
5228 case MCC ('e', 'q'): return MCC ('n', 'e');
5229 case MCC ('v', 'c'): return MCC ('v', 's');
5230 case MCC ('v', 's'): return MCC ('v', 'c');
5231 case MCC ('p', 'l'): return MCC ('m', 'i');
5232 case MCC ('m', 'i'): return MCC ('p', 'l');
5233 case MCC ('g', 'e'): return MCC ('l', 't');
5234 case MCC ('l', 't'): return MCC ('g', 'e');
5235 case MCC ('g', 't'): return MCC ('l', 'e');
5236 case MCC ('l', 'e'): return MCC ('g', 't');
5237 }
5238 return cc;
5239 }
5240
5241 /* Build an MRI structured control expression. This generates test
5242 and branch instructions. It goes to TRUELAB if the condition is
5243 true, and to FALSELAB if the condition is false. Exactly one of
5244 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5245 is the size qualifier for the expression. EXTENT is the size to
5246 use for the branch. */
5247
5248 static void
5249 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5250 rightstop, truelab, falselab, extent)
5251 int qual;
5252 int cc;
5253 char *leftstart;
5254 char *leftstop;
5255 char *rightstart;
5256 char *rightstop;
5257 const char *truelab;
5258 const char *falselab;
5259 int extent;
5260 {
5261 char *buf;
5262 char *s;
5263
5264 if (leftstart != NULL)
5265 {
5266 struct m68k_op leftop, rightop;
5267 char c;
5268
5269 /* Swap the compare operands, if necessary, to produce a legal
5270 m68k compare instruction. Comparing a register operand with
5271 a non-register operand requires the register to be on the
5272 right (cmp, cmpa). Comparing an immediate value with
5273 anything requires the immediate value to be on the left
5274 (cmpi). */
5275
5276 c = *leftstop;
5277 *leftstop = '\0';
5278 (void) m68k_ip_op (leftstart, &leftop);
5279 *leftstop = c;
5280
5281 c = *rightstop;
5282 *rightstop = '\0';
5283 (void) m68k_ip_op (rightstart, &rightop);
5284 *rightstop = c;
5285
5286 if (rightop.mode == IMMED
5287 || ((leftop.mode == DREG || leftop.mode == AREG)
5288 && (rightop.mode != DREG && rightop.mode != AREG)))
5289 {
5290 char *temp;
5291
5292 cc = swap_mri_condition (cc);
5293 temp = leftstart;
5294 leftstart = rightstart;
5295 rightstart = temp;
5296 temp = leftstop;
5297 leftstop = rightstop;
5298 rightstop = temp;
5299 }
5300 }
5301
5302 if (truelab == NULL)
5303 {
5304 cc = reverse_mri_condition (cc);
5305 truelab = falselab;
5306 }
5307
5308 if (leftstart != NULL)
5309 {
5310 buf = (char *) xmalloc (20
5311 + (leftstop - leftstart)
5312 + (rightstop - rightstart));
5313 s = buf;
5314 *s++ = 'c';
5315 *s++ = 'm';
5316 *s++ = 'p';
5317 if (qual != '\0')
5318 *s++ = qual;
5319 *s++ = ' ';
5320 memcpy (s, leftstart, leftstop - leftstart);
5321 s += leftstop - leftstart;
5322 *s++ = ',';
5323 memcpy (s, rightstart, rightstop - rightstart);
5324 s += rightstop - rightstart;
5325 *s = '\0';
5326 md_assemble (buf);
5327 free (buf);
5328 }
5329
5330 buf = (char *) xmalloc (20 + strlen (truelab));
5331 s = buf;
5332 *s++ = 'b';
5333 *s++ = cc >> 8;
5334 *s++ = cc & 0xff;
5335 if (extent != '\0')
5336 *s++ = extent;
5337 *s++ = ' ';
5338 strcpy (s, truelab);
5339 md_assemble (buf);
5340 free (buf);
5341 }
5342
5343 /* Parse an MRI structured control expression. This generates test
5344 and branch instructions. STOP is where the expression ends. It
5345 goes to TRUELAB if the condition is true, and to FALSELAB if the
5346 condition is false. Exactly one of TRUELAB and FALSELAB will be
5347 NULL, meaning to fall through. QUAL is the size qualifier for the
5348 expression. EXTENT is the size to use for the branch. */
5349
5350 static void
5351 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5352 char *stop;
5353 int qual;
5354 const char *truelab;
5355 const char *falselab;
5356 int extent;
5357 {
5358 int c;
5359 int cc;
5360 char *leftstart;
5361 char *leftstop;
5362 char *rightstart;
5363 char *rightstop;
5364
5365 c = *stop;
5366 *stop = '\0';
5367
5368 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5369 &rightstart, &rightstop))
5370 {
5371 *stop = c;
5372 return;
5373 }
5374
5375 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5376 {
5377 const char *flab;
5378
5379 if (falselab != NULL)
5380 flab = falselab;
5381 else
5382 flab = mri_control_label ();
5383
5384 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5385 rightstop, (const char *) NULL, flab, extent);
5386
5387 input_line_pointer += 3;
5388 if (*input_line_pointer != '.'
5389 || input_line_pointer[1] == '\0')
5390 qual = '\0';
5391 else
5392 {
5393 qual = input_line_pointer[1];
5394 input_line_pointer += 2;
5395 }
5396
5397 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5398 &rightstart, &rightstop))
5399 {
5400 *stop = c;
5401 return;
5402 }
5403
5404 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5405 rightstop, truelab, falselab, extent);
5406
5407 if (falselab == NULL)
5408 colon (flab);
5409 }
5410 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5411 {
5412 const char *tlab;
5413
5414 if (truelab != NULL)
5415 tlab = truelab;
5416 else
5417 tlab = mri_control_label ();
5418
5419 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5420 rightstop, tlab, (const char *) NULL, extent);
5421
5422 input_line_pointer += 2;
5423 if (*input_line_pointer != '.'
5424 || input_line_pointer[1] == '\0')
5425 qual = '\0';
5426 else
5427 {
5428 qual = input_line_pointer[1];
5429 input_line_pointer += 2;
5430 }
5431
5432 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5433 &rightstart, &rightstop))
5434 {
5435 *stop = c;
5436 return;
5437 }
5438
5439 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5440 rightstop, truelab, falselab, extent);
5441
5442 if (truelab == NULL)
5443 colon (tlab);
5444 }
5445 else
5446 {
5447 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5448 rightstop, truelab, falselab, extent);
5449 }
5450
5451 *stop = c;
5452 if (input_line_pointer != stop)
5453 as_bad ("syntax error in structured control directive");
5454 }
5455
5456 /* Handle the MRI IF pseudo-op. This may be a structured control
5457 directive, or it may be a regular assembler conditional, depending
5458 on its operands. */
5459
5460 static void
5461 s_mri_if (qual)
5462 int qual;
5463 {
5464 char *s;
5465 int c;
5466 struct mri_control_info *n;
5467
5468 /* A structured control directive must end with THEN with an
5469 optional qualifier. */
5470 s = input_line_pointer;
5471 while (! is_end_of_line[(unsigned char) *s]
5472 && (! flag_mri || *s != '*'))
5473 ++s;
5474 --s;
5475 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5476 --s;
5477
5478 if (s - input_line_pointer > 1
5479 && s[-1] == '.')
5480 s -= 2;
5481
5482 if (s - input_line_pointer < 3
5483 || strncasecmp (s - 3, "THEN", 4) != 0)
5484 {
5485 if (qual != '\0')
5486 {
5487 as_bad ("missing then");
5488 ignore_rest_of_line ();
5489 return;
5490 }
5491
5492 /* It's a conditional. */
5493 s_if (O_ne);
5494 return;
5495 }
5496
5497 /* Since this might be a conditional if, this pseudo-op will be
5498 called even if we are supported to be ignoring input. Double
5499 check now. Clobber *input_line_pointer so that ignore_input
5500 thinks that this is not a special pseudo-op. */
5501 c = *input_line_pointer;
5502 *input_line_pointer = 0;
5503 if (ignore_input ())
5504 {
5505 *input_line_pointer = c;
5506 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5507 ++input_line_pointer;
5508 demand_empty_rest_of_line ();
5509 return;
5510 }
5511 *input_line_pointer = c;
5512
5513 n = push_mri_control (mri_if);
5514
5515 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5516 n->next, s[1] == '.' ? s[2] : '\0');
5517
5518 if (s[1] == '.')
5519 input_line_pointer = s + 3;
5520 else
5521 input_line_pointer = s + 1;
5522
5523 if (flag_mri)
5524 {
5525 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5526 ++input_line_pointer;
5527 }
5528
5529 demand_empty_rest_of_line ();
5530 }
5531
5532 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5533 structured IF, associate the ELSE with the IF. Otherwise, assume
5534 it is a conditional else. */
5535
5536 static void
5537 s_mri_else (qual)
5538 int qual;
5539 {
5540 int c;
5541 char *buf;
5542 char q[2];
5543
5544 if (qual == '\0'
5545 && (mri_control_stack == NULL
5546 || mri_control_stack->type != mri_if
5547 || mri_control_stack->else_seen))
5548 {
5549 s_else (0);
5550 return;
5551 }
5552
5553 c = *input_line_pointer;
5554 *input_line_pointer = 0;
5555 if (ignore_input ())
5556 {
5557 *input_line_pointer = c;
5558 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5559 ++input_line_pointer;
5560 demand_empty_rest_of_line ();
5561 return;
5562 }
5563 *input_line_pointer = c;
5564
5565 if (mri_control_stack == NULL
5566 || mri_control_stack->type != mri_if
5567 || mri_control_stack->else_seen)
5568 {
5569 as_bad ("else without matching if");
5570 ignore_rest_of_line ();
5571 return;
5572 }
5573
5574 mri_control_stack->else_seen = 1;
5575
5576 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5577 q[0] = qual;
5578 q[1] = '\0';
5579 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5580 md_assemble (buf);
5581 free (buf);
5582
5583 colon (mri_control_stack->next);
5584
5585 if (flag_mri)
5586 {
5587 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5588 ++input_line_pointer;
5589 }
5590
5591 demand_empty_rest_of_line ();
5592 }
5593
5594 /* Handle the MRI ENDI pseudo-op. */
5595
5596 static void
5597 s_mri_endi (ignore)
5598 int ignore;
5599 {
5600 if (mri_control_stack == NULL
5601 || mri_control_stack->type != mri_if)
5602 {
5603 as_bad ("endi without matching if");
5604 ignore_rest_of_line ();
5605 return;
5606 }
5607
5608 /* ignore_input will not return true for ENDI, so we don't need to
5609 worry about checking it again here. */
5610
5611 if (! mri_control_stack->else_seen)
5612 colon (mri_control_stack->next);
5613 colon (mri_control_stack->bottom);
5614
5615 pop_mri_control ();
5616
5617 if (flag_mri)
5618 {
5619 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5620 ++input_line_pointer;
5621 }
5622
5623 demand_empty_rest_of_line ();
5624 }
5625
5626 /* Handle the MRI BREAK pseudo-op. */
5627
5628 static void
5629 s_mri_break (extent)
5630 int extent;
5631 {
5632 struct mri_control_info *n;
5633 char *buf;
5634 char ex[2];
5635
5636 n = mri_control_stack;
5637 while (n != NULL
5638 && n->type != mri_for
5639 && n->type != mri_repeat
5640 && n->type != mri_while)
5641 n = n->outer;
5642 if (n == NULL)
5643 {
5644 as_bad ("break outside of structured loop");
5645 ignore_rest_of_line ();
5646 return;
5647 }
5648
5649 buf = (char *) xmalloc (20 + strlen (n->bottom));
5650 ex[0] = extent;
5651 ex[1] = '\0';
5652 sprintf (buf, "bra%s %s", ex, n->bottom);
5653 md_assemble (buf);
5654 free (buf);
5655
5656 if (flag_mri)
5657 {
5658 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5659 ++input_line_pointer;
5660 }
5661
5662 demand_empty_rest_of_line ();
5663 }
5664
5665 /* Handle the MRI NEXT pseudo-op. */
5666
5667 static void
5668 s_mri_next (extent)
5669 int extent;
5670 {
5671 struct mri_control_info *n;
5672 char *buf;
5673 char ex[2];
5674
5675 n = mri_control_stack;
5676 while (n != NULL
5677 && n->type != mri_for
5678 && n->type != mri_repeat
5679 && n->type != mri_while)
5680 n = n->outer;
5681 if (n == NULL)
5682 {
5683 as_bad ("next outside of structured loop");
5684 ignore_rest_of_line ();
5685 return;
5686 }
5687
5688 buf = (char *) xmalloc (20 + strlen (n->next));
5689 ex[0] = extent;
5690 ex[1] = '\0';
5691 sprintf (buf, "bra%s %s", ex, n->next);
5692 md_assemble (buf);
5693 free (buf);
5694
5695 if (flag_mri)
5696 {
5697 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5698 ++input_line_pointer;
5699 }
5700
5701 demand_empty_rest_of_line ();
5702 }
5703
5704 /* Handle the MRI FOR pseudo-op. */
5705
5706 static void
5707 s_mri_for (qual)
5708 int qual;
5709 {
5710 const char *varstart, *varstop;
5711 const char *initstart, *initstop;
5712 const char *endstart, *endstop;
5713 const char *bystart, *bystop;
5714 int up;
5715 int by;
5716 int extent;
5717 struct mri_control_info *n;
5718 char *buf;
5719 char *s;
5720 char ex[2];
5721
5722 /* The syntax is
5723 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5724 */
5725
5726 SKIP_WHITESPACE ();
5727 varstart = input_line_pointer;
5728
5729 /* Look for the '='. */
5730 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5731 && *input_line_pointer != '=')
5732 ++input_line_pointer;
5733 if (*input_line_pointer != '=')
5734 {
5735 as_bad ("missing =");
5736 ignore_rest_of_line ();
5737 return;
5738 }
5739
5740 varstop = input_line_pointer;
5741 if (varstop > varstart
5742 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5743 --varstop;
5744
5745 ++input_line_pointer;
5746
5747 initstart = input_line_pointer;
5748
5749 /* Look for TO or DOWNTO. */
5750 up = 1;
5751 initstop = NULL;
5752 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5753 {
5754 if (strncasecmp (input_line_pointer, "TO", 2) == 0
5755 && ! is_part_of_name (input_line_pointer[2]))
5756 {
5757 initstop = input_line_pointer;
5758 input_line_pointer += 2;
5759 break;
5760 }
5761 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
5762 && ! is_part_of_name (input_line_pointer[6]))
5763 {
5764 initstop = input_line_pointer;
5765 up = 0;
5766 input_line_pointer += 6;
5767 break;
5768 }
5769 ++input_line_pointer;
5770 }
5771 if (initstop == NULL)
5772 {
5773 as_bad ("missing to or downto");
5774 ignore_rest_of_line ();
5775 return;
5776 }
5777 if (initstop > initstart
5778 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
5779 --initstop;
5780
5781 SKIP_WHITESPACE ();
5782 endstart = input_line_pointer;
5783
5784 /* Look for BY or DO. */
5785 by = 0;
5786 endstop = NULL;
5787 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5788 {
5789 if (strncasecmp (input_line_pointer, "BY", 2) == 0
5790 && ! is_part_of_name (input_line_pointer[2]))
5791 {
5792 endstop = input_line_pointer;
5793 by = 1;
5794 input_line_pointer += 2;
5795 break;
5796 }
5797 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5798 && (input_line_pointer[2] == '.'
5799 || ! is_part_of_name (input_line_pointer[2])))
5800 {
5801 endstop = input_line_pointer;
5802 input_line_pointer += 2;
5803 break;
5804 }
5805 ++input_line_pointer;
5806 }
5807 if (endstop == NULL)
5808 {
5809 as_bad ("missing do");
5810 ignore_rest_of_line ();
5811 return;
5812 }
5813 if (endstop > endstart
5814 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
5815 --endstop;
5816
5817 if (! by)
5818 {
5819 bystart = "#1";
5820 bystop = bystart + 2;
5821 }
5822 else
5823 {
5824 SKIP_WHITESPACE ();
5825 bystart = input_line_pointer;
5826
5827 /* Look for DO. */
5828 bystop = NULL;
5829 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5830 {
5831 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5832 && (input_line_pointer[2] == '.'
5833 || ! is_part_of_name (input_line_pointer[2])))
5834 {
5835 bystop = input_line_pointer;
5836 input_line_pointer += 2;
5837 break;
5838 }
5839 ++input_line_pointer;
5840 }
5841 if (bystop == NULL)
5842 {
5843 as_bad ("missing do");
5844 ignore_rest_of_line ();
5845 return;
5846 }
5847 if (bystop > bystart
5848 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
5849 --bystop;
5850 }
5851
5852 if (*input_line_pointer != '.')
5853 extent = '\0';
5854 else
5855 {
5856 extent = input_line_pointer[1];
5857 input_line_pointer += 2;
5858 }
5859
5860 /* We have fully parsed the FOR operands. Now build the loop. */
5861
5862 n = push_mri_control (mri_for);
5863
5864 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
5865
5866 /* move init,var */
5867 s = buf;
5868 *s++ = 'm';
5869 *s++ = 'o';
5870 *s++ = 'v';
5871 *s++ = 'e';
5872 if (qual != '\0')
5873 *s++ = qual;
5874 *s++ = ' ';
5875 memcpy (s, initstart, initstop - initstart);
5876 s += initstop - initstart;
5877 *s++ = ',';
5878 memcpy (s, varstart, varstop - varstart);
5879 s += varstop - varstart;
5880 *s = '\0';
5881 md_assemble (buf);
5882
5883 colon (n->top);
5884
5885 /* cmp end,var */
5886 s = buf;
5887 *s++ = 'c';
5888 *s++ = 'm';
5889 *s++ = 'p';
5890 if (qual != '\0')
5891 *s++ = qual;
5892 *s++ = ' ';
5893 memcpy (s, endstart, endstop - endstart);
5894 s += endstop - endstart;
5895 *s++ = ',';
5896 memcpy (s, varstart, varstop - varstart);
5897 s += varstop - varstart;
5898 *s = '\0';
5899 md_assemble (buf);
5900
5901 /* bcc bottom */
5902 ex[0] = extent;
5903 ex[1] = '\0';
5904 if (up)
5905 sprintf (buf, "blt%s %s", ex, n->bottom);
5906 else
5907 sprintf (buf, "bgt%s %s", ex, n->bottom);
5908 md_assemble (buf);
5909
5910 /* Put together the add or sub instruction used by ENDF. */
5911 s = buf;
5912 if (up)
5913 strcpy (s, "add");
5914 else
5915 strcpy (s, "sub");
5916 s += 3;
5917 if (qual != '\0')
5918 *s++ = qual;
5919 *s++ = ' ';
5920 memcpy (s, bystart, bystop - bystart);
5921 s += bystop - bystart;
5922 *s++ = ',';
5923 memcpy (s, varstart, varstop - varstart);
5924 s += varstop - varstart;
5925 *s = '\0';
5926 n->incr = buf;
5927
5928 if (flag_mri)
5929 {
5930 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5931 ++input_line_pointer;
5932 }
5933
5934 demand_empty_rest_of_line ();
5935 }
5936
5937 /* Handle the MRI ENDF pseudo-op. */
5938
5939 static void
5940 s_mri_endf (ignore)
5941 int ignore;
5942 {
5943 if (mri_control_stack == NULL
5944 || mri_control_stack->type != mri_for)
5945 {
5946 as_bad ("endf without for");
5947 ignore_rest_of_line ();
5948 return;
5949 }
5950
5951 colon (mri_control_stack->next);
5952
5953 md_assemble (mri_control_stack->incr);
5954
5955 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
5956 md_assemble (mri_control_stack->incr);
5957
5958 free (mri_control_stack->incr);
5959
5960 colon (mri_control_stack->bottom);
5961
5962 pop_mri_control ();
5963
5964 if (flag_mri)
5965 {
5966 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5967 ++input_line_pointer;
5968 }
5969
5970 demand_empty_rest_of_line ();
5971 }
5972
5973 /* Handle the MRI REPEAT pseudo-op. */
5974
5975 static void
5976 s_mri_repeat (ignore)
5977 int ignore;
5978 {
5979 struct mri_control_info *n;
5980
5981 n = push_mri_control (mri_repeat);
5982 colon (n->top);
5983 if (flag_mri)
5984 {
5985 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5986 ++input_line_pointer;
5987 }
5988 demand_empty_rest_of_line ();
5989 }
5990
5991 /* Handle the MRI UNTIL pseudo-op. */
5992
5993 static void
5994 s_mri_until (qual)
5995 int qual;
5996 {
5997 char *s;
5998
5999 if (mri_control_stack == NULL
6000 || mri_control_stack->type != mri_repeat)
6001 {
6002 as_bad ("until without repeat");
6003 ignore_rest_of_line ();
6004 return;
6005 }
6006
6007 colon (mri_control_stack->next);
6008
6009 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6010 ;
6011
6012 parse_mri_control_expression (s, qual, (const char *) NULL,
6013 mri_control_stack->top, '\0');
6014
6015 colon (mri_control_stack->bottom);
6016
6017 input_line_pointer = s;
6018
6019 pop_mri_control ();
6020
6021 if (flag_mri)
6022 {
6023 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6024 ++input_line_pointer;
6025 }
6026
6027 demand_empty_rest_of_line ();
6028 }
6029
6030 /* Handle the MRI WHILE pseudo-op. */
6031
6032 static void
6033 s_mri_while (qual)
6034 int qual;
6035 {
6036 char *s;
6037
6038 struct mri_control_info *n;
6039
6040 s = input_line_pointer;
6041 while (! is_end_of_line[(unsigned char) *s]
6042 && (! flag_mri || *s != '*'))
6043 s++;
6044 --s;
6045 while (*s == ' ' || *s == '\t')
6046 --s;
6047 if (s - input_line_pointer > 1
6048 && s[-1] == '.')
6049 s -= 2;
6050 if (s - input_line_pointer < 2
6051 || strncasecmp (s - 1, "DO", 2) != 0)
6052 {
6053 as_bad ("missing do");
6054 ignore_rest_of_line ();
6055 return;
6056 }
6057
6058 n = push_mri_control (mri_while);
6059
6060 colon (n->next);
6061
6062 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6063 s[1] == '.' ? s[2] : '\0');
6064
6065 input_line_pointer = s + 1;
6066 if (*input_line_pointer == '.')
6067 input_line_pointer += 2;
6068
6069 if (flag_mri)
6070 {
6071 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6072 ++input_line_pointer;
6073 }
6074
6075 demand_empty_rest_of_line ();
6076 }
6077
6078 /* Handle the MRI ENDW pseudo-op. */
6079
6080 static void
6081 s_mri_endw (ignore)
6082 int ignore;
6083 {
6084 char *buf;
6085
6086 if (mri_control_stack == NULL
6087 || mri_control_stack->type != mri_while)
6088 {
6089 as_bad ("endw without while");
6090 ignore_rest_of_line ();
6091 return;
6092 }
6093
6094 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6095 sprintf (buf, "bra %s", mri_control_stack->next);
6096 md_assemble (buf);
6097 free (buf);
6098
6099 colon (mri_control_stack->bottom);
6100
6101 pop_mri_control ();
6102
6103 if (flag_mri)
6104 {
6105 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6106 ++input_line_pointer;
6107 }
6108
6109 demand_empty_rest_of_line ();
6110 }
6111 \f
6112 /*
6113 * md_parse_option
6114 * Invocation line includes a switch not recognized by the base assembler.
6115 * See if it's a processor-specific option. These are:
6116 *
6117 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6118 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6119 * Select the architecture. Instructions or features not
6120 * supported by the selected architecture cause fatal
6121 * errors. More than one may be specified. The default is
6122 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6123 * for -m68000, and -m68882 is a synonym for -m68881.
6124 * -[A]m[c]no-68851, -[A]m[c]no-68881
6125 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6126 * so don't use or document it, but that's the way the parsing
6127 * works).
6128 *
6129 * -pic Indicates PIC.
6130 * -k Indicates PIC. (Sun 3 only.)
6131 *
6132 */
6133
6134 #ifdef OBJ_ELF
6135 CONST char *md_shortopts = "lSA:m:kQ:V";
6136 #else
6137 CONST char *md_shortopts = "lSA:m:k";
6138 #endif
6139
6140 struct option md_longopts[] = {
6141 #define OPTION_PIC (OPTION_MD_BASE)
6142 {"pic", no_argument, NULL, OPTION_PIC},
6143 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6144 {"register-prefix-optional", no_argument, NULL,
6145 OPTION_REGISTER_PREFIX_OPTIONAL},
6146 {NULL, no_argument, NULL, 0}
6147 };
6148 size_t md_longopts_size = sizeof(md_longopts);
6149
6150 int
6151 md_parse_option (c, arg)
6152 int c;
6153 char *arg;
6154 {
6155 switch (c)
6156 {
6157 case 'l': /* -l means keep external to 2 bit offset
6158 rather than 16 bit one */
6159 flag_short_refs = 1;
6160 break;
6161
6162 case 'S': /* -S means that jbsr's always turn into
6163 jsr's. */
6164 flag_long_jumps = 1;
6165 break;
6166
6167 case 'A':
6168 if (*arg == 'm')
6169 arg++;
6170 /* intentional fall-through */
6171 case 'm':
6172
6173 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6174 {
6175 int i;
6176 unsigned long arch;
6177 const char *oarg = arg;
6178
6179 arg += 3;
6180 if (*arg == 'm')
6181 {
6182 arg++;
6183 if (arg[0] == 'c' && arg[1] == '6')
6184 arg++;
6185 }
6186 for (i = 0; i < n_archs; i++)
6187 if (!strcmp (arg, archs[i].name))
6188 break;
6189 if (i == n_archs)
6190 {
6191 unknown:
6192 as_bad ("unrecognized option `%s'", oarg);
6193 return 0;
6194 }
6195 arch = archs[i].arch;
6196 if (arch == m68881)
6197 no_68881 = 1;
6198 else if (arch == m68851)
6199 no_68851 = 1;
6200 else
6201 goto unknown;
6202 }
6203 else
6204 {
6205 int i;
6206
6207 if (arg[0] == 'c' && arg[1] == '6')
6208 arg++;
6209
6210 for (i = 0; i < n_archs; i++)
6211 if (!strcmp (arg, archs[i].name))
6212 {
6213 unsigned long arch = archs[i].arch;
6214 if (cpu_of_arch (arch))
6215 /* It's a cpu spec. */
6216 {
6217 current_architecture &= ~m68000up;
6218 current_architecture |= arch;
6219 }
6220 else if (arch == m68881)
6221 {
6222 current_architecture |= m68881;
6223 no_68881 = 0;
6224 }
6225 else if (arch == m68851)
6226 {
6227 current_architecture |= m68851;
6228 no_68851 = 0;
6229 }
6230 else
6231 /* ??? */
6232 abort ();
6233 break;
6234 }
6235 if (i == n_archs)
6236 {
6237 as_bad ("unrecognized architecture specification `%s'", arg);
6238 return 0;
6239 }
6240 }
6241 break;
6242
6243 case OPTION_PIC:
6244 case 'k':
6245 flag_want_pic = 1;
6246 break; /* -pic, Position Independent Code */
6247
6248 case OPTION_REGISTER_PREFIX_OPTIONAL:
6249 flag_reg_prefix_optional = 1;
6250 reg_prefix_optional_seen = 1;
6251 break;
6252
6253 /* -V: SVR4 argument to print version ID. */
6254 case 'V':
6255 print_version_id ();
6256 break;
6257
6258 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6259 should be emitted or not. FIXME: Not implemented. */
6260 case 'Q':
6261 break;
6262
6263 default:
6264 return 0;
6265 }
6266
6267 return 1;
6268 }
6269
6270 void
6271 md_show_usage (stream)
6272 FILE *stream;
6273 {
6274 fprintf(stream, "\
6275 680X0 options:\n\
6276 -l use 1 word for refs to undefined symbols [default 2]\n\
6277 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6278 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6279 | -mcpu32\n\
6280 specify variant of 680X0 architecture [default 68020]\n\
6281 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6282 target has/lacks floating-point coprocessor\n\
6283 [default yes for 68020, 68030, and cpu32]\n");
6284 fprintf(stream, "\
6285 -m68851 | -mno-68851\n\
6286 target has/lacks memory-management unit coprocessor\n\
6287 [default yes for 68020 and up]\n\
6288 -pic, -k generate position independent code\n\
6289 -S turn jbsr into jsr\n\
6290 --register-prefix-optional\n\
6291 recognize register names without prefix character\n");
6292 }
6293 \f
6294 #ifdef TEST2
6295
6296 /* TEST2: Test md_assemble() */
6297 /* Warning, this routine probably doesn't work anymore */
6298
6299 main ()
6300 {
6301 struct m68k_it the_ins;
6302 char buf[120];
6303 char *cp;
6304 int n;
6305
6306 m68k_ip_begin ();
6307 for (;;)
6308 {
6309 if (!gets (buf) || !*buf)
6310 break;
6311 if (buf[0] == '|' || buf[1] == '.')
6312 continue;
6313 for (cp = buf; *cp; cp++)
6314 if (*cp == '\t')
6315 *cp = ' ';
6316 if (is_label (buf))
6317 continue;
6318 memset (&the_ins, '\0', sizeof (the_ins));
6319 m68k_ip (&the_ins, buf);
6320 if (the_ins.error)
6321 {
6322 printf ("Error %s in %s\n", the_ins.error, buf);
6323 }
6324 else
6325 {
6326 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6327 for (n = 0; n < the_ins.numo; n++)
6328 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6329 printf (" ");
6330 print_the_insn (&the_ins.opcode[0], stdout);
6331 (void) putchar ('\n');
6332 }
6333 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6334 {
6335 if (the_ins.operands[n].error)
6336 {
6337 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6338 continue;
6339 }
6340 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6341 if (the_ins.operands[n].b_const)
6342 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6343 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6344 if (the_ins.operands[n].b_iadd)
6345 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6346 (void) putchar ('\n');
6347 }
6348 }
6349 m68k_ip_end ();
6350 return 0;
6351 }
6352
6353 is_label (str)
6354 char *str;
6355 {
6356 while (*str == ' ')
6357 str++;
6358 while (*str && *str != ' ')
6359 str++;
6360 if (str[-1] == ':' || str[1] == '=')
6361 return 1;
6362 return 0;
6363 }
6364
6365 #endif
6366
6367 /* Possible states for relaxation:
6368
6369 0 0 branch offset byte (bra, etc)
6370 0 1 word
6371 0 2 long
6372
6373 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6374 1 1 word
6375 1 2 long
6376
6377 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6378 2 1 word-long
6379 2 2 long-word
6380 2 3 long-long
6381
6382 */
6383
6384 /* We have no need to default values of symbols. */
6385
6386 /* ARGSUSED */
6387 symbolS *
6388 md_undefined_symbol (name)
6389 char *name;
6390 {
6391 return 0;
6392 }
6393
6394 /* Round up a section size to the appropriate boundary. */
6395 valueT
6396 md_section_align (segment, size)
6397 segT segment;
6398 valueT size;
6399 {
6400 return size; /* Byte alignment is fine */
6401 }
6402
6403 /* Exactly what point is a PC-relative offset relative TO?
6404 On the 68k, it is relative to the address of the first extension
6405 word. The difference between the addresses of the offset and the
6406 first extension word is stored in fx_pcrel_adjust. */
6407 long
6408 md_pcrel_from (fixP)
6409 fixS *fixP;
6410 {
6411 int adjust;
6412
6413 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6414 -1 as 64. */
6415 adjust = fixP->fx_pcrel_adjust;
6416 if (adjust == 64)
6417 adjust = -1;
6418 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6419 }
6420
6421 #ifndef BFD_ASSEMBLER
6422 /*ARGSUSED*/
6423 void
6424 tc_coff_symbol_emit_hook (ignore)
6425 symbolS *ignore;
6426 {
6427 }
6428
6429 int
6430 tc_coff_sizemachdep (frag)
6431 fragS *frag;
6432 {
6433 switch (frag->fr_subtype & 0x3)
6434 {
6435 case BYTE:
6436 return 1;
6437 case SHORT:
6438 return 2;
6439 case LONG:
6440 return 4;
6441 default:
6442 abort ();
6443 return 0;
6444 }
6445 }
6446 #endif
6447
6448 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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