projects / deliverable / binutils-gdb.git / blob
? search:


d0b74ff56b65ec4eeabaf3ae0ac11eff7ab8a396
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* All the m68k specific stuff in one convenient, huge, slow to
2 compile, easy to find file.
3
4 Copyright (C) 1987, 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
22 #include <ctype.h>
23 #define NO_RELOC 0
24 #include "as.h"
25 #include "obstack.h"
26
27 /* The opcode table is too big for some versions of gcc, which require
28 exponential(?) space at compile time for initialized arrays. */
29 #ifdef __GNUC__
30 #define DO_BREAK_UP_BIG_DECL
31 #define BREAK_UP_BIG_DECL }; struct m68k_opcode m68k_opcodes_2[] = {
32 #define AND_OTHER_PART sizeof (m68k_opcodes_2)
33 #endif
34
35 /* Note that this file includes real declarations and thus can only be
36 included by one source file per executable. */
37 #include "opcode/m68k.h"
38
39 /* This array holds the chars that always start a comment. If the
40 pre-processor is disabled, these aren't very useful */
41 #ifdef OBJ_ELF
42 CONST char comment_chars[] = "|#";
43 #else
44 CONST char comment_chars[] = "|";
45 #endif
46
47 /* This array holds the chars that only start a comment at the beginning of
48 a line. If the line seems to have the form '# 123 filename'
49 .line and .file directives will appear in the pre-processed output */
50 /* Note that input_file.c hand checks for '#' at the beginning of the
51 first line of the input file. This is because the compiler outputs
52 #NO_APP at the beginning of its output. */
53 /* Also note that comments like this one will always work. */
54 CONST char line_comment_chars[] = "#";
55
56 CONST char line_separator_chars[] = "";
57
58 /* Chars that can be used to separate mant from exp in floating point nums */
59 CONST char EXP_CHARS[] = "eE";
60
61 /* Chars that mean this number is a floating point constant, as
62 in "0f12.456" or "0d1.2345e12". */
63
64 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
65
66 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
67 changed in read.c . Ideally it shouldn't have to know about it at all,
68 but nothing is ideal around here. */
69
70 const int md_reloc_size = 8; /* Size of relocation record */
71
72 /* Are we trying to generate PIC code? If so, absolute references
73 ought to be made into linkage table references or pc-relative
74 references. */
75 int flag_want_pic;
76
77 static int flag_short_refs; /* -l option */
78 static int flag_long_jumps; /* -S option */
79
80 #ifdef REGISTER_PREFIX_OPTIONAL
81 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
82 #else
83 int flag_reg_prefix_optional;
84 #endif
85
86 /* Its an arbitrary name: This means I don't approve of it */
87 /* See flames below */
88 static struct obstack robyn;
89
90 #define TAB(x,y) (((x)<<2)+(y))
91 #define TABTYPE(xy) ((xy) >> 2)
92 #define BYTE 0
93 #define SHORT 1
94 #define LONG 2
95 #define SZ_UNDEF 3
96 #undef BRANCH
97 /* Case `g' except when BCC68000 is applicable. */
98 #define ABRANCH 1
99 /* Coprocessor branches. */
100 #define FBRANCH 2
101 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
102 supported on all cpus. Widens to 32-bit absolute. */
103 #define PCREL 3
104 /* For inserting an extra jmp instruction with long offset on 68000,
105 for expanding conditional branches. (Not bsr or bra.) Since the
106 68000 doesn't support 32-bit displacements for conditional
107 branches, we fake it by reversing the condition and branching
108 around a jmp with an absolute long operand. */
109 #define BCC68000 4
110 /* For the DBcc "instructions". If the displacement requires 32 bits,
111 the branch-around-a-jump game is played here too. */
112 #define DBCC 5
113 /* Not currently used? */
114 #define PCLEA 6
115 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
116 in 16 or 8 bits. */
117 #define PCINDEX 7
118
119 struct m68k_incant
120 {
121 char *m_operands;
122 unsigned long m_opcode;
123 short m_opnum;
124 short m_codenum;
125 int m_arch;
126 struct m68k_incant *m_next;
127 };
128
129 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
130 #define gettwo(x) (((x)->m_opcode)&0xffff)
131
132 /* Operands we can parse: (And associated modes)
133
134 numb: 8 bit num
135 numw: 16 bit num
136 numl: 32 bit num
137 dreg: data reg 0-7
138 reg: address or data register
139 areg: address register
140 apc: address register, PC, ZPC or empty string
141 num: 16 or 32 bit num
142 num2: like num
143 sz: w or l if omitted, l assumed
144 scale: 1 2 4 or 8 if omitted, 1 assumed
145
146 7.4 IMMED #num --> NUM
147 0.? DREG dreg --> dreg
148 1.? AREG areg --> areg
149 2.? AINDR areg@ --> *(areg)
150 3.? AINC areg@+ --> *(areg++)
151 4.? ADEC areg@- --> *(--areg)
152 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
153 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
154 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
155 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
156 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
157 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
158 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
159 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
160 7.0 ABSL num:sz --> *(num)
161 num --> *(num) (sz L assumed)
162 *** MSCR otherreg --> Magic
163 With -l option
164 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
165 ?.? DINDR dreg@ --> (dreg) -- cas2 only
166
167 examples:
168 #foo #0x35 #12
169 d2
170 a4
171 a3@
172 a5@+
173 a6@-
174 a2@(12) pc@(14)
175 a1@(5,d2:w:1) @(45,d6:l:4)
176 pc@(a2) @(d4)
177 etc . . .
178
179
180 #name@(numw) -->turn into PC rel mode
181 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
182
183 */
184
185 enum operand_type
186 {
187 IMMED = 1,
188 DREG,
189 AREG,
190 AINDR,
191 ADEC,
192 AINC,
193 AOFF,
194 AINDX,
195 APODX,
196 AMIND,
197 APRDX,
198 ABSL,
199 MSCR,
200 REGLST,
201 DINDR
202 };
203
204
205 struct m68k_exp
206 {
207 char *e_beg;
208 char *e_end;
209 segT e_seg;
210 expressionS e_exp;
211 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
212 };
213
214 /* DATA and ADDR have to be contiguous, so that reg-DATA gives
215 0-7==data reg, 8-15==addr reg for operands that take both types.
216
217 We don't use forms like "ADDR0 = ADDR" here because this file is
218 likely to be used on an Apollo, and the broken Apollo compiler
219 gives an `undefined variable' error if we do that, according to
220 troy@cbme.unsw.edu.au. */
221
222 #define DATA DATA0
223 #define ADDR ADDR0
224 #define SP ADDR7
225 #define FPREG FP0
226 #define COPNUM COP0
227 #define BAD BAD0
228 #define BAC BAC0
229
230 enum _register
231 {
232 DATA0 = 1, /* 1- 8 == data registers 0-7 */
233 DATA1,
234 DATA2,
235 DATA3,
236 DATA4,
237 DATA5,
238 DATA6,
239 DATA7,
240
241 ADDR0,
242 ADDR1,
243 ADDR2,
244 ADDR3,
245 ADDR4,
246 ADDR5,
247 ADDR6,
248 ADDR7,
249
250 FP0, /* Eight FP registers */
251 FP1,
252 FP2,
253 FP3,
254 FP4,
255 FP5,
256 FP6,
257 FP7,
258
259 /* Note that COP0==processor #1 -- COP0+7==#8, which stores as 000 */
260 /* I think. . . */
261
262 COP0, /* Co-processor #1-#8 */
263 COP1,
264 COP2,
265 COP3,
266 COP4,
267 COP5,
268 COP6,
269 COP7,
270
271 PC, /* Program counter */
272 ZPC, /* Hack for Program space, but 0 addressing */
273 SR, /* Status Reg */
274 CCR, /* Condition code Reg */
275
276 /* These have to be grouped together for the movec instruction to work. */
277 USP, /* User Stack Pointer */
278 ISP, /* Interrupt stack pointer */
279 SFC,
280 DFC,
281 CACR,
282 VBR,
283 CAAR,
284 MSP,
285 ITT0,
286 ITT1,
287 DTT0,
288 DTT1,
289 MMUSR,
290 TC,
291 SRP,
292 URP,
293 BUSCR, /* 68060 added these */
294 PCR,
295 #define last_movec_reg PCR
296 /* end of movec ordering constraints */
297
298 FPI,
299 FPS,
300 FPC,
301
302 DRP, /* 68851 or 68030 MMU regs */
303 CRP,
304 CAL,
305 VAL,
306 SCC,
307 AC,
308 BAD0,
309 BAD1,
310 BAD2,
311 BAD3,
312 BAD4,
313 BAD5,
314 BAD6,
315 BAD7,
316 BAC0,
317 BAC1,
318 BAC2,
319 BAC3,
320 BAC4,
321 BAC5,
322 BAC6,
323 BAC7,
324 PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040)
325 and ACUSR on 68ec030 */
326 PCSR,
327
328 IC, /* instruction cache token */
329 DC, /* data cache token */
330 NC, /* no cache token */
331 BC, /* both caches token */
332
333 TT0, /* 68030 access control unit regs */
334 TT1,
335 };
336
337 static const enum _register m68000_control_regs[] = { 0 };
338 static const enum _register m68010_control_regs[] = {
339 SFC, DFC, USP, VBR,
340 0
341 };
342 static const enum _register m68020_control_regs[] = {
343 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
344 0
345 };
346 static const enum _register m68040_control_regs[] = {
347 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
348 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
349 0
350 };
351 static const enum _register m68060_control_regs[] = {
352 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
353 USP, VBR, URP, SRP, PCR,
354 0
355 };
356 #define cpu32_control_regs m68010_control_regs
357
358 static const enum _register *control_regs;
359
360 /* Internal form of an operand. */
361 struct m68k_op
362 {
363 char *error; /* Couldn't parse it */
364 enum operand_type mode; /* What mode this instruction is in. */
365 enum _register reg; /* Base register */
366 struct m68k_exp *con1;
367 int ireg; /* Index register */
368 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
369 int imul; /* Multipy ireg by this (1,2,4,or 8) */
370 struct m68k_exp *con2;
371 };
372
373 /* internal form of a 68020 instruction */
374 struct m68k_it
375 {
376 char *error;
377 char *args; /* list of opcode info */
378 int numargs;
379
380 int numo; /* Number of shorts in opcode */
381 short opcode[11];
382
383 struct m68k_op operands[6];
384
385 int nexp; /* number of exprs in use */
386 struct m68k_exp exprs[4];
387
388 int nfrag; /* Number of frags we have to produce */
389 struct
390 {
391 int fragoff; /* Where in the current opcode[] the frag ends */
392 symbolS *fadd;
393 long foff;
394 int fragty;
395 }
396 fragb[4];
397
398 int nrel; /* Num of reloc strucs in use */
399 struct
400 {
401 int n;
402 expressionS exp;
403 char wid;
404 char pcrel;
405 /* In a pc relative address the difference between the address
406 of the offset and the address that the offset is relative
407 to. This depends on the addressing mode. Basically this
408 is the value to put in the offset field to address the
409 first byte of the offset, without regarding the special
410 significance of some values (in the branch instruction, for
411 example). */
412 int pcrel_fix;
413 }
414 reloc[5]; /* Five is enough??? */
415 };
416
417 #define cpu_of_arch(x) ((x) & m68000up)
418 #define float_of_arch(x) ((x) & mfloat)
419 #define mmu_of_arch(x) ((x) & mmmu)
420
421 static struct m68k_it the_ins; /* the instruction being assembled */
422
423 #define seg(exp) ((exp)->e_seg)
424 #define op(exp) ((exp)->e_exp.X_op)
425 #define adds(exp) ((exp)->e_exp.X_add_symbol)
426 #define subs(exp) ((exp)->e_exp.X_op_symbol)
427 #define offs(exp) ((exp)->e_exp.X_add_number)
428
429 /* Macros for adding things to the m68k_it struct */
430
431 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
432
433 /* Like addword, but goes BEFORE general operands */
434 static void
435 insop (w, opcode)
436 int w;
437 struct m68k_incant *opcode;
438 {
439 int z;
440 for(z=the_ins.numo;z>opcode->m_codenum;--z)
441 the_ins.opcode[z]=the_ins.opcode[z-1];
442 for(z=0;z<the_ins.nrel;z++)
443 the_ins.reloc[z].n+=2;
444 for (z = 0; z < the_ins.nfrag; z++)
445 the_ins.fragb[z].fragoff++;
446 the_ins.opcode[opcode->m_codenum]=w;
447 the_ins.numo++;
448 }
449
450 static struct m68k_exp *
451 add_exp (beg, end)
452 char *beg;
453 char *end;
454 {
455 the_ins.exprs[the_ins.nexp].e_beg=beg;
456 the_ins.exprs[the_ins.nexp].e_end=end;
457 return &the_ins.exprs[the_ins.nexp++];
458 }
459
460
461 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
462 Blecch. */
463 static void
464 add_fix (width, exp, pc_rel, pc_fix)
465 char width;
466 struct m68k_exp *exp;
467 int pc_rel;
468 int pc_fix;
469 {
470 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
471 ? (the_ins.numo*2-1)
472 : (((width)=='b')
473 ? (the_ins.numo*2+1)
474 : (the_ins.numo*2)));
475 the_ins.reloc[the_ins.nrel].exp = exp->e_exp;
476 the_ins.reloc[the_ins.nrel].wid = width;
477 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
478 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
479 }
480
481 /* Cause an extra frag to be generated here, inserting up to 10 bytes
482 (that value is chosen in the frag_var call in md_assemble). TYPE
483 is the subtype of the frag to be generated; its primary type is
484 rs_machine_dependent.
485
486 The TYPE parameter is also used by md_convert_frag_1 and
487 md_estimate_size_before_relax. The appropriate type of fixup will
488 be emitted by md_convert_frag_1.
489
490 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
491 static void
492 add_frag(add,off,type)
493 symbolS *add;
494 long off;
495 int type;
496 {
497 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
498 the_ins.fragb[the_ins.nfrag].fadd=add;
499 the_ins.fragb[the_ins.nfrag].foff=off;
500 the_ins.fragb[the_ins.nfrag++].fragty=type;
501 }
502
503 #define isvar(exp) \
504 ((exp) && op (exp) != O_constant && op (exp) != O_big)
505
506 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
507 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
508 static int get_regs PARAMS ((int i, char *str, struct m68k_op *opP));
509 static int reverse_16_bits PARAMS ((int in));
510 static int reverse_8_bits PARAMS ((int in));
511 static int try_index PARAMS ((char **s, struct m68k_op *opP));
512 static void install_gen_operand PARAMS ((int mode, int val));
513 static void install_operand PARAMS ((int mode, int val));
514 static void s_bss PARAMS ((int));
515 static void s_data1 PARAMS ((int));
516 static void s_data2 PARAMS ((int));
517 static void s_even PARAMS ((int));
518 static void s_proc PARAMS ((int));
519
520 static int current_architecture;
521
522 struct m68k_cpu {
523 unsigned long arch;
524 const char *name;
525 };
526
527 static const struct m68k_cpu archs[] = {
528 { m68000, "68000" },
529 { m68010, "68010" },
530 { m68020, "68020" },
531 { m68030, "68030" },
532 { m68040, "68040" },
533 { m68060, "68060" },
534 { cpu32, "cpu32" },
535 { m68881, "68881" },
536 { m68851, "68851" },
537 /* Aliases (effectively, so far as gas is concerned) for the above
538 cpus. */
539 { m68020, "68k" },
540 { m68000, "68302" },
541 { m68000, "68008" },
542 { cpu32, "68331" },
543 { cpu32, "68332" },
544 { cpu32, "68333" },
545 { cpu32, "68340" },
546 { cpu32, "68360" },
547 { m68881, "68882" },
548 };
549
550 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
551
552 /* BCC68000 is for patching in an extra jmp instruction for long offsets
553 on the 68000. The 68000 doesn't support long branches with branchs */
554
555 /* This table desribes how you change sizes for the various types of variable
556 size expressions. This version only supports two kinds. */
557
558 /* Note that calls to frag_var need to specify the maximum expansion
559 needed; this is currently 10 bytes for DBCC. */
560
561 /* The fields are:
562 How far Forward this mode will reach:
563 How far Backward this mode will reach:
564 How many bytes this mode will add to the size of the frag
565 Which mode to go to if the offset won't fit in this one
566 */
567 relax_typeS md_relax_table[] =
568 {
569 {1, 1, 0, 0}, /* First entries aren't used */
570 {1, 1, 0, 0}, /* For no good reason except */
571 {1, 1, 0, 0}, /* that the VAX doesn't either */
572 {1, 1, 0, 0},
573
574 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
575 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
576 {0, 0, 4, 0},
577 {1, 1, 0, 0},
578
579 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
580 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
581 {0, 0, 4, 0},
582 {1, 1, 0, 0},
583
584 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
585 {(32767), (-32768), 2, TAB (PCREL, LONG)},
586 {0, 0, 4, 0},
587 {1, 1, 0, 0},
588
589 {(127), (-128), 0, TAB (BCC68000, SHORT)},
590 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
591 {0, 0, 6, 0}, /* jmp long space */
592 {1, 1, 0, 0},
593
594 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
595 {(32767), (-32768), 2, TAB (DBCC, LONG)},
596 {0, 0, 10, 0}, /* bra/jmp long space */
597 {1, 1, 0, 0},
598
599 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
600 {32767, -32768, 2, TAB (PCLEA, LONG)},
601 {0, 0, 6, 0},
602 {1, 1, 0, 0},
603
604 /* For, e.g., jmp pcrel indexed. */
605 {125, -130, 0, TAB (PCINDEX, SHORT)},
606 {32765, -32770, 2, TAB (PCINDEX, LONG)},
607 {0, 0, 4, 0},
608 {1, 1, 0, 0},
609 };
610
611 /* These are the machine dependent pseudo-ops. These are included so
612 the assembler can work on the output from the SUN C compiler, which
613 generates these.
614 */
615
616 /* This table describes all the machine specific pseudo-ops the assembler
617 has to support. The fields are:
618 pseudo-op name without dot
619 function to call to execute this pseudo-op
620 Integer arg to pass to the function
621 */
622 CONST pseudo_typeS md_pseudo_table[] =
623 {
624 {"data1", s_data1, 0},
625 {"data2", s_data2, 0},
626 {"bss", s_bss, 0},
627 {"even", s_even, 0},
628 {"skip", s_space, 0},
629 {"proc", s_proc, 0},
630 #ifdef TE_SUN3
631 {"align", s_align_bytes, 0},
632 #endif
633 #ifdef OBJ_ELF
634 {"swbeg", s_ignore, 0},
635 #endif
636 {0, 0, 0}
637 };
638
639
640 /* The mote pseudo ops are put into the opcode table, since they
641 don't start with a . they look like opcodes to gas.
642 */
643 extern void obj_coff_section ();
644
645 CONST pseudo_typeS mote_pseudo_table[] =
646 {
647
648 {"dcl", cons, 4},
649 {"dc", cons, 2},
650 {"dcw", cons, 2},
651 {"dcb", cons, 1},
652
653 {"dsl", s_space, 4},
654 {"ds", s_space, 2},
655 {"dsw", s_space, 2},
656 {"dsb", s_space, 1},
657
658 {"xdef", s_globl, 0},
659 {"align", s_align_ptwo, 0},
660 #ifdef M68KCOFF
661 {"sect", obj_coff_section, 0},
662 {"section", obj_coff_section, 0},
663 #endif
664 {0, 0, 0}
665 };
666
667 #define issbyte(x) ((x)>=-128 && (x)<=127)
668 #define isubyte(x) ((x)>=0 && (x)<=255)
669 #define issword(x) ((x)>=-32768 && (x)<=32767)
670 #define isuword(x) ((x)>=0 && (x)<=65535)
671
672 #define isbyte(x) ((x)>= -255 && (x)<=255)
673 #define isword(x) ((x)>=-32768 && (x)<=65535)
674 #define islong(x) (1)
675
676 extern char *input_line_pointer;
677
678 enum
679 {
680 FAIL = 0,
681 OK = 1,
682 };
683
684 static char mklower_table[256];
685 #define mklower(c) (mklower_table[(unsigned char)(c)])
686 static char notend_table[256];
687 static char alt_notend_table[256];
688 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
689 alt_notend_table[(unsigned char)(s[1])])))
690
691 /* JF modified this to handle cases where the first part of a symbol name
692 looks like a register */
693
694 /*
695 * m68k_reg_parse() := if it looks like a register, return it's token &
696 * advance the pointer.
697 */
698
699 enum _register
700 m68k_reg_parse (ccp)
701 register char **ccp;
702 {
703 char *start = *ccp;
704 char c;
705 char *p;
706 symbolS *symbolP;
707
708 if (flag_reg_prefix_optional)
709 {
710 if (*start == REGISTER_PREFIX)
711 start++;
712 p = start;
713 }
714 else
715 {
716 if (*start != REGISTER_PREFIX)
717 return FAIL;
718 p = start + 1;
719 }
720
721 if (!isalpha (*p) || !is_name_beginner (*p))
722 return FAIL;
723
724 c = *p++;
725 while (isalpha (c) || isdigit (c) || c == '_')
726 {
727 c = *p++;
728 }
729
730 *--p = 0;
731 symbolP = symbol_find (start);
732 *p = c;
733
734 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
735 {
736 *ccp = p;
737 return S_GET_VALUE (symbolP);
738 }
739
740 return FAIL;
741 }
742
743 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
744 #define SKIP_W() { ss++; if(*ss==' ') ss++;}
745
746 /* Parse an index specification using Motorola syntax. */
747
748 static int
749 try_moto_index (s, opP)
750 char **s;
751 struct m68k_op *opP;
752 {
753 register int i;
754 char *ss;
755
756 ss = *s;
757 /* SKIP_W(); */
758 if (*ss == ' ')
759 ss++;
760 i = m68k_reg_parse (&ss);
761 if (!(i >= DATA + 0 && i <= ADDR + 7))
762 { /* if i is not DATA or ADDR reg */
763 opP->error = "Invalid index register";
764 *s = ss;
765 return FAIL;
766 }
767 opP->ireg = i;
768 /* SKIP_W(); */
769 if (*ss == ')')
770 {
771 opP->isiz = 0;
772 opP->imul = 1;
773 SKIP_W ();
774 *s = ss;
775 return OK;
776 }
777 if (*ss != '.')
778 {
779 opP->error = "Missing . in index register";
780 *s = ss;
781 return FAIL;
782 }
783 SKIP_W ();
784 if (mklower (*ss) == 'w')
785 opP->isiz = 2;
786 else if (mklower (*ss) == 'l')
787 opP->isiz = 3;
788 else
789 {
790 opP->error = "Size spec not .W or .L";
791 *s = ss;
792 return FAIL;
793 }
794 SKIP_W ();
795 if (*ss == '.' || *ss == '*')
796 {
797 SKIP_W ();
798 switch (*ss)
799 {
800 case '1':
801 case '2':
802 case '4':
803 case '8':
804 opP->imul = *ss - '0';
805 break;
806 default:
807 opP->error = "index multiplier not 1, 2, 4 or 8";
808 *s = ss;
809 return FAIL;
810 }
811 SKIP_W ();
812 }
813 else
814 opP->imul = 1;
815 if (*ss != ')')
816 {
817 opP->error = "Missing )";
818 *s = ss;
819 return FAIL;
820 }
821 SKIP_W ();
822 *s = ss;
823 return OK;
824 }
825
826 /*
827 *
828 * try_index := data_or_address_register + ')' + SKIP_W
829 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
830 *
831 * multiplier := <empty>
832 * | ':' + multiplier_number
833 * ;
834 *
835 * multiplier_number := '1' | '2' | '4' | '8' ;
836 *
837 * size_spec := 'l' | 'L' | 'w' | 'W' ;
838 *
839 * SKIP_W := <empty> | ' ' ;
840 *
841 */
842
843 static int
844 try_index (s, opP)
845 char **s;
846 struct m68k_op *opP;
847 {
848 register int i;
849 char *ss;
850
851 ss = *s;
852 /* SKIP_W(); */
853 i = m68k_reg_parse (&ss);
854 if (!(i >= DATA + 0 && i <= ADDR + 7))
855 { /* if i is not DATA or ADDR reg */
856 *s = ss;
857 return FAIL;
858 }
859 opP->ireg = i;
860 /* SKIP_W(); */
861 if (*ss == ')')
862 {
863 opP->isiz = 0;
864 opP->imul = 1;
865 SKIP_W ();
866 *s = ss;
867 return OK;
868 }
869 if (*ss != ':')
870 {
871 opP->error = "Missing : in index register";
872 *s = ss;
873 return FAIL;
874 }
875 SKIP_W ();
876 switch (*ss)
877 {
878 case 'w':
879 case 'W':
880 opP->isiz = 2;
881 break;
882 case 'l':
883 case 'L':
884 opP->isiz = 3;
885 break;
886 default:
887 opP->error = "Index register size spec not :w or :l";
888 *s = ss;
889 return FAIL;
890 }
891 SKIP_W ();
892 if (*ss == ':')
893 {
894 SKIP_W ();
895 switch (*ss)
896 {
897 case '1':
898 case '2':
899 case '4':
900 case '8':
901 if (cpu_of_arch (current_architecture) < m68020)
902 {
903 opP->error = "no index scaling in pre-68020's";
904 *s = ss;
905 return FAIL;
906 }
907 opP->imul = *ss - '0';
908 break;
909 default:
910 opP->error = "index multiplier not 1, 2, 4 or 8";
911 *s = ss;
912 return FAIL;
913 }
914 SKIP_W ();
915 }
916 else
917 opP->imul = 1;
918 if (*ss != ')')
919 {
920 opP->error = "Missing )";
921 *s = ss;
922 return FAIL;
923 }
924 SKIP_W ();
925 *s = ss;
926 return OK;
927 } /* try_index() */
928
929 /* Ian Taylor expanded this function to accept both MIT and Motorola
930 syntax. I removed the old comment, since it was wrong. The syntax
931 this accepted even before my changes was complex and undocumented.
932 I mainly added a large case when the operand string does not
933 contain an '@', since the Motorola syntax does not use the '@'
934 character. */
935
936 int
937 m68k_ip_op (str, opP)
938 char *str;
939 register struct m68k_op *opP;
940 {
941 char *strend;
942 long i;
943 char *parse_index ();
944 int needp;
945
946 if (*str == ' ')
947 {
948 str++;
949 } /* Find the beginning of the string */
950
951 if (!*str)
952 {
953 opP->error = "Missing operand";
954 return FAIL;
955 } /* Out of gas */
956
957 for (strend = str; *strend; strend++)
958 ;
959 --strend;
960
961 if (*str == '#' || *str == '&')
962 {
963 str++;
964 opP->con1 = add_exp (str, strend);
965 opP->mode = IMMED;
966 return OK;
967 } /* Guess what: A constant. Shar and enjoy */
968
969 i = m68k_reg_parse (&str);
970
971 if (i != FAIL)
972 {
973 if (*str == '/' || *str == '-')
974 {
975 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
976 opP->mode = REGLST;
977 return get_regs (i, str, opP);
978 }
979 if (*str == '\0')
980 {
981 opP->reg = i;
982 /* "Rn" Register Direct mode */
983 if (i >= DATA + 0 && i <= DATA + 7)
984 opP->mode = DREG;
985 else if (i >= ADDR + 0 && i <= ADDR + 7)
986 opP->mode = AREG;
987 else
988 opP->mode = MSCR;
989 return OK;
990 }
991 }
992
993 if (*str != '@')
994 {
995 char *stmp;
996
997 if ((stmp = strchr (str, '@')) != 0)
998 {
999 opP->con1 = add_exp (str, stmp - 1);
1000 if (stmp == strend)
1001 {
1002 opP->mode = AINDX;
1003 return (OK);
1004 }
1005
1006 if ((current_architecture & m68020up) == 0)
1007 {
1008 return (FAIL);
1009 } /* if target is not a '20 or better */
1010
1011 stmp++;
1012 if (*stmp++ != '(' || *strend-- != ')')
1013 {
1014 opP->error = "Malformed operand";
1015 return (FAIL);
1016 }
1017 i = try_index (&stmp, opP);
1018 opP->con2 = add_exp (stmp, strend);
1019
1020 if (i == FAIL)
1021 {
1022 opP->mode = AMIND;
1023 }
1024 else
1025 {
1026 opP->mode = APODX;
1027 }
1028 return (OK);
1029 } /* if there's an '@' */
1030
1031 #ifndef MIT_SYNTAX_ONLY
1032 /* The operand has no '@'. Try to parse it using
1033 Motorola syntax. */
1034 /* Logic of the parsing switch(*str):
1035 case opP->mode =
1036 ---- -----------
1037 #anything IMMED 1
1038 REG AREG or DREG or MSCR 3 or 2 or 13
1039 REG- or REG/ REGLST 14
1040 (REG) AINDR 4
1041 (REG)+ AINC 6
1042 (REG,INDX) AINDX 8
1043 (EXPR,REG) AOFF 7
1044 (EXPR,REG,INDX) AINDX 8
1045 -(REG) ADEC 5
1046 EXP2(REG) AOFF 7
1047 EXP2(REG,INDX) AINDX 8
1048 EXP2 ABSL 12
1049
1050 REG means truth(m68k_reg_parse(&str))
1051 INDX means truth(try_moto_index(&str,opP))
1052 EXPR means not REG
1053 EXP2 means not REG and not '(' and not '-('
1054 */
1055
1056 if (*str == '(')
1057 {
1058 str++;
1059 i = m68k_reg_parse (&str);
1060 if ((i < ADDR + 0 || i > ADDR + 7)
1061 && (i < DATA + 0 || i > DATA + 7
1062 || *str != ')' || str[1] != '0')
1063 && i != PC && i != ZPC && i != FAIL)
1064 {
1065 /* Can't indirect off non address regs */
1066 opP->error = "Invalid indirect register";
1067 return FAIL;
1068 }
1069 if (i != FAIL)
1070 {
1071 opP->reg = i;
1072 if (*str == ')')
1073 {
1074 str++;
1075 if (*str == '\0')
1076 {
1077 /* "(An)" Address Register Indirect mode
1078 or "(Dn)" for cas2. */
1079 if (i >= DATA + 0 && i <= DATA + 7)
1080 opP->mode = DINDR;
1081 else
1082 opP->mode = AINDR;
1083 return OK;
1084 }
1085 if (*str == '+')
1086 {
1087 if (str[1] == '\0')
1088 {
1089 /* "(An)+" Register Indirect w Postincrement */
1090 opP->mode = AINC;
1091 return OK;
1092 }
1093 }
1094 opP->error = "Junk after indirect";
1095 return FAIL;
1096 }
1097 if (*str == ',')
1098 {
1099 str++;
1100 i = try_moto_index (&str, opP);
1101 if (i == FAIL)
1102 return FAIL;
1103 /* "(An,Rn)" Register Indirect with Index mode*/
1104 opP->mode = AINDX;
1105 return OK;
1106 }
1107 else
1108 {
1109 opP->error = "Bad indirect syntax";
1110 return FAIL;
1111 }
1112 }
1113 else
1114 {
1115 /* "(EXPR,..." , a displacement */
1116 char *stmp;
1117
1118 if ((stmp = strchr (str, ',')) != NULL)
1119 {
1120 opP->con1 = add_exp (str, stmp - 1);
1121 str = stmp;
1122 SKIP_WHITE ();
1123 i = m68k_reg_parse (&str);
1124 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC)
1125 {
1126 /* Can't indirect off non address regs */
1127 opP->error = "Invalid indirect register";
1128 return FAIL;
1129 }
1130 if (i != FAIL)
1131 {
1132 opP->reg = i;
1133 if (*str == ')')
1134 {
1135 /* "(d,An)" Register Indirect w Displacement */
1136 opP->mode = AOFF;
1137 return OK;
1138 }
1139 if (*str == ',')
1140 {
1141 str++;
1142 i = try_moto_index (&str, opP);
1143 if (i == FAIL)
1144 return FAIL;
1145 /* "(d,An,Rn)" Register Indirect with Index */
1146 opP->mode = AINDX;
1147 return OK;
1148 }
1149 else
1150 {
1151 opP->error = "Bad indirect syntax";
1152 return FAIL;
1153 }
1154 }
1155 else
1156 {
1157 opP->error = "Invalid register";
1158 return FAIL;
1159 }
1160 }
1161 else
1162 {
1163 opP->mode = ABSL;
1164 opP->con1 = add_exp (str - 1, strend);
1165 return OK;
1166 }
1167 }
1168 }
1169
1170 if (*str == '-')
1171 {
1172 if (str[1] == '(')
1173 {
1174 str = str + 2;
1175 i = m68k_reg_parse (&str);
1176 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL)
1177 {
1178 /* Can't indirect off non address regs */
1179 opP->error = "Invalid indirect register";
1180 return FAIL;
1181 }
1182 if (i != FAIL)
1183 {
1184 opP->reg = i;
1185 if (*str == ')')
1186 {
1187 str++;
1188 if (*str == '\0')
1189 {
1190 /* "-(An)" Register Indirect with Predecrement */
1191 opP->mode = ADEC;
1192 return OK;
1193 }
1194 opP->error = "Junk after indirect";
1195 return FAIL;
1196 }
1197 opP->error = "Bad indirect syntax";
1198 return FAIL;
1199 }
1200 opP->mode = ABSL;
1201 opP->con1 = add_exp (str - 2, strend);
1202 return OK;
1203 }
1204 /* if '-' but not "-(', do nothing */
1205 }
1206
1207 /* whether *str=='-' or not */
1208 {
1209 /* "EXP2" or "EXP2(REG..." */
1210 char *stmp;
1211 if ((stmp = strchr (str, '(')) != NULL)
1212 {
1213 char *ostr = str;
1214
1215 opP->con1 = add_exp (str, stmp - 1);
1216 str = stmp + 1;
1217 i = m68k_reg_parse (&str);
1218 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC
1219 && i != ZPC && i != FAIL)
1220 {
1221 /* Can't indirect off non address regs */
1222 opP->error = "Invalid indirect register";
1223 return FAIL;
1224 }
1225 if (i != FAIL)
1226 {
1227 opP->reg = i;
1228 if (*str == ')')
1229 {
1230 /* "d(An)" Register Indirect w Displacement */
1231 opP->mode = AOFF;
1232 return OK;
1233 }
1234 if (*str == ',')
1235 {
1236 str++;
1237 i = try_moto_index (&str, opP);
1238 if (i == FAIL)
1239 return FAIL;
1240 /* "d(An,Rn)" Register Indirect with Index */
1241 opP->mode = AINDX;
1242 return OK;
1243 }
1244 else
1245 {
1246 opP->error = "Bad indirect syntax";
1247 return FAIL;
1248 }
1249 }
1250 else
1251 {
1252 opP->mode = ABSL;
1253 opP->con1 = add_exp (ostr, strend);
1254 return OK;
1255 }
1256 }
1257 else
1258 {
1259 /* "EXP2" Absolute */
1260 opP->mode = ABSL;
1261 opP->isiz = 0;
1262 if (strend[-1] == '.' || strend[-1] == ':')
1263 {
1264 /* mode ==foo.[wl] */
1265 switch (*strend)
1266 {
1267 case 'w':
1268 case 'W':
1269 opP->isiz = 2;
1270 break;
1271 case 'l':
1272 case 'L':
1273 opP->isiz = 3;
1274 break;
1275 }
1276 }
1277 opP->con1 = add_exp (str, strend);
1278 return OK;
1279 }
1280 }
1281 /*NOTREACHED*/
1282 #else /* defined (MIT_SYNTAX_ONLY) */
1283 opP->mode = ABSL;
1284 opP->con1 = add_exp (str, strend);
1285 return OK;
1286 #endif /* defined (MIT_SYNTAX_ONLY) */
1287 }
1288
1289 opP->reg = i;
1290
1291 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1292 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL
1293 && (str[1] != '\0' || i < DATA + 0 || i > DATA + 7))
1294 {
1295 opP->error = "Invalid indirect register";
1296 return FAIL;
1297 }
1298 know (*str == '@');
1299
1300 str++;
1301 switch (*str)
1302 {
1303 case '\0':
1304 if (i < DATA + 0 || i > DATA + 7)
1305 opP->mode = AINDR;
1306 else
1307 opP->mode = DINDR;
1308 return OK;
1309 case '-':
1310 opP->mode = ADEC;
1311 return OK;
1312 case '+':
1313 opP->mode = AINC;
1314 return OK;
1315 case '(':
1316 str++;
1317 break;
1318 default:
1319 opP->error = "Junk after indirect";
1320 return FAIL;
1321 }
1322 /* Some kind of indexing involved. Lets find out how bad it is */
1323 i = try_index (&str, opP);
1324 /* Didn't start with an index reg, maybe its offset or offset,reg */
1325 if (i == FAIL)
1326 {
1327 char *beg_str;
1328
1329 beg_str = str;
1330 for (i = 1; i;)
1331 {
1332 switch (*str++)
1333 {
1334 case '\0':
1335 opP->error = "Missing )";
1336 return FAIL;
1337 case ',':
1338 i = 0;
1339 break;
1340 case '(':
1341 i++;
1342 break;
1343 case ')':
1344 --i;
1345 break;
1346 }
1347 }
1348 opP->con1 = add_exp (beg_str, str - 2);
1349 /* Should be offset,reg */
1350 if (str[-1] == ',')
1351 {
1352 i = try_index (&str, opP);
1353 if (i == FAIL)
1354 {
1355 opP->error = "Malformed index reg";
1356 return FAIL;
1357 }
1358 }
1359 }
1360 /* We've now got offset) offset,reg) or reg) */
1361
1362 if (*str == '\0')
1363 {
1364 /* Th-the-thats all folks */
1365 if (opP->reg == FAIL)
1366 opP->mode = AINDX; /* Other form of indirect */
1367 else if (opP->ireg == FAIL)
1368 opP->mode = AOFF;
1369 else
1370 opP->mode = AINDX;
1371 return (OK);
1372 }
1373 /* Next thing had better be another @ */
1374 if (*str == '@')
1375 {
1376 if (str[1] == '(')
1377 {
1378 needp = 1;
1379 str += 2;
1380 }
1381 else
1382 {
1383 needp = 0;
1384 str++;
1385 }
1386 }
1387
1388 if ((current_architecture & m68020up) == 0)
1389 {
1390 return (FAIL);
1391 } /* if target is not a '20 or better */
1392
1393
1394 if (opP->ireg != FAIL)
1395 {
1396 opP->mode = APRDX;
1397
1398 i = try_index (&str, opP);
1399 if (i != FAIL)
1400 {
1401 opP->error = "Two index registers! not allowed!";
1402 return (FAIL);
1403 }
1404 }
1405 else
1406 {
1407 i = try_index (&str, opP);
1408 }
1409
1410 if (i == FAIL)
1411 {
1412 char *beg_str;
1413
1414 beg_str = str;
1415
1416 for (i = 1; i;)
1417 {
1418 switch (*str++)
1419 {
1420 case '\0':
1421 if (needp)
1422 opP->error = "Missing )";
1423 return (FAIL);
1424 break;
1425 case ',':
1426 i = 0;
1427 break;
1428 case '(':
1429 i++;
1430 break;
1431 case ')':
1432 --i;
1433 break;
1434 }
1435 }
1436
1437 opP->con2 = add_exp (beg_str, str - 2);
1438
1439 if (str[-1] == ',')
1440 {
1441 if (opP->ireg != FAIL)
1442 {
1443 opP->error = "Can't have two index regs";
1444 return (FAIL);
1445 }
1446
1447 i = try_index (&str, opP);
1448
1449 if (i == FAIL)
1450 {
1451 opP->error = "malformed index reg";
1452 return (FAIL);
1453 }
1454
1455 opP->mode = APODX;
1456 }
1457 else if (opP->ireg != FAIL)
1458 {
1459 opP->mode = APRDX;
1460 }
1461 else
1462 {
1463 opP->mode = AMIND;
1464 }
1465 }
1466 else
1467 {
1468 opP->mode = APODX;
1469 }
1470
1471 if (*str != '\0')
1472 {
1473 opP->error = "Junk after indirect";
1474 return FAIL;
1475 }
1476 return (OK);
1477 }
1478
1479
1480 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
1481
1482 #ifdef NO_PCREL_RELOCS
1483
1484 int
1485 make_pcrel_absolute(fixP, add_number)
1486 fixS *fixP;
1487 long *add_number;
1488 {
1489 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
1490
1491 /* rewrite the PC relative instructions to absolute address ones.
1492 * these are rumoured to be faster, and the apollo linker refuses
1493 * to deal with the PC relative relocations.
1494 */
1495 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
1496 {
1497 opcode[0] = 0x4e;
1498 opcode[1] = 0xf9;
1499 }
1500 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
1501 {
1502 opcode[0] = 0x4e;
1503 opcode[1] = 0xb9;
1504 }
1505 else
1506 as_fatal ("Unknown PC relative instruction");
1507 *add_number -= 4;
1508 return 0;
1509 }
1510
1511 #endif /* NO_PCREL_RELOCS */
1512
1513 short
1514 tc_coff_fix2rtype (fixP)
1515 fixS *fixP;
1516 {
1517 #ifdef NO_PCREL_RELOCS
1518 know (fixP->fx_pcrel == 0);
1519 return (fixP->fx_size == 1 ? R_RELBYTE
1520 : fixP->fx_size == 2 ? R_DIR16
1521 : R_DIR32);
1522 #else
1523 return (fixP->fx_pcrel ?
1524 (fixP->fx_size == 1 ? R_PCRBYTE :
1525 fixP->fx_size == 2 ? R_PCRWORD :
1526 R_PCRLONG) :
1527 (fixP->fx_size == 1 ? R_RELBYTE :
1528 fixP->fx_size == 2 ? R_RELWORD :
1529 R_RELLONG));
1530 #endif
1531 }
1532
1533 #endif
1534
1535 #ifdef BFD_ASSEMBLER
1536
1537 arelent *
1538 tc_gen_reloc (section, fixp)
1539 asection *section;
1540 fixS *fixp;
1541 {
1542 arelent *reloc;
1543 bfd_reloc_code_real_type code;
1544
1545 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1546 switch (F (fixp->fx_size, fixp->fx_pcrel))
1547 {
1548 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1549 MAP (1, 0, BFD_RELOC_8);
1550 MAP (2, 0, BFD_RELOC_16);
1551 MAP (4, 0, BFD_RELOC_32);
1552 MAP (1, 1, BFD_RELOC_8_PCREL);
1553 MAP (2, 1, BFD_RELOC_16_PCREL);
1554 MAP (4, 1, BFD_RELOC_32_PCREL);
1555 default:
1556 abort ();
1557 }
1558
1559 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
1560 assert (reloc != 0);
1561 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
1562 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1563 if (fixp->fx_pcrel)
1564 reloc->addend = fixp->fx_addnumber;
1565 else
1566 reloc->addend = 0;
1567
1568 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1569 assert (reloc->howto != 0);
1570
1571 return reloc;
1572 }
1573
1574 #endif /* BFD_ASSEMBLER */
1575
1576 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1577 main ()
1578 {
1579 char buf[128];
1580 struct m68k_op thark;
1581
1582 for (;;)
1583 {
1584 if (!gets (buf))
1585 break;
1586 memset (&thark, '\0', sizeof (thark));
1587 if (!m68k_ip_op (buf, &thark))
1588 printf ("FAIL:");
1589 if (thark.error)
1590 printf ("op1 error %s in %s\n", thark.error, buf);
1591 printf ("mode %d, reg %d, ", thark.mode, thark.reg);
1592 if (thark.b_const)
1593 printf ("Constant: '%.*s',", 1 + thark.e_const - thark.b_const, thark.b_const);
1594 printf ("ireg %d, isiz %d, imul %d ", thark.ireg, thark.isiz, thark.imul);
1595 if (thark.b_iadd)
1596 printf ("Iadd: '%.*s'", 1 + thark.e_iadd - thark.b_iadd, thark.b_iadd);
1597 printf ("\n");
1598 }
1599 exit (EXIT_SUCCESS);
1600 }
1601
1602 #endif
1603
1604
1605 /* Handle of the OPCODE hash table. NULL means any use before
1606 m68k_ip_begin() will crash. */
1607 static struct hash_control *op_hash;
1608 \f
1609
1610 /*
1611 * m 6 8 k _ i p ( )
1612 *
1613 * This converts a string into a 68k instruction.
1614 * The string must be a bare single instruction in sun format
1615 * with RMS-style 68020 indirects
1616 * (example: )
1617 *
1618 * It provides some error messages: at most one fatal error message (which
1619 * stops the scan) and at most one warning message for each operand.
1620 * The 68k instruction is returned in exploded form, since we have no
1621 * knowledge of how you parse (or evaluate) your expressions.
1622 * We do however strip off and decode addressing modes and operation
1623 * mnemonic.
1624 *
1625 * This function's value is a string. If it is not "" then an internal
1626 * logic error was found: read this code to assign meaning to the string.
1627 * No argument string should generate such an error string:
1628 * it means a bug in our code, not in the user's text.
1629 *
1630 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1631 * this function.
1632 */
1633
1634 /* JF this function no longer returns a useful value. Sorry */
1635 void
1636 m68k_ip (instring)
1637 char *instring;
1638 {
1639 register char *p;
1640 register struct m68k_op *opP;
1641 register struct m68k_incant *opcode;
1642 register char *s;
1643 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1644 char *pdot, *pdotmove;
1645 int siz1, siz2;
1646 char c;
1647 int losing;
1648 int opsfound;
1649 char *crack_operand ();
1650 LITTLENUM_TYPE words[6];
1651 LITTLENUM_TYPE *wordp;
1652 unsigned long ok_arch = 0;
1653
1654 if (*instring == ' ')
1655 instring++; /* skip leading whitespace */
1656
1657 /* Scan up to end of operation-code, which MUST end in end-of-string
1658 or exactly 1 space. */
1659 pdot = 0;
1660 for (p = instring; *p != '\0'; p++)
1661 {
1662 if (*p == ' ')
1663 break;
1664 if (*p == '.')
1665 pdot = p;
1666 }
1667
1668 if (p == instring)
1669 {
1670 the_ins.error = "No operator";
1671 the_ins.opcode[0] = 0;
1672 /* the_ins.numo=1; */
1673 return;
1674 }
1675
1676 /* p now points to the end of the opcode name, probably whitespace.
1677 make sure the name is null terminated by clobbering the whitespace,
1678 look it up in the hash table, then fix it back.
1679 Remove a dot, first, since the opcode tables have none. */
1680 if (pdot != NULL)
1681 {
1682 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1683 *pdotmove = pdotmove[1];
1684 p--;
1685 }
1686
1687 c = *p;
1688 *p = '\0';
1689 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
1690 *p = c;
1691
1692 if (pdot != NULL)
1693 {
1694 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1695 *pdotmove = pdotmove[-1];
1696 *pdot = '.';
1697 ++p;
1698 }
1699
1700 if (opcode == NULL)
1701 {
1702 the_ins.error = "Unknown operator";
1703 the_ins.opcode[0] = 0;
1704 /* the_ins.numo=1; */
1705 return;
1706 }
1707
1708 /* found a legitimate opcode, start matching operands */
1709 while (*p == ' ')
1710 ++p;
1711
1712
1713 if (opcode->m_operands == 0)
1714 {
1715 char *old = input_line_pointer;
1716 *old = '\n';
1717 input_line_pointer = p;
1718 /* Ahh - it's a motorola style psuedo op */
1719 mote_pseudo_table[opcode->m_opnum].poc_handler
1720 (mote_pseudo_table[opcode->m_opnum].poc_val);
1721 input_line_pointer = old;
1722 *old = 0;
1723
1724 return;
1725 }
1726
1727 for (opP = &the_ins.operands[0]; *p; opP++)
1728 {
1729
1730 p = crack_operand (p, opP);
1731
1732 if (opP->error)
1733 {
1734 the_ins.error = opP->error;
1735 return;
1736 }
1737 }
1738
1739 opsfound = opP - &the_ins.operands[0];
1740
1741 /* This ugly hack is to support the floating pt opcodes in their standard form */
1742 /* Essentially, we fake a first enty of type COP#1 */
1743 if (opcode->m_operands[0] == 'I')
1744 {
1745 int n;
1746
1747 for (n = opsfound; n > 0; --n)
1748 the_ins.operands[n] = the_ins.operands[n - 1];
1749
1750 memset ((char *) (&the_ins.operands[0]), '\0', sizeof (the_ins.operands[0]));
1751 the_ins.operands[0].mode = MSCR;
1752 the_ins.operands[0].reg = COPNUM; /* COP #1 */
1753 opsfound++;
1754 }
1755
1756 /* We've got the operands. Find an opcode that'll accept them */
1757 for (losing = 0;;)
1758 {
1759 /* If we didn't get the right number of ops, or we have no
1760 common model with this pattern then reject this pattern. */
1761
1762 if (opsfound != opcode->m_opnum
1763 || ((opcode->m_arch & current_architecture) == 0))
1764 {
1765 ++losing;
1766 ok_arch |= opcode->m_arch;
1767 }
1768 else
1769 {
1770 for (s = opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++)
1771 {
1772 /* Warning: this switch is huge! */
1773 /* I've tried to organize the cases into this order:
1774 non-alpha first, then alpha by letter. Lower-case
1775 goes directly before uppercase counterpart. */
1776 /* Code with multiple case ...: gets sorted by the lowest
1777 case ... it belongs to. I hope this makes sense. */
1778 switch (*s)
1779 {
1780 case '!':
1781 if (opP->mode == MSCR || opP->mode == IMMED
1782 || opP->mode == DREG || opP->mode == AREG
1783 || opP->mode == AINC || opP->mode == ADEC
1784 || opP->mode == REGLST)
1785 losing++;
1786 break;
1787
1788 case '`':
1789 switch (opP->mode)
1790 {
1791 case MSCR:
1792 case IMMED:
1793 case DREG:
1794 case AREG:
1795 case AINC:
1796 case REGLST:
1797 case AINDR:
1798 losing++;
1799 break;
1800 default:
1801 break;
1802 }
1803 break;
1804
1805 case '#':
1806 if (opP->mode != IMMED)
1807 losing++;
1808 else
1809 {
1810 long t;
1811
1812 t = get_num (opP->con1, 80);
1813 if (s[1] == 'b' && !isbyte (t))
1814 losing++;
1815 else if (s[1] == 'w' && !isword (t))
1816 losing++;
1817 }
1818 break;
1819
1820 case '^':
1821 case 'T':
1822 if (opP->mode != IMMED)
1823 losing++;
1824 break;
1825
1826 case '$':
1827 if (opP->mode == MSCR || opP->mode == AREG ||
1828 opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1829 losing++;
1830 break;
1831
1832 case '%':
1833 if (opP->mode == MSCR || opP->reg == PC ||
1834 opP->reg == ZPC || opP->mode == REGLST)
1835 losing++;
1836 break;
1837
1838
1839 case '&':
1840 if (opP->mode == MSCR || opP->mode == DREG ||
1841 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC ||
1842 opP->mode == AINC || opP->mode == ADEC || opP->mode == REGLST)
1843 losing++;
1844 break;
1845
1846 case '*':
1847 if (opP->mode == MSCR || opP->mode == REGLST)
1848 losing++;
1849 break;
1850
1851 case '+':
1852 if (opP->mode != AINC)
1853 losing++;
1854 break;
1855
1856 case '-':
1857 if (opP->mode != ADEC)
1858 losing++;
1859 break;
1860
1861 case '/':
1862 if (opP->mode == MSCR || opP->mode == AREG ||
1863 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->mode == REGLST)
1864 losing++;
1865 break;
1866
1867 case ';':
1868 if (opP->mode == MSCR || opP->mode == AREG || opP->mode == REGLST)
1869 losing++;
1870 break;
1871
1872 case '?':
1873 if (opP->mode == MSCR || opP->mode == AREG ||
1874 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->reg == PC ||
1875 opP->reg == ZPC || opP->mode == REGLST)
1876 losing++;
1877 break;
1878
1879 case '@':
1880 if (opP->mode == MSCR || opP->mode == AREG ||
1881 opP->mode == IMMED || opP->mode == REGLST)
1882 losing++;
1883 break;
1884
1885 case '~': /* For now! (JF FOO is this right?) */
1886 if (opP->mode == MSCR || opP->mode == DREG ||
1887 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1888 losing++;
1889 break;
1890
1891 case '3':
1892 if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1))
1893 losing++;
1894 break;
1895
1896 case 'A':
1897 if (opP->mode != AREG)
1898 losing++;
1899 break;
1900 case 'a':
1901 if (opP->mode != AINDR)
1902 {
1903 ++losing;
1904 } /* if not address register indirect */
1905 break;
1906 case 'B': /* FOO */
1907 if (opP->mode != ABSL || (flag_long_jumps && instring[0] == 'j'
1908 && instring[1] == 'b'
1909 && instring[2] == 's'
1910 && instring[3] == 'r'))
1911 losing++;
1912 break;
1913
1914 case 'C':
1915 if (opP->mode != MSCR || opP->reg != CCR)
1916 losing++;
1917 break;
1918
1919 case 'd': /* FOO This mode is a KLUDGE!! */
1920 if (opP->mode != AOFF && (opP->mode != ABSL ||
1921 opP->con1->e_beg[0] != '(' || opP->con1->e_end[0] != ')'))
1922 losing++;
1923 break;
1924
1925 case 'D':
1926 if (opP->mode != DREG)
1927 losing++;
1928 break;
1929
1930 case 'F':
1931 if (opP->mode != MSCR || opP->reg < (FPREG + 0) || opP->reg > (FPREG + 7))
1932 losing++;
1933 break;
1934
1935 case 'I':
1936 if (opP->mode != MSCR || opP->reg < COPNUM ||
1937 opP->reg >= COPNUM + 7)
1938 losing++;
1939 break;
1940
1941 case 'J':
1942 if (opP->mode != MSCR
1943 || opP->reg < USP
1944 || opP->reg > last_movec_reg)
1945 losing++;
1946 else
1947 {
1948 const enum _register *rp;
1949 for (rp = control_regs; *rp; rp++)
1950 if (*rp == opP->reg)
1951 break;
1952 if (*rp == 0)
1953 losing++;
1954 }
1955 break;
1956
1957 case 'k':
1958 if (opP->mode != IMMED)
1959 losing++;
1960 break;
1961
1962 case 'l':
1963 case 'L':
1964 if (opP->mode == DREG || opP->mode == AREG || opP->mode == FPREG)
1965 {
1966 if (s[1] == '8')
1967 losing++;
1968 else
1969 {
1970 opP->mode = REGLST;
1971 opP->reg = 1 << (opP->reg - DATA);
1972 }
1973 }
1974 else if (opP->mode != REGLST)
1975 {
1976 losing++;
1977 }
1978 else if (s[1] == '8' && opP->reg & 0x0FFffFF)
1979 losing++;
1980 else if (s[1] == '3' && opP->reg & 0x7000000)
1981 losing++;
1982 break;
1983
1984 case 'M':
1985 if (opP->mode != IMMED)
1986 losing++;
1987 else
1988 {
1989 long t;
1990
1991 t = get_num (opP->con1, 0);
1992 if (!issbyte (t)
1993 || isvar (opP->con1))
1994 losing++;
1995 }
1996 break;
1997
1998 case 'O':
1999 if (opP->mode != DREG && opP->mode != IMMED)
2000 losing++;
2001 break;
2002
2003 case 'Q':
2004 if (opP->mode != IMMED)
2005 losing++;
2006 else
2007 {
2008 long t;
2009
2010 t = get_num (opP->con1, 80);
2011 if (t < 1 || t > 8 || isvar (opP->con1))
2012 losing++;
2013 }
2014 break;
2015
2016 case 'R':
2017 if (opP->mode != DREG && opP->mode != AREG)
2018 losing++;
2019 break;
2020
2021 case 'r':
2022 if (opP->mode != AINDR && opP->mode != DINDR)
2023 losing++;
2024 break;
2025
2026 case 's':
2027 if (opP->mode != MSCR || !(opP->reg == FPI || opP->reg == FPS || opP->reg == FPC))
2028 losing++;
2029 break;
2030
2031 case 'S':
2032 if (opP->mode != MSCR || opP->reg != SR)
2033 losing++;
2034 break;
2035
2036 case 't':
2037 if (opP->mode != IMMED)
2038 losing++;
2039 else
2040 {
2041 long t = get_num (opP->con1, 80);
2042 if (t < 0 || t > 7 || isvar (opP->con1))
2043 losing++;
2044 }
2045 break;
2046
2047 case 'U':
2048 if (opP->mode != MSCR || opP->reg != USP)
2049 losing++;
2050 break;
2051
2052 /* JF these are out of order. We could put them
2053 in order if we were willing to put up with
2054 bunches of #ifdef m68851s in the code.
2055
2056 Don't forget that you need these operands
2057 to use 68030 MMU instructions. */
2058 #ifndef NO_68851
2059 /* Memory addressing mode used by pflushr */
2060 case '|':
2061 if (opP->mode == MSCR || opP->mode == DREG ||
2062 opP->mode == AREG || opP->mode == REGLST)
2063 losing++;
2064 break;
2065
2066 case 'f':
2067 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
2068 losing++;
2069 break;
2070
2071 case 'P':
2072 if (opP->mode != MSCR
2073 || (opP->reg != TC && opP->reg != CAL
2074 && opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
2075 losing++;
2076 break;
2077
2078 case 'V':
2079 if (opP->reg != VAL)
2080 losing++;
2081 break;
2082
2083 case 'W':
2084 if (opP->mode != MSCR
2085 || (opP->reg != DRP && opP->reg != SRP
2086 && opP->reg != CRP))
2087 losing++;
2088 break;
2089
2090 case 'X':
2091 if (opP->mode != MSCR ||
2092 (!(opP->reg >= BAD && opP->reg <= BAD + 7) &&
2093 !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2094 losing++;
2095 break;
2096
2097 case 'Y':
2098 if (opP->reg != PSR)
2099 losing++;
2100 break;
2101
2102 case 'Z':
2103 if (opP->reg != PCSR)
2104 losing++;
2105 break;
2106 #endif
2107 case 'c':
2108 if (opP->reg != NC
2109 && opP->reg != IC
2110 && opP->reg != DC
2111 && opP->reg != BC)
2112 {
2113 losing++;
2114 } /* not a cache specifier. */
2115 break;
2116
2117 case '_':
2118 if (opP->mode != ABSL)
2119 {
2120 ++losing;
2121 } /* not absolute */
2122 break;
2123
2124 default:
2125 as_fatal ("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
2126 *s, __LINE__, __FILE__);
2127 } /* switch on type of operand */
2128
2129 if (losing)
2130 break;
2131 } /* for each operand */
2132 } /* if immediately wrong */
2133
2134 if (!losing)
2135 {
2136 break;
2137 } /* got it. */
2138
2139 opcode = opcode->m_next;
2140
2141 if (!opcode)
2142 {
2143 if (ok_arch
2144 && !(ok_arch & current_architecture))
2145 {
2146 char buf[200], *cp;
2147 int len;
2148 strcpy (buf, "invalid instruction for this architecture; needs ");
2149 cp = buf + strlen (buf);
2150 switch (ok_arch)
2151 {
2152 case mfloat:
2153 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
2154 break;
2155 case mmmu:
2156 strcpy (cp, "mmu (68030 or 68851)");
2157 break;
2158 case m68020up:
2159 strcpy (cp, "68020 or higher");
2160 break;
2161 case m68000up:
2162 strcpy (cp, "68000 or higher");
2163 break;
2164 case m68010up:
2165 strcpy (cp, "68010 or higher");
2166 break;
2167 default:
2168 {
2169 int got_one = 0, idx;
2170 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]); idx++)
2171 {
2172 if (archs[idx].arch & ok_arch)
2173 {
2174 if (got_one)
2175 {
2176 strcpy (cp, " or ");
2177 cp += strlen (cp);
2178 }
2179 got_one = 1;
2180 strcpy (cp, archs[idx].name);
2181 cp += strlen (cp);
2182 }
2183 }
2184 }
2185 }
2186 len = cp - buf + 1;
2187 cp = malloc (len);
2188 strcpy (cp, buf);
2189 the_ins.error = cp;
2190 }
2191 else
2192 the_ins.error = "operands mismatch";
2193 return;
2194 } /* Fell off the end */
2195
2196 losing = 0;
2197 }
2198
2199 /* now assemble it */
2200
2201 the_ins.args = opcode->m_operands;
2202 the_ins.numargs = opcode->m_opnum;
2203 the_ins.numo = opcode->m_codenum;
2204 the_ins.opcode[0] = getone (opcode);
2205 the_ins.opcode[1] = gettwo (opcode);
2206
2207 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2208 {
2209 /* This switch is a doozy.
2210 Watch the first step; its a big one! */
2211 switch (s[0])
2212 {
2213
2214 case '*':
2215 case '~':
2216 case '%':
2217 case ';':
2218 case '@':
2219 case '!':
2220 case '&':
2221 case '$':
2222 case '?':
2223 case '/':
2224 case '`':
2225 #ifndef NO_68851
2226 case '|':
2227 #endif
2228 switch (opP->mode)
2229 {
2230 case IMMED:
2231 tmpreg = 0x3c; /* 7.4 */
2232 if (strchr ("bwl", s[1]))
2233 nextword = get_num (opP->con1, 80);
2234 else
2235 nextword = get_num (opP->con1, 0);
2236 if (isvar (opP->con1))
2237 add_fix (s[1], opP->con1, 0, 0);
2238 switch (s[1])
2239 {
2240 case 'b':
2241 if (!isbyte (nextword))
2242 opP->error = "operand out of range";
2243 addword (nextword);
2244 baseo = 0;
2245 break;
2246 case 'w':
2247 if (!isword (nextword))
2248 opP->error = "operand out of range";
2249 addword (nextword);
2250 baseo = 0;
2251 break;
2252 case 'l':
2253 addword (nextword >> 16);
2254 addword (nextword);
2255 baseo = 0;
2256 break;
2257
2258 case 'f':
2259 baseo = 2;
2260 outro = 8;
2261 break;
2262 case 'F':
2263 baseo = 4;
2264 outro = 11;
2265 break;
2266 case 'x':
2267 baseo = 6;
2268 outro = 15;
2269 break;
2270 case 'p':
2271 baseo = 6;
2272 outro = -1;
2273 break;
2274 default:
2275 as_fatal ("Internal error: Can't decode %c%c in line %d of file \"%s\"",
2276 *s, s[1], __LINE__, __FILE__);
2277 }
2278 if (!baseo)
2279 break;
2280
2281 /* We gotta put out some float */
2282 if (op (opP->con1) != O_big)
2283 {
2284 valueT val;
2285 int gencnt;
2286
2287 /* Can other cases happen here? */
2288 if (op (opP->con1) != O_constant)
2289 abort ();
2290
2291 val = (valueT) offs (opP->con1);
2292 gencnt = 0;
2293 do
2294 {
2295 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2296 val >>= LITTLENUM_NUMBER_OF_BITS;
2297 ++gencnt;
2298 }
2299 while (val != 0);
2300 offs (opP->con1) = gencnt;
2301 }
2302 if (offs (opP->con1) > 0)
2303 {
2304 if (offs (opP->con1) > baseo)
2305 {
2306 as_warn ("Bignum too big for %c format; truncated", s[1]);
2307 offs (opP->con1) = baseo;
2308 }
2309 baseo -= offs (opP->con1);
2310 while (baseo--)
2311 addword (0);
2312 for (wordp = generic_bignum + offs (opP->con1) - 1; offs (opP->con1)--; --wordp)
2313 addword (*wordp);
2314 break;
2315 }
2316 gen_to_words (words, baseo, (long) outro);
2317 for (wordp = words; baseo--; wordp++)
2318 addword (*wordp);
2319 break;
2320 case DREG:
2321 tmpreg = opP->reg - DATA; /* 0.dreg */
2322 break;
2323 case AREG:
2324 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2325 break;
2326 case AINDR:
2327 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2328 break;
2329 case ADEC:
2330 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2331 break;
2332 case AINC:
2333 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2334 break;
2335 case AOFF:
2336
2337 nextword = get_num (opP->con1, 80);
2338 /* Force into index mode. Hope this works */
2339
2340 /* We do the first bit for 32-bit displacements, and the
2341 second bit for 16 bit ones. It is possible that we
2342 should make the default be WORD instead of LONG, but
2343 I think that'd break GCC, so we put up with a little
2344 inefficiency for the sake of working output. */
2345
2346 if (!issword (nextword)
2347 || (isvar (opP->con1)
2348 && ((opP->con1->e_siz == 0
2349 && flag_short_refs == 0
2350 && cpu_of_arch (current_architecture) >= m68020)
2351 || opP->con1->e_siz == 3)))
2352 {
2353
2354 if (opP->reg == PC)
2355 tmpreg = 0x3B; /* 7.3 */
2356 else
2357 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2358 if (isvar (opP->con1))
2359 {
2360 if (opP->reg == PC)
2361 {
2362 #if 0
2363 addword (0x0170);
2364 add_fix ('l', opP->con1, 1, 2);
2365 addword (0), addword (0);
2366 #else
2367 add_frag (adds (opP->con1),
2368 offs (opP->con1),
2369 TAB (PCLEA, SZ_UNDEF));
2370 #endif
2371 break;
2372 }
2373 else
2374 {
2375 addword (0x0170);
2376 add_fix ('l', opP->con1, 0, 0);
2377 }
2378 }
2379 else
2380 addword (0x0170);
2381 addword (nextword >> 16);
2382 }
2383 else
2384 {
2385 if (opP->reg == PC)
2386 tmpreg = 0x3A; /* 7.2 */
2387 else
2388 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2389
2390 if (isvar (opP->con1))
2391 {
2392 if (opP->reg == PC)
2393 {
2394 add_fix ('w', opP->con1, 1, 0);
2395 }
2396 else
2397 add_fix ('w', opP->con1, 0, 0);
2398 }
2399 }
2400 addword (nextword);
2401 break;
2402
2403 case APODX:
2404 case AMIND:
2405 case APRDX:
2406 know (current_architecture & m68020up);
2407 /* intentional fall-through */
2408 case AINDX:
2409 nextword = 0;
2410 baseo = get_num (opP->con1, 80);
2411 outro = get_num (opP->con2, 80);
2412 /* Figure out the `addressing mode'.
2413 Also turn on the BASE_DISABLE bit, if needed. */
2414 if (opP->reg == PC || opP->reg == ZPC)
2415 {
2416 tmpreg = 0x3b;/* 7.3 */
2417 if (opP->reg == ZPC)
2418 nextword |= 0x80;
2419 }
2420 else if (opP->reg == FAIL)
2421 {
2422 nextword |= 0x80;
2423 tmpreg = 0x30;/* 6.garbage */
2424 }
2425 else
2426 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2427
2428 siz1 = (opP->con1) ? opP->con1->e_siz : 0;
2429 siz2 = (opP->con2) ? opP->con2->e_siz : 0;
2430
2431 /* Index register stuff */
2432 if (opP->ireg >= DATA + 0 && opP->ireg <= ADDR + 7)
2433 {
2434 nextword |= (opP->ireg - DATA) << 12;
2435
2436 if (opP->isiz == 0 || opP->isiz == 3)
2437 nextword |= 0x800;
2438 switch (opP->imul)
2439 {
2440 case 1:
2441 break;
2442 case 2:
2443 nextword |= 0x200;
2444 break;
2445 case 4:
2446 nextword |= 0x400;
2447 break;
2448 case 8:
2449 nextword |= 0x600;
2450 break;
2451 default:
2452 as_fatal ("failed sanity check.");
2453 }
2454 /* IF its simple,
2455 GET US OUT OF HERE! */
2456
2457 /* Must be INDEX, with an index register. Address
2458 register cannot be ZERO-PC, and either :b was
2459 forced, or we know it will fit. For a 68000 or
2460 68010, force this mode anyways, because the
2461 larger modes aren't supported. */
2462 if (opP->mode == AINDX
2463 && opP->reg != FAIL
2464 && opP->reg != ZPC
2465 && (/* :b specified */
2466 siz1 == 1
2467 /* known to fit in 8 bits */
2468 || (issbyte (baseo) && !isvar (opP->con1))
2469 /* doesn't support wider modes */
2470 || cpu_of_arch (current_architecture) < m68020
2471 /* simple enough to do relaxation */
2472 || subs (opP->con1) == NULL
2473 ))
2474 {
2475 if (((!isvar (opP->con1)
2476 || subs (opP->con1) != NULL)
2477 && siz1 == 0)
2478 || siz1 == 1)
2479 {
2480 /* Can't handle more complex expressions
2481 here yet. Should only wind up here if
2482 the CPU doesn't support wider modes, so
2483 do a byte relocation and let the fixup
2484 processing later complain if it won't
2485 reach. */
2486 nextword += baseo & 0xff;
2487 addword (nextword);
2488 if (isvar (opP->con1))
2489 {
2490 if (opP->reg == PC)
2491 add_fix ('B', opP->con1, 1, 1);
2492 else
2493 add_fix ('B', opP->con1, 0, 0);
2494 }
2495 }
2496 else if (opP->reg != PC || siz1 != 0)
2497 {
2498 goto no_pc_relax;
2499 }
2500 else
2501 {
2502 nextword += baseo & 0xff;
2503 addword (nextword);
2504 add_frag (adds (opP->con1), offs (opP->con1),
2505 TAB (PCINDEX, SZ_UNDEF));
2506 }
2507 break;
2508 }
2509 }
2510 else
2511 nextword |= 0x40; /* No index reg */
2512
2513 no_pc_relax:
2514 /* It isn't simple. */
2515 nextword |= 0x100;
2516 /* If the guy specified a width, we assume that it is
2517 wide enough. Maybe it isn't. If so, we lose. */
2518 switch (siz1)
2519 {
2520 case 0:
2521 if (isvar (opP->con1) || !issword (baseo))
2522 {
2523 siz1 = 3;
2524 nextword |= 0x30;
2525 }
2526 else if (baseo == 0)
2527 nextword |= 0x10;
2528 else
2529 {
2530 nextword |= 0x20;
2531 siz1 = 2;
2532 }
2533 break;
2534 case 1:
2535 as_warn ("Byte dispacement won't work. Defaulting to :w");
2536 case 2:
2537 nextword |= 0x20;
2538 break;
2539 case 3:
2540 nextword |= 0x30;
2541 break;
2542 }
2543
2544 /* Figure out innner displacement stuff */
2545 if (opP->mode != AINDX)
2546 {
2547 switch (siz2)
2548 {
2549 case 0:
2550 if (isvar (opP->con2) || !issword (outro))
2551 {
2552 siz2 = 3;
2553 nextword |= 0x3;
2554 }
2555 else if (outro == 0)
2556 nextword |= 0x1;
2557 else
2558 {
2559 nextword |= 0x2;
2560 siz2 = 2;
2561 }
2562 break;
2563 case 1:
2564 as_warn ("Byte dispacement won't work. Defaulting to :w");
2565 case 2:
2566 nextword |= 0x2;
2567 break;
2568 case 3:
2569 nextword |= 0x3;
2570 break;
2571 }
2572 if (opP->mode == APODX)
2573 nextword |= 0x04;
2574 else if (opP->mode == AMIND)
2575 nextword |= 0x40;
2576 }
2577 addword (nextword);
2578
2579 if (isvar (opP->con1))
2580 {
2581 if (opP->reg == PC || opP->reg == ZPC)
2582 {
2583 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 1, 2);
2584 }
2585 else
2586 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 0, 0);
2587 }
2588 if (siz1 == 3)
2589 addword (baseo >> 16);
2590 if (siz1)
2591 addword (baseo);
2592
2593 if (isvar (opP->con2))
2594 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 0, 0);
2595 if (siz2 == 3)
2596 addword (outro >> 16);
2597 if (siz2)
2598 addword (outro);
2599
2600 break;
2601
2602 case ABSL:
2603 nextword = get_num (opP->con1, 80);
2604 switch (opP->con1->e_siz)
2605 {
2606 default:
2607 as_warn ("Unknown size for absolute reference");
2608 case 0:
2609 if (!isvar (opP->con1) && issword (offs (opP->con1)))
2610 {
2611 tmpreg = 0x38; /* 7.0 */
2612 addword (nextword);
2613 break;
2614 }
2615 /* Don't generate pc relative code on 68010 and
2616 68000. */
2617 if (isvar (opP->con1)
2618 && !subs (opP->con1)
2619 && seg (opP->con1) == text_section
2620 && now_seg == text_section
2621 && cpu_of_arch (current_architecture) >= m68020
2622 && !flag_long_jumps
2623 && !strchr ("~%&$?", s[0]))
2624 {
2625 tmpreg = 0x3A; /* 7.2 */
2626 add_frag (adds (opP->con1),
2627 offs (opP->con1),
2628 TAB (PCREL, SZ_UNDEF));
2629 break;
2630 }
2631 /* Fall through into long */
2632 case 3:
2633 if (isvar (opP->con1))
2634 add_fix ('l', opP->con1, 0, 0);
2635
2636 tmpreg = 0x39;/* 7.1 mode */
2637 addword (nextword >> 16);
2638 addword (nextword);
2639 break;
2640
2641 case 2: /* Word */
2642 if (isvar (opP->con1))
2643 add_fix ('w', opP->con1, 0, 0);
2644
2645 tmpreg = 0x38;/* 7.0 mode */
2646 addword (nextword);
2647 break;
2648 }
2649 break;
2650 case DINDR:
2651 as_bad ("invalid indirect register");
2652 break;
2653 case MSCR:
2654 default:
2655 as_bad ("unknown/incorrect operand");
2656 /* abort(); */
2657 }
2658 install_gen_operand (s[1], tmpreg);
2659 break;
2660
2661 case '#':
2662 case '^':
2663 switch (s[1])
2664 { /* JF: I hate floating point! */
2665 case 'j':
2666 tmpreg = 70;
2667 break;
2668 case '8':
2669 tmpreg = 20;
2670 break;
2671 case 'C':
2672 tmpreg = 50;
2673 break;
2674 case '3':
2675 default:
2676 tmpreg = 80;
2677 break;
2678 }
2679 tmpreg = get_num (opP->con1, tmpreg);
2680 if (isvar (opP->con1))
2681 add_fix (s[1], opP->con1, 0, 0);
2682 switch (s[1])
2683 {
2684 case 'b': /* Danger: These do no check for
2685 certain types of overflow.
2686 user beware! */
2687 if (!isbyte (tmpreg))
2688 opP->error = "out of range";
2689 insop (tmpreg, opcode);
2690 if (isvar (opP->con1))
2691 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2692 break;
2693 case 'w':
2694 if (!isword (tmpreg))
2695 opP->error = "out of range";
2696 insop (tmpreg, opcode);
2697 if (isvar (opP->con1))
2698 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2699 break;
2700 case 'l':
2701 /* Because of the way insop works, we put these two out
2702 backwards. */
2703 insop (tmpreg, opcode);
2704 insop (tmpreg >> 16, opcode);
2705 if (isvar (opP->con1))
2706 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2707 break;
2708 case '3':
2709 tmpreg &= 0xFF;
2710 case '8':
2711 case 'C':
2712 install_operand (s[1], tmpreg);
2713 break;
2714 default:
2715 as_fatal ("Internal error: Unknown mode #%c in line %d of file \"%s\"", s[1], __LINE__, __FILE__);
2716 }
2717 break;
2718
2719 case '+':
2720 case '-':
2721 case 'A':
2722 case 'a':
2723 install_operand (s[1], opP->reg - ADDR);
2724 break;
2725
2726 case 'B':
2727 tmpreg = get_num (opP->con1, 80);
2728 switch (s[1])
2729 {
2730 case 'B':
2731 add_fix ('B', opP->con1, 1, -1);
2732 break;
2733 case 'W':
2734 add_fix ('w', opP->con1, 1, 0);
2735 addword (0);
2736 break;
2737 case 'L':
2738 long_branch:
2739 if (cpu_of_arch (current_architecture) < m68020) /* 68000 or 010 */
2740 as_warn ("Can't use long branches on 68000/68010");
2741 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2742 add_fix ('l', opP->con1, 1, 0);
2743 addword (0);
2744 addword (0);
2745 break;
2746 case 'g':
2747 if (subs (opP->con1)) /* We can't relax it */
2748 goto long_branch;
2749
2750 /* This could either be a symbol, or an
2751 absolute address. No matter, the
2752 frag hacking will finger it out.
2753 Not quite: it can't switch from
2754 BRANCH to BCC68000 for the case
2755 where opnd is absolute (it needs
2756 to use the 68000 hack since no
2757 conditional abs jumps). */
2758 if (((cpu_of_arch (current_architecture) < m68020)
2759 || (0 == adds (opP->con1)))
2760 && (the_ins.opcode[0] >= 0x6200)
2761 && (the_ins.opcode[0] <= 0x6f00))
2762 {
2763 add_frag (adds (opP->con1), offs (opP->con1), TAB (BCC68000, SZ_UNDEF));
2764 }
2765 else
2766 {
2767 add_frag (adds (opP->con1), offs (opP->con1), TAB (ABRANCH, SZ_UNDEF));
2768 }
2769 break;
2770 case 'w':
2771 if (isvar (opP->con1))
2772 {
2773 #if 1
2774 /* check for DBcc instruction */
2775 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2776 {
2777 /* size varies if patch */
2778 /* needed for long form */
2779 add_frag (adds (opP->con1), offs (opP->con1),
2780 TAB (DBCC, SZ_UNDEF));
2781 break;
2782 }
2783 #endif
2784 add_fix ('w', opP->con1, 1, 0);
2785 }
2786 addword (0);
2787 break;
2788 case 'C': /* Fixed size LONG coproc branches */
2789 add_fix ('l', opP->con1, 1, 0);
2790 addword (0);
2791 addword (0);
2792 break;
2793 case 'c': /* Var size Coprocesssor branches */
2794 if (subs (opP->con1))
2795 {
2796 add_fix ('l', opP->con1, 1, 0);
2797 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2798 }
2799 else if (adds (opP->con1))
2800 {
2801 add_frag (adds (opP->con1), offs (opP->con1), TAB (FBRANCH, SZ_UNDEF));
2802 }
2803 else
2804 {
2805 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2806 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2807 add_fix ('l', opP->con1, 1, 0);
2808 addword (0);
2809 addword (0);
2810 }
2811 break;
2812 default:
2813 as_fatal ("Internal error: operand type B%c unknown in line %d of file \"%s\"",
2814 s[1], __LINE__, __FILE__);
2815 }
2816 break;
2817
2818 case 'C': /* Ignore it */
2819 break;
2820
2821 case 'd': /* JF this is a kludge */
2822 if (opP->mode == AOFF)
2823 {
2824 install_operand ('s', opP->reg - ADDR);
2825 }
2826 else
2827 {
2828 char *tmpP;
2829
2830 tmpP = opP->con1->e_end - 2;
2831 opP->con1->e_beg++;
2832 opP->con1->e_end -= 4; /* point to the , */
2833 baseo = m68k_reg_parse (&tmpP);
2834 if (baseo < ADDR + 0 || baseo > ADDR + 7)
2835 {
2836 as_bad ("Unknown address reg, using A0");
2837 baseo = 0;
2838 }
2839 else
2840 baseo -= ADDR;
2841 install_operand ('s', baseo);
2842 }
2843 tmpreg = get_num (opP->con1, 80);
2844 if (!issword (tmpreg))
2845 {
2846 as_warn ("Expression out of range, using 0");
2847 tmpreg = 0;
2848 }
2849 addword (tmpreg);
2850 break;
2851
2852 case 'D':
2853 install_operand (s[1], opP->reg - DATA);
2854 break;
2855
2856 case 'F':
2857 install_operand (s[1], opP->reg - FPREG);
2858 break;
2859
2860 case 'I':
2861 tmpreg = 1 + opP->reg - COPNUM;
2862 if (tmpreg == 8)
2863 tmpreg = 0;
2864 install_operand (s[1], tmpreg);
2865 break;
2866
2867 case 'J': /* JF foo */
2868 switch (opP->reg)
2869 {
2870 case SFC:
2871 tmpreg = 0x000;
2872 break;
2873 case DFC:
2874 tmpreg = 0x001;
2875 break;
2876 case CACR:
2877 tmpreg = 0x002;
2878 break;
2879 case TC:
2880 tmpreg = 0x003;
2881 break;
2882 case ITT0:
2883 tmpreg = 0x004;
2884 break;
2885 case ITT1:
2886 tmpreg = 0x005;
2887 break;
2888 case DTT0:
2889 tmpreg = 0x006;
2890 break;
2891 case DTT1:
2892 tmpreg = 0x007;
2893 break;
2894 case BUSCR:
2895 tmpreg = 0x008;
2896 break;
2897
2898 case USP:
2899 tmpreg = 0x800;
2900 break;
2901 case VBR:
2902 tmpreg = 0x801;
2903 break;
2904 case CAAR:
2905 tmpreg = 0x802;
2906 break;
2907 case MSP:
2908 tmpreg = 0x803;
2909 break;
2910 case ISP:
2911 tmpreg = 0x804;
2912 break;
2913 case MMUSR:
2914 tmpreg = 0x805;
2915 break;
2916 case URP:
2917 tmpreg = 0x806;
2918 break;
2919 case SRP:
2920 tmpreg = 0x807;
2921 break;
2922 case PCR:
2923 tmpreg = 0x808;
2924 break;
2925 default:
2926 as_fatal ("failed sanity check.");
2927 }
2928 install_operand (s[1], tmpreg);
2929 break;
2930
2931 case 'k':
2932 tmpreg = get_num (opP->con1, 55);
2933 install_operand (s[1], tmpreg & 0x7f);
2934 break;
2935
2936 case 'l':
2937 tmpreg = opP->reg;
2938 if (s[1] == 'w')
2939 {
2940 if (tmpreg & 0x7FF0000)
2941 as_bad ("Floating point register in register list");
2942 insop (reverse_16_bits (tmpreg), opcode);
2943 }
2944 else
2945 {
2946 if (tmpreg & 0x700FFFF)
2947 as_bad ("Wrong register in floating-point reglist");
2948 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2949 }
2950 break;
2951
2952 case 'L':
2953 tmpreg = opP->reg;
2954 if (s[1] == 'w')
2955 {
2956 if (tmpreg & 0x7FF0000)
2957 as_bad ("Floating point register in register list");
2958 insop (tmpreg, opcode);
2959 }
2960 else if (s[1] == '8')
2961 {
2962 if (tmpreg & 0x0FFFFFF)
2963 as_bad ("incorrect register in reglist");
2964 install_operand (s[1], tmpreg >> 24);
2965 }
2966 else
2967 {
2968 if (tmpreg & 0x700FFFF)
2969 as_bad ("wrong register in floating-point reglist");
2970 else
2971 install_operand (s[1], tmpreg >> 16);
2972 }
2973 break;
2974
2975 case 'M':
2976 install_operand (s[1], get_num (opP->con1, 60));
2977 break;
2978
2979 case 'O':
2980 tmpreg = (opP->mode == DREG)
2981 ? 0x20 + opP->reg - DATA
2982 : (get_num (opP->con1, 40) & 0x1F);
2983 install_operand (s[1], tmpreg);
2984 break;
2985
2986 case 'Q':
2987 tmpreg = get_num (opP->con1, 10);
2988 if (tmpreg == 8)
2989 tmpreg = 0;
2990 install_operand (s[1], tmpreg);
2991 break;
2992
2993 case 'R':
2994 case 'r':
2995 /* This depends on the fact that ADDR registers are
2996 eight more than their corresponding DATA regs, so
2997 the result will have the ADDR_REG bit set */
2998 install_operand (s[1], opP->reg - DATA);
2999 break;
3000
3001 case 's':
3002 if (opP->reg == FPI)
3003 tmpreg = 0x1;
3004 else if (opP->reg == FPS)
3005 tmpreg = 0x2;
3006 else if (opP->reg == FPC)
3007 tmpreg = 0x4;
3008 else
3009 as_fatal ("failed sanity check.");
3010 install_operand (s[1], tmpreg);
3011 break;
3012
3013 case 'S': /* Ignore it */
3014 break;
3015
3016 case 'T':
3017 install_operand (s[1], get_num (opP->con1, 30));
3018 break;
3019
3020 case 'U': /* Ignore it */
3021 break;
3022
3023 case 'c':
3024 switch (opP->reg)
3025 {
3026 case NC:
3027 tmpreg = 0;
3028 break;
3029 case DC:
3030 tmpreg = 1;
3031 break;
3032 case IC:
3033 tmpreg = 2;
3034 break;
3035 case BC:
3036 tmpreg = 3;
3037 break;
3038 default:
3039 as_fatal ("failed sanity check");
3040 } /* switch on cache token */
3041 install_operand (s[1], tmpreg);
3042 break;
3043 #ifndef NO_68851
3044 /* JF: These are out of order, I fear. */
3045 case 'f':
3046 switch (opP->reg)
3047 {
3048 case SFC:
3049 tmpreg = 0;
3050 break;
3051 case DFC:
3052 tmpreg = 1;
3053 break;
3054 default:
3055 as_fatal ("failed sanity check.");
3056 }
3057 install_operand (s[1], tmpreg);
3058 break;
3059
3060 case 'P':
3061 switch (opP->reg)
3062 {
3063 case TC:
3064 tmpreg = 0;
3065 break;
3066 case CAL:
3067 tmpreg = 4;
3068 break;
3069 case VAL:
3070 tmpreg = 5;
3071 break;
3072 case SCC:
3073 tmpreg = 6;
3074 break;
3075 case AC:
3076 tmpreg = 7;
3077 break;
3078 default:
3079 as_fatal ("failed sanity check.");
3080 }
3081 install_operand (s[1], tmpreg);
3082 break;
3083
3084 case 'V':
3085 if (opP->reg == VAL)
3086 break;
3087 as_fatal ("failed sanity check.");
3088
3089 case 'W':
3090 switch (opP->reg)
3091 {
3092
3093 case DRP:
3094 tmpreg = 1;
3095 break;
3096 case SRP:
3097 tmpreg = 2;
3098 break;
3099 case CRP:
3100 tmpreg = 3;
3101 break;
3102 default:
3103 as_fatal ("failed sanity check.");
3104 }
3105 install_operand (s[1], tmpreg);
3106 break;
3107
3108 case 'X':
3109 switch (opP->reg)
3110 {
3111 case BAD:
3112 case BAD + 1:
3113 case BAD + 2:
3114 case BAD + 3:
3115 case BAD + 4:
3116 case BAD + 5:
3117 case BAD + 6:
3118 case BAD + 7:
3119 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3120 break;
3121
3122 case BAC:
3123 case BAC + 1:
3124 case BAC + 2:
3125 case BAC + 3:
3126 case BAC + 4:
3127 case BAC + 5:
3128 case BAC + 6:
3129 case BAC + 7:
3130 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3131 break;
3132
3133 default:
3134 as_fatal ("failed sanity check.");
3135 }
3136 install_operand (s[1], tmpreg);
3137 break;
3138 case 'Y':
3139 know (opP->reg == PSR);
3140 break;
3141 case 'Z':
3142 know (opP->reg == PCSR);
3143 break;
3144 #endif /* m68851 */
3145 case '3':
3146 switch (opP->reg)
3147 {
3148 case TT0:
3149 tmpreg = 2;
3150 break;
3151 case TT1:
3152 tmpreg = 3;
3153 break;
3154 default:
3155 as_fatal ("failed sanity check");
3156 }
3157 install_operand (s[1], tmpreg);
3158 break;
3159 case 't':
3160 tmpreg = get_num (opP->con1, 20);
3161 install_operand (s[1], tmpreg);
3162 break;
3163 case '_': /* used only for move16 absolute 32-bit address */
3164 tmpreg = get_num (opP->con1, 80);
3165 addword (tmpreg >> 16);
3166 addword (tmpreg & 0xFFFF);
3167 break;
3168 default:
3169 as_fatal ("Internal error: Operand type %c unknown in line %d of file \"%s\"",
3170 s[0], __LINE__, __FILE__);
3171 }
3172 }
3173
3174 /* By the time whe get here (FINALLY) the_ins contains the complete
3175 instruction, ready to be emitted. . . */
3176 } /* m68k_ip() */
3177
3178 /*
3179 * get_regs := '/' + ?
3180 * | '-' + <register>
3181 * | '-' + <register> + ?
3182 * | <empty>
3183 * ;
3184 *
3185
3186 * The idea here must be to scan in a set of registers but I don't
3187 * understand it. Looks awfully sloppy to me but I don't have any doc on
3188 * this format so...
3189
3190 *
3191 *
3192 */
3193
3194 static int
3195 get_regs (i, str, opP)
3196 int i;
3197 struct m68k_op *opP;
3198 char *str;
3199 {
3200 /* 26, 25, 24, 23-16, 15-8, 0-7 */
3201 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
3202 unsigned long cur_regs = 0;
3203 int reg1, reg2;
3204
3205 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
3206 else if(x==FPS) cur_regs|=(1<<25);\
3207 else if(x==FPC) cur_regs|=(1<<26);\
3208 else cur_regs|=(1<<(x-1)); }
3209
3210 reg1 = i;
3211 for (;;)
3212 {
3213 if (*str == '/')
3214 {
3215 ADD_REG (reg1);
3216 str++;
3217 }
3218 else if (*str == '-')
3219 {
3220 str++;
3221 reg2 = m68k_reg_parse (&str);
3222 if (reg2 < DATA || reg2 >= FPREG + 8 || reg1 == FPI || reg1 == FPS || reg1 == FPC)
3223 {
3224 opP->error = "unknown register in register list";
3225 return FAIL;
3226 }
3227 while (reg1 <= reg2)
3228 {
3229 ADD_REG (reg1);
3230 reg1++;
3231 }
3232 if (*str == '\0')
3233 break;
3234 }
3235 else if (*str == '\0')
3236 {
3237 ADD_REG (reg1);
3238 break;
3239 }
3240 else
3241 {
3242 opP->error = "unknow character in register list";
3243 return FAIL;
3244 }
3245 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
3246 if (*str == '/')
3247 str++;
3248 reg1 = m68k_reg_parse (&str);
3249 if ((reg1 < DATA || reg1 >= FPREG + 8) && !(reg1 == FPI || reg1 == FPS || reg1 == FPC))
3250 {
3251 opP->error = "unknown register in register list";
3252 return FAIL;
3253 }
3254 }
3255 opP->reg = cur_regs;
3256 return OK;
3257 } /* get_regs() */
3258
3259 static int
3260 reverse_16_bits (in)
3261 int in;
3262 {
3263 int out = 0;
3264 int n;
3265
3266 static int mask[16] =
3267 {
3268 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3269 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3270 };
3271 for (n = 0; n < 16; n++)
3272 {
3273 if (in & mask[n])
3274 out |= mask[15 - n];
3275 }
3276 return out;
3277 } /* reverse_16_bits() */
3278
3279 static int
3280 reverse_8_bits (in)
3281 int in;
3282 {
3283 int out = 0;
3284 int n;
3285
3286 static int mask[8] =
3287 {
3288 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3289 };
3290
3291 for (n = 0; n < 8; n++)
3292 {
3293 if (in & mask[n])
3294 out |= mask[7 - n];
3295 }
3296 return out;
3297 } /* reverse_8_bits() */
3298
3299 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3300 (that value is chosen in the frag_var call in md_assemble). TYPE
3301 is the subtype of the frag to be generated; its primary type is
3302 rs_machine_dependent.
3303
3304 The TYPE parameter is also used by md_convert_frag_1 and
3305 md_estimate_size_before_relax. The appropriate type of fixup will
3306 be emitted by md_convert_frag_1.
3307
3308 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3309 static void
3310 install_operand (mode, val)
3311 int mode;
3312 int val;
3313 {
3314 switch (mode)
3315 {
3316 case 's':
3317 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3318 break;
3319 case 'd':
3320 the_ins.opcode[0] |= val << 9;
3321 break;
3322 case '1':
3323 the_ins.opcode[1] |= val << 12;
3324 break;
3325 case '2':
3326 the_ins.opcode[1] |= val << 6;
3327 break;
3328 case '3':
3329 the_ins.opcode[1] |= val;
3330 break;
3331 case '4':
3332 the_ins.opcode[2] |= val << 12;
3333 break;
3334 case '5':
3335 the_ins.opcode[2] |= val << 6;
3336 break;
3337 case '6':
3338 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3339 three words long! */
3340 the_ins.numo++;
3341 the_ins.opcode[2] |= val;
3342 break;
3343 case '7':
3344 the_ins.opcode[1] |= val << 7;
3345 break;
3346 case '8':
3347 the_ins.opcode[1] |= val << 10;
3348 break;
3349 #ifndef NO_68851
3350 case '9':
3351 the_ins.opcode[1] |= val << 5;
3352 break;
3353 #endif
3354
3355 case 't':
3356 the_ins.opcode[1] |= (val << 10) | (val << 7);
3357 break;
3358 case 'D':
3359 the_ins.opcode[1] |= (val << 12) | val;
3360 break;
3361 case 'g':
3362 the_ins.opcode[0] |= val = 0xff;
3363 break;
3364 case 'i':
3365 the_ins.opcode[0] |= val << 9;
3366 break;
3367 case 'C':
3368 the_ins.opcode[1] |= val;
3369 break;
3370 case 'j':
3371 the_ins.opcode[1] |= val;
3372 the_ins.numo++; /* What a hack */
3373 break;
3374 case 'k':
3375 the_ins.opcode[1] |= val << 4;
3376 break;
3377 case 'b':
3378 case 'w':
3379 case 'l':
3380 break;
3381 case 'e':
3382 the_ins.opcode[0] |= (val << 6);
3383 break;
3384 case 'L':
3385 the_ins.opcode[1] = (val >> 16);
3386 the_ins.opcode[2] = val & 0xffff;
3387 break;
3388 case 'c':
3389 default:
3390 as_fatal ("failed sanity check.");
3391 }
3392 } /* install_operand() */
3393
3394 static void
3395 install_gen_operand (mode, val)
3396 int mode;
3397 int val;
3398 {
3399 switch (mode)
3400 {
3401 case 's':
3402 the_ins.opcode[0] |= val;
3403 break;
3404 case 'd':
3405 /* This is a kludge!!! */
3406 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3407 break;
3408 case 'b':
3409 case 'w':
3410 case 'l':
3411 case 'f':
3412 case 'F':
3413 case 'x':
3414 case 'p':
3415 the_ins.opcode[0] |= val;
3416 break;
3417 /* more stuff goes here */
3418 default:
3419 as_fatal ("failed sanity check.");
3420 }
3421 } /* install_gen_operand() */
3422
3423 /*
3424 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3425 * then deal with the bitfield hack.
3426 */
3427
3428 static char *
3429 crack_operand (str, opP)
3430 register char *str;
3431 register struct m68k_op *opP;
3432 {
3433 register int parens;
3434 register int c;
3435 register char *beg_str;
3436
3437 if (!str)
3438 {
3439 return str;
3440 }
3441 beg_str = str;
3442 for (parens = 0; *str && (parens > 0 || notend (str)); str++)
3443 {
3444 if (*str == '(')
3445 parens++;
3446 else if (*str == ')')
3447 {
3448 if (!parens)
3449 { /* ERROR */
3450 opP->error = "Extra )";
3451 return str;
3452 }
3453 --parens;
3454 }
3455 }
3456 if (!*str && parens)
3457 { /* ERROR */
3458 opP->error = "Missing )";
3459 return str;
3460 }
3461 c = *str;
3462 *str = '\0';
3463 if (m68k_ip_op (beg_str, opP) == FAIL)
3464 {
3465 *str = c;
3466 return str;
3467 }
3468 *str = c;
3469 if (c == '}')
3470 c = *++str; /* JF bitfield hack */
3471 if (c)
3472 {
3473 c = *++str;
3474 if (!c)
3475 as_bad ("Missing operand");
3476 }
3477 return str;
3478 }
3479
3480 /* This is the guts of the machine-dependent assembler. STR points to a
3481 machine dependent instruction. This function is supposed to emit
3482 the frags/bytes it assembles to.
3483 */
3484
3485 void
3486 insert_reg (regname, regnum)
3487 char *regname;
3488 int regnum;
3489 {
3490 char buf[100];
3491 int i;
3492
3493 #ifdef REGISTER_PREFIX
3494 if (!flag_reg_prefix_optional)
3495 {
3496 buf[0] = REGISTER_PREFIX;
3497 strcpy (buf + 1, regname);
3498 regname = buf;
3499 }
3500 #endif
3501
3502 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3503 &zero_address_frag));
3504
3505 for (i = 0; regname[i]; i++)
3506 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3507 buf[i] = '\0';
3508
3509 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3510 &zero_address_frag));
3511 }
3512
3513 struct init_entry
3514 {
3515 const char *name;
3516 int number;
3517 };
3518
3519 static const struct init_entry init_table[] =
3520 {
3521 { "d0", DATA0 },
3522 { "d1", DATA1 },
3523 { "d2", DATA2 },
3524 { "d3", DATA3 },
3525 { "d4", DATA4 },
3526 { "d5", DATA5 },
3527 { "d6", DATA6 },
3528 { "d7", DATA7 },
3529 { "a0", ADDR0 },
3530 { "a1", ADDR1 },
3531 { "a2", ADDR2 },
3532 { "a3", ADDR3 },
3533 { "a4", ADDR4 },
3534 { "a5", ADDR5 },
3535 { "a6", ADDR6 },
3536 { "fp", ADDR6 },
3537 { "a7", ADDR7 },
3538 { "sp", ADDR7 },
3539 { "fp0", FP0 },
3540 { "fp1", FP1 },
3541 { "fp2", FP2 },
3542 { "fp3", FP3 },
3543 { "fp4", FP4 },
3544 { "fp5", FP5 },
3545 { "fp6", FP6 },
3546 { "fp7", FP7 },
3547 { "fpi", FPI },
3548 { "fpiar", FPI },
3549 { "fpc", FPI },
3550 { "fps", FPS },
3551 { "fpsr", FPS },
3552 { "fpc", FPC },
3553 { "fpcr", FPC },
3554
3555 { "cop0", COP0 },
3556 { "cop1", COP1 },
3557 { "cop2", COP2 },
3558 { "cop3", COP3 },
3559 { "cop4", COP4 },
3560 { "cop5", COP5 },
3561 { "cop6", COP6 },
3562 { "cop7", COP7 },
3563 { "pc", PC },
3564 { "zpc", ZPC },
3565 { "sr", SR },
3566
3567 { "ccr", CCR },
3568 { "cc", CCR },
3569
3570 { "usp", USP },
3571 { "isp", ISP },
3572 { "sfc", SFC },
3573 { "dfc", DFC },
3574 { "cacr", CACR },
3575 { "caar", CAAR },
3576
3577 { "vbr", VBR },
3578
3579 { "msp", MSP },
3580 { "itt0", ITT0 },
3581 { "itt1", ITT1 },
3582 { "dtt0", DTT0 },
3583 { "dtt1", DTT1 },
3584 { "mmusr", MMUSR },
3585 { "tc", TC },
3586 { "srp", SRP },
3587 { "urp", URP },
3588 { "buscr", BUSCR },
3589 { "pcr", PCR },
3590
3591 { "ac", AC },
3592 { "bc", BC },
3593 { "cal", CAL },
3594 { "crp", CRP },
3595 { "drp", DRP },
3596 { "pcsr", PCSR },
3597 { "psr", PSR },
3598 { "scc", SCC },
3599 { "val", VAL },
3600 { "bad0", BAD0 },
3601 { "bad1", BAD1 },
3602 { "bad2", BAD2 },
3603 { "bad3", BAD3 },
3604 { "bad4", BAD4 },
3605 { "bad5", BAD5 },
3606 { "bad6", BAD6 },
3607 { "bad7", BAD7 },
3608 { "bac0", BAC0 },
3609 { "bac1", BAC1 },
3610 { "bac2", BAC2 },
3611 { "bac3", BAC3 },
3612 { "bac4", BAC4 },
3613 { "bac5", BAC5 },
3614 { "bac6", BAC6 },
3615 { "bac7", BAC7 },
3616
3617 { "ic", IC },
3618 { "dc", DC },
3619 { "nc", NC },
3620
3621 { "tt0", TT0 },
3622 { "tt1", TT1 },
3623 /* 68ec030 versions of same */
3624 { "ac0", TT0 },
3625 { "ac1", TT1 },
3626 /* 68ec030 access control unit, identical to 030 MMU status reg */
3627 { "acusr", PSR },
3628
3629 { 0, 0 }
3630 };
3631
3632 void
3633 init_regtable ()
3634 {
3635 int i;
3636 for (i = 0; init_table[i].name; i++)
3637 insert_reg (init_table[i].name, init_table[i].number);
3638 }
3639
3640 static int no_68851, no_68881;
3641
3642 #ifdef OBJ_AOUT
3643 /* a.out machine type. Default to 68020. */
3644 int m68k_aout_machtype = 2;
3645 #endif
3646
3647 void
3648 md_assemble (str)
3649 char *str;
3650 {
3651 char *er;
3652 short *fromP;
3653 char *toP = NULL;
3654 int m, n = 0;
3655 char *to_beg_P;
3656 int shorts_this_frag;
3657 fixS *fixP;
3658
3659 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3660 m68k_ip (str);
3661 er = the_ins.error;
3662 if (!er)
3663 {
3664 for (n = the_ins.numargs; n; --n)
3665 if (the_ins.operands[n].error)
3666 {
3667 er = the_ins.operands[n].error;
3668 break;
3669 }
3670 }
3671 if (er)
3672 {
3673 as_bad ("%s -- statement `%s' ignored", er, str);
3674 return;
3675 }
3676
3677 if (the_ins.nfrag == 0)
3678 {
3679 /* No frag hacking involved; just put it out */
3680 toP = frag_more (2 * the_ins.numo);
3681 fromP = &the_ins.opcode[0];
3682 for (m = the_ins.numo; m; --m)
3683 {
3684 md_number_to_chars (toP, (long) (*fromP), 2);
3685 toP += 2;
3686 fromP++;
3687 }
3688 /* put out symbol-dependent info */
3689 for (m = 0; m < the_ins.nrel; m++)
3690 {
3691 switch (the_ins.reloc[m].wid)
3692 {
3693 case 'B':
3694 n = 1;
3695 break;
3696 case 'b':
3697 n = 1;
3698 break;
3699 case '3':
3700 n = 2;
3701 break;
3702 case 'w':
3703 n = 2;
3704 break;
3705 case 'l':
3706 n = 4;
3707 break;
3708 default:
3709 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3710 the_ins.reloc[m].wid);
3711 }
3712
3713 fixP = fix_new_exp (frag_now,
3714 ((toP - frag_now->fr_literal)
3715 - the_ins.numo * 2 + the_ins.reloc[m].n),
3716 n,
3717 &the_ins.reloc[m].exp,
3718 the_ins.reloc[m].pcrel,
3719 NO_RELOC);
3720 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3721 }
3722 return;
3723 }
3724
3725 /* There's some frag hacking */
3726 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3727 {
3728 int wid;
3729
3730 if (n == 0)
3731 wid = 2 * the_ins.fragb[n].fragoff;
3732 else
3733 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3734 toP = frag_more (wid);
3735 to_beg_P = toP;
3736 shorts_this_frag = 0;
3737 for (m = wid / 2; m; --m)
3738 {
3739 md_number_to_chars (toP, (long) (*fromP), 2);
3740 toP += 2;
3741 fromP++;
3742 shorts_this_frag++;
3743 }
3744 for (m = 0; m < the_ins.nrel; m++)
3745 {
3746 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3747 {
3748 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3749 break;
3750 }
3751 wid = the_ins.reloc[m].wid;
3752 if (wid == 0)
3753 continue;
3754 the_ins.reloc[m].wid = 0;
3755 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3756
3757 fixP = fix_new_exp (frag_now,
3758 ((toP - frag_now->fr_literal)
3759 - the_ins.numo * 2 + the_ins.reloc[m].n),
3760 wid,
3761 &the_ins.reloc[m].exp,
3762 the_ins.reloc[m].pcrel,
3763 NO_RELOC);
3764 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3765 }
3766 (void) frag_var (rs_machine_dependent, 10, 0,
3767 (relax_substateT) (the_ins.fragb[n].fragty),
3768 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3769 }
3770 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3771 shorts_this_frag = 0;
3772 if (n)
3773 {
3774 toP = frag_more (n * sizeof (short));
3775 while (n--)
3776 {
3777 md_number_to_chars (toP, (long) (*fromP), 2);
3778 toP += 2;
3779 fromP++;
3780 shorts_this_frag++;
3781 }
3782 }
3783 for (m = 0; m < the_ins.nrel; m++)
3784 {
3785 int wid;
3786
3787 wid = the_ins.reloc[m].wid;
3788 if (wid == 0)
3789 continue;
3790 the_ins.reloc[m].wid = 0;
3791 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3792
3793 fixP = fix_new_exp (frag_now,
3794 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3795 - shorts_this_frag * 2),
3796 wid,
3797 &the_ins.reloc[m].exp,
3798 the_ins.reloc[m].pcrel,
3799 NO_RELOC);
3800 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3801 }
3802 }
3803
3804 /* See BREAK_UP_BIG_DECL definition, above. */
3805 #ifdef DO_BREAK_UP_BIG_DECL
3806 static const struct m68k_opcode *
3807 opcode_ptr (i)
3808 int i;
3809 {
3810 int lim1 = sizeof (m68k_opcodes) / sizeof (m68k_opcodes[0]);
3811 if (i >= lim1)
3812 return m68k_opcodes_2 + (i - lim1);
3813 return m68k_opcodes + i;
3814 }
3815 #else
3816 #define opcode_ptr(i) (m68k_opcodes + i)
3817 #endif
3818
3819 void
3820 md_begin ()
3821 {
3822 /*
3823 * md_begin -- set up hash tables with 68000 instructions.
3824 * similar to what the vax assembler does. ---phr
3825 */
3826 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3827 a copy of it at runtime, adding in the information we want but isn't
3828 there. I think it'd be better to have an awk script hack the table
3829 at compile time. Or even just xstr the table and use it as-is. But
3830 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3831 names. */
3832
3833 register const struct m68k_opcode *ins;
3834 register struct m68k_incant *hack, *slak;
3835 register const char *retval = 0; /* empty string, or error msg text */
3836 register unsigned int i;
3837 register char c;
3838
3839 op_hash = hash_new ();
3840
3841 obstack_begin (&robyn, 4000);
3842 for (i = 0; i < numopcodes; i++)
3843 {
3844 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3845 do
3846 {
3847 ins = opcode_ptr (i);
3848 /* We *could* ignore insns that don't match our arch here
3849 but just leaving them out of the hash. */
3850 slak->m_operands = ins->args;
3851 slak->m_opnum = strlen (slak->m_operands) / 2;
3852 slak->m_arch = ins->arch;
3853 slak->m_opcode = ins->opcode;
3854 /* This is kludgey */
3855 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3856 if (i + 1 != numopcodes
3857 && !strcmp (ins->name, opcode_ptr (i + 1)->name))
3858 {
3859 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3860 i++;
3861 }
3862 else
3863 slak->m_next = 0;
3864 slak = slak->m_next;
3865 }
3866 while (slak);
3867
3868 retval = hash_insert (op_hash, ins->name, (char *) hack);
3869 if (retval)
3870 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3871 }
3872
3873 for (i = 0; i < numaliases; i++)
3874 {
3875 const char *name = m68k_opcode_aliases[i].primary;
3876 const char *alias = m68k_opcode_aliases[i].alias;
3877 PTR val = hash_find (op_hash, name);
3878 if (!val)
3879 as_fatal ("Internal Error: Can't find %s in hash table", name);
3880 retval = hash_insert (op_hash, alias, val);
3881 if (retval)
3882 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3883 }
3884
3885 for (i = 0; i < sizeof (mklower_table); i++)
3886 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3887
3888 for (i = 0; i < sizeof (notend_table); i++)
3889 {
3890 notend_table[i] = 0;
3891 alt_notend_table[i] = 0;
3892 }
3893 notend_table[','] = 1;
3894 notend_table['{'] = 1;
3895 notend_table['}'] = 1;
3896 alt_notend_table['a'] = 1;
3897 alt_notend_table['A'] = 1;
3898 alt_notend_table['d'] = 1;
3899 alt_notend_table['D'] = 1;
3900 alt_notend_table['#'] = 1;
3901 alt_notend_table['&'] = 1;
3902 alt_notend_table['f'] = 1;
3903 alt_notend_table['F'] = 1;
3904 #ifdef REGISTER_PREFIX
3905 alt_notend_table[REGISTER_PREFIX] = 1;
3906 #endif
3907
3908 #ifndef MIT_SYNTAX_ONLY
3909 /* Insert pseudo ops, these have to go into the opcode table since
3910 gas expects pseudo ops to start with a dot */
3911 {
3912 int n = 0;
3913 while (mote_pseudo_table[n].poc_name)
3914 {
3915 hack = (struct m68k_incant *)
3916 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3917 hash_insert (op_hash,
3918 mote_pseudo_table[n].poc_name, (char *) hack);
3919 hack->m_operands = 0;
3920 hack->m_opnum = n;
3921 n++;
3922 }
3923 }
3924 #endif
3925
3926 init_regtable ();
3927 }
3928
3929 void
3930 m68k_init_after_args ()
3931 {
3932 if (cpu_of_arch (current_architecture) == 0)
3933 {
3934 int cpu_type, i;
3935 const char *default_cpu = TARGET_CPU;
3936
3937 if (*default_cpu == 'm')
3938 default_cpu++;
3939 for (i = 0; i < n_archs; i++)
3940 if (!strcmp (default_cpu, archs[i].name))
3941 break;
3942 if (i == n_archs)
3943 {
3944 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3945 current_architecture |= m68020;
3946 }
3947 else
3948 current_architecture |= archs[i].arch;
3949 }
3950 /* Permit m68881 specification with all cpus; those that can't work
3951 with a coprocessor could be doing emulation. */
3952 if (current_architecture & m68851)
3953 {
3954 if (current_architecture & m68040)
3955 {
3956 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3957 }
3958 }
3959 /* What other incompatibilities could we check for? */
3960
3961 /* Toss in some default assumptions about coprocessors. */
3962 if (!no_68881
3963 && (cpu_of_arch (current_architecture)
3964 /* Can CPU32 have a 68881 coprocessor?? */
3965 & (m68020 | m68030 | cpu32)))
3966 {
3967 current_architecture |= m68881;
3968 }
3969 if (!no_68851
3970 && (cpu_of_arch (current_architecture) & m68020up) != 0
3971 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3972 {
3973 current_architecture |= m68851;
3974 }
3975 if (no_68881 && (current_architecture & m68881))
3976 as_bad ("options for 68881 and no-68881 both given");
3977 if (no_68851 && (current_architecture & m68851))
3978 as_bad ("options for 68851 and no-68851 both given");
3979
3980 #ifdef OBJ_AOUT
3981 /* Work out the magic number. This isn't very general. */
3982 if (current_architecture & m68000)
3983 m68k_aout_machtype = 0;
3984 else if (current_architecture & m68010)
3985 m68k_aout_machtype = 1;
3986 else if (current_architecture & m68020)
3987 m68k_aout_machtype = 2;
3988 else
3989 m68k_aout_machtype = 2;
3990 #endif
3991
3992 /* Note which set of "movec" control registers is available. */
3993 switch (cpu_of_arch (current_architecture))
3994 {
3995 case m68000:
3996 control_regs = m68000_control_regs;
3997 break;
3998 case m68010:
3999 control_regs = m68010_control_regs;
4000 break;
4001 case m68020:
4002 case m68030:
4003 control_regs = m68020_control_regs;
4004 break;
4005 case m68040:
4006 control_regs = m68040_control_regs;
4007 break;
4008 case m68060:
4009 control_regs = m68060_control_regs;
4010 break;
4011 case cpu32:
4012 control_regs = cpu32_control_regs;
4013 break;
4014 default:
4015 abort ();
4016 }
4017
4018 if (cpu_of_arch (current_architecture) < m68020)
4019 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4020 }
4021
4022 /* Equal to MAX_PRECISION in atof-ieee.c */
4023 #define MAX_LITTLENUMS 6
4024
4025 /* Turn a string in input_line_pointer into a floating point constant of type
4026 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
4027 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
4028 */
4029 char *
4030 md_atof (type, litP, sizeP)
4031 char type;
4032 char *litP;
4033 int *sizeP;
4034 {
4035 int prec;
4036 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4037 LITTLENUM_TYPE *wordP;
4038 char *t;
4039 char *atof_ieee ();
4040
4041 switch (type)
4042 {
4043 case 'f':
4044 case 'F':
4045 case 's':
4046 case 'S':
4047 prec = 2;
4048 break;
4049
4050 case 'd':
4051 case 'D':
4052 case 'r':
4053 case 'R':
4054 prec = 4;
4055 break;
4056
4057 case 'x':
4058 case 'X':
4059 prec = 6;
4060 break;
4061
4062 case 'p':
4063 case 'P':
4064 prec = 6;
4065 break;
4066
4067 default:
4068 *sizeP = 0;
4069 return "Bad call to MD_ATOF()";
4070 }
4071 t = atof_ieee (input_line_pointer, type, words);
4072 if (t)
4073 input_line_pointer = t;
4074
4075 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4076 for (wordP = words; prec--;)
4077 {
4078 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4079 litP += sizeof (LITTLENUM_TYPE);
4080 }
4081 return 0;
4082 }
4083
4084 void
4085 md_number_to_chars (buf, val, n)
4086 char *buf;
4087 valueT val;
4088 int n;
4089 {
4090 number_to_chars_bigendian (buf, val, n);
4091 }
4092
4093 static void
4094 md_apply_fix_2 (fixP, val)
4095 fixS *fixP;
4096 offsetT val;
4097 {
4098 addressT upper_limit;
4099 offsetT lower_limit;
4100
4101 /* This is unnecessary but it convinces the native rs6000 compiler
4102 to generate the code we want. */
4103 char *buf = fixP->fx_frag->fr_literal;
4104 buf += fixP->fx_where;
4105 /* end ibm compiler workaround */
4106
4107 if (val & 0x80000000)
4108 val |= ~(addressT)0x7fffffff;
4109 else
4110 val &= 0x7fffffff;
4111
4112 switch (fixP->fx_size)
4113 {
4114 /* The cast to offsetT below are necessary to make code correct for
4115 machines where ints are smaller than offsetT */
4116 case 1:
4117 *buf++ = val;
4118 upper_limit = 0x7f;
4119 lower_limit = - (offsetT) 0x80;
4120 break;
4121 case 2:
4122 *buf++ = (val >> 8);
4123 *buf++ = val;
4124 upper_limit = 0x7fff;
4125 lower_limit = - (offsetT) 0x8000;
4126 break;
4127 case 4:
4128 *buf++ = (val >> 24);
4129 *buf++ = (val >> 16);
4130 *buf++ = (val >> 8);
4131 *buf++ = val;
4132 upper_limit = 0x7fffffff;
4133 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4134 break;
4135 default:
4136 BAD_CASE (fixP->fx_size);
4137 }
4138
4139 /* For non-pc-relative values, it's conceivable we might get something
4140 like "0xff" for a byte field. So extend the upper part of the range
4141 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4142 so that we can do any range checking at all. */
4143 if (!fixP->fx_pcrel)
4144 upper_limit = upper_limit * 2 + 1;
4145
4146 if ((addressT) val > upper_limit
4147 && (val > 0 || val < lower_limit))
4148 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
4149
4150 /* A one byte PC-relative reloc means a short branch. We can't use
4151 a short branch with a value of 0 or -1, because those indicate
4152 different opcodes (branches with longer offsets). */
4153 if (fixP->fx_pcrel
4154 && fixP->fx_size == 1
4155 && (fixP->fx_addsy == NULL
4156 || S_IS_DEFINED (fixP->fx_addsy))
4157 && (val == 0 || val == -1))
4158 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
4159 }
4160
4161 #ifdef BFD_ASSEMBLER
4162 int
4163 md_apply_fix (fixP, valp)
4164 fixS *fixP;
4165 valueT *valp;
4166 {
4167 md_apply_fix_2 (fixP, (addressT) *valp);
4168 return 1;
4169 }
4170 #else
4171 void md_apply_fix (fixP, val)
4172 fixS *fixP;
4173 long val;
4174 {
4175 md_apply_fix_2 (fixP, (addressT) val);
4176 }
4177 #endif
4178
4179 /* *fragP has been relaxed to its final size, and now needs to have
4180 the bytes inside it modified to conform to the new size There is UGLY
4181 MAGIC here. ..
4182 */
4183 void
4184 md_convert_frag_1 (fragP)
4185 register fragS *fragP;
4186 {
4187 long disp;
4188 long ext = 0;
4189 fixS *fixP;
4190
4191 /* Address in object code of the displacement. */
4192 register int object_address = fragP->fr_fix + fragP->fr_address;
4193
4194 /* Address in gas core of the place to store the displacement. */
4195 /* This convinces the native rs6000 compiler to generate the code we
4196 want. */
4197 register char *buffer_address = fragP->fr_literal;
4198 buffer_address += fragP->fr_fix;
4199 /* end ibm compiler workaround */
4200
4201 /* The displacement of the address, from current location. */
4202 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4203 disp = (disp + fragP->fr_offset) - object_address;
4204
4205 #ifdef BFD_ASSEMBLER
4206 disp += fragP->fr_symbol->sy_frag->fr_address;
4207 #endif
4208
4209 switch (fragP->fr_subtype)
4210 {
4211 case TAB (BCC68000, BYTE):
4212 case TAB (ABRANCH, BYTE):
4213 know (issbyte (disp));
4214 if (disp == 0)
4215 as_bad ("short branch with zero offset: use :w");
4216 fragP->fr_opcode[1] = disp;
4217 ext = 0;
4218 break;
4219 case TAB (DBCC, SHORT):
4220 know (issword (disp));
4221 ext = 2;
4222 break;
4223 case TAB (BCC68000, SHORT):
4224 case TAB (ABRANCH, SHORT):
4225 know (issword (disp));
4226 fragP->fr_opcode[1] = 0x00;
4227 ext = 2;
4228 break;
4229 case TAB (ABRANCH, LONG):
4230 if (cpu_of_arch (current_architecture) < m68020)
4231 {
4232 if (fragP->fr_opcode[0] == 0x61)
4233 /* BSR */
4234 {
4235 fragP->fr_opcode[0] = 0x4E;
4236 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4237 subseg_change (text_section, 0); /* @@ */
4238
4239 fix_new (fragP,
4240 fragP->fr_fix,
4241 4,
4242 fragP->fr_symbol,
4243 fragP->fr_offset,
4244 0,
4245 NO_RELOC);
4246
4247 fragP->fr_fix += 4;
4248 ext = 0;
4249 }
4250 /* BRA */
4251 else if (fragP->fr_opcode[0] == 0x60)
4252 {
4253 fragP->fr_opcode[0] = 0x4E;
4254 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4255 subseg_change (text_section, 0); /* @@ */
4256 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4257 fragP->fr_offset, 0, NO_RELOC);
4258 fragP->fr_fix += 4;
4259 ext = 0;
4260 }
4261 else
4262 {
4263 as_bad ("Long branch offset not supported.");
4264 }
4265 }
4266 else
4267 {
4268 fragP->fr_opcode[1] = (char) 0xff;
4269 ext = 4;
4270 }
4271 break;
4272 case TAB (BCC68000, LONG):
4273 /* only Bcc 68000 instructions can come here */
4274 /* change bcc into b!cc/jmp absl long */
4275 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4276 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4277
4278 /* JF: these used to be fr_opcode[2,3], but they may be in a
4279 different frag, in which case refering to them is a no-no.
4280 Only fr_opcode[0,1] are guaranteed to work. */
4281 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4282 *buffer_address++ = (char) 0xf9;
4283 fragP->fr_fix += 2; /* account for jmp instruction */
4284 subseg_change (text_section, 0);
4285 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4286 fragP->fr_offset, 0, NO_RELOC);
4287 fragP->fr_fix += 4;
4288 ext = 0;
4289 break;
4290 case TAB (DBCC, LONG):
4291 /* only DBcc 68000 instructions can come here */
4292 /* change dbcc into dbcc/jmp absl long */
4293 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4294 *buffer_address++ = 0x00; /* branch offset = 4 */
4295 *buffer_address++ = 0x04;
4296 *buffer_address++ = 0x60; /* put in bra pc+6 */
4297 *buffer_address++ = 0x06;
4298 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4299 *buffer_address++ = (char) 0xf9;
4300
4301 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4302 subseg_change (text_section, 0);
4303 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4304 fragP->fr_offset, 0, NO_RELOC);
4305 fragP->fr_fix += 4;
4306 ext = 0;
4307 break;
4308 case TAB (FBRANCH, SHORT):
4309 know ((fragP->fr_opcode[1] & 0x40) == 0);
4310 ext = 2;
4311 break;
4312 case TAB (FBRANCH, LONG):
4313 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4314 ext = 4;
4315 break;
4316 case TAB (PCREL, SHORT):
4317 ext = 2;
4318 break;
4319 case TAB (PCREL, LONG):
4320 /* The thing to do here is force it to ABSOLUTE LONG, since
4321 PCREL is really trying to shorten an ABSOLUTE address anyway */
4322 /* JF FOO This code has not been tested */
4323 subseg_change (text_section, 0);
4324 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4325 0, NO_RELOC);
4326 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4327 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4328 (unsigned) fragP->fr_opcode[0],
4329 (unsigned long) fragP->fr_address);
4330 fragP->fr_opcode[1] &= ~0x3F;
4331 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4332 fragP->fr_fix += 4;
4333 ext = 0;
4334 break;
4335 case TAB (PCLEA, SHORT):
4336 subseg_change (text_section, 0);
4337 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4338 fragP->fr_offset, 1, NO_RELOC);
4339 fragP->fr_opcode[1] &= ~0x3F;
4340 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4341 ext = 2;
4342 break;
4343 case TAB (PCLEA, LONG):
4344 subseg_change (text_section, 0);
4345 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4346 fragP->fr_offset, 1, NO_RELOC);
4347 fixP->fx_pcrel_adjust = 2;
4348 /* Already set to mode 7.3; this indicates: PC indirect with
4349 suppressed index, 32-bit displacement. */
4350 *buffer_address++ = 0x01;
4351 *buffer_address++ = 0x70;
4352 fragP->fr_fix += 2;
4353 ext = 4;
4354 break;
4355
4356 case TAB (PCINDEX, BYTE):
4357 disp += 2;
4358 if (!issbyte (disp))
4359 {
4360 as_bad ("displacement doesn't fit in one byte");
4361 disp = 0;
4362 }
4363 assert (fragP->fr_fix >= 2);
4364 buffer_address[-2] &= ~1;
4365 buffer_address[-1] = disp;
4366 ext = 0;
4367 break;
4368 case TAB (PCINDEX, SHORT):
4369 subseg_change (text_section, 0);
4370 disp += 2;
4371 assert (issword (disp));
4372 assert (fragP->fr_fix >= 2);
4373 buffer_address[-2] |= 0x1;
4374 buffer_address[-1] = 0x20;
4375 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4376 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4377 NO_RELOC);
4378 fixP->fx_pcrel_adjust = 2;
4379 ext = 2;
4380 break;
4381 case TAB (PCINDEX, LONG):
4382 subseg_change (text_section, 0);
4383 disp += 2;
4384 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4385 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4386 NO_RELOC);
4387 fixP->fx_pcrel_adjust = 2;
4388 assert (fragP->fr_fix >= 2);
4389 buffer_address[-2] |= 0x1;
4390 buffer_address[-1] = 0x30;
4391 ext = 4;
4392 break;
4393 }
4394
4395 if (ext)
4396 {
4397 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4398 fragP->fr_fix += ext;
4399 }
4400 }
4401
4402 #ifndef BFD_ASSEMBLER
4403
4404 void
4405 md_convert_frag (headers, seg, fragP)
4406 object_headers *headers;
4407 segT seg;
4408 fragS *fragP;
4409 {
4410 md_convert_frag_1 (fragP);
4411 }
4412
4413 #else
4414
4415 void
4416 md_convert_frag (abfd, sec, fragP)
4417 bfd *abfd;
4418 segT sec;
4419 fragS *fragP;
4420 {
4421 md_convert_frag_1 (fragP);
4422 }
4423 #endif
4424
4425 /* Force truly undefined symbols to their maximum size, and generally set up
4426 the frag list to be relaxed
4427 */
4428 int
4429 md_estimate_size_before_relax (fragP, segment)
4430 register fragS *fragP;
4431 segT segment;
4432 {
4433 int old_fix;
4434 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4435
4436 old_fix = fragP->fr_fix;
4437
4438 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4439 switch (fragP->fr_subtype)
4440 {
4441
4442 case TAB (ABRANCH, SZ_UNDEF):
4443 {
4444 if ((fragP->fr_symbol != NULL) /* Not absolute */
4445 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4446 {
4447 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4448 break;
4449 }
4450 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4451 {
4452 /* On 68000, or for absolute value, switch to abs long */
4453 /* FIXME, we should check abs val, pick short or long */
4454 if (fragP->fr_opcode[0] == 0x61)
4455 {
4456 fragP->fr_opcode[0] = 0x4E;
4457 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4458 subseg_change (text_section, 0);
4459 fix_new (fragP, fragP->fr_fix, 4,
4460 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4461 fragP->fr_fix += 4;
4462 frag_wane (fragP);
4463 }
4464 else if (fragP->fr_opcode[0] == 0x60)
4465 {
4466 fragP->fr_opcode[0] = 0x4E;
4467 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4468 subseg_change (text_section, 0);
4469 fix_new (fragP, fragP->fr_fix, 4,
4470 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4471 fragP->fr_fix += 4;
4472 frag_wane (fragP);
4473 }
4474 else
4475 {
4476 as_warn ("Long branch offset to extern symbol not supported.");
4477 }
4478 }
4479 else
4480 { /* Symbol is still undefined. Make it simple */
4481 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4482 fragP->fr_offset, 1, NO_RELOC);
4483 fragP->fr_fix += 4;
4484 fragP->fr_opcode[1] = (char) 0xff;
4485 frag_wane (fragP);
4486 break;
4487 }
4488
4489 break;
4490 } /* case TAB(ABRANCH,SZ_UNDEF) */
4491
4492 case TAB (FBRANCH, SZ_UNDEF):
4493 {
4494 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4495 {
4496 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4497 fragP->fr_var += 2;
4498 }
4499 else
4500 {
4501 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4502 fragP->fr_offset, 1, NO_RELOC);
4503 fragP->fr_fix += 4;
4504 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4505 frag_wane (fragP);
4506 }
4507 break;
4508 } /* TAB(FBRANCH,SZ_UNDEF) */
4509
4510 case TAB (PCREL, SZ_UNDEF):
4511 {
4512 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4513 || flag_short_refs
4514 || cpu_of_arch (current_architecture) < m68020)
4515 {
4516 fragP->fr_subtype = TAB (PCREL, SHORT);
4517 fragP->fr_var += 2;
4518 }
4519 else
4520 {
4521 fragP->fr_subtype = TAB (PCREL, LONG);
4522 fragP->fr_var += 4;
4523 }
4524 break;
4525 } /* TAB(PCREL,SZ_UNDEF) */
4526
4527 case TAB (BCC68000, SZ_UNDEF):
4528 {
4529 if ((fragP->fr_symbol != NULL)
4530 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4531 {
4532 fragP->fr_subtype = TAB (BCC68000, BYTE);
4533 break;
4534 }
4535 /* only Bcc 68000 instructions can come here */
4536 /* change bcc into b!cc/jmp absl long */
4537 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4538 if (flag_short_refs)
4539 {
4540 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4541 /* JF: these were fr_opcode[2,3] */
4542 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4543 buffer_address[1] = (char) 0xf8;
4544 fragP->fr_fix += 2; /* account for jmp instruction */
4545 subseg_change (text_section, 0);
4546 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4547 fragP->fr_offset, 0, NO_RELOC);
4548 fragP->fr_fix += 2;
4549 }
4550 else
4551 {
4552 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4553 /* JF: these were fr_opcode[2,3] */
4554 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4555 buffer_address[1] = (char) 0xf9;
4556 fragP->fr_fix += 2; /* account for jmp instruction */
4557 subseg_change (text_section, 0);
4558 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4559 fragP->fr_offset, 0, NO_RELOC);
4560 fragP->fr_fix += 4;
4561 }
4562 frag_wane (fragP);
4563 break;
4564 } /* case TAB(BCC68000,SZ_UNDEF) */
4565
4566 case TAB (DBCC, SZ_UNDEF):
4567 {
4568 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4569 {
4570 fragP->fr_subtype = TAB (DBCC, SHORT);
4571 fragP->fr_var += 2;
4572 break;
4573 }
4574 /* only DBcc 68000 instructions can come here */
4575 /* change dbcc into dbcc/jmp absl long */
4576 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4577 buffer_address[0] = 0x00; /* branch offset = 4 */
4578 buffer_address[1] = 0x04;
4579 buffer_address[2] = 0x60; /* put in bra pc + ... */
4580
4581 if (flag_short_refs)
4582 {
4583 /* JF: these were fr_opcode[5-7] */
4584 buffer_address[3] = 0x04; /* plus 4 */
4585 buffer_address[4] = 0x4e; /* Put in Jump Word */
4586 buffer_address[5] = (char) 0xf8;
4587 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4588 subseg_change (text_section, 0);
4589 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4590 fragP->fr_offset, 0, NO_RELOC);
4591 fragP->fr_fix += 2;
4592 }
4593 else
4594 {
4595 /* JF: these were fr_opcode[5-7] */
4596 buffer_address[3] = 0x06; /* Plus 6 */
4597 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4598 buffer_address[5] = (char) 0xf9;
4599 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4600 subseg_change (text_section, 0);
4601 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4602 fragP->fr_offset, 0, NO_RELOC);
4603 fragP->fr_fix += 4;
4604 }
4605
4606 frag_wane (fragP);
4607 break;
4608 } /* case TAB(DBCC,SZ_UNDEF) */
4609
4610 case TAB (PCLEA, SZ_UNDEF):
4611 {
4612 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4613 || flag_short_refs
4614 || cpu_of_arch (current_architecture) < m68020)
4615 {
4616 fragP->fr_subtype = TAB (PCLEA, SHORT);
4617 fragP->fr_var += 2;
4618 }
4619 else
4620 {
4621 fragP->fr_subtype = TAB (PCLEA, LONG);
4622 fragP->fr_var += 6;
4623 }
4624 break;
4625 } /* TAB(PCLEA,SZ_UNDEF) */
4626
4627 case TAB (PCINDEX, SZ_UNDEF):
4628 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4629 || cpu_of_arch (current_architecture) < m68020)
4630 {
4631 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4632 }
4633 else
4634 {
4635 fragP->fr_subtype = TAB (PCINDEX, LONG);
4636 fragP->fr_var += 4;
4637 }
4638 break;
4639
4640 default:
4641 break;
4642 }
4643
4644 /* now that SZ_UNDEF are taken care of, check others */
4645 switch (fragP->fr_subtype)
4646 {
4647 case TAB (BCC68000, BYTE):
4648 case TAB (ABRANCH, BYTE):
4649 /* We can't do a short jump to the next instruction,
4650 so we force word mode. */
4651 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
4652 fragP->fr_symbol->sy_frag == fragP->fr_next)
4653 {
4654 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4655 fragP->fr_var += 2;
4656 }
4657 break;
4658 default:
4659 break;
4660 }
4661 return fragP->fr_var + fragP->fr_fix - old_fix;
4662 }
4663
4664 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4665 /* the bit-field entries in the relocation_info struct plays hell
4666 with the byte-order problems of cross-assembly. So as a hack,
4667 I added this mach. dependent ri twiddler. Ugly, but it gets
4668 you there. -KWK */
4669 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4670 are symbolnum, most sig. byte first. Last byte is broken up with
4671 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4672 nibble as nuthin. (on Sun 3 at least) */
4673 /* Translate the internal relocation information into target-specific
4674 format. */
4675 #ifdef comment
4676 void
4677 md_ri_to_chars (the_bytes, ri)
4678 char *the_bytes;
4679 struct reloc_info_generic *ri;
4680 {
4681 /* this is easy */
4682 md_number_to_chars (the_bytes, ri->r_address, 4);
4683 /* now the fun stuff */
4684 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4685 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4686 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4687 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4688 ((ri->r_extern << 4) & 0x10));
4689 }
4690
4691 #endif /* comment */
4692
4693 #ifndef BFD_ASSEMBLER
4694 void
4695 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4696 char *where;
4697 fixS *fixP;
4698 relax_addressT segment_address_in_file;
4699 {
4700 /*
4701 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4702 * Out: GNU LD relocation length code: 0, 1, or 2.
4703 */
4704
4705 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4706 long r_symbolnum;
4707
4708 know (fixP->fx_addsy != NULL);
4709
4710 md_number_to_chars (where,
4711 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4712 4);
4713
4714 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4715 ? S_GET_TYPE (fixP->fx_addsy)
4716 : fixP->fx_addsy->sy_number);
4717
4718 where[4] = (r_symbolnum >> 16) & 0x0ff;
4719 where[5] = (r_symbolnum >> 8) & 0x0ff;
4720 where[6] = r_symbolnum & 0x0ff;
4721 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4722 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4723 }
4724 #endif
4725
4726 #endif /* OBJ_AOUT or OBJ_BOUT */
4727
4728 #ifndef WORKING_DOT_WORD
4729 CONST int md_short_jump_size = 4;
4730 CONST int md_long_jump_size = 6;
4731
4732 void
4733 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4734 char *ptr;
4735 addressT from_addr, to_addr;
4736 fragS *frag;
4737 symbolS *to_symbol;
4738 {
4739 valueT offset;
4740
4741 offset = to_addr - (from_addr + 2);
4742
4743 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4744 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4745 }
4746
4747 void
4748 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4749 char *ptr;
4750 addressT from_addr, to_addr;
4751 fragS *frag;
4752 symbolS *to_symbol;
4753 {
4754 valueT offset;
4755
4756 if (cpu_of_arch (current_architecture) < m68020)
4757 {
4758 offset = to_addr - S_GET_VALUE (to_symbol);
4759 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4760 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4761 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4762 0, NO_RELOC);
4763 }
4764 else
4765 {
4766 offset = to_addr - (from_addr + 2);
4767 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4768 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4769 }
4770 }
4771
4772 #endif
4773 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
4774
4775 0: Everything is OK
4776 10: Absolute 1:8 only
4777 20: Absolute 0:7 only
4778 30: absolute 0:15 only
4779 40: Absolute 0:31 only
4780 50: absolute 0:127 only
4781 55: absolute -64:63 only
4782 60: absolute -128:127 only
4783 70: absolute 0:4095 only
4784 80: No bignums
4785
4786 */
4787
4788 static int
4789 get_num (exp, ok)
4790 struct m68k_exp *exp;
4791 int ok;
4792 {
4793 #ifdef TEST2
4794 long l = 0;
4795
4796 if (!exp->e_beg)
4797 return 0;
4798 if (*exp->e_beg == '0')
4799 {
4800 if (exp->e_beg[1] == 'x')
4801 sscanf (exp->e_beg + 2, "%x", &l);
4802 else
4803 sscanf (exp->e_beg + 1, "%O", &l);
4804 return l;
4805 }
4806 return atol (exp->e_beg);
4807 #else
4808 char *save_in;
4809 char c_save;
4810 segT section;
4811
4812 if (!exp)
4813 {
4814 /* Can't do anything */
4815 return 0;
4816 }
4817 if (!exp->e_beg || !exp->e_end)
4818 {
4819 seg (exp) = absolute_section;
4820 adds (exp) = 0;
4821 subs (exp) = 0;
4822 offs (exp) = (ok == 10) ? 1 : 0;
4823 as_warn ("Null expression defaults to %ld", offs (exp));
4824 return 0;
4825 }
4826
4827 exp->e_siz = 0;
4828 if ( /* ok!=80 && */ (exp->e_end[-1] == ':' || exp->e_end[-1] == '.')
4829 && (exp->e_end - exp->e_beg) >= 2)
4830 {
4831 switch (exp->e_end[0])
4832 {
4833 case 's':
4834 case 'S':
4835 case 'b':
4836 case 'B':
4837 exp->e_siz = 1;
4838 exp->e_end -= 2;
4839 break;
4840 case 'w':
4841 case 'W':
4842 exp->e_siz = 2;
4843 exp->e_end -= 2;
4844 break;
4845 case 'l':
4846 case 'L':
4847 exp->e_siz = 3;
4848 exp->e_end -= 2;
4849 break;
4850 default:
4851 if (exp->e_end[-1] == ':')
4852 as_bad ("Unknown size for expression \"%c\"", exp->e_end[0]);
4853 break;
4854 }
4855 }
4856 c_save = exp->e_end[1];
4857 exp->e_end[1] = '\0';
4858 save_in = input_line_pointer;
4859 input_line_pointer = exp->e_beg;
4860 section = expression (&exp->e_exp);
4861 seg (exp) = section;
4862 if (exp->e_exp.X_op == O_absent)
4863 {
4864 /* Do the same thing the VAX asm does */
4865 seg (exp) = absolute_section;
4866 op (exp) = O_constant;
4867 adds (exp) = 0;
4868 subs (exp) = 0;
4869 offs (exp) = 0;
4870 if (ok == 10)
4871 {
4872 as_warn ("expression out of range: defaulting to 1");
4873 offs (exp) = 1;
4874 }
4875 }
4876 else if (exp->e_exp.X_op == O_constant)
4877 {
4878 switch (ok)
4879 {
4880 case 10:
4881 if (offs (exp) < 1 || offs (exp) > 8)
4882 {
4883 as_warn ("expression out of range: defaulting to 1");
4884 offs (exp) = 1;
4885 }
4886 break;
4887 case 20:
4888 if (offs (exp) < 0 || offs (exp) > 7)
4889 goto outrange;
4890 break;
4891 case 30:
4892 if (offs (exp) < 0 || offs (exp) > 15)
4893 goto outrange;
4894 break;
4895 case 40:
4896 if (offs (exp) < 0 || offs (exp) > 32)
4897 goto outrange;
4898 break;
4899 case 50:
4900 if (offs (exp) < 0 || offs (exp) > 127)
4901 goto outrange;
4902 break;
4903 case 55:
4904 if (offs (exp) < -64 || offs (exp) > 63)
4905 goto outrange;
4906 break;
4907 case 60:
4908 if (offs (exp) < -128 || offs (exp) > 127)
4909 goto outrange;
4910 break;
4911 case 70:
4912 if (offs (exp) < 0 || offs (exp) > 4095)
4913 {
4914 outrange:
4915 as_warn ("expression out of range: defaulting to 0");
4916 offs (exp) = 0;
4917 }
4918 break;
4919 default:
4920 break;
4921 }
4922 }
4923 else if (exp->e_exp.X_op == O_big)
4924 {
4925 if (offs (exp) <= 0 /* flonum */
4926 && (ok == 80 /* no bignums */
4927 || (ok > 10 /* small-int ranges including 0 ok */
4928 /* If we have a flonum zero, a zero integer should
4929 do as well (e.g., in moveq). */
4930 && generic_floating_point_number.exponent == 0
4931 && generic_floating_point_number.low[0] == 0)))
4932 {
4933 /* HACK! Turn it into a long */
4934 LITTLENUM_TYPE words[6];
4935
4936 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4937 seg (exp) = absolute_section;
4938 op (exp) = O_constant;
4939 adds (exp) = 0;
4940 subs (exp) = 0;
4941 offs (exp) = words[1] | (words[0] << 16);
4942 }
4943 else if (ok != 0)
4944 {
4945 seg (exp) = absolute_section;
4946 op (exp) = O_constant;
4947 adds (exp) = 0;
4948 subs (exp) = 0;
4949 offs (exp) = (ok == 10) ? 1 : 0;
4950 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4951 }
4952 }
4953 else
4954 {
4955 if (ok >= 10 && ok <= 70)
4956 {
4957 seg (exp) = absolute_section;
4958 op (exp) = O_constant;
4959 adds (exp) = 0;
4960 subs (exp) = 0;
4961 offs (exp) = (ok == 10) ? 1 : 0;
4962 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4963 }
4964 }
4965
4966 if (input_line_pointer != exp->e_end + 1)
4967 as_bad ("Ignoring junk after expression");
4968 exp->e_end[1] = c_save;
4969 input_line_pointer = save_in;
4970 if (exp->e_siz)
4971 {
4972 switch (exp->e_siz)
4973 {
4974 case 1:
4975 if (!isbyte (offs (exp)))
4976 as_warn ("expression doesn't fit in BYTE");
4977 break;
4978 case 2:
4979 if (!isword (offs (exp)))
4980 as_warn ("expression doesn't fit in WORD");
4981 break;
4982 }
4983 }
4984 return offs (exp);
4985 #endif
4986 }
4987
4988 /* These are the back-ends for the various machine dependent pseudo-ops. */
4989 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4990
4991 static void
4992 s_data1 (ignore)
4993 int ignore;
4994 {
4995 subseg_set (data_section, 1);
4996 demand_empty_rest_of_line ();
4997 }
4998
4999 static void
5000 s_data2 (ignore)
5001 int ignore;
5002 {
5003 subseg_set (data_section, 2);
5004 demand_empty_rest_of_line ();
5005 }
5006
5007 static void
5008 s_bss (ignore)
5009 int ignore;
5010 {
5011 /* We don't support putting frags in the BSS segment, we fake it
5012 by marking in_bss, then looking at s_skip for clues. */
5013
5014 subseg_set (bss_section, 0);
5015 demand_empty_rest_of_line ();
5016 }
5017
5018 static void
5019 s_even (ignore)
5020 int ignore;
5021 {
5022 register int temp;
5023 register long temp_fill;
5024
5025 temp = 1; /* JF should be 2? */
5026 temp_fill = get_absolute_expression ();
5027 if (!need_pass_2) /* Never make frag if expect extra pass. */
5028 frag_align (temp, (int) temp_fill);
5029 demand_empty_rest_of_line ();
5030 }
5031
5032 static void
5033 s_proc (ignore)
5034 int ignore;
5035 {
5036 demand_empty_rest_of_line ();
5037 }
5038
5039 /* s_space is defined in read.c .skip is simply an alias to it. */
5040
5041 \f
5042 /*
5043 * md_parse_option
5044 * Invocation line includes a switch not recognized by the base assembler.
5045 * See if it's a processor-specific option. These are:
5046 *
5047 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
5048 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
5049 * Select the architecture. Instructions or features not
5050 * supported by the selected architecture cause fatal
5051 * errors. More than one may be specified. The default is
5052 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
5053 * for -m68000, and -m68882 is a synonym for -m68881.
5054 * -[A]m[c]no-68851, -[A]m[c]no-68881
5055 * Don't accept 688?1 instructions. (The "c" is kind of silly,
5056 * so don't use or document it, but that's the way the parsing
5057 * works).
5058 *
5059 * -pic Indicates PIC.
5060 * -k Indicates PIC. (Sun 3 only.)
5061 *
5062 */
5063
5064 #ifdef OBJ_ELF
5065 CONST char *md_shortopts = "lSA:m:kQ:V";
5066 #else
5067 CONST char *md_shortopts = "lSA:m:k";
5068 #endif
5069
5070 struct option md_longopts[] = {
5071 #define OPTION_PIC (OPTION_MD_BASE)
5072 {"pic", no_argument, NULL, OPTION_PIC},
5073 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
5074 {"register-prefix-optional", no_argument, NULL,
5075 OPTION_REGISTER_PREFIX_OPTIONAL},
5076 {NULL, no_argument, NULL, 0}
5077 };
5078 size_t md_longopts_size = sizeof(md_longopts);
5079
5080 int
5081 md_parse_option (c, arg)
5082 int c;
5083 char *arg;
5084 {
5085 int i;
5086 unsigned long arch;
5087
5088 switch (c)
5089 {
5090 case 'l': /* -l means keep external to 2 bit offset
5091 rather than 16 bit one */
5092 flag_short_refs = 1;
5093 break;
5094
5095 case 'S': /* -S means that jbsr's always turn into
5096 jsr's. */
5097 flag_long_jumps = 1;
5098 break;
5099
5100 case 'A':
5101 if (*arg == 'm')
5102 arg++;
5103 /* intentional fall-through */
5104 case 'm':
5105
5106 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
5107 {
5108 int i, arch;
5109 const char *oarg = arg;
5110
5111 arg += 3;
5112 if (*arg == 'm')
5113 {
5114 arg++;
5115 if (arg[0] == 'c' && arg[1] == '6')
5116 arg++;
5117 }
5118 for (i = 0; i < n_archs; i++)
5119 if (!strcmp (arg, archs[i].name))
5120 break;
5121 if (i == n_archs)
5122 {
5123 unknown:
5124 as_bad ("unrecognized option `%s'", oarg);
5125 return 0;
5126 }
5127 arch = archs[i].arch;
5128 if (arch == m68881)
5129 no_68881 = 1;
5130 else if (arch == m68851)
5131 no_68851 = 1;
5132 else
5133 goto unknown;
5134 }
5135 else
5136 {
5137 int i;
5138
5139 if (arg[0] == 'c' && arg[1] == '6')
5140 arg++;
5141
5142 for (i = 0; i < n_archs; i++)
5143 if (!strcmp (arg, archs[i].name))
5144 {
5145 unsigned long arch = archs[i].arch;
5146 if (cpu_of_arch (arch))
5147 /* It's a cpu spec. */
5148 {
5149 current_architecture &= ~m68000up;
5150 current_architecture |= arch;
5151 }
5152 else if (arch == m68881)
5153 {
5154 current_architecture |= m68881;
5155 no_68881 = 0;
5156 }
5157 else if (arch == m68851)
5158 {
5159 current_architecture |= m68851;
5160 no_68851 = 0;
5161 }
5162 else
5163 /* ??? */
5164 abort ();
5165 break;
5166 }
5167 if (i == n_archs)
5168 {
5169 as_bad ("unrecognized architecture specification `%s'", arg);
5170 return 0;
5171 }
5172 }
5173 break;
5174
5175 case OPTION_PIC:
5176 case 'k':
5177 flag_want_pic = 1;
5178 break; /* -pic, Position Independent Code */
5179
5180 case OPTION_REGISTER_PREFIX_OPTIONAL:
5181 flag_reg_prefix_optional = 1;
5182 break;
5183
5184 case 'Q':
5185 case 'V':
5186 break;
5187
5188 default:
5189 return 0;
5190 }
5191
5192 return 1;
5193 }
5194
5195 void
5196 md_show_usage (stream)
5197 FILE *stream;
5198 {
5199 fprintf(stream, "\
5200 680X0 options:\n\
5201 -l use 1 word for refs to undefined symbols [default 2]\n\
5202 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
5203 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
5204 | -mcpu32\n\
5205 specify variant of 680X0 architecture [default 68020]\n\
5206 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
5207 target has/lacks floating-point coprocessor\n\
5208 [default yes for 68020, 68030, and cpu32]\n\
5209 -m68851 | -mno-68851\n\
5210 target has/lacks memory-management unit coprocessor\n\
5211 [default yes for 68020 and up]\n\
5212 -pic, -k generate position independent code\n\
5213 -S turn jbsr into jsr\n\
5214 --register-prefix-optional\n\
5215 recognize register names without prefix character\n");
5216 }
5217 \f
5218 #ifdef TEST2
5219
5220 /* TEST2: Test md_assemble() */
5221 /* Warning, this routine probably doesn't work anymore */
5222
5223 main ()
5224 {
5225 struct m68k_it the_ins;
5226 char buf[120];
5227 char *cp;
5228 int n;
5229
5230 m68k_ip_begin ();
5231 for (;;)
5232 {
5233 if (!gets (buf) || !*buf)
5234 break;
5235 if (buf[0] == '|' || buf[1] == '.')
5236 continue;
5237 for (cp = buf; *cp; cp++)
5238 if (*cp == '\t')
5239 *cp = ' ';
5240 if (is_label (buf))
5241 continue;
5242 memset (&the_ins, '\0', sizeof (the_ins));
5243 m68k_ip (&the_ins, buf);
5244 if (the_ins.error)
5245 {
5246 printf ("Error %s in %s\n", the_ins.error, buf);
5247 }
5248 else
5249 {
5250 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
5251 for (n = 0; n < the_ins.numo; n++)
5252 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
5253 printf (" ");
5254 print_the_insn (&the_ins.opcode[0], stdout);
5255 (void) putchar ('\n');
5256 }
5257 for (n = 0; n < strlen (the_ins.args) / 2; n++)
5258 {
5259 if (the_ins.operands[n].error)
5260 {
5261 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
5262 continue;
5263 }
5264 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
5265 if (the_ins.operands[n].b_const)
5266 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
5267 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
5268 if (the_ins.operands[n].b_iadd)
5269 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
5270 (void) putchar ('\n');
5271 }
5272 }
5273 m68k_ip_end ();
5274 return 0;
5275 }
5276
5277 is_label (str)
5278 char *str;
5279 {
5280 while (*str == ' ')
5281 str++;
5282 while (*str && *str != ' ')
5283 str++;
5284 if (str[-1] == ':' || str[1] == '=')
5285 return 1;
5286 return 0;
5287 }
5288
5289 #endif
5290
5291 /* Possible states for relaxation:
5292
5293 0 0 branch offset byte (bra, etc)
5294 0 1 word
5295 0 2 long
5296
5297 1 0 indexed offsets byte a0@(32,d4:w:1) etc
5298 1 1 word
5299 1 2 long
5300
5301 2 0 two-offset index word-word a0@(32,d4)@(45) etc
5302 2 1 word-long
5303 2 2 long-word
5304 2 3 long-long
5305
5306 */
5307
5308 /* We have no need to default values of symbols. */
5309
5310 /* ARGSUSED */
5311 symbolS *
5312 md_undefined_symbol (name)
5313 char *name;
5314 {
5315 return 0;
5316 }
5317
5318 /* Round up a section size to the appropriate boundary. */
5319 valueT
5320 md_section_align (segment, size)
5321 segT segment;
5322 valueT size;
5323 {
5324 return size; /* Byte alignment is fine */
5325 }
5326
5327 /* Exactly what point is a PC-relative offset relative TO?
5328 On the 68k, it is relative to the address of the first extension
5329 word. The difference between the addresses of the offset and the
5330 first extension word is stored in fx_pcrel_adjust. */
5331 long
5332 md_pcrel_from (fixP)
5333 fixS *fixP;
5334 {
5335 return (fixP->fx_where + fixP->fx_frag->fr_address - fixP->fx_pcrel_adjust);
5336 }
5337
5338 #ifndef BFD_ASSEMBLER
5339 /*ARGSUSED*/
5340 void
5341 tc_coff_symbol_emit_hook (ignore)
5342 symbolS *ignore;
5343 {
5344 }
5345
5346 int
5347 tc_coff_sizemachdep (frag)
5348 fragS *frag;
5349 {
5350 switch (frag->fr_subtype & 0x3)
5351 {
5352 case BYTE:
5353 return 1;
5354 case SHORT:
5355 return 2;
5356 case LONG:
5357 return 4;
5358 default:
5359 abort ();
5360 }
5361 }
5362 #endif
5363
5364 /* end of tc-m68k.c */
GDB Binutils - Deliverables
This page took 0.143952 seconds and 4 git commands to generate.