1 /* All the m68k specific stuff in one convenient, huge, slow to
2 compile, easy to find file.
4 Copyright (C) 1987, 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 /* The opcode table is too big for some versions of gcc, which require
28 exponential(?) space at compile time for initialized arrays. */
30 #define DO_BREAK_UP_BIG_DECL
31 #define BREAK_UP_BIG_DECL }; struct m68k_opcode m68k_opcodes_2[] = {
32 #define AND_OTHER_PART sizeof (m68k_opcodes_2)
35 /* Note that this file includes real declarations and thus can only be
36 included by one source file per executable. */
37 #include "opcode/m68k.h"
39 /* This array holds the chars that always start a comment. If the
40 pre-processor is disabled, these aren't very useful */
42 CONST
char comment_chars
[] = "|#";
44 CONST
char comment_chars
[] = "|";
47 /* This array holds the chars that only start a comment at the beginning of
48 a line. If the line seems to have the form '# 123 filename'
49 .line and .file directives will appear in the pre-processed output */
50 /* Note that input_file.c hand checks for '#' at the beginning of the
51 first line of the input file. This is because the compiler outputs
52 #NO_APP at the beginning of its output. */
53 /* Also note that comments like this one will always work. */
54 CONST
char line_comment_chars
[] = "#";
56 CONST
char line_separator_chars
[] = "";
58 /* Chars that can be used to separate mant from exp in floating point nums */
59 CONST
char EXP_CHARS
[] = "eE";
61 /* Chars that mean this number is a floating point constant, as
62 in "0f12.456" or "0d1.2345e12". */
64 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
66 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
67 changed in read.c . Ideally it shouldn't have to know about it at all,
68 but nothing is ideal around here. */
70 const int md_reloc_size
= 8; /* Size of relocation record */
72 /* Are we trying to generate PIC code? If so, absolute references
73 ought to be made into linkage table references or pc-relative
77 static int flag_short_refs
; /* -l option */
78 static int flag_long_jumps
; /* -S option */
80 #ifdef REGISTER_PREFIX_OPTIONAL
81 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
83 int flag_reg_prefix_optional
;
86 /* Its an arbitrary name: This means I don't approve of it */
87 /* See flames below */
88 static struct obstack robyn
;
90 #define TAB(x,y) (((x)<<2)+(y))
91 #define TABTYPE(xy) ((xy) >> 2)
97 /* Case `g' except when BCC68000 is applicable. */
99 /* Coprocessor branches. */
101 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
102 supported on all cpus. Widens to 32-bit absolute. */
104 /* For inserting an extra jmp instruction with long offset on 68000,
105 for expanding conditional branches. (Not bsr or bra.) Since the
106 68000 doesn't support 32-bit displacements for conditional
107 branches, we fake it by reversing the condition and branching
108 around a jmp with an absolute long operand. */
110 /* For the DBcc "instructions". If the displacement requires 32 bits,
111 the branch-around-a-jump game is played here too. */
113 /* Not currently used? */
115 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
122 unsigned long m_opcode
;
126 struct m68k_incant
*m_next
;
129 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
130 #define gettwo(x) (((x)->m_opcode)&0xffff)
132 /* Operands we can parse: (And associated modes)
138 reg: address or data register
139 areg: address register
140 apc: address register, PC, ZPC or empty string
141 num: 16 or 32 bit num
143 sz: w or l if omitted, l assumed
144 scale: 1 2 4 or 8 if omitted, 1 assumed
146 7.4 IMMED #num --> NUM
147 0.? DREG dreg --> dreg
148 1.? AREG areg --> areg
149 2.? AINDR areg@ --> *(areg)
150 3.? AINC areg@+ --> *(areg++)
151 4.? ADEC areg@- --> *(--areg)
152 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
153 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
154 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
155 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
156 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
157 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
158 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
159 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
160 7.0 ABSL num:sz --> *(num)
161 num --> *(num) (sz L assumed)
162 *** MSCR otherreg --> Magic
164 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
165 ?.? DINDR dreg@ --> (dreg) -- cas2 only
175 a1@(5,d2:w:1) @(45,d6:l:4)
180 #name@(numw) -->turn into PC rel mode
181 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
211 short e_siz
; /* 0== default 1==short/byte 2==word 3==long */
214 /* DATA and ADDR have to be contiguous, so that reg-DATA gives
215 0-7==data reg, 8-15==addr reg for operands that take both types.
217 We don't use forms like "ADDR0 = ADDR" here because this file is
218 likely to be used on an Apollo, and the broken Apollo compiler
219 gives an `undefined variable' error if we do that, according to
220 troy@cbme.unsw.edu.au. */
232 DATA0
= 1, /* 1- 8 == data registers 0-7 */
250 FP0
, /* Eight FP registers */
259 /* Note that COP0==processor #1 -- COP0+7==#8, which stores as 000 */
262 COP0
, /* Co-processor #1-#8 */
271 PC
, /* Program counter */
272 ZPC
, /* Hack for Program space, but 0 addressing */
274 CCR
, /* Condition code Reg */
276 /* These have to be grouped together for the movec instruction to work. */
277 USP
, /* User Stack Pointer */
278 ISP
, /* Interrupt stack pointer */
293 BUSCR
, /* 68060 added these */
295 #define last_movec_reg PCR
296 /* end of movec ordering constraints */
302 DRP
, /* 68851 or 68030 MMU regs */
324 PSR
, /* aka MMUSR on 68030 (but not MMUSR on 68040)
325 and ACUSR on 68ec030 */
328 IC
, /* instruction cache token */
329 DC
, /* data cache token */
330 NC
, /* no cache token */
331 BC
, /* both caches token */
333 TT0
, /* 68030 access control unit regs */
337 static const enum _register m68000_control_regs
[] = { 0 };
338 static const enum _register m68010_control_regs
[] = {
342 static const enum _register m68020_control_regs
[] = {
343 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
346 static const enum _register m68040_control_regs
[] = {
347 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
348 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
351 static const enum _register m68060_control_regs
[] = {
352 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
353 USP
, VBR
, URP
, SRP
, PCR
,
356 #define cpu32_control_regs m68010_control_regs
358 static const enum _register
*control_regs
;
360 /* Internal form of an operand. */
363 char *error
; /* Couldn't parse it */
364 enum operand_type mode
; /* What mode this instruction is in. */
365 enum _register reg
; /* Base register */
366 struct m68k_exp
*con1
;
367 int ireg
; /* Index register */
368 int isiz
; /* 0==unspec 1==byte(?) 2==short 3==long */
369 int imul
; /* Multipy ireg by this (1,2,4,or 8) */
370 struct m68k_exp
*con2
;
373 /* internal form of a 68020 instruction */
377 char *args
; /* list of opcode info */
380 int numo
; /* Number of shorts in opcode */
383 struct m68k_op operands
[6];
385 int nexp
; /* number of exprs in use */
386 struct m68k_exp exprs
[4];
388 int nfrag
; /* Number of frags we have to produce */
391 int fragoff
; /* Where in the current opcode[] the frag ends */
398 int nrel
; /* Num of reloc strucs in use */
405 /* In a pc relative address the difference between the address
406 of the offset and the address that the offset is relative
407 to. This depends on the addressing mode. Basically this
408 is the value to put in the offset field to address the
409 first byte of the offset, without regarding the special
410 significance of some values (in the branch instruction, for
414 reloc
[5]; /* Five is enough??? */
417 #define cpu_of_arch(x) ((x) & m68000up)
418 #define float_of_arch(x) ((x) & mfloat)
419 #define mmu_of_arch(x) ((x) & mmmu)
421 static struct m68k_it the_ins
; /* the instruction being assembled */
423 #define seg(exp) ((exp)->e_seg)
424 #define op(exp) ((exp)->e_exp.X_op)
425 #define adds(exp) ((exp)->e_exp.X_add_symbol)
426 #define subs(exp) ((exp)->e_exp.X_op_symbol)
427 #define offs(exp) ((exp)->e_exp.X_add_number)
429 /* Macros for adding things to the m68k_it struct */
431 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
433 /* Like addword, but goes BEFORE general operands */
437 struct m68k_incant
*opcode
;
440 for(z
=the_ins
.numo
;z
>opcode
->m_codenum
;--z
)
441 the_ins
.opcode
[z
]=the_ins
.opcode
[z
-1];
442 for(z
=0;z
<the_ins
.nrel
;z
++)
443 the_ins
.reloc
[z
].n
+=2;
444 for (z
= 0; z
< the_ins
.nfrag
; z
++)
445 the_ins
.fragb
[z
].fragoff
++;
446 the_ins
.opcode
[opcode
->m_codenum
]=w
;
450 static struct m68k_exp
*
455 the_ins
.exprs
[the_ins
.nexp
].e_beg
=beg
;
456 the_ins
.exprs
[the_ins
.nexp
].e_end
=end
;
457 return &the_ins
.exprs
[the_ins
.nexp
++];
461 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
464 add_fix (width
, exp
, pc_rel
, pc_fix
)
466 struct m68k_exp
*exp
;
470 the_ins
.reloc
[the_ins
.nrel
].n
= (((width
)=='B')
474 : (the_ins
.numo
*2)));
475 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->e_exp
;
476 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
477 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
478 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
481 /* Cause an extra frag to be generated here, inserting up to 10 bytes
482 (that value is chosen in the frag_var call in md_assemble). TYPE
483 is the subtype of the frag to be generated; its primary type is
484 rs_machine_dependent.
486 The TYPE parameter is also used by md_convert_frag_1 and
487 md_estimate_size_before_relax. The appropriate type of fixup will
488 be emitted by md_convert_frag_1.
490 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
492 add_frag(add
,off
,type
)
497 the_ins
.fragb
[the_ins
.nfrag
].fragoff
=the_ins
.numo
;
498 the_ins
.fragb
[the_ins
.nfrag
].fadd
=add
;
499 the_ins
.fragb
[the_ins
.nfrag
].foff
=off
;
500 the_ins
.fragb
[the_ins
.nfrag
++].fragty
=type
;
504 ((exp) && op (exp) != O_constant && op (exp) != O_big)
506 static char *crack_operand
PARAMS ((char *str
, struct m68k_op
*opP
));
507 static int get_num
PARAMS ((struct m68k_exp
*exp
, int ok
));
508 static int get_regs
PARAMS ((int i
, char *str
, struct m68k_op
*opP
));
509 static int reverse_16_bits
PARAMS ((int in
));
510 static int reverse_8_bits
PARAMS ((int in
));
511 static int try_index
PARAMS ((char **s
, struct m68k_op
*opP
));
512 static void install_gen_operand
PARAMS ((int mode
, int val
));
513 static void install_operand
PARAMS ((int mode
, int val
));
514 static void s_bss
PARAMS ((int));
515 static void s_data1
PARAMS ((int));
516 static void s_data2
PARAMS ((int));
517 static void s_even
PARAMS ((int));
518 static void s_proc
PARAMS ((int));
520 static int current_architecture
;
527 static const struct m68k_cpu archs
[] = {
537 /* Aliases (effectively, so far as gas is concerned) for the above
550 static const int n_archs
= sizeof (archs
) / sizeof (archs
[0]);
552 /* BCC68000 is for patching in an extra jmp instruction for long offsets
553 on the 68000. The 68000 doesn't support long branches with branchs */
555 /* This table desribes how you change sizes for the various types of variable
556 size expressions. This version only supports two kinds. */
558 /* Note that calls to frag_var need to specify the maximum expansion
559 needed; this is currently 10 bytes for DBCC. */
562 How far Forward this mode will reach:
563 How far Backward this mode will reach:
564 How many bytes this mode will add to the size of the frag
565 Which mode to go to if the offset won't fit in this one
567 relax_typeS md_relax_table
[] =
569 {1, 1, 0, 0}, /* First entries aren't used */
570 {1, 1, 0, 0}, /* For no good reason except */
571 {1, 1, 0, 0}, /* that the VAX doesn't either */
574 {(127), (-128), 0, TAB (ABRANCH
, SHORT
)},
575 {(32767), (-32768), 2, TAB (ABRANCH
, LONG
)},
579 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
580 {(32767), (-32768), 2, TAB (FBRANCH
, LONG
)},
584 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
585 {(32767), (-32768), 2, TAB (PCREL
, LONG
)},
589 {(127), (-128), 0, TAB (BCC68000
, SHORT
)},
590 {(32767), (-32768), 2, TAB (BCC68000
, LONG
)},
591 {0, 0, 6, 0}, /* jmp long space */
594 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
595 {(32767), (-32768), 2, TAB (DBCC
, LONG
)},
596 {0, 0, 10, 0}, /* bra/jmp long space */
599 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
600 {32767, -32768, 2, TAB (PCLEA
, LONG
)},
604 /* For, e.g., jmp pcrel indexed. */
605 {125, -130, 0, TAB (PCINDEX
, SHORT
)},
606 {32765, -32770, 2, TAB (PCINDEX
, LONG
)},
611 /* These are the machine dependent pseudo-ops. These are included so
612 the assembler can work on the output from the SUN C compiler, which
616 /* This table describes all the machine specific pseudo-ops the assembler
617 has to support. The fields are:
618 pseudo-op name without dot
619 function to call to execute this pseudo-op
620 Integer arg to pass to the function
622 CONST pseudo_typeS md_pseudo_table
[] =
624 {"data1", s_data1
, 0},
625 {"data2", s_data2
, 0},
628 {"skip", s_space
, 0},
631 {"align", s_align_bytes
, 0},
634 {"swbeg", s_ignore
, 0},
640 /* The mote pseudo ops are put into the opcode table, since they
641 don't start with a . they look like opcodes to gas.
643 extern void obj_coff_section ();
645 CONST pseudo_typeS mote_pseudo_table
[] =
658 {"xdef", s_globl
, 0},
659 {"align", s_align_ptwo
, 0},
661 {"sect", obj_coff_section
, 0},
662 {"section", obj_coff_section
, 0},
667 #define issbyte(x) ((x)>=-128 && (x)<=127)
668 #define isubyte(x) ((x)>=0 && (x)<=255)
669 #define issword(x) ((x)>=-32768 && (x)<=32767)
670 #define isuword(x) ((x)>=0 && (x)<=65535)
672 #define isbyte(x) ((x)>= -255 && (x)<=255)
673 #define isword(x) ((x)>=-32768 && (x)<=65535)
674 #define islong(x) (1)
676 extern char *input_line_pointer
;
684 static char mklower_table
[256];
685 #define mklower(c) (mklower_table[(unsigned char)(c)])
686 static char notend_table
[256];
687 static char alt_notend_table
[256];
688 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
689 alt_notend_table[(unsigned char)(s[1])])))
691 /* JF modified this to handle cases where the first part of a symbol name
692 looks like a register */
695 * m68k_reg_parse() := if it looks like a register, return it's token &
696 * advance the pointer.
708 if (flag_reg_prefix_optional
)
710 if (*start
== REGISTER_PREFIX
)
716 if (*start
!= REGISTER_PREFIX
)
721 if (!isalpha (*p
) || !is_name_beginner (*p
))
725 while (isalpha (c
) || isdigit (c
) || c
== '_')
731 symbolP
= symbol_find (start
);
734 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
737 return S_GET_VALUE (symbolP
);
743 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
744 #define SKIP_W() { ss++; if(*ss==' ') ss++;}
746 /* Parse an index specification using Motorola syntax. */
749 try_moto_index (s
, opP
)
760 i
= m68k_reg_parse (&ss
);
761 if (!(i
>= DATA
+ 0 && i
<= ADDR
+ 7))
762 { /* if i is not DATA or ADDR reg */
763 opP
->error
= "Invalid index register";
779 opP
->error
= "Missing . in index register";
784 if (mklower (*ss
) == 'w')
786 else if (mklower (*ss
) == 'l')
790 opP
->error
= "Size spec not .W or .L";
795 if (*ss
== '.' || *ss
== '*')
804 opP
->imul
= *ss
- '0';
807 opP
->error
= "index multiplier not 1, 2, 4 or 8";
817 opP
->error
= "Missing )";
828 * try_index := data_or_address_register + ')' + SKIP_W
829 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
831 * multiplier := <empty>
832 * | ':' + multiplier_number
835 * multiplier_number := '1' | '2' | '4' | '8' ;
837 * size_spec := 'l' | 'L' | 'w' | 'W' ;
839 * SKIP_W := <empty> | ' ' ;
853 i
= m68k_reg_parse (&ss
);
854 if (!(i
>= DATA
+ 0 && i
<= ADDR
+ 7))
855 { /* if i is not DATA or ADDR reg */
871 opP
->error
= "Missing : in index register";
887 opP
->error
= "Index register size spec not :w or :l";
901 if (cpu_of_arch (current_architecture
) < m68020
)
903 opP
->error
= "no index scaling in pre-68020's";
907 opP
->imul
= *ss
- '0';
910 opP
->error
= "index multiplier not 1, 2, 4 or 8";
920 opP
->error
= "Missing )";
929 /* Ian Taylor expanded this function to accept both MIT and Motorola
930 syntax. I removed the old comment, since it was wrong. The syntax
931 this accepted even before my changes was complex and undocumented.
932 I mainly added a large case when the operand string does not
933 contain an '@', since the Motorola syntax does not use the '@'
937 m68k_ip_op (str
, opP
)
939 register struct m68k_op
*opP
;
943 char *parse_index ();
949 } /* Find the beginning of the string */
953 opP
->error
= "Missing operand";
957 for (strend
= str
; *strend
; strend
++)
961 if (*str
== '#' || *str
== '&')
964 opP
->con1
= add_exp (str
, strend
);
967 } /* Guess what: A constant. Shar and enjoy */
969 i
= m68k_reg_parse (&str
);
973 if (*str
== '/' || *str
== '-')
975 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
977 return get_regs (i
, str
, opP
);
982 /* "Rn" Register Direct mode */
983 if (i
>= DATA
+ 0 && i
<= DATA
+ 7)
985 else if (i
>= ADDR
+ 0 && i
<= ADDR
+ 7)
997 if ((stmp
= strchr (str
, '@')) != 0)
999 opP
->con1
= add_exp (str
, stmp
- 1);
1006 if ((current_architecture
& m68020up
) == 0)
1009 } /* if target is not a '20 or better */
1012 if (*stmp
++ != '(' || *strend
-- != ')')
1014 opP
->error
= "Malformed operand";
1017 i
= try_index (&stmp
, opP
);
1018 opP
->con2
= add_exp (stmp
, strend
);
1029 } /* if there's an '@' */
1031 #ifndef MIT_SYNTAX_ONLY
1032 /* The operand has no '@'. Try to parse it using
1034 /* Logic of the parsing switch(*str):
1038 REG AREG or DREG or MSCR 3 or 2 or 13
1039 REG- or REG/ REGLST 14
1044 (EXPR,REG,INDX) AINDX 8
1047 EXP2(REG,INDX) AINDX 8
1050 REG means truth(m68k_reg_parse(&str))
1051 INDX means truth(try_moto_index(&str,opP))
1053 EXP2 means not REG and not '(' and not '-('
1059 i
= m68k_reg_parse (&str
);
1060 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7)
1061 && (i
< DATA
+ 0 || i
> DATA
+ 7
1062 || *str
!= ')' || str
[1] != '0')
1063 && i
!= PC
&& i
!= ZPC
&& i
!= FAIL
)
1065 /* Can't indirect off non address regs */
1066 opP
->error
= "Invalid indirect register";
1077 /* "(An)" Address Register Indirect mode
1078 or "(Dn)" for cas2. */
1079 if (i
>= DATA
+ 0 && i
<= DATA
+ 7)
1089 /* "(An)+" Register Indirect w Postincrement */
1094 opP
->error
= "Junk after indirect";
1100 i
= try_moto_index (&str
, opP
);
1103 /* "(An,Rn)" Register Indirect with Index mode*/
1109 opP
->error
= "Bad indirect syntax";
1115 /* "(EXPR,..." , a displacement */
1118 if ((stmp
= strchr (str
, ',')) != NULL
)
1120 opP
->con1
= add_exp (str
, stmp
- 1);
1123 i
= m68k_reg_parse (&str
);
1124 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
&& i
!= ZPC
)
1126 /* Can't indirect off non address regs */
1127 opP
->error
= "Invalid indirect register";
1135 /* "(d,An)" Register Indirect w Displacement */
1142 i
= try_moto_index (&str
, opP
);
1145 /* "(d,An,Rn)" Register Indirect with Index */
1151 opP
->error
= "Bad indirect syntax";
1157 opP
->error
= "Invalid register";
1164 opP
->con1
= add_exp (str
- 1, strend
);
1175 i
= m68k_reg_parse (&str
);
1176 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
&& i
!= ZPC
&& i
!= FAIL
)
1178 /* Can't indirect off non address regs */
1179 opP
->error
= "Invalid indirect register";
1190 /* "-(An)" Register Indirect with Predecrement */
1194 opP
->error
= "Junk after indirect";
1197 opP
->error
= "Bad indirect syntax";
1201 opP
->con1
= add_exp (str
- 2, strend
);
1204 /* if '-' but not "-(', do nothing */
1207 /* whether *str=='-' or not */
1209 /* "EXP2" or "EXP2(REG..." */
1211 if ((stmp
= strchr (str
, '(')) != NULL
)
1215 opP
->con1
= add_exp (str
, stmp
- 1);
1217 i
= m68k_reg_parse (&str
);
1218 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
1219 && i
!= ZPC
&& i
!= FAIL
)
1221 /* Can't indirect off non address regs */
1222 opP
->error
= "Invalid indirect register";
1230 /* "d(An)" Register Indirect w Displacement */
1237 i
= try_moto_index (&str
, opP
);
1240 /* "d(An,Rn)" Register Indirect with Index */
1246 opP
->error
= "Bad indirect syntax";
1253 opP
->con1
= add_exp (ostr
, strend
);
1259 /* "EXP2" Absolute */
1262 if (strend
[-1] == '.' || strend
[-1] == ':')
1264 /* mode ==foo.[wl] */
1277 opP
->con1
= add_exp (str
, strend
);
1282 #else /* defined (MIT_SYNTAX_ONLY) */
1284 opP
->con1
= add_exp (str
, strend
);
1286 #endif /* defined (MIT_SYNTAX_ONLY) */
1291 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1292 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
&& i
!= ZPC
&& i
!= FAIL
1293 && (str
[1] != '\0' || i
< DATA
+ 0 || i
> DATA
+ 7))
1295 opP
->error
= "Invalid indirect register";
1304 if (i
< DATA
+ 0 || i
> DATA
+ 7)
1319 opP
->error
= "Junk after indirect";
1322 /* Some kind of indexing involved. Lets find out how bad it is */
1323 i
= try_index (&str
, opP
);
1324 /* Didn't start with an index reg, maybe its offset or offset,reg */
1335 opP
->error
= "Missing )";
1348 opP
->con1
= add_exp (beg_str
, str
- 2);
1349 /* Should be offset,reg */
1352 i
= try_index (&str
, opP
);
1355 opP
->error
= "Malformed index reg";
1360 /* We've now got offset) offset,reg) or reg) */
1364 /* Th-the-thats all folks */
1365 if (opP
->reg
== FAIL
)
1366 opP
->mode
= AINDX
; /* Other form of indirect */
1367 else if (opP
->ireg
== FAIL
)
1373 /* Next thing had better be another @ */
1388 if ((current_architecture
& m68020up
) == 0)
1391 } /* if target is not a '20 or better */
1394 if (opP
->ireg
!= FAIL
)
1398 i
= try_index (&str
, opP
);
1401 opP
->error
= "Two index registers! not allowed!";
1407 i
= try_index (&str
, opP
);
1422 opP
->error
= "Missing )";
1437 opP
->con2
= add_exp (beg_str
, str
- 2);
1441 if (opP
->ireg
!= FAIL
)
1443 opP
->error
= "Can't have two index regs";
1447 i
= try_index (&str
, opP
);
1451 opP
->error
= "malformed index reg";
1457 else if (opP
->ireg
!= FAIL
)
1473 opP
->error
= "Junk after indirect";
1480 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
1482 #ifdef NO_PCREL_RELOCS
1485 make_pcrel_absolute(fixP
, add_number
)
1489 register unsigned char *opcode
= fixP
->fx_frag
->fr_opcode
;
1491 /* rewrite the PC relative instructions to absolute address ones.
1492 * these are rumoured to be faster, and the apollo linker refuses
1493 * to deal with the PC relative relocations.
1495 if (opcode
[0] == 0x60 && opcode
[1] == 0xff) /* BRA -> JMP */
1500 else if (opcode
[0] == 0x61 && opcode
[1] == 0xff) /* BSR -> JSR */
1506 as_fatal ("Unknown PC relative instruction");
1511 #endif /* NO_PCREL_RELOCS */
1514 tc_coff_fix2rtype (fixP
)
1517 #ifdef NO_PCREL_RELOCS
1518 know (fixP
->fx_pcrel
== 0);
1519 return (fixP
->fx_size
== 1 ? R_RELBYTE
1520 : fixP
->fx_size
== 2 ? R_DIR16
1523 return (fixP
->fx_pcrel
?
1524 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
1525 fixP
->fx_size
== 2 ? R_PCRWORD
:
1527 (fixP
->fx_size
== 1 ? R_RELBYTE
:
1528 fixP
->fx_size
== 2 ? R_RELWORD
:
1535 #ifdef BFD_ASSEMBLER
1538 tc_gen_reloc (section
, fixp
)
1543 bfd_reloc_code_real_type code
;
1545 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1546 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
1548 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1549 MAP (1, 0, BFD_RELOC_8
);
1550 MAP (2, 0, BFD_RELOC_16
);
1551 MAP (4, 0, BFD_RELOC_32
);
1552 MAP (1, 1, BFD_RELOC_8_PCREL
);
1553 MAP (2, 1, BFD_RELOC_16_PCREL
);
1554 MAP (4, 1, BFD_RELOC_32_PCREL
);
1559 reloc
= (arelent
*) bfd_alloc_by_size_t (stdoutput
, sizeof (arelent
));
1560 assert (reloc
!= 0);
1561 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1562 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1564 reloc
->addend
= fixp
->fx_addnumber
;
1568 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1569 assert (reloc
->howto
!= 0);
1574 #endif /* BFD_ASSEMBLER */
1576 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1580 struct m68k_op thark
;
1586 memset (&thark
, '\0', sizeof (thark
));
1587 if (!m68k_ip_op (buf
, &thark
))
1590 printf ("op1 error %s in %s\n", thark
.error
, buf
);
1591 printf ("mode %d, reg %d, ", thark
.mode
, thark
.reg
);
1593 printf ("Constant: '%.*s',", 1 + thark
.e_const
- thark
.b_const
, thark
.b_const
);
1594 printf ("ireg %d, isiz %d, imul %d ", thark
.ireg
, thark
.isiz
, thark
.imul
);
1596 printf ("Iadd: '%.*s'", 1 + thark
.e_iadd
- thark
.b_iadd
, thark
.b_iadd
);
1599 exit (EXIT_SUCCESS
);
1605 /* Handle of the OPCODE hash table. NULL means any use before
1606 m68k_ip_begin() will crash. */
1607 static struct hash_control
*op_hash
;
1613 * This converts a string into a 68k instruction.
1614 * The string must be a bare single instruction in sun format
1615 * with RMS-style 68020 indirects
1618 * It provides some error messages: at most one fatal error message (which
1619 * stops the scan) and at most one warning message for each operand.
1620 * The 68k instruction is returned in exploded form, since we have no
1621 * knowledge of how you parse (or evaluate) your expressions.
1622 * We do however strip off and decode addressing modes and operation
1625 * This function's value is a string. If it is not "" then an internal
1626 * logic error was found: read this code to assign meaning to the string.
1627 * No argument string should generate such an error string:
1628 * it means a bug in our code, not in the user's text.
1630 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1634 /* JF this function no longer returns a useful value. Sorry */
1640 register struct m68k_op
*opP
;
1641 register struct m68k_incant
*opcode
;
1643 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1644 char *pdot
, *pdotmove
;
1649 char *crack_operand ();
1650 LITTLENUM_TYPE words
[6];
1651 LITTLENUM_TYPE
*wordp
;
1652 unsigned long ok_arch
= 0;
1654 if (*instring
== ' ')
1655 instring
++; /* skip leading whitespace */
1657 /* Scan up to end of operation-code, which MUST end in end-of-string
1658 or exactly 1 space. */
1660 for (p
= instring
; *p
!= '\0'; p
++)
1670 the_ins
.error
= "No operator";
1671 the_ins
.opcode
[0] = 0;
1672 /* the_ins.numo=1; */
1676 /* p now points to the end of the opcode name, probably whitespace.
1677 make sure the name is null terminated by clobbering the whitespace,
1678 look it up in the hash table, then fix it back.
1679 Remove a dot, first, since the opcode tables have none. */
1682 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1683 *pdotmove
= pdotmove
[1];
1689 opcode
= (struct m68k_incant
*) hash_find (op_hash
, instring
);
1694 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1695 *pdotmove
= pdotmove
[-1];
1702 the_ins
.error
= "Unknown operator";
1703 the_ins
.opcode
[0] = 0;
1704 /* the_ins.numo=1; */
1708 /* found a legitimate opcode, start matching operands */
1713 if (opcode
->m_operands
== 0)
1715 char *old
= input_line_pointer
;
1717 input_line_pointer
= p
;
1718 /* Ahh - it's a motorola style psuedo op */
1719 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1720 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1721 input_line_pointer
= old
;
1727 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1730 p
= crack_operand (p
, opP
);
1734 the_ins
.error
= opP
->error
;
1739 opsfound
= opP
- &the_ins
.operands
[0];
1741 /* This ugly hack is to support the floating pt opcodes in their standard form */
1742 /* Essentially, we fake a first enty of type COP#1 */
1743 if (opcode
->m_operands
[0] == 'I')
1747 for (n
= opsfound
; n
> 0; --n
)
1748 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1750 memset ((char *) (&the_ins
.operands
[0]), '\0', sizeof (the_ins
.operands
[0]));
1751 the_ins
.operands
[0].mode
= MSCR
;
1752 the_ins
.operands
[0].reg
= COPNUM
; /* COP #1 */
1756 /* We've got the operands. Find an opcode that'll accept them */
1759 /* If we didn't get the right number of ops, or we have no
1760 common model with this pattern then reject this pattern. */
1762 if (opsfound
!= opcode
->m_opnum
1763 || ((opcode
->m_arch
& current_architecture
) == 0))
1766 ok_arch
|= opcode
->m_arch
;
1770 for (s
= opcode
->m_operands
, opP
= &the_ins
.operands
[0]; *s
&& !losing
; s
+= 2, opP
++)
1772 /* Warning: this switch is huge! */
1773 /* I've tried to organize the cases into this order:
1774 non-alpha first, then alpha by letter. Lower-case
1775 goes directly before uppercase counterpart. */
1776 /* Code with multiple case ...: gets sorted by the lowest
1777 case ... it belongs to. I hope this makes sense. */
1781 if (opP
->mode
== MSCR
|| opP
->mode
== IMMED
1782 || opP
->mode
== DREG
|| opP
->mode
== AREG
1783 || opP
->mode
== AINC
|| opP
->mode
== ADEC
1784 || opP
->mode
== REGLST
)
1806 if (opP
->mode
!= IMMED
)
1812 t
= get_num (opP
->con1
, 80);
1813 if (s
[1] == 'b' && !isbyte (t
))
1815 else if (s
[1] == 'w' && !isword (t
))
1822 if (opP
->mode
!= IMMED
)
1827 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1828 opP
->mode
== IMMED
|| opP
->reg
== PC
|| opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1833 if (opP
->mode
== MSCR
|| opP
->reg
== PC
||
1834 opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1840 if (opP
->mode
== MSCR
|| opP
->mode
== DREG
||
1841 opP
->mode
== AREG
|| opP
->mode
== IMMED
|| opP
->reg
== PC
|| opP
->reg
== ZPC
||
1842 opP
->mode
== AINC
|| opP
->mode
== ADEC
|| opP
->mode
== REGLST
)
1847 if (opP
->mode
== MSCR
|| opP
->mode
== REGLST
)
1852 if (opP
->mode
!= AINC
)
1857 if (opP
->mode
!= ADEC
)
1862 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1863 opP
->mode
== AINC
|| opP
->mode
== ADEC
|| opP
->mode
== IMMED
|| opP
->mode
== REGLST
)
1868 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
|| opP
->mode
== REGLST
)
1873 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1874 opP
->mode
== AINC
|| opP
->mode
== ADEC
|| opP
->mode
== IMMED
|| opP
->reg
== PC
||
1875 opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1880 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1881 opP
->mode
== IMMED
|| opP
->mode
== REGLST
)
1885 case '~': /* For now! (JF FOO is this right?) */
1886 if (opP
->mode
== MSCR
|| opP
->mode
== DREG
||
1887 opP
->mode
== AREG
|| opP
->mode
== IMMED
|| opP
->reg
== PC
|| opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1892 if (opP
->mode
!= MSCR
|| (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1897 if (opP
->mode
!= AREG
)
1901 if (opP
->mode
!= AINDR
)
1904 } /* if not address register indirect */
1907 if (opP
->mode
!= ABSL
|| (flag_long_jumps
&& instring
[0] == 'j'
1908 && instring
[1] == 'b'
1909 && instring
[2] == 's'
1910 && instring
[3] == 'r'))
1915 if (opP
->mode
!= MSCR
|| opP
->reg
!= CCR
)
1919 case 'd': /* FOO This mode is a KLUDGE!! */
1920 if (opP
->mode
!= AOFF
&& (opP
->mode
!= ABSL
||
1921 opP
->con1
->e_beg
[0] != '(' || opP
->con1
->e_end
[0] != ')'))
1926 if (opP
->mode
!= DREG
)
1931 if (opP
->mode
!= MSCR
|| opP
->reg
< (FPREG
+ 0) || opP
->reg
> (FPREG
+ 7))
1936 if (opP
->mode
!= MSCR
|| opP
->reg
< COPNUM
||
1937 opP
->reg
>= COPNUM
+ 7)
1942 if (opP
->mode
!= MSCR
1944 || opP
->reg
> last_movec_reg
)
1948 const enum _register
*rp
;
1949 for (rp
= control_regs
; *rp
; rp
++)
1950 if (*rp
== opP
->reg
)
1958 if (opP
->mode
!= IMMED
)
1964 if (opP
->mode
== DREG
|| opP
->mode
== AREG
|| opP
->mode
== FPREG
)
1971 opP
->reg
= 1 << (opP
->reg
- DATA
);
1974 else if (opP
->mode
!= REGLST
)
1978 else if (s
[1] == '8' && opP
->reg
& 0x0FFffFF)
1980 else if (s
[1] == '3' && opP
->reg
& 0x7000000)
1985 if (opP
->mode
!= IMMED
)
1991 t
= get_num (opP
->con1
, 0);
1993 || isvar (opP
->con1
))
1999 if (opP
->mode
!= DREG
&& opP
->mode
!= IMMED
)
2004 if (opP
->mode
!= IMMED
)
2010 t
= get_num (opP
->con1
, 80);
2011 if (t
< 1 || t
> 8 || isvar (opP
->con1
))
2017 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
2022 if (opP
->mode
!= AINDR
&& opP
->mode
!= DINDR
)
2027 if (opP
->mode
!= MSCR
|| !(opP
->reg
== FPI
|| opP
->reg
== FPS
|| opP
->reg
== FPC
))
2032 if (opP
->mode
!= MSCR
|| opP
->reg
!= SR
)
2037 if (opP
->mode
!= IMMED
)
2041 long t
= get_num (opP
->con1
, 80);
2042 if (t
< 0 || t
> 7 || isvar (opP
->con1
))
2048 if (opP
->mode
!= MSCR
|| opP
->reg
!= USP
)
2052 /* JF these are out of order. We could put them
2053 in order if we were willing to put up with
2054 bunches of #ifdef m68851s in the code.
2056 Don't forget that you need these operands
2057 to use 68030 MMU instructions. */
2059 /* Memory addressing mode used by pflushr */
2061 if (opP
->mode
== MSCR
|| opP
->mode
== DREG
||
2062 opP
->mode
== AREG
|| opP
->mode
== REGLST
)
2067 if (opP
->mode
!= MSCR
|| (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
2072 if (opP
->mode
!= MSCR
2073 || (opP
->reg
!= TC
&& opP
->reg
!= CAL
2074 && opP
->reg
!= VAL
&& opP
->reg
!= SCC
&& opP
->reg
!= AC
))
2079 if (opP
->reg
!= VAL
)
2084 if (opP
->mode
!= MSCR
2085 || (opP
->reg
!= DRP
&& opP
->reg
!= SRP
2086 && opP
->reg
!= CRP
))
2091 if (opP
->mode
!= MSCR
||
2092 (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7) &&
2093 !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
2098 if (opP
->reg
!= PSR
)
2103 if (opP
->reg
!= PCSR
)
2114 } /* not a cache specifier. */
2118 if (opP
->mode
!= ABSL
)
2121 } /* not absolute */
2125 as_fatal ("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
2126 *s
, __LINE__
, __FILE__
);
2127 } /* switch on type of operand */
2131 } /* for each operand */
2132 } /* if immediately wrong */
2139 opcode
= opcode
->m_next
;
2144 && !(ok_arch
& current_architecture
))
2148 strcpy (buf
, "invalid instruction for this architecture; needs ");
2149 cp
= buf
+ strlen (buf
);
2153 strcpy (cp
, "fpu (68040, 68060 or 68881/68882)");
2156 strcpy (cp
, "mmu (68030 or 68851)");
2159 strcpy (cp
, "68020 or higher");
2162 strcpy (cp
, "68000 or higher");
2165 strcpy (cp
, "68010 or higher");
2169 int got_one
= 0, idx
;
2170 for (idx
= 0; idx
< sizeof (archs
) / sizeof (archs
[0]); idx
++)
2172 if (archs
[idx
].arch
& ok_arch
)
2176 strcpy (cp
, " or ");
2180 strcpy (cp
, archs
[idx
].name
);
2192 the_ins
.error
= "operands mismatch";
2194 } /* Fell off the end */
2199 /* now assemble it */
2201 the_ins
.args
= opcode
->m_operands
;
2202 the_ins
.numargs
= opcode
->m_opnum
;
2203 the_ins
.numo
= opcode
->m_codenum
;
2204 the_ins
.opcode
[0] = getone (opcode
);
2205 the_ins
.opcode
[1] = gettwo (opcode
);
2207 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2209 /* This switch is a doozy.
2210 Watch the first step; its a big one! */
2231 tmpreg
= 0x3c; /* 7.4 */
2232 if (strchr ("bwl", s
[1]))
2233 nextword
= get_num (opP
->con1
, 80);
2235 nextword
= get_num (opP
->con1
, 0);
2236 if (isvar (opP
->con1
))
2237 add_fix (s
[1], opP
->con1
, 0, 0);
2241 if (!isbyte (nextword
))
2242 opP
->error
= "operand out of range";
2247 if (!isword (nextword
))
2248 opP
->error
= "operand out of range";
2253 addword (nextword
>> 16);
2275 as_fatal ("Internal error: Can't decode %c%c in line %d of file \"%s\"",
2276 *s
, s
[1], __LINE__
, __FILE__
);
2281 /* We gotta put out some float */
2282 if (op (opP
->con1
) != O_big
)
2287 /* Can other cases happen here? */
2288 if (op (opP
->con1
) != O_constant
)
2291 val
= (valueT
) offs (opP
->con1
);
2295 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2296 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2300 offs (opP
->con1
) = gencnt
;
2302 if (offs (opP
->con1
) > 0)
2304 if (offs (opP
->con1
) > baseo
)
2306 as_warn ("Bignum too big for %c format; truncated", s
[1]);
2307 offs (opP
->con1
) = baseo
;
2309 baseo
-= offs (opP
->con1
);
2312 for (wordp
= generic_bignum
+ offs (opP
->con1
) - 1; offs (opP
->con1
)--; --wordp
)
2316 gen_to_words (words
, baseo
, (long) outro
);
2317 for (wordp
= words
; baseo
--; wordp
++)
2321 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2324 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2327 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2330 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2333 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2337 nextword
= get_num (opP
->con1
, 80);
2338 /* Force into index mode. Hope this works */
2340 /* We do the first bit for 32-bit displacements, and the
2341 second bit for 16 bit ones. It is possible that we
2342 should make the default be WORD instead of LONG, but
2343 I think that'd break GCC, so we put up with a little
2344 inefficiency for the sake of working output. */
2346 if (!issword (nextword
)
2347 || (isvar (opP
->con1
)
2348 && ((opP
->con1
->e_siz
== 0
2349 && flag_short_refs
== 0
2350 && cpu_of_arch (current_architecture
) >= m68020
)
2351 || opP
->con1
->e_siz
== 3)))
2355 tmpreg
= 0x3B; /* 7.3 */
2357 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2358 if (isvar (opP
->con1
))
2364 add_fix ('l', opP
->con1
, 1, 2);
2365 addword (0), addword (0);
2367 add_frag (adds (opP
->con1
),
2369 TAB (PCLEA
, SZ_UNDEF
));
2376 add_fix ('l', opP
->con1
, 0, 0);
2381 addword (nextword
>> 16);
2386 tmpreg
= 0x3A; /* 7.2 */
2388 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2390 if (isvar (opP
->con1
))
2394 add_fix ('w', opP
->con1
, 1, 0);
2397 add_fix ('w', opP
->con1
, 0, 0);
2406 know (current_architecture
& m68020up
);
2407 /* intentional fall-through */
2410 baseo
= get_num (opP
->con1
, 80);
2411 outro
= get_num (opP
->con2
, 80);
2412 /* Figure out the `addressing mode'.
2413 Also turn on the BASE_DISABLE bit, if needed. */
2414 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2416 tmpreg
= 0x3b;/* 7.3 */
2417 if (opP
->reg
== ZPC
)
2420 else if (opP
->reg
== FAIL
)
2423 tmpreg
= 0x30;/* 6.garbage */
2426 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2428 siz1
= (opP
->con1
) ? opP
->con1
->e_siz
: 0;
2429 siz2
= (opP
->con2
) ? opP
->con2
->e_siz
: 0;
2431 /* Index register stuff */
2432 if (opP
->ireg
>= DATA
+ 0 && opP
->ireg
<= ADDR
+ 7)
2434 nextword
|= (opP
->ireg
- DATA
) << 12;
2436 if (opP
->isiz
== 0 || opP
->isiz
== 3)
2452 as_fatal ("failed sanity check.");
2455 GET US OUT OF HERE! */
2457 /* Must be INDEX, with an index register. Address
2458 register cannot be ZERO-PC, and either :b was
2459 forced, or we know it will fit. For a 68000 or
2460 68010, force this mode anyways, because the
2461 larger modes aren't supported. */
2462 if (opP
->mode
== AINDX
2465 && (/* :b specified */
2467 /* known to fit in 8 bits */
2468 || (issbyte (baseo
) && !isvar (opP
->con1
))
2469 /* doesn't support wider modes */
2470 || cpu_of_arch (current_architecture
) < m68020
2471 /* simple enough to do relaxation */
2472 || subs (opP
->con1
) == NULL
2475 if (((!isvar (opP
->con1
)
2476 || subs (opP
->con1
) != NULL
)
2480 /* Can't handle more complex expressions
2481 here yet. Should only wind up here if
2482 the CPU doesn't support wider modes, so
2483 do a byte relocation and let the fixup
2484 processing later complain if it won't
2486 nextword
+= baseo
& 0xff;
2488 if (isvar (opP
->con1
))
2491 add_fix ('B', opP
->con1
, 1, 1);
2493 add_fix ('B', opP
->con1
, 0, 0);
2496 else if (opP
->reg
!= PC
|| siz1
!= 0)
2502 nextword
+= baseo
& 0xff;
2504 add_frag (adds (opP
->con1
), offs (opP
->con1
),
2505 TAB (PCINDEX
, SZ_UNDEF
));
2511 nextword
|= 0x40; /* No index reg */
2514 /* It isn't simple. */
2516 /* If the guy specified a width, we assume that it is
2517 wide enough. Maybe it isn't. If so, we lose. */
2521 if (isvar (opP
->con1
) || !issword (baseo
))
2526 else if (baseo
== 0)
2535 as_warn ("Byte dispacement won't work. Defaulting to :w");
2544 /* Figure out innner displacement stuff */
2545 if (opP
->mode
!= AINDX
)
2550 if (isvar (opP
->con2
) || !issword (outro
))
2555 else if (outro
== 0)
2564 as_warn ("Byte dispacement won't work. Defaulting to :w");
2572 if (opP
->mode
== APODX
)
2574 else if (opP
->mode
== AMIND
)
2579 if (isvar (opP
->con1
))
2581 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2583 add_fix (siz1
== 3 ? 'l' : 'w', opP
->con1
, 1, 2);
2586 add_fix (siz1
== 3 ? 'l' : 'w', opP
->con1
, 0, 0);
2589 addword (baseo
>> 16);
2593 if (isvar (opP
->con2
))
2594 add_fix (siz2
== 3 ? 'l' : 'w', opP
->con2
, 0, 0);
2596 addword (outro
>> 16);
2603 nextword
= get_num (opP
->con1
, 80);
2604 switch (opP
->con1
->e_siz
)
2607 as_warn ("Unknown size for absolute reference");
2609 if (!isvar (opP
->con1
) && issword (offs (opP
->con1
)))
2611 tmpreg
= 0x38; /* 7.0 */
2615 /* Don't generate pc relative code on 68010 and
2617 if (isvar (opP
->con1
)
2618 && !subs (opP
->con1
)
2619 && seg (opP
->con1
) == text_section
2620 && now_seg
== text_section
2621 && cpu_of_arch (current_architecture
) >= m68020
2623 && !strchr ("~%&$?", s
[0]))
2625 tmpreg
= 0x3A; /* 7.2 */
2626 add_frag (adds (opP
->con1
),
2628 TAB (PCREL
, SZ_UNDEF
));
2631 /* Fall through into long */
2633 if (isvar (opP
->con1
))
2634 add_fix ('l', opP
->con1
, 0, 0);
2636 tmpreg
= 0x39;/* 7.1 mode */
2637 addword (nextword
>> 16);
2642 if (isvar (opP
->con1
))
2643 add_fix ('w', opP
->con1
, 0, 0);
2645 tmpreg
= 0x38;/* 7.0 mode */
2651 as_bad ("invalid indirect register");
2655 as_bad ("unknown/incorrect operand");
2658 install_gen_operand (s
[1], tmpreg
);
2664 { /* JF: I hate floating point! */
2679 tmpreg
= get_num (opP
->con1
, tmpreg
);
2680 if (isvar (opP
->con1
))
2681 add_fix (s
[1], opP
->con1
, 0, 0);
2684 case 'b': /* Danger: These do no check for
2685 certain types of overflow.
2687 if (!isbyte (tmpreg
))
2688 opP
->error
= "out of range";
2689 insop (tmpreg
, opcode
);
2690 if (isvar (opP
->con1
))
2691 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2694 if (!isword (tmpreg
))
2695 opP
->error
= "out of range";
2696 insop (tmpreg
, opcode
);
2697 if (isvar (opP
->con1
))
2698 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2701 /* Because of the way insop works, we put these two out
2703 insop (tmpreg
, opcode
);
2704 insop (tmpreg
>> 16, opcode
);
2705 if (isvar (opP
->con1
))
2706 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2712 install_operand (s
[1], tmpreg
);
2715 as_fatal ("Internal error: Unknown mode #%c in line %d of file \"%s\"", s
[1], __LINE__
, __FILE__
);
2723 install_operand (s
[1], opP
->reg
- ADDR
);
2727 tmpreg
= get_num (opP
->con1
, 80);
2731 add_fix ('B', opP
->con1
, 1, -1);
2734 add_fix ('w', opP
->con1
, 1, 0);
2739 if (cpu_of_arch (current_architecture
) < m68020
) /* 68000 or 010 */
2740 as_warn ("Can't use long branches on 68000/68010");
2741 the_ins
.opcode
[the_ins
.numo
- 1] |= 0xff;
2742 add_fix ('l', opP
->con1
, 1, 0);
2747 if (subs (opP
->con1
)) /* We can't relax it */
2750 /* This could either be a symbol, or an
2751 absolute address. No matter, the
2752 frag hacking will finger it out.
2753 Not quite: it can't switch from
2754 BRANCH to BCC68000 for the case
2755 where opnd is absolute (it needs
2756 to use the 68000 hack since no
2757 conditional abs jumps). */
2758 if (((cpu_of_arch (current_architecture
) < m68020
)
2759 || (0 == adds (opP
->con1
)))
2760 && (the_ins
.opcode
[0] >= 0x6200)
2761 && (the_ins
.opcode
[0] <= 0x6f00))
2763 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (BCC68000
, SZ_UNDEF
));
2767 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (ABRANCH
, SZ_UNDEF
));
2771 if (isvar (opP
->con1
))
2774 /* check for DBcc instruction */
2775 if ((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2777 /* size varies if patch */
2778 /* needed for long form */
2779 add_frag (adds (opP
->con1
), offs (opP
->con1
),
2780 TAB (DBCC
, SZ_UNDEF
));
2784 add_fix ('w', opP
->con1
, 1, 0);
2788 case 'C': /* Fixed size LONG coproc branches */
2789 add_fix ('l', opP
->con1
, 1, 0);
2793 case 'c': /* Var size Coprocesssor branches */
2794 if (subs (opP
->con1
))
2796 add_fix ('l', opP
->con1
, 1, 0);
2797 add_frag ((symbolS
*) 0, (long) 0, TAB (FBRANCH
, LONG
));
2799 else if (adds (opP
->con1
))
2801 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (FBRANCH
, SZ_UNDEF
));
2805 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2806 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2807 add_fix ('l', opP
->con1
, 1, 0);
2813 as_fatal ("Internal error: operand type B%c unknown in line %d of file \"%s\"",
2814 s
[1], __LINE__
, __FILE__
);
2818 case 'C': /* Ignore it */
2821 case 'd': /* JF this is a kludge */
2822 if (opP
->mode
== AOFF
)
2824 install_operand ('s', opP
->reg
- ADDR
);
2830 tmpP
= opP
->con1
->e_end
- 2;
2832 opP
->con1
->e_end
-= 4; /* point to the , */
2833 baseo
= m68k_reg_parse (&tmpP
);
2834 if (baseo
< ADDR
+ 0 || baseo
> ADDR
+ 7)
2836 as_bad ("Unknown address reg, using A0");
2841 install_operand ('s', baseo
);
2843 tmpreg
= get_num (opP
->con1
, 80);
2844 if (!issword (tmpreg
))
2846 as_warn ("Expression out of range, using 0");
2853 install_operand (s
[1], opP
->reg
- DATA
);
2857 install_operand (s
[1], opP
->reg
- FPREG
);
2861 tmpreg
= 1 + opP
->reg
- COPNUM
;
2864 install_operand (s
[1], tmpreg
);
2867 case 'J': /* JF foo */
2926 as_fatal ("failed sanity check.");
2928 install_operand (s
[1], tmpreg
);
2932 tmpreg
= get_num (opP
->con1
, 55);
2933 install_operand (s
[1], tmpreg
& 0x7f);
2940 if (tmpreg
& 0x7FF0000)
2941 as_bad ("Floating point register in register list");
2942 insop (reverse_16_bits (tmpreg
), opcode
);
2946 if (tmpreg
& 0x700FFFF)
2947 as_bad ("Wrong register in floating-point reglist");
2948 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
2956 if (tmpreg
& 0x7FF0000)
2957 as_bad ("Floating point register in register list");
2958 insop (tmpreg
, opcode
);
2960 else if (s
[1] == '8')
2962 if (tmpreg
& 0x0FFFFFF)
2963 as_bad ("incorrect register in reglist");
2964 install_operand (s
[1], tmpreg
>> 24);
2968 if (tmpreg
& 0x700FFFF)
2969 as_bad ("wrong register in floating-point reglist");
2971 install_operand (s
[1], tmpreg
>> 16);
2976 install_operand (s
[1], get_num (opP
->con1
, 60));
2980 tmpreg
= (opP
->mode
== DREG
)
2981 ? 0x20 + opP
->reg
- DATA
2982 : (get_num (opP
->con1
, 40) & 0x1F);
2983 install_operand (s
[1], tmpreg
);
2987 tmpreg
= get_num (opP
->con1
, 10);
2990 install_operand (s
[1], tmpreg
);
2995 /* This depends on the fact that ADDR registers are
2996 eight more than their corresponding DATA regs, so
2997 the result will have the ADDR_REG bit set */
2998 install_operand (s
[1], opP
->reg
- DATA
);
3002 if (opP
->reg
== FPI
)
3004 else if (opP
->reg
== FPS
)
3006 else if (opP
->reg
== FPC
)
3009 as_fatal ("failed sanity check.");
3010 install_operand (s
[1], tmpreg
);
3013 case 'S': /* Ignore it */
3017 install_operand (s
[1], get_num (opP
->con1
, 30));
3020 case 'U': /* Ignore it */
3039 as_fatal ("failed sanity check");
3040 } /* switch on cache token */
3041 install_operand (s
[1], tmpreg
);
3044 /* JF: These are out of order, I fear. */
3055 as_fatal ("failed sanity check.");
3057 install_operand (s
[1], tmpreg
);
3079 as_fatal ("failed sanity check.");
3081 install_operand (s
[1], tmpreg
);
3085 if (opP
->reg
== VAL
)
3087 as_fatal ("failed sanity check.");
3103 as_fatal ("failed sanity check.");
3105 install_operand (s
[1], tmpreg
);
3119 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3130 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3134 as_fatal ("failed sanity check.");
3136 install_operand (s
[1], tmpreg
);
3139 know (opP
->reg
== PSR
);
3142 know (opP
->reg
== PCSR
);
3155 as_fatal ("failed sanity check");
3157 install_operand (s
[1], tmpreg
);
3160 tmpreg
= get_num (opP
->con1
, 20);
3161 install_operand (s
[1], tmpreg
);
3163 case '_': /* used only for move16 absolute 32-bit address */
3164 tmpreg
= get_num (opP
->con1
, 80);
3165 addword (tmpreg
>> 16);
3166 addword (tmpreg
& 0xFFFF);
3169 as_fatal ("Internal error: Operand type %c unknown in line %d of file \"%s\"",
3170 s
[0], __LINE__
, __FILE__
);
3174 /* By the time whe get here (FINALLY) the_ins contains the complete
3175 instruction, ready to be emitted. . . */
3179 * get_regs := '/' + ?
3180 * | '-' + <register>
3181 * | '-' + <register> + ?
3186 * The idea here must be to scan in a set of registers but I don't
3187 * understand it. Looks awfully sloppy to me but I don't have any doc on
3195 get_regs (i
, str
, opP
)
3197 struct m68k_op
*opP
;
3200 /* 26, 25, 24, 23-16, 15-8, 0-7 */
3201 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
3202 unsigned long cur_regs
= 0;
3205 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
3206 else if(x==FPS) cur_regs|=(1<<25);\
3207 else if(x==FPC) cur_regs|=(1<<26);\
3208 else cur_regs|=(1<<(x-1)); }
3218 else if (*str
== '-')
3221 reg2
= m68k_reg_parse (&str
);
3222 if (reg2
< DATA
|| reg2
>= FPREG
+ 8 || reg1
== FPI
|| reg1
== FPS
|| reg1
== FPC
)
3224 opP
->error
= "unknown register in register list";
3227 while (reg1
<= reg2
)
3235 else if (*str
== '\0')
3242 opP
->error
= "unknow character in register list";
3245 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
3248 reg1
= m68k_reg_parse (&str
);
3249 if ((reg1
< DATA
|| reg1
>= FPREG
+ 8) && !(reg1
== FPI
|| reg1
== FPS
|| reg1
== FPC
))
3251 opP
->error
= "unknown register in register list";
3255 opP
->reg
= cur_regs
;
3260 reverse_16_bits (in
)
3266 static int mask
[16] =
3268 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3269 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3271 for (n
= 0; n
< 16; n
++)
3274 out
|= mask
[15 - n
];
3277 } /* reverse_16_bits() */
3286 static int mask
[8] =
3288 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3291 for (n
= 0; n
< 8; n
++)
3297 } /* reverse_8_bits() */
3299 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3300 (that value is chosen in the frag_var call in md_assemble). TYPE
3301 is the subtype of the frag to be generated; its primary type is
3302 rs_machine_dependent.
3304 The TYPE parameter is also used by md_convert_frag_1 and
3305 md_estimate_size_before_relax. The appropriate type of fixup will
3306 be emitted by md_convert_frag_1.
3308 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3310 install_operand (mode
, val
)
3317 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge */
3320 the_ins
.opcode
[0] |= val
<< 9;
3323 the_ins
.opcode
[1] |= val
<< 12;
3326 the_ins
.opcode
[1] |= val
<< 6;
3329 the_ins
.opcode
[1] |= val
;
3332 the_ins
.opcode
[2] |= val
<< 12;
3335 the_ins
.opcode
[2] |= val
<< 6;
3338 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3339 three words long! */
3341 the_ins
.opcode
[2] |= val
;
3344 the_ins
.opcode
[1] |= val
<< 7;
3347 the_ins
.opcode
[1] |= val
<< 10;
3351 the_ins
.opcode
[1] |= val
<< 5;
3356 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3359 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3362 the_ins
.opcode
[0] |= val
= 0xff;
3365 the_ins
.opcode
[0] |= val
<< 9;
3368 the_ins
.opcode
[1] |= val
;
3371 the_ins
.opcode
[1] |= val
;
3372 the_ins
.numo
++; /* What a hack */
3375 the_ins
.opcode
[1] |= val
<< 4;
3382 the_ins
.opcode
[0] |= (val
<< 6);
3385 the_ins
.opcode
[1] = (val
>> 16);
3386 the_ins
.opcode
[2] = val
& 0xffff;
3390 as_fatal ("failed sanity check.");
3392 } /* install_operand() */
3395 install_gen_operand (mode
, val
)
3402 the_ins
.opcode
[0] |= val
;
3405 /* This is a kludge!!! */
3406 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3415 the_ins
.opcode
[0] |= val
;
3417 /* more stuff goes here */
3419 as_fatal ("failed sanity check.");
3421 } /* install_gen_operand() */
3424 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3425 * then deal with the bitfield hack.
3429 crack_operand (str
, opP
)
3431 register struct m68k_op
*opP
;
3433 register int parens
;
3435 register char *beg_str
;
3442 for (parens
= 0; *str
&& (parens
> 0 || notend (str
)); str
++)
3446 else if (*str
== ')')
3450 opP
->error
= "Extra )";
3456 if (!*str
&& parens
)
3458 opP
->error
= "Missing )";
3463 if (m68k_ip_op (beg_str
, opP
) == FAIL
)
3470 c
= *++str
; /* JF bitfield hack */
3475 as_bad ("Missing operand");
3480 /* This is the guts of the machine-dependent assembler. STR points to a
3481 machine dependent instruction. This function is supposed to emit
3482 the frags/bytes it assembles to.
3486 insert_reg (regname
, regnum
)
3493 #ifdef REGISTER_PREFIX
3494 if (!flag_reg_prefix_optional
)
3496 buf
[0] = REGISTER_PREFIX
;
3497 strcpy (buf
+ 1, regname
);
3502 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
3503 &zero_address_frag
));
3505 for (i
= 0; regname
[i
]; i
++)
3506 buf
[i
] = islower (regname
[i
]) ? toupper (regname
[i
]) : regname
[i
];
3509 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
3510 &zero_address_frag
));
3519 static const struct init_entry init_table
[] =
3623 /* 68ec030 versions of same */
3626 /* 68ec030 access control unit, identical to 030 MMU status reg */
3636 for (i
= 0; init_table
[i
].name
; i
++)
3637 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
3640 static int no_68851
, no_68881
;
3643 /* a.out machine type. Default to 68020. */
3644 int m68k_aout_machtype
= 2;
3656 int shorts_this_frag
;
3659 memset ((char *) (&the_ins
), '\0', sizeof (the_ins
));
3664 for (n
= the_ins
.numargs
; n
; --n
)
3665 if (the_ins
.operands
[n
].error
)
3667 er
= the_ins
.operands
[n
].error
;
3673 as_bad ("%s -- statement `%s' ignored", er
, str
);
3677 if (the_ins
.nfrag
== 0)
3679 /* No frag hacking involved; just put it out */
3680 toP
= frag_more (2 * the_ins
.numo
);
3681 fromP
= &the_ins
.opcode
[0];
3682 for (m
= the_ins
.numo
; m
; --m
)
3684 md_number_to_chars (toP
, (long) (*fromP
), 2);
3688 /* put out symbol-dependent info */
3689 for (m
= 0; m
< the_ins
.nrel
; m
++)
3691 switch (the_ins
.reloc
[m
].wid
)
3709 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3710 the_ins
.reloc
[m
].wid
);
3713 fixP
= fix_new_exp (frag_now
,
3714 ((toP
- frag_now
->fr_literal
)
3715 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3717 &the_ins
.reloc
[m
].exp
,
3718 the_ins
.reloc
[m
].pcrel
,
3720 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3725 /* There's some frag hacking */
3726 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
3731 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
3733 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3734 toP
= frag_more (wid
);
3736 shorts_this_frag
= 0;
3737 for (m
= wid
/ 2; m
; --m
)
3739 md_number_to_chars (toP
, (long) (*fromP
), 2);
3744 for (m
= 0; m
< the_ins
.nrel
; m
++)
3746 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
3748 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
3751 wid
= the_ins
.reloc
[m
].wid
;
3754 the_ins
.reloc
[m
].wid
= 0;
3755 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3757 fixP
= fix_new_exp (frag_now
,
3758 ((toP
- frag_now
->fr_literal
)
3759 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3761 &the_ins
.reloc
[m
].exp
,
3762 the_ins
.reloc
[m
].pcrel
,
3764 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3766 (void) frag_var (rs_machine_dependent
, 10, 0,
3767 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
3768 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
3770 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3771 shorts_this_frag
= 0;
3774 toP
= frag_more (n
* sizeof (short));
3777 md_number_to_chars (toP
, (long) (*fromP
), 2);
3783 for (m
= 0; m
< the_ins
.nrel
; m
++)
3787 wid
= the_ins
.reloc
[m
].wid
;
3790 the_ins
.reloc
[m
].wid
= 0;
3791 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3793 fixP
= fix_new_exp (frag_now
,
3794 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
3795 - shorts_this_frag
* 2),
3797 &the_ins
.reloc
[m
].exp
,
3798 the_ins
.reloc
[m
].pcrel
,
3800 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3804 /* See BREAK_UP_BIG_DECL definition, above. */
3805 #ifdef DO_BREAK_UP_BIG_DECL
3806 static const struct m68k_opcode
*
3810 int lim1
= sizeof (m68k_opcodes
) / sizeof (m68k_opcodes
[0]);
3812 return m68k_opcodes_2
+ (i
- lim1
);
3813 return m68k_opcodes
+ i
;
3816 #define opcode_ptr(i) (m68k_opcodes + i)
3823 * md_begin -- set up hash tables with 68000 instructions.
3824 * similar to what the vax assembler does. ---phr
3826 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3827 a copy of it at runtime, adding in the information we want but isn't
3828 there. I think it'd be better to have an awk script hack the table
3829 at compile time. Or even just xstr the table and use it as-is. But
3830 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3833 register const struct m68k_opcode
*ins
;
3834 register struct m68k_incant
*hack
, *slak
;
3835 register const char *retval
= 0; /* empty string, or error msg text */
3836 register unsigned int i
;
3839 op_hash
= hash_new ();
3841 obstack_begin (&robyn
, 4000);
3842 for (i
= 0; i
< numopcodes
; i
++)
3844 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3847 ins
= opcode_ptr (i
);
3848 /* We *could* ignore insns that don't match our arch here
3849 but just leaving them out of the hash. */
3850 slak
->m_operands
= ins
->args
;
3851 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
3852 slak
->m_arch
= ins
->arch
;
3853 slak
->m_opcode
= ins
->opcode
;
3854 /* This is kludgey */
3855 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
3856 if (i
+ 1 != numopcodes
3857 && !strcmp (ins
->name
, opcode_ptr (i
+ 1)->name
))
3859 slak
->m_next
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3864 slak
= slak
->m_next
;
3868 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
3870 as_fatal ("Internal Error: Can't hash %s: %s", ins
->name
, retval
);
3873 for (i
= 0; i
< numaliases
; i
++)
3875 const char *name
= m68k_opcode_aliases
[i
].primary
;
3876 const char *alias
= m68k_opcode_aliases
[i
].alias
;
3877 PTR val
= hash_find (op_hash
, name
);
3879 as_fatal ("Internal Error: Can't find %s in hash table", name
);
3880 retval
= hash_insert (op_hash
, alias
, val
);
3882 as_fatal ("Internal Error: Can't hash %s: %s", alias
, retval
);
3885 for (i
= 0; i
< sizeof (mklower_table
); i
++)
3886 mklower_table
[i
] = (isupper (c
= (char) i
)) ? tolower (c
) : c
;
3888 for (i
= 0; i
< sizeof (notend_table
); i
++)
3890 notend_table
[i
] = 0;
3891 alt_notend_table
[i
] = 0;
3893 notend_table
[','] = 1;
3894 notend_table
['{'] = 1;
3895 notend_table
['}'] = 1;
3896 alt_notend_table
['a'] = 1;
3897 alt_notend_table
['A'] = 1;
3898 alt_notend_table
['d'] = 1;
3899 alt_notend_table
['D'] = 1;
3900 alt_notend_table
['#'] = 1;
3901 alt_notend_table
['&'] = 1;
3902 alt_notend_table
['f'] = 1;
3903 alt_notend_table
['F'] = 1;
3904 #ifdef REGISTER_PREFIX
3905 alt_notend_table
[REGISTER_PREFIX
] = 1;
3908 #ifndef MIT_SYNTAX_ONLY
3909 /* Insert pseudo ops, these have to go into the opcode table since
3910 gas expects pseudo ops to start with a dot */
3913 while (mote_pseudo_table
[n
].poc_name
)
3915 hack
= (struct m68k_incant
*)
3916 obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3917 hash_insert (op_hash
,
3918 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
3919 hack
->m_operands
= 0;
3930 m68k_init_after_args ()
3932 if (cpu_of_arch (current_architecture
) == 0)
3935 const char *default_cpu
= TARGET_CPU
;
3937 if (*default_cpu
== 'm')
3939 for (i
= 0; i
< n_archs
; i
++)
3940 if (!strcmp (default_cpu
, archs
[i
].name
))
3944 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU
);
3945 current_architecture
|= m68020
;
3948 current_architecture
|= archs
[i
].arch
;
3950 /* Permit m68881 specification with all cpus; those that can't work
3951 with a coprocessor could be doing emulation. */
3952 if (current_architecture
& m68851
)
3954 if (current_architecture
& m68040
)
3956 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3959 /* What other incompatibilities could we check for? */
3961 /* Toss in some default assumptions about coprocessors. */
3963 && (cpu_of_arch (current_architecture
)
3964 /* Can CPU32 have a 68881 coprocessor?? */
3965 & (m68020
| m68030
| cpu32
)))
3967 current_architecture
|= m68881
;
3970 && (cpu_of_arch (current_architecture
) & m68020up
) != 0
3971 && (cpu_of_arch (current_architecture
) & m68040up
) == 0)
3973 current_architecture
|= m68851
;
3975 if (no_68881
&& (current_architecture
& m68881
))
3976 as_bad ("options for 68881 and no-68881 both given");
3977 if (no_68851
&& (current_architecture
& m68851
))
3978 as_bad ("options for 68851 and no-68851 both given");
3981 /* Work out the magic number. This isn't very general. */
3982 if (current_architecture
& m68000
)
3983 m68k_aout_machtype
= 0;
3984 else if (current_architecture
& m68010
)
3985 m68k_aout_machtype
= 1;
3986 else if (current_architecture
& m68020
)
3987 m68k_aout_machtype
= 2;
3989 m68k_aout_machtype
= 2;
3992 /* Note which set of "movec" control registers is available. */
3993 switch (cpu_of_arch (current_architecture
))
3996 control_regs
= m68000_control_regs
;
3999 control_regs
= m68010_control_regs
;
4003 control_regs
= m68020_control_regs
;
4006 control_regs
= m68040_control_regs
;
4009 control_regs
= m68060_control_regs
;
4012 control_regs
= cpu32_control_regs
;
4018 if (cpu_of_arch (current_architecture
) < m68020
)
4019 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
4022 /* Equal to MAX_PRECISION in atof-ieee.c */
4023 #define MAX_LITTLENUMS 6
4025 /* Turn a string in input_line_pointer into a floating point constant of type
4026 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
4027 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
4030 md_atof (type
, litP
, sizeP
)
4036 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4037 LITTLENUM_TYPE
*wordP
;
4069 return "Bad call to MD_ATOF()";
4071 t
= atof_ieee (input_line_pointer
, type
, words
);
4073 input_line_pointer
= t
;
4075 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4076 for (wordP
= words
; prec
--;)
4078 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
4079 litP
+= sizeof (LITTLENUM_TYPE
);
4085 md_number_to_chars (buf
, val
, n
)
4090 number_to_chars_bigendian (buf
, val
, n
);
4094 md_apply_fix_2 (fixP
, val
)
4098 addressT upper_limit
;
4099 offsetT lower_limit
;
4101 /* This is unnecessary but it convinces the native rs6000 compiler
4102 to generate the code we want. */
4103 char *buf
= fixP
->fx_frag
->fr_literal
;
4104 buf
+= fixP
->fx_where
;
4105 /* end ibm compiler workaround */
4107 if (val
& 0x80000000)
4108 val
|= ~(addressT
)0x7fffffff;
4112 switch (fixP
->fx_size
)
4114 /* The cast to offsetT below are necessary to make code correct for
4115 machines where ints are smaller than offsetT */
4119 lower_limit
= - (offsetT
) 0x80;
4122 *buf
++ = (val
>> 8);
4124 upper_limit
= 0x7fff;
4125 lower_limit
= - (offsetT
) 0x8000;
4128 *buf
++ = (val
>> 24);
4129 *buf
++ = (val
>> 16);
4130 *buf
++ = (val
>> 8);
4132 upper_limit
= 0x7fffffff;
4133 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* avoid constant overflow */
4136 BAD_CASE (fixP
->fx_size
);
4139 /* For non-pc-relative values, it's conceivable we might get something
4140 like "0xff" for a byte field. So extend the upper part of the range
4141 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4142 so that we can do any range checking at all. */
4143 if (!fixP
->fx_pcrel
)
4144 upper_limit
= upper_limit
* 2 + 1;
4146 if ((addressT
) val
> upper_limit
4147 && (val
> 0 || val
< lower_limit
))
4148 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "value out of range");
4150 /* A one byte PC-relative reloc means a short branch. We can't use
4151 a short branch with a value of 0 or -1, because those indicate
4152 different opcodes (branches with longer offsets). */
4154 && fixP
->fx_size
== 1
4155 && (fixP
->fx_addsy
== NULL
4156 || S_IS_DEFINED (fixP
->fx_addsy
))
4157 && (val
== 0 || val
== -1))
4158 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "invalid byte branch offset");
4161 #ifdef BFD_ASSEMBLER
4163 md_apply_fix (fixP
, valp
)
4167 md_apply_fix_2 (fixP
, (addressT
) *valp
);
4171 void md_apply_fix (fixP
, val
)
4175 md_apply_fix_2 (fixP
, (addressT
) val
);
4179 /* *fragP has been relaxed to its final size, and now needs to have
4180 the bytes inside it modified to conform to the new size There is UGLY
4184 md_convert_frag_1 (fragP
)
4185 register fragS
*fragP
;
4191 /* Address in object code of the displacement. */
4192 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4194 /* Address in gas core of the place to store the displacement. */
4195 /* This convinces the native rs6000 compiler to generate the code we
4197 register char *buffer_address
= fragP
->fr_literal
;
4198 buffer_address
+= fragP
->fr_fix
;
4199 /* end ibm compiler workaround */
4201 /* The displacement of the address, from current location. */
4202 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4203 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4205 #ifdef BFD_ASSEMBLER
4206 disp
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
4209 switch (fragP
->fr_subtype
)
4211 case TAB (BCC68000
, BYTE
):
4212 case TAB (ABRANCH
, BYTE
):
4213 know (issbyte (disp
));
4215 as_bad ("short branch with zero offset: use :w");
4216 fragP
->fr_opcode
[1] = disp
;
4219 case TAB (DBCC
, SHORT
):
4220 know (issword (disp
));
4223 case TAB (BCC68000
, SHORT
):
4224 case TAB (ABRANCH
, SHORT
):
4225 know (issword (disp
));
4226 fragP
->fr_opcode
[1] = 0x00;
4229 case TAB (ABRANCH
, LONG
):
4230 if (cpu_of_arch (current_architecture
) < m68020
)
4232 if (fragP
->fr_opcode
[0] == 0x61)
4235 fragP
->fr_opcode
[0] = 0x4E;
4236 fragP
->fr_opcode
[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4237 subseg_change (text_section
, 0); /* @@ */
4251 else if (fragP
->fr_opcode
[0] == 0x60)
4253 fragP
->fr_opcode
[0] = 0x4E;
4254 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4255 subseg_change (text_section
, 0); /* @@ */
4256 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4257 fragP
->fr_offset
, 0, NO_RELOC
);
4263 as_bad ("Long branch offset not supported.");
4268 fragP
->fr_opcode
[1] = (char) 0xff;
4272 case TAB (BCC68000
, LONG
):
4273 /* only Bcc 68000 instructions can come here */
4274 /* change bcc into b!cc/jmp absl long */
4275 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
4276 fragP
->fr_opcode
[1] = 0x6;/* branch offset = 6 */
4278 /* JF: these used to be fr_opcode[2,3], but they may be in a
4279 different frag, in which case refering to them is a no-no.
4280 Only fr_opcode[0,1] are guaranteed to work. */
4281 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4282 *buffer_address
++ = (char) 0xf9;
4283 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4284 subseg_change (text_section
, 0);
4285 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4286 fragP
->fr_offset
, 0, NO_RELOC
);
4290 case TAB (DBCC
, LONG
):
4291 /* only DBcc 68000 instructions can come here */
4292 /* change dbcc into dbcc/jmp absl long */
4293 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4294 *buffer_address
++ = 0x00; /* branch offset = 4 */
4295 *buffer_address
++ = 0x04;
4296 *buffer_address
++ = 0x60; /* put in bra pc+6 */
4297 *buffer_address
++ = 0x06;
4298 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4299 *buffer_address
++ = (char) 0xf9;
4301 fragP
->fr_fix
+= 6; /* account for bra/jmp instructions */
4302 subseg_change (text_section
, 0);
4303 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4304 fragP
->fr_offset
, 0, NO_RELOC
);
4308 case TAB (FBRANCH
, SHORT
):
4309 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4312 case TAB (FBRANCH
, LONG
):
4313 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit */
4316 case TAB (PCREL
, SHORT
):
4319 case TAB (PCREL
, LONG
):
4320 /* The thing to do here is force it to ABSOLUTE LONG, since
4321 PCREL is really trying to shorten an ABSOLUTE address anyway */
4322 /* JF FOO This code has not been tested */
4323 subseg_change (text_section
, 0);
4324 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4326 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
4327 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4328 (unsigned) fragP
->fr_opcode
[0],
4329 (unsigned long) fragP
->fr_address
);
4330 fragP
->fr_opcode
[1] &= ~0x3F;
4331 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
4335 case TAB (PCLEA
, SHORT
):
4336 subseg_change (text_section
, 0);
4337 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4338 fragP
->fr_offset
, 1, NO_RELOC
);
4339 fragP
->fr_opcode
[1] &= ~0x3F;
4340 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
4343 case TAB (PCLEA
, LONG
):
4344 subseg_change (text_section
, 0);
4345 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
) + 2, 4, fragP
->fr_symbol
,
4346 fragP
->fr_offset
, 1, NO_RELOC
);
4347 fixP
->fx_pcrel_adjust
= 2;
4348 /* Already set to mode 7.3; this indicates: PC indirect with
4349 suppressed index, 32-bit displacement. */
4350 *buffer_address
++ = 0x01;
4351 *buffer_address
++ = 0x70;
4356 case TAB (PCINDEX
, BYTE
):
4358 if (!issbyte (disp
))
4360 as_bad ("displacement doesn't fit in one byte");
4363 assert (fragP
->fr_fix
>= 2);
4364 buffer_address
[-2] &= ~1;
4365 buffer_address
[-1] = disp
;
4368 case TAB (PCINDEX
, SHORT
):
4369 subseg_change (text_section
, 0);
4371 assert (issword (disp
));
4372 assert (fragP
->fr_fix
>= 2);
4373 buffer_address
[-2] |= 0x1;
4374 buffer_address
[-1] = 0x20;
4375 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4376 fragP
->fr_offset
, (fragP
->fr_opcode
[1] & 077) == 073,
4378 fixP
->fx_pcrel_adjust
= 2;
4381 case TAB (PCINDEX
, LONG
):
4382 subseg_change (text_section
, 0);
4384 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4385 fragP
->fr_offset
, (fragP
->fr_opcode
[1] & 077) == 073,
4387 fixP
->fx_pcrel_adjust
= 2;
4388 assert (fragP
->fr_fix
>= 2);
4389 buffer_address
[-2] |= 0x1;
4390 buffer_address
[-1] = 0x30;
4397 md_number_to_chars (buffer_address
, (long) disp
, (int) ext
);
4398 fragP
->fr_fix
+= ext
;
4402 #ifndef BFD_ASSEMBLER
4405 md_convert_frag (headers
, seg
, fragP
)
4406 object_headers
*headers
;
4410 md_convert_frag_1 (fragP
);
4416 md_convert_frag (abfd
, sec
, fragP
)
4421 md_convert_frag_1 (fragP
);
4425 /* Force truly undefined symbols to their maximum size, and generally set up
4426 the frag list to be relaxed
4429 md_estimate_size_before_relax (fragP
, segment
)
4430 register fragS
*fragP
;
4434 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
4436 old_fix
= fragP
->fr_fix
;
4438 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4439 switch (fragP
->fr_subtype
)
4442 case TAB (ABRANCH
, SZ_UNDEF
):
4444 if ((fragP
->fr_symbol
!= NULL
) /* Not absolute */
4445 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4447 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4450 else if ((fragP
->fr_symbol
== 0) || (cpu_of_arch (current_architecture
) < m68020
))
4452 /* On 68000, or for absolute value, switch to abs long */
4453 /* FIXME, we should check abs val, pick short or long */
4454 if (fragP
->fr_opcode
[0] == 0x61)
4456 fragP
->fr_opcode
[0] = 0x4E;
4457 fragP
->fr_opcode
[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4458 subseg_change (text_section
, 0);
4459 fix_new (fragP
, fragP
->fr_fix
, 4,
4460 fragP
->fr_symbol
, fragP
->fr_offset
, 0, NO_RELOC
);
4464 else if (fragP
->fr_opcode
[0] == 0x60)
4466 fragP
->fr_opcode
[0] = 0x4E;
4467 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4468 subseg_change (text_section
, 0);
4469 fix_new (fragP
, fragP
->fr_fix
, 4,
4470 fragP
->fr_symbol
, fragP
->fr_offset
, 0, NO_RELOC
);
4476 as_warn ("Long branch offset to extern symbol not supported.");
4480 { /* Symbol is still undefined. Make it simple */
4481 fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4482 fragP
->fr_offset
, 1, NO_RELOC
);
4484 fragP
->fr_opcode
[1] = (char) 0xff;
4490 } /* case TAB(ABRANCH,SZ_UNDEF) */
4492 case TAB (FBRANCH
, SZ_UNDEF
):
4494 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
|| flag_short_refs
)
4496 fragP
->fr_subtype
= TAB (FBRANCH
, SHORT
);
4501 fix_new (fragP
, (int) fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4502 fragP
->fr_offset
, 1, NO_RELOC
);
4504 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit */
4508 } /* TAB(FBRANCH,SZ_UNDEF) */
4510 case TAB (PCREL
, SZ_UNDEF
):
4512 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4514 || cpu_of_arch (current_architecture
) < m68020
)
4516 fragP
->fr_subtype
= TAB (PCREL
, SHORT
);
4521 fragP
->fr_subtype
= TAB (PCREL
, LONG
);
4525 } /* TAB(PCREL,SZ_UNDEF) */
4527 case TAB (BCC68000
, SZ_UNDEF
):
4529 if ((fragP
->fr_symbol
!= NULL
)
4530 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4532 fragP
->fr_subtype
= TAB (BCC68000
, BYTE
);
4535 /* only Bcc 68000 instructions can come here */
4536 /* change bcc into b!cc/jmp absl long */
4537 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
4538 if (flag_short_refs
)
4540 fragP
->fr_opcode
[1] = 0x04; /* branch offset = 6 */
4541 /* JF: these were fr_opcode[2,3] */
4542 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
4543 buffer_address
[1] = (char) 0xf8;
4544 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4545 subseg_change (text_section
, 0);
4546 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4547 fragP
->fr_offset
, 0, NO_RELOC
);
4552 fragP
->fr_opcode
[1] = 0x06; /* branch offset = 6 */
4553 /* JF: these were fr_opcode[2,3] */
4554 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
4555 buffer_address
[1] = (char) 0xf9;
4556 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4557 subseg_change (text_section
, 0);
4558 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4559 fragP
->fr_offset
, 0, NO_RELOC
);
4564 } /* case TAB(BCC68000,SZ_UNDEF) */
4566 case TAB (DBCC
, SZ_UNDEF
):
4568 if (fragP
->fr_symbol
!= NULL
&& S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4570 fragP
->fr_subtype
= TAB (DBCC
, SHORT
);
4574 /* only DBcc 68000 instructions can come here */
4575 /* change dbcc into dbcc/jmp absl long */
4576 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4577 buffer_address
[0] = 0x00; /* branch offset = 4 */
4578 buffer_address
[1] = 0x04;
4579 buffer_address
[2] = 0x60; /* put in bra pc + ... */
4581 if (flag_short_refs
)
4583 /* JF: these were fr_opcode[5-7] */
4584 buffer_address
[3] = 0x04; /* plus 4 */
4585 buffer_address
[4] = 0x4e; /* Put in Jump Word */
4586 buffer_address
[5] = (char) 0xf8;
4587 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
4588 subseg_change (text_section
, 0);
4589 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4590 fragP
->fr_offset
, 0, NO_RELOC
);
4595 /* JF: these were fr_opcode[5-7] */
4596 buffer_address
[3] = 0x06; /* Plus 6 */
4597 buffer_address
[4] = 0x4e; /* put in jmp long (0x4ef9) */
4598 buffer_address
[5] = (char) 0xf9;
4599 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
4600 subseg_change (text_section
, 0);
4601 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4602 fragP
->fr_offset
, 0, NO_RELOC
);
4608 } /* case TAB(DBCC,SZ_UNDEF) */
4610 case TAB (PCLEA
, SZ_UNDEF
):
4612 if ((S_GET_SEGMENT (fragP
->fr_symbol
)) == segment
4614 || cpu_of_arch (current_architecture
) < m68020
)
4616 fragP
->fr_subtype
= TAB (PCLEA
, SHORT
);
4621 fragP
->fr_subtype
= TAB (PCLEA
, LONG
);
4625 } /* TAB(PCLEA,SZ_UNDEF) */
4627 case TAB (PCINDEX
, SZ_UNDEF
):
4628 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4629 || cpu_of_arch (current_architecture
) < m68020
)
4631 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
4635 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
4644 /* now that SZ_UNDEF are taken care of, check others */
4645 switch (fragP
->fr_subtype
)
4647 case TAB (BCC68000
, BYTE
):
4648 case TAB (ABRANCH
, BYTE
):
4649 /* We can't do a short jump to the next instruction,
4650 so we force word mode. */
4651 if (fragP
->fr_symbol
&& S_GET_VALUE (fragP
->fr_symbol
) == 0 &&
4652 fragP
->fr_symbol
->sy_frag
== fragP
->fr_next
)
4654 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4661 return fragP
->fr_var
+ fragP
->fr_fix
- old_fix
;
4664 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4665 /* the bit-field entries in the relocation_info struct plays hell
4666 with the byte-order problems of cross-assembly. So as a hack,
4667 I added this mach. dependent ri twiddler. Ugly, but it gets
4669 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4670 are symbolnum, most sig. byte first. Last byte is broken up with
4671 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4672 nibble as nuthin. (on Sun 3 at least) */
4673 /* Translate the internal relocation information into target-specific
4677 md_ri_to_chars (the_bytes
, ri
)
4679 struct reloc_info_generic
*ri
;
4682 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
4683 /* now the fun stuff */
4684 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
4685 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
4686 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
4687 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80) | ((ri
->r_length
<< 5) & 0x60) |
4688 ((ri
->r_extern
<< 4) & 0x10));
4691 #endif /* comment */
4693 #ifndef BFD_ASSEMBLER
4695 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4698 relax_addressT segment_address_in_file
;
4701 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4702 * Out: GNU LD relocation length code: 0, 1, or 2.
4705 static CONST
unsigned char nbytes_r_length
[] = {42, 0, 1, 42, 2};
4708 know (fixP
->fx_addsy
!= NULL
);
4710 md_number_to_chars (where
,
4711 fixP
->fx_frag
->fr_address
+ fixP
->fx_where
- segment_address_in_file
,
4714 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4715 ? S_GET_TYPE (fixP
->fx_addsy
)
4716 : fixP
->fx_addsy
->sy_number
);
4718 where
[4] = (r_symbolnum
>> 16) & 0x0ff;
4719 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4720 where
[6] = r_symbolnum
& 0x0ff;
4721 where
[7] = (((fixP
->fx_pcrel
<< 7) & 0x80) | ((nbytes_r_length
[fixP
->fx_size
] << 5) & 0x60) |
4722 (((!S_IS_DEFINED (fixP
->fx_addsy
)) << 4) & 0x10));
4726 #endif /* OBJ_AOUT or OBJ_BOUT */
4728 #ifndef WORKING_DOT_WORD
4729 CONST
int md_short_jump_size
= 4;
4730 CONST
int md_long_jump_size
= 6;
4733 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4735 addressT from_addr
, to_addr
;
4741 offset
= to_addr
- (from_addr
+ 2);
4743 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
4744 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
4748 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4750 addressT from_addr
, to_addr
;
4756 if (cpu_of_arch (current_architecture
) < m68020
)
4758 offset
= to_addr
- S_GET_VALUE (to_symbol
);
4759 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
4760 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4761 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
4766 offset
= to_addr
- (from_addr
+ 2);
4767 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
4768 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4773 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
4776 10: Absolute 1:8 only
4777 20: Absolute 0:7 only
4778 30: absolute 0:15 only
4779 40: Absolute 0:31 only
4780 50: absolute 0:127 only
4781 55: absolute -64:63 only
4782 60: absolute -128:127 only
4783 70: absolute 0:4095 only
4790 struct m68k_exp
*exp
;
4798 if (*exp
->e_beg
== '0')
4800 if (exp
->e_beg
[1] == 'x')
4801 sscanf (exp
->e_beg
+ 2, "%x", &l
);
4803 sscanf (exp
->e_beg
+ 1, "%O", &l
);
4806 return atol (exp
->e_beg
);
4814 /* Can't do anything */
4817 if (!exp
->e_beg
|| !exp
->e_end
)
4819 seg (exp
) = absolute_section
;
4822 offs (exp
) = (ok
== 10) ? 1 : 0;
4823 as_warn ("Null expression defaults to %ld", offs (exp
));
4828 if ( /* ok!=80 && */ (exp
->e_end
[-1] == ':' || exp
->e_end
[-1] == '.')
4829 && (exp
->e_end
- exp
->e_beg
) >= 2)
4831 switch (exp
->e_end
[0])
4851 if (exp
->e_end
[-1] == ':')
4852 as_bad ("Unknown size for expression \"%c\"", exp
->e_end
[0]);
4856 c_save
= exp
->e_end
[1];
4857 exp
->e_end
[1] = '\0';
4858 save_in
= input_line_pointer
;
4859 input_line_pointer
= exp
->e_beg
;
4860 section
= expression (&exp
->e_exp
);
4861 seg (exp
) = section
;
4862 if (exp
->e_exp
.X_op
== O_absent
)
4864 /* Do the same thing the VAX asm does */
4865 seg (exp
) = absolute_section
;
4866 op (exp
) = O_constant
;
4872 as_warn ("expression out of range: defaulting to 1");
4876 else if (exp
->e_exp
.X_op
== O_constant
)
4881 if (offs (exp
) < 1 || offs (exp
) > 8)
4883 as_warn ("expression out of range: defaulting to 1");
4888 if (offs (exp
) < 0 || offs (exp
) > 7)
4892 if (offs (exp
) < 0 || offs (exp
) > 15)
4896 if (offs (exp
) < 0 || offs (exp
) > 32)
4900 if (offs (exp
) < 0 || offs (exp
) > 127)
4904 if (offs (exp
) < -64 || offs (exp
) > 63)
4908 if (offs (exp
) < -128 || offs (exp
) > 127)
4912 if (offs (exp
) < 0 || offs (exp
) > 4095)
4915 as_warn ("expression out of range: defaulting to 0");
4923 else if (exp
->e_exp
.X_op
== O_big
)
4925 if (offs (exp
) <= 0 /* flonum */
4926 && (ok
== 80 /* no bignums */
4927 || (ok
> 10 /* small-int ranges including 0 ok */
4928 /* If we have a flonum zero, a zero integer should
4929 do as well (e.g., in moveq). */
4930 && generic_floating_point_number
.exponent
== 0
4931 && generic_floating_point_number
.low
[0] == 0)))
4933 /* HACK! Turn it into a long */
4934 LITTLENUM_TYPE words
[6];
4936 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
4937 seg (exp
) = absolute_section
;
4938 op (exp
) = O_constant
;
4941 offs (exp
) = words
[1] | (words
[0] << 16);
4945 seg (exp
) = absolute_section
;
4946 op (exp
) = O_constant
;
4949 offs (exp
) = (ok
== 10) ? 1 : 0;
4950 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp
->e_beg
, offs (exp
));
4955 if (ok
>= 10 && ok
<= 70)
4957 seg (exp
) = absolute_section
;
4958 op (exp
) = O_constant
;
4961 offs (exp
) = (ok
== 10) ? 1 : 0;
4962 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp
->e_beg
, offs (exp
));
4966 if (input_line_pointer
!= exp
->e_end
+ 1)
4967 as_bad ("Ignoring junk after expression");
4968 exp
->e_end
[1] = c_save
;
4969 input_line_pointer
= save_in
;
4975 if (!isbyte (offs (exp
)))
4976 as_warn ("expression doesn't fit in BYTE");
4979 if (!isword (offs (exp
)))
4980 as_warn ("expression doesn't fit in WORD");
4988 /* These are the back-ends for the various machine dependent pseudo-ops. */
4989 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4995 subseg_set (data_section
, 1);
4996 demand_empty_rest_of_line ();
5003 subseg_set (data_section
, 2);
5004 demand_empty_rest_of_line ();
5011 /* We don't support putting frags in the BSS segment, we fake it
5012 by marking in_bss, then looking at s_skip for clues. */
5014 subseg_set (bss_section
, 0);
5015 demand_empty_rest_of_line ();
5023 register long temp_fill
;
5025 temp
= 1; /* JF should be 2? */
5026 temp_fill
= get_absolute_expression ();
5027 if (!need_pass_2
) /* Never make frag if expect extra pass. */
5028 frag_align (temp
, (int) temp_fill
);
5029 demand_empty_rest_of_line ();
5036 demand_empty_rest_of_line ();
5039 /* s_space is defined in read.c .skip is simply an alias to it. */
5044 * Invocation line includes a switch not recognized by the base assembler.
5045 * See if it's a processor-specific option. These are:
5047 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
5048 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
5049 * Select the architecture. Instructions or features not
5050 * supported by the selected architecture cause fatal
5051 * errors. More than one may be specified. The default is
5052 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
5053 * for -m68000, and -m68882 is a synonym for -m68881.
5054 * -[A]m[c]no-68851, -[A]m[c]no-68881
5055 * Don't accept 688?1 instructions. (The "c" is kind of silly,
5056 * so don't use or document it, but that's the way the parsing
5059 * -pic Indicates PIC.
5060 * -k Indicates PIC. (Sun 3 only.)
5065 CONST
char *md_shortopts
= "lSA:m:kQ:V";
5067 CONST
char *md_shortopts
= "lSA:m:k";
5070 struct option md_longopts
[] = {
5071 #define OPTION_PIC (OPTION_MD_BASE)
5072 {"pic", no_argument
, NULL
, OPTION_PIC
},
5073 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
5074 {"register-prefix-optional", no_argument
, NULL
,
5075 OPTION_REGISTER_PREFIX_OPTIONAL
},
5076 {NULL
, no_argument
, NULL
, 0}
5078 size_t md_longopts_size
= sizeof(md_longopts
);
5081 md_parse_option (c
, arg
)
5090 case 'l': /* -l means keep external to 2 bit offset
5091 rather than 16 bit one */
5092 flag_short_refs
= 1;
5095 case 'S': /* -S means that jbsr's always turn into
5097 flag_long_jumps
= 1;
5103 /* intentional fall-through */
5106 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
5109 const char *oarg
= arg
;
5115 if (arg
[0] == 'c' && arg
[1] == '6')
5118 for (i
= 0; i
< n_archs
; i
++)
5119 if (!strcmp (arg
, archs
[i
].name
))
5124 as_bad ("unrecognized option `%s'", oarg
);
5127 arch
= archs
[i
].arch
;
5130 else if (arch
== m68851
)
5139 if (arg
[0] == 'c' && arg
[1] == '6')
5142 for (i
= 0; i
< n_archs
; i
++)
5143 if (!strcmp (arg
, archs
[i
].name
))
5145 unsigned long arch
= archs
[i
].arch
;
5146 if (cpu_of_arch (arch
))
5147 /* It's a cpu spec. */
5149 current_architecture
&= ~m68000up
;
5150 current_architecture
|= arch
;
5152 else if (arch
== m68881
)
5154 current_architecture
|= m68881
;
5157 else if (arch
== m68851
)
5159 current_architecture
|= m68851
;
5169 as_bad ("unrecognized architecture specification `%s'", arg
);
5178 break; /* -pic, Position Independent Code */
5180 case OPTION_REGISTER_PREFIX_OPTIONAL
:
5181 flag_reg_prefix_optional
= 1;
5196 md_show_usage (stream
)
5201 -l use 1 word for refs to undefined symbols [default 2]\n\
5202 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
5203 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
5205 specify variant of 680X0 architecture [default 68020]\n\
5206 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
5207 target has/lacks floating-point coprocessor\n\
5208 [default yes for 68020, 68030, and cpu32]\n\
5209 -m68851 | -mno-68851\n\
5210 target has/lacks memory-management unit coprocessor\n\
5211 [default yes for 68020 and up]\n\
5212 -pic, -k generate position independent code\n\
5213 -S turn jbsr into jsr\n\
5214 --register-prefix-optional\n\
5215 recognize register names without prefix character\n");
5220 /* TEST2: Test md_assemble() */
5221 /* Warning, this routine probably doesn't work anymore */
5225 struct m68k_it the_ins
;
5233 if (!gets (buf
) || !*buf
)
5235 if (buf
[0] == '|' || buf
[1] == '.')
5237 for (cp
= buf
; *cp
; cp
++)
5242 memset (&the_ins
, '\0', sizeof (the_ins
));
5243 m68k_ip (&the_ins
, buf
);
5246 printf ("Error %s in %s\n", the_ins
.error
, buf
);
5250 printf ("Opcode(%d.%s): ", the_ins
.numo
, the_ins
.args
);
5251 for (n
= 0; n
< the_ins
.numo
; n
++)
5252 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
5254 print_the_insn (&the_ins
.opcode
[0], stdout
);
5255 (void) putchar ('\n');
5257 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
5259 if (the_ins
.operands
[n
].error
)
5261 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
5264 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
, the_ins
.operands
[n
].reg
);
5265 if (the_ins
.operands
[n
].b_const
)
5266 printf ("Constant: '%.*s', ", 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
, the_ins
.operands
[n
].b_const
);
5267 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
, the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
5268 if (the_ins
.operands
[n
].b_iadd
)
5269 printf ("Iadd: '%.*s',", 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
, the_ins
.operands
[n
].b_iadd
);
5270 (void) putchar ('\n');
5282 while (*str
&& *str
!= ' ')
5284 if (str
[-1] == ':' || str
[1] == '=')
5291 /* Possible states for relaxation:
5293 0 0 branch offset byte (bra, etc)
5297 1 0 indexed offsets byte a0@(32,d4:w:1) etc
5301 2 0 two-offset index word-word a0@(32,d4)@(45) etc
5308 /* We have no need to default values of symbols. */
5312 md_undefined_symbol (name
)
5318 /* Round up a section size to the appropriate boundary. */
5320 md_section_align (segment
, size
)
5324 return size
; /* Byte alignment is fine */
5327 /* Exactly what point is a PC-relative offset relative TO?
5328 On the 68k, it is relative to the address of the first extension
5329 word. The difference between the addresses of the offset and the
5330 first extension word is stored in fx_pcrel_adjust. */
5332 md_pcrel_from (fixP
)
5335 return (fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- fixP
->fx_pcrel_adjust
);
5338 #ifndef BFD_ASSEMBLER
5341 tc_coff_symbol_emit_hook (ignore
)
5347 tc_coff_sizemachdep (frag
)
5350 switch (frag
->fr_subtype
& 0x3)
5364 /* end of tc-m68k.c */