1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "opcode/m68k.h"
27 #include "m68k-parse.h"
29 /* This array holds the chars that always start a comment. If the
30 pre-processor is disabled, these aren't very useful */
31 #if defined (OBJ_ELF) || defined (TE_DELTA)
32 const char comment_chars
[] = "|#";
34 const char comment_chars
[] = "|";
37 /* This array holds the chars that only start a comment at the beginning of
38 a line. If the line seems to have the form '# 123 filename'
39 .line and .file directives will appear in the pre-processed output */
40 /* Note that input_file.c hand checks for '#' at the beginning of the
41 first line of the input file. This is because the compiler outputs
42 #NO_APP at the beginning of its output. */
43 /* Also note that comments like this one will always work. */
44 const char line_comment_chars
[] = "#";
46 const char line_separator_chars
[] = "";
48 /* Chars that can be used to separate mant from exp in floating point nums */
49 CONST
char EXP_CHARS
[] = "eE";
51 /* Chars that mean this number is a floating point constant, as
52 in "0f12.456" or "0d1.2345e12". */
54 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
56 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
57 changed in read.c . Ideally it shouldn't have to know about it at all,
58 but nothing is ideal around here. */
60 const int md_reloc_size
= 8; /* Size of relocation record */
62 /* Are we trying to generate PIC code? If so, absolute references
63 ought to be made into linkage table references or pc-relative
64 references. Not implemented. For ELF there are other means
65 to denote pic relocations. */
68 static int flag_short_refs
; /* -l option */
69 static int flag_long_jumps
; /* -S option */
71 #ifdef REGISTER_PREFIX_OPTIONAL
72 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
74 int flag_reg_prefix_optional
;
77 /* Whether --register-prefix-optional was used on the command line. */
78 static int reg_prefix_optional_seen
;
80 /* The floating point coprocessor to use by default. */
81 static enum m68k_register m68k_float_copnum
= COP1
;
83 /* If this is non-zero, then references to number(%pc) will be taken
84 to refer to number, rather than to %pc + number. */
85 static int m68k_abspcadd
;
87 /* If this is non-zero, then the quick forms of the move, add, and sub
88 instructions are used when possible. */
89 static int m68k_quick
= 1;
91 /* If this is non-zero, then if the size is not specified for a base
92 or outer displacement, the assembler assumes that the size should
94 static int m68k_rel32
= 1;
96 /* Its an arbitrary name: This means I don't approve of it */
97 /* See flames below */
98 static struct obstack robyn
;
100 #define TAB(x,y) (((x)<<2)+(y))
101 #define TABTYPE(xy) ((xy) >> 2)
107 /* Case `g' except when BCC68000 is applicable. */
109 /* Coprocessor branches. */
111 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
112 supported on all cpus. Widens to 32-bit absolute. */
114 /* For inserting an extra jmp instruction with long offset on 68000,
115 for expanding conditional branches. (Not bsr or bra.) Since the
116 68000 doesn't support 32-bit displacements for conditional
117 branches, we fake it by reversing the condition and branching
118 around a jmp with an absolute long operand. */
120 /* For the DBcc "instructions". If the displacement requires 32 bits,
121 the branch-around-a-jump game is played here too. */
123 /* Not currently used? */
125 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
131 const char *m_operands
;
132 unsigned long m_opcode
;
136 struct m68k_incant
*m_next
;
139 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
140 #define gettwo(x) (((x)->m_opcode)&0xffff)
142 static const enum m68k_register m68000_control_regs
[] = { 0 };
143 static const enum m68k_register m68010_control_regs
[] = {
147 static const enum m68k_register m68020_control_regs
[] = {
148 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
151 static const enum m68k_register m68040_control_regs
[] = {
152 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
153 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
156 static const enum m68k_register m68060_control_regs
[] = {
157 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
158 USP
, VBR
, URP
, SRP
, PCR
,
161 #define cpu32_control_regs m68010_control_regs
163 static const enum m68k_register
*control_regs
;
165 /* internal form of a 68020 instruction */
169 const char *args
; /* list of opcode info */
172 int numo
; /* Number of shorts in opcode */
175 struct m68k_op operands
[6];
177 int nexp
; /* number of exprs in use */
178 struct m68k_exp exprs
[4];
180 int nfrag
; /* Number of frags we have to produce */
183 int fragoff
; /* Where in the current opcode the frag ends */
190 int nrel
; /* Num of reloc strucs in use */
197 /* In a pc relative address the difference between the address
198 of the offset and the address that the offset is relative
199 to. This depends on the addressing mode. Basically this
200 is the value to put in the offset field to address the
201 first byte of the offset, without regarding the special
202 significance of some values (in the branch instruction, for
206 /* Whether this expression needs special pic relocation, and if
208 enum pic_relocation pic_reloc
;
211 reloc
[5]; /* Five is enough??? */
214 #define cpu_of_arch(x) ((x) & m68000up)
215 #define float_of_arch(x) ((x) & mfloat)
216 #define mmu_of_arch(x) ((x) & mmmu)
218 static struct m68k_it the_ins
; /* the instruction being assembled */
220 #define op(ex) ((ex)->exp.X_op)
221 #define adds(ex) ((ex)->exp.X_add_symbol)
222 #define subs(ex) ((ex)->exp.X_op_symbol)
223 #define offs(ex) ((ex)->exp.X_add_number)
225 /* Macros for adding things to the m68k_it struct */
227 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
229 /* Like addword, but goes BEFORE general operands */
233 struct m68k_incant
*opcode
;
236 for(z
=the_ins
.numo
;z
>opcode
->m_codenum
;--z
)
237 the_ins
.opcode
[z
]=the_ins
.opcode
[z
-1];
238 for(z
=0;z
<the_ins
.nrel
;z
++)
239 the_ins
.reloc
[z
].n
+=2;
240 for (z
= 0; z
< the_ins
.nfrag
; z
++)
241 the_ins
.fragb
[z
].fragoff
++;
242 the_ins
.opcode
[opcode
->m_codenum
]=w
;
246 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
249 add_fix (width
, exp
, pc_rel
, pc_fix
)
251 struct m68k_exp
*exp
;
255 the_ins
.reloc
[the_ins
.nrel
].n
= (((width
)=='B')
259 : (the_ins
.numo
*2)));
260 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
261 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
262 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
264 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
266 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
269 /* Cause an extra frag to be generated here, inserting up to 10 bytes
270 (that value is chosen in the frag_var call in md_assemble). TYPE
271 is the subtype of the frag to be generated; its primary type is
272 rs_machine_dependent.
274 The TYPE parameter is also used by md_convert_frag_1 and
275 md_estimate_size_before_relax. The appropriate type of fixup will
276 be emitted by md_convert_frag_1.
278 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
280 add_frag(add
,off
,type
)
285 the_ins
.fragb
[the_ins
.nfrag
].fragoff
=the_ins
.numo
;
286 the_ins
.fragb
[the_ins
.nfrag
].fadd
=add
;
287 the_ins
.fragb
[the_ins
.nfrag
].foff
=off
;
288 the_ins
.fragb
[the_ins
.nfrag
++].fragty
=type
;
292 (op (ex) != O_constant && op (ex) != O_big)
294 static char *crack_operand
PARAMS ((char *str
, struct m68k_op
*opP
));
295 static int get_num
PARAMS ((struct m68k_exp
*exp
, int ok
));
296 static int reverse_16_bits
PARAMS ((int in
));
297 static int reverse_8_bits
PARAMS ((int in
));
298 static void install_gen_operand
PARAMS ((int mode
, int val
));
299 static void install_operand
PARAMS ((int mode
, int val
));
300 static void s_bss
PARAMS ((int));
301 static void s_data1
PARAMS ((int));
302 static void s_data2
PARAMS ((int));
303 static void s_even
PARAMS ((int));
304 static void s_proc
PARAMS ((int));
305 static void mri_chip
PARAMS ((void));
306 static void s_chip
PARAMS ((int));
307 static void s_fopt
PARAMS ((int));
308 static void s_opt
PARAMS ((int));
309 static void s_reg
PARAMS ((int));
310 static void s_restore
PARAMS ((int));
311 static void s_save
PARAMS ((int));
312 static void s_mri_if
PARAMS ((int));
313 static void s_mri_else
PARAMS ((int));
314 static void s_mri_endi
PARAMS ((int));
315 static void s_mri_break
PARAMS ((int));
316 static void s_mri_next
PARAMS ((int));
317 static void s_mri_for
PARAMS ((int));
318 static void s_mri_endf
PARAMS ((int));
319 static void s_mri_repeat
PARAMS ((int));
320 static void s_mri_until
PARAMS ((int));
321 static void s_mri_while
PARAMS ((int));
322 static void s_mri_endw
PARAMS ((int));
324 static int current_architecture
;
332 static const struct m68k_cpu archs
[] = {
333 { m68000
, "68000", 0 },
334 { m68010
, "68010", 0 },
335 { m68020
, "68020", 0 },
336 { m68030
, "68030", 0 },
337 { m68040
, "68040", 0 },
338 { m68060
, "68060", 0 },
339 { cpu32
, "cpu32", 0 },
340 { m68881
, "68881", 0 },
341 { m68851
, "68851", 0 },
342 /* Aliases (effectively, so far as gas is concerned) for the above
344 { m68020
, "68k", 1 },
345 { m68000
, "68302", 1 },
346 { m68000
, "68008", 1 },
347 { m68000
, "68ec000", 1 },
348 { m68000
, "68hc000", 1 },
349 { m68000
, "68hc001", 1 },
350 { m68020
, "68ec020", 1 },
351 { m68030
, "68ec030", 1 },
352 { m68040
, "68ec040", 1 },
353 { cpu32
, "68330", 1 },
354 { cpu32
, "68331", 1 },
355 { cpu32
, "68332", 1 },
356 { cpu32
, "68333", 1 },
357 { cpu32
, "68340", 1 },
358 { cpu32
, "68360", 1 },
359 { m68881
, "68882", 1 },
362 static const int n_archs
= sizeof (archs
) / sizeof (archs
[0]);
364 /* BCC68000 is for patching in an extra jmp instruction for long offsets
365 on the 68000. The 68000 doesn't support long branches with branchs */
367 /* This table desribes how you change sizes for the various types of variable
368 size expressions. This version only supports two kinds. */
370 /* Note that calls to frag_var need to specify the maximum expansion
371 needed; this is currently 10 bytes for DBCC. */
374 How far Forward this mode will reach:
375 How far Backward this mode will reach:
376 How many bytes this mode will add to the size of the frag
377 Which mode to go to if the offset won't fit in this one
379 relax_typeS md_relax_table
[] =
381 {1, 1, 0, 0}, /* First entries aren't used */
382 {1, 1, 0, 0}, /* For no good reason except */
383 {1, 1, 0, 0}, /* that the VAX doesn't either */
386 {(127), (-128), 0, TAB (ABRANCH
, SHORT
)},
387 {(32767), (-32768), 2, TAB (ABRANCH
, LONG
)},
391 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
392 {(32767), (-32768), 2, TAB (FBRANCH
, LONG
)},
396 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
397 {(32767), (-32768), 2, TAB (PCREL
, LONG
)},
401 {(127), (-128), 0, TAB (BCC68000
, SHORT
)},
402 {(32767), (-32768), 2, TAB (BCC68000
, LONG
)},
403 {0, 0, 6, 0}, /* jmp long space */
406 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
407 {(32767), (-32768), 2, TAB (DBCC
, LONG
)},
408 {0, 0, 10, 0}, /* bra/jmp long space */
411 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
412 {32767, -32768, 2, TAB (PCLEA
, LONG
)},
416 /* For, e.g., jmp pcrel indexed. */
417 {125, -130, 0, TAB (PCINDEX
, SHORT
)},
418 {32765, -32770, 2, TAB (PCINDEX
, LONG
)},
423 /* These are the machine dependent pseudo-ops. These are included so
424 the assembler can work on the output from the SUN C compiler, which
428 /* This table describes all the machine specific pseudo-ops the assembler
429 has to support. The fields are:
430 pseudo-op name without dot
431 function to call to execute this pseudo-op
432 Integer arg to pass to the function
434 const pseudo_typeS md_pseudo_table
[] =
436 {"data1", s_data1
, 0},
437 {"data2", s_data2
, 0},
440 {"skip", s_space
, 0},
442 #if defined (TE_SUN3) || defined (OBJ_ELF)
443 {"align", s_align_bytes
, 0},
446 {"swbeg", s_ignore
, 0},
448 {"extend", float_cons
, 'x'},
449 {"ldouble", float_cons
, 'x'},
451 /* The following pseudo-ops are supported for MRI compatibility. */
453 {"comline", s_space
, 1},
455 {"mask2", s_ignore
, 0},
458 {"restore", s_restore
, 0},
462 {"if.b", s_mri_if
, 'b'},
463 {"if.w", s_mri_if
, 'w'},
464 {"if.l", s_mri_if
, 'l'},
465 {"else", s_mri_else
, 0},
466 {"else.s", s_mri_else
, 's'},
467 {"else.l", s_mri_else
, 'l'},
468 {"endi", s_mri_endi
, 0},
469 {"break", s_mri_break
, 0},
470 {"break.s", s_mri_break
, 's'},
471 {"break.l", s_mri_break
, 'l'},
472 {"next", s_mri_next
, 0},
473 {"next.s", s_mri_next
, 's'},
474 {"next.l", s_mri_next
, 'l'},
475 {"for", s_mri_for
, 0},
476 {"for.b", s_mri_for
, 'b'},
477 {"for.w", s_mri_for
, 'w'},
478 {"for.l", s_mri_for
, 'l'},
479 {"endf", s_mri_endf
, 0},
480 {"repeat", s_mri_repeat
, 0},
481 {"until", s_mri_until
, 0},
482 {"until.b", s_mri_until
, 'b'},
483 {"until.w", s_mri_until
, 'w'},
484 {"until.l", s_mri_until
, 'l'},
485 {"while", s_mri_while
, 0},
486 {"while.b", s_mri_while
, 'b'},
487 {"while.w", s_mri_while
, 'w'},
488 {"while.l", s_mri_while
, 'l'},
489 {"endw", s_mri_endw
, 0},
495 /* The mote pseudo ops are put into the opcode table, since they
496 don't start with a . they look like opcodes to gas.
498 extern void obj_coff_section ();
500 CONST pseudo_typeS mote_pseudo_table
[] =
513 {"xdef", s_globl
, 0},
515 {"align", s_align_bytes
, 0},
517 {"align", s_align_ptwo
, 0},
520 {"sect", obj_coff_section
, 0},
521 {"section", obj_coff_section
, 0},
526 #define issbyte(x) ((x)>=-128 && (x)<=127)
527 #define isubyte(x) ((x)>=0 && (x)<=255)
528 #define issword(x) ((x)>=-32768 && (x)<=32767)
529 #define isuword(x) ((x)>=0 && (x)<=65535)
531 #define isbyte(x) ((x)>= -255 && (x)<=255)
532 #define isword(x) ((x)>=-65536 && (x)<=65535)
533 #define islong(x) (1)
535 extern char *input_line_pointer
;
537 static char mklower_table
[256];
538 #define mklower(c) (mklower_table[(unsigned char)(c)])
539 static char notend_table
[256];
540 static char alt_notend_table
[256];
542 (! (notend_table[(unsigned char) *s] \
544 && alt_notend_table[(unsigned char) s[1]])))
546 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
548 #ifdef NO_PCREL_RELOCS
551 make_pcrel_absolute(fixP
, add_number
)
555 register unsigned char *opcode
= fixP
->fx_frag
->fr_opcode
;
557 /* rewrite the PC relative instructions to absolute address ones.
558 * these are rumoured to be faster, and the apollo linker refuses
559 * to deal with the PC relative relocations.
561 if (opcode
[0] == 0x60 && opcode
[1] == 0xff) /* BRA -> JMP */
566 else if (opcode
[0] == 0x61 && opcode
[1] == 0xff) /* BSR -> JSR */
572 as_fatal ("Unknown PC relative instruction");
577 #endif /* NO_PCREL_RELOCS */
580 tc_coff_fix2rtype (fixP
)
583 if (fixP
->fx_tcbit
&& fixP
->fx_size
== 4)
584 return R_RELLONG_NEG
;
585 #ifdef NO_PCREL_RELOCS
586 know (fixP
->fx_pcrel
== 0);
587 return (fixP
->fx_size
== 1 ? R_RELBYTE
588 : fixP
->fx_size
== 2 ? R_DIR16
591 return (fixP
->fx_pcrel
?
592 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
593 fixP
->fx_size
== 2 ? R_PCRWORD
:
595 (fixP
->fx_size
== 1 ? R_RELBYTE
:
596 fixP
->fx_size
== 2 ? R_RELWORD
:
605 /* Compute the relocation code for a fixup of SIZE bytes, using pc
606 relative relocation if PCREL is non-zero. PIC says whether a special
607 pic relocation was requested. */
609 static bfd_reloc_code_real_type get_reloc_code
610 PARAMS ((int, int, enum pic_relocation
));
612 static bfd_reloc_code_real_type
613 get_reloc_code (size
, pcrel
, pic
)
616 enum pic_relocation pic
;
624 return BFD_RELOC_8_GOT_PCREL
;
626 return BFD_RELOC_16_GOT_PCREL
;
628 return BFD_RELOC_32_GOT_PCREL
;
636 return BFD_RELOC_8_GOTOFF
;
638 return BFD_RELOC_16_GOTOFF
;
640 return BFD_RELOC_32_GOTOFF
;
648 return BFD_RELOC_8_PLT_PCREL
;
650 return BFD_RELOC_16_PLT_PCREL
;
652 return BFD_RELOC_32_PLT_PCREL
;
660 return BFD_RELOC_8_PLTOFF
;
662 return BFD_RELOC_16_PLTOFF
;
664 return BFD_RELOC_32_PLTOFF
;
674 return BFD_RELOC_8_PCREL
;
676 return BFD_RELOC_16_PCREL
;
678 return BFD_RELOC_32_PCREL
;
695 as_bad ("Can not do %d byte %s%srelocation", size
,
696 pcrel
? "pc-relative " : "",
697 pic
== pic_none
? "" : "pic ");
698 return BFD_RELOC_NONE
;
701 /* Here we decide which fixups can be adjusted to make them relative
702 to the beginning of the section instead of the symbol. Basically
703 we need to make sure that the dynamic relocations are done
704 correctly, so in some cases we force the original symbol to be
707 tc_m68k_fix_adjustable (fixP
)
710 /* Prevent all adjustments to global symbols. */
711 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
714 /* adjust_reloc_syms doesn't know about the GOT */
715 switch (fixP
->fx_r_type
)
717 case BFD_RELOC_8_GOT_PCREL
:
718 case BFD_RELOC_16_GOT_PCREL
:
719 case BFD_RELOC_32_GOT_PCREL
:
720 case BFD_RELOC_8_GOTOFF
:
721 case BFD_RELOC_16_GOTOFF
:
722 case BFD_RELOC_32_GOTOFF
:
723 case BFD_RELOC_8_PLT_PCREL
:
724 case BFD_RELOC_16_PLT_PCREL
:
725 case BFD_RELOC_32_PLT_PCREL
:
726 case BFD_RELOC_8_PLTOFF
:
727 case BFD_RELOC_16_PLTOFF
:
728 case BFD_RELOC_32_PLTOFF
:
738 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
745 tc_gen_reloc (section
, fixp
)
750 bfd_reloc_code_real_type code
;
755 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
756 code
= fixp
->fx_r_type
;
759 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
760 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
762 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
763 MAP (1, 0, BFD_RELOC_8
);
764 MAP (2, 0, BFD_RELOC_16
);
765 MAP (4, 0, BFD_RELOC_32
);
766 MAP (1, 1, BFD_RELOC_8_PCREL
);
767 MAP (2, 1, BFD_RELOC_16_PCREL
);
768 MAP (4, 1, BFD_RELOC_32_PCREL
);
776 reloc
= (arelent
*) bfd_alloc_by_size_t (stdoutput
, sizeof (arelent
));
778 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
779 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
782 reloc
->addend
= fixp
->fx_addnumber
;
787 reloc
->addend
= fixp
->fx_addnumber
;
788 else if ((fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
789 reloc
->addend
= (section
->vma
790 + (fixp
->fx_pcrel_adjust
== 64
791 ? -1 : fixp
->fx_pcrel_adjust
)
793 + md_pcrel_from (fixp
));
795 reloc
->addend
= (fixp
->fx_offset
796 + (fixp
->fx_pcrel_adjust
== 64
797 ? -1 : fixp
->fx_pcrel_adjust
));
800 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
801 assert (reloc
->howto
!= 0);
806 #endif /* BFD_ASSEMBLER */
808 /* Handle of the OPCODE hash table. NULL means any use before
809 m68k_ip_begin() will crash. */
810 static struct hash_control
*op_hash
;
812 /* Assemble an m68k instruction. */
819 register struct m68k_op
*opP
;
820 register struct m68k_incant
*opcode
;
821 register const char *s
;
822 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
823 char *pdot
, *pdotmove
;
824 enum m68k_size siz1
, siz2
;
828 char *crack_operand ();
829 LITTLENUM_TYPE words
[6];
830 LITTLENUM_TYPE
*wordp
;
831 unsigned long ok_arch
= 0;
833 if (*instring
== ' ')
834 instring
++; /* skip leading whitespace */
836 /* Scan up to end of operation-code, which MUST end in end-of-string
837 or exactly 1 space. */
839 for (p
= instring
; *p
!= '\0'; p
++)
849 the_ins
.error
= "No operator";
853 /* p now points to the end of the opcode name, probably whitespace.
854 Make sure the name is null terminated by clobbering the
855 whitespace, look it up in the hash table, then fix it back.
856 Remove a dot, first, since the opcode tables have none. */
859 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
860 *pdotmove
= pdotmove
[1];
866 opcode
= (struct m68k_incant
*) hash_find (op_hash
, instring
);
871 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
872 *pdotmove
= pdotmove
[-1];
879 the_ins
.error
= "Unknown operator";
883 /* found a legitimate opcode, start matching operands */
887 if (opcode
->m_operands
== 0)
889 char *old
= input_line_pointer
;
891 input_line_pointer
= p
;
892 /* Ahh - it's a motorola style psuedo op */
893 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
894 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
895 input_line_pointer
= old
;
901 if (flag_mri
&& opcode
->m_opnum
== 0)
903 /* In MRI mode, random garbage is allowed after an instruction
904 which accepts no operands. */
905 the_ins
.args
= opcode
->m_operands
;
906 the_ins
.numargs
= opcode
->m_opnum
;
907 the_ins
.numo
= opcode
->m_codenum
;
908 the_ins
.opcode
[0] = getone (opcode
);
909 the_ins
.opcode
[1] = gettwo (opcode
);
913 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
915 p
= crack_operand (p
, opP
);
919 the_ins
.error
= opP
->error
;
924 opsfound
= opP
- &the_ins
.operands
[0];
926 /* This ugly hack is to support the floating pt opcodes in their
927 standard form. Essentially, we fake a first enty of type COP#1 */
928 if (opcode
->m_operands
[0] == 'I')
932 for (n
= opsfound
; n
> 0; --n
)
933 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
935 memset ((char *) (&the_ins
.operands
[0]), '\0',
936 sizeof (the_ins
.operands
[0]));
937 the_ins
.operands
[0].mode
= CONTROL
;
938 the_ins
.operands
[0].reg
= m68k_float_copnum
;
942 /* We've got the operands. Find an opcode that'll accept them */
945 /* If we didn't get the right number of ops, or we have no
946 common model with this pattern then reject this pattern. */
948 if (opsfound
!= opcode
->m_opnum
949 || ((opcode
->m_arch
& current_architecture
) == 0))
952 ok_arch
|= opcode
->m_arch
;
956 for (s
= opcode
->m_operands
, opP
= &the_ins
.operands
[0];
960 /* Warning: this switch is huge! */
961 /* I've tried to organize the cases into this order:
962 non-alpha first, then alpha by letter. Lower-case
963 goes directly before uppercase counterpart. */
964 /* Code with multiple case ...: gets sorted by the lowest
965 case ... it belongs to. I hope this makes sense. */
1005 if (opP
->mode
!= IMMED
)
1007 else if (s
[1] == 'b'
1008 && ! isvar (&opP
->disp
)
1009 && (opP
->disp
.exp
.X_op
!= O_constant
1010 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1012 else if (s
[1] == 'w'
1013 && ! isvar (&opP
->disp
)
1014 && (opP
->disp
.exp
.X_op
!= O_constant
1015 || ! isword (opP
->disp
.exp
.X_add_number
)))
1017 else if (s
[1] == 'W'
1018 && ! isvar (&opP
->disp
)
1019 && (opP
->disp
.exp
.X_op
!= O_constant
1020 || ! issword (opP
->disp
.exp
.X_add_number
)))
1026 if (opP
->mode
!= IMMED
)
1031 if (opP
->mode
== AREG
1032 || opP
->mode
== CONTROL
1033 || opP
->mode
== FPREG
1034 || opP
->mode
== IMMED
1035 || opP
->mode
== REGLST
1036 || (opP
->mode
!= ABSL
1038 || opP
->reg
== ZPC
)))
1043 if (opP
->mode
== CONTROL
1044 || opP
->mode
== FPREG
1045 || opP
->mode
== REGLST
1046 || opP
->mode
== IMMED
1047 || (opP
->mode
!= ABSL
1049 || opP
->reg
== ZPC
)))
1077 if (opP
->mode
== CONTROL
1078 || opP
->mode
== FPREG
1079 || opP
->mode
== REGLST
)
1084 if (opP
->mode
!= AINC
)
1089 if (opP
->mode
!= ADEC
)
1139 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1160 case '~': /* For now! (JF FOO is this right?) */
1182 if (opP
->mode
!= CONTROL
1183 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1188 if (opP
->mode
!= AREG
)
1193 if (opP
->mode
!= AINDR
)
1198 if (opP
->mode
!= ABSL
1200 && strncmp (instring
, "jbsr", 4) == 0))
1205 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1210 if (opP
->mode
!= DISP
1212 || opP
->reg
> ADDR7
)
1217 if (opP
->mode
!= DREG
)
1222 if (opP
->mode
!= FPREG
)
1227 if (opP
->mode
!= CONTROL
1234 if (opP
->mode
!= CONTROL
1236 || opP
->reg
> last_movec_reg
)
1240 const enum m68k_register
*rp
;
1241 for (rp
= control_regs
; *rp
; rp
++)
1242 if (*rp
== opP
->reg
)
1250 if (opP
->mode
!= IMMED
)
1256 if (opP
->mode
== DREG
1257 || opP
->mode
== AREG
1258 || opP
->mode
== FPREG
)
1267 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1270 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1273 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1281 else if (opP
->mode
== CONTROL
)
1290 opP
->mask
= 1 << 24;
1293 opP
->mask
= 1 << 25;
1296 opP
->mask
= 1 << 26;
1305 else if (opP
->mode
== ABSL
1306 && opP
->disp
.size
== SIZE_UNSPEC
1307 && opP
->disp
.exp
.X_op
== O_constant
)
1309 /* This is what the MRI REG pseudo-op generates. */
1311 opP
->mask
= opP
->disp
.exp
.X_add_number
;
1313 else if (opP
->mode
!= REGLST
)
1315 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
1317 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
1322 if (opP
->mode
!= IMMED
)
1324 else if (opP
->disp
.exp
.X_op
!= O_constant
1325 || ! issbyte (opP
->disp
.exp
.X_add_number
))
1327 else if (! m68k_quick
1328 && instring
[3] != 'q'
1329 && instring
[4] != 'q')
1334 if (opP
->mode
!= DREG
&& opP
->mode
!= IMMED
)
1339 if (opP
->mode
!= IMMED
)
1341 else if (opP
->disp
.exp
.X_op
!= O_constant
1342 || opP
->disp
.exp
.X_add_number
< 1
1343 || opP
->disp
.exp
.X_add_number
> 8)
1345 else if (! m68k_quick
1346 && (strncmp (instring
, "add", 3) == 0
1347 || strncmp (instring
, "sub", 3) == 0)
1348 && instring
[3] != 'q')
1353 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1358 if (opP
->mode
!= AINDR
1359 && (opP
->mode
!= BASE
1361 && opP
->reg
!= ZADDR0
)
1362 || opP
->disp
.exp
.X_op
!= O_absent
1363 || ((opP
->index
.reg
< DATA0
1364 || opP
->index
.reg
> DATA7
)
1365 && (opP
->index
.reg
< ADDR0
1366 || opP
->index
.reg
> ADDR7
))
1367 || opP
->index
.size
!= SIZE_UNSPEC
1368 || opP
->index
.scale
!= 1))
1373 if (opP
->mode
!= CONTROL
1374 || ! (opP
->reg
== FPI
1376 || opP
->reg
== FPC
))
1381 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
1386 if (opP
->mode
!= IMMED
)
1388 else if (opP
->disp
.exp
.X_op
!= O_constant
1389 || opP
->disp
.exp
.X_add_number
< 0
1390 || opP
->disp
.exp
.X_add_number
> 7)
1395 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
1399 /* JF these are out of order. We could put them
1400 in order if we were willing to put up with
1401 bunches of #ifdef m68851s in the code.
1403 Don't forget that you need these operands
1404 to use 68030 MMU instructions. */
1406 /* Memory addressing mode used by pflushr */
1408 if (opP
->mode
== CONTROL
1409 || opP
->mode
== FPREG
1410 || opP
->mode
== DREG
1411 || opP
->mode
== AREG
1412 || opP
->mode
== REGLST
)
1414 /* We should accept immediate operands, but they
1415 supposedly have to be quad word, and we don't
1416 handle that. I would like to see what a Motorola
1417 assembler does before doing something here. */
1418 if (opP
->mode
== IMMED
)
1423 if (opP
->mode
!= CONTROL
1424 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1429 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
1434 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
1439 if (opP
->mode
!= CONTROL
1442 && opP
->reg
!= SCC
))
1447 if (opP
->mode
!= CONTROL
1453 if (opP
->mode
!= CONTROL
1456 && opP
->reg
!= CRP
))
1461 if (opP
->mode
!= CONTROL
1462 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
1463 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
1468 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
1473 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
1478 if (opP
->mode
!= CONTROL
1485 } /* not a cache specifier. */
1489 if (opP
->mode
!= ABSL
)
1495 } /* switch on type of operand */
1499 } /* for each operand */
1500 } /* if immediately wrong */
1507 opcode
= opcode
->m_next
;
1512 && !(ok_arch
& current_architecture
))
1517 "invalid instruction for this architecture; needs ");
1518 cp
= buf
+ strlen (buf
);
1522 strcpy (cp
, "fpu (68040, 68060 or 68881/68882)");
1525 strcpy (cp
, "mmu (68030 or 68851)");
1528 strcpy (cp
, "68020 or higher");
1531 strcpy (cp
, "68000 or higher");
1534 strcpy (cp
, "68010 or higher");
1538 int got_one
= 0, idx
;
1539 for (idx
= 0; idx
< sizeof (archs
) / sizeof (archs
[0]);
1542 if ((archs
[idx
].arch
& ok_arch
)
1543 && ! archs
[idx
].alias
)
1547 strcpy (cp
, " or ");
1551 strcpy (cp
, archs
[idx
].name
);
1563 the_ins
.error
= "operands mismatch";
1565 } /* Fell off the end */
1570 /* now assemble it */
1572 the_ins
.args
= opcode
->m_operands
;
1573 the_ins
.numargs
= opcode
->m_opnum
;
1574 the_ins
.numo
= opcode
->m_codenum
;
1575 the_ins
.opcode
[0] = getone (opcode
);
1576 the_ins
.opcode
[1] = gettwo (opcode
);
1578 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
1580 /* This switch is a doozy.
1581 Watch the first step; its a big one! */
1602 tmpreg
= 0x3c; /* 7.4 */
1603 if (strchr ("bwl", s
[1]))
1604 nextword
= get_num (&opP
->disp
, 80);
1606 nextword
= get_num (&opP
->disp
, 0);
1607 if (isvar (&opP
->disp
))
1608 add_fix (s
[1], &opP
->disp
, 0, 0);
1612 if (!isbyte (nextword
))
1613 opP
->error
= "operand out of range";
1618 if (!isword (nextword
))
1619 opP
->error
= "operand out of range";
1624 if (!issword (nextword
))
1625 opP
->error
= "operand out of range";
1630 addword (nextword
>> 16);
1657 /* We gotta put out some float */
1658 if (op (&opP
->disp
) != O_big
)
1663 /* Can other cases happen here? */
1664 if (op (&opP
->disp
) != O_constant
)
1667 val
= (valueT
) offs (&opP
->disp
);
1671 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
1672 val
>>= LITTLENUM_NUMBER_OF_BITS
;
1676 offs (&opP
->disp
) = gencnt
;
1678 if (offs (&opP
->disp
) > 0)
1680 if (offs (&opP
->disp
) > baseo
)
1682 as_warn ("Bignum too big for %c format; truncated",
1684 offs (&opP
->disp
) = baseo
;
1686 baseo
-= offs (&opP
->disp
);
1689 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
1690 offs (&opP
->disp
)--;
1695 gen_to_words (words
, baseo
, (long) outro
);
1696 for (wordp
= words
; baseo
--; wordp
++)
1700 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
1703 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
1706 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
1709 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
1712 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
1716 nextword
= get_num (&opP
->disp
, 80);
1719 && ! isvar (&opP
->disp
)
1722 opP
->disp
.exp
.X_op
= O_symbol
;
1723 #ifndef BFD_ASSEMBLER
1724 opP
->disp
.exp
.X_add_symbol
= &abs_symbol
;
1726 opP
->disp
.exp
.X_add_symbol
=
1727 section_symbol (absolute_section
);
1731 /* Force into index mode. Hope this works */
1733 /* We do the first bit for 32-bit displacements, and the
1734 second bit for 16 bit ones. It is possible that we
1735 should make the default be WORD instead of LONG, but
1736 I think that'd break GCC, so we put up with a little
1737 inefficiency for the sake of working output. */
1739 if (!issword (nextword
)
1740 || (isvar (&opP
->disp
)
1741 && ((opP
->disp
.size
== SIZE_UNSPEC
1742 && flag_short_refs
== 0
1743 && cpu_of_arch (current_architecture
) >= m68020
)
1744 || opP
->disp
.size
== SIZE_LONG
)))
1747 tmpreg
= 0x3B; /* 7.3 */
1749 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
1750 if (isvar (&opP
->disp
))
1754 if (opP
->disp
.size
== SIZE_LONG
1756 /* If the displacement needs pic
1757 relocation it cannot be relaxed. */
1758 || opP
->disp
.pic_reloc
!= pic_none
1763 add_fix ('l', &opP
->disp
, 1, 2);
1767 add_frag (adds (&opP
->disp
),
1769 TAB (PCLEA
, SZ_UNDEF
));
1776 add_fix ('l', &opP
->disp
, 0, 0);
1781 addword (nextword
>> 16);
1786 tmpreg
= 0x3A; /* 7.2 */
1788 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
1790 if (isvar (&opP
->disp
))
1794 add_fix ('w', &opP
->disp
, 1, 0);
1797 add_fix ('w', &opP
->disp
, 0, 0);
1807 baseo
= get_num (&opP
->disp
, 80);
1808 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
1809 outro
= get_num (&opP
->odisp
, 80);
1810 /* Figure out the `addressing mode'.
1811 Also turn on the BASE_DISABLE bit, if needed. */
1812 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1814 tmpreg
= 0x3b; /* 7.3 */
1815 if (opP
->reg
== ZPC
)
1818 else if (opP
->reg
== 0)
1821 tmpreg
= 0x30; /* 6.garbage */
1823 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
1826 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
1829 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
1831 siz1
= opP
->disp
.size
;
1832 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
1833 siz2
= opP
->odisp
.size
;
1837 /* Index register stuff */
1838 if (opP
->index
.reg
!= 0
1839 && opP
->index
.reg
>= DATA
1840 && opP
->index
.reg
<= ADDR7
)
1842 nextword
|= (opP
->index
.reg
- DATA
) << 12;
1844 if (opP
->index
.size
== SIZE_UNSPEC
1845 || opP
->index
.size
== SIZE_LONG
)
1848 if (cpu_of_arch (current_architecture
) < m68020
)
1850 if (opP
->index
.scale
!= 1)
1853 "scale factor invalid on this architecture; needs 68020 or higher";
1857 switch (opP
->index
.scale
)
1874 GET US OUT OF HERE! */
1876 /* Must be INDEX, with an index register. Address
1877 register cannot be ZERO-PC, and either :b was
1878 forced, or we know it will fit. For a 68000 or
1879 68010, force this mode anyways, because the
1880 larger modes aren't supported. */
1881 if (opP
->mode
== BASE
1882 && ((opP
->reg
>= ADDR0
1883 && opP
->reg
<= ADDR7
)
1886 if (siz1
== SIZE_BYTE
1887 || cpu_of_arch (current_architecture
) < m68020
1888 || (siz1
== SIZE_UNSPEC
1889 && ! isvar (&opP
->disp
)
1890 && issbyte (baseo
)))
1892 nextword
+= baseo
& 0xff;
1894 if (isvar (&opP
->disp
))
1896 /* Do a byte relocation. If it doesn't
1897 fit (possible on m68000) let the
1898 fixup processing complain later. */
1900 add_fix ('B', &opP
->disp
, 1, 1);
1902 add_fix ('B', &opP
->disp
, 0, 0);
1904 else if (siz1
!= SIZE_BYTE
)
1906 if (siz1
!= SIZE_UNSPEC
)
1907 as_warn ("Forcing byte displacement");
1908 if (! issbyte (baseo
))
1909 opP
->error
= "byte displacement out of range";
1914 else if (siz1
== SIZE_UNSPEC
1916 && isvar (&opP
->disp
)
1917 && subs (&opP
->disp
) == NULL
1919 /* If the displacement needs pic
1920 relocation it cannot be relaxed. */
1921 && opP
->disp
.pic_reloc
== pic_none
1925 nextword
+= baseo
& 0xff;
1927 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
1928 TAB (PCINDEX
, SZ_UNDEF
));
1936 nextword
|= 0x40; /* No index reg */
1937 if (opP
->index
.reg
>= ZDATA0
1938 && opP
->index
.reg
<= ZDATA7
)
1939 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
1940 else if (opP
->index
.reg
>= ZADDR0
1941 || opP
->index
.reg
<= ZADDR7
)
1942 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
1945 /* It isn't simple. */
1947 if (cpu_of_arch (current_architecture
) < m68020
)
1949 "invalid operand mode for this architecture; needs 68020 or higher";
1952 /* If the guy specified a width, we assume that it is
1953 wide enough. Maybe it isn't. If so, we lose. */
1957 if (isvar (&opP
->disp
)
1959 : ! issword (baseo
))
1964 else if (! isvar (&opP
->disp
) && baseo
== 0)
1973 as_warn (":b not permitted; defaulting to :w");
1983 /* Figure out innner displacement stuff */
1984 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
1989 if (isvar (&opP
->odisp
)
1991 : ! issword (outro
))
1996 else if (! isvar (&opP
->odisp
) && outro
== 0)
2005 as_warn (":b not permitted; defaulting to :w");
2014 if (opP
->mode
== POST
2015 && (nextword
& 0x40) == 0)
2020 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2022 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2023 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2025 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2027 if (siz1
== SIZE_LONG
)
2028 addword (baseo
>> 16);
2029 if (siz1
!= SIZE_UNSPEC
)
2032 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2033 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2034 if (siz2
== SIZE_LONG
)
2035 addword (outro
>> 16);
2036 if (siz2
!= SIZE_UNSPEC
)
2042 nextword
= get_num (&opP
->disp
, 80);
2043 switch (opP
->disp
.size
)
2048 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2050 tmpreg
= 0x38; /* 7.0 */
2054 /* Don't generate pc relative code on 68010 and
2056 if (isvar (&opP
->disp
)
2057 && !subs (&opP
->disp
)
2058 && adds (&opP
->disp
)
2060 /* If the displacement needs pic relocation it
2061 cannot be relaxed. */
2062 && opP
->disp
.pic_reloc
== pic_none
2064 && S_GET_SEGMENT (adds (&opP
->disp
)) == now_seg
2065 && cpu_of_arch (current_architecture
) >= m68020
2067 && !strchr ("~%&$?", s
[0]))
2069 tmpreg
= 0x3A; /* 7.2 */
2070 add_frag (adds (&opP
->disp
),
2072 TAB (PCREL
, SZ_UNDEF
));
2075 /* Fall through into long */
2077 if (isvar (&opP
->disp
))
2078 add_fix ('l', &opP
->disp
, 0, 0);
2080 tmpreg
= 0x39;/* 7.1 mode */
2081 addword (nextword
>> 16);
2085 case SIZE_WORD
: /* Word */
2086 if (isvar (&opP
->disp
))
2087 add_fix ('w', &opP
->disp
, 0, 0);
2089 tmpreg
= 0x38;/* 7.0 mode */
2097 as_bad ("unknown/incorrect operand");
2100 install_gen_operand (s
[1], tmpreg
);
2106 { /* JF: I hate floating point! */
2121 tmpreg
= get_num (&opP
->disp
, tmpreg
);
2122 if (isvar (&opP
->disp
))
2123 add_fix (s
[1], &opP
->disp
, 0, 0);
2126 case 'b': /* Danger: These do no check for
2127 certain types of overflow.
2129 if (!isbyte (tmpreg
))
2130 opP
->error
= "out of range";
2131 insop (tmpreg
, opcode
);
2132 if (isvar (&opP
->disp
))
2133 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
2134 (opcode
->m_codenum
) * 2 + 1;
2137 if (!isword (tmpreg
))
2138 opP
->error
= "out of range";
2139 insop (tmpreg
, opcode
);
2140 if (isvar (&opP
->disp
))
2141 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2144 if (!issword (tmpreg
))
2145 opP
->error
= "out of range";
2146 insop (tmpreg
, opcode
);
2147 if (isvar (&opP
->disp
))
2148 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2151 /* Because of the way insop works, we put these two out
2153 insop (tmpreg
, opcode
);
2154 insop (tmpreg
>> 16, opcode
);
2155 if (isvar (&opP
->disp
))
2156 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2162 install_operand (s
[1], tmpreg
);
2173 install_operand (s
[1], opP
->reg
- ADDR
);
2177 tmpreg
= get_num (&opP
->disp
, 80);
2181 /* The pc_fix argument winds up in fx_pcrel_adjust,
2182 which is a char, and may therefore be unsigned. We
2183 want to pass -1, but we pass 64 instead, and convert
2184 back in md_pcrel_from. */
2185 add_fix ('B', &opP
->disp
, 1, 64);
2188 add_fix ('w', &opP
->disp
, 1, 0);
2193 if (cpu_of_arch (current_architecture
) < m68020
)
2194 as_warn ("Can't use long branches on 68000/68010");
2195 the_ins
.opcode
[the_ins
.numo
- 1] |= 0xff;
2196 add_fix ('l', &opP
->disp
, 1, 0);
2201 if (subs (&opP
->disp
)) /* We can't relax it */
2205 /* If the displacement needs pic relocation it cannot be
2207 if (opP
->disp
.pic_reloc
!= pic_none
)
2211 /* This could either be a symbol, or an absolute
2212 address. No matter, the frag hacking will finger it
2213 out. Not quite: it can't switch from BRANCH to
2214 BCC68000 for the case where opnd is absolute (it
2215 needs to use the 68000 hack since no conditional abs
2217 if (((cpu_of_arch (current_architecture
) < m68020
)
2218 || (0 == adds (&opP
->disp
)))
2219 && (the_ins
.opcode
[0] >= 0x6200)
2220 && (the_ins
.opcode
[0] <= 0x6f00))
2221 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2222 TAB (BCC68000
, SZ_UNDEF
));
2224 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2225 TAB (ABRANCH
, SZ_UNDEF
));
2228 if (isvar (&opP
->disp
))
2231 /* check for DBcc instruction */
2232 if ((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2234 /* size varies if patch */
2235 /* needed for long form */
2236 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2237 TAB (DBCC
, SZ_UNDEF
));
2241 add_fix ('w', &opP
->disp
, 1, 0);
2245 case 'C': /* Fixed size LONG coproc branches */
2246 add_fix ('l', &opP
->disp
, 1, 0);
2250 case 'c': /* Var size Coprocesssor branches */
2251 if (subs (&opP
->disp
))
2253 add_fix ('l', &opP
->disp
, 1, 0);
2254 add_frag ((symbolS
*) 0, (long) 0, TAB (FBRANCH
, LONG
));
2256 else if (adds (&opP
->disp
))
2257 add_frag (adds (&opP
->disp
), offs (&opP
->disp
),
2258 TAB (FBRANCH
, SZ_UNDEF
));
2261 /* add_frag((symbolS *) 0, offs(&opP->disp),
2262 TAB(FBRANCH,SHORT)); */
2263 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2264 add_fix ('l', &opP
->disp
, 1, 0);
2274 case 'C': /* Ignore it */
2277 case 'd': /* JF this is a kludge */
2278 install_operand ('s', opP
->reg
- ADDR
);
2279 tmpreg
= get_num (&opP
->disp
, 80);
2280 if (!issword (tmpreg
))
2282 as_warn ("Expression out of range, using 0");
2289 install_operand (s
[1], opP
->reg
- DATA
);
2293 install_operand (s
[1], opP
->reg
- FP0
);
2297 tmpreg
= opP
->reg
- COP0
;
2298 install_operand (s
[1], tmpreg
);
2301 case 'J': /* JF foo */
2362 install_operand (s
[1], tmpreg
);
2366 tmpreg
= get_num (&opP
->disp
, 55);
2367 install_operand (s
[1], tmpreg
& 0x7f);
2374 if (tmpreg
& 0x7FF0000)
2375 as_bad ("Floating point register in register list");
2376 insop (reverse_16_bits (tmpreg
), opcode
);
2380 if (tmpreg
& 0x700FFFF)
2381 as_bad ("Wrong register in floating-point reglist");
2382 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
2390 if (tmpreg
& 0x7FF0000)
2391 as_bad ("Floating point register in register list");
2392 insop (tmpreg
, opcode
);
2394 else if (s
[1] == '8')
2396 if (tmpreg
& 0x0FFFFFF)
2397 as_bad ("incorrect register in reglist");
2398 install_operand (s
[1], tmpreg
>> 24);
2402 if (tmpreg
& 0x700FFFF)
2403 as_bad ("wrong register in floating-point reglist");
2405 install_operand (s
[1], tmpreg
>> 16);
2410 install_operand (s
[1], get_num (&opP
->disp
, 60));
2414 tmpreg
= ((opP
->mode
== DREG
)
2415 ? 0x20 + opP
->reg
- DATA
2416 : (get_num (&opP
->disp
, 40) & 0x1F));
2417 install_operand (s
[1], tmpreg
);
2421 tmpreg
= get_num (&opP
->disp
, 10);
2424 install_operand (s
[1], tmpreg
);
2428 /* This depends on the fact that ADDR registers are eight
2429 more than their corresponding DATA regs, so the result
2430 will have the ADDR_REG bit set */
2431 install_operand (s
[1], opP
->reg
- DATA
);
2435 if (opP
->mode
== AINDR
)
2436 install_operand (s
[1], opP
->reg
- DATA
);
2438 install_operand (s
[1], opP
->index
.reg
- DATA
);
2442 if (opP
->reg
== FPI
)
2444 else if (opP
->reg
== FPS
)
2446 else if (opP
->reg
== FPC
)
2450 install_operand (s
[1], tmpreg
);
2453 case 'S': /* Ignore it */
2457 install_operand (s
[1], get_num (&opP
->disp
, 30));
2460 case 'U': /* Ignore it */
2479 as_fatal ("failed sanity check");
2480 } /* switch on cache token */
2481 install_operand (s
[1], tmpreg
);
2484 /* JF: These are out of order, I fear. */
2497 install_operand (s
[1], tmpreg
);
2523 install_operand (s
[1], tmpreg
);
2527 if (opP
->reg
== VAL
)
2546 install_operand (s
[1], tmpreg
);
2560 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
2571 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
2577 install_operand (s
[1], tmpreg
);
2580 know (opP
->reg
== PSR
);
2583 know (opP
->reg
== PCSR
);
2598 install_operand (s
[1], tmpreg
);
2601 tmpreg
= get_num (&opP
->disp
, 20);
2602 install_operand (s
[1], tmpreg
);
2604 case '_': /* used only for move16 absolute 32-bit address */
2605 tmpreg
= get_num (&opP
->disp
, 80);
2606 addword (tmpreg
>> 16);
2607 addword (tmpreg
& 0xFFFF);
2614 /* By the time whe get here (FINALLY) the_ins contains the complete
2615 instruction, ready to be emitted. . . */
2619 reverse_16_bits (in
)
2625 static int mask
[16] =
2627 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2628 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2630 for (n
= 0; n
< 16; n
++)
2633 out
|= mask
[15 - n
];
2636 } /* reverse_16_bits() */
2645 static int mask
[8] =
2647 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2650 for (n
= 0; n
< 8; n
++)
2656 } /* reverse_8_bits() */
2658 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2659 (that value is chosen in the frag_var call in md_assemble). TYPE
2660 is the subtype of the frag to be generated; its primary type is
2661 rs_machine_dependent.
2663 The TYPE parameter is also used by md_convert_frag_1 and
2664 md_estimate_size_before_relax. The appropriate type of fixup will
2665 be emitted by md_convert_frag_1.
2667 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2669 install_operand (mode
, val
)
2676 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge */
2679 the_ins
.opcode
[0] |= val
<< 9;
2682 the_ins
.opcode
[1] |= val
<< 12;
2685 the_ins
.opcode
[1] |= val
<< 6;
2688 the_ins
.opcode
[1] |= val
;
2691 the_ins
.opcode
[2] |= val
<< 12;
2694 the_ins
.opcode
[2] |= val
<< 6;
2697 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2698 three words long! */
2700 the_ins
.opcode
[2] |= val
;
2703 the_ins
.opcode
[1] |= val
<< 7;
2706 the_ins
.opcode
[1] |= val
<< 10;
2710 the_ins
.opcode
[1] |= val
<< 5;
2715 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
2718 the_ins
.opcode
[1] |= (val
<< 12) | val
;
2721 the_ins
.opcode
[0] |= val
= 0xff;
2724 the_ins
.opcode
[0] |= val
<< 9;
2727 the_ins
.opcode
[1] |= val
;
2730 the_ins
.opcode
[1] |= val
;
2731 the_ins
.numo
++; /* What a hack */
2734 the_ins
.opcode
[1] |= val
<< 4;
2742 the_ins
.opcode
[0] |= (val
<< 6);
2745 the_ins
.opcode
[1] = (val
>> 16);
2746 the_ins
.opcode
[2] = val
& 0xffff;
2750 as_fatal ("failed sanity check.");
2752 } /* install_operand() */
2755 install_gen_operand (mode
, val
)
2762 the_ins
.opcode
[0] |= val
;
2765 /* This is a kludge!!! */
2766 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
2775 the_ins
.opcode
[0] |= val
;
2777 /* more stuff goes here */
2779 as_fatal ("failed sanity check.");
2781 } /* install_gen_operand() */
2784 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2785 * then deal with the bitfield hack.
2789 crack_operand (str
, opP
)
2791 register struct m68k_op
*opP
;
2793 register int parens
;
2795 register char *beg_str
;
2803 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
2809 else if (*str
== ')')
2813 opP
->error
= "Extra )";
2819 if (flag_mri
&& *str
== '\'')
2820 inquote
= ! inquote
;
2822 if (!*str
&& parens
)
2824 opP
->error
= "Missing )";
2829 if (m68k_ip_op (beg_str
, opP
) != 0)
2836 c
= *++str
; /* JF bitfield hack */
2841 as_bad ("Missing operand");
2846 /* This is the guts of the machine-dependent assembler. STR points to a
2847 machine dependent instruction. This function is supposed to emit
2848 the frags/bytes it assembles to.
2852 insert_reg (regname
, regnum
)
2859 #ifdef REGISTER_PREFIX
2860 if (!flag_reg_prefix_optional
)
2862 buf
[0] = REGISTER_PREFIX
;
2863 strcpy (buf
+ 1, regname
);
2868 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
2869 &zero_address_frag
));
2871 for (i
= 0; regname
[i
]; i
++)
2872 buf
[i
] = islower (regname
[i
]) ? toupper (regname
[i
]) : regname
[i
];
2875 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
2876 &zero_address_frag
));
2885 static const struct init_entry init_table
[] =
2995 /* 68ec030 versions of same */
2998 /* 68ec030 access control unit, identical to 030 MMU status reg */
3001 /* Suppressed data and address registers. */
3026 for (i
= 0; init_table
[i
].name
; i
++)
3027 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
3030 static int no_68851
, no_68881
;
3033 /* a.out machine type. Default to 68020. */
3034 int m68k_aout_machtype
= 2;
3046 int shorts_this_frag
;
3049 /* In MRI mode, the instruction and operands are separated by a
3050 space. Anything following the operands is a comment. The label
3051 has already been removed. */
3059 for (s
= str
; *s
!= '\0'; s
++)
3061 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
3079 inquote
= ! inquote
;
3084 memset ((char *) (&the_ins
), '\0', sizeof (the_ins
));
3089 for (n
= 0; n
< the_ins
.numargs
; n
++)
3090 if (the_ins
.operands
[n
].error
)
3092 er
= the_ins
.operands
[n
].error
;
3098 as_bad ("%s -- statement `%s' ignored", er
, str
);
3102 if (the_ins
.nfrag
== 0)
3104 /* No frag hacking involved; just put it out */
3105 toP
= frag_more (2 * the_ins
.numo
);
3106 fromP
= &the_ins
.opcode
[0];
3107 for (m
= the_ins
.numo
; m
; --m
)
3109 md_number_to_chars (toP
, (long) (*fromP
), 2);
3113 /* put out symbol-dependent info */
3114 for (m
= 0; m
< the_ins
.nrel
; m
++)
3116 switch (the_ins
.reloc
[m
].wid
)
3134 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3135 the_ins
.reloc
[m
].wid
);
3138 fixP
= fix_new_exp (frag_now
,
3139 ((toP
- frag_now
->fr_literal
)
3140 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3142 &the_ins
.reloc
[m
].exp
,
3143 the_ins
.reloc
[m
].pcrel
,
3144 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
3145 the_ins
.reloc
[m
].pic_reloc
));
3146 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3151 /* There's some frag hacking */
3152 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
3157 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
3159 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3160 toP
= frag_more (wid
);
3162 shorts_this_frag
= 0;
3163 for (m
= wid
/ 2; m
; --m
)
3165 md_number_to_chars (toP
, (long) (*fromP
), 2);
3170 for (m
= 0; m
< the_ins
.nrel
; m
++)
3172 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
3174 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
3177 wid
= the_ins
.reloc
[m
].wid
;
3180 the_ins
.reloc
[m
].wid
= 0;
3181 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3183 fixP
= fix_new_exp (frag_now
,
3184 ((toP
- frag_now
->fr_literal
)
3185 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3187 &the_ins
.reloc
[m
].exp
,
3188 the_ins
.reloc
[m
].pcrel
,
3189 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
3190 the_ins
.reloc
[m
].pic_reloc
));
3191 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3193 (void) frag_var (rs_machine_dependent
, 10, 0,
3194 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
3195 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
3197 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3198 shorts_this_frag
= 0;
3201 toP
= frag_more (n
* sizeof (short));
3204 md_number_to_chars (toP
, (long) (*fromP
), 2);
3210 for (m
= 0; m
< the_ins
.nrel
; m
++)
3214 wid
= the_ins
.reloc
[m
].wid
;
3217 the_ins
.reloc
[m
].wid
= 0;
3218 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3220 fixP
= fix_new_exp (frag_now
,
3221 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
3222 - shorts_this_frag
* 2),
3224 &the_ins
.reloc
[m
].exp
,
3225 the_ins
.reloc
[m
].pcrel
,
3226 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
3227 the_ins
.reloc
[m
].pic_reloc
));
3228 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3236 * md_begin -- set up hash tables with 68000 instructions.
3237 * similar to what the vax assembler does. ---phr
3239 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3240 a copy of it at runtime, adding in the information we want but isn't
3241 there. I think it'd be better to have an awk script hack the table
3242 at compile time. Or even just xstr the table and use it as-is. But
3243 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3246 register const struct m68k_opcode
*ins
;
3247 register struct m68k_incant
*hack
, *slak
;
3248 register const char *retval
= 0; /* empty string, or error msg text */
3249 register unsigned int i
;
3254 flag_reg_prefix_optional
= 1;
3259 op_hash
= hash_new ();
3261 obstack_begin (&robyn
, 4000);
3262 for (i
= 0; i
< m68k_numopcodes
; i
++)
3264 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3267 ins
= &m68k_opcodes
[i
];
3268 /* We *could* ignore insns that don't match our arch here
3269 but just leaving them out of the hash. */
3270 slak
->m_operands
= ins
->args
;
3271 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
3272 slak
->m_arch
= ins
->arch
;
3273 slak
->m_opcode
= ins
->opcode
;
3274 /* This is kludgey */
3275 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
3276 if (i
+ 1 != m68k_numopcodes
3277 && !strcmp (ins
->name
, m68k_opcodes
[i
+ 1].name
))
3279 slak
->m_next
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3284 slak
= slak
->m_next
;
3288 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
3290 as_fatal ("Internal Error: Can't hash %s: %s", ins
->name
, retval
);
3293 for (i
= 0; i
< m68k_numaliases
; i
++)
3295 const char *name
= m68k_opcode_aliases
[i
].primary
;
3296 const char *alias
= m68k_opcode_aliases
[i
].alias
;
3297 PTR val
= hash_find (op_hash
, name
);
3299 as_fatal ("Internal Error: Can't find %s in hash table", name
);
3300 retval
= hash_insert (op_hash
, alias
, val
);
3302 as_fatal ("Internal Error: Can't hash %s: %s", alias
, retval
);
3305 /* In MRI mode, all unsized branches are variable sized. Normally,
3306 they are word sized. */
3309 static struct m68k_opcode_alias mri_aliases
[] =
3329 for (i
= 0; i
< sizeof mri_aliases
/ sizeof mri_aliases
[0]; i
++)
3331 const char *name
= mri_aliases
[i
].primary
;
3332 const char *alias
= mri_aliases
[i
].alias
;
3333 PTR val
= hash_find (op_hash
, name
);
3335 as_fatal ("Internal Error: Can't find %s in hash table", name
);
3336 retval
= hash_jam (op_hash
, alias
, val
);
3338 as_fatal ("Internal Error: Can't hash %s: %s", alias
, retval
);
3342 for (i
= 0; i
< sizeof (mklower_table
); i
++)
3343 mklower_table
[i
] = (isupper (c
= (char) i
)) ? tolower (c
) : c
;
3345 for (i
= 0; i
< sizeof (notend_table
); i
++)
3347 notend_table
[i
] = 0;
3348 alt_notend_table
[i
] = 0;
3350 notend_table
[','] = 1;
3351 notend_table
['{'] = 1;
3352 notend_table
['}'] = 1;
3353 alt_notend_table
['a'] = 1;
3354 alt_notend_table
['A'] = 1;
3355 alt_notend_table
['d'] = 1;
3356 alt_notend_table
['D'] = 1;
3357 alt_notend_table
['#'] = 1;
3358 alt_notend_table
['&'] = 1;
3359 alt_notend_table
['f'] = 1;
3360 alt_notend_table
['F'] = 1;
3361 #ifdef REGISTER_PREFIX
3362 alt_notend_table
[REGISTER_PREFIX
] = 1;
3365 /* We need to put '(' in alt_notend_table to handle
3366 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3368 alt_notend_table
['('] = 1;
3370 /* We need to put '@' in alt_notend_table to handle
3371 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3373 alt_notend_table
['@'] = 1;
3375 #ifndef MIT_SYNTAX_ONLY
3376 /* Insert pseudo ops, these have to go into the opcode table since
3377 gas expects pseudo ops to start with a dot */
3380 while (mote_pseudo_table
[n
].poc_name
)
3382 hack
= (struct m68k_incant
*)
3383 obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3384 hash_insert (op_hash
,
3385 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
3386 hack
->m_operands
= 0;
3396 record_alignment (text_section
, 2);
3397 record_alignment (data_section
, 2);
3398 record_alignment (bss_section
, 2);
3403 m68k_init_after_args ()
3405 if (cpu_of_arch (current_architecture
) == 0)
3408 const char *default_cpu
= TARGET_CPU
;
3410 if (*default_cpu
== 'm')
3412 for (i
= 0; i
< n_archs
; i
++)
3413 if (strcasecmp (default_cpu
, archs
[i
].name
) == 0)
3417 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU
);
3418 current_architecture
|= m68020
;
3421 current_architecture
|= archs
[i
].arch
;
3423 /* Permit m68881 specification with all cpus; those that can't work
3424 with a coprocessor could be doing emulation. */
3425 if (current_architecture
& m68851
)
3427 if (current_architecture
& m68040
)
3429 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3432 /* What other incompatibilities could we check for? */
3434 /* Toss in some default assumptions about coprocessors. */
3436 && (cpu_of_arch (current_architecture
)
3437 /* Can CPU32 have a 68881 coprocessor?? */
3438 & (m68020
| m68030
| cpu32
)))
3440 current_architecture
|= m68881
;
3443 && (cpu_of_arch (current_architecture
) & m68020up
) != 0
3444 && (cpu_of_arch (current_architecture
) & m68040up
) == 0)
3446 current_architecture
|= m68851
;
3448 if (no_68881
&& (current_architecture
& m68881
))
3449 as_bad ("options for 68881 and no-68881 both given");
3450 if (no_68851
&& (current_architecture
& m68851
))
3451 as_bad ("options for 68851 and no-68851 both given");
3454 /* Work out the magic number. This isn't very general. */
3455 if (current_architecture
& m68000
)
3456 m68k_aout_machtype
= 0;
3457 else if (current_architecture
& m68010
)
3458 m68k_aout_machtype
= 1;
3459 else if (current_architecture
& m68020
)
3460 m68k_aout_machtype
= 2;
3462 m68k_aout_machtype
= 2;
3465 /* Note which set of "movec" control registers is available. */
3466 switch (cpu_of_arch (current_architecture
))
3469 control_regs
= m68000_control_regs
;
3472 control_regs
= m68010_control_regs
;
3476 control_regs
= m68020_control_regs
;
3479 control_regs
= m68040_control_regs
;
3482 control_regs
= m68060_control_regs
;
3485 control_regs
= cpu32_control_regs
;
3491 if (cpu_of_arch (current_architecture
) < m68020
)
3492 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
3495 /* This is called if we go in or out of MRI mode because of the .mri
3499 m68k_mri_mode_change (on
)
3504 if (! flag_reg_prefix_optional
)
3506 flag_reg_prefix_optional
= 1;
3507 #ifdef REGISTER_PREFIX
3516 if (! reg_prefix_optional_seen
)
3518 #ifdef REGISTER_PREFIX_OPTIONAL
3519 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
3521 flag_reg_prefix_optional
= 0;
3523 #ifdef REGISTER_PREFIX
3532 /* Equal to MAX_PRECISION in atof-ieee.c */
3533 #define MAX_LITTLENUMS 6
3535 /* Turn a string in input_line_pointer into a floating point constant
3536 of type type, and store the appropriate bytes in *litP. The number
3537 of LITTLENUMS emitted is stored in *sizeP . An error message is
3538 returned, or NULL on OK. */
3541 md_atof (type
, litP
, sizeP
)
3547 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3548 LITTLENUM_TYPE
*wordP
;
3580 return "Bad call to MD_ATOF()";
3582 t
= atof_ieee (input_line_pointer
, type
, words
);
3584 input_line_pointer
= t
;
3586 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
3587 for (wordP
= words
; prec
--;)
3589 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
3590 litP
+= sizeof (LITTLENUM_TYPE
);
3596 md_number_to_chars (buf
, val
, n
)
3601 number_to_chars_bigendian (buf
, val
, n
);
3605 md_apply_fix_2 (fixP
, val
)
3609 addressT upper_limit
;
3610 offsetT lower_limit
;
3612 /* This is unnecessary but it convinces the native rs6000 compiler
3613 to generate the code we want. */
3614 char *buf
= fixP
->fx_frag
->fr_literal
;
3615 buf
+= fixP
->fx_where
;
3616 /* end ibm compiler workaround */
3618 if (val
& 0x80000000)
3619 val
|= ~(addressT
)0x7fffffff;
3626 memset (buf
, 0, fixP
->fx_size
);
3627 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc */
3632 switch (fixP
->fx_size
)
3634 /* The cast to offsetT below are necessary to make code correct for
3635 machines where ints are smaller than offsetT */
3639 lower_limit
= - (offsetT
) 0x80;
3642 *buf
++ = (val
>> 8);
3644 upper_limit
= 0x7fff;
3645 lower_limit
= - (offsetT
) 0x8000;
3648 *buf
++ = (val
>> 24);
3649 *buf
++ = (val
>> 16);
3650 *buf
++ = (val
>> 8);
3652 upper_limit
= 0x7fffffff;
3653 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* avoid constant overflow */
3656 BAD_CASE (fixP
->fx_size
);
3659 /* Fix up a negative reloc. */
3660 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
3662 fixP
->fx_addsy
= fixP
->fx_subsy
;
3663 fixP
->fx_subsy
= NULL
;
3667 /* For non-pc-relative values, it's conceivable we might get something
3668 like "0xff" for a byte field. So extend the upper part of the range
3669 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3670 so that we can do any range checking at all. */
3671 if (!fixP
->fx_pcrel
)
3672 upper_limit
= upper_limit
* 2 + 1;
3674 if ((addressT
) val
> upper_limit
3675 && (val
> 0 || val
< lower_limit
))
3676 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "value out of range");
3678 /* A one byte PC-relative reloc means a short branch. We can't use
3679 a short branch with a value of 0 or -1, because those indicate
3680 different opcodes (branches with longer offsets). */
3682 && fixP
->fx_size
== 1
3683 && (fixP
->fx_addsy
== NULL
3684 || S_IS_DEFINED (fixP
->fx_addsy
))
3685 && (val
== 0 || val
== -1))
3686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "invalid byte branch offset");
3689 #ifdef BFD_ASSEMBLER
3691 md_apply_fix (fixP
, valp
)
3695 md_apply_fix_2 (fixP
, (addressT
) *valp
);
3699 void md_apply_fix (fixP
, val
)
3703 md_apply_fix_2 (fixP
, (addressT
) val
);
3707 /* *fragP has been relaxed to its final size, and now needs to have
3708 the bytes inside it modified to conform to the new size There is UGLY
3712 md_convert_frag_1 (fragP
)
3713 register fragS
*fragP
;
3719 /* Address in object code of the displacement. */
3720 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
3722 /* Address in gas core of the place to store the displacement. */
3723 /* This convinces the native rs6000 compiler to generate the code we
3725 register char *buffer_address
= fragP
->fr_literal
;
3726 buffer_address
+= fragP
->fr_fix
;
3727 /* end ibm compiler workaround */
3729 /* The displacement of the address, from current location. */
3730 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
3731 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
3733 #ifdef BFD_ASSEMBLER
3734 disp
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
3737 switch (fragP
->fr_subtype
)
3739 case TAB (BCC68000
, BYTE
):
3740 case TAB (ABRANCH
, BYTE
):
3741 know (issbyte (disp
));
3743 as_bad ("short branch with zero offset: use :w");
3744 fragP
->fr_opcode
[1] = disp
;
3747 case TAB (DBCC
, SHORT
):
3748 know (issword (disp
));
3751 case TAB (BCC68000
, SHORT
):
3752 case TAB (ABRANCH
, SHORT
):
3753 know (issword (disp
));
3754 fragP
->fr_opcode
[1] = 0x00;
3757 case TAB (ABRANCH
, LONG
):
3758 if (cpu_of_arch (current_architecture
) < m68020
)
3760 if (fragP
->fr_opcode
[0] == 0x61)
3763 fragP
->fr_opcode
[0] = 0x4E;
3764 fragP
->fr_opcode
[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3778 else if (fragP
->fr_opcode
[0] == 0x60)
3780 fragP
->fr_opcode
[0] = 0x4E;
3781 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3782 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
3783 fragP
->fr_offset
, 0, NO_RELOC
);
3789 as_bad ("Long branch offset not supported.");
3794 fragP
->fr_opcode
[1] = (char) 0xff;
3798 case TAB (BCC68000
, LONG
):
3799 /* only Bcc 68000 instructions can come here */
3800 /* change bcc into b!cc/jmp absl long */
3801 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
3802 fragP
->fr_opcode
[1] = 0x6;/* branch offset = 6 */
3804 /* JF: these used to be fr_opcode[2,3], but they may be in a
3805 different frag, in which case refering to them is a no-no.
3806 Only fr_opcode[0,1] are guaranteed to work. */
3807 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
3808 *buffer_address
++ = (char) 0xf9;
3809 fragP
->fr_fix
+= 2; /* account for jmp instruction */
3810 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
3811 fragP
->fr_offset
, 0, NO_RELOC
);
3815 case TAB (DBCC
, LONG
):
3816 /* only DBcc 68000 instructions can come here */
3817 /* change dbcc into dbcc/jmp absl long */
3818 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3819 *buffer_address
++ = 0x00; /* branch offset = 4 */
3820 *buffer_address
++ = 0x04;
3821 *buffer_address
++ = 0x60; /* put in bra pc+6 */
3822 *buffer_address
++ = 0x06;
3823 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
3824 *buffer_address
++ = (char) 0xf9;
3826 fragP
->fr_fix
+= 6; /* account for bra/jmp instructions */
3827 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
3828 fragP
->fr_offset
, 0, NO_RELOC
);
3832 case TAB (FBRANCH
, SHORT
):
3833 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
3836 case TAB (FBRANCH
, LONG
):
3837 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit */
3840 case TAB (PCREL
, SHORT
):
3843 case TAB (PCREL
, LONG
):
3844 /* The thing to do here is force it to ABSOLUTE LONG, since
3845 PCREL is really trying to shorten an ABSOLUTE address anyway */
3846 /* JF FOO This code has not been tested */
3847 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
3849 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
3850 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3851 (unsigned) fragP
->fr_opcode
[0],
3852 (unsigned long) fragP
->fr_address
);
3853 fragP
->fr_opcode
[1] &= ~0x3F;
3854 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
3858 case TAB (PCLEA
, SHORT
):
3859 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
3860 fragP
->fr_offset
, 1, NO_RELOC
);
3861 fragP
->fr_opcode
[1] &= ~0x3F;
3862 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
3865 case TAB (PCLEA
, LONG
):
3866 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
) + 2, 4, fragP
->fr_symbol
,
3867 fragP
->fr_offset
, 1, NO_RELOC
);
3868 fixP
->fx_pcrel_adjust
= 2;
3869 /* Already set to mode 7.3; this indicates: PC indirect with
3870 suppressed index, 32-bit displacement. */
3871 *buffer_address
++ = 0x01;
3872 *buffer_address
++ = 0x70;
3877 case TAB (PCINDEX
, BYTE
):
3879 if (!issbyte (disp
))
3881 as_bad ("displacement doesn't fit in one byte");
3884 assert (fragP
->fr_fix
>= 2);
3885 buffer_address
[-2] &= ~1;
3886 buffer_address
[-1] = disp
;
3889 case TAB (PCINDEX
, SHORT
):
3891 assert (issword (disp
));
3892 assert (fragP
->fr_fix
>= 2);
3893 buffer_address
[-2] |= 0x1;
3894 buffer_address
[-1] = 0x20;
3895 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
3896 fragP
->fr_offset
, (fragP
->fr_opcode
[1] & 077) == 073,
3898 fixP
->fx_pcrel_adjust
= 2;
3901 case TAB (PCINDEX
, LONG
):
3903 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
3904 fragP
->fr_offset
, (fragP
->fr_opcode
[1] & 077) == 073,
3906 fixP
->fx_pcrel_adjust
= 2;
3907 assert (fragP
->fr_fix
>= 2);
3908 buffer_address
[-2] |= 0x1;
3909 buffer_address
[-1] = 0x30;
3916 md_number_to_chars (buffer_address
, (long) disp
, (int) ext
);
3917 fragP
->fr_fix
+= ext
;
3921 #ifndef BFD_ASSEMBLER
3924 md_convert_frag (headers
, sec
, fragP
)
3925 object_headers
*headers
;
3929 md_convert_frag_1 (fragP
);
3935 md_convert_frag (abfd
, sec
, fragP
)
3940 md_convert_frag_1 (fragP
);
3944 /* Force truly undefined symbols to their maximum size, and generally set up
3945 the frag list to be relaxed
3948 md_estimate_size_before_relax (fragP
, segment
)
3949 register fragS
*fragP
;
3953 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
3955 old_fix
= fragP
->fr_fix
;
3957 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3958 switch (fragP
->fr_subtype
)
3961 case TAB (ABRANCH
, SZ_UNDEF
):
3963 if ((fragP
->fr_symbol
!= NULL
) /* Not absolute */
3964 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
3966 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
3969 else if ((fragP
->fr_symbol
== 0) || (cpu_of_arch (current_architecture
) < m68020
))
3971 /* On 68000, or for absolute value, switch to abs long */
3972 /* FIXME, we should check abs val, pick short or long */
3973 if (fragP
->fr_opcode
[0] == 0x61)
3975 fragP
->fr_opcode
[0] = 0x4E;
3976 fragP
->fr_opcode
[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3977 fix_new (fragP
, fragP
->fr_fix
, 4,
3978 fragP
->fr_symbol
, fragP
->fr_offset
, 0, NO_RELOC
);
3982 else if (fragP
->fr_opcode
[0] == 0x60)
3984 fragP
->fr_opcode
[0] = 0x4E;
3985 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3986 fix_new (fragP
, fragP
->fr_fix
, 4,
3987 fragP
->fr_symbol
, fragP
->fr_offset
, 0, NO_RELOC
);
3993 as_warn ("Long branch offset to extern symbol not supported.");
3997 { /* Symbol is still undefined. Make it simple */
3998 fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
3999 fragP
->fr_offset
, 1, NO_RELOC
);
4001 fragP
->fr_opcode
[1] = (char) 0xff;
4007 } /* case TAB(ABRANCH,SZ_UNDEF) */
4009 case TAB (FBRANCH
, SZ_UNDEF
):
4011 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
|| flag_short_refs
)
4013 fragP
->fr_subtype
= TAB (FBRANCH
, SHORT
);
4018 fix_new (fragP
, (int) fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4019 fragP
->fr_offset
, 1, NO_RELOC
);
4021 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit */
4025 } /* TAB(FBRANCH,SZ_UNDEF) */
4027 case TAB (PCREL
, SZ_UNDEF
):
4029 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4031 || cpu_of_arch (current_architecture
) < m68020
)
4033 fragP
->fr_subtype
= TAB (PCREL
, SHORT
);
4038 fragP
->fr_subtype
= TAB (PCREL
, LONG
);
4042 } /* TAB(PCREL,SZ_UNDEF) */
4044 case TAB (BCC68000
, SZ_UNDEF
):
4046 if ((fragP
->fr_symbol
!= NULL
)
4047 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4049 fragP
->fr_subtype
= TAB (BCC68000
, BYTE
);
4052 /* only Bcc 68000 instructions can come here */
4053 /* change bcc into b!cc/jmp absl long */
4054 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
4055 if (flag_short_refs
)
4057 fragP
->fr_opcode
[1] = 0x04; /* branch offset = 6 */
4058 /* JF: these were fr_opcode[2,3] */
4059 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
4060 buffer_address
[1] = (char) 0xf8;
4061 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4062 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4063 fragP
->fr_offset
, 0, NO_RELOC
);
4068 fragP
->fr_opcode
[1] = 0x06; /* branch offset = 6 */
4069 /* JF: these were fr_opcode[2,3] */
4070 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
4071 buffer_address
[1] = (char) 0xf9;
4072 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4073 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4074 fragP
->fr_offset
, 0, NO_RELOC
);
4079 } /* case TAB(BCC68000,SZ_UNDEF) */
4081 case TAB (DBCC
, SZ_UNDEF
):
4083 if (fragP
->fr_symbol
!= NULL
&& S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4085 fragP
->fr_subtype
= TAB (DBCC
, SHORT
);
4089 /* only DBcc 68000 instructions can come here */
4090 /* change dbcc into dbcc/jmp absl long */
4091 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4092 buffer_address
[0] = 0x00; /* branch offset = 4 */
4093 buffer_address
[1] = 0x04;
4094 buffer_address
[2] = 0x60; /* put in bra pc + ... */
4096 if (flag_short_refs
)
4098 /* JF: these were fr_opcode[5-7] */
4099 buffer_address
[3] = 0x04; /* plus 4 */
4100 buffer_address
[4] = 0x4e; /* Put in Jump Word */
4101 buffer_address
[5] = (char) 0xf8;
4102 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
4103 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4104 fragP
->fr_offset
, 0, NO_RELOC
);
4109 /* JF: these were fr_opcode[5-7] */
4110 buffer_address
[3] = 0x06; /* Plus 6 */
4111 buffer_address
[4] = 0x4e; /* put in jmp long (0x4ef9) */
4112 buffer_address
[5] = (char) 0xf9;
4113 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
4114 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4115 fragP
->fr_offset
, 0, NO_RELOC
);
4121 } /* case TAB(DBCC,SZ_UNDEF) */
4123 case TAB (PCLEA
, SZ_UNDEF
):
4125 if ((S_GET_SEGMENT (fragP
->fr_symbol
)) == segment
4127 || cpu_of_arch (current_architecture
) < m68020
)
4129 fragP
->fr_subtype
= TAB (PCLEA
, SHORT
);
4134 fragP
->fr_subtype
= TAB (PCLEA
, LONG
);
4138 } /* TAB(PCLEA,SZ_UNDEF) */
4140 case TAB (PCINDEX
, SZ_UNDEF
):
4141 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4142 || cpu_of_arch (current_architecture
) < m68020
)
4144 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
4148 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
4157 /* now that SZ_UNDEF are taken care of, check others */
4158 switch (fragP
->fr_subtype
)
4160 case TAB (BCC68000
, BYTE
):
4161 case TAB (ABRANCH
, BYTE
):
4162 /* We can't do a short jump to the next instruction,
4163 so we force word mode. */
4164 if (fragP
->fr_symbol
&& S_GET_VALUE (fragP
->fr_symbol
) == 0 &&
4165 fragP
->fr_symbol
->sy_frag
== fragP
->fr_next
)
4167 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4174 return fragP
->fr_var
+ fragP
->fr_fix
- old_fix
;
4177 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4178 /* the bit-field entries in the relocation_info struct plays hell
4179 with the byte-order problems of cross-assembly. So as a hack,
4180 I added this mach. dependent ri twiddler. Ugly, but it gets
4182 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4183 are symbolnum, most sig. byte first. Last byte is broken up with
4184 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4185 nibble as nuthin. (on Sun 3 at least) */
4186 /* Translate the internal relocation information into target-specific
4190 md_ri_to_chars (the_bytes
, ri
)
4192 struct reloc_info_generic
*ri
;
4195 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
4196 /* now the fun stuff */
4197 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
4198 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
4199 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
4200 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80) | ((ri
->r_length
<< 5) & 0x60) |
4201 ((ri
->r_extern
<< 4) & 0x10));
4204 #endif /* comment */
4206 #ifndef BFD_ASSEMBLER
4208 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4211 relax_addressT segment_address_in_file
;
4214 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4215 * Out: GNU LD relocation length code: 0, 1, or 2.
4218 static CONST
unsigned char nbytes_r_length
[] = {42, 0, 1, 42, 2};
4221 know (fixP
->fx_addsy
!= NULL
);
4223 md_number_to_chars (where
,
4224 fixP
->fx_frag
->fr_address
+ fixP
->fx_where
- segment_address_in_file
,
4227 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4228 ? S_GET_TYPE (fixP
->fx_addsy
)
4229 : fixP
->fx_addsy
->sy_number
);
4231 where
[4] = (r_symbolnum
>> 16) & 0x0ff;
4232 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4233 where
[6] = r_symbolnum
& 0x0ff;
4234 where
[7] = (((fixP
->fx_pcrel
<< 7) & 0x80) | ((nbytes_r_length
[fixP
->fx_size
] << 5) & 0x60) |
4235 (((!S_IS_DEFINED (fixP
->fx_addsy
)) << 4) & 0x10));
4239 #endif /* OBJ_AOUT or OBJ_BOUT */
4241 #ifndef WORKING_DOT_WORD
4242 CONST
int md_short_jump_size
= 4;
4243 CONST
int md_long_jump_size
= 6;
4246 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4248 addressT from_addr
, to_addr
;
4254 offset
= to_addr
- (from_addr
+ 2);
4256 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
4257 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
4261 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4263 addressT from_addr
, to_addr
;
4269 if (cpu_of_arch (current_architecture
) < m68020
)
4271 offset
= to_addr
- S_GET_VALUE (to_symbol
);
4272 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
4273 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4274 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
4279 offset
= to_addr
- (from_addr
+ 2);
4280 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
4281 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4287 /* Different values of OK tell what its OK to return. Things that
4288 aren't OK are an error (what a shock, no?)
4291 10: Absolute 1:8 only
4292 20: Absolute 0:7 only
4293 30: absolute 0:15 only
4294 40: Absolute 0:31 only
4295 50: absolute 0:127 only
4296 55: absolute -64:63 only
4297 60: absolute -128:127 only
4298 70: absolute 0:4095 only
4305 struct m68k_exp
*exp
;
4308 if (exp
->exp
.X_op
== O_absent
)
4310 /* Do the same thing the VAX asm does */
4311 op (exp
) = O_constant
;
4317 as_warn ("expression out of range: defaulting to 1");
4321 else if (exp
->exp
.X_op
== O_constant
)
4326 if (offs (exp
) < 1 || offs (exp
) > 8)
4328 as_warn ("expression out of range: defaulting to 1");
4333 if (offs (exp
) < 0 || offs (exp
) > 7)
4337 if (offs (exp
) < 0 || offs (exp
) > 15)
4341 if (offs (exp
) < 0 || offs (exp
) > 32)
4345 if (offs (exp
) < 0 || offs (exp
) > 127)
4349 if (offs (exp
) < -64 || offs (exp
) > 63)
4353 if (offs (exp
) < -128 || offs (exp
) > 127)
4357 if (offs (exp
) < 0 || offs (exp
) > 4095)
4360 as_warn ("expression out of range: defaulting to 0");
4368 else if (exp
->exp
.X_op
== O_big
)
4370 if (offs (exp
) <= 0 /* flonum */
4371 && (ok
== 80 /* no bignums */
4372 || (ok
> 10 /* small-int ranges including 0 ok */
4373 /* If we have a flonum zero, a zero integer should
4374 do as well (e.g., in moveq). */
4375 && generic_floating_point_number
.exponent
== 0
4376 && generic_floating_point_number
.low
[0] == 0)))
4378 /* HACK! Turn it into a long */
4379 LITTLENUM_TYPE words
[6];
4381 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
4382 op (exp
) = O_constant
;
4385 offs (exp
) = words
[1] | (words
[0] << 16);
4389 op (exp
) = O_constant
;
4392 offs (exp
) = (ok
== 10) ? 1 : 0;
4393 as_warn ("Can't deal with expression; defaulting to %ld",
4399 if (ok
>= 10 && ok
<= 70)
4401 op (exp
) = O_constant
;
4404 offs (exp
) = (ok
== 10) ? 1 : 0;
4405 as_warn ("Can't deal with expression; defaulting to %ld",
4410 if (exp
->size
!= SIZE_UNSPEC
)
4418 if (!isbyte (offs (exp
)))
4419 as_warn ("expression doesn't fit in BYTE");
4422 if (!isword (offs (exp
)))
4423 as_warn ("expression doesn't fit in WORD");
4431 /* These are the back-ends for the various machine dependent pseudo-ops. */
4432 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4438 subseg_set (data_section
, 1);
4439 demand_empty_rest_of_line ();
4446 subseg_set (data_section
, 2);
4447 demand_empty_rest_of_line ();
4454 /* We don't support putting frags in the BSS segment, we fake it
4455 by marking in_bss, then looking at s_skip for clues. */
4457 subseg_set (bss_section
, 0);
4458 demand_empty_rest_of_line ();
4466 register long temp_fill
;
4468 temp
= 1; /* JF should be 2? */
4469 temp_fill
= get_absolute_expression ();
4470 if (!need_pass_2
) /* Never make frag if expect extra pass. */
4471 frag_align (temp
, (int) temp_fill
);
4472 demand_empty_rest_of_line ();
4479 demand_empty_rest_of_line ();
4482 /* Pseudo-ops handled for MRI compatibility. */
4484 /* Handle an MRI style chip specification. */
4493 s
= input_line_pointer
;
4494 c
= get_symbol_end ();
4495 for (i
= 0; i
< n_archs
; i
++)
4496 if (strcasecmp (s
, archs
[i
].name
) == 0)
4500 as_bad ("%s: unrecognized processor name", s
);
4501 *input_line_pointer
= c
;
4502 ignore_rest_of_line ();
4505 *input_line_pointer
= c
;
4507 if (*input_line_pointer
== '/')
4508 current_architecture
= 0;
4510 current_architecture
&= m68881
| m68851
;
4511 current_architecture
|= archs
[i
].arch
;
4513 while (*input_line_pointer
== '/')
4515 ++input_line_pointer
;
4516 s
= input_line_pointer
;
4517 c
= get_symbol_end ();
4518 if (strcmp (s
, "68881") == 0)
4519 current_architecture
|= m68881
;
4520 else if (strcmp (s
, "68851") == 0)
4521 current_architecture
|= m68851
;
4522 *input_line_pointer
= c
;
4526 /* The MRI CHIP pseudo-op. */
4536 stop
= mri_comment_field (&stopc
);
4539 mri_comment_end (stop
, stopc
);
4540 demand_empty_rest_of_line ();
4543 /* The MRI FOPT pseudo-op. */
4551 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
4555 input_line_pointer
+= 3;
4556 temp
= get_absolute_expression ();
4557 if (temp
< 0 || temp
> 7)
4558 as_bad ("bad coprocessor id");
4560 m68k_float_copnum
= COP0
+ temp
;
4564 as_bad ("unrecognized fopt option");
4565 ignore_rest_of_line ();
4569 demand_empty_rest_of_line ();
4572 /* The structure used to handle the MRI OPT pseudo-op. */
4576 /* The name of the option. */
4579 /* If this is not NULL, just call this function. The first argument
4580 is the ARG field of this structure, the second argument is
4581 whether the option was negated. */
4582 void (*pfn
) PARAMS ((int arg
, int on
));
4584 /* If this is not NULL, and the PFN field is NULL, set the variable
4585 this points to. Set it to the ARG field if the option was not
4586 negated, and the NOTARG field otherwise. */
4589 /* The value to pass to PFN or to assign to *PVAR. */
4592 /* The value to assign to *PVAR if the option is negated. If PFN is
4593 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4594 the option may not be negated. */
4598 /* The table used to handle the MRI OPT pseudo-op. */
4600 static void skip_to_comma
PARAMS ((int, int));
4601 static void opt_nest
PARAMS ((int, int));
4602 static void opt_chip
PARAMS ((int, int));
4603 static void opt_list
PARAMS ((int, int));
4604 static void opt_list_symbols
PARAMS ((int, int));
4606 static const struct opt_action opt_table
[] =
4608 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
4610 /* We do relaxing, so there is little use for these options. */
4611 { "b", 0, 0, 0, 0 },
4612 { "brs", 0, 0, 0, 0 },
4613 { "brb", 0, 0, 0, 0 },
4614 { "brl", 0, 0, 0, 0 },
4615 { "brw", 0, 0, 0, 0 },
4617 { "c", 0, 0, 0, 0 },
4618 { "cex", 0, 0, 0, 0 },
4619 { "case", 0, &symbols_case_sensitive
, 1, 0 },
4620 { "cl", 0, 0, 0, 0 },
4621 { "cre", 0, 0, 0, 0 },
4622 { "d", 0, &flag_keep_locals
, 1, 0 },
4623 { "e", 0, 0, 0, 0 },
4624 { "f", 0, &flag_short_refs
, 1, 0 },
4625 { "frs", 0, &flag_short_refs
, 1, 0 },
4626 { "frl", 0, &flag_short_refs
, 0, 1 },
4627 { "g", 0, 0, 0, 0 },
4628 { "i", 0, 0, 0, 0 },
4629 { "m", 0, 0, 0, 0 },
4630 { "mex", 0, 0, 0, 0 },
4631 { "mc", 0, 0, 0, 0 },
4632 { "md", 0, 0, 0, 0 },
4633 { "nest", opt_nest
, 0, 0, 0 },
4634 { "next", skip_to_comma
, 0, 0, 0 },
4635 { "o", 0, 0, 0, 0 },
4636 { "old", 0, 0, 0, 0 },
4637 { "op", skip_to_comma
, 0, 0, 0 },
4638 { "pco", 0, 0, 0, 0 },
4639 { "p", opt_chip
, 0, 0, 0 },
4640 { "pcr", 0, 0, 0, 0 },
4641 { "pcs", 0, 0, 0, 0 },
4642 { "r", 0, 0, 0, 0 },
4643 { "quick", 0, &m68k_quick
, 1, 0 },
4644 { "rel32", 0, &m68k_rel32
, 1, 0 },
4645 { "s", opt_list
, 0, 0, 0 },
4646 { "t", opt_list_symbols
, 0, 0, 0 },
4647 { "w", 0, &flag_no_warnings
, 0, 1 },
4651 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4653 /* The MRI OPT pseudo-op. */
4665 const struct opt_action
*o
;
4670 if (*input_line_pointer
== '-')
4672 ++input_line_pointer
;
4675 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
4677 input_line_pointer
+= 2;
4681 s
= input_line_pointer
;
4682 c
= get_symbol_end ();
4684 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
4686 if (strcasecmp (s
, o
->name
) == 0)
4690 /* Restore input_line_pointer now in case the option
4692 *input_line_pointer
= c
;
4693 (*o
->pfn
) (o
->arg
, t
);
4695 else if (o
->pvar
!= NULL
)
4697 if (! t
&& o
->arg
== o
->notarg
)
4698 as_bad ("option `%s' may not be negated", s
);
4699 *input_line_pointer
= c
;
4700 *o
->pvar
= t
? o
->arg
: o
->notarg
;
4703 *input_line_pointer
= c
;
4709 as_bad ("option `%s' not recognized", s
);
4710 *input_line_pointer
= c
;
4713 while (*input_line_pointer
++ == ',');
4715 /* Move back to terminating character. */
4716 --input_line_pointer
;
4717 demand_empty_rest_of_line ();
4720 /* Skip ahead to a comma. This is used for OPT options which we do
4721 not suppor tand which take arguments. */
4724 skip_to_comma (arg
, on
)
4728 while (*input_line_pointer
!= ','
4729 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
4730 ++input_line_pointer
;
4733 /* Handle the OPT NEST=depth option. */
4740 if (*input_line_pointer
!= '=')
4742 as_bad ("bad format of OPT NEST=depth");
4746 ++input_line_pointer
;
4747 max_macro_nest
= get_absolute_expression ();
4750 /* Handle the OPT P=chip option. */
4757 if (*input_line_pointer
!= '=')
4759 /* This is just OPT P, which we do not support. */
4763 ++input_line_pointer
;
4767 /* Handle the OPT S option. */
4777 /* Handle the OPT T option. */
4780 opt_list_symbols (arg
, on
)
4785 listing
|= LISTING_SYMBOLS
;
4787 listing
&=~ LISTING_SYMBOLS
;
4790 /* Handle the MRI REG pseudo-op. */
4803 if (line_label
== NULL
)
4805 as_bad ("missing label");
4806 ignore_rest_of_line ();
4811 stop
= mri_comment_field (&stopc
);
4815 s
= input_line_pointer
;
4816 while (isalnum ((unsigned char) *input_line_pointer
)
4817 #ifdef REGISTER_PREFIX
4818 || *input_line_pointer
== REGISTER_PREFIX
4820 || *input_line_pointer
== '/'
4821 || *input_line_pointer
== '-')
4822 ++input_line_pointer
;
4823 c
= *input_line_pointer
;
4824 *input_line_pointer
= '\0';
4826 if (m68k_ip_op (s
, &rop
) != 0)
4828 if (rop
.error
== NULL
)
4829 as_bad ("bad register list");
4831 as_bad ("bad register list: %s", rop
.error
);
4832 *input_line_pointer
= c
;
4833 ignore_rest_of_line ();
4837 *input_line_pointer
= c
;
4839 if (rop
.mode
== REGLST
)
4841 else if (rop
.mode
== DREG
)
4842 mask
= 1 << (rop
.reg
- DATA0
);
4843 else if (rop
.mode
== AREG
)
4844 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
4845 else if (rop
.mode
== FPREG
)
4846 mask
= 1 << (rop
.reg
- FP0
+ 16);
4847 else if (rop
.mode
== CONTROL
4850 else if (rop
.mode
== CONTROL
4853 else if (rop
.mode
== CONTROL
4858 as_bad ("bad register list");
4859 ignore_rest_of_line ();
4863 S_SET_SEGMENT (line_label
, absolute_section
);
4864 S_SET_VALUE (line_label
, mask
);
4865 line_label
->sy_frag
= &zero_address_frag
;
4868 mri_comment_end (stop
, stopc
);
4870 demand_empty_rest_of_line ();
4873 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4877 struct save_opts
*next
;
4879 int symbols_case_sensitive
;
4887 /* FIXME: We don't save OPT S. */
4890 /* This variable holds the stack of saved options. */
4892 static struct save_opts
*save_stack
;
4894 /* The MRI SAVE pseudo-op. */
4900 struct save_opts
*s
;
4902 s
= (struct save_opts
*) xmalloc (sizeof (struct save_opts
));
4903 s
->abspcadd
= m68k_abspcadd
;
4904 s
->symbols_case_sensitive
= symbols_case_sensitive
;
4905 s
->keep_locals
= flag_keep_locals
;
4906 s
->short_refs
= flag_short_refs
;
4907 s
->architecture
= current_architecture
;
4908 s
->quick
= m68k_quick
;
4909 s
->rel32
= m68k_rel32
;
4910 s
->listing
= listing
;
4911 s
->no_warnings
= flag_no_warnings
;
4913 s
->next
= save_stack
;
4916 demand_empty_rest_of_line ();
4919 /* The MRI RESTORE pseudo-op. */
4925 struct save_opts
*s
;
4927 if (save_stack
== NULL
)
4929 as_bad ("restore without save");
4930 ignore_rest_of_line ();
4935 save_stack
= s
->next
;
4937 m68k_abspcadd
= s
->abspcadd
;
4938 symbols_case_sensitive
= s
->symbols_case_sensitive
;
4939 flag_keep_locals
= s
->keep_locals
;
4940 flag_short_refs
= s
->short_refs
;
4941 current_architecture
= s
->architecture
;
4942 m68k_quick
= s
->quick
;
4943 m68k_rel32
= s
->rel32
;
4944 listing
= s
->listing
;
4945 flag_no_warnings
= s
->no_warnings
;
4949 demand_empty_rest_of_line ();
4952 /* Types of MRI structured control directives. */
4954 enum mri_control_type
4962 /* This structure is used to stack the MRI structured control
4965 struct mri_control_info
4967 /* The directive within which this one is enclosed. */
4968 struct mri_control_info
*outer
;
4970 /* The type of directive. */
4971 enum mri_control_type type
;
4973 /* Whether an ELSE has been in an IF. */
4976 /* The add or sub statement at the end of a FOR. */
4979 /* The label of the top of a FOR or REPEAT loop. */
4982 /* The label to jump to for the next iteration, or the else
4983 expression of a conditional. */
4986 /* The label to jump to to break out of the loop, or the label past
4987 the end of a conditional. */
4991 /* The stack of MRI structured control directives. */
4993 static struct mri_control_info
*mri_control_stack
;
4995 /* The current MRI structured control directive index number, used to
4996 generate label names. */
4998 static int mri_control_index
;
5000 /* Some function prototypes. */
5002 static char *mri_control_label
PARAMS ((void));
5003 static struct mri_control_info
*push_mri_control
5004 PARAMS ((enum mri_control_type
));
5005 static void pop_mri_control
PARAMS ((void));
5006 static int parse_mri_condition
PARAMS ((int *));
5007 static int parse_mri_control_operand
5008 PARAMS ((int *, char **, char **, char **, char **));
5009 static int swap_mri_condition
PARAMS ((int));
5010 static int reverse_mri_condition
PARAMS ((int));
5011 static void build_mri_control_operand
5012 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5013 const char *, int));
5014 static void parse_mri_control_expression
5015 PARAMS ((char *, int, const char *, const char *, int));
5017 /* Generate a new MRI label structured control directive label name. */
5020 mri_control_label ()
5024 n
= (char *) xmalloc (20);
5025 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
5026 ++mri_control_index
;
5030 /* Create a new MRI structured control directive. */
5032 static struct mri_control_info
*
5033 push_mri_control (type
)
5034 enum mri_control_type type
;
5036 struct mri_control_info
*n
;
5038 n
= (struct mri_control_info
*) xmalloc (sizeof (struct mri_control_info
));
5042 if (type
== mri_if
|| type
== mri_while
)
5045 n
->top
= mri_control_label ();
5046 n
->next
= mri_control_label ();
5047 n
->bottom
= mri_control_label ();
5049 n
->outer
= mri_control_stack
;
5050 mri_control_stack
= n
;
5055 /* Pop off the stack of MRI structured control directives. */
5060 struct mri_control_info
*n
;
5062 n
= mri_control_stack
;
5063 mri_control_stack
= n
->outer
;
5071 /* Recognize a condition code in an MRI structured control expression. */
5074 parse_mri_condition (pcc
)
5079 know (*input_line_pointer
== '<');
5081 ++input_line_pointer
;
5082 c1
= *input_line_pointer
++;
5083 c2
= *input_line_pointer
++;
5085 if (*input_line_pointer
!= '>')
5087 as_bad ("syntax error in structured control directive");
5091 ++input_line_pointer
;
5099 *pcc
= (c1
<< 8) | c2
;
5104 /* Parse a single operand in an MRI structured control expression. */
5107 parse_mri_control_operand (pcc
, leftstart
, leftstop
, rightstart
, rightstop
)
5124 if (*input_line_pointer
== '<')
5126 /* It's just a condition code. */
5127 return parse_mri_condition (pcc
);
5130 /* Look ahead for the condition code. */
5131 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5133 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
5138 as_bad ("missing condition code in structured control directive");
5142 *leftstart
= input_line_pointer
;
5144 if (*leftstop
> *leftstart
5145 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
5148 input_line_pointer
= s
;
5149 if (! parse_mri_condition (pcc
))
5152 /* Look ahead for AND or OR or end of line. */
5153 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5155 if ((strncasecmp (s
, "AND", 3) == 0
5156 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
5157 || (strncasecmp (s
, "OR", 2) == 0
5158 && (s
[2] == '.' || ! is_part_of_name (s
[2]))))
5162 *rightstart
= input_line_pointer
;
5164 if (*rightstop
> *rightstart
5165 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
5168 input_line_pointer
= s
;
5173 #define MCC(b1, b2) (((b1) << 8) | (b2))
5175 /* Swap the sense of a condition. This changes the condition so that
5176 it generates the same result when the operands are swapped. */
5179 swap_mri_condition (cc
)
5184 case MCC ('h', 'i'): return MCC ('c', 's');
5185 case MCC ('l', 's'): return MCC ('c', 'c');
5186 case MCC ('c', 'c'): return MCC ('l', 's');
5187 case MCC ('c', 's'): return MCC ('h', 'i');
5188 case MCC ('p', 'l'): return MCC ('m', 'i');
5189 case MCC ('m', 'i'): return MCC ('p', 'l');
5190 case MCC ('g', 'e'): return MCC ('l', 'e');
5191 case MCC ('l', 't'): return MCC ('g', 't');
5192 case MCC ('g', 't'): return MCC ('l', 't');
5193 case MCC ('l', 'e'): return MCC ('g', 'e');
5198 /* Reverse the sense of a condition. */
5201 reverse_mri_condition (cc
)
5206 case MCC ('h', 'i'): return MCC ('l', 's');
5207 case MCC ('l', 's'): return MCC ('h', 'i');
5208 case MCC ('c', 'c'): return MCC ('c', 's');
5209 case MCC ('c', 's'): return MCC ('c', 'c');
5210 case MCC ('n', 'e'): return MCC ('e', 'q');
5211 case MCC ('e', 'q'): return MCC ('n', 'e');
5212 case MCC ('v', 'c'): return MCC ('v', 's');
5213 case MCC ('v', 's'): return MCC ('v', 'c');
5214 case MCC ('p', 'l'): return MCC ('m', 'i');
5215 case MCC ('m', 'i'): return MCC ('p', 'l');
5216 case MCC ('g', 'e'): return MCC ('l', 't');
5217 case MCC ('l', 't'): return MCC ('g', 'e');
5218 case MCC ('g', 't'): return MCC ('l', 'e');
5219 case MCC ('l', 'e'): return MCC ('g', 't');
5224 /* Build an MRI structured control expression. This generates test
5225 and branch instructions. It goes to TRUELAB if the condition is
5226 true, and to FALSELAB if the condition is false. Exactly one of
5227 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5228 is the size qualifier for the expression. EXTENT is the size to
5229 use for the branch. */
5232 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5233 rightstop
, truelab
, falselab
, extent
)
5240 const char *truelab
;
5241 const char *falselab
;
5247 if (leftstart
!= NULL
)
5249 struct m68k_op leftop
, rightop
;
5252 /* Swap the compare operands, if necessary, to produce a legal
5253 m68k compare instruction. Comparing a register operand with
5254 a non-register operand requires the register to be on the
5255 right (cmp, cmpa). Comparing an immediate value with
5256 anything requires the immediate value to be on the left
5261 (void) m68k_ip_op (leftstart
, &leftop
);
5266 (void) m68k_ip_op (rightstart
, &rightop
);
5269 if (rightop
.mode
== IMMED
5270 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
5271 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
5275 cc
= swap_mri_condition (cc
);
5277 leftstart
= rightstart
;
5280 leftstop
= rightstop
;
5285 if (truelab
== NULL
)
5287 cc
= reverse_mri_condition (cc
);
5291 if (leftstart
!= NULL
)
5293 buf
= (char *) xmalloc (20
5294 + (leftstop
- leftstart
)
5295 + (rightstop
- rightstart
));
5303 memcpy (s
, leftstart
, leftstop
- leftstart
);
5304 s
+= leftstop
- leftstart
;
5306 memcpy (s
, rightstart
, rightstop
- rightstart
);
5307 s
+= rightstop
- rightstart
;
5313 buf
= (char *) xmalloc (20 + strlen (truelab
));
5321 strcpy (s
, truelab
);
5326 /* Parse an MRI structured control expression. This generates test
5327 and branch instructions. STOP is where the expression ends. It
5328 goes to TRUELAB if the condition is true, and to FALSELAB if the
5329 condition is false. Exactly one of TRUELAB and FALSELAB will be
5330 NULL, meaning to fall through. QUAL is the size qualifier for the
5331 expression. EXTENT is the size to use for the branch. */
5334 parse_mri_control_expression (stop
, qual
, truelab
, falselab
, extent
)
5337 const char *truelab
;
5338 const char *falselab
;
5351 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
5352 &rightstart
, &rightstop
))
5358 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
5362 if (falselab
!= NULL
)
5365 flab
= mri_control_label ();
5367 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5368 rightstop
, (const char *) NULL
, flab
, extent
);
5370 input_line_pointer
+= 3;
5371 if (*input_line_pointer
!= '.'
5372 || input_line_pointer
[1] == '\0')
5376 qual
= input_line_pointer
[1];
5377 input_line_pointer
+= 2;
5380 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
5381 &rightstart
, &rightstop
))
5387 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5388 rightstop
, truelab
, falselab
, extent
);
5390 if (falselab
== NULL
)
5393 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
5397 if (truelab
!= NULL
)
5400 tlab
= mri_control_label ();
5402 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5403 rightstop
, tlab
, (const char *) NULL
, extent
);
5405 input_line_pointer
+= 2;
5406 if (*input_line_pointer
!= '.'
5407 || input_line_pointer
[1] == '\0')
5411 qual
= input_line_pointer
[1];
5412 input_line_pointer
+= 2;
5415 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
5416 &rightstart
, &rightstop
))
5422 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5423 rightstop
, truelab
, falselab
, extent
);
5425 if (truelab
== NULL
)
5430 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
5431 rightstop
, truelab
, falselab
, extent
);
5435 if (input_line_pointer
!= stop
)
5436 as_bad ("syntax error in structured control directive");
5439 /* Handle the MRI IF pseudo-op. This may be a structured control
5440 directive, or it may be a regular assembler conditional, depending
5449 struct mri_control_info
*n
;
5451 /* A structured control directive must end with THEN with an
5452 optional qualifier. */
5453 s
= input_line_pointer
;
5454 while (! is_end_of_line
[(unsigned char) *s
]
5455 && (! flag_mri
|| *s
!= '*'))
5458 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
5461 if (s
- input_line_pointer
> 1
5465 if (s
- input_line_pointer
< 3
5466 || strncasecmp (s
- 3, "THEN", 4) != 0)
5470 as_bad ("missing then");
5471 ignore_rest_of_line ();
5475 /* It's a conditional. */
5480 /* Since this might be a conditional if, this pseudo-op will be
5481 called even if we are supported to be ignoring input. Double
5482 check now. Clobber *input_line_pointer so that ignore_input
5483 thinks that this is not a special pseudo-op. */
5484 c
= *input_line_pointer
;
5485 *input_line_pointer
= 0;
5486 if (ignore_input ())
5488 *input_line_pointer
= c
;
5489 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5490 ++input_line_pointer
;
5491 demand_empty_rest_of_line ();
5494 *input_line_pointer
= c
;
5496 n
= push_mri_control (mri_if
);
5498 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
5499 n
->next
, s
[1] == '.' ? s
[2] : '\0');
5502 input_line_pointer
= s
+ 3;
5504 input_line_pointer
= s
+ 1;
5508 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5509 ++input_line_pointer
;
5512 demand_empty_rest_of_line ();
5515 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5516 structured IF, associate the ELSE with the IF. Otherwise, assume
5517 it is a conditional else. */
5528 && (mri_control_stack
== NULL
5529 || mri_control_stack
->type
!= mri_if
5530 || mri_control_stack
->else_seen
))
5536 c
= *input_line_pointer
;
5537 *input_line_pointer
= 0;
5538 if (ignore_input ())
5540 *input_line_pointer
= c
;
5541 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5542 ++input_line_pointer
;
5543 demand_empty_rest_of_line ();
5546 *input_line_pointer
= c
;
5548 if (mri_control_stack
== NULL
5549 || mri_control_stack
->type
!= mri_if
5550 || mri_control_stack
->else_seen
)
5552 as_bad ("else without matching if");
5553 ignore_rest_of_line ();
5557 mri_control_stack
->else_seen
= 1;
5559 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->bottom
));
5562 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
5566 colon (mri_control_stack
->next
);
5570 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5571 ++input_line_pointer
;
5574 demand_empty_rest_of_line ();
5577 /* Handle the MRI ENDI pseudo-op. */
5583 if (mri_control_stack
== NULL
5584 || mri_control_stack
->type
!= mri_if
)
5586 as_bad ("endi without matching if");
5587 ignore_rest_of_line ();
5591 /* ignore_input will not return true for ENDI, so we don't need to
5592 worry about checking it again here. */
5594 if (! mri_control_stack
->else_seen
)
5595 colon (mri_control_stack
->next
);
5596 colon (mri_control_stack
->bottom
);
5602 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5603 ++input_line_pointer
;
5606 demand_empty_rest_of_line ();
5609 /* Handle the MRI BREAK pseudo-op. */
5612 s_mri_break (extent
)
5615 struct mri_control_info
*n
;
5619 n
= mri_control_stack
;
5621 && n
->type
!= mri_for
5622 && n
->type
!= mri_repeat
5623 && n
->type
!= mri_while
)
5627 as_bad ("break outside of structured loop");
5628 ignore_rest_of_line ();
5632 buf
= (char *) xmalloc (20 + strlen (n
->bottom
));
5635 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
5641 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5642 ++input_line_pointer
;
5645 demand_empty_rest_of_line ();
5648 /* Handle the MRI NEXT pseudo-op. */
5654 struct mri_control_info
*n
;
5658 n
= mri_control_stack
;
5660 && n
->type
!= mri_for
5661 && n
->type
!= mri_repeat
5662 && n
->type
!= mri_while
)
5666 as_bad ("next outside of structured loop");
5667 ignore_rest_of_line ();
5671 buf
= (char *) xmalloc (20 + strlen (n
->next
));
5674 sprintf (buf
, "bra%s %s", ex
, n
->next
);
5680 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5681 ++input_line_pointer
;
5684 demand_empty_rest_of_line ();
5687 /* Handle the MRI FOR pseudo-op. */
5693 const char *varstart
, *varstop
;
5694 const char *initstart
, *initstop
;
5695 const char *endstart
, *endstop
;
5696 const char *bystart
, *bystop
;
5700 struct mri_control_info
*n
;
5706 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5710 varstart
= input_line_pointer
;
5712 /* Look for the '='. */
5713 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
5714 && *input_line_pointer
!= '=')
5715 ++input_line_pointer
;
5716 if (*input_line_pointer
!= '=')
5718 as_bad ("missing =");
5719 ignore_rest_of_line ();
5723 varstop
= input_line_pointer
;
5724 if (varstop
> varstart
5725 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
5728 ++input_line_pointer
;
5730 initstart
= input_line_pointer
;
5732 /* Look for TO or DOWNTO. */
5735 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5737 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
5738 && ! is_part_of_name (input_line_pointer
[2]))
5740 initstop
= input_line_pointer
;
5741 input_line_pointer
+= 2;
5744 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
5745 && ! is_part_of_name (input_line_pointer
[6]))
5747 initstop
= input_line_pointer
;
5749 input_line_pointer
+= 6;
5752 ++input_line_pointer
;
5754 if (initstop
== NULL
)
5756 as_bad ("missing to or downto");
5757 ignore_rest_of_line ();
5760 if (initstop
> initstart
5761 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
5765 endstart
= input_line_pointer
;
5767 /* Look for BY or DO. */
5770 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5772 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
5773 && ! is_part_of_name (input_line_pointer
[2]))
5775 endstop
= input_line_pointer
;
5777 input_line_pointer
+= 2;
5780 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
5781 && (input_line_pointer
[2] == '.'
5782 || ! is_part_of_name (input_line_pointer
[2])))
5784 endstop
= input_line_pointer
;
5785 input_line_pointer
+= 2;
5788 ++input_line_pointer
;
5790 if (endstop
== NULL
)
5792 as_bad ("missing do");
5793 ignore_rest_of_line ();
5796 if (endstop
> endstart
5797 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
5803 bystop
= bystart
+ 2;
5808 bystart
= input_line_pointer
;
5812 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5814 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
5815 && (input_line_pointer
[2] == '.'
5816 || ! is_part_of_name (input_line_pointer
[2])))
5818 bystop
= input_line_pointer
;
5819 input_line_pointer
+= 2;
5822 ++input_line_pointer
;
5826 as_bad ("missing do");
5827 ignore_rest_of_line ();
5830 if (bystop
> bystart
5831 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
5835 if (*input_line_pointer
!= '.')
5839 extent
= input_line_pointer
[1];
5840 input_line_pointer
+= 2;
5843 /* We have fully parsed the FOR operands. Now build the loop. */
5845 n
= push_mri_control (mri_for
);
5847 buf
= (char *) xmalloc (50 + (input_line_pointer
- varstart
));
5858 memcpy (s
, initstart
, initstop
- initstart
);
5859 s
+= initstop
- initstart
;
5861 memcpy (s
, varstart
, varstop
- varstart
);
5862 s
+= varstop
- varstart
;
5876 memcpy (s
, endstart
, endstop
- endstart
);
5877 s
+= endstop
- endstart
;
5879 memcpy (s
, varstart
, varstop
- varstart
);
5880 s
+= varstop
- varstart
;
5888 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
5890 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
5893 /* Put together the add or sub instruction used by ENDF. */
5903 memcpy (s
, bystart
, bystop
- bystart
);
5904 s
+= bystop
- bystart
;
5906 memcpy (s
, varstart
, varstop
- varstart
);
5907 s
+= varstop
- varstart
;
5913 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5914 ++input_line_pointer
;
5917 demand_empty_rest_of_line ();
5920 /* Handle the MRI ENDF pseudo-op. */
5926 if (mri_control_stack
== NULL
5927 || mri_control_stack
->type
!= mri_for
)
5929 as_bad ("endf without for");
5930 ignore_rest_of_line ();
5934 colon (mri_control_stack
->next
);
5936 md_assemble (mri_control_stack
->incr
);
5938 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
5939 md_assemble (mri_control_stack
->incr
);
5941 free (mri_control_stack
->incr
);
5943 colon (mri_control_stack
->bottom
);
5949 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5950 ++input_line_pointer
;
5953 demand_empty_rest_of_line ();
5956 /* Handle the MRI REPEAT pseudo-op. */
5959 s_mri_repeat (ignore
)
5962 struct mri_control_info
*n
;
5964 n
= push_mri_control (mri_repeat
);
5968 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5969 ++input_line_pointer
;
5971 demand_empty_rest_of_line ();
5974 /* Handle the MRI UNTIL pseudo-op. */
5982 if (mri_control_stack
== NULL
5983 || mri_control_stack
->type
!= mri_repeat
)
5985 as_bad ("until without repeat");
5986 ignore_rest_of_line ();
5990 colon (mri_control_stack
->next
);
5992 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
5995 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
5996 mri_control_stack
->top
, '\0');
5998 colon (mri_control_stack
->bottom
);
6000 input_line_pointer
= s
;
6006 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6007 ++input_line_pointer
;
6010 demand_empty_rest_of_line ();
6013 /* Handle the MRI WHILE pseudo-op. */
6021 struct mri_control_info
*n
;
6023 s
= input_line_pointer
;
6024 while (! is_end_of_line
[(unsigned char) *s
]
6025 && (! flag_mri
|| *s
!= '*'))
6028 while (*s
== ' ' || *s
== '\t')
6030 if (s
- input_line_pointer
> 1
6033 if (s
- input_line_pointer
< 2
6034 || strncasecmp (s
- 1, "DO", 2) != 0)
6036 as_bad ("missing do");
6037 ignore_rest_of_line ();
6041 n
= push_mri_control (mri_while
);
6045 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
6046 s
[1] == '.' ? s
[2] : '\0');
6048 input_line_pointer
= s
+ 1;
6049 if (*input_line_pointer
== '.')
6050 input_line_pointer
+= 2;
6054 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6055 ++input_line_pointer
;
6058 demand_empty_rest_of_line ();
6061 /* Handle the MRI ENDW pseudo-op. */
6069 if (mri_control_stack
== NULL
6070 || mri_control_stack
->type
!= mri_while
)
6072 as_bad ("endw without while");
6073 ignore_rest_of_line ();
6077 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->next
));
6078 sprintf (buf
, "bra %s", mri_control_stack
->next
);
6082 colon (mri_control_stack
->bottom
);
6088 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6089 ++input_line_pointer
;
6092 demand_empty_rest_of_line ();
6097 * Invocation line includes a switch not recognized by the base assembler.
6098 * See if it's a processor-specific option. These are:
6100 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6101 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6102 * Select the architecture. Instructions or features not
6103 * supported by the selected architecture cause fatal
6104 * errors. More than one may be specified. The default is
6105 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6106 * for -m68000, and -m68882 is a synonym for -m68881.
6107 * -[A]m[c]no-68851, -[A]m[c]no-68881
6108 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6109 * so don't use or document it, but that's the way the parsing
6112 * -pic Indicates PIC.
6113 * -k Indicates PIC. (Sun 3 only.)
6118 CONST
char *md_shortopts
= "lSA:m:kQ:V";
6120 CONST
char *md_shortopts
= "lSA:m:k";
6123 struct option md_longopts
[] = {
6124 #define OPTION_PIC (OPTION_MD_BASE)
6125 {"pic", no_argument
, NULL
, OPTION_PIC
},
6126 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6127 {"register-prefix-optional", no_argument
, NULL
,
6128 OPTION_REGISTER_PREFIX_OPTIONAL
},
6129 {NULL
, no_argument
, NULL
, 0}
6131 size_t md_longopts_size
= sizeof(md_longopts
);
6134 md_parse_option (c
, arg
)
6140 case 'l': /* -l means keep external to 2 bit offset
6141 rather than 16 bit one */
6142 flag_short_refs
= 1;
6145 case 'S': /* -S means that jbsr's always turn into
6147 flag_long_jumps
= 1;
6153 /* intentional fall-through */
6156 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
6160 const char *oarg
= arg
;
6166 if (arg
[0] == 'c' && arg
[1] == '6')
6169 for (i
= 0; i
< n_archs
; i
++)
6170 if (!strcmp (arg
, archs
[i
].name
))
6175 as_bad ("unrecognized option `%s'", oarg
);
6178 arch
= archs
[i
].arch
;
6181 else if (arch
== m68851
)
6190 if (arg
[0] == 'c' && arg
[1] == '6')
6193 for (i
= 0; i
< n_archs
; i
++)
6194 if (!strcmp (arg
, archs
[i
].name
))
6196 unsigned long arch
= archs
[i
].arch
;
6197 if (cpu_of_arch (arch
))
6198 /* It's a cpu spec. */
6200 current_architecture
&= ~m68000up
;
6201 current_architecture
|= arch
;
6203 else if (arch
== m68881
)
6205 current_architecture
|= m68881
;
6208 else if (arch
== m68851
)
6210 current_architecture
|= m68851
;
6220 as_bad ("unrecognized architecture specification `%s'", arg
);
6229 break; /* -pic, Position Independent Code */
6231 case OPTION_REGISTER_PREFIX_OPTIONAL
:
6232 flag_reg_prefix_optional
= 1;
6233 reg_prefix_optional_seen
= 1;
6236 /* -V: SVR4 argument to print version ID. */
6238 print_version_id ();
6241 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6242 should be emitted or not. FIXME: Not implemented. */
6254 md_show_usage (stream
)
6259 -l use 1 word for refs to undefined symbols [default 2]\n\
6260 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6261 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6263 specify variant of 680X0 architecture [default 68020]\n\
6264 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6265 target has/lacks floating-point coprocessor\n\
6266 [default yes for 68020, 68030, and cpu32]\n");
6268 -m68851 | -mno-68851\n\
6269 target has/lacks memory-management unit coprocessor\n\
6270 [default yes for 68020 and up]\n\
6271 -pic, -k generate position independent code\n\
6272 -S turn jbsr into jsr\n\
6273 --register-prefix-optional\n\
6274 recognize register names without prefix character\n");
6279 /* TEST2: Test md_assemble() */
6280 /* Warning, this routine probably doesn't work anymore */
6284 struct m68k_it the_ins
;
6292 if (!gets (buf
) || !*buf
)
6294 if (buf
[0] == '|' || buf
[1] == '.')
6296 for (cp
= buf
; *cp
; cp
++)
6301 memset (&the_ins
, '\0', sizeof (the_ins
));
6302 m68k_ip (&the_ins
, buf
);
6305 printf ("Error %s in %s\n", the_ins
.error
, buf
);
6309 printf ("Opcode(%d.%s): ", the_ins
.numo
, the_ins
.args
);
6310 for (n
= 0; n
< the_ins
.numo
; n
++)
6311 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
6313 print_the_insn (&the_ins
.opcode
[0], stdout
);
6314 (void) putchar ('\n');
6316 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
6318 if (the_ins
.operands
[n
].error
)
6320 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
6323 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
, the_ins
.operands
[n
].reg
);
6324 if (the_ins
.operands
[n
].b_const
)
6325 printf ("Constant: '%.*s', ", 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
, the_ins
.operands
[n
].b_const
);
6326 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
, the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
6327 if (the_ins
.operands
[n
].b_iadd
)
6328 printf ("Iadd: '%.*s',", 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
, the_ins
.operands
[n
].b_iadd
);
6329 (void) putchar ('\n');
6341 while (*str
&& *str
!= ' ')
6343 if (str
[-1] == ':' || str
[1] == '=')
6350 /* Possible states for relaxation:
6352 0 0 branch offset byte (bra, etc)
6356 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6360 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6367 /* We have no need to default values of symbols. */
6371 md_undefined_symbol (name
)
6377 /* Round up a section size to the appropriate boundary. */
6379 md_section_align (segment
, size
)
6383 return size
; /* Byte alignment is fine */
6386 /* Exactly what point is a PC-relative offset relative TO?
6387 On the 68k, it is relative to the address of the first extension
6388 word. The difference between the addresses of the offset and the
6389 first extension word is stored in fx_pcrel_adjust. */
6391 md_pcrel_from (fixP
)
6396 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6398 adjust
= fixP
->fx_pcrel_adjust
;
6401 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
6404 #ifndef BFD_ASSEMBLER
6407 tc_coff_symbol_emit_hook (ignore
)
6413 tc_coff_sizemachdep (frag
)
6416 switch (frag
->fr_subtype
& 0x3)
6431 /* end of tc-m68k.c */