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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 #include <ctype.h>
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if defined (TE_SVR4) || defined (TE_DELTA)
35 const char *m68k_comment_chars = "|#";
36 #else
37 const char *m68k_comment_chars = "|";
38 #endif
39
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars[] = "#*";
48
49 const char line_separator_chars[] = "";
50
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST char EXP_CHARS[] = "eE";
53
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
56
57 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
58
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
62
63 const int md_reloc_size = 8; /* Size of relocation record */
64
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
69 int flag_want_pic;
70
71 static int flag_short_refs; /* -l option */
72 static int flag_long_jumps; /* -S option */
73
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
76 #else
77 int flag_reg_prefix_optional;
78 #endif
79
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen;
82
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum = COP1;
85
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd;
89
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick = 1;
93
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
96 be 32 bits. */
97 static int m68k_rel32 = 1;
98
99 /* This is non-zero if m68k_rel32 was set from the command line. */
100 static int m68k_rel32_from_cmdline;
101
102 /* The default width to use for an index register when using a base
103 displacement. */
104 static enum m68k_size m68k_index_width_default = SIZE_LONG;
105
106 /* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
108 label. */
109
110 struct label_line
111 {
112 struct label_line *next;
113 symbolS *label;
114 char *file;
115 unsigned int line;
116 int text;
117 };
118
119 /* The list of labels. */
120
121 static struct label_line *labels;
122
123 /* The current label. */
124
125 static struct label_line *current_label;
126
127 /* Its an arbitrary name: This means I don't approve of it */
128 /* See flames below */
129 static struct obstack robyn;
130
131 #define TAB(x,y) (((x)<<2)+(y))
132 #define TABTYPE(xy) ((xy) >> 2)
133 #define BYTE 0
134 #define SHORT 1
135 #define LONG 2
136 #define SZ_UNDEF 3
137 #undef BRANCH
138 /* Case `g' except when BCC68000 is applicable. */
139 #define ABRANCH 1
140 /* Coprocessor branches. */
141 #define FBRANCH 2
142 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
144 #define PCREL 3
145 /* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
150 #define BCC68000 4
151 /* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
153 #define DBCC 5
154 /* Not currently used? */
155 #define PCLEA 6
156 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
157 in 16 or 8 bits. */
158 #define PCINDEX 7
159
160 struct m68k_incant
161 {
162 const char *m_operands;
163 unsigned long m_opcode;
164 short m_opnum;
165 short m_codenum;
166 int m_arch;
167 struct m68k_incant *m_next;
168 };
169
170 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171 #define gettwo(x) (((x)->m_opcode)&0xffff)
172
173 static const enum m68k_register m68000_control_regs[] = { 0 };
174 static const enum m68k_register m68010_control_regs[] = {
175 SFC, DFC, USP, VBR,
176 0
177 };
178 static const enum m68k_register m68020_control_regs[] = {
179 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
180 0
181 };
182 static const enum m68k_register m68040_control_regs[] = {
183 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
184 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
185 0
186 };
187 static const enum m68k_register m68060_control_regs[] = {
188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
189 USP, VBR, URP, SRP, PCR,
190 0
191 };
192 static const enum m68k_register mcf5200_control_regs[] = {
193 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
194 RAMBAR0, RAMBAR1, MBAR,
195 0
196 };
197 #define cpu32_control_regs m68010_control_regs
198
199 static const enum m68k_register *control_regs;
200
201 /* internal form of a 68020 instruction */
202 struct m68k_it
203 {
204 const char *error;
205 const char *args; /* list of opcode info */
206 int numargs;
207
208 int numo; /* Number of shorts in opcode */
209 short opcode[11];
210
211 struct m68k_op operands[6];
212
213 int nexp; /* number of exprs in use */
214 struct m68k_exp exprs[4];
215
216 int nfrag; /* Number of frags we have to produce */
217 struct
218 {
219 int fragoff; /* Where in the current opcode the frag ends */
220 symbolS *fadd;
221 long foff;
222 int fragty;
223 }
224 fragb[4];
225
226 int nrel; /* Num of reloc strucs in use */
227 struct
228 {
229 int n;
230 expressionS exp;
231 char wid;
232 char pcrel;
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
239 example). */
240 int pcrel_fix;
241 #ifdef OBJ_ELF
242 /* Whether this expression needs special pic relocation, and if
243 so, which. */
244 enum pic_relocation pic_reloc;
245 #endif
246 }
247 reloc[5]; /* Five is enough??? */
248 };
249
250 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
251 #define float_of_arch(x) ((x) & mfloat)
252 #define mmu_of_arch(x) ((x) & mmmu)
253
254 /* Macros for determining if cpu supports a specific addressing mode */
255 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
256
257 static struct m68k_it the_ins; /* the instruction being assembled */
258
259 #define op(ex) ((ex)->exp.X_op)
260 #define adds(ex) ((ex)->exp.X_add_symbol)
261 #define subs(ex) ((ex)->exp.X_op_symbol)
262 #define offs(ex) ((ex)->exp.X_add_number)
263
264 /* Macros for adding things to the m68k_it struct */
265
266 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
267
268 /* Like addword, but goes BEFORE general operands */
269 static void
270 insop (w, opcode)
271 int w;
272 struct m68k_incant *opcode;
273 {
274 int z;
275 for(z=the_ins.numo;z>opcode->m_codenum;--z)
276 the_ins.opcode[z]=the_ins.opcode[z-1];
277 for(z=0;z<the_ins.nrel;z++)
278 the_ins.reloc[z].n+=2;
279 for (z = 0; z < the_ins.nfrag; z++)
280 the_ins.fragb[z].fragoff++;
281 the_ins.opcode[opcode->m_codenum]=w;
282 the_ins.numo++;
283 }
284
285 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
286 Blecch. */
287 static void
288 add_fix (width, exp, pc_rel, pc_fix)
289 char width;
290 struct m68k_exp *exp;
291 int pc_rel;
292 int pc_fix;
293 {
294 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
295 ? (the_ins.numo*2-1)
296 : (((width)=='b')
297 ? (the_ins.numo*2+1)
298 : (the_ins.numo*2)));
299 the_ins.reloc[the_ins.nrel].exp = exp->exp;
300 the_ins.reloc[the_ins.nrel].wid = width;
301 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
302 #ifdef OBJ_ELF
303 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
304 #endif
305 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
306 }
307
308 /* Cause an extra frag to be generated here, inserting up to 10 bytes
309 (that value is chosen in the frag_var call in md_assemble). TYPE
310 is the subtype of the frag to be generated; its primary type is
311 rs_machine_dependent.
312
313 The TYPE parameter is also used by md_convert_frag_1 and
314 md_estimate_size_before_relax. The appropriate type of fixup will
315 be emitted by md_convert_frag_1.
316
317 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
318 static void
319 add_frag(add,off,type)
320 symbolS *add;
321 long off;
322 int type;
323 {
324 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
325 the_ins.fragb[the_ins.nfrag].fadd=add;
326 the_ins.fragb[the_ins.nfrag].foff=off;
327 the_ins.fragb[the_ins.nfrag++].fragty=type;
328 }
329
330 #define isvar(ex) \
331 (op (ex) != O_constant && op (ex) != O_big)
332
333 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
334 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
335 static int reverse_16_bits PARAMS ((int in));
336 static int reverse_8_bits PARAMS ((int in));
337 static void install_gen_operand PARAMS ((int mode, int val));
338 static void install_operand PARAMS ((int mode, int val));
339 static void s_bss PARAMS ((int));
340 static void s_data1 PARAMS ((int));
341 static void s_data2 PARAMS ((int));
342 static void s_even PARAMS ((int));
343 static void s_proc PARAMS ((int));
344 static void mri_chip PARAMS ((void));
345 static void s_chip PARAMS ((int));
346 static void s_fopt PARAMS ((int));
347 static void s_opt PARAMS ((int));
348 static void s_reg PARAMS ((int));
349 static void s_restore PARAMS ((int));
350 static void s_save PARAMS ((int));
351 static void s_mri_if PARAMS ((int));
352 static void s_mri_else PARAMS ((int));
353 static void s_mri_endi PARAMS ((int));
354 static void s_mri_break PARAMS ((int));
355 static void s_mri_next PARAMS ((int));
356 static void s_mri_for PARAMS ((int));
357 static void s_mri_endf PARAMS ((int));
358 static void s_mri_repeat PARAMS ((int));
359 static void s_mri_until PARAMS ((int));
360 static void s_mri_while PARAMS ((int));
361 static void s_mri_endw PARAMS ((int));
362
363 static int current_architecture;
364
365 struct m68k_cpu {
366 unsigned long arch;
367 const char *name;
368 int alias;
369 };
370
371 static const struct m68k_cpu archs[] = {
372 { m68000, "68000", 0 },
373 { m68010, "68010", 0 },
374 { m68020, "68020", 0 },
375 { m68030, "68030", 0 },
376 { m68040, "68040", 0 },
377 { m68060, "68060", 0 },
378 { cpu32, "cpu32", 0 },
379 { m68881, "68881", 0 },
380 { m68851, "68851", 0 },
381 { mcf5200, "5200", 0 },
382 /* Aliases (effectively, so far as gas is concerned) for the above
383 cpus. */
384 { m68020, "68k", 1 },
385 { m68000, "68302", 1 },
386 { m68000, "68008", 1 },
387 { m68000, "68ec000", 1 },
388 { m68000, "68hc000", 1 },
389 { m68000, "68hc001", 1 },
390 { m68020, "68ec020", 1 },
391 { m68030, "68ec030", 1 },
392 { m68040, "68ec040", 1 },
393 { m68060, "68ec060", 1 },
394 { cpu32, "68330", 1 },
395 { cpu32, "68331", 1 },
396 { cpu32, "68332", 1 },
397 { cpu32, "68333", 1 },
398 { cpu32, "68340", 1 },
399 { cpu32, "68360", 1 },
400 { m68881, "68882", 1 },
401 };
402
403 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
404
405 /* BCC68000 is for patching in an extra jmp instruction for long offsets
406 on the 68000. The 68000 doesn't support long branches with branchs */
407
408 /* This table desribes how you change sizes for the various types of variable
409 size expressions. This version only supports two kinds. */
410
411 /* Note that calls to frag_var need to specify the maximum expansion
412 needed; this is currently 10 bytes for DBCC. */
413
414 /* The fields are:
415 How far Forward this mode will reach:
416 How far Backward this mode will reach:
417 How many bytes this mode will add to the size of the frag
418 Which mode to go to if the offset won't fit in this one
419 */
420 relax_typeS md_relax_table[] =
421 {
422 {1, 1, 0, 0}, /* First entries aren't used */
423 {1, 1, 0, 0}, /* For no good reason except */
424 {1, 1, 0, 0}, /* that the VAX doesn't either */
425 {1, 1, 0, 0},
426
427 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
428 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
429 {0, 0, 4, 0},
430 {1, 1, 0, 0},
431
432 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
433 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
434 {0, 0, 4, 0},
435 {1, 1, 0, 0},
436
437 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
438 {(32767), (-32768), 2, TAB (PCREL, LONG)},
439 {0, 0, 4, 0},
440 {1, 1, 0, 0},
441
442 {(127), (-128), 0, TAB (BCC68000, SHORT)},
443 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
444 {0, 0, 6, 0}, /* jmp long space */
445 {1, 1, 0, 0},
446
447 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
448 {(32767), (-32768), 2, TAB (DBCC, LONG)},
449 {0, 0, 10, 0}, /* bra/jmp long space */
450 {1, 1, 0, 0},
451
452 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
453 {32767, -32768, 2, TAB (PCLEA, LONG)},
454 {0, 0, 6, 0},
455 {1, 1, 0, 0},
456
457 /* For, e.g., jmp pcrel indexed. */
458 {125, -130, 0, TAB (PCINDEX, SHORT)},
459 {32765, -32770, 2, TAB (PCINDEX, LONG)},
460 {0, 0, 4, 0},
461 {1, 1, 0, 0},
462 };
463
464 /* These are the machine dependent pseudo-ops. These are included so
465 the assembler can work on the output from the SUN C compiler, which
466 generates these.
467 */
468
469 /* This table describes all the machine specific pseudo-ops the assembler
470 has to support. The fields are:
471 pseudo-op name without dot
472 function to call to execute this pseudo-op
473 Integer arg to pass to the function
474 */
475 const pseudo_typeS md_pseudo_table[] =
476 {
477 {"data1", s_data1, 0},
478 {"data2", s_data2, 0},
479 {"bss", s_bss, 0},
480 {"even", s_even, 0},
481 {"skip", s_space, 0},
482 {"proc", s_proc, 0},
483 #if defined (TE_SUN3) || defined (OBJ_ELF)
484 {"align", s_align_bytes, 0},
485 #endif
486 #ifdef OBJ_ELF
487 {"swbeg", s_ignore, 0},
488 #endif
489 {"extend", float_cons, 'x'},
490 {"ldouble", float_cons, 'x'},
491
492 /* The following pseudo-ops are supported for MRI compatibility. */
493 {"chip", s_chip, 0},
494 {"comline", s_space, 1},
495 {"fopt", s_fopt, 0},
496 {"mask2", s_ignore, 0},
497 {"opt", s_opt, 0},
498 {"reg", s_reg, 0},
499 {"restore", s_restore, 0},
500 {"save", s_save, 0},
501
502 {"if", s_mri_if, 0},
503 {"if.b", s_mri_if, 'b'},
504 {"if.w", s_mri_if, 'w'},
505 {"if.l", s_mri_if, 'l'},
506 {"else", s_mri_else, 0},
507 {"else.s", s_mri_else, 's'},
508 {"else.l", s_mri_else, 'l'},
509 {"endi", s_mri_endi, 0},
510 {"break", s_mri_break, 0},
511 {"break.s", s_mri_break, 's'},
512 {"break.l", s_mri_break, 'l'},
513 {"next", s_mri_next, 0},
514 {"next.s", s_mri_next, 's'},
515 {"next.l", s_mri_next, 'l'},
516 {"for", s_mri_for, 0},
517 {"for.b", s_mri_for, 'b'},
518 {"for.w", s_mri_for, 'w'},
519 {"for.l", s_mri_for, 'l'},
520 {"endf", s_mri_endf, 0},
521 {"repeat", s_mri_repeat, 0},
522 {"until", s_mri_until, 0},
523 {"until.b", s_mri_until, 'b'},
524 {"until.w", s_mri_until, 'w'},
525 {"until.l", s_mri_until, 'l'},
526 {"while", s_mri_while, 0},
527 {"while.b", s_mri_while, 'b'},
528 {"while.w", s_mri_while, 'w'},
529 {"while.l", s_mri_while, 'l'},
530 {"endw", s_mri_endw, 0},
531
532 {0, 0, 0}
533 };
534
535
536 /* The mote pseudo ops are put into the opcode table, since they
537 don't start with a . they look like opcodes to gas.
538 */
539 extern void obj_coff_section ();
540
541 CONST pseudo_typeS mote_pseudo_table[] =
542 {
543
544 {"dcl", cons, 4},
545 {"dc", cons, 2},
546 {"dcw", cons, 2},
547 {"dcb", cons, 1},
548
549 {"dsl", s_space, 4},
550 {"ds", s_space, 2},
551 {"dsw", s_space, 2},
552 {"dsb", s_space, 1},
553
554 {"xdef", s_globl, 0},
555 #ifdef OBJ_ELF
556 {"align", s_align_bytes, 0},
557 #else
558 {"align", s_align_ptwo, 0},
559 #endif
560 #ifdef M68KCOFF
561 {"sect", obj_coff_section, 0},
562 {"section", obj_coff_section, 0},
563 #endif
564 {0, 0, 0}
565 };
566
567 #define issbyte(x) ((x)>=-128 && (x)<=127)
568 #define isubyte(x) ((x)>=0 && (x)<=255)
569 #define issword(x) ((x)>=-32768 && (x)<=32767)
570 #define isuword(x) ((x)>=0 && (x)<=65535)
571
572 #define isbyte(x) ((x)>= -255 && (x)<=255)
573 #define isword(x) ((x)>=-65536 && (x)<=65535)
574 #define islong(x) (1)
575
576 extern char *input_line_pointer;
577
578 static char mklower_table[256];
579 #define mklower(c) (mklower_table[(unsigned char)(c)])
580 static char notend_table[256];
581 static char alt_notend_table[256];
582 #define notend(s) \
583 (! (notend_table[(unsigned char) *s] \
584 || (*s == ':' \
585 && alt_notend_table[(unsigned char) s[1]])))
586
587 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
588
589 #ifdef NO_PCREL_RELOCS
590
591 int
592 make_pcrel_absolute(fixP, add_number)
593 fixS *fixP;
594 long *add_number;
595 {
596 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
597
598 /* rewrite the PC relative instructions to absolute address ones.
599 * these are rumoured to be faster, and the apollo linker refuses
600 * to deal with the PC relative relocations.
601 */
602 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
603 {
604 opcode[0] = 0x4e;
605 opcode[1] = 0xf9;
606 }
607 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
608 {
609 opcode[0] = 0x4e;
610 opcode[1] = 0xb9;
611 }
612 else
613 as_fatal ("Unknown PC relative instruction");
614 *add_number -= 4;
615 return 0;
616 }
617
618 #endif /* NO_PCREL_RELOCS */
619
620 short
621 tc_coff_fix2rtype (fixP)
622 fixS *fixP;
623 {
624 if (fixP->fx_tcbit && fixP->fx_size == 4)
625 return R_RELLONG_NEG;
626 #ifdef NO_PCREL_RELOCS
627 know (fixP->fx_pcrel == 0);
628 return (fixP->fx_size == 1 ? R_RELBYTE
629 : fixP->fx_size == 2 ? R_DIR16
630 : R_DIR32);
631 #else
632 return (fixP->fx_pcrel ?
633 (fixP->fx_size == 1 ? R_PCRBYTE :
634 fixP->fx_size == 2 ? R_PCRWORD :
635 R_PCRLONG) :
636 (fixP->fx_size == 1 ? R_RELBYTE :
637 fixP->fx_size == 2 ? R_RELWORD :
638 R_RELLONG));
639 #endif
640 }
641
642 #endif
643
644 #ifdef OBJ_ELF
645
646 /* Compute the relocation code for a fixup of SIZE bytes, using pc
647 relative relocation if PCREL is non-zero. PIC says whether a special
648 pic relocation was requested. */
649
650 static bfd_reloc_code_real_type get_reloc_code
651 PARAMS ((int, int, enum pic_relocation));
652
653 static bfd_reloc_code_real_type
654 get_reloc_code (size, pcrel, pic)
655 int size;
656 int pcrel;
657 enum pic_relocation pic;
658 {
659 switch (pic)
660 {
661 case pic_got_pcrel:
662 switch (size)
663 {
664 case 1:
665 return BFD_RELOC_8_GOT_PCREL;
666 case 2:
667 return BFD_RELOC_16_GOT_PCREL;
668 case 4:
669 return BFD_RELOC_32_GOT_PCREL;
670 }
671 break;
672
673 case pic_got_off:
674 switch (size)
675 {
676 case 1:
677 return BFD_RELOC_8_GOTOFF;
678 case 2:
679 return BFD_RELOC_16_GOTOFF;
680 case 4:
681 return BFD_RELOC_32_GOTOFF;
682 }
683 break;
684
685 case pic_plt_pcrel:
686 switch (size)
687 {
688 case 1:
689 return BFD_RELOC_8_PLT_PCREL;
690 case 2:
691 return BFD_RELOC_16_PLT_PCREL;
692 case 4:
693 return BFD_RELOC_32_PLT_PCREL;
694 }
695 break;
696
697 case pic_plt_off:
698 switch (size)
699 {
700 case 1:
701 return BFD_RELOC_8_PLTOFF;
702 case 2:
703 return BFD_RELOC_16_PLTOFF;
704 case 4:
705 return BFD_RELOC_32_PLTOFF;
706 }
707 break;
708
709 case pic_none:
710 if (pcrel)
711 {
712 switch (size)
713 {
714 case 1:
715 return BFD_RELOC_8_PCREL;
716 case 2:
717 return BFD_RELOC_16_PCREL;
718 case 4:
719 return BFD_RELOC_32_PCREL;
720 }
721 }
722 else
723 {
724 switch (size)
725 {
726 case 1:
727 return BFD_RELOC_8;
728 case 2:
729 return BFD_RELOC_16;
730 case 4:
731 return BFD_RELOC_32;
732 }
733 }
734 }
735
736 as_bad ("Can not do %d byte %s%srelocation", size,
737 pcrel ? "pc-relative " : "",
738 pic == pic_none ? "" : "pic ");
739 return BFD_RELOC_NONE;
740 }
741
742 /* Here we decide which fixups can be adjusted to make them relative
743 to the beginning of the section instead of the symbol. Basically
744 we need to make sure that the dynamic relocations are done
745 correctly, so in some cases we force the original symbol to be
746 used. */
747 int
748 tc_m68k_fix_adjustable (fixP)
749 fixS *fixP;
750 {
751 /* Prevent all adjustments to global symbols. */
752 if (S_IS_EXTERNAL (fixP->fx_addsy))
753 return 0;
754
755 /* adjust_reloc_syms doesn't know about the GOT */
756 switch (fixP->fx_r_type)
757 {
758 case BFD_RELOC_8_GOT_PCREL:
759 case BFD_RELOC_16_GOT_PCREL:
760 case BFD_RELOC_32_GOT_PCREL:
761 case BFD_RELOC_8_GOTOFF:
762 case BFD_RELOC_16_GOTOFF:
763 case BFD_RELOC_32_GOTOFF:
764 case BFD_RELOC_8_PLT_PCREL:
765 case BFD_RELOC_16_PLT_PCREL:
766 case BFD_RELOC_32_PLT_PCREL:
767 case BFD_RELOC_8_PLTOFF:
768 case BFD_RELOC_16_PLTOFF:
769 case BFD_RELOC_32_PLTOFF:
770 return 0;
771
772 default:
773 return 1;
774 }
775 }
776
777 #else /* !OBJ_ELF */
778
779 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
780
781 #endif /* OBJ_ELF */
782
783 #ifdef BFD_ASSEMBLER
784
785 arelent *
786 tc_gen_reloc (section, fixp)
787 asection *section;
788 fixS *fixp;
789 {
790 arelent *reloc;
791 bfd_reloc_code_real_type code;
792
793 if (fixp->fx_tcbit)
794 abort ();
795
796 if (fixp->fx_r_type != BFD_RELOC_NONE)
797 {
798 code = fixp->fx_r_type;
799
800 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
801 that fixup_segment converted a non-PC relative reloc into a
802 PC relative reloc. In such a case, we need to convert the
803 reloc code. */
804 if (fixp->fx_pcrel)
805 {
806 switch (code)
807 {
808 case BFD_RELOC_8:
809 code = BFD_RELOC_8_PCREL;
810 break;
811 case BFD_RELOC_16:
812 code = BFD_RELOC_16_PCREL;
813 break;
814 case BFD_RELOC_32:
815 code = BFD_RELOC_32_PCREL;
816 break;
817 case BFD_RELOC_8_PCREL:
818 case BFD_RELOC_16_PCREL:
819 case BFD_RELOC_32_PCREL:
820 case BFD_RELOC_8_GOT_PCREL:
821 case BFD_RELOC_16_GOT_PCREL:
822 case BFD_RELOC_32_GOT_PCREL:
823 case BFD_RELOC_8_GOTOFF:
824 case BFD_RELOC_16_GOTOFF:
825 case BFD_RELOC_32_GOTOFF:
826 case BFD_RELOC_8_PLT_PCREL:
827 case BFD_RELOC_16_PLT_PCREL:
828 case BFD_RELOC_32_PLT_PCREL:
829 case BFD_RELOC_8_PLTOFF:
830 case BFD_RELOC_16_PLTOFF:
831 case BFD_RELOC_32_PLTOFF:
832 break;
833 default:
834 as_bad_where (fixp->fx_file, fixp->fx_line,
835 "Cannot make %s relocation PC relative",
836 bfd_get_reloc_code_name (code));
837 }
838 }
839 }
840 else
841 {
842 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
843 switch (F (fixp->fx_size, fixp->fx_pcrel))
844 {
845 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
846 MAP (1, 0, BFD_RELOC_8);
847 MAP (2, 0, BFD_RELOC_16);
848 MAP (4, 0, BFD_RELOC_32);
849 MAP (1, 1, BFD_RELOC_8_PCREL);
850 MAP (2, 1, BFD_RELOC_16_PCREL);
851 MAP (4, 1, BFD_RELOC_32_PCREL);
852 default:
853 abort ();
854 }
855 }
856 #undef F
857 #undef MAP
858
859 reloc = (arelent *) xmalloc (sizeof (arelent));
860 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
861 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
862 #ifndef OBJ_ELF
863 if (fixp->fx_pcrel)
864 reloc->addend = fixp->fx_addnumber;
865 else
866 reloc->addend = 0;
867 #else
868 if (!fixp->fx_pcrel)
869 reloc->addend = fixp->fx_addnumber;
870 else
871 reloc->addend = (section->vma
872 + (fixp->fx_pcrel_adjust == 64
873 ? -1 : fixp->fx_pcrel_adjust)
874 + fixp->fx_addnumber
875 + md_pcrel_from (fixp));
876 #endif
877
878 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
879 assert (reloc->howto != 0);
880
881 return reloc;
882 }
883
884 #endif /* BFD_ASSEMBLER */
885
886 /* Handle of the OPCODE hash table. NULL means any use before
887 m68k_ip_begin() will crash. */
888 static struct hash_control *op_hash;
889 \f
890 /* Assemble an m68k instruction. */
891
892 void
893 m68k_ip (instring)
894 char *instring;
895 {
896 register char *p;
897 register struct m68k_op *opP;
898 register struct m68k_incant *opcode;
899 register const char *s;
900 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
901 char *pdot, *pdotmove;
902 enum m68k_size siz1, siz2;
903 char c;
904 int losing;
905 int opsfound;
906 LITTLENUM_TYPE words[6];
907 LITTLENUM_TYPE *wordp;
908 unsigned long ok_arch = 0;
909
910 if (*instring == ' ')
911 instring++; /* skip leading whitespace */
912
913 /* Scan up to end of operation-code, which MUST end in end-of-string
914 or exactly 1 space. */
915 pdot = 0;
916 for (p = instring; *p != '\0'; p++)
917 {
918 if (*p == ' ')
919 break;
920 if (*p == '.')
921 pdot = p;
922 }
923
924 if (p == instring)
925 {
926 the_ins.error = "No operator";
927 return;
928 }
929
930 /* p now points to the end of the opcode name, probably whitespace.
931 Make sure the name is null terminated by clobbering the
932 whitespace, look it up in the hash table, then fix it back.
933 Remove a dot, first, since the opcode tables have none. */
934 if (pdot != NULL)
935 {
936 for (pdotmove = pdot; pdotmove < p; pdotmove++)
937 *pdotmove = pdotmove[1];
938 p--;
939 }
940
941 c = *p;
942 *p = '\0';
943 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
944 *p = c;
945
946 if (pdot != NULL)
947 {
948 for (pdotmove = p; pdotmove > pdot; pdotmove--)
949 *pdotmove = pdotmove[-1];
950 *pdot = '.';
951 ++p;
952 }
953
954 if (opcode == NULL)
955 {
956 the_ins.error = "Unknown operator";
957 return;
958 }
959
960 /* found a legitimate opcode, start matching operands */
961 while (*p == ' ')
962 ++p;
963
964 if (opcode->m_operands == 0)
965 {
966 char *old = input_line_pointer;
967 *old = '\n';
968 input_line_pointer = p;
969 /* Ahh - it's a motorola style psuedo op */
970 mote_pseudo_table[opcode->m_opnum].poc_handler
971 (mote_pseudo_table[opcode->m_opnum].poc_val);
972 input_line_pointer = old;
973 *old = 0;
974
975 return;
976 }
977
978 if (flag_mri && opcode->m_opnum == 0)
979 {
980 /* In MRI mode, random garbage is allowed after an instruction
981 which accepts no operands. */
982 the_ins.args = opcode->m_operands;
983 the_ins.numargs = opcode->m_opnum;
984 the_ins.numo = opcode->m_codenum;
985 the_ins.opcode[0] = getone (opcode);
986 the_ins.opcode[1] = gettwo (opcode);
987 return;
988 }
989
990 for (opP = &the_ins.operands[0]; *p; opP++)
991 {
992 p = crack_operand (p, opP);
993
994 if (opP->error)
995 {
996 the_ins.error = opP->error;
997 return;
998 }
999 }
1000
1001 opsfound = opP - &the_ins.operands[0];
1002
1003 /* This ugly hack is to support the floating pt opcodes in their
1004 standard form. Essentially, we fake a first enty of type COP#1 */
1005 if (opcode->m_operands[0] == 'I')
1006 {
1007 int n;
1008
1009 for (n = opsfound; n > 0; --n)
1010 the_ins.operands[n] = the_ins.operands[n - 1];
1011
1012 memset ((char *) (&the_ins.operands[0]), '\0',
1013 sizeof (the_ins.operands[0]));
1014 the_ins.operands[0].mode = CONTROL;
1015 the_ins.operands[0].reg = m68k_float_copnum;
1016 opsfound++;
1017 }
1018
1019 /* We've got the operands. Find an opcode that'll accept them */
1020 for (losing = 0;;)
1021 {
1022 /* If we didn't get the right number of ops, or we have no
1023 common model with this pattern then reject this pattern. */
1024
1025 ok_arch |= opcode->m_arch;
1026 if (opsfound != opcode->m_opnum
1027 || ((opcode->m_arch & current_architecture) == 0))
1028 ++losing;
1029 else
1030 {
1031 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1032 *s && !losing;
1033 s += 2, opP++)
1034 {
1035 /* Warning: this switch is huge! */
1036 /* I've tried to organize the cases into this order:
1037 non-alpha first, then alpha by letter. Lower-case
1038 goes directly before uppercase counterpart. */
1039 /* Code with multiple case ...: gets sorted by the lowest
1040 case ... it belongs to. I hope this makes sense. */
1041 switch (*s)
1042 {
1043 case '!':
1044 switch (opP->mode)
1045 {
1046 case IMMED:
1047 case DREG:
1048 case AREG:
1049 case FPREG:
1050 case CONTROL:
1051 case AINC:
1052 case ADEC:
1053 case REGLST:
1054 losing++;
1055 break;
1056 default:
1057 break;
1058 }
1059 break;
1060
1061 case '`':
1062 switch (opP->mode)
1063 {
1064 case IMMED:
1065 case DREG:
1066 case AREG:
1067 case FPREG:
1068 case CONTROL:
1069 case AINC:
1070 case REGLST:
1071 case AINDR:
1072 losing++;
1073 break;
1074 default:
1075 break;
1076 }
1077 break;
1078
1079 case '<':
1080 switch (opP->mode)
1081 {
1082 case DREG:
1083 case AREG:
1084 case FPREG:
1085 case CONTROL:
1086 case IMMED:
1087 case ADEC:
1088 case REGLST:
1089 losing++;
1090 break;
1091 default:
1092 break;
1093 }
1094 break;
1095
1096 case '>':
1097 switch (opP->mode)
1098 {
1099 case DREG:
1100 case AREG:
1101 case FPREG:
1102 case CONTROL:
1103 case IMMED:
1104 case AINC:
1105 case REGLST:
1106 losing++;
1107 break;
1108 case ABSL:
1109 break;
1110 default:
1111 if (opP->reg == PC
1112 || opP->reg == ZPC)
1113 losing++;
1114 break;
1115 }
1116 break;
1117
1118 case 'm':
1119 switch (opP->mode)
1120 {
1121 case DREG:
1122 case AREG:
1123 case AINDR:
1124 case AINC:
1125 case ADEC:
1126 break;
1127 default:
1128 losing++;
1129 }
1130 break;
1131
1132 case 'n':
1133 switch (opP->mode)
1134 {
1135 case DISP:
1136 break;
1137 default:
1138 losing++;
1139 }
1140 break;
1141
1142 case 'o':
1143 switch (opP->mode)
1144 {
1145 case BASE:
1146 case ABSL:
1147 case IMMED:
1148 break;
1149 default:
1150 losing++;
1151 }
1152 break;
1153
1154 case 'p':
1155 switch (opP->mode)
1156 {
1157 case DREG:
1158 case AREG:
1159 case AINDR:
1160 case AINC:
1161 case ADEC:
1162 break;
1163 case DISP:
1164 if (opP->reg == PC || opP->reg == ZPC)
1165 losing++;
1166 break;
1167 default:
1168 losing++;
1169 }
1170 break;
1171
1172 case '#':
1173 if (opP->mode != IMMED)
1174 losing++;
1175 else if (s[1] == 'b'
1176 && ! isvar (&opP->disp)
1177 && (opP->disp.exp.X_op != O_constant
1178 || ! isbyte (opP->disp.exp.X_add_number)))
1179 losing++;
1180 else if (s[1] == 'B'
1181 && ! isvar (&opP->disp)
1182 && (opP->disp.exp.X_op != O_constant
1183 || ! issbyte (opP->disp.exp.X_add_number)))
1184 losing++;
1185 else if (s[1] == 'w'
1186 && ! isvar (&opP->disp)
1187 && (opP->disp.exp.X_op != O_constant
1188 || ! isword (opP->disp.exp.X_add_number)))
1189 losing++;
1190 else if (s[1] == 'W'
1191 && ! isvar (&opP->disp)
1192 && (opP->disp.exp.X_op != O_constant
1193 || ! issword (opP->disp.exp.X_add_number)))
1194 losing++;
1195 break;
1196
1197 case '^':
1198 case 'T':
1199 if (opP->mode != IMMED)
1200 losing++;
1201 break;
1202
1203 case '$':
1204 if (opP->mode == AREG
1205 || opP->mode == CONTROL
1206 || opP->mode == FPREG
1207 || opP->mode == IMMED
1208 || opP->mode == REGLST
1209 || (opP->mode != ABSL
1210 && (opP->reg == PC
1211 || opP->reg == ZPC)))
1212 losing++;
1213 break;
1214
1215 case '%':
1216 if (opP->mode == CONTROL
1217 || opP->mode == FPREG
1218 || opP->mode == REGLST
1219 || opP->mode == IMMED
1220 || (opP->mode != ABSL
1221 && (opP->reg == PC
1222 || opP->reg == ZPC)))
1223 losing++;
1224 break;
1225
1226 case '&':
1227 switch (opP->mode)
1228 {
1229 case DREG:
1230 case AREG:
1231 case FPREG:
1232 case CONTROL:
1233 case IMMED:
1234 case AINC:
1235 case ADEC:
1236 case REGLST:
1237 losing++;
1238 break;
1239 case ABSL:
1240 break;
1241 default:
1242 if (opP->reg == PC
1243 || opP->reg == ZPC)
1244 losing++;
1245 break;
1246 }
1247 break;
1248
1249 case '*':
1250 if (opP->mode == CONTROL
1251 || opP->mode == FPREG
1252 || opP->mode == REGLST)
1253 losing++;
1254 break;
1255
1256 case '+':
1257 if (opP->mode != AINC)
1258 losing++;
1259 break;
1260
1261 case '-':
1262 if (opP->mode != ADEC)
1263 losing++;
1264 break;
1265
1266 case '/':
1267 switch (opP->mode)
1268 {
1269 case AREG:
1270 case CONTROL:
1271 case FPREG:
1272 case AINC:
1273 case ADEC:
1274 case IMMED:
1275 case REGLST:
1276 losing++;
1277 break;
1278 default:
1279 break;
1280 }
1281 break;
1282
1283 case ';':
1284 switch (opP->mode)
1285 {
1286 case AREG:
1287 case CONTROL:
1288 case FPREG:
1289 case REGLST:
1290 losing++;
1291 break;
1292 default:
1293 break;
1294 }
1295 break;
1296
1297 case '?':
1298 switch (opP->mode)
1299 {
1300 case AREG:
1301 case CONTROL:
1302 case FPREG:
1303 case AINC:
1304 case ADEC:
1305 case IMMED:
1306 case REGLST:
1307 losing++;
1308 break;
1309 case ABSL:
1310 break;
1311 default:
1312 if (opP->reg == PC || opP->reg == ZPC)
1313 losing++;
1314 break;
1315 }
1316 break;
1317
1318 case '@':
1319 switch (opP->mode)
1320 {
1321 case AREG:
1322 case CONTROL:
1323 case FPREG:
1324 case IMMED:
1325 case REGLST:
1326 losing++;
1327 break;
1328 default:
1329 break;
1330 }
1331 break;
1332
1333 case '~': /* For now! (JF FOO is this right?) */
1334 switch (opP->mode)
1335 {
1336 case DREG:
1337 case AREG:
1338 case CONTROL:
1339 case FPREG:
1340 case IMMED:
1341 case REGLST:
1342 losing++;
1343 break;
1344 case ABSL:
1345 break;
1346 default:
1347 if (opP->reg == PC
1348 || opP->reg == ZPC)
1349 losing++;
1350 break;
1351 }
1352 break;
1353
1354 case '3':
1355 if (opP->mode != CONTROL
1356 || (opP->reg != TT0 && opP->reg != TT1))
1357 losing++;
1358 break;
1359
1360 case 'A':
1361 if (opP->mode != AREG)
1362 losing++;
1363 break;
1364
1365 case 'a':
1366 if (opP->mode != AINDR)
1367 ++losing;
1368 break;
1369
1370 case 'B': /* FOO */
1371 if (opP->mode != ABSL
1372 || (flag_long_jumps
1373 && strncmp (instring, "jbsr", 4) == 0))
1374 losing++;
1375 break;
1376
1377 case 'C':
1378 if (opP->mode != CONTROL || opP->reg != CCR)
1379 losing++;
1380 break;
1381
1382 case 'd':
1383 if (opP->mode != DISP
1384 || opP->reg < ADDR0
1385 || opP->reg > ADDR7)
1386 losing++;
1387 break;
1388
1389 case 'D':
1390 if (opP->mode != DREG)
1391 losing++;
1392 break;
1393
1394 case 'F':
1395 if (opP->mode != FPREG)
1396 losing++;
1397 break;
1398
1399 case 'I':
1400 if (opP->mode != CONTROL
1401 || opP->reg < COP0
1402 || opP->reg > COP7)
1403 losing++;
1404 break;
1405
1406 case 'J':
1407 if (opP->mode != CONTROL
1408 || opP->reg < USP
1409 || opP->reg > last_movec_reg)
1410 losing++;
1411 else
1412 {
1413 const enum m68k_register *rp;
1414 for (rp = control_regs; *rp; rp++)
1415 if (*rp == opP->reg)
1416 break;
1417 if (*rp == 0)
1418 losing++;
1419 }
1420 break;
1421
1422 case 'k':
1423 if (opP->mode != IMMED)
1424 losing++;
1425 break;
1426
1427 case 'l':
1428 case 'L':
1429 if (opP->mode == DREG
1430 || opP->mode == AREG
1431 || opP->mode == FPREG)
1432 {
1433 if (s[1] == '8')
1434 losing++;
1435 else
1436 {
1437 switch (opP->mode)
1438 {
1439 case DREG:
1440 opP->mask = 1 << (opP->reg - DATA0);
1441 break;
1442 case AREG:
1443 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1444 break;
1445 case FPREG:
1446 opP->mask = 1 << (opP->reg - FP0 + 16);
1447 break;
1448 default:
1449 abort ();
1450 }
1451 opP->mode = REGLST;
1452 }
1453 }
1454 else if (opP->mode == CONTROL)
1455 {
1456 if (s[1] != '8')
1457 losing++;
1458 else
1459 {
1460 switch (opP->reg)
1461 {
1462 case FPI:
1463 opP->mask = 1 << 24;
1464 break;
1465 case FPS:
1466 opP->mask = 1 << 25;
1467 break;
1468 case FPC:
1469 opP->mask = 1 << 26;
1470 break;
1471 default:
1472 losing++;
1473 break;
1474 }
1475 opP->mode = REGLST;
1476 }
1477 }
1478 else if (opP->mode == ABSL
1479 && opP->disp.size == SIZE_UNSPEC
1480 && opP->disp.exp.X_op == O_constant)
1481 {
1482 /* This is what the MRI REG pseudo-op generates. */
1483 opP->mode = REGLST;
1484 opP->mask = opP->disp.exp.X_add_number;
1485 }
1486 else if (opP->mode != REGLST)
1487 losing++;
1488 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1489 losing++;
1490 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1491 losing++;
1492 break;
1493
1494 case 'M':
1495 if (opP->mode != IMMED)
1496 losing++;
1497 else if (opP->disp.exp.X_op != O_constant
1498 || ! issbyte (opP->disp.exp.X_add_number))
1499 losing++;
1500 else if (! m68k_quick
1501 && instring[3] != 'q'
1502 && instring[4] != 'q')
1503 losing++;
1504 break;
1505
1506 case 'O':
1507 if (opP->mode != DREG
1508 && opP->mode != IMMED
1509 && opP->mode != ABSL)
1510 losing++;
1511 break;
1512
1513 case 'Q':
1514 if (opP->mode != IMMED)
1515 losing++;
1516 else if (opP->disp.exp.X_op != O_constant
1517 || opP->disp.exp.X_add_number < 1
1518 || opP->disp.exp.X_add_number > 8)
1519 losing++;
1520 else if (! m68k_quick
1521 && (strncmp (instring, "add", 3) == 0
1522 || strncmp (instring, "sub", 3) == 0)
1523 && instring[3] != 'q')
1524 losing++;
1525 break;
1526
1527 case 'R':
1528 if (opP->mode != DREG && opP->mode != AREG)
1529 losing++;
1530 break;
1531
1532 case 'r':
1533 if (opP->mode != AINDR
1534 && (opP->mode != BASE
1535 || (opP->reg != 0
1536 && opP->reg != ZADDR0)
1537 || opP->disp.exp.X_op != O_absent
1538 || ((opP->index.reg < DATA0
1539 || opP->index.reg > DATA7)
1540 && (opP->index.reg < ADDR0
1541 || opP->index.reg > ADDR7))
1542 || opP->index.size != SIZE_UNSPEC
1543 || opP->index.scale != 1))
1544 losing++;
1545 break;
1546
1547 case 's':
1548 if (opP->mode != CONTROL
1549 || ! (opP->reg == FPI
1550 || opP->reg == FPS
1551 || opP->reg == FPC))
1552 losing++;
1553 break;
1554
1555 case 'S':
1556 if (opP->mode != CONTROL || opP->reg != SR)
1557 losing++;
1558 break;
1559
1560 case 't':
1561 if (opP->mode != IMMED)
1562 losing++;
1563 else if (opP->disp.exp.X_op != O_constant
1564 || opP->disp.exp.X_add_number < 0
1565 || opP->disp.exp.X_add_number > 7)
1566 losing++;
1567 break;
1568
1569 case 'U':
1570 if (opP->mode != CONTROL || opP->reg != USP)
1571 losing++;
1572 break;
1573
1574 /* JF these are out of order. We could put them
1575 in order if we were willing to put up with
1576 bunches of #ifdef m68851s in the code.
1577
1578 Don't forget that you need these operands
1579 to use 68030 MMU instructions. */
1580 #ifndef NO_68851
1581 /* Memory addressing mode used by pflushr */
1582 case '|':
1583 if (opP->mode == CONTROL
1584 || opP->mode == FPREG
1585 || opP->mode == DREG
1586 || opP->mode == AREG
1587 || opP->mode == REGLST)
1588 losing++;
1589 /* We should accept immediate operands, but they
1590 supposedly have to be quad word, and we don't
1591 handle that. I would like to see what a Motorola
1592 assembler does before doing something here. */
1593 if (opP->mode == IMMED)
1594 losing++;
1595 break;
1596
1597 case 'f':
1598 if (opP->mode != CONTROL
1599 || (opP->reg != SFC && opP->reg != DFC))
1600 losing++;
1601 break;
1602
1603 case '0':
1604 if (opP->mode != CONTROL || opP->reg != TC)
1605 losing++;
1606 break;
1607
1608 case '1':
1609 if (opP->mode != CONTROL || opP->reg != AC)
1610 losing++;
1611 break;
1612
1613 case '2':
1614 if (opP->mode != CONTROL
1615 || (opP->reg != CAL
1616 && opP->reg != VAL
1617 && opP->reg != SCC))
1618 losing++;
1619 break;
1620
1621 case 'V':
1622 if (opP->mode != CONTROL
1623 || opP->reg != VAL)
1624 losing++;
1625 break;
1626
1627 case 'W':
1628 if (opP->mode != CONTROL
1629 || (opP->reg != DRP
1630 && opP->reg != SRP
1631 && opP->reg != CRP))
1632 losing++;
1633 break;
1634
1635 case 'X':
1636 if (opP->mode != CONTROL
1637 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1638 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1639 losing++;
1640 break;
1641
1642 case 'Y':
1643 if (opP->mode != CONTROL || opP->reg != PSR)
1644 losing++;
1645 break;
1646
1647 case 'Z':
1648 if (opP->mode != CONTROL || opP->reg != PCSR)
1649 losing++;
1650 break;
1651 #endif
1652 case 'c':
1653 if (opP->mode != CONTROL
1654 || (opP->reg != NC
1655 && opP->reg != IC
1656 && opP->reg != DC
1657 && opP->reg != BC))
1658 {
1659 losing++;
1660 } /* not a cache specifier. */
1661 break;
1662
1663 case '_':
1664 if (opP->mode != ABSL)
1665 ++losing;
1666 break;
1667
1668 default:
1669 abort ();
1670 } /* switch on type of operand */
1671
1672 if (losing)
1673 break;
1674 } /* for each operand */
1675 } /* if immediately wrong */
1676
1677 if (!losing)
1678 {
1679 break;
1680 } /* got it. */
1681
1682 opcode = opcode->m_next;
1683
1684 if (!opcode)
1685 {
1686 if (ok_arch
1687 && !(ok_arch & current_architecture))
1688 {
1689 char buf[200], *cp;
1690
1691 strcpy (buf,
1692 "invalid instruction for this architecture; needs ");
1693 cp = buf + strlen (buf);
1694 switch (ok_arch)
1695 {
1696 case mfloat:
1697 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1698 break;
1699 case mmmu:
1700 strcpy (cp, "mmu (68030 or 68851)");
1701 break;
1702 case m68020up:
1703 strcpy (cp, "68020 or higher");
1704 break;
1705 case m68000up:
1706 strcpy (cp, "68000 or higher");
1707 break;
1708 case m68010up:
1709 strcpy (cp, "68010 or higher");
1710 break;
1711 default:
1712 {
1713 int got_one = 0, idx;
1714 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1715 idx++)
1716 {
1717 if ((archs[idx].arch & ok_arch)
1718 && ! archs[idx].alias)
1719 {
1720 if (got_one)
1721 {
1722 strcpy (cp, " or ");
1723 cp += strlen (cp);
1724 }
1725 got_one = 1;
1726 strcpy (cp, archs[idx].name);
1727 cp += strlen (cp);
1728 }
1729 }
1730 }
1731 }
1732 cp = xmalloc (strlen (buf) + 1);
1733 strcpy (cp, buf);
1734 the_ins.error = cp;
1735 }
1736 else
1737 the_ins.error = "operands mismatch";
1738 return;
1739 } /* Fell off the end */
1740
1741 losing = 0;
1742 }
1743
1744 /* now assemble it */
1745
1746 the_ins.args = opcode->m_operands;
1747 the_ins.numargs = opcode->m_opnum;
1748 the_ins.numo = opcode->m_codenum;
1749 the_ins.opcode[0] = getone (opcode);
1750 the_ins.opcode[1] = gettwo (opcode);
1751
1752 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1753 {
1754 /* This switch is a doozy.
1755 Watch the first step; its a big one! */
1756 switch (s[0])
1757 {
1758
1759 case '*':
1760 case '~':
1761 case '%':
1762 case ';':
1763 case '@':
1764 case '!':
1765 case '&':
1766 case '$':
1767 case '?':
1768 case '/':
1769 case '`':
1770 case '<':
1771 case '>':
1772 case 'm':
1773 case 'n':
1774 case 'o':
1775 case 'p':
1776 #ifndef NO_68851
1777 case '|':
1778 #endif
1779 switch (opP->mode)
1780 {
1781 case IMMED:
1782 tmpreg = 0x3c; /* 7.4 */
1783 if (strchr ("bwl", s[1]))
1784 nextword = get_num (&opP->disp, 80);
1785 else
1786 nextword = get_num (&opP->disp, 0);
1787 if (isvar (&opP->disp))
1788 add_fix (s[1], &opP->disp, 0, 0);
1789 switch (s[1])
1790 {
1791 case 'b':
1792 if (!isbyte (nextword))
1793 opP->error = "operand out of range";
1794 addword (nextword);
1795 baseo = 0;
1796 break;
1797 case 'w':
1798 if (!isword (nextword))
1799 opP->error = "operand out of range";
1800 addword (nextword);
1801 baseo = 0;
1802 break;
1803 case 'W':
1804 if (!issword (nextword))
1805 opP->error = "operand out of range";
1806 addword (nextword);
1807 baseo = 0;
1808 break;
1809 case 'l':
1810 addword (nextword >> 16);
1811 addword (nextword);
1812 baseo = 0;
1813 break;
1814
1815 case 'f':
1816 baseo = 2;
1817 outro = 8;
1818 break;
1819 case 'F':
1820 baseo = 4;
1821 outro = 11;
1822 break;
1823 case 'x':
1824 baseo = 6;
1825 outro = 15;
1826 break;
1827 case 'p':
1828 baseo = 6;
1829 outro = -1;
1830 break;
1831 default:
1832 abort ();
1833 }
1834 if (!baseo)
1835 break;
1836
1837 /* We gotta put out some float */
1838 if (op (&opP->disp) != O_big)
1839 {
1840 valueT val;
1841 int gencnt;
1842
1843 /* Can other cases happen here? */
1844 if (op (&opP->disp) != O_constant)
1845 abort ();
1846
1847 val = (valueT) offs (&opP->disp);
1848 gencnt = 0;
1849 do
1850 {
1851 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1852 val >>= LITTLENUM_NUMBER_OF_BITS;
1853 ++gencnt;
1854 }
1855 while (val != 0);
1856 offs (&opP->disp) = gencnt;
1857 }
1858 if (offs (&opP->disp) > 0)
1859 {
1860 if (offs (&opP->disp) > baseo)
1861 {
1862 as_warn ("Bignum too big for %c format; truncated",
1863 s[1]);
1864 offs (&opP->disp) = baseo;
1865 }
1866 baseo -= offs (&opP->disp);
1867 while (baseo--)
1868 addword (0);
1869 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1870 offs (&opP->disp)--;
1871 --wordp)
1872 addword (*wordp);
1873 break;
1874 }
1875 gen_to_words (words, baseo, (long) outro);
1876 for (wordp = words; baseo--; wordp++)
1877 addword (*wordp);
1878 break;
1879 case DREG:
1880 tmpreg = opP->reg - DATA; /* 0.dreg */
1881 break;
1882 case AREG:
1883 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1884 break;
1885 case AINDR:
1886 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1887 break;
1888 case ADEC:
1889 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1890 break;
1891 case AINC:
1892 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1893 break;
1894 case DISP:
1895
1896 nextword = get_num (&opP->disp, 80);
1897
1898 if (opP->reg == PC
1899 && ! isvar (&opP->disp)
1900 && m68k_abspcadd)
1901 {
1902 opP->disp.exp.X_op = O_symbol;
1903 #ifndef BFD_ASSEMBLER
1904 opP->disp.exp.X_add_symbol = &abs_symbol;
1905 #else
1906 opP->disp.exp.X_add_symbol =
1907 section_symbol (absolute_section);
1908 #endif
1909 }
1910
1911 /* Force into index mode. Hope this works */
1912
1913 /* We do the first bit for 32-bit displacements, and the
1914 second bit for 16 bit ones. It is possible that we
1915 should make the default be WORD instead of LONG, but
1916 I think that'd break GCC, so we put up with a little
1917 inefficiency for the sake of working output. */
1918
1919 if (!issword (nextword)
1920 || (isvar (&opP->disp)
1921 && ((opP->disp.size == SIZE_UNSPEC
1922 && flag_short_refs == 0
1923 && cpu_of_arch (current_architecture) >= m68020)
1924 || opP->disp.size == SIZE_LONG)))
1925 {
1926 if (cpu_of_arch (current_architecture) < m68020)
1927 opP->error =
1928 "displacement too large for this architecture; needs 68020 or higher";
1929 if (opP->reg == PC)
1930 tmpreg = 0x3B; /* 7.3 */
1931 else
1932 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1933 if (isvar (&opP->disp))
1934 {
1935 if (opP->reg == PC)
1936 {
1937 if (opP->disp.size == SIZE_LONG
1938 #ifdef OBJ_ELF
1939 /* If the displacement needs pic
1940 relocation it cannot be relaxed. */
1941 || opP->disp.pic_reloc != pic_none
1942 #endif
1943 )
1944 {
1945 addword (0x0170);
1946 add_fix ('l', &opP->disp, 1, 2);
1947 }
1948 else
1949 {
1950 add_frag (adds (&opP->disp),
1951 offs (&opP->disp),
1952 TAB (PCLEA, SZ_UNDEF));
1953 break;
1954 }
1955 }
1956 else
1957 {
1958 addword (0x0170);
1959 add_fix ('l', &opP->disp, 0, 0);
1960 }
1961 }
1962 else
1963 addword (0x0170);
1964 addword (nextword >> 16);
1965 }
1966 else
1967 {
1968 if (opP->reg == PC)
1969 tmpreg = 0x3A; /* 7.2 */
1970 else
1971 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1972
1973 if (isvar (&opP->disp))
1974 {
1975 if (opP->reg == PC)
1976 {
1977 add_fix ('w', &opP->disp, 1, 0);
1978 }
1979 else
1980 add_fix ('w', &opP->disp, 0, 0);
1981 }
1982 }
1983 addword (nextword);
1984 break;
1985
1986 case POST:
1987 case PRE:
1988 case BASE:
1989 nextword = 0;
1990 baseo = get_num (&opP->disp, 80);
1991 if (opP->mode == POST || opP->mode == PRE)
1992 outro = get_num (&opP->odisp, 80);
1993 /* Figure out the `addressing mode'.
1994 Also turn on the BASE_DISABLE bit, if needed. */
1995 if (opP->reg == PC || opP->reg == ZPC)
1996 {
1997 tmpreg = 0x3b; /* 7.3 */
1998 if (opP->reg == ZPC)
1999 nextword |= 0x80;
2000 }
2001 else if (opP->reg == 0)
2002 {
2003 nextword |= 0x80;
2004 tmpreg = 0x30; /* 6.garbage */
2005 }
2006 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2007 {
2008 nextword |= 0x80;
2009 tmpreg = 0x30 + opP->reg - ZADDR0;
2010 }
2011 else
2012 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2013
2014 siz1 = opP->disp.size;
2015 if (opP->mode == POST || opP->mode == PRE)
2016 siz2 = opP->odisp.size;
2017 else
2018 siz2 = SIZE_UNSPEC;
2019
2020 /* Index register stuff */
2021 if (opP->index.reg != 0
2022 && opP->index.reg >= DATA
2023 && opP->index.reg <= ADDR7)
2024 {
2025 nextword |= (opP->index.reg - DATA) << 12;
2026
2027 if (opP->index.size == SIZE_LONG
2028 || (opP->index.size == SIZE_UNSPEC
2029 && m68k_index_width_default == SIZE_LONG))
2030 nextword |= 0x800;
2031
2032 if ((opP->index.scale != 1
2033 && cpu_of_arch (current_architecture) < m68020)
2034 || (opP->index.scale == 8
2035 && current_architecture == mcf5200))
2036 {
2037 opP->error =
2038 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
2039 }
2040
2041 switch (opP->index.scale)
2042 {
2043 case 1:
2044 break;
2045 case 2:
2046 nextword |= 0x200;
2047 break;
2048 case 4:
2049 nextword |= 0x400;
2050 break;
2051 case 8:
2052 nextword |= 0x600;
2053 break;
2054 default:
2055 abort ();
2056 }
2057 /* IF its simple,
2058 GET US OUT OF HERE! */
2059
2060 /* Must be INDEX, with an index register. Address
2061 register cannot be ZERO-PC, and either :b was
2062 forced, or we know it will fit. For a 68000 or
2063 68010, force this mode anyways, because the
2064 larger modes aren't supported. */
2065 if (opP->mode == BASE
2066 && ((opP->reg >= ADDR0
2067 && opP->reg <= ADDR7)
2068 || opP->reg == PC))
2069 {
2070 if (siz1 == SIZE_BYTE
2071 || cpu_of_arch (current_architecture) < m68020
2072 || (siz1 == SIZE_UNSPEC
2073 && ! isvar (&opP->disp)
2074 && issbyte (baseo)))
2075 {
2076 nextword += baseo & 0xff;
2077 addword (nextword);
2078 if (isvar (&opP->disp))
2079 {
2080 /* Do a byte relocation. If it doesn't
2081 fit (possible on m68000) let the
2082 fixup processing complain later. */
2083 if (opP->reg == PC)
2084 add_fix ('B', &opP->disp, 1, 1);
2085 else
2086 add_fix ('B', &opP->disp, 0, 0);
2087 }
2088 else if (siz1 != SIZE_BYTE)
2089 {
2090 if (siz1 != SIZE_UNSPEC)
2091 as_warn ("Forcing byte displacement");
2092 if (! issbyte (baseo))
2093 opP->error = "byte displacement out of range";
2094 }
2095
2096 break;
2097 }
2098 else if (siz1 == SIZE_UNSPEC
2099 && opP->reg == PC
2100 && isvar (&opP->disp)
2101 && subs (&opP->disp) == NULL
2102 #ifdef OBJ_ELF
2103 /* If the displacement needs pic
2104 relocation it cannot be relaxed. */
2105 && opP->disp.pic_reloc == pic_none
2106 #endif
2107 )
2108 {
2109 /* The code in md_convert_frag_1 needs to be
2110 able to adjust nextword. Call frag_grow
2111 to ensure that we have enough space in
2112 the frag obstack to make all the bytes
2113 contiguous. */
2114 frag_grow (14);
2115 nextword += baseo & 0xff;
2116 addword (nextword);
2117 add_frag (adds (&opP->disp), offs (&opP->disp),
2118 TAB (PCINDEX, SZ_UNDEF));
2119
2120 break;
2121 }
2122 }
2123 }
2124 else
2125 {
2126 nextword |= 0x40; /* No index reg */
2127 if (opP->index.reg >= ZDATA0
2128 && opP->index.reg <= ZDATA7)
2129 nextword |= (opP->index.reg - ZDATA0) << 12;
2130 else if (opP->index.reg >= ZADDR0
2131 || opP->index.reg <= ZADDR7)
2132 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2133 }
2134
2135 /* It isn't simple. */
2136
2137 if (cpu_of_arch (current_architecture) < m68020)
2138 opP->error =
2139 "invalid operand mode for this architecture; needs 68020 or higher";
2140
2141 nextword |= 0x100;
2142 /* If the guy specified a width, we assume that it is
2143 wide enough. Maybe it isn't. If so, we lose. */
2144 switch (siz1)
2145 {
2146 case SIZE_UNSPEC:
2147 if (isvar (&opP->disp)
2148 ? m68k_rel32
2149 : ! issword (baseo))
2150 {
2151 siz1 = SIZE_LONG;
2152 nextword |= 0x30;
2153 }
2154 else if (! isvar (&opP->disp) && baseo == 0)
2155 nextword |= 0x10;
2156 else
2157 {
2158 nextword |= 0x20;
2159 siz1 = SIZE_WORD;
2160 }
2161 break;
2162 case SIZE_BYTE:
2163 as_warn (":b not permitted; defaulting to :w");
2164 /* Fall through. */
2165 case SIZE_WORD:
2166 nextword |= 0x20;
2167 break;
2168 case SIZE_LONG:
2169 nextword |= 0x30;
2170 break;
2171 }
2172
2173 /* Figure out innner displacement stuff */
2174 if (opP->mode == POST || opP->mode == PRE)
2175 {
2176 if (cpu_of_arch (current_architecture) & cpu32)
2177 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
2178 switch (siz2)
2179 {
2180 case SIZE_UNSPEC:
2181 if (isvar (&opP->odisp)
2182 ? m68k_rel32
2183 : ! issword (outro))
2184 {
2185 siz2 = SIZE_LONG;
2186 nextword |= 0x3;
2187 }
2188 else if (! isvar (&opP->odisp) && outro == 0)
2189 nextword |= 0x1;
2190 else
2191 {
2192 nextword |= 0x2;
2193 siz2 = SIZE_WORD;
2194 }
2195 break;
2196 case 1:
2197 as_warn (":b not permitted; defaulting to :w");
2198 /* Fall through. */
2199 case 2:
2200 nextword |= 0x2;
2201 break;
2202 case 3:
2203 nextword |= 0x3;
2204 break;
2205 }
2206 if (opP->mode == POST
2207 && (nextword & 0x40) == 0)
2208 nextword |= 0x04;
2209 }
2210 addword (nextword);
2211
2212 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2213 {
2214 if (opP->reg == PC || opP->reg == ZPC)
2215 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2216 else
2217 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2218 }
2219 if (siz1 == SIZE_LONG)
2220 addword (baseo >> 16);
2221 if (siz1 != SIZE_UNSPEC)
2222 addword (baseo);
2223
2224 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2225 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2226 if (siz2 == SIZE_LONG)
2227 addword (outro >> 16);
2228 if (siz2 != SIZE_UNSPEC)
2229 addword (outro);
2230
2231 break;
2232
2233 case ABSL:
2234 nextword = get_num (&opP->disp, 80);
2235 switch (opP->disp.size)
2236 {
2237 default:
2238 abort ();
2239 case SIZE_UNSPEC:
2240 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2241 {
2242 tmpreg = 0x38; /* 7.0 */
2243 addword (nextword);
2244 break;
2245 }
2246 /* Don't generate pc relative code on 68010 and
2247 68000. */
2248 if (isvar (&opP->disp)
2249 && !subs (&opP->disp)
2250 && adds (&opP->disp)
2251 #ifdef OBJ_ELF
2252 /* If the displacement needs pic relocation it
2253 cannot be relaxed. */
2254 && opP->disp.pic_reloc == pic_none
2255 #endif
2256 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2257 && HAVE_LONG_BRANCH(current_architecture)
2258 && !flag_long_jumps
2259 && !strchr ("~%&$?", s[0]))
2260 {
2261 tmpreg = 0x3A; /* 7.2 */
2262 add_frag (adds (&opP->disp),
2263 offs (&opP->disp),
2264 TAB (PCREL, SZ_UNDEF));
2265 break;
2266 }
2267 /* Fall through into long */
2268 case SIZE_LONG:
2269 if (isvar (&opP->disp))
2270 add_fix ('l', &opP->disp, 0, 0);
2271
2272 tmpreg = 0x39;/* 7.1 mode */
2273 addword (nextword >> 16);
2274 addword (nextword);
2275 break;
2276
2277 case SIZE_WORD: /* Word */
2278 if (isvar (&opP->disp))
2279 add_fix ('w', &opP->disp, 0, 0);
2280
2281 tmpreg = 0x38;/* 7.0 mode */
2282 addword (nextword);
2283 break;
2284 }
2285 break;
2286 case CONTROL:
2287 case FPREG:
2288 default:
2289 as_bad ("unknown/incorrect operand");
2290 /* abort(); */
2291 }
2292 install_gen_operand (s[1], tmpreg);
2293 break;
2294
2295 case '#':
2296 case '^':
2297 switch (s[1])
2298 { /* JF: I hate floating point! */
2299 case 'j':
2300 tmpreg = 70;
2301 break;
2302 case '8':
2303 tmpreg = 20;
2304 break;
2305 case 'C':
2306 tmpreg = 50;
2307 break;
2308 case '3':
2309 default:
2310 tmpreg = 80;
2311 break;
2312 }
2313 tmpreg = get_num (&opP->disp, tmpreg);
2314 if (isvar (&opP->disp))
2315 add_fix (s[1], &opP->disp, 0, 0);
2316 switch (s[1])
2317 {
2318 case 'b': /* Danger: These do no check for
2319 certain types of overflow.
2320 user beware! */
2321 if (!isbyte (tmpreg))
2322 opP->error = "out of range";
2323 insop (tmpreg, opcode);
2324 if (isvar (&opP->disp))
2325 the_ins.reloc[the_ins.nrel - 1].n =
2326 (opcode->m_codenum) * 2 + 1;
2327 break;
2328 case 'B':
2329 if (!issbyte (tmpreg))
2330 opP->error = "out of range";
2331 opcode->m_opcode |= tmpreg;
2332 if (isvar (&opP->disp))
2333 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2334 break;
2335 case 'w':
2336 if (!isword (tmpreg))
2337 opP->error = "out of range";
2338 insop (tmpreg, opcode);
2339 if (isvar (&opP->disp))
2340 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2341 break;
2342 case 'W':
2343 if (!issword (tmpreg))
2344 opP->error = "out of range";
2345 insop (tmpreg, opcode);
2346 if (isvar (&opP->disp))
2347 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2348 break;
2349 case 'l':
2350 /* Because of the way insop works, we put these two out
2351 backwards. */
2352 insop (tmpreg, opcode);
2353 insop (tmpreg >> 16, opcode);
2354 if (isvar (&opP->disp))
2355 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2356 break;
2357 case '3':
2358 tmpreg &= 0xFF;
2359 case '8':
2360 case 'C':
2361 install_operand (s[1], tmpreg);
2362 break;
2363 default:
2364 abort ();
2365 }
2366 break;
2367
2368 case '+':
2369 case '-':
2370 case 'A':
2371 case 'a':
2372 install_operand (s[1], opP->reg - ADDR);
2373 break;
2374
2375 case 'B':
2376 tmpreg = get_num (&opP->disp, 80);
2377 switch (s[1])
2378 {
2379 case 'B':
2380 /* The pc_fix argument winds up in fx_pcrel_adjust,
2381 which is a char, and may therefore be unsigned. We
2382 want to pass -1, but we pass 64 instead, and convert
2383 back in md_pcrel_from. */
2384 add_fix ('B', &opP->disp, 1, 64);
2385 break;
2386 case 'W':
2387 add_fix ('w', &opP->disp, 1, 0);
2388 addword (0);
2389 break;
2390 case 'L':
2391 long_branch:
2392 if (!HAVE_LONG_BRANCH(current_architecture))
2393 as_warn ("Can't use long branches on 68000/68010/5200");
2394 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2395 add_fix ('l', &opP->disp, 1, 0);
2396 addword (0);
2397 addword (0);
2398 break;
2399 case 'g':
2400 if (subs (&opP->disp)) /* We can't relax it */
2401 goto long_branch;
2402
2403 #ifdef OBJ_ELF
2404 /* If the displacement needs pic relocation it cannot be
2405 relaxed. */
2406 if (opP->disp.pic_reloc != pic_none)
2407 goto long_branch;
2408 #endif
2409
2410 /* This could either be a symbol, or an absolute
2411 address. No matter, the frag hacking will finger it
2412 out. Not quite: it can't switch from BRANCH to
2413 BCC68000 for the case where opnd is absolute (it
2414 needs to use the 68000 hack since no conditional abs
2415 jumps). */
2416 if (( !HAVE_LONG_BRANCH(current_architecture)
2417 || (0 == adds (&opP->disp)))
2418 && (the_ins.opcode[0] >= 0x6200)
2419 && (the_ins.opcode[0] <= 0x6f00))
2420 add_frag (adds (&opP->disp), offs (&opP->disp),
2421 TAB (BCC68000, SZ_UNDEF));
2422 else
2423 add_frag (adds (&opP->disp), offs (&opP->disp),
2424 TAB (ABRANCH, SZ_UNDEF));
2425 break;
2426 case 'w':
2427 if (isvar (&opP->disp))
2428 {
2429 #if 1
2430 /* check for DBcc instruction */
2431 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2432 {
2433 /* size varies if patch */
2434 /* needed for long form */
2435 add_frag (adds (&opP->disp), offs (&opP->disp),
2436 TAB (DBCC, SZ_UNDEF));
2437 break;
2438 }
2439 #endif
2440 add_fix ('w', &opP->disp, 1, 0);
2441 }
2442 addword (0);
2443 break;
2444 case 'C': /* Fixed size LONG coproc branches */
2445 add_fix ('l', &opP->disp, 1, 0);
2446 addword (0);
2447 addword (0);
2448 break;
2449 case 'c': /* Var size Coprocesssor branches */
2450 if (subs (&opP->disp))
2451 {
2452 add_fix ('l', &opP->disp, 1, 0);
2453 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2454 }
2455 else if (adds (&opP->disp))
2456 add_frag (adds (&opP->disp), offs (&opP->disp),
2457 TAB (FBRANCH, SZ_UNDEF));
2458 else
2459 {
2460 /* add_frag((symbolS *) 0, offs(&opP->disp),
2461 TAB(FBRANCH,SHORT)); */
2462 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2463 add_fix ('l', &opP->disp, 1, 0);
2464 addword (0);
2465 addword (0);
2466 }
2467 break;
2468 default:
2469 abort ();
2470 }
2471 break;
2472
2473 case 'C': /* Ignore it */
2474 break;
2475
2476 case 'd': /* JF this is a kludge */
2477 install_operand ('s', opP->reg - ADDR);
2478 tmpreg = get_num (&opP->disp, 80);
2479 if (!issword (tmpreg))
2480 {
2481 as_warn ("Expression out of range, using 0");
2482 tmpreg = 0;
2483 }
2484 addword (tmpreg);
2485 break;
2486
2487 case 'D':
2488 install_operand (s[1], opP->reg - DATA);
2489 break;
2490
2491 case 'F':
2492 install_operand (s[1], opP->reg - FP0);
2493 break;
2494
2495 case 'I':
2496 tmpreg = opP->reg - COP0;
2497 install_operand (s[1], tmpreg);
2498 break;
2499
2500 case 'J': /* JF foo */
2501 switch (opP->reg)
2502 {
2503 case SFC:
2504 tmpreg = 0x000;
2505 break;
2506 case DFC:
2507 tmpreg = 0x001;
2508 break;
2509 case CACR:
2510 tmpreg = 0x002;
2511 break;
2512 case TC:
2513 tmpreg = 0x003;
2514 break;
2515 case ITT0:
2516 tmpreg = 0x004;
2517 break;
2518 case ITT1:
2519 tmpreg = 0x005;
2520 break;
2521 case DTT0:
2522 tmpreg = 0x006;
2523 break;
2524 case DTT1:
2525 tmpreg = 0x007;
2526 break;
2527 case BUSCR:
2528 tmpreg = 0x008;
2529 break;
2530
2531 case USP:
2532 tmpreg = 0x800;
2533 break;
2534 case VBR:
2535 tmpreg = 0x801;
2536 break;
2537 case CAAR:
2538 tmpreg = 0x802;
2539 break;
2540 case MSP:
2541 tmpreg = 0x803;
2542 break;
2543 case ISP:
2544 tmpreg = 0x804;
2545 break;
2546 case MMUSR:
2547 tmpreg = 0x805;
2548 break;
2549 case URP:
2550 tmpreg = 0x806;
2551 break;
2552 case SRP:
2553 tmpreg = 0x807;
2554 break;
2555 case PCR:
2556 tmpreg = 0x808;
2557 break;
2558 case ROMBAR:
2559 tmpreg = 0xC00;
2560 break;
2561 case RAMBAR0:
2562 tmpreg = 0xC04;
2563 break;
2564 case RAMBAR1:
2565 tmpreg = 0xC05;
2566 break;
2567 case MBAR:
2568 tmpreg = 0xC0F;
2569 break;
2570 default:
2571 abort ();
2572 }
2573 install_operand (s[1], tmpreg);
2574 break;
2575
2576 case 'k':
2577 tmpreg = get_num (&opP->disp, 55);
2578 install_operand (s[1], tmpreg & 0x7f);
2579 break;
2580
2581 case 'l':
2582 tmpreg = opP->mask;
2583 if (s[1] == 'w')
2584 {
2585 if (tmpreg & 0x7FF0000)
2586 as_bad ("Floating point register in register list");
2587 insop (reverse_16_bits (tmpreg), opcode);
2588 }
2589 else
2590 {
2591 if (tmpreg & 0x700FFFF)
2592 as_bad ("Wrong register in floating-point reglist");
2593 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2594 }
2595 break;
2596
2597 case 'L':
2598 tmpreg = opP->mask;
2599 if (s[1] == 'w')
2600 {
2601 if (tmpreg & 0x7FF0000)
2602 as_bad ("Floating point register in register list");
2603 insop (tmpreg, opcode);
2604 }
2605 else if (s[1] == '8')
2606 {
2607 if (tmpreg & 0x0FFFFFF)
2608 as_bad ("incorrect register in reglist");
2609 install_operand (s[1], tmpreg >> 24);
2610 }
2611 else
2612 {
2613 if (tmpreg & 0x700FFFF)
2614 as_bad ("wrong register in floating-point reglist");
2615 else
2616 install_operand (s[1], tmpreg >> 16);
2617 }
2618 break;
2619
2620 case 'M':
2621 install_operand (s[1], get_num (&opP->disp, 60));
2622 break;
2623
2624 case 'O':
2625 tmpreg = ((opP->mode == DREG)
2626 ? 0x20 + opP->reg - DATA
2627 : (get_num (&opP->disp, 40) & 0x1F));
2628 install_operand (s[1], tmpreg);
2629 break;
2630
2631 case 'Q':
2632 tmpreg = get_num (&opP->disp, 10);
2633 if (tmpreg == 8)
2634 tmpreg = 0;
2635 install_operand (s[1], tmpreg);
2636 break;
2637
2638 case 'R':
2639 /* This depends on the fact that ADDR registers are eight
2640 more than their corresponding DATA regs, so the result
2641 will have the ADDR_REG bit set */
2642 install_operand (s[1], opP->reg - DATA);
2643 break;
2644
2645 case 'r':
2646 if (opP->mode == AINDR)
2647 install_operand (s[1], opP->reg - DATA);
2648 else
2649 install_operand (s[1], opP->index.reg - DATA);
2650 break;
2651
2652 case 's':
2653 if (opP->reg == FPI)
2654 tmpreg = 0x1;
2655 else if (opP->reg == FPS)
2656 tmpreg = 0x2;
2657 else if (opP->reg == FPC)
2658 tmpreg = 0x4;
2659 else
2660 abort ();
2661 install_operand (s[1], tmpreg);
2662 break;
2663
2664 case 'S': /* Ignore it */
2665 break;
2666
2667 case 'T':
2668 install_operand (s[1], get_num (&opP->disp, 30));
2669 break;
2670
2671 case 'U': /* Ignore it */
2672 break;
2673
2674 case 'c':
2675 switch (opP->reg)
2676 {
2677 case NC:
2678 tmpreg = 0;
2679 break;
2680 case DC:
2681 tmpreg = 1;
2682 break;
2683 case IC:
2684 tmpreg = 2;
2685 break;
2686 case BC:
2687 tmpreg = 3;
2688 break;
2689 default:
2690 as_fatal ("failed sanity check");
2691 } /* switch on cache token */
2692 install_operand (s[1], tmpreg);
2693 break;
2694 #ifndef NO_68851
2695 /* JF: These are out of order, I fear. */
2696 case 'f':
2697 switch (opP->reg)
2698 {
2699 case SFC:
2700 tmpreg = 0;
2701 break;
2702 case DFC:
2703 tmpreg = 1;
2704 break;
2705 default:
2706 abort ();
2707 }
2708 install_operand (s[1], tmpreg);
2709 break;
2710
2711 case '0':
2712 case '1':
2713 case '2':
2714 switch (opP->reg)
2715 {
2716 case TC:
2717 tmpreg = 0;
2718 break;
2719 case CAL:
2720 tmpreg = 4;
2721 break;
2722 case VAL:
2723 tmpreg = 5;
2724 break;
2725 case SCC:
2726 tmpreg = 6;
2727 break;
2728 case AC:
2729 tmpreg = 7;
2730 break;
2731 default:
2732 abort ();
2733 }
2734 install_operand (s[1], tmpreg);
2735 break;
2736
2737 case 'V':
2738 if (opP->reg == VAL)
2739 break;
2740 abort ();
2741
2742 case 'W':
2743 switch (opP->reg)
2744 {
2745 case DRP:
2746 tmpreg = 1;
2747 break;
2748 case SRP:
2749 tmpreg = 2;
2750 break;
2751 case CRP:
2752 tmpreg = 3;
2753 break;
2754 default:
2755 abort ();
2756 }
2757 install_operand (s[1], tmpreg);
2758 break;
2759
2760 case 'X':
2761 switch (opP->reg)
2762 {
2763 case BAD:
2764 case BAD + 1:
2765 case BAD + 2:
2766 case BAD + 3:
2767 case BAD + 4:
2768 case BAD + 5:
2769 case BAD + 6:
2770 case BAD + 7:
2771 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2772 break;
2773
2774 case BAC:
2775 case BAC + 1:
2776 case BAC + 2:
2777 case BAC + 3:
2778 case BAC + 4:
2779 case BAC + 5:
2780 case BAC + 6:
2781 case BAC + 7:
2782 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2783 break;
2784
2785 default:
2786 abort ();
2787 }
2788 install_operand (s[1], tmpreg);
2789 break;
2790 case 'Y':
2791 know (opP->reg == PSR);
2792 break;
2793 case 'Z':
2794 know (opP->reg == PCSR);
2795 break;
2796 #endif /* m68851 */
2797 case '3':
2798 switch (opP->reg)
2799 {
2800 case TT0:
2801 tmpreg = 2;
2802 break;
2803 case TT1:
2804 tmpreg = 3;
2805 break;
2806 default:
2807 abort ();
2808 }
2809 install_operand (s[1], tmpreg);
2810 break;
2811 case 't':
2812 tmpreg = get_num (&opP->disp, 20);
2813 install_operand (s[1], tmpreg);
2814 break;
2815 case '_': /* used only for move16 absolute 32-bit address */
2816 tmpreg = get_num (&opP->disp, 80);
2817 addword (tmpreg >> 16);
2818 addword (tmpreg & 0xFFFF);
2819 break;
2820 default:
2821 abort ();
2822 }
2823 }
2824
2825 /* By the time whe get here (FINALLY) the_ins contains the complete
2826 instruction, ready to be emitted. . . */
2827 }
2828
2829 static int
2830 reverse_16_bits (in)
2831 int in;
2832 {
2833 int out = 0;
2834 int n;
2835
2836 static int mask[16] =
2837 {
2838 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2839 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2840 };
2841 for (n = 0; n < 16; n++)
2842 {
2843 if (in & mask[n])
2844 out |= mask[15 - n];
2845 }
2846 return out;
2847 } /* reverse_16_bits() */
2848
2849 static int
2850 reverse_8_bits (in)
2851 int in;
2852 {
2853 int out = 0;
2854 int n;
2855
2856 static int mask[8] =
2857 {
2858 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2859 };
2860
2861 for (n = 0; n < 8; n++)
2862 {
2863 if (in & mask[n])
2864 out |= mask[7 - n];
2865 }
2866 return out;
2867 } /* reverse_8_bits() */
2868
2869 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2870 (that value is chosen in the frag_var call in md_assemble). TYPE
2871 is the subtype of the frag to be generated; its primary type is
2872 rs_machine_dependent.
2873
2874 The TYPE parameter is also used by md_convert_frag_1 and
2875 md_estimate_size_before_relax. The appropriate type of fixup will
2876 be emitted by md_convert_frag_1.
2877
2878 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2879 static void
2880 install_operand (mode, val)
2881 int mode;
2882 int val;
2883 {
2884 switch (mode)
2885 {
2886 case 's':
2887 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2888 break;
2889 case 'd':
2890 the_ins.opcode[0] |= val << 9;
2891 break;
2892 case '1':
2893 the_ins.opcode[1] |= val << 12;
2894 break;
2895 case '2':
2896 the_ins.opcode[1] |= val << 6;
2897 break;
2898 case '3':
2899 the_ins.opcode[1] |= val;
2900 break;
2901 case '4':
2902 the_ins.opcode[2] |= val << 12;
2903 break;
2904 case '5':
2905 the_ins.opcode[2] |= val << 6;
2906 break;
2907 case '6':
2908 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2909 three words long! */
2910 the_ins.numo++;
2911 the_ins.opcode[2] |= val;
2912 break;
2913 case '7':
2914 the_ins.opcode[1] |= val << 7;
2915 break;
2916 case '8':
2917 the_ins.opcode[1] |= val << 10;
2918 break;
2919 #ifndef NO_68851
2920 case '9':
2921 the_ins.opcode[1] |= val << 5;
2922 break;
2923 #endif
2924
2925 case 't':
2926 the_ins.opcode[1] |= (val << 10) | (val << 7);
2927 break;
2928 case 'D':
2929 the_ins.opcode[1] |= (val << 12) | val;
2930 break;
2931 case 'g':
2932 the_ins.opcode[0] |= val = 0xff;
2933 break;
2934 case 'i':
2935 the_ins.opcode[0] |= val << 9;
2936 break;
2937 case 'C':
2938 the_ins.opcode[1] |= val;
2939 break;
2940 case 'j':
2941 the_ins.opcode[1] |= val;
2942 the_ins.numo++; /* What a hack */
2943 break;
2944 case 'k':
2945 the_ins.opcode[1] |= val << 4;
2946 break;
2947 case 'b':
2948 case 'w':
2949 case 'W':
2950 case 'l':
2951 break;
2952 case 'e':
2953 the_ins.opcode[0] |= (val << 6);
2954 break;
2955 case 'L':
2956 the_ins.opcode[1] = (val >> 16);
2957 the_ins.opcode[2] = val & 0xffff;
2958 break;
2959 case 'c':
2960 default:
2961 as_fatal ("failed sanity check.");
2962 }
2963 } /* install_operand() */
2964
2965 static void
2966 install_gen_operand (mode, val)
2967 int mode;
2968 int val;
2969 {
2970 switch (mode)
2971 {
2972 case 's':
2973 the_ins.opcode[0] |= val;
2974 break;
2975 case 'd':
2976 /* This is a kludge!!! */
2977 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2978 break;
2979 case 'b':
2980 case 'w':
2981 case 'l':
2982 case 'f':
2983 case 'F':
2984 case 'x':
2985 case 'p':
2986 the_ins.opcode[0] |= val;
2987 break;
2988 /* more stuff goes here */
2989 default:
2990 as_fatal ("failed sanity check.");
2991 }
2992 } /* install_gen_operand() */
2993
2994 /*
2995 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2996 * then deal with the bitfield hack.
2997 */
2998
2999 static char *
3000 crack_operand (str, opP)
3001 register char *str;
3002 register struct m68k_op *opP;
3003 {
3004 register int parens;
3005 register int c;
3006 register char *beg_str;
3007 int inquote = 0;
3008
3009 if (!str)
3010 {
3011 return str;
3012 }
3013 beg_str = str;
3014 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3015 {
3016 if (! inquote)
3017 {
3018 if (*str == '(')
3019 parens++;
3020 else if (*str == ')')
3021 {
3022 if (!parens)
3023 { /* ERROR */
3024 opP->error = "Extra )";
3025 return str;
3026 }
3027 --parens;
3028 }
3029 }
3030 if (flag_mri && *str == '\'')
3031 inquote = ! inquote;
3032 }
3033 if (!*str && parens)
3034 { /* ERROR */
3035 opP->error = "Missing )";
3036 return str;
3037 }
3038 c = *str;
3039 *str = '\0';
3040 if (m68k_ip_op (beg_str, opP) != 0)
3041 {
3042 *str = c;
3043 return str;
3044 }
3045 *str = c;
3046 if (c == '}')
3047 c = *++str; /* JF bitfield hack */
3048 if (c)
3049 {
3050 c = *++str;
3051 if (!c)
3052 as_bad ("Missing operand");
3053 }
3054 return str;
3055 }
3056
3057 /* This is the guts of the machine-dependent assembler. STR points to a
3058 machine dependent instruction. This function is supposed to emit
3059 the frags/bytes it assembles to.
3060 */
3061
3062 void
3063 insert_reg (regname, regnum)
3064 char *regname;
3065 int regnum;
3066 {
3067 char buf[100];
3068 int i;
3069
3070 #ifdef REGISTER_PREFIX
3071 if (!flag_reg_prefix_optional)
3072 {
3073 buf[0] = REGISTER_PREFIX;
3074 strcpy (buf + 1, regname);
3075 regname = buf;
3076 }
3077 #endif
3078
3079 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3080 &zero_address_frag));
3081
3082 for (i = 0; regname[i]; i++)
3083 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3084 buf[i] = '\0';
3085
3086 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3087 &zero_address_frag));
3088 }
3089
3090 struct init_entry
3091 {
3092 const char *name;
3093 int number;
3094 };
3095
3096 static const struct init_entry init_table[] =
3097 {
3098 { "d0", DATA0 },
3099 { "d1", DATA1 },
3100 { "d2", DATA2 },
3101 { "d3", DATA3 },
3102 { "d4", DATA4 },
3103 { "d5", DATA5 },
3104 { "d6", DATA6 },
3105 { "d7", DATA7 },
3106 { "a0", ADDR0 },
3107 { "a1", ADDR1 },
3108 { "a2", ADDR2 },
3109 { "a3", ADDR3 },
3110 { "a4", ADDR4 },
3111 { "a5", ADDR5 },
3112 { "a6", ADDR6 },
3113 { "fp", ADDR6 },
3114 { "a7", ADDR7 },
3115 { "sp", ADDR7 },
3116 { "ssp", ADDR7 },
3117 { "fp0", FP0 },
3118 { "fp1", FP1 },
3119 { "fp2", FP2 },
3120 { "fp3", FP3 },
3121 { "fp4", FP4 },
3122 { "fp5", FP5 },
3123 { "fp6", FP6 },
3124 { "fp7", FP7 },
3125 { "fpi", FPI },
3126 { "fpiar", FPI },
3127 { "fpc", FPI },
3128 { "fps", FPS },
3129 { "fpsr", FPS },
3130 { "fpc", FPC },
3131 { "fpcr", FPC },
3132 { "control", FPC },
3133 { "status", FPS },
3134 { "iaddr", FPI },
3135
3136 { "cop0", COP0 },
3137 { "cop1", COP1 },
3138 { "cop2", COP2 },
3139 { "cop3", COP3 },
3140 { "cop4", COP4 },
3141 { "cop5", COP5 },
3142 { "cop6", COP6 },
3143 { "cop7", COP7 },
3144 { "pc", PC },
3145 { "zpc", ZPC },
3146 { "sr", SR },
3147
3148 { "ccr", CCR },
3149 { "cc", CCR },
3150
3151 /* control registers */
3152 { "sfc", SFC }, /* Source Function Code */
3153 { "sfcr", SFC },
3154 { "dfc", DFC }, /* Destination Function Code */
3155 { "dfcr", DFC },
3156 { "cacr", CACR }, /* Cache Control Register */
3157 { "caar", CAAR }, /* Cache Address Register */
3158
3159 { "usp", USP }, /* User Stack Pointer */
3160 { "vbr", VBR }, /* Vector Base Register */
3161 { "msp", MSP }, /* Master Stack Pointer */
3162 { "isp", ISP }, /* Interrupt Stack Pointer */
3163
3164 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3165 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3166 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3167 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3168
3169 /* 68ec040 versions of same */
3170 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3171 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3172 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3173 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3174
3175 /* mcf5200 versions of same. The ColdFire programmer's reference
3176 manual indicated that the order is 2,3,0,1, but Ken Rose
3177 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3178 { "acr0", ITT0 }, /* Access Control Unit 0 */
3179 { "acr1", ITT1 }, /* Access Control Unit 1 */
3180 { "acr2", DTT0 }, /* Access Control Unit 2 */
3181 { "acr3", DTT1 }, /* Access Control Unit 3 */
3182
3183 { "tc", TC }, /* MMU Translation Control Register */
3184 { "tcr", TC },
3185
3186 { "mmusr", MMUSR }, /* MMU Status Register */
3187 { "srp", SRP }, /* User Root Pointer */
3188 { "urp", URP }, /* Supervisor Root Pointer */
3189
3190 { "buscr", BUSCR },
3191 { "pcr", PCR },
3192
3193 { "rombar", ROMBAR }, /* ROM Base Address Register */
3194 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3195 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3196 { "mbar", MBAR }, /* Module Base Address Register */
3197 /* end of control registers */
3198
3199 { "ac", AC },
3200 { "bc", BC },
3201 { "cal", CAL },
3202 { "crp", CRP },
3203 { "drp", DRP },
3204 { "pcsr", PCSR },
3205 { "psr", PSR },
3206 { "scc", SCC },
3207 { "val", VAL },
3208 { "bad0", BAD0 },
3209 { "bad1", BAD1 },
3210 { "bad2", BAD2 },
3211 { "bad3", BAD3 },
3212 { "bad4", BAD4 },
3213 { "bad5", BAD5 },
3214 { "bad6", BAD6 },
3215 { "bad7", BAD7 },
3216 { "bac0", BAC0 },
3217 { "bac1", BAC1 },
3218 { "bac2", BAC2 },
3219 { "bac3", BAC3 },
3220 { "bac4", BAC4 },
3221 { "bac5", BAC5 },
3222 { "bac6", BAC6 },
3223 { "bac7", BAC7 },
3224
3225 { "ic", IC },
3226 { "dc", DC },
3227 { "nc", NC },
3228
3229 { "tt0", TT0 },
3230 { "tt1", TT1 },
3231 /* 68ec030 versions of same */
3232 { "ac0", TT0 },
3233 { "ac1", TT1 },
3234 /* 68ec030 access control unit, identical to 030 MMU status reg */
3235 { "acusr", PSR },
3236
3237 /* Suppressed data and address registers. */
3238 { "zd0", ZDATA0 },
3239 { "zd1", ZDATA1 },
3240 { "zd2", ZDATA2 },
3241 { "zd3", ZDATA3 },
3242 { "zd4", ZDATA4 },
3243 { "zd5", ZDATA5 },
3244 { "zd6", ZDATA6 },
3245 { "zd7", ZDATA7 },
3246 { "za0", ZADDR0 },
3247 { "za1", ZADDR1 },
3248 { "za2", ZADDR2 },
3249 { "za3", ZADDR3 },
3250 { "za4", ZADDR4 },
3251 { "za5", ZADDR5 },
3252 { "za6", ZADDR6 },
3253 { "za7", ZADDR7 },
3254
3255 { 0, 0 }
3256 };
3257
3258 void
3259 init_regtable ()
3260 {
3261 int i;
3262 for (i = 0; init_table[i].name; i++)
3263 insert_reg (init_table[i].name, init_table[i].number);
3264 }
3265
3266 static int no_68851, no_68881;
3267
3268 #ifdef OBJ_AOUT
3269 /* a.out machine type. Default to 68020. */
3270 int m68k_aout_machtype = 2;
3271 #endif
3272
3273 void
3274 md_assemble (str)
3275 char *str;
3276 {
3277 const char *er;
3278 short *fromP;
3279 char *toP = NULL;
3280 int m, n = 0;
3281 char *to_beg_P;
3282 int shorts_this_frag;
3283 fixS *fixP;
3284
3285 /* In MRI mode, the instruction and operands are separated by a
3286 space. Anything following the operands is a comment. The label
3287 has already been removed. */
3288 if (flag_mri)
3289 {
3290 char *s;
3291 int fields = 0;
3292 int infield = 0;
3293 int inquote = 0;
3294
3295 for (s = str; *s != '\0'; s++)
3296 {
3297 if ((*s == ' ' || *s == '\t') && ! inquote)
3298 {
3299 if (infield)
3300 {
3301 ++fields;
3302 if (fields >= 2)
3303 {
3304 *s = '\0';
3305 break;
3306 }
3307 infield = 0;
3308 }
3309 }
3310 else
3311 {
3312 if (! infield)
3313 infield = 1;
3314 if (*s == '\'')
3315 inquote = ! inquote;
3316 }
3317 }
3318 }
3319
3320 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3321 m68k_ip (str);
3322 er = the_ins.error;
3323 if (!er)
3324 {
3325 for (n = 0; n < the_ins.numargs; n++)
3326 if (the_ins.operands[n].error)
3327 {
3328 er = the_ins.operands[n].error;
3329 break;
3330 }
3331 }
3332 if (er)
3333 {
3334 as_bad ("%s -- statement `%s' ignored", er, str);
3335 return;
3336 }
3337
3338 /* If there is a current label, record that it marks an instruction. */
3339 if (current_label != NULL)
3340 {
3341 current_label->text = 1;
3342 current_label = NULL;
3343 }
3344
3345 if (the_ins.nfrag == 0)
3346 {
3347 /* No frag hacking involved; just put it out */
3348 toP = frag_more (2 * the_ins.numo);
3349 fromP = &the_ins.opcode[0];
3350 for (m = the_ins.numo; m; --m)
3351 {
3352 md_number_to_chars (toP, (long) (*fromP), 2);
3353 toP += 2;
3354 fromP++;
3355 }
3356 /* put out symbol-dependent info */
3357 for (m = 0; m < the_ins.nrel; m++)
3358 {
3359 switch (the_ins.reloc[m].wid)
3360 {
3361 case 'B':
3362 n = 1;
3363 break;
3364 case 'b':
3365 n = 1;
3366 break;
3367 case '3':
3368 n = 1;
3369 break;
3370 case 'w':
3371 case 'W':
3372 n = 2;
3373 break;
3374 case 'l':
3375 n = 4;
3376 break;
3377 default:
3378 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3379 the_ins.reloc[m].wid);
3380 }
3381
3382 fixP = fix_new_exp (frag_now,
3383 ((toP - frag_now->fr_literal)
3384 - the_ins.numo * 2 + the_ins.reloc[m].n),
3385 n,
3386 &the_ins.reloc[m].exp,
3387 the_ins.reloc[m].pcrel,
3388 get_reloc_code (n, the_ins.reloc[m].pcrel,
3389 the_ins.reloc[m].pic_reloc));
3390 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3391 if (the_ins.reloc[m].wid == 'B')
3392 fixP->fx_signed = 1;
3393 }
3394 return;
3395 }
3396
3397 /* There's some frag hacking */
3398 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3399 {
3400 int wid;
3401
3402 if (n == 0)
3403 wid = 2 * the_ins.fragb[n].fragoff;
3404 else
3405 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3406 toP = frag_more (wid);
3407 to_beg_P = toP;
3408 shorts_this_frag = 0;
3409 for (m = wid / 2; m; --m)
3410 {
3411 md_number_to_chars (toP, (long) (*fromP), 2);
3412 toP += 2;
3413 fromP++;
3414 shorts_this_frag++;
3415 }
3416 for (m = 0; m < the_ins.nrel; m++)
3417 {
3418 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3419 {
3420 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3421 break;
3422 }
3423 wid = the_ins.reloc[m].wid;
3424 if (wid == 0)
3425 continue;
3426 the_ins.reloc[m].wid = 0;
3427 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3428
3429 fixP = fix_new_exp (frag_now,
3430 ((toP - frag_now->fr_literal)
3431 - the_ins.numo * 2 + the_ins.reloc[m].n),
3432 wid,
3433 &the_ins.reloc[m].exp,
3434 the_ins.reloc[m].pcrel,
3435 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3436 the_ins.reloc[m].pic_reloc));
3437 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3438 }
3439 (void) frag_var (rs_machine_dependent, 10, 0,
3440 (relax_substateT) (the_ins.fragb[n].fragty),
3441 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3442 }
3443 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3444 shorts_this_frag = 0;
3445 if (n)
3446 {
3447 toP = frag_more (n * sizeof (short));
3448 while (n--)
3449 {
3450 md_number_to_chars (toP, (long) (*fromP), 2);
3451 toP += 2;
3452 fromP++;
3453 shorts_this_frag++;
3454 }
3455 }
3456 for (m = 0; m < the_ins.nrel; m++)
3457 {
3458 int wid;
3459
3460 wid = the_ins.reloc[m].wid;
3461 if (wid == 0)
3462 continue;
3463 the_ins.reloc[m].wid = 0;
3464 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3465
3466 fixP = fix_new_exp (frag_now,
3467 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3468 - shorts_this_frag * 2),
3469 wid,
3470 &the_ins.reloc[m].exp,
3471 the_ins.reloc[m].pcrel,
3472 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3473 the_ins.reloc[m].pic_reloc));
3474 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3475 }
3476 }
3477
3478 void
3479 md_begin ()
3480 {
3481 /*
3482 * md_begin -- set up hash tables with 68000 instructions.
3483 * similar to what the vax assembler does. ---phr
3484 */
3485 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3486 a copy of it at runtime, adding in the information we want but isn't
3487 there. I think it'd be better to have an awk script hack the table
3488 at compile time. Or even just xstr the table and use it as-is. But
3489 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3490 names. */
3491
3492 register const struct m68k_opcode *ins;
3493 register struct m68k_incant *hack, *slak;
3494 register const char *retval = 0; /* empty string, or error msg text */
3495 register unsigned int i;
3496 register char c;
3497
3498 if (flag_mri)
3499 {
3500 flag_reg_prefix_optional = 1;
3501 m68k_abspcadd = 1;
3502 if (! m68k_rel32_from_cmdline)
3503 m68k_rel32 = 0;
3504 }
3505
3506 op_hash = hash_new ();
3507
3508 obstack_begin (&robyn, 4000);
3509 for (i = 0; i < m68k_numopcodes; i++)
3510 {
3511 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3512 do
3513 {
3514 ins = &m68k_opcodes[i];
3515 /* We *could* ignore insns that don't match our arch here
3516 but just leaving them out of the hash. */
3517 slak->m_operands = ins->args;
3518 slak->m_opnum = strlen (slak->m_operands) / 2;
3519 slak->m_arch = ins->arch;
3520 slak->m_opcode = ins->opcode;
3521 /* This is kludgey */
3522 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3523 if (i + 1 != m68k_numopcodes
3524 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3525 {
3526 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3527 i++;
3528 }
3529 else
3530 slak->m_next = 0;
3531 slak = slak->m_next;
3532 }
3533 while (slak);
3534
3535 retval = hash_insert (op_hash, ins->name, (char *) hack);
3536 if (retval)
3537 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3538 }
3539
3540 for (i = 0; i < m68k_numaliases; i++)
3541 {
3542 const char *name = m68k_opcode_aliases[i].primary;
3543 const char *alias = m68k_opcode_aliases[i].alias;
3544 PTR val = hash_find (op_hash, name);
3545 if (!val)
3546 as_fatal ("Internal Error: Can't find %s in hash table", name);
3547 retval = hash_insert (op_hash, alias, val);
3548 if (retval)
3549 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3550 }
3551
3552 /* In MRI mode, all unsized branches are variable sized. Normally,
3553 they are word sized. */
3554 if (flag_mri)
3555 {
3556 static struct m68k_opcode_alias mri_aliases[] =
3557 {
3558 { "bhi", "jhi", },
3559 { "bls", "jls", },
3560 { "bcc", "jcc", },
3561 { "bcs", "jcs", },
3562 { "bne", "jne", },
3563 { "beq", "jeq", },
3564 { "bvc", "jvc", },
3565 { "bvs", "jvs", },
3566 { "bpl", "jpl", },
3567 { "bmi", "jmi", },
3568 { "bge", "jge", },
3569 { "blt", "jlt", },
3570 { "bgt", "jgt", },
3571 { "ble", "jle", },
3572 { "bra", "jra", },
3573 { "bsr", "jbsr", },
3574 };
3575
3576 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3577 {
3578 const char *name = mri_aliases[i].primary;
3579 const char *alias = mri_aliases[i].alias;
3580 PTR val = hash_find (op_hash, name);
3581 if (!val)
3582 as_fatal ("Internal Error: Can't find %s in hash table", name);
3583 retval = hash_jam (op_hash, alias, val);
3584 if (retval)
3585 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3586 }
3587 }
3588
3589 for (i = 0; i < sizeof (mklower_table); i++)
3590 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3591
3592 for (i = 0; i < sizeof (notend_table); i++)
3593 {
3594 notend_table[i] = 0;
3595 alt_notend_table[i] = 0;
3596 }
3597 notend_table[','] = 1;
3598 notend_table['{'] = 1;
3599 notend_table['}'] = 1;
3600 alt_notend_table['a'] = 1;
3601 alt_notend_table['A'] = 1;
3602 alt_notend_table['d'] = 1;
3603 alt_notend_table['D'] = 1;
3604 alt_notend_table['#'] = 1;
3605 alt_notend_table['&'] = 1;
3606 alt_notend_table['f'] = 1;
3607 alt_notend_table['F'] = 1;
3608 #ifdef REGISTER_PREFIX
3609 alt_notend_table[REGISTER_PREFIX] = 1;
3610 #endif
3611
3612 /* We need to put '(' in alt_notend_table to handle
3613 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3614 */
3615 alt_notend_table['('] = 1;
3616
3617 /* We need to put '@' in alt_notend_table to handle
3618 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3619 */
3620 alt_notend_table['@'] = 1;
3621
3622 /* We need to put digits in alt_notend_table to handle
3623 bfextu %d0{24:1},%d0
3624 */
3625 alt_notend_table['0'] = 1;
3626 alt_notend_table['1'] = 1;
3627 alt_notend_table['2'] = 1;
3628 alt_notend_table['3'] = 1;
3629 alt_notend_table['4'] = 1;
3630 alt_notend_table['5'] = 1;
3631 alt_notend_table['6'] = 1;
3632 alt_notend_table['7'] = 1;
3633 alt_notend_table['8'] = 1;
3634 alt_notend_table['9'] = 1;
3635
3636 #ifndef MIT_SYNTAX_ONLY
3637 /* Insert pseudo ops, these have to go into the opcode table since
3638 gas expects pseudo ops to start with a dot */
3639 {
3640 int n = 0;
3641 while (mote_pseudo_table[n].poc_name)
3642 {
3643 hack = (struct m68k_incant *)
3644 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3645 hash_insert (op_hash,
3646 mote_pseudo_table[n].poc_name, (char *) hack);
3647 hack->m_operands = 0;
3648 hack->m_opnum = n;
3649 n++;
3650 }
3651 }
3652 #endif
3653
3654 init_regtable ();
3655
3656 #ifdef OBJ_ELF
3657 record_alignment (text_section, 2);
3658 record_alignment (data_section, 2);
3659 record_alignment (bss_section, 2);
3660 #endif
3661 }
3662
3663 static void
3664 select_control_regs ()
3665 {
3666 /* Note which set of "movec" control registers is available. */
3667 switch (cpu_of_arch (current_architecture))
3668 {
3669 case m68000:
3670 control_regs = m68000_control_regs;
3671 break;
3672 case m68010:
3673 control_regs = m68010_control_regs;
3674 break;
3675 case m68020:
3676 case m68030:
3677 control_regs = m68020_control_regs;
3678 break;
3679 case m68040:
3680 control_regs = m68040_control_regs;
3681 break;
3682 case m68060:
3683 control_regs = m68060_control_regs;
3684 break;
3685 case cpu32:
3686 control_regs = cpu32_control_regs;
3687 break;
3688 case mcf5200:
3689 control_regs = mcf5200_control_regs;
3690 break;
3691 default:
3692 abort ();
3693 }
3694 }
3695
3696 void
3697 m68k_init_after_args ()
3698 {
3699 if (cpu_of_arch (current_architecture) == 0)
3700 {
3701 int i;
3702 const char *default_cpu = TARGET_CPU;
3703
3704 if (*default_cpu == 'm')
3705 default_cpu++;
3706 for (i = 0; i < n_archs; i++)
3707 if (strcasecmp (default_cpu, archs[i].name) == 0)
3708 break;
3709 if (i == n_archs)
3710 {
3711 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3712 current_architecture |= m68020;
3713 }
3714 else
3715 current_architecture |= archs[i].arch;
3716 }
3717 /* Permit m68881 specification with all cpus; those that can't work
3718 with a coprocessor could be doing emulation. */
3719 if (current_architecture & m68851)
3720 {
3721 if (current_architecture & m68040)
3722 {
3723 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3724 }
3725 }
3726 /* What other incompatibilities could we check for? */
3727
3728 /* Toss in some default assumptions about coprocessors. */
3729 if (!no_68881
3730 && (cpu_of_arch (current_architecture)
3731 /* Can CPU32 have a 68881 coprocessor?? */
3732 & (m68020 | m68030 | cpu32)))
3733 {
3734 current_architecture |= m68881;
3735 }
3736 if (!no_68851
3737 && (cpu_of_arch (current_architecture) & m68020up) != 0
3738 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3739 {
3740 current_architecture |= m68851;
3741 }
3742 if (no_68881 && (current_architecture & m68881))
3743 as_bad ("options for 68881 and no-68881 both given");
3744 if (no_68851 && (current_architecture & m68851))
3745 as_bad ("options for 68851 and no-68851 both given");
3746
3747 #ifdef OBJ_AOUT
3748 /* Work out the magic number. This isn't very general. */
3749 if (current_architecture & m68000)
3750 m68k_aout_machtype = 0;
3751 else if (current_architecture & m68010)
3752 m68k_aout_machtype = 1;
3753 else if (current_architecture & m68020)
3754 m68k_aout_machtype = 2;
3755 else
3756 m68k_aout_machtype = 2;
3757 #endif
3758
3759 /* Note which set of "movec" control registers is available. */
3760 select_control_regs ();
3761
3762 if (cpu_of_arch (current_architecture) < m68020)
3763 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3764 }
3765 \f
3766 /* This is called when a label is defined. */
3767
3768 void
3769 m68k_frob_label (sym)
3770 symbolS *sym;
3771 {
3772 struct label_line *n;
3773
3774 n = (struct label_line *) xmalloc (sizeof *n);
3775 n->next = labels;
3776 n->label = sym;
3777 as_where (&n->file, &n->line);
3778 n->text = 0;
3779 labels = n;
3780 current_label = n;
3781 }
3782
3783 /* This is called when a value that is not an instruction is emitted. */
3784
3785 void
3786 m68k_flush_pending_output ()
3787 {
3788 current_label = NULL;
3789 }
3790
3791 /* This is called at the end of the assembly, when the final value of
3792 the label is known. We warn if this is a text symbol aligned at an
3793 odd location. */
3794
3795 void
3796 m68k_frob_symbol (sym)
3797 symbolS *sym;
3798 {
3799 if ((S_GET_VALUE (sym) & 1) != 0)
3800 {
3801 struct label_line *l;
3802
3803 for (l = labels; l != NULL; l = l->next)
3804 {
3805 if (l->label == sym)
3806 {
3807 if (l->text)
3808 as_warn_where (l->file, l->line,
3809 "text label `%s' aligned to odd boundary",
3810 S_GET_NAME (sym));
3811 break;
3812 }
3813 }
3814 }
3815 }
3816 \f
3817 /* This is called if we go in or out of MRI mode because of the .mri
3818 pseudo-op. */
3819
3820 void
3821 m68k_mri_mode_change (on)
3822 int on;
3823 {
3824 if (on)
3825 {
3826 if (! flag_reg_prefix_optional)
3827 {
3828 flag_reg_prefix_optional = 1;
3829 #ifdef REGISTER_PREFIX
3830 init_regtable ();
3831 #endif
3832 }
3833 m68k_abspcadd = 1;
3834 if (! m68k_rel32_from_cmdline)
3835 m68k_rel32 = 0;
3836 }
3837 else
3838 {
3839 if (! reg_prefix_optional_seen)
3840 {
3841 #ifdef REGISTER_PREFIX_OPTIONAL
3842 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3843 #else
3844 flag_reg_prefix_optional = 0;
3845 #endif
3846 #ifdef REGISTER_PREFIX
3847 init_regtable ();
3848 #endif
3849 }
3850 m68k_abspcadd = 0;
3851 if (! m68k_rel32_from_cmdline)
3852 m68k_rel32 = 1;
3853 }
3854 }
3855
3856 /* Equal to MAX_PRECISION in atof-ieee.c */
3857 #define MAX_LITTLENUMS 6
3858
3859 /* Turn a string in input_line_pointer into a floating point constant
3860 of type type, and store the appropriate bytes in *litP. The number
3861 of LITTLENUMS emitted is stored in *sizeP . An error message is
3862 returned, or NULL on OK. */
3863
3864 char *
3865 md_atof (type, litP, sizeP)
3866 char type;
3867 char *litP;
3868 int *sizeP;
3869 {
3870 int prec;
3871 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3872 LITTLENUM_TYPE *wordP;
3873 char *t;
3874 char *atof_ieee ();
3875
3876 switch (type)
3877 {
3878 case 'f':
3879 case 'F':
3880 case 's':
3881 case 'S':
3882 prec = 2;
3883 break;
3884
3885 case 'd':
3886 case 'D':
3887 case 'r':
3888 case 'R':
3889 prec = 4;
3890 break;
3891
3892 case 'x':
3893 case 'X':
3894 prec = 6;
3895 break;
3896
3897 case 'p':
3898 case 'P':
3899 prec = 6;
3900 break;
3901
3902 default:
3903 *sizeP = 0;
3904 return "Bad call to MD_ATOF()";
3905 }
3906 t = atof_ieee (input_line_pointer, type, words);
3907 if (t)
3908 input_line_pointer = t;
3909
3910 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3911 for (wordP = words; prec--;)
3912 {
3913 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3914 litP += sizeof (LITTLENUM_TYPE);
3915 }
3916 return 0;
3917 }
3918
3919 void
3920 md_number_to_chars (buf, val, n)
3921 char *buf;
3922 valueT val;
3923 int n;
3924 {
3925 number_to_chars_bigendian (buf, val, n);
3926 }
3927
3928 static void
3929 md_apply_fix_2 (fixP, val)
3930 fixS *fixP;
3931 offsetT val;
3932 {
3933 addressT upper_limit;
3934 offsetT lower_limit;
3935
3936 /* This is unnecessary but it convinces the native rs6000 compiler
3937 to generate the code we want. */
3938 char *buf = fixP->fx_frag->fr_literal;
3939 buf += fixP->fx_where;
3940 /* end ibm compiler workaround */
3941
3942 if (val & 0x80000000)
3943 val |= ~(addressT)0x7fffffff;
3944 else
3945 val &= 0x7fffffff;
3946
3947 #ifdef OBJ_ELF
3948 if (fixP->fx_addsy)
3949 {
3950 memset (buf, 0, fixP->fx_size);
3951 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3952 return;
3953 }
3954 #endif
3955
3956 switch (fixP->fx_size)
3957 {
3958 /* The cast to offsetT below are necessary to make code correct for
3959 machines where ints are smaller than offsetT */
3960 case 1:
3961 *buf++ = val;
3962 upper_limit = 0x7f;
3963 lower_limit = - (offsetT) 0x80;
3964 break;
3965 case 2:
3966 *buf++ = (val >> 8);
3967 *buf++ = val;
3968 upper_limit = 0x7fff;
3969 lower_limit = - (offsetT) 0x8000;
3970 break;
3971 case 4:
3972 *buf++ = (val >> 24);
3973 *buf++ = (val >> 16);
3974 *buf++ = (val >> 8);
3975 *buf++ = val;
3976 upper_limit = 0x7fffffff;
3977 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3978 break;
3979 default:
3980 BAD_CASE (fixP->fx_size);
3981 }
3982
3983 /* Fix up a negative reloc. */
3984 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3985 {
3986 fixP->fx_addsy = fixP->fx_subsy;
3987 fixP->fx_subsy = NULL;
3988 fixP->fx_tcbit = 1;
3989 }
3990
3991 /* For non-pc-relative values, it's conceivable we might get something
3992 like "0xff" for a byte field. So extend the upper part of the range
3993 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3994 so that we can do any range checking at all. */
3995 if (! fixP->fx_pcrel && ! fixP->fx_signed)
3996 upper_limit = upper_limit * 2 + 1;
3997
3998 if ((addressT) val > upper_limit
3999 && (val > 0 || val < lower_limit))
4000 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
4001
4002 /* A one byte PC-relative reloc means a short branch. We can't use
4003 a short branch with a value of 0 or -1, because those indicate
4004 different opcodes (branches with longer offsets). */
4005 if (fixP->fx_pcrel
4006 && fixP->fx_size == 1
4007 && (fixP->fx_addsy == NULL
4008 || S_IS_DEFINED (fixP->fx_addsy))
4009 && (val == 0 || val == -1))
4010 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
4011 }
4012
4013 #ifdef BFD_ASSEMBLER
4014 int
4015 md_apply_fix (fixP, valp)
4016 fixS *fixP;
4017 valueT *valp;
4018 {
4019 md_apply_fix_2 (fixP, (addressT) *valp);
4020 return 1;
4021 }
4022 #else
4023 void md_apply_fix (fixP, val)
4024 fixS *fixP;
4025 long val;
4026 {
4027 md_apply_fix_2 (fixP, (addressT) val);
4028 }
4029 #endif
4030
4031 /* *fragP has been relaxed to its final size, and now needs to have
4032 the bytes inside it modified to conform to the new size There is UGLY
4033 MAGIC here. ..
4034 */
4035 void
4036 md_convert_frag_1 (fragP)
4037 register fragS *fragP;
4038 {
4039 long disp;
4040 long ext = 0;
4041 fixS *fixP;
4042
4043 /* Address in object code of the displacement. */
4044 register int object_address = fragP->fr_fix + fragP->fr_address;
4045
4046 /* Address in gas core of the place to store the displacement. */
4047 /* This convinces the native rs6000 compiler to generate the code we
4048 want. */
4049 register char *buffer_address = fragP->fr_literal;
4050 buffer_address += fragP->fr_fix;
4051 /* end ibm compiler workaround */
4052
4053 /* The displacement of the address, from current location. */
4054 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4055 disp = (disp + fragP->fr_offset) - object_address;
4056
4057 #ifdef BFD_ASSEMBLER
4058 disp += fragP->fr_symbol->sy_frag->fr_address;
4059 #endif
4060
4061 switch (fragP->fr_subtype)
4062 {
4063 case TAB (BCC68000, BYTE):
4064 case TAB (ABRANCH, BYTE):
4065 know (issbyte (disp));
4066 if (disp == 0)
4067 as_bad ("short branch with zero offset: use :w");
4068 fragP->fr_opcode[1] = disp;
4069 ext = 0;
4070 break;
4071 case TAB (DBCC, SHORT):
4072 know (issword (disp));
4073 ext = 2;
4074 break;
4075 case TAB (BCC68000, SHORT):
4076 case TAB (ABRANCH, SHORT):
4077 know (issword (disp));
4078 fragP->fr_opcode[1] = 0x00;
4079 ext = 2;
4080 break;
4081 case TAB (ABRANCH, LONG):
4082 if (!HAVE_LONG_BRANCH(current_architecture))
4083 {
4084 if (fragP->fr_opcode[0] == 0x61)
4085 /* BSR */
4086 {
4087 fragP->fr_opcode[0] = 0x4E;
4088 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4089
4090 fix_new (fragP,
4091 fragP->fr_fix,
4092 4,
4093 fragP->fr_symbol,
4094 fragP->fr_offset,
4095 0,
4096 NO_RELOC);
4097
4098 fragP->fr_fix += 4;
4099 ext = 0;
4100 }
4101 /* BRA */
4102 else if (fragP->fr_opcode[0] == 0x60)
4103 {
4104 fragP->fr_opcode[0] = 0x4E;
4105 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4106 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4107 fragP->fr_offset, 0, NO_RELOC);
4108 fragP->fr_fix += 4;
4109 ext = 0;
4110 }
4111 else
4112 {
4113 as_bad ("Long branch offset not supported.");
4114 }
4115 }
4116 else
4117 {
4118 fragP->fr_opcode[1] = (char) 0xff;
4119 ext = 4;
4120 }
4121 break;
4122 case TAB (BCC68000, LONG):
4123 /* only Bcc 68000 instructions can come here */
4124 /* change bcc into b!cc/jmp absl long */
4125 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4126 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4127
4128 /* JF: these used to be fr_opcode[2,3], but they may be in a
4129 different frag, in which case refering to them is a no-no.
4130 Only fr_opcode[0,1] are guaranteed to work. */
4131 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4132 *buffer_address++ = (char) 0xf9;
4133 fragP->fr_fix += 2; /* account for jmp instruction */
4134 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4135 fragP->fr_offset, 0, NO_RELOC);
4136 fragP->fr_fix += 4;
4137 ext = 0;
4138 break;
4139 case TAB (DBCC, LONG):
4140 /* only DBcc 68000 instructions can come here */
4141 /* change dbcc into dbcc/jmp absl long */
4142 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4143 *buffer_address++ = 0x00; /* branch offset = 4 */
4144 *buffer_address++ = 0x04;
4145 *buffer_address++ = 0x60; /* put in bra pc+6 */
4146 *buffer_address++ = 0x06;
4147 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4148 *buffer_address++ = (char) 0xf9;
4149
4150 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4151 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4152 fragP->fr_offset, 0, NO_RELOC);
4153 fragP->fr_fix += 4;
4154 ext = 0;
4155 break;
4156 case TAB (FBRANCH, SHORT):
4157 know ((fragP->fr_opcode[1] & 0x40) == 0);
4158 ext = 2;
4159 break;
4160 case TAB (FBRANCH, LONG):
4161 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4162 ext = 4;
4163 break;
4164 case TAB (PCREL, SHORT):
4165 ext = 2;
4166 break;
4167 case TAB (PCREL, LONG):
4168 /* The thing to do here is force it to ABSOLUTE LONG, since
4169 PCREL is really trying to shorten an ABSOLUTE address anyway */
4170 /* JF FOO This code has not been tested */
4171 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4172 0, NO_RELOC);
4173 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4174 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4175 (unsigned) fragP->fr_opcode[0],
4176 (unsigned long) fragP->fr_address);
4177 fragP->fr_opcode[1] &= ~0x3F;
4178 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4179 fragP->fr_fix += 4;
4180 ext = 0;
4181 break;
4182 case TAB (PCLEA, SHORT):
4183 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4184 fragP->fr_offset, 1, NO_RELOC);
4185 fragP->fr_opcode[1] &= ~0x3F;
4186 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4187 ext = 2;
4188 break;
4189 case TAB (PCLEA, LONG):
4190 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4191 fragP->fr_offset, 1, NO_RELOC);
4192 fixP->fx_pcrel_adjust = 2;
4193 /* Already set to mode 7.3; this indicates: PC indirect with
4194 suppressed index, 32-bit displacement. */
4195 *buffer_address++ = 0x01;
4196 *buffer_address++ = 0x70;
4197 fragP->fr_fix += 2;
4198 ext = 4;
4199 break;
4200
4201 case TAB (PCINDEX, BYTE):
4202 disp += 2;
4203 if (!issbyte (disp))
4204 {
4205 as_bad ("displacement doesn't fit in one byte");
4206 disp = 0;
4207 }
4208 assert (fragP->fr_fix >= 2);
4209 buffer_address[-2] &= ~1;
4210 buffer_address[-1] = disp;
4211 ext = 0;
4212 break;
4213 case TAB (PCINDEX, SHORT):
4214 disp += 2;
4215 assert (issword (disp));
4216 assert (fragP->fr_fix >= 2);
4217 buffer_address[-2] |= 0x1;
4218 buffer_address[-1] = 0x20;
4219 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4220 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4221 NO_RELOC);
4222 fixP->fx_pcrel_adjust = 2;
4223 ext = 2;
4224 break;
4225 case TAB (PCINDEX, LONG):
4226 disp += 2;
4227 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4228 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4229 NO_RELOC);
4230 fixP->fx_pcrel_adjust = 2;
4231 assert (fragP->fr_fix >= 2);
4232 buffer_address[-2] |= 0x1;
4233 buffer_address[-1] = 0x30;
4234 ext = 4;
4235 break;
4236 }
4237
4238 if (ext)
4239 {
4240 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4241 fragP->fr_fix += ext;
4242 }
4243 }
4244
4245 #ifndef BFD_ASSEMBLER
4246
4247 void
4248 md_convert_frag (headers, sec, fragP)
4249 object_headers *headers;
4250 segT sec;
4251 fragS *fragP;
4252 {
4253 md_convert_frag_1 (fragP);
4254 }
4255
4256 #else
4257
4258 void
4259 md_convert_frag (abfd, sec, fragP)
4260 bfd *abfd;
4261 segT sec;
4262 fragS *fragP;
4263 {
4264 md_convert_frag_1 (fragP);
4265 }
4266 #endif
4267
4268 /* Force truly undefined symbols to their maximum size, and generally set up
4269 the frag list to be relaxed
4270 */
4271 int
4272 md_estimate_size_before_relax (fragP, segment)
4273 register fragS *fragP;
4274 segT segment;
4275 {
4276 int old_fix;
4277 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4278
4279 old_fix = fragP->fr_fix;
4280
4281 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4282 switch (fragP->fr_subtype)
4283 {
4284
4285 case TAB (ABRANCH, SZ_UNDEF):
4286 {
4287 if ((fragP->fr_symbol != NULL) /* Not absolute */
4288 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4289 {
4290 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4291 break;
4292 }
4293 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4294 {
4295 /* On 68000, or for absolute value, switch to abs long */
4296 /* FIXME, we should check abs val, pick short or long */
4297 if (fragP->fr_opcode[0] == 0x61)
4298 {
4299 fragP->fr_opcode[0] = 0x4E;
4300 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4301 fix_new (fragP, fragP->fr_fix, 4,
4302 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4303 fragP->fr_fix += 4;
4304 frag_wane (fragP);
4305 }
4306 else if (fragP->fr_opcode[0] == 0x60)
4307 {
4308 fragP->fr_opcode[0] = 0x4E;
4309 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4310 fix_new (fragP, fragP->fr_fix, 4,
4311 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4312 fragP->fr_fix += 4;
4313 frag_wane (fragP);
4314 }
4315 else
4316 {
4317 as_warn ("Long branch offset to extern symbol not supported.");
4318 }
4319 }
4320 else
4321 { /* Symbol is still undefined. Make it simple */
4322 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4323 fragP->fr_offset, 1, NO_RELOC);
4324 fragP->fr_fix += 4;
4325 fragP->fr_opcode[1] = (char) 0xff;
4326 frag_wane (fragP);
4327 break;
4328 }
4329
4330 break;
4331 } /* case TAB(ABRANCH,SZ_UNDEF) */
4332
4333 case TAB (FBRANCH, SZ_UNDEF):
4334 {
4335 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4336 {
4337 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4338 fragP->fr_var += 2;
4339 }
4340 else
4341 {
4342 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4343 fragP->fr_offset, 1, NO_RELOC);
4344 fragP->fr_fix += 4;
4345 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4346 frag_wane (fragP);
4347 }
4348 break;
4349 } /* TAB(FBRANCH,SZ_UNDEF) */
4350
4351 case TAB (PCREL, SZ_UNDEF):
4352 {
4353 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4354 || flag_short_refs
4355 || cpu_of_arch (current_architecture) < m68020)
4356 {
4357 fragP->fr_subtype = TAB (PCREL, SHORT);
4358 fragP->fr_var += 2;
4359 }
4360 else
4361 {
4362 fragP->fr_subtype = TAB (PCREL, LONG);
4363 fragP->fr_var += 4;
4364 }
4365 break;
4366 } /* TAB(PCREL,SZ_UNDEF) */
4367
4368 case TAB (BCC68000, SZ_UNDEF):
4369 {
4370 if ((fragP->fr_symbol != NULL)
4371 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4372 {
4373 fragP->fr_subtype = TAB (BCC68000, BYTE);
4374 break;
4375 }
4376 /* only Bcc 68000 instructions can come here */
4377 /* change bcc into b!cc/jmp absl long */
4378 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4379 if (flag_short_refs)
4380 {
4381 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4382 /* JF: these were fr_opcode[2,3] */
4383 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4384 buffer_address[1] = (char) 0xf8;
4385 fragP->fr_fix += 2; /* account for jmp instruction */
4386 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4387 fragP->fr_offset, 0, NO_RELOC);
4388 fragP->fr_fix += 2;
4389 }
4390 else
4391 {
4392 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4393 /* JF: these were fr_opcode[2,3] */
4394 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4395 buffer_address[1] = (char) 0xf9;
4396 fragP->fr_fix += 2; /* account for jmp instruction */
4397 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4398 fragP->fr_offset, 0, NO_RELOC);
4399 fragP->fr_fix += 4;
4400 }
4401 frag_wane (fragP);
4402 break;
4403 } /* case TAB(BCC68000,SZ_UNDEF) */
4404
4405 case TAB (DBCC, SZ_UNDEF):
4406 {
4407 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4408 {
4409 fragP->fr_subtype = TAB (DBCC, SHORT);
4410 fragP->fr_var += 2;
4411 break;
4412 }
4413 /* only DBcc 68000 instructions can come here */
4414 /* change dbcc into dbcc/jmp absl long */
4415 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4416 buffer_address[0] = 0x00; /* branch offset = 4 */
4417 buffer_address[1] = 0x04;
4418 buffer_address[2] = 0x60; /* put in bra pc + ... */
4419
4420 if (flag_short_refs)
4421 {
4422 /* JF: these were fr_opcode[5-7] */
4423 buffer_address[3] = 0x04; /* plus 4 */
4424 buffer_address[4] = 0x4e; /* Put in Jump Word */
4425 buffer_address[5] = (char) 0xf8;
4426 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4427 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4428 fragP->fr_offset, 0, NO_RELOC);
4429 fragP->fr_fix += 2;
4430 }
4431 else
4432 {
4433 /* JF: these were fr_opcode[5-7] */
4434 buffer_address[3] = 0x06; /* Plus 6 */
4435 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4436 buffer_address[5] = (char) 0xf9;
4437 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4438 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4439 fragP->fr_offset, 0, NO_RELOC);
4440 fragP->fr_fix += 4;
4441 }
4442
4443 frag_wane (fragP);
4444 break;
4445 } /* case TAB(DBCC,SZ_UNDEF) */
4446
4447 case TAB (PCLEA, SZ_UNDEF):
4448 {
4449 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4450 || flag_short_refs
4451 || cpu_of_arch (current_architecture) < m68020)
4452 {
4453 fragP->fr_subtype = TAB (PCLEA, SHORT);
4454 fragP->fr_var += 2;
4455 }
4456 else
4457 {
4458 fragP->fr_subtype = TAB (PCLEA, LONG);
4459 fragP->fr_var += 6;
4460 }
4461 break;
4462 } /* TAB(PCLEA,SZ_UNDEF) */
4463
4464 case TAB (PCINDEX, SZ_UNDEF):
4465 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4466 || cpu_of_arch (current_architecture) < m68020)
4467 {
4468 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4469 }
4470 else
4471 {
4472 fragP->fr_subtype = TAB (PCINDEX, LONG);
4473 fragP->fr_var += 4;
4474 }
4475 break;
4476
4477 default:
4478 break;
4479 }
4480
4481 /* now that SZ_UNDEF are taken care of, check others */
4482 switch (fragP->fr_subtype)
4483 {
4484 case TAB (BCC68000, BYTE):
4485 case TAB (ABRANCH, BYTE):
4486 /* We can't do a short jump to the next instruction, so in that
4487 case we force word mode. At this point S_GET_VALUE should
4488 return the offset of the symbol within its frag. If the
4489 symbol is at the start of a frag, and it is the next frag
4490 with any data in it (usually this is just the next frag, but
4491 assembler listings may introduce empty frags), we must use
4492 word mode. */
4493 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4494 {
4495 fragS *l;
4496
4497 for (l = fragP->fr_next;
4498 l != fragP->fr_symbol->sy_frag;
4499 l = l->fr_next)
4500 if (l->fr_fix + l->fr_var != 0)
4501 break;
4502 if (l == fragP->fr_symbol->sy_frag)
4503 {
4504 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4505 fragP->fr_var += 2;
4506 }
4507 }
4508 break;
4509 default:
4510 break;
4511 }
4512 return fragP->fr_var + fragP->fr_fix - old_fix;
4513 }
4514
4515 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4516 /* the bit-field entries in the relocation_info struct plays hell
4517 with the byte-order problems of cross-assembly. So as a hack,
4518 I added this mach. dependent ri twiddler. Ugly, but it gets
4519 you there. -KWK */
4520 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4521 are symbolnum, most sig. byte first. Last byte is broken up with
4522 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4523 nibble as nuthin. (on Sun 3 at least) */
4524 /* Translate the internal relocation information into target-specific
4525 format. */
4526 #ifdef comment
4527 void
4528 md_ri_to_chars (the_bytes, ri)
4529 char *the_bytes;
4530 struct reloc_info_generic *ri;
4531 {
4532 /* this is easy */
4533 md_number_to_chars (the_bytes, ri->r_address, 4);
4534 /* now the fun stuff */
4535 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4536 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4537 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4538 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4539 ((ri->r_extern << 4) & 0x10));
4540 }
4541
4542 #endif /* comment */
4543
4544 #ifndef BFD_ASSEMBLER
4545 void
4546 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4547 char *where;
4548 fixS *fixP;
4549 relax_addressT segment_address_in_file;
4550 {
4551 /*
4552 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4553 * Out: GNU LD relocation length code: 0, 1, or 2.
4554 */
4555
4556 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4557 long r_symbolnum;
4558
4559 know (fixP->fx_addsy != NULL);
4560
4561 md_number_to_chars (where,
4562 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4563 4);
4564
4565 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4566 ? S_GET_TYPE (fixP->fx_addsy)
4567 : fixP->fx_addsy->sy_number);
4568
4569 where[4] = (r_symbolnum >> 16) & 0x0ff;
4570 where[5] = (r_symbolnum >> 8) & 0x0ff;
4571 where[6] = r_symbolnum & 0x0ff;
4572 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4573 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4574 }
4575 #endif
4576
4577 #endif /* OBJ_AOUT or OBJ_BOUT */
4578
4579 #ifndef WORKING_DOT_WORD
4580 CONST int md_short_jump_size = 4;
4581 CONST int md_long_jump_size = 6;
4582
4583 void
4584 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4585 char *ptr;
4586 addressT from_addr, to_addr;
4587 fragS *frag;
4588 symbolS *to_symbol;
4589 {
4590 valueT offset;
4591
4592 offset = to_addr - (from_addr + 2);
4593
4594 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4595 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4596 }
4597
4598 void
4599 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4600 char *ptr;
4601 addressT from_addr, to_addr;
4602 fragS *frag;
4603 symbolS *to_symbol;
4604 {
4605 valueT offset;
4606
4607 if (!HAVE_LONG_BRANCH(current_architecture))
4608 {
4609 offset = to_addr - S_GET_VALUE (to_symbol);
4610 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4611 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4612 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4613 0, NO_RELOC);
4614 }
4615 else
4616 {
4617 offset = to_addr - (from_addr + 2);
4618 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4619 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4620 }
4621 }
4622
4623 #endif
4624
4625 /* Different values of OK tell what its OK to return. Things that
4626 aren't OK are an error (what a shock, no?)
4627
4628 0: Everything is OK
4629 10: Absolute 1:8 only
4630 20: Absolute 0:7 only
4631 30: absolute 0:15 only
4632 40: Absolute 0:31 only
4633 50: absolute 0:127 only
4634 55: absolute -64:63 only
4635 60: absolute -128:127 only
4636 70: absolute 0:4095 only
4637 80: No bignums
4638
4639 */
4640
4641 static int
4642 get_num (exp, ok)
4643 struct m68k_exp *exp;
4644 int ok;
4645 {
4646 if (exp->exp.X_op == O_absent)
4647 {
4648 /* Do the same thing the VAX asm does */
4649 op (exp) = O_constant;
4650 adds (exp) = 0;
4651 subs (exp) = 0;
4652 offs (exp) = 0;
4653 if (ok == 10)
4654 {
4655 as_warn ("expression out of range: defaulting to 1");
4656 offs (exp) = 1;
4657 }
4658 }
4659 else if (exp->exp.X_op == O_constant)
4660 {
4661 switch (ok)
4662 {
4663 case 10:
4664 if (offs (exp) < 1 || offs (exp) > 8)
4665 {
4666 as_warn ("expression out of range: defaulting to 1");
4667 offs (exp) = 1;
4668 }
4669 break;
4670 case 20:
4671 if (offs (exp) < 0 || offs (exp) > 7)
4672 goto outrange;
4673 break;
4674 case 30:
4675 if (offs (exp) < 0 || offs (exp) > 15)
4676 goto outrange;
4677 break;
4678 case 40:
4679 if (offs (exp) < 0 || offs (exp) > 32)
4680 goto outrange;
4681 break;
4682 case 50:
4683 if (offs (exp) < 0 || offs (exp) > 127)
4684 goto outrange;
4685 break;
4686 case 55:
4687 if (offs (exp) < -64 || offs (exp) > 63)
4688 goto outrange;
4689 break;
4690 case 60:
4691 if (offs (exp) < -128 || offs (exp) > 127)
4692 goto outrange;
4693 break;
4694 case 70:
4695 if (offs (exp) < 0 || offs (exp) > 4095)
4696 {
4697 outrange:
4698 as_warn ("expression out of range: defaulting to 0");
4699 offs (exp) = 0;
4700 }
4701 break;
4702 default:
4703 break;
4704 }
4705 }
4706 else if (exp->exp.X_op == O_big)
4707 {
4708 if (offs (exp) <= 0 /* flonum */
4709 && (ok == 80 /* no bignums */
4710 || (ok > 10 /* small-int ranges including 0 ok */
4711 /* If we have a flonum zero, a zero integer should
4712 do as well (e.g., in moveq). */
4713 && generic_floating_point_number.exponent == 0
4714 && generic_floating_point_number.low[0] == 0)))
4715 {
4716 /* HACK! Turn it into a long */
4717 LITTLENUM_TYPE words[6];
4718
4719 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4720 op (exp) = O_constant;
4721 adds (exp) = 0;
4722 subs (exp) = 0;
4723 offs (exp) = words[1] | (words[0] << 16);
4724 }
4725 else if (ok != 0)
4726 {
4727 op (exp) = O_constant;
4728 adds (exp) = 0;
4729 subs (exp) = 0;
4730 offs (exp) = (ok == 10) ? 1 : 0;
4731 as_warn ("Can't deal with expression; defaulting to %ld",
4732 offs (exp));
4733 }
4734 }
4735 else
4736 {
4737 if (ok >= 10 && ok <= 70)
4738 {
4739 op (exp) = O_constant;
4740 adds (exp) = 0;
4741 subs (exp) = 0;
4742 offs (exp) = (ok == 10) ? 1 : 0;
4743 as_warn ("Can't deal with expression; defaulting to %ld",
4744 offs (exp));
4745 }
4746 }
4747
4748 if (exp->size != SIZE_UNSPEC)
4749 {
4750 switch (exp->size)
4751 {
4752 case SIZE_UNSPEC:
4753 case SIZE_LONG:
4754 break;
4755 case SIZE_BYTE:
4756 if (!isbyte (offs (exp)))
4757 as_warn ("expression doesn't fit in BYTE");
4758 break;
4759 case SIZE_WORD:
4760 if (!isword (offs (exp)))
4761 as_warn ("expression doesn't fit in WORD");
4762 break;
4763 }
4764 }
4765
4766 return offs (exp);
4767 }
4768
4769 /* These are the back-ends for the various machine dependent pseudo-ops. */
4770 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4771
4772 static void
4773 s_data1 (ignore)
4774 int ignore;
4775 {
4776 subseg_set (data_section, 1);
4777 demand_empty_rest_of_line ();
4778 }
4779
4780 static void
4781 s_data2 (ignore)
4782 int ignore;
4783 {
4784 subseg_set (data_section, 2);
4785 demand_empty_rest_of_line ();
4786 }
4787
4788 static void
4789 s_bss (ignore)
4790 int ignore;
4791 {
4792 /* We don't support putting frags in the BSS segment, we fake it
4793 by marking in_bss, then looking at s_skip for clues. */
4794
4795 subseg_set (bss_section, 0);
4796 demand_empty_rest_of_line ();
4797 }
4798
4799 static void
4800 s_even (ignore)
4801 int ignore;
4802 {
4803 register int temp;
4804 register long temp_fill;
4805
4806 temp = 1; /* JF should be 2? */
4807 temp_fill = get_absolute_expression ();
4808 if (!need_pass_2) /* Never make frag if expect extra pass. */
4809 frag_align (temp, (int) temp_fill, 0);
4810 demand_empty_rest_of_line ();
4811 record_alignment (now_seg, temp);
4812 }
4813
4814 static void
4815 s_proc (ignore)
4816 int ignore;
4817 {
4818 demand_empty_rest_of_line ();
4819 }
4820 \f
4821 /* Pseudo-ops handled for MRI compatibility. */
4822
4823 /* This function returns non-zero if the argument is a conditional
4824 pseudo-op. This is called when checking whether a pending
4825 alignment is needed. */
4826
4827 int
4828 m68k_conditional_pseudoop (pop)
4829 pseudo_typeS *pop;
4830 {
4831 return (pop->poc_handler == s_mri_if
4832 || pop->poc_handler == s_mri_else);
4833 }
4834
4835 /* Handle an MRI style chip specification. */
4836
4837 static void
4838 mri_chip ()
4839 {
4840 char *s;
4841 char c;
4842 int i;
4843
4844 s = input_line_pointer;
4845 c = get_symbol_end ();
4846 for (i = 0; i < n_archs; i++)
4847 if (strcasecmp (s, archs[i].name) == 0)
4848 break;
4849 if (i >= n_archs)
4850 {
4851 as_bad ("%s: unrecognized processor name", s);
4852 *input_line_pointer = c;
4853 ignore_rest_of_line ();
4854 return;
4855 }
4856 *input_line_pointer = c;
4857
4858 if (*input_line_pointer == '/')
4859 current_architecture = 0;
4860 else
4861 current_architecture &= m68881 | m68851;
4862 current_architecture |= archs[i].arch;
4863
4864 while (*input_line_pointer == '/')
4865 {
4866 ++input_line_pointer;
4867 s = input_line_pointer;
4868 c = get_symbol_end ();
4869 if (strcmp (s, "68881") == 0)
4870 current_architecture |= m68881;
4871 else if (strcmp (s, "68851") == 0)
4872 current_architecture |= m68851;
4873 *input_line_pointer = c;
4874 }
4875
4876 /* Update info about available control registers. */
4877 select_control_regs ();
4878 }
4879
4880 /* The MRI CHIP pseudo-op. */
4881
4882 static void
4883 s_chip (ignore)
4884 int ignore;
4885 {
4886 char *stop = NULL;
4887 char stopc;
4888
4889 if (flag_mri)
4890 stop = mri_comment_field (&stopc);
4891 mri_chip ();
4892 if (flag_mri)
4893 mri_comment_end (stop, stopc);
4894 demand_empty_rest_of_line ();
4895 }
4896
4897 /* The MRI FOPT pseudo-op. */
4898
4899 static void
4900 s_fopt (ignore)
4901 int ignore;
4902 {
4903 SKIP_WHITESPACE ();
4904
4905 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4906 {
4907 int temp;
4908
4909 input_line_pointer += 3;
4910 temp = get_absolute_expression ();
4911 if (temp < 0 || temp > 7)
4912 as_bad ("bad coprocessor id");
4913 else
4914 m68k_float_copnum = COP0 + temp;
4915 }
4916 else
4917 {
4918 as_bad ("unrecognized fopt option");
4919 ignore_rest_of_line ();
4920 return;
4921 }
4922
4923 demand_empty_rest_of_line ();
4924 }
4925
4926 /* The structure used to handle the MRI OPT pseudo-op. */
4927
4928 struct opt_action
4929 {
4930 /* The name of the option. */
4931 const char *name;
4932
4933 /* If this is not NULL, just call this function. The first argument
4934 is the ARG field of this structure, the second argument is
4935 whether the option was negated. */
4936 void (*pfn) PARAMS ((int arg, int on));
4937
4938 /* If this is not NULL, and the PFN field is NULL, set the variable
4939 this points to. Set it to the ARG field if the option was not
4940 negated, and the NOTARG field otherwise. */
4941 int *pvar;
4942
4943 /* The value to pass to PFN or to assign to *PVAR. */
4944 int arg;
4945
4946 /* The value to assign to *PVAR if the option is negated. If PFN is
4947 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4948 the option may not be negated. */
4949 int notarg;
4950 };
4951
4952 /* The table used to handle the MRI OPT pseudo-op. */
4953
4954 static void skip_to_comma PARAMS ((int, int));
4955 static void opt_nest PARAMS ((int, int));
4956 static void opt_chip PARAMS ((int, int));
4957 static void opt_list PARAMS ((int, int));
4958 static void opt_list_symbols PARAMS ((int, int));
4959
4960 static const struct opt_action opt_table[] =
4961 {
4962 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4963
4964 /* We do relaxing, so there is little use for these options. */
4965 { "b", 0, 0, 0, 0 },
4966 { "brs", 0, 0, 0, 0 },
4967 { "brb", 0, 0, 0, 0 },
4968 { "brl", 0, 0, 0, 0 },
4969 { "brw", 0, 0, 0, 0 },
4970
4971 { "c", 0, 0, 0, 0 },
4972 { "cex", 0, 0, 0, 0 },
4973 { "case", 0, &symbols_case_sensitive, 1, 0 },
4974 { "cl", 0, 0, 0, 0 },
4975 { "cre", 0, 0, 0, 0 },
4976 { "d", 0, &flag_keep_locals, 1, 0 },
4977 { "e", 0, 0, 0, 0 },
4978 { "f", 0, &flag_short_refs, 1, 0 },
4979 { "frs", 0, &flag_short_refs, 1, 0 },
4980 { "frl", 0, &flag_short_refs, 0, 1 },
4981 { "g", 0, 0, 0, 0 },
4982 { "i", 0, 0, 0, 0 },
4983 { "m", 0, 0, 0, 0 },
4984 { "mex", 0, 0, 0, 0 },
4985 { "mc", 0, 0, 0, 0 },
4986 { "md", 0, 0, 0, 0 },
4987 { "nest", opt_nest, 0, 0, 0 },
4988 { "next", skip_to_comma, 0, 0, 0 },
4989 { "o", 0, 0, 0, 0 },
4990 { "old", 0, 0, 0, 0 },
4991 { "op", skip_to_comma, 0, 0, 0 },
4992 { "pco", 0, 0, 0, 0 },
4993 { "p", opt_chip, 0, 0, 0 },
4994 { "pcr", 0, 0, 0, 0 },
4995 { "pcs", 0, 0, 0, 0 },
4996 { "r", 0, 0, 0, 0 },
4997 { "quick", 0, &m68k_quick, 1, 0 },
4998 { "rel32", 0, &m68k_rel32, 1, 0 },
4999 { "s", opt_list, 0, 0, 0 },
5000 { "t", opt_list_symbols, 0, 0, 0 },
5001 { "w", 0, &flag_no_warnings, 0, 1 },
5002 { "x", 0, 0, 0, 0 }
5003 };
5004
5005 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5006
5007 /* The MRI OPT pseudo-op. */
5008
5009 static void
5010 s_opt (ignore)
5011 int ignore;
5012 {
5013 do
5014 {
5015 int t;
5016 char *s;
5017 char c;
5018 int i;
5019 const struct opt_action *o;
5020
5021 SKIP_WHITESPACE ();
5022
5023 t = 1;
5024 if (*input_line_pointer == '-')
5025 {
5026 ++input_line_pointer;
5027 t = 0;
5028 }
5029 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5030 {
5031 input_line_pointer += 2;
5032 t = 0;
5033 }
5034
5035 s = input_line_pointer;
5036 c = get_symbol_end ();
5037
5038 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5039 {
5040 if (strcasecmp (s, o->name) == 0)
5041 {
5042 if (o->pfn)
5043 {
5044 /* Restore input_line_pointer now in case the option
5045 takes arguments. */
5046 *input_line_pointer = c;
5047 (*o->pfn) (o->arg, t);
5048 }
5049 else if (o->pvar != NULL)
5050 {
5051 if (! t && o->arg == o->notarg)
5052 as_bad ("option `%s' may not be negated", s);
5053 *input_line_pointer = c;
5054 *o->pvar = t ? o->arg : o->notarg;
5055 }
5056 else
5057 *input_line_pointer = c;
5058 break;
5059 }
5060 }
5061 if (i >= OPTCOUNT)
5062 {
5063 as_bad ("option `%s' not recognized", s);
5064 *input_line_pointer = c;
5065 }
5066 }
5067 while (*input_line_pointer++ == ',');
5068
5069 /* Move back to terminating character. */
5070 --input_line_pointer;
5071 demand_empty_rest_of_line ();
5072 }
5073
5074 /* Skip ahead to a comma. This is used for OPT options which we do
5075 not suppor tand which take arguments. */
5076
5077 static void
5078 skip_to_comma (arg, on)
5079 int arg;
5080 int on;
5081 {
5082 while (*input_line_pointer != ','
5083 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5084 ++input_line_pointer;
5085 }
5086
5087 /* Handle the OPT NEST=depth option. */
5088
5089 static void
5090 opt_nest (arg, on)
5091 int arg;
5092 int on;
5093 {
5094 if (*input_line_pointer != '=')
5095 {
5096 as_bad ("bad format of OPT NEST=depth");
5097 return;
5098 }
5099
5100 ++input_line_pointer;
5101 max_macro_nest = get_absolute_expression ();
5102 }
5103
5104 /* Handle the OPT P=chip option. */
5105
5106 static void
5107 opt_chip (arg, on)
5108 int arg;
5109 int on;
5110 {
5111 if (*input_line_pointer != '=')
5112 {
5113 /* This is just OPT P, which we do not support. */
5114 return;
5115 }
5116
5117 ++input_line_pointer;
5118 mri_chip ();
5119 }
5120
5121 /* Handle the OPT S option. */
5122
5123 static void
5124 opt_list (arg, on)
5125 int arg;
5126 int on;
5127 {
5128 listing_list (on);
5129 }
5130
5131 /* Handle the OPT T option. */
5132
5133 static void
5134 opt_list_symbols (arg, on)
5135 int arg;
5136 int on;
5137 {
5138 if (on)
5139 listing |= LISTING_SYMBOLS;
5140 else
5141 listing &=~ LISTING_SYMBOLS;
5142 }
5143
5144 /* Handle the MRI REG pseudo-op. */
5145
5146 static void
5147 s_reg (ignore)
5148 int ignore;
5149 {
5150 char *s;
5151 int c;
5152 struct m68k_op rop;
5153 unsigned long mask;
5154 char *stop = NULL;
5155 char stopc;
5156
5157 if (line_label == NULL)
5158 {
5159 as_bad ("missing label");
5160 ignore_rest_of_line ();
5161 return;
5162 }
5163
5164 if (flag_mri)
5165 stop = mri_comment_field (&stopc);
5166
5167 SKIP_WHITESPACE ();
5168
5169 s = input_line_pointer;
5170 while (isalnum ((unsigned char) *input_line_pointer)
5171 #ifdef REGISTER_PREFIX
5172 || *input_line_pointer == REGISTER_PREFIX
5173 #endif
5174 || *input_line_pointer == '/'
5175 || *input_line_pointer == '-')
5176 ++input_line_pointer;
5177 c = *input_line_pointer;
5178 *input_line_pointer = '\0';
5179
5180 if (m68k_ip_op (s, &rop) != 0)
5181 {
5182 if (rop.error == NULL)
5183 as_bad ("bad register list");
5184 else
5185 as_bad ("bad register list: %s", rop.error);
5186 *input_line_pointer = c;
5187 ignore_rest_of_line ();
5188 return;
5189 }
5190
5191 *input_line_pointer = c;
5192
5193 if (rop.mode == REGLST)
5194 mask = rop.mask;
5195 else if (rop.mode == DREG)
5196 mask = 1 << (rop.reg - DATA0);
5197 else if (rop.mode == AREG)
5198 mask = 1 << (rop.reg - ADDR0 + 8);
5199 else if (rop.mode == FPREG)
5200 mask = 1 << (rop.reg - FP0 + 16);
5201 else if (rop.mode == CONTROL
5202 && rop.reg == FPI)
5203 mask = 1 << 24;
5204 else if (rop.mode == CONTROL
5205 && rop.reg == FPS)
5206 mask = 1 << 25;
5207 else if (rop.mode == CONTROL
5208 && rop.reg == FPC)
5209 mask = 1 << 26;
5210 else
5211 {
5212 as_bad ("bad register list");
5213 ignore_rest_of_line ();
5214 return;
5215 }
5216
5217 S_SET_SEGMENT (line_label, absolute_section);
5218 S_SET_VALUE (line_label, mask);
5219 line_label->sy_frag = &zero_address_frag;
5220
5221 if (flag_mri)
5222 mri_comment_end (stop, stopc);
5223
5224 demand_empty_rest_of_line ();
5225 }
5226
5227 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5228
5229 struct save_opts
5230 {
5231 struct save_opts *next;
5232 int abspcadd;
5233 int symbols_case_sensitive;
5234 int keep_locals;
5235 int short_refs;
5236 int architecture;
5237 int quick;
5238 int rel32;
5239 int listing;
5240 int no_warnings;
5241 /* FIXME: We don't save OPT S. */
5242 };
5243
5244 /* This variable holds the stack of saved options. */
5245
5246 static struct save_opts *save_stack;
5247
5248 /* The MRI SAVE pseudo-op. */
5249
5250 static void
5251 s_save (ignore)
5252 int ignore;
5253 {
5254 struct save_opts *s;
5255
5256 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5257 s->abspcadd = m68k_abspcadd;
5258 s->symbols_case_sensitive = symbols_case_sensitive;
5259 s->keep_locals = flag_keep_locals;
5260 s->short_refs = flag_short_refs;
5261 s->architecture = current_architecture;
5262 s->quick = m68k_quick;
5263 s->rel32 = m68k_rel32;
5264 s->listing = listing;
5265 s->no_warnings = flag_no_warnings;
5266
5267 s->next = save_stack;
5268 save_stack = s;
5269
5270 demand_empty_rest_of_line ();
5271 }
5272
5273 /* The MRI RESTORE pseudo-op. */
5274
5275 static void
5276 s_restore (ignore)
5277 int ignore;
5278 {
5279 struct save_opts *s;
5280
5281 if (save_stack == NULL)
5282 {
5283 as_bad ("restore without save");
5284 ignore_rest_of_line ();
5285 return;
5286 }
5287
5288 s = save_stack;
5289 save_stack = s->next;
5290
5291 m68k_abspcadd = s->abspcadd;
5292 symbols_case_sensitive = s->symbols_case_sensitive;
5293 flag_keep_locals = s->keep_locals;
5294 flag_short_refs = s->short_refs;
5295 current_architecture = s->architecture;
5296 m68k_quick = s->quick;
5297 m68k_rel32 = s->rel32;
5298 listing = s->listing;
5299 flag_no_warnings = s->no_warnings;
5300
5301 free (s);
5302
5303 demand_empty_rest_of_line ();
5304 }
5305
5306 /* Types of MRI structured control directives. */
5307
5308 enum mri_control_type
5309 {
5310 mri_for,
5311 mri_if,
5312 mri_repeat,
5313 mri_while
5314 };
5315
5316 /* This structure is used to stack the MRI structured control
5317 directives. */
5318
5319 struct mri_control_info
5320 {
5321 /* The directive within which this one is enclosed. */
5322 struct mri_control_info *outer;
5323
5324 /* The type of directive. */
5325 enum mri_control_type type;
5326
5327 /* Whether an ELSE has been in an IF. */
5328 int else_seen;
5329
5330 /* The add or sub statement at the end of a FOR. */
5331 char *incr;
5332
5333 /* The label of the top of a FOR or REPEAT loop. */
5334 char *top;
5335
5336 /* The label to jump to for the next iteration, or the else
5337 expression of a conditional. */
5338 char *next;
5339
5340 /* The label to jump to to break out of the loop, or the label past
5341 the end of a conditional. */
5342 char *bottom;
5343 };
5344
5345 /* The stack of MRI structured control directives. */
5346
5347 static struct mri_control_info *mri_control_stack;
5348
5349 /* The current MRI structured control directive index number, used to
5350 generate label names. */
5351
5352 static int mri_control_index;
5353
5354 /* Some function prototypes. */
5355
5356 static char *mri_control_label PARAMS ((void));
5357 static struct mri_control_info *push_mri_control
5358 PARAMS ((enum mri_control_type));
5359 static void pop_mri_control PARAMS ((void));
5360 static int parse_mri_condition PARAMS ((int *));
5361 static int parse_mri_control_operand
5362 PARAMS ((int *, char **, char **, char **, char **));
5363 static int swap_mri_condition PARAMS ((int));
5364 static int reverse_mri_condition PARAMS ((int));
5365 static void build_mri_control_operand
5366 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5367 const char *, int));
5368 static void parse_mri_control_expression
5369 PARAMS ((char *, int, const char *, const char *, int));
5370
5371 /* Generate a new MRI label structured control directive label name. */
5372
5373 static char *
5374 mri_control_label ()
5375 {
5376 char *n;
5377
5378 n = (char *) xmalloc (20);
5379 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5380 ++mri_control_index;
5381 return n;
5382 }
5383
5384 /* Create a new MRI structured control directive. */
5385
5386 static struct mri_control_info *
5387 push_mri_control (type)
5388 enum mri_control_type type;
5389 {
5390 struct mri_control_info *n;
5391
5392 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5393
5394 n->type = type;
5395 n->else_seen = 0;
5396 if (type == mri_if || type == mri_while)
5397 n->top = NULL;
5398 else
5399 n->top = mri_control_label ();
5400 n->next = mri_control_label ();
5401 n->bottom = mri_control_label ();
5402
5403 n->outer = mri_control_stack;
5404 mri_control_stack = n;
5405
5406 return n;
5407 }
5408
5409 /* Pop off the stack of MRI structured control directives. */
5410
5411 static void
5412 pop_mri_control ()
5413 {
5414 struct mri_control_info *n;
5415
5416 n = mri_control_stack;
5417 mri_control_stack = n->outer;
5418 if (n->top != NULL)
5419 free (n->top);
5420 free (n->next);
5421 free (n->bottom);
5422 free (n);
5423 }
5424
5425 /* Recognize a condition code in an MRI structured control expression. */
5426
5427 static int
5428 parse_mri_condition (pcc)
5429 int *pcc;
5430 {
5431 char c1, c2;
5432
5433 know (*input_line_pointer == '<');
5434
5435 ++input_line_pointer;
5436 c1 = *input_line_pointer++;
5437 c2 = *input_line_pointer++;
5438
5439 if (*input_line_pointer != '>')
5440 {
5441 as_bad ("syntax error in structured control directive");
5442 return 0;
5443 }
5444
5445 ++input_line_pointer;
5446 SKIP_WHITESPACE ();
5447
5448 if (isupper (c1))
5449 c1 = tolower (c1);
5450 if (isupper (c2))
5451 c2 = tolower (c2);
5452
5453 *pcc = (c1 << 8) | c2;
5454
5455 return 1;
5456 }
5457
5458 /* Parse a single operand in an MRI structured control expression. */
5459
5460 static int
5461 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5462 int *pcc;
5463 char **leftstart;
5464 char **leftstop;
5465 char **rightstart;
5466 char **rightstop;
5467 {
5468 char *s;
5469
5470 SKIP_WHITESPACE ();
5471
5472 *pcc = -1;
5473 *leftstart = NULL;
5474 *leftstop = NULL;
5475 *rightstart = NULL;
5476 *rightstop = NULL;
5477
5478 if (*input_line_pointer == '<')
5479 {
5480 /* It's just a condition code. */
5481 return parse_mri_condition (pcc);
5482 }
5483
5484 /* Look ahead for the condition code. */
5485 for (s = input_line_pointer; *s != '\0'; ++s)
5486 {
5487 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5488 break;
5489 }
5490 if (*s == '\0')
5491 {
5492 as_bad ("missing condition code in structured control directive");
5493 return 0;
5494 }
5495
5496 *leftstart = input_line_pointer;
5497 *leftstop = s;
5498 if (*leftstop > *leftstart
5499 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5500 --*leftstop;
5501
5502 input_line_pointer = s;
5503 if (! parse_mri_condition (pcc))
5504 return 0;
5505
5506 /* Look ahead for AND or OR or end of line. */
5507 for (s = input_line_pointer; *s != '\0'; ++s)
5508 {
5509 if ((strncasecmp (s, "AND", 3) == 0
5510 && (s[3] == '.' || ! is_part_of_name (s[3])))
5511 || (strncasecmp (s, "OR", 2) == 0
5512 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5513 break;
5514 }
5515
5516 *rightstart = input_line_pointer;
5517 *rightstop = s;
5518 if (*rightstop > *rightstart
5519 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5520 --*rightstop;
5521
5522 input_line_pointer = s;
5523
5524 return 1;
5525 }
5526
5527 #define MCC(b1, b2) (((b1) << 8) | (b2))
5528
5529 /* Swap the sense of a condition. This changes the condition so that
5530 it generates the same result when the operands are swapped. */
5531
5532 static int
5533 swap_mri_condition (cc)
5534 int cc;
5535 {
5536 switch (cc)
5537 {
5538 case MCC ('h', 'i'): return MCC ('c', 's');
5539 case MCC ('l', 's'): return MCC ('c', 'c');
5540 case MCC ('c', 'c'): return MCC ('l', 's');
5541 case MCC ('c', 's'): return MCC ('h', 'i');
5542 case MCC ('p', 'l'): return MCC ('m', 'i');
5543 case MCC ('m', 'i'): return MCC ('p', 'l');
5544 case MCC ('g', 'e'): return MCC ('l', 'e');
5545 case MCC ('l', 't'): return MCC ('g', 't');
5546 case MCC ('g', 't'): return MCC ('l', 't');
5547 case MCC ('l', 'e'): return MCC ('g', 'e');
5548 }
5549 return cc;
5550 }
5551
5552 /* Reverse the sense of a condition. */
5553
5554 static int
5555 reverse_mri_condition (cc)
5556 int cc;
5557 {
5558 switch (cc)
5559 {
5560 case MCC ('h', 'i'): return MCC ('l', 's');
5561 case MCC ('l', 's'): return MCC ('h', 'i');
5562 case MCC ('c', 'c'): return MCC ('c', 's');
5563 case MCC ('c', 's'): return MCC ('c', 'c');
5564 case MCC ('n', 'e'): return MCC ('e', 'q');
5565 case MCC ('e', 'q'): return MCC ('n', 'e');
5566 case MCC ('v', 'c'): return MCC ('v', 's');
5567 case MCC ('v', 's'): return MCC ('v', 'c');
5568 case MCC ('p', 'l'): return MCC ('m', 'i');
5569 case MCC ('m', 'i'): return MCC ('p', 'l');
5570 case MCC ('g', 'e'): return MCC ('l', 't');
5571 case MCC ('l', 't'): return MCC ('g', 'e');
5572 case MCC ('g', 't'): return MCC ('l', 'e');
5573 case MCC ('l', 'e'): return MCC ('g', 't');
5574 }
5575 return cc;
5576 }
5577
5578 /* Build an MRI structured control expression. This generates test
5579 and branch instructions. It goes to TRUELAB if the condition is
5580 true, and to FALSELAB if the condition is false. Exactly one of
5581 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5582 is the size qualifier for the expression. EXTENT is the size to
5583 use for the branch. */
5584
5585 static void
5586 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5587 rightstop, truelab, falselab, extent)
5588 int qual;
5589 int cc;
5590 char *leftstart;
5591 char *leftstop;
5592 char *rightstart;
5593 char *rightstop;
5594 const char *truelab;
5595 const char *falselab;
5596 int extent;
5597 {
5598 char *buf;
5599 char *s;
5600
5601 if (leftstart != NULL)
5602 {
5603 struct m68k_op leftop, rightop;
5604 char c;
5605
5606 /* Swap the compare operands, if necessary, to produce a legal
5607 m68k compare instruction. Comparing a register operand with
5608 a non-register operand requires the register to be on the
5609 right (cmp, cmpa). Comparing an immediate value with
5610 anything requires the immediate value to be on the left
5611 (cmpi). */
5612
5613 c = *leftstop;
5614 *leftstop = '\0';
5615 (void) m68k_ip_op (leftstart, &leftop);
5616 *leftstop = c;
5617
5618 c = *rightstop;
5619 *rightstop = '\0';
5620 (void) m68k_ip_op (rightstart, &rightop);
5621 *rightstop = c;
5622
5623 if (rightop.mode == IMMED
5624 || ((leftop.mode == DREG || leftop.mode == AREG)
5625 && (rightop.mode != DREG && rightop.mode != AREG)))
5626 {
5627 char *temp;
5628
5629 cc = swap_mri_condition (cc);
5630 temp = leftstart;
5631 leftstart = rightstart;
5632 rightstart = temp;
5633 temp = leftstop;
5634 leftstop = rightstop;
5635 rightstop = temp;
5636 }
5637 }
5638
5639 if (truelab == NULL)
5640 {
5641 cc = reverse_mri_condition (cc);
5642 truelab = falselab;
5643 }
5644
5645 if (leftstart != NULL)
5646 {
5647 buf = (char *) xmalloc (20
5648 + (leftstop - leftstart)
5649 + (rightstop - rightstart));
5650 s = buf;
5651 *s++ = 'c';
5652 *s++ = 'm';
5653 *s++ = 'p';
5654 if (qual != '\0')
5655 *s++ = qual;
5656 *s++ = ' ';
5657 memcpy (s, leftstart, leftstop - leftstart);
5658 s += leftstop - leftstart;
5659 *s++ = ',';
5660 memcpy (s, rightstart, rightstop - rightstart);
5661 s += rightstop - rightstart;
5662 *s = '\0';
5663 md_assemble (buf);
5664 free (buf);
5665 }
5666
5667 buf = (char *) xmalloc (20 + strlen (truelab));
5668 s = buf;
5669 *s++ = 'b';
5670 *s++ = cc >> 8;
5671 *s++ = cc & 0xff;
5672 if (extent != '\0')
5673 *s++ = extent;
5674 *s++ = ' ';
5675 strcpy (s, truelab);
5676 md_assemble (buf);
5677 free (buf);
5678 }
5679
5680 /* Parse an MRI structured control expression. This generates test
5681 and branch instructions. STOP is where the expression ends. It
5682 goes to TRUELAB if the condition is true, and to FALSELAB if the
5683 condition is false. Exactly one of TRUELAB and FALSELAB will be
5684 NULL, meaning to fall through. QUAL is the size qualifier for the
5685 expression. EXTENT is the size to use for the branch. */
5686
5687 static void
5688 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5689 char *stop;
5690 int qual;
5691 const char *truelab;
5692 const char *falselab;
5693 int extent;
5694 {
5695 int c;
5696 int cc;
5697 char *leftstart;
5698 char *leftstop;
5699 char *rightstart;
5700 char *rightstop;
5701
5702 c = *stop;
5703 *stop = '\0';
5704
5705 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5706 &rightstart, &rightstop))
5707 {
5708 *stop = c;
5709 return;
5710 }
5711
5712 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5713 {
5714 const char *flab;
5715
5716 if (falselab != NULL)
5717 flab = falselab;
5718 else
5719 flab = mri_control_label ();
5720
5721 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5722 rightstop, (const char *) NULL, flab, extent);
5723
5724 input_line_pointer += 3;
5725 if (*input_line_pointer != '.'
5726 || input_line_pointer[1] == '\0')
5727 qual = '\0';
5728 else
5729 {
5730 qual = input_line_pointer[1];
5731 input_line_pointer += 2;
5732 }
5733
5734 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5735 &rightstart, &rightstop))
5736 {
5737 *stop = c;
5738 return;
5739 }
5740
5741 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5742 rightstop, truelab, falselab, extent);
5743
5744 if (falselab == NULL)
5745 colon (flab);
5746 }
5747 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5748 {
5749 const char *tlab;
5750
5751 if (truelab != NULL)
5752 tlab = truelab;
5753 else
5754 tlab = mri_control_label ();
5755
5756 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5757 rightstop, tlab, (const char *) NULL, extent);
5758
5759 input_line_pointer += 2;
5760 if (*input_line_pointer != '.'
5761 || input_line_pointer[1] == '\0')
5762 qual = '\0';
5763 else
5764 {
5765 qual = input_line_pointer[1];
5766 input_line_pointer += 2;
5767 }
5768
5769 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5770 &rightstart, &rightstop))
5771 {
5772 *stop = c;
5773 return;
5774 }
5775
5776 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5777 rightstop, truelab, falselab, extent);
5778
5779 if (truelab == NULL)
5780 colon (tlab);
5781 }
5782 else
5783 {
5784 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5785 rightstop, truelab, falselab, extent);
5786 }
5787
5788 *stop = c;
5789 if (input_line_pointer != stop)
5790 as_bad ("syntax error in structured control directive");
5791 }
5792
5793 /* Handle the MRI IF pseudo-op. This may be a structured control
5794 directive, or it may be a regular assembler conditional, depending
5795 on its operands. */
5796
5797 static void
5798 s_mri_if (qual)
5799 int qual;
5800 {
5801 char *s;
5802 int c;
5803 struct mri_control_info *n;
5804
5805 /* A structured control directive must end with THEN with an
5806 optional qualifier. */
5807 s = input_line_pointer;
5808 while (! is_end_of_line[(unsigned char) *s]
5809 && (! flag_mri || *s != '*'))
5810 ++s;
5811 --s;
5812 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5813 --s;
5814
5815 if (s - input_line_pointer > 1
5816 && s[-1] == '.')
5817 s -= 2;
5818
5819 if (s - input_line_pointer < 3
5820 || strncasecmp (s - 3, "THEN", 4) != 0)
5821 {
5822 if (qual != '\0')
5823 {
5824 as_bad ("missing then");
5825 ignore_rest_of_line ();
5826 return;
5827 }
5828
5829 /* It's a conditional. */
5830 s_if (O_ne);
5831 return;
5832 }
5833
5834 /* Since this might be a conditional if, this pseudo-op will be
5835 called even if we are supported to be ignoring input. Double
5836 check now. Clobber *input_line_pointer so that ignore_input
5837 thinks that this is not a special pseudo-op. */
5838 c = *input_line_pointer;
5839 *input_line_pointer = 0;
5840 if (ignore_input ())
5841 {
5842 *input_line_pointer = c;
5843 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5844 ++input_line_pointer;
5845 demand_empty_rest_of_line ();
5846 return;
5847 }
5848 *input_line_pointer = c;
5849
5850 n = push_mri_control (mri_if);
5851
5852 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5853 n->next, s[1] == '.' ? s[2] : '\0');
5854
5855 if (s[1] == '.')
5856 input_line_pointer = s + 3;
5857 else
5858 input_line_pointer = s + 1;
5859
5860 if (flag_mri)
5861 {
5862 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5863 ++input_line_pointer;
5864 }
5865
5866 demand_empty_rest_of_line ();
5867 }
5868
5869 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5870 structured IF, associate the ELSE with the IF. Otherwise, assume
5871 it is a conditional else. */
5872
5873 static void
5874 s_mri_else (qual)
5875 int qual;
5876 {
5877 int c;
5878 char *buf;
5879 char q[2];
5880
5881 if (qual == '\0'
5882 && (mri_control_stack == NULL
5883 || mri_control_stack->type != mri_if
5884 || mri_control_stack->else_seen))
5885 {
5886 s_else (0);
5887 return;
5888 }
5889
5890 c = *input_line_pointer;
5891 *input_line_pointer = 0;
5892 if (ignore_input ())
5893 {
5894 *input_line_pointer = c;
5895 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5896 ++input_line_pointer;
5897 demand_empty_rest_of_line ();
5898 return;
5899 }
5900 *input_line_pointer = c;
5901
5902 if (mri_control_stack == NULL
5903 || mri_control_stack->type != mri_if
5904 || mri_control_stack->else_seen)
5905 {
5906 as_bad ("else without matching if");
5907 ignore_rest_of_line ();
5908 return;
5909 }
5910
5911 mri_control_stack->else_seen = 1;
5912
5913 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5914 q[0] = qual;
5915 q[1] = '\0';
5916 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5917 md_assemble (buf);
5918 free (buf);
5919
5920 colon (mri_control_stack->next);
5921
5922 if (flag_mri)
5923 {
5924 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5925 ++input_line_pointer;
5926 }
5927
5928 demand_empty_rest_of_line ();
5929 }
5930
5931 /* Handle the MRI ENDI pseudo-op. */
5932
5933 static void
5934 s_mri_endi (ignore)
5935 int ignore;
5936 {
5937 if (mri_control_stack == NULL
5938 || mri_control_stack->type != mri_if)
5939 {
5940 as_bad ("endi without matching if");
5941 ignore_rest_of_line ();
5942 return;
5943 }
5944
5945 /* ignore_input will not return true for ENDI, so we don't need to
5946 worry about checking it again here. */
5947
5948 if (! mri_control_stack->else_seen)
5949 colon (mri_control_stack->next);
5950 colon (mri_control_stack->bottom);
5951
5952 pop_mri_control ();
5953
5954 if (flag_mri)
5955 {
5956 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5957 ++input_line_pointer;
5958 }
5959
5960 demand_empty_rest_of_line ();
5961 }
5962
5963 /* Handle the MRI BREAK pseudo-op. */
5964
5965 static void
5966 s_mri_break (extent)
5967 int extent;
5968 {
5969 struct mri_control_info *n;
5970 char *buf;
5971 char ex[2];
5972
5973 n = mri_control_stack;
5974 while (n != NULL
5975 && n->type != mri_for
5976 && n->type != mri_repeat
5977 && n->type != mri_while)
5978 n = n->outer;
5979 if (n == NULL)
5980 {
5981 as_bad ("break outside of structured loop");
5982 ignore_rest_of_line ();
5983 return;
5984 }
5985
5986 buf = (char *) xmalloc (20 + strlen (n->bottom));
5987 ex[0] = extent;
5988 ex[1] = '\0';
5989 sprintf (buf, "bra%s %s", ex, n->bottom);
5990 md_assemble (buf);
5991 free (buf);
5992
5993 if (flag_mri)
5994 {
5995 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5996 ++input_line_pointer;
5997 }
5998
5999 demand_empty_rest_of_line ();
6000 }
6001
6002 /* Handle the MRI NEXT pseudo-op. */
6003
6004 static void
6005 s_mri_next (extent)
6006 int extent;
6007 {
6008 struct mri_control_info *n;
6009 char *buf;
6010 char ex[2];
6011
6012 n = mri_control_stack;
6013 while (n != NULL
6014 && n->type != mri_for
6015 && n->type != mri_repeat
6016 && n->type != mri_while)
6017 n = n->outer;
6018 if (n == NULL)
6019 {
6020 as_bad ("next outside of structured loop");
6021 ignore_rest_of_line ();
6022 return;
6023 }
6024
6025 buf = (char *) xmalloc (20 + strlen (n->next));
6026 ex[0] = extent;
6027 ex[1] = '\0';
6028 sprintf (buf, "bra%s %s", ex, n->next);
6029 md_assemble (buf);
6030 free (buf);
6031
6032 if (flag_mri)
6033 {
6034 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6035 ++input_line_pointer;
6036 }
6037
6038 demand_empty_rest_of_line ();
6039 }
6040
6041 /* Handle the MRI FOR pseudo-op. */
6042
6043 static void
6044 s_mri_for (qual)
6045 int qual;
6046 {
6047 const char *varstart, *varstop;
6048 const char *initstart, *initstop;
6049 const char *endstart, *endstop;
6050 const char *bystart, *bystop;
6051 int up;
6052 int by;
6053 int extent;
6054 struct mri_control_info *n;
6055 char *buf;
6056 char *s;
6057 char ex[2];
6058
6059 /* The syntax is
6060 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6061 */
6062
6063 SKIP_WHITESPACE ();
6064 varstart = input_line_pointer;
6065
6066 /* Look for the '='. */
6067 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6068 && *input_line_pointer != '=')
6069 ++input_line_pointer;
6070 if (*input_line_pointer != '=')
6071 {
6072 as_bad ("missing =");
6073 ignore_rest_of_line ();
6074 return;
6075 }
6076
6077 varstop = input_line_pointer;
6078 if (varstop > varstart
6079 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6080 --varstop;
6081
6082 ++input_line_pointer;
6083
6084 initstart = input_line_pointer;
6085
6086 /* Look for TO or DOWNTO. */
6087 up = 1;
6088 initstop = NULL;
6089 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6090 {
6091 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6092 && ! is_part_of_name (input_line_pointer[2]))
6093 {
6094 initstop = input_line_pointer;
6095 input_line_pointer += 2;
6096 break;
6097 }
6098 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6099 && ! is_part_of_name (input_line_pointer[6]))
6100 {
6101 initstop = input_line_pointer;
6102 up = 0;
6103 input_line_pointer += 6;
6104 break;
6105 }
6106 ++input_line_pointer;
6107 }
6108 if (initstop == NULL)
6109 {
6110 as_bad ("missing to or downto");
6111 ignore_rest_of_line ();
6112 return;
6113 }
6114 if (initstop > initstart
6115 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6116 --initstop;
6117
6118 SKIP_WHITESPACE ();
6119 endstart = input_line_pointer;
6120
6121 /* Look for BY or DO. */
6122 by = 0;
6123 endstop = NULL;
6124 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6125 {
6126 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6127 && ! is_part_of_name (input_line_pointer[2]))
6128 {
6129 endstop = input_line_pointer;
6130 by = 1;
6131 input_line_pointer += 2;
6132 break;
6133 }
6134 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6135 && (input_line_pointer[2] == '.'
6136 || ! is_part_of_name (input_line_pointer[2])))
6137 {
6138 endstop = input_line_pointer;
6139 input_line_pointer += 2;
6140 break;
6141 }
6142 ++input_line_pointer;
6143 }
6144 if (endstop == NULL)
6145 {
6146 as_bad ("missing do");
6147 ignore_rest_of_line ();
6148 return;
6149 }
6150 if (endstop > endstart
6151 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6152 --endstop;
6153
6154 if (! by)
6155 {
6156 bystart = "#1";
6157 bystop = bystart + 2;
6158 }
6159 else
6160 {
6161 SKIP_WHITESPACE ();
6162 bystart = input_line_pointer;
6163
6164 /* Look for DO. */
6165 bystop = NULL;
6166 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6167 {
6168 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6169 && (input_line_pointer[2] == '.'
6170 || ! is_part_of_name (input_line_pointer[2])))
6171 {
6172 bystop = input_line_pointer;
6173 input_line_pointer += 2;
6174 break;
6175 }
6176 ++input_line_pointer;
6177 }
6178 if (bystop == NULL)
6179 {
6180 as_bad ("missing do");
6181 ignore_rest_of_line ();
6182 return;
6183 }
6184 if (bystop > bystart
6185 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6186 --bystop;
6187 }
6188
6189 if (*input_line_pointer != '.')
6190 extent = '\0';
6191 else
6192 {
6193 extent = input_line_pointer[1];
6194 input_line_pointer += 2;
6195 }
6196
6197 /* We have fully parsed the FOR operands. Now build the loop. */
6198
6199 n = push_mri_control (mri_for);
6200
6201 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6202
6203 /* move init,var */
6204 s = buf;
6205 *s++ = 'm';
6206 *s++ = 'o';
6207 *s++ = 'v';
6208 *s++ = 'e';
6209 if (qual != '\0')
6210 *s++ = qual;
6211 *s++ = ' ';
6212 memcpy (s, initstart, initstop - initstart);
6213 s += initstop - initstart;
6214 *s++ = ',';
6215 memcpy (s, varstart, varstop - varstart);
6216 s += varstop - varstart;
6217 *s = '\0';
6218 md_assemble (buf);
6219
6220 colon (n->top);
6221
6222 /* cmp end,var */
6223 s = buf;
6224 *s++ = 'c';
6225 *s++ = 'm';
6226 *s++ = 'p';
6227 if (qual != '\0')
6228 *s++ = qual;
6229 *s++ = ' ';
6230 memcpy (s, endstart, endstop - endstart);
6231 s += endstop - endstart;
6232 *s++ = ',';
6233 memcpy (s, varstart, varstop - varstart);
6234 s += varstop - varstart;
6235 *s = '\0';
6236 md_assemble (buf);
6237
6238 /* bcc bottom */
6239 ex[0] = extent;
6240 ex[1] = '\0';
6241 if (up)
6242 sprintf (buf, "blt%s %s", ex, n->bottom);
6243 else
6244 sprintf (buf, "bgt%s %s", ex, n->bottom);
6245 md_assemble (buf);
6246
6247 /* Put together the add or sub instruction used by ENDF. */
6248 s = buf;
6249 if (up)
6250 strcpy (s, "add");
6251 else
6252 strcpy (s, "sub");
6253 s += 3;
6254 if (qual != '\0')
6255 *s++ = qual;
6256 *s++ = ' ';
6257 memcpy (s, bystart, bystop - bystart);
6258 s += bystop - bystart;
6259 *s++ = ',';
6260 memcpy (s, varstart, varstop - varstart);
6261 s += varstop - varstart;
6262 *s = '\0';
6263 n->incr = buf;
6264
6265 if (flag_mri)
6266 {
6267 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6268 ++input_line_pointer;
6269 }
6270
6271 demand_empty_rest_of_line ();
6272 }
6273
6274 /* Handle the MRI ENDF pseudo-op. */
6275
6276 static void
6277 s_mri_endf (ignore)
6278 int ignore;
6279 {
6280 if (mri_control_stack == NULL
6281 || mri_control_stack->type != mri_for)
6282 {
6283 as_bad ("endf without for");
6284 ignore_rest_of_line ();
6285 return;
6286 }
6287
6288 colon (mri_control_stack->next);
6289
6290 md_assemble (mri_control_stack->incr);
6291
6292 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6293 md_assemble (mri_control_stack->incr);
6294
6295 free (mri_control_stack->incr);
6296
6297 colon (mri_control_stack->bottom);
6298
6299 pop_mri_control ();
6300
6301 if (flag_mri)
6302 {
6303 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6304 ++input_line_pointer;
6305 }
6306
6307 demand_empty_rest_of_line ();
6308 }
6309
6310 /* Handle the MRI REPEAT pseudo-op. */
6311
6312 static void
6313 s_mri_repeat (ignore)
6314 int ignore;
6315 {
6316 struct mri_control_info *n;
6317
6318 n = push_mri_control (mri_repeat);
6319 colon (n->top);
6320 if (flag_mri)
6321 {
6322 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6323 ++input_line_pointer;
6324 }
6325 demand_empty_rest_of_line ();
6326 }
6327
6328 /* Handle the MRI UNTIL pseudo-op. */
6329
6330 static void
6331 s_mri_until (qual)
6332 int qual;
6333 {
6334 char *s;
6335
6336 if (mri_control_stack == NULL
6337 || mri_control_stack->type != mri_repeat)
6338 {
6339 as_bad ("until without repeat");
6340 ignore_rest_of_line ();
6341 return;
6342 }
6343
6344 colon (mri_control_stack->next);
6345
6346 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6347 ;
6348
6349 parse_mri_control_expression (s, qual, (const char *) NULL,
6350 mri_control_stack->top, '\0');
6351
6352 colon (mri_control_stack->bottom);
6353
6354 input_line_pointer = s;
6355
6356 pop_mri_control ();
6357
6358 if (flag_mri)
6359 {
6360 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6361 ++input_line_pointer;
6362 }
6363
6364 demand_empty_rest_of_line ();
6365 }
6366
6367 /* Handle the MRI WHILE pseudo-op. */
6368
6369 static void
6370 s_mri_while (qual)
6371 int qual;
6372 {
6373 char *s;
6374
6375 struct mri_control_info *n;
6376
6377 s = input_line_pointer;
6378 while (! is_end_of_line[(unsigned char) *s]
6379 && (! flag_mri || *s != '*'))
6380 s++;
6381 --s;
6382 while (*s == ' ' || *s == '\t')
6383 --s;
6384 if (s - input_line_pointer > 1
6385 && s[-1] == '.')
6386 s -= 2;
6387 if (s - input_line_pointer < 2
6388 || strncasecmp (s - 1, "DO", 2) != 0)
6389 {
6390 as_bad ("missing do");
6391 ignore_rest_of_line ();
6392 return;
6393 }
6394
6395 n = push_mri_control (mri_while);
6396
6397 colon (n->next);
6398
6399 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6400 s[1] == '.' ? s[2] : '\0');
6401
6402 input_line_pointer = s + 1;
6403 if (*input_line_pointer == '.')
6404 input_line_pointer += 2;
6405
6406 if (flag_mri)
6407 {
6408 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6409 ++input_line_pointer;
6410 }
6411
6412 demand_empty_rest_of_line ();
6413 }
6414
6415 /* Handle the MRI ENDW pseudo-op. */
6416
6417 static void
6418 s_mri_endw (ignore)
6419 int ignore;
6420 {
6421 char *buf;
6422
6423 if (mri_control_stack == NULL
6424 || mri_control_stack->type != mri_while)
6425 {
6426 as_bad ("endw without while");
6427 ignore_rest_of_line ();
6428 return;
6429 }
6430
6431 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6432 sprintf (buf, "bra %s", mri_control_stack->next);
6433 md_assemble (buf);
6434 free (buf);
6435
6436 colon (mri_control_stack->bottom);
6437
6438 pop_mri_control ();
6439
6440 if (flag_mri)
6441 {
6442 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6443 ++input_line_pointer;
6444 }
6445
6446 demand_empty_rest_of_line ();
6447 }
6448 \f
6449 /*
6450 * md_parse_option
6451 * Invocation line includes a switch not recognized by the base assembler.
6452 * See if it's a processor-specific option. These are:
6453 *
6454 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6455 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6456 * Select the architecture. Instructions or features not
6457 * supported by the selected architecture cause fatal
6458 * errors. More than one may be specified. The default is
6459 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6460 * for -m68000, and -m68882 is a synonym for -m68881.
6461 * -[A]m[c]no-68851, -[A]m[c]no-68881
6462 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6463 * so don't use or document it, but that's the way the parsing
6464 * works).
6465 *
6466 * -pic Indicates PIC.
6467 * -k Indicates PIC. (Sun 3 only.)
6468 *
6469 * --bitwise-or
6470 * Permit `|' to be used in expressions.
6471 *
6472 */
6473
6474 #ifdef OBJ_ELF
6475 CONST char *md_shortopts = "lSA:m:kQ:V";
6476 #else
6477 CONST char *md_shortopts = "lSA:m:k";
6478 #endif
6479
6480 struct option md_longopts[] = {
6481 #define OPTION_PIC (OPTION_MD_BASE)
6482 {"pic", no_argument, NULL, OPTION_PIC},
6483 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6484 {"register-prefix-optional", no_argument, NULL,
6485 OPTION_REGISTER_PREFIX_OPTIONAL},
6486 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6487 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6488 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6489 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6490 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6491 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6492 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6493 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6494 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6495 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6496 {NULL, no_argument, NULL, 0}
6497 };
6498 size_t md_longopts_size = sizeof(md_longopts);
6499
6500 int
6501 md_parse_option (c, arg)
6502 int c;
6503 char *arg;
6504 {
6505 switch (c)
6506 {
6507 case 'l': /* -l means keep external to 2 bit offset
6508 rather than 16 bit one */
6509 flag_short_refs = 1;
6510 break;
6511
6512 case 'S': /* -S means that jbsr's always turn into
6513 jsr's. */
6514 flag_long_jumps = 1;
6515 break;
6516
6517 case 'A':
6518 if (*arg == 'm')
6519 arg++;
6520 /* intentional fall-through */
6521 case 'm':
6522
6523 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6524 {
6525 int i;
6526 unsigned long arch;
6527 const char *oarg = arg;
6528
6529 arg += 3;
6530 if (*arg == 'm')
6531 {
6532 arg++;
6533 if (arg[0] == 'c' && arg[1] == '6')
6534 arg++;
6535 }
6536 for (i = 0; i < n_archs; i++)
6537 if (!strcmp (arg, archs[i].name))
6538 break;
6539 if (i == n_archs)
6540 {
6541 unknown:
6542 as_bad ("unrecognized option `%s'", oarg);
6543 return 0;
6544 }
6545 arch = archs[i].arch;
6546 if (arch == m68881)
6547 no_68881 = 1;
6548 else if (arch == m68851)
6549 no_68851 = 1;
6550 else
6551 goto unknown;
6552 }
6553 else
6554 {
6555 int i;
6556
6557 if (arg[0] == 'c' && arg[1] == '6')
6558 arg++;
6559
6560 for (i = 0; i < n_archs; i++)
6561 if (!strcmp (arg, archs[i].name))
6562 {
6563 unsigned long arch = archs[i].arch;
6564 if (cpu_of_arch (arch))
6565 /* It's a cpu spec. */
6566 {
6567 current_architecture &= ~m68000up;
6568 current_architecture |= arch;
6569 }
6570 else if (arch == m68881)
6571 {
6572 current_architecture |= m68881;
6573 no_68881 = 0;
6574 }
6575 else if (arch == m68851)
6576 {
6577 current_architecture |= m68851;
6578 no_68851 = 0;
6579 }
6580 else
6581 /* ??? */
6582 abort ();
6583 break;
6584 }
6585 if (i == n_archs)
6586 {
6587 as_bad ("unrecognized architecture specification `%s'", arg);
6588 return 0;
6589 }
6590 }
6591 break;
6592
6593 case OPTION_PIC:
6594 case 'k':
6595 flag_want_pic = 1;
6596 break; /* -pic, Position Independent Code */
6597
6598 case OPTION_REGISTER_PREFIX_OPTIONAL:
6599 flag_reg_prefix_optional = 1;
6600 reg_prefix_optional_seen = 1;
6601 break;
6602
6603 /* -V: SVR4 argument to print version ID. */
6604 case 'V':
6605 print_version_id ();
6606 break;
6607
6608 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6609 should be emitted or not. FIXME: Not implemented. */
6610 case 'Q':
6611 break;
6612
6613 case OPTION_BITWISE_OR:
6614 {
6615 char *n, *t;
6616 const char *s;
6617
6618 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6619 t = n;
6620 for (s = m68k_comment_chars; *s != '\0'; s++)
6621 if (*s != '|')
6622 *t++ = *s;
6623 *t = '\0';
6624 m68k_comment_chars = n;
6625 }
6626 break;
6627
6628 case OPTION_BASE_SIZE_DEFAULT_16:
6629 m68k_index_width_default = SIZE_WORD;
6630 break;
6631
6632 case OPTION_BASE_SIZE_DEFAULT_32:
6633 m68k_index_width_default = SIZE_LONG;
6634 break;
6635
6636 case OPTION_DISP_SIZE_DEFAULT_16:
6637 m68k_rel32 = 0;
6638 m68k_rel32_from_cmdline = 1;
6639 break;
6640
6641 case OPTION_DISP_SIZE_DEFAULT_32:
6642 m68k_rel32 = 1;
6643 m68k_rel32_from_cmdline = 1;
6644 break;
6645
6646 default:
6647 return 0;
6648 }
6649
6650 return 1;
6651 }
6652
6653 void
6654 md_show_usage (stream)
6655 FILE *stream;
6656 {
6657 fprintf(stream, "\
6658 680X0 options:\n\
6659 -l use 1 word for refs to undefined symbols [default 2]\n\
6660 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6661 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6662 | -mcpu32 | -m5200\n\
6663 specify variant of 680X0 architecture [default 68020]\n\
6664 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6665 target has/lacks floating-point coprocessor\n\
6666 [default yes for 68020, 68030, and cpu32]\n");
6667 fprintf(stream, "\
6668 -m68851 | -mno-68851\n\
6669 target has/lacks memory-management unit coprocessor\n\
6670 [default yes for 68020 and up]\n\
6671 -pic, -k generate position independent code\n\
6672 -S turn jbsr into jsr\n\
6673 --register-prefix-optional\n\
6674 recognize register names without prefix character\n\
6675 --bitwise-or do not treat `|' as a comment character\n");
6676 fprintf (stream, "\
6677 --base-size-default-16 base reg without size is 16 bits\n\
6678 --base-size-default-32 base reg without size is 32 bits (default)\n\
6679 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6680 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n");
6681 }
6682 \f
6683 #ifdef TEST2
6684
6685 /* TEST2: Test md_assemble() */
6686 /* Warning, this routine probably doesn't work anymore */
6687
6688 main ()
6689 {
6690 struct m68k_it the_ins;
6691 char buf[120];
6692 char *cp;
6693 int n;
6694
6695 m68k_ip_begin ();
6696 for (;;)
6697 {
6698 if (!gets (buf) || !*buf)
6699 break;
6700 if (buf[0] == '|' || buf[1] == '.')
6701 continue;
6702 for (cp = buf; *cp; cp++)
6703 if (*cp == '\t')
6704 *cp = ' ';
6705 if (is_label (buf))
6706 continue;
6707 memset (&the_ins, '\0', sizeof (the_ins));
6708 m68k_ip (&the_ins, buf);
6709 if (the_ins.error)
6710 {
6711 printf ("Error %s in %s\n", the_ins.error, buf);
6712 }
6713 else
6714 {
6715 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6716 for (n = 0; n < the_ins.numo; n++)
6717 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6718 printf (" ");
6719 print_the_insn (&the_ins.opcode[0], stdout);
6720 (void) putchar ('\n');
6721 }
6722 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6723 {
6724 if (the_ins.operands[n].error)
6725 {
6726 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6727 continue;
6728 }
6729 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6730 if (the_ins.operands[n].b_const)
6731 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6732 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6733 if (the_ins.operands[n].b_iadd)
6734 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6735 (void) putchar ('\n');
6736 }
6737 }
6738 m68k_ip_end ();
6739 return 0;
6740 }
6741
6742 is_label (str)
6743 char *str;
6744 {
6745 while (*str == ' ')
6746 str++;
6747 while (*str && *str != ' ')
6748 str++;
6749 if (str[-1] == ':' || str[1] == '=')
6750 return 1;
6751 return 0;
6752 }
6753
6754 #endif
6755
6756 /* Possible states for relaxation:
6757
6758 0 0 branch offset byte (bra, etc)
6759 0 1 word
6760 0 2 long
6761
6762 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6763 1 1 word
6764 1 2 long
6765
6766 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6767 2 1 word-long
6768 2 2 long-word
6769 2 3 long-long
6770
6771 */
6772
6773 /* We have no need to default values of symbols. */
6774
6775 /* ARGSUSED */
6776 symbolS *
6777 md_undefined_symbol (name)
6778 char *name;
6779 {
6780 return 0;
6781 }
6782
6783 /* Round up a section size to the appropriate boundary. */
6784 valueT
6785 md_section_align (segment, size)
6786 segT segment;
6787 valueT size;
6788 {
6789 return size; /* Byte alignment is fine */
6790 }
6791
6792 /* Exactly what point is a PC-relative offset relative TO?
6793 On the 68k, it is relative to the address of the first extension
6794 word. The difference between the addresses of the offset and the
6795 first extension word is stored in fx_pcrel_adjust. */
6796 long
6797 md_pcrel_from (fixP)
6798 fixS *fixP;
6799 {
6800 int adjust;
6801
6802 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6803 -1 as 64. */
6804 adjust = fixP->fx_pcrel_adjust;
6805 if (adjust == 64)
6806 adjust = -1;
6807 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6808 }
6809
6810 #ifndef BFD_ASSEMBLER
6811 /*ARGSUSED*/
6812 void
6813 tc_coff_symbol_emit_hook (ignore)
6814 symbolS *ignore;
6815 {
6816 }
6817
6818 int
6819 tc_coff_sizemachdep (frag)
6820 fragS *frag;
6821 {
6822 switch (frag->fr_subtype & 0x3)
6823 {
6824 case BYTE:
6825 return 1;
6826 case SHORT:
6827 return 2;
6828 case LONG:
6829 return 4;
6830 default:
6831 abort ();
6832 return 0;
6833 }
6834 }
6835 #endif
6836
6837 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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