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m68k_ip: for pc-rel addressing of a symbol, fix offset so +2 isn't needed
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
2 slow to compile, easy to find file.
3
4 Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21
22 #include <ctype.h>
23 #define NO_RELOC 0
24 #include "as.h"
25
26 #include "obstack.h"
27
28 /* note that this file includes real declarations and thus can only be included by one source file per executable. */
29 #include "opcode/m68k.h"
30
31 #ifdef TE_SUN
32 /* This variable contains the value to write out at the beginning of
33 the a.out file. The 2<<16 means that this is a 68020 file instead
34 of an old-style 68000 file */
35
36 long omagic = 2 << 16 | OMAGIC; /* Magic byte for header file */
37 #else
38 long omagic = OMAGIC;
39 #endif
40
41 /* This array holds the chars that always start a comment. If the
42 pre-processor is disabled, these aren't very useful */
43 const char comment_chars[] = "|";
44
45 /* This array holds the chars that only start a comment at the beginning of
46 a line. If the line seems to have the form '# 123 filename'
47 .line and .file directives will appear in the pre-processed output */
48 /* Note that input_file.c hand checks for '#' at the beginning of the
49 first line of the input file. This is because the compiler outputs
50 #NO_APP at the beginning of its output. */
51 /* Also note that comments like this one will always work. */
52 const char line_comment_chars[] = "#";
53
54 const char line_separator_chars[] = "";
55
56 /* Chars that can be used to separate mant from exp in floating point nums */
57 const char EXP_CHARS[] = "eE";
58
59 /* Chars that mean this number is a floating point constant */
60 /* As in 0f12.456 */
61 /* or 0d1.2345e12 */
62
63 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
64
65 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here.
68 */
69
70 int md_reloc_size = 8; /* Size of relocation record */
71
72 /* Its an arbitrary name: This means I don't approve of it */
73 /* See flames below */
74 static struct obstack robyn;
75
76 #define TAB(x,y) (((x)<<2)+(y))
77 #define TABTYPE(xy) ((xy) >> 2)
78 #define BYTE 0
79 #define SHORT 1
80 #define LONG 2
81 #define SZ_UNDEF 3
82 #undef BRANCH
83 #define ABRANCH 1
84 #define FBRANCH 2
85 #define PCREL 3
86 #define BCC68000 4
87 #define DBCC 5
88 #define PCLEA 6
89
90 /* Operands we can parse: (And associated modes)
91
92 numb: 8 bit num
93 numw: 16 bit num
94 numl: 32 bit num
95 dreg: data reg 0-7
96 reg: address or data register
97 areg: address register
98 apc: address register, PC, ZPC or empty string
99 num: 16 or 32 bit num
100 num2: like num
101 sz: w or l if omitted, l assumed
102 scale: 1 2 4 or 8 if omitted, 1 assumed
103
104 7.4 IMMED #num --> NUM
105 0.? DREG dreg --> dreg
106 1.? AREG areg --> areg
107 2.? AINDR areg@ --> *(areg)
108 3.? AINC areg@+ --> *(areg++)
109 4.? ADEC areg@- --> *(--areg)
110 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
111 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
112 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
113 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
114 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
115 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
116 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
117 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
118 7.0 ABSL num:sz --> *(num)
119 num --> *(num) (sz L assumed)
120 *** MSCR otherreg --> Magic
121 With -l option
122 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
123 ?.? DINDR dreg@ --> (dreg) -- cas2 only
124
125 examples:
126 #foo #0x35 #12
127 d2
128 a4
129 a3@
130 a5@+
131 a6@-
132 a2@(12) pc@(14)
133 a1@(5,d2:w:1) @(45,d6:l:4)
134 pc@(a2) @(d4)
135 etc . . .
136
137
138 #name@(numw) -->turn into PC rel mode
139 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
140
141 */
142
143 enum operand_type
144 {
145 IMMED = 1,
146 DREG,
147 AREG,
148 AINDR,
149 ADEC,
150 AINC,
151 AOFF,
152 AINDX,
153 APODX,
154 AMIND,
155 APRDX,
156 ABSL,
157 MSCR,
158 REGLST,
159 DINDR
160 };
161
162
163 struct m68k_exp
164 {
165 char *e_beg;
166 char *e_end;
167 expressionS e_exp;
168 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
169 };
170
171 /* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
172 8-15==addr reg for operands that take both types */
173
174 enum _register
175 {
176 DATA = 1, /* 1- 8 == data registers 0-7 */
177 DATA0 = DATA,
178 DATA1,
179 DATA2,
180 DATA3,
181 DATA4,
182 DATA5,
183 DATA6,
184 DATA7,
185
186 ADDR,
187 ADDR0 = ADDR,
188 ADDR1,
189 ADDR2,
190 ADDR3,
191 ADDR4,
192 ADDR5,
193 ADDR6,
194 ADDR7,
195
196 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
197 /* I think. . . */
198
199 SP = ADDR7,
200
201 FPREG, /* Eight FP registers */
202 FP0 = FPREG,
203 FP1,
204 FP2,
205 FP3,
206 FP4,
207 FP5,
208 FP6,
209 FP7,
210 COPNUM = (FPREG + 8), /* Co-processor #1-#8 */
211 COP0 = COPNUM,
212 COP1,
213 COP2,
214 COP3,
215 COP4,
216 COP5,
217 COP6,
218 COP7,
219 PC, /* Program counter */
220 ZPC, /* Hack for Program space, but 0 addressing */
221 SR, /* Status Reg */
222 CCR, /* Condition code Reg */
223
224 /* These have to be in order for the movec instruction to work. */
225 USP, /* User Stack Pointer */
226 ISP, /* Interrupt stack pointer */
227 SFC,
228 DFC,
229 CACR,
230 VBR,
231 CAAR,
232 MSP,
233 ITT0,
234 ITT1,
235 DTT0,
236 DTT1,
237 MMUSR,
238 TC,
239 SRP,
240 URP,
241 /* end of movec ordering constraints */
242
243 FPI,
244 FPS,
245 FPC,
246
247 DRP, /* 68851 or 68030 MMU regs */
248 CRP,
249 CAL,
250 VAL,
251 SCC,
252 AC,
253 BAD,
254 BAD0 = BAD,
255 BAD1,
256 BAD2,
257 BAD3,
258 BAD4,
259 BAD5,
260 BAD6,
261 BAD7,
262 BAC,
263 BAC0 = BAC,
264 BAC1,
265 BAC2,
266 BAC3,
267 BAC4,
268 BAC5,
269 BAC6,
270 BAC7,
271 PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040)
272 and ACUSR on 68ec030 */
273 PCSR,
274
275 IC, /* instruction cache token */
276 DC, /* data cache token */
277 NC, /* no cache token */
278 BC, /* both caches token */
279
280 TT0, /* 68030 access control unit regs */
281 TT1,
282 };
283
284 /* Internal form of an operand. */
285 struct m68k_op
286 {
287 char *error; /* Couldn't parse it */
288 enum operand_type mode; /* What mode this instruction is in. */
289 enum _register reg; /* Base register */
290 struct m68k_exp *con1;
291 int ireg; /* Index register */
292 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
293 int imul; /* Multipy ireg by this (1,2,4,or 8) */
294 struct m68k_exp *con2;
295 };
296
297 /* internal form of a 68020 instruction */
298 struct m68k_it
299 {
300 char *error;
301 char *args; /* list of opcode info */
302 int numargs;
303
304 int numo; /* Number of shorts in opcode */
305 short opcode[11];
306
307 struct m68k_op operands[6];
308
309 int nexp; /* number of exprs in use */
310 struct m68k_exp exprs[4];
311
312 int nfrag; /* Number of frags we have to produce */
313 struct
314 {
315 int fragoff; /* Where in the current opcode[] the frag ends */
316 symbolS *fadd;
317 long foff;
318 int fragty;
319 }
320 fragb[4];
321
322 int nrel; /* Num of reloc strucs in use */
323 struct
324 {
325 int n;
326 symbolS *add, *sub;
327 long off;
328 char wid;
329 char pcrel;
330 }
331 reloc[5]; /* Five is enough??? */
332 };
333
334 #define cpu_of_arch(x) ((x) & m68000up)
335 #define float_of_arch(x) ((x) & mfloat)
336 #define mmu_of_arch(x) ((x) & mmmu)
337
338 static struct m68k_it the_ins; /* the instruction being assembled */
339
340 /* Macros for adding things to the m68k_it struct */
341
342 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
343
344 /* Like addword, but goes BEFORE general operands */
345 #define insop(w) {int z;\
346 for(z=the_ins.numo;z>opcode->m_codenum;--z)\
347 the_ins.opcode[z]=the_ins.opcode[z-1];\
348 for(z=0;z<the_ins.nrel;z++)\
349 the_ins.reloc[z].n+=2;\
350 the_ins.opcode[opcode->m_codenum]=w;\
351 the_ins.numo++;\
352 }
353
354
355 #define add_exp(beg,end) (\
356 the_ins.exprs[the_ins.nexp].e_beg=beg,\
357 the_ins.exprs[the_ins.nexp].e_end=end,\
358 &the_ins.exprs[the_ins.nexp++]\
359 )
360
361
362 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
363 Blecch. */
364 #define add_fix(width,exp,pc_rel) \
365 {\
366 the_ins.reloc[the_ins.nrel].n= (((width)=='B') \
367 ? (the_ins.numo*2-1) \
368 : (((width)=='b') \
369 ? ((the_ins.numo-1)*2) \
370 : (the_ins.numo*2)));\
371 the_ins.reloc[the_ins.nrel].add=adds((exp));\
372 the_ins.reloc[the_ins.nrel].sub=subs((exp));\
373 the_ins.reloc[the_ins.nrel].off=offs((exp));\
374 the_ins.reloc[the_ins.nrel].wid=width;\
375 the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\
376 }
377
378 #define add_frag(add,off,type) \
379 {\
380 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\
381 the_ins.fragb[the_ins.nfrag].fadd=add;\
382 the_ins.fragb[the_ins.nfrag].foff=off;\
383 the_ins.fragb[the_ins.nfrag++].fragty=type;\
384 }
385
386 #define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
387
388 #define seg(exp) ((exp)->e_exp.X_seg)
389 #define adds(exp) ((exp)->e_exp.X_add_symbol)
390 #define subs(exp) ((exp)->e_exp.X_subtract_symbol)
391 #define offs(exp) ((exp)->e_exp.X_add_number)
392
393
394 struct m68k_incant
395 {
396 char *m_operands;
397 unsigned long m_opcode;
398 short m_opnum;
399 short m_codenum;
400 int m_arch;
401 struct m68k_incant *m_next;
402 };
403
404
405
406 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
407 #define gettwo(x) (((x)->m_opcode)&0xffff)
408
409
410 #if __STDC__ == 1
411
412 static char *crack_operand (char *str, struct m68k_op *opP);
413 static int get_num (struct m68k_exp *exp, int ok);
414 static int get_regs (int i, char *str, struct m68k_op *opP);
415 static int reverse_16_bits (int in);
416 static int reverse_8_bits (int in);
417 static int try_index (char **s, struct m68k_op *opP);
418 static void install_gen_operand (int mode, int val);
419 static void install_operand (int mode, int val);
420 static void s_bss (void);
421 static void s_data1 (void);
422 static void s_data2 (void);
423 static void s_even (void);
424 static void s_proc (void);
425
426 #else /* not __STDC__ */
427
428 static char *crack_operand ();
429 static int get_num ();
430 static int get_regs ();
431 static int reverse_16_bits ();
432 static int reverse_8_bits ();
433 static int try_index ();
434 static void install_gen_operand ();
435 static void install_operand ();
436 static void s_bss ();
437 void s_align_bytes ();
438 static void s_data1 ();
439 static void s_data2 ();
440 static void s_even ();
441 static void s_proc ();
442
443 #endif /* not __STDC__ */
444
445 static int current_architecture = 0;
446
447 /* BCC68000 is for patching in an extra jmp instruction for long offsets
448 on the 68000. The 68000 doesn't support long branches with branchs */
449
450 /* This table desribes how you change sizes for the various types of variable
451 size expressions. This version only supports two kinds. */
452
453 /* Note that calls to frag_var need to specify the maximum expansion needed */
454 /* This is currently 10 bytes for DBCC */
455
456 /* The fields are:
457 How far Forward this mode will reach:
458 How far Backward this mode will reach:
459 How many bytes this mode will add to the size of the frag
460 Which mode to go to if the offset won't fit in this one
461 */
462 const relax_typeS
463 md_relax_table[] =
464 {
465 {1, 1, 0, 0}, /* First entries aren't used */
466 {1, 1, 0, 0}, /* For no good reason except */
467 {1, 1, 0, 0}, /* that the VAX doesn't either */
468 {1, 1, 0, 0},
469
470 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
471 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
472 {0, 0, 4, 0},
473 {1, 1, 0, 0},
474
475 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
476 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
477 {0, 0, 4, 0},
478 {1, 1, 0, 0},
479
480 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
481 {(32767), (-32768), 2, TAB (PCREL, LONG)},
482 {0, 0, 4, 0},
483 {1, 1, 0, 0},
484
485 {(127), (-128), 0, TAB (BCC68000, SHORT)},
486 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
487 {0, 0, 6, 0}, /* jmp long space */
488 {1, 1, 0, 0},
489
490 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
491 {(32767), (-32768), 2, TAB (DBCC, LONG)},
492 {0, 0, 10, 0}, /* bra/jmp long space */
493 {1, 1, 0, 0},
494
495 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
496 {32767, -32768, 2, TAB (PCLEA, LONG)},
497 {0, 0, 6, 0},
498 {1, 1, 0, 0},
499
500 };
501
502 /* These are the machine dependent pseudo-ops. These are included so
503 the assembler can work on the output from the SUN C compiler, which
504 generates these.
505 */
506
507 /* This table describes all the machine specific pseudo-ops the assembler
508 has to support. The fields are:
509 pseudo-op name without dot
510 function to call to execute this pseudo-op
511 Integer arg to pass to the function
512 */
513 const pseudo_typeS md_pseudo_table[] =
514 {
515 {"data1", s_data1, 0},
516 {"data2", s_data2, 0},
517 {"bss", s_bss, 0},
518 {"even", s_even, 0},
519 {"skip", s_space, 0},
520 {"proc", s_proc, 0},
521 #ifdef TE_SUN3
522 {"align", s_align_bytes, 0},
523 #endif
524 {0, 0, 0}
525 };
526
527
528 /* The mote pseudo ops are put into the opcode table, since they
529 don't start with a . they look like opcodes to gas.
530 */
531 extern void obj_coff_section ();
532
533 const pseudo_typeS mote_pseudo_table[] =
534 {
535
536 {"dc.l", cons, 4},
537 {"dc", cons, 2},
538 {"dc.w", cons, 2},
539 {"dc.b", cons, 1},
540
541 {"ds.l", s_space, 4},
542 {"ds", s_space, 2},
543 {"ds.w", s_space, 2},
544 {"ds.b", s_space, 1},
545
546 {"xdef", s_globl, 0},
547 {"align", s_align_ptwo, 0},
548 #ifdef M68KCOFF
549 {"sect", obj_coff_section, 0},
550 {"section", obj_coff_section, 0},
551 #endif
552 0,
553 };
554
555 /* #define isbyte(x) ((x)>=-128 && (x)<=127) */
556 /* #define isword(x) ((x)>=-32768 && (x)<=32767) */
557
558 #define issbyte(x) ((x)>=-128 && (x)<=127)
559 #define isubyte(x) ((x)>=0 && (x)<=255)
560 #define issword(x) ((x)>=-32768 && (x)<=32767)
561 #define isuword(x) ((x)>=0 && (x)<=65535)
562
563 #define isbyte(x) ((x)>=-128 && (x)<=255)
564 #define isword(x) ((x)>=-32768 && (x)<=65535)
565 #define islong(x) (1)
566
567 extern char *input_line_pointer;
568
569 enum
570 {
571 FAIL = 0,
572 OK = 1,
573 };
574
575 /* JF these tables here are for speed at the expense of size */
576 /* You can replace them with the #if 0 versions if you really
577 need space and don't mind it running a bit slower */
578
579 static char mklower_table[256];
580 #define mklower(c) (mklower_table[(unsigned char)(c)])
581 static char notend_table[256];
582 static char alt_notend_table[256];
583 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
584 alt_notend_table[(unsigned char)(s[1])])))
585
586 #if 0
587 #define mklower(c) (isupper(c) ? tolower(c) : c)
588 #endif
589
590
591 /* JF modified this to handle cases where the first part of a symbol name
592 looks like a register */
593
594 /*
595 * m68k_reg_parse() := if it looks like a register, return it's token &
596 * advance the pointer.
597 */
598
599 enum _register
600 m68k_reg_parse (ccp)
601 register char **ccp;
602 {
603 char *start = *ccp;
604 char c;
605 char *p;
606 symbolS *symbolP;
607
608 #ifdef REGISTER_PREFIX
609 if (*start != REGISTER_PREFIX)
610 return FAIL;
611 p = start + 1;
612 #else
613 p = start;
614 if (*p == OPTIONAL_REGISTER_PREFIX)
615 p++, start++;
616 #endif
617 if (!isalpha (*p) || !is_name_beginner (*p))
618 return FAIL;
619
620 c = *p++;
621 while (isalpha (c) || isdigit (c) || c == '_')
622 {
623 c = *p++;
624 }
625
626 *--p = 0;
627 symbolP = symbol_find (start);
628 *p = c;
629
630 if (symbolP && S_GET_SEGMENT (symbolP) == SEG_REGISTER)
631 {
632 *ccp = p;
633 return S_GET_VALUE (symbolP);
634 }
635
636 return FAIL;
637 }
638
639 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
640 #define SKIP_W() { ss++; if(*ss==' ') ss++;}
641
642 /* Parse an index specification using Motorola syntax. */
643
644 static int
645 try_moto_index (s, opP)
646 char **s;
647 struct m68k_op *opP;
648 {
649 register int i;
650 char *ss;
651
652 ss = *s;
653 /* SKIP_W(); */
654 if (*ss == ' ')
655 ss++;
656 i = m68k_reg_parse (&ss);
657 if (!(i >= DATA + 0 && i <= ADDR + 7))
658 { /* if i is not DATA or ADDR reg */
659 opP->error = "Invalid index register";
660 *s = ss;
661 return FAIL;
662 }
663 opP->ireg = i;
664 /* SKIP_W(); */
665 if (*ss == ')')
666 {
667 opP->isiz = 0;
668 opP->imul = 1;
669 SKIP_W ();
670 *s = ss;
671 return OK;
672 }
673 if (*ss != '.')
674 {
675 opP->error = "Missing . in index register";
676 *s = ss;
677 return FAIL;
678 }
679 SKIP_W ();
680 if (mklower (*ss) == 'w')
681 opP->isiz = 2;
682 else if (mklower (*ss) == 'l')
683 opP->isiz = 3;
684 else
685 {
686 opP->error = "Size spec not .W or .L";
687 *s = ss;
688 return FAIL;
689 }
690 SKIP_W ();
691 if (*ss == '.' || *ss == '*')
692 {
693 SKIP_W ();
694 switch (*ss)
695 {
696 case '1':
697 case '2':
698 case '4':
699 case '8':
700 opP->imul = *ss - '0';
701 break;
702 default:
703 opP->error = "index multiplier not 1, 2, 4 or 8";
704 *s = ss;
705 return FAIL;
706 }
707 SKIP_W ();
708 }
709 else
710 opP->imul = 1;
711 if (*ss != ')')
712 {
713 opP->error = "Missing )";
714 *s = ss;
715 return FAIL;
716 }
717 SKIP_W ();
718 *s = ss;
719 return OK;
720 }
721
722 /*
723 *
724 * try_index := data_or_address_register + ')' + SKIP_W
725 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
726 *
727 * multiplier := <empty>
728 * | ':' + multiplier_number
729 * ;
730 *
731 * multiplier_number := '1' | '2' | '4' | '8' ;
732 *
733 * size_spec := 'l' | 'L' | 'w' | 'W' ;
734 *
735 * SKIP_W := <empty> | ' ' ;
736 *
737 */
738
739 static int
740 try_index (s, opP)
741 char **s;
742 struct m68k_op *opP;
743 {
744 register int i;
745 char *ss;
746
747 ss = *s;
748 /* SKIP_W(); */
749 i = m68k_reg_parse (&ss);
750 if (!(i >= DATA + 0 && i <= ADDR + 7))
751 { /* if i is not DATA or ADDR reg */
752 *s = ss;
753 return FAIL;
754 }
755 opP->ireg = i;
756 /* SKIP_W(); */
757 if (*ss == ')')
758 {
759 opP->isiz = 0;
760 opP->imul = 1;
761 SKIP_W ();
762 *s = ss;
763 return OK;
764 }
765 if (*ss != ':')
766 {
767 opP->error = "Missing : in index register";
768 *s = ss;
769 return FAIL;
770 }
771 SKIP_W ();
772 switch (*ss)
773 {
774 case 'w':
775 case 'W':
776 opP->isiz = 2;
777 break;
778 case 'l':
779 case 'L':
780 opP->isiz = 3;
781 break;
782 default:
783 opP->error = "Index register size spec not :w or :l";
784 *s = ss;
785 return FAIL;
786 }
787 SKIP_W ();
788 if (*ss == ':')
789 {
790 SKIP_W ();
791 switch (*ss)
792 {
793 case '1':
794 case '2':
795 case '4':
796 case '8':
797 if (cpu_of_arch (current_architecture) < m68020)
798 {
799 opP->error = "no index scaling in pre-68020's";
800 *s = ss;
801 return FAIL;
802 }
803 opP->imul = *ss - '0';
804 break;
805 default:
806 opP->error = "index multiplier not 1, 2, 4 or 8";
807 *s = ss;
808 return FAIL;
809 }
810 SKIP_W ();
811 }
812 else
813 opP->imul = 1;
814 if (*ss != ')')
815 {
816 opP->error = "Missing )";
817 *s = ss;
818 return FAIL;
819 }
820 SKIP_W ();
821 *s = ss;
822 return OK;
823 } /* try_index() */
824
825 /* Ian Taylor expanded this function to accept both MIT and Motorola
826 syntax. I removed the old comment, since it was wrong. The syntax
827 this accepted even before my changes was complex and undocumented.
828 I mainly added a large case when the operand string does not
829 contain an '@', since the Motorola syntax does not use the '@'
830 character. */
831
832 int
833 m68k_ip_op (str, opP)
834 char *str;
835 register struct m68k_op *opP;
836 {
837 char *strend;
838 long i;
839 char *parse_index ();
840 int needp;
841
842 if (*str == ' ')
843 {
844 str++;
845 } /* Find the beginning of the string */
846
847 if (!*str)
848 {
849 opP->error = "Missing operand";
850 return FAIL;
851 } /* Out of gas */
852
853 for (strend = str; *strend; strend++)
854 ;
855 --strend;
856
857 if (*str == '#')
858 {
859 str++;
860 opP->con1 = add_exp (str, strend);
861 opP->mode = IMMED;
862 return OK;
863 } /* Guess what: A constant. Shar and enjoy */
864
865 i = m68k_reg_parse (&str);
866
867 if (i != FAIL)
868 {
869 if (*str == '/' || *str == '-')
870 {
871 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
872 opP->mode = REGLST;
873 return get_regs (i, str, opP);
874 }
875 if (*str == '\0')
876 {
877 opP->reg = i;
878 /* "Rn" Register Direct mode */
879 if (i >= DATA + 0 && i <= DATA + 7)
880 opP->mode = DREG;
881 else if (i >= ADDR + 0 && i <= ADDR + 7)
882 opP->mode = AREG;
883 else
884 opP->mode = MSCR;
885 return OK;
886 }
887 }
888
889 if (*str != '@')
890 {
891 char *stmp;
892
893 if ((stmp = strchr (str, '@')) != 0)
894 {
895 opP->con1 = add_exp (str, stmp - 1);
896 if (stmp == strend)
897 {
898 opP->mode = AINDX;
899 return (OK);
900 }
901
902 if ((current_architecture & m68020up) == 0)
903 {
904 return (FAIL);
905 } /* if target is not a '20 or better */
906
907 stmp++;
908 if (*stmp++ != '(' || *strend-- != ')')
909 {
910 opP->error = "Malformed operand";
911 return (FAIL);
912 }
913 i = try_index (&stmp, opP);
914 opP->con2 = add_exp (stmp, strend);
915
916 if (i == FAIL)
917 {
918 opP->mode = AMIND;
919 }
920 else
921 {
922 opP->mode = APODX;
923 }
924 return (OK);
925 } /* if there's an '@' */
926
927 #ifndef MIT_SYNTAX_ONLY
928 /* The operand has no '@'. Try to parse it using
929 Motorola syntax. */
930 /* Logic of the parsing switch(*str):
931 case opP->mode =
932 ---- -----------
933 #anything IMMED 1
934 REG AREG or DREG or MSCR 3 or 2 or 13
935 REG- or REG/ REGLST 14
936 (REG) AINDR 4
937 (REG)+ AINC 6
938 (REG,INDX) AINDX 8
939 (EXPR,REG) AOFF 7
940 (EXPR,REG,INDX) AINDX 8
941 -(REG) ADEC 5
942 EXP2(REG) AOFF 7
943 EXP2(REG,INDX) AINDX 8
944 EXP2 ABSL 12
945
946 REG means truth(m68k_reg_parse(&str))
947 INDX means truth(try_moto_index(&str,opP))
948 EXPR means not REG
949 EXP2 means not REG and not '(' and not '-('
950 */
951
952 if (*str == '(')
953 {
954 str++;
955 i = m68k_reg_parse (&str);
956 if ((i < ADDR + 0 || i > ADDR + 7)
957 && (i < DATA + 0 || i > DATA + 7
958 || *str != ')' || str[1] != '0')
959 && i != PC && i != ZPC && i != FAIL)
960 {
961 /* Can't indirect off non address regs */
962 opP->error = "Invalid indirect register";
963 return FAIL;
964 }
965 if (i != FAIL)
966 {
967 opP->reg = i;
968 if (*str == ')')
969 {
970 str++;
971 if (*str == '\0')
972 {
973 /* "(An)" Address Register Indirect mode
974 or "(Dn)" for cas2. */
975 if (i >= DATA + 0 && i <= DATA + 7)
976 opP->mode = DINDR;
977 else
978 opP->mode = AINDR;
979 return OK;
980 }
981 if (*str == '+')
982 {
983 if (str[1] == '\0')
984 {
985 /* "(An)+" Register Indirect w Postincrement */
986 opP->mode = AINC;
987 return OK;
988 }
989 }
990 opP->error = "Junk after indirect";
991 return FAIL;
992 }
993 if (*str == ',')
994 {
995 str++;
996 i = try_moto_index (&str, opP);
997 if (i == FAIL)
998 return FAIL;
999 /* "(An,Rn)" Register Indirect with Index mode*/
1000 opP->mode = AINDX;
1001 return OK;
1002 }
1003 else
1004 {
1005 opP->error = "Bad indirect syntax";
1006 return FAIL;
1007 }
1008 }
1009 else
1010 {
1011 /* "(EXPR,..." , a displacement */
1012 char *stmp;
1013 char *index ();
1014
1015 if (stmp = index (str, ','))
1016 {
1017 opP->con1 = add_exp (str, stmp - 1);
1018 str = stmp;
1019 SKIP_WHITE ();
1020 i = m68k_reg_parse (&str);
1021 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC)
1022 {
1023 /* Can't indirect off non address regs */
1024 opP->error = "Invalid indirect register";
1025 return FAIL;
1026 }
1027 if (i != FAIL)
1028 {
1029 opP->reg = i;
1030 if (*str == ')')
1031 {
1032 /* "(d,An)" Register Indirect w Displacement */
1033 opP->mode = AOFF;
1034 return OK;
1035 }
1036 if (*str == ',')
1037 {
1038 str++;
1039 i = try_moto_index (&str, opP);
1040 if (i == FAIL)
1041 return FAIL;
1042 /* "(d,An,Rn)" Register Indirect with Index */
1043 opP->mode = AINDX;
1044 return OK;
1045 }
1046 else
1047 {
1048 opP->error = "Bad indirect syntax";
1049 return FAIL;
1050 }
1051 }
1052 else
1053 {
1054 opP->error = "Invalid register";
1055 return FAIL;
1056 }
1057 }
1058 else
1059 {
1060 opP->mode = ABSL;
1061 opP->con1 = add_exp (str - 1, strend);
1062 return OK;
1063 }
1064 }
1065 }
1066
1067 if (*str == '-')
1068 {
1069 if (str[1] == '(')
1070 {
1071 str = str + 2;
1072 i = m68k_reg_parse (&str);
1073 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL)
1074 {
1075 /* Can't indirect off non address regs */
1076 opP->error = "Invalid indirect register";
1077 return FAIL;
1078 }
1079 if (i != FAIL)
1080 {
1081 opP->reg = i;
1082 if (*str == ')')
1083 {
1084 str++;
1085 if (*str == '\0')
1086 {
1087 /* "-(An)" Register Indirect with Predecrement */
1088 opP->mode = ADEC;
1089 return OK;
1090 }
1091 opP->error = "Junk after indirect";
1092 return FAIL;
1093 }
1094 opP->error = "Bad indirect syntax";
1095 return FAIL;
1096 }
1097 opP->mode = ABSL;
1098 opP->con1 = add_exp (str - 2, strend);
1099 return OK;
1100 }
1101 /* if '-' but not "-(', do nothing */
1102 }
1103
1104 /* whether *str=='-' or not */
1105 {
1106 /* "EXP2" or "EXP2(REG..." */
1107 char *stmp;
1108 char *index ();
1109 if (stmp = index (str, '('))
1110 {
1111 char *ostr = str;
1112
1113 opP->con1 = add_exp (str, stmp - 1);
1114 str = stmp + 1;
1115 i = m68k_reg_parse (&str);
1116 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC
1117 && i != ZPC && i != FAIL)
1118 {
1119 /* Can't indirect off non address regs */
1120 opP->error = "Invalid indirect register";
1121 return FAIL;
1122 }
1123 if (i != FAIL)
1124 {
1125 opP->reg = i;
1126 if (*str == ')')
1127 {
1128 /* "d(An)" Register Indirect w Displacement */
1129 opP->mode = AOFF;
1130 return OK;
1131 }
1132 if (*str == ',')
1133 {
1134 str++;
1135 i = try_moto_index (&str, opP);
1136 if (i == FAIL)
1137 return FAIL;
1138 /* "d(An,Rn)" Register Indirect with Index */
1139 opP->mode = AINDX;
1140 return OK;
1141 }
1142 else
1143 {
1144 opP->error = "Bad indirect syntax";
1145 return FAIL;
1146 }
1147 }
1148 else
1149 {
1150 opP->mode = ABSL;
1151 opP->con1 = add_exp (ostr, strend);
1152 return OK;
1153 }
1154 }
1155 else
1156 {
1157 /* "EXP2" Absolute */
1158 opP->mode = ABSL;
1159 opP->isiz = 0;
1160 if (strend[-1] == '.' || strend[-1] == ':')
1161 {
1162 /* mode ==foo.[wl] */
1163 switch (*strend)
1164 {
1165 case 'w':
1166 case 'W':
1167 opP->isiz = 2;
1168 strend -= 2;
1169 break;
1170 case 'l':
1171 case 'L':
1172 opP->isiz = 3;
1173 strend -= 2;
1174 break;
1175 }
1176 }
1177 opP->con1 = add_exp (str, strend);
1178 return OK;
1179 }
1180 }
1181 /*NOTREACHED*/
1182 #else /* defined (MIT_SYNTAX_ONLY) */
1183 opP->mode = ABSL;
1184 opP->con1 = add_exp (str, strend);
1185 return OK;
1186 #endif /* defined (MIT_SYNTAX_ONLY) */
1187 }
1188
1189 opP->reg = i;
1190
1191 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1192 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL
1193 && (str[1] != '\0' || i < DATA + 0 || i > DATA + 7))
1194 {
1195 opP->error = "Invalid indirect register";
1196 return FAIL;
1197 }
1198 know (*str == '@');
1199
1200 str++;
1201 switch (*str)
1202 {
1203 case '\0':
1204 if (i < DATA + 0 || i > DATA + 7)
1205 opP->mode = AINDR;
1206 else
1207 opP->mode = DINDR;
1208 return OK;
1209 case '-':
1210 opP->mode = ADEC;
1211 return OK;
1212 case '+':
1213 opP->mode = AINC;
1214 return OK;
1215 case '(':
1216 str++;
1217 break;
1218 default:
1219 opP->error = "Junk after indirect";
1220 return FAIL;
1221 }
1222 /* Some kind of indexing involved. Lets find out how bad it is */
1223 i = try_index (&str, opP);
1224 /* Didn't start with an index reg, maybe its offset or offset,reg */
1225 if (i == FAIL)
1226 {
1227 char *beg_str;
1228
1229 beg_str = str;
1230 for (i = 1; i;)
1231 {
1232 switch (*str++)
1233 {
1234 case '\0':
1235 opP->error = "Missing )";
1236 return FAIL;
1237 case ',':
1238 i = 0;
1239 break;
1240 case '(':
1241 i++;
1242 break;
1243 case ')':
1244 --i;
1245 break;
1246 }
1247 }
1248 /* if(str[-3]==':') {
1249 int siz;
1250
1251 switch(str[-2]) {
1252 case 'b':
1253 case 'B':
1254 siz=1;
1255 break;
1256 case 'w':
1257 case 'W':
1258 siz=2;
1259 break;
1260 case 'l':
1261 case 'L':
1262 siz=3;
1263 break;
1264 default:
1265 opP->error="Specified size isn't :w or :l";
1266 return FAIL;
1267 }
1268 opP->con1=add_exp(beg_str,str-4);
1269 opP->con1->e_siz=siz;
1270 } else */
1271 opP->con1 = add_exp (beg_str, str - 2);
1272 /* Should be offset,reg */
1273 if (str[-1] == ',')
1274 {
1275 i = try_index (&str, opP);
1276 if (i == FAIL)
1277 {
1278 opP->error = "Malformed index reg";
1279 return FAIL;
1280 }
1281 }
1282 }
1283 /* We've now got offset) offset,reg) or reg) */
1284
1285 if (*str == '\0')
1286 {
1287 /* Th-the-thats all folks */
1288 if (opP->reg == FAIL)
1289 opP->mode = AINDX; /* Other form of indirect */
1290 else if (opP->ireg == FAIL)
1291 opP->mode = AOFF;
1292 else
1293 opP->mode = AINDX;
1294 return (OK);
1295 }
1296 /* Next thing had better be another @ */
1297 if (*str == '@')
1298 {
1299 if (str[1] == '(')
1300 {
1301 needp = 1;
1302 str += 2;
1303 }
1304 else
1305 {
1306 needp = 0;
1307 str++;
1308 }
1309 }
1310
1311 if ((current_architecture & m68020up) == 0)
1312 {
1313 return (FAIL);
1314 } /* if target is not a '20 or better */
1315
1316
1317 if (opP->ireg != FAIL)
1318 {
1319 opP->mode = APRDX;
1320
1321 i = try_index (&str, opP);
1322 if (i != FAIL)
1323 {
1324 opP->error = "Two index registers! not allowed!";
1325 return (FAIL);
1326 }
1327 }
1328 else
1329 {
1330 i = try_index (&str, opP);
1331 }
1332
1333 if (i == FAIL)
1334 {
1335 char *beg_str;
1336
1337 beg_str = str;
1338
1339 for (i = 1; i;)
1340 {
1341 switch (*str++)
1342 {
1343 case '\0':
1344 if (needp)
1345 opP->error = "Missing )";
1346 return (FAIL);
1347 break;
1348 case ',':
1349 i = 0;
1350 break;
1351 case '(':
1352 i++;
1353 break;
1354 case ')':
1355 --i;
1356 break;
1357 }
1358 }
1359
1360 opP->con2 = add_exp (beg_str, str - 2);
1361
1362 if (str[-1] == ',')
1363 {
1364 if (opP->ireg != FAIL)
1365 {
1366 opP->error = "Can't have two index regs";
1367 return (FAIL);
1368 }
1369
1370 i = try_index (&str, opP);
1371
1372 if (i == FAIL)
1373 {
1374 opP->error = "malformed index reg";
1375 return (FAIL);
1376 }
1377
1378 opP->mode = APODX;
1379 }
1380 else if (opP->ireg != FAIL)
1381 {
1382 opP->mode = APRDX;
1383 }
1384 else
1385 {
1386 opP->mode = AMIND;
1387 }
1388 }
1389 else
1390 {
1391 opP->mode = APODX;
1392 }
1393
1394 if (*str != '\0')
1395 {
1396 opP->error = "Junk after indirect";
1397 return FAIL;
1398 }
1399 return (OK);
1400 } /* m68k_ip_op() */
1401
1402
1403 #ifdef M68KCOFF
1404
1405 short
1406 tc_coff_fix2rtype (fixP)
1407 fixS *fixP;
1408 {
1409 return (fixP->fx_pcrel ?
1410 (fixP->fx_size == 1 ? R_PCRBYTE :
1411 fixP->fx_size == 2 ? R_PCRWORD :
1412 R_PCRLONG) :
1413 (fixP->fx_size == 1 ? R_RELBYTE :
1414 fixP->fx_size == 2 ? R_RELWORD :
1415 R_RELLONG));
1416
1417
1418 }
1419
1420 #endif
1421
1422 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1423 main ()
1424 {
1425 char buf[128];
1426 struct m68k_op thark;
1427
1428 for (;;)
1429 {
1430 if (!gets (buf))
1431 break;
1432 memset (&thark, '\0', sizeof (thark));
1433 if (!m68k_ip_op (buf, &thark))
1434 printf ("FAIL:");
1435 if (thark.error)
1436 printf ("op1 error %s in %s\n", thark.error, buf);
1437 printf ("mode %d, reg %d, ", thark.mode, thark.reg);
1438 if (thark.b_const)
1439 printf ("Constant: '%.*s',", 1 + thark.e_const - thark.b_const, thark.b_const);
1440 printf ("ireg %d, isiz %d, imul %d ", thark.ireg, thark.isiz, thark.imul);
1441 if (thark.b_iadd)
1442 printf ("Iadd: '%.*s'", 1 + thark.e_iadd - thark.b_iadd, thark.b_iadd);
1443 printf ("\n");
1444 }
1445 exit (0);
1446 }
1447
1448 #endif
1449
1450
1451 static struct hash_control *op_hash = NULL; /* handle of the OPCODE hash table
1452 NULL means any use before m68k_ip_begin()
1453 will crash */
1454 \f
1455
1456 /*
1457 * m 6 8 k _ i p ( )
1458 *
1459 * This converts a string into a 68k instruction.
1460 * The string must be a bare single instruction in sun format
1461 * with RMS-style 68020 indirects
1462 * (example: )
1463 *
1464 * It provides some error messages: at most one fatal error message (which
1465 * stops the scan) and at most one warning message for each operand.
1466 * The 68k instruction is returned in exploded form, since we have no
1467 * knowledge of how you parse (or evaluate) your expressions.
1468 * We do however strip off and decode addressing modes and operation
1469 * mnemonic.
1470 *
1471 * This function's value is a string. If it is not "" then an internal
1472 * logic error was found: read this code to assign meaning to the string.
1473 * No argument string should generate such an error string:
1474 * it means a bug in our code, not in the user's text.
1475 *
1476 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1477 * this function.
1478 */
1479
1480 /* JF this function no longer returns a useful value. Sorry */
1481 void
1482 m68k_ip (instring)
1483 char *instring;
1484 {
1485 register char *p;
1486 register struct m68k_op *opP;
1487 register struct m68k_incant *opcode;
1488 register char *s;
1489 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1490 char *pdot, *pdotmove;
1491 int siz1, siz2;
1492 char c;
1493 int losing;
1494 int opsfound;
1495 char *crack_operand ();
1496 LITTLENUM_TYPE words[6];
1497 LITTLENUM_TYPE *wordp;
1498 unsigned long ok_arch = 0;
1499
1500 if (*instring == ' ')
1501 instring++; /* skip leading whitespace */
1502
1503 /* Scan up to end of operation-code, which MUST end in end-of-string
1504 or exactly 1 space. */
1505 pdot = 0;
1506 for (p = instring; *p != '\0'; p++)
1507 {
1508 if (*p == ' ')
1509 break;
1510 if (*p == '.')
1511 pdot = p;
1512 }
1513
1514 if (p == instring)
1515 {
1516 the_ins.error = "No operator";
1517 the_ins.opcode[0] = NULL;
1518 /* the_ins.numo=1; */
1519 return;
1520 }
1521
1522 /* p now points to the end of the opcode name, probably whitespace.
1523 make sure the name is null terminated by clobbering the whitespace,
1524 look it up in the hash table, then fix it back.
1525 Remove a dot, first, since the opcode tables have none. */
1526 if (pdot != NULL)
1527 {
1528 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1529 *pdotmove = pdotmove[1];
1530 p--;
1531 }
1532
1533 c = *p;
1534 *p = '\0';
1535 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
1536 *p = c;
1537
1538 if (pdot != NULL)
1539 {
1540 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1541 *pdotmove = pdotmove[-1];
1542 *pdot = '.';
1543 ++p;
1544 }
1545
1546 if (opcode == NULL)
1547 {
1548 the_ins.error = "Unknown operator";
1549 the_ins.opcode[0] = NULL;
1550 /* the_ins.numo=1; */
1551 return;
1552 }
1553
1554 /* found a legitimate opcode, start matching operands */
1555 while (*p == ' ')
1556 ++p;
1557
1558
1559 if (opcode->m_operands == 0)
1560 {
1561 char *old = input_line_pointer;
1562 *old = '\n';
1563 input_line_pointer = p;
1564 /* Ahh - it's a motorola style psuedo op */
1565 mote_pseudo_table[opcode->m_opnum].poc_handler
1566 (mote_pseudo_table[opcode->m_opnum].poc_val);
1567 input_line_pointer = old;
1568 *old = 0;
1569
1570 return;
1571 }
1572
1573 for (opP = &the_ins.operands[0]; *p; opP++)
1574 {
1575
1576 p = crack_operand (p, opP);
1577
1578 if (opP->error)
1579 {
1580 the_ins.error = opP->error;
1581 return;
1582 }
1583 }
1584
1585 opsfound = opP - &the_ins.operands[0];
1586
1587 /* This ugly hack is to support the floating pt opcodes in their standard form */
1588 /* Essentially, we fake a first enty of type COP#1 */
1589 if (opcode->m_operands[0] == 'I')
1590 {
1591 int n;
1592
1593 for (n = opsfound; n > 0; --n)
1594 the_ins.operands[n] = the_ins.operands[n - 1];
1595
1596 memset ((char *) (&the_ins.operands[0]), '\0', sizeof (the_ins.operands[0]));
1597 the_ins.operands[0].mode = MSCR;
1598 the_ins.operands[0].reg = COPNUM; /* COP #1 */
1599 opsfound++;
1600 }
1601
1602 /* We've got the operands. Find an opcode that'll accept them */
1603 for (losing = 0;;)
1604 {
1605 /* if we didn't get the right number of ops,
1606 or we have no common model with this pattern
1607 then reject this pattern. */
1608
1609 if (opsfound != opcode->m_opnum
1610 || ((opcode->m_arch & current_architecture) == 0))
1611 {
1612 ++losing;
1613 ok_arch |= opcode->m_arch;
1614 }
1615 else
1616 {
1617 for (s = opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++)
1618 {
1619 /* Warning: this switch is huge! */
1620 /* I've tried to organize the cases into this order:
1621 non-alpha first, then alpha by letter. lower-case goes directly
1622 before uppercase counterpart. */
1623 /* Code with multiple case ...: gets sorted by the lowest case ...
1624 it belongs to. I hope this makes sense. */
1625 switch (*s)
1626 {
1627 case '!':
1628 if (opP->mode == MSCR || opP->mode == IMMED
1629 || opP->mode == DREG || opP->mode == AREG
1630 || opP->mode == AINC || opP->mode == ADEC
1631 || opP->mode == REGLST)
1632 losing++;
1633 break;
1634
1635 case '`':
1636 switch (opP->mode)
1637 {
1638 case MSCR:
1639 case IMMED:
1640 case DREG:
1641 case AREG:
1642 case AINC:
1643 case REGLST:
1644 case AINDR:
1645 losing++;
1646 }
1647 break;
1648
1649 case '#':
1650 if (opP->mode != IMMED)
1651 losing++;
1652 else
1653 {
1654 long t;
1655
1656 t = get_num (opP->con1, 80);
1657 if (s[1] == 'b' && !isbyte (t))
1658 losing++;
1659 else if (s[1] == 'w' && !isword (t))
1660 losing++;
1661 }
1662 break;
1663
1664 case '^':
1665 case 'T':
1666 if (opP->mode != IMMED)
1667 losing++;
1668 break;
1669
1670 case '$':
1671 if (opP->mode == MSCR || opP->mode == AREG ||
1672 opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1673 losing++;
1674 break;
1675
1676 case '%':
1677 if (opP->mode == MSCR || opP->reg == PC ||
1678 opP->reg == ZPC || opP->mode == REGLST)
1679 losing++;
1680 break;
1681
1682
1683 case '&':
1684 if (opP->mode == MSCR || opP->mode == DREG ||
1685 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC ||
1686 opP->mode == AINC || opP->mode == ADEC || opP->mode == REGLST)
1687 losing++;
1688 break;
1689
1690 case '*':
1691 if (opP->mode == MSCR || opP->mode == REGLST)
1692 losing++;
1693 break;
1694
1695 case '+':
1696 if (opP->mode != AINC)
1697 losing++;
1698 break;
1699
1700 case '-':
1701 if (opP->mode != ADEC)
1702 losing++;
1703 break;
1704
1705 case '/':
1706 if (opP->mode == MSCR || opP->mode == AREG ||
1707 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->mode == REGLST)
1708 losing++;
1709 break;
1710
1711 case ';':
1712 if (opP->mode == MSCR || opP->mode == AREG || opP->mode == REGLST)
1713 losing++;
1714 break;
1715
1716 case '?':
1717 if (opP->mode == MSCR || opP->mode == AREG ||
1718 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->reg == PC ||
1719 opP->reg == ZPC || opP->mode == REGLST)
1720 losing++;
1721 break;
1722
1723 case '@':
1724 if (opP->mode == MSCR || opP->mode == AREG ||
1725 opP->mode == IMMED || opP->mode == REGLST)
1726 losing++;
1727 break;
1728
1729 case '~': /* For now! (JF FOO is this right?) */
1730 if (opP->mode == MSCR || opP->mode == DREG ||
1731 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1732 losing++;
1733 break;
1734
1735 case '3':
1736 if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1))
1737 losing++;
1738 break;
1739
1740 case 'A':
1741 if (opP->mode != AREG)
1742 losing++;
1743 break;
1744 case 'a':
1745 if (opP->mode != AINDR)
1746 {
1747 ++losing;
1748 } /* if not address register indirect */
1749 break;
1750 case 'B': /* FOO */
1751 if (opP->mode != ABSL || (flagseen['S'] && instring[0] == 'j'
1752 && instring[1] == 'b'
1753 && instring[2] == 's'
1754 && instring[3] == 'r'))
1755 losing++;
1756 break;
1757
1758 case 'C':
1759 if (opP->mode != MSCR || opP->reg != CCR)
1760 losing++;
1761 break;
1762
1763 case 'd': /* FOO This mode is a KLUDGE!! */
1764 if (opP->mode != AOFF && (opP->mode != ABSL ||
1765 opP->con1->e_beg[0] != '(' || opP->con1->e_end[0] != ')'))
1766 losing++;
1767 break;
1768
1769 case 'D':
1770 if (opP->mode != DREG)
1771 losing++;
1772 break;
1773
1774 case 'F':
1775 if (opP->mode != MSCR || opP->reg < (FPREG + 0) || opP->reg > (FPREG + 7))
1776 losing++;
1777 break;
1778
1779 case 'I':
1780 if (opP->mode != MSCR || opP->reg < COPNUM ||
1781 opP->reg >= COPNUM + 7)
1782 losing++;
1783 break;
1784
1785 case 'J':
1786 if (opP->mode != MSCR
1787 || opP->reg < USP
1788 || opP->reg > URP
1789 || cpu_of_arch (current_architecture) < m68010 /* before 68010 had none */
1790 || (cpu_of_arch (current_architecture) < m68020
1791 && opP->reg != SFC
1792 && opP->reg != DFC
1793 && opP->reg != USP
1794 && opP->reg != VBR) /* 68010's had only these */
1795 || (cpu_of_arch (current_architecture) < m68040
1796 && opP->reg != SFC
1797 && opP->reg != DFC
1798 && opP->reg != USP
1799 && opP->reg != VBR
1800 && opP->reg != CACR
1801 && opP->reg != CAAR
1802 && opP->reg != MSP
1803 && opP->reg != ISP) /* 680[23]0's have only these */
1804 || (cpu_of_arch (current_architecture) == m68040 /* 68040 has all but this */
1805 && opP->reg == CAAR))
1806 {
1807 losing++;
1808 } /* doesn't cut it */
1809 break;
1810
1811 case 'k':
1812 if (opP->mode != IMMED)
1813 losing++;
1814 break;
1815
1816 case 'l':
1817 case 'L':
1818 if (opP->mode == DREG || opP->mode == AREG || opP->mode == FPREG)
1819 {
1820 if (s[1] == '8')
1821 losing++;
1822 else
1823 {
1824 opP->mode = REGLST;
1825 opP->reg = 1 << (opP->reg - DATA);
1826 }
1827 }
1828 else if (opP->mode != REGLST)
1829 {
1830 losing++;
1831 }
1832 else if (s[1] == '8' && opP->reg & 0x0FFffFF)
1833 losing++;
1834 else if (s[1] == '3' && opP->reg & 0x7000000)
1835 losing++;
1836 break;
1837
1838 case 'M':
1839 if (opP->mode != IMMED)
1840 losing++;
1841 else
1842 {
1843 long t;
1844
1845 t = get_num (opP->con1, 80);
1846 if (!issbyte (t) || isvar (opP->con1))
1847 losing++;
1848 }
1849 break;
1850
1851 case 'O':
1852 if (opP->mode != DREG && opP->mode != IMMED)
1853 losing++;
1854 break;
1855
1856 case 'Q':
1857 if (opP->mode != IMMED)
1858 losing++;
1859 else
1860 {
1861 long t;
1862
1863 t = get_num (opP->con1, 80);
1864 if (t < 1 || t > 8 || isvar (opP->con1))
1865 losing++;
1866 }
1867 break;
1868
1869 case 'R':
1870 if (opP->mode != DREG && opP->mode != AREG)
1871 losing++;
1872 break;
1873
1874 case 'r':
1875 if (opP->mode != AINDR && opP->mode != DINDR)
1876 losing++;
1877 break;
1878
1879 case 's':
1880 if (opP->mode != MSCR || !(opP->reg == FPI || opP->reg == FPS || opP->reg == FPC))
1881 losing++;
1882 break;
1883
1884 case 'S':
1885 if (opP->mode != MSCR || opP->reg != SR)
1886 losing++;
1887 break;
1888
1889 case 't':
1890 if (opP->mode != IMMED)
1891 losing++;
1892 else
1893 {
1894 long t = get_num (opP->con1, 80);
1895 if (t < 0 || t > 7 || isvar (opP->con1))
1896 losing++;
1897 }
1898 break;
1899
1900 case 'U':
1901 if (opP->mode != MSCR || opP->reg != USP)
1902 losing++;
1903 break;
1904
1905 /* JF these are out of order. We could put them
1906 in order if we were willing to put up with
1907 bunches of #ifdef m68851s in the code.
1908
1909 Don't forget that you need these operands
1910 to use 68030 MMU instructions. */
1911 #ifndef NO_68851
1912 /* Memory addressing mode used by pflushr */
1913 case '|':
1914 if (opP->mode == MSCR || opP->mode == DREG ||
1915 opP->mode == AREG || opP->mode == REGLST)
1916 losing++;
1917 break;
1918
1919 case 'f':
1920 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
1921 losing++;
1922 break;
1923
1924 case 'P':
1925 if (opP->mode != MSCR
1926 || (opP->reg != TC && opP->reg != CAL
1927 && opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
1928 losing++;
1929 break;
1930
1931 case 'V':
1932 if (opP->reg != VAL)
1933 losing++;
1934 break;
1935
1936 case 'W':
1937 if (opP->mode != MSCR
1938 || (opP->reg != DRP && opP->reg != SRP
1939 && opP->reg != CRP))
1940 losing++;
1941 break;
1942
1943 case 'X':
1944 if (opP->mode != MSCR ||
1945 (!(opP->reg >= BAD && opP->reg <= BAD + 7) &&
1946 !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1947 losing++;
1948 break;
1949
1950 case 'Y':
1951 if (opP->reg != PSR)
1952 losing++;
1953 break;
1954
1955 case 'Z':
1956 if (opP->reg != PCSR)
1957 losing++;
1958 break;
1959 #endif
1960 case 'c':
1961 if (opP->reg != NC
1962 && opP->reg != IC
1963 && opP->reg != DC
1964 && opP->reg != BC)
1965 {
1966 losing++;
1967 } /* not a cache specifier. */
1968 break;
1969
1970 case '_':
1971 if (opP->mode != ABSL)
1972 {
1973 ++losing;
1974 } /* not absolute */
1975 break;
1976
1977 default:
1978 as_fatal ("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
1979 *s, __LINE__, __FILE__);
1980 } /* switch on type of operand */
1981
1982 if (losing)
1983 break;
1984 } /* for each operand */
1985 } /* if immediately wrong */
1986
1987 if (!losing)
1988 {
1989 break;
1990 } /* got it. */
1991
1992 opcode = opcode->m_next;
1993
1994 if (!opcode)
1995 {
1996 if (ok_arch
1997 && !(ok_arch & current_architecture))
1998 {
1999 char buf[200], *cp;
2000 int len;
2001 strcpy (buf, "invalid instruction for this architecture; needs ");
2002 cp = buf + strlen (buf);
2003 switch (ok_arch)
2004 {
2005 case mfloat:
2006 strcpy (cp, "fpu (68040 or 68881/68882)");
2007 break;
2008 case mmmu:
2009 strcpy (cp, "mmu (68030 or 68851)");
2010 break;
2011 case m68020up:
2012 strcpy (cp, "68020 or higher");
2013 break;
2014 case m68000up:
2015 strcpy (cp, "68000 or higher");
2016 break;
2017 case m68010up:
2018 strcpy (cp, "68010 or higher");
2019 break;
2020 default:
2021 {
2022 int got_one = 0, idx;
2023 const static struct
2024 {
2025 int arch;
2026 const char *name;
2027 }
2028 archs[] =
2029 {
2030 m68000, "68000",
2031 m68010, "68010",
2032 m68020, "68020",
2033 m68030, "68030",
2034 m68040, "68040",
2035 cpu32, "cpu32",
2036 m68881, "68881",
2037 m68851, "68851",
2038 };
2039 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]); idx++)
2040 {
2041 if (archs[idx].arch & ok_arch)
2042 {
2043 if (got_one)
2044 {
2045 strcpy (cp, " or ");
2046 cp += strlen (cp);
2047 }
2048 got_one = 1;
2049 strcpy (cp, archs[idx].name);
2050 cp += strlen (cp);
2051 }
2052 }
2053 }
2054 }
2055 len = cp - buf + 1;
2056 cp = malloc (len);
2057 strcpy (cp, buf);
2058 the_ins.error = cp;
2059 }
2060 else
2061 the_ins.error = "operands mismatch";
2062 return;
2063 } /* Fell off the end */
2064
2065 losing = 0;
2066 }
2067
2068 /* now assemble it */
2069
2070 the_ins.args = opcode->m_operands;
2071 the_ins.numargs = opcode->m_opnum;
2072 the_ins.numo = opcode->m_codenum;
2073 the_ins.opcode[0] = getone (opcode);
2074 the_ins.opcode[1] = gettwo (opcode);
2075
2076 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2077 {
2078 /* This switch is a doozy.
2079 Watch the first step; its a big one! */
2080 switch (s[0])
2081 {
2082
2083 case '*':
2084 case '~':
2085 case '%':
2086 case ';':
2087 case '@':
2088 case '!':
2089 case '&':
2090 case '$':
2091 case '?':
2092 case '/':
2093 case '`':
2094 #ifndef NO_68851
2095 case '|':
2096 #endif
2097 switch (opP->mode)
2098 {
2099 case IMMED:
2100 tmpreg = 0x3c; /* 7.4 */
2101 if (strchr ("bwl", s[1]))
2102 nextword = get_num (opP->con1, 80);
2103 else
2104 nextword = nextword = get_num (opP->con1, 0);
2105 if (isvar (opP->con1))
2106 add_fix (s[1], opP->con1, 0);
2107 switch (s[1])
2108 {
2109 case 'b':
2110 if (!isbyte (nextword))
2111 opP->error = "operand out of range";
2112 addword (nextword);
2113 baseo = 0;
2114 break;
2115 case 'w':
2116 if (!isword (nextword))
2117 opP->error = "operand out of range";
2118 addword (nextword);
2119 baseo = 0;
2120 break;
2121 case 'l':
2122 addword (nextword >> 16);
2123 addword (nextword);
2124 baseo = 0;
2125 break;
2126
2127 case 'f':
2128 baseo = 2;
2129 outro = 8;
2130 break;
2131 case 'F':
2132 baseo = 4;
2133 outro = 11;
2134 break;
2135 case 'x':
2136 baseo = 6;
2137 outro = 15;
2138 break;
2139 case 'p':
2140 baseo = 6;
2141 outro = -1;
2142 break;
2143 default:
2144 as_fatal ("Internal error: Can't decode %c%c in line %s of file \"%s\"",
2145 *s, s[1], __LINE__, __FILE__);
2146 }
2147 if (!baseo)
2148 break;
2149
2150 /* We gotta put out some float */
2151 #if 0
2152 if (seg (opP->con1) != SEG_BIG)
2153 {
2154 int_to_gen (nextword);
2155 gen_to_words (words, baseo, (long int) outro);
2156 for (wordp = words; baseo--; wordp++)
2157 addword (*wordp);
2158 break;
2159 } /* Its BIG */
2160 #else
2161 if (seg (opP->con1) != SEG_BIG)
2162 {
2163 abort ();
2164 }
2165 #endif
2166 if (offs (opP->con1) > 0)
2167 {
2168 if (offs (opP->con1) > baseo)
2169 {
2170 as_warn ("Bignum too big for %c format; truncated", s[1]);
2171 offs (opP->con1) = baseo;
2172 }
2173 baseo -= offs (opP->con1);
2174 for (wordp = generic_bignum + offs (opP->con1) - 1; offs (opP->con1)--; --wordp)
2175 addword (*wordp);
2176 while (baseo--)
2177 addword (0);
2178 break;
2179 }
2180 gen_to_words (words, baseo, (long) outro);
2181 for (wordp = words; baseo--; wordp++)
2182 addword (*wordp);
2183 break;
2184 case DREG:
2185 tmpreg = opP->reg - DATA; /* 0.dreg */
2186 break;
2187 case AREG:
2188 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2189 break;
2190 case AINDR:
2191 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2192 break;
2193 case ADEC:
2194 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2195 break;
2196 case AINC:
2197 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2198 break;
2199 case AOFF:
2200
2201 nextword = get_num (opP->con1, 80);
2202 /* Force into index mode. Hope this works */
2203
2204 /* We do the first bit for 32-bit displacements, and the
2205 second bit for 16 bit ones. It is possible that we
2206 should make the default be WORD instead of LONG, but
2207 I think that'd break GCC, so we put up with a little
2208 inefficiency for the sake of working output. */
2209
2210 if (!issword (nextword)
2211 || (isvar (opP->con1)
2212 && ((opP->con1->e_siz == 0
2213 && flagseen['l'] == 0)
2214 || opP->con1->e_siz == 3)))
2215 {
2216
2217 if (opP->reg == PC)
2218 tmpreg = 0x3B; /* 7.3 */
2219 else
2220 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2221 if (isvar (opP->con1))
2222 {
2223 if (opP->reg == PC)
2224 {
2225 add_frag (adds (opP->con1),
2226 offs (opP->con1) + 2,
2227 TAB (PCLEA, SZ_UNDEF));
2228 break;
2229 }
2230 else
2231 {
2232 addword (0x0170);
2233 add_fix ('l', opP->con1, 0);
2234 }
2235 }
2236 else
2237 addword (0x0170);
2238 addword (nextword >> 16);
2239 }
2240 else
2241 {
2242 if (opP->reg == PC)
2243 tmpreg = 0x3A; /* 7.2 */
2244 else
2245 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2246
2247 if (isvar (opP->con1))
2248 {
2249 if (opP->reg == PC)
2250 {
2251 add_fix ('w', opP->con1, 1);
2252 }
2253 else
2254 add_fix ('w', opP->con1, 0);
2255 }
2256 }
2257 addword (nextword);
2258 break;
2259
2260 case APODX:
2261 case AMIND:
2262 case APRDX:
2263 know (current_architecture & m68020up);
2264 /* intentional fall-through */
2265 case AINDX:
2266 nextword = 0;
2267 baseo = get_num (opP->con1, 80);
2268 outro = get_num (opP->con2, 80);
2269 /* Figure out the 'addressing mode' */
2270 /* Also turn on the BASE_DISABLE bit, if needed */
2271 if (opP->reg == PC || opP->reg == ZPC)
2272 {
2273 tmpreg = 0x3b;/* 7.3 */
2274 if (opP->reg == ZPC)
2275 nextword |= 0x80;
2276 }
2277 else if (opP->reg == FAIL)
2278 {
2279 nextword |= 0x80;
2280 tmpreg = 0x30;/* 6.garbage */
2281 }
2282 else
2283 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2284
2285 siz1 = (opP->con1) ? opP->con1->e_siz : 0;
2286 siz2 = (opP->con2) ? opP->con2->e_siz : 0;
2287
2288 /* Index register stuff */
2289 if (opP->ireg >= DATA + 0 && opP->ireg <= ADDR + 7)
2290 {
2291 nextword |= (opP->ireg - DATA) << 12;
2292
2293 if (opP->isiz == 0 || opP->isiz == 3)
2294 nextword |= 0x800;
2295 switch (opP->imul)
2296 {
2297 case 1:
2298 break;
2299 case 2:
2300 nextword |= 0x200;
2301 break;
2302 case 4:
2303 nextword |= 0x400;
2304 break;
2305 case 8:
2306 nextword |= 0x600;
2307 break;
2308 default:
2309 as_fatal ("failed sanity check.");
2310 }
2311 /* IF its simple,
2312 GET US OUT OF HERE! */
2313
2314 /* Must be INDEX, with an index
2315 register. Address register
2316 cannot be ZERO-PC, and either
2317 :b was forced, or we know
2318 it will fit */
2319 if (opP->mode == AINDX
2320 && opP->reg != FAIL
2321 && opP->reg != ZPC
2322 && (siz1 == 1
2323 || (issbyte (baseo)
2324 && !isvar (opP->con1))))
2325 {
2326 nextword += baseo & 0xff;
2327 addword (nextword);
2328 if (isvar (opP->con1))
2329 add_fix ('B', opP->con1, 0);
2330 break;
2331 }
2332 }
2333 else
2334 nextword |= 0x40; /* No index reg */
2335
2336 /* It aint simple */
2337 nextword |= 0x100;
2338 /* If the guy specified a width, we assume that
2339 it is wide enough. Maybe it isn't. If so, we lose
2340 */
2341 switch (siz1)
2342 {
2343 case 0:
2344 if (isvar (opP->con1) || !issword (baseo))
2345 {
2346 siz1 = 3;
2347 nextword |= 0x30;
2348 }
2349 else if (baseo == 0)
2350 nextword |= 0x10;
2351 else
2352 {
2353 nextword |= 0x20;
2354 siz1 = 2;
2355 }
2356 break;
2357 case 1:
2358 as_warn ("Byte dispacement won't work. Defaulting to :w");
2359 case 2:
2360 nextword |= 0x20;
2361 break;
2362 case 3:
2363 nextword |= 0x30;
2364 break;
2365 }
2366
2367 /* Figure out innner displacement stuff */
2368 if (opP->mode != AINDX)
2369 {
2370 switch (siz2)
2371 {
2372 case 0:
2373 if (isvar (opP->con2) || !issword (outro))
2374 {
2375 siz2 = 3;
2376 nextword |= 0x3;
2377 }
2378 else if (outro == 0)
2379 nextword |= 0x1;
2380 else
2381 {
2382 nextword |= 0x2;
2383 siz2 = 2;
2384 }
2385 break;
2386 case 1:
2387 as_warn ("Byte dispacement won't work. Defaulting to :w");
2388 case 2:
2389 nextword |= 0x2;
2390 break;
2391 case 3:
2392 nextword |= 0x3;
2393 break;
2394 }
2395 if (opP->mode == APODX)
2396 nextword |= 0x04;
2397 else if (opP->mode == AMIND)
2398 nextword |= 0x40;
2399 }
2400 addword (nextword);
2401
2402 if (isvar (opP->con1))
2403 {
2404 if (opP->reg == PC || opP->reg == ZPC)
2405 {
2406 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 1);
2407 opP->con1->e_exp.X_add_number += 6;
2408 }
2409 else
2410 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 0);
2411 }
2412 if (siz1 == 3)
2413 addword (baseo >> 16);
2414 if (siz1)
2415 addword (baseo);
2416
2417 if (isvar (opP->con2))
2418 {
2419 if (opP->reg == PC || opP->reg == ZPC)
2420 {
2421 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 1);
2422 opP->con1->e_exp.X_add_number += 6;
2423 }
2424 else
2425 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 0);
2426 }
2427 if (siz2 == 3)
2428 addword (outro >> 16);
2429 if (siz2)
2430 addword (outro);
2431
2432 break;
2433
2434 case ABSL:
2435 nextword = get_num (opP->con1, 80);
2436 switch (opP->con1->e_siz)
2437 {
2438 default:
2439 as_warn ("Unknown size for absolute reference");
2440 case 0:
2441 if (!isvar (opP->con1) && issword (offs (opP->con1)))
2442 {
2443 tmpreg = 0x38; /* 7.0 */
2444 addword (nextword);
2445 break;
2446 }
2447 /* Don't generate pc relative code
2448 on 68010 and 68000 */
2449 if (isvar (opP->con1)
2450 && !subs (opP->con1)
2451 && seg (opP->con1) == SEG_TEXT
2452 && now_seg == SEG_TEXT
2453 && cpu_of_arch (current_architecture) >= m68020
2454 && !flagseen['S']
2455 && !strchr ("~%&$?", s[0]))
2456 {
2457 tmpreg = 0x3A; /* 7.2 */
2458 add_frag (adds (opP->con1),
2459 offs (opP->con1),
2460 TAB (PCREL, SZ_UNDEF));
2461 break;
2462 }
2463 case 3: /* Fall through into long */
2464 if (isvar (opP->con1))
2465 add_fix ('l', opP->con1, 0);
2466
2467 tmpreg = 0x39;/* 7.1 mode */
2468 addword (nextword >> 16);
2469 addword (nextword);
2470 break;
2471
2472 case 2: /* Word */
2473 if (isvar (opP->con1))
2474 add_fix ('w', opP->con1, 0);
2475
2476 tmpreg = 0x38;/* 7.0 mode */
2477 addword (nextword);
2478 break;
2479 }
2480 break;
2481 case DINDR:
2482 as_bad ("invalid indirect register");
2483 break;
2484 case MSCR:
2485 default:
2486 as_bad ("unknown/incorrect operand");
2487 /* abort(); */
2488 }
2489 install_gen_operand (s[1], tmpreg);
2490 break;
2491
2492 case '#':
2493 case '^':
2494 switch (s[1])
2495 { /* JF: I hate floating point! */
2496 case 'j':
2497 tmpreg = 70;
2498 break;
2499 case '8':
2500 tmpreg = 20;
2501 break;
2502 case 'C':
2503 tmpreg = 50;
2504 break;
2505 case '3':
2506 default:
2507 tmpreg = 80;
2508 break;
2509 }
2510 tmpreg = get_num (opP->con1, tmpreg);
2511 if (isvar (opP->con1))
2512 add_fix (s[1], opP->con1, 0);
2513 switch (s[1])
2514 {
2515 case 'b': /* Danger: These do no check for
2516 certain types of overflow.
2517 user beware! */
2518 if (!isbyte (tmpreg))
2519 opP->error = "out of range";
2520 insop (tmpreg);
2521 if (isvar (opP->con1))
2522 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2523 break;
2524 case 'w':
2525 if (!isword (tmpreg))
2526 opP->error = "out of range";
2527 insop (tmpreg);
2528 if (isvar (opP->con1))
2529 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2530 break;
2531 case 'l':
2532 insop (tmpreg); /* Because of the way insop works, we put these two out backwards */
2533 insop (tmpreg >> 16);
2534 if (isvar (opP->con1))
2535 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2536 break;
2537 case '3':
2538 tmpreg &= 0xFF;
2539 case '8':
2540 case 'C':
2541 install_operand (s[1], tmpreg);
2542 break;
2543 default:
2544 as_fatal ("Internal error: Unknown mode #%c in line %s of file \"%s\"", s[1], __LINE__, __FILE__);
2545 }
2546 break;
2547
2548 case '+':
2549 case '-':
2550 case 'A':
2551 case 'a':
2552 install_operand (s[1], opP->reg - ADDR);
2553 break;
2554
2555 case 'B':
2556 tmpreg = get_num (opP->con1, 80);
2557 switch (s[1])
2558 {
2559 case 'B':
2560 /* Needs no offsetting */
2561 add_fix ('B', opP->con1, 1);
2562 break;
2563 case 'W':
2564 /* Offset the displacement to be relative to byte disp location */
2565 opP->con1->e_exp.X_add_number += 2;
2566 add_fix ('w', opP->con1, 1);
2567 addword (0);
2568 break;
2569 case 'L':
2570 long_branch:
2571 if (cpu_of_arch (current_architecture) < m68020) /* 68000 or 010 */
2572 as_warn ("Can't use long branches on 68000/68010");
2573 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2574 /* Offset the displacement to be relative to byte disp location */
2575 opP->con1->e_exp.X_add_number += 4;
2576 add_fix ('l', opP->con1, 1);
2577 addword (0);
2578 addword (0);
2579 break;
2580 case 'g':
2581 if (subs (opP->con1)) /* We can't relax it */
2582 goto long_branch;
2583
2584 /* This could either be a symbol, or an
2585 absolute address. No matter, the
2586 frag hacking will finger it out.
2587 Not quite: it can't switch from
2588 BRANCH to BCC68000 for the case
2589 where opnd is absolute (it needs
2590 to use the 68000 hack since no
2591 conditional abs jumps). */
2592 if (((cpu_of_arch (current_architecture) < m68020) || (0 == adds (opP->con1)))
2593 && (the_ins.opcode[0] >= 0x6200)
2594 && (the_ins.opcode[0] <= 0x6f00))
2595 {
2596 add_frag (adds (opP->con1), offs (opP->con1), TAB (BCC68000, SZ_UNDEF));
2597 }
2598 else
2599 {
2600 add_frag (adds (opP->con1), offs (opP->con1), TAB (ABRANCH, SZ_UNDEF));
2601 }
2602 break;
2603 case 'w':
2604 if (isvar (opP->con1))
2605 {
2606 /* check for DBcc instruction */
2607 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2608 {
2609 /* size varies if patch */
2610 /* needed for long form */
2611 add_frag (adds (opP->con1), offs (opP->con1), TAB (DBCC, SZ_UNDEF));
2612 break;
2613 }
2614
2615 /* Don't ask! */
2616 opP->con1->e_exp.X_add_number += 2;
2617 add_fix ('w', opP->con1, 1);
2618 }
2619 addword (0);
2620 break;
2621 case 'C': /* Fixed size LONG coproc branches */
2622 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2623 /* Offset the displacement to be relative to byte disp location */
2624 /* Coproc branches don't have a byte disp option, but they are
2625 compatible with the ordinary branches, which do... */
2626 opP->con1->e_exp.X_add_number += 4;
2627 add_fix ('l', opP->con1, 1);
2628 addword (0);
2629 addword (0);
2630 break;
2631 case 'c': /* Var size Coprocesssor branches */
2632 if (subs (opP->con1))
2633 {
2634 add_fix ('l', opP->con1, 1);
2635 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2636 }
2637 else if (adds (opP->con1))
2638 {
2639 add_frag (adds (opP->con1), offs (opP->con1), TAB (FBRANCH, SZ_UNDEF));
2640 }
2641 else
2642 {
2643 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2644 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2645 add_fix ('l', opP->con1, 1);
2646 addword (0);
2647 addword (4);
2648 }
2649 break;
2650 default:
2651 as_fatal ("Internal error: operand type B%c unknown in line %s of file \"%s\"",
2652 s[1], __LINE__, __FILE__);
2653 }
2654 break;
2655
2656 case 'C': /* Ignore it */
2657 break;
2658
2659 case 'd': /* JF this is a kludge */
2660 if (opP->mode == AOFF)
2661 {
2662 install_operand ('s', opP->reg - ADDR);
2663 }
2664 else
2665 {
2666 char *tmpP;
2667
2668 tmpP = opP->con1->e_end - 2;
2669 opP->con1->e_beg++;
2670 opP->con1->e_end -= 4; /* point to the , */
2671 baseo = m68k_reg_parse (&tmpP);
2672 if (baseo < ADDR + 0 || baseo > ADDR + 7)
2673 {
2674 as_bad ("Unknown address reg, using A0");
2675 baseo = 0;
2676 }
2677 else
2678 baseo -= ADDR;
2679 install_operand ('s', baseo);
2680 }
2681 tmpreg = get_num (opP->con1, 80);
2682 if (!issword (tmpreg))
2683 {
2684 as_warn ("Expression out of range, using 0");
2685 tmpreg = 0;
2686 }
2687 addword (tmpreg);
2688 break;
2689
2690 case 'D':
2691 install_operand (s[1], opP->reg - DATA);
2692 break;
2693
2694 case 'F':
2695 install_operand (s[1], opP->reg - FPREG);
2696 break;
2697
2698 case 'I':
2699 tmpreg = 1 + opP->reg - COPNUM;
2700 if (tmpreg == 8)
2701 tmpreg = 0;
2702 install_operand (s[1], tmpreg);
2703 break;
2704
2705 case 'J': /* JF foo */
2706 switch (opP->reg)
2707 {
2708 case SFC:
2709 tmpreg = 0x000;
2710 break;
2711 case DFC:
2712 tmpreg = 0x001;
2713 break;
2714 case CACR:
2715 tmpreg = 0x002;
2716 break;
2717 case TC:
2718 tmpreg = 0x003;
2719 break;
2720 case ITT0:
2721 tmpreg = 0x004;
2722 break;
2723 case ITT1:
2724 tmpreg = 0x005;
2725 break;
2726 case DTT0:
2727 tmpreg = 0x006;
2728 break;
2729 case DTT1:
2730 tmpreg = 0x007;
2731 break;
2732
2733 case USP:
2734 tmpreg = 0x800;
2735 break;
2736 case VBR:
2737 tmpreg = 0x801;
2738 break;
2739 case CAAR:
2740 tmpreg = 0x802;
2741 break;
2742 case MSP:
2743 tmpreg = 0x803;
2744 break;
2745 case ISP:
2746 tmpreg = 0x804;
2747 break;
2748 case MMUSR:
2749 tmpreg = 0x805;
2750 break;
2751 case URP:
2752 tmpreg = 0x806;
2753 break;
2754 case SRP:
2755 tmpreg = 0x807;
2756 break;
2757 default:
2758 as_fatal ("failed sanity check.");
2759 }
2760 install_operand (s[1], tmpreg);
2761 break;
2762
2763 case 'k':
2764 tmpreg = get_num (opP->con1, 55);
2765 install_operand (s[1], tmpreg & 0x7f);
2766 break;
2767
2768 case 'l':
2769 tmpreg = opP->reg;
2770 if (s[1] == 'w')
2771 {
2772 if (tmpreg & 0x7FF0000)
2773 as_bad ("Floating point register in register list");
2774 insop (reverse_16_bits (tmpreg));
2775 }
2776 else
2777 {
2778 if (tmpreg & 0x700FFFF)
2779 as_bad ("Wrong register in floating-point reglist");
2780 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2781 }
2782 break;
2783
2784 case 'L':
2785 tmpreg = opP->reg;
2786 if (s[1] == 'w')
2787 {
2788 if (tmpreg & 0x7FF0000)
2789 as_bad ("Floating point register in register list");
2790 insop (tmpreg);
2791 }
2792 else if (s[1] == '8')
2793 {
2794 if (tmpreg & 0x0FFFFFF)
2795 as_bad ("incorrect register in reglist");
2796 install_operand (s[1], tmpreg >> 24);
2797 }
2798 else
2799 {
2800 if (tmpreg & 0x700FFFF)
2801 as_bad ("wrong register in floating-point reglist");
2802 else
2803 install_operand (s[1], tmpreg >> 16);
2804 }
2805 break;
2806
2807 case 'M':
2808 install_operand (s[1], get_num (opP->con1, 60));
2809 break;
2810
2811 case 'O':
2812 tmpreg = (opP->mode == DREG)
2813 ? 0x20 + opP->reg - DATA
2814 : (get_num (opP->con1, 40) & 0x1F);
2815 install_operand (s[1], tmpreg);
2816 break;
2817
2818 case 'Q':
2819 tmpreg = get_num (opP->con1, 10);
2820 if (tmpreg == 8)
2821 tmpreg = 0;
2822 install_operand (s[1], tmpreg);
2823 break;
2824
2825 case 'R':
2826 case 'r':
2827 /* This depends on the fact that ADDR registers are
2828 eight more than their corresponding DATA regs, so
2829 the result will have the ADDR_REG bit set */
2830 install_operand (s[1], opP->reg - DATA);
2831 break;
2832
2833 case 's':
2834 if (opP->reg == FPI)
2835 tmpreg = 0x1;
2836 else if (opP->reg == FPS)
2837 tmpreg = 0x2;
2838 else if (opP->reg == FPC)
2839 tmpreg = 0x4;
2840 else
2841 as_fatal ("failed sanity check.");
2842 install_operand (s[1], tmpreg);
2843 break;
2844
2845 case 'S': /* Ignore it */
2846 break;
2847
2848 case 'T':
2849 install_operand (s[1], get_num (opP->con1, 30));
2850 break;
2851
2852 case 'U': /* Ignore it */
2853 break;
2854
2855 case 'c':
2856 switch (opP->reg)
2857 {
2858 case NC:
2859 tmpreg = 0;
2860 break;
2861 case DC:
2862 tmpreg = 1;
2863 break;
2864 case IC:
2865 tmpreg = 2;
2866 break;
2867 case BC:
2868 tmpreg = 3;
2869 break;
2870 default:
2871 as_fatal ("failed sanity check");
2872 } /* switch on cache token */
2873 install_operand (s[1], tmpreg);
2874 break;
2875 #ifndef NO_68851
2876 /* JF: These are out of order, I fear. */
2877 case 'f':
2878 switch (opP->reg)
2879 {
2880 case SFC:
2881 tmpreg = 0;
2882 break;
2883 case DFC:
2884 tmpreg = 1;
2885 break;
2886 default:
2887 as_fatal ("failed sanity check.");
2888 }
2889 install_operand (s[1], tmpreg);
2890 break;
2891
2892 case 'P':
2893 switch (opP->reg)
2894 {
2895 case TC:
2896 tmpreg = 0;
2897 break;
2898 case CAL:
2899 tmpreg = 4;
2900 break;
2901 case VAL:
2902 tmpreg = 5;
2903 break;
2904 case SCC:
2905 tmpreg = 6;
2906 break;
2907 case AC:
2908 tmpreg = 7;
2909 break;
2910 default:
2911 as_fatal ("failed sanity check.");
2912 }
2913 install_operand (s[1], tmpreg);
2914 break;
2915
2916 case 'V':
2917 if (opP->reg == VAL)
2918 break;
2919 as_fatal ("failed sanity check.");
2920
2921 case 'W':
2922 switch (opP->reg)
2923 {
2924
2925 case DRP:
2926 tmpreg = 1;
2927 break;
2928 case SRP:
2929 tmpreg = 2;
2930 break;
2931 case CRP:
2932 tmpreg = 3;
2933 break;
2934 default:
2935 as_fatal ("failed sanity check.");
2936 }
2937 install_operand (s[1], tmpreg);
2938 break;
2939
2940 case 'X':
2941 switch (opP->reg)
2942 {
2943 case BAD:
2944 case BAD + 1:
2945 case BAD + 2:
2946 case BAD + 3:
2947 case BAD + 4:
2948 case BAD + 5:
2949 case BAD + 6:
2950 case BAD + 7:
2951 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2952 break;
2953
2954 case BAC:
2955 case BAC + 1:
2956 case BAC + 2:
2957 case BAC + 3:
2958 case BAC + 4:
2959 case BAC + 5:
2960 case BAC + 6:
2961 case BAC + 7:
2962 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2963 break;
2964
2965 default:
2966 as_fatal ("failed sanity check.");
2967 }
2968 install_operand (s[1], tmpreg);
2969 break;
2970 case 'Y':
2971 know (opP->reg == PSR);
2972 break;
2973 case 'Z':
2974 know (opP->reg == PCSR);
2975 break;
2976 #endif /* m68851 */
2977 case '3':
2978 switch (opP->reg)
2979 {
2980 case TT0:
2981 tmpreg = 2;
2982 break;
2983 case TT1:
2984 tmpreg = 3;
2985 break;
2986 default:
2987 as_fatal ("failed sanity check");
2988 }
2989 install_operand (s[1], tmpreg);
2990 break;
2991 case 't':
2992 tmpreg = get_num (opP->con1, 20);
2993 install_operand (s[1], tmpreg);
2994 break;
2995 case '_': /* used only for move16 absolute 32-bit address */
2996 tmpreg = get_num (opP->con1, 80);
2997 addword (tmpreg >> 16);
2998 addword (tmpreg & 0xFFFF);
2999 break;
3000 default:
3001 as_fatal ("Internal error: Operand type %c unknown in line %d of file \"%s\"",
3002 s[0], __LINE__, __FILE__);
3003 }
3004 }
3005
3006 /* By the time whe get here (FINALLY) the_ins contains the complete
3007 instruction, ready to be emitted. . . */
3008 } /* m68k_ip() */
3009
3010 /*
3011 * get_regs := '/' + ?
3012 * | '-' + <register>
3013 * | '-' + <register> + ?
3014 * | <empty>
3015 * ;
3016 *
3017
3018 * The idea here must be to scan in a set of registers but I don't
3019 * understand it. Looks awfully sloppy to me but I don't have any doc on
3020 * this format so...
3021
3022 *
3023 *
3024 */
3025
3026 static int
3027 get_regs (i, str, opP)
3028 int i;
3029 struct m68k_op *opP;
3030 char *str;
3031 {
3032 /* 26, 25, 24, 23-16, 15-8, 0-7 */
3033 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
3034 unsigned long cur_regs = 0;
3035 int reg1, reg2;
3036
3037 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
3038 else if(x==FPS) cur_regs|=(1<<25);\
3039 else if(x==FPC) cur_regs|=(1<<26);\
3040 else cur_regs|=(1<<(x-1)); }
3041
3042 reg1 = i;
3043 for (;;)
3044 {
3045 if (*str == '/')
3046 {
3047 ADD_REG (reg1);
3048 str++;
3049 }
3050 else if (*str == '-')
3051 {
3052 str++;
3053 reg2 = m68k_reg_parse (&str);
3054 if (reg2 < DATA || reg2 >= FPREG + 8 || reg1 == FPI || reg1 == FPS || reg1 == FPC)
3055 {
3056 opP->error = "unknown register in register list";
3057 return FAIL;
3058 }
3059 while (reg1 <= reg2)
3060 {
3061 ADD_REG (reg1);
3062 reg1++;
3063 }
3064 if (*str == '\0')
3065 break;
3066 }
3067 else if (*str == '\0')
3068 {
3069 ADD_REG (reg1);
3070 break;
3071 }
3072 else
3073 {
3074 opP->error = "unknow character in register list";
3075 return FAIL;
3076 }
3077 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
3078 if (*str == '/')
3079 str++;
3080 reg1 = m68k_reg_parse (&str);
3081 if ((reg1 < DATA || reg1 >= FPREG + 8) && !(reg1 == FPI || reg1 == FPS || reg1 == FPC))
3082 {
3083 opP->error = "unknown register in register list";
3084 return FAIL;
3085 }
3086 }
3087 opP->reg = cur_regs;
3088 return OK;
3089 } /* get_regs() */
3090
3091 static int
3092 reverse_16_bits (in)
3093 int in;
3094 {
3095 int out = 0;
3096 int n;
3097
3098 static int mask[16] =
3099 {
3100 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3101 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3102 };
3103 for (n = 0; n < 16; n++)
3104 {
3105 if (in & mask[n])
3106 out |= mask[15 - n];
3107 }
3108 return out;
3109 } /* reverse_16_bits() */
3110
3111 static int
3112 reverse_8_bits (in)
3113 int in;
3114 {
3115 int out = 0;
3116 int n;
3117
3118 static int mask[8] =
3119 {
3120 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3121 };
3122
3123 for (n = 0; n < 8; n++)
3124 {
3125 if (in & mask[n])
3126 out |= mask[7 - n];
3127 }
3128 return out;
3129 } /* reverse_8_bits() */
3130
3131 static void
3132 install_operand (mode, val)
3133 int mode;
3134 int val;
3135 {
3136 switch (mode)
3137 {
3138 case 's':
3139 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3140 break;
3141 case 'd':
3142 the_ins.opcode[0] |= val << 9;
3143 break;
3144 case '1':
3145 the_ins.opcode[1] |= val << 12;
3146 break;
3147 case '2':
3148 the_ins.opcode[1] |= val << 6;
3149 break;
3150 case '3':
3151 the_ins.opcode[1] |= val;
3152 break;
3153 case '4':
3154 the_ins.opcode[2] |= val << 12;
3155 break;
3156 case '5':
3157 the_ins.opcode[2] |= val << 6;
3158 break;
3159 case '6':
3160 /* DANGER! This is a hack to force cas2l and cas2w cmds
3161 to be three words long! */
3162 the_ins.numo++;
3163 the_ins.opcode[2] |= val;
3164 break;
3165 case '7':
3166 the_ins.opcode[1] |= val << 7;
3167 break;
3168 case '8':
3169 the_ins.opcode[1] |= val << 10;
3170 break;
3171 #ifndef NO_68851
3172 case '9':
3173 the_ins.opcode[1] |= val << 5;
3174 break;
3175 #endif
3176
3177 case 't':
3178 the_ins.opcode[1] |= (val << 10) | (val << 7);
3179 break;
3180 case 'D':
3181 the_ins.opcode[1] |= (val << 12) | val;
3182 break;
3183 case 'g':
3184 the_ins.opcode[0] |= val = 0xff;
3185 break;
3186 case 'i':
3187 the_ins.opcode[0] |= val << 9;
3188 break;
3189 case 'C':
3190 the_ins.opcode[1] |= val;
3191 break;
3192 case 'j':
3193 the_ins.opcode[1] |= val;
3194 the_ins.numo++; /* What a hack */
3195 break;
3196 case 'k':
3197 the_ins.opcode[1] |= val << 4;
3198 break;
3199 case 'b':
3200 case 'w':
3201 case 'l':
3202 break;
3203 case 'e':
3204 the_ins.opcode[0] |= (val << 6);
3205 break;
3206 case 'L':
3207 the_ins.opcode[1] = (val >> 16);
3208 the_ins.opcode[2] = val & 0xffff;
3209 break;
3210 case 'c':
3211 default:
3212 as_fatal ("failed sanity check.");
3213 }
3214 } /* install_operand() */
3215
3216 static void
3217 install_gen_operand (mode, val)
3218 int mode;
3219 int val;
3220 {
3221 switch (mode)
3222 {
3223 case 's':
3224 the_ins.opcode[0] |= val;
3225 break;
3226 case 'd':
3227 /* This is a kludge!!! */
3228 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3229 break;
3230 case 'b':
3231 case 'w':
3232 case 'l':
3233 case 'f':
3234 case 'F':
3235 case 'x':
3236 case 'p':
3237 the_ins.opcode[0] |= val;
3238 break;
3239 /* more stuff goes here */
3240 default:
3241 as_fatal ("failed sanity check.");
3242 }
3243 } /* install_gen_operand() */
3244
3245 /*
3246 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3247 * then deal with the bitfield hack.
3248 */
3249
3250 static char *
3251 crack_operand (str, opP)
3252 register char *str;
3253 register struct m68k_op *opP;
3254 {
3255 register int parens;
3256 register int c;
3257 register char *beg_str;
3258
3259 if (!str)
3260 {
3261 return str;
3262 }
3263 beg_str = str;
3264 for (parens = 0; *str && (parens > 0 || notend (str)); str++)
3265 {
3266 if (*str == '(')
3267 parens++;
3268 else if (*str == ')')
3269 {
3270 if (!parens)
3271 { /* ERROR */
3272 opP->error = "Extra )";
3273 return str;
3274 }
3275 --parens;
3276 }
3277 }
3278 if (!*str && parens)
3279 { /* ERROR */
3280 opP->error = "Missing )";
3281 return str;
3282 }
3283 c = *str;
3284 *str = '\0';
3285 if (m68k_ip_op (beg_str, opP) == FAIL)
3286 {
3287 *str = c;
3288 return str;
3289 }
3290 *str = c;
3291 if (c == '}')
3292 c = *++str; /* JF bitfield hack */
3293 if (c)
3294 {
3295 c = *++str;
3296 if (!c)
3297 as_bad ("Missing operand");
3298 }
3299 return str;
3300 }
3301
3302 /* See the comment up above where the #define notend(... is */
3303 #if 0
3304 notend (s)
3305 char *s;
3306 {
3307 if (*s == ',')
3308 return 0;
3309 if (*s == '{' || *s == '}')
3310 return 0;
3311 if (*s != ':')
3312 return 1;
3313 /* This kludge here is for the division cmd, which is a kludge */
3314 if (index ("aAdD#", s[1]))
3315 return 0;
3316 return 1;
3317 }
3318
3319 #endif
3320
3321 /* This is the guts of the machine-dependent assembler. STR points to a
3322 machine dependent instruction. This function is supposed to emit
3323 the frags/bytes it assembles to.
3324 */
3325
3326 void
3327 insert_reg (regname, regnum)
3328 char *regname;
3329 int regnum;
3330 {
3331 char buf[100];
3332 int i;
3333
3334 #ifdef REGISTER_PREFIX
3335 buf[0] = REGISTER_PREFIX;
3336 strcpy (buf + 1, regname);
3337 regname = buf;
3338 #endif
3339
3340 symbol_table_insert (symbol_new (regname, SEG_REGISTER, regnum, &zero_address_frag));
3341
3342 for (i = 0; regname[i]; i++)
3343 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3344 buf[i] = '\0';
3345
3346 symbol_table_insert (symbol_new (buf, SEG_REGISTER, regnum, &zero_address_frag));
3347 }
3348
3349 static const struct
3350 {
3351 char *name;
3352 int number;
3353 }
3354
3355 init_table[] =
3356 {
3357 "d0", DATA0,
3358 "d1", DATA1,
3359 "d2", DATA2,
3360 "d3", DATA3,
3361 "d4", DATA4,
3362 "d5", DATA5,
3363 "d6", DATA6,
3364 "d7", DATA7,
3365 "a0", ADDR0,
3366 "a1", ADDR1,
3367 "a2", ADDR2,
3368 "a3", ADDR3,
3369 "a4", ADDR4,
3370 "a5", ADDR5,
3371 "a6", ADDR6,
3372 "fp", ADDR6,
3373 "a7", ADDR7,
3374 "sp", ADDR7,
3375 "fp0", FP0,
3376 "fp1", FP1,
3377 "fp2", FP2,
3378 "fp3", FP3,
3379 "fp4", FP4,
3380 "fp5", FP5,
3381 "fp6", FP6,
3382 "fp7", FP7,
3383 "fpi", FPI,
3384 "fpiar", FPI,
3385 "fpc", FPI,
3386 "fps", FPS,
3387 "fpsr", FPS,
3388 "fpc", FPC,
3389 "fpcr", FPC,
3390
3391 "cop0", COP0,
3392 "cop1", COP1,
3393 "cop2", COP2,
3394 "cop3", COP3,
3395 "cop4", COP4,
3396 "cop5", COP5,
3397 "cop6", COP6,
3398 "cop7", COP7,
3399 "pc", PC,
3400 "zpc", ZPC,
3401 "sr", SR,
3402
3403 "ccr", CCR,
3404 "cc", CCR,
3405
3406 "usp", USP,
3407 "isp", ISP,
3408 "sfc", SFC,
3409 "dfc", DFC,
3410 "cacr", CACR,
3411 "caar", CAAR,
3412
3413 "vbr", VBR,
3414
3415 "msp", MSP,
3416 "itt0", ITT0,
3417 "itt1", ITT1,
3418 "dtt0", DTT0,
3419 "dtt1", DTT1,
3420 "mmusr", MMUSR,
3421 "tc", TC,
3422 "srp", SRP,
3423 "urp", URP,
3424
3425 "ac", AC,
3426 "bc", BC,
3427 "cal", CAL,
3428 "crp", CRP,
3429 "drp", DRP,
3430 "pcsr", PCSR,
3431 "psr", PSR,
3432 "scc", SCC,
3433 "val", VAL,
3434 "bad0", BAD0,
3435 "bad1", BAD1,
3436 "bad2", BAD2,
3437 "bad3", BAD3,
3438 "bad4", BAD4,
3439 "bad5", BAD5,
3440 "bad6", BAD6,
3441 "bad7", BAD7,
3442 "bac0", BAC0,
3443 "bac1", BAC1,
3444 "bac2", BAC2,
3445 "bac3", BAC3,
3446 "bac4", BAC4,
3447 "bac5", BAC5,
3448 "bac6", BAC6,
3449 "bac7", BAC7,
3450
3451 "ic", IC,
3452 "dc", DC,
3453 "nc", NC,
3454
3455 "tt0", TT0,
3456 "tt1", TT1,
3457 /* 68ec030 versions of same */
3458 "ac0", TT0,
3459 "ac1", TT1,
3460 /* 68ec030 access control unit, identical to 030 MMU status reg */
3461 "acusr", PSR,
3462
3463 0,
3464
3465 };
3466
3467
3468 void
3469 init_regtable ()
3470 {
3471 int i;
3472 for (i = 0; init_table[i].name; i++)
3473 insert_reg (init_table[i].name, init_table[i].number);
3474 }
3475
3476 static int no_68851, no_68881;
3477
3478 void
3479 md_assemble (str)
3480 char *str;
3481 {
3482 char *er;
3483 short *fromP;
3484 char *toP = NULL;
3485 int m, n = 0;
3486 char *to_beg_P;
3487 int shorts_this_frag;
3488 static int done_first_time;
3489
3490 if (!done_first_time)
3491 {
3492 done_first_time = 1;
3493
3494 if (cpu_of_arch (current_architecture) == 0)
3495 {
3496 int cpu_type;
3497
3498 #ifndef TARGET_CPU
3499 cpu_type = m68020;
3500 #else
3501 if (strcmp (TARGET_CPU, "m68000") == 0)
3502 cpu_type = m68000;
3503 else if (strcmp (TARGET_CPU, "m68010") == 0)
3504 cpu_type = m68010;
3505 else if (strcmp (TARGET_CPU, "m68020") == 0
3506 || strcmp (TARGET_CPU, "m68k") == 0)
3507 cpu_type = m68020;
3508 else if (strcmp (TARGET_CPU, "m68030") == 0)
3509 cpu_type = m68030;
3510 else if (strcmp (TARGET_CPU, "m68040") == 0)
3511 cpu_type = m68040;
3512 else if (strcmp (TARGET_CPU, "cpu32") == 0)
3513 cpu_type = cpu32;
3514 else
3515 cpu_type = m68020;
3516 #endif
3517
3518 current_architecture |= cpu_type;
3519 }
3520 #if 0 /* Could be doing emulation. */
3521 if (current_architecture & m68881)
3522 {
3523 if (current_architecture & m68000)
3524 as_bad ("incompatible processors 68000 and 68881/2 specified");
3525 if (current_architecture & m68010)
3526 as_bad ("incompatible processors 68010 and 68881/2 specified");
3527 if (current_architecture & m68040)
3528 as_bad ("incompatible processors 68040 and 68881/2 specified");
3529 }
3530 #endif
3531 /* What other incompatibilities could we check for? */
3532
3533 /* Toss in some default assumptions about coprocessors. */
3534 if (!no_68881
3535 && (cpu_of_arch (current_architecture)
3536 /* Can CPU32 have a 68881 coprocessor?? */
3537 & (m68020 | m68030 | cpu32)))
3538 {
3539 current_architecture |= m68881;
3540 }
3541 if (!no_68851
3542 && (cpu_of_arch (current_architecture) & m68020up) != 0)
3543 {
3544 current_architecture |= m68851;
3545 }
3546 if (no_68881 && (current_architecture & m68881))
3547 as_bad ("options for 68881 and no-68881 both given");
3548 if (no_68851 && (current_architecture & m68851))
3549 as_bad ("options for 68851 and no-68851 both given");
3550 done_first_time = 1;
3551 }
3552
3553 memset ((char *) (&the_ins), '\0', sizeof (the_ins)); /* JF for paranoia sake */
3554 m68k_ip (str);
3555 er = the_ins.error;
3556 if (!er)
3557 {
3558 for (n = the_ins.numargs; n; --n)
3559 if (the_ins.operands[n].error)
3560 {
3561 er = the_ins.operands[n].error;
3562 break;
3563 }
3564 }
3565 if (er)
3566 {
3567 as_bad ("%s -- statement `%s' ignored", er, str);
3568 return;
3569 }
3570
3571 if (the_ins.nfrag == 0)
3572 { /* No frag hacking involved; just put it out */
3573 toP = frag_more (2 * the_ins.numo);
3574 fromP = &the_ins.opcode[0];
3575 for (m = the_ins.numo; m; --m)
3576 {
3577 md_number_to_chars (toP, (long) (*fromP), 2);
3578 toP += 2;
3579 fromP++;
3580 }
3581 /* put out symbol-dependent info */
3582 for (m = 0; m < the_ins.nrel; m++)
3583 {
3584 switch (the_ins.reloc[m].wid)
3585 {
3586 case 'B':
3587 n = 1;
3588 break;
3589 case 'b':
3590 n = 1;
3591 break;
3592 case '3':
3593 n = 2;
3594 break;
3595 case 'w':
3596 n = 2;
3597 break;
3598 case 'l':
3599 n = 4;
3600 break;
3601 default:
3602 as_fatal ("Don't know how to figure width of %c in md_assemble()", the_ins.reloc[m].wid);
3603 }
3604
3605 fix_new (frag_now,
3606 (toP - frag_now->fr_literal) - the_ins.numo * 2 + the_ins.reloc[m].n,
3607 n,
3608 the_ins.reloc[m].add,
3609 the_ins.reloc[m].sub,
3610 the_ins.reloc[m].off,
3611 the_ins.reloc[m].pcrel,
3612 NO_RELOC);
3613 }
3614 return;
3615 }
3616
3617 /* There's some frag hacking */
3618 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3619 {
3620 int wid;
3621
3622 if (n == 0)
3623 wid = 2 * the_ins.fragb[n].fragoff;
3624 else
3625 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3626 toP = frag_more (wid);
3627 to_beg_P = toP;
3628 shorts_this_frag = 0;
3629 for (m = wid / 2; m; --m)
3630 {
3631 md_number_to_chars (toP, (long) (*fromP), 2);
3632 toP += 2;
3633 fromP++;
3634 shorts_this_frag++;
3635 }
3636 for (m = 0; m < the_ins.nrel; m++)
3637 {
3638 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag /* 2*the_ins.fragb[n].fragoff */ )
3639 {
3640 the_ins.reloc[m].n -= 2 * shorts_this_frag /* 2*the_ins.fragb[n].fragoff */ ;
3641 break;
3642 }
3643 wid = the_ins.reloc[m].wid;
3644 if (wid == 0)
3645 continue;
3646 the_ins.reloc[m].wid = 0;
3647 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3648
3649 fix_new (frag_now,
3650 (toP - frag_now->fr_literal) - the_ins.numo * 2 + the_ins.reloc[m].n,
3651 wid,
3652 the_ins.reloc[m].add,
3653 the_ins.reloc[m].sub,
3654 the_ins.reloc[m].off,
3655 the_ins.reloc[m].pcrel,
3656 NO_RELOC);
3657 }
3658 /* know(the_ins.fragb[n].fadd); */
3659 (void) frag_var (rs_machine_dependent, 10, 0, (relax_substateT) (the_ins.fragb[n].fragty),
3660 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3661 }
3662 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3663 shorts_this_frag = 0;
3664 if (n)
3665 {
3666 toP = frag_more (n * sizeof (short));
3667 while (n--)
3668 {
3669 md_number_to_chars (toP, (long) (*fromP), 2);
3670 toP += 2;
3671 fromP++;
3672 shorts_this_frag++;
3673 }
3674 }
3675 for (m = 0; m < the_ins.nrel; m++)
3676 {
3677 int wid;
3678
3679 wid = the_ins.reloc[m].wid;
3680 if (wid == 0)
3681 continue;
3682 the_ins.reloc[m].wid = 0;
3683 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3684
3685 fix_new (frag_now,
3686 (the_ins.reloc[m].n + toP - frag_now->fr_literal) - /* the_ins.numo */ shorts_this_frag * 2,
3687 wid,
3688 the_ins.reloc[m].add,
3689 the_ins.reloc[m].sub,
3690 the_ins.reloc[m].off,
3691 the_ins.reloc[m].pcrel,
3692 NO_RELOC);
3693 }
3694 }
3695
3696
3697
3698 void
3699 md_begin ()
3700 {
3701 /*
3702 * md_begin -- set up hash tables with 68000 instructions.
3703 * similar to what the vax assembler does. ---phr
3704 */
3705 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3706 a copy of it at runtime, adding in the information we want but isn't
3707 there. I think it'd be better to have an awk script hack the table
3708 at compile time. Or even just xstr the table and use it as-is. But
3709 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3710 names. */
3711
3712 register const struct m68k_opcode *ins;
3713 register struct m68k_incant *hack, *slak;
3714 register char *retval = 0; /* empty string, or error msg text */
3715 register unsigned int i;
3716 register char c;
3717
3718 if ((op_hash = hash_new ()) == NULL)
3719 as_fatal ("Virtual memory exhausted");
3720
3721 obstack_begin (&robyn, 4000);
3722 for (ins = m68k_opcodes; ins < endop; ins++)
3723 {
3724 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3725 do
3726 {
3727 /* we *could* ignore insns that don't match our
3728 arch here but just leaving them out of the
3729 hash. */
3730 slak->m_operands = ins->args;
3731 slak->m_opnum = strlen (slak->m_operands) / 2;
3732 slak->m_arch = ins->arch;
3733 slak->m_opcode = ins->opcode;
3734 /* This is kludgey */
3735 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3736 if ((ins + 1) != endop && !strcmp (ins->name, (ins + 1)->name))
3737 {
3738 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3739 ins++;
3740 }
3741 else
3742 slak->m_next = 0;
3743 slak = slak->m_next;
3744 }
3745 while (slak);
3746
3747 retval = hash_insert (op_hash, ins->name, (char *) hack);
3748 /* Didn't his mommy tell him about null pointers? */
3749 if (retval && *retval)
3750 as_bad ("Internal Error: Can't hash %s: %s", ins->name, retval);
3751 }
3752
3753 for (i = 0; i < sizeof (mklower_table); i++)
3754 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3755
3756 for (i = 0; i < sizeof (notend_table); i++)
3757 {
3758 notend_table[i] = 0;
3759 alt_notend_table[i] = 0;
3760 }
3761 notend_table[','] = 1;
3762 notend_table['{'] = 1;
3763 notend_table['}'] = 1;
3764 alt_notend_table['a'] = 1;
3765 alt_notend_table['A'] = 1;
3766 alt_notend_table['d'] = 1;
3767 alt_notend_table['D'] = 1;
3768 alt_notend_table['#'] = 1;
3769 alt_notend_table['f'] = 1;
3770 alt_notend_table['F'] = 1;
3771 #ifdef REGISTER_PREFIX
3772 alt_notend_table[REGISTER_PREFIX] = 1;
3773 #endif
3774 #ifdef OPTIONAL_REGISTER_PREFIX
3775 alt_notend_table[OPTIONAL_REGISTER_PREFIX] = 1;
3776 #endif
3777
3778 #ifndef MIT_SYNTAX_ONLY
3779 /* Insert pseudo ops, these have to go into the opcode table since
3780 gas expects pseudo ops to start with a dot */
3781 {
3782 int n = 0;
3783 while (mote_pseudo_table[n].poc_name)
3784 {
3785 hack = (struct m68k_incant *)
3786 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3787 hash_insert (op_hash,
3788 mote_pseudo_table[n].poc_name, (char *) hack);
3789 hack->m_operands = 0;
3790 hack->m_opnum = n;
3791 n++;
3792 }
3793 }
3794 #endif
3795
3796 init_regtable ();
3797 }
3798
3799 #if 0
3800 #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
3801 || (*s == ':' && strchr("aAdD#", s[1]))) \
3802 ? 0 : 1)
3803 #endif
3804
3805 /* This funciton is called once, before the assembler exits. It is
3806 supposed to do any final cleanup for this part of the assembler.
3807 */
3808 void
3809 md_end ()
3810 {
3811 }
3812
3813 /* Equal to MAX_PRECISION in atof-ieee.c */
3814 #define MAX_LITTLENUMS 6
3815
3816 /* Turn a string in input_line_pointer into a floating point constant of type
3817 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3818 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
3819 */
3820 char *
3821 md_atof (type, litP, sizeP)
3822 char type;
3823 char *litP;
3824 int *sizeP;
3825 {
3826 int prec;
3827 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3828 LITTLENUM_TYPE *wordP;
3829 char *t;
3830 char *atof_ieee ();
3831
3832 switch (type)
3833 {
3834 case 'f':
3835 case 'F':
3836 case 's':
3837 case 'S':
3838 prec = 2;
3839 break;
3840
3841 case 'd':
3842 case 'D':
3843 case 'r':
3844 case 'R':
3845 prec = 4;
3846 break;
3847
3848 case 'x':
3849 case 'X':
3850 prec = 6;
3851 break;
3852
3853 case 'p':
3854 case 'P':
3855 prec = 6;
3856 break;
3857
3858 default:
3859 *sizeP = 0;
3860 return "Bad call to MD_ATOF()";
3861 }
3862 t = atof_ieee (input_line_pointer, type, words);
3863 if (t)
3864 input_line_pointer = t;
3865
3866 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3867 for (wordP = words; prec--;)
3868 {
3869 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3870 litP += sizeof (LITTLENUM_TYPE);
3871 }
3872 return ""; /* Someone should teach Dean about null pointers */
3873 }
3874
3875 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3876 for use in the a.out file, and stores them in the array pointed to by buf.
3877 This knows about the endian-ness of the target machine and does
3878 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3879 2 (short) and 4 (long) Floating numbers are put out as a series of
3880 LITTLENUMS (shorts, here at least)
3881 */
3882 void
3883 md_number_to_chars (buf, val, n)
3884 char *buf;
3885 long val;
3886 int n;
3887 {
3888 switch (n)
3889 {
3890 case 1:
3891 *buf++ = val;
3892 break;
3893 case 2:
3894 *buf++ = (val >> 8);
3895 *buf++ = val;
3896 break;
3897 case 4:
3898 *buf++ = (val >> 24);
3899 *buf++ = (val >> 16);
3900 *buf++ = (val >> 8);
3901 *buf++ = val;
3902 break;
3903 default:
3904 as_fatal ("failed sanity check.");
3905 }
3906 }
3907
3908 void
3909 md_apply_fix (fixP, val)
3910 fixS *fixP;
3911 long val;
3912 {
3913 #ifdef IBM_COMPILER_SUX
3914 /* This is unnecessary but it convinces the native rs6000
3915 compiler to generate the code we want. */
3916 char *buf = fixP->fx_frag->fr_literal;
3917 buf += fixP->fx_where;
3918 #else /* IBM_COMPILER_SUX */
3919 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3920 #endif /* IBM_COMPILER_SUX */
3921
3922 switch (fixP->fx_size)
3923 {
3924 case 1:
3925 *buf++ = val;
3926 break;
3927 case 2:
3928 *buf++ = (val >> 8);
3929 *buf++ = val;
3930 break;
3931 case 4:
3932 *buf++ = (val >> 24);
3933 *buf++ = (val >> 16);
3934 *buf++ = (val >> 8);
3935 *buf++ = val;
3936 break;
3937 default:
3938 BAD_CASE (fixP->fx_size);
3939 }
3940 }
3941
3942
3943 /* *fragP has been relaxed to its final size, and now needs to have
3944 the bytes inside it modified to conform to the new size There is UGLY
3945 MAGIC here. ..
3946 */
3947 void
3948 md_convert_frag (headers, fragP)
3949 object_headers *headers;
3950 register fragS *fragP;
3951 {
3952 long disp;
3953 long ext = 0;
3954
3955 /* Address in object code of the displacement. */
3956 register int object_address = fragP->fr_fix + fragP->fr_address;
3957
3958 #ifdef IBM_COMPILER_SUX
3959 /* This is wrong but it convinces the native rs6000 compiler to
3960 generate the code we want. */
3961 register char *buffer_address = fragP->fr_literal;
3962 buffer_address += fragP->fr_fix;
3963 #else /* IBM_COMPILER_SUX */
3964 /* Address in gas core of the place to store the displacement. */
3965 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3966 #endif /* IBM_COMPILER_SUX */
3967
3968 /* No longer true: know(fragP->fr_symbol); */
3969
3970 /* The displacement of the address, from current location. */
3971 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3972 disp = (disp + fragP->fr_offset) - object_address;
3973
3974 switch (fragP->fr_subtype)
3975 {
3976 case TAB (BCC68000, BYTE):
3977 case TAB (ABRANCH, BYTE):
3978 know (issbyte (disp));
3979 if (disp == 0)
3980 as_bad ("short branch with zero offset: use :w");
3981 fragP->fr_opcode[1] = disp;
3982 ext = 0;
3983 break;
3984 case TAB (DBCC, SHORT):
3985 know (issword (disp));
3986 ext = 2;
3987 break;
3988 case TAB (BCC68000, SHORT):
3989 case TAB (ABRANCH, SHORT):
3990 know (issword (disp));
3991 fragP->fr_opcode[1] = 0x00;
3992 ext = 2;
3993 break;
3994 case TAB (ABRANCH, LONG):
3995 if (cpu_of_arch (current_architecture) < m68020)
3996 {
3997 if (fragP->fr_opcode[0] == 0x61)
3998 {
3999 fragP->fr_opcode[0] = 0x4E;
4000 fragP->fr_opcode[1] = 0xB9; /* JBSR with ABSL LONG offset */
4001 subseg_change (SEG_TEXT, 0);
4002
4003 fix_new (fragP,
4004 fragP->fr_fix,
4005 4,
4006 fragP->fr_symbol,
4007 0,
4008 fragP->fr_offset,
4009 0,
4010 NO_RELOC);
4011
4012 fragP->fr_fix += 4;
4013 ext = 0;
4014 }
4015 else if (fragP->fr_opcode[0] == 0x60)
4016 {
4017 fragP->fr_opcode[0] = 0x4E;
4018 fragP->fr_opcode[1] = 0xF9; /* JMP with ABSL LONG offset */
4019 subseg_change (SEG_TEXT, 0);
4020 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0,
4021 NO_RELOC);
4022 fragP->fr_fix += 4;
4023 ext = 0;
4024 }
4025 else
4026 {
4027 as_bad ("Long branch offset not supported.");
4028 }
4029 }
4030 else
4031 {
4032 fragP->fr_opcode[1] = 0xff;
4033 ext = 4;
4034 }
4035 break;
4036 case TAB (BCC68000, LONG):
4037 /* only Bcc 68000 instructions can come here */
4038 /* change bcc into b!cc/jmp absl long */
4039 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4040 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4041
4042 /* JF: these used to be fr_opcode[2,3], but they may be in a
4043 different frag, in which case refering to them is a no-no.
4044 Only fr_opcode[0,1] are guaranteed to work. */
4045 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4046 *buffer_address++ = 0xf9;
4047 fragP->fr_fix += 2; /* account for jmp instruction */
4048 subseg_change (SEG_TEXT, 0);
4049 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
4050 fragP->fr_offset, 0,
4051 NO_RELOC);
4052 fragP->fr_fix += 4;
4053 ext = 0;
4054 break;
4055 case TAB (DBCC, LONG):
4056 /* only DBcc 68000 instructions can come here */
4057 /* change dbcc into dbcc/jmp absl long */
4058 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4059 *buffer_address++ = 0x00; /* branch offset = 4 */
4060 *buffer_address++ = 0x04;
4061 *buffer_address++ = 0x60; /* put in bra pc+6 */
4062 *buffer_address++ = 0x06;
4063 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4064 *buffer_address++ = 0xf9;
4065
4066 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4067 subseg_change (SEG_TEXT, 0);
4068 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
4069 fragP->fr_offset, 0,
4070 NO_RELOC);
4071 fragP->fr_fix += 4;
4072 ext = 0;
4073 break;
4074 case TAB (FBRANCH, SHORT):
4075 know ((fragP->fr_opcode[1] & 0x40) == 0);
4076 ext = 2;
4077 break;
4078 case TAB (FBRANCH, LONG):
4079 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4080 ext = 4;
4081 break;
4082 case TAB (PCREL, SHORT):
4083 ext = 2;
4084 break;
4085 case TAB (PCREL, LONG):
4086 /* The thing to do here is force it to ABSOLUTE LONG, since
4087 PCREL is really trying to shorten an ABSOLUTE address anyway */
4088 /* JF FOO This code has not been tested */
4089 subseg_change (SEG_TEXT, 0);
4090 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
4091 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4092 as_bad ("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
4093 fragP->fr_opcode[0], fragP->fr_address);
4094 fragP->fr_opcode[1] &= ~0x3F;
4095 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4096 fragP->fr_fix += 4;
4097 /* md_number_to_chars(buffer_address,
4098 (long)(fragP->fr_symbol->sy_value + fragP->fr_offset),
4099 4); */
4100 ext = 0;
4101 break;
4102 case TAB (PCLEA, SHORT):
4103 subseg_change (SEG_TEXT, 0);
4104 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, (symbolS *) 0, fragP->fr_offset, 1,
4105 NO_RELOC);
4106 fragP->fr_opcode[1] &= ~0x3F;
4107 fragP->fr_opcode[1] |= 0x3A;
4108 ext = 2;
4109 break;
4110 case TAB (PCLEA, LONG):
4111 subseg_change (SEG_TEXT, 0);
4112 fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol, (symbolS *) 0, fragP->fr_offset + 2, 1,
4113 NO_RELOC);
4114 *buffer_address++ = 0x01;
4115 *buffer_address++ = 0x70;
4116 fragP->fr_fix += 2;
4117 /* buffer_address+=2; */
4118 ext = 4;
4119 break;
4120
4121 } /* switch on subtype */
4122
4123 if (ext)
4124 {
4125 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4126 fragP->fr_fix += ext;
4127 /* H_SET_TEXT_SIZE(headers, H_GET_TEXT_SIZE(headers) + ext); */
4128 } /* if extending */
4129
4130 return;
4131 } /* md_convert_frag() */
4132
4133 /* Force truly undefined symbols to their maximum size, and generally set up
4134 the frag list to be relaxed
4135 */
4136 int
4137 md_estimate_size_before_relax (fragP, segment)
4138 register fragS *fragP;
4139 segT segment;
4140 {
4141 int old_fix;
4142 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4143
4144 old_fix = fragP->fr_fix;
4145
4146 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4147 switch (fragP->fr_subtype)
4148 {
4149
4150 case TAB (ABRANCH, SZ_UNDEF):
4151 {
4152 if ((fragP->fr_symbol != NULL) /* Not absolute */
4153 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4154 {
4155 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4156 break;
4157 }
4158 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4159 {
4160 /* On 68000, or for absolute value, switch to abs long */
4161 /* FIXME, we should check abs val, pick short or long */
4162 if (fragP->fr_opcode[0] == 0x61)
4163 {
4164 fragP->fr_opcode[0] = 0x4E;
4165 fragP->fr_opcode[1] = 0xB9; /* JBSR with ABSL LONG offset */
4166 subseg_change (SEG_TEXT, 0);
4167 fix_new (fragP, fragP->fr_fix, 4,
4168 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
4169 fragP->fr_fix += 4;
4170 frag_wane (fragP);
4171 }
4172 else if (fragP->fr_opcode[0] == 0x60)
4173 {
4174 fragP->fr_opcode[0] = 0x4E;
4175 fragP->fr_opcode[1] = 0xF9; /* JMP with ABSL LONG offset */
4176 subseg_change (SEG_TEXT, 0);
4177 fix_new (fragP, fragP->fr_fix, 4,
4178 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
4179 fragP->fr_fix += 4;
4180 frag_wane (fragP);
4181 }
4182 else
4183 {
4184 as_warn ("Long branch offset to extern symbol not supported.");
4185 }
4186 }
4187 else
4188 { /* Symbol is still undefined. Make it simple */
4189 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4190 (symbolS *) 0, fragP->fr_offset + 4, 1, NO_RELOC);
4191 fragP->fr_fix += 4;
4192 fragP->fr_opcode[1] = 0xff;
4193 frag_wane (fragP);
4194 break;
4195 }
4196
4197 break;
4198 } /* case TAB(ABRANCH,SZ_UNDEF) */
4199
4200 case TAB (FBRANCH, SZ_UNDEF):
4201 {
4202 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flagseen['l'])
4203 {
4204 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4205 fragP->fr_var += 2;
4206 }
4207 else
4208 {
4209 fragP->fr_subtype = TAB (FBRANCH, LONG);
4210 fragP->fr_var += 4;
4211 }
4212 break;
4213 } /* TAB(FBRANCH,SZ_UNDEF) */
4214
4215 case TAB (PCREL, SZ_UNDEF):
4216 {
4217 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flagseen['l'])
4218 {
4219 fragP->fr_subtype = TAB (PCREL, SHORT);
4220 fragP->fr_var += 2;
4221 }
4222 else
4223 {
4224 fragP->fr_subtype = TAB (PCREL, LONG);
4225 fragP->fr_var += 4;
4226 }
4227 break;
4228 } /* TAB(PCREL,SZ_UNDEF) */
4229
4230 case TAB (BCC68000, SZ_UNDEF):
4231 {
4232 if ((fragP->fr_symbol != NULL)
4233 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4234 {
4235 fragP->fr_subtype = TAB (BCC68000, BYTE);
4236 break;
4237 }
4238 /* only Bcc 68000 instructions can come here */
4239 /* change bcc into b!cc/jmp absl long */
4240 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4241 if (flagseen['l'])
4242 {
4243 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4244 /* JF: these were fr_opcode[2,3] */
4245 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4246 buffer_address[1] = 0xf8;
4247 fragP->fr_fix += 2; /* account for jmp instruction */
4248 subseg_change (SEG_TEXT, 0);
4249 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
4250 fragP->fr_offset, 0, NO_RELOC);
4251 fragP->fr_fix += 2;
4252 }
4253 else
4254 {
4255 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4256 /* JF: these were fr_opcode[2,3] */
4257 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4258 buffer_address[1] = 0xf9;
4259 fragP->fr_fix += 2; /* account for jmp instruction */
4260 subseg_change (SEG_TEXT, 0);
4261 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
4262 fragP->fr_offset, 0, NO_RELOC);
4263 fragP->fr_fix += 4;
4264 }
4265 frag_wane (fragP);
4266 break;
4267 } /* case TAB(BCC68000,SZ_UNDEF) */
4268
4269 case TAB (DBCC, SZ_UNDEF):
4270 {
4271 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4272 {
4273 fragP->fr_subtype = TAB (DBCC, SHORT);
4274 fragP->fr_var += 2;
4275 break;
4276 }
4277 /* only DBcc 68000 instructions can come here */
4278 /* change dbcc into dbcc/jmp absl long */
4279 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4280 buffer_address[0] = 0x00; /* branch offset = 4 */
4281 buffer_address[1] = 0x04;
4282 buffer_address[2] = 0x60; /* put in bra pc + ... */
4283
4284 if (flagseen['l'])
4285 {
4286 /* JF: these were fr_opcode[5-7] */
4287 buffer_address[3] = 0x04; /* plus 4 */
4288 buffer_address[4] = 0x4e; /* Put in Jump Word */
4289 buffer_address[5] = 0xf8;
4290 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4291 subseg_change (SEG_TEXT, 0);
4292 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
4293
4294
4295 fragP->fr_offset, 0, NO_RELOC);
4296 fragP->fr_fix += 2;
4297 }
4298 else
4299 {
4300 /* JF: these were fr_opcode[5-7] */
4301 buffer_address[3] = 0x06; /* Plus 6 */
4302 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4303 buffer_address[5] = 0xf9;
4304 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4305 subseg_change (SEG_TEXT, 0);
4306 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
4307 fragP->fr_offset, 0, NO_RELOC);
4308 fragP->fr_fix += 4;
4309 }
4310
4311 frag_wane (fragP);
4312 break;
4313 } /* case TAB(DBCC,SZ_UNDEF) */
4314
4315 case TAB (PCLEA, SZ_UNDEF):
4316 {
4317 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment || flagseen['l'])
4318 {
4319 fragP->fr_subtype = TAB (PCLEA, SHORT);
4320 fragP->fr_var += 2;
4321 }
4322 else
4323 {
4324 fragP->fr_subtype = TAB (PCLEA, LONG);
4325 fragP->fr_var += 6;
4326 }
4327 break;
4328 } /* TAB(PCLEA,SZ_UNDEF) */
4329
4330 default:
4331 break;
4332
4333 } /* switch on subtype looking for SZ_UNDEF's. */
4334
4335 /* now that SZ_UNDEF are taken care of, check others */
4336 switch (fragP->fr_subtype)
4337 {
4338 case TAB (BCC68000, BYTE):
4339 case TAB (ABRANCH, BYTE):
4340 /* We can't do a short jump to the next instruction,
4341 so we force word mode. */
4342 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
4343 fragP->fr_symbol->sy_frag == fragP->fr_next)
4344 {
4345 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4346 fragP->fr_var += 2;
4347 }
4348 break;
4349 default:
4350 break;
4351 }
4352 return fragP->fr_var + fragP->fr_fix - old_fix;
4353 }
4354
4355 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4356 /* the bit-field entries in the relocation_info struct plays hell
4357 with the byte-order problems of cross-assembly. So as a hack,
4358 I added this mach. dependent ri twiddler. Ugly, but it gets
4359 you there. -KWK */
4360 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4361 are symbolnum, most sig. byte first. Last byte is broken up with
4362 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4363 nibble as nuthin. (on Sun 3 at least) */
4364 /* Translate the internal relocation information into target-specific
4365 format. */
4366 #ifdef comment
4367 void
4368 md_ri_to_chars (the_bytes, ri)
4369 char *the_bytes;
4370 struct reloc_info_generic *ri;
4371 {
4372 /* this is easy */
4373 md_number_to_chars (the_bytes, ri->r_address, 4);
4374 /* now the fun stuff */
4375 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4376 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4377 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4378 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4379 ((ri->r_extern << 4) & 0x10));
4380 }
4381
4382 #endif /* comment */
4383
4384 void
4385 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4386 char *where;
4387 fixS *fixP;
4388 relax_addressT segment_address_in_file;
4389 {
4390 /*
4391 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4392 * Out: GNU LD relocation length code: 0, 1, or 2.
4393 */
4394
4395 static CONST unsigned char nbytes_r_length[] =
4396 {42, 0, 1, 42, 2};
4397 long r_symbolnum;
4398
4399 know (fixP->fx_addsy != NULL);
4400
4401 md_number_to_chars (where,
4402 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4403 4);
4404
4405 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4406 ? S_GET_TYPE (fixP->fx_addsy)
4407 : fixP->fx_addsy->sy_number);
4408
4409 where[4] = (r_symbolnum >> 16) & 0x0ff;
4410 where[5] = (r_symbolnum >> 8) & 0x0ff;
4411 where[6] = r_symbolnum & 0x0ff;
4412 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4413 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4414
4415 return;
4416 } /* tc_aout_fix_to_chars() */
4417
4418 #endif /* OBJ_AOUT or OBJ_BOUT */
4419
4420 #ifndef WORKING_DOT_WORD
4421 const int md_short_jump_size = 4;
4422 const int md_long_jump_size = 6;
4423
4424 void
4425 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4426 char *ptr;
4427 long from_addr, to_addr;
4428 fragS *frag;
4429 symbolS *to_symbol;
4430 {
4431 long offset;
4432
4433 offset = to_addr - (from_addr + 2);
4434
4435 md_number_to_chars (ptr, (long) 0x6000, 2);
4436 md_number_to_chars (ptr + 2, (long) offset, 2);
4437 }
4438
4439 void
4440 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4441 char *ptr;
4442 long from_addr, to_addr;
4443 fragS *frag;
4444 symbolS *to_symbol;
4445 {
4446 long offset;
4447
4448 if (cpu_of_arch (current_architecture) < m68020)
4449 {
4450 offset = to_addr - S_GET_VALUE (to_symbol);
4451 md_number_to_chars (ptr, (long) 0x4EF9, 2);
4452 md_number_to_chars (ptr + 2, (long) offset, 4);
4453 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (symbolS *) 0, (long) 0, 0,
4454 NO_RELOC);
4455 }
4456 else
4457 {
4458 offset = to_addr - (from_addr + 2);
4459 md_number_to_chars (ptr, (long) 0x60ff, 2);
4460 md_number_to_chars (ptr + 2, (long) offset, 4);
4461 }
4462 }
4463
4464 #endif
4465 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
4466
4467 0: Everything is OK
4468 10: Absolute 1:8 only
4469 20: Absolute 0:7 only
4470 30: absolute 0:15 only
4471 40: Absolute 0:31 only
4472 50: absolute 0:127 only
4473 55: absolute -64:63 only
4474 60: absolute -128:127 only
4475 70: absolute 0:4095 only
4476 80: No bignums
4477
4478 */
4479
4480 static int
4481 get_num (exp, ok)
4482 struct m68k_exp *exp;
4483 int ok;
4484 {
4485 #ifdef TEST2
4486 long l = 0;
4487
4488 if (!exp->e_beg)
4489 return 0;
4490 if (*exp->e_beg == '0')
4491 {
4492 if (exp->e_beg[1] == 'x')
4493 sscanf (exp->e_beg + 2, "%x", &l);
4494 else
4495 sscanf (exp->e_beg + 1, "%O", &l);
4496 return l;
4497 }
4498 return atol (exp->e_beg);
4499 #else
4500 char *save_in;
4501 char c_save;
4502
4503 if (!exp)
4504 {
4505 /* Can't do anything */
4506 return 0;
4507 }
4508 if (!exp->e_beg || !exp->e_end)
4509 {
4510 seg (exp) = SEG_ABSOLUTE;
4511 adds (exp) = 0;
4512 subs (exp) = 0;
4513 offs (exp) = (ok == 10) ? 1 : 0;
4514 as_warn ("Null expression defaults to %ld", offs (exp));
4515 return 0;
4516 }
4517
4518 exp->e_siz = 0;
4519 if ( /* ok!=80 && */ (exp->e_end[-1] == ':' || exp->e_end[-1] == '.')
4520 && (exp->e_end - exp->e_beg) >= 2)
4521 {
4522 switch (exp->e_end[0])
4523 {
4524 case 's':
4525 case 'S':
4526 case 'b':
4527 case 'B':
4528 exp->e_siz = 1;
4529 exp->e_end -= 2;
4530 break;
4531 case 'w':
4532 case 'W':
4533 exp->e_siz = 2;
4534 exp->e_end -= 2;
4535 break;
4536 case 'l':
4537 case 'L':
4538 exp->e_siz = 3;
4539 exp->e_end -= 2;
4540 break;
4541 default:
4542 if (exp->e_end[-1] == ':')
4543 as_bad ("Unknown size for expression \"%c\"", exp->e_end[0]);
4544 break;
4545 }
4546 }
4547 c_save = exp->e_end[1];
4548 exp->e_end[1] = '\0';
4549 save_in = input_line_pointer;
4550 input_line_pointer = exp->e_beg;
4551 switch (expression (&(exp->e_exp)))
4552 {
4553 case SEG_PASS1:
4554 seg (exp) = SEG_ABSOLUTE;
4555 adds (exp) = 0;
4556 subs (exp) = 0;
4557 offs (exp) = (ok == 10) ? 1 : 0;
4558 as_warn ("Unknown expression: '%s' defaulting to %d", exp->e_beg, offs (exp));
4559 break;
4560
4561 case SEG_ABSENT:
4562 /* Do the same thing the VAX asm does */
4563 seg (exp) = SEG_ABSOLUTE;
4564 adds (exp) = 0;
4565 subs (exp) = 0;
4566 offs (exp) = 0;
4567 if (ok == 10)
4568 {
4569 as_warn ("expression out of range: defaulting to 1");
4570 offs (exp) = 1;
4571 }
4572 break;
4573 case SEG_ABSOLUTE:
4574 switch (ok)
4575 {
4576 case 10:
4577 if (offs (exp) < 1 || offs (exp) > 8)
4578 {
4579 as_warn ("expression out of range: defaulting to 1");
4580 offs (exp) = 1;
4581 }
4582 break;
4583 case 20:
4584 if (offs (exp) < 0 || offs (exp) > 7)
4585 goto outrange;
4586 break;
4587 case 30:
4588 if (offs (exp) < 0 || offs (exp) > 15)
4589 goto outrange;
4590 break;
4591 case 40:
4592 if (offs (exp) < 0 || offs (exp) > 32)
4593 goto outrange;
4594 break;
4595 case 50:
4596 if (offs (exp) < 0 || offs (exp) > 127)
4597 goto outrange;
4598 break;
4599 case 55:
4600 if (offs (exp) < -64 || offs (exp) > 63)
4601 goto outrange;
4602 break;
4603 case 60:
4604 if (offs (exp) < -128 || offs (exp) > 127)
4605 goto outrange;
4606 break;
4607 case 70:
4608 if (offs (exp) < 0 || offs (exp) > 4095)
4609 {
4610 outrange:
4611 as_warn ("expression out of range: defaulting to 0");
4612 offs (exp) = 0;
4613 }
4614 break;
4615 default:
4616 break;
4617 }
4618 break;
4619 case SEG_BIG:
4620 if (offs (exp) < 0 /* flonum */
4621 && (ok == 80 /* no bignums */
4622 || (ok > 10 /* small-int ranges including 0 ok */
4623 /* If we have a flonum zero, a zero integer should
4624 do as well (e.g., in moveq). */
4625 && generic_floating_point_number.exponent == 0
4626 && generic_floating_point_number.low[0] == 0)))
4627 {
4628 /* HACK! Turn it into a long */
4629 LITTLENUM_TYPE words[6];
4630
4631 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4632 seg (exp) = SEG_ABSOLUTE;
4633 adds (exp) = 0;
4634 subs (exp) = 0;
4635 offs (exp) = words[1] | (words[0] << 16);
4636 }
4637 else if (ok != 0)
4638 {
4639 seg (exp) = SEG_ABSOLUTE;
4640 adds (exp) = 0;
4641 subs (exp) = 0;
4642 offs (exp) = (ok == 10) ? 1 : 0;
4643 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4644 }
4645 break;
4646 default:
4647 case SEG_TEXT:
4648 case SEG_DATA:
4649 case SEG_BSS:
4650 case SEG_UNKNOWN:
4651 case SEG_DIFFERENCE:
4652 if (ok >= 10 && ok <= 70)
4653 {
4654 seg (exp) = SEG_ABSOLUTE;
4655 adds (exp) = 0;
4656 subs (exp) = 0;
4657 offs (exp) = (ok == 10) ? 1 : 0;
4658 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4659 }
4660 break;
4661
4662
4663 }
4664 if (input_line_pointer != exp->e_end + 1)
4665 as_bad ("Ignoring junk after expression");
4666 exp->e_end[1] = c_save;
4667 input_line_pointer = save_in;
4668 if (exp->e_siz)
4669 {
4670 switch (exp->e_siz)
4671 {
4672 case 1:
4673 if (!isbyte (offs (exp)))
4674 as_warn ("expression doesn't fit in BYTE");
4675 break;
4676 case 2:
4677 if (!isword (offs (exp)))
4678 as_warn ("expression doesn't fit in WORD");
4679 break;
4680 }
4681 }
4682 return offs (exp);
4683 #endif
4684 } /* get_num() */
4685
4686 /* These are the back-ends for the various machine dependent pseudo-ops. */
4687 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4688
4689 static void
4690 s_data1 ()
4691 {
4692 subseg_new (SEG_DATA, 1);
4693 demand_empty_rest_of_line ();
4694 } /* s_data1() */
4695
4696 static void
4697 s_data2 ()
4698 {
4699 subseg_new (SEG_DATA, 2);
4700 demand_empty_rest_of_line ();
4701 } /* s_data2() */
4702
4703 static void
4704 s_bss ()
4705 {
4706 /* We don't support putting frags in the BSS segment, we fake it
4707 by marking in_bss, then looking at s_skip for clues */
4708
4709 subseg_new (SEG_BSS, 0);
4710 demand_empty_rest_of_line ();
4711 } /* s_bss() */
4712
4713 static void
4714 s_even ()
4715 {
4716 register int temp;
4717 register long temp_fill;
4718
4719 temp = 1; /* JF should be 2? */
4720 temp_fill = get_absolute_expression ();
4721 if (!need_pass_2) /* Never make frag if expect extra pass. */
4722 frag_align (temp, (int) temp_fill);
4723 demand_empty_rest_of_line ();
4724 } /* s_even() */
4725
4726 static void
4727 s_proc ()
4728 {
4729 demand_empty_rest_of_line ();
4730 } /* s_proc() */
4731
4732 /* s_space is defined in read.c .skip is simply an alias to it. */
4733
4734 /*
4735 * md_parse_option
4736 * Invocation line includes a switch not recognized by the base assembler.
4737 * See if it's a processor-specific option. These are:
4738 *
4739 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4740 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4741 * Select the architecture. Instructions or features not
4742 * supported by the selected architecture cause fatal
4743 * errors. More than one may be specified. The default is
4744 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4745 * for -m68000, and -m68882 is a synonym for -m68881.
4746 * -[A]m[c]no-68851, -[A]m[c]no-68881
4747 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4748 * so don't use or document it, but that's the way the parsing
4749 * works).
4750 *
4751 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4752 * (e.g. m68020) also requests that float instructions be included. This
4753 * is the default setup, mostly to avoid hassling users. A better
4754 * rearrangement of this structure would be to add an option to DENY
4755 * floating point opcodes, for people who want to really know there's none
4756 * of that funny floaty stuff going on. FIXME-later.
4757 */
4758 #ifndef MAYBE_FLOAT_TOO
4759 #define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */
4760 #endif
4761
4762 int
4763 md_parse_option (argP, cntP, vecP)
4764 char **argP;
4765 int *cntP;
4766 char ***vecP;
4767 {
4768 switch (**argP)
4769 {
4770 case 'l': /* -l means keep external to 2 bit offset
4771 rather than 16 bit one */
4772 break;
4773
4774 case 'S': /* -S means that jbsr's always turn into jsr's. */
4775 break;
4776
4777 case 'A':
4778 (*argP)++;
4779 /* intentional fall-through */
4780 case 'm':
4781 (*argP)++;
4782
4783 if (**argP == 'c')
4784 {
4785 (*argP)++;
4786 } /* allow an optional "c" */
4787
4788 if (!strcmp (*argP, "68000")
4789 || !strcmp (*argP, "68008"))
4790 {
4791 current_architecture |= m68000;
4792 }
4793 else if (!strcmp (*argP, "68010"))
4794 {
4795 #ifdef TE_SUN
4796 omagic = 1 << 16 | OMAGIC;
4797 #endif
4798 current_architecture |= m68010;
4799 }
4800 else if (!strcmp (*argP, "68020"))
4801 {
4802 current_architecture |= m68020 | MAYBE_FLOAT_TOO;
4803 }
4804 else if (!strcmp (*argP, "68030"))
4805 {
4806 current_architecture |= m68030 | MAYBE_FLOAT_TOO;
4807 }
4808 else if (!strcmp (*argP, "68040"))
4809 {
4810 current_architecture |= m68040 | MAYBE_FLOAT_TOO;
4811 #ifndef NO_68881
4812 }
4813 else if (!strcmp (*argP, "68881"))
4814 {
4815 current_architecture |= m68881;
4816 }
4817 else if (!strcmp (*argP, "68882"))
4818 {
4819 current_architecture |= m68882;
4820 #endif /* NO_68881 */
4821 /* Even if we aren't configured to support the processor,
4822 it should still be possible to assert that the user
4823 doesn't have it... */
4824 }
4825 else if (!strcmp (*argP, "no-68881")
4826 || !strcmp (*argP, "no-68882"))
4827 {
4828 no_68881 = 1;
4829 #ifndef NO_68851
4830 }
4831 else if (!strcmp (*argP, "68851"))
4832 {
4833 current_architecture |= m68851;
4834 #endif /* NO_68851 */
4835 }
4836 else if (!strcmp (*argP, "no-68851"))
4837 {
4838 no_68851 = 1;
4839 }
4840 else if (!strcmp (*argP, "pu32"))
4841 { /* "-mcpu32" */
4842 current_architecture |= cpu32;
4843 }
4844 else
4845 {
4846 as_warn ("Unknown architecture, \"%s\". option ignored", *argP);
4847 } /* switch on architecture */
4848
4849 while (**argP)
4850 (*argP)++;
4851
4852 break;
4853
4854 case 'p':
4855 if (!strcmp (*argP, "pic"))
4856 {
4857 (*argP) += 3;
4858 break; /* -pic, Position Independent Code */
4859 }
4860 else
4861 {
4862 return (0);
4863 } /* pic or not */
4864
4865 default:
4866 return 0;
4867 }
4868 return 1;
4869 }
4870
4871
4872 #ifdef TEST2
4873
4874 /* TEST2: Test md_assemble() */
4875 /* Warning, this routine probably doesn't work anymore */
4876
4877 main ()
4878 {
4879 struct m68k_it the_ins;
4880 char buf[120];
4881 char *cp;
4882 int n;
4883
4884 m68k_ip_begin ();
4885 for (;;)
4886 {
4887 if (!gets (buf) || !*buf)
4888 break;
4889 if (buf[0] == '|' || buf[1] == '.')
4890 continue;
4891 for (cp = buf; *cp; cp++)
4892 if (*cp == '\t')
4893 *cp = ' ';
4894 if (is_label (buf))
4895 continue;
4896 memset (&the_ins, '\0', sizeof (the_ins));
4897 m68k_ip (&the_ins, buf);
4898 if (the_ins.error)
4899 {
4900 printf ("Error %s in %s\n", the_ins.error, buf);
4901 }
4902 else
4903 {
4904 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
4905 for (n = 0; n < the_ins.numo; n++)
4906 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
4907 printf (" ");
4908 print_the_insn (&the_ins.opcode[0], stdout);
4909 (void) putchar ('\n');
4910 }
4911 for (n = 0; n < strlen (the_ins.args) / 2; n++)
4912 {
4913 if (the_ins.operands[n].error)
4914 {
4915 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
4916 continue;
4917 }
4918 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
4919 if (the_ins.operands[n].b_const)
4920 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
4921 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
4922 if (the_ins.operands[n].b_iadd)
4923 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
4924 (void) putchar ('\n');
4925 }
4926 }
4927 m68k_ip_end ();
4928 return 0;
4929 }
4930
4931 is_label (str)
4932 char *str;
4933 {
4934 while (*str == ' ')
4935 str++;
4936 while (*str && *str != ' ')
4937 str++;
4938 if (str[-1] == ':' || str[1] == '=')
4939 return 1;
4940 return 0;
4941 }
4942
4943 #endif
4944
4945 /* Possible states for relaxation:
4946
4947 0 0 branch offset byte (bra, etc)
4948 0 1 word
4949 0 2 long
4950
4951 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4952 1 1 word
4953 1 2 long
4954
4955 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4956 2 1 word-long
4957 2 2 long-word
4958 2 3 long-long
4959
4960 */
4961
4962 /* We have no need to default values of symbols. */
4963
4964 /* ARGSUSED */
4965 symbolS *
4966 md_undefined_symbol (name)
4967 char *name;
4968 {
4969 return 0;
4970 }
4971
4972 /* Parse an operand that is machine-specific.
4973 We just return without modifying the expression if we have nothing
4974 to do. */
4975
4976 /* ARGSUSED */
4977 void
4978 md_operand (expressionP)
4979 expressionS *expressionP;
4980 {
4981 }
4982
4983 /* Round up a section size to the appropriate boundary. */
4984 long
4985 md_section_align (segment, size)
4986 segT segment;
4987 long size;
4988 {
4989 return size; /* Byte alignment is fine */
4990 }
4991
4992 /* Exactly what point is a PC-relative offset relative TO?
4993 On the 68k, they're relative to the address of the offset, plus
4994 its size. (??? Is this right? FIXME-SOON!) */
4995 long
4996 md_pcrel_from (fixP)
4997 fixS *fixP;
4998 {
4999 return (fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address);
5000 }
5001
5002 void
5003 tc_coff_symbol_emit_hook ()
5004 {
5005 }
5006
5007 int
5008 tc_coff_sizemachdep (frag)
5009 fragS *frag;
5010 {
5011 switch (frag->fr_subtype & 0x3)
5012 {
5013 case BYTE:
5014 return 1;
5015 case SHORT:
5016 return 2;
5017 case LONG:
5018 return 4;
5019 default:
5020 abort ();
5021 }
5022
5023 }
5024
5025 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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