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Mon Aug 24 12:45:12 1992 Ian Lance Taylor (ian@cygnus.com)
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
2 slow to compile, easy to find file.
3
4 Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21
22 #include <ctype.h>
23 #define NO_RELOC 0
24 #include "as.h"
25
26 #include "obstack.h"
27
28 /* note that this file includes real declarations and thus can only be included by one source file per executable. */
29 #include "opcode/m68k.h"
30 #ifdef TE_SUN
31 /* This variable contains the value to write out at the beginning of
32 the a.out file. The 2<<16 means that this is a 68020 file instead
33 of an old-style 68000 file */
34
35 long omagic = 2<<16|OMAGIC; /* Magic byte for header file */
36 #else
37 long omagic = OMAGIC;
38 #endif
39
40 /* This array holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful */
42 const char comment_chars[] = "|";
43
44 /* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47 /* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
49 #NO_APP at the beginning of its output. */
50 /* Also note that comments like this one will always work. */
51 const char line_comment_chars[] = "#";
52
53 /* Chars that can be used to separate mant from exp in floating point nums */
54 const char EXP_CHARS[] = "eE";
55
56 /* Chars that mean this number is a floating point constant */
57 /* As in 0f12.456 */
58 /* or 0d1.2345e12 */
59
60 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
61
62 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
63 changed in read.c . Ideally it shouldn't have to know about it at all,
64 but nothing is ideal around here.
65 */
66
67 int md_reloc_size = 8; /* Size of relocation record */
68
69 /* Its an arbitrary name: This means I don't approve of it */
70 /* See flames below */
71 static struct obstack robyn;
72
73 #define TAB(x,y) (((x)<<2)+(y))
74 #define TABTYPE(xy) ((xy) >> 2)
75 #define BYTE 0
76 #define SHORT 1
77 #define LONG 2
78 #define SZ_UNDEF 3
79
80 #define BRANCH 1
81 #define FBRANCH 2
82 #define PCREL 3
83 #define BCC68000 4
84 #define DBCC 5
85 #define PCLEA 6
86
87 /* Operands we can parse: (And associated modes)
88
89 numb: 8 bit num
90 numw: 16 bit num
91 numl: 32 bit num
92 dreg: data reg 0-7
93 reg: address or data register
94 areg: address register
95 apc: address register, PC, ZPC or empty string
96 num: 16 or 32 bit num
97 num2: like num
98 sz: w or l if omitted, l assumed
99 scale: 1 2 4 or 8 if omitted, 1 assumed
100
101 7.4 IMMED #num --> NUM
102 0.? DREG dreg --> dreg
103 1.? AREG areg --> areg
104 2.? AINDR areg@ --> *(areg)
105 3.? AINC areg@+ --> *(areg++)
106 4.? ADEC areg@- --> *(--areg)
107 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
108 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
109 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
110 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
111 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
112 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
113 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
114 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
115 7.0 ABSL num:sz --> *(num)
116 num --> *(num) (sz L assumed)
117 *** MSCR otherreg --> Magic
118 With -l option
119 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
120 ?.? DINDR dreg@ --> (dreg) -- cas2 only
121
122 examples:
123 #foo #0x35 #12
124 d2
125 a4
126 a3@
127 a5@+
128 a6@-
129 a2@(12) pc@(14)
130 a1@(5,d2:w:1) @(45,d6:l:4)
131 pc@(a2) @(d4)
132 etc . . .
133
134
135 #name@(numw) -->turn into PC rel mode
136 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
137
138 */
139
140 enum operand_type {
141 IMMED = 1,
142 DREG,
143 AREG,
144 AINDR,
145 ADEC,
146 AINC,
147 AOFF,
148 AINDX,
149 APODX,
150 AMIND,
151 APRDX,
152 ABSL,
153 MSCR,
154 REGLST,
155 DINDR
156 };
157
158
159 struct m68k_exp {
160 char *e_beg;
161 char *e_end;
162 expressionS e_exp;
163 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
164 };
165
166 /* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
167 8-15==addr reg for operands that take both types */
168
169 enum _register {
170 DATA = 1, /* 1- 8 == data registers 0-7 */
171 DATA0 = DATA,
172 DATA1,
173 DATA2,
174 DATA3,
175 DATA4,
176 DATA5,
177 DATA6,
178 DATA7,
179
180 ADDR,
181 ADDR0 = ADDR,
182 ADDR1,
183 ADDR2,
184 ADDR3,
185 ADDR4,
186 ADDR5,
187 ADDR6,
188 ADDR7,
189
190 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
191 /* I think. . . */
192
193 SP = ADDR7,
194
195 FPREG, /* Eight FP registers */
196 FP0 = FPREG,
197 FP1,
198 FP2,
199 FP3,
200 FP4,
201 FP5,
202 FP6,
203 FP7,
204 COPNUM = (FPREG+8), /* Co-processor #1-#8 */
205 COP0 = COPNUM,
206 COP1,
207 COP2,
208 COP3,
209 COP4,
210 COP5,
211 COP6,
212 COP7,
213 PC, /* Program counter */
214 ZPC, /* Hack for Program space, but 0 addressing */
215 SR, /* Status Reg */
216 CCR, /* Condition code Reg */
217
218 /* These have to be in order for the movec instruction to work. */
219 USP, /* User Stack Pointer */
220 ISP, /* Interrupt stack pointer */
221 SFC,
222 DFC,
223 CACR,
224 VBR,
225 CAAR,
226 MSP,
227 ITT0,
228 ITT1,
229 DTT0,
230 DTT1,
231 MMUSR,
232 TC,
233 SRP,
234 URP,
235 /* end of movec ordering constraints */
236
237 FPI,
238 FPS,
239 FPC,
240
241 DRP,
242 CRP,
243 CAL,
244 VAL,
245 SCC,
246 AC,
247 BAD,
248 BAD0 = BAD,
249 BAD1,
250 BAD2,
251 BAD3,
252 BAD4,
253 BAD5,
254 BAD6,
255 BAD7,
256 BAC,
257 BAC0 = BAC,
258 BAC1,
259 BAC2,
260 BAC3,
261 BAC4,
262 BAC5,
263 BAC6,
264 BAC7,
265 PSR,
266 PCSR,
267
268 IC, /* instruction cache token */
269 DC, /* data cache token */
270 NC, /* no cache token */
271 BC, /* both caches token */
272
273 };
274
275 /* Internal form of an operand. */
276 struct m68k_op {
277 char *error; /* Couldn't parse it */
278 enum operand_type mode; /* What mode this instruction is in. */
279 enum _register reg; /* Base register */
280 struct m68k_exp *con1;
281 int ireg; /* Index register */
282 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
283 int imul; /* Multipy ireg by this (1,2,4,or 8) */
284 struct m68k_exp *con2;
285 };
286
287 /* internal form of a 68020 instruction */
288 struct m68k_it {
289 char *error;
290 char *args; /* list of opcode info */
291 int numargs;
292
293 int numo; /* Number of shorts in opcode */
294 short opcode[11];
295
296 struct m68k_op operands[6];
297
298 int nexp; /* number of exprs in use */
299 struct m68k_exp exprs[4];
300
301 int nfrag; /* Number of frags we have to produce */
302 struct {
303 int fragoff; /* Where in the current opcode[] the frag ends */
304 symbolS *fadd;
305 long foff;
306 int fragty;
307 } fragb[4];
308
309 int nrel; /* Num of reloc strucs in use */
310 struct {
311 int n;
312 symbolS *add,
313 *sub;
314 long off;
315 char wid;
316 char pcrel;
317 } reloc[5]; /* Five is enough??? */
318 };
319
320 #define cpu_of_arch(x) ((x) & m68000up)
321 #define float_of_arch(x) ((x) & mfloat)
322 #define mmu_of_arch(x) ((x) & mmmu)
323
324 static struct m68k_it the_ins; /* the instruction being assembled */
325
326 /* Macros for adding things to the m68k_it struct */
327
328 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
329
330 /* Like addword, but goes BEFORE general operands */
331 #define insop(w) {int z;\
332 for(z=the_ins.numo;z>opcode->m_codenum;--z)\
333 the_ins.opcode[z]=the_ins.opcode[z-1];\
334 for(z=0;z<the_ins.nrel;z++)\
335 the_ins.reloc[z].n+=2;\
336 the_ins.opcode[opcode->m_codenum]=w;\
337 the_ins.numo++;\
338 }
339
340
341 #define add_exp(beg,end) (\
342 the_ins.exprs[the_ins.nexp].e_beg=beg,\
343 the_ins.exprs[the_ins.nexp].e_end=end,\
344 &the_ins.exprs[the_ins.nexp++]\
345 )
346
347
348 /* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/
349 #define add_fix(width,exp,pc_rel) {\
350 the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \
351 (((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\
352 the_ins.reloc[the_ins.nrel].add=adds((exp));\
353 the_ins.reloc[the_ins.nrel].sub=subs((exp));\
354 the_ins.reloc[the_ins.nrel].off=offs((exp));\
355 the_ins.reloc[the_ins.nrel].wid=width;\
356 the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\
357 }
358
359 #define add_frag(add,off,type) {\
360 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\
361 the_ins.fragb[the_ins.nfrag].fadd=add;\
362 the_ins.fragb[the_ins.nfrag].foff=off;\
363 the_ins.fragb[the_ins.nfrag++].fragty=type;\
364 }
365
366 #define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
367
368 #define seg(exp) ((exp)->e_exp.X_seg)
369 #define adds(exp) ((exp)->e_exp.X_add_symbol)
370 #define subs(exp) ((exp)->e_exp.X_subtract_symbol)
371 #define offs(exp) ((exp)->e_exp.X_add_number)
372
373
374 struct m68k_incant {
375 char *m_operands;
376 unsigned long m_opcode;
377 short m_opnum;
378 short m_codenum;
379 enum m68k_architecture m_arch;
380 struct m68k_incant *m_next;
381 };
382
383 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
384 #define gettwo(x) (((x)->m_opcode)&0xffff)
385
386
387 #if __STDC__ == 1
388
389 static char *crack_operand(char *str, struct m68k_op *opP);
390 static int get_num(struct m68k_exp *exp, int ok);
391 static int get_regs(int i, char *str, struct m68k_op *opP);
392 static int reverse_16_bits(int in);
393 static int reverse_8_bits(int in);
394 static int try_index(char **s, struct m68k_op *opP);
395 static void install_gen_operand(int mode, int val);
396 static void install_operand(int mode, int val);
397 void s_bss(void);
398 static void s_data1(void);
399 static void s_data2(void);
400 static void s_even(void);
401 static void s_proc(void);
402
403 #else /* not __STDC__ */
404
405 static char *crack_operand();
406 static int get_num();
407 static int get_regs();
408 static int reverse_16_bits();
409 static int reverse_8_bits();
410 static int try_index();
411 static void install_gen_operand();
412 static void install_operand();
413 void s_bss();
414 void s_align_bytes();
415 static void s_data1();
416 static void s_data2();
417 static void s_even();
418 static void s_proc();
419
420 #endif /* not __STDC__ */
421
422 static enum m68k_architecture current_architecture = 0;
423
424 /* BCC68000 is for patching in an extra jmp instruction for long offsets
425 on the 68000. The 68000 doesn't support long branches with branchs */
426
427 /* This table desribes how you change sizes for the various types of variable
428 size expressions. This version only supports two kinds. */
429
430 /* Note that calls to frag_var need to specify the maximum expansion needed */
431 /* This is currently 10 bytes for DBCC */
432
433 /* The fields are:
434 How far Forward this mode will reach:
435 How far Backward this mode will reach:
436 How many bytes this mode will add to the size of the frag
437 Which mode to go to if the offset won't fit in this one
438 */
439 const relax_typeS
440 md_relax_table[] = {
441 { 1, 1, 0, 0 }, /* First entries aren't used */
442 { 1, 1, 0, 0 }, /* For no good reason except */
443 { 1, 1, 0, 0 }, /* that the VAX doesn't either */
444 { 1, 1, 0, 0 },
445
446 { (127), (-128), 0, TAB(BRANCH,SHORT)},
447 { (32767), (-32768), 2, TAB(BRANCH,LONG) },
448 { 0, 0, 4, 0 },
449 { 1, 1, 0, 0 },
450
451 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
452 { (32767), (-32768), 2, TAB(FBRANCH,LONG)},
453 { 0, 0, 4, 0 },
454 { 1, 1, 0, 0 },
455
456 { 1, 1, 0, 0 }, /* PCREL doesn't come BYTE */
457 { (32767), (-32768), 2, TAB(PCREL,LONG)},
458 { 0, 0, 4, 0 },
459 { 1, 1, 0, 0 },
460
461 { (127), (-128), 0, TAB(BCC68000,SHORT)},
462 { (32767), (-32768), 2, TAB(BCC68000,LONG) },
463 { 0, 0, 6, 0 }, /* jmp long space */
464 { 1, 1, 0, 0 },
465
466 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
467 { (32767), (-32768), 2, TAB(DBCC,LONG) },
468 { 0, 0, 10, 0 }, /* bra/jmp long space */
469 { 1, 1, 0, 0 },
470
471 { 1, 1, 0, 0 }, /* PCLEA doesn't come BYTE */
472 { 32767, -32768, 2, TAB(PCLEA,LONG) },
473 { 0, 0, 6, 0 },
474 { 1, 1, 0, 0 },
475
476 };
477
478 /* These are the machine dependent pseudo-ops. These are included so
479 the assembler can work on the output from the SUN C compiler, which
480 generates these.
481 */
482
483 /* This table describes all the machine specific pseudo-ops the assembler
484 has to support. The fields are:
485 pseudo-op name without dot
486 function to call to execute this pseudo-op
487 Integer arg to pass to the function
488 */
489 const pseudo_typeS md_pseudo_table[] = {
490 { "data1", s_data1, 0 },
491 { "data2", s_data2, 0 },
492 { "bss", s_bss, 0 },
493 { "even", s_even, 0 },
494 { "skip", s_space, 0 },
495 { "proc", s_proc, 0 },
496 #ifdef TE_SUN3
497 { "align", s_align_bytes, 0 },
498 #endif
499 { 0, 0, 0 }
500 };
501
502
503 /* #define isbyte(x) ((x)>=-128 && (x)<=127) */
504 /* #define isword(x) ((x)>=-32768 && (x)<=32767) */
505
506 #define issbyte(x) ((x)>=-128 && (x)<=127)
507 #define isubyte(x) ((x)>=0 && (x)<=255)
508 #define issword(x) ((x)>=-32768 && (x)<=32767)
509 #define isuword(x) ((x)>=0 && (x)<=65535)
510
511 #define isbyte(x) ((x)>=-128 && (x)<=255)
512 #define isword(x) ((x)>=-32768 && (x)<=65535)
513 #define islong(x) (1)
514
515 extern char *input_line_pointer;
516
517 enum {
518 FAIL = 0,
519 OK = 1,
520 };
521
522 /* JF these tables here are for speed at the expense of size */
523 /* You can replace them with the #if 0 versions if you really
524 need space and don't mind it running a bit slower */
525
526 static char mklower_table[256];
527 #define mklower(c) (mklower_table[(unsigned char)(c)])
528 static char notend_table[256];
529 static char alt_notend_table[256];
530 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
531 alt_notend_table[(unsigned char)(s[1])])))
532
533 #if 0
534 #define mklower(c) (isupper(c) ? tolower(c) : c)
535 #endif
536
537
538 /* JF modified this to handle cases where the first part of a symbol name
539 looks like a register */
540
541 /*
542 * m68k_reg_parse() := if it looks like a register, return it's token &
543 * advance the pointer.
544 */
545
546 enum _register m68k_reg_parse(ccp)
547 register char **ccp;
548 {
549 char *start = *ccp;
550
551 if (isalpha(*start) && is_name_beginner(*start))
552 {
553 char c;
554 char *p = start;
555 symbolS *symbolP;
556
557 while (is_part_of_name(c = *p++))
558 ;
559 * -- p = 0;
560 symbolP = symbol_find(start);
561 *p = c;
562
563 if (symbolP && S_GET_SEGMENT(symbolP) == SEG_REGISTER)
564 {
565 *ccp = p;
566 return S_GET_VALUE(symbolP);
567 }
568 }
569 return FAIL;
570
571
572 }
573
574 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
575
576 /*
577 * m68k_ip_op := '#' + <anything>
578 * | <register> + range_sep + get_regs
579 * ;
580 *
581 * range_sep := '/' | '-' ;
582 *
583 * SKIP_WHITE := <empty> | ' ' ;
584 *
585 */
586
587 int
588 m68k_ip_op(str,opP)
589 char *str;
590 register struct m68k_op *opP;
591 {
592 char *strend;
593 long i;
594 char *parse_index();
595 int needp;
596 if (*str==' ') {
597 str++;
598 } /* Find the beginning of the string */
599
600 if(!*str) {
601 opP->error="Missing operand";
602 return FAIL;
603 } /* Out of gas */
604
605 for(strend = str; *strend; strend++) ;;
606
607 --strend;
608
609 if(*str=='#') {
610 str++;
611 opP->con1=add_exp(str,strend);
612 opP->mode=IMMED;
613 return OK;
614 } /* Guess what: A constant. Shar and enjoy */
615
616 i = m68k_reg_parse(&str);
617
618 /* is a register, is exactly a register, and is followed by '@' */
619
620 if((i==FAIL || *str!='\0') && *str!='@') {
621 char *stmp;
622
623 if(i!=FAIL && (*str=='/' || *str=='-')) {
624 opP->mode=REGLST;
625 return(get_regs(i,str,opP));
626 }
627 if ((stmp=strchr(str,'@')) != '\0') {
628 opP->con1=add_exp(str,stmp-1);
629 if(stmp==strend) {
630 opP->mode=AINDX;
631 return(OK);
632 }
633
634 if ((current_architecture & m68020up) == 0) {
635 return(FAIL);
636 } /* if target is not a '20 or better */
637
638 stmp++;
639 if(*stmp++!='(' || *strend--!=')') {
640 opP->error="Malformed operand";
641 return(FAIL);
642 }
643 i=try_index(&stmp,opP);
644 opP->con2=add_exp(stmp,strend);
645
646 if (i == FAIL) {
647 opP->mode=AMIND;
648 } else {
649 opP->mode=APODX;
650 }
651 return(OK);
652 } /* if there's an '@' */
653 opP->mode = ABSL;
654 opP->con1 = add_exp(str,strend);
655 return(OK);
656 } /* not a register, not exactly a register, or no '@' */
657
658 opP->reg=i;
659
660 if (*str=='\0') {
661 if(i>=DATA+0 && i<=DATA+7)
662 opP->mode=DREG;
663 else if(i>=ADDR+0 && i<=ADDR+7)
664 opP->mode=AREG;
665 else
666 opP->mode=MSCR;
667 return OK;
668 }
669
670 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
671 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL
672 && (str[1] != '\0' || i<DATA+0 || i>DATA+7)) {
673 opP->error="Invalid indirect register";
674 return FAIL;
675 }
676 know(*str == '@');
677
678 str++;
679 switch(*str) {
680 case '\0':
681 if (i < DATA + 0 || i > DATA + 7)
682 opP->mode=AINDR;
683 else
684 opP->mode=DINDR;
685 return OK;
686 case '-':
687 opP->mode=ADEC;
688 return OK;
689 case '+':
690 opP->mode=AINC;
691 return OK;
692 case '(':
693 str++;
694 break;
695 default:
696 opP->error="Junk after indirect";
697 return FAIL;
698 }
699 /* Some kind of indexing involved. Lets find out how bad it is */
700 i=try_index(&str,opP);
701 /* Didn't start with an index reg, maybe its offset or offset,reg */
702 if(i==FAIL) {
703 char *beg_str;
704
705 beg_str=str;
706 for(i=1;i;) {
707 switch(*str++) {
708 case '\0':
709 opP->error="Missing )";
710 return FAIL;
711 case ',': i=0; break;
712 case '(': i++; break;
713 case ')': --i; break;
714 }
715 }
716 /* if(str[-3]==':') {
717 int siz;
718
719 switch(str[-2]) {
720 case 'b':
721 case 'B':
722 siz=1;
723 break;
724 case 'w':
725 case 'W':
726 siz=2;
727 break;
728 case 'l':
729 case 'L':
730 siz=3;
731 break;
732 default:
733 opP->error="Specified size isn't :w or :l";
734 return FAIL;
735 }
736 opP->con1=add_exp(beg_str,str-4);
737 opP->con1->e_siz=siz;
738 } else */
739 opP->con1=add_exp(beg_str,str-2);
740 /* Should be offset,reg */
741 if(str[-1]==',') {
742 i=try_index(&str,opP);
743 if(i==FAIL) {
744 opP->error="Malformed index reg";
745 return FAIL;
746 }
747 }
748 }
749 /* We've now got offset) offset,reg) or reg) */
750
751 if (*str == '\0') {
752 /* Th-the-thats all folks */
753 if (opP->reg == FAIL) opP->mode = AINDX; /* Other form of indirect */
754 else if(opP->ireg == FAIL) opP->mode = AOFF;
755 else opP->mode = AINDX;
756 return(OK);
757 }
758 /* Next thing had better be another @ */
759 if (*str == '@') {
760 if (str[1] == '(') {
761 needp = 1;
762 str+=2;
763 }
764 else {
765 needp = 0;
766 str++;
767 }
768 }
769
770 if ((current_architecture & m68020up) == 0) {
771 return(FAIL);
772 } /* if target is not a '20 or better */
773
774
775 if(opP->ireg != FAIL) {
776 opP->mode = APRDX;
777
778 i = try_index(&str, opP);
779 if (i != FAIL) {
780 opP->error = "Two index registers! not allowed!";
781 return(FAIL);
782 }
783 } else {
784 i = try_index(&str, opP);
785 }
786
787 if (i == FAIL) {
788 char *beg_str;
789
790 beg_str = str;
791
792 for (i = 1; i; ) {
793 switch(*str++) {
794 case '\0':
795 if (needp)
796 opP->error="Missing )";
797 return(FAIL);
798 break;
799 case ',': i=0; break;
800 case '(': i++; break;
801 case ')': --i; break;
802 }
803 }
804
805 opP->con2=add_exp(beg_str,str-2);
806
807 if (str[-1] == ',') {
808 if (opP->ireg != FAIL) {
809 opP->error = "Can't have two index regs";
810 return(FAIL);
811 }
812
813 i = try_index(&str, opP);
814
815 if (i == FAIL) {
816 opP->error = "malformed index reg";
817 return(FAIL);
818 }
819
820 opP->mode = APODX;
821 } else if (opP->ireg != FAIL) {
822 opP->mode = APRDX;
823 } else {
824 opP->mode = AMIND;
825 }
826 } else {
827 opP->mode = APODX;
828 }
829
830 if(*str!='\0') {
831 opP->error="Junk after indirect";
832 return FAIL;
833 }
834 return(OK);
835 } /* m68k_ip_op() */
836
837 /*
838 *
839 * try_index := data_or_address_register + ')' + SKIP_W
840 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
841 *
842 * multiplier := <empty>
843 * | ':' + multiplier_number
844 * ;
845 *
846 * multiplier_number := '1' | '2' | '4' | '8' ;
847 *
848 * size_spec := 'l' | 'L' | 'w' | 'W' ;
849 *
850 * SKIP_W := <empty> | ' ' ;
851 *
852 */
853
854 static int try_index(s,opP)
855 char **s;
856 struct m68k_op *opP;
857 {
858 register int i;
859 char *ss;
860 #define SKIP_W() { ss++; if (*ss==' ') ss++;}
861
862 ss= *s;
863 /* SKIP_W(); */
864 i=m68k_reg_parse(&ss);
865 if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */
866 *s=ss;
867 return FAIL;
868 }
869 opP->ireg=i;
870 /* SKIP_W(); */
871 if(*ss==')') {
872 opP->isiz=0;
873 opP->imul=1;
874 SKIP_W();
875 *s=ss;
876 return OK;
877 }
878 if(*ss!=':') {
879 opP->error="Missing : in index register";
880 *s=ss;
881 return FAIL;
882 }
883 SKIP_W();
884 switch(*ss) {
885 case 'w':
886 case 'W':
887 opP->isiz=2;
888 break;
889 case 'l':
890 case 'L':
891 opP->isiz=3;
892 break;
893 default:
894 opP->error="Index register size spec not :w or :l";
895 *s=ss;
896 return FAIL;
897 }
898 SKIP_W();
899 if(*ss==':') {
900 SKIP_W();
901 switch(*ss) {
902 case '1':
903 case '2':
904 case '4':
905 case '8':
906 if (cpu_of_arch(current_architecture) < m68020) {
907 opP->error="no index scaling in pre-68020's";
908 *s=ss;
909 return FAIL;
910 }
911 opP->imul= *ss-'0';
912 break;
913 default:
914 opP->error="index multiplier not 1, 2, 4 or 8";
915 *s=ss;
916 return FAIL;
917 }
918 SKIP_W();
919 } else opP->imul=1;
920 if(*ss!=')') {
921 opP->error="Missing )";
922 *s=ss;
923 return FAIL;
924 }
925 SKIP_W();
926 *s=ss;
927 return OK;
928 } /* try_index() */
929
930 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
931 main()
932 {
933 char buf[128];
934 struct m68k_op thark;
935
936 for(;;) {
937 if(!gets(buf))
938 break;
939 memset(&thark, '\0', sizeof(thark));
940 if(!m68k_ip_op(buf,&thark)) printf("FAIL:");
941 if(thark.error)
942 printf("op1 error %s in %s\n",thark.error,buf);
943 printf("mode %d, reg %d, ",thark.mode,thark.reg);
944 if(thark.b_const)
945 printf("Constant: '%.*s',",1+thark.e_const-thark.b_const,thark.b_const);
946 printf("ireg %d, isiz %d, imul %d ",thark.ireg,thark.isiz,thark.imul);
947 if(thark.b_iadd)
948 printf("Iadd: '%.*s'",1+thark.e_iadd-thark.b_iadd,thark.b_iadd);
949 printf("\n");
950 }
951 exit(0);
952 }
953
954 #endif
955
956
957 static struct hash_control* op_hash = NULL; /* handle of the OPCODE hash table
958 NULL means any use before m68k_ip_begin()
959 will crash */
960
961 \f
962 /*
963 * m 6 8 k _ i p ( )
964 *
965 * This converts a string into a 68k instruction.
966 * The string must be a bare single instruction in sun format
967 * with RMS-style 68020 indirects
968 * (example: )
969 *
970 * It provides some error messages: at most one fatal error message (which
971 * stops the scan) and at most one warning message for each operand.
972 * The 68k instruction is returned in exploded form, since we have no
973 * knowledge of how you parse (or evaluate) your expressions.
974 * We do however strip off and decode addressing modes and operation
975 * mnemonic.
976 *
977 * This function's value is a string. If it is not "" then an internal
978 * logic error was found: read this code to assign meaning to the string.
979 * No argument string should generate such an error string:
980 * it means a bug in our code, not in the user's text.
981 *
982 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
983 * this function.
984 */
985
986 /* JF this function no longer returns a useful value. Sorry */
987 void m68k_ip (instring)
988 char *instring;
989 {
990 register char *p;
991 register struct m68k_op *opP;
992 register struct m68k_incant *opcode;
993 register char *s;
994 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
995 int siz1, siz2;
996 char c;
997 int losing;
998 int opsfound;
999 char *crack_operand();
1000 LITTLENUM_TYPE words[6];
1001 LITTLENUM_TYPE *wordp;
1002 unsigned long ok_arch = 0;
1003
1004 if (*instring == ' ')
1005 instring++; /* skip leading whitespace */
1006
1007 /* Scan up to end of operation-code, which MUST end in end-of-string
1008 or exactly 1 space. */
1009 for (p = instring; *p != '\0'; p++)
1010 if (*p == ' ')
1011 break;
1012
1013
1014 if (p == instring) {
1015 the_ins.error = "No operator";
1016 the_ins.opcode[0] = NULL;
1017 /* the_ins.numo=1; */
1018 return;
1019 }
1020
1021 /* p now points to the end of the opcode name, probably whitespace.
1022 make sure the name is null terminated by clobbering the whitespace,
1023 look it up in the hash table, then fix it back. */
1024 c = *p;
1025 *p = '\0';
1026 opcode = (struct m68k_incant *)hash_find (op_hash, instring);
1027 *p = c;
1028
1029 if (opcode == NULL) {
1030 the_ins.error = "Unknown operator";
1031 the_ins.opcode[0] = NULL;
1032 /* the_ins.numo=1; */
1033 return;
1034 }
1035
1036 /* found a legitimate opcode, start matching operands */
1037 while (*p == ' ') ++p;
1038
1039 for(opP = &the_ins.operands[0]; *p; opP++) {
1040
1041 p = crack_operand(p, opP);
1042
1043 if (opP->error) {
1044 the_ins.error=opP->error;
1045 return;
1046 }
1047 }
1048
1049 opsfound = opP - &the_ins.operands[0];
1050
1051 /* This ugly hack is to support the floating pt opcodes in their standard form */
1052 /* Essentially, we fake a first enty of type COP#1 */
1053 if (opcode->m_operands[0]=='I') {
1054 int n;
1055
1056 for(n=opsfound;n>0;--n)
1057 the_ins.operands[n]=the_ins.operands[n-1];
1058
1059 memset((char *)(&the_ins.operands[0]), '\0', sizeof(the_ins.operands[0]));
1060 the_ins.operands[0].mode=MSCR;
1061 the_ins.operands[0].reg=COPNUM; /* COP #1 */
1062 opsfound++;
1063 }
1064
1065 /* We've got the operands. Find an opcode that'll accept them */
1066 for (losing = 0; ; ) {
1067 /* if we didn't get the right number of ops,
1068 or we have no common model with this pattern
1069 then reject this pattern. */
1070
1071 if (opsfound != opcode->m_opnum
1072 || ((opcode->m_arch & current_architecture) == 0))
1073 {
1074 ++losing;
1075 ok_arch |= opcode->m_arch;
1076 }
1077 else {
1078 for (s=opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++) {
1079 /* Warning: this switch is huge! */
1080 /* I've tried to organize the cases into this order:
1081 non-alpha first, then alpha by letter. lower-case goes directly
1082 before uppercase counterpart. */
1083 /* Code with multiple case ...: gets sorted by the lowest case ...
1084 it belongs to. I hope this makes sense. */
1085 switch(*s) {
1086 case '!':
1087 if (opP->mode == MSCR || opP->mode == IMMED
1088 || opP->mode == DREG || opP->mode == AREG
1089 || opP->mode == AINC || opP->mode == ADEC
1090 || opP->mode == REGLST)
1091 losing++;
1092 break;
1093
1094 case '#':
1095 if(opP->mode!=IMMED)
1096 losing++;
1097 else {
1098 long t;
1099
1100 t=get_num(opP->con1,80);
1101 if(s[1]=='b' && !isbyte(t))
1102 losing++;
1103 else if(s[1]=='w' && !isword(t))
1104 losing++;
1105 }
1106 break;
1107
1108 case '^':
1109 case 'T':
1110 if(opP->mode!=IMMED)
1111 losing++;
1112 break;
1113
1114 case '$':
1115 if(opP->mode==MSCR || opP->mode==AREG ||
1116 opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1117 losing++;
1118 break;
1119
1120 case '%':
1121 if(opP->mode==MSCR || opP->reg==PC ||
1122 opP->reg==ZPC || opP->mode==REGLST)
1123 losing++;
1124 break;
1125
1126
1127 case '&':
1128 if(opP->mode==MSCR || opP->mode==DREG ||
1129 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC ||
1130 opP->mode==AINC || opP->mode==ADEC || opP->mode==REGLST)
1131 losing++;
1132 break;
1133
1134 case '*':
1135 if(opP->mode==MSCR || opP->mode==REGLST)
1136 losing++;
1137 break;
1138
1139 case '+':
1140 if(opP->mode!=AINC)
1141 losing++;
1142 break;
1143
1144 case '-':
1145 if(opP->mode!=ADEC)
1146 losing++;
1147 break;
1148
1149 case '/':
1150 if(opP->mode==MSCR || opP->mode==AREG ||
1151 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->mode==REGLST)
1152 losing++;
1153 break;
1154
1155 case ';':
1156 if(opP->mode==MSCR || opP->mode==AREG || opP->mode==REGLST)
1157 losing++;
1158 break;
1159
1160 case '?':
1161 if(opP->mode==MSCR || opP->mode==AREG ||
1162 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->reg==PC ||
1163 opP->reg==ZPC || opP->mode==REGLST)
1164 losing++;
1165 break;
1166
1167 case '@':
1168 if(opP->mode==MSCR || opP->mode==AREG ||
1169 opP->mode==IMMED || opP->mode==REGLST)
1170 losing++;
1171 break;
1172
1173 case '~': /* For now! (JF FOO is this right?) */
1174 if(opP->mode==MSCR || opP->mode==DREG ||
1175 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1176 losing++;
1177 break;
1178
1179 case 'A':
1180 if(opP->mode!=AREG)
1181 losing++;
1182 break;
1183 case 'a':
1184 if (opP->mode != AINDR) {
1185 ++losing;
1186 } /* if not address register indirect */
1187 break;
1188 case 'B': /* FOO */
1189 if(opP->mode!=ABSL || (flagseen['S'] && instring[0] == 'j'
1190 && instring[1] == 'b'
1191 && instring[2] == 's'
1192 && instring[3] == 'r'))
1193 losing++;
1194 break;
1195
1196 case 'C':
1197 if(opP->mode!=MSCR || opP->reg!=CCR)
1198 losing++;
1199 break;
1200
1201 case 'd': /* FOO This mode is a KLUDGE!! */
1202 if(opP->mode!=AOFF && (opP->mode!=ABSL ||
1203 opP->con1->e_beg[0]!='(' || opP->con1->e_end[0]!=')'))
1204 losing++;
1205 break;
1206
1207 case 'D':
1208 if(opP->mode!=DREG)
1209 losing++;
1210 break;
1211
1212 case 'F':
1213 if(opP->mode!=MSCR || opP->reg<(FPREG+0) || opP->reg>(FPREG+7))
1214 losing++;
1215 break;
1216
1217 case 'I':
1218 if(opP->mode!=MSCR || opP->reg<COPNUM ||
1219 opP->reg>=COPNUM+7)
1220 losing++;
1221 break;
1222
1223 case 'J':
1224 if (opP->mode != MSCR
1225 || opP->reg < USP
1226 || opP->reg > URP
1227 || cpu_of_arch(current_architecture) < m68010 /* before 68010 had none */
1228 || (cpu_of_arch(current_architecture) < m68020
1229 && opP->reg != SFC
1230 && opP->reg != DFC
1231 && opP->reg != USP
1232 && opP->reg != VBR) /* 68010's had only these */
1233 || (cpu_of_arch(current_architecture) < m68040
1234 && opP->reg != SFC
1235 && opP->reg != DFC
1236 && opP->reg != USP
1237 && opP->reg != VBR
1238 && opP->reg != CACR
1239 && opP->reg != CAAR
1240 && opP->reg != MSP
1241 && opP->reg != ISP) /* 680[23]0's have only these */
1242 || (cpu_of_arch(current_architecture) == m68040 /* 68040 has all but this */
1243 && opP->reg == CAAR)) {
1244 losing++;
1245 } /* doesn't cut it */
1246 break;
1247
1248 case 'k':
1249 if(opP->mode!=IMMED)
1250 losing++;
1251 break;
1252
1253 case 'l':
1254 case 'L':
1255 if(opP->mode==DREG || opP->mode==AREG || opP->mode==FPREG) {
1256 if(s[1]=='8')
1257 losing++;
1258 else {
1259 opP->mode=REGLST;
1260 opP->reg=1<<(opP->reg-DATA);
1261 }
1262 } else if(opP->mode!=REGLST) {
1263 losing++;
1264 } else if(s[1]=='8' && opP->reg&0x0FFffFF)
1265 losing++;
1266 else if(s[1]=='3' && opP->reg&0x7000000)
1267 losing++;
1268 break;
1269
1270 case 'M':
1271 if(opP->mode!=IMMED)
1272 losing++;
1273 else {
1274 long t;
1275
1276 t=get_num(opP->con1,80);
1277 if(!issbyte(t) || isvar(opP->con1))
1278 losing++;
1279 }
1280 break;
1281
1282 case 'O':
1283 if(opP->mode!=DREG && opP->mode!=IMMED)
1284 losing++;
1285 break;
1286
1287 case 'Q':
1288 if(opP->mode!=IMMED)
1289 losing++;
1290 else {
1291 long t;
1292
1293 t=get_num(opP->con1,80);
1294 if(t<1 || t>8 || isvar(opP->con1))
1295 losing++;
1296 }
1297 break;
1298
1299 case 'R':
1300 if(opP->mode!=DREG && opP->mode!=AREG)
1301 losing++;
1302 break;
1303
1304 case 'r':
1305 if (opP->mode!=AINDR && opP->mode!=DINDR)
1306 losing++;
1307 break;
1308
1309 case 's':
1310 if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC))
1311 losing++;
1312 break;
1313
1314 case 'S':
1315 if(opP->mode!=MSCR || opP->reg!=SR)
1316 losing++;
1317 break;
1318
1319 case 'U':
1320 if(opP->mode!=MSCR || opP->reg!=USP)
1321 losing++;
1322 break;
1323
1324 /* JF these are out of order. We could put them
1325 in order if we were willing to put up with
1326 bunches of #ifdef m68851s in the code */
1327 #ifndef NO_68851
1328 /* Memory addressing mode used by pflushr */
1329 case '|':
1330 if(opP->mode==MSCR || opP->mode==DREG ||
1331 opP->mode==AREG || opP->mode==REGLST)
1332 losing++;
1333 break;
1334
1335 case 'f':
1336 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
1337 losing++;
1338 break;
1339
1340 case 'P':
1341 if (opP->mode != MSCR || (opP->reg != TC && opP->reg != CAL &&
1342 opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
1343 losing++;
1344 break;
1345
1346 case 'V':
1347 if (opP->reg != VAL)
1348 losing++;
1349 break;
1350
1351 case 'W':
1352 if (opP->mode != MSCR || (opP->reg != DRP && opP->reg != SRP &&
1353 opP->reg != CRP))
1354 losing++;
1355 break;
1356
1357 case 'X':
1358 if (opP->mode != MSCR ||
1359 (!(opP->reg >= BAD && opP->reg <= BAD+7) &&
1360 !(opP->reg >= BAC && opP->reg <= BAC+7)))
1361 losing++;
1362 break;
1363
1364 case 'Y':
1365 if (opP->reg != PSR)
1366 losing++;
1367 break;
1368
1369 case 'Z':
1370 if (opP->reg != PCSR)
1371 losing++;
1372 break;
1373 #endif
1374 case 'c':
1375 if (opP->reg != NC
1376 && opP->reg != IC
1377 && opP->reg != DC
1378 && opP->reg != BC) {
1379 losing++;
1380 } /* not a cache specifier. */
1381 break;
1382
1383 case '_':
1384 if (opP->mode != ABSL) {
1385 ++losing;
1386 } /* not absolute */
1387 break;
1388
1389 default:
1390 as_fatal("Internal error: Operand mode %c unknown in line %s of file \"%s\"",
1391 *s, __LINE__, __FILE__);
1392 } /* switch on type of operand */
1393
1394 if (losing)
1395 break;
1396 } /* for each operand */
1397 } /* if immediately wrong */
1398
1399 if (!losing) {
1400 break;
1401 } /* got it. */
1402
1403 opcode = opcode->m_next;
1404
1405 if (!opcode) {
1406 if (ok_arch)
1407 {
1408 char buf[200], *cp;
1409 int len;
1410 strcpy (buf, "invalid instruction for this architecture; needs ");
1411 cp = buf + strlen (buf);
1412 switch (ok_arch)
1413 {
1414 case mfloat:
1415 strcpy (cp, "fpu");
1416 break;
1417 case mmmu:
1418 strcpy (cp, "mmu");
1419 break;
1420 case m68020up:
1421 strcpy (cp, "68020 or higher");
1422 break;
1423 case m68000up:
1424 strcpy (cp, "68000 or higher");
1425 break;
1426 case m68010up:
1427 strcpy (cp, "68010 or higher");
1428 break;
1429 default:
1430 {
1431 int got_one = 0, idx;
1432 const static struct {
1433 enum m68k_architecture arch;
1434 const char *name;
1435 } archs[] = {
1436 m68000, "68000",
1437 m68010, "68010",
1438 m68020, "68020",
1439 m68030, "68030",
1440 m68040, "68040",
1441 m68881, "68881",
1442 m68851, "68851",
1443 };
1444 for (idx = 0; idx < sizeof (archs)/sizeof (archs[0]); idx++)
1445 {
1446 if (archs[idx].arch & ok_arch)
1447 {
1448 if (got_one)
1449 {
1450 strcpy (cp, " or ");
1451 cp += strlen (cp);
1452 }
1453 got_one = 1;
1454 strcpy (cp, archs[idx].name);
1455 cp += strlen (cp);
1456 }
1457 }
1458 }
1459 }
1460 len = cp - buf + 1;
1461 cp = malloc (len);
1462 strcpy (cp, buf);
1463 the_ins.error = cp;
1464 }
1465 else
1466 the_ins.error = "operands mismatch";
1467 return;
1468 } /* Fell off the end */
1469
1470 losing = 0;
1471 }
1472
1473 /* now assemble it */
1474
1475 the_ins.args=opcode->m_operands;
1476 the_ins.numargs=opcode->m_opnum;
1477 the_ins.numo=opcode->m_codenum;
1478 the_ins.opcode[0]=getone(opcode);
1479 the_ins.opcode[1]=gettwo(opcode);
1480
1481 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) {
1482 /* This switch is a doozy.
1483 Watch the first step; its a big one! */
1484 switch(s[0]) {
1485
1486 case '*':
1487 case '~':
1488 case '%':
1489 case ';':
1490 case '@':
1491 case '!':
1492 case '&':
1493 case '$':
1494 case '?':
1495 case '/':
1496 #ifndef NO_68851
1497 case '|':
1498 #endif
1499 switch(opP->mode) {
1500 case IMMED:
1501 tmpreg=0x3c; /* 7.4 */
1502 if (strchr("bwl",s[1])) nextword=get_num(opP->con1,80);
1503 else nextword=nextword=get_num(opP->con1,0);
1504 if(isvar(opP->con1))
1505 add_fix(s[1],opP->con1,0);
1506 switch(s[1]) {
1507 case 'b':
1508 if(!isbyte(nextword))
1509 opP->error="operand out of range";
1510 addword(nextword);
1511 baseo=0;
1512 break;
1513 case 'w':
1514 if(!isword(nextword))
1515 opP->error="operand out of range";
1516 addword(nextword);
1517 baseo=0;
1518 break;
1519 case 'l':
1520 addword(nextword>>16);
1521 addword(nextword);
1522 baseo=0;
1523 break;
1524
1525 case 'f':
1526 baseo=2;
1527 outro=8;
1528 break;
1529 case 'F':
1530 baseo=4;
1531 outro=11;
1532 break;
1533 case 'x':
1534 baseo=6;
1535 outro=15;
1536 break;
1537 case 'p':
1538 baseo=6;
1539 outro= -1;
1540 break;
1541 default:
1542 as_fatal("Internal error: Can't decode %c%c in line %s of file \"%s\"",
1543 *s, s[1], __LINE__, __FILE__);
1544 }
1545 if(!baseo)
1546 break;
1547
1548 /* We gotta put out some float */
1549 if(seg(opP->con1)!=SEG_BIG) {
1550 int_to_gen(nextword);
1551 gen_to_words(words,baseo,(long int)outro);
1552 for(wordp=words;baseo--;wordp++)
1553 addword(*wordp);
1554 break;
1555 } /* Its BIG */
1556 if(offs(opP->con1)>0) {
1557 as_warn("Bignum assumed to be binary bit-pattern");
1558 if(offs(opP->con1)>baseo) {
1559 as_warn("Bignum too big for %c format; truncated",s[1]);
1560 offs(opP->con1)=baseo;
1561 }
1562 baseo-=offs(opP->con1);
1563 for(wordp=generic_bignum+offs(opP->con1)-1;offs(opP->con1)--;--wordp)
1564 addword(*wordp);
1565 while(baseo--)
1566 addword(0);
1567 break;
1568 }
1569 gen_to_words(words,baseo,(long)outro);
1570 for (wordp=words;baseo--;wordp++)
1571 addword(*wordp);
1572 break;
1573 case DREG:
1574 tmpreg=opP->reg-DATA; /* 0.dreg */
1575 break;
1576 case AREG:
1577 tmpreg=0x08+opP->reg-ADDR; /* 1.areg */
1578 break;
1579 case AINDR:
1580 tmpreg=0x10+opP->reg-ADDR; /* 2.areg */
1581 break;
1582 case ADEC:
1583 tmpreg=0x20+opP->reg-ADDR; /* 4.areg */
1584 break;
1585 case AINC:
1586 tmpreg=0x18+opP->reg-ADDR; /* 3.areg */
1587 break;
1588 case AOFF:
1589
1590 nextword=get_num(opP->con1,80);
1591 /* Force into index mode. Hope this works */
1592
1593 /* We do the first bit for 32-bit displacements,
1594 and the second bit for 16 bit ones. It is
1595 possible that we should make the default be
1596 WORD instead of LONG, but I think that'd
1597 break GCC, so we put up with a little
1598 inefficiency for the sake of working output.
1599 */
1600
1601 if( !issword(nextword)
1602 || ( isvar(opP->con1)
1603 && ( ( opP->con1->e_siz==0
1604 && flagseen['l']==0)
1605 || opP->con1->e_siz==3))) {
1606
1607 if(opP->reg==PC)
1608 tmpreg=0x3B; /* 7.3 */
1609 else
1610 tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
1611 if(isvar(opP->con1)) {
1612 if(opP->reg==PC) {
1613 add_frag(adds(opP->con1),
1614 offs(opP->con1),
1615 TAB(PCLEA,SZ_UNDEF));
1616 break;
1617 } else {
1618 addword(0x0170);
1619 add_fix('l',opP->con1,1);
1620 }
1621 } else
1622 addword(0x0170);
1623 addword(nextword>>16);
1624 } else {
1625 if(opP->reg==PC)
1626 tmpreg=0x3A; /* 7.2 */
1627 else
1628 tmpreg=0x28+opP->reg-ADDR; /* 5.areg */
1629
1630 if(isvar(opP->con1)) {
1631 if(opP->reg==PC) {
1632 add_fix('w',opP->con1,1);
1633 } else
1634 add_fix('w',opP->con1,0);
1635 }
1636 }
1637 addword(nextword);
1638 break;
1639
1640 case APODX:
1641 case AMIND:
1642 case APRDX:
1643 know(current_architecture & m68020up);
1644 /* intentional fall-through */
1645 case AINDX:
1646 nextword=0;
1647 baseo=get_num(opP->con1,80);
1648 outro=get_num(opP->con2,80);
1649 /* Figure out the 'addressing mode' */
1650 /* Also turn on the BASE_DISABLE bit, if needed */
1651 if(opP->reg==PC || opP->reg==ZPC) {
1652 tmpreg=0x3b; /* 7.3 */
1653 if(opP->reg==ZPC)
1654 nextword|=0x80;
1655 } else if(opP->reg==FAIL) {
1656 nextword|=0x80;
1657 tmpreg=0x30; /* 6.garbage */
1658 } else tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
1659
1660 siz1= (opP->con1) ? opP->con1->e_siz : 0;
1661 siz2= (opP->con2) ? opP->con2->e_siz : 0;
1662
1663 /* Index register stuff */
1664 if(opP->ireg>=DATA+0 && opP->ireg<=ADDR+7) {
1665 nextword|=(opP->ireg-DATA)<<12;
1666
1667 if(opP->isiz==0 || opP->isiz==3)
1668 nextword|=0x800;
1669 switch(opP->imul) {
1670 case 1: break;
1671 case 2: nextword|=0x200; break;
1672 case 4: nextword|=0x400; break;
1673 case 8: nextword|=0x600; break;
1674 default: as_fatal("failed sanity check.");
1675 }
1676 /* IF its simple,
1677 GET US OUT OF HERE! */
1678
1679 /* Must be INDEX, with an index
1680 register. Address register
1681 cannot be ZERO-PC, and either
1682 :b was forced, or we know
1683 it will fit */
1684 if( opP->mode==AINDX
1685 && opP->reg!=FAIL
1686 && opP->reg!=ZPC
1687 && ( siz1==1
1688 || ( issbyte(baseo)
1689 && !isvar(opP->con1)))) {
1690 nextword +=baseo&0xff;
1691 addword(nextword);
1692 if(isvar(opP->con1))
1693 add_fix('B',opP->con1,0);
1694 break;
1695 }
1696 } else
1697 nextword|=0x40; /* No index reg */
1698
1699 /* It aint simple */
1700 nextword|=0x100;
1701 /* If the guy specified a width, we assume that
1702 it is wide enough. Maybe it isn't. If so, we lose
1703 */
1704 switch(siz1) {
1705 case 0:
1706 if(isvar(opP->con1) || !issword(baseo)) {
1707 siz1=3;
1708 nextword|=0x30;
1709 } else if(baseo==0)
1710 nextword|=0x10;
1711 else {
1712 nextword|=0x20;
1713 siz1=2;
1714 }
1715 break;
1716 case 1:
1717 as_warn("Byte dispacement won't work. Defaulting to :w");
1718 case 2:
1719 nextword|=0x20;
1720 break;
1721 case 3:
1722 nextword|=0x30;
1723 break;
1724 }
1725
1726 /* Figure out innner displacement stuff */
1727 if(opP->mode!=AINDX) {
1728 switch(siz2) {
1729 case 0:
1730 if(isvar(opP->con2) || !issword(outro)) {
1731 siz2=3;
1732 nextword|=0x3;
1733 } else if(outro==0)
1734 nextword|=0x1;
1735 else {
1736 nextword|=0x2;
1737 siz2=2;
1738 }
1739 break;
1740 case 1:
1741 as_warn("Byte dispacement won't work. Defaulting to :w");
1742 case 2:
1743 nextword|=0x2;
1744 break;
1745 case 3:
1746 nextword|=0x3;
1747 break;
1748 }
1749 if(opP->mode==APODX) nextword|=0x04;
1750 else if(opP->mode==AMIND) nextword|=0x40;
1751 }
1752 addword(nextword);
1753
1754 if(isvar(opP->con1)) {
1755 if(opP->reg==PC || opP->reg==ZPC) {
1756 add_fix(siz1==3 ? 'l' : 'w',opP->con1,1);
1757 opP->con1->e_exp.X_add_number+=6;
1758 } else
1759 add_fix(siz1==3 ? 'l' : 'w',opP->con1,0);
1760 }
1761 if(siz1==3)
1762 addword(baseo>>16);
1763 if(siz1)
1764 addword(baseo);
1765
1766 if(isvar(opP->con2)) {
1767 if(opP->reg==PC || opP->reg==ZPC) {
1768 add_fix(siz2==3 ? 'l' : 'w',opP->con2,1);
1769 opP->con1->e_exp.X_add_number+=6;
1770 } else
1771 add_fix(siz2==3 ? 'l' : 'w',opP->con2,0);
1772 }
1773 if(siz2==3)
1774 addword(outro>>16);
1775 if(siz2)
1776 addword(outro);
1777
1778 break;
1779
1780 case ABSL:
1781 nextword=get_num(opP->con1,80);
1782 switch(opP->con1->e_siz) {
1783 default:
1784 as_warn("Unknown size for absolute reference");
1785 case 0:
1786 if(!isvar(opP->con1) && issword(offs(opP->con1))) {
1787 tmpreg=0x38; /* 7.0 */
1788 addword(nextword);
1789 break;
1790 }
1791 /* Don't generate pc relative code
1792 on 68010 and 68000 */
1793 if(isvar(opP->con1)
1794 && !subs(opP->con1)
1795 && seg(opP->con1) == SEG_TEXT
1796 && now_seg == SEG_TEXT
1797 && cpu_of_arch(current_architecture) >= m68020
1798 && !flagseen['S']
1799 && !strchr("~%&$?", s[0])) {
1800 tmpreg=0x3A; /* 7.2 */
1801 add_frag(adds(opP->con1),
1802 offs(opP->con1),
1803 TAB(PCREL,SZ_UNDEF));
1804 break;
1805 }
1806 case 3: /* Fall through into long */
1807 if(isvar(opP->con1))
1808 add_fix('l',opP->con1,0);
1809
1810 tmpreg=0x39; /* 7.1 mode */
1811 addword(nextword>>16);
1812 addword(nextword);
1813 break;
1814
1815 case 2: /* Word */
1816 if(isvar(opP->con1))
1817 add_fix('w',opP->con1,0);
1818
1819 tmpreg=0x38; /* 7.0 mode */
1820 addword(nextword);
1821 break;
1822 }
1823 break;
1824 case DINDR:
1825 as_bad("invalid indirect register");
1826 break;
1827 case MSCR:
1828 default:
1829 as_bad("unknown/incorrect operand");
1830 /* abort(); */
1831 }
1832 install_gen_operand(s[1],tmpreg);
1833 break;
1834
1835 case '#':
1836 case '^':
1837 switch(s[1]) { /* JF: I hate floating point! */
1838 case 'j':
1839 tmpreg=70;
1840 break;
1841 case '8':
1842 tmpreg=20;
1843 break;
1844 case 'C':
1845 tmpreg=50;
1846 break;
1847 case '3':
1848 default:
1849 tmpreg=80;
1850 break;
1851 }
1852 tmpreg=get_num(opP->con1,tmpreg);
1853 if(isvar(opP->con1))
1854 add_fix(s[1],opP->con1,0);
1855 switch(s[1]) {
1856 case 'b': /* Danger: These do no check for
1857 certain types of overflow.
1858 user beware! */
1859 if(!isbyte(tmpreg))
1860 opP->error="out of range";
1861 insop(tmpreg);
1862 if(isvar(opP->con1))
1863 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
1864 break;
1865 case 'w':
1866 if(!isword(tmpreg))
1867 opP->error="out of range";
1868 insop(tmpreg);
1869 if(isvar(opP->con1))
1870 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
1871 break;
1872 case 'l':
1873 insop(tmpreg); /* Because of the way insop works, we put these two out backwards */
1874 insop(tmpreg>>16);
1875 if(isvar(opP->con1))
1876 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
1877 break;
1878 case '3':
1879 tmpreg&=0xFF;
1880 case '8':
1881 case 'C':
1882 install_operand(s[1],tmpreg);
1883 break;
1884 default:
1885 as_fatal("Internal error: Unknown mode #%c in line %s of file \"%s\"", s[1], __LINE__, __FILE__);
1886 }
1887 break;
1888
1889 case '+':
1890 case '-':
1891 case 'A':
1892 case 'a':
1893 install_operand(s[1],opP->reg-ADDR);
1894 break;
1895
1896 case 'B':
1897 tmpreg=get_num(opP->con1,80);
1898 switch(s[1]) {
1899 case 'B':
1900 /* Needs no offsetting */
1901 add_fix('B',opP->con1,1);
1902 break;
1903 case 'W':
1904 /* Offset the displacement to be relative to byte disp location */
1905 opP->con1->e_exp.X_add_number+=2;
1906 add_fix('w',opP->con1,1);
1907 addword(0);
1908 break;
1909 case 'L':
1910 long_branch:
1911 if (cpu_of_arch(current_architecture) < m68020) /* 68000 or 010 */
1912 as_warn("Can't use long branches on 68000/68010");
1913 the_ins.opcode[the_ins.numo-1]|=0xff;
1914 /* Offset the displacement to be relative to byte disp location */
1915 opP->con1->e_exp.X_add_number+=4;
1916 add_fix('l',opP->con1,1);
1917 addword(0);
1918 addword(0);
1919 break;
1920 case 'g':
1921 if(subs(opP->con1)) /* We can't relax it */
1922 goto long_branch;
1923
1924 /* This could either be a symbol, or an
1925 absolute address. No matter, the
1926 frag hacking will finger it out.
1927 Not quite: it can't switch from
1928 BRANCH to BCC68000 for the case
1929 where opnd is absolute (it needs
1930 to use the 68000 hack since no
1931 conditional abs jumps). */
1932 if (((cpu_of_arch(current_architecture) < m68020) || (0==adds(opP->con1)))
1933 && (the_ins.opcode[0] >= 0x6200)
1934 && (the_ins.opcode[0] <= 0x6f00)) {
1935 add_frag(adds(opP->con1),offs(opP->con1),TAB(BCC68000,SZ_UNDEF));
1936 } else {
1937 add_frag(adds(opP->con1),offs(opP->con1),TAB(BRANCH,SZ_UNDEF));
1938 }
1939 break;
1940 case 'w':
1941 if(isvar(opP->con1)) {
1942 /* check for DBcc instruction */
1943 if ((the_ins.opcode[0] & 0xf0f8) ==0x50c8) {
1944 /* size varies if patch */
1945 /* needed for long form */
1946 add_frag(adds(opP->con1),offs(opP->con1),TAB(DBCC,SZ_UNDEF));
1947 break;
1948 }
1949
1950 /* Don't ask! */
1951 opP->con1->e_exp.X_add_number+=2;
1952 add_fix('w',opP->con1,1);
1953 }
1954 addword(0);
1955 break;
1956 case 'C': /* Fixed size LONG coproc branches */
1957 the_ins.opcode[the_ins.numo-1]|=0x40;
1958 /* Offset the displacement to be relative to byte disp location */
1959 /* Coproc branches don't have a byte disp option, but they are
1960 compatible with the ordinary branches, which do... */
1961 opP->con1->e_exp.X_add_number+=4;
1962 add_fix('l',opP->con1,1);
1963 addword(0);
1964 addword(0);
1965 break;
1966 case 'c': /* Var size Coprocesssor branches */
1967 if(subs(opP->con1)) {
1968 add_fix('l',opP->con1,1);
1969 add_frag((symbolS *)0,(long)0,TAB(FBRANCH,LONG));
1970 } else if(adds(opP->con1)) {
1971 add_frag(adds(opP->con1),offs(opP->con1),TAB(FBRANCH,SZ_UNDEF));
1972 } else {
1973 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
1974 the_ins.opcode[the_ins.numo-1]|=0x40;
1975 add_fix('l',opP->con1,1);
1976 addword(0);
1977 addword(4);
1978 }
1979 break;
1980 default:
1981 as_fatal("Internal error: operand type B%c unknown in line %s of file \"%s\"",
1982 s[1], __LINE__, __FILE__);
1983 }
1984 break;
1985
1986 case 'C': /* Ignore it */
1987 break;
1988
1989 case 'd': /* JF this is a kludge */
1990 if(opP->mode==AOFF) {
1991 install_operand('s',opP->reg-ADDR);
1992 } else {
1993 char *tmpP;
1994
1995 tmpP=opP->con1->e_end-2;
1996 opP->con1->e_beg++;
1997 opP->con1->e_end-=4; /* point to the , */
1998 baseo=m68k_reg_parse(&tmpP);
1999 if(baseo<ADDR+0 || baseo>ADDR+7) {
2000 as_bad("Unknown address reg, using A0");
2001 baseo=0;
2002 } else baseo-=ADDR;
2003 install_operand('s',baseo);
2004 }
2005 tmpreg=get_num(opP->con1,80);
2006 if(!issword(tmpreg)) {
2007 as_warn("Expression out of range, using 0");
2008 tmpreg=0;
2009 }
2010 addword(tmpreg);
2011 break;
2012
2013 case 'D':
2014 install_operand(s[1],opP->reg-DATA);
2015 break;
2016
2017 case 'F':
2018 install_operand(s[1],opP->reg-FPREG);
2019 break;
2020
2021 case 'I':
2022 tmpreg=1+opP->reg-COPNUM;
2023 if(tmpreg==8)
2024 tmpreg=0;
2025 install_operand(s[1],tmpreg);
2026 break;
2027
2028 case 'J': /* JF foo */
2029 switch(opP->reg) {
2030 case SFC: tmpreg=0x000; break;
2031 case DFC: tmpreg=0x001; break;
2032 case CACR: tmpreg=0x002; break;
2033 case TC: tmpreg=0x003; break;
2034 case ITT0: tmpreg=0x004; break;
2035 case ITT1: tmpreg=0x005; break;
2036 case DTT0: tmpreg=0x006; break;
2037 case DTT1: tmpreg=0x007; break;
2038
2039 case USP: tmpreg=0x800; break;
2040 case VBR: tmpreg=0x801; break;
2041 case CAAR: tmpreg=0x802; break;
2042 case MSP: tmpreg=0x803; break;
2043 case ISP: tmpreg=0x804; break;
2044 case MMUSR: tmpreg=0x805; break;
2045 case URP: tmpreg=0x806; break;
2046 case SRP: tmpreg=0x807; break;
2047 default:
2048 as_fatal("failed sanity check.");
2049 }
2050 install_operand(s[1],tmpreg);
2051 break;
2052
2053 case 'k':
2054 tmpreg=get_num(opP->con1,55);
2055 install_operand(s[1],tmpreg&0x7f);
2056 break;
2057
2058 case 'l':
2059 tmpreg=opP->reg;
2060 if(s[1]=='w') {
2061 if(tmpreg&0x7FF0000)
2062 as_bad("Floating point register in register list");
2063 insop(reverse_16_bits(tmpreg));
2064 } else {
2065 if(tmpreg&0x700FFFF)
2066 as_bad("Wrong register in floating-point reglist");
2067 install_operand(s[1],reverse_8_bits(tmpreg>>16));
2068 }
2069 break;
2070
2071 case 'L':
2072 tmpreg=opP->reg;
2073 if(s[1]=='w') {
2074 if(tmpreg&0x7FF0000)
2075 as_bad("Floating point register in register list");
2076 insop(tmpreg);
2077 } else if(s[1]=='8') {
2078 if(tmpreg&0x0FFFFFF)
2079 as_bad("incorrect register in reglist");
2080 install_operand(s[1],tmpreg>>24);
2081 } else {
2082 if(tmpreg&0x700FFFF)
2083 as_bad("wrong register in floating-point reglist");
2084 else
2085 install_operand(s[1],tmpreg>>16);
2086 }
2087 break;
2088
2089 case 'M':
2090 install_operand(s[1],get_num(opP->con1,60));
2091 break;
2092
2093 case 'O':
2094 tmpreg= (opP->mode==DREG)
2095 ? 0x20+opP->reg-DATA
2096 : (get_num(opP->con1,40)&0x1F);
2097 install_operand(s[1],tmpreg);
2098 break;
2099
2100 case 'Q':
2101 tmpreg=get_num(opP->con1,10);
2102 if(tmpreg==8)
2103 tmpreg=0;
2104 install_operand(s[1],tmpreg);
2105 break;
2106
2107 case 'R':
2108 case 'r':
2109 /* This depends on the fact that ADDR registers are
2110 eight more than their corresponding DATA regs, so
2111 the result will have the ADDR_REG bit set */
2112 install_operand(s[1],opP->reg-DATA);
2113 break;
2114
2115 case 's':
2116 if(opP->reg==FPI) tmpreg=0x1;
2117 else if(opP->reg==FPS) tmpreg=0x2;
2118 else if(opP->reg==FPC) tmpreg=0x4;
2119 else as_fatal("failed sanity check.");
2120 install_operand(s[1],tmpreg);
2121 break;
2122
2123 case 'S': /* Ignore it */
2124 break;
2125
2126 case 'T':
2127 install_operand(s[1],get_num(opP->con1,30));
2128 break;
2129
2130 case 'U': /* Ignore it */
2131 break;
2132
2133 case 'c':
2134 switch (opP->reg) {
2135 case NC: tmpreg = 0; break;
2136 case DC: tmpreg = 1; break;
2137 case IC: tmpreg = 2; break;
2138 case BC: tmpreg = 3; break;
2139 default:
2140 as_fatal("failed sanity check");
2141 } /* switch on cache token */
2142 install_operand(s[1], tmpreg);
2143 break;
2144 #ifndef NO_68851
2145 /* JF: These are out of order, I fear. */
2146 case 'f':
2147 switch (opP->reg) {
2148 case SFC:
2149 tmpreg=0;
2150 break;
2151 case DFC:
2152 tmpreg=1;
2153 break;
2154 default:
2155 as_fatal("failed sanity check.");
2156 }
2157 install_operand(s[1],tmpreg);
2158 break;
2159
2160 case 'P':
2161 switch(opP->reg) {
2162 case TC:
2163 tmpreg=0;
2164 break;
2165 case CAL:
2166 tmpreg=4;
2167 break;
2168 case VAL:
2169 tmpreg=5;
2170 break;
2171 case SCC:
2172 tmpreg=6;
2173 break;
2174 case AC:
2175 tmpreg=7;
2176 break;
2177 default:
2178 as_fatal("failed sanity check.");
2179 }
2180 install_operand(s[1],tmpreg);
2181 break;
2182
2183 case 'V':
2184 if (opP->reg == VAL)
2185 break;
2186 as_fatal("failed sanity check.");
2187
2188 case 'W':
2189 switch(opP->reg) {
2190
2191 case DRP:
2192 tmpreg=1;
2193 break;
2194 case SRP:
2195 tmpreg=2;
2196 break;
2197 case CRP:
2198 tmpreg=3;
2199 break;
2200 default:
2201 as_fatal("failed sanity check.");
2202 }
2203 install_operand(s[1],tmpreg);
2204 break;
2205
2206 case 'X':
2207 switch (opP->reg) {
2208 case BAD: case BAD+1: case BAD+2: case BAD+3:
2209 case BAD+4: case BAD+5: case BAD+6: case BAD+7:
2210 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2211 break;
2212
2213 case BAC: case BAC+1: case BAC+2: case BAC+3:
2214 case BAC+4: case BAC+5: case BAC+6: case BAC+7:
2215 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2216 break;
2217
2218 default:
2219 as_fatal("failed sanity check.");
2220 }
2221 install_operand(s[1], tmpreg);
2222 break;
2223 case 'Y':
2224 know(opP->reg == PSR);
2225 break;
2226 case 'Z':
2227 know(opP->reg == PCSR);
2228 break;
2229 #endif /* m68851 */
2230 case '_':
2231 tmpreg=get_num(opP->con1,80);
2232 install_operand(s[1], tmpreg);
2233 break;
2234 default:
2235 as_fatal("Internal error: Operand type %c unknown in line %s of file \"%s\"", s[0], __LINE__, __FILE__);
2236 }
2237 }
2238 /* By the time whe get here (FINALLY) the_ins contains the complete
2239 instruction, ready to be emitted. . . */
2240 } /* m68k_ip() */
2241
2242 /*
2243 * get_regs := '/' + ?
2244 * | '-' + <register>
2245 * | '-' + <register> + ?
2246 * | <empty>
2247 * ;
2248 *
2249
2250 * The idea here must be to scan in a set of registers but I don't
2251 * understand it. Looks awfully sloppy to me but I don't have any doc on
2252 * this format so...
2253
2254 *
2255 *
2256 */
2257
2258 static int get_regs(i,str,opP)
2259 int i;
2260 struct m68k_op *opP;
2261 char *str;
2262 {
2263 /* 26, 25, 24, 23-16, 15-8, 0-7 */
2264 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
2265 unsigned long cur_regs = 0;
2266 int reg1,
2267 reg2;
2268
2269 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
2270 else if(x==FPS) cur_regs|=(1<<25);\
2271 else if(x==FPC) cur_regs|=(1<<26);\
2272 else cur_regs|=(1<<(x-1)); }
2273
2274 reg1=i;
2275 for(;;) {
2276 if(*str=='/') {
2277 ADD_REG(reg1);
2278 str++;
2279 } else if(*str=='-') {
2280 str++;
2281 reg2=m68k_reg_parse(&str);
2282 if(reg2<DATA || reg2>=FPREG+8 || reg1==FPI || reg1==FPS || reg1==FPC) {
2283 opP->error="unknown register in register list";
2284 return FAIL;
2285 }
2286 while(reg1<=reg2) {
2287 ADD_REG(reg1);
2288 reg1++;
2289 }
2290 if(*str=='\0')
2291 break;
2292 } else if(*str=='\0') {
2293 ADD_REG(reg1);
2294 break;
2295 } else {
2296 opP->error="unknow character in register list";
2297 return FAIL;
2298 }
2299 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
2300 if (*str=='/')
2301 str ++;
2302 reg1=m68k_reg_parse(&str);
2303 if((reg1<DATA || reg1>=FPREG+8) && !(reg1==FPI || reg1==FPS || reg1==FPC)) {
2304 opP->error="unknown register in register list";
2305 return FAIL;
2306 }
2307 }
2308 opP->reg=cur_regs;
2309 return OK;
2310 } /* get_regs() */
2311
2312 static int reverse_16_bits(in)
2313 int in;
2314 {
2315 int out=0;
2316 int n;
2317
2318 static int mask[16] = {
2319 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2320 0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000
2321 };
2322 for(n=0;n<16;n++) {
2323 if(in&mask[n])
2324 out|=mask[15-n];
2325 }
2326 return out;
2327 } /* reverse_16_bits() */
2328
2329 static int reverse_8_bits(in)
2330 int in;
2331 {
2332 int out=0;
2333 int n;
2334
2335 static int mask[8] = {
2336 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2337 };
2338
2339 for(n=0;n<8;n++) {
2340 if(in&mask[n])
2341 out|=mask[7-n];
2342 }
2343 return out;
2344 } /* reverse_8_bits() */
2345
2346 static void install_operand(mode,val)
2347 int mode;
2348 int val;
2349 {
2350 switch(mode) {
2351 case 's':
2352 the_ins.opcode[0]|=val & 0xFF; /* JF FF is for M kludge */
2353 break;
2354 case 'd':
2355 the_ins.opcode[0]|=val<<9;
2356 break;
2357 case '1':
2358 the_ins.opcode[1]|=val<<12;
2359 break;
2360 case '2':
2361 the_ins.opcode[1]|=val<<6;
2362 break;
2363 case '3':
2364 the_ins.opcode[1]|=val;
2365 break;
2366 case '4':
2367 the_ins.opcode[2]|=val<<12;
2368 break;
2369 case '5':
2370 the_ins.opcode[2]|=val<<6;
2371 break;
2372 case '6':
2373 /* DANGER! This is a hack to force cas2l and cas2w cmds
2374 to be three words long! */
2375 the_ins.numo++;
2376 the_ins.opcode[2]|=val;
2377 break;
2378 case '7':
2379 the_ins.opcode[1]|=val<<7;
2380 break;
2381 case '8':
2382 the_ins.opcode[1]|=val<<10;
2383 break;
2384 #ifndef NO_68851
2385 case '9':
2386 the_ins.opcode[1]|=val<<5;
2387 break;
2388 #endif
2389
2390 case 't':
2391 the_ins.opcode[1]|=(val<<10)|(val<<7);
2392 break;
2393 case 'D':
2394 the_ins.opcode[1]|=(val<<12)|val;
2395 break;
2396 case 'g':
2397 the_ins.opcode[0]|=val=0xff;
2398 break;
2399 case 'i':
2400 the_ins.opcode[0]|=val<<9;
2401 break;
2402 case 'C':
2403 the_ins.opcode[1]|=val;
2404 break;
2405 case 'j':
2406 the_ins.opcode[1]|=val;
2407 the_ins.numo++; /* What a hack */
2408 break;
2409 case 'k':
2410 the_ins.opcode[1]|=val<<4;
2411 break;
2412 case 'b':
2413 case 'w':
2414 case 'l':
2415 break;
2416 case 'e':
2417 the_ins.opcode[0] |= (val << 6);
2418 break;
2419 case 'L':
2420 the_ins.opcode[1] = (val >> 16);
2421 the_ins.opcode[2] = val & 0xffff;
2422 break;
2423 case 'c':
2424 default:
2425 as_fatal("failed sanity check.");
2426 }
2427 } /* install_operand() */
2428
2429 static void install_gen_operand(mode,val)
2430 int mode;
2431 int val;
2432 {
2433 switch(mode) {
2434 case 's':
2435 the_ins.opcode[0]|=val;
2436 break;
2437 case 'd':
2438 /* This is a kludge!!! */
2439 the_ins.opcode[0]|=(val&0x07)<<9|(val&0x38)<<3;
2440 break;
2441 case 'b':
2442 case 'w':
2443 case 'l':
2444 case 'f':
2445 case 'F':
2446 case 'x':
2447 case 'p':
2448 the_ins.opcode[0]|=val;
2449 break;
2450 /* more stuff goes here */
2451 default:
2452 as_fatal("failed sanity check.");
2453 }
2454 } /* install_gen_operand() */
2455
2456 /*
2457 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2458 * then deal with the bitfield hack.
2459 */
2460
2461 static char *crack_operand(str,opP)
2462 register char *str;
2463 register struct m68k_op *opP;
2464 {
2465 register int parens;
2466 register int c;
2467 register char *beg_str;
2468
2469 if(!str) {
2470 return str;
2471 }
2472 beg_str=str;
2473 for(parens=0;*str && (parens>0 || notend(str));str++) {
2474 if(*str=='(') parens++;
2475 else if(*str==')') {
2476 if(!parens) { /* ERROR */
2477 opP->error="Extra )";
2478 return str;
2479 }
2480 --parens;
2481 }
2482 }
2483 if(!*str && parens) { /* ERROR */
2484 opP->error="Missing )";
2485 return str;
2486 }
2487 c= *str;
2488 *str='\0';
2489 if(m68k_ip_op(beg_str,opP)==FAIL) {
2490 *str=c;
2491 return str;
2492 }
2493 *str=c;
2494 if(c=='}')
2495 c= *++str; /* JF bitfield hack */
2496 if(c) {
2497 c= *++str;
2498 if(!c)
2499 as_bad("Missing operand");
2500 }
2501 return str;
2502 }
2503
2504 /* See the comment up above where the #define notend(... is */
2505 #if 0
2506 notend(s)
2507 char *s;
2508 {
2509 if(*s==',') return 0;
2510 if(*s=='{' || *s=='}')
2511 return 0;
2512 if(*s!=':') return 1;
2513 /* This kludge here is for the division cmd, which is a kludge */
2514 if(index("aAdD#",s[1])) return 0;
2515 return 1;
2516 }
2517 #endif
2518
2519 /* This is the guts of the machine-dependent assembler. STR points to a
2520 machine dependent instruction. This function is supposed to emit
2521 the frags/bytes it assembles to.
2522 */
2523
2524 void
2525 insert_reg(regname, regnum)
2526 char *regname;
2527 int regnum;
2528 {
2529 char buf[100];
2530 int i;
2531 symbol_table_insert(symbol_new(regname, SEG_REGISTER, regnum, &zero_address_frag));
2532
2533 for (i = 0; regname[i]; i++)
2534 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2535 buf[i] = '\0';
2536
2537 symbol_table_insert(symbol_new(buf, SEG_REGISTER, regnum, &zero_address_frag));
2538 }
2539
2540 static struct {
2541 char *name;
2542 int number;
2543 } init_table[] =
2544 {
2545 "d0", DATA0,
2546 "d1", DATA1,
2547 "d2", DATA2,
2548 "d3", DATA3,
2549 "d4", DATA4,
2550 "d5", DATA5,
2551 "d6", DATA6,
2552 "d7", DATA7,
2553 "a0", ADDR0,
2554 "a1", ADDR1,
2555 "a2", ADDR2,
2556 "a3", ADDR3,
2557 "a4", ADDR4,
2558 "a5", ADDR5,
2559 "a6", ADDR6,
2560 "fp", ADDR6,
2561 "a7", ADDR7,
2562 "sp", ADDR7,
2563 "fp0", FP0,
2564 "fp1", FP1,
2565 "fp2", FP2,
2566 "fp3", FP3,
2567 "fp4", FP4,
2568 "fp5", FP5,
2569 "fp6", FP6,
2570 "fp7", FP7,
2571 "fpi", FPI,
2572 "fpiar", FPI,
2573 "fpc", FPI,
2574 "fps", FPS,
2575 "fpsr", FPS,
2576 "fpc", FPC,
2577 "fpcr", FPC,
2578
2579 "cop0", COP0,
2580 "cop1", COP1,
2581 "cop2", COP2,
2582 "cop3", COP3,
2583 "cop4", COP4,
2584 "cop5", COP5,
2585 "cop6", COP6,
2586 "cop7", COP7,
2587 "pc", PC,
2588 "zpc", ZPC,
2589 "sr", SR,
2590
2591 "ccr", CCR,
2592 "cc", CCR,
2593
2594 "usp", USP,
2595 "isp", ISP,
2596 "sfc", SFC,
2597 "dfc", DFC,
2598 "cacr", CACR,
2599 "caar", CAAR,
2600
2601 "vbr", VBR,
2602
2603 "msp", MSP,
2604 "itt0", ITT0,
2605 "itt1", ITT1,
2606 "dtt0", DTT0,
2607 "dtt1", DTT1,
2608 "mmusr", MMUSR,
2609 "tc", TC,
2610 "srp", SRP,
2611 "urp", URP,
2612
2613 #ifndef NO_68851
2614 "ac", AC,
2615 "bc", BC,
2616 "cal", CAL,
2617 "crp", CRP,
2618 "drp", DRP,
2619 "pcsr", PCSR,
2620 "psr", PSR,
2621 "scc", SCC,
2622 "val", VAL,
2623 "bad0", BAD0,
2624 "bad1", BAD1,
2625 "bad2", BAD2,
2626 "bad3", BAD3,
2627 "bad4", BAD4,
2628 "bad5", BAD5,
2629 "bad6", BAD6,
2630 "bad7", BAD7,
2631 "bac0", BAC0,
2632 "bac1", BAC1,
2633 "bac2", BAC2,
2634 "bac3", BAC3,
2635 "bac4", BAC4,
2636 "bac5", BAC5,
2637 "bac6", BAC6,
2638 "bac7", BAC7,
2639 #endif
2640
2641 "ic", IC,
2642 "dc", DC,
2643 "nc", NC,
2644
2645 0,
2646
2647 };
2648
2649
2650 void
2651 init_regtable()
2652 {
2653 int i;
2654 for (i = 0; init_table[i].name; i++)
2655 {
2656 insert_reg(init_table[i].name, init_table[i].number);
2657 }
2658 }
2659
2660
2661 void
2662 md_assemble(str)
2663 char *str;
2664 {
2665 char *er;
2666 short *fromP;
2667 char *toP = NULL;
2668 int m,n = 0;
2669 char *to_beg_P;
2670 int shorts_this_frag;
2671
2672
2673 if (cpu_of_arch (current_architecture) == 0)
2674 {
2675 enum m68k_architecture cpu_type;
2676
2677 #ifndef TARGET_CPU
2678 cpu_type = m68020;
2679 #else
2680 if (strcmp (TARGET_CPU, "m68000") == 0)
2681 cpu_type = m68000;
2682 else if (strcmp (TARGET_CPU, "m68010") == 0)
2683 cpu_type = m68010;
2684 else if (strcmp (TARGET_CPU, "m68020") == 0
2685 || strcmp (TARGET_CPU, "m68k") == 0)
2686 cpu_type = m68020;
2687 else if (strcmp (TARGET_CPU, "m68030") == 0)
2688 cpu_type = m68030;
2689 else if (strcmp (TARGET_CPU, "m68040") == 0)
2690 cpu_type = m68040;
2691 else
2692 cpu_type = m68020;
2693 #endif
2694
2695 /* If float or mmu were specified, just default cpu. */
2696 if (current_architecture != 0)
2697 current_architecture |= cpu_type;
2698 else
2699 {
2700 if ((cpu_type & m68020up) != 0)
2701 current_architecture = (cpu_type
2702 #ifndef NO_68881
2703 | m68881
2704 #endif
2705 #ifndef NO_68851
2706 | m68851
2707 #endif
2708 );
2709 else
2710 current_architecture = cpu_type;
2711 }
2712 }
2713
2714 memset((char *)(&the_ins), '\0', sizeof(the_ins)); /* JF for paranoia sake */
2715 m68k_ip(str);
2716 er=the_ins.error;
2717 if(!er) {
2718 for(n=the_ins.numargs;n;--n)
2719 if(the_ins.operands[n].error) {
2720 er=the_ins.operands[n].error;
2721 break;
2722 }
2723 }
2724 if(er) {
2725 as_bad("%s -- statement `%s' ignored",er,str);
2726 return;
2727 }
2728
2729 if(the_ins.nfrag==0) { /* No frag hacking involved; just put it out */
2730 toP=frag_more(2*the_ins.numo);
2731 fromP= &the_ins.opcode[0];
2732 for(m=the_ins.numo;m;--m) {
2733 md_number_to_chars(toP,(long)(*fromP),2);
2734 toP+=2;
2735 fromP++;
2736 }
2737 /* put out symbol-dependent info */
2738 for(m=0;m<the_ins.nrel;m++) {
2739 switch(the_ins.reloc[m].wid) {
2740 case 'B':
2741 n=1;
2742 break;
2743 case 'b':
2744 n=1;
2745 break;
2746 case '3':
2747 n=2;
2748 break;
2749 case 'w':
2750 n=2;
2751 break;
2752 case 'l':
2753 n=4;
2754 break;
2755 default:
2756 as_fatal("Don't know how to figure width of %c in md_assemble()",the_ins.reloc[m].wid);
2757 }
2758
2759 fix_new(frag_now,
2760 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
2761 n,
2762 the_ins.reloc[m].add,
2763 the_ins.reloc[m].sub,
2764 the_ins.reloc[m].off,
2765 the_ins.reloc[m].pcrel,
2766 NO_RELOC);
2767 }
2768 return;
2769 }
2770
2771 /* There's some frag hacking */
2772 for(n=0,fromP= &the_ins.opcode[0];n<the_ins.nfrag;n++) {
2773 int wid;
2774
2775 if(n==0) wid=2*the_ins.fragb[n].fragoff;
2776 else wid=2*(the_ins.numo-the_ins.fragb[n-1].fragoff);
2777 toP=frag_more(wid);
2778 to_beg_P=toP;
2779 shorts_this_frag=0;
2780 for(m=wid/2;m;--m) {
2781 md_number_to_chars(toP,(long)(*fromP),2);
2782 toP+=2;
2783 fromP++;
2784 shorts_this_frag++;
2785 }
2786 for(m=0;m<the_ins.nrel;m++) {
2787 if((the_ins.reloc[m].n)>= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */) {
2788 the_ins.reloc[m].n-= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */;
2789 break;
2790 }
2791 wid=the_ins.reloc[m].wid;
2792 if(wid==0)
2793 continue;
2794 the_ins.reloc[m].wid=0;
2795 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
2796
2797 fix_new(frag_now,
2798 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
2799 wid,
2800 the_ins.reloc[m].add,
2801 the_ins.reloc[m].sub,
2802 the_ins.reloc[m].off,
2803 the_ins.reloc[m].pcrel,
2804 NO_RELOC);
2805 }
2806 /* know(the_ins.fragb[n].fadd); */
2807 (void)frag_var(rs_machine_dependent,10,0,(relax_substateT)(the_ins.fragb[n].fragty),
2808 the_ins.fragb[n].fadd,the_ins.fragb[n].foff,to_beg_P);
2809 }
2810 n=(the_ins.numo-the_ins.fragb[n-1].fragoff);
2811 shorts_this_frag=0;
2812 if(n) {
2813 toP=frag_more(n*sizeof(short));
2814 while(n--) {
2815 md_number_to_chars(toP,(long)(*fromP),2);
2816 toP+=2;
2817 fromP++;
2818 shorts_this_frag++;
2819 }
2820 }
2821 for(m=0;m<the_ins.nrel;m++) {
2822 int wid;
2823
2824 wid=the_ins.reloc[m].wid;
2825 if(wid==0)
2826 continue;
2827 the_ins.reloc[m].wid=0;
2828 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
2829
2830 fix_new(frag_now,
2831 (the_ins.reloc[m].n + toP-frag_now->fr_literal)-/* the_ins.numo */ shorts_this_frag*2,
2832 wid,
2833 the_ins.reloc[m].add,
2834 the_ins.reloc[m].sub,
2835 the_ins.reloc[m].off,
2836 the_ins.reloc[m].pcrel,
2837 NO_RELOC);
2838 }
2839 }
2840
2841
2842
2843
2844
2845 void
2846 md_begin()
2847 {
2848 /*
2849 * md_begin -- set up hash tables with 68000 instructions.
2850 * similar to what the vax assembler does. ---phr
2851 */
2852 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
2853 a copy of it at runtime, adding in the information we want but isn't
2854 there. I think it'd be better to have an awk script hack the table
2855 at compile time. Or even just xstr the table and use it as-is. But
2856 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
2857 names. */
2858
2859 register const struct m68k_opcode *ins;
2860 register struct m68k_incant *hack,
2861 *slak;
2862 register char *retval = 0; /* empty string, or error msg text */
2863 register unsigned int i;
2864 register char c;
2865
2866 if ((op_hash = hash_new()) == NULL)
2867 as_fatal("Virtual memory exhausted");
2868
2869 obstack_begin(&robyn,4000);
2870 for (ins = m68k_opcodes; ins < endop; ins++) {
2871 hack=slak=(struct m68k_incant *)obstack_alloc(&robyn,sizeof(struct m68k_incant));
2872 do {
2873 /* we *could* ignore insns that don't match our
2874 arch here but just leaving them out of the
2875 hash. */
2876 slak->m_operands=ins->args;
2877 slak->m_opnum=strlen(slak->m_operands)/2;
2878 slak->m_arch = ins->arch;
2879 slak->m_opcode=ins->opcode;
2880 /* This is kludgey */
2881 slak->m_codenum=((ins->match)&0xffffL) ? 2 : 1;
2882 if((ins+1)!=endop && !strcmp(ins->name,(ins+1)->name)) {
2883 slak->m_next=(struct m68k_incant *) obstack_alloc(&robyn,sizeof(struct m68k_incant));
2884 ins++;
2885 } else
2886 slak->m_next=0;
2887 slak=slak->m_next;
2888 } while(slak);
2889
2890 retval = hash_insert (op_hash, ins->name,(char *)hack);
2891 /* Didn't his mommy tell him about null pointers? */
2892 if(retval && *retval)
2893 as_fatal("Internal Error: Can't hash %s: %s",ins->name,retval);
2894 }
2895
2896 for (i = 0; i < sizeof(mklower_table) ; i++)
2897 mklower_table[i] = (isupper(c = (char) i)) ? tolower(c) : c;
2898
2899 for (i = 0 ; i < sizeof(notend_table) ; i++) {
2900 notend_table[i] = 0;
2901 alt_notend_table[i] = 0;
2902 }
2903 notend_table[','] = 1;
2904 notend_table['{'] = 1;
2905 notend_table['}'] = 1;
2906 alt_notend_table['a'] = 1;
2907 alt_notend_table['A'] = 1;
2908 alt_notend_table['d'] = 1;
2909 alt_notend_table['D'] = 1;
2910 alt_notend_table['#'] = 1;
2911 alt_notend_table['f'] = 1;
2912 alt_notend_table['F'] = 1;
2913 #ifdef REGISTER_PREFIX
2914 alt_notend_table[REGISTER_PREFIX] = 1;
2915 #endif
2916
2917 init_regtable();
2918 }
2919
2920 #if 0
2921 #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
2922 || (*s == ':' && strchr("aAdD#", s[1]))) \
2923 ? 0 : 1)
2924 #endif
2925
2926 /* This funciton is called once, before the assembler exits. It is
2927 supposed to do any final cleanup for this part of the assembler.
2928 */
2929 void
2930 md_end()
2931 {
2932 }
2933
2934 /* Equal to MAX_PRECISION in atof-ieee.c */
2935 #define MAX_LITTLENUMS 6
2936
2937 /* Turn a string in input_line_pointer into a floating point constant of type
2938 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2939 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2940 */
2941 char *
2942 md_atof(type,litP,sizeP)
2943 char type;
2944 char *litP;
2945 int *sizeP;
2946 {
2947 int prec;
2948 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2949 LITTLENUM_TYPE *wordP;
2950 char *t;
2951 char *atof_ieee();
2952
2953 switch(type) {
2954 case 'f':
2955 case 'F':
2956 case 's':
2957 case 'S':
2958 prec = 2;
2959 break;
2960
2961 case 'd':
2962 case 'D':
2963 case 'r':
2964 case 'R':
2965 prec = 4;
2966 break;
2967
2968 case 'x':
2969 case 'X':
2970 prec = 6;
2971 break;
2972
2973 case 'p':
2974 case 'P':
2975 prec = 6;
2976 break;
2977
2978 default:
2979 *sizeP=0;
2980 return "Bad call to MD_ATOF()";
2981 }
2982 t=atof_ieee(input_line_pointer,type,words);
2983 if(t)
2984 input_line_pointer=t;
2985
2986 *sizeP=prec * sizeof(LITTLENUM_TYPE);
2987 for(wordP=words;prec--;) {
2988 md_number_to_chars(litP,(long)(*wordP++),sizeof(LITTLENUM_TYPE));
2989 litP+=sizeof(LITTLENUM_TYPE);
2990 }
2991 return ""; /* Someone should teach Dean about null pointers */
2992 }
2993
2994 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
2995 for use in the a.out file, and stores them in the array pointed to by buf.
2996 This knows about the endian-ness of the target machine and does
2997 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
2998 2 (short) and 4 (long) Floating numbers are put out as a series of
2999 LITTLENUMS (shorts, here at least)
3000 */
3001 void
3002 md_number_to_chars(buf,val,n)
3003 char *buf;
3004 long val;
3005 int n;
3006 {
3007 switch(n) {
3008 case 1:
3009 *buf++=val;
3010 break;
3011 case 2:
3012 *buf++=(val>>8);
3013 *buf++=val;
3014 break;
3015 case 4:
3016 *buf++=(val>>24);
3017 *buf++=(val>>16);
3018 *buf++=(val>>8);
3019 *buf++=val;
3020 break;
3021 default:
3022 as_fatal("failed sanity check.");
3023 }
3024 }
3025
3026 void
3027 md_apply_fix(fixP, val)
3028 fixS *fixP;
3029 long val;
3030 {
3031 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3032
3033 switch(fixP->fx_size) {
3034 case 1:
3035 *buf++=val;
3036 break;
3037 case 2:
3038 *buf++=(val>>8);
3039 *buf++=val;
3040 break;
3041 case 4:
3042 *buf++=(val>>24);
3043 *buf++=(val>>16);
3044 *buf++=(val>>8);
3045 *buf++=val;
3046 break;
3047 default:
3048 BAD_CASE (fixP->fx_size);
3049 }
3050 }
3051
3052
3053 /* *fragP has been relaxed to its final size, and now needs to have
3054 the bytes inside it modified to conform to the new size There is UGLY
3055 MAGIC here. ..
3056 */
3057 void
3058 md_convert_frag(headers, fragP)
3059 object_headers *headers;
3060 register fragS *fragP;
3061 {
3062 long disp;
3063 long ext = 0;
3064
3065 /* Address in object code of the displacement. */
3066 register int object_address = fragP -> fr_fix + fragP -> fr_address;
3067
3068 #ifdef IBM_COMPILER_SUX
3069 /* This is wrong but it convinces the native rs6000 compiler to
3070 generate the code we want. */
3071 register char *buffer_address = fragP -> fr_literal;
3072 buffer_address += fragP -> fr_fix;
3073 #else /* IBM_COMPILER_SUX */
3074 /* Address in gas core of the place to store the displacement. */
3075 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3076 #endif /* IBM_COMPILER_SUX */
3077
3078 /* No longer true: know(fragP->fr_symbol); */
3079
3080 /* The displacement of the address, from current location. */
3081 disp = fragP->fr_symbol ? S_GET_VALUE(fragP->fr_symbol) : 0;
3082 disp = (disp + fragP->fr_offset) - object_address;
3083
3084 switch(fragP->fr_subtype) {
3085 case TAB(BCC68000,BYTE):
3086 case TAB(BRANCH,BYTE):
3087 know(issbyte(disp));
3088 if(disp==0)
3089 as_bad("short branch with zero offset: use :w");
3090 fragP->fr_opcode[1]=disp;
3091 ext=0;
3092 break;
3093 case TAB(DBCC,SHORT):
3094 know(issword(disp));
3095 ext=2;
3096 break;
3097 case TAB(BCC68000,SHORT):
3098 case TAB(BRANCH,SHORT):
3099 know(issword(disp));
3100 fragP->fr_opcode[1]=0x00;
3101 ext=2;
3102 break;
3103 case TAB(BRANCH,LONG):
3104 if (cpu_of_arch(current_architecture) < m68020) {
3105 if (fragP->fr_opcode[0]==0x61) {
3106 fragP->fr_opcode[0]= 0x4E;
3107 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3108 subseg_change(SEG_TEXT, 0);
3109
3110 fix_new(fragP,
3111 fragP->fr_fix,
3112 4,
3113 fragP->fr_symbol,
3114 0,
3115 fragP->fr_offset,
3116 0,
3117 NO_RELOC);
3118
3119 fragP->fr_fix+=4;
3120 ext=0;
3121 } else if (fragP->fr_opcode[0]==0x60) {
3122 fragP->fr_opcode[0]= 0x4E;
3123 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3124 subseg_change(SEG_TEXT, 0);
3125 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset,0,
3126 NO_RELOC);
3127 fragP->fr_fix+=4;
3128 ext=0;
3129 } else {
3130 as_bad("Long branch offset not supported.");
3131 }
3132 } else {
3133 fragP->fr_opcode[1]=0xff;
3134 ext=4;
3135 }
3136 break;
3137 case TAB(BCC68000,LONG):
3138 /* only Bcc 68000 instructions can come here */
3139 /* change bcc into b!cc/jmp absl long */
3140 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3141 fragP->fr_opcode[1] = 0x6; /* branch offset = 6 */
3142
3143 /* JF: these used to be fr_opcode[2,3], but they may be in a
3144 different frag, in which case refering to them is a no-no.
3145 Only fr_opcode[0,1] are guaranteed to work. */
3146 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3147 *buffer_address++ = 0xf9;
3148 fragP->fr_fix += 2; /* account for jmp instruction */
3149 subseg_change(SEG_TEXT,0);
3150 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3151 fragP->fr_offset,0,
3152 NO_RELOC);
3153 fragP->fr_fix += 4;
3154 ext=0;
3155 break;
3156 case TAB(DBCC,LONG):
3157 /* only DBcc 68000 instructions can come here */
3158 /* change dbcc into dbcc/jmp absl long */
3159 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3160 *buffer_address++ = 0x00; /* branch offset = 4 */
3161 *buffer_address++ = 0x04;
3162 *buffer_address++ = 0x60; /* put in bra pc+6 */
3163 *buffer_address++ = 0x06;
3164 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3165 *buffer_address++ = 0xf9;
3166
3167 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3168 subseg_change(SEG_TEXT,0);
3169 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3170 fragP->fr_offset,0,
3171 NO_RELOC);
3172 fragP->fr_fix += 4;
3173 ext=0;
3174 break;
3175 case TAB(FBRANCH,SHORT):
3176 know((fragP->fr_opcode[1]&0x40)==0);
3177 ext=2;
3178 break;
3179 case TAB(FBRANCH,LONG):
3180 fragP->fr_opcode[1]|=0x40; /* Turn on LONG bit */
3181 ext=4;
3182 break;
3183 case TAB(PCREL,SHORT):
3184 ext=2;
3185 break;
3186 case TAB(PCREL,LONG):
3187 /* The thing to do here is force it to ABSOLUTE LONG, since
3188 PCREL is really trying to shorten an ABSOLUTE address anyway */
3189 /* JF FOO This code has not been tested */
3190 subseg_change(SEG_TEXT,0);
3191 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3192 if((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3193 as_bad("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
3194 fragP->fr_opcode[0],fragP->fr_address);
3195 fragP->fr_opcode[1]&= ~0x3F;
3196 fragP->fr_opcode[1]|=0x39; /* Mode 7.1 */
3197 fragP->fr_fix+=4;
3198 /* md_number_to_chars(buffer_address,
3199 (long)(fragP->fr_symbol->sy_value + fragP->fr_offset),
3200 4); */
3201 ext=0;
3202 break;
3203 case TAB(PCLEA,SHORT):
3204 subseg_change(SEG_TEXT,0);
3205 fix_new(fragP,(int)(fragP->fr_fix),2,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset,1,
3206 NO_RELOC);
3207 fragP->fr_opcode[1] &= ~0x3F;
3208 fragP->fr_opcode[1] |= 0x3A;
3209 ext=2;
3210 break;
3211 case TAB(PCLEA,LONG):
3212 subseg_change(SEG_TEXT,0);
3213 fix_new(fragP,(int)(fragP->fr_fix)+2,4,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset+2,1,
3214 NO_RELOC);
3215 *buffer_address++ = 0x01;
3216 *buffer_address++ = 0x70;
3217 fragP->fr_fix+=2;
3218 /* buffer_address+=2; */
3219 ext=4;
3220 break;
3221
3222 } /* switch on subtype */
3223
3224 if (ext) {
3225 md_number_to_chars(buffer_address, (long) disp, (int) ext);
3226 fragP->fr_fix += ext;
3227 /* H_SET_TEXT_SIZE(headers, H_GET_TEXT_SIZE(headers) + ext); */
3228 } /* if extending */
3229
3230 return;
3231 } /* md_convert_frag() */
3232
3233 /* Force truly undefined symbols to their maximum size, and generally set up
3234 the frag list to be relaxed
3235 */
3236 int md_estimate_size_before_relax(fragP, segment)
3237 register fragS *fragP;
3238 segT segment;
3239 {
3240 int old_fix;
3241 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3242
3243 old_fix = fragP->fr_fix;
3244
3245 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3246 switch (fragP->fr_subtype) {
3247
3248 case TAB(BRANCH,SZ_UNDEF): {
3249 if((fragP->fr_symbol != NULL) /* Not absolute */
3250 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3251 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),BYTE);
3252 break;
3253 } else if((fragP->fr_symbol == 0) || (cpu_of_arch(current_architecture) < m68020)) {
3254 /* On 68000, or for absolute value, switch to abs long */
3255 /* FIXME, we should check abs val, pick short or long */
3256 if(fragP->fr_opcode[0]==0x61) {
3257 fragP->fr_opcode[0]= 0x4E;
3258 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3259 subseg_change(SEG_TEXT, 0);
3260 fix_new(fragP, fragP->fr_fix, 4,
3261 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3262 fragP->fr_fix+=4;
3263 frag_wane(fragP);
3264 } else if(fragP->fr_opcode[0]==0x60) {
3265 fragP->fr_opcode[0]= 0x4E;
3266 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3267 subseg_change(SEG_TEXT, 0);
3268 fix_new(fragP, fragP->fr_fix, 4,
3269 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3270 fragP->fr_fix+=4;
3271 frag_wane(fragP);
3272 } else {
3273 as_warn("Long branch offset to extern symbol not supported.");
3274 }
3275 } else { /* Symbol is still undefined. Make it simple */
3276 fix_new(fragP, (int)(fragP->fr_fix), 4, fragP->fr_symbol,
3277 (symbolS *)0, fragP->fr_offset+4, 1, NO_RELOC);
3278 fragP->fr_fix+=4;
3279 fragP->fr_opcode[1]=0xff;
3280 frag_wane(fragP);
3281 break;
3282 }
3283
3284 break;
3285 } /* case TAB(BRANCH,SZ_UNDEF) */
3286
3287 case TAB(FBRANCH,SZ_UNDEF): {
3288 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3289 fragP->fr_subtype = TAB(FBRANCH,SHORT);
3290 fragP->fr_var += 2;
3291 } else {
3292 fragP->fr_subtype = TAB(FBRANCH,LONG);
3293 fragP->fr_var += 4;
3294 }
3295 break;
3296 } /* TAB(FBRANCH,SZ_UNDEF) */
3297
3298 case TAB(PCREL,SZ_UNDEF): {
3299 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3300 fragP->fr_subtype = TAB(PCREL,SHORT);
3301 fragP->fr_var += 2;
3302 } else {
3303 fragP->fr_subtype = TAB(PCREL,LONG);
3304 fragP->fr_var += 4;
3305 }
3306 break;
3307 } /* TAB(PCREL,SZ_UNDEF) */
3308
3309 case TAB(BCC68000,SZ_UNDEF): {
3310 if((fragP->fr_symbol != NULL)
3311 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3312 fragP->fr_subtype=TAB(BCC68000,BYTE);
3313 break;
3314 }
3315 /* only Bcc 68000 instructions can come here */
3316 /* change bcc into b!cc/jmp absl long */
3317 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3318 if(flagseen['l']) {
3319 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3320 /* JF: these were fr_opcode[2,3] */
3321 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3322 buffer_address[1] = 0xf8;
3323 fragP->fr_fix += 2; /* account for jmp instruction */
3324 subseg_change(SEG_TEXT,0);
3325 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
3326 fragP->fr_offset, 0, NO_RELOC);
3327 fragP->fr_fix += 2;
3328 } else {
3329 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3330 /* JF: these were fr_opcode[2,3] */
3331 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3332 buffer_address[1] = 0xf9;
3333 fragP->fr_fix += 2; /* account for jmp instruction */
3334 subseg_change(SEG_TEXT,0);
3335 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3336 fragP->fr_offset, 0, NO_RELOC);
3337 fragP->fr_fix += 4;
3338 }
3339 frag_wane(fragP);
3340 break;
3341 } /* case TAB(BCC68000,SZ_UNDEF) */
3342
3343 case TAB(DBCC,SZ_UNDEF): {
3344 if (fragP->fr_symbol != NULL && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3345 fragP->fr_subtype=TAB(DBCC,SHORT);
3346 fragP->fr_var+=2;
3347 break;
3348 }
3349 /* only DBcc 68000 instructions can come here */
3350 /* change dbcc into dbcc/jmp absl long */
3351 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3352 buffer_address[0] = 0x00; /* branch offset = 4 */
3353 buffer_address[1] = 0x04;
3354 buffer_address[2] = 0x60; /* put in bra pc + ... */
3355
3356 if(flagseen['l']) {
3357 /* JF: these were fr_opcode[5-7] */
3358 buffer_address[3] = 0x04; /* plus 4 */
3359 buffer_address[4] = 0x4e;/* Put in Jump Word */
3360 buffer_address[5] = 0xf8;
3361 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3362 subseg_change(SEG_TEXT,0);
3363 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
3364
3365
3366 fragP->fr_offset, 0, NO_RELOC);
3367 fragP->fr_fix += 2;
3368 } else {
3369 /* JF: these were fr_opcode[5-7] */
3370 buffer_address[3] = 0x06; /* Plus 6 */
3371 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3372 buffer_address[5] = 0xf9;
3373 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3374 subseg_change(SEG_TEXT,0);
3375 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3376 fragP->fr_offset, 0, NO_RELOC);
3377 fragP->fr_fix += 4;
3378 }
3379
3380 frag_wane(fragP);
3381 break;
3382 } /* case TAB(DBCC,SZ_UNDEF) */
3383
3384 case TAB(PCLEA,SZ_UNDEF): {
3385 if ((S_GET_SEGMENT(fragP->fr_symbol))==segment || flagseen['l']) {
3386 fragP->fr_subtype=TAB(PCLEA,SHORT);
3387 fragP->fr_var+=2;
3388 } else {
3389 fragP->fr_subtype=TAB(PCLEA,LONG);
3390 fragP->fr_var+=6;
3391 }
3392 break;
3393 } /* TAB(PCLEA,SZ_UNDEF) */
3394
3395 default:
3396 break;
3397
3398 } /* switch on subtype looking for SZ_UNDEF's. */
3399
3400 /* now that SZ_UNDEF are taken care of, check others */
3401 switch (fragP->fr_subtype) {
3402 case TAB(BCC68000,BYTE):
3403 case TAB(BRANCH,BYTE):
3404 /* We can't do a short jump to the next instruction,
3405 so we force word mode. */
3406 if (fragP->fr_symbol && S_GET_VALUE(fragP->fr_symbol)==0 &&
3407 fragP->fr_symbol->sy_frag==fragP->fr_next) {
3408 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),SHORT);
3409 fragP->fr_var+=2;
3410 }
3411 break;
3412 default:
3413 break;
3414 }
3415 return fragP->fr_var + fragP->fr_fix - old_fix;
3416 }
3417
3418 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3419 /* the bit-field entries in the relocation_info struct plays hell
3420 with the byte-order problems of cross-assembly. So as a hack,
3421 I added this mach. dependent ri twiddler. Ugly, but it gets
3422 you there. -KWK */
3423 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3424 are symbolnum, most sig. byte first. Last byte is broken up with
3425 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3426 nibble as nuthin. (on Sun 3 at least) */
3427 /* Translate the internal relocation information into target-specific
3428 format. */
3429 #ifdef comment
3430 void
3431 md_ri_to_chars(the_bytes, ri)
3432 char *the_bytes;
3433 struct reloc_info_generic *ri;
3434 {
3435 /* this is easy */
3436 md_number_to_chars(the_bytes, ri->r_address, 4);
3437 /* now the fun stuff */
3438 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3439 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3440 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3441 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3442 ((ri->r_extern << 4) & 0x10));
3443 }
3444 #endif /* comment */
3445
3446 void tc_aout_fix_to_chars(where, fixP, segment_address_in_file)
3447 char *where;
3448 fixS *fixP;
3449 relax_addressT segment_address_in_file;
3450 {
3451 /*
3452 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3453 * Out: GNU LD relocation length code: 0, 1, or 2.
3454 */
3455
3456 static unsigned char nbytes_r_length [] = { 42, 0, 1, 42, 2 };
3457 long r_symbolnum;
3458
3459 know(fixP->fx_addsy != NULL);
3460
3461 md_number_to_chars(where,
3462 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3463 4);
3464
3465 r_symbolnum = (S_IS_DEFINED(fixP->fx_addsy)
3466 ? S_GET_TYPE(fixP->fx_addsy)
3467 : fixP->fx_addsy->sy_number);
3468
3469 where[4] = (r_symbolnum >> 16) & 0x0ff;
3470 where[5] = (r_symbolnum >> 8) & 0x0ff;
3471 where[6] = r_symbolnum & 0x0ff;
3472 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3473 (((!S_IS_DEFINED(fixP->fx_addsy)) << 4) & 0x10));
3474
3475 return;
3476 } /* tc_aout_fix_to_chars() */
3477
3478 #endif /* OBJ_AOUT or OBJ_BOUT */
3479
3480 #ifndef WORKING_DOT_WORD
3481 const int md_short_jump_size = 4;
3482 const int md_long_jump_size = 6;
3483
3484 void
3485 md_create_short_jump(ptr,from_addr,to_addr,frag,to_symbol)
3486 char *ptr;
3487 long from_addr,
3488 to_addr;
3489 fragS *frag;
3490 symbolS *to_symbol;
3491 {
3492 long offset;
3493
3494 offset = to_addr - (from_addr+2);
3495
3496 md_number_to_chars(ptr ,(long)0x6000,2);
3497 md_number_to_chars(ptr+2,(long)offset,2);
3498 }
3499
3500 void
3501 md_create_long_jump(ptr,from_addr,to_addr,frag,to_symbol)
3502 char *ptr;
3503 long from_addr,
3504 to_addr;
3505 fragS *frag;
3506 symbolS *to_symbol;
3507 {
3508 long offset;
3509
3510 if (cpu_of_arch(current_architecture) < m68020) {
3511 offset=to_addr-S_GET_VALUE(to_symbol);
3512 md_number_to_chars(ptr ,(long)0x4EF9,2);
3513 md_number_to_chars(ptr+2,(long)offset,4);
3514 fix_new(frag,(ptr+2)-frag->fr_literal,4,to_symbol,(symbolS *)0,(long)0,0,
3515 NO_RELOC);
3516 } else {
3517 offset=to_addr - (from_addr+2);
3518 md_number_to_chars(ptr ,(long)0x60ff,2);
3519 md_number_to_chars(ptr+2,(long)offset,4);
3520 }
3521 }
3522
3523 #endif
3524 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
3525
3526 0: Everything is OK
3527 10: Absolute 1:8 only
3528 20: Absolute 0:7 only
3529 30: absolute 0:15 only
3530 40: Absolute 0:31 only
3531 50: absolute 0:127 only
3532 55: absolute -64:63 only
3533 60: absolute -128:127 only
3534 70: absolute 0:4095 only
3535 80: No bignums
3536
3537 */
3538
3539 static int get_num(exp,ok)
3540 struct m68k_exp *exp;
3541 int ok;
3542 {
3543 #ifdef TEST2
3544 long l = 0;
3545
3546 if(!exp->e_beg)
3547 return 0;
3548 if(*exp->e_beg=='0') {
3549 if(exp->e_beg[1]=='x')
3550 sscanf(exp->e_beg+2,"%x",&l);
3551 else
3552 sscanf(exp->e_beg+1,"%O",&l);
3553 return l;
3554 }
3555 return atol(exp->e_beg);
3556 #else
3557 char *save_in;
3558 char c_save;
3559
3560 if(!exp) {
3561 /* Can't do anything */
3562 return 0;
3563 }
3564 if(!exp->e_beg || !exp->e_end) {
3565 seg(exp)=SEG_ABSOLUTE;
3566 adds(exp)=0;
3567 subs(exp)=0;
3568 offs(exp)= (ok==10) ? 1 : 0;
3569 as_warn("Null expression defaults to %ld",offs(exp));
3570 return 0;
3571 }
3572
3573 exp->e_siz=0;
3574 if(/* ok!=80 && */exp->e_end[-1]==':' && (exp->e_end-exp->e_beg)>=2) {
3575 switch(exp->e_end[0]) {
3576 case 's':
3577 case 'S':
3578 case 'b':
3579 case 'B':
3580 exp->e_siz=1;
3581 break;
3582 case 'w':
3583 case 'W':
3584 exp->e_siz=2;
3585 break;
3586 case 'l':
3587 case 'L':
3588 exp->e_siz=3;
3589 break;
3590 default:
3591 as_bad("Unknown size for expression \"%c\"",exp->e_end[0]);
3592 }
3593 exp->e_end-=2;
3594 }
3595 c_save=exp->e_end[1];
3596 exp->e_end[1]='\0';
3597 save_in=input_line_pointer;
3598 input_line_pointer=exp->e_beg;
3599 switch(expression(&(exp->e_exp))) {
3600 case SEG_PASS1:
3601 seg(exp)=SEG_ABSOLUTE;
3602 adds(exp)=0;
3603 subs(exp)=0;
3604 offs(exp)= (ok==10) ? 1 : 0;
3605 as_warn("Unknown expression: '%s' defaulting to %d",exp->e_beg,offs(exp));
3606 break;
3607
3608 case SEG_ABSENT:
3609 /* Do the same thing the VAX asm does */
3610 seg(exp)=SEG_ABSOLUTE;
3611 adds(exp)=0;
3612 subs(exp)=0;
3613 offs(exp)=0;
3614 if(ok==10) {
3615 as_warn("expression out of range: defaulting to 1");
3616 offs(exp)=1;
3617 }
3618 break;
3619 case SEG_ABSOLUTE:
3620 switch(ok) {
3621 case 10:
3622 if(offs(exp)<1 || offs(exp)>8) {
3623 as_warn("expression out of range: defaulting to 1");
3624 offs(exp)=1;
3625 }
3626 break;
3627 case 20:
3628 if(offs(exp)<0 || offs(exp)>7)
3629 goto outrange;
3630 break;
3631 case 30:
3632 if(offs(exp)<0 || offs(exp)>15)
3633 goto outrange;
3634 break;
3635 case 40:
3636 if(offs(exp)<0 || offs(exp)>32)
3637 goto outrange;
3638 break;
3639 case 50:
3640 if(offs(exp)<0 || offs(exp)>127)
3641 goto outrange;
3642 break;
3643 case 55:
3644 if(offs(exp)<-64 || offs(exp)>63)
3645 goto outrange;
3646 break;
3647 case 60:
3648 if(offs(exp)<-128 || offs(exp)>127)
3649 goto outrange;
3650 break;
3651 case 70:
3652 if(offs(exp)<0 || offs(exp)>4095) {
3653 outrange:
3654 as_warn("expression out of range: defaulting to 0");
3655 offs(exp)=0;
3656 }
3657 break;
3658 default:
3659 break;
3660 }
3661 break;
3662 case SEG_TEXT:
3663 case SEG_DATA:
3664 case SEG_BSS:
3665 case SEG_UNKNOWN:
3666 case SEG_DIFFERENCE:
3667 if(ok>=10 && ok<=70) {
3668 seg(exp)=SEG_ABSOLUTE;
3669 adds(exp)=0;
3670 subs(exp)=0;
3671 offs(exp)= (ok==10) ? 1 : 0;
3672 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
3673 }
3674 break;
3675 case SEG_BIG:
3676 if(ok==80 && offs(exp)<0) { /* HACK! Turn it into a long */
3677 LITTLENUM_TYPE words[6];
3678
3679 gen_to_words(words,2,8L);/* These numbers are magic! */
3680 seg(exp)=SEG_ABSOLUTE;
3681 adds(exp)=0;
3682 subs(exp)=0;
3683 offs(exp)=words[1]|(words[0]<<16);
3684 } else if(ok!=0) {
3685 seg(exp)=SEG_ABSOLUTE;
3686 adds(exp)=0;
3687 subs(exp)=0;
3688 offs(exp)= (ok==10) ? 1 : 0;
3689 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
3690 }
3691 break;
3692 default:
3693 as_fatal("failed sanity check.");
3694 }
3695 if(input_line_pointer!=exp->e_end+1)
3696 as_bad("Ignoring junk after expression");
3697 exp->e_end[1]=c_save;
3698 input_line_pointer=save_in;
3699 if(exp->e_siz) {
3700 switch(exp->e_siz) {
3701 case 1:
3702 if(!isbyte(offs(exp)))
3703 as_warn("expression doesn't fit in BYTE");
3704 break;
3705 case 2:
3706 if(!isword(offs(exp)))
3707 as_warn("expression doesn't fit in WORD");
3708 break;
3709 }
3710 }
3711 return offs(exp);
3712 #endif
3713 } /* get_num() */
3714
3715 /* These are the back-ends for the various machine dependent pseudo-ops. */
3716 void demand_empty_rest_of_line(); /* Hate those extra verbose names */
3717
3718 static void s_data1() {
3719 subseg_new(SEG_DATA,1);
3720 demand_empty_rest_of_line();
3721 } /* s_data1() */
3722
3723 static void s_data2() {
3724 subseg_new(SEG_DATA,2);
3725 demand_empty_rest_of_line();
3726 } /* s_data2() */
3727
3728 static void s_bss()
3729 {
3730 /* We don't support putting frags in the BSS segment, we fake it
3731 by marking in_bss, then looking at s_skip for clues */
3732
3733 subseg_new(SEG_BSS, 0);
3734 demand_empty_rest_of_line();
3735 } /* s_bss() */
3736
3737 static void s_even() {
3738 register int temp;
3739 register long temp_fill;
3740
3741 temp = 1; /* JF should be 2? */
3742 temp_fill = get_absolute_expression ();
3743 if ( ! need_pass_2 ) /* Never make frag if expect extra pass. */
3744 frag_align (temp, (int)temp_fill);
3745 demand_empty_rest_of_line();
3746 } /* s_even() */
3747
3748 static void s_proc() {
3749 demand_empty_rest_of_line();
3750 } /* s_proc() */
3751
3752 /* s_space is defined in read.c .skip is simply an alias to it. */
3753
3754 /*
3755 * md_parse_option
3756 * Invocation line includes a switch not recognized by the base assembler.
3757 * See if it's a processor-specific option. These are:
3758 *
3759 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
3760 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
3761 * Select the architecture. Instructions or features not
3762 * supported by the selected architecture cause fatal
3763 * errors. More than one may be specified. The default is
3764 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
3765 * for -m68000, and -m68882 is a synonym for -m68881.
3766 *
3767 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
3768 * (e.g. m68020) also requests that float instructions be included. This
3769 * is the default setup, mostly to avoid hassling users. A better
3770 * rearrangement of this structure would be to add an option to DENY
3771 * floating point opcodes, for people who want to really know there's none
3772 * of that funny floaty stuff going on. FIXME-later.
3773 */
3774 #ifndef MAYBE_FLOAT_TOO
3775 #define MAYBE_FLOAT_TOO m68881
3776 #endif
3777
3778 int md_parse_option(argP,cntP,vecP)
3779 char **argP;
3780 int *cntP;
3781 char ***vecP;
3782 {
3783 switch(**argP) {
3784 case 'l': /* -l means keep external to 2 bit offset
3785 rather than 16 bit one */
3786 break;
3787
3788 case 'S': /* -S means that jbsr's always turn into jsr's. */
3789 break;
3790
3791 case 'A':
3792 (*argP)++;
3793 /* intentional fall-through */
3794 case 'm':
3795 (*argP)++;
3796
3797 if (**argP=='c') {
3798 (*argP)++;
3799 } /* allow an optional "c" */
3800
3801 if (!strcmp(*argP, "68000")
3802 || !strcmp(*argP, "68008")) {
3803 current_architecture |= m68000;
3804 } else if (!strcmp(*argP, "68010")) {
3805 #ifdef TE_SUN
3806 omagic= 1<<16|OMAGIC;
3807 #endif
3808 current_architecture |= m68010;
3809
3810 } else if (!strcmp(*argP, "68020")) {
3811 current_architecture |= m68020 | MAYBE_FLOAT_TOO;
3812
3813 } else if (!strcmp(*argP, "68030")) {
3814 current_architecture |= m68030 | MAYBE_FLOAT_TOO;
3815
3816 } else if (!strcmp(*argP, "68040")) {
3817 current_architecture |= m68040 | MAYBE_FLOAT_TOO;
3818
3819 #ifndef NO_68881
3820 } else if (!strcmp(*argP, "68881")) {
3821 current_architecture |= m68881;
3822
3823 } else if (!strcmp(*argP, "68882")) {
3824 current_architecture |= m68882;
3825
3826 #endif /* NO_68881 */
3827 #ifndef NO_68851
3828 } else if (!strcmp(*argP,"68851")) {
3829 current_architecture |= m68851;
3830
3831 #endif /* NO_68851 */
3832 } else {
3833 as_warn("Unknown architecture, \"%s\". option ignored", *argP);
3834 } /* switch on architecture */
3835
3836 while(**argP) (*argP)++;
3837
3838 break;
3839
3840 case 'p':
3841 if (!strcmp(*argP,"pic")) {
3842 (*argP) += 3;
3843 break; /* -pic, Position Independent Code */
3844 } else {
3845 return(0);
3846 } /* pic or not */
3847
3848 default:
3849 return 0;
3850 }
3851 return 1;
3852 }
3853
3854
3855 #ifdef TEST2
3856
3857 /* TEST2: Test md_assemble() */
3858 /* Warning, this routine probably doesn't work anymore */
3859
3860 main()
3861 {
3862 struct m68k_it the_ins;
3863 char buf[120];
3864 char *cp;
3865 int n;
3866
3867 m68k_ip_begin();
3868 for(;;) {
3869 if(!gets(buf) || !*buf)
3870 break;
3871 if(buf[0]=='|' || buf[1]=='.')
3872 continue;
3873 for(cp=buf;*cp;cp++)
3874 if(*cp=='\t')
3875 *cp=' ';
3876 if(is_label(buf))
3877 continue;
3878 memset(&the_ins, '\0', sizeof(the_ins));
3879 m68k_ip(&the_ins,buf);
3880 if(the_ins.error) {
3881 printf("Error %s in %s\n",the_ins.error,buf);
3882 } else {
3883 printf("Opcode(%d.%s): ",the_ins.numo,the_ins.args);
3884 for(n=0;n<the_ins.numo;n++)
3885 printf(" 0x%x",the_ins.opcode[n]&0xffff);
3886 printf(" ");
3887 print_the_insn(&the_ins.opcode[0],stdout);
3888 (void)putchar('\n');
3889 }
3890 for(n=0;n<strlen(the_ins.args)/2;n++) {
3891 if(the_ins.operands[n].error) {
3892 printf("op%d Error %s in %s\n",n,the_ins.operands[n].error,buf);
3893 continue;
3894 }
3895 printf("mode %d, reg %d, ",the_ins.operands[n].mode,the_ins.operands[n].reg);
3896 if(the_ins.operands[n].b_const)
3897 printf("Constant: '%.*s', ",1+the_ins.operands[n].e_const-the_ins.operands[n].b_const,the_ins.operands[n].b_const);
3898 printf("ireg %d, isiz %d, imul %d, ",the_ins.operands[n].ireg,the_ins.operands[n].isiz,the_ins.operands[n].imul);
3899 if(the_ins.operands[n].b_iadd)
3900 printf("Iadd: '%.*s',",1+the_ins.operands[n].e_iadd-the_ins.operands[n].b_iadd,the_ins.operands[n].b_iadd);
3901 (void)putchar('\n');
3902 }
3903 }
3904 m68k_ip_end();
3905 return 0;
3906 }
3907
3908 is_label(str)
3909 char *str;
3910 {
3911 while(*str==' ')
3912 str++;
3913 while(*str && *str!=' ')
3914 str++;
3915 if(str[-1]==':' || str[1]=='=')
3916 return 1;
3917 return 0;
3918 }
3919
3920 #endif
3921
3922 /* Possible states for relaxation:
3923
3924 0 0 branch offset byte (bra, etc)
3925 0 1 word
3926 0 2 long
3927
3928 1 0 indexed offsets byte a0@(32,d4:w:1) etc
3929 1 1 word
3930 1 2 long
3931
3932 2 0 two-offset index word-word a0@(32,d4)@(45) etc
3933 2 1 word-long
3934 2 2 long-word
3935 2 3 long-long
3936
3937 */
3938
3939
3940
3941 #ifdef DONTDEF
3942 abort()
3943 {
3944 printf("ABORT!\n");
3945 exit(12);
3946 }
3947
3948 print_frags()
3949 {
3950 fragS *fragP;
3951 extern fragS *text_frag_root;
3952
3953 for(fragP=text_frag_root;fragP;fragP=fragP->fr_next) {
3954 printf("addr %lu next 0x%x fix %ld var %ld symbol 0x%x offset %ld\n",
3955 fragP->fr_address,fragP->fr_next,fragP->fr_fix,fragP->fr_var,fragP->fr_symbol,fragP->fr_offset);
3956 printf("opcode 0x%x type %d subtype %d\n\n",fragP->fr_opcode,fragP->fr_type,fragP->fr_subtype);
3957 }
3958 fflush(stdout);
3959 return 0;
3960 }
3961 #endif
3962
3963 #ifdef DONTDEF
3964 /*VARARGS1*/
3965 panic(format,args)
3966 char *format;
3967 {
3968 fputs("Internal error:",stderr);
3969 _doprnt(format,&args,stderr);
3970 (void)putc('\n',stderr);
3971 as_where();
3972 abort();
3973 }
3974 #endif
3975
3976 /* We have no need to default values of symbols. */
3977
3978 /* ARGSUSED */
3979 symbolS *
3980 md_undefined_symbol (name)
3981 char *name;
3982 {
3983 return 0;
3984 }
3985
3986 /* Parse an operand that is machine-specific.
3987 We just return without modifying the expression if we have nothing
3988 to do. */
3989
3990 /* ARGSUSED */
3991 void
3992 md_operand (expressionP)
3993 expressionS *expressionP;
3994 {
3995 }
3996
3997 /* Round up a section size to the appropriate boundary. */
3998 long
3999 md_section_align (segment, size)
4000 segT segment;
4001 long size;
4002 {
4003 return size; /* Byte alignment is fine */
4004 }
4005
4006 /* Exactly what point is a PC-relative offset relative TO?
4007 On the 68k, they're relative to the address of the offset, plus
4008 its size. (??? Is this right? FIXME-SOON!) */
4009 long
4010 md_pcrel_from (fixP)
4011 fixS *fixP;
4012 {
4013 return(fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address);
4014 }
4015
4016 /*
4017 * Local Variables:
4018 * comment-column: 0
4019 * fill-column: 131
4020 * End:
4021 */
4022
4023 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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