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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
2 slow to compile, easy to find file.
3
4 Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21
22 #include <ctype.h>
23 #define NO_RELOC 0
24 #include "as.h"
25 #include "read.h"
26
27 #include "obstack.h"
28
29 /* note that this file includes real declarations and thus can only be included by one source file per executable. */
30 #include "opcode/m68k.h"
31
32 #ifdef TE_SUN
33 /* This variable contains the value to write out at the beginning of
34 the a.out file. The 2<<16 means that this is a 68020 file instead
35 of an old-style 68000 file */
36
37 long omagic = 2<<16|OMAGIC; /* Magic byte for header file */
38 #else
39 long omagic = OMAGIC;
40 #endif
41
42 /* This array holds the chars that always start a comment. If the
43 pre-processor is disabled, these aren't very useful */
44 const char comment_chars[] = "|";
45
46 /* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49 /* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52 /* Also note that comments like this one will always work. */
53 const char line_comment_chars[] = "#";
54
55 /* Chars that can be used to separate mant from exp in floating point nums */
56 const char EXP_CHARS[] = "eE";
57
58 /* Chars that mean this number is a floating point constant */
59 /* As in 0f12.456 */
60 /* or 0d1.2345e12 */
61
62 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
63
64 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
65 changed in read.c . Ideally it shouldn't have to know about it at all,
66 but nothing is ideal around here.
67 */
68
69 int md_reloc_size = 8; /* Size of relocation record */
70
71 /* Its an arbitrary name: This means I don't approve of it */
72 /* See flames below */
73 static struct obstack robyn;
74
75 #define TAB(x,y) (((x)<<2)+(y))
76 #define TABTYPE(xy) ((xy) >> 2)
77 #define BYTE 0
78 #define SHORT 1
79 #define LONG 2
80 #define SZ_UNDEF 3
81 #undef BRANCH
82 #define ABRANCH 1
83 #define FBRANCH 2
84 #define PCREL 3
85 #define BCC68000 4
86 #define DBCC 5
87 #define PCLEA 6
88
89 /* Operands we can parse: (And associated modes)
90
91 numb: 8 bit num
92 numw: 16 bit num
93 numl: 32 bit num
94 dreg: data reg 0-7
95 reg: address or data register
96 areg: address register
97 apc: address register, PC, ZPC or empty string
98 num: 16 or 32 bit num
99 num2: like num
100 sz: w or l if omitted, l assumed
101 scale: 1 2 4 or 8 if omitted, 1 assumed
102
103 7.4 IMMED #num --> NUM
104 0.? DREG dreg --> dreg
105 1.? AREG areg --> areg
106 2.? AINDR areg@ --> *(areg)
107 3.? AINC areg@+ --> *(areg++)
108 4.? ADEC areg@- --> *(--areg)
109 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
110 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
111 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
112 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
113 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
114 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
115 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
116 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
117 7.0 ABSL num:sz --> *(num)
118 num --> *(num) (sz L assumed)
119 *** MSCR otherreg --> Magic
120 With -l option
121 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
122 ?.? DINDR dreg@ --> (dreg) -- cas2 only
123
124 examples:
125 #foo #0x35 #12
126 d2
127 a4
128 a3@
129 a5@+
130 a6@-
131 a2@(12) pc@(14)
132 a1@(5,d2:w:1) @(45,d6:l:4)
133 pc@(a2) @(d4)
134 etc . . .
135
136
137 #name@(numw) -->turn into PC rel mode
138 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
139
140 */
141
142 enum operand_type {
143 IMMED = 1,
144 DREG,
145 AREG,
146 AINDR,
147 ADEC,
148 AINC,
149 AOFF,
150 AINDX,
151 APODX,
152 AMIND,
153 APRDX,
154 ABSL,
155 MSCR,
156 REGLST,
157 DINDR
158 };
159
160
161 struct m68k_exp {
162 char *e_beg;
163 char *e_end;
164 expressionS e_exp;
165 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
166 };
167
168 /* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
169 8-15==addr reg for operands that take both types */
170
171 enum _register {
172 DATA = 1, /* 1- 8 == data registers 0-7 */
173 DATA0 = DATA,
174 DATA1,
175 DATA2,
176 DATA3,
177 DATA4,
178 DATA5,
179 DATA6,
180 DATA7,
181
182 ADDR,
183 ADDR0 = ADDR,
184 ADDR1,
185 ADDR2,
186 ADDR3,
187 ADDR4,
188 ADDR5,
189 ADDR6,
190 ADDR7,
191
192 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
193 /* I think. . . */
194
195 SP = ADDR7,
196
197 FPREG, /* Eight FP registers */
198 FP0 = FPREG,
199 FP1,
200 FP2,
201 FP3,
202 FP4,
203 FP5,
204 FP6,
205 FP7,
206 COPNUM = (FPREG+8), /* Co-processor #1-#8 */
207 COP0 = COPNUM,
208 COP1,
209 COP2,
210 COP3,
211 COP4,
212 COP5,
213 COP6,
214 COP7,
215 PC, /* Program counter */
216 ZPC, /* Hack for Program space, but 0 addressing */
217 SR, /* Status Reg */
218 CCR, /* Condition code Reg */
219
220 /* These have to be in order for the movec instruction to work. */
221 USP, /* User Stack Pointer */
222 ISP, /* Interrupt stack pointer */
223 SFC,
224 DFC,
225 CACR,
226 VBR,
227 CAAR,
228 MSP,
229 ITT0,
230 ITT1,
231 DTT0,
232 DTT1,
233 MMUSR,
234 TC,
235 SRP,
236 URP,
237 /* end of movec ordering constraints */
238
239 FPI,
240 FPS,
241 FPC,
242
243 DRP, /* 68851 or 68030 MMU regs */
244 CRP,
245 CAL,
246 VAL,
247 SCC,
248 AC,
249 BAD,
250 BAD0 = BAD,
251 BAD1,
252 BAD2,
253 BAD3,
254 BAD4,
255 BAD5,
256 BAD6,
257 BAD7,
258 BAC,
259 BAC0 = BAC,
260 BAC1,
261 BAC2,
262 BAC3,
263 BAC4,
264 BAC5,
265 BAC6,
266 BAC7,
267 PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040)
268 and ACUSR on 68ec030 */
269 PCSR,
270
271 IC, /* instruction cache token */
272 DC, /* data cache token */
273 NC, /* no cache token */
274 BC, /* both caches token */
275
276 TT0, /* 68030 access control unit regs */
277 TT1,
278 };
279
280 /* Internal form of an operand. */
281 struct m68k_op {
282 char *error; /* Couldn't parse it */
283 enum operand_type mode; /* What mode this instruction is in. */
284 enum _register reg; /* Base register */
285 struct m68k_exp *con1;
286 int ireg; /* Index register */
287 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
288 int imul; /* Multipy ireg by this (1,2,4,or 8) */
289 struct m68k_exp *con2;
290 };
291
292 /* internal form of a 68020 instruction */
293 struct m68k_it {
294 char *error;
295 char *args; /* list of opcode info */
296 int numargs;
297
298 int numo; /* Number of shorts in opcode */
299 short opcode[11];
300
301 struct m68k_op operands[6];
302
303 int nexp; /* number of exprs in use */
304 struct m68k_exp exprs[4];
305
306 int nfrag; /* Number of frags we have to produce */
307 struct {
308 int fragoff; /* Where in the current opcode[] the frag ends */
309 symbolS *fadd;
310 long foff;
311 int fragty;
312 } fragb[4];
313
314 int nrel; /* Num of reloc strucs in use */
315 struct {
316 int n;
317 symbolS *add,
318 *sub;
319 long off;
320 char wid;
321 char pcrel;
322 } reloc[5]; /* Five is enough??? */
323 };
324
325 #define cpu_of_arch(x) ((x) & m68000up)
326 #define float_of_arch(x) ((x) & mfloat)
327 #define mmu_of_arch(x) ((x) & mmmu)
328
329 static struct m68k_it the_ins; /* the instruction being assembled */
330
331 /* Macros for adding things to the m68k_it struct */
332
333 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
334
335 /* Like addword, but goes BEFORE general operands */
336 #define insop(w) {int z;\
337 for(z=the_ins.numo;z>opcode->m_codenum;--z)\
338 the_ins.opcode[z]=the_ins.opcode[z-1];\
339 for(z=0;z<the_ins.nrel;z++)\
340 the_ins.reloc[z].n+=2;\
341 the_ins.opcode[opcode->m_codenum]=w;\
342 the_ins.numo++;\
343 }
344
345
346 #define add_exp(beg,end) (\
347 the_ins.exprs[the_ins.nexp].e_beg=beg,\
348 the_ins.exprs[the_ins.nexp].e_end=end,\
349 &the_ins.exprs[the_ins.nexp++]\
350 )
351
352
353 /* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/
354 #define add_fix(width,exp,pc_rel) {\
355 the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \
356 (((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\
357 the_ins.reloc[the_ins.nrel].add=adds((exp));\
358 the_ins.reloc[the_ins.nrel].sub=subs((exp));\
359 the_ins.reloc[the_ins.nrel].off=offs((exp));\
360 the_ins.reloc[the_ins.nrel].wid=width;\
361 the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\
362 }
363
364 #define add_frag(add,off,type) {\
365 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\
366 the_ins.fragb[the_ins.nfrag].fadd=add;\
367 the_ins.fragb[the_ins.nfrag].foff=off;\
368 the_ins.fragb[the_ins.nfrag++].fragty=type;\
369 }
370
371 #define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
372
373 #define seg(exp) ((exp)->e_exp.X_seg)
374 #define adds(exp) ((exp)->e_exp.X_add_symbol)
375 #define subs(exp) ((exp)->e_exp.X_subtract_symbol)
376 #define offs(exp) ((exp)->e_exp.X_add_number)
377
378
379 struct m68k_incant {
380 char *m_operands;
381 unsigned long m_opcode;
382 short m_opnum;
383 short m_codenum;
384 enum m68k_architecture m_arch;
385 struct m68k_incant *m_next;
386 };
387
388
389
390 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
391 #define gettwo(x) (((x)->m_opcode)&0xffff)
392
393
394 #if __STDC__ == 1
395
396 static char *crack_operand(char *str, struct m68k_op *opP);
397 static int get_num(struct m68k_exp *exp, int ok);
398 static int get_regs(int i, char *str, struct m68k_op *opP);
399 static int reverse_16_bits(int in);
400 static int reverse_8_bits(int in);
401 static int try_index(char **s, struct m68k_op *opP);
402 static void install_gen_operand(int mode, int val);
403 static void install_operand(int mode, int val);
404 static void s_bss(void);
405 static void s_data1(void);
406 static void s_data2(void);
407 static void s_even(void);
408 static void s_proc(void);
409
410 #else /* not __STDC__ */
411
412 static char *crack_operand();
413 static int get_num();
414 static int get_regs();
415 static int reverse_16_bits();
416 static int reverse_8_bits();
417 static int try_index();
418 static void install_gen_operand();
419 static void install_operand();
420 static void s_bss();
421 void s_align_bytes();
422 static void s_data1();
423 static void s_data2();
424 static void s_even();
425 static void s_proc();
426
427 #endif /* not __STDC__ */
428
429 static enum m68k_architecture current_architecture = 0;
430
431 /* BCC68000 is for patching in an extra jmp instruction for long offsets
432 on the 68000. The 68000 doesn't support long branches with branchs */
433
434 /* This table desribes how you change sizes for the various types of variable
435 size expressions. This version only supports two kinds. */
436
437 /* Note that calls to frag_var need to specify the maximum expansion needed */
438 /* This is currently 10 bytes for DBCC */
439
440 /* The fields are:
441 How far Forward this mode will reach:
442 How far Backward this mode will reach:
443 How many bytes this mode will add to the size of the frag
444 Which mode to go to if the offset won't fit in this one
445 */
446 const relax_typeS
447 md_relax_table[] = {
448 { 1, 1, 0, 0 }, /* First entries aren't used */
449 { 1, 1, 0, 0 }, /* For no good reason except */
450 { 1, 1, 0, 0 }, /* that the VAX doesn't either */
451 { 1, 1, 0, 0 },
452
453 { (127), (-128), 0, TAB(ABRANCH,SHORT)},
454 { (32767), (-32768), 2, TAB(ABRANCH,LONG) },
455 { 0, 0, 4, 0 },
456 { 1, 1, 0, 0 },
457
458 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
459 { (32767), (-32768), 2, TAB(FBRANCH,LONG)},
460 { 0, 0, 4, 0 },
461 { 1, 1, 0, 0 },
462
463 { 1, 1, 0, 0 }, /* PCREL doesn't come BYTE */
464 { (32767), (-32768), 2, TAB(PCREL,LONG)},
465 { 0, 0, 4, 0 },
466 { 1, 1, 0, 0 },
467
468 { (127), (-128), 0, TAB(BCC68000,SHORT)},
469 { (32767), (-32768), 2, TAB(BCC68000,LONG) },
470 { 0, 0, 6, 0 }, /* jmp long space */
471 { 1, 1, 0, 0 },
472
473 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
474 { (32767), (-32768), 2, TAB(DBCC,LONG) },
475 { 0, 0, 10, 0 }, /* bra/jmp long space */
476 { 1, 1, 0, 0 },
477
478 { 1, 1, 0, 0 }, /* PCLEA doesn't come BYTE */
479 { 32767, -32768, 2, TAB(PCLEA,LONG) },
480 { 0, 0, 6, 0 },
481 { 1, 1, 0, 0 },
482
483 };
484
485 /* These are the machine dependent pseudo-ops. These are included so
486 the assembler can work on the output from the SUN C compiler, which
487 generates these.
488 */
489
490 /* This table describes all the machine specific pseudo-ops the assembler
491 has to support. The fields are:
492 pseudo-op name without dot
493 function to call to execute this pseudo-op
494 Integer arg to pass to the function
495 */
496 const pseudo_typeS md_pseudo_table[] = {
497 { "data1", s_data1, 0 },
498 { "data2", s_data2, 0 },
499 { "bss", s_bss, 0 },
500 { "even", s_even, 0 },
501 { "skip", s_space, 0 },
502 { "proc", s_proc, 0 },
503 #ifdef TE_SUN3
504 { "align", s_align_bytes, 0 },
505 #endif
506 { 0, 0, 0 }
507 };
508
509
510 /* The mote pseudo ops are put into the opcode table, since they
511 don't start with a . they look like opcodes to gas.
512 */
513 extern void obj_coff_section();
514
515 const pseudo_typeS mote_pseudo_table[] =
516 {
517
518 { "dc.l", cons,4},
519 { "dc", cons,2},
520 { "dc.w", cons,2},
521 { "dc.b", cons,1},
522
523 { "ds.l", s_space,4},
524 { "ds", s_space,2},
525 { "ds.w", s_space,2},
526 { "ds.b", s_space,1},
527
528 { "xdef", s_globl, 0},
529 { "align", s_align_ptwo, 0},
530 #ifdef M68KCOFF
531 { "sect", obj_coff_section,0},
532 { "section", obj_coff_section,0},
533 #endif
534 0,
535 };
536
537 /* #define isbyte(x) ((x)>=-128 && (x)<=127) */
538 /* #define isword(x) ((x)>=-32768 && (x)<=32767) */
539
540 #define issbyte(x) ((x)>=-128 && (x)<=127)
541 #define isubyte(x) ((x)>=0 && (x)<=255)
542 #define issword(x) ((x)>=-32768 && (x)<=32767)
543 #define isuword(x) ((x)>=0 && (x)<=65535)
544
545 #define isbyte(x) ((x)>=-128 && (x)<=255)
546 #define isword(x) ((x)>=-32768 && (x)<=65535)
547 #define islong(x) (1)
548
549 extern char *input_line_pointer;
550
551 enum {
552 FAIL = 0,
553 OK = 1,
554 };
555
556 /* JF these tables here are for speed at the expense of size */
557 /* You can replace them with the #if 0 versions if you really
558 need space and don't mind it running a bit slower */
559
560 static char mklower_table[256];
561 #define mklower(c) (mklower_table[(unsigned char)(c)])
562 static char notend_table[256];
563 static char alt_notend_table[256];
564 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
565 alt_notend_table[(unsigned char)(s[1])])))
566
567 #if 0
568 #define mklower(c) (isupper(c) ? tolower(c) : c)
569 #endif
570
571
572 /* JF modified this to handle cases where the first part of a symbol name
573 looks like a register */
574
575 /*
576 * m68k_reg_parse() := if it looks like a register, return it's token &
577 * advance the pointer.
578 */
579
580 enum _register m68k_reg_parse(ccp)
581 register char **ccp;
582 {
583 char *start = *ccp;
584
585 if (isalpha(*start) && is_name_beginner(*start))
586 {
587 char c;
588 char *p = start;
589 symbolS *symbolP;
590
591 c = *p++;
592 while (isalpha(c) || isdigit(c))
593 {
594 c = *p++;
595 }
596
597 ;
598 * -- p = 0;
599 symbolP = symbol_find(start);
600 *p = c;
601
602 if (symbolP && S_GET_SEGMENT(symbolP) == SEG_REGISTER)
603 {
604 *ccp = p;
605 return S_GET_VALUE(symbolP);
606 }
607 }
608 return FAIL;
609
610
611 }
612
613 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
614 #define SKIP_W() { ss++; if(*ss==' ') ss++;}
615
616 /* Parse an index specification using Motorola syntax. */
617
618 static int
619 try_moto_index(s,opP)
620 char **s;
621 struct m68k_op *opP;
622 {
623 register int i;
624 char *ss;
625
626 ss= *s;
627 /* SKIP_W(); */
628 if(*ss==' ') ss++;
629 i=m68k_reg_parse(&ss);
630 if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */
631 opP->error="Invalid index register";
632 *s=ss;
633 return FAIL;
634 }
635 opP->ireg=i;
636 /* SKIP_W(); */
637 if(*ss==')') {
638 opP->isiz=0;
639 opP->imul=1;
640 SKIP_W();
641 *s=ss;
642 return OK;
643 }
644 if(*ss!='.') {
645 opP->error="Missing . in index register";
646 *s=ss;
647 return FAIL;
648 }
649 SKIP_W();
650 if(mklower(*ss)=='w') opP->isiz=2;
651 else if(mklower(*ss)=='l') opP->isiz=3;
652 else {
653 opP->error="Size spec not .W or .L";
654 *s=ss;
655 return FAIL;
656 }
657 SKIP_W();
658 if(*ss=='.' || *ss=='*') {
659 SKIP_W();
660 switch(*ss) {
661 case '1':
662 case '2':
663 case '4':
664 case '8':
665 opP->imul= *ss-'0';
666 break;
667 default:
668 opP->error="index multiplier not 1, 2, 4 or 8";
669 *s=ss;
670 return FAIL;
671 }
672 SKIP_W();
673 } else opP->imul=1;
674 if(*ss!=')') {
675 opP->error="Missing )";
676 *s=ss;
677 return FAIL;
678 }
679 SKIP_W();
680 *s=ss;
681 return OK;
682 }
683
684 /*
685 *
686 * try_index := data_or_address_register + ')' + SKIP_W
687 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
688 *
689 * multiplier := <empty>
690 * | ':' + multiplier_number
691 * ;
692 *
693 * multiplier_number := '1' | '2' | '4' | '8' ;
694 *
695 * size_spec := 'l' | 'L' | 'w' | 'W' ;
696 *
697 * SKIP_W := <empty> | ' ' ;
698 *
699 */
700
701 static int try_index(s,opP)
702 char **s;
703 struct m68k_op *opP;
704 {
705 register int i;
706 char *ss;
707
708 ss= *s;
709 /* SKIP_W(); */
710 i=m68k_reg_parse(&ss);
711 if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */
712 *s=ss;
713 return FAIL;
714 }
715 opP->ireg=i;
716 /* SKIP_W(); */
717 if(*ss==')') {
718 opP->isiz=0;
719 opP->imul=1;
720 SKIP_W();
721 *s=ss;
722 return OK;
723 }
724 if(*ss!=':') {
725 opP->error="Missing : in index register";
726 *s=ss;
727 return FAIL;
728 }
729 SKIP_W();
730 switch(*ss) {
731 case 'w':
732 case 'W':
733 opP->isiz=2;
734 break;
735 case 'l':
736 case 'L':
737 opP->isiz=3;
738 break;
739 default:
740 opP->error="Index register size spec not :w or :l";
741 *s=ss;
742 return FAIL;
743 }
744 SKIP_W();
745 if(*ss==':') {
746 SKIP_W();
747 switch(*ss) {
748 case '1':
749 case '2':
750 case '4':
751 case '8':
752 if (cpu_of_arch(current_architecture) < m68020) {
753 opP->error="no index scaling in pre-68020's";
754 *s=ss;
755 return FAIL;
756 }
757 opP->imul= *ss-'0';
758 break;
759 default:
760 opP->error="index multiplier not 1, 2, 4 or 8";
761 *s=ss;
762 return FAIL;
763 }
764 SKIP_W();
765 } else opP->imul=1;
766 if(*ss!=')') {
767 opP->error="Missing )";
768 *s=ss;
769 return FAIL;
770 }
771 SKIP_W();
772 *s=ss;
773 return OK;
774 } /* try_index() */
775
776 /* Ian Taylor expanded this function to accept both MIT and Motorola
777 syntax. I removed the old comment, since it was wrong. The syntax
778 this accepted even before my changes was complex and undocumented.
779 I mainly added a large case when the operand string does not
780 contain an '@', since the Motorola syntax does not use the '@'
781 character. */
782
783 int
784 m68k_ip_op(str,opP)
785 char *str;
786 register struct m68k_op *opP;
787 {
788 char *strend;
789 long i;
790 char *parse_index();
791 int needp;
792
793 if (*str==' ') {
794 str++;
795 } /* Find the beginning of the string */
796
797 if(!*str) {
798 opP->error="Missing operand";
799 return FAIL;
800 } /* Out of gas */
801
802 for(strend = str; *strend; strend++)
803 ;
804 --strend;
805
806 if(*str=='#') {
807 str++;
808 opP->con1=add_exp(str,strend);
809 opP->mode=IMMED;
810 return OK;
811 } /* Guess what: A constant. Shar and enjoy */
812
813 i = m68k_reg_parse(&str);
814
815 if (i!=FAIL) {
816 if(*str=='/' || *str=='-') {
817 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
818 opP->mode=REGLST;
819 return get_regs(i,str,opP);
820 }
821 if(*str=='\0') {
822 opP->reg=i;
823 /* "Rn" Register Direct mode */
824 if(i>=DATA+0 && i<=DATA+7)
825 opP->mode=DREG;
826 else if(i>=ADDR+0 && i<=ADDR+7)
827 opP->mode=AREG;
828 else
829 opP->mode=MSCR;
830 return OK;
831 }
832 }
833
834 if (*str!='@') {
835 char *stmp;
836
837 if ((stmp=strchr(str,'@')) != 0) {
838 opP->con1=add_exp(str,stmp-1);
839 if(stmp==strend) {
840 opP->mode=AINDX;
841 return(OK);
842 }
843
844 if ((current_architecture & m68020up) == 0) {
845 return(FAIL);
846 } /* if target is not a '20 or better */
847
848 stmp++;
849 if(*stmp++!='(' || *strend--!=')') {
850 opP->error="Malformed operand";
851 return(FAIL);
852 }
853 i=try_index(&stmp,opP);
854 opP->con2=add_exp(stmp,strend);
855
856 if (i == FAIL) {
857 opP->mode=AMIND;
858 } else {
859 opP->mode=APODX;
860 }
861 return(OK);
862 } /* if there's an '@' */
863
864 #ifndef MIT_SYNTAX_ONLY
865 /* The operand has no '@'. Try to parse it using
866 Motorola syntax. */
867 /* Logic of the parsing switch(*str):
868 case opP->mode =
869 ---- -----------
870 #anything IMMED 1
871 REG AREG or DREG or MSCR 3 or 2 or 13
872 REG- or REG/ REGLST 14
873 (REG) AINDR 4
874 (REG)+ AINC 6
875 (REG,INDX) AINDX 8
876 (EXPR,REG) AOFF 7
877 (EXPR,REG,INDX) AINDX 8
878 -(REG) ADEC 5
879 EXP2(REG) AOFF 7
880 EXP2(REG,INDX) AINDX 8
881 EXP2 ABSL 12
882
883 REG means truth(m68k_reg_parse(&str))
884 INDX means truth(try_moto_index(&str,opP))
885 EXPR means not REG
886 EXP2 means not REG and not '(' and not '-('
887 */
888
889 if(*str=='(') {
890 str++;
891 i=m68k_reg_parse(&str);
892 if((i<ADDR+0 || i>ADDR+7)
893 && (i<DATA+0 || i>DATA+7
894 || *str != ')' || str[1] != '0')
895 && i!=PC && i!=ZPC && i!=FAIL) {
896 /* Can't indirect off non address regs */
897 opP->error="Invalid indirect register";
898 return FAIL;
899 }
900 if(i!=FAIL) {
901 opP->reg=i;
902 if(*str==')') {
903 str++;
904 if(*str=='\0') {
905 /* "(An)" Address Register Indirect mode
906 or "(Dn)" for cas2. */
907 if (i>=DATA+0 && i<=DATA+7)
908 opP->mode=DINDR;
909 else
910 opP->mode=AINDR;
911 return OK;
912 }
913 if(*str=='+') {
914 if(str[1]=='\0') {
915 /* "(An)+" Register Indirect w Postincrement */
916 opP->mode=AINC;
917 return OK;
918 }
919 }
920 opP->error="Junk after indirect";
921 return FAIL;
922 }
923 if(*str==',') {
924 str++;
925 i=try_moto_index(&str,opP);
926 if(i==FAIL) return FAIL;
927 /* "(An,Rn)" Register Indirect with Index mode*/
928 opP->mode=AINDX;
929 return OK;
930 }
931 else {
932 opP->error="Bad indirect syntax";
933 return FAIL;
934 }
935 }
936 else {
937 /* "(EXPR,..." , a displacement */
938 char *stmp;
939 char *index();
940
941 if(stmp=index(str,',')) {
942 opP->con1=add_exp(str,stmp-1);
943 str=stmp;
944 SKIP_WHITE();
945 i=m68k_reg_parse(&str);
946 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC) {
947 /* Can't indirect off non address regs */
948 opP->error="Invalid indirect register";
949 return FAIL;
950 }
951 if(i!=FAIL) {
952 opP->reg=i;
953 if(*str==')') {
954 /* "(d,An)" Register Indirect w Displacement */
955 opP->mode=AOFF;
956 return OK;
957 }
958 if(*str==',') {
959 str++;
960 i=try_moto_index(&str,opP);
961 if(i==FAIL) return FAIL;
962 /* "(d,An,Rn)" Register Indirect with Index */
963 opP->mode=AINDX;
964 return OK;
965 }
966 else {
967 opP->error="Bad indirect syntax";
968 return FAIL;
969 }
970 }
971 else {
972 opP->error="Invalid register";
973 return FAIL;
974 }
975 }
976 else {
977 opP->mode = ABSL;
978 opP->con1 = add_exp(str-1,strend);
979 return OK;
980 }
981 }
982 }
983
984 if(*str=='-') {
985 if(str[1]=='(') {
986 str = str+2;
987 i=m68k_reg_parse(&str);
988 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL) {
989 /* Can't indirect off non address regs */
990 opP->error="Invalid indirect register";
991 return FAIL;
992 }
993 if(i!=FAIL) {
994 opP->reg=i;
995 if(*str==')') {
996 str++;
997 if(*str=='\0') {
998 /* "-(An)" Register Indirect with Predecrement */
999 opP->mode=ADEC;
1000 return OK;
1001 }
1002 opP->error="Junk after indirect";
1003 return FAIL;
1004 }
1005 opP->error="Bad indirect syntax";
1006 return FAIL;
1007 }
1008 opP->mode = ABSL;
1009 opP->con1 = add_exp(str-2,strend);
1010 return OK;
1011 }
1012 /* if '-' but not "-(', do nothing */
1013 }
1014
1015 /* whether *str=='-' or not */
1016 {
1017 /* "EXP2" or "EXP2(REG..." */
1018 char *stmp;
1019 char *index();
1020 if(stmp=index(str,'(')) {
1021 char *ostr=str;
1022
1023 opP->con1=add_exp(str,stmp-1);
1024 str=stmp+1;
1025 i=m68k_reg_parse(&str);
1026 if((i<ADDR+0 || i>ADDR+7) && i!=PC
1027 && i!=ZPC && i!=FAIL) {
1028 /* Can't indirect off non address regs */
1029 opP->error="Invalid indirect register";
1030 return FAIL;
1031 }
1032 if(i!=FAIL) {
1033 opP->reg=i;
1034 if(*str==')') {
1035 /* "d(An)" Register Indirect w Displacement */
1036 opP->mode=AOFF;
1037 return OK;
1038 }
1039 if(*str==',') {
1040 str++;
1041 i=try_moto_index(&str,opP);
1042 if(i==FAIL) return FAIL;
1043 /* "d(An,Rn)" Register Indirect with Index */
1044 opP->mode=AINDX;
1045 return OK;
1046 }
1047 else {
1048 opP->error="Bad indirect syntax";
1049 return FAIL;
1050 }
1051 }
1052 else {
1053 opP->mode = ABSL;
1054 opP->con1 = add_exp(ostr,strend);
1055 return OK;
1056 }
1057 }
1058 else {
1059 /* "EXP2" Absolute */
1060 opP->mode=ABSL;
1061 opP->isiz=0;
1062 if(strend[-1]=='.' || strend[-1]==':') {
1063 /* mode ==foo.[wl] */
1064 switch(*strend) {
1065 case 'w':
1066 case 'W':
1067 opP->isiz=2;
1068 strend-=2;
1069 break;
1070 case 'l':
1071 case 'L':
1072 opP->isiz=3;
1073 strend-=2;
1074 break;
1075 }
1076 }
1077 opP->con1=add_exp(str,strend);
1078 return OK;
1079 }
1080 }
1081 /*NOTREACHED*/
1082 #else /* defined (MIT_SYNTAX_ONLY) */
1083 opP->mode=ABSL;
1084 opP->con1=add_exp(str,strend);
1085 return OK;
1086 #endif /* defined (MIT_SYNTAX_ONLY) */
1087 }
1088
1089 opP->reg=i;
1090
1091 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1092 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL
1093 && (str[1] != '\0' || i<DATA+0 || i>DATA+7)) {
1094 opP->error="Invalid indirect register";
1095 return FAIL;
1096 }
1097 know(*str == '@');
1098
1099 str++;
1100 switch(*str) {
1101 case '\0':
1102 if (i<DATA+0 || i>DATA+7)
1103 opP->mode=AINDR;
1104 else
1105 opP->mode=DINDR;
1106 return OK;
1107 case '-':
1108 opP->mode=ADEC;
1109 return OK;
1110 case '+':
1111 opP->mode=AINC;
1112 return OK;
1113 case '(':
1114 str++;
1115 break;
1116 default:
1117 opP->error="Junk after indirect";
1118 return FAIL;
1119 }
1120 /* Some kind of indexing involved. Lets find out how bad it is */
1121 i=try_index(&str,opP);
1122 /* Didn't start with an index reg, maybe its offset or offset,reg */
1123 if(i==FAIL) {
1124 char *beg_str;
1125
1126 beg_str=str;
1127 for(i=1;i;) {
1128 switch(*str++) {
1129 case '\0':
1130 opP->error="Missing )";
1131 return FAIL;
1132 case ',': i=0; break;
1133 case '(': i++; break;
1134 case ')': --i; break;
1135 }
1136 }
1137 /* if(str[-3]==':') {
1138 int siz;
1139
1140 switch(str[-2]) {
1141 case 'b':
1142 case 'B':
1143 siz=1;
1144 break;
1145 case 'w':
1146 case 'W':
1147 siz=2;
1148 break;
1149 case 'l':
1150 case 'L':
1151 siz=3;
1152 break;
1153 default:
1154 opP->error="Specified size isn't :w or :l";
1155 return FAIL;
1156 }
1157 opP->con1=add_exp(beg_str,str-4);
1158 opP->con1->e_siz=siz;
1159 } else */
1160 opP->con1=add_exp(beg_str,str-2);
1161 /* Should be offset,reg */
1162 if(str[-1]==',') {
1163 i=try_index(&str,opP);
1164 if(i==FAIL) {
1165 opP->error="Malformed index reg";
1166 return FAIL;
1167 }
1168 }
1169 }
1170 /* We've now got offset) offset,reg) or reg) */
1171
1172 if (*str == '\0') {
1173 /* Th-the-thats all folks */
1174 if (opP->reg == FAIL) opP->mode = AINDX; /* Other form of indirect */
1175 else if(opP->ireg == FAIL) opP->mode = AOFF;
1176 else opP->mode = AINDX;
1177 return(OK);
1178 }
1179 /* Next thing had better be another @ */
1180 if (*str == '@') {
1181 if (str[1] == '(') {
1182 needp = 1;
1183 str+=2;
1184 }
1185 else {
1186 needp = 0;
1187 str++;
1188 }
1189 }
1190
1191 if ((current_architecture & m68020up) == 0) {
1192 return(FAIL);
1193 } /* if target is not a '20 or better */
1194
1195
1196 if(opP->ireg != FAIL) {
1197 opP->mode = APRDX;
1198
1199 i = try_index(&str, opP);
1200 if (i != FAIL) {
1201 opP->error = "Two index registers! not allowed!";
1202 return(FAIL);
1203 }
1204 } else {
1205 i = try_index(&str, opP);
1206 }
1207
1208 if (i == FAIL) {
1209 char *beg_str;
1210
1211 beg_str = str;
1212
1213 for (i = 1; i; ) {
1214 switch(*str++) {
1215 case '\0':
1216 if (needp)
1217 opP->error="Missing )";
1218 return(FAIL);
1219 break;
1220 case ',': i=0; break;
1221 case '(': i++; break;
1222 case ')': --i; break;
1223 }
1224 }
1225
1226 opP->con2=add_exp(beg_str,str-2);
1227
1228 if (str[-1] == ',') {
1229 if (opP->ireg != FAIL) {
1230 opP->error = "Can't have two index regs";
1231 return(FAIL);
1232 }
1233
1234 i = try_index(&str, opP);
1235
1236 if (i == FAIL) {
1237 opP->error = "malformed index reg";
1238 return(FAIL);
1239 }
1240
1241 opP->mode = APODX;
1242 } else if (opP->ireg != FAIL) {
1243 opP->mode = APRDX;
1244 } else {
1245 opP->mode = AMIND;
1246 }
1247 } else {
1248 opP->mode = APODX;
1249 }
1250
1251 if(*str!='\0') {
1252 opP->error="Junk after indirect";
1253 return FAIL;
1254 }
1255 return(OK);
1256 } /* m68k_ip_op() */
1257
1258
1259 #ifdef M68KCOFF
1260
1261 short tc_coff_fix2rtype(fixP)
1262 fixS *fixP;
1263 {
1264 return (fixP->fx_pcrel ?
1265 (fixP->fx_size == 1 ? R_PCRBYTE :
1266 fixP->fx_size == 2 ? R_PCRWORD :
1267 R_PCRLONG):
1268 (fixP->fx_size == 1 ? R_RELBYTE :
1269 fixP->fx_size == 2 ? R_RELWORD :
1270 R_RELLONG));
1271
1272
1273 }
1274
1275 #endif
1276
1277 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1278 main()
1279 {
1280 char buf[128];
1281 struct m68k_op thark;
1282
1283 for(;;) {
1284 if(!gets(buf))
1285 break;
1286 memset(&thark, '\0', sizeof(thark));
1287 if(!m68k_ip_op(buf,&thark)) printf("FAIL:");
1288 if(thark.error)
1289 printf("op1 error %s in %s\n",thark.error,buf);
1290 printf("mode %d, reg %d, ",thark.mode,thark.reg);
1291 if(thark.b_const)
1292 printf("Constant: '%.*s',",1+thark.e_const-thark.b_const,thark.b_const);
1293 printf("ireg %d, isiz %d, imul %d ",thark.ireg,thark.isiz,thark.imul);
1294 if(thark.b_iadd)
1295 printf("Iadd: '%.*s'",1+thark.e_iadd-thark.b_iadd,thark.b_iadd);
1296 printf("\n");
1297 }
1298 exit(0);
1299 }
1300
1301 #endif
1302
1303
1304 static struct hash_control* op_hash = NULL; /* handle of the OPCODE hash table
1305 NULL means any use before m68k_ip_begin()
1306 will crash */
1307
1308 \f
1309 /*
1310 * m 6 8 k _ i p ( )
1311 *
1312 * This converts a string into a 68k instruction.
1313 * The string must be a bare single instruction in sun format
1314 * with RMS-style 68020 indirects
1315 * (example: )
1316 *
1317 * It provides some error messages: at most one fatal error message (which
1318 * stops the scan) and at most one warning message for each operand.
1319 * The 68k instruction is returned in exploded form, since we have no
1320 * knowledge of how you parse (or evaluate) your expressions.
1321 * We do however strip off and decode addressing modes and operation
1322 * mnemonic.
1323 *
1324 * This function's value is a string. If it is not "" then an internal
1325 * logic error was found: read this code to assign meaning to the string.
1326 * No argument string should generate such an error string:
1327 * it means a bug in our code, not in the user's text.
1328 *
1329 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1330 * this function.
1331 */
1332
1333 /* JF this function no longer returns a useful value. Sorry */
1334 void m68k_ip (instring)
1335 char *instring;
1336 {
1337 register char *p;
1338 register struct m68k_op *opP;
1339 register struct m68k_incant *opcode;
1340 register char *s;
1341 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1342 char *pdot, *pdotmove;
1343 int siz1, siz2;
1344 char c;
1345 int losing;
1346 int opsfound;
1347 char *crack_operand();
1348 LITTLENUM_TYPE words[6];
1349 LITTLENUM_TYPE *wordp;
1350 unsigned long ok_arch = 0;
1351
1352 if (*instring == ' ')
1353 instring++; /* skip leading whitespace */
1354
1355 /* Scan up to end of operation-code, which MUST end in end-of-string
1356 or exactly 1 space. */
1357 pdot = 0;
1358 for (p = instring; *p != '\0'; p++) {
1359 if (*p == ' ')
1360 break;
1361 if (*p == '.')
1362 pdot = p;
1363 }
1364
1365 if (p == instring) {
1366 the_ins.error = "No operator";
1367 the_ins.opcode[0] = NULL;
1368 /* the_ins.numo=1; */
1369 return;
1370 }
1371
1372 /* p now points to the end of the opcode name, probably whitespace.
1373 make sure the name is null terminated by clobbering the whitespace,
1374 look it up in the hash table, then fix it back.
1375 Remove a dot, first, since the opcode tables have none. */
1376 if (pdot != NULL) {
1377 for (pdotmove=pdot; pdotmove<p; pdotmove++)
1378 *pdotmove=pdotmove[1];
1379 p--;
1380 }
1381
1382 c = *p;
1383 *p = '\0';
1384 opcode = (struct m68k_incant *)hash_find (op_hash, instring);
1385 *p = c;
1386
1387 if (pdot != NULL) {
1388 for (pdotmove=p; pdotmove>pdot; pdotmove--)
1389 *pdotmove=pdotmove[-1];
1390 *pdot='.';
1391 ++p;
1392 }
1393
1394 if (opcode == NULL) {
1395 the_ins.error = "Unknown operator";
1396 the_ins.opcode[0] = NULL;
1397 /* the_ins.numo=1; */
1398 return;
1399 }
1400
1401 /* found a legitimate opcode, start matching operands */
1402 while (*p == ' ') ++p;
1403
1404
1405 if (opcode->m_operands == 0) {
1406 char *old = input_line_pointer;
1407 *old = '\n';
1408 input_line_pointer = p;
1409 /* Ahh - it's a motorola style psuedo op */
1410 mote_pseudo_table[opcode->m_opnum].poc_handler
1411 ( mote_pseudo_table[opcode->m_opnum].poc_val);
1412 input_line_pointer = old;
1413 *old = 0;
1414
1415 return;
1416 }
1417
1418 for(opP = &the_ins.operands[0]; *p; opP++) {
1419
1420 p = crack_operand(p, opP);
1421
1422 if (opP->error) {
1423 the_ins.error=opP->error;
1424 return;
1425 }
1426 }
1427
1428 opsfound = opP - &the_ins.operands[0];
1429
1430 /* This ugly hack is to support the floating pt opcodes in their standard form */
1431 /* Essentially, we fake a first enty of type COP#1 */
1432 if (opcode->m_operands[0]=='I') {
1433 int n;
1434
1435 for(n=opsfound;n>0;--n)
1436 the_ins.operands[n]=the_ins.operands[n-1];
1437
1438 memset((char *)(&the_ins.operands[0]), '\0', sizeof(the_ins.operands[0]));
1439 the_ins.operands[0].mode=MSCR;
1440 the_ins.operands[0].reg=COPNUM; /* COP #1 */
1441 opsfound++;
1442 }
1443
1444 /* We've got the operands. Find an opcode that'll accept them */
1445 for (losing = 0; ; ) {
1446 /* if we didn't get the right number of ops,
1447 or we have no common model with this pattern
1448 then reject this pattern. */
1449
1450 if (opsfound != opcode->m_opnum
1451 || ((opcode->m_arch & current_architecture) == 0))
1452 {
1453 ++losing;
1454 ok_arch |= opcode->m_arch;
1455 }
1456 else {
1457 for (s=opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++) {
1458 /* Warning: this switch is huge! */
1459 /* I've tried to organize the cases into this order:
1460 non-alpha first, then alpha by letter. lower-case goes directly
1461 before uppercase counterpart. */
1462 /* Code with multiple case ...: gets sorted by the lowest case ...
1463 it belongs to. I hope this makes sense. */
1464 switch(*s) {
1465 case '!':
1466 if (opP->mode == MSCR || opP->mode == IMMED
1467 || opP->mode == DREG || opP->mode == AREG
1468 || opP->mode == AINC || opP->mode == ADEC
1469 || opP->mode == REGLST)
1470 losing++;
1471 break;
1472
1473 case '#':
1474 if(opP->mode!=IMMED)
1475 losing++;
1476 else {
1477 long t;
1478
1479 t=get_num(opP->con1,80);
1480 if(s[1]=='b' && !isbyte(t))
1481 losing++;
1482 else if(s[1]=='w' && !isword(t))
1483 losing++;
1484 }
1485 break;
1486
1487 case '^':
1488 case 'T':
1489 if(opP->mode!=IMMED)
1490 losing++;
1491 break;
1492
1493 case '$':
1494 if(opP->mode==MSCR || opP->mode==AREG ||
1495 opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1496 losing++;
1497 break;
1498
1499 case '%':
1500 if(opP->mode==MSCR || opP->reg==PC ||
1501 opP->reg==ZPC || opP->mode==REGLST)
1502 losing++;
1503 break;
1504
1505
1506 case '&':
1507 if(opP->mode==MSCR || opP->mode==DREG ||
1508 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC ||
1509 opP->mode==AINC || opP->mode==ADEC || opP->mode==REGLST)
1510 losing++;
1511 break;
1512
1513 case '*':
1514 if(opP->mode==MSCR || opP->mode==REGLST)
1515 losing++;
1516 break;
1517
1518 case '+':
1519 if(opP->mode!=AINC)
1520 losing++;
1521 break;
1522
1523 case '-':
1524 if(opP->mode!=ADEC)
1525 losing++;
1526 break;
1527
1528 case '/':
1529 if(opP->mode==MSCR || opP->mode==AREG ||
1530 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->mode==REGLST)
1531 losing++;
1532 break;
1533
1534 case ';':
1535 if(opP->mode==MSCR || opP->mode==AREG || opP->mode==REGLST)
1536 losing++;
1537 break;
1538
1539 case '?':
1540 if(opP->mode==MSCR || opP->mode==AREG ||
1541 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->reg==PC ||
1542 opP->reg==ZPC || opP->mode==REGLST)
1543 losing++;
1544 break;
1545
1546 case '@':
1547 if(opP->mode==MSCR || opP->mode==AREG ||
1548 opP->mode==IMMED || opP->mode==REGLST)
1549 losing++;
1550 break;
1551
1552 case '~': /* For now! (JF FOO is this right?) */
1553 if(opP->mode==MSCR || opP->mode==DREG ||
1554 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1555 losing++;
1556 break;
1557
1558 case '3':
1559 if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1))
1560 losing++;
1561 break;
1562
1563 case 'A':
1564 if(opP->mode!=AREG)
1565 losing++;
1566 break;
1567 case 'a':
1568 if (opP->mode != AINDR) {
1569 ++losing;
1570 } /* if not address register indirect */
1571 break;
1572 case 'B': /* FOO */
1573 if(opP->mode!=ABSL || (flagseen['S'] && instring[0] == 'j'
1574 && instring[1] == 'b'
1575 && instring[2] == 's'
1576 && instring[3] == 'r'))
1577 losing++;
1578 break;
1579
1580 case 'C':
1581 if(opP->mode!=MSCR || opP->reg!=CCR)
1582 losing++;
1583 break;
1584
1585 case 'd': /* FOO This mode is a KLUDGE!! */
1586 if(opP->mode!=AOFF && (opP->mode!=ABSL ||
1587 opP->con1->e_beg[0]!='(' || opP->con1->e_end[0]!=')'))
1588 losing++;
1589 break;
1590
1591 case 'D':
1592 if(opP->mode!=DREG)
1593 losing++;
1594 break;
1595
1596 case 'F':
1597 if(opP->mode!=MSCR || opP->reg<(FPREG+0) || opP->reg>(FPREG+7))
1598 losing++;
1599 break;
1600
1601 case 'I':
1602 if(opP->mode!=MSCR || opP->reg<COPNUM ||
1603 opP->reg>=COPNUM+7)
1604 losing++;
1605 break;
1606
1607 case 'J':
1608 if (opP->mode != MSCR
1609 || opP->reg < USP
1610 || opP->reg > URP
1611 || cpu_of_arch(current_architecture) < m68010 /* before 68010 had none */
1612 || (cpu_of_arch(current_architecture) < m68020
1613 && opP->reg != SFC
1614 && opP->reg != DFC
1615 && opP->reg != USP
1616 && opP->reg != VBR) /* 68010's had only these */
1617 || (cpu_of_arch(current_architecture) < m68040
1618 && opP->reg != SFC
1619 && opP->reg != DFC
1620 && opP->reg != USP
1621 && opP->reg != VBR
1622 && opP->reg != CACR
1623 && opP->reg != CAAR
1624 && opP->reg != MSP
1625 && opP->reg != ISP) /* 680[23]0's have only these */
1626 || (cpu_of_arch(current_architecture) == m68040 /* 68040 has all but this */
1627 && opP->reg == CAAR)) {
1628 losing++;
1629 } /* doesn't cut it */
1630 break;
1631
1632 case 'k':
1633 if(opP->mode!=IMMED)
1634 losing++;
1635 break;
1636
1637 case 'l':
1638 case 'L':
1639 if(opP->mode==DREG || opP->mode==AREG || opP->mode==FPREG) {
1640 if(s[1]=='8')
1641 losing++;
1642 else {
1643 opP->mode=REGLST;
1644 opP->reg=1<<(opP->reg-DATA);
1645 }
1646 } else if(opP->mode!=REGLST) {
1647 losing++;
1648 } else if(s[1]=='8' && opP->reg&0x0FFffFF)
1649 losing++;
1650 else if(s[1]=='3' && opP->reg&0x7000000)
1651 losing++;
1652 break;
1653
1654 case 'M':
1655 if(opP->mode!=IMMED)
1656 losing++;
1657 else {
1658 long t;
1659
1660 t=get_num(opP->con1,80);
1661 if(!issbyte(t) || isvar(opP->con1))
1662 losing++;
1663 }
1664 break;
1665
1666 case 'O':
1667 if(opP->mode!=DREG && opP->mode!=IMMED)
1668 losing++;
1669 break;
1670
1671 case 'Q':
1672 if(opP->mode!=IMMED)
1673 losing++;
1674 else {
1675 long t;
1676
1677 t=get_num(opP->con1,80);
1678 if(t<1 || t>8 || isvar(opP->con1))
1679 losing++;
1680 }
1681 break;
1682
1683 case 'R':
1684 if(opP->mode!=DREG && opP->mode!=AREG)
1685 losing++;
1686 break;
1687
1688 case 'r':
1689 if (opP->mode!=AINDR && opP->mode!=DINDR)
1690 losing++;
1691 break;
1692
1693 case 's':
1694 if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC))
1695 losing++;
1696 break;
1697
1698 case 'S':
1699 if(opP->mode!=MSCR || opP->reg!=SR)
1700 losing++;
1701 break;
1702
1703 case 't':
1704 if (opP->mode != IMMED)
1705 losing++;
1706 else
1707 {
1708 long t = get_num (opP->con1, 80);
1709 if (t < 0 || t > 7 || isvar (opP->con1))
1710 losing++;
1711 }
1712 break;
1713
1714 case 'U':
1715 if(opP->mode!=MSCR || opP->reg!=USP)
1716 losing++;
1717 break;
1718
1719 /* JF these are out of order. We could put them
1720 in order if we were willing to put up with
1721 bunches of #ifdef m68851s in the code.
1722
1723 Don't forget that you need these operands
1724 to use 68030 MMU instructions. */
1725 #ifndef NO_68851
1726 /* Memory addressing mode used by pflushr */
1727 case '|':
1728 if(opP->mode==MSCR || opP->mode==DREG ||
1729 opP->mode==AREG || opP->mode==REGLST)
1730 losing++;
1731 break;
1732
1733 case 'f':
1734 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
1735 losing++;
1736 break;
1737
1738 case 'P':
1739 if (opP->mode != MSCR
1740 || (opP->reg != TC && opP->reg != CAL
1741 && opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
1742 losing++;
1743 break;
1744
1745 case 'V':
1746 if (opP->reg != VAL)
1747 losing++;
1748 break;
1749
1750 case 'W':
1751 if (opP->mode != MSCR
1752 || (opP->reg != DRP && opP->reg != SRP
1753 && opP->reg != CRP))
1754 losing++;
1755 break;
1756
1757 case 'X':
1758 if (opP->mode != MSCR ||
1759 (!(opP->reg >= BAD && opP->reg <= BAD+7) &&
1760 !(opP->reg >= BAC && opP->reg <= BAC+7)))
1761 losing++;
1762 break;
1763
1764 case 'Y':
1765 if (opP->reg != PSR)
1766 losing++;
1767 break;
1768
1769 case 'Z':
1770 if (opP->reg != PCSR)
1771 losing++;
1772 break;
1773 #endif
1774 case 'c':
1775 if (opP->reg != NC
1776 && opP->reg != IC
1777 && opP->reg != DC
1778 && opP->reg != BC) {
1779 losing++;
1780 } /* not a cache specifier. */
1781 break;
1782
1783 case '_':
1784 if (opP->mode != ABSL) {
1785 ++losing;
1786 } /* not absolute */
1787 break;
1788
1789 default:
1790 as_fatal("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
1791 *s, __LINE__, __FILE__);
1792 } /* switch on type of operand */
1793
1794 if (losing)
1795 break;
1796 } /* for each operand */
1797 } /* if immediately wrong */
1798
1799 if (!losing) {
1800 break;
1801 } /* got it. */
1802
1803 opcode = opcode->m_next;
1804
1805 if (!opcode) {
1806 if (ok_arch
1807 && !(ok_arch & current_architecture))
1808 {
1809 char buf[200], *cp;
1810 int len;
1811 strcpy (buf, "invalid instruction for this architecture; needs ");
1812 cp = buf + strlen (buf);
1813 switch (ok_arch)
1814 {
1815 case mfloat:
1816 strcpy (cp, "fpu (68040 or 68881/68882)");
1817 break;
1818 case mmmu:
1819 strcpy (cp, "mmu (68030 or 68851)");
1820 break;
1821 case m68020up:
1822 strcpy (cp, "68020 or higher");
1823 break;
1824 case m68000up:
1825 strcpy (cp, "68000 or higher");
1826 break;
1827 case m68010up:
1828 strcpy (cp, "68010 or higher");
1829 break;
1830 default:
1831 {
1832 int got_one = 0, idx;
1833 const static struct {
1834 enum m68k_architecture arch;
1835 const char *name;
1836 } archs[] = {
1837 m68000, "68000",
1838 m68010, "68010",
1839 m68020, "68020",
1840 m68030, "68030",
1841 m68040, "68040",
1842 m68881, "68881",
1843 m68851, "68851",
1844 };
1845 for (idx = 0; idx < sizeof (archs)/sizeof (archs[0]); idx++)
1846 {
1847 if (archs[idx].arch & ok_arch)
1848 {
1849 if (got_one)
1850 {
1851 strcpy (cp, " or ");
1852 cp += strlen (cp);
1853 }
1854 got_one = 1;
1855 strcpy (cp, archs[idx].name);
1856 cp += strlen (cp);
1857 }
1858 }
1859 }
1860 }
1861 len = cp - buf + 1;
1862 cp = malloc (len);
1863 strcpy (cp, buf);
1864 the_ins.error = cp;
1865 }
1866 else
1867 the_ins.error = "operands mismatch";
1868 return;
1869 } /* Fell off the end */
1870
1871 losing = 0;
1872 }
1873
1874 /* now assemble it */
1875
1876 the_ins.args=opcode->m_operands;
1877 the_ins.numargs=opcode->m_opnum;
1878 the_ins.numo=opcode->m_codenum;
1879 the_ins.opcode[0]=getone(opcode);
1880 the_ins.opcode[1]=gettwo(opcode);
1881
1882 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) {
1883 /* This switch is a doozy.
1884 Watch the first step; its a big one! */
1885 switch(s[0]) {
1886
1887 case '*':
1888 case '~':
1889 case '%':
1890 case ';':
1891 case '@':
1892 case '!':
1893 case '&':
1894 case '$':
1895 case '?':
1896 case '/':
1897 #ifndef NO_68851
1898 case '|':
1899 #endif
1900 switch(opP->mode) {
1901 case IMMED:
1902 tmpreg=0x3c; /* 7.4 */
1903 if (strchr("bwl",s[1])) nextword=get_num(opP->con1,80);
1904 else nextword=nextword=get_num(opP->con1,0);
1905 if(isvar(opP->con1))
1906 add_fix(s[1],opP->con1,0);
1907 switch(s[1]) {
1908 case 'b':
1909 if(!isbyte(nextword))
1910 opP->error="operand out of range";
1911 addword(nextword);
1912 baseo=0;
1913 break;
1914 case 'w':
1915 if(!isword(nextword))
1916 opP->error="operand out of range";
1917 addword(nextword);
1918 baseo=0;
1919 break;
1920 case 'l':
1921 addword(nextword>>16);
1922 addword(nextword);
1923 baseo=0;
1924 break;
1925
1926 case 'f':
1927 baseo=2;
1928 outro=8;
1929 break;
1930 case 'F':
1931 baseo=4;
1932 outro=11;
1933 break;
1934 case 'x':
1935 baseo=6;
1936 outro=15;
1937 break;
1938 case 'p':
1939 baseo=6;
1940 outro= -1;
1941 break;
1942 default:
1943 as_fatal("Internal error: Can't decode %c%c in line %s of file \"%s\"",
1944 *s, s[1], __LINE__, __FILE__);
1945 }
1946 if(!baseo)
1947 break;
1948
1949 /* We gotta put out some float */
1950 if(seg(opP->con1)!=SEG_BIG) {
1951 int_to_gen(nextword);
1952 gen_to_words(words,baseo,(long int)outro);
1953 for(wordp=words;baseo--;wordp++)
1954 addword(*wordp);
1955 break;
1956 } /* Its BIG */
1957 if(offs(opP->con1)>0) {
1958 as_warn("Bignum assumed to be binary bit-pattern");
1959 if(offs(opP->con1)>baseo) {
1960 as_warn("Bignum too big for %c format; truncated",s[1]);
1961 offs(opP->con1)=baseo;
1962 }
1963 baseo-=offs(opP->con1);
1964 for(wordp=generic_bignum+offs(opP->con1)-1;offs(opP->con1)--;--wordp)
1965 addword(*wordp);
1966 while(baseo--)
1967 addword(0);
1968 break;
1969 }
1970 gen_to_words(words,baseo,(long)outro);
1971 for (wordp=words;baseo--;wordp++)
1972 addword(*wordp);
1973 break;
1974 case DREG:
1975 tmpreg=opP->reg-DATA; /* 0.dreg */
1976 break;
1977 case AREG:
1978 tmpreg=0x08+opP->reg-ADDR; /* 1.areg */
1979 break;
1980 case AINDR:
1981 tmpreg=0x10+opP->reg-ADDR; /* 2.areg */
1982 break;
1983 case ADEC:
1984 tmpreg=0x20+opP->reg-ADDR; /* 4.areg */
1985 break;
1986 case AINC:
1987 tmpreg=0x18+opP->reg-ADDR; /* 3.areg */
1988 break;
1989 case AOFF:
1990
1991 nextword=get_num(opP->con1,80);
1992 /* Force into index mode. Hope this works */
1993
1994 /* We do the first bit for 32-bit displacements,
1995 and the second bit for 16 bit ones. It is
1996 possible that we should make the default be
1997 WORD instead of LONG, but I think that'd
1998 break GCC, so we put up with a little
1999 inefficiency for the sake of working output.
2000 */
2001
2002 if( !issword(nextword)
2003 || ( isvar(opP->con1)
2004 && ( ( opP->con1->e_siz==0
2005 && flagseen['l']==0)
2006 || opP->con1->e_siz==3))) {
2007
2008 if(opP->reg==PC)
2009 tmpreg=0x3B; /* 7.3 */
2010 else
2011 tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
2012 if(isvar(opP->con1)) {
2013 if(opP->reg==PC) {
2014 add_frag(adds(opP->con1),
2015 offs(opP->con1),
2016 TAB(PCLEA,SZ_UNDEF));
2017 break;
2018 } else {
2019 addword(0x0170);
2020 add_fix('l',opP->con1,0);
2021 }
2022 } else
2023 addword(0x0170);
2024 addword(nextword>>16);
2025 } else {
2026 if(opP->reg==PC)
2027 tmpreg=0x3A; /* 7.2 */
2028 else
2029 tmpreg=0x28+opP->reg-ADDR; /* 5.areg */
2030
2031 if(isvar(opP->con1)) {
2032 if(opP->reg==PC) {
2033 add_fix('w',opP->con1,1);
2034 } else
2035 add_fix('w',opP->con1,0);
2036 }
2037 }
2038 addword(nextword);
2039 break;
2040
2041 case APODX:
2042 case AMIND:
2043 case APRDX:
2044 know(current_architecture & m68020up);
2045 /* intentional fall-through */
2046 case AINDX:
2047 nextword=0;
2048 baseo=get_num(opP->con1,80);
2049 outro=get_num(opP->con2,80);
2050 /* Figure out the 'addressing mode' */
2051 /* Also turn on the BASE_DISABLE bit, if needed */
2052 if(opP->reg==PC || opP->reg==ZPC) {
2053 tmpreg=0x3b; /* 7.3 */
2054 if(opP->reg==ZPC)
2055 nextword|=0x80;
2056 } else if(opP->reg==FAIL) {
2057 nextword|=0x80;
2058 tmpreg=0x30; /* 6.garbage */
2059 } else tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
2060
2061 siz1= (opP->con1) ? opP->con1->e_siz : 0;
2062 siz2= (opP->con2) ? opP->con2->e_siz : 0;
2063
2064 /* Index register stuff */
2065 if(opP->ireg>=DATA+0 && opP->ireg<=ADDR+7) {
2066 nextword|=(opP->ireg-DATA)<<12;
2067
2068 if(opP->isiz==0 || opP->isiz==3)
2069 nextword|=0x800;
2070 switch(opP->imul) {
2071 case 1: break;
2072 case 2: nextword|=0x200; break;
2073 case 4: nextword|=0x400; break;
2074 case 8: nextword|=0x600; break;
2075 default: as_fatal("failed sanity check.");
2076 }
2077 /* IF its simple,
2078 GET US OUT OF HERE! */
2079
2080 /* Must be INDEX, with an index
2081 register. Address register
2082 cannot be ZERO-PC, and either
2083 :b was forced, or we know
2084 it will fit */
2085 if( opP->mode==AINDX
2086 && opP->reg!=FAIL
2087 && opP->reg!=ZPC
2088 && ( siz1==1
2089 || ( issbyte(baseo)
2090 && !isvar(opP->con1)))) {
2091 nextword +=baseo&0xff;
2092 addword(nextword);
2093 if(isvar(opP->con1))
2094 add_fix('B',opP->con1,0);
2095 break;
2096 }
2097 } else
2098 nextword|=0x40; /* No index reg */
2099
2100 /* It aint simple */
2101 nextword|=0x100;
2102 /* If the guy specified a width, we assume that
2103 it is wide enough. Maybe it isn't. If so, we lose
2104 */
2105 switch(siz1) {
2106 case 0:
2107 if(isvar(opP->con1) || !issword(baseo)) {
2108 siz1=3;
2109 nextword|=0x30;
2110 } else if(baseo==0)
2111 nextword|=0x10;
2112 else {
2113 nextword|=0x20;
2114 siz1=2;
2115 }
2116 break;
2117 case 1:
2118 as_warn("Byte dispacement won't work. Defaulting to :w");
2119 case 2:
2120 nextword|=0x20;
2121 break;
2122 case 3:
2123 nextword|=0x30;
2124 break;
2125 }
2126
2127 /* Figure out innner displacement stuff */
2128 if(opP->mode!=AINDX) {
2129 switch(siz2) {
2130 case 0:
2131 if(isvar(opP->con2) || !issword(outro)) {
2132 siz2=3;
2133 nextword|=0x3;
2134 } else if(outro==0)
2135 nextword|=0x1;
2136 else {
2137 nextword|=0x2;
2138 siz2=2;
2139 }
2140 break;
2141 case 1:
2142 as_warn("Byte dispacement won't work. Defaulting to :w");
2143 case 2:
2144 nextword|=0x2;
2145 break;
2146 case 3:
2147 nextword|=0x3;
2148 break;
2149 }
2150 if(opP->mode==APODX) nextword|=0x04;
2151 else if(opP->mode==AMIND) nextword|=0x40;
2152 }
2153 addword(nextword);
2154
2155 if(isvar(opP->con1)) {
2156 if(opP->reg==PC || opP->reg==ZPC) {
2157 add_fix(siz1==3 ? 'l' : 'w',opP->con1,1);
2158 opP->con1->e_exp.X_add_number+=6;
2159 } else
2160 add_fix(siz1==3 ? 'l' : 'w',opP->con1,0);
2161 }
2162 if(siz1==3)
2163 addword(baseo>>16);
2164 if(siz1)
2165 addword(baseo);
2166
2167 if(isvar(opP->con2)) {
2168 if(opP->reg==PC || opP->reg==ZPC) {
2169 add_fix(siz2==3 ? 'l' : 'w',opP->con2,1);
2170 opP->con1->e_exp.X_add_number+=6;
2171 } else
2172 add_fix(siz2==3 ? 'l' : 'w',opP->con2,0);
2173 }
2174 if(siz2==3)
2175 addword(outro>>16);
2176 if(siz2)
2177 addword(outro);
2178
2179 break;
2180
2181 case ABSL:
2182 nextword=get_num(opP->con1,80);
2183 switch(opP->con1->e_siz) {
2184 default:
2185 as_warn("Unknown size for absolute reference");
2186 case 0:
2187 if(!isvar(opP->con1) && issword(offs(opP->con1))) {
2188 tmpreg=0x38; /* 7.0 */
2189 addword(nextword);
2190 break;
2191 }
2192 /* Don't generate pc relative code
2193 on 68010 and 68000 */
2194 if(isvar(opP->con1)
2195 && !subs(opP->con1)
2196 && seg(opP->con1) == SEG_TEXT
2197 && now_seg == SEG_TEXT
2198 && cpu_of_arch(current_architecture) >= m68020
2199 && !flagseen['S']
2200 && !strchr("~%&$?", s[0])) {
2201 tmpreg=0x3A; /* 7.2 */
2202 add_frag(adds(opP->con1),
2203 offs(opP->con1),
2204 TAB(PCREL,SZ_UNDEF));
2205 break;
2206 }
2207 case 3: /* Fall through into long */
2208 if(isvar(opP->con1))
2209 add_fix('l',opP->con1,0);
2210
2211 tmpreg=0x39; /* 7.1 mode */
2212 addword(nextword>>16);
2213 addword(nextword);
2214 break;
2215
2216 case 2: /* Word */
2217 if(isvar(opP->con1))
2218 add_fix('w',opP->con1,0);
2219
2220 tmpreg=0x38; /* 7.0 mode */
2221 addword(nextword);
2222 break;
2223 }
2224 break;
2225 case DINDR:
2226 as_bad("invalid indirect register");
2227 break;
2228 case MSCR:
2229 default:
2230 as_bad("unknown/incorrect operand");
2231 /* abort(); */
2232 }
2233 install_gen_operand(s[1],tmpreg);
2234 break;
2235
2236 case '#':
2237 case '^':
2238 switch(s[1]) { /* JF: I hate floating point! */
2239 case 'j':
2240 tmpreg=70;
2241 break;
2242 case '8':
2243 tmpreg=20;
2244 break;
2245 case 'C':
2246 tmpreg=50;
2247 break;
2248 case '3':
2249 default:
2250 tmpreg=80;
2251 break;
2252 }
2253 tmpreg=get_num(opP->con1,tmpreg);
2254 if(isvar(opP->con1))
2255 add_fix(s[1],opP->con1,0);
2256 switch(s[1]) {
2257 case 'b': /* Danger: These do no check for
2258 certain types of overflow.
2259 user beware! */
2260 if(!isbyte(tmpreg))
2261 opP->error="out of range";
2262 insop(tmpreg);
2263 if(isvar(opP->con1))
2264 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2265 break;
2266 case 'w':
2267 if(!isword(tmpreg))
2268 opP->error="out of range";
2269 insop(tmpreg);
2270 if(isvar(opP->con1))
2271 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2272 break;
2273 case 'l':
2274 insop(tmpreg); /* Because of the way insop works, we put these two out backwards */
2275 insop(tmpreg>>16);
2276 if(isvar(opP->con1))
2277 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2278 break;
2279 case '3':
2280 tmpreg&=0xFF;
2281 case '8':
2282 case 'C':
2283 install_operand(s[1],tmpreg);
2284 break;
2285 default:
2286 as_fatal("Internal error: Unknown mode #%c in line %s of file \"%s\"", s[1], __LINE__, __FILE__);
2287 }
2288 break;
2289
2290 case '+':
2291 case '-':
2292 case 'A':
2293 case 'a':
2294 install_operand(s[1],opP->reg-ADDR);
2295 break;
2296
2297 case 'B':
2298 tmpreg=get_num(opP->con1,80);
2299 switch(s[1]) {
2300 case 'B':
2301 /* Needs no offsetting */
2302 add_fix('B',opP->con1,1);
2303 break;
2304 case 'W':
2305 /* Offset the displacement to be relative to byte disp location */
2306 opP->con1->e_exp.X_add_number+=2;
2307 add_fix('w',opP->con1,1);
2308 addword(0);
2309 break;
2310 case 'L':
2311 long_branch:
2312 if (cpu_of_arch(current_architecture) < m68020) /* 68000 or 010 */
2313 as_warn("Can't use long branches on 68000/68010");
2314 the_ins.opcode[the_ins.numo-1]|=0xff;
2315 /* Offset the displacement to be relative to byte disp location */
2316 opP->con1->e_exp.X_add_number+=4;
2317 add_fix('l',opP->con1,1);
2318 addword(0);
2319 addword(0);
2320 break;
2321 case 'g':
2322 if(subs(opP->con1)) /* We can't relax it */
2323 goto long_branch;
2324
2325 /* This could either be a symbol, or an
2326 absolute address. No matter, the
2327 frag hacking will finger it out.
2328 Not quite: it can't switch from
2329 BRANCH to BCC68000 for the case
2330 where opnd is absolute (it needs
2331 to use the 68000 hack since no
2332 conditional abs jumps). */
2333 if (((cpu_of_arch(current_architecture) < m68020) || (0==adds(opP->con1)))
2334 && (the_ins.opcode[0] >= 0x6200)
2335 && (the_ins.opcode[0] <= 0x6f00)) {
2336 add_frag(adds(opP->con1),offs(opP->con1),TAB(BCC68000,SZ_UNDEF));
2337 } else {
2338 add_frag(adds(opP->con1),offs(opP->con1),TAB(ABRANCH,SZ_UNDEF));
2339 }
2340 break;
2341 case 'w':
2342 if(isvar(opP->con1)) {
2343 /* check for DBcc instruction */
2344 if ((the_ins.opcode[0] & 0xf0f8) ==0x50c8) {
2345 /* size varies if patch */
2346 /* needed for long form */
2347 add_frag(adds(opP->con1),offs(opP->con1),TAB(DBCC,SZ_UNDEF));
2348 break;
2349 }
2350
2351 /* Don't ask! */
2352 opP->con1->e_exp.X_add_number+=2;
2353 add_fix('w',opP->con1,1);
2354 }
2355 addword(0);
2356 break;
2357 case 'C': /* Fixed size LONG coproc branches */
2358 the_ins.opcode[the_ins.numo-1]|=0x40;
2359 /* Offset the displacement to be relative to byte disp location */
2360 /* Coproc branches don't have a byte disp option, but they are
2361 compatible with the ordinary branches, which do... */
2362 opP->con1->e_exp.X_add_number+=4;
2363 add_fix('l',opP->con1,1);
2364 addword(0);
2365 addword(0);
2366 break;
2367 case 'c': /* Var size Coprocesssor branches */
2368 if(subs(opP->con1)) {
2369 add_fix('l',opP->con1,1);
2370 add_frag((symbolS *)0,(long)0,TAB(FBRANCH,LONG));
2371 } else if(adds(opP->con1)) {
2372 add_frag(adds(opP->con1),offs(opP->con1),TAB(FBRANCH,SZ_UNDEF));
2373 } else {
2374 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2375 the_ins.opcode[the_ins.numo-1]|=0x40;
2376 add_fix('l',opP->con1,1);
2377 addword(0);
2378 addword(4);
2379 }
2380 break;
2381 default:
2382 as_fatal("Internal error: operand type B%c unknown in line %s of file \"%s\"",
2383 s[1], __LINE__, __FILE__);
2384 }
2385 break;
2386
2387 case 'C': /* Ignore it */
2388 break;
2389
2390 case 'd': /* JF this is a kludge */
2391 if(opP->mode==AOFF) {
2392 install_operand('s',opP->reg-ADDR);
2393 } else {
2394 char *tmpP;
2395
2396 tmpP=opP->con1->e_end-2;
2397 opP->con1->e_beg++;
2398 opP->con1->e_end-=4; /* point to the , */
2399 baseo=m68k_reg_parse(&tmpP);
2400 if(baseo<ADDR+0 || baseo>ADDR+7) {
2401 as_bad("Unknown address reg, using A0");
2402 baseo=0;
2403 } else baseo-=ADDR;
2404 install_operand('s',baseo);
2405 }
2406 tmpreg=get_num(opP->con1,80);
2407 if(!issword(tmpreg)) {
2408 as_warn("Expression out of range, using 0");
2409 tmpreg=0;
2410 }
2411 addword(tmpreg);
2412 break;
2413
2414 case 'D':
2415 install_operand(s[1],opP->reg-DATA);
2416 break;
2417
2418 case 'F':
2419 install_operand(s[1],opP->reg-FPREG);
2420 break;
2421
2422 case 'I':
2423 tmpreg=1+opP->reg-COPNUM;
2424 if(tmpreg==8)
2425 tmpreg=0;
2426 install_operand(s[1],tmpreg);
2427 break;
2428
2429 case 'J': /* JF foo */
2430 switch(opP->reg) {
2431 case SFC: tmpreg=0x000; break;
2432 case DFC: tmpreg=0x001; break;
2433 case CACR: tmpreg=0x002; break;
2434 case TC: tmpreg=0x003; break;
2435 case ITT0: tmpreg=0x004; break;
2436 case ITT1: tmpreg=0x005; break;
2437 case DTT0: tmpreg=0x006; break;
2438 case DTT1: tmpreg=0x007; break;
2439
2440 case USP: tmpreg=0x800; break;
2441 case VBR: tmpreg=0x801; break;
2442 case CAAR: tmpreg=0x802; break;
2443 case MSP: tmpreg=0x803; break;
2444 case ISP: tmpreg=0x804; break;
2445 case MMUSR: tmpreg=0x805; break;
2446 case URP: tmpreg=0x806; break;
2447 case SRP: tmpreg=0x807; break;
2448 default:
2449 as_fatal("failed sanity check.");
2450 }
2451 install_operand(s[1],tmpreg);
2452 break;
2453
2454 case 'k':
2455 tmpreg=get_num(opP->con1,55);
2456 install_operand(s[1],tmpreg&0x7f);
2457 break;
2458
2459 case 'l':
2460 tmpreg=opP->reg;
2461 if(s[1]=='w') {
2462 if(tmpreg&0x7FF0000)
2463 as_bad("Floating point register in register list");
2464 insop(reverse_16_bits(tmpreg));
2465 } else {
2466 if(tmpreg&0x700FFFF)
2467 as_bad("Wrong register in floating-point reglist");
2468 install_operand(s[1],reverse_8_bits(tmpreg>>16));
2469 }
2470 break;
2471
2472 case 'L':
2473 tmpreg=opP->reg;
2474 if(s[1]=='w') {
2475 if(tmpreg&0x7FF0000)
2476 as_bad("Floating point register in register list");
2477 insop(tmpreg);
2478 } else if(s[1]=='8') {
2479 if(tmpreg&0x0FFFFFF)
2480 as_bad("incorrect register in reglist");
2481 install_operand(s[1],tmpreg>>24);
2482 } else {
2483 if(tmpreg&0x700FFFF)
2484 as_bad("wrong register in floating-point reglist");
2485 else
2486 install_operand(s[1],tmpreg>>16);
2487 }
2488 break;
2489
2490 case 'M':
2491 install_operand(s[1],get_num(opP->con1,60));
2492 break;
2493
2494 case 'O':
2495 tmpreg= (opP->mode==DREG)
2496 ? 0x20+opP->reg-DATA
2497 : (get_num(opP->con1,40)&0x1F);
2498 install_operand(s[1],tmpreg);
2499 break;
2500
2501 case 'Q':
2502 tmpreg=get_num(opP->con1,10);
2503 if(tmpreg==8)
2504 tmpreg=0;
2505 install_operand(s[1],tmpreg);
2506 break;
2507
2508 case 'R':
2509 case 'r':
2510 /* This depends on the fact that ADDR registers are
2511 eight more than their corresponding DATA regs, so
2512 the result will have the ADDR_REG bit set */
2513 install_operand(s[1],opP->reg-DATA);
2514 break;
2515
2516 case 's':
2517 if(opP->reg==FPI) tmpreg=0x1;
2518 else if(opP->reg==FPS) tmpreg=0x2;
2519 else if(opP->reg==FPC) tmpreg=0x4;
2520 else as_fatal("failed sanity check.");
2521 install_operand(s[1],tmpreg);
2522 break;
2523
2524 case 'S': /* Ignore it */
2525 break;
2526
2527 case 'T':
2528 install_operand(s[1],get_num(opP->con1,30));
2529 break;
2530
2531 case 'U': /* Ignore it */
2532 break;
2533
2534 case 'c':
2535 switch (opP->reg) {
2536 case NC: tmpreg = 0; break;
2537 case DC: tmpreg = 1; break;
2538 case IC: tmpreg = 2; break;
2539 case BC: tmpreg = 3; break;
2540 default:
2541 as_fatal("failed sanity check");
2542 } /* switch on cache token */
2543 install_operand(s[1], tmpreg);
2544 break;
2545 #ifndef NO_68851
2546 /* JF: These are out of order, I fear. */
2547 case 'f':
2548 switch (opP->reg) {
2549 case SFC:
2550 tmpreg=0;
2551 break;
2552 case DFC:
2553 tmpreg=1;
2554 break;
2555 default:
2556 as_fatal("failed sanity check.");
2557 }
2558 install_operand(s[1],tmpreg);
2559 break;
2560
2561 case 'P':
2562 switch(opP->reg) {
2563 case TC:
2564 tmpreg=0;
2565 break;
2566 case CAL:
2567 tmpreg=4;
2568 break;
2569 case VAL:
2570 tmpreg=5;
2571 break;
2572 case SCC:
2573 tmpreg=6;
2574 break;
2575 case AC:
2576 tmpreg=7;
2577 break;
2578 default:
2579 as_fatal("failed sanity check.");
2580 }
2581 install_operand(s[1],tmpreg);
2582 break;
2583
2584 case 'V':
2585 if (opP->reg == VAL)
2586 break;
2587 as_fatal("failed sanity check.");
2588
2589 case 'W':
2590 switch(opP->reg) {
2591
2592 case DRP:
2593 tmpreg=1;
2594 break;
2595 case SRP:
2596 tmpreg=2;
2597 break;
2598 case CRP:
2599 tmpreg=3;
2600 break;
2601 default:
2602 as_fatal("failed sanity check.");
2603 }
2604 install_operand(s[1],tmpreg);
2605 break;
2606
2607 case 'X':
2608 switch (opP->reg) {
2609 case BAD: case BAD+1: case BAD+2: case BAD+3:
2610 case BAD+4: case BAD+5: case BAD+6: case BAD+7:
2611 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2612 break;
2613
2614 case BAC: case BAC+1: case BAC+2: case BAC+3:
2615 case BAC+4: case BAC+5: case BAC+6: case BAC+7:
2616 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2617 break;
2618
2619 default:
2620 as_fatal("failed sanity check.");
2621 }
2622 install_operand(s[1], tmpreg);
2623 break;
2624 case 'Y':
2625 know(opP->reg == PSR);
2626 break;
2627 case 'Z':
2628 know(opP->reg == PCSR);
2629 break;
2630 #endif /* m68851 */
2631 case '3':
2632 switch (opP->reg)
2633 {
2634 case TT0:
2635 tmpreg = 2;
2636 break;
2637 case TT1:
2638 tmpreg = 3;
2639 break;
2640 default:
2641 as_fatal ("failed sanity check");
2642 }
2643 install_operand (s[1], tmpreg);
2644 break;
2645 case 't':
2646 tmpreg = get_num (opP->con1, 20);
2647 install_operand (s[1], tmpreg);
2648 break;
2649 case '_': /* used only for move16 absolute 32-bit address */
2650 tmpreg=get_num(opP->con1,80);
2651 install_operand(s[1], tmpreg);
2652 break;
2653 default:
2654 as_fatal("Internal error: Operand type %c unknown in line %d of file \"%s\"",
2655 s[0], __LINE__, __FILE__);
2656 }
2657 }
2658
2659 /* By the time whe get here (FINALLY) the_ins contains the complete
2660 instruction, ready to be emitted. . . */
2661 } /* m68k_ip() */
2662
2663 /*
2664 * get_regs := '/' + ?
2665 * | '-' + <register>
2666 * | '-' + <register> + ?
2667 * | <empty>
2668 * ;
2669 *
2670
2671 * The idea here must be to scan in a set of registers but I don't
2672 * understand it. Looks awfully sloppy to me but I don't have any doc on
2673 * this format so...
2674
2675 *
2676 *
2677 */
2678
2679 static int get_regs(i,str,opP)
2680 int i;
2681 struct m68k_op *opP;
2682 char *str;
2683 {
2684 /* 26, 25, 24, 23-16, 15-8, 0-7 */
2685 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
2686 unsigned long cur_regs = 0;
2687 int reg1,
2688 reg2;
2689
2690 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
2691 else if(x==FPS) cur_regs|=(1<<25);\
2692 else if(x==FPC) cur_regs|=(1<<26);\
2693 else cur_regs|=(1<<(x-1)); }
2694
2695 reg1=i;
2696 for(;;) {
2697 if(*str=='/') {
2698 ADD_REG(reg1);
2699 str++;
2700 } else if(*str=='-') {
2701 str++;
2702 reg2=m68k_reg_parse(&str);
2703 if(reg2<DATA || reg2>=FPREG+8 || reg1==FPI || reg1==FPS || reg1==FPC) {
2704 opP->error="unknown register in register list";
2705 return FAIL;
2706 }
2707 while(reg1<=reg2) {
2708 ADD_REG(reg1);
2709 reg1++;
2710 }
2711 if(*str=='\0')
2712 break;
2713 } else if(*str=='\0') {
2714 ADD_REG(reg1);
2715 break;
2716 } else {
2717 opP->error="unknow character in register list";
2718 return FAIL;
2719 }
2720 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
2721 if (*str=='/')
2722 str ++;
2723 reg1=m68k_reg_parse(&str);
2724 if((reg1<DATA || reg1>=FPREG+8) && !(reg1==FPI || reg1==FPS || reg1==FPC)) {
2725 opP->error="unknown register in register list";
2726 return FAIL;
2727 }
2728 }
2729 opP->reg=cur_regs;
2730 return OK;
2731 } /* get_regs() */
2732
2733 static int reverse_16_bits(in)
2734 int in;
2735 {
2736 int out=0;
2737 int n;
2738
2739 static int mask[16] = {
2740 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2741 0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000
2742 };
2743 for(n=0;n<16;n++) {
2744 if(in&mask[n])
2745 out|=mask[15-n];
2746 }
2747 return out;
2748 } /* reverse_16_bits() */
2749
2750 static int reverse_8_bits(in)
2751 int in;
2752 {
2753 int out=0;
2754 int n;
2755
2756 static int mask[8] = {
2757 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2758 };
2759
2760 for(n=0;n<8;n++) {
2761 if(in&mask[n])
2762 out|=mask[7-n];
2763 }
2764 return out;
2765 } /* reverse_8_bits() */
2766
2767 static void install_operand(mode,val)
2768 int mode;
2769 int val;
2770 {
2771 switch(mode) {
2772 case 's':
2773 the_ins.opcode[0]|=val & 0xFF; /* JF FF is for M kludge */
2774 break;
2775 case 'd':
2776 the_ins.opcode[0]|=val<<9;
2777 break;
2778 case '1':
2779 the_ins.opcode[1]|=val<<12;
2780 break;
2781 case '2':
2782 the_ins.opcode[1]|=val<<6;
2783 break;
2784 case '3':
2785 the_ins.opcode[1]|=val;
2786 break;
2787 case '4':
2788 the_ins.opcode[2]|=val<<12;
2789 break;
2790 case '5':
2791 the_ins.opcode[2]|=val<<6;
2792 break;
2793 case '6':
2794 /* DANGER! This is a hack to force cas2l and cas2w cmds
2795 to be three words long! */
2796 the_ins.numo++;
2797 the_ins.opcode[2]|=val;
2798 break;
2799 case '7':
2800 the_ins.opcode[1]|=val<<7;
2801 break;
2802 case '8':
2803 the_ins.opcode[1]|=val<<10;
2804 break;
2805 #ifndef NO_68851
2806 case '9':
2807 the_ins.opcode[1]|=val<<5;
2808 break;
2809 #endif
2810
2811 case 't':
2812 the_ins.opcode[1]|=(val<<10)|(val<<7);
2813 break;
2814 case 'D':
2815 the_ins.opcode[1]|=(val<<12)|val;
2816 break;
2817 case 'g':
2818 the_ins.opcode[0]|=val=0xff;
2819 break;
2820 case 'i':
2821 the_ins.opcode[0]|=val<<9;
2822 break;
2823 case 'C':
2824 the_ins.opcode[1]|=val;
2825 break;
2826 case 'j':
2827 the_ins.opcode[1]|=val;
2828 the_ins.numo++; /* What a hack */
2829 break;
2830 case 'k':
2831 the_ins.opcode[1]|=val<<4;
2832 break;
2833 case 'b':
2834 case 'w':
2835 case 'l':
2836 break;
2837 case 'e':
2838 the_ins.opcode[0] |= (val << 6);
2839 break;
2840 case 'L':
2841 the_ins.opcode[1] = (val >> 16);
2842 the_ins.opcode[2] = val & 0xffff;
2843 break;
2844 case 'c':
2845 default:
2846 as_fatal("failed sanity check.");
2847 }
2848 } /* install_operand() */
2849
2850 static void install_gen_operand(mode,val)
2851 int mode;
2852 int val;
2853 {
2854 switch(mode) {
2855 case 's':
2856 the_ins.opcode[0]|=val;
2857 break;
2858 case 'd':
2859 /* This is a kludge!!! */
2860 the_ins.opcode[0]|=(val&0x07)<<9|(val&0x38)<<3;
2861 break;
2862 case 'b':
2863 case 'w':
2864 case 'l':
2865 case 'f':
2866 case 'F':
2867 case 'x':
2868 case 'p':
2869 the_ins.opcode[0]|=val;
2870 break;
2871 /* more stuff goes here */
2872 default:
2873 as_fatal("failed sanity check.");
2874 }
2875 } /* install_gen_operand() */
2876
2877 /*
2878 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2879 * then deal with the bitfield hack.
2880 */
2881
2882 static char *crack_operand(str,opP)
2883 register char *str;
2884 register struct m68k_op *opP;
2885 {
2886 register int parens;
2887 register int c;
2888 register char *beg_str;
2889
2890 if(!str) {
2891 return str;
2892 }
2893 beg_str=str;
2894 for(parens=0;*str && (parens>0 || notend(str));str++) {
2895 if(*str=='(') parens++;
2896 else if(*str==')') {
2897 if(!parens) { /* ERROR */
2898 opP->error="Extra )";
2899 return str;
2900 }
2901 --parens;
2902 }
2903 }
2904 if(!*str && parens) { /* ERROR */
2905 opP->error="Missing )";
2906 return str;
2907 }
2908 c= *str;
2909 *str='\0';
2910 if(m68k_ip_op(beg_str,opP)==FAIL) {
2911 *str=c;
2912 return str;
2913 }
2914 *str=c;
2915 if(c=='}')
2916 c= *++str; /* JF bitfield hack */
2917 if(c) {
2918 c= *++str;
2919 if(!c)
2920 as_bad("Missing operand");
2921 }
2922 return str;
2923 }
2924
2925 /* See the comment up above where the #define notend(... is */
2926 #if 0
2927 notend(s)
2928 char *s;
2929 {
2930 if(*s==',') return 0;
2931 if(*s=='{' || *s=='}')
2932 return 0;
2933 if(*s!=':') return 1;
2934 /* This kludge here is for the division cmd, which is a kludge */
2935 if(index("aAdD#",s[1])) return 0;
2936 return 1;
2937 }
2938 #endif
2939
2940 /* This is the guts of the machine-dependent assembler. STR points to a
2941 machine dependent instruction. This function is supposed to emit
2942 the frags/bytes it assembles to.
2943 */
2944
2945 void
2946 insert_reg(regname, regnum)
2947 char *regname;
2948 int regnum;
2949 {
2950 char buf[100];
2951 int i;
2952 symbol_table_insert(symbol_new(regname, SEG_REGISTER, regnum, &zero_address_frag));
2953
2954 for (i = 0; regname[i]; i++)
2955 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2956 buf[i] = '\0';
2957
2958 symbol_table_insert(symbol_new(buf, SEG_REGISTER, regnum, &zero_address_frag));
2959 }
2960
2961 static const struct {
2962 char *name;
2963 int number;
2964 } init_table[] = {
2965 "d0", DATA0,
2966 "d1", DATA1,
2967 "d2", DATA2,
2968 "d3", DATA3,
2969 "d4", DATA4,
2970 "d5", DATA5,
2971 "d6", DATA6,
2972 "d7", DATA7,
2973 "a0", ADDR0,
2974 "a1", ADDR1,
2975 "a2", ADDR2,
2976 "a3", ADDR3,
2977 "a4", ADDR4,
2978 "a5", ADDR5,
2979 "a6", ADDR6,
2980 "fp", ADDR6,
2981 "a7", ADDR7,
2982 "sp", ADDR7,
2983 "fp0", FP0,
2984 "fp1", FP1,
2985 "fp2", FP2,
2986 "fp3", FP3,
2987 "fp4", FP4,
2988 "fp5", FP5,
2989 "fp6", FP6,
2990 "fp7", FP7,
2991 "fpi", FPI,
2992 "fpiar", FPI,
2993 "fpc", FPI,
2994 "fps", FPS,
2995 "fpsr", FPS,
2996 "fpc", FPC,
2997 "fpcr", FPC,
2998
2999 "cop0", COP0,
3000 "cop1", COP1,
3001 "cop2", COP2,
3002 "cop3", COP3,
3003 "cop4", COP4,
3004 "cop5", COP5,
3005 "cop6", COP6,
3006 "cop7", COP7,
3007 "pc", PC,
3008 "zpc", ZPC,
3009 "sr", SR,
3010
3011 "ccr", CCR,
3012 "cc", CCR,
3013
3014 "usp", USP,
3015 "isp", ISP,
3016 "sfc", SFC,
3017 "dfc", DFC,
3018 "cacr", CACR,
3019 "caar", CAAR,
3020
3021 "vbr", VBR,
3022
3023 "msp", MSP,
3024 "itt0", ITT0,
3025 "itt1", ITT1,
3026 "dtt0", DTT0,
3027 "dtt1", DTT1,
3028 "mmusr", MMUSR,
3029 "tc", TC,
3030 "srp", SRP,
3031 "urp", URP,
3032
3033 "ac", AC,
3034 "bc", BC,
3035 "cal", CAL,
3036 "crp", CRP,
3037 "drp", DRP,
3038 "pcsr", PCSR,
3039 "psr", PSR,
3040 "scc", SCC,
3041 "val", VAL,
3042 "bad0", BAD0,
3043 "bad1", BAD1,
3044 "bad2", BAD2,
3045 "bad3", BAD3,
3046 "bad4", BAD4,
3047 "bad5", BAD5,
3048 "bad6", BAD6,
3049 "bad7", BAD7,
3050 "bac0", BAC0,
3051 "bac1", BAC1,
3052 "bac2", BAC2,
3053 "bac3", BAC3,
3054 "bac4", BAC4,
3055 "bac5", BAC5,
3056 "bac6", BAC6,
3057 "bac7", BAC7,
3058
3059 "ic", IC,
3060 "dc", DC,
3061 "nc", NC,
3062
3063 "tt0", TT0,
3064 "tt1", TT1,
3065 /* 68ec030 versions of same */
3066 "ac0", TT0,
3067 "ac1", TT1,
3068 /* 68ec030 access control unit, identical to 030 MMU status reg */
3069 "acusr", PSR,
3070
3071 0,
3072
3073 };
3074
3075
3076 void
3077 init_regtable()
3078 {
3079 int i;
3080 for (i = 0; init_table[i].name; i++)
3081 insert_reg(init_table[i].name, init_table[i].number);
3082 }
3083
3084
3085 void
3086 md_assemble(str)
3087 char *str;
3088 {
3089 char *er;
3090 short *fromP;
3091 char *toP = NULL;
3092 int m,n = 0;
3093 char *to_beg_P;
3094 int shorts_this_frag;
3095 static int done_first_time;
3096
3097 if (!done_first_time)
3098 {
3099 done_first_time = 1;
3100
3101 if (cpu_of_arch (current_architecture) == 0)
3102 {
3103 enum m68k_architecture cpu_type;
3104
3105 #ifndef TARGET_CPU
3106 cpu_type = m68020;
3107 #else
3108 if (strcmp (TARGET_CPU, "m68000") == 0)
3109 cpu_type = m68000;
3110 else if (strcmp (TARGET_CPU, "m68010") == 0)
3111 cpu_type = m68010;
3112 else if (strcmp (TARGET_CPU, "m68020") == 0
3113 || strcmp (TARGET_CPU, "m68k") == 0)
3114 cpu_type = m68020;
3115 else if (strcmp (TARGET_CPU, "m68030") == 0)
3116 cpu_type = m68030;
3117 else if (strcmp (TARGET_CPU, "m68040") == 0)
3118 cpu_type = m68040;
3119 else
3120 cpu_type = m68020;
3121 #endif
3122
3123 /* If float or mmu were specified, just default cpu. */
3124 if (current_architecture != 0)
3125 current_architecture |= cpu_type;
3126 else
3127 {
3128 if ((cpu_type & m68020up) != 0)
3129 current_architecture = (cpu_type
3130 #ifndef NO_68881
3131 | m68881
3132 #endif
3133 #ifndef NO_68851
3134 | m68851
3135 #endif
3136 );
3137 else
3138 current_architecture = cpu_type;
3139 }
3140 }
3141 if (cpu_of_arch (current_architecture) == m68000
3142 && (current_architecture & m68881) != 0)
3143 {
3144 as_bad ("incompatible processors 68000 and 68881 specified");
3145 }
3146 done_first_time = 1;
3147 }
3148
3149 memset((char *)(&the_ins), '\0', sizeof(the_ins)); /* JF for paranoia sake */
3150 m68k_ip(str);
3151 er=the_ins.error;
3152 if(!er) {
3153 for(n=the_ins.numargs;n;--n)
3154 if(the_ins.operands[n].error) {
3155 er=the_ins.operands[n].error;
3156 break;
3157 }
3158 }
3159 if(er) {
3160 as_bad("%s -- statement `%s' ignored",er,str);
3161 return;
3162 }
3163
3164 if(the_ins.nfrag==0) { /* No frag hacking involved; just put it out */
3165 toP=frag_more(2*the_ins.numo);
3166 fromP= &the_ins.opcode[0];
3167 for(m=the_ins.numo;m;--m) {
3168 md_number_to_chars(toP,(long)(*fromP),2);
3169 toP+=2;
3170 fromP++;
3171 }
3172 /* put out symbol-dependent info */
3173 for(m=0;m<the_ins.nrel;m++) {
3174 switch(the_ins.reloc[m].wid) {
3175 case 'B':
3176 n=1;
3177 break;
3178 case 'b':
3179 n=1;
3180 break;
3181 case '3':
3182 n=2;
3183 break;
3184 case 'w':
3185 n=2;
3186 break;
3187 case 'l':
3188 n=4;
3189 break;
3190 default:
3191 as_fatal("Don't know how to figure width of %c in md_assemble()",the_ins.reloc[m].wid);
3192 }
3193
3194 fix_new(frag_now,
3195 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
3196 n,
3197 the_ins.reloc[m].add,
3198 the_ins.reloc[m].sub,
3199 the_ins.reloc[m].off,
3200 the_ins.reloc[m].pcrel,
3201 NO_RELOC);
3202 }
3203 return;
3204 }
3205
3206 /* There's some frag hacking */
3207 for(n=0,fromP= &the_ins.opcode[0];n<the_ins.nfrag;n++) {
3208 int wid;
3209
3210 if(n==0) wid=2*the_ins.fragb[n].fragoff;
3211 else wid=2*(the_ins.numo-the_ins.fragb[n-1].fragoff);
3212 toP=frag_more(wid);
3213 to_beg_P=toP;
3214 shorts_this_frag=0;
3215 for(m=wid/2;m;--m) {
3216 md_number_to_chars(toP,(long)(*fromP),2);
3217 toP+=2;
3218 fromP++;
3219 shorts_this_frag++;
3220 }
3221 for(m=0;m<the_ins.nrel;m++) {
3222 if((the_ins.reloc[m].n)>= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */) {
3223 the_ins.reloc[m].n-= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */;
3224 break;
3225 }
3226 wid=the_ins.reloc[m].wid;
3227 if(wid==0)
3228 continue;
3229 the_ins.reloc[m].wid=0;
3230 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
3231
3232 fix_new(frag_now,
3233 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
3234 wid,
3235 the_ins.reloc[m].add,
3236 the_ins.reloc[m].sub,
3237 the_ins.reloc[m].off,
3238 the_ins.reloc[m].pcrel,
3239 NO_RELOC);
3240 }
3241 /* know(the_ins.fragb[n].fadd); */
3242 (void)frag_var(rs_machine_dependent,10,0,(relax_substateT)(the_ins.fragb[n].fragty),
3243 the_ins.fragb[n].fadd,the_ins.fragb[n].foff,to_beg_P);
3244 }
3245 n=(the_ins.numo-the_ins.fragb[n-1].fragoff);
3246 shorts_this_frag=0;
3247 if(n) {
3248 toP=frag_more(n*sizeof(short));
3249 while(n--) {
3250 md_number_to_chars(toP,(long)(*fromP),2);
3251 toP+=2;
3252 fromP++;
3253 shorts_this_frag++;
3254 }
3255 }
3256 for(m=0;m<the_ins.nrel;m++) {
3257 int wid;
3258
3259 wid=the_ins.reloc[m].wid;
3260 if(wid==0)
3261 continue;
3262 the_ins.reloc[m].wid=0;
3263 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
3264
3265 fix_new(frag_now,
3266 (the_ins.reloc[m].n + toP-frag_now->fr_literal)-/* the_ins.numo */ shorts_this_frag*2,
3267 wid,
3268 the_ins.reloc[m].add,
3269 the_ins.reloc[m].sub,
3270 the_ins.reloc[m].off,
3271 the_ins.reloc[m].pcrel,
3272 NO_RELOC);
3273 }
3274 }
3275
3276
3277
3278 void
3279 md_begin()
3280 {
3281 /*
3282 * md_begin -- set up hash tables with 68000 instructions.
3283 * similar to what the vax assembler does. ---phr
3284 */
3285 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3286 a copy of it at runtime, adding in the information we want but isn't
3287 there. I think it'd be better to have an awk script hack the table
3288 at compile time. Or even just xstr the table and use it as-is. But
3289 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3290 names. */
3291
3292 register const struct m68k_opcode *ins;
3293 register struct m68k_incant *hack,
3294 *slak;
3295 register char *retval = 0; /* empty string, or error msg text */
3296 register unsigned int i;
3297 register char c;
3298
3299 if ((op_hash = hash_new()) == NULL)
3300 as_fatal("Virtual memory exhausted");
3301
3302 obstack_begin(&robyn,4000);
3303 for (ins = m68k_opcodes; ins < endop; ins++) {
3304 hack=slak=(struct m68k_incant *)obstack_alloc(&robyn,sizeof(struct m68k_incant));
3305 do {
3306 /* we *could* ignore insns that don't match our
3307 arch here but just leaving them out of the
3308 hash. */
3309 slak->m_operands=ins->args;
3310 slak->m_opnum=strlen(slak->m_operands)/2;
3311 slak->m_arch = ins->arch;
3312 slak->m_opcode=ins->opcode;
3313 /* This is kludgey */
3314 slak->m_codenum=((ins->match)&0xffffL) ? 2 : 1;
3315 if((ins+1)!=endop && !strcmp(ins->name,(ins+1)->name)) {
3316 slak->m_next=(struct m68k_incant *) obstack_alloc(&robyn,sizeof(struct m68k_incant));
3317 ins++;
3318 } else
3319 slak->m_next=0;
3320 slak=slak->m_next;
3321 } while(slak);
3322
3323 retval = hash_insert (op_hash, ins->name,(char *)hack);
3324 /* Didn't his mommy tell him about null pointers? */
3325 if(retval && *retval)
3326 as_bad("Internal Error: Can't hash %s: %s",ins->name,retval);
3327 }
3328
3329 for (i = 0; i < sizeof(mklower_table) ; i++)
3330 mklower_table[i] = (isupper(c = (char) i)) ? tolower(c) : c;
3331
3332 for (i = 0 ; i < sizeof(notend_table) ; i++) {
3333 notend_table[i] = 0;
3334 alt_notend_table[i] = 0;
3335 }
3336 notend_table[','] = 1;
3337 notend_table['{'] = 1;
3338 notend_table['}'] = 1;
3339 alt_notend_table['a'] = 1;
3340 alt_notend_table['A'] = 1;
3341 alt_notend_table['d'] = 1;
3342 alt_notend_table['D'] = 1;
3343 alt_notend_table['#'] = 1;
3344 alt_notend_table['f'] = 1;
3345 alt_notend_table['F'] = 1;
3346 #ifdef REGISTER_PREFIX
3347 alt_notend_table[REGISTER_PREFIX] = 1;
3348 #endif
3349
3350 #ifndef MIT_SYNTAX_ONLY
3351 /* Insert pseudo ops, these have to go into the opcode table since
3352 gas expects pseudo ops to start with a dot */
3353 {
3354 int n = 0;
3355 while (mote_pseudo_table[n].poc_name)
3356 {
3357 hack=(struct m68k_incant *)
3358 obstack_alloc(&robyn,sizeof(struct m68k_incant));
3359 hash_insert(op_hash,
3360 mote_pseudo_table[n].poc_name, (char *)hack);
3361 hack->m_operands = 0;
3362 hack->m_opnum = n;
3363 n++;
3364 }
3365 }
3366 #endif
3367
3368 init_regtable();
3369 }
3370
3371 #if 0
3372 #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
3373 || (*s == ':' && strchr("aAdD#", s[1]))) \
3374 ? 0 : 1)
3375 #endif
3376
3377 /* This funciton is called once, before the assembler exits. It is
3378 supposed to do any final cleanup for this part of the assembler.
3379 */
3380 void
3381 md_end()
3382 {
3383 }
3384
3385 /* Equal to MAX_PRECISION in atof-ieee.c */
3386 #define MAX_LITTLENUMS 6
3387
3388 /* Turn a string in input_line_pointer into a floating point constant of type
3389 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3390 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
3391 */
3392 char *
3393 md_atof(type,litP,sizeP)
3394 char type;
3395 char *litP;
3396 int *sizeP;
3397 {
3398 int prec;
3399 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3400 LITTLENUM_TYPE *wordP;
3401 char *t;
3402 char *atof_ieee();
3403
3404 switch(type) {
3405 case 'f':
3406 case 'F':
3407 case 's':
3408 case 'S':
3409 prec = 2;
3410 break;
3411
3412 case 'd':
3413 case 'D':
3414 case 'r':
3415 case 'R':
3416 prec = 4;
3417 break;
3418
3419 case 'x':
3420 case 'X':
3421 prec = 6;
3422 break;
3423
3424 case 'p':
3425 case 'P':
3426 prec = 6;
3427 break;
3428
3429 default:
3430 *sizeP=0;
3431 return "Bad call to MD_ATOF()";
3432 }
3433 t=atof_ieee(input_line_pointer,type,words);
3434 if(t)
3435 input_line_pointer=t;
3436
3437 *sizeP=prec * sizeof(LITTLENUM_TYPE);
3438 for(wordP=words;prec--;) {
3439 md_number_to_chars(litP,(long)(*wordP++),sizeof(LITTLENUM_TYPE));
3440 litP+=sizeof(LITTLENUM_TYPE);
3441 }
3442 return ""; /* Someone should teach Dean about null pointers */
3443 }
3444
3445 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3446 for use in the a.out file, and stores them in the array pointed to by buf.
3447 This knows about the endian-ness of the target machine and does
3448 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3449 2 (short) and 4 (long) Floating numbers are put out as a series of
3450 LITTLENUMS (shorts, here at least)
3451 */
3452 void
3453 md_number_to_chars(buf,val,n)
3454 char *buf;
3455 long val;
3456 int n;
3457 {
3458 switch(n) {
3459 case 1:
3460 *buf++=val;
3461 break;
3462 case 2:
3463 *buf++=(val>>8);
3464 *buf++=val;
3465 break;
3466 case 4:
3467 *buf++=(val>>24);
3468 *buf++=(val>>16);
3469 *buf++=(val>>8);
3470 *buf++=val;
3471 break;
3472 default:
3473 as_fatal("failed sanity check.");
3474 }
3475 }
3476
3477 void
3478 md_apply_fix(fixP, val)
3479 fixS *fixP;
3480 long val;
3481 {
3482 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3483
3484 switch(fixP->fx_size) {
3485 case 1:
3486 *buf++=val;
3487 break;
3488 case 2:
3489 *buf++=(val>>8);
3490 *buf++=val;
3491 break;
3492 case 4:
3493 *buf++=(val>>24);
3494 *buf++=(val>>16);
3495 *buf++=(val>>8);
3496 *buf++=val;
3497 break;
3498 default:
3499 BAD_CASE (fixP->fx_size);
3500 }
3501 }
3502
3503
3504 /* *fragP has been relaxed to its final size, and now needs to have
3505 the bytes inside it modified to conform to the new size There is UGLY
3506 MAGIC here. ..
3507 */
3508 void
3509 md_convert_frag(headers, fragP)
3510 object_headers *headers;
3511 register fragS *fragP;
3512 {
3513 long disp;
3514 long ext = 0;
3515
3516 /* Address in object code of the displacement. */
3517 register int object_address = fragP -> fr_fix + fragP -> fr_address;
3518
3519 #ifdef IBM_COMPILER_SUX
3520 /* This is wrong but it convinces the native rs6000 compiler to
3521 generate the code we want. */
3522 register char *buffer_address = fragP -> fr_literal;
3523 buffer_address += fragP -> fr_fix;
3524 #else /* IBM_COMPILER_SUX */
3525 /* Address in gas core of the place to store the displacement. */
3526 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3527 #endif /* IBM_COMPILER_SUX */
3528
3529 /* No longer true: know(fragP->fr_symbol); */
3530
3531 /* The displacement of the address, from current location. */
3532 disp = fragP->fr_symbol ? S_GET_VALUE(fragP->fr_symbol) : 0;
3533 disp = (disp + fragP->fr_offset) - object_address;
3534
3535 switch(fragP->fr_subtype) {
3536 case TAB(BCC68000,BYTE):
3537 case TAB(ABRANCH,BYTE):
3538 know(issbyte(disp));
3539 if(disp==0)
3540 as_bad("short branch with zero offset: use :w");
3541 fragP->fr_opcode[1]=disp;
3542 ext=0;
3543 break;
3544 case TAB(DBCC,SHORT):
3545 know(issword(disp));
3546 ext=2;
3547 break;
3548 case TAB(BCC68000,SHORT):
3549 case TAB(ABRANCH,SHORT):
3550 know(issword(disp));
3551 fragP->fr_opcode[1]=0x00;
3552 ext=2;
3553 break;
3554 case TAB(ABRANCH,LONG):
3555 if (cpu_of_arch(current_architecture) < m68020) {
3556 if (fragP->fr_opcode[0]==0x61) {
3557 fragP->fr_opcode[0]= 0x4E;
3558 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3559 subseg_change(SEG_TEXT, 0);
3560
3561 fix_new(fragP,
3562 fragP->fr_fix,
3563 4,
3564 fragP->fr_symbol,
3565 0,
3566 fragP->fr_offset,
3567 0,
3568 NO_RELOC);
3569
3570 fragP->fr_fix+=4;
3571 ext=0;
3572 } else if (fragP->fr_opcode[0]==0x60) {
3573 fragP->fr_opcode[0]= 0x4E;
3574 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3575 subseg_change(SEG_TEXT, 0);
3576 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset,0,
3577 NO_RELOC);
3578 fragP->fr_fix+=4;
3579 ext=0;
3580 } else {
3581 as_bad("Long branch offset not supported.");
3582 }
3583 } else {
3584 fragP->fr_opcode[1]=0xff;
3585 ext=4;
3586 }
3587 break;
3588 case TAB(BCC68000,LONG):
3589 /* only Bcc 68000 instructions can come here */
3590 /* change bcc into b!cc/jmp absl long */
3591 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3592 fragP->fr_opcode[1] = 0x6; /* branch offset = 6 */
3593
3594 /* JF: these used to be fr_opcode[2,3], but they may be in a
3595 different frag, in which case refering to them is a no-no.
3596 Only fr_opcode[0,1] are guaranteed to work. */
3597 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3598 *buffer_address++ = 0xf9;
3599 fragP->fr_fix += 2; /* account for jmp instruction */
3600 subseg_change(SEG_TEXT,0);
3601 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3602 fragP->fr_offset,0,
3603 NO_RELOC);
3604 fragP->fr_fix += 4;
3605 ext=0;
3606 break;
3607 case TAB(DBCC,LONG):
3608 /* only DBcc 68000 instructions can come here */
3609 /* change dbcc into dbcc/jmp absl long */
3610 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3611 *buffer_address++ = 0x00; /* branch offset = 4 */
3612 *buffer_address++ = 0x04;
3613 *buffer_address++ = 0x60; /* put in bra pc+6 */
3614 *buffer_address++ = 0x06;
3615 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3616 *buffer_address++ = 0xf9;
3617
3618 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3619 subseg_change(SEG_TEXT,0);
3620 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3621 fragP->fr_offset,0,
3622 NO_RELOC);
3623 fragP->fr_fix += 4;
3624 ext=0;
3625 break;
3626 case TAB(FBRANCH,SHORT):
3627 know((fragP->fr_opcode[1]&0x40)==0);
3628 ext=2;
3629 break;
3630 case TAB(FBRANCH,LONG):
3631 fragP->fr_opcode[1]|=0x40; /* Turn on LONG bit */
3632 ext=4;
3633 break;
3634 case TAB(PCREL,SHORT):
3635 ext=2;
3636 break;
3637 case TAB(PCREL,LONG):
3638 /* The thing to do here is force it to ABSOLUTE LONG, since
3639 PCREL is really trying to shorten an ABSOLUTE address anyway */
3640 /* JF FOO This code has not been tested */
3641 subseg_change(SEG_TEXT,0);
3642 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3643 if((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3644 as_bad("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
3645 fragP->fr_opcode[0],fragP->fr_address);
3646 fragP->fr_opcode[1]&= ~0x3F;
3647 fragP->fr_opcode[1]|=0x39; /* Mode 7.1 */
3648 fragP->fr_fix+=4;
3649 /* md_number_to_chars(buffer_address,
3650 (long)(fragP->fr_symbol->sy_value + fragP->fr_offset),
3651 4); */
3652 ext=0;
3653 break;
3654 case TAB(PCLEA,SHORT):
3655 subseg_change(SEG_TEXT,0);
3656 fix_new(fragP,(int)(fragP->fr_fix),2,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset,1,
3657 NO_RELOC);
3658 fragP->fr_opcode[1] &= ~0x3F;
3659 fragP->fr_opcode[1] |= 0x3A;
3660 ext=2;
3661 break;
3662 case TAB(PCLEA,LONG):
3663 subseg_change(SEG_TEXT,0);
3664 fix_new(fragP,(int)(fragP->fr_fix)+2,4,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset+2,1,
3665 NO_RELOC);
3666 *buffer_address++ = 0x01;
3667 *buffer_address++ = 0x70;
3668 fragP->fr_fix+=2;
3669 /* buffer_address+=2; */
3670 ext=4;
3671 break;
3672
3673 } /* switch on subtype */
3674
3675 if (ext) {
3676 md_number_to_chars(buffer_address, (long) disp, (int) ext);
3677 fragP->fr_fix += ext;
3678 /* H_SET_TEXT_SIZE(headers, H_GET_TEXT_SIZE(headers) + ext); */
3679 } /* if extending */
3680
3681 return;
3682 } /* md_convert_frag() */
3683
3684 /* Force truly undefined symbols to their maximum size, and generally set up
3685 the frag list to be relaxed
3686 */
3687 int md_estimate_size_before_relax(fragP, segment)
3688 register fragS *fragP;
3689 segT segment;
3690 {
3691 int old_fix;
3692 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3693
3694 old_fix = fragP->fr_fix;
3695
3696 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3697 switch (fragP->fr_subtype) {
3698
3699 case TAB(ABRANCH,SZ_UNDEF): {
3700 if((fragP->fr_symbol != NULL) /* Not absolute */
3701 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3702 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),BYTE);
3703 break;
3704 } else if((fragP->fr_symbol == 0) || (cpu_of_arch(current_architecture) < m68020)) {
3705 /* On 68000, or for absolute value, switch to abs long */
3706 /* FIXME, we should check abs val, pick short or long */
3707 if(fragP->fr_opcode[0]==0x61) {
3708 fragP->fr_opcode[0]= 0x4E;
3709 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3710 subseg_change(SEG_TEXT, 0);
3711 fix_new(fragP, fragP->fr_fix, 4,
3712 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3713 fragP->fr_fix+=4;
3714 frag_wane(fragP);
3715 } else if(fragP->fr_opcode[0]==0x60) {
3716 fragP->fr_opcode[0]= 0x4E;
3717 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3718 subseg_change(SEG_TEXT, 0);
3719 fix_new(fragP, fragP->fr_fix, 4,
3720 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3721 fragP->fr_fix+=4;
3722 frag_wane(fragP);
3723 } else {
3724 as_warn("Long branch offset to extern symbol not supported.");
3725 }
3726 } else { /* Symbol is still undefined. Make it simple */
3727 fix_new(fragP, (int)(fragP->fr_fix), 4, fragP->fr_symbol,
3728 (symbolS *)0, fragP->fr_offset+4, 1, NO_RELOC);
3729 fragP->fr_fix+=4;
3730 fragP->fr_opcode[1]=0xff;
3731 frag_wane(fragP);
3732 break;
3733 }
3734
3735 break;
3736 } /* case TAB(ABRANCH,SZ_UNDEF) */
3737
3738 case TAB(FBRANCH,SZ_UNDEF): {
3739 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3740 fragP->fr_subtype = TAB(FBRANCH,SHORT);
3741 fragP->fr_var += 2;
3742 } else {
3743 fragP->fr_subtype = TAB(FBRANCH,LONG);
3744 fragP->fr_var += 4;
3745 }
3746 break;
3747 } /* TAB(FBRANCH,SZ_UNDEF) */
3748
3749 case TAB(PCREL,SZ_UNDEF): {
3750 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3751 fragP->fr_subtype = TAB(PCREL,SHORT);
3752 fragP->fr_var += 2;
3753 } else {
3754 fragP->fr_subtype = TAB(PCREL,LONG);
3755 fragP->fr_var += 4;
3756 }
3757 break;
3758 } /* TAB(PCREL,SZ_UNDEF) */
3759
3760 case TAB(BCC68000,SZ_UNDEF): {
3761 if((fragP->fr_symbol != NULL)
3762 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3763 fragP->fr_subtype=TAB(BCC68000,BYTE);
3764 break;
3765 }
3766 /* only Bcc 68000 instructions can come here */
3767 /* change bcc into b!cc/jmp absl long */
3768 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3769 if(flagseen['l']) {
3770 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3771 /* JF: these were fr_opcode[2,3] */
3772 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3773 buffer_address[1] = 0xf8;
3774 fragP->fr_fix += 2; /* account for jmp instruction */
3775 subseg_change(SEG_TEXT,0);
3776 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
3777 fragP->fr_offset, 0, NO_RELOC);
3778 fragP->fr_fix += 2;
3779 } else {
3780 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3781 /* JF: these were fr_opcode[2,3] */
3782 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3783 buffer_address[1] = 0xf9;
3784 fragP->fr_fix += 2; /* account for jmp instruction */
3785 subseg_change(SEG_TEXT,0);
3786 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3787 fragP->fr_offset, 0, NO_RELOC);
3788 fragP->fr_fix += 4;
3789 }
3790 frag_wane(fragP);
3791 break;
3792 } /* case TAB(BCC68000,SZ_UNDEF) */
3793
3794 case TAB(DBCC,SZ_UNDEF): {
3795 if (fragP->fr_symbol != NULL && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3796 fragP->fr_subtype=TAB(DBCC,SHORT);
3797 fragP->fr_var+=2;
3798 break;
3799 }
3800 /* only DBcc 68000 instructions can come here */
3801 /* change dbcc into dbcc/jmp absl long */
3802 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3803 buffer_address[0] = 0x00; /* branch offset = 4 */
3804 buffer_address[1] = 0x04;
3805 buffer_address[2] = 0x60; /* put in bra pc + ... */
3806
3807 if(flagseen['l']) {
3808 /* JF: these were fr_opcode[5-7] */
3809 buffer_address[3] = 0x04; /* plus 4 */
3810 buffer_address[4] = 0x4e;/* Put in Jump Word */
3811 buffer_address[5] = 0xf8;
3812 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3813 subseg_change(SEG_TEXT,0);
3814 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
3815
3816
3817 fragP->fr_offset, 0, NO_RELOC);
3818 fragP->fr_fix += 2;
3819 } else {
3820 /* JF: these were fr_opcode[5-7] */
3821 buffer_address[3] = 0x06; /* Plus 6 */
3822 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3823 buffer_address[5] = 0xf9;
3824 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3825 subseg_change(SEG_TEXT,0);
3826 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3827 fragP->fr_offset, 0, NO_RELOC);
3828 fragP->fr_fix += 4;
3829 }
3830
3831 frag_wane(fragP);
3832 break;
3833 } /* case TAB(DBCC,SZ_UNDEF) */
3834
3835 case TAB(PCLEA,SZ_UNDEF): {
3836 if ((S_GET_SEGMENT(fragP->fr_symbol))==segment || flagseen['l']) {
3837 fragP->fr_subtype=TAB(PCLEA,SHORT);
3838 fragP->fr_var+=2;
3839 } else {
3840 fragP->fr_subtype=TAB(PCLEA,LONG);
3841 fragP->fr_var+=6;
3842 }
3843 break;
3844 } /* TAB(PCLEA,SZ_UNDEF) */
3845
3846 default:
3847 break;
3848
3849 } /* switch on subtype looking for SZ_UNDEF's. */
3850
3851 /* now that SZ_UNDEF are taken care of, check others */
3852 switch (fragP->fr_subtype) {
3853 case TAB(BCC68000,BYTE):
3854 case TAB(ABRANCH,BYTE):
3855 /* We can't do a short jump to the next instruction,
3856 so we force word mode. */
3857 if (fragP->fr_symbol && S_GET_VALUE(fragP->fr_symbol)==0 &&
3858 fragP->fr_symbol->sy_frag==fragP->fr_next) {
3859 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),SHORT);
3860 fragP->fr_var+=2;
3861 }
3862 break;
3863 default:
3864 break;
3865 }
3866 return fragP->fr_var + fragP->fr_fix - old_fix;
3867 }
3868
3869 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3870 /* the bit-field entries in the relocation_info struct plays hell
3871 with the byte-order problems of cross-assembly. So as a hack,
3872 I added this mach. dependent ri twiddler. Ugly, but it gets
3873 you there. -KWK */
3874 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3875 are symbolnum, most sig. byte first. Last byte is broken up with
3876 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3877 nibble as nuthin. (on Sun 3 at least) */
3878 /* Translate the internal relocation information into target-specific
3879 format. */
3880 #ifdef comment
3881 void
3882 md_ri_to_chars(the_bytes, ri)
3883 char *the_bytes;
3884 struct reloc_info_generic *ri;
3885 {
3886 /* this is easy */
3887 md_number_to_chars(the_bytes, ri->r_address, 4);
3888 /* now the fun stuff */
3889 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3890 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3891 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3892 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3893 ((ri->r_extern << 4) & 0x10));
3894 }
3895 #endif /* comment */
3896
3897 void tc_aout_fix_to_chars(where, fixP, segment_address_in_file)
3898 char *where;
3899 fixS *fixP;
3900 relax_addressT segment_address_in_file;
3901 {
3902 /*
3903 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3904 * Out: GNU LD relocation length code: 0, 1, or 2.
3905 */
3906
3907 static unsigned char nbytes_r_length [] = { 42, 0, 1, 42, 2 };
3908 long r_symbolnum;
3909
3910 know(fixP->fx_addsy != NULL);
3911
3912 md_number_to_chars(where,
3913 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3914 4);
3915
3916 r_symbolnum = (S_IS_DEFINED(fixP->fx_addsy)
3917 ? S_GET_TYPE(fixP->fx_addsy)
3918 : fixP->fx_addsy->sy_number);
3919
3920 where[4] = (r_symbolnum >> 16) & 0x0ff;
3921 where[5] = (r_symbolnum >> 8) & 0x0ff;
3922 where[6] = r_symbolnum & 0x0ff;
3923 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3924 (((!S_IS_DEFINED(fixP->fx_addsy)) << 4) & 0x10));
3925
3926 return;
3927 } /* tc_aout_fix_to_chars() */
3928
3929 #endif /* OBJ_AOUT or OBJ_BOUT */
3930
3931 #ifndef WORKING_DOT_WORD
3932 const int md_short_jump_size = 4;
3933 const int md_long_jump_size = 6;
3934
3935 void
3936 md_create_short_jump(ptr,from_addr,to_addr,frag,to_symbol)
3937 char *ptr;
3938 long from_addr,
3939 to_addr;
3940 fragS *frag;
3941 symbolS *to_symbol;
3942 {
3943 long offset;
3944
3945 offset = to_addr - (from_addr+2);
3946
3947 md_number_to_chars(ptr ,(long)0x6000,2);
3948 md_number_to_chars(ptr+2,(long)offset,2);
3949 }
3950
3951 void
3952 md_create_long_jump(ptr,from_addr,to_addr,frag,to_symbol)
3953 char *ptr;
3954 long from_addr,
3955 to_addr;
3956 fragS *frag;
3957 symbolS *to_symbol;
3958 {
3959 long offset;
3960
3961 if (cpu_of_arch(current_architecture) < m68020) {
3962 offset=to_addr-S_GET_VALUE(to_symbol);
3963 md_number_to_chars(ptr ,(long)0x4EF9,2);
3964 md_number_to_chars(ptr+2,(long)offset,4);
3965 fix_new(frag,(ptr+2)-frag->fr_literal,4,to_symbol,(symbolS *)0,(long)0,0,
3966 NO_RELOC);
3967 } else {
3968 offset=to_addr - (from_addr+2);
3969 md_number_to_chars(ptr ,(long)0x60ff,2);
3970 md_number_to_chars(ptr+2,(long)offset,4);
3971 }
3972 }
3973
3974 #endif
3975 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
3976
3977 0: Everything is OK
3978 10: Absolute 1:8 only
3979 20: Absolute 0:7 only
3980 30: absolute 0:15 only
3981 40: Absolute 0:31 only
3982 50: absolute 0:127 only
3983 55: absolute -64:63 only
3984 60: absolute -128:127 only
3985 70: absolute 0:4095 only
3986 80: No bignums
3987
3988 */
3989
3990 static int get_num(exp,ok)
3991 struct m68k_exp *exp;
3992 int ok;
3993 {
3994 #ifdef TEST2
3995 long l = 0;
3996
3997 if(!exp->e_beg)
3998 return 0;
3999 if(*exp->e_beg=='0') {
4000 if(exp->e_beg[1]=='x')
4001 sscanf(exp->e_beg+2,"%x",&l);
4002 else
4003 sscanf(exp->e_beg+1,"%O",&l);
4004 return l;
4005 }
4006 return atol(exp->e_beg);
4007 #else
4008 char *save_in;
4009 char c_save;
4010
4011 if(!exp) {
4012 /* Can't do anything */
4013 return 0;
4014 }
4015 if(!exp->e_beg || !exp->e_end) {
4016 seg(exp)=SEG_ABSOLUTE;
4017 adds(exp)=0;
4018 subs(exp)=0;
4019 offs(exp)= (ok==10) ? 1 : 0;
4020 as_warn("Null expression defaults to %ld",offs(exp));
4021 return 0;
4022 }
4023
4024 exp->e_siz=0;
4025 if(/* ok!=80 && */ (exp->e_end[-1]==':' || exp->e_end[-1]=='.')
4026 && (exp->e_end-exp->e_beg)>=2) {
4027 switch(exp->e_end[0]) {
4028 case 's':
4029 case 'S':
4030 case 'b':
4031 case 'B':
4032 exp->e_siz=1;
4033 exp->e_end-=2;
4034 break;
4035 case 'w':
4036 case 'W':
4037 exp->e_siz=2;
4038 exp->e_end-=2;
4039 break;
4040 case 'l':
4041 case 'L':
4042 exp->e_siz=3;
4043 exp->e_end-=2;
4044 break;
4045 default:
4046 if (exp->e_end[-1] == ':')
4047 as_bad("Unknown size for expression \"%c\"",exp->e_end[0]);
4048 break;
4049 }
4050 }
4051 c_save=exp->e_end[1];
4052 exp->e_end[1]='\0';
4053 save_in=input_line_pointer;
4054 input_line_pointer=exp->e_beg;
4055 switch(expression(&(exp->e_exp))) {
4056 case SEG_PASS1:
4057 seg(exp)=SEG_ABSOLUTE;
4058 adds(exp)=0;
4059 subs(exp)=0;
4060 offs(exp)= (ok==10) ? 1 : 0;
4061 as_warn("Unknown expression: '%s' defaulting to %d",exp->e_beg,offs(exp));
4062 break;
4063
4064 case SEG_ABSENT:
4065 /* Do the same thing the VAX asm does */
4066 seg(exp)=SEG_ABSOLUTE;
4067 adds(exp)=0;
4068 subs(exp)=0;
4069 offs(exp)=0;
4070 if(ok==10) {
4071 as_warn("expression out of range: defaulting to 1");
4072 offs(exp)=1;
4073 }
4074 break;
4075 case SEG_ABSOLUTE:
4076 switch(ok) {
4077 case 10:
4078 if(offs(exp)<1 || offs(exp)>8) {
4079 as_warn("expression out of range: defaulting to 1");
4080 offs(exp)=1;
4081 }
4082 break;
4083 case 20:
4084 if(offs(exp)<0 || offs(exp)>7)
4085 goto outrange;
4086 break;
4087 case 30:
4088 if(offs(exp)<0 || offs(exp)>15)
4089 goto outrange;
4090 break;
4091 case 40:
4092 if(offs(exp)<0 || offs(exp)>32)
4093 goto outrange;
4094 break;
4095 case 50:
4096 if(offs(exp)<0 || offs(exp)>127)
4097 goto outrange;
4098 break;
4099 case 55:
4100 if(offs(exp)<-64 || offs(exp)>63)
4101 goto outrange;
4102 break;
4103 case 60:
4104 if(offs(exp)<-128 || offs(exp)>127)
4105 goto outrange;
4106 break;
4107 case 70:
4108 if(offs(exp)<0 || offs(exp)>4095) {
4109 outrange:
4110 as_warn("expression out of range: defaulting to 0");
4111 offs(exp)=0;
4112 }
4113 break;
4114 default:
4115 break;
4116 }
4117 break;
4118 case SEG_TEXT:
4119 case SEG_DATA:
4120 case SEG_BSS:
4121 case SEG_UNKNOWN:
4122 case SEG_DIFFERENCE:
4123 if(ok>=10 && ok<=70) {
4124 seg(exp)=SEG_ABSOLUTE;
4125 adds(exp)=0;
4126 subs(exp)=0;
4127 offs(exp)= (ok==10) ? 1 : 0;
4128 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
4129 }
4130 break;
4131 case SEG_BIG:
4132 if (offs (exp) < 0 /* flonum */
4133 && (ok == 80 /* no bignums */
4134 || (ok > 10 /* small-int ranges including 0 ok */
4135 /* If we have a flonum zero, a zero integer should
4136 do as well (e.g., in moveq). */
4137 && generic_floating_point_number.exponent == 0
4138 && generic_floating_point_number.low[0] == 0)))
4139 {
4140 /* HACK! Turn it into a long */
4141 LITTLENUM_TYPE words[6];
4142
4143 gen_to_words(words,2,8L);/* These numbers are magic! */
4144 seg(exp)=SEG_ABSOLUTE;
4145 adds(exp)=0;
4146 subs(exp)=0;
4147 offs(exp)=words[1]|(words[0]<<16);
4148 }
4149 else if(ok!=0) {
4150 seg(exp)=SEG_ABSOLUTE;
4151 adds(exp)=0;
4152 subs(exp)=0;
4153 offs(exp)= (ok==10) ? 1 : 0;
4154 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
4155 }
4156 break;
4157 default:
4158 as_fatal("failed sanity check.");
4159 }
4160 if(input_line_pointer!=exp->e_end+1)
4161 as_bad("Ignoring junk after expression");
4162 exp->e_end[1]=c_save;
4163 input_line_pointer=save_in;
4164 if(exp->e_siz) {
4165 switch(exp->e_siz) {
4166 case 1:
4167 if(!isbyte(offs(exp)))
4168 as_warn("expression doesn't fit in BYTE");
4169 break;
4170 case 2:
4171 if(!isword(offs(exp)))
4172 as_warn("expression doesn't fit in WORD");
4173 break;
4174 }
4175 }
4176 return offs(exp);
4177 #endif
4178 } /* get_num() */
4179
4180 /* These are the back-ends for the various machine dependent pseudo-ops. */
4181 void demand_empty_rest_of_line(); /* Hate those extra verbose names */
4182
4183 static void s_data1() {
4184 subseg_new(SEG_DATA,1);
4185 demand_empty_rest_of_line();
4186 } /* s_data1() */
4187
4188 static void s_data2() {
4189 subseg_new(SEG_DATA,2);
4190 demand_empty_rest_of_line();
4191 } /* s_data2() */
4192
4193 static void s_bss()
4194 {
4195 /* We don't support putting frags in the BSS segment, we fake it
4196 by marking in_bss, then looking at s_skip for clues */
4197
4198 subseg_new(SEG_BSS, 0);
4199 demand_empty_rest_of_line();
4200 } /* s_bss() */
4201
4202 static void s_even() {
4203 register int temp;
4204 register long temp_fill;
4205
4206 temp = 1; /* JF should be 2? */
4207 temp_fill = get_absolute_expression ();
4208 if ( ! need_pass_2 ) /* Never make frag if expect extra pass. */
4209 frag_align (temp, (int)temp_fill);
4210 demand_empty_rest_of_line();
4211 } /* s_even() */
4212
4213 static void s_proc() {
4214 demand_empty_rest_of_line();
4215 } /* s_proc() */
4216
4217 /* s_space is defined in read.c .skip is simply an alias to it. */
4218
4219 /*
4220 * md_parse_option
4221 * Invocation line includes a switch not recognized by the base assembler.
4222 * See if it's a processor-specific option. These are:
4223 *
4224 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4225 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4226 * Select the architecture. Instructions or features not
4227 * supported by the selected architecture cause fatal
4228 * errors. More than one may be specified. The default is
4229 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4230 * for -m68000, and -m68882 is a synonym for -m68881.
4231 *
4232 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4233 * (e.g. m68020) also requests that float instructions be included. This
4234 * is the default setup, mostly to avoid hassling users. A better
4235 * rearrangement of this structure would be to add an option to DENY
4236 * floating point opcodes, for people who want to really know there's none
4237 * of that funny floaty stuff going on. FIXME-later.
4238 */
4239 #ifndef MAYBE_FLOAT_TOO
4240 #define MAYBE_FLOAT_TOO m68881
4241 #endif
4242
4243 int md_parse_option(argP,cntP,vecP)
4244 char **argP;
4245 int *cntP;
4246 char ***vecP;
4247 {
4248 switch(**argP) {
4249 case 'l': /* -l means keep external to 2 bit offset
4250 rather than 16 bit one */
4251 break;
4252
4253 case 'S': /* -S means that jbsr's always turn into jsr's. */
4254 break;
4255
4256 case 'A':
4257 (*argP)++;
4258 /* intentional fall-through */
4259 case 'm':
4260 (*argP)++;
4261
4262 if (**argP=='c') {
4263 (*argP)++;
4264 } /* allow an optional "c" */
4265
4266 if (!strcmp(*argP, "68000")
4267 || !strcmp(*argP, "68008")) {
4268 current_architecture |= m68000;
4269 } else if (!strcmp(*argP, "68010")) {
4270 #ifdef TE_SUN
4271 omagic= 1<<16|OMAGIC;
4272 #endif
4273 current_architecture |= m68010;
4274
4275 } else if (!strcmp(*argP, "68020")) {
4276 current_architecture |= m68020 | MAYBE_FLOAT_TOO;
4277
4278 } else if (!strcmp(*argP, "68030")) {
4279 current_architecture |= m68030 | MAYBE_FLOAT_TOO;
4280
4281 } else if (!strcmp(*argP, "68040")) {
4282 current_architecture |= m68040 | MAYBE_FLOAT_TOO;
4283
4284 #ifndef NO_68881
4285 } else if (!strcmp(*argP, "68881")) {
4286 current_architecture |= m68881;
4287
4288 } else if (!strcmp(*argP, "68882")) {
4289 current_architecture |= m68882;
4290
4291 #endif /* NO_68881 */
4292 #ifndef NO_68851
4293 } else if (!strcmp(*argP,"68851")) {
4294 current_architecture |= m68851;
4295
4296 #endif /* NO_68851 */
4297 } else {
4298 as_warn("Unknown architecture, \"%s\". option ignored", *argP);
4299 } /* switch on architecture */
4300
4301 while(**argP) (*argP)++;
4302
4303 break;
4304
4305 case 'p':
4306 if (!strcmp(*argP,"pic")) {
4307 (*argP) += 3;
4308 break; /* -pic, Position Independent Code */
4309 } else {
4310 return(0);
4311 } /* pic or not */
4312
4313 default:
4314 return 0;
4315 }
4316 return 1;
4317 }
4318
4319
4320 #ifdef TEST2
4321
4322 /* TEST2: Test md_assemble() */
4323 /* Warning, this routine probably doesn't work anymore */
4324
4325 main()
4326 {
4327 struct m68k_it the_ins;
4328 char buf[120];
4329 char *cp;
4330 int n;
4331
4332 m68k_ip_begin();
4333 for(;;) {
4334 if(!gets(buf) || !*buf)
4335 break;
4336 if(buf[0]=='|' || buf[1]=='.')
4337 continue;
4338 for(cp=buf;*cp;cp++)
4339 if(*cp=='\t')
4340 *cp=' ';
4341 if(is_label(buf))
4342 continue;
4343 memset(&the_ins, '\0', sizeof(the_ins));
4344 m68k_ip(&the_ins,buf);
4345 if(the_ins.error) {
4346 printf("Error %s in %s\n",the_ins.error,buf);
4347 } else {
4348 printf("Opcode(%d.%s): ",the_ins.numo,the_ins.args);
4349 for(n=0;n<the_ins.numo;n++)
4350 printf(" 0x%x",the_ins.opcode[n]&0xffff);
4351 printf(" ");
4352 print_the_insn(&the_ins.opcode[0],stdout);
4353 (void)putchar('\n');
4354 }
4355 for(n=0;n<strlen(the_ins.args)/2;n++) {
4356 if(the_ins.operands[n].error) {
4357 printf("op%d Error %s in %s\n",n,the_ins.operands[n].error,buf);
4358 continue;
4359 }
4360 printf("mode %d, reg %d, ",the_ins.operands[n].mode,the_ins.operands[n].reg);
4361 if(the_ins.operands[n].b_const)
4362 printf("Constant: '%.*s', ",1+the_ins.operands[n].e_const-the_ins.operands[n].b_const,the_ins.operands[n].b_const);
4363 printf("ireg %d, isiz %d, imul %d, ",the_ins.operands[n].ireg,the_ins.operands[n].isiz,the_ins.operands[n].imul);
4364 if(the_ins.operands[n].b_iadd)
4365 printf("Iadd: '%.*s',",1+the_ins.operands[n].e_iadd-the_ins.operands[n].b_iadd,the_ins.operands[n].b_iadd);
4366 (void)putchar('\n');
4367 }
4368 }
4369 m68k_ip_end();
4370 return 0;
4371 }
4372
4373 is_label(str)
4374 char *str;
4375 {
4376 while(*str==' ')
4377 str++;
4378 while(*str && *str!=' ')
4379 str++;
4380 if(str[-1]==':' || str[1]=='=')
4381 return 1;
4382 return 0;
4383 }
4384
4385 #endif
4386
4387 /* Possible states for relaxation:
4388
4389 0 0 branch offset byte (bra, etc)
4390 0 1 word
4391 0 2 long
4392
4393 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4394 1 1 word
4395 1 2 long
4396
4397 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4398 2 1 word-long
4399 2 2 long-word
4400 2 3 long-long
4401
4402 */
4403
4404
4405
4406 #ifdef DONTDEF
4407 abort()
4408 {
4409 printf("ABORT!\n");
4410 exit(12);
4411 }
4412
4413 print_frags()
4414 {
4415 fragS *fragP;
4416 extern fragS *text_frag_root;
4417
4418 for(fragP=text_frag_root;fragP;fragP=fragP->fr_next) {
4419 printf("addr %lu next 0x%x fix %ld var %ld symbol 0x%x offset %ld\n",
4420 fragP->fr_address,fragP->fr_next,fragP->fr_fix,fragP->fr_var,fragP->fr_symbol,fragP->fr_offset);
4421 printf("opcode 0x%x type %d subtype %d\n\n",fragP->fr_opcode,fragP->fr_type,fragP->fr_subtype);
4422 }
4423 fflush(stdout);
4424 return 0;
4425 }
4426 #endif
4427
4428 #ifdef DONTDEF
4429 /*VARARGS1*/
4430 panic(format,args)
4431 char *format;
4432 {
4433 fputs("Internal error:",stderr);
4434 _doprnt(format,&args,stderr);
4435 (void)putc('\n',stderr);
4436 as_where();
4437 abort();
4438 }
4439 #endif
4440
4441 /* We have no need to default values of symbols. */
4442
4443 /* ARGSUSED */
4444 symbolS *
4445 md_undefined_symbol (name)
4446 char *name;
4447 {
4448 return 0;
4449 }
4450
4451 /* Parse an operand that is machine-specific.
4452 We just return without modifying the expression if we have nothing
4453 to do. */
4454
4455 /* ARGSUSED */
4456 void
4457 md_operand (expressionP)
4458 expressionS *expressionP;
4459 {
4460 }
4461
4462 /* Round up a section size to the appropriate boundary. */
4463 long
4464 md_section_align (segment, size)
4465 segT segment;
4466 long size;
4467 {
4468 return size; /* Byte alignment is fine */
4469 }
4470
4471 /* Exactly what point is a PC-relative offset relative TO?
4472 On the 68k, they're relative to the address of the offset, plus
4473 its size. (??? Is this right? FIXME-SOON!) */
4474 long
4475 md_pcrel_from (fixP)
4476 fixS *fixP;
4477 {
4478 return(fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address);
4479 }
4480
4481 void
4482 tc_coff_symbol_emit_hook ()
4483 {
4484 }
4485
4486 int
4487 tc_coff_sizemachdep(frag)
4488 fragS *frag;
4489 {
4490 switch (frag->fr_subtype & 0x3)
4491 {
4492 case BYTE: return 1;
4493 case SHORT: return 2;
4494 case LONG: return 4;
4495 default: abort();
4496 }
4497
4498 }
4499 /*
4500 * Local Variables:
4501 * comment-column: 0
4502 * fill-column: 131
4503 * End:
4504 */
4505
4506 /* end of tc-m68k.c */
4507
GDB Binutils - Deliverables
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