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68060 support
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
2 slow to compile, easy to find file.
3
4 Copyright (C) 1987, 1991, 1992, 1993 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21
22 #include <ctype.h>
23 #define NO_RELOC 0
24 #include "as.h"
25
26 /* need TARGET_CPU */
27 #include "config.h"
28
29 #include "obstack.h"
30
31 /* The opcode table is too big for gcc, which (currently) requires
32 exponential space at compile time for initialized arrays. */
33 #ifdef __GNUC__
34 #define DO_BREAK_UP_BIG_DECL
35 #define BREAK_UP_BIG_DECL }; struct m68k_opcode m68k_opcodes_2[] = {
36 #define AND_OTHER_PART sizeof (m68k_opcodes_2)
37 #endif
38
39 /* Note that this file includes real declarations and thus can only be
40 included by one source file per executable. */
41 #include "opcode/m68k.h"
42
43 /* This array holds the chars that always start a comment. If the
44 pre-processor is disabled, these aren't very useful */
45 CONST char comment_chars[] = "|";
46
47 /* This array holds the chars that only start a comment at the beginning of
48 a line. If the line seems to have the form '# 123 filename'
49 .line and .file directives will appear in the pre-processed output */
50 /* Note that input_file.c hand checks for '#' at the beginning of the
51 first line of the input file. This is because the compiler outputs
52 #NO_APP at the beginning of its output. */
53 /* Also note that comments like this one will always work. */
54 CONST char line_comment_chars[] = "#";
55
56 CONST char line_separator_chars[] = "";
57
58 /* Chars that can be used to separate mant from exp in floating point nums */
59 CONST char EXP_CHARS[] = "eE";
60
61 /* Chars that mean this number is a floating point constant, as
62 in "0f12.456" or "0d1.2345e12". */
63
64 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
65
66 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
67 changed in read.c . Ideally it shouldn't have to know about it at all,
68 but nothing is ideal around here. */
69
70 const int md_reloc_size = 8; /* Size of relocation record */
71
72 /* Are we trying to generate PIC code? If so, absolute references
73 ought to be made into linkage table references or pc-relative
74 references. */
75 int flag_want_pic;
76
77 #ifdef REGISTER_PREFIX_OPTIONAL
78 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
79 #else
80 int flag_reg_prefix_optional;
81 #endif
82
83 /* Its an arbitrary name: This means I don't approve of it */
84 /* See flames below */
85 static struct obstack robyn;
86
87 #define TAB(x,y) (((x)<<2)+(y))
88 #define TABTYPE(xy) ((xy) >> 2)
89 #define BYTE 0
90 #define SHORT 1
91 #define LONG 2
92 #define SZ_UNDEF 3
93 #undef BRANCH
94 #define ABRANCH 1
95 #define FBRANCH 2
96 #define PCREL 3
97 #define BCC68000 4
98 #define DBCC 5
99 #define PCLEA 6
100
101 struct m68k_incant
102 {
103 char *m_operands;
104 unsigned long m_opcode;
105 short m_opnum;
106 short m_codenum;
107 int m_arch;
108 struct m68k_incant *m_next;
109 };
110
111 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
112 #define gettwo(x) (((x)->m_opcode)&0xffff)
113
114 /* Operands we can parse: (And associated modes)
115
116 numb: 8 bit num
117 numw: 16 bit num
118 numl: 32 bit num
119 dreg: data reg 0-7
120 reg: address or data register
121 areg: address register
122 apc: address register, PC, ZPC or empty string
123 num: 16 or 32 bit num
124 num2: like num
125 sz: w or l if omitted, l assumed
126 scale: 1 2 4 or 8 if omitted, 1 assumed
127
128 7.4 IMMED #num --> NUM
129 0.? DREG dreg --> dreg
130 1.? AREG areg --> areg
131 2.? AINDR areg@ --> *(areg)
132 3.? AINC areg@+ --> *(areg++)
133 4.? ADEC areg@- --> *(--areg)
134 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
135 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
136 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
137 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
138 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
139 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
140 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
141 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
142 7.0 ABSL num:sz --> *(num)
143 num --> *(num) (sz L assumed)
144 *** MSCR otherreg --> Magic
145 With -l option
146 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
147 ?.? DINDR dreg@ --> (dreg) -- cas2 only
148
149 examples:
150 #foo #0x35 #12
151 d2
152 a4
153 a3@
154 a5@+
155 a6@-
156 a2@(12) pc@(14)
157 a1@(5,d2:w:1) @(45,d6:l:4)
158 pc@(a2) @(d4)
159 etc . . .
160
161
162 #name@(numw) -->turn into PC rel mode
163 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
164
165 */
166
167 enum operand_type
168 {
169 IMMED = 1,
170 DREG,
171 AREG,
172 AINDR,
173 ADEC,
174 AINC,
175 AOFF,
176 AINDX,
177 APODX,
178 AMIND,
179 APRDX,
180 ABSL,
181 MSCR,
182 REGLST,
183 DINDR
184 };
185
186
187 struct m68k_exp
188 {
189 char *e_beg;
190 char *e_end;
191 segT e_seg;
192 expressionS e_exp;
193 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
194 };
195
196 /* DATA and ADDR have to be contiguous, so that reg-DATA gives
197 0-7==data reg, 8-15==addr reg for operands that take both types.
198
199 We don't use forms like "ADDR0 = ADDR" here because this file is
200 likely to be used on an Apollo, and the broken Apollo compiler
201 gives an `undefined variable' error if we do that, according to
202 troy@cbme.unsw.edu.au. */
203
204 #define DATA DATA0
205 #define ADDR ADDR0
206 #define SP ADDR7
207 #define FPREG FP0
208 #define COPNUM COP0
209 #define BAD BAD0
210 #define BAC BAC0
211
212 enum _register
213 {
214 DATA0 = 1, /* 1- 8 == data registers 0-7 */
215 DATA1,
216 DATA2,
217 DATA3,
218 DATA4,
219 DATA5,
220 DATA6,
221 DATA7,
222
223 ADDR0,
224 ADDR1,
225 ADDR2,
226 ADDR3,
227 ADDR4,
228 ADDR5,
229 ADDR6,
230 ADDR7,
231
232 /* Note that COP0==processor #1 -- COP0+7==#8, which stores as 000 */
233 /* I think. . . */
234
235 FP0, /* Eight FP registers */
236 FP1,
237 FP2,
238 FP3,
239 FP4,
240 FP5,
241 FP6,
242 FP7,
243
244 COP0, /* Co-processor #1-#8 */
245 COP1,
246 COP2,
247 COP3,
248 COP4,
249 COP5,
250 COP6,
251 COP7,
252
253 PC, /* Program counter */
254 ZPC, /* Hack for Program space, but 0 addressing */
255 SR, /* Status Reg */
256 CCR, /* Condition code Reg */
257
258 /* These have to be grouped together for the movec instruction to work. */
259 USP, /* User Stack Pointer */
260 ISP, /* Interrupt stack pointer */
261 SFC,
262 DFC,
263 CACR,
264 VBR,
265 CAAR,
266 MSP,
267 ITT0,
268 ITT1,
269 DTT0,
270 DTT1,
271 MMUSR,
272 TC,
273 SRP,
274 URP,
275 BUSCR, /* 68060 added these */
276 PCR,
277 #define last_movec_reg PCR
278 /* end of movec ordering constraints */
279
280 FPI,
281 FPS,
282 FPC,
283
284 DRP, /* 68851 or 68030 MMU regs */
285 CRP,
286 CAL,
287 VAL,
288 SCC,
289 AC,
290 BAD0,
291 BAD1,
292 BAD2,
293 BAD3,
294 BAD4,
295 BAD5,
296 BAD6,
297 BAD7,
298 BAC0,
299 BAC1,
300 BAC2,
301 BAC3,
302 BAC4,
303 BAC5,
304 BAC6,
305 BAC7,
306 PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040)
307 and ACUSR on 68ec030 */
308 PCSR,
309
310 IC, /* instruction cache token */
311 DC, /* data cache token */
312 NC, /* no cache token */
313 BC, /* both caches token */
314
315 TT0, /* 68030 access control unit regs */
316 TT1,
317 };
318
319 static const enum _register m68000_control_regs[] = { 0 };
320 static const enum _register m68010_control_regs[] = {
321 SFC, DFC, USP, VBR,
322 0
323 };
324 static const enum _register m68020_control_regs[] = {
325 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
326 0
327 };
328 static const enum _register m68040_control_regs[] = {
329 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
330 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
331 0
332 };
333 static const enum _register m68060_control_regs[] = {
334 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
335 USP, VBR, URP, SRP, PCR,
336 0
337 };
338
339 static const enum _register *control_regs;
340
341 /* Internal form of an operand. */
342 struct m68k_op
343 {
344 char *error; /* Couldn't parse it */
345 enum operand_type mode; /* What mode this instruction is in. */
346 enum _register reg; /* Base register */
347 struct m68k_exp *con1;
348 int ireg; /* Index register */
349 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
350 int imul; /* Multipy ireg by this (1,2,4,or 8) */
351 struct m68k_exp *con2;
352 };
353
354 /* internal form of a 68020 instruction */
355 struct m68k_it
356 {
357 char *error;
358 char *args; /* list of opcode info */
359 int numargs;
360
361 int numo; /* Number of shorts in opcode */
362 short opcode[11];
363
364 struct m68k_op operands[6];
365
366 int nexp; /* number of exprs in use */
367 struct m68k_exp exprs[4];
368
369 int nfrag; /* Number of frags we have to produce */
370 struct
371 {
372 int fragoff; /* Where in the current opcode[] the frag ends */
373 symbolS *fadd;
374 long foff;
375 int fragty;
376 }
377 fragb[4];
378
379 int nrel; /* Num of reloc strucs in use */
380 struct
381 {
382 int n;
383 expressionS exp;
384 char wid;
385 char pcrel;
386 }
387 reloc[5]; /* Five is enough??? */
388 };
389
390 #define cpu_of_arch(x) ((x) & m68000up)
391 #define float_of_arch(x) ((x) & mfloat)
392 #define mmu_of_arch(x) ((x) & mmmu)
393
394 static struct m68k_it the_ins; /* the instruction being assembled */
395
396 #define seg(exp) ((exp)->e_seg)
397 #define op(exp) ((exp)->e_exp.X_op)
398 #define adds(exp) ((exp)->e_exp.X_add_symbol)
399 #define subs(exp) ((exp)->e_exp.X_op_symbol)
400 #define offs(exp) ((exp)->e_exp.X_add_number)
401
402 /* Macros for adding things to the m68k_it struct */
403
404 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
405
406 /* Like addword, but goes BEFORE general operands */
407 static void
408 insop (w, opcode)
409 int w;
410 struct m68k_incant *opcode;
411 {
412 int z;
413 for(z=the_ins.numo;z>opcode->m_codenum;--z)
414 the_ins.opcode[z]=the_ins.opcode[z-1];
415 for(z=0;z<the_ins.nrel;z++)
416 the_ins.reloc[z].n+=2;
417 the_ins.opcode[opcode->m_codenum]=w;
418 the_ins.numo++;
419 }
420
421 static struct m68k_exp *
422 add_exp (beg, end)
423 char *beg;
424 char *end;
425 {
426 the_ins.exprs[the_ins.nexp].e_beg=beg;
427 the_ins.exprs[the_ins.nexp].e_end=end;
428 return &the_ins.exprs[the_ins.nexp++];
429 }
430
431
432 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
433 Blecch. */
434 static void
435 add_fix (width, exp, pc_rel)
436 char width;
437 struct m68k_exp *exp;
438 int pc_rel;
439 {
440 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
441 ? (the_ins.numo*2-1)
442 : (((width)=='b')
443 ? ((the_ins.numo-1)*2)
444 : (the_ins.numo*2)));
445 the_ins.reloc[the_ins.nrel].exp = exp->e_exp;
446 the_ins.reloc[the_ins.nrel].wid = width;
447 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
448 }
449
450 static void
451 add_frag(add,off,type)
452 symbolS *add;
453 long off;
454 int type;
455 {
456 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
457 the_ins.fragb[the_ins.nfrag].fadd=add;
458 the_ins.fragb[the_ins.nfrag].foff=off;
459 the_ins.fragb[the_ins.nfrag++].fragty=type;
460 }
461
462 #define isvar(exp) \
463 ((exp) && op (exp) != O_constant && op (exp) != O_big)
464
465 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
466 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
467 static int get_regs PARAMS ((int i, char *str, struct m68k_op *opP));
468 static int reverse_16_bits PARAMS ((int in));
469 static int reverse_8_bits PARAMS ((int in));
470 static int try_index PARAMS ((char **s, struct m68k_op *opP));
471 static void install_gen_operand PARAMS ((int mode, int val));
472 static void install_operand PARAMS ((int mode, int val));
473 static void s_bss PARAMS ((int));
474 static void s_data1 PARAMS ((int));
475 static void s_data2 PARAMS ((int));
476 static void s_even PARAMS ((int));
477 static void s_proc PARAMS ((int));
478
479 static int current_architecture;
480
481 /* BCC68000 is for patching in an extra jmp instruction for long offsets
482 on the 68000. The 68000 doesn't support long branches with branchs */
483
484 /* This table desribes how you change sizes for the various types of variable
485 size expressions. This version only supports two kinds. */
486
487 /* Note that calls to frag_var need to specify the maximum expansion
488 needed; this is currently 10 bytes for DBCC. */
489
490 /* The fields are:
491 How far Forward this mode will reach:
492 How far Backward this mode will reach:
493 How many bytes this mode will add to the size of the frag
494 Which mode to go to if the offset won't fit in this one
495 */
496 CONST relax_typeS md_relax_table[] =
497 {
498 {1, 1, 0, 0}, /* First entries aren't used */
499 {1, 1, 0, 0}, /* For no good reason except */
500 {1, 1, 0, 0}, /* that the VAX doesn't either */
501 {1, 1, 0, 0},
502
503 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
504 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
505 {0, 0, 4, 0},
506 {1, 1, 0, 0},
507
508 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
509 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
510 {0, 0, 4, 0},
511 {1, 1, 0, 0},
512
513 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
514 {(32767), (-32768), 2, TAB (PCREL, LONG)},
515 {0, 0, 4, 0},
516 {1, 1, 0, 0},
517
518 {(127), (-128), 0, TAB (BCC68000, SHORT)},
519 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
520 {0, 0, 6, 0}, /* jmp long space */
521 {1, 1, 0, 0},
522
523 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
524 {(32767), (-32768), 2, TAB (DBCC, LONG)},
525 {0, 0, 10, 0}, /* bra/jmp long space */
526 {1, 1, 0, 0},
527
528 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
529 {32767, -32768, 2, TAB (PCLEA, LONG)},
530 {0, 0, 6, 0},
531 {1, 1, 0, 0},
532
533 };
534
535 /* These are the machine dependent pseudo-ops. These are included so
536 the assembler can work on the output from the SUN C compiler, which
537 generates these.
538 */
539
540 /* This table describes all the machine specific pseudo-ops the assembler
541 has to support. The fields are:
542 pseudo-op name without dot
543 function to call to execute this pseudo-op
544 Integer arg to pass to the function
545 */
546 CONST pseudo_typeS md_pseudo_table[] =
547 {
548 {"data1", s_data1, 0},
549 {"data2", s_data2, 0},
550 {"bss", s_bss, 0},
551 {"even", s_even, 0},
552 {"skip", s_space, 0},
553 {"proc", s_proc, 0},
554 #ifdef TE_SUN3
555 {"align", s_align_bytes, 0},
556 #endif
557 {0, 0, 0}
558 };
559
560
561 /* The mote pseudo ops are put into the opcode table, since they
562 don't start with a . they look like opcodes to gas.
563 */
564 extern void obj_coff_section ();
565
566 CONST pseudo_typeS mote_pseudo_table[] =
567 {
568
569 {"dc.l", cons, 4},
570 {"dc", cons, 2},
571 {"dc.w", cons, 2},
572 {"dc.b", cons, 1},
573
574 {"ds.l", s_space, 4},
575 {"ds", s_space, 2},
576 {"ds.w", s_space, 2},
577 {"ds.b", s_space, 1},
578
579 {"xdef", s_globl, 0},
580 {"align", s_align_ptwo, 0},
581 #ifdef M68KCOFF
582 {"sect", obj_coff_section, 0},
583 {"section", obj_coff_section, 0},
584 #endif
585 {0, 0, 0}
586 };
587
588 #define issbyte(x) ((x)>=-128 && (x)<=127)
589 #define isubyte(x) ((x)>=0 && (x)<=255)
590 #define issword(x) ((x)>=-32768 && (x)<=32767)
591 #define isuword(x) ((x)>=0 && (x)<=65535)
592
593 #define isbyte(x) ((x)>= -255 && (x)<=255)
594 #define isword(x) ((x)>=-32768 && (x)<=65535)
595 #define islong(x) (1)
596
597 extern char *input_line_pointer;
598
599 enum
600 {
601 FAIL = 0,
602 OK = 1,
603 };
604
605 /* JF these tables here are for speed at the expense of size */
606 /* You can replace them with the #if 0 versions if you really
607 need space and don't mind it running a bit slower */
608
609 static char mklower_table[256];
610 #define mklower(c) (mklower_table[(unsigned char)(c)])
611 static char notend_table[256];
612 static char alt_notend_table[256];
613 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
614 alt_notend_table[(unsigned char)(s[1])])))
615
616 #if 0
617 #define mklower(c) (isupper(c) ? tolower(c) : c)
618 #endif
619
620
621 /* JF modified this to handle cases where the first part of a symbol name
622 looks like a register */
623
624 /*
625 * m68k_reg_parse() := if it looks like a register, return it's token &
626 * advance the pointer.
627 */
628
629 enum _register
630 m68k_reg_parse (ccp)
631 register char **ccp;
632 {
633 char *start = *ccp;
634 char c;
635 char *p;
636 symbolS *symbolP;
637
638 if (flag_reg_prefix_optional)
639 {
640 if (*start == REGISTER_PREFIX)
641 start++;
642 p = start;
643 }
644 else
645 {
646 if (*start != REGISTER_PREFIX)
647 return FAIL;
648 p = start + 1;
649 }
650
651 if (!isalpha (*p) || !is_name_beginner (*p))
652 return FAIL;
653
654 c = *p++;
655 while (isalpha (c) || isdigit (c) || c == '_')
656 {
657 c = *p++;
658 }
659
660 *--p = 0;
661 symbolP = symbol_find (start);
662 *p = c;
663
664 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
665 {
666 *ccp = p;
667 return S_GET_VALUE (symbolP);
668 }
669
670 return FAIL;
671 }
672
673 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
674 #define SKIP_W() { ss++; if(*ss==' ') ss++;}
675
676 /* Parse an index specification using Motorola syntax. */
677
678 static int
679 try_moto_index (s, opP)
680 char **s;
681 struct m68k_op *opP;
682 {
683 register int i;
684 char *ss;
685
686 ss = *s;
687 /* SKIP_W(); */
688 if (*ss == ' ')
689 ss++;
690 i = m68k_reg_parse (&ss);
691 if (!(i >= DATA + 0 && i <= ADDR + 7))
692 { /* if i is not DATA or ADDR reg */
693 opP->error = "Invalid index register";
694 *s = ss;
695 return FAIL;
696 }
697 opP->ireg = i;
698 /* SKIP_W(); */
699 if (*ss == ')')
700 {
701 opP->isiz = 0;
702 opP->imul = 1;
703 SKIP_W ();
704 *s = ss;
705 return OK;
706 }
707 if (*ss != '.')
708 {
709 opP->error = "Missing . in index register";
710 *s = ss;
711 return FAIL;
712 }
713 SKIP_W ();
714 if (mklower (*ss) == 'w')
715 opP->isiz = 2;
716 else if (mklower (*ss) == 'l')
717 opP->isiz = 3;
718 else
719 {
720 opP->error = "Size spec not .W or .L";
721 *s = ss;
722 return FAIL;
723 }
724 SKIP_W ();
725 if (*ss == '.' || *ss == '*')
726 {
727 SKIP_W ();
728 switch (*ss)
729 {
730 case '1':
731 case '2':
732 case '4':
733 case '8':
734 opP->imul = *ss - '0';
735 break;
736 default:
737 opP->error = "index multiplier not 1, 2, 4 or 8";
738 *s = ss;
739 return FAIL;
740 }
741 SKIP_W ();
742 }
743 else
744 opP->imul = 1;
745 if (*ss != ')')
746 {
747 opP->error = "Missing )";
748 *s = ss;
749 return FAIL;
750 }
751 SKIP_W ();
752 *s = ss;
753 return OK;
754 }
755
756 /*
757 *
758 * try_index := data_or_address_register + ')' + SKIP_W
759 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
760 *
761 * multiplier := <empty>
762 * | ':' + multiplier_number
763 * ;
764 *
765 * multiplier_number := '1' | '2' | '4' | '8' ;
766 *
767 * size_spec := 'l' | 'L' | 'w' | 'W' ;
768 *
769 * SKIP_W := <empty> | ' ' ;
770 *
771 */
772
773 static int
774 try_index (s, opP)
775 char **s;
776 struct m68k_op *opP;
777 {
778 register int i;
779 char *ss;
780
781 ss = *s;
782 /* SKIP_W(); */
783 i = m68k_reg_parse (&ss);
784 if (!(i >= DATA + 0 && i <= ADDR + 7))
785 { /* if i is not DATA or ADDR reg */
786 *s = ss;
787 return FAIL;
788 }
789 opP->ireg = i;
790 /* SKIP_W(); */
791 if (*ss == ')')
792 {
793 opP->isiz = 0;
794 opP->imul = 1;
795 SKIP_W ();
796 *s = ss;
797 return OK;
798 }
799 if (*ss != ':')
800 {
801 opP->error = "Missing : in index register";
802 *s = ss;
803 return FAIL;
804 }
805 SKIP_W ();
806 switch (*ss)
807 {
808 case 'w':
809 case 'W':
810 opP->isiz = 2;
811 break;
812 case 'l':
813 case 'L':
814 opP->isiz = 3;
815 break;
816 default:
817 opP->error = "Index register size spec not :w or :l";
818 *s = ss;
819 return FAIL;
820 }
821 SKIP_W ();
822 if (*ss == ':')
823 {
824 SKIP_W ();
825 switch (*ss)
826 {
827 case '1':
828 case '2':
829 case '4':
830 case '8':
831 if (cpu_of_arch (current_architecture) < m68020)
832 {
833 opP->error = "no index scaling in pre-68020's";
834 *s = ss;
835 return FAIL;
836 }
837 opP->imul = *ss - '0';
838 break;
839 default:
840 opP->error = "index multiplier not 1, 2, 4 or 8";
841 *s = ss;
842 return FAIL;
843 }
844 SKIP_W ();
845 }
846 else
847 opP->imul = 1;
848 if (*ss != ')')
849 {
850 opP->error = "Missing )";
851 *s = ss;
852 return FAIL;
853 }
854 SKIP_W ();
855 *s = ss;
856 return OK;
857 } /* try_index() */
858
859 /* Ian Taylor expanded this function to accept both MIT and Motorola
860 syntax. I removed the old comment, since it was wrong. The syntax
861 this accepted even before my changes was complex and undocumented.
862 I mainly added a large case when the operand string does not
863 contain an '@', since the Motorola syntax does not use the '@'
864 character. */
865
866 int
867 m68k_ip_op (str, opP)
868 char *str;
869 register struct m68k_op *opP;
870 {
871 char *strend;
872 long i;
873 char *parse_index ();
874 int needp;
875
876 if (*str == ' ')
877 {
878 str++;
879 } /* Find the beginning of the string */
880
881 if (!*str)
882 {
883 opP->error = "Missing operand";
884 return FAIL;
885 } /* Out of gas */
886
887 for (strend = str; *strend; strend++)
888 ;
889 --strend;
890
891 if (*str == '#' || *str == '&')
892 {
893 str++;
894 opP->con1 = add_exp (str, strend);
895 opP->mode = IMMED;
896 return OK;
897 } /* Guess what: A constant. Shar and enjoy */
898
899 i = m68k_reg_parse (&str);
900
901 if (i != FAIL)
902 {
903 if (*str == '/' || *str == '-')
904 {
905 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
906 opP->mode = REGLST;
907 return get_regs (i, str, opP);
908 }
909 if (*str == '\0')
910 {
911 opP->reg = i;
912 /* "Rn" Register Direct mode */
913 if (i >= DATA + 0 && i <= DATA + 7)
914 opP->mode = DREG;
915 else if (i >= ADDR + 0 && i <= ADDR + 7)
916 opP->mode = AREG;
917 else
918 opP->mode = MSCR;
919 return OK;
920 }
921 }
922
923 if (*str != '@')
924 {
925 char *stmp;
926
927 if ((stmp = strchr (str, '@')) != 0)
928 {
929 opP->con1 = add_exp (str, stmp - 1);
930 if (stmp == strend)
931 {
932 opP->mode = AINDX;
933 return (OK);
934 }
935
936 if ((current_architecture & m68020up) == 0)
937 {
938 return (FAIL);
939 } /* if target is not a '20 or better */
940
941 stmp++;
942 if (*stmp++ != '(' || *strend-- != ')')
943 {
944 opP->error = "Malformed operand";
945 return (FAIL);
946 }
947 i = try_index (&stmp, opP);
948 opP->con2 = add_exp (stmp, strend);
949
950 if (i == FAIL)
951 {
952 opP->mode = AMIND;
953 }
954 else
955 {
956 opP->mode = APODX;
957 }
958 return (OK);
959 } /* if there's an '@' */
960
961 #ifndef MIT_SYNTAX_ONLY
962 /* The operand has no '@'. Try to parse it using
963 Motorola syntax. */
964 /* Logic of the parsing switch(*str):
965 case opP->mode =
966 ---- -----------
967 #anything IMMED 1
968 REG AREG or DREG or MSCR 3 or 2 or 13
969 REG- or REG/ REGLST 14
970 (REG) AINDR 4
971 (REG)+ AINC 6
972 (REG,INDX) AINDX 8
973 (EXPR,REG) AOFF 7
974 (EXPR,REG,INDX) AINDX 8
975 -(REG) ADEC 5
976 EXP2(REG) AOFF 7
977 EXP2(REG,INDX) AINDX 8
978 EXP2 ABSL 12
979
980 REG means truth(m68k_reg_parse(&str))
981 INDX means truth(try_moto_index(&str,opP))
982 EXPR means not REG
983 EXP2 means not REG and not '(' and not '-('
984 */
985
986 if (*str == '(')
987 {
988 str++;
989 i = m68k_reg_parse (&str);
990 if ((i < ADDR + 0 || i > ADDR + 7)
991 && (i < DATA + 0 || i > DATA + 7
992 || *str != ')' || str[1] != '0')
993 && i != PC && i != ZPC && i != FAIL)
994 {
995 /* Can't indirect off non address regs */
996 opP->error = "Invalid indirect register";
997 return FAIL;
998 }
999 if (i != FAIL)
1000 {
1001 opP->reg = i;
1002 if (*str == ')')
1003 {
1004 str++;
1005 if (*str == '\0')
1006 {
1007 /* "(An)" Address Register Indirect mode
1008 or "(Dn)" for cas2. */
1009 if (i >= DATA + 0 && i <= DATA + 7)
1010 opP->mode = DINDR;
1011 else
1012 opP->mode = AINDR;
1013 return OK;
1014 }
1015 if (*str == '+')
1016 {
1017 if (str[1] == '\0')
1018 {
1019 /* "(An)+" Register Indirect w Postincrement */
1020 opP->mode = AINC;
1021 return OK;
1022 }
1023 }
1024 opP->error = "Junk after indirect";
1025 return FAIL;
1026 }
1027 if (*str == ',')
1028 {
1029 str++;
1030 i = try_moto_index (&str, opP);
1031 if (i == FAIL)
1032 return FAIL;
1033 /* "(An,Rn)" Register Indirect with Index mode*/
1034 opP->mode = AINDX;
1035 return OK;
1036 }
1037 else
1038 {
1039 opP->error = "Bad indirect syntax";
1040 return FAIL;
1041 }
1042 }
1043 else
1044 {
1045 /* "(EXPR,..." , a displacement */
1046 char *stmp;
1047
1048 if ((stmp = strchr (str, ',')) != NULL)
1049 {
1050 opP->con1 = add_exp (str, stmp - 1);
1051 str = stmp;
1052 SKIP_WHITE ();
1053 i = m68k_reg_parse (&str);
1054 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC)
1055 {
1056 /* Can't indirect off non address regs */
1057 opP->error = "Invalid indirect register";
1058 return FAIL;
1059 }
1060 if (i != FAIL)
1061 {
1062 opP->reg = i;
1063 if (*str == ')')
1064 {
1065 /* "(d,An)" Register Indirect w Displacement */
1066 opP->mode = AOFF;
1067 return OK;
1068 }
1069 if (*str == ',')
1070 {
1071 str++;
1072 i = try_moto_index (&str, opP);
1073 if (i == FAIL)
1074 return FAIL;
1075 /* "(d,An,Rn)" Register Indirect with Index */
1076 opP->mode = AINDX;
1077 return OK;
1078 }
1079 else
1080 {
1081 opP->error = "Bad indirect syntax";
1082 return FAIL;
1083 }
1084 }
1085 else
1086 {
1087 opP->error = "Invalid register";
1088 return FAIL;
1089 }
1090 }
1091 else
1092 {
1093 opP->mode = ABSL;
1094 opP->con1 = add_exp (str - 1, strend);
1095 return OK;
1096 }
1097 }
1098 }
1099
1100 if (*str == '-')
1101 {
1102 if (str[1] == '(')
1103 {
1104 str = str + 2;
1105 i = m68k_reg_parse (&str);
1106 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL)
1107 {
1108 /* Can't indirect off non address regs */
1109 opP->error = "Invalid indirect register";
1110 return FAIL;
1111 }
1112 if (i != FAIL)
1113 {
1114 opP->reg = i;
1115 if (*str == ')')
1116 {
1117 str++;
1118 if (*str == '\0')
1119 {
1120 /* "-(An)" Register Indirect with Predecrement */
1121 opP->mode = ADEC;
1122 return OK;
1123 }
1124 opP->error = "Junk after indirect";
1125 return FAIL;
1126 }
1127 opP->error = "Bad indirect syntax";
1128 return FAIL;
1129 }
1130 opP->mode = ABSL;
1131 opP->con1 = add_exp (str - 2, strend);
1132 return OK;
1133 }
1134 /* if '-' but not "-(', do nothing */
1135 }
1136
1137 /* whether *str=='-' or not */
1138 {
1139 /* "EXP2" or "EXP2(REG..." */
1140 char *stmp;
1141 if ((stmp = strchr (str, '(')) != NULL)
1142 {
1143 char *ostr = str;
1144
1145 opP->con1 = add_exp (str, stmp - 1);
1146 str = stmp + 1;
1147 i = m68k_reg_parse (&str);
1148 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC
1149 && i != ZPC && i != FAIL)
1150 {
1151 /* Can't indirect off non address regs */
1152 opP->error = "Invalid indirect register";
1153 return FAIL;
1154 }
1155 if (i != FAIL)
1156 {
1157 opP->reg = i;
1158 if (*str == ')')
1159 {
1160 /* "d(An)" Register Indirect w Displacement */
1161 opP->mode = AOFF;
1162 return OK;
1163 }
1164 if (*str == ',')
1165 {
1166 str++;
1167 i = try_moto_index (&str, opP);
1168 if (i == FAIL)
1169 return FAIL;
1170 /* "d(An,Rn)" Register Indirect with Index */
1171 opP->mode = AINDX;
1172 return OK;
1173 }
1174 else
1175 {
1176 opP->error = "Bad indirect syntax";
1177 return FAIL;
1178 }
1179 }
1180 else
1181 {
1182 opP->mode = ABSL;
1183 opP->con1 = add_exp (ostr, strend);
1184 return OK;
1185 }
1186 }
1187 else
1188 {
1189 /* "EXP2" Absolute */
1190 opP->mode = ABSL;
1191 opP->isiz = 0;
1192 if (strend[-1] == '.' || strend[-1] == ':')
1193 {
1194 /* mode ==foo.[wl] */
1195 switch (*strend)
1196 {
1197 case 'w':
1198 case 'W':
1199 opP->isiz = 2;
1200 break;
1201 case 'l':
1202 case 'L':
1203 opP->isiz = 3;
1204 break;
1205 }
1206 }
1207 opP->con1 = add_exp (str, strend);
1208 return OK;
1209 }
1210 }
1211 /*NOTREACHED*/
1212 #else /* defined (MIT_SYNTAX_ONLY) */
1213 opP->mode = ABSL;
1214 opP->con1 = add_exp (str, strend);
1215 return OK;
1216 #endif /* defined (MIT_SYNTAX_ONLY) */
1217 }
1218
1219 opP->reg = i;
1220
1221 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1222 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL
1223 && (str[1] != '\0' || i < DATA + 0 || i > DATA + 7))
1224 {
1225 opP->error = "Invalid indirect register";
1226 return FAIL;
1227 }
1228 know (*str == '@');
1229
1230 str++;
1231 switch (*str)
1232 {
1233 case '\0':
1234 if (i < DATA + 0 || i > DATA + 7)
1235 opP->mode = AINDR;
1236 else
1237 opP->mode = DINDR;
1238 return OK;
1239 case '-':
1240 opP->mode = ADEC;
1241 return OK;
1242 case '+':
1243 opP->mode = AINC;
1244 return OK;
1245 case '(':
1246 str++;
1247 break;
1248 default:
1249 opP->error = "Junk after indirect";
1250 return FAIL;
1251 }
1252 /* Some kind of indexing involved. Lets find out how bad it is */
1253 i = try_index (&str, opP);
1254 /* Didn't start with an index reg, maybe its offset or offset,reg */
1255 if (i == FAIL)
1256 {
1257 char *beg_str;
1258
1259 beg_str = str;
1260 for (i = 1; i;)
1261 {
1262 switch (*str++)
1263 {
1264 case '\0':
1265 opP->error = "Missing )";
1266 return FAIL;
1267 case ',':
1268 i = 0;
1269 break;
1270 case '(':
1271 i++;
1272 break;
1273 case ')':
1274 --i;
1275 break;
1276 }
1277 }
1278 #if 0
1279 if (str[-3]==':')
1280 {
1281 int siz;
1282
1283 switch (str[-2])
1284 {
1285 case 'b':
1286 case 'B':
1287 siz=1;
1288 break;
1289 case 'w':
1290 case 'W':
1291 siz=2;
1292 break;
1293 case 'l':
1294 case 'L':
1295 siz=3;
1296 break;
1297 default:
1298 opP->error="Specified size isn't :w or :l";
1299 return FAIL;
1300 }
1301 opP->con1=add_exp(beg_str,str-4);
1302 opP->con1->e_siz=siz;
1303 }
1304 else
1305 #endif
1306 opP->con1 = add_exp (beg_str, str - 2);
1307 /* Should be offset,reg */
1308 if (str[-1] == ',')
1309 {
1310 i = try_index (&str, opP);
1311 if (i == FAIL)
1312 {
1313 opP->error = "Malformed index reg";
1314 return FAIL;
1315 }
1316 }
1317 }
1318 /* We've now got offset) offset,reg) or reg) */
1319
1320 if (*str == '\0')
1321 {
1322 /* Th-the-thats all folks */
1323 if (opP->reg == FAIL)
1324 opP->mode = AINDX; /* Other form of indirect */
1325 else if (opP->ireg == FAIL)
1326 opP->mode = AOFF;
1327 else
1328 opP->mode = AINDX;
1329 return (OK);
1330 }
1331 /* Next thing had better be another @ */
1332 if (*str == '@')
1333 {
1334 if (str[1] == '(')
1335 {
1336 needp = 1;
1337 str += 2;
1338 }
1339 else
1340 {
1341 needp = 0;
1342 str++;
1343 }
1344 }
1345
1346 if ((current_architecture & m68020up) == 0)
1347 {
1348 return (FAIL);
1349 } /* if target is not a '20 or better */
1350
1351
1352 if (opP->ireg != FAIL)
1353 {
1354 opP->mode = APRDX;
1355
1356 i = try_index (&str, opP);
1357 if (i != FAIL)
1358 {
1359 opP->error = "Two index registers! not allowed!";
1360 return (FAIL);
1361 }
1362 }
1363 else
1364 {
1365 i = try_index (&str, opP);
1366 }
1367
1368 if (i == FAIL)
1369 {
1370 char *beg_str;
1371
1372 beg_str = str;
1373
1374 for (i = 1; i;)
1375 {
1376 switch (*str++)
1377 {
1378 case '\0':
1379 if (needp)
1380 opP->error = "Missing )";
1381 return (FAIL);
1382 break;
1383 case ',':
1384 i = 0;
1385 break;
1386 case '(':
1387 i++;
1388 break;
1389 case ')':
1390 --i;
1391 break;
1392 }
1393 }
1394
1395 opP->con2 = add_exp (beg_str, str - 2);
1396
1397 if (str[-1] == ',')
1398 {
1399 if (opP->ireg != FAIL)
1400 {
1401 opP->error = "Can't have two index regs";
1402 return (FAIL);
1403 }
1404
1405 i = try_index (&str, opP);
1406
1407 if (i == FAIL)
1408 {
1409 opP->error = "malformed index reg";
1410 return (FAIL);
1411 }
1412
1413 opP->mode = APODX;
1414 }
1415 else if (opP->ireg != FAIL)
1416 {
1417 opP->mode = APRDX;
1418 }
1419 else
1420 {
1421 opP->mode = AMIND;
1422 }
1423 }
1424 else
1425 {
1426 opP->mode = APODX;
1427 }
1428
1429 if (*str != '\0')
1430 {
1431 opP->error = "Junk after indirect";
1432 return FAIL;
1433 }
1434 return (OK);
1435 } /* m68k_ip_op() */
1436
1437
1438 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
1439
1440 #ifdef NO_PCREL_RELOCS
1441
1442 int
1443 make_pcrel_absolute(fixP, add_number)
1444 fixS *fixP;
1445 long *add_number;
1446 {
1447 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
1448
1449 /* rewrite the PC relative instructions to absolute address ones.
1450 * these are rumoured to be faster, and the apollo linker refuses
1451 * to deal with the PC relative relocations.
1452 */
1453 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
1454 {
1455 opcode[0] = 0x4e;
1456 opcode[1] = 0xf9;
1457 }
1458 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
1459 {
1460 opcode[0] = 0x4e;
1461 opcode[1] = 0xb9;
1462 }
1463 else
1464 as_fatal ("Unknown PC relative instruction");
1465 *add_number -= 4;
1466 return 0;
1467 }
1468
1469 #endif /* NO_PCREL_RELOCS */
1470
1471 short
1472 tc_coff_fix2rtype (fixP)
1473 fixS *fixP;
1474 {
1475 #ifdef NO_PCREL_RELOCS
1476 know (fixP->fx_pcrel == 0);
1477 return (fixP->fx_size == 1 ? R_RELBYTE
1478 : fixP->fx_size == 2 ? R_DIR16
1479 : R_DIR32);
1480 #else
1481 return (fixP->fx_pcrel ?
1482 (fixP->fx_size == 1 ? R_PCRBYTE :
1483 fixP->fx_size == 2 ? R_PCRWORD :
1484 R_PCRLONG) :
1485 (fixP->fx_size == 1 ? R_RELBYTE :
1486 fixP->fx_size == 2 ? R_RELWORD :
1487 R_RELLONG));
1488 #endif
1489 }
1490
1491 #endif
1492
1493 #ifdef BFD_ASSEMBLER
1494
1495 arelent *
1496 tc_gen_reloc (section, fixp)
1497 asection *section;
1498 fixS *fixp;
1499 {
1500 arelent *reloc;
1501 bfd_reloc_code_real_type code;
1502
1503 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1504 switch (F (fixp->fx_size, fixp->fx_pcrel))
1505 {
1506 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1507 MAP (1, 0, BFD_RELOC_8);
1508 MAP (2, 0, BFD_RELOC_16);
1509 MAP (4, 0, BFD_RELOC_32);
1510 MAP (1, 1, BFD_RELOC_8_PCREL);
1511 MAP (2, 1, BFD_RELOC_16_PCREL);
1512 MAP (4, 1, BFD_RELOC_32_PCREL);
1513 default:
1514 abort ();
1515 }
1516
1517 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
1518 assert (reloc != 0);
1519 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
1520 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1521 if (fixp->fx_pcrel)
1522 reloc->addend = fixp->fx_addnumber;
1523 else
1524 reloc->addend = 0;
1525
1526 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1527 assert (reloc->howto != 0);
1528
1529 return reloc;
1530 }
1531
1532 #endif /* BFD_ASSEMBLER */
1533
1534 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1535 main ()
1536 {
1537 char buf[128];
1538 struct m68k_op thark;
1539
1540 for (;;)
1541 {
1542 if (!gets (buf))
1543 break;
1544 memset (&thark, '\0', sizeof (thark));
1545 if (!m68k_ip_op (buf, &thark))
1546 printf ("FAIL:");
1547 if (thark.error)
1548 printf ("op1 error %s in %s\n", thark.error, buf);
1549 printf ("mode %d, reg %d, ", thark.mode, thark.reg);
1550 if (thark.b_const)
1551 printf ("Constant: '%.*s',", 1 + thark.e_const - thark.b_const, thark.b_const);
1552 printf ("ireg %d, isiz %d, imul %d ", thark.ireg, thark.isiz, thark.imul);
1553 if (thark.b_iadd)
1554 printf ("Iadd: '%.*s'", 1 + thark.e_iadd - thark.b_iadd, thark.b_iadd);
1555 printf ("\n");
1556 }
1557 exit (0);
1558 }
1559
1560 #endif
1561
1562
1563 /* Handle of the OPCODE hash table. NULL means any use before
1564 m68k_ip_begin() will crash. */
1565 static struct hash_control *op_hash;
1566 \f
1567
1568 /*
1569 * m 6 8 k _ i p ( )
1570 *
1571 * This converts a string into a 68k instruction.
1572 * The string must be a bare single instruction in sun format
1573 * with RMS-style 68020 indirects
1574 * (example: )
1575 *
1576 * It provides some error messages: at most one fatal error message (which
1577 * stops the scan) and at most one warning message for each operand.
1578 * The 68k instruction is returned in exploded form, since we have no
1579 * knowledge of how you parse (or evaluate) your expressions.
1580 * We do however strip off and decode addressing modes and operation
1581 * mnemonic.
1582 *
1583 * This function's value is a string. If it is not "" then an internal
1584 * logic error was found: read this code to assign meaning to the string.
1585 * No argument string should generate such an error string:
1586 * it means a bug in our code, not in the user's text.
1587 *
1588 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1589 * this function.
1590 */
1591
1592 /* JF this function no longer returns a useful value. Sorry */
1593 void
1594 m68k_ip (instring)
1595 char *instring;
1596 {
1597 register char *p;
1598 register struct m68k_op *opP;
1599 register struct m68k_incant *opcode;
1600 register char *s;
1601 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1602 char *pdot, *pdotmove;
1603 int siz1, siz2;
1604 char c;
1605 int losing;
1606 int opsfound;
1607 char *crack_operand ();
1608 LITTLENUM_TYPE words[6];
1609 LITTLENUM_TYPE *wordp;
1610 unsigned long ok_arch = 0;
1611
1612 if (*instring == ' ')
1613 instring++; /* skip leading whitespace */
1614
1615 /* Scan up to end of operation-code, which MUST end in end-of-string
1616 or exactly 1 space. */
1617 pdot = 0;
1618 for (p = instring; *p != '\0'; p++)
1619 {
1620 if (*p == ' ')
1621 break;
1622 if (*p == '.')
1623 pdot = p;
1624 }
1625
1626 if (p == instring)
1627 {
1628 the_ins.error = "No operator";
1629 the_ins.opcode[0] = 0;
1630 /* the_ins.numo=1; */
1631 return;
1632 }
1633
1634 /* p now points to the end of the opcode name, probably whitespace.
1635 make sure the name is null terminated by clobbering the whitespace,
1636 look it up in the hash table, then fix it back.
1637 Remove a dot, first, since the opcode tables have none. */
1638 if (pdot != NULL)
1639 {
1640 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1641 *pdotmove = pdotmove[1];
1642 p--;
1643 }
1644
1645 c = *p;
1646 *p = '\0';
1647 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
1648 *p = c;
1649
1650 if (pdot != NULL)
1651 {
1652 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1653 *pdotmove = pdotmove[-1];
1654 *pdot = '.';
1655 ++p;
1656 }
1657
1658 if (opcode == NULL)
1659 {
1660 the_ins.error = "Unknown operator";
1661 the_ins.opcode[0] = 0;
1662 /* the_ins.numo=1; */
1663 return;
1664 }
1665
1666 /* found a legitimate opcode, start matching operands */
1667 while (*p == ' ')
1668 ++p;
1669
1670
1671 if (opcode->m_operands == 0)
1672 {
1673 char *old = input_line_pointer;
1674 *old = '\n';
1675 input_line_pointer = p;
1676 /* Ahh - it's a motorola style psuedo op */
1677 mote_pseudo_table[opcode->m_opnum].poc_handler
1678 (mote_pseudo_table[opcode->m_opnum].poc_val);
1679 input_line_pointer = old;
1680 *old = 0;
1681
1682 return;
1683 }
1684
1685 for (opP = &the_ins.operands[0]; *p; opP++)
1686 {
1687
1688 p = crack_operand (p, opP);
1689
1690 if (opP->error)
1691 {
1692 the_ins.error = opP->error;
1693 return;
1694 }
1695 }
1696
1697 opsfound = opP - &the_ins.operands[0];
1698
1699 /* This ugly hack is to support the floating pt opcodes in their standard form */
1700 /* Essentially, we fake a first enty of type COP#1 */
1701 if (opcode->m_operands[0] == 'I')
1702 {
1703 int n;
1704
1705 for (n = opsfound; n > 0; --n)
1706 the_ins.operands[n] = the_ins.operands[n - 1];
1707
1708 memset ((char *) (&the_ins.operands[0]), '\0', sizeof (the_ins.operands[0]));
1709 the_ins.operands[0].mode = MSCR;
1710 the_ins.operands[0].reg = COPNUM; /* COP #1 */
1711 opsfound++;
1712 }
1713
1714 /* We've got the operands. Find an opcode that'll accept them */
1715 for (losing = 0;;)
1716 {
1717 /* If we didn't get the right number of ops, or we have no
1718 common model with this pattern then reject this pattern. */
1719
1720 if (opsfound != opcode->m_opnum
1721 || ((opcode->m_arch & current_architecture) == 0))
1722 {
1723 ++losing;
1724 ok_arch |= opcode->m_arch;
1725 }
1726 else
1727 {
1728 for (s = opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++)
1729 {
1730 /* Warning: this switch is huge! */
1731 /* I've tried to organize the cases into this order:
1732 non-alpha first, then alpha by letter. Lower-case
1733 goes directly before uppercase counterpart. */
1734 /* Code with multiple case ...: gets sorted by the lowest
1735 case ... it belongs to. I hope this makes sense. */
1736 switch (*s)
1737 {
1738 case '!':
1739 if (opP->mode == MSCR || opP->mode == IMMED
1740 || opP->mode == DREG || opP->mode == AREG
1741 || opP->mode == AINC || opP->mode == ADEC
1742 || opP->mode == REGLST)
1743 losing++;
1744 break;
1745
1746 case '`':
1747 switch (opP->mode)
1748 {
1749 case MSCR:
1750 case IMMED:
1751 case DREG:
1752 case AREG:
1753 case AINC:
1754 case REGLST:
1755 case AINDR:
1756 losing++;
1757 break;
1758 default:
1759 break;
1760 }
1761 break;
1762
1763 case '#':
1764 if (opP->mode != IMMED)
1765 losing++;
1766 else
1767 {
1768 long t;
1769
1770 t = get_num (opP->con1, 80);
1771 if (s[1] == 'b' && !isbyte (t))
1772 losing++;
1773 else if (s[1] == 'w' && !isword (t))
1774 losing++;
1775 }
1776 break;
1777
1778 case '^':
1779 case 'T':
1780 if (opP->mode != IMMED)
1781 losing++;
1782 break;
1783
1784 case '$':
1785 if (opP->mode == MSCR || opP->mode == AREG ||
1786 opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1787 losing++;
1788 break;
1789
1790 case '%':
1791 if (opP->mode == MSCR || opP->reg == PC ||
1792 opP->reg == ZPC || opP->mode == REGLST)
1793 losing++;
1794 break;
1795
1796
1797 case '&':
1798 if (opP->mode == MSCR || opP->mode == DREG ||
1799 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC ||
1800 opP->mode == AINC || opP->mode == ADEC || opP->mode == REGLST)
1801 losing++;
1802 break;
1803
1804 case '*':
1805 if (opP->mode == MSCR || opP->mode == REGLST)
1806 losing++;
1807 break;
1808
1809 case '+':
1810 if (opP->mode != AINC)
1811 losing++;
1812 break;
1813
1814 case '-':
1815 if (opP->mode != ADEC)
1816 losing++;
1817 break;
1818
1819 case '/':
1820 if (opP->mode == MSCR || opP->mode == AREG ||
1821 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->mode == REGLST)
1822 losing++;
1823 break;
1824
1825 case ';':
1826 if (opP->mode == MSCR || opP->mode == AREG || opP->mode == REGLST)
1827 losing++;
1828 break;
1829
1830 case '?':
1831 if (opP->mode == MSCR || opP->mode == AREG ||
1832 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->reg == PC ||
1833 opP->reg == ZPC || opP->mode == REGLST)
1834 losing++;
1835 break;
1836
1837 case '@':
1838 if (opP->mode == MSCR || opP->mode == AREG ||
1839 opP->mode == IMMED || opP->mode == REGLST)
1840 losing++;
1841 break;
1842
1843 case '~': /* For now! (JF FOO is this right?) */
1844 if (opP->mode == MSCR || opP->mode == DREG ||
1845 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1846 losing++;
1847 break;
1848
1849 case '3':
1850 if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1))
1851 losing++;
1852 break;
1853
1854 case 'A':
1855 if (opP->mode != AREG)
1856 losing++;
1857 break;
1858 case 'a':
1859 if (opP->mode != AINDR)
1860 {
1861 ++losing;
1862 } /* if not address register indirect */
1863 break;
1864 case 'B': /* FOO */
1865 if (opP->mode != ABSL || (flagseen['S'] && instring[0] == 'j'
1866 && instring[1] == 'b'
1867 && instring[2] == 's'
1868 && instring[3] == 'r'))
1869 losing++;
1870 break;
1871
1872 case 'C':
1873 if (opP->mode != MSCR || opP->reg != CCR)
1874 losing++;
1875 break;
1876
1877 case 'd': /* FOO This mode is a KLUDGE!! */
1878 if (opP->mode != AOFF && (opP->mode != ABSL ||
1879 opP->con1->e_beg[0] != '(' || opP->con1->e_end[0] != ')'))
1880 losing++;
1881 break;
1882
1883 case 'D':
1884 if (opP->mode != DREG)
1885 losing++;
1886 break;
1887
1888 case 'F':
1889 if (opP->mode != MSCR || opP->reg < (FPREG + 0) || opP->reg > (FPREG + 7))
1890 losing++;
1891 break;
1892
1893 case 'I':
1894 if (opP->mode != MSCR || opP->reg < COPNUM ||
1895 opP->reg >= COPNUM + 7)
1896 losing++;
1897 break;
1898
1899 case 'J':
1900 if (opP->mode != MSCR
1901 || opP->reg < USP
1902 || opP->reg > last_movec_reg)
1903 losing++;
1904 else
1905 {
1906 enum _register *rp;
1907 for (rp = control_regs; *rp; rp++)
1908 if (*rp == opP->reg)
1909 break;
1910 if (*rp == 0)
1911 losing++;
1912 }
1913 break;
1914
1915 case 'k':
1916 if (opP->mode != IMMED)
1917 losing++;
1918 break;
1919
1920 case 'l':
1921 case 'L':
1922 if (opP->mode == DREG || opP->mode == AREG || opP->mode == FPREG)
1923 {
1924 if (s[1] == '8')
1925 losing++;
1926 else
1927 {
1928 opP->mode = REGLST;
1929 opP->reg = 1 << (opP->reg - DATA);
1930 }
1931 }
1932 else if (opP->mode != REGLST)
1933 {
1934 losing++;
1935 }
1936 else if (s[1] == '8' && opP->reg & 0x0FFffFF)
1937 losing++;
1938 else if (s[1] == '3' && opP->reg & 0x7000000)
1939 losing++;
1940 break;
1941
1942 case 'M':
1943 if (opP->mode != IMMED)
1944 losing++;
1945 else
1946 {
1947 long t;
1948
1949 t = get_num (opP->con1, 0);
1950 if (!issbyte (t)
1951 || isvar (opP->con1))
1952 losing++;
1953 }
1954 break;
1955
1956 case 'O':
1957 if (opP->mode != DREG && opP->mode != IMMED)
1958 losing++;
1959 break;
1960
1961 case 'Q':
1962 if (opP->mode != IMMED)
1963 losing++;
1964 else
1965 {
1966 long t;
1967
1968 t = get_num (opP->con1, 80);
1969 if (t < 1 || t > 8 || isvar (opP->con1))
1970 losing++;
1971 }
1972 break;
1973
1974 case 'R':
1975 if (opP->mode != DREG && opP->mode != AREG)
1976 losing++;
1977 break;
1978
1979 case 'r':
1980 if (opP->mode != AINDR && opP->mode != DINDR)
1981 losing++;
1982 break;
1983
1984 case 's':
1985 if (opP->mode != MSCR || !(opP->reg == FPI || opP->reg == FPS || opP->reg == FPC))
1986 losing++;
1987 break;
1988
1989 case 'S':
1990 if (opP->mode != MSCR || opP->reg != SR)
1991 losing++;
1992 break;
1993
1994 case 't':
1995 if (opP->mode != IMMED)
1996 losing++;
1997 else
1998 {
1999 long t = get_num (opP->con1, 80);
2000 if (t < 0 || t > 7 || isvar (opP->con1))
2001 losing++;
2002 }
2003 break;
2004
2005 case 'U':
2006 if (opP->mode != MSCR || opP->reg != USP)
2007 losing++;
2008 break;
2009
2010 /* JF these are out of order. We could put them
2011 in order if we were willing to put up with
2012 bunches of #ifdef m68851s in the code.
2013
2014 Don't forget that you need these operands
2015 to use 68030 MMU instructions. */
2016 #ifndef NO_68851
2017 /* Memory addressing mode used by pflushr */
2018 case '|':
2019 if (opP->mode == MSCR || opP->mode == DREG ||
2020 opP->mode == AREG || opP->mode == REGLST)
2021 losing++;
2022 break;
2023
2024 case 'f':
2025 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
2026 losing++;
2027 break;
2028
2029 case 'P':
2030 if (opP->mode != MSCR
2031 || (opP->reg != TC && opP->reg != CAL
2032 && opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
2033 losing++;
2034 break;
2035
2036 case 'V':
2037 if (opP->reg != VAL)
2038 losing++;
2039 break;
2040
2041 case 'W':
2042 if (opP->mode != MSCR
2043 || (opP->reg != DRP && opP->reg != SRP
2044 && opP->reg != CRP))
2045 losing++;
2046 break;
2047
2048 case 'X':
2049 if (opP->mode != MSCR ||
2050 (!(opP->reg >= BAD && opP->reg <= BAD + 7) &&
2051 !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2052 losing++;
2053 break;
2054
2055 case 'Y':
2056 if (opP->reg != PSR)
2057 losing++;
2058 break;
2059
2060 case 'Z':
2061 if (opP->reg != PCSR)
2062 losing++;
2063 break;
2064 #endif
2065 case 'c':
2066 if (opP->reg != NC
2067 && opP->reg != IC
2068 && opP->reg != DC
2069 && opP->reg != BC)
2070 {
2071 losing++;
2072 } /* not a cache specifier. */
2073 break;
2074
2075 case '_':
2076 if (opP->mode != ABSL)
2077 {
2078 ++losing;
2079 } /* not absolute */
2080 break;
2081
2082 default:
2083 as_fatal ("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
2084 *s, __LINE__, __FILE__);
2085 } /* switch on type of operand */
2086
2087 if (losing)
2088 break;
2089 } /* for each operand */
2090 } /* if immediately wrong */
2091
2092 if (!losing)
2093 {
2094 break;
2095 } /* got it. */
2096
2097 opcode = opcode->m_next;
2098
2099 if (!opcode)
2100 {
2101 if (ok_arch
2102 && !(ok_arch & current_architecture))
2103 {
2104 char buf[200], *cp;
2105 int len;
2106 strcpy (buf, "invalid instruction for this architecture; needs ");
2107 cp = buf + strlen (buf);
2108 switch (ok_arch)
2109 {
2110 case mfloat:
2111 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
2112 break;
2113 case mmmu:
2114 strcpy (cp, "mmu (68030 or 68851)");
2115 break;
2116 case m68020up:
2117 strcpy (cp, "68020 or higher");
2118 break;
2119 case m68000up:
2120 strcpy (cp, "68000 or higher");
2121 break;
2122 case m68010up:
2123 strcpy (cp, "68010 or higher");
2124 break;
2125 default:
2126 {
2127 int got_one = 0, idx;
2128 static const struct
2129 {
2130 int arch;
2131 const char *name;
2132 }
2133 archs[] =
2134 {
2135 { m68000, "68000" },
2136 { m68010, "68010" },
2137 { m68020, "68020" },
2138 { m68030, "68030" },
2139 { m68040, "68040" },
2140 { m68060, "68060" },
2141 { cpu32, "cpu32" },
2142 { m68881, "68881" },
2143 { m68851, "68851" }
2144 };
2145 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]); idx++)
2146 {
2147 if (archs[idx].arch & ok_arch)
2148 {
2149 if (got_one)
2150 {
2151 strcpy (cp, " or ");
2152 cp += strlen (cp);
2153 }
2154 got_one = 1;
2155 strcpy (cp, archs[idx].name);
2156 cp += strlen (cp);
2157 }
2158 }
2159 }
2160 }
2161 len = cp - buf + 1;
2162 cp = malloc (len);
2163 strcpy (cp, buf);
2164 the_ins.error = cp;
2165 }
2166 else
2167 the_ins.error = "operands mismatch";
2168 return;
2169 } /* Fell off the end */
2170
2171 losing = 0;
2172 }
2173
2174 /* now assemble it */
2175
2176 the_ins.args = opcode->m_operands;
2177 the_ins.numargs = opcode->m_opnum;
2178 the_ins.numo = opcode->m_codenum;
2179 the_ins.opcode[0] = getone (opcode);
2180 the_ins.opcode[1] = gettwo (opcode);
2181
2182 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2183 {
2184 /* This switch is a doozy.
2185 Watch the first step; its a big one! */
2186 switch (s[0])
2187 {
2188
2189 case '*':
2190 case '~':
2191 case '%':
2192 case ';':
2193 case '@':
2194 case '!':
2195 case '&':
2196 case '$':
2197 case '?':
2198 case '/':
2199 case '`':
2200 #ifndef NO_68851
2201 case '|':
2202 #endif
2203 switch (opP->mode)
2204 {
2205 case IMMED:
2206 tmpreg = 0x3c; /* 7.4 */
2207 if (strchr ("bwl", s[1]))
2208 nextword = get_num (opP->con1, 80);
2209 else
2210 nextword = get_num (opP->con1, 0);
2211 if (isvar (opP->con1))
2212 add_fix (s[1], opP->con1, 0);
2213 switch (s[1])
2214 {
2215 case 'b':
2216 if (!isbyte (nextword))
2217 opP->error = "operand out of range";
2218 addword (nextword);
2219 baseo = 0;
2220 break;
2221 case 'w':
2222 if (!isword (nextword))
2223 opP->error = "operand out of range";
2224 addword (nextword);
2225 baseo = 0;
2226 break;
2227 case 'l':
2228 addword (nextword >> 16);
2229 addword (nextword);
2230 baseo = 0;
2231 break;
2232
2233 case 'f':
2234 baseo = 2;
2235 outro = 8;
2236 break;
2237 case 'F':
2238 baseo = 4;
2239 outro = 11;
2240 break;
2241 case 'x':
2242 baseo = 6;
2243 outro = 15;
2244 break;
2245 case 'p':
2246 baseo = 6;
2247 outro = -1;
2248 break;
2249 default:
2250 as_fatal ("Internal error: Can't decode %c%c in line %d of file \"%s\"",
2251 *s, s[1], __LINE__, __FILE__);
2252 }
2253 if (!baseo)
2254 break;
2255
2256 /* We gotta put out some float */
2257 if (op (opP->con1) != O_big)
2258 {
2259 valueT val;
2260 int gencnt;
2261
2262 /* Can other cases happen here? */
2263 if (op (opP->con1) != O_constant)
2264 abort ();
2265
2266 val = (valueT) offs (opP->con1);
2267 gencnt = 0;
2268 do
2269 {
2270 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2271 val >>= LITTLENUM_NUMBER_OF_BITS;
2272 ++gencnt;
2273 }
2274 while (val != 0);
2275 offs (opP->con1) = gencnt;
2276 }
2277 if (offs (opP->con1) > 0)
2278 {
2279 if (offs (opP->con1) > baseo)
2280 {
2281 as_warn ("Bignum too big for %c format; truncated", s[1]);
2282 offs (opP->con1) = baseo;
2283 }
2284 baseo -= offs (opP->con1);
2285 while (baseo--)
2286 addword (0);
2287 for (wordp = generic_bignum + offs (opP->con1) - 1; offs (opP->con1)--; --wordp)
2288 addword (*wordp);
2289 break;
2290 }
2291 gen_to_words (words, baseo, (long) outro);
2292 for (wordp = words; baseo--; wordp++)
2293 addword (*wordp);
2294 break;
2295 case DREG:
2296 tmpreg = opP->reg - DATA; /* 0.dreg */
2297 break;
2298 case AREG:
2299 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2300 break;
2301 case AINDR:
2302 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2303 break;
2304 case ADEC:
2305 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2306 break;
2307 case AINC:
2308 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2309 break;
2310 case AOFF:
2311
2312 nextword = get_num (opP->con1, 80);
2313 /* Force into index mode. Hope this works */
2314
2315 /* We do the first bit for 32-bit displacements, and the
2316 second bit for 16 bit ones. It is possible that we
2317 should make the default be WORD instead of LONG, but
2318 I think that'd break GCC, so we put up with a little
2319 inefficiency for the sake of working output. */
2320
2321 if (!issword (nextword)
2322 || (isvar (opP->con1)
2323 && ((opP->con1->e_siz == 0
2324 && flagseen['l'] == 0)
2325 || opP->con1->e_siz == 3)))
2326 {
2327
2328 if (opP->reg == PC)
2329 tmpreg = 0x3B; /* 7.3 */
2330 else
2331 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2332 if (isvar (opP->con1))
2333 {
2334 if (opP->reg == PC)
2335 {
2336 addword (0x0170);
2337 opP->con1->e_exp.X_add_number += 6;
2338 add_fix ('l', opP->con1, 1);
2339 addword (0), addword (0);
2340 break;
2341 }
2342 else
2343 {
2344 addword (0x0170);
2345 add_fix ('l', opP->con1, 0);
2346 }
2347 }
2348 else
2349 addword (0x0170);
2350 addword (nextword >> 16);
2351 }
2352 else
2353 {
2354 if (opP->reg == PC)
2355 tmpreg = 0x3A; /* 7.2 */
2356 else
2357 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2358
2359 if (isvar (opP->con1))
2360 {
2361 if (opP->reg == PC)
2362 {
2363 opP->con1->e_exp.X_add_number += 2;
2364 add_fix ('w', opP->con1, 1);
2365 }
2366 else
2367 add_fix ('w', opP->con1, 0);
2368 }
2369 }
2370 addword (nextword);
2371 break;
2372
2373 case APODX:
2374 case AMIND:
2375 case APRDX:
2376 know (current_architecture & m68020up);
2377 /* intentional fall-through */
2378 case AINDX:
2379 nextword = 0;
2380 baseo = get_num (opP->con1, 80);
2381 outro = get_num (opP->con2, 80);
2382 /* Figure out the `addressing mode'.
2383 Also turn on the BASE_DISABLE bit, if needed. */
2384 if (opP->reg == PC || opP->reg == ZPC)
2385 {
2386 tmpreg = 0x3b;/* 7.3 */
2387 if (opP->reg == ZPC)
2388 nextword |= 0x80;
2389 }
2390 else if (opP->reg == FAIL)
2391 {
2392 nextword |= 0x80;
2393 tmpreg = 0x30;/* 6.garbage */
2394 }
2395 else
2396 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2397
2398 siz1 = (opP->con1) ? opP->con1->e_siz : 0;
2399 siz2 = (opP->con2) ? opP->con2->e_siz : 0;
2400
2401 /* Index register stuff */
2402 if (opP->ireg >= DATA + 0 && opP->ireg <= ADDR + 7)
2403 {
2404 nextword |= (opP->ireg - DATA) << 12;
2405
2406 if (opP->isiz == 0 || opP->isiz == 3)
2407 nextword |= 0x800;
2408 switch (opP->imul)
2409 {
2410 case 1:
2411 break;
2412 case 2:
2413 nextword |= 0x200;
2414 break;
2415 case 4:
2416 nextword |= 0x400;
2417 break;
2418 case 8:
2419 nextword |= 0x600;
2420 break;
2421 default:
2422 as_fatal ("failed sanity check.");
2423 }
2424 /* IF its simple,
2425 GET US OUT OF HERE! */
2426
2427 /* Must be INDEX, with an index
2428 register. Address register
2429 cannot be ZERO-PC, and either
2430 :b was forced, or we know
2431 it will fit */
2432 if (opP->mode == AINDX
2433 && opP->reg != FAIL
2434 && opP->reg != ZPC
2435 && (siz1 == 1
2436 || (issbyte (baseo)
2437 && !isvar (opP->con1))))
2438 {
2439 nextword += baseo & 0xff;
2440 addword (nextword);
2441 if (isvar (opP->con1))
2442 add_fix ('B', opP->con1, 0);
2443 break;
2444 }
2445 }
2446 else
2447 nextword |= 0x40; /* No index reg */
2448
2449 /* It isn't simple. */
2450 nextword |= 0x100;
2451 /* If the guy specified a width, we assume that it is
2452 wide enough. Maybe it isn't. If so, we lose. */
2453 switch (siz1)
2454 {
2455 case 0:
2456 if (isvar (opP->con1) || !issword (baseo))
2457 {
2458 siz1 = 3;
2459 nextword |= 0x30;
2460 }
2461 else if (baseo == 0)
2462 nextword |= 0x10;
2463 else
2464 {
2465 nextword |= 0x20;
2466 siz1 = 2;
2467 }
2468 break;
2469 case 1:
2470 as_warn ("Byte dispacement won't work. Defaulting to :w");
2471 case 2:
2472 nextword |= 0x20;
2473 break;
2474 case 3:
2475 nextword |= 0x30;
2476 break;
2477 }
2478
2479 /* Figure out innner displacement stuff */
2480 if (opP->mode != AINDX)
2481 {
2482 switch (siz2)
2483 {
2484 case 0:
2485 if (isvar (opP->con2) || !issword (outro))
2486 {
2487 siz2 = 3;
2488 nextword |= 0x3;
2489 }
2490 else if (outro == 0)
2491 nextword |= 0x1;
2492 else
2493 {
2494 nextword |= 0x2;
2495 siz2 = 2;
2496 }
2497 break;
2498 case 1:
2499 as_warn ("Byte dispacement won't work. Defaulting to :w");
2500 case 2:
2501 nextword |= 0x2;
2502 break;
2503 case 3:
2504 nextword |= 0x3;
2505 break;
2506 }
2507 if (opP->mode == APODX)
2508 nextword |= 0x04;
2509 else if (opP->mode == AMIND)
2510 nextword |= 0x40;
2511 }
2512 addword (nextword);
2513
2514 if (isvar (opP->con1))
2515 {
2516 if (opP->reg == PC || opP->reg == ZPC)
2517 {
2518 opP->con1->e_exp.X_add_number += 6;
2519 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 1);
2520 }
2521 else
2522 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 0);
2523 }
2524 if (siz1 == 3)
2525 addword (baseo >> 16);
2526 if (siz1)
2527 addword (baseo);
2528
2529 if (isvar (opP->con2))
2530 {
2531 if (opP->reg == PC || opP->reg == ZPC)
2532 {
2533 opP->con1->e_exp.X_add_number += 6;
2534 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 1);
2535 }
2536 else
2537 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 0);
2538 }
2539 if (siz2 == 3)
2540 addword (outro >> 16);
2541 if (siz2)
2542 addword (outro);
2543
2544 break;
2545
2546 case ABSL:
2547 nextword = get_num (opP->con1, 80);
2548 switch (opP->con1->e_siz)
2549 {
2550 default:
2551 as_warn ("Unknown size for absolute reference");
2552 case 0:
2553 if (!isvar (opP->con1) && issword (offs (opP->con1)))
2554 {
2555 tmpreg = 0x38; /* 7.0 */
2556 addword (nextword);
2557 break;
2558 }
2559 /* Don't generate pc relative code on 68010 and
2560 68000. */
2561 if (isvar (opP->con1)
2562 && !subs (opP->con1)
2563 && seg (opP->con1) == text_section
2564 && now_seg == text_section
2565 && cpu_of_arch (current_architecture) >= m68020
2566 && !flagseen['S']
2567 && !strchr ("~%&$?", s[0]))
2568 {
2569 tmpreg = 0x3A; /* 7.2 */
2570 add_frag (adds (opP->con1),
2571 offs (opP->con1),
2572 TAB (PCREL, SZ_UNDEF));
2573 break;
2574 }
2575 case 3: /* Fall through into long */
2576 if (isvar (opP->con1))
2577 add_fix ('l', opP->con1, 0);
2578
2579 tmpreg = 0x39;/* 7.1 mode */
2580 addword (nextword >> 16);
2581 addword (nextword);
2582 break;
2583
2584 case 2: /* Word */
2585 if (isvar (opP->con1))
2586 add_fix ('w', opP->con1, 0);
2587
2588 tmpreg = 0x38;/* 7.0 mode */
2589 addword (nextword);
2590 break;
2591 }
2592 break;
2593 case DINDR:
2594 as_bad ("invalid indirect register");
2595 break;
2596 case MSCR:
2597 default:
2598 as_bad ("unknown/incorrect operand");
2599 /* abort(); */
2600 }
2601 install_gen_operand (s[1], tmpreg);
2602 break;
2603
2604 case '#':
2605 case '^':
2606 switch (s[1])
2607 { /* JF: I hate floating point! */
2608 case 'j':
2609 tmpreg = 70;
2610 break;
2611 case '8':
2612 tmpreg = 20;
2613 break;
2614 case 'C':
2615 tmpreg = 50;
2616 break;
2617 case '3':
2618 default:
2619 tmpreg = 80;
2620 break;
2621 }
2622 tmpreg = get_num (opP->con1, tmpreg);
2623 if (isvar (opP->con1))
2624 add_fix (s[1], opP->con1, 0);
2625 switch (s[1])
2626 {
2627 case 'b': /* Danger: These do no check for
2628 certain types of overflow.
2629 user beware! */
2630 if (!isbyte (tmpreg))
2631 opP->error = "out of range";
2632 insop (tmpreg, opcode);
2633 if (isvar (opP->con1))
2634 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2635 break;
2636 case 'w':
2637 if (!isword (tmpreg))
2638 opP->error = "out of range";
2639 insop (tmpreg, opcode);
2640 if (isvar (opP->con1))
2641 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2642 break;
2643 case 'l':
2644 /* Because of the way insop works, we put these two out
2645 backwards. */
2646 insop (tmpreg, opcode);
2647 insop (tmpreg >> 16, opcode);
2648 if (isvar (opP->con1))
2649 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2650 break;
2651 case '3':
2652 tmpreg &= 0xFF;
2653 case '8':
2654 case 'C':
2655 install_operand (s[1], tmpreg);
2656 break;
2657 default:
2658 as_fatal ("Internal error: Unknown mode #%c in line %d of file \"%s\"", s[1], __LINE__, __FILE__);
2659 }
2660 break;
2661
2662 case '+':
2663 case '-':
2664 case 'A':
2665 case 'a':
2666 install_operand (s[1], opP->reg - ADDR);
2667 break;
2668
2669 case 'B':
2670 tmpreg = get_num (opP->con1, 80);
2671 switch (s[1])
2672 {
2673 case 'B':
2674 /* Needs no offsetting */
2675 add_fix ('B', opP->con1, 1);
2676 break;
2677 case 'W':
2678 /* Offset the displacement to be relative to byte disp location */
2679 opP->con1->e_exp.X_add_number += 2;
2680 add_fix ('w', opP->con1, 1);
2681 addword (0);
2682 break;
2683 case 'L':
2684 long_branch:
2685 if (cpu_of_arch (current_architecture) < m68020) /* 68000 or 010 */
2686 as_warn ("Can't use long branches on 68000/68010");
2687 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2688 /* Offset the displacement to be relative to byte disp location */
2689 opP->con1->e_exp.X_add_number += 4;
2690 add_fix ('l', opP->con1, 1);
2691 addword (0);
2692 addword (0);
2693 break;
2694 case 'g':
2695 if (subs (opP->con1)) /* We can't relax it */
2696 goto long_branch;
2697
2698 /* This could either be a symbol, or an
2699 absolute address. No matter, the
2700 frag hacking will finger it out.
2701 Not quite: it can't switch from
2702 BRANCH to BCC68000 for the case
2703 where opnd is absolute (it needs
2704 to use the 68000 hack since no
2705 conditional abs jumps). */
2706 if (((cpu_of_arch (current_architecture) < m68020) || (0 == adds (opP->con1)))
2707 && (the_ins.opcode[0] >= 0x6200)
2708 && (the_ins.opcode[0] <= 0x6f00))
2709 {
2710 add_frag (adds (opP->con1), offs (opP->con1), TAB (BCC68000, SZ_UNDEF));
2711 }
2712 else
2713 {
2714 add_frag (adds (opP->con1), offs (opP->con1), TAB (ABRANCH, SZ_UNDEF));
2715 }
2716 break;
2717 case 'w':
2718 if (isvar (opP->con1))
2719 {
2720 #if 1
2721 /* check for DBcc instruction */
2722 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2723 {
2724 /* size varies if patch */
2725 /* needed for long form */
2726 add_frag (adds (opP->con1), offs (opP->con1), TAB (DBCC, SZ_UNDEF));
2727 break;
2728 }
2729 #endif
2730 /* Don't ask! */
2731 opP->con1->e_exp.X_add_number += 2;
2732 add_fix ('w', opP->con1, 1);
2733 }
2734 addword (0);
2735 break;
2736 case 'C': /* Fixed size LONG coproc branches */
2737 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2738 /* Offset the displacement to be relative to byte disp location */
2739 /* Coproc branches don't have a byte disp option, but they are
2740 compatible with the ordinary branches, which do... */
2741 opP->con1->e_exp.X_add_number += 4;
2742 add_fix ('l', opP->con1, 1);
2743 addword (0);
2744 addword (0);
2745 break;
2746 case 'c': /* Var size Coprocesssor branches */
2747 if (subs (opP->con1))
2748 {
2749 add_fix ('l', opP->con1, 1);
2750 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2751 }
2752 else if (adds (opP->con1))
2753 {
2754 add_frag (adds (opP->con1), offs (opP->con1), TAB (FBRANCH, SZ_UNDEF));
2755 }
2756 else
2757 {
2758 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2759 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2760 add_fix ('l', opP->con1, 1);
2761 addword (0);
2762 addword (4);
2763 }
2764 break;
2765 default:
2766 as_fatal ("Internal error: operand type B%c unknown in line %d of file \"%s\"",
2767 s[1], __LINE__, __FILE__);
2768 }
2769 break;
2770
2771 case 'C': /* Ignore it */
2772 break;
2773
2774 case 'd': /* JF this is a kludge */
2775 if (opP->mode == AOFF)
2776 {
2777 install_operand ('s', opP->reg - ADDR);
2778 }
2779 else
2780 {
2781 char *tmpP;
2782
2783 tmpP = opP->con1->e_end - 2;
2784 opP->con1->e_beg++;
2785 opP->con1->e_end -= 4; /* point to the , */
2786 baseo = m68k_reg_parse (&tmpP);
2787 if (baseo < ADDR + 0 || baseo > ADDR + 7)
2788 {
2789 as_bad ("Unknown address reg, using A0");
2790 baseo = 0;
2791 }
2792 else
2793 baseo -= ADDR;
2794 install_operand ('s', baseo);
2795 }
2796 tmpreg = get_num (opP->con1, 80);
2797 if (!issword (tmpreg))
2798 {
2799 as_warn ("Expression out of range, using 0");
2800 tmpreg = 0;
2801 }
2802 addword (tmpreg);
2803 break;
2804
2805 case 'D':
2806 install_operand (s[1], opP->reg - DATA);
2807 break;
2808
2809 case 'F':
2810 install_operand (s[1], opP->reg - FPREG);
2811 break;
2812
2813 case 'I':
2814 tmpreg = 1 + opP->reg - COPNUM;
2815 if (tmpreg == 8)
2816 tmpreg = 0;
2817 install_operand (s[1], tmpreg);
2818 break;
2819
2820 case 'J': /* JF foo */
2821 switch (opP->reg)
2822 {
2823 case SFC:
2824 tmpreg = 0x000;
2825 break;
2826 case DFC:
2827 tmpreg = 0x001;
2828 break;
2829 case CACR:
2830 tmpreg = 0x002;
2831 break;
2832 case TC:
2833 tmpreg = 0x003;
2834 break;
2835 case ITT0:
2836 tmpreg = 0x004;
2837 break;
2838 case ITT1:
2839 tmpreg = 0x005;
2840 break;
2841 case DTT0:
2842 tmpreg = 0x006;
2843 break;
2844 case DTT1:
2845 tmpreg = 0x007;
2846 break;
2847
2848 case USP:
2849 tmpreg = 0x800;
2850 break;
2851 case VBR:
2852 tmpreg = 0x801;
2853 break;
2854 case CAAR:
2855 tmpreg = 0x802;
2856 break;
2857 case MSP:
2858 tmpreg = 0x803;
2859 break;
2860 case ISP:
2861 tmpreg = 0x804;
2862 break;
2863 case MMUSR:
2864 tmpreg = 0x805;
2865 break;
2866 case URP:
2867 tmpreg = 0x806;
2868 break;
2869 case SRP:
2870 tmpreg = 0x807;
2871 break;
2872 default:
2873 as_fatal ("failed sanity check.");
2874 }
2875 install_operand (s[1], tmpreg);
2876 break;
2877
2878 case 'k':
2879 tmpreg = get_num (opP->con1, 55);
2880 install_operand (s[1], tmpreg & 0x7f);
2881 break;
2882
2883 case 'l':
2884 tmpreg = opP->reg;
2885 if (s[1] == 'w')
2886 {
2887 if (tmpreg & 0x7FF0000)
2888 as_bad ("Floating point register in register list");
2889 insop (reverse_16_bits (tmpreg), opcode);
2890 }
2891 else
2892 {
2893 if (tmpreg & 0x700FFFF)
2894 as_bad ("Wrong register in floating-point reglist");
2895 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2896 }
2897 break;
2898
2899 case 'L':
2900 tmpreg = opP->reg;
2901 if (s[1] == 'w')
2902 {
2903 if (tmpreg & 0x7FF0000)
2904 as_bad ("Floating point register in register list");
2905 insop (tmpreg, opcode);
2906 }
2907 else if (s[1] == '8')
2908 {
2909 if (tmpreg & 0x0FFFFFF)
2910 as_bad ("incorrect register in reglist");
2911 install_operand (s[1], tmpreg >> 24);
2912 }
2913 else
2914 {
2915 if (tmpreg & 0x700FFFF)
2916 as_bad ("wrong register in floating-point reglist");
2917 else
2918 install_operand (s[1], tmpreg >> 16);
2919 }
2920 break;
2921
2922 case 'M':
2923 install_operand (s[1], get_num (opP->con1, 60));
2924 break;
2925
2926 case 'O':
2927 tmpreg = (opP->mode == DREG)
2928 ? 0x20 + opP->reg - DATA
2929 : (get_num (opP->con1, 40) & 0x1F);
2930 install_operand (s[1], tmpreg);
2931 break;
2932
2933 case 'Q':
2934 tmpreg = get_num (opP->con1, 10);
2935 if (tmpreg == 8)
2936 tmpreg = 0;
2937 install_operand (s[1], tmpreg);
2938 break;
2939
2940 case 'R':
2941 case 'r':
2942 /* This depends on the fact that ADDR registers are
2943 eight more than their corresponding DATA regs, so
2944 the result will have the ADDR_REG bit set */
2945 install_operand (s[1], opP->reg - DATA);
2946 break;
2947
2948 case 's':
2949 if (opP->reg == FPI)
2950 tmpreg = 0x1;
2951 else if (opP->reg == FPS)
2952 tmpreg = 0x2;
2953 else if (opP->reg == FPC)
2954 tmpreg = 0x4;
2955 else
2956 as_fatal ("failed sanity check.");
2957 install_operand (s[1], tmpreg);
2958 break;
2959
2960 case 'S': /* Ignore it */
2961 break;
2962
2963 case 'T':
2964 install_operand (s[1], get_num (opP->con1, 30));
2965 break;
2966
2967 case 'U': /* Ignore it */
2968 break;
2969
2970 case 'c':
2971 switch (opP->reg)
2972 {
2973 case NC:
2974 tmpreg = 0;
2975 break;
2976 case DC:
2977 tmpreg = 1;
2978 break;
2979 case IC:
2980 tmpreg = 2;
2981 break;
2982 case BC:
2983 tmpreg = 3;
2984 break;
2985 default:
2986 as_fatal ("failed sanity check");
2987 } /* switch on cache token */
2988 install_operand (s[1], tmpreg);
2989 break;
2990 #ifndef NO_68851
2991 /* JF: These are out of order, I fear. */
2992 case 'f':
2993 switch (opP->reg)
2994 {
2995 case SFC:
2996 tmpreg = 0;
2997 break;
2998 case DFC:
2999 tmpreg = 1;
3000 break;
3001 default:
3002 as_fatal ("failed sanity check.");
3003 }
3004 install_operand (s[1], tmpreg);
3005 break;
3006
3007 case 'P':
3008 switch (opP->reg)
3009 {
3010 case TC:
3011 tmpreg = 0;
3012 break;
3013 case CAL:
3014 tmpreg = 4;
3015 break;
3016 case VAL:
3017 tmpreg = 5;
3018 break;
3019 case SCC:
3020 tmpreg = 6;
3021 break;
3022 case AC:
3023 tmpreg = 7;
3024 break;
3025 default:
3026 as_fatal ("failed sanity check.");
3027 }
3028 install_operand (s[1], tmpreg);
3029 break;
3030
3031 case 'V':
3032 if (opP->reg == VAL)
3033 break;
3034 as_fatal ("failed sanity check.");
3035
3036 case 'W':
3037 switch (opP->reg)
3038 {
3039
3040 case DRP:
3041 tmpreg = 1;
3042 break;
3043 case SRP:
3044 tmpreg = 2;
3045 break;
3046 case CRP:
3047 tmpreg = 3;
3048 break;
3049 default:
3050 as_fatal ("failed sanity check.");
3051 }
3052 install_operand (s[1], tmpreg);
3053 break;
3054
3055 case 'X':
3056 switch (opP->reg)
3057 {
3058 case BAD:
3059 case BAD + 1:
3060 case BAD + 2:
3061 case BAD + 3:
3062 case BAD + 4:
3063 case BAD + 5:
3064 case BAD + 6:
3065 case BAD + 7:
3066 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3067 break;
3068
3069 case BAC:
3070 case BAC + 1:
3071 case BAC + 2:
3072 case BAC + 3:
3073 case BAC + 4:
3074 case BAC + 5:
3075 case BAC + 6:
3076 case BAC + 7:
3077 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3078 break;
3079
3080 default:
3081 as_fatal ("failed sanity check.");
3082 }
3083 install_operand (s[1], tmpreg);
3084 break;
3085 case 'Y':
3086 know (opP->reg == PSR);
3087 break;
3088 case 'Z':
3089 know (opP->reg == PCSR);
3090 break;
3091 #endif /* m68851 */
3092 case '3':
3093 switch (opP->reg)
3094 {
3095 case TT0:
3096 tmpreg = 2;
3097 break;
3098 case TT1:
3099 tmpreg = 3;
3100 break;
3101 default:
3102 as_fatal ("failed sanity check");
3103 }
3104 install_operand (s[1], tmpreg);
3105 break;
3106 case 't':
3107 tmpreg = get_num (opP->con1, 20);
3108 install_operand (s[1], tmpreg);
3109 break;
3110 case '_': /* used only for move16 absolute 32-bit address */
3111 tmpreg = get_num (opP->con1, 80);
3112 addword (tmpreg >> 16);
3113 addword (tmpreg & 0xFFFF);
3114 break;
3115 default:
3116 as_fatal ("Internal error: Operand type %c unknown in line %d of file \"%s\"",
3117 s[0], __LINE__, __FILE__);
3118 }
3119 }
3120
3121 /* By the time whe get here (FINALLY) the_ins contains the complete
3122 instruction, ready to be emitted. . . */
3123 } /* m68k_ip() */
3124
3125 /*
3126 * get_regs := '/' + ?
3127 * | '-' + <register>
3128 * | '-' + <register> + ?
3129 * | <empty>
3130 * ;
3131 *
3132
3133 * The idea here must be to scan in a set of registers but I don't
3134 * understand it. Looks awfully sloppy to me but I don't have any doc on
3135 * this format so...
3136
3137 *
3138 *
3139 */
3140
3141 static int
3142 get_regs (i, str, opP)
3143 int i;
3144 struct m68k_op *opP;
3145 char *str;
3146 {
3147 /* 26, 25, 24, 23-16, 15-8, 0-7 */
3148 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
3149 unsigned long cur_regs = 0;
3150 int reg1, reg2;
3151
3152 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
3153 else if(x==FPS) cur_regs|=(1<<25);\
3154 else if(x==FPC) cur_regs|=(1<<26);\
3155 else cur_regs|=(1<<(x-1)); }
3156
3157 reg1 = i;
3158 for (;;)
3159 {
3160 if (*str == '/')
3161 {
3162 ADD_REG (reg1);
3163 str++;
3164 }
3165 else if (*str == '-')
3166 {
3167 str++;
3168 reg2 = m68k_reg_parse (&str);
3169 if (reg2 < DATA || reg2 >= FPREG + 8 || reg1 == FPI || reg1 == FPS || reg1 == FPC)
3170 {
3171 opP->error = "unknown register in register list";
3172 return FAIL;
3173 }
3174 while (reg1 <= reg2)
3175 {
3176 ADD_REG (reg1);
3177 reg1++;
3178 }
3179 if (*str == '\0')
3180 break;
3181 }
3182 else if (*str == '\0')
3183 {
3184 ADD_REG (reg1);
3185 break;
3186 }
3187 else
3188 {
3189 opP->error = "unknow character in register list";
3190 return FAIL;
3191 }
3192 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
3193 if (*str == '/')
3194 str++;
3195 reg1 = m68k_reg_parse (&str);
3196 if ((reg1 < DATA || reg1 >= FPREG + 8) && !(reg1 == FPI || reg1 == FPS || reg1 == FPC))
3197 {
3198 opP->error = "unknown register in register list";
3199 return FAIL;
3200 }
3201 }
3202 opP->reg = cur_regs;
3203 return OK;
3204 } /* get_regs() */
3205
3206 static int
3207 reverse_16_bits (in)
3208 int in;
3209 {
3210 int out = 0;
3211 int n;
3212
3213 static int mask[16] =
3214 {
3215 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3216 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3217 };
3218 for (n = 0; n < 16; n++)
3219 {
3220 if (in & mask[n])
3221 out |= mask[15 - n];
3222 }
3223 return out;
3224 } /* reverse_16_bits() */
3225
3226 static int
3227 reverse_8_bits (in)
3228 int in;
3229 {
3230 int out = 0;
3231 int n;
3232
3233 static int mask[8] =
3234 {
3235 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3236 };
3237
3238 for (n = 0; n < 8; n++)
3239 {
3240 if (in & mask[n])
3241 out |= mask[7 - n];
3242 }
3243 return out;
3244 } /* reverse_8_bits() */
3245
3246 static void
3247 install_operand (mode, val)
3248 int mode;
3249 int val;
3250 {
3251 switch (mode)
3252 {
3253 case 's':
3254 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3255 break;
3256 case 'd':
3257 the_ins.opcode[0] |= val << 9;
3258 break;
3259 case '1':
3260 the_ins.opcode[1] |= val << 12;
3261 break;
3262 case '2':
3263 the_ins.opcode[1] |= val << 6;
3264 break;
3265 case '3':
3266 the_ins.opcode[1] |= val;
3267 break;
3268 case '4':
3269 the_ins.opcode[2] |= val << 12;
3270 break;
3271 case '5':
3272 the_ins.opcode[2] |= val << 6;
3273 break;
3274 case '6':
3275 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3276 three words long! */
3277 the_ins.numo++;
3278 the_ins.opcode[2] |= val;
3279 break;
3280 case '7':
3281 the_ins.opcode[1] |= val << 7;
3282 break;
3283 case '8':
3284 the_ins.opcode[1] |= val << 10;
3285 break;
3286 #ifndef NO_68851
3287 case '9':
3288 the_ins.opcode[1] |= val << 5;
3289 break;
3290 #endif
3291
3292 case 't':
3293 the_ins.opcode[1] |= (val << 10) | (val << 7);
3294 break;
3295 case 'D':
3296 the_ins.opcode[1] |= (val << 12) | val;
3297 break;
3298 case 'g':
3299 the_ins.opcode[0] |= val = 0xff;
3300 break;
3301 case 'i':
3302 the_ins.opcode[0] |= val << 9;
3303 break;
3304 case 'C':
3305 the_ins.opcode[1] |= val;
3306 break;
3307 case 'j':
3308 the_ins.opcode[1] |= val;
3309 the_ins.numo++; /* What a hack */
3310 break;
3311 case 'k':
3312 the_ins.opcode[1] |= val << 4;
3313 break;
3314 case 'b':
3315 case 'w':
3316 case 'l':
3317 break;
3318 case 'e':
3319 the_ins.opcode[0] |= (val << 6);
3320 break;
3321 case 'L':
3322 the_ins.opcode[1] = (val >> 16);
3323 the_ins.opcode[2] = val & 0xffff;
3324 break;
3325 case 'c':
3326 default:
3327 as_fatal ("failed sanity check.");
3328 }
3329 } /* install_operand() */
3330
3331 static void
3332 install_gen_operand (mode, val)
3333 int mode;
3334 int val;
3335 {
3336 switch (mode)
3337 {
3338 case 's':
3339 the_ins.opcode[0] |= val;
3340 break;
3341 case 'd':
3342 /* This is a kludge!!! */
3343 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3344 break;
3345 case 'b':
3346 case 'w':
3347 case 'l':
3348 case 'f':
3349 case 'F':
3350 case 'x':
3351 case 'p':
3352 the_ins.opcode[0] |= val;
3353 break;
3354 /* more stuff goes here */
3355 default:
3356 as_fatal ("failed sanity check.");
3357 }
3358 } /* install_gen_operand() */
3359
3360 /*
3361 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3362 * then deal with the bitfield hack.
3363 */
3364
3365 static char *
3366 crack_operand (str, opP)
3367 register char *str;
3368 register struct m68k_op *opP;
3369 {
3370 register int parens;
3371 register int c;
3372 register char *beg_str;
3373
3374 if (!str)
3375 {
3376 return str;
3377 }
3378 beg_str = str;
3379 for (parens = 0; *str && (parens > 0 || notend (str)); str++)
3380 {
3381 if (*str == '(')
3382 parens++;
3383 else if (*str == ')')
3384 {
3385 if (!parens)
3386 { /* ERROR */
3387 opP->error = "Extra )";
3388 return str;
3389 }
3390 --parens;
3391 }
3392 }
3393 if (!*str && parens)
3394 { /* ERROR */
3395 opP->error = "Missing )";
3396 return str;
3397 }
3398 c = *str;
3399 *str = '\0';
3400 if (m68k_ip_op (beg_str, opP) == FAIL)
3401 {
3402 *str = c;
3403 return str;
3404 }
3405 *str = c;
3406 if (c == '}')
3407 c = *++str; /* JF bitfield hack */
3408 if (c)
3409 {
3410 c = *++str;
3411 if (!c)
3412 as_bad ("Missing operand");
3413 }
3414 return str;
3415 }
3416
3417 /* See the comment up above where the #define notend(... is */
3418 #if 0
3419 notend (s)
3420 char *s;
3421 {
3422 if (*s == ',')
3423 return 0;
3424 if (*s == '{' || *s == '}')
3425 return 0;
3426 if (*s != ':')
3427 return 1;
3428 /* This kludge here is for the division cmd, which is a kludge */
3429 if (index ("aAdD#", s[1]))
3430 return 0;
3431 return 1;
3432 }
3433
3434 #endif
3435
3436 /* This is the guts of the machine-dependent assembler. STR points to a
3437 machine dependent instruction. This function is supposed to emit
3438 the frags/bytes it assembles to.
3439 */
3440
3441 void
3442 insert_reg (regname, regnum)
3443 char *regname;
3444 int regnum;
3445 {
3446 char buf[100];
3447 int i;
3448
3449 #ifdef REGISTER_PREFIX
3450 if (!flag_reg_prefix_optional)
3451 {
3452 buf[0] = REGISTER_PREFIX;
3453 strcpy (buf + 1, regname);
3454 regname = buf;
3455 }
3456 #endif
3457
3458 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3459 &zero_address_frag));
3460
3461 for (i = 0; regname[i]; i++)
3462 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3463 buf[i] = '\0';
3464
3465 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3466 &zero_address_frag));
3467 }
3468
3469 struct init_entry
3470 {
3471 const char *name;
3472 int number;
3473 };
3474
3475 static const struct init_entry init_table[] =
3476 {
3477 { "d0", DATA0 },
3478 { "d1", DATA1 },
3479 { "d2", DATA2 },
3480 { "d3", DATA3 },
3481 { "d4", DATA4 },
3482 { "d5", DATA5 },
3483 { "d6", DATA6 },
3484 { "d7", DATA7 },
3485 { "a0", ADDR0 },
3486 { "a1", ADDR1 },
3487 { "a2", ADDR2 },
3488 { "a3", ADDR3 },
3489 { "a4", ADDR4 },
3490 { "a5", ADDR5 },
3491 { "a6", ADDR6 },
3492 { "fp", ADDR6 },
3493 { "a7", ADDR7 },
3494 { "sp", ADDR7 },
3495 { "fp0", FP0 },
3496 { "fp1", FP1 },
3497 { "fp2", FP2 },
3498 { "fp3", FP3 },
3499 { "fp4", FP4 },
3500 { "fp5", FP5 },
3501 { "fp6", FP6 },
3502 { "fp7", FP7 },
3503 { "fpi", FPI },
3504 { "fpiar", FPI },
3505 { "fpc", FPI },
3506 { "fps", FPS },
3507 { "fpsr", FPS },
3508 { "fpc", FPC },
3509 { "fpcr", FPC },
3510
3511 { "cop0", COP0 },
3512 { "cop1", COP1 },
3513 { "cop2", COP2 },
3514 { "cop3", COP3 },
3515 { "cop4", COP4 },
3516 { "cop5", COP5 },
3517 { "cop6", COP6 },
3518 { "cop7", COP7 },
3519 { "pc", PC },
3520 { "zpc", ZPC },
3521 { "sr", SR },
3522
3523 { "ccr", CCR },
3524 { "cc", CCR },
3525
3526 { "usp", USP },
3527 { "isp", ISP },
3528 { "sfc", SFC },
3529 { "dfc", DFC },
3530 { "cacr", CACR },
3531 { "caar", CAAR },
3532
3533 { "vbr", VBR },
3534
3535 { "msp", MSP },
3536 { "itt0", ITT0 },
3537 { "itt1", ITT1 },
3538 { "dtt0", DTT0 },
3539 { "dtt1", DTT1 },
3540 { "mmusr", MMUSR },
3541 { "tc", TC },
3542 { "srp", SRP },
3543 { "urp", URP },
3544
3545 { "ac", AC },
3546 { "bc", BC },
3547 { "cal", CAL },
3548 { "crp", CRP },
3549 { "drp", DRP },
3550 { "pcsr", PCSR },
3551 { "psr", PSR },
3552 { "scc", SCC },
3553 { "val", VAL },
3554 { "bad0", BAD0 },
3555 { "bad1", BAD1 },
3556 { "bad2", BAD2 },
3557 { "bad3", BAD3 },
3558 { "bad4", BAD4 },
3559 { "bad5", BAD5 },
3560 { "bad6", BAD6 },
3561 { "bad7", BAD7 },
3562 { "bac0", BAC0 },
3563 { "bac1", BAC1 },
3564 { "bac2", BAC2 },
3565 { "bac3", BAC3 },
3566 { "bac4", BAC4 },
3567 { "bac5", BAC5 },
3568 { "bac6", BAC6 },
3569 { "bac7", BAC7 },
3570
3571 { "ic", IC },
3572 { "dc", DC },
3573 { "nc", NC },
3574
3575 { "tt0", TT0 },
3576 { "tt1", TT1 },
3577 /* 68ec030 versions of same */
3578 { "ac0", TT0 },
3579 { "ac1", TT1 },
3580 /* 68ec030 access control unit, identical to 030 MMU status reg */
3581 { "acusr", PSR },
3582
3583 { 0, 0 }
3584 };
3585
3586 void
3587 init_regtable ()
3588 {
3589 int i;
3590 for (i = 0; init_table[i].name; i++)
3591 insert_reg (init_table[i].name, init_table[i].number);
3592 }
3593
3594 static int no_68851, no_68881;
3595
3596 #ifdef OBJ_AOUT
3597 /* a.out machine type. Default to 68020. */
3598 int m68k_aout_machtype = 2;
3599 #endif
3600
3601 void
3602 md_assemble (str)
3603 char *str;
3604 {
3605 char *er;
3606 short *fromP;
3607 char *toP = NULL;
3608 int m, n = 0;
3609 char *to_beg_P;
3610 int shorts_this_frag;
3611
3612 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3613 m68k_ip (str);
3614 er = the_ins.error;
3615 if (!er)
3616 {
3617 for (n = the_ins.numargs; n; --n)
3618 if (the_ins.operands[n].error)
3619 {
3620 er = the_ins.operands[n].error;
3621 break;
3622 }
3623 }
3624 if (er)
3625 {
3626 as_bad ("%s -- statement `%s' ignored", er, str);
3627 return;
3628 }
3629
3630 if (the_ins.nfrag == 0)
3631 {
3632 /* No frag hacking involved; just put it out */
3633 toP = frag_more (2 * the_ins.numo);
3634 fromP = &the_ins.opcode[0];
3635 for (m = the_ins.numo; m; --m)
3636 {
3637 md_number_to_chars (toP, (long) (*fromP), 2);
3638 toP += 2;
3639 fromP++;
3640 }
3641 /* put out symbol-dependent info */
3642 for (m = 0; m < the_ins.nrel; m++)
3643 {
3644 switch (the_ins.reloc[m].wid)
3645 {
3646 case 'B':
3647 n = 1;
3648 break;
3649 case 'b':
3650 n = 1;
3651 break;
3652 case '3':
3653 n = 2;
3654 break;
3655 case 'w':
3656 n = 2;
3657 break;
3658 case 'l':
3659 n = 4;
3660 break;
3661 default:
3662 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3663 the_ins.reloc[m].wid);
3664 }
3665
3666 fix_new_exp (frag_now,
3667 ((toP - frag_now->fr_literal)
3668 - the_ins.numo * 2 + the_ins.reloc[m].n),
3669 n,
3670 &the_ins.reloc[m].exp,
3671 the_ins.reloc[m].pcrel,
3672 NO_RELOC);
3673 }
3674 return;
3675 }
3676
3677 /* There's some frag hacking */
3678 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3679 {
3680 int wid;
3681
3682 if (n == 0)
3683 wid = 2 * the_ins.fragb[n].fragoff;
3684 else
3685 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3686 toP = frag_more (wid);
3687 to_beg_P = toP;
3688 shorts_this_frag = 0;
3689 for (m = wid / 2; m; --m)
3690 {
3691 md_number_to_chars (toP, (long) (*fromP), 2);
3692 toP += 2;
3693 fromP++;
3694 shorts_this_frag++;
3695 }
3696 for (m = 0; m < the_ins.nrel; m++)
3697 {
3698 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3699 {
3700 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3701 break;
3702 }
3703 wid = the_ins.reloc[m].wid;
3704 if (wid == 0)
3705 continue;
3706 the_ins.reloc[m].wid = 0;
3707 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3708
3709 fix_new_exp (frag_now,
3710 ((toP - frag_now->fr_literal)
3711 - the_ins.numo * 2 + the_ins.reloc[m].n),
3712 wid,
3713 &the_ins.reloc[m].exp,
3714 the_ins.reloc[m].pcrel,
3715 NO_RELOC);
3716 }
3717 (void) frag_var (rs_machine_dependent, 10, 0,
3718 (relax_substateT) (the_ins.fragb[n].fragty),
3719 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3720 }
3721 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3722 shorts_this_frag = 0;
3723 if (n)
3724 {
3725 toP = frag_more (n * sizeof (short));
3726 while (n--)
3727 {
3728 md_number_to_chars (toP, (long) (*fromP), 2);
3729 toP += 2;
3730 fromP++;
3731 shorts_this_frag++;
3732 }
3733 }
3734 for (m = 0; m < the_ins.nrel; m++)
3735 {
3736 int wid;
3737
3738 wid = the_ins.reloc[m].wid;
3739 if (wid == 0)
3740 continue;
3741 the_ins.reloc[m].wid = 0;
3742 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3743
3744 fix_new_exp (frag_now,
3745 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3746 - shorts_this_frag * 2),
3747 wid,
3748 &the_ins.reloc[m].exp,
3749 the_ins.reloc[m].pcrel,
3750 NO_RELOC);
3751 }
3752 }
3753
3754 /* See BREAK_UP_BIG_DECL definition, above. */
3755 static struct m68k_opcode *
3756 opcode_ptr (i)
3757 int i;
3758 {
3759 #ifdef DO_BREAK_UP_BIG_DECL
3760 int lim1 = sizeof (m68k_opcodes) / sizeof (m68k_opcodes[0]);
3761 if (i >= lim1)
3762 return m68k_opcodes_2 + (i - lim1);
3763 #endif
3764 return m68k_opcodes + i;
3765 }
3766
3767 void
3768 md_begin ()
3769 {
3770 /*
3771 * md_begin -- set up hash tables with 68000 instructions.
3772 * similar to what the vax assembler does. ---phr
3773 */
3774 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3775 a copy of it at runtime, adding in the information we want but isn't
3776 there. I think it'd be better to have an awk script hack the table
3777 at compile time. Or even just xstr the table and use it as-is. But
3778 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3779 names. */
3780
3781 register CONST struct m68k_opcode *ins;
3782 register struct m68k_incant *hack, *slak;
3783 register const char *retval = 0; /* empty string, or error msg text */
3784 register unsigned int i;
3785 register char c;
3786
3787 op_hash = hash_new ();
3788
3789 obstack_begin (&robyn, 4000);
3790 for (i = 0; i < numopcodes; i++)
3791 {
3792 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3793 do
3794 {
3795 ins = opcode_ptr (i);
3796 /* We *could* ignore insns that don't match our arch here
3797 but just leaving them out of the hash. */
3798 slak->m_operands = ins->args;
3799 slak->m_opnum = strlen (slak->m_operands) / 2;
3800 slak->m_arch = ins->arch;
3801 slak->m_opcode = ins->opcode;
3802 /* This is kludgey */
3803 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3804 if (i + 1 != numopcodes
3805 && !strcmp (ins->name, opcode_ptr (i + 1)->name))
3806 {
3807 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3808 i++;
3809 }
3810 else
3811 slak->m_next = 0;
3812 slak = slak->m_next;
3813 }
3814 while (slak);
3815
3816 retval = hash_insert (op_hash, ins->name, (char *) hack);
3817 if (retval)
3818 as_bad ("Internal Error: Can't hash %s: %s", ins->name, retval);
3819 }
3820
3821 for (i = 0; i < sizeof (mklower_table); i++)
3822 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3823
3824 for (i = 0; i < sizeof (notend_table); i++)
3825 {
3826 notend_table[i] = 0;
3827 alt_notend_table[i] = 0;
3828 }
3829 notend_table[','] = 1;
3830 notend_table['{'] = 1;
3831 notend_table['}'] = 1;
3832 alt_notend_table['a'] = 1;
3833 alt_notend_table['A'] = 1;
3834 alt_notend_table['d'] = 1;
3835 alt_notend_table['D'] = 1;
3836 alt_notend_table['#'] = 1;
3837 alt_notend_table['f'] = 1;
3838 alt_notend_table['F'] = 1;
3839 #ifdef REGISTER_PREFIX
3840 alt_notend_table[REGISTER_PREFIX] = 1;
3841 #endif
3842
3843 #ifndef MIT_SYNTAX_ONLY
3844 /* Insert pseudo ops, these have to go into the opcode table since
3845 gas expects pseudo ops to start with a dot */
3846 {
3847 int n = 0;
3848 while (mote_pseudo_table[n].poc_name)
3849 {
3850 hack = (struct m68k_incant *)
3851 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3852 hash_insert (op_hash,
3853 mote_pseudo_table[n].poc_name, (char *) hack);
3854 hack->m_operands = 0;
3855 hack->m_opnum = n;
3856 n++;
3857 }
3858 }
3859 #endif
3860
3861 init_regtable ();
3862 }
3863
3864 void
3865 m68k_init_after_args ()
3866 {
3867 if (cpu_of_arch (current_architecture) == 0)
3868 {
3869 int cpu_type;
3870
3871 if (strcmp (TARGET_CPU, "m68000") == 0
3872 || strcmp (TARGET_CPU, "m68302") == 0)
3873 cpu_type = m68000;
3874 else if (strcmp (TARGET_CPU, "m68010") == 0)
3875 cpu_type = m68010;
3876 else if (strcmp (TARGET_CPU, "m68020") == 0
3877 || strcmp (TARGET_CPU, "m68k") == 0)
3878 cpu_type = m68020;
3879 else if (strcmp (TARGET_CPU, "m68030") == 0)
3880 cpu_type = m68030;
3881 else if (strcmp (TARGET_CPU, "m68040") == 0)
3882 cpu_type = m68040;
3883 else if (strcmp (TARGET_CPU, "m68060") == 0)
3884 cpu_type = m68060;
3885 else if (strcmp (TARGET_CPU, "cpu32") == 0
3886 || strcmp (TARGET_CPU, "m68331") == 0
3887 || strcmp (TARGET_CPU, "m68332") == 0
3888 || strcmp (TARGET_CPU, "m68333") == 0
3889 || strcmp (TARGET_CPU, "m68340") == 0)
3890 cpu_type = cpu32;
3891 else
3892 cpu_type = m68020;
3893
3894 current_architecture |= cpu_type;
3895 }
3896 #if 0 /* Could be doing emulation. */
3897 if (current_architecture & m68881)
3898 {
3899 if (current_architecture & m68000)
3900 as_bad ("incompatible processors 68000 and 68881/2 specified");
3901 if (current_architecture & m68010)
3902 as_bad ("incompatible processors 68010 and 68881/2 specified");
3903 if (current_architecture & m68040)
3904 as_bad ("incompatible processors 68040 and 68881/2 specified");
3905 }
3906 #endif
3907 if (current_architecture & m68851)
3908 {
3909 if (current_architecture & m68040)
3910 {
3911 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3912 }
3913 }
3914 /* What other incompatibilities could we check for? */
3915
3916 /* Toss in some default assumptions about coprocessors. */
3917 if (!no_68881
3918 && (cpu_of_arch (current_architecture)
3919 /* Can CPU32 have a 68881 coprocessor?? */
3920 & (m68020 | m68030 | cpu32)))
3921 {
3922 current_architecture |= m68881;
3923 }
3924 if (!no_68851
3925 && (cpu_of_arch (current_architecture) & m68020up) != 0
3926 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3927 {
3928 current_architecture |= m68851;
3929 }
3930 if (no_68881 && (current_architecture & m68881))
3931 as_bad ("options for 68881 and no-68881 both given");
3932 if (no_68851 && (current_architecture & m68851))
3933 as_bad ("options for 68851 and no-68851 both given");
3934
3935 #ifdef OBJ_AOUT
3936 /* Work out the magic number. This isn't very general. */
3937 if (current_architecture & m68000)
3938 m68k_aout_machtype = 0;
3939 else if (current_architecture & m68010)
3940 m68k_aout_machtype = 1;
3941 else if (current_architecture & m68020)
3942 m68k_aout_machtype = 2;
3943 else
3944 m68k_aout_machtype = 2;
3945 #endif
3946
3947 /* Note which set of "movec" control registers is available. */
3948 switch (cpu_of_arch (current_architecture))
3949 {
3950 case m68000:
3951 control_regs = m68000_control_regs;
3952 break;
3953 case m68010:
3954 control_regs = m68010_control_regs;
3955 break;
3956 case m68020:
3957 case m68030:
3958 control_regs = m68020_control_regs;
3959 break;
3960 case m68040:
3961 control_regs = m68040_control_regs;
3962 break;
3963 case m68060:
3964 control_regs = m68060_control_regs;
3965 break;
3966 default:
3967 abort ();
3968 }
3969 }
3970
3971 #if 0
3972 #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
3973 || (*s == ':' && strchr("aAdD#", s[1]))) \
3974 ? 0 : 1)
3975 #endif
3976
3977 /* Equal to MAX_PRECISION in atof-ieee.c */
3978 #define MAX_LITTLENUMS 6
3979
3980 /* Turn a string in input_line_pointer into a floating point constant of type
3981 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3982 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
3983 */
3984 char *
3985 md_atof (type, litP, sizeP)
3986 char type;
3987 char *litP;
3988 int *sizeP;
3989 {
3990 int prec;
3991 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3992 LITTLENUM_TYPE *wordP;
3993 char *t;
3994 char *atof_ieee ();
3995
3996 switch (type)
3997 {
3998 case 'f':
3999 case 'F':
4000 case 's':
4001 case 'S':
4002 prec = 2;
4003 break;
4004
4005 case 'd':
4006 case 'D':
4007 case 'r':
4008 case 'R':
4009 prec = 4;
4010 break;
4011
4012 case 'x':
4013 case 'X':
4014 prec = 6;
4015 break;
4016
4017 case 'p':
4018 case 'P':
4019 prec = 6;
4020 break;
4021
4022 default:
4023 *sizeP = 0;
4024 return "Bad call to MD_ATOF()";
4025 }
4026 t = atof_ieee (input_line_pointer, type, words);
4027 if (t)
4028 input_line_pointer = t;
4029
4030 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4031 for (wordP = words; prec--;)
4032 {
4033 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4034 litP += sizeof (LITTLENUM_TYPE);
4035 }
4036 return 0;
4037 }
4038
4039 void
4040 md_number_to_chars (buf, val, n)
4041 char *buf;
4042 valueT val;
4043 int n;
4044 {
4045 number_to_chars_bigendian (buf, val, n);
4046 }
4047
4048 static void
4049 md_apply_fix_2 (fixP, val)
4050 fixS *fixP;
4051 long val;
4052 {
4053 unsigned long upper_limit;
4054 long lower_limit;
4055
4056 #ifdef IBM_COMPILER_SUX
4057 /* This is unnecessary but it convinces the native rs6000
4058 compiler to generate the code we want. */
4059 char *buf = fixP->fx_frag->fr_literal;
4060 buf += fixP->fx_where;
4061 #else /* IBM_COMPILER_SUX */
4062 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
4063 #endif /* IBM_COMPILER_SUX */
4064
4065 switch (fixP->fx_size)
4066 {
4067 case 1:
4068 *buf++ = val;
4069 upper_limit = 0x7f;
4070 lower_limit = -0x80;
4071 break;
4072 case 2:
4073 *buf++ = (val >> 8);
4074 *buf++ = val;
4075 upper_limit = 0x7fff;
4076 lower_limit = -0x8000;
4077 break;
4078 case 4:
4079 *buf++ = (val >> 24);
4080 *buf++ = (val >> 16);
4081 *buf++ = (val >> 8);
4082 *buf++ = val;
4083 upper_limit = 0x7fffffff;
4084 lower_limit = -0x80000000;
4085 break;
4086 default:
4087 BAD_CASE (fixP->fx_size);
4088 }
4089
4090 /* For non-pc-relative values, it's conceivable we might get something
4091 like "0xff" for a byte field. So extend the upper part of the range
4092 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4093 so that we can do any range checking at all. */
4094 if (!fixP->fx_pcrel)
4095 upper_limit = upper_limit * 2 + 1;
4096
4097 if ((unsigned) val > upper_limit && (val > 0 || val < lower_limit))
4098 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
4099
4100 /* A one byte PC-relative reloc means a short branch. We can't use
4101 a short branch with a value of 0 or -1, because those indicate
4102 different opcodes (branches with longer offsets). */
4103 if (fixP->fx_pcrel
4104 && fixP->fx_size == 1
4105 && (fixP->fx_addsy == NULL
4106 || S_IS_DEFINED (fixP->fx_addsy))
4107 && (val == 0 || val == -1))
4108 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
4109 }
4110
4111 #ifdef BFD_ASSEMBLER
4112 int
4113 md_apply_fix (fixP, valp)
4114 fixS *fixP;
4115 long *valp;
4116 {
4117 md_apply_fix_2 (fixP, *valp);
4118 return 1;
4119 }
4120 #else
4121 void md_apply_fix (fixP, val)
4122 fixS *fixP;
4123 long val;
4124 {
4125 md_apply_fix_2 (fixP, val);
4126 }
4127 #endif
4128
4129 /* *fragP has been relaxed to its final size, and now needs to have
4130 the bytes inside it modified to conform to the new size There is UGLY
4131 MAGIC here. ..
4132 */
4133 void
4134 md_convert_frag_1 (fragP)
4135 register fragS *fragP;
4136 {
4137 long disp;
4138 long ext = 0;
4139
4140 /* Address in object code of the displacement. */
4141 register int object_address = fragP->fr_fix + fragP->fr_address;
4142
4143 #ifdef IBM_COMPILER_SUX
4144 /* This is wrong but it convinces the native rs6000 compiler to
4145 generate the code we want. */
4146 register char *buffer_address = fragP->fr_literal;
4147 buffer_address += fragP->fr_fix;
4148 #else /* IBM_COMPILER_SUX */
4149 /* Address in gas core of the place to store the displacement. */
4150 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4151 #endif /* IBM_COMPILER_SUX */
4152
4153 /* No longer true: know(fragP->fr_symbol); */
4154
4155 /* The displacement of the address, from current location. */
4156 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4157 disp = (disp + fragP->fr_offset) - object_address;
4158
4159 switch (fragP->fr_subtype)
4160 {
4161 case TAB (BCC68000, BYTE):
4162 case TAB (ABRANCH, BYTE):
4163 know (issbyte (disp));
4164 if (disp == 0)
4165 as_bad ("short branch with zero offset: use :w");
4166 fragP->fr_opcode[1] = disp;
4167 ext = 0;
4168 break;
4169 case TAB (DBCC, SHORT):
4170 know (issword (disp));
4171 ext = 2;
4172 break;
4173 case TAB (BCC68000, SHORT):
4174 case TAB (ABRANCH, SHORT):
4175 know (issword (disp));
4176 fragP->fr_opcode[1] = 0x00;
4177 ext = 2;
4178 break;
4179 case TAB (ABRANCH, LONG):
4180 if (cpu_of_arch (current_architecture) < m68020)
4181 {
4182 if (fragP->fr_opcode[0] == 0x61)
4183 {
4184 fragP->fr_opcode[0] = 0x4E;
4185 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4186 subseg_change (text_section, 0); /* @@ */
4187
4188 fix_new (fragP,
4189 fragP->fr_fix,
4190 4,
4191 fragP->fr_symbol,
4192 fragP->fr_offset,
4193 0,
4194 NO_RELOC);
4195
4196 fragP->fr_fix += 4;
4197 ext = 0;
4198 }
4199 else if (fragP->fr_opcode[0] == 0x60)
4200 {
4201 fragP->fr_opcode[0] = 0x4E;
4202 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4203 subseg_change (text_section, 0); /* @@ */
4204 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4205 fragP->fr_offset, 0, NO_RELOC);
4206 fragP->fr_fix += 4;
4207 ext = 0;
4208 }
4209 else
4210 {
4211 as_bad ("Long branch offset not supported.");
4212 }
4213 }
4214 else
4215 {
4216 fragP->fr_opcode[1] = (char) 0xff;
4217 ext = 4;
4218 }
4219 break;
4220 case TAB (BCC68000, LONG):
4221 /* only Bcc 68000 instructions can come here */
4222 /* change bcc into b!cc/jmp absl long */
4223 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4224 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4225
4226 /* JF: these used to be fr_opcode[2,3], but they may be in a
4227 different frag, in which case refering to them is a no-no.
4228 Only fr_opcode[0,1] are guaranteed to work. */
4229 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4230 *buffer_address++ = (char) 0xf9;
4231 fragP->fr_fix += 2; /* account for jmp instruction */
4232 subseg_change (text_section, 0);
4233 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4234 fragP->fr_offset, 0, NO_RELOC);
4235 fragP->fr_fix += 4;
4236 ext = 0;
4237 break;
4238 case TAB (DBCC, LONG):
4239 /* only DBcc 68000 instructions can come here */
4240 /* change dbcc into dbcc/jmp absl long */
4241 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4242 *buffer_address++ = 0x00; /* branch offset = 4 */
4243 *buffer_address++ = 0x04;
4244 *buffer_address++ = 0x60; /* put in bra pc+6 */
4245 *buffer_address++ = 0x06;
4246 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4247 *buffer_address++ = (char) 0xf9;
4248
4249 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4250 subseg_change (text_section, 0);
4251 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4252 fragP->fr_offset, 0, NO_RELOC);
4253 fragP->fr_fix += 4;
4254 ext = 0;
4255 break;
4256 case TAB (FBRANCH, SHORT):
4257 know ((fragP->fr_opcode[1] & 0x40) == 0);
4258 ext = 2;
4259 break;
4260 case TAB (FBRANCH, LONG):
4261 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4262 ext = 4;
4263 break;
4264 case TAB (PCREL, SHORT):
4265 ext = 2;
4266 break;
4267 case TAB (PCREL, LONG):
4268 /* The thing to do here is force it to ABSOLUTE LONG, since
4269 PCREL is really trying to shorten an ABSOLUTE address anyway */
4270 /* JF FOO This code has not been tested */
4271 subseg_change (text_section, 0);
4272 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4273 0, NO_RELOC);
4274 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4275 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4276 (unsigned) fragP->fr_opcode[0],
4277 (unsigned long) fragP->fr_address);
4278 fragP->fr_opcode[1] &= ~0x3F;
4279 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4280 fragP->fr_fix += 4;
4281 ext = 0;
4282 break;
4283 case TAB (PCLEA, SHORT):
4284 subseg_change (text_section, 0);
4285 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4286 fragP->fr_offset, 1, NO_RELOC);
4287 fragP->fr_opcode[1] &= ~0x3F;
4288 fragP->fr_opcode[1] |= 0x3A;
4289 ext = 2;
4290 break;
4291 case TAB (PCLEA, LONG):
4292 subseg_change (text_section, 0);
4293 fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4294 fragP->fr_offset + 2, 1, NO_RELOC);
4295 *buffer_address++ = 0x01;
4296 *buffer_address++ = 0x70;
4297 fragP->fr_fix += 2;
4298 ext = 4;
4299 break;
4300 }
4301
4302 if (ext)
4303 {
4304 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4305 fragP->fr_fix += ext;
4306 }
4307 }
4308
4309 #ifndef BFD_ASSEMBLER
4310
4311 void
4312 md_convert_frag (headers, fragP)
4313 object_headers *headers;
4314 fragS *fragP;
4315 {
4316 md_convert_frag_1 (fragP);
4317 }
4318
4319 #else
4320
4321 void
4322 md_convert_frag (abfd, sec, fragP)
4323 bfd *abfd;
4324 asection sec;
4325 fragS *fragP;
4326 {
4327 md_convert_frag_1 (fragP);
4328 }
4329 #endif
4330
4331 /* Force truly undefined symbols to their maximum size, and generally set up
4332 the frag list to be relaxed
4333 */
4334 int
4335 md_estimate_size_before_relax (fragP, segment)
4336 register fragS *fragP;
4337 segT segment;
4338 {
4339 int old_fix;
4340 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4341
4342 old_fix = fragP->fr_fix;
4343
4344 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4345 switch (fragP->fr_subtype)
4346 {
4347
4348 case TAB (ABRANCH, SZ_UNDEF):
4349 {
4350 if ((fragP->fr_symbol != NULL) /* Not absolute */
4351 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4352 {
4353 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4354 break;
4355 }
4356 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4357 {
4358 /* On 68000, or for absolute value, switch to abs long */
4359 /* FIXME, we should check abs val, pick short or long */
4360 if (fragP->fr_opcode[0] == 0x61)
4361 {
4362 fragP->fr_opcode[0] = 0x4E;
4363 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4364 subseg_change (text_section, 0);
4365 fix_new (fragP, fragP->fr_fix, 4,
4366 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4367 fragP->fr_fix += 4;
4368 frag_wane (fragP);
4369 }
4370 else if (fragP->fr_opcode[0] == 0x60)
4371 {
4372 fragP->fr_opcode[0] = 0x4E;
4373 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4374 subseg_change (text_section, 0);
4375 fix_new (fragP, fragP->fr_fix, 4,
4376 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4377 fragP->fr_fix += 4;
4378 frag_wane (fragP);
4379 }
4380 else
4381 {
4382 as_warn ("Long branch offset to extern symbol not supported.");
4383 }
4384 }
4385 else
4386 { /* Symbol is still undefined. Make it simple */
4387 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4388 fragP->fr_offset + 4, 1, NO_RELOC);
4389 fragP->fr_fix += 4;
4390 fragP->fr_opcode[1] = (char) 0xff;
4391 frag_wane (fragP);
4392 break;
4393 }
4394
4395 break;
4396 } /* case TAB(ABRANCH,SZ_UNDEF) */
4397
4398 case TAB (FBRANCH, SZ_UNDEF):
4399 {
4400 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flagseen['l'])
4401 {
4402 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4403 fragP->fr_var += 2;
4404 }
4405 else
4406 {
4407 fragP->fr_subtype = TAB (FBRANCH, LONG);
4408 fragP->fr_var += 4;
4409 }
4410 break;
4411 } /* TAB(FBRANCH,SZ_UNDEF) */
4412
4413 case TAB (PCREL, SZ_UNDEF):
4414 {
4415 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flagseen['l'])
4416 {
4417 fragP->fr_subtype = TAB (PCREL, SHORT);
4418 fragP->fr_var += 2;
4419 }
4420 else
4421 {
4422 fragP->fr_subtype = TAB (PCREL, LONG);
4423 fragP->fr_var += 4;
4424 }
4425 break;
4426 } /* TAB(PCREL,SZ_UNDEF) */
4427
4428 case TAB (BCC68000, SZ_UNDEF):
4429 {
4430 if ((fragP->fr_symbol != NULL)
4431 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4432 {
4433 fragP->fr_subtype = TAB (BCC68000, BYTE);
4434 break;
4435 }
4436 /* only Bcc 68000 instructions can come here */
4437 /* change bcc into b!cc/jmp absl long */
4438 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4439 if (flagseen['l'])
4440 {
4441 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4442 /* JF: these were fr_opcode[2,3] */
4443 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4444 buffer_address[1] = (char) 0xf8;
4445 fragP->fr_fix += 2; /* account for jmp instruction */
4446 subseg_change (text_section, 0);
4447 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4448 fragP->fr_offset, 0, NO_RELOC);
4449 fragP->fr_fix += 2;
4450 }
4451 else
4452 {
4453 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4454 /* JF: these were fr_opcode[2,3] */
4455 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4456 buffer_address[1] = (char) 0xf9;
4457 fragP->fr_fix += 2; /* account for jmp instruction */
4458 subseg_change (text_section, 0);
4459 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4460 fragP->fr_offset, 0, NO_RELOC);
4461 fragP->fr_fix += 4;
4462 }
4463 frag_wane (fragP);
4464 break;
4465 } /* case TAB(BCC68000,SZ_UNDEF) */
4466
4467 case TAB (DBCC, SZ_UNDEF):
4468 {
4469 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4470 {
4471 fragP->fr_subtype = TAB (DBCC, SHORT);
4472 fragP->fr_var += 2;
4473 break;
4474 }
4475 /* only DBcc 68000 instructions can come here */
4476 /* change dbcc into dbcc/jmp absl long */
4477 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4478 buffer_address[0] = 0x00; /* branch offset = 4 */
4479 buffer_address[1] = 0x04;
4480 buffer_address[2] = 0x60; /* put in bra pc + ... */
4481
4482 if (flagseen['l'])
4483 {
4484 /* JF: these were fr_opcode[5-7] */
4485 buffer_address[3] = 0x04; /* plus 4 */
4486 buffer_address[4] = 0x4e; /* Put in Jump Word */
4487 buffer_address[5] = (char) 0xf8;
4488 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4489 subseg_change (text_section, 0);
4490 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4491 fragP->fr_offset, 0, NO_RELOC);
4492 fragP->fr_fix += 2;
4493 }
4494 else
4495 {
4496 /* JF: these were fr_opcode[5-7] */
4497 buffer_address[3] = 0x06; /* Plus 6 */
4498 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4499 buffer_address[5] = (char) 0xf9;
4500 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4501 subseg_change (text_section, 0);
4502 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4503 fragP->fr_offset, 0, NO_RELOC);
4504 fragP->fr_fix += 4;
4505 }
4506
4507 frag_wane (fragP);
4508 break;
4509 } /* case TAB(DBCC,SZ_UNDEF) */
4510
4511 case TAB (PCLEA, SZ_UNDEF):
4512 {
4513 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment || flagseen['l'])
4514 {
4515 fragP->fr_subtype = TAB (PCLEA, SHORT);
4516 fragP->fr_var += 2;
4517 }
4518 else
4519 {
4520 fragP->fr_subtype = TAB (PCLEA, LONG);
4521 fragP->fr_var += 6;
4522 }
4523 break;
4524 } /* TAB(PCLEA,SZ_UNDEF) */
4525
4526 default:
4527 break;
4528
4529 } /* switch on subtype looking for SZ_UNDEF's. */
4530
4531 /* now that SZ_UNDEF are taken care of, check others */
4532 switch (fragP->fr_subtype)
4533 {
4534 case TAB (BCC68000, BYTE):
4535 case TAB (ABRANCH, BYTE):
4536 /* We can't do a short jump to the next instruction,
4537 so we force word mode. */
4538 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
4539 fragP->fr_symbol->sy_frag == fragP->fr_next)
4540 {
4541 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4542 fragP->fr_var += 2;
4543 }
4544 break;
4545 default:
4546 break;
4547 }
4548 return fragP->fr_var + fragP->fr_fix - old_fix;
4549 }
4550
4551 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4552 /* the bit-field entries in the relocation_info struct plays hell
4553 with the byte-order problems of cross-assembly. So as a hack,
4554 I added this mach. dependent ri twiddler. Ugly, but it gets
4555 you there. -KWK */
4556 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4557 are symbolnum, most sig. byte first. Last byte is broken up with
4558 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4559 nibble as nuthin. (on Sun 3 at least) */
4560 /* Translate the internal relocation information into target-specific
4561 format. */
4562 #ifdef comment
4563 void
4564 md_ri_to_chars (the_bytes, ri)
4565 char *the_bytes;
4566 struct reloc_info_generic *ri;
4567 {
4568 /* this is easy */
4569 md_number_to_chars (the_bytes, ri->r_address, 4);
4570 /* now the fun stuff */
4571 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4572 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4573 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4574 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4575 ((ri->r_extern << 4) & 0x10));
4576 }
4577
4578 #endif /* comment */
4579
4580 #ifndef BFD_ASSEMBLER
4581 void
4582 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4583 char *where;
4584 fixS *fixP;
4585 relax_addressT segment_address_in_file;
4586 {
4587 /*
4588 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4589 * Out: GNU LD relocation length code: 0, 1, or 2.
4590 */
4591
4592 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4593 long r_symbolnum;
4594
4595 know (fixP->fx_addsy != NULL);
4596
4597 md_number_to_chars (where,
4598 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4599 4);
4600
4601 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4602 ? S_GET_TYPE (fixP->fx_addsy)
4603 : fixP->fx_addsy->sy_number);
4604
4605 where[4] = (r_symbolnum >> 16) & 0x0ff;
4606 where[5] = (r_symbolnum >> 8) & 0x0ff;
4607 where[6] = r_symbolnum & 0x0ff;
4608 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4609 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4610 }
4611 #endif
4612
4613 #endif /* OBJ_AOUT or OBJ_BOUT */
4614
4615 #ifndef WORKING_DOT_WORD
4616 CONST int md_short_jump_size = 4;
4617 CONST int md_long_jump_size = 6;
4618
4619 void
4620 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4621 char *ptr;
4622 addressT from_addr, to_addr;
4623 fragS *frag;
4624 symbolS *to_symbol;
4625 {
4626 valueT offset;
4627
4628 offset = to_addr - (from_addr + 2);
4629
4630 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4631 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4632 }
4633
4634 void
4635 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4636 char *ptr;
4637 addressT from_addr, to_addr;
4638 fragS *frag;
4639 symbolS *to_symbol;
4640 {
4641 valueT offset;
4642
4643 if (cpu_of_arch (current_architecture) < m68020)
4644 {
4645 offset = to_addr - S_GET_VALUE (to_symbol);
4646 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4647 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4648 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4649 0, NO_RELOC);
4650 }
4651 else
4652 {
4653 offset = to_addr - (from_addr + 2);
4654 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4655 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4656 }
4657 }
4658
4659 #endif
4660 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
4661
4662 0: Everything is OK
4663 10: Absolute 1:8 only
4664 20: Absolute 0:7 only
4665 30: absolute 0:15 only
4666 40: Absolute 0:31 only
4667 50: absolute 0:127 only
4668 55: absolute -64:63 only
4669 60: absolute -128:127 only
4670 70: absolute 0:4095 only
4671 80: No bignums
4672
4673 */
4674
4675 static int
4676 get_num (exp, ok)
4677 struct m68k_exp *exp;
4678 int ok;
4679 {
4680 #ifdef TEST2
4681 long l = 0;
4682
4683 if (!exp->e_beg)
4684 return 0;
4685 if (*exp->e_beg == '0')
4686 {
4687 if (exp->e_beg[1] == 'x')
4688 sscanf (exp->e_beg + 2, "%x", &l);
4689 else
4690 sscanf (exp->e_beg + 1, "%O", &l);
4691 return l;
4692 }
4693 return atol (exp->e_beg);
4694 #else
4695 char *save_in;
4696 char c_save;
4697 segT section;
4698
4699 if (!exp)
4700 {
4701 /* Can't do anything */
4702 return 0;
4703 }
4704 if (!exp->e_beg || !exp->e_end)
4705 {
4706 seg (exp) = absolute_section;
4707 adds (exp) = 0;
4708 subs (exp) = 0;
4709 offs (exp) = (ok == 10) ? 1 : 0;
4710 as_warn ("Null expression defaults to %ld", offs (exp));
4711 return 0;
4712 }
4713
4714 exp->e_siz = 0;
4715 if ( /* ok!=80 && */ (exp->e_end[-1] == ':' || exp->e_end[-1] == '.')
4716 && (exp->e_end - exp->e_beg) >= 2)
4717 {
4718 switch (exp->e_end[0])
4719 {
4720 case 's':
4721 case 'S':
4722 case 'b':
4723 case 'B':
4724 exp->e_siz = 1;
4725 exp->e_end -= 2;
4726 break;
4727 case 'w':
4728 case 'W':
4729 exp->e_siz = 2;
4730 exp->e_end -= 2;
4731 break;
4732 case 'l':
4733 case 'L':
4734 exp->e_siz = 3;
4735 exp->e_end -= 2;
4736 break;
4737 default:
4738 if (exp->e_end[-1] == ':')
4739 as_bad ("Unknown size for expression \"%c\"", exp->e_end[0]);
4740 break;
4741 }
4742 }
4743 c_save = exp->e_end[1];
4744 exp->e_end[1] = '\0';
4745 save_in = input_line_pointer;
4746 input_line_pointer = exp->e_beg;
4747 section = expression (&exp->e_exp);
4748 seg (exp) = section;
4749 if (exp->e_exp.X_op == O_absent)
4750 {
4751 /* Do the same thing the VAX asm does */
4752 seg (exp) = absolute_section;
4753 op (exp) = O_constant;
4754 adds (exp) = 0;
4755 subs (exp) = 0;
4756 offs (exp) = 0;
4757 if (ok == 10)
4758 {
4759 as_warn ("expression out of range: defaulting to 1");
4760 offs (exp) = 1;
4761 }
4762 }
4763 else if (exp->e_exp.X_op == O_constant)
4764 {
4765 switch (ok)
4766 {
4767 case 10:
4768 if (offs (exp) < 1 || offs (exp) > 8)
4769 {
4770 as_warn ("expression out of range: defaulting to 1");
4771 offs (exp) = 1;
4772 }
4773 break;
4774 case 20:
4775 if (offs (exp) < 0 || offs (exp) > 7)
4776 goto outrange;
4777 break;
4778 case 30:
4779 if (offs (exp) < 0 || offs (exp) > 15)
4780 goto outrange;
4781 break;
4782 case 40:
4783 if (offs (exp) < 0 || offs (exp) > 32)
4784 goto outrange;
4785 break;
4786 case 50:
4787 if (offs (exp) < 0 || offs (exp) > 127)
4788 goto outrange;
4789 break;
4790 case 55:
4791 if (offs (exp) < -64 || offs (exp) > 63)
4792 goto outrange;
4793 break;
4794 case 60:
4795 if (offs (exp) < -128 || offs (exp) > 127)
4796 goto outrange;
4797 break;
4798 case 70:
4799 if (offs (exp) < 0 || offs (exp) > 4095)
4800 {
4801 outrange:
4802 as_warn ("expression out of range: defaulting to 0");
4803 offs (exp) = 0;
4804 }
4805 break;
4806 default:
4807 break;
4808 }
4809 }
4810 else if (exp->e_exp.X_op == O_big)
4811 {
4812 if (offs (exp) <= 0 /* flonum */
4813 && (ok == 80 /* no bignums */
4814 || (ok > 10 /* small-int ranges including 0 ok */
4815 /* If we have a flonum zero, a zero integer should
4816 do as well (e.g., in moveq). */
4817 && generic_floating_point_number.exponent == 0
4818 && generic_floating_point_number.low[0] == 0)))
4819 {
4820 /* HACK! Turn it into a long */
4821 LITTLENUM_TYPE words[6];
4822
4823 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4824 seg (exp) = absolute_section;
4825 op (exp) = O_constant;
4826 adds (exp) = 0;
4827 subs (exp) = 0;
4828 offs (exp) = words[1] | (words[0] << 16);
4829 }
4830 else if (ok != 0)
4831 {
4832 seg (exp) = absolute_section;
4833 op (exp) = O_constant;
4834 adds (exp) = 0;
4835 subs (exp) = 0;
4836 offs (exp) = (ok == 10) ? 1 : 0;
4837 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4838 }
4839 }
4840 else
4841 {
4842 if (ok >= 10 && ok <= 70)
4843 {
4844 seg (exp) = absolute_section;
4845 op (exp) = O_constant;
4846 adds (exp) = 0;
4847 subs (exp) = 0;
4848 offs (exp) = (ok == 10) ? 1 : 0;
4849 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4850 }
4851 }
4852
4853 if (input_line_pointer != exp->e_end + 1)
4854 as_bad ("Ignoring junk after expression");
4855 exp->e_end[1] = c_save;
4856 input_line_pointer = save_in;
4857 if (exp->e_siz)
4858 {
4859 switch (exp->e_siz)
4860 {
4861 case 1:
4862 if (!isbyte (offs (exp)))
4863 as_warn ("expression doesn't fit in BYTE");
4864 break;
4865 case 2:
4866 if (!isword (offs (exp)))
4867 as_warn ("expression doesn't fit in WORD");
4868 break;
4869 }
4870 }
4871 return offs (exp);
4872 #endif
4873 }
4874
4875 /* These are the back-ends for the various machine dependent pseudo-ops. */
4876 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4877
4878 static void
4879 s_data1 (ignore)
4880 int ignore;
4881 {
4882 subseg_set (data_section, 1);
4883 demand_empty_rest_of_line ();
4884 }
4885
4886 static void
4887 s_data2 (ignore)
4888 int ignore;
4889 {
4890 subseg_set (data_section, 2);
4891 demand_empty_rest_of_line ();
4892 }
4893
4894 static void
4895 s_bss (ignore)
4896 int ignore;
4897 {
4898 /* We don't support putting frags in the BSS segment, we fake it
4899 by marking in_bss, then looking at s_skip for clues. */
4900
4901 subseg_set (bss_section, 0);
4902 demand_empty_rest_of_line ();
4903 }
4904
4905 static void
4906 s_even (ignore)
4907 int ignore;
4908 {
4909 register int temp;
4910 register long temp_fill;
4911
4912 temp = 1; /* JF should be 2? */
4913 temp_fill = get_absolute_expression ();
4914 if (!need_pass_2) /* Never make frag if expect extra pass. */
4915 frag_align (temp, (int) temp_fill);
4916 demand_empty_rest_of_line ();
4917 }
4918
4919 static void
4920 s_proc (ignore)
4921 int ignore;
4922 {
4923 demand_empty_rest_of_line ();
4924 }
4925
4926 /* s_space is defined in read.c .skip is simply an alias to it. */
4927
4928 /*
4929 * md_parse_option
4930 * Invocation line includes a switch not recognized by the base assembler.
4931 * See if it's a processor-specific option. These are:
4932 *
4933 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4934 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4935 * Select the architecture. Instructions or features not
4936 * supported by the selected architecture cause fatal
4937 * errors. More than one may be specified. The default is
4938 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4939 * for -m68000, and -m68882 is a synonym for -m68881.
4940 * -[A]m[c]no-68851, -[A]m[c]no-68881
4941 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4942 * so don't use or document it, but that's the way the parsing
4943 * works).
4944 *
4945 * -pic Indicates PIC.
4946 * -k Indicates PIC. (Sun 3 only.)
4947 *
4948 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4949 * (e.g. m68020) also requests that float instructions be included. This
4950 * is the default setup, mostly to avoid hassling users. A better
4951 * rearrangement of this structure would be to add an option to DENY
4952 * floating point opcodes, for people who want to really know there's none
4953 * of that funny floaty stuff going on. FIXME-later.
4954 */
4955 #ifndef MAYBE_FLOAT_TOO
4956 #define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */
4957 #endif
4958
4959 int
4960 m68k_parse_long_option (opt)
4961 char *opt;
4962 {
4963 /* Skip over double-dash. */
4964 opt += 2;
4965 if (!strcmp (opt, "register-prefix-optional"))
4966 {
4967 flag_reg_prefix_optional = 1;
4968 return 1;
4969 }
4970 return 0;
4971 }
4972
4973 int
4974 md_parse_option (argP, cntP, vecP)
4975 char **argP;
4976 int *cntP;
4977 char ***vecP;
4978 {
4979 switch (**argP)
4980 {
4981 case 'l': /* -l means keep external to 2 bit offset
4982 rather than 16 bit one */
4983 break;
4984
4985 case 'S': /* -S means that jbsr's always turn into
4986 jsr's. */
4987 break;
4988
4989 case 'A':
4990 (*argP)++;
4991 /* intentional fall-through */
4992 case 'm':
4993 (*argP)++;
4994
4995 if (**argP == 'c')
4996 {
4997 (*argP)++;
4998 } /* allow an optional "c" */
4999
5000 if (!strcmp (*argP, "68000")
5001 || !strcmp (*argP, "68008")
5002 || !strcmp (*argP, "68302"))
5003 {
5004 current_architecture |= m68000;
5005 }
5006 else if (!strcmp (*argP, "68010"))
5007 {
5008 current_architecture |= m68010;
5009 }
5010 else if (!strcmp (*argP, "68020"))
5011 {
5012 current_architecture |= m68020 | MAYBE_FLOAT_TOO;
5013 }
5014 else if (!strcmp (*argP, "68030"))
5015 {
5016 current_architecture |= m68030 | MAYBE_FLOAT_TOO;
5017 }
5018 else if (!strcmp (*argP, "68040"))
5019 {
5020 current_architecture |= m68040 | MAYBE_FLOAT_TOO;
5021 }
5022 else if (!strcmp (*argP, "68060"))
5023 {
5024 current_architecture |= m68060 | MAYBE_FLOAT_TOO;
5025 }
5026 #ifndef NO_68881
5027 else if (!strcmp (*argP, "68881"))
5028 {
5029 current_architecture |= m68881;
5030 }
5031 else if (!strcmp (*argP, "68882"))
5032 {
5033 current_architecture |= m68882;
5034 }
5035 #endif /* NO_68881 */
5036 /* Even if we aren't configured to support the processor,
5037 it should still be possible to assert that the user
5038 doesn't have it... */
5039 else if (!strcmp (*argP, "no-68881")
5040 || !strcmp (*argP, "no-68882"))
5041 {
5042 no_68881 = 1;
5043 }
5044 #ifndef NO_68851
5045 else if (!strcmp (*argP, "68851"))
5046 {
5047 current_architecture |= m68851;
5048 }
5049 #endif /* NO_68851 */
5050 else if (!strcmp (*argP, "no-68851"))
5051 {
5052 no_68851 = 1;
5053 }
5054 else if (!strcmp (*argP, "pu32") /* "cpu32" minus 'c' */
5055 || !strcmp (*argP, "68331")
5056 || !strcmp (*argP, "68332")
5057 || !strcmp (*argP, "68333")
5058 || !strcmp (*argP, "68340"))
5059 {
5060 current_architecture |= cpu32;
5061 }
5062 else
5063 {
5064 as_warn ("Unknown architecture, \"%s\". option ignored", *argP);
5065 } /* switch on architecture */
5066
5067 while (**argP)
5068 (*argP)++;
5069
5070 break;
5071
5072 case 'p':
5073 if (!strcmp (*argP, "pic"))
5074 {
5075 *argP += 3;
5076 flag_want_pic = 1;
5077 break; /* -pic, Position Independent Code */
5078 }
5079 else
5080 goto bad_arg;
5081
5082 #ifdef TE_SUN3
5083 case 'k':
5084 flag_want_pic = 1;
5085 break;
5086 #endif
5087
5088 default:
5089 bad_arg:
5090 return 0;
5091 }
5092 return 1;
5093 }
5094
5095
5096 #ifdef TEST2
5097
5098 /* TEST2: Test md_assemble() */
5099 /* Warning, this routine probably doesn't work anymore */
5100
5101 main ()
5102 {
5103 struct m68k_it the_ins;
5104 char buf[120];
5105 char *cp;
5106 int n;
5107
5108 m68k_ip_begin ();
5109 for (;;)
5110 {
5111 if (!gets (buf) || !*buf)
5112 break;
5113 if (buf[0] == '|' || buf[1] == '.')
5114 continue;
5115 for (cp = buf; *cp; cp++)
5116 if (*cp == '\t')
5117 *cp = ' ';
5118 if (is_label (buf))
5119 continue;
5120 memset (&the_ins, '\0', sizeof (the_ins));
5121 m68k_ip (&the_ins, buf);
5122 if (the_ins.error)
5123 {
5124 printf ("Error %s in %s\n", the_ins.error, buf);
5125 }
5126 else
5127 {
5128 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
5129 for (n = 0; n < the_ins.numo; n++)
5130 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
5131 printf (" ");
5132 print_the_insn (&the_ins.opcode[0], stdout);
5133 (void) putchar ('\n');
5134 }
5135 for (n = 0; n < strlen (the_ins.args) / 2; n++)
5136 {
5137 if (the_ins.operands[n].error)
5138 {
5139 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
5140 continue;
5141 }
5142 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
5143 if (the_ins.operands[n].b_const)
5144 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
5145 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
5146 if (the_ins.operands[n].b_iadd)
5147 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
5148 (void) putchar ('\n');
5149 }
5150 }
5151 m68k_ip_end ();
5152 return 0;
5153 }
5154
5155 is_label (str)
5156 char *str;
5157 {
5158 while (*str == ' ')
5159 str++;
5160 while (*str && *str != ' ')
5161 str++;
5162 if (str[-1] == ':' || str[1] == '=')
5163 return 1;
5164 return 0;
5165 }
5166
5167 #endif
5168
5169 /* Possible states for relaxation:
5170
5171 0 0 branch offset byte (bra, etc)
5172 0 1 word
5173 0 2 long
5174
5175 1 0 indexed offsets byte a0@(32,d4:w:1) etc
5176 1 1 word
5177 1 2 long
5178
5179 2 0 two-offset index word-word a0@(32,d4)@(45) etc
5180 2 1 word-long
5181 2 2 long-word
5182 2 3 long-long
5183
5184 */
5185
5186 /* We have no need to default values of symbols. */
5187
5188 /* ARGSUSED */
5189 symbolS *
5190 md_undefined_symbol (name)
5191 char *name;
5192 {
5193 return 0;
5194 }
5195
5196 /* Parse an operand that is machine-specific.
5197 We just return without modifying the expression if we have nothing
5198 to do. */
5199
5200 /* ARGSUSED */
5201 void
5202 md_operand (expressionP)
5203 expressionS *expressionP;
5204 {
5205 }
5206
5207 /* Round up a section size to the appropriate boundary. */
5208 valueT
5209 md_section_align (segment, size)
5210 segT segment;
5211 valueT size;
5212 {
5213 return size; /* Byte alignment is fine */
5214 }
5215
5216 /* Exactly what point is a PC-relative offset relative TO?
5217 On the 68k, they're relative to the address of the offset, plus
5218 its size. (??? Is this right? FIXME-SOON!) */
5219 long
5220 md_pcrel_from (fixP)
5221 fixS *fixP;
5222 {
5223 return (fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address);
5224 }
5225
5226 #ifndef BFD_ASSEMBLER
5227 void
5228 tc_coff_symbol_emit_hook ()
5229 {
5230 }
5231
5232 int
5233 tc_coff_sizemachdep (frag)
5234 fragS *frag;
5235 {
5236 switch (frag->fr_subtype & 0x3)
5237 {
5238 case BYTE:
5239 return 1;
5240 case SHORT:
5241 return 2;
5242 case LONG:
5243 return 4;
5244 default:
5245 abort ();
5246 }
5247 }
5248 #endif
5249
5250 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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