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* config/tc-m68k.c (m68k_ip): Accept 'B' as a size for an
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 #include <ctype.h>
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if (defined (OBJ_ELF) && ! defined (TE_PSOS) && ! defined (TE_LINUX)) || defined (TE_DELTA)
35 const char *m68k_comment_chars = "|#";
36 #else
37 const char *m68k_comment_chars = "|";
38 #endif
39
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars[] = "#";
48
49 const char line_separator_chars[] = "";
50
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST char EXP_CHARS[] = "eE";
53
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
56
57 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
58
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
62
63 const int md_reloc_size = 8; /* Size of relocation record */
64
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
69 int flag_want_pic;
70
71 static int flag_short_refs; /* -l option */
72 static int flag_long_jumps; /* -S option */
73
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
76 #else
77 int flag_reg_prefix_optional;
78 #endif
79
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen;
82
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum = COP1;
85
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd;
89
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick = 1;
93
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
96 be 32 bits. */
97 static int m68k_rel32 = 1;
98
99 /* This is non-zero if m68k_rel32 was set from the command line. */
100 static int m68k_rel32_from_cmdline;
101
102 /* The default width to use for an index register when using a base
103 displacement. */
104 static enum m68k_size m68k_index_width_default = SIZE_LONG;
105
106 /* Its an arbitrary name: This means I don't approve of it */
107 /* See flames below */
108 static struct obstack robyn;
109
110 #define TAB(x,y) (((x)<<2)+(y))
111 #define TABTYPE(xy) ((xy) >> 2)
112 #define BYTE 0
113 #define SHORT 1
114 #define LONG 2
115 #define SZ_UNDEF 3
116 #undef BRANCH
117 /* Case `g' except when BCC68000 is applicable. */
118 #define ABRANCH 1
119 /* Coprocessor branches. */
120 #define FBRANCH 2
121 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
122 supported on all cpus. Widens to 32-bit absolute. */
123 #define PCREL 3
124 /* For inserting an extra jmp instruction with long offset on 68000,
125 for expanding conditional branches. (Not bsr or bra.) Since the
126 68000 doesn't support 32-bit displacements for conditional
127 branches, we fake it by reversing the condition and branching
128 around a jmp with an absolute long operand. */
129 #define BCC68000 4
130 /* For the DBcc "instructions". If the displacement requires 32 bits,
131 the branch-around-a-jump game is played here too. */
132 #define DBCC 5
133 /* Not currently used? */
134 #define PCLEA 6
135 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
136 in 16 or 8 bits. */
137 #define PCINDEX 7
138
139 struct m68k_incant
140 {
141 const char *m_operands;
142 unsigned long m_opcode;
143 short m_opnum;
144 short m_codenum;
145 int m_arch;
146 struct m68k_incant *m_next;
147 };
148
149 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
150 #define gettwo(x) (((x)->m_opcode)&0xffff)
151
152 static const enum m68k_register m68000_control_regs[] = { 0 };
153 static const enum m68k_register m68010_control_regs[] = {
154 SFC, DFC, USP, VBR,
155 0
156 };
157 static const enum m68k_register m68020_control_regs[] = {
158 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
159 0
160 };
161 static const enum m68k_register m68040_control_regs[] = {
162 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
163 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
164 0
165 };
166 static const enum m68k_register m68060_control_regs[] = {
167 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
168 USP, VBR, URP, SRP, PCR,
169 0
170 };
171 static const enum m68k_register mcf5200_control_regs[] = {
172 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
173 RAMBAR0, RAMBAR1, MBAR,
174 0
175 };
176 #define cpu32_control_regs m68010_control_regs
177
178 static const enum m68k_register *control_regs;
179
180 /* internal form of a 68020 instruction */
181 struct m68k_it
182 {
183 const char *error;
184 const char *args; /* list of opcode info */
185 int numargs;
186
187 int numo; /* Number of shorts in opcode */
188 short opcode[11];
189
190 struct m68k_op operands[6];
191
192 int nexp; /* number of exprs in use */
193 struct m68k_exp exprs[4];
194
195 int nfrag; /* Number of frags we have to produce */
196 struct
197 {
198 int fragoff; /* Where in the current opcode the frag ends */
199 symbolS *fadd;
200 long foff;
201 int fragty;
202 }
203 fragb[4];
204
205 int nrel; /* Num of reloc strucs in use */
206 struct
207 {
208 int n;
209 expressionS exp;
210 char wid;
211 char pcrel;
212 /* In a pc relative address the difference between the address
213 of the offset and the address that the offset is relative
214 to. This depends on the addressing mode. Basically this
215 is the value to put in the offset field to address the
216 first byte of the offset, without regarding the special
217 significance of some values (in the branch instruction, for
218 example). */
219 int pcrel_fix;
220 #ifdef OBJ_ELF
221 /* Whether this expression needs special pic relocation, and if
222 so, which. */
223 enum pic_relocation pic_reloc;
224 #endif
225 }
226 reloc[5]; /* Five is enough??? */
227 };
228
229 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
230 #define float_of_arch(x) ((x) & mfloat)
231 #define mmu_of_arch(x) ((x) & mmmu)
232
233 static struct m68k_it the_ins; /* the instruction being assembled */
234
235 #define op(ex) ((ex)->exp.X_op)
236 #define adds(ex) ((ex)->exp.X_add_symbol)
237 #define subs(ex) ((ex)->exp.X_op_symbol)
238 #define offs(ex) ((ex)->exp.X_add_number)
239
240 /* Macros for adding things to the m68k_it struct */
241
242 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
243
244 /* Like addword, but goes BEFORE general operands */
245 static void
246 insop (w, opcode)
247 int w;
248 struct m68k_incant *opcode;
249 {
250 int z;
251 for(z=the_ins.numo;z>opcode->m_codenum;--z)
252 the_ins.opcode[z]=the_ins.opcode[z-1];
253 for(z=0;z<the_ins.nrel;z++)
254 the_ins.reloc[z].n+=2;
255 for (z = 0; z < the_ins.nfrag; z++)
256 the_ins.fragb[z].fragoff++;
257 the_ins.opcode[opcode->m_codenum]=w;
258 the_ins.numo++;
259 }
260
261 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
262 Blecch. */
263 static void
264 add_fix (width, exp, pc_rel, pc_fix)
265 char width;
266 struct m68k_exp *exp;
267 int pc_rel;
268 int pc_fix;
269 {
270 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
271 ? (the_ins.numo*2-1)
272 : (((width)=='b')
273 ? (the_ins.numo*2+1)
274 : (the_ins.numo*2)));
275 the_ins.reloc[the_ins.nrel].exp = exp->exp;
276 the_ins.reloc[the_ins.nrel].wid = width;
277 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
278 #ifdef OBJ_ELF
279 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
280 #endif
281 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
282 }
283
284 /* Cause an extra frag to be generated here, inserting up to 10 bytes
285 (that value is chosen in the frag_var call in md_assemble). TYPE
286 is the subtype of the frag to be generated; its primary type is
287 rs_machine_dependent.
288
289 The TYPE parameter is also used by md_convert_frag_1 and
290 md_estimate_size_before_relax. The appropriate type of fixup will
291 be emitted by md_convert_frag_1.
292
293 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
294 static void
295 add_frag(add,off,type)
296 symbolS *add;
297 long off;
298 int type;
299 {
300 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
301 the_ins.fragb[the_ins.nfrag].fadd=add;
302 the_ins.fragb[the_ins.nfrag].foff=off;
303 the_ins.fragb[the_ins.nfrag++].fragty=type;
304 }
305
306 #define isvar(ex) \
307 (op (ex) != O_constant && op (ex) != O_big)
308
309 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
310 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
311 static int reverse_16_bits PARAMS ((int in));
312 static int reverse_8_bits PARAMS ((int in));
313 static void install_gen_operand PARAMS ((int mode, int val));
314 static void install_operand PARAMS ((int mode, int val));
315 static void s_bss PARAMS ((int));
316 static void s_data1 PARAMS ((int));
317 static void s_data2 PARAMS ((int));
318 static void s_even PARAMS ((int));
319 static void s_proc PARAMS ((int));
320 static void mri_chip PARAMS ((void));
321 static void s_chip PARAMS ((int));
322 static void s_fopt PARAMS ((int));
323 static void s_opt PARAMS ((int));
324 static void s_reg PARAMS ((int));
325 static void s_restore PARAMS ((int));
326 static void s_save PARAMS ((int));
327 static void s_mri_if PARAMS ((int));
328 static void s_mri_else PARAMS ((int));
329 static void s_mri_endi PARAMS ((int));
330 static void s_mri_break PARAMS ((int));
331 static void s_mri_next PARAMS ((int));
332 static void s_mri_for PARAMS ((int));
333 static void s_mri_endf PARAMS ((int));
334 static void s_mri_repeat PARAMS ((int));
335 static void s_mri_until PARAMS ((int));
336 static void s_mri_while PARAMS ((int));
337 static void s_mri_endw PARAMS ((int));
338
339 static int current_architecture;
340
341 struct m68k_cpu {
342 unsigned long arch;
343 const char *name;
344 int alias;
345 };
346
347 static const struct m68k_cpu archs[] = {
348 { m68000, "68000", 0 },
349 { m68010, "68010", 0 },
350 { m68020, "68020", 0 },
351 { m68030, "68030", 0 },
352 { m68040, "68040", 0 },
353 { m68060, "68060", 0 },
354 { cpu32, "cpu32", 0 },
355 { m68881, "68881", 0 },
356 { m68851, "68851", 0 },
357 { mcf5200, "5200", 0 },
358 /* Aliases (effectively, so far as gas is concerned) for the above
359 cpus. */
360 { m68020, "68k", 1 },
361 { m68000, "68302", 1 },
362 { m68000, "68008", 1 },
363 { m68000, "68ec000", 1 },
364 { m68000, "68hc000", 1 },
365 { m68000, "68hc001", 1 },
366 { m68020, "68ec020", 1 },
367 { m68030, "68ec030", 1 },
368 { m68040, "68ec040", 1 },
369 { m68060, "68ec060", 1 },
370 { cpu32, "68330", 1 },
371 { cpu32, "68331", 1 },
372 { cpu32, "68332", 1 },
373 { cpu32, "68333", 1 },
374 { cpu32, "68340", 1 },
375 { cpu32, "68360", 1 },
376 { m68881, "68882", 1 },
377 };
378
379 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
380
381 /* BCC68000 is for patching in an extra jmp instruction for long offsets
382 on the 68000. The 68000 doesn't support long branches with branchs */
383
384 /* This table desribes how you change sizes for the various types of variable
385 size expressions. This version only supports two kinds. */
386
387 /* Note that calls to frag_var need to specify the maximum expansion
388 needed; this is currently 10 bytes for DBCC. */
389
390 /* The fields are:
391 How far Forward this mode will reach:
392 How far Backward this mode will reach:
393 How many bytes this mode will add to the size of the frag
394 Which mode to go to if the offset won't fit in this one
395 */
396 relax_typeS md_relax_table[] =
397 {
398 {1, 1, 0, 0}, /* First entries aren't used */
399 {1, 1, 0, 0}, /* For no good reason except */
400 {1, 1, 0, 0}, /* that the VAX doesn't either */
401 {1, 1, 0, 0},
402
403 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
404 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
405 {0, 0, 4, 0},
406 {1, 1, 0, 0},
407
408 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
409 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
410 {0, 0, 4, 0},
411 {1, 1, 0, 0},
412
413 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
414 {(32767), (-32768), 2, TAB (PCREL, LONG)},
415 {0, 0, 4, 0},
416 {1, 1, 0, 0},
417
418 {(127), (-128), 0, TAB (BCC68000, SHORT)},
419 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
420 {0, 0, 6, 0}, /* jmp long space */
421 {1, 1, 0, 0},
422
423 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
424 {(32767), (-32768), 2, TAB (DBCC, LONG)},
425 {0, 0, 10, 0}, /* bra/jmp long space */
426 {1, 1, 0, 0},
427
428 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
429 {32767, -32768, 2, TAB (PCLEA, LONG)},
430 {0, 0, 6, 0},
431 {1, 1, 0, 0},
432
433 /* For, e.g., jmp pcrel indexed. */
434 {125, -130, 0, TAB (PCINDEX, SHORT)},
435 {32765, -32770, 2, TAB (PCINDEX, LONG)},
436 {0, 0, 4, 0},
437 {1, 1, 0, 0},
438 };
439
440 /* These are the machine dependent pseudo-ops. These are included so
441 the assembler can work on the output from the SUN C compiler, which
442 generates these.
443 */
444
445 /* This table describes all the machine specific pseudo-ops the assembler
446 has to support. The fields are:
447 pseudo-op name without dot
448 function to call to execute this pseudo-op
449 Integer arg to pass to the function
450 */
451 const pseudo_typeS md_pseudo_table[] =
452 {
453 {"data1", s_data1, 0},
454 {"data2", s_data2, 0},
455 {"bss", s_bss, 0},
456 {"even", s_even, 0},
457 {"skip", s_space, 0},
458 {"proc", s_proc, 0},
459 #if defined (TE_SUN3) || defined (OBJ_ELF)
460 {"align", s_align_bytes, 0},
461 #endif
462 #ifdef OBJ_ELF
463 {"swbeg", s_ignore, 0},
464 #endif
465 {"extend", float_cons, 'x'},
466 {"ldouble", float_cons, 'x'},
467
468 /* The following pseudo-ops are supported for MRI compatibility. */
469 {"chip", s_chip, 0},
470 {"comline", s_space, 1},
471 {"fopt", s_fopt, 0},
472 {"mask2", s_ignore, 0},
473 {"opt", s_opt, 0},
474 {"reg", s_reg, 0},
475 {"restore", s_restore, 0},
476 {"save", s_save, 0},
477
478 {"if", s_mri_if, 0},
479 {"if.b", s_mri_if, 'b'},
480 {"if.w", s_mri_if, 'w'},
481 {"if.l", s_mri_if, 'l'},
482 {"else", s_mri_else, 0},
483 {"else.s", s_mri_else, 's'},
484 {"else.l", s_mri_else, 'l'},
485 {"endi", s_mri_endi, 0},
486 {"break", s_mri_break, 0},
487 {"break.s", s_mri_break, 's'},
488 {"break.l", s_mri_break, 'l'},
489 {"next", s_mri_next, 0},
490 {"next.s", s_mri_next, 's'},
491 {"next.l", s_mri_next, 'l'},
492 {"for", s_mri_for, 0},
493 {"for.b", s_mri_for, 'b'},
494 {"for.w", s_mri_for, 'w'},
495 {"for.l", s_mri_for, 'l'},
496 {"endf", s_mri_endf, 0},
497 {"repeat", s_mri_repeat, 0},
498 {"until", s_mri_until, 0},
499 {"until.b", s_mri_until, 'b'},
500 {"until.w", s_mri_until, 'w'},
501 {"until.l", s_mri_until, 'l'},
502 {"while", s_mri_while, 0},
503 {"while.b", s_mri_while, 'b'},
504 {"while.w", s_mri_while, 'w'},
505 {"while.l", s_mri_while, 'l'},
506 {"endw", s_mri_endw, 0},
507
508 {0, 0, 0}
509 };
510
511
512 /* The mote pseudo ops are put into the opcode table, since they
513 don't start with a . they look like opcodes to gas.
514 */
515 extern void obj_coff_section ();
516
517 CONST pseudo_typeS mote_pseudo_table[] =
518 {
519
520 {"dcl", cons, 4},
521 {"dc", cons, 2},
522 {"dcw", cons, 2},
523 {"dcb", cons, 1},
524
525 {"dsl", s_space, 4},
526 {"ds", s_space, 2},
527 {"dsw", s_space, 2},
528 {"dsb", s_space, 1},
529
530 {"xdef", s_globl, 0},
531 #ifdef OBJ_ELF
532 {"align", s_align_bytes, 0},
533 #else
534 {"align", s_align_ptwo, 0},
535 #endif
536 #ifdef M68KCOFF
537 {"sect", obj_coff_section, 0},
538 {"section", obj_coff_section, 0},
539 #endif
540 {0, 0, 0}
541 };
542
543 #define issbyte(x) ((x)>=-128 && (x)<=127)
544 #define isubyte(x) ((x)>=0 && (x)<=255)
545 #define issword(x) ((x)>=-32768 && (x)<=32767)
546 #define isuword(x) ((x)>=0 && (x)<=65535)
547
548 #define isbyte(x) ((x)>= -255 && (x)<=255)
549 #define isword(x) ((x)>=-65536 && (x)<=65535)
550 #define islong(x) (1)
551
552 extern char *input_line_pointer;
553
554 static char mklower_table[256];
555 #define mklower(c) (mklower_table[(unsigned char)(c)])
556 static char notend_table[256];
557 static char alt_notend_table[256];
558 #define notend(s) \
559 (! (notend_table[(unsigned char) *s] \
560 || (*s == ':' \
561 && alt_notend_table[(unsigned char) s[1]])))
562
563 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
564
565 #ifdef NO_PCREL_RELOCS
566
567 int
568 make_pcrel_absolute(fixP, add_number)
569 fixS *fixP;
570 long *add_number;
571 {
572 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
573
574 /* rewrite the PC relative instructions to absolute address ones.
575 * these are rumoured to be faster, and the apollo linker refuses
576 * to deal with the PC relative relocations.
577 */
578 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
579 {
580 opcode[0] = 0x4e;
581 opcode[1] = 0xf9;
582 }
583 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
584 {
585 opcode[0] = 0x4e;
586 opcode[1] = 0xb9;
587 }
588 else
589 as_fatal ("Unknown PC relative instruction");
590 *add_number -= 4;
591 return 0;
592 }
593
594 #endif /* NO_PCREL_RELOCS */
595
596 short
597 tc_coff_fix2rtype (fixP)
598 fixS *fixP;
599 {
600 if (fixP->fx_tcbit && fixP->fx_size == 4)
601 return R_RELLONG_NEG;
602 #ifdef NO_PCREL_RELOCS
603 know (fixP->fx_pcrel == 0);
604 return (fixP->fx_size == 1 ? R_RELBYTE
605 : fixP->fx_size == 2 ? R_DIR16
606 : R_DIR32);
607 #else
608 return (fixP->fx_pcrel ?
609 (fixP->fx_size == 1 ? R_PCRBYTE :
610 fixP->fx_size == 2 ? R_PCRWORD :
611 R_PCRLONG) :
612 (fixP->fx_size == 1 ? R_RELBYTE :
613 fixP->fx_size == 2 ? R_RELWORD :
614 R_RELLONG));
615 #endif
616 }
617
618 #endif
619
620 #ifdef OBJ_ELF
621
622 /* Compute the relocation code for a fixup of SIZE bytes, using pc
623 relative relocation if PCREL is non-zero. PIC says whether a special
624 pic relocation was requested. */
625
626 static bfd_reloc_code_real_type get_reloc_code
627 PARAMS ((int, int, enum pic_relocation));
628
629 static bfd_reloc_code_real_type
630 get_reloc_code (size, pcrel, pic)
631 int size;
632 int pcrel;
633 enum pic_relocation pic;
634 {
635 switch (pic)
636 {
637 case pic_got_pcrel:
638 switch (size)
639 {
640 case 1:
641 return BFD_RELOC_8_GOT_PCREL;
642 case 2:
643 return BFD_RELOC_16_GOT_PCREL;
644 case 4:
645 return BFD_RELOC_32_GOT_PCREL;
646 }
647 break;
648
649 case pic_got_off:
650 switch (size)
651 {
652 case 1:
653 return BFD_RELOC_8_GOTOFF;
654 case 2:
655 return BFD_RELOC_16_GOTOFF;
656 case 4:
657 return BFD_RELOC_32_GOTOFF;
658 }
659 break;
660
661 case pic_plt_pcrel:
662 switch (size)
663 {
664 case 1:
665 return BFD_RELOC_8_PLT_PCREL;
666 case 2:
667 return BFD_RELOC_16_PLT_PCREL;
668 case 4:
669 return BFD_RELOC_32_PLT_PCREL;
670 }
671 break;
672
673 case pic_plt_off:
674 switch (size)
675 {
676 case 1:
677 return BFD_RELOC_8_PLTOFF;
678 case 2:
679 return BFD_RELOC_16_PLTOFF;
680 case 4:
681 return BFD_RELOC_32_PLTOFF;
682 }
683 break;
684
685 case pic_none:
686 if (pcrel)
687 {
688 switch (size)
689 {
690 case 1:
691 return BFD_RELOC_8_PCREL;
692 case 2:
693 return BFD_RELOC_16_PCREL;
694 case 4:
695 return BFD_RELOC_32_PCREL;
696 }
697 }
698 else
699 {
700 switch (size)
701 {
702 case 1:
703 return BFD_RELOC_8;
704 case 2:
705 return BFD_RELOC_16;
706 case 4:
707 return BFD_RELOC_32;
708 }
709 }
710 }
711
712 as_bad ("Can not do %d byte %s%srelocation", size,
713 pcrel ? "pc-relative " : "",
714 pic == pic_none ? "" : "pic ");
715 return BFD_RELOC_NONE;
716 }
717
718 /* Here we decide which fixups can be adjusted to make them relative
719 to the beginning of the section instead of the symbol. Basically
720 we need to make sure that the dynamic relocations are done
721 correctly, so in some cases we force the original symbol to be
722 used. */
723 int
724 tc_m68k_fix_adjustable (fixP)
725 fixS *fixP;
726 {
727 /* Prevent all adjustments to global symbols. */
728 if (S_IS_EXTERNAL (fixP->fx_addsy))
729 return 0;
730
731 /* adjust_reloc_syms doesn't know about the GOT */
732 switch (fixP->fx_r_type)
733 {
734 case BFD_RELOC_8_GOT_PCREL:
735 case BFD_RELOC_16_GOT_PCREL:
736 case BFD_RELOC_32_GOT_PCREL:
737 case BFD_RELOC_8_GOTOFF:
738 case BFD_RELOC_16_GOTOFF:
739 case BFD_RELOC_32_GOTOFF:
740 case BFD_RELOC_8_PLT_PCREL:
741 case BFD_RELOC_16_PLT_PCREL:
742 case BFD_RELOC_32_PLT_PCREL:
743 case BFD_RELOC_8_PLTOFF:
744 case BFD_RELOC_16_PLTOFF:
745 case BFD_RELOC_32_PLTOFF:
746 return 0;
747
748 default:
749 return 1;
750 }
751 }
752
753 #else /* !OBJ_ELF */
754
755 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
756
757 #endif /* OBJ_ELF */
758
759 #ifdef BFD_ASSEMBLER
760
761 arelent *
762 tc_gen_reloc (section, fixp)
763 asection *section;
764 fixS *fixp;
765 {
766 arelent *reloc;
767 bfd_reloc_code_real_type code;
768
769 if (fixp->fx_tcbit)
770 abort ();
771
772 if (fixp->fx_r_type != BFD_RELOC_NONE)
773 {
774 code = fixp->fx_r_type;
775
776 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
777 that fixup_segment converted a non-PC relative reloc into a
778 PC relative reloc. In such a case, we need to convert the
779 reloc code. */
780 if (fixp->fx_pcrel)
781 {
782 switch (code)
783 {
784 case BFD_RELOC_8:
785 code = BFD_RELOC_8_PCREL;
786 break;
787 case BFD_RELOC_16:
788 code = BFD_RELOC_16_PCREL;
789 break;
790 case BFD_RELOC_32:
791 code = BFD_RELOC_32_PCREL;
792 break;
793 case BFD_RELOC_8_PCREL:
794 case BFD_RELOC_16_PCREL:
795 case BFD_RELOC_32_PCREL:
796 case BFD_RELOC_8_GOT_PCREL:
797 case BFD_RELOC_16_GOT_PCREL:
798 case BFD_RELOC_32_GOT_PCREL:
799 case BFD_RELOC_8_GOTOFF:
800 case BFD_RELOC_16_GOTOFF:
801 case BFD_RELOC_32_GOTOFF:
802 case BFD_RELOC_8_PLT_PCREL:
803 case BFD_RELOC_16_PLT_PCREL:
804 case BFD_RELOC_32_PLT_PCREL:
805 case BFD_RELOC_8_PLTOFF:
806 case BFD_RELOC_16_PLTOFF:
807 case BFD_RELOC_32_PLTOFF:
808 break;
809 default:
810 as_bad_where (fixp->fx_file, fixp->fx_line,
811 "Cannot make %s relocation PC relative",
812 bfd_get_reloc_code_name (code));
813 }
814 }
815 }
816 else
817 {
818 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
819 switch (F (fixp->fx_size, fixp->fx_pcrel))
820 {
821 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
822 MAP (1, 0, BFD_RELOC_8);
823 MAP (2, 0, BFD_RELOC_16);
824 MAP (4, 0, BFD_RELOC_32);
825 MAP (1, 1, BFD_RELOC_8_PCREL);
826 MAP (2, 1, BFD_RELOC_16_PCREL);
827 MAP (4, 1, BFD_RELOC_32_PCREL);
828 default:
829 abort ();
830 }
831 }
832 #undef F
833 #undef MAP
834
835 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
836 assert (reloc != 0);
837 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
838 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
839 #ifndef OBJ_ELF
840 if (fixp->fx_pcrel)
841 reloc->addend = fixp->fx_addnumber;
842 else
843 reloc->addend = 0;
844 #else
845 if (!fixp->fx_pcrel)
846 reloc->addend = fixp->fx_addnumber;
847 else
848 reloc->addend = (section->vma
849 + (fixp->fx_pcrel_adjust == 64
850 ? -1 : fixp->fx_pcrel_adjust)
851 + fixp->fx_addnumber
852 + md_pcrel_from (fixp));
853 #endif
854
855 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
856 assert (reloc->howto != 0);
857
858 return reloc;
859 }
860
861 #endif /* BFD_ASSEMBLER */
862
863 /* Handle of the OPCODE hash table. NULL means any use before
864 m68k_ip_begin() will crash. */
865 static struct hash_control *op_hash;
866 \f
867 /* Assemble an m68k instruction. */
868
869 void
870 m68k_ip (instring)
871 char *instring;
872 {
873 register char *p;
874 register struct m68k_op *opP;
875 register struct m68k_incant *opcode;
876 register const char *s;
877 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
878 char *pdot, *pdotmove;
879 enum m68k_size siz1, siz2;
880 char c;
881 int losing;
882 int opsfound;
883 char *crack_operand ();
884 LITTLENUM_TYPE words[6];
885 LITTLENUM_TYPE *wordp;
886 unsigned long ok_arch = 0;
887
888 if (*instring == ' ')
889 instring++; /* skip leading whitespace */
890
891 /* Scan up to end of operation-code, which MUST end in end-of-string
892 or exactly 1 space. */
893 pdot = 0;
894 for (p = instring; *p != '\0'; p++)
895 {
896 if (*p == ' ')
897 break;
898 if (*p == '.')
899 pdot = p;
900 }
901
902 if (p == instring)
903 {
904 the_ins.error = "No operator";
905 return;
906 }
907
908 /* p now points to the end of the opcode name, probably whitespace.
909 Make sure the name is null terminated by clobbering the
910 whitespace, look it up in the hash table, then fix it back.
911 Remove a dot, first, since the opcode tables have none. */
912 if (pdot != NULL)
913 {
914 for (pdotmove = pdot; pdotmove < p; pdotmove++)
915 *pdotmove = pdotmove[1];
916 p--;
917 }
918
919 c = *p;
920 *p = '\0';
921 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
922 *p = c;
923
924 if (pdot != NULL)
925 {
926 for (pdotmove = p; pdotmove > pdot; pdotmove--)
927 *pdotmove = pdotmove[-1];
928 *pdot = '.';
929 ++p;
930 }
931
932 if (opcode == NULL)
933 {
934 the_ins.error = "Unknown operator";
935 return;
936 }
937
938 /* found a legitimate opcode, start matching operands */
939 while (*p == ' ')
940 ++p;
941
942 if (opcode->m_operands == 0)
943 {
944 char *old = input_line_pointer;
945 *old = '\n';
946 input_line_pointer = p;
947 /* Ahh - it's a motorola style psuedo op */
948 mote_pseudo_table[opcode->m_opnum].poc_handler
949 (mote_pseudo_table[opcode->m_opnum].poc_val);
950 input_line_pointer = old;
951 *old = 0;
952
953 return;
954 }
955
956 if (flag_mri && opcode->m_opnum == 0)
957 {
958 /* In MRI mode, random garbage is allowed after an instruction
959 which accepts no operands. */
960 the_ins.args = opcode->m_operands;
961 the_ins.numargs = opcode->m_opnum;
962 the_ins.numo = opcode->m_codenum;
963 the_ins.opcode[0] = getone (opcode);
964 the_ins.opcode[1] = gettwo (opcode);
965 return;
966 }
967
968 for (opP = &the_ins.operands[0]; *p; opP++)
969 {
970 p = crack_operand (p, opP);
971
972 if (opP->error)
973 {
974 the_ins.error = opP->error;
975 return;
976 }
977 }
978
979 opsfound = opP - &the_ins.operands[0];
980
981 /* This ugly hack is to support the floating pt opcodes in their
982 standard form. Essentially, we fake a first enty of type COP#1 */
983 if (opcode->m_operands[0] == 'I')
984 {
985 int n;
986
987 for (n = opsfound; n > 0; --n)
988 the_ins.operands[n] = the_ins.operands[n - 1];
989
990 memset ((char *) (&the_ins.operands[0]), '\0',
991 sizeof (the_ins.operands[0]));
992 the_ins.operands[0].mode = CONTROL;
993 the_ins.operands[0].reg = m68k_float_copnum;
994 opsfound++;
995 }
996
997 /* We've got the operands. Find an opcode that'll accept them */
998 for (losing = 0;;)
999 {
1000 /* If we didn't get the right number of ops, or we have no
1001 common model with this pattern then reject this pattern. */
1002
1003 ok_arch |= opcode->m_arch;
1004 if (opsfound != opcode->m_opnum
1005 || ((opcode->m_arch & current_architecture) == 0))
1006 ++losing;
1007 else
1008 {
1009 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1010 *s && !losing;
1011 s += 2, opP++)
1012 {
1013 /* Warning: this switch is huge! */
1014 /* I've tried to organize the cases into this order:
1015 non-alpha first, then alpha by letter. Lower-case
1016 goes directly before uppercase counterpart. */
1017 /* Code with multiple case ...: gets sorted by the lowest
1018 case ... it belongs to. I hope this makes sense. */
1019 switch (*s)
1020 {
1021 case '!':
1022 switch (opP->mode)
1023 {
1024 case IMMED:
1025 case DREG:
1026 case AREG:
1027 case FPREG:
1028 case CONTROL:
1029 case AINC:
1030 case ADEC:
1031 case REGLST:
1032 losing++;
1033 break;
1034 default:
1035 break;
1036 }
1037 break;
1038
1039 case '`':
1040 switch (opP->mode)
1041 {
1042 case IMMED:
1043 case DREG:
1044 case AREG:
1045 case FPREG:
1046 case CONTROL:
1047 case AINC:
1048 case REGLST:
1049 case AINDR:
1050 losing++;
1051 break;
1052 default:
1053 break;
1054 }
1055 break;
1056
1057 case '<':
1058 switch (opP->mode)
1059 {
1060 case DREG:
1061 case AREG:
1062 case FPREG:
1063 case CONTROL:
1064 case IMMED:
1065 case ADEC:
1066 case REGLST:
1067 losing++;
1068 break;
1069 default:
1070 break;
1071 }
1072 break;
1073
1074 case '>':
1075 switch (opP->mode)
1076 {
1077 case DREG:
1078 case AREG:
1079 case FPREG:
1080 case CONTROL:
1081 case IMMED:
1082 case AINC:
1083 case REGLST:
1084 losing++;
1085 break;
1086 case ABSL:
1087 break;
1088 default:
1089 if (opP->reg == PC
1090 || opP->reg == ZPC)
1091 losing++;
1092 break;
1093 }
1094 break;
1095
1096 case 'm':
1097 switch (opP->mode)
1098 {
1099 case DREG:
1100 case AREG:
1101 case AINDR:
1102 case AINC:
1103 case ADEC:
1104 break;
1105 default:
1106 losing++;
1107 }
1108 break;
1109
1110 case 'n':
1111 switch (opP->mode)
1112 {
1113 case DISP:
1114 break;
1115 default:
1116 losing++;
1117 }
1118 break;
1119
1120 case 'o':
1121 switch (opP->mode)
1122 {
1123 case BASE:
1124 case ABSL:
1125 case IMMED:
1126 break;
1127 default:
1128 losing++;
1129 }
1130 break;
1131
1132 case 'p':
1133 switch (opP->mode)
1134 {
1135 case DREG:
1136 case AREG:
1137 case AINDR:
1138 case AINC:
1139 case ADEC:
1140 case DISP:
1141 break;
1142 default:
1143 losing++;
1144 }
1145 break;
1146
1147 case '#':
1148 if (opP->mode != IMMED)
1149 losing++;
1150 else if (s[1] == 'b'
1151 && ! isvar (&opP->disp)
1152 && (opP->disp.exp.X_op != O_constant
1153 || ! isbyte (opP->disp.exp.X_add_number)))
1154 losing++;
1155 else if (s[1] == 'B'
1156 && ! isvar (&opP->disp)
1157 && (opP->disp.exp.X_op != O_constant
1158 || ! issbyte (opP->disp.exp.X_add_number)))
1159 losing++;
1160 else if (s[1] == 'w'
1161 && ! isvar (&opP->disp)
1162 && (opP->disp.exp.X_op != O_constant
1163 || ! isword (opP->disp.exp.X_add_number)))
1164 losing++;
1165 else if (s[1] == 'W'
1166 && ! isvar (&opP->disp)
1167 && (opP->disp.exp.X_op != O_constant
1168 || ! issword (opP->disp.exp.X_add_number)))
1169 losing++;
1170 break;
1171
1172 case '^':
1173 case 'T':
1174 if (opP->mode != IMMED)
1175 losing++;
1176 break;
1177
1178 case '$':
1179 if (opP->mode == AREG
1180 || opP->mode == CONTROL
1181 || opP->mode == FPREG
1182 || opP->mode == IMMED
1183 || opP->mode == REGLST
1184 || (opP->mode != ABSL
1185 && (opP->reg == PC
1186 || opP->reg == ZPC)))
1187 losing++;
1188 break;
1189
1190 case '%':
1191 if (opP->mode == CONTROL
1192 || opP->mode == FPREG
1193 || opP->mode == REGLST
1194 || opP->mode == IMMED
1195 || (opP->mode != ABSL
1196 && (opP->reg == PC
1197 || opP->reg == ZPC)))
1198 losing++;
1199 break;
1200
1201 case '&':
1202 switch (opP->mode)
1203 {
1204 case DREG:
1205 case AREG:
1206 case FPREG:
1207 case CONTROL:
1208 case IMMED:
1209 case AINC:
1210 case ADEC:
1211 case REGLST:
1212 losing++;
1213 break;
1214 case ABSL:
1215 break;
1216 default:
1217 if (opP->reg == PC
1218 || opP->reg == ZPC)
1219 losing++;
1220 break;
1221 }
1222 break;
1223
1224 case '*':
1225 if (opP->mode == CONTROL
1226 || opP->mode == FPREG
1227 || opP->mode == REGLST)
1228 losing++;
1229 break;
1230
1231 case '+':
1232 if (opP->mode != AINC)
1233 losing++;
1234 break;
1235
1236 case '-':
1237 if (opP->mode != ADEC)
1238 losing++;
1239 break;
1240
1241 case '/':
1242 switch (opP->mode)
1243 {
1244 case AREG:
1245 case CONTROL:
1246 case FPREG:
1247 case AINC:
1248 case ADEC:
1249 case IMMED:
1250 case REGLST:
1251 losing++;
1252 break;
1253 default:
1254 break;
1255 }
1256 break;
1257
1258 case ';':
1259 switch (opP->mode)
1260 {
1261 case AREG:
1262 case CONTROL:
1263 case FPREG:
1264 case REGLST:
1265 losing++;
1266 break;
1267 default:
1268 break;
1269 }
1270 break;
1271
1272 case '?':
1273 switch (opP->mode)
1274 {
1275 case AREG:
1276 case CONTROL:
1277 case FPREG:
1278 case AINC:
1279 case ADEC:
1280 case IMMED:
1281 case REGLST:
1282 losing++;
1283 break;
1284 case ABSL:
1285 break;
1286 default:
1287 if (opP->reg == PC || opP->reg == ZPC)
1288 losing++;
1289 break;
1290 }
1291 break;
1292
1293 case '@':
1294 switch (opP->mode)
1295 {
1296 case AREG:
1297 case CONTROL:
1298 case FPREG:
1299 case IMMED:
1300 case REGLST:
1301 losing++;
1302 break;
1303 default:
1304 break;
1305 }
1306 break;
1307
1308 case '~': /* For now! (JF FOO is this right?) */
1309 switch (opP->mode)
1310 {
1311 case DREG:
1312 case AREG:
1313 case CONTROL:
1314 case FPREG:
1315 case IMMED:
1316 case REGLST:
1317 losing++;
1318 break;
1319 case ABSL:
1320 break;
1321 default:
1322 if (opP->reg == PC
1323 || opP->reg == ZPC)
1324 losing++;
1325 break;
1326 }
1327 break;
1328
1329 case '3':
1330 if (opP->mode != CONTROL
1331 || (opP->reg != TT0 && opP->reg != TT1))
1332 losing++;
1333 break;
1334
1335 case 'A':
1336 if (opP->mode != AREG)
1337 losing++;
1338 break;
1339
1340 case 'a':
1341 if (opP->mode != AINDR)
1342 ++losing;
1343 break;
1344
1345 case 'B': /* FOO */
1346 if (opP->mode != ABSL
1347 || (flag_long_jumps
1348 && strncmp (instring, "jbsr", 4) == 0))
1349 losing++;
1350 break;
1351
1352 case 'C':
1353 if (opP->mode != CONTROL || opP->reg != CCR)
1354 losing++;
1355 break;
1356
1357 case 'd':
1358 if (opP->mode != DISP
1359 || opP->reg < ADDR0
1360 || opP->reg > ADDR7)
1361 losing++;
1362 break;
1363
1364 case 'D':
1365 if (opP->mode != DREG)
1366 losing++;
1367 break;
1368
1369 case 'F':
1370 if (opP->mode != FPREG)
1371 losing++;
1372 break;
1373
1374 case 'I':
1375 if (opP->mode != CONTROL
1376 || opP->reg < COP0
1377 || opP->reg > COP7)
1378 losing++;
1379 break;
1380
1381 case 'J':
1382 if (opP->mode != CONTROL
1383 || opP->reg < USP
1384 || opP->reg > last_movec_reg)
1385 losing++;
1386 else
1387 {
1388 const enum m68k_register *rp;
1389 for (rp = control_regs; *rp; rp++)
1390 if (*rp == opP->reg)
1391 break;
1392 if (*rp == 0)
1393 losing++;
1394 }
1395 break;
1396
1397 case 'k':
1398 if (opP->mode != IMMED)
1399 losing++;
1400 break;
1401
1402 case 'l':
1403 case 'L':
1404 if (opP->mode == DREG
1405 || opP->mode == AREG
1406 || opP->mode == FPREG)
1407 {
1408 if (s[1] == '8')
1409 losing++;
1410 else
1411 {
1412 switch (opP->mode)
1413 {
1414 case DREG:
1415 opP->mask = 1 << (opP->reg - DATA0);
1416 break;
1417 case AREG:
1418 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1419 break;
1420 case FPREG:
1421 opP->mask = 1 << (opP->reg - FP0 + 16);
1422 break;
1423 default:
1424 abort ();
1425 }
1426 opP->mode = REGLST;
1427 }
1428 }
1429 else if (opP->mode == CONTROL)
1430 {
1431 if (s[1] != '8')
1432 losing++;
1433 else
1434 {
1435 switch (opP->reg)
1436 {
1437 case FPI:
1438 opP->mask = 1 << 24;
1439 break;
1440 case FPS:
1441 opP->mask = 1 << 25;
1442 break;
1443 case FPC:
1444 opP->mask = 1 << 26;
1445 break;
1446 default:
1447 losing++;
1448 break;
1449 }
1450 opP->mode = REGLST;
1451 }
1452 }
1453 else if (opP->mode == ABSL
1454 && opP->disp.size == SIZE_UNSPEC
1455 && opP->disp.exp.X_op == O_constant)
1456 {
1457 /* This is what the MRI REG pseudo-op generates. */
1458 opP->mode = REGLST;
1459 opP->mask = opP->disp.exp.X_add_number;
1460 }
1461 else if (opP->mode != REGLST)
1462 losing++;
1463 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1464 losing++;
1465 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1466 losing++;
1467 break;
1468
1469 case 'M':
1470 if (opP->mode != IMMED)
1471 losing++;
1472 else if (opP->disp.exp.X_op != O_constant
1473 || ! issbyte (opP->disp.exp.X_add_number))
1474 losing++;
1475 else if (! m68k_quick
1476 && instring[3] != 'q'
1477 && instring[4] != 'q')
1478 losing++;
1479 break;
1480
1481 case 'O':
1482 if (opP->mode != DREG
1483 && opP->mode != IMMED
1484 && opP->mode != ABSL)
1485 losing++;
1486 break;
1487
1488 case 'Q':
1489 if (opP->mode != IMMED)
1490 losing++;
1491 else if (opP->disp.exp.X_op != O_constant
1492 || opP->disp.exp.X_add_number < 1
1493 || opP->disp.exp.X_add_number > 8)
1494 losing++;
1495 else if (! m68k_quick
1496 && (strncmp (instring, "add", 3) == 0
1497 || strncmp (instring, "sub", 3) == 0)
1498 && instring[3] != 'q')
1499 losing++;
1500 break;
1501
1502 case 'R':
1503 if (opP->mode != DREG && opP->mode != AREG)
1504 losing++;
1505 break;
1506
1507 case 'r':
1508 if (opP->mode != AINDR
1509 && (opP->mode != BASE
1510 || (opP->reg != 0
1511 && opP->reg != ZADDR0)
1512 || opP->disp.exp.X_op != O_absent
1513 || ((opP->index.reg < DATA0
1514 || opP->index.reg > DATA7)
1515 && (opP->index.reg < ADDR0
1516 || opP->index.reg > ADDR7))
1517 || opP->index.size != SIZE_UNSPEC
1518 || opP->index.scale != 1))
1519 losing++;
1520 break;
1521
1522 case 's':
1523 if (opP->mode != CONTROL
1524 || ! (opP->reg == FPI
1525 || opP->reg == FPS
1526 || opP->reg == FPC))
1527 losing++;
1528 break;
1529
1530 case 'S':
1531 if (opP->mode != CONTROL || opP->reg != SR)
1532 losing++;
1533 break;
1534
1535 case 't':
1536 if (opP->mode != IMMED)
1537 losing++;
1538 else if (opP->disp.exp.X_op != O_constant
1539 || opP->disp.exp.X_add_number < 0
1540 || opP->disp.exp.X_add_number > 7)
1541 losing++;
1542 break;
1543
1544 case 'U':
1545 if (opP->mode != CONTROL || opP->reg != USP)
1546 losing++;
1547 break;
1548
1549 /* JF these are out of order. We could put them
1550 in order if we were willing to put up with
1551 bunches of #ifdef m68851s in the code.
1552
1553 Don't forget that you need these operands
1554 to use 68030 MMU instructions. */
1555 #ifndef NO_68851
1556 /* Memory addressing mode used by pflushr */
1557 case '|':
1558 if (opP->mode == CONTROL
1559 || opP->mode == FPREG
1560 || opP->mode == DREG
1561 || opP->mode == AREG
1562 || opP->mode == REGLST)
1563 losing++;
1564 /* We should accept immediate operands, but they
1565 supposedly have to be quad word, and we don't
1566 handle that. I would like to see what a Motorola
1567 assembler does before doing something here. */
1568 if (opP->mode == IMMED)
1569 losing++;
1570 break;
1571
1572 case 'f':
1573 if (opP->mode != CONTROL
1574 || (opP->reg != SFC && opP->reg != DFC))
1575 losing++;
1576 break;
1577
1578 case '0':
1579 if (opP->mode != CONTROL || opP->reg != TC)
1580 losing++;
1581 break;
1582
1583 case '1':
1584 if (opP->mode != CONTROL || opP->reg != AC)
1585 losing++;
1586 break;
1587
1588 case '2':
1589 if (opP->mode != CONTROL
1590 || (opP->reg != CAL
1591 && opP->reg != VAL
1592 && opP->reg != SCC))
1593 losing++;
1594 break;
1595
1596 case 'V':
1597 if (opP->mode != CONTROL
1598 || opP->reg != VAL)
1599 losing++;
1600 break;
1601
1602 case 'W':
1603 if (opP->mode != CONTROL
1604 || (opP->reg != DRP
1605 && opP->reg != SRP
1606 && opP->reg != CRP))
1607 losing++;
1608 break;
1609
1610 case 'X':
1611 if (opP->mode != CONTROL
1612 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1613 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1614 losing++;
1615 break;
1616
1617 case 'Y':
1618 if (opP->mode != CONTROL || opP->reg != PSR)
1619 losing++;
1620 break;
1621
1622 case 'Z':
1623 if (opP->mode != CONTROL || opP->reg != PCSR)
1624 losing++;
1625 break;
1626 #endif
1627 case 'c':
1628 if (opP->mode != CONTROL
1629 || (opP->reg != NC
1630 && opP->reg != IC
1631 && opP->reg != DC
1632 && opP->reg != BC))
1633 {
1634 losing++;
1635 } /* not a cache specifier. */
1636 break;
1637
1638 case '_':
1639 if (opP->mode != ABSL)
1640 ++losing;
1641 break;
1642
1643 default:
1644 abort ();
1645 } /* switch on type of operand */
1646
1647 if (losing)
1648 break;
1649 } /* for each operand */
1650 } /* if immediately wrong */
1651
1652 if (!losing)
1653 {
1654 break;
1655 } /* got it. */
1656
1657 opcode = opcode->m_next;
1658
1659 if (!opcode)
1660 {
1661 if (ok_arch
1662 && !(ok_arch & current_architecture))
1663 {
1664 char buf[200], *cp;
1665
1666 strcpy (buf,
1667 "invalid instruction for this architecture; needs ");
1668 cp = buf + strlen (buf);
1669 switch (ok_arch)
1670 {
1671 case mfloat:
1672 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1673 break;
1674 case mmmu:
1675 strcpy (cp, "mmu (68030 or 68851)");
1676 break;
1677 case m68020up:
1678 strcpy (cp, "68020 or higher");
1679 break;
1680 case m68000up:
1681 strcpy (cp, "68000 or higher");
1682 break;
1683 case m68010up:
1684 strcpy (cp, "68010 or higher");
1685 break;
1686 default:
1687 {
1688 int got_one = 0, idx;
1689 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1690 idx++)
1691 {
1692 if ((archs[idx].arch & ok_arch)
1693 && ! archs[idx].alias)
1694 {
1695 if (got_one)
1696 {
1697 strcpy (cp, " or ");
1698 cp += strlen (cp);
1699 }
1700 got_one = 1;
1701 strcpy (cp, archs[idx].name);
1702 cp += strlen (cp);
1703 }
1704 }
1705 }
1706 }
1707 cp = xmalloc (strlen (buf) + 1);
1708 strcpy (cp, buf);
1709 the_ins.error = cp;
1710 }
1711 else
1712 the_ins.error = "operands mismatch";
1713 return;
1714 } /* Fell off the end */
1715
1716 losing = 0;
1717 }
1718
1719 /* now assemble it */
1720
1721 the_ins.args = opcode->m_operands;
1722 the_ins.numargs = opcode->m_opnum;
1723 the_ins.numo = opcode->m_codenum;
1724 the_ins.opcode[0] = getone (opcode);
1725 the_ins.opcode[1] = gettwo (opcode);
1726
1727 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1728 {
1729 /* This switch is a doozy.
1730 Watch the first step; its a big one! */
1731 switch (s[0])
1732 {
1733
1734 case '*':
1735 case '~':
1736 case '%':
1737 case ';':
1738 case '@':
1739 case '!':
1740 case '&':
1741 case '$':
1742 case '?':
1743 case '/':
1744 case '`':
1745 case '<':
1746 case '>':
1747 case 'm':
1748 case 'n':
1749 case 'o':
1750 case 'p':
1751 #ifndef NO_68851
1752 case '|':
1753 #endif
1754 switch (opP->mode)
1755 {
1756 case IMMED:
1757 tmpreg = 0x3c; /* 7.4 */
1758 if (strchr ("bwl", s[1]))
1759 nextword = get_num (&opP->disp, 80);
1760 else
1761 nextword = get_num (&opP->disp, 0);
1762 if (isvar (&opP->disp))
1763 add_fix (s[1], &opP->disp, 0, 0);
1764 switch (s[1])
1765 {
1766 case 'b':
1767 if (!isbyte (nextword))
1768 opP->error = "operand out of range";
1769 addword (nextword);
1770 baseo = 0;
1771 break;
1772 case 'w':
1773 if (!isword (nextword))
1774 opP->error = "operand out of range";
1775 addword (nextword);
1776 baseo = 0;
1777 break;
1778 case 'W':
1779 if (!issword (nextword))
1780 opP->error = "operand out of range";
1781 addword (nextword);
1782 baseo = 0;
1783 break;
1784 case 'l':
1785 addword (nextword >> 16);
1786 addword (nextword);
1787 baseo = 0;
1788 break;
1789
1790 case 'f':
1791 baseo = 2;
1792 outro = 8;
1793 break;
1794 case 'F':
1795 baseo = 4;
1796 outro = 11;
1797 break;
1798 case 'x':
1799 baseo = 6;
1800 outro = 15;
1801 break;
1802 case 'p':
1803 baseo = 6;
1804 outro = -1;
1805 break;
1806 default:
1807 abort ();
1808 }
1809 if (!baseo)
1810 break;
1811
1812 /* We gotta put out some float */
1813 if (op (&opP->disp) != O_big)
1814 {
1815 valueT val;
1816 int gencnt;
1817
1818 /* Can other cases happen here? */
1819 if (op (&opP->disp) != O_constant)
1820 abort ();
1821
1822 val = (valueT) offs (&opP->disp);
1823 gencnt = 0;
1824 do
1825 {
1826 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1827 val >>= LITTLENUM_NUMBER_OF_BITS;
1828 ++gencnt;
1829 }
1830 while (val != 0);
1831 offs (&opP->disp) = gencnt;
1832 }
1833 if (offs (&opP->disp) > 0)
1834 {
1835 if (offs (&opP->disp) > baseo)
1836 {
1837 as_warn ("Bignum too big for %c format; truncated",
1838 s[1]);
1839 offs (&opP->disp) = baseo;
1840 }
1841 baseo -= offs (&opP->disp);
1842 while (baseo--)
1843 addword (0);
1844 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1845 offs (&opP->disp)--;
1846 --wordp)
1847 addword (*wordp);
1848 break;
1849 }
1850 gen_to_words (words, baseo, (long) outro);
1851 for (wordp = words; baseo--; wordp++)
1852 addword (*wordp);
1853 break;
1854 case DREG:
1855 tmpreg = opP->reg - DATA; /* 0.dreg */
1856 break;
1857 case AREG:
1858 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1859 break;
1860 case AINDR:
1861 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1862 break;
1863 case ADEC:
1864 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1865 break;
1866 case AINC:
1867 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1868 break;
1869 case DISP:
1870
1871 nextword = get_num (&opP->disp, 80);
1872
1873 if (opP->reg == PC
1874 && ! isvar (&opP->disp)
1875 && m68k_abspcadd)
1876 {
1877 opP->disp.exp.X_op = O_symbol;
1878 #ifndef BFD_ASSEMBLER
1879 opP->disp.exp.X_add_symbol = &abs_symbol;
1880 #else
1881 opP->disp.exp.X_add_symbol =
1882 section_symbol (absolute_section);
1883 #endif
1884 }
1885
1886 /* Force into index mode. Hope this works */
1887
1888 /* We do the first bit for 32-bit displacements, and the
1889 second bit for 16 bit ones. It is possible that we
1890 should make the default be WORD instead of LONG, but
1891 I think that'd break GCC, so we put up with a little
1892 inefficiency for the sake of working output. */
1893
1894 if (!issword (nextword)
1895 || (isvar (&opP->disp)
1896 && ((opP->disp.size == SIZE_UNSPEC
1897 && flag_short_refs == 0
1898 && cpu_of_arch (current_architecture) >= m68020)
1899 || opP->disp.size == SIZE_LONG)))
1900 {
1901 if (cpu_of_arch (current_architecture) < m68020)
1902 opP->error =
1903 "displacement too large for this architecture; needs 68020 or higher";
1904 if (opP->reg == PC)
1905 tmpreg = 0x3B; /* 7.3 */
1906 else
1907 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1908 if (isvar (&opP->disp))
1909 {
1910 if (opP->reg == PC)
1911 {
1912 if (opP->disp.size == SIZE_LONG
1913 #ifdef OBJ_ELF
1914 /* If the displacement needs pic
1915 relocation it cannot be relaxed. */
1916 || opP->disp.pic_reloc != pic_none
1917 #endif
1918 )
1919 {
1920 addword (0x0170);
1921 add_fix ('l', &opP->disp, 1, 2);
1922 }
1923 else
1924 {
1925 add_frag (adds (&opP->disp),
1926 offs (&opP->disp),
1927 TAB (PCLEA, SZ_UNDEF));
1928 break;
1929 }
1930 }
1931 else
1932 {
1933 addword (0x0170);
1934 add_fix ('l', &opP->disp, 0, 0);
1935 }
1936 }
1937 else
1938 addword (0x0170);
1939 addword (nextword >> 16);
1940 }
1941 else
1942 {
1943 if (opP->reg == PC)
1944 tmpreg = 0x3A; /* 7.2 */
1945 else
1946 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1947
1948 if (isvar (&opP->disp))
1949 {
1950 if (opP->reg == PC)
1951 {
1952 add_fix ('w', &opP->disp, 1, 0);
1953 }
1954 else
1955 add_fix ('w', &opP->disp, 0, 0);
1956 }
1957 }
1958 addword (nextword);
1959 break;
1960
1961 case POST:
1962 case PRE:
1963 case BASE:
1964 nextword = 0;
1965 baseo = get_num (&opP->disp, 80);
1966 if (opP->mode == POST || opP->mode == PRE)
1967 outro = get_num (&opP->odisp, 80);
1968 /* Figure out the `addressing mode'.
1969 Also turn on the BASE_DISABLE bit, if needed. */
1970 if (opP->reg == PC || opP->reg == ZPC)
1971 {
1972 tmpreg = 0x3b; /* 7.3 */
1973 if (opP->reg == ZPC)
1974 nextword |= 0x80;
1975 }
1976 else if (opP->reg == 0)
1977 {
1978 nextword |= 0x80;
1979 tmpreg = 0x30; /* 6.garbage */
1980 }
1981 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1982 {
1983 nextword |= 0x80;
1984 tmpreg = 0x30 + opP->reg - ZADDR0;
1985 }
1986 else
1987 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1988
1989 siz1 = opP->disp.size;
1990 if (opP->mode == POST || opP->mode == PRE)
1991 siz2 = opP->odisp.size;
1992 else
1993 siz2 = SIZE_UNSPEC;
1994
1995 /* Index register stuff */
1996 if (opP->index.reg != 0
1997 && opP->index.reg >= DATA
1998 && opP->index.reg <= ADDR7)
1999 {
2000 nextword |= (opP->index.reg - DATA) << 12;
2001
2002 if (opP->index.size == SIZE_LONG
2003 || (opP->index.size == SIZE_UNSPEC
2004 && m68k_index_width_default == SIZE_LONG))
2005 nextword |= 0x800;
2006
2007 if ((opP->index.scale != 1
2008 && cpu_of_arch (current_architecture) < m68020)
2009 || (opP->index.scale == 8
2010 && current_architecture == mcf5200))
2011 {
2012 opP->error =
2013 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
2014 }
2015
2016 switch (opP->index.scale)
2017 {
2018 case 1:
2019 break;
2020 case 2:
2021 nextword |= 0x200;
2022 break;
2023 case 4:
2024 nextword |= 0x400;
2025 break;
2026 case 8:
2027 nextword |= 0x600;
2028 break;
2029 default:
2030 abort ();
2031 }
2032 /* IF its simple,
2033 GET US OUT OF HERE! */
2034
2035 /* Must be INDEX, with an index register. Address
2036 register cannot be ZERO-PC, and either :b was
2037 forced, or we know it will fit. For a 68000 or
2038 68010, force this mode anyways, because the
2039 larger modes aren't supported. */
2040 if (opP->mode == BASE
2041 && ((opP->reg >= ADDR0
2042 && opP->reg <= ADDR7)
2043 || opP->reg == PC))
2044 {
2045 if (siz1 == SIZE_BYTE
2046 || cpu_of_arch (current_architecture) < m68020
2047 || (siz1 == SIZE_UNSPEC
2048 && ! isvar (&opP->disp)
2049 && issbyte (baseo)))
2050 {
2051 nextword += baseo & 0xff;
2052 addword (nextword);
2053 if (isvar (&opP->disp))
2054 {
2055 /* Do a byte relocation. If it doesn't
2056 fit (possible on m68000) let the
2057 fixup processing complain later. */
2058 if (opP->reg == PC)
2059 add_fix ('B', &opP->disp, 1, 1);
2060 else
2061 add_fix ('B', &opP->disp, 0, 0);
2062 }
2063 else if (siz1 != SIZE_BYTE)
2064 {
2065 if (siz1 != SIZE_UNSPEC)
2066 as_warn ("Forcing byte displacement");
2067 if (! issbyte (baseo))
2068 opP->error = "byte displacement out of range";
2069 }
2070
2071 break;
2072 }
2073 else if (siz1 == SIZE_UNSPEC
2074 && opP->reg == PC
2075 && isvar (&opP->disp)
2076 && subs (&opP->disp) == NULL
2077 #ifdef OBJ_ELF
2078 /* If the displacement needs pic
2079 relocation it cannot be relaxed. */
2080 && opP->disp.pic_reloc == pic_none
2081 #endif
2082 )
2083 {
2084 nextword += baseo & 0xff;
2085 addword (nextword);
2086 add_frag (adds (&opP->disp), offs (&opP->disp),
2087 TAB (PCINDEX, SZ_UNDEF));
2088
2089 break;
2090 }
2091 }
2092 }
2093 else
2094 {
2095 nextword |= 0x40; /* No index reg */
2096 if (opP->index.reg >= ZDATA0
2097 && opP->index.reg <= ZDATA7)
2098 nextword |= (opP->index.reg - ZDATA0) << 12;
2099 else if (opP->index.reg >= ZADDR0
2100 || opP->index.reg <= ZADDR7)
2101 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2102 }
2103
2104 /* It isn't simple. */
2105
2106 if (cpu_of_arch (current_architecture) < m68020)
2107 opP->error =
2108 "invalid operand mode for this architecture; needs 68020 or higher";
2109
2110 nextword |= 0x100;
2111 /* If the guy specified a width, we assume that it is
2112 wide enough. Maybe it isn't. If so, we lose. */
2113 switch (siz1)
2114 {
2115 case SIZE_UNSPEC:
2116 if (isvar (&opP->disp)
2117 ? m68k_rel32
2118 : ! issword (baseo))
2119 {
2120 siz1 = SIZE_LONG;
2121 nextword |= 0x30;
2122 }
2123 else if (! isvar (&opP->disp) && baseo == 0)
2124 nextword |= 0x10;
2125 else
2126 {
2127 nextword |= 0x20;
2128 siz1 = SIZE_WORD;
2129 }
2130 break;
2131 case SIZE_BYTE:
2132 as_warn (":b not permitted; defaulting to :w");
2133 /* Fall through. */
2134 case SIZE_WORD:
2135 nextword |= 0x20;
2136 break;
2137 case SIZE_LONG:
2138 nextword |= 0x30;
2139 break;
2140 }
2141
2142 /* Figure out innner displacement stuff */
2143 if (opP->mode == POST || opP->mode == PRE)
2144 {
2145 if (cpu_of_arch (current_architecture) & cpu32)
2146 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
2147 switch (siz2)
2148 {
2149 case SIZE_UNSPEC:
2150 if (isvar (&opP->odisp)
2151 ? m68k_rel32
2152 : ! issword (outro))
2153 {
2154 siz2 = SIZE_LONG;
2155 nextword |= 0x3;
2156 }
2157 else if (! isvar (&opP->odisp) && outro == 0)
2158 nextword |= 0x1;
2159 else
2160 {
2161 nextword |= 0x2;
2162 siz2 = SIZE_WORD;
2163 }
2164 break;
2165 case 1:
2166 as_warn (":b not permitted; defaulting to :w");
2167 /* Fall through. */
2168 case 2:
2169 nextword |= 0x2;
2170 break;
2171 case 3:
2172 nextword |= 0x3;
2173 break;
2174 }
2175 if (opP->mode == POST
2176 && (nextword & 0x40) == 0)
2177 nextword |= 0x04;
2178 }
2179 addword (nextword);
2180
2181 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2182 {
2183 if (opP->reg == PC || opP->reg == ZPC)
2184 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2185 else
2186 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2187 }
2188 if (siz1 == SIZE_LONG)
2189 addword (baseo >> 16);
2190 if (siz1 != SIZE_UNSPEC)
2191 addword (baseo);
2192
2193 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2194 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2195 if (siz2 == SIZE_LONG)
2196 addword (outro >> 16);
2197 if (siz2 != SIZE_UNSPEC)
2198 addword (outro);
2199
2200 break;
2201
2202 case ABSL:
2203 nextword = get_num (&opP->disp, 80);
2204 switch (opP->disp.size)
2205 {
2206 default:
2207 abort ();
2208 case SIZE_UNSPEC:
2209 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2210 {
2211 tmpreg = 0x38; /* 7.0 */
2212 addword (nextword);
2213 break;
2214 }
2215 /* Don't generate pc relative code on 68010 and
2216 68000. */
2217 if (isvar (&opP->disp)
2218 && !subs (&opP->disp)
2219 && adds (&opP->disp)
2220 #ifdef OBJ_ELF
2221 /* If the displacement needs pic relocation it
2222 cannot be relaxed. */
2223 && opP->disp.pic_reloc == pic_none
2224 #endif
2225 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2226 && cpu_of_arch (current_architecture) >= m68020
2227 && !flag_long_jumps
2228 && !strchr ("~%&$?", s[0]))
2229 {
2230 tmpreg = 0x3A; /* 7.2 */
2231 add_frag (adds (&opP->disp),
2232 offs (&opP->disp),
2233 TAB (PCREL, SZ_UNDEF));
2234 break;
2235 }
2236 /* Fall through into long */
2237 case SIZE_LONG:
2238 if (isvar (&opP->disp))
2239 add_fix ('l', &opP->disp, 0, 0);
2240
2241 tmpreg = 0x39;/* 7.1 mode */
2242 addword (nextword >> 16);
2243 addword (nextword);
2244 break;
2245
2246 case SIZE_WORD: /* Word */
2247 if (isvar (&opP->disp))
2248 add_fix ('w', &opP->disp, 0, 0);
2249
2250 tmpreg = 0x38;/* 7.0 mode */
2251 addword (nextword);
2252 break;
2253 }
2254 break;
2255 case CONTROL:
2256 case FPREG:
2257 default:
2258 as_bad ("unknown/incorrect operand");
2259 /* abort(); */
2260 }
2261 install_gen_operand (s[1], tmpreg);
2262 break;
2263
2264 case '#':
2265 case '^':
2266 switch (s[1])
2267 { /* JF: I hate floating point! */
2268 case 'j':
2269 tmpreg = 70;
2270 break;
2271 case '8':
2272 tmpreg = 20;
2273 break;
2274 case 'C':
2275 tmpreg = 50;
2276 break;
2277 case '3':
2278 default:
2279 tmpreg = 80;
2280 break;
2281 }
2282 tmpreg = get_num (&opP->disp, tmpreg);
2283 if (isvar (&opP->disp))
2284 add_fix (s[1], &opP->disp, 0, 0);
2285 switch (s[1])
2286 {
2287 case 'b': /* Danger: These do no check for
2288 certain types of overflow.
2289 user beware! */
2290 if (!isbyte (tmpreg))
2291 opP->error = "out of range";
2292 insop (tmpreg, opcode);
2293 if (isvar (&opP->disp))
2294 the_ins.reloc[the_ins.nrel - 1].n =
2295 (opcode->m_codenum) * 2 + 1;
2296 break;
2297 case 'B':
2298 if (!issbyte (tmpreg))
2299 opP->error = "out of range";
2300 opcode->m_opcode |= tmpreg;
2301 if (isvar (&opP->disp))
2302 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2303 break;
2304 case 'w':
2305 if (!isword (tmpreg))
2306 opP->error = "out of range";
2307 insop (tmpreg, opcode);
2308 if (isvar (&opP->disp))
2309 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2310 break;
2311 case 'W':
2312 if (!issword (tmpreg))
2313 opP->error = "out of range";
2314 insop (tmpreg, opcode);
2315 if (isvar (&opP->disp))
2316 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2317 break;
2318 case 'l':
2319 /* Because of the way insop works, we put these two out
2320 backwards. */
2321 insop (tmpreg, opcode);
2322 insop (tmpreg >> 16, opcode);
2323 if (isvar (&opP->disp))
2324 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2325 break;
2326 case '3':
2327 tmpreg &= 0xFF;
2328 case '8':
2329 case 'C':
2330 install_operand (s[1], tmpreg);
2331 break;
2332 default:
2333 abort ();
2334 }
2335 break;
2336
2337 case '+':
2338 case '-':
2339 case 'A':
2340 case 'a':
2341 install_operand (s[1], opP->reg - ADDR);
2342 break;
2343
2344 case 'B':
2345 tmpreg = get_num (&opP->disp, 80);
2346 switch (s[1])
2347 {
2348 case 'B':
2349 /* The pc_fix argument winds up in fx_pcrel_adjust,
2350 which is a char, and may therefore be unsigned. We
2351 want to pass -1, but we pass 64 instead, and convert
2352 back in md_pcrel_from. */
2353 add_fix ('B', &opP->disp, 1, 64);
2354 break;
2355 case 'W':
2356 add_fix ('w', &opP->disp, 1, 0);
2357 addword (0);
2358 break;
2359 case 'L':
2360 long_branch:
2361 if (cpu_of_arch (current_architecture) < m68020)
2362 as_warn ("Can't use long branches on 68000/68010");
2363 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2364 add_fix ('l', &opP->disp, 1, 0);
2365 addword (0);
2366 addword (0);
2367 break;
2368 case 'g':
2369 if (subs (&opP->disp)) /* We can't relax it */
2370 goto long_branch;
2371
2372 #ifdef OBJ_ELF
2373 /* If the displacement needs pic relocation it cannot be
2374 relaxed. */
2375 if (opP->disp.pic_reloc != pic_none)
2376 goto long_branch;
2377 #endif
2378
2379 /* This could either be a symbol, or an absolute
2380 address. No matter, the frag hacking will finger it
2381 out. Not quite: it can't switch from BRANCH to
2382 BCC68000 for the case where opnd is absolute (it
2383 needs to use the 68000 hack since no conditional abs
2384 jumps). */
2385 if (((cpu_of_arch (current_architecture) < m68020)
2386 || (0 == adds (&opP->disp)))
2387 && (the_ins.opcode[0] >= 0x6200)
2388 && (the_ins.opcode[0] <= 0x6f00))
2389 add_frag (adds (&opP->disp), offs (&opP->disp),
2390 TAB (BCC68000, SZ_UNDEF));
2391 else
2392 add_frag (adds (&opP->disp), offs (&opP->disp),
2393 TAB (ABRANCH, SZ_UNDEF));
2394 break;
2395 case 'w':
2396 if (isvar (&opP->disp))
2397 {
2398 #if 1
2399 /* check for DBcc instruction */
2400 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2401 {
2402 /* size varies if patch */
2403 /* needed for long form */
2404 add_frag (adds (&opP->disp), offs (&opP->disp),
2405 TAB (DBCC, SZ_UNDEF));
2406 break;
2407 }
2408 #endif
2409 add_fix ('w', &opP->disp, 1, 0);
2410 }
2411 addword (0);
2412 break;
2413 case 'C': /* Fixed size LONG coproc branches */
2414 add_fix ('l', &opP->disp, 1, 0);
2415 addword (0);
2416 addword (0);
2417 break;
2418 case 'c': /* Var size Coprocesssor branches */
2419 if (subs (&opP->disp))
2420 {
2421 add_fix ('l', &opP->disp, 1, 0);
2422 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2423 }
2424 else if (adds (&opP->disp))
2425 add_frag (adds (&opP->disp), offs (&opP->disp),
2426 TAB (FBRANCH, SZ_UNDEF));
2427 else
2428 {
2429 /* add_frag((symbolS *) 0, offs(&opP->disp),
2430 TAB(FBRANCH,SHORT)); */
2431 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2432 add_fix ('l', &opP->disp, 1, 0);
2433 addword (0);
2434 addword (0);
2435 }
2436 break;
2437 default:
2438 abort ();
2439 }
2440 break;
2441
2442 case 'C': /* Ignore it */
2443 break;
2444
2445 case 'd': /* JF this is a kludge */
2446 install_operand ('s', opP->reg - ADDR);
2447 tmpreg = get_num (&opP->disp, 80);
2448 if (!issword (tmpreg))
2449 {
2450 as_warn ("Expression out of range, using 0");
2451 tmpreg = 0;
2452 }
2453 addword (tmpreg);
2454 break;
2455
2456 case 'D':
2457 install_operand (s[1], opP->reg - DATA);
2458 break;
2459
2460 case 'F':
2461 install_operand (s[1], opP->reg - FP0);
2462 break;
2463
2464 case 'I':
2465 tmpreg = opP->reg - COP0;
2466 install_operand (s[1], tmpreg);
2467 break;
2468
2469 case 'J': /* JF foo */
2470 switch (opP->reg)
2471 {
2472 case SFC:
2473 tmpreg = 0x000;
2474 break;
2475 case DFC:
2476 tmpreg = 0x001;
2477 break;
2478 case CACR:
2479 tmpreg = 0x002;
2480 break;
2481 case TC:
2482 tmpreg = 0x003;
2483 break;
2484 case ITT0:
2485 tmpreg = 0x004;
2486 break;
2487 case ITT1:
2488 tmpreg = 0x005;
2489 break;
2490 case DTT0:
2491 tmpreg = 0x006;
2492 break;
2493 case DTT1:
2494 tmpreg = 0x007;
2495 break;
2496 case BUSCR:
2497 tmpreg = 0x008;
2498 break;
2499
2500 case USP:
2501 tmpreg = 0x800;
2502 break;
2503 case VBR:
2504 tmpreg = 0x801;
2505 break;
2506 case CAAR:
2507 tmpreg = 0x802;
2508 break;
2509 case MSP:
2510 tmpreg = 0x803;
2511 break;
2512 case ISP:
2513 tmpreg = 0x804;
2514 break;
2515 case MMUSR:
2516 tmpreg = 0x805;
2517 break;
2518 case URP:
2519 tmpreg = 0x806;
2520 break;
2521 case SRP:
2522 tmpreg = 0x807;
2523 break;
2524 case PCR:
2525 tmpreg = 0x808;
2526 break;
2527 case ROMBAR:
2528 tmpreg = 0xC00;
2529 break;
2530 case RAMBAR0:
2531 tmpreg = 0xC04;
2532 break;
2533 case RAMBAR1:
2534 tmpreg = 0xC05;
2535 break;
2536 case MBAR:
2537 tmpreg = 0xC0F;
2538 break;
2539 default:
2540 abort ();
2541 }
2542 install_operand (s[1], tmpreg);
2543 break;
2544
2545 case 'k':
2546 tmpreg = get_num (&opP->disp, 55);
2547 install_operand (s[1], tmpreg & 0x7f);
2548 break;
2549
2550 case 'l':
2551 tmpreg = opP->mask;
2552 if (s[1] == 'w')
2553 {
2554 if (tmpreg & 0x7FF0000)
2555 as_bad ("Floating point register in register list");
2556 insop (reverse_16_bits (tmpreg), opcode);
2557 }
2558 else
2559 {
2560 if (tmpreg & 0x700FFFF)
2561 as_bad ("Wrong register in floating-point reglist");
2562 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2563 }
2564 break;
2565
2566 case 'L':
2567 tmpreg = opP->mask;
2568 if (s[1] == 'w')
2569 {
2570 if (tmpreg & 0x7FF0000)
2571 as_bad ("Floating point register in register list");
2572 insop (tmpreg, opcode);
2573 }
2574 else if (s[1] == '8')
2575 {
2576 if (tmpreg & 0x0FFFFFF)
2577 as_bad ("incorrect register in reglist");
2578 install_operand (s[1], tmpreg >> 24);
2579 }
2580 else
2581 {
2582 if (tmpreg & 0x700FFFF)
2583 as_bad ("wrong register in floating-point reglist");
2584 else
2585 install_operand (s[1], tmpreg >> 16);
2586 }
2587 break;
2588
2589 case 'M':
2590 install_operand (s[1], get_num (&opP->disp, 60));
2591 break;
2592
2593 case 'O':
2594 tmpreg = ((opP->mode == DREG)
2595 ? 0x20 + opP->reg - DATA
2596 : (get_num (&opP->disp, 40) & 0x1F));
2597 install_operand (s[1], tmpreg);
2598 break;
2599
2600 case 'Q':
2601 tmpreg = get_num (&opP->disp, 10);
2602 if (tmpreg == 8)
2603 tmpreg = 0;
2604 install_operand (s[1], tmpreg);
2605 break;
2606
2607 case 'R':
2608 /* This depends on the fact that ADDR registers are eight
2609 more than their corresponding DATA regs, so the result
2610 will have the ADDR_REG bit set */
2611 install_operand (s[1], opP->reg - DATA);
2612 break;
2613
2614 case 'r':
2615 if (opP->mode == AINDR)
2616 install_operand (s[1], opP->reg - DATA);
2617 else
2618 install_operand (s[1], opP->index.reg - DATA);
2619 break;
2620
2621 case 's':
2622 if (opP->reg == FPI)
2623 tmpreg = 0x1;
2624 else if (opP->reg == FPS)
2625 tmpreg = 0x2;
2626 else if (opP->reg == FPC)
2627 tmpreg = 0x4;
2628 else
2629 abort ();
2630 install_operand (s[1], tmpreg);
2631 break;
2632
2633 case 'S': /* Ignore it */
2634 break;
2635
2636 case 'T':
2637 install_operand (s[1], get_num (&opP->disp, 30));
2638 break;
2639
2640 case 'U': /* Ignore it */
2641 break;
2642
2643 case 'c':
2644 switch (opP->reg)
2645 {
2646 case NC:
2647 tmpreg = 0;
2648 break;
2649 case DC:
2650 tmpreg = 1;
2651 break;
2652 case IC:
2653 tmpreg = 2;
2654 break;
2655 case BC:
2656 tmpreg = 3;
2657 break;
2658 default:
2659 as_fatal ("failed sanity check");
2660 } /* switch on cache token */
2661 install_operand (s[1], tmpreg);
2662 break;
2663 #ifndef NO_68851
2664 /* JF: These are out of order, I fear. */
2665 case 'f':
2666 switch (opP->reg)
2667 {
2668 case SFC:
2669 tmpreg = 0;
2670 break;
2671 case DFC:
2672 tmpreg = 1;
2673 break;
2674 default:
2675 abort ();
2676 }
2677 install_operand (s[1], tmpreg);
2678 break;
2679
2680 case '0':
2681 case '1':
2682 case '2':
2683 switch (opP->reg)
2684 {
2685 case TC:
2686 tmpreg = 0;
2687 break;
2688 case CAL:
2689 tmpreg = 4;
2690 break;
2691 case VAL:
2692 tmpreg = 5;
2693 break;
2694 case SCC:
2695 tmpreg = 6;
2696 break;
2697 case AC:
2698 tmpreg = 7;
2699 break;
2700 default:
2701 abort ();
2702 }
2703 install_operand (s[1], tmpreg);
2704 break;
2705
2706 case 'V':
2707 if (opP->reg == VAL)
2708 break;
2709 abort ();
2710
2711 case 'W':
2712 switch (opP->reg)
2713 {
2714 case DRP:
2715 tmpreg = 1;
2716 break;
2717 case SRP:
2718 tmpreg = 2;
2719 break;
2720 case CRP:
2721 tmpreg = 3;
2722 break;
2723 default:
2724 abort ();
2725 }
2726 install_operand (s[1], tmpreg);
2727 break;
2728
2729 case 'X':
2730 switch (opP->reg)
2731 {
2732 case BAD:
2733 case BAD + 1:
2734 case BAD + 2:
2735 case BAD + 3:
2736 case BAD + 4:
2737 case BAD + 5:
2738 case BAD + 6:
2739 case BAD + 7:
2740 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2741 break;
2742
2743 case BAC:
2744 case BAC + 1:
2745 case BAC + 2:
2746 case BAC + 3:
2747 case BAC + 4:
2748 case BAC + 5:
2749 case BAC + 6:
2750 case BAC + 7:
2751 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2752 break;
2753
2754 default:
2755 abort ();
2756 }
2757 install_operand (s[1], tmpreg);
2758 break;
2759 case 'Y':
2760 know (opP->reg == PSR);
2761 break;
2762 case 'Z':
2763 know (opP->reg == PCSR);
2764 break;
2765 #endif /* m68851 */
2766 case '3':
2767 switch (opP->reg)
2768 {
2769 case TT0:
2770 tmpreg = 2;
2771 break;
2772 case TT1:
2773 tmpreg = 3;
2774 break;
2775 default:
2776 abort ();
2777 }
2778 install_operand (s[1], tmpreg);
2779 break;
2780 case 't':
2781 tmpreg = get_num (&opP->disp, 20);
2782 install_operand (s[1], tmpreg);
2783 break;
2784 case '_': /* used only for move16 absolute 32-bit address */
2785 tmpreg = get_num (&opP->disp, 80);
2786 addword (tmpreg >> 16);
2787 addword (tmpreg & 0xFFFF);
2788 break;
2789 default:
2790 abort ();
2791 }
2792 }
2793
2794 /* By the time whe get here (FINALLY) the_ins contains the complete
2795 instruction, ready to be emitted. . . */
2796 }
2797
2798 static int
2799 reverse_16_bits (in)
2800 int in;
2801 {
2802 int out = 0;
2803 int n;
2804
2805 static int mask[16] =
2806 {
2807 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2808 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2809 };
2810 for (n = 0; n < 16; n++)
2811 {
2812 if (in & mask[n])
2813 out |= mask[15 - n];
2814 }
2815 return out;
2816 } /* reverse_16_bits() */
2817
2818 static int
2819 reverse_8_bits (in)
2820 int in;
2821 {
2822 int out = 0;
2823 int n;
2824
2825 static int mask[8] =
2826 {
2827 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2828 };
2829
2830 for (n = 0; n < 8; n++)
2831 {
2832 if (in & mask[n])
2833 out |= mask[7 - n];
2834 }
2835 return out;
2836 } /* reverse_8_bits() */
2837
2838 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2839 (that value is chosen in the frag_var call in md_assemble). TYPE
2840 is the subtype of the frag to be generated; its primary type is
2841 rs_machine_dependent.
2842
2843 The TYPE parameter is also used by md_convert_frag_1 and
2844 md_estimate_size_before_relax. The appropriate type of fixup will
2845 be emitted by md_convert_frag_1.
2846
2847 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2848 static void
2849 install_operand (mode, val)
2850 int mode;
2851 int val;
2852 {
2853 switch (mode)
2854 {
2855 case 's':
2856 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2857 break;
2858 case 'd':
2859 the_ins.opcode[0] |= val << 9;
2860 break;
2861 case '1':
2862 the_ins.opcode[1] |= val << 12;
2863 break;
2864 case '2':
2865 the_ins.opcode[1] |= val << 6;
2866 break;
2867 case '3':
2868 the_ins.opcode[1] |= val;
2869 break;
2870 case '4':
2871 the_ins.opcode[2] |= val << 12;
2872 break;
2873 case '5':
2874 the_ins.opcode[2] |= val << 6;
2875 break;
2876 case '6':
2877 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2878 three words long! */
2879 the_ins.numo++;
2880 the_ins.opcode[2] |= val;
2881 break;
2882 case '7':
2883 the_ins.opcode[1] |= val << 7;
2884 break;
2885 case '8':
2886 the_ins.opcode[1] |= val << 10;
2887 break;
2888 #ifndef NO_68851
2889 case '9':
2890 the_ins.opcode[1] |= val << 5;
2891 break;
2892 #endif
2893
2894 case 't':
2895 the_ins.opcode[1] |= (val << 10) | (val << 7);
2896 break;
2897 case 'D':
2898 the_ins.opcode[1] |= (val << 12) | val;
2899 break;
2900 case 'g':
2901 the_ins.opcode[0] |= val = 0xff;
2902 break;
2903 case 'i':
2904 the_ins.opcode[0] |= val << 9;
2905 break;
2906 case 'C':
2907 the_ins.opcode[1] |= val;
2908 break;
2909 case 'j':
2910 the_ins.opcode[1] |= val;
2911 the_ins.numo++; /* What a hack */
2912 break;
2913 case 'k':
2914 the_ins.opcode[1] |= val << 4;
2915 break;
2916 case 'b':
2917 case 'w':
2918 case 'W':
2919 case 'l':
2920 break;
2921 case 'e':
2922 the_ins.opcode[0] |= (val << 6);
2923 break;
2924 case 'L':
2925 the_ins.opcode[1] = (val >> 16);
2926 the_ins.opcode[2] = val & 0xffff;
2927 break;
2928 case 'c':
2929 default:
2930 as_fatal ("failed sanity check.");
2931 }
2932 } /* install_operand() */
2933
2934 static void
2935 install_gen_operand (mode, val)
2936 int mode;
2937 int val;
2938 {
2939 switch (mode)
2940 {
2941 case 's':
2942 the_ins.opcode[0] |= val;
2943 break;
2944 case 'd':
2945 /* This is a kludge!!! */
2946 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2947 break;
2948 case 'b':
2949 case 'w':
2950 case 'l':
2951 case 'f':
2952 case 'F':
2953 case 'x':
2954 case 'p':
2955 the_ins.opcode[0] |= val;
2956 break;
2957 /* more stuff goes here */
2958 default:
2959 as_fatal ("failed sanity check.");
2960 }
2961 } /* install_gen_operand() */
2962
2963 /*
2964 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2965 * then deal with the bitfield hack.
2966 */
2967
2968 static char *
2969 crack_operand (str, opP)
2970 register char *str;
2971 register struct m68k_op *opP;
2972 {
2973 register int parens;
2974 register int c;
2975 register char *beg_str;
2976 int inquote = 0;
2977
2978 if (!str)
2979 {
2980 return str;
2981 }
2982 beg_str = str;
2983 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
2984 {
2985 if (! inquote)
2986 {
2987 if (*str == '(')
2988 parens++;
2989 else if (*str == ')')
2990 {
2991 if (!parens)
2992 { /* ERROR */
2993 opP->error = "Extra )";
2994 return str;
2995 }
2996 --parens;
2997 }
2998 }
2999 if (flag_mri && *str == '\'')
3000 inquote = ! inquote;
3001 }
3002 if (!*str && parens)
3003 { /* ERROR */
3004 opP->error = "Missing )";
3005 return str;
3006 }
3007 c = *str;
3008 *str = '\0';
3009 if (m68k_ip_op (beg_str, opP) != 0)
3010 {
3011 *str = c;
3012 return str;
3013 }
3014 *str = c;
3015 if (c == '}')
3016 c = *++str; /* JF bitfield hack */
3017 if (c)
3018 {
3019 c = *++str;
3020 if (!c)
3021 as_bad ("Missing operand");
3022 }
3023 return str;
3024 }
3025
3026 /* This is the guts of the machine-dependent assembler. STR points to a
3027 machine dependent instruction. This function is supposed to emit
3028 the frags/bytes it assembles to.
3029 */
3030
3031 void
3032 insert_reg (regname, regnum)
3033 char *regname;
3034 int regnum;
3035 {
3036 char buf[100];
3037 int i;
3038
3039 #ifdef REGISTER_PREFIX
3040 if (!flag_reg_prefix_optional)
3041 {
3042 buf[0] = REGISTER_PREFIX;
3043 strcpy (buf + 1, regname);
3044 regname = buf;
3045 }
3046 #endif
3047
3048 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3049 &zero_address_frag));
3050
3051 for (i = 0; regname[i]; i++)
3052 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3053 buf[i] = '\0';
3054
3055 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3056 &zero_address_frag));
3057 }
3058
3059 struct init_entry
3060 {
3061 const char *name;
3062 int number;
3063 };
3064
3065 static const struct init_entry init_table[] =
3066 {
3067 { "d0", DATA0 },
3068 { "d1", DATA1 },
3069 { "d2", DATA2 },
3070 { "d3", DATA3 },
3071 { "d4", DATA4 },
3072 { "d5", DATA5 },
3073 { "d6", DATA6 },
3074 { "d7", DATA7 },
3075 { "a0", ADDR0 },
3076 { "a1", ADDR1 },
3077 { "a2", ADDR2 },
3078 { "a3", ADDR3 },
3079 { "a4", ADDR4 },
3080 { "a5", ADDR5 },
3081 { "a6", ADDR6 },
3082 { "fp", ADDR6 },
3083 { "a7", ADDR7 },
3084 { "sp", ADDR7 },
3085 { "ssp", ADDR7 },
3086 { "fp0", FP0 },
3087 { "fp1", FP1 },
3088 { "fp2", FP2 },
3089 { "fp3", FP3 },
3090 { "fp4", FP4 },
3091 { "fp5", FP5 },
3092 { "fp6", FP6 },
3093 { "fp7", FP7 },
3094 { "fpi", FPI },
3095 { "fpiar", FPI },
3096 { "fpc", FPI },
3097 { "fps", FPS },
3098 { "fpsr", FPS },
3099 { "fpc", FPC },
3100 { "fpcr", FPC },
3101 { "control", FPC },
3102 { "status", FPS },
3103 { "iaddr", FPI },
3104
3105 { "cop0", COP0 },
3106 { "cop1", COP1 },
3107 { "cop2", COP2 },
3108 { "cop3", COP3 },
3109 { "cop4", COP4 },
3110 { "cop5", COP5 },
3111 { "cop6", COP6 },
3112 { "cop7", COP7 },
3113 { "pc", PC },
3114 { "zpc", ZPC },
3115 { "sr", SR },
3116
3117 { "ccr", CCR },
3118 { "cc", CCR },
3119
3120 /* control registers */
3121 { "sfc", SFC }, /* Source Function Code */
3122 { "sfcr", SFC },
3123 { "dfc", DFC }, /* Destination Function Code */
3124 { "dfcr", DFC },
3125 { "cacr", CACR }, /* Cache Control Register */
3126 { "caar", CAAR }, /* Cache Address Register */
3127
3128 { "usp", USP }, /* User Stack Pointer */
3129 { "vbr", VBR }, /* Vector Base Register */
3130 { "msp", MSP }, /* Master Stack Pointer */
3131 { "isp", ISP }, /* Interrupt Stack Pointer */
3132
3133 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3134 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3135 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3136 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3137
3138 /* 68ec040 versions of same */
3139 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3140 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3141 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3142 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3143
3144 /* mcf5200 versions of same. The ColdFire programmer's reference
3145 manual indicated that the order is 2,3,0,1, but Ken Rose
3146 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3147 { "acr0", ITT0 }, /* Access Control Unit 0 */
3148 { "acr1", ITT1 }, /* Access Control Unit 1 */
3149 { "acr2", DTT0 }, /* Access Control Unit 2 */
3150 { "acr3", DTT1 }, /* Access Control Unit 3 */
3151
3152 { "tc", TC }, /* MMU Translation Control Register */
3153 { "tcr", TC },
3154
3155 { "mmusr", MMUSR }, /* MMU Status Register */
3156 { "srp", SRP }, /* User Root Pointer */
3157 { "urp", URP }, /* Supervisor Root Pointer */
3158
3159 { "buscr", BUSCR },
3160 { "pcr", PCR },
3161
3162 { "rombar", ROMBAR }, /* ROM Base Address Register */
3163 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3164 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3165 { "mbar", MBAR }, /* Module Base Address Register */
3166 /* end of control registers */
3167
3168 { "ac", AC },
3169 { "bc", BC },
3170 { "cal", CAL },
3171 { "crp", CRP },
3172 { "drp", DRP },
3173 { "pcsr", PCSR },
3174 { "psr", PSR },
3175 { "scc", SCC },
3176 { "val", VAL },
3177 { "bad0", BAD0 },
3178 { "bad1", BAD1 },
3179 { "bad2", BAD2 },
3180 { "bad3", BAD3 },
3181 { "bad4", BAD4 },
3182 { "bad5", BAD5 },
3183 { "bad6", BAD6 },
3184 { "bad7", BAD7 },
3185 { "bac0", BAC0 },
3186 { "bac1", BAC1 },
3187 { "bac2", BAC2 },
3188 { "bac3", BAC3 },
3189 { "bac4", BAC4 },
3190 { "bac5", BAC5 },
3191 { "bac6", BAC6 },
3192 { "bac7", BAC7 },
3193
3194 { "ic", IC },
3195 { "dc", DC },
3196 { "nc", NC },
3197
3198 { "tt0", TT0 },
3199 { "tt1", TT1 },
3200 /* 68ec030 versions of same */
3201 { "ac0", TT0 },
3202 { "ac1", TT1 },
3203 /* 68ec030 access control unit, identical to 030 MMU status reg */
3204 { "acusr", PSR },
3205
3206 /* Suppressed data and address registers. */
3207 { "zd0", ZDATA0 },
3208 { "zd1", ZDATA1 },
3209 { "zd2", ZDATA2 },
3210 { "zd3", ZDATA3 },
3211 { "zd4", ZDATA4 },
3212 { "zd5", ZDATA5 },
3213 { "zd6", ZDATA6 },
3214 { "zd7", ZDATA7 },
3215 { "za0", ZADDR0 },
3216 { "za1", ZADDR1 },
3217 { "za2", ZADDR2 },
3218 { "za3", ZADDR3 },
3219 { "za4", ZADDR4 },
3220 { "za5", ZADDR5 },
3221 { "za6", ZADDR6 },
3222 { "za7", ZADDR7 },
3223
3224 { 0, 0 }
3225 };
3226
3227 void
3228 init_regtable ()
3229 {
3230 int i;
3231 for (i = 0; init_table[i].name; i++)
3232 insert_reg (init_table[i].name, init_table[i].number);
3233 }
3234
3235 static int no_68851, no_68881;
3236
3237 #ifdef OBJ_AOUT
3238 /* a.out machine type. Default to 68020. */
3239 int m68k_aout_machtype = 2;
3240 #endif
3241
3242 void
3243 md_assemble (str)
3244 char *str;
3245 {
3246 const char *er;
3247 short *fromP;
3248 char *toP = NULL;
3249 int m, n = 0;
3250 char *to_beg_P;
3251 int shorts_this_frag;
3252 fixS *fixP;
3253
3254 /* In MRI mode, the instruction and operands are separated by a
3255 space. Anything following the operands is a comment. The label
3256 has already been removed. */
3257 if (flag_mri)
3258 {
3259 char *s;
3260 int fields = 0;
3261 int infield = 0;
3262 int inquote = 0;
3263
3264 for (s = str; *s != '\0'; s++)
3265 {
3266 if ((*s == ' ' || *s == '\t') && ! inquote)
3267 {
3268 if (infield)
3269 {
3270 ++fields;
3271 if (fields >= 2)
3272 {
3273 *s = '\0';
3274 break;
3275 }
3276 infield = 0;
3277 }
3278 }
3279 else
3280 {
3281 if (! infield)
3282 infield = 1;
3283 if (*s == '\'')
3284 inquote = ! inquote;
3285 }
3286 }
3287 }
3288
3289 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3290 m68k_ip (str);
3291 er = the_ins.error;
3292 if (!er)
3293 {
3294 for (n = 0; n < the_ins.numargs; n++)
3295 if (the_ins.operands[n].error)
3296 {
3297 er = the_ins.operands[n].error;
3298 break;
3299 }
3300 }
3301 if (er)
3302 {
3303 as_bad ("%s -- statement `%s' ignored", er, str);
3304 return;
3305 }
3306
3307 if (the_ins.nfrag == 0)
3308 {
3309 /* No frag hacking involved; just put it out */
3310 toP = frag_more (2 * the_ins.numo);
3311 fromP = &the_ins.opcode[0];
3312 for (m = the_ins.numo; m; --m)
3313 {
3314 md_number_to_chars (toP, (long) (*fromP), 2);
3315 toP += 2;
3316 fromP++;
3317 }
3318 /* put out symbol-dependent info */
3319 for (m = 0; m < the_ins.nrel; m++)
3320 {
3321 switch (the_ins.reloc[m].wid)
3322 {
3323 case 'B':
3324 n = 1;
3325 break;
3326 case 'b':
3327 n = 1;
3328 break;
3329 case '3':
3330 n = 1;
3331 break;
3332 case 'w':
3333 n = 2;
3334 break;
3335 case 'l':
3336 n = 4;
3337 break;
3338 default:
3339 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3340 the_ins.reloc[m].wid);
3341 }
3342
3343 fixP = fix_new_exp (frag_now,
3344 ((toP - frag_now->fr_literal)
3345 - the_ins.numo * 2 + the_ins.reloc[m].n),
3346 n,
3347 &the_ins.reloc[m].exp,
3348 the_ins.reloc[m].pcrel,
3349 get_reloc_code (n, the_ins.reloc[m].pcrel,
3350 the_ins.reloc[m].pic_reloc));
3351 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3352 if (the_ins.reloc[m].wid == 'B')
3353 fixP->fx_signed = 1;
3354 }
3355 return;
3356 }
3357
3358 /* There's some frag hacking */
3359 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3360 {
3361 int wid;
3362
3363 if (n == 0)
3364 wid = 2 * the_ins.fragb[n].fragoff;
3365 else
3366 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3367 toP = frag_more (wid);
3368 to_beg_P = toP;
3369 shorts_this_frag = 0;
3370 for (m = wid / 2; m; --m)
3371 {
3372 md_number_to_chars (toP, (long) (*fromP), 2);
3373 toP += 2;
3374 fromP++;
3375 shorts_this_frag++;
3376 }
3377 for (m = 0; m < the_ins.nrel; m++)
3378 {
3379 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3380 {
3381 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3382 break;
3383 }
3384 wid = the_ins.reloc[m].wid;
3385 if (wid == 0)
3386 continue;
3387 the_ins.reloc[m].wid = 0;
3388 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3389
3390 fixP = fix_new_exp (frag_now,
3391 ((toP - frag_now->fr_literal)
3392 - the_ins.numo * 2 + the_ins.reloc[m].n),
3393 wid,
3394 &the_ins.reloc[m].exp,
3395 the_ins.reloc[m].pcrel,
3396 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3397 the_ins.reloc[m].pic_reloc));
3398 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3399 }
3400 (void) frag_var (rs_machine_dependent, 10, 0,
3401 (relax_substateT) (the_ins.fragb[n].fragty),
3402 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3403 }
3404 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3405 shorts_this_frag = 0;
3406 if (n)
3407 {
3408 toP = frag_more (n * sizeof (short));
3409 while (n--)
3410 {
3411 md_number_to_chars (toP, (long) (*fromP), 2);
3412 toP += 2;
3413 fromP++;
3414 shorts_this_frag++;
3415 }
3416 }
3417 for (m = 0; m < the_ins.nrel; m++)
3418 {
3419 int wid;
3420
3421 wid = the_ins.reloc[m].wid;
3422 if (wid == 0)
3423 continue;
3424 the_ins.reloc[m].wid = 0;
3425 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3426
3427 fixP = fix_new_exp (frag_now,
3428 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3429 - shorts_this_frag * 2),
3430 wid,
3431 &the_ins.reloc[m].exp,
3432 the_ins.reloc[m].pcrel,
3433 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3434 the_ins.reloc[m].pic_reloc));
3435 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3436 }
3437 }
3438
3439 void
3440 md_begin ()
3441 {
3442 /*
3443 * md_begin -- set up hash tables with 68000 instructions.
3444 * similar to what the vax assembler does. ---phr
3445 */
3446 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3447 a copy of it at runtime, adding in the information we want but isn't
3448 there. I think it'd be better to have an awk script hack the table
3449 at compile time. Or even just xstr the table and use it as-is. But
3450 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3451 names. */
3452
3453 register const struct m68k_opcode *ins;
3454 register struct m68k_incant *hack, *slak;
3455 register const char *retval = 0; /* empty string, or error msg text */
3456 register unsigned int i;
3457 register char c;
3458
3459 if (flag_mri)
3460 {
3461 flag_reg_prefix_optional = 1;
3462 m68k_abspcadd = 1;
3463 if (! m68k_rel32_from_cmdline)
3464 m68k_rel32 = 0;
3465 }
3466
3467 op_hash = hash_new ();
3468
3469 obstack_begin (&robyn, 4000);
3470 for (i = 0; i < m68k_numopcodes; i++)
3471 {
3472 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3473 do
3474 {
3475 ins = &m68k_opcodes[i];
3476 /* We *could* ignore insns that don't match our arch here
3477 but just leaving them out of the hash. */
3478 slak->m_operands = ins->args;
3479 slak->m_opnum = strlen (slak->m_operands) / 2;
3480 slak->m_arch = ins->arch;
3481 slak->m_opcode = ins->opcode;
3482 /* This is kludgey */
3483 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3484 if (i + 1 != m68k_numopcodes
3485 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3486 {
3487 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3488 i++;
3489 }
3490 else
3491 slak->m_next = 0;
3492 slak = slak->m_next;
3493 }
3494 while (slak);
3495
3496 retval = hash_insert (op_hash, ins->name, (char *) hack);
3497 if (retval)
3498 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3499 }
3500
3501 for (i = 0; i < m68k_numaliases; i++)
3502 {
3503 const char *name = m68k_opcode_aliases[i].primary;
3504 const char *alias = m68k_opcode_aliases[i].alias;
3505 PTR val = hash_find (op_hash, name);
3506 if (!val)
3507 as_fatal ("Internal Error: Can't find %s in hash table", name);
3508 retval = hash_insert (op_hash, alias, val);
3509 if (retval)
3510 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3511 }
3512
3513 /* In MRI mode, all unsized branches are variable sized. Normally,
3514 they are word sized. */
3515 if (flag_mri)
3516 {
3517 static struct m68k_opcode_alias mri_aliases[] =
3518 {
3519 { "bhi", "jhi", },
3520 { "bls", "jls", },
3521 { "bcc", "jcc", },
3522 { "bcs", "jcs", },
3523 { "bne", "jne", },
3524 { "beq", "jeq", },
3525 { "bvc", "jvc", },
3526 { "bvs", "jvs", },
3527 { "bpl", "jpl", },
3528 { "bmi", "jmi", },
3529 { "bge", "jge", },
3530 { "blt", "jlt", },
3531 { "bgt", "jgt", },
3532 { "ble", "jle", },
3533 { "bra", "jra", },
3534 { "bsr", "jbsr", },
3535 };
3536
3537 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3538 {
3539 const char *name = mri_aliases[i].primary;
3540 const char *alias = mri_aliases[i].alias;
3541 PTR val = hash_find (op_hash, name);
3542 if (!val)
3543 as_fatal ("Internal Error: Can't find %s in hash table", name);
3544 retval = hash_jam (op_hash, alias, val);
3545 if (retval)
3546 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3547 }
3548 }
3549
3550 for (i = 0; i < sizeof (mklower_table); i++)
3551 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3552
3553 for (i = 0; i < sizeof (notend_table); i++)
3554 {
3555 notend_table[i] = 0;
3556 alt_notend_table[i] = 0;
3557 }
3558 notend_table[','] = 1;
3559 notend_table['{'] = 1;
3560 notend_table['}'] = 1;
3561 alt_notend_table['a'] = 1;
3562 alt_notend_table['A'] = 1;
3563 alt_notend_table['d'] = 1;
3564 alt_notend_table['D'] = 1;
3565 alt_notend_table['#'] = 1;
3566 alt_notend_table['&'] = 1;
3567 alt_notend_table['f'] = 1;
3568 alt_notend_table['F'] = 1;
3569 #ifdef REGISTER_PREFIX
3570 alt_notend_table[REGISTER_PREFIX] = 1;
3571 #endif
3572
3573 /* We need to put '(' in alt_notend_table to handle
3574 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3575 */
3576 alt_notend_table['('] = 1;
3577
3578 /* We need to put '@' in alt_notend_table to handle
3579 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3580 */
3581 alt_notend_table['@'] = 1;
3582
3583 /* We need to put digits in alt_notend_table to handle
3584 bfextu %d0{24:1},%d0
3585 */
3586 alt_notend_table['0'] = 1;
3587 alt_notend_table['1'] = 1;
3588 alt_notend_table['2'] = 1;
3589 alt_notend_table['3'] = 1;
3590 alt_notend_table['4'] = 1;
3591 alt_notend_table['5'] = 1;
3592 alt_notend_table['6'] = 1;
3593 alt_notend_table['7'] = 1;
3594 alt_notend_table['8'] = 1;
3595 alt_notend_table['9'] = 1;
3596
3597 #ifndef MIT_SYNTAX_ONLY
3598 /* Insert pseudo ops, these have to go into the opcode table since
3599 gas expects pseudo ops to start with a dot */
3600 {
3601 int n = 0;
3602 while (mote_pseudo_table[n].poc_name)
3603 {
3604 hack = (struct m68k_incant *)
3605 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3606 hash_insert (op_hash,
3607 mote_pseudo_table[n].poc_name, (char *) hack);
3608 hack->m_operands = 0;
3609 hack->m_opnum = n;
3610 n++;
3611 }
3612 }
3613 #endif
3614
3615 init_regtable ();
3616
3617 #ifdef OBJ_ELF
3618 record_alignment (text_section, 2);
3619 record_alignment (data_section, 2);
3620 record_alignment (bss_section, 2);
3621 #endif
3622 }
3623
3624 static void
3625 select_control_regs ()
3626 {
3627 /* Note which set of "movec" control registers is available. */
3628 switch (cpu_of_arch (current_architecture))
3629 {
3630 case m68000:
3631 control_regs = m68000_control_regs;
3632 break;
3633 case m68010:
3634 control_regs = m68010_control_regs;
3635 break;
3636 case m68020:
3637 case m68030:
3638 control_regs = m68020_control_regs;
3639 break;
3640 case m68040:
3641 control_regs = m68040_control_regs;
3642 break;
3643 case m68060:
3644 control_regs = m68060_control_regs;
3645 break;
3646 case cpu32:
3647 control_regs = cpu32_control_regs;
3648 break;
3649 case mcf5200:
3650 control_regs = mcf5200_control_regs;
3651 break;
3652 default:
3653 abort ();
3654 }
3655 }
3656
3657 void
3658 m68k_init_after_args ()
3659 {
3660 if (cpu_of_arch (current_architecture) == 0)
3661 {
3662 int i;
3663 const char *default_cpu = TARGET_CPU;
3664
3665 if (*default_cpu == 'm')
3666 default_cpu++;
3667 for (i = 0; i < n_archs; i++)
3668 if (strcasecmp (default_cpu, archs[i].name) == 0)
3669 break;
3670 if (i == n_archs)
3671 {
3672 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3673 current_architecture |= m68020;
3674 }
3675 else
3676 current_architecture |= archs[i].arch;
3677 }
3678 /* Permit m68881 specification with all cpus; those that can't work
3679 with a coprocessor could be doing emulation. */
3680 if (current_architecture & m68851)
3681 {
3682 if (current_architecture & m68040)
3683 {
3684 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3685 }
3686 }
3687 /* What other incompatibilities could we check for? */
3688
3689 /* Toss in some default assumptions about coprocessors. */
3690 if (!no_68881
3691 && (cpu_of_arch (current_architecture)
3692 /* Can CPU32 have a 68881 coprocessor?? */
3693 & (m68020 | m68030 | cpu32)))
3694 {
3695 current_architecture |= m68881;
3696 }
3697 if (!no_68851
3698 && (cpu_of_arch (current_architecture) & m68020up) != 0
3699 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3700 {
3701 current_architecture |= m68851;
3702 }
3703 if (no_68881 && (current_architecture & m68881))
3704 as_bad ("options for 68881 and no-68881 both given");
3705 if (no_68851 && (current_architecture & m68851))
3706 as_bad ("options for 68851 and no-68851 both given");
3707
3708 #ifdef OBJ_AOUT
3709 /* Work out the magic number. This isn't very general. */
3710 if (current_architecture & m68000)
3711 m68k_aout_machtype = 0;
3712 else if (current_architecture & m68010)
3713 m68k_aout_machtype = 1;
3714 else if (current_architecture & m68020)
3715 m68k_aout_machtype = 2;
3716 else
3717 m68k_aout_machtype = 2;
3718 #endif
3719
3720 /* Note which set of "movec" control registers is available. */
3721 select_control_regs ();
3722
3723 if (cpu_of_arch (current_architecture) < m68020)
3724 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3725 }
3726
3727 /* This is called if we go in or out of MRI mode because of the .mri
3728 pseudo-op. */
3729
3730 void
3731 m68k_mri_mode_change (on)
3732 int on;
3733 {
3734 if (on)
3735 {
3736 if (! flag_reg_prefix_optional)
3737 {
3738 flag_reg_prefix_optional = 1;
3739 #ifdef REGISTER_PREFIX
3740 init_regtable ();
3741 #endif
3742 }
3743 m68k_abspcadd = 1;
3744 if (! m68k_rel32_from_cmdline)
3745 m68k_rel32 = 0;
3746 }
3747 else
3748 {
3749 if (! reg_prefix_optional_seen)
3750 {
3751 #ifdef REGISTER_PREFIX_OPTIONAL
3752 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3753 #else
3754 flag_reg_prefix_optional = 0;
3755 #endif
3756 #ifdef REGISTER_PREFIX
3757 init_regtable ();
3758 #endif
3759 }
3760 m68k_abspcadd = 0;
3761 if (! m68k_rel32_from_cmdline)
3762 m68k_rel32 = 1;
3763 }
3764 }
3765
3766 /* Equal to MAX_PRECISION in atof-ieee.c */
3767 #define MAX_LITTLENUMS 6
3768
3769 /* Turn a string in input_line_pointer into a floating point constant
3770 of type type, and store the appropriate bytes in *litP. The number
3771 of LITTLENUMS emitted is stored in *sizeP . An error message is
3772 returned, or NULL on OK. */
3773
3774 char *
3775 md_atof (type, litP, sizeP)
3776 char type;
3777 char *litP;
3778 int *sizeP;
3779 {
3780 int prec;
3781 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3782 LITTLENUM_TYPE *wordP;
3783 char *t;
3784 char *atof_ieee ();
3785
3786 switch (type)
3787 {
3788 case 'f':
3789 case 'F':
3790 case 's':
3791 case 'S':
3792 prec = 2;
3793 break;
3794
3795 case 'd':
3796 case 'D':
3797 case 'r':
3798 case 'R':
3799 prec = 4;
3800 break;
3801
3802 case 'x':
3803 case 'X':
3804 prec = 6;
3805 break;
3806
3807 case 'p':
3808 case 'P':
3809 prec = 6;
3810 break;
3811
3812 default:
3813 *sizeP = 0;
3814 return "Bad call to MD_ATOF()";
3815 }
3816 t = atof_ieee (input_line_pointer, type, words);
3817 if (t)
3818 input_line_pointer = t;
3819
3820 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3821 for (wordP = words; prec--;)
3822 {
3823 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3824 litP += sizeof (LITTLENUM_TYPE);
3825 }
3826 return 0;
3827 }
3828
3829 void
3830 md_number_to_chars (buf, val, n)
3831 char *buf;
3832 valueT val;
3833 int n;
3834 {
3835 number_to_chars_bigendian (buf, val, n);
3836 }
3837
3838 static void
3839 md_apply_fix_2 (fixP, val)
3840 fixS *fixP;
3841 offsetT val;
3842 {
3843 addressT upper_limit;
3844 offsetT lower_limit;
3845
3846 /* This is unnecessary but it convinces the native rs6000 compiler
3847 to generate the code we want. */
3848 char *buf = fixP->fx_frag->fr_literal;
3849 buf += fixP->fx_where;
3850 /* end ibm compiler workaround */
3851
3852 if (val & 0x80000000)
3853 val |= ~(addressT)0x7fffffff;
3854 else
3855 val &= 0x7fffffff;
3856
3857 #ifdef OBJ_ELF
3858 if (fixP->fx_addsy)
3859 {
3860 memset (buf, 0, fixP->fx_size);
3861 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3862 return;
3863 }
3864 #endif
3865
3866 switch (fixP->fx_size)
3867 {
3868 /* The cast to offsetT below are necessary to make code correct for
3869 machines where ints are smaller than offsetT */
3870 case 1:
3871 *buf++ = val;
3872 upper_limit = 0x7f;
3873 lower_limit = - (offsetT) 0x80;
3874 break;
3875 case 2:
3876 *buf++ = (val >> 8);
3877 *buf++ = val;
3878 upper_limit = 0x7fff;
3879 lower_limit = - (offsetT) 0x8000;
3880 break;
3881 case 4:
3882 *buf++ = (val >> 24);
3883 *buf++ = (val >> 16);
3884 *buf++ = (val >> 8);
3885 *buf++ = val;
3886 upper_limit = 0x7fffffff;
3887 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3888 break;
3889 default:
3890 BAD_CASE (fixP->fx_size);
3891 }
3892
3893 /* Fix up a negative reloc. */
3894 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3895 {
3896 fixP->fx_addsy = fixP->fx_subsy;
3897 fixP->fx_subsy = NULL;
3898 fixP->fx_tcbit = 1;
3899 }
3900
3901 /* For non-pc-relative values, it's conceivable we might get something
3902 like "0xff" for a byte field. So extend the upper part of the range
3903 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3904 so that we can do any range checking at all. */
3905 if (! fixP->fx_pcrel && ! fixP->fx_signed)
3906 upper_limit = upper_limit * 2 + 1;
3907
3908 if ((addressT) val > upper_limit
3909 && (val > 0 || val < lower_limit))
3910 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3911
3912 /* A one byte PC-relative reloc means a short branch. We can't use
3913 a short branch with a value of 0 or -1, because those indicate
3914 different opcodes (branches with longer offsets). */
3915 if (fixP->fx_pcrel
3916 && fixP->fx_size == 1
3917 && (fixP->fx_addsy == NULL
3918 || S_IS_DEFINED (fixP->fx_addsy))
3919 && (val == 0 || val == -1))
3920 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3921 }
3922
3923 #ifdef BFD_ASSEMBLER
3924 int
3925 md_apply_fix (fixP, valp)
3926 fixS *fixP;
3927 valueT *valp;
3928 {
3929 md_apply_fix_2 (fixP, (addressT) *valp);
3930 return 1;
3931 }
3932 #else
3933 void md_apply_fix (fixP, val)
3934 fixS *fixP;
3935 long val;
3936 {
3937 md_apply_fix_2 (fixP, (addressT) val);
3938 }
3939 #endif
3940
3941 /* *fragP has been relaxed to its final size, and now needs to have
3942 the bytes inside it modified to conform to the new size There is UGLY
3943 MAGIC here. ..
3944 */
3945 void
3946 md_convert_frag_1 (fragP)
3947 register fragS *fragP;
3948 {
3949 long disp;
3950 long ext = 0;
3951 fixS *fixP;
3952
3953 /* Address in object code of the displacement. */
3954 register int object_address = fragP->fr_fix + fragP->fr_address;
3955
3956 /* Address in gas core of the place to store the displacement. */
3957 /* This convinces the native rs6000 compiler to generate the code we
3958 want. */
3959 register char *buffer_address = fragP->fr_literal;
3960 buffer_address += fragP->fr_fix;
3961 /* end ibm compiler workaround */
3962
3963 /* The displacement of the address, from current location. */
3964 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3965 disp = (disp + fragP->fr_offset) - object_address;
3966
3967 #ifdef BFD_ASSEMBLER
3968 disp += fragP->fr_symbol->sy_frag->fr_address;
3969 #endif
3970
3971 switch (fragP->fr_subtype)
3972 {
3973 case TAB (BCC68000, BYTE):
3974 case TAB (ABRANCH, BYTE):
3975 know (issbyte (disp));
3976 if (disp == 0)
3977 as_bad ("short branch with zero offset: use :w");
3978 fragP->fr_opcode[1] = disp;
3979 ext = 0;
3980 break;
3981 case TAB (DBCC, SHORT):
3982 know (issword (disp));
3983 ext = 2;
3984 break;
3985 case TAB (BCC68000, SHORT):
3986 case TAB (ABRANCH, SHORT):
3987 know (issword (disp));
3988 fragP->fr_opcode[1] = 0x00;
3989 ext = 2;
3990 break;
3991 case TAB (ABRANCH, LONG):
3992 if (cpu_of_arch (current_architecture) < m68020)
3993 {
3994 if (fragP->fr_opcode[0] == 0x61)
3995 /* BSR */
3996 {
3997 fragP->fr_opcode[0] = 0x4E;
3998 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3999
4000 fix_new (fragP,
4001 fragP->fr_fix,
4002 4,
4003 fragP->fr_symbol,
4004 fragP->fr_offset,
4005 0,
4006 NO_RELOC);
4007
4008 fragP->fr_fix += 4;
4009 ext = 0;
4010 }
4011 /* BRA */
4012 else if (fragP->fr_opcode[0] == 0x60)
4013 {
4014 fragP->fr_opcode[0] = 0x4E;
4015 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4016 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4017 fragP->fr_offset, 0, NO_RELOC);
4018 fragP->fr_fix += 4;
4019 ext = 0;
4020 }
4021 else
4022 {
4023 as_bad ("Long branch offset not supported.");
4024 }
4025 }
4026 else
4027 {
4028 fragP->fr_opcode[1] = (char) 0xff;
4029 ext = 4;
4030 }
4031 break;
4032 case TAB (BCC68000, LONG):
4033 /* only Bcc 68000 instructions can come here */
4034 /* change bcc into b!cc/jmp absl long */
4035 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4036 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4037
4038 /* JF: these used to be fr_opcode[2,3], but they may be in a
4039 different frag, in which case refering to them is a no-no.
4040 Only fr_opcode[0,1] are guaranteed to work. */
4041 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4042 *buffer_address++ = (char) 0xf9;
4043 fragP->fr_fix += 2; /* account for jmp instruction */
4044 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4045 fragP->fr_offset, 0, NO_RELOC);
4046 fragP->fr_fix += 4;
4047 ext = 0;
4048 break;
4049 case TAB (DBCC, LONG):
4050 /* only DBcc 68000 instructions can come here */
4051 /* change dbcc into dbcc/jmp absl long */
4052 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4053 *buffer_address++ = 0x00; /* branch offset = 4 */
4054 *buffer_address++ = 0x04;
4055 *buffer_address++ = 0x60; /* put in bra pc+6 */
4056 *buffer_address++ = 0x06;
4057 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4058 *buffer_address++ = (char) 0xf9;
4059
4060 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4061 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4062 fragP->fr_offset, 0, NO_RELOC);
4063 fragP->fr_fix += 4;
4064 ext = 0;
4065 break;
4066 case TAB (FBRANCH, SHORT):
4067 know ((fragP->fr_opcode[1] & 0x40) == 0);
4068 ext = 2;
4069 break;
4070 case TAB (FBRANCH, LONG):
4071 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4072 ext = 4;
4073 break;
4074 case TAB (PCREL, SHORT):
4075 ext = 2;
4076 break;
4077 case TAB (PCREL, LONG):
4078 /* The thing to do here is force it to ABSOLUTE LONG, since
4079 PCREL is really trying to shorten an ABSOLUTE address anyway */
4080 /* JF FOO This code has not been tested */
4081 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4082 0, NO_RELOC);
4083 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4084 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4085 (unsigned) fragP->fr_opcode[0],
4086 (unsigned long) fragP->fr_address);
4087 fragP->fr_opcode[1] &= ~0x3F;
4088 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4089 fragP->fr_fix += 4;
4090 ext = 0;
4091 break;
4092 case TAB (PCLEA, SHORT):
4093 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4094 fragP->fr_offset, 1, NO_RELOC);
4095 fragP->fr_opcode[1] &= ~0x3F;
4096 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4097 ext = 2;
4098 break;
4099 case TAB (PCLEA, LONG):
4100 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4101 fragP->fr_offset, 1, NO_RELOC);
4102 fixP->fx_pcrel_adjust = 2;
4103 /* Already set to mode 7.3; this indicates: PC indirect with
4104 suppressed index, 32-bit displacement. */
4105 *buffer_address++ = 0x01;
4106 *buffer_address++ = 0x70;
4107 fragP->fr_fix += 2;
4108 ext = 4;
4109 break;
4110
4111 case TAB (PCINDEX, BYTE):
4112 disp += 2;
4113 if (!issbyte (disp))
4114 {
4115 as_bad ("displacement doesn't fit in one byte");
4116 disp = 0;
4117 }
4118 assert (fragP->fr_fix >= 2);
4119 buffer_address[-2] &= ~1;
4120 buffer_address[-1] = disp;
4121 ext = 0;
4122 break;
4123 case TAB (PCINDEX, SHORT):
4124 disp += 2;
4125 assert (issword (disp));
4126 assert (fragP->fr_fix >= 2);
4127 buffer_address[-2] |= 0x1;
4128 buffer_address[-1] = 0x20;
4129 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4130 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4131 NO_RELOC);
4132 fixP->fx_pcrel_adjust = 2;
4133 ext = 2;
4134 break;
4135 case TAB (PCINDEX, LONG):
4136 disp += 2;
4137 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4138 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4139 NO_RELOC);
4140 fixP->fx_pcrel_adjust = 2;
4141 assert (fragP->fr_fix >= 2);
4142 buffer_address[-2] |= 0x1;
4143 buffer_address[-1] = 0x30;
4144 ext = 4;
4145 break;
4146 }
4147
4148 if (ext)
4149 {
4150 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4151 fragP->fr_fix += ext;
4152 }
4153 }
4154
4155 #ifndef BFD_ASSEMBLER
4156
4157 void
4158 md_convert_frag (headers, sec, fragP)
4159 object_headers *headers;
4160 segT sec;
4161 fragS *fragP;
4162 {
4163 md_convert_frag_1 (fragP);
4164 }
4165
4166 #else
4167
4168 void
4169 md_convert_frag (abfd, sec, fragP)
4170 bfd *abfd;
4171 segT sec;
4172 fragS *fragP;
4173 {
4174 md_convert_frag_1 (fragP);
4175 }
4176 #endif
4177
4178 /* Force truly undefined symbols to their maximum size, and generally set up
4179 the frag list to be relaxed
4180 */
4181 int
4182 md_estimate_size_before_relax (fragP, segment)
4183 register fragS *fragP;
4184 segT segment;
4185 {
4186 int old_fix;
4187 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4188
4189 old_fix = fragP->fr_fix;
4190
4191 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4192 switch (fragP->fr_subtype)
4193 {
4194
4195 case TAB (ABRANCH, SZ_UNDEF):
4196 {
4197 if ((fragP->fr_symbol != NULL) /* Not absolute */
4198 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4199 {
4200 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4201 break;
4202 }
4203 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4204 {
4205 /* On 68000, or for absolute value, switch to abs long */
4206 /* FIXME, we should check abs val, pick short or long */
4207 if (fragP->fr_opcode[0] == 0x61)
4208 {
4209 fragP->fr_opcode[0] = 0x4E;
4210 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4211 fix_new (fragP, fragP->fr_fix, 4,
4212 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4213 fragP->fr_fix += 4;
4214 frag_wane (fragP);
4215 }
4216 else if (fragP->fr_opcode[0] == 0x60)
4217 {
4218 fragP->fr_opcode[0] = 0x4E;
4219 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4220 fix_new (fragP, fragP->fr_fix, 4,
4221 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4222 fragP->fr_fix += 4;
4223 frag_wane (fragP);
4224 }
4225 else
4226 {
4227 as_warn ("Long branch offset to extern symbol not supported.");
4228 }
4229 }
4230 else
4231 { /* Symbol is still undefined. Make it simple */
4232 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4233 fragP->fr_offset, 1, NO_RELOC);
4234 fragP->fr_fix += 4;
4235 fragP->fr_opcode[1] = (char) 0xff;
4236 frag_wane (fragP);
4237 break;
4238 }
4239
4240 break;
4241 } /* case TAB(ABRANCH,SZ_UNDEF) */
4242
4243 case TAB (FBRANCH, SZ_UNDEF):
4244 {
4245 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4246 {
4247 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4248 fragP->fr_var += 2;
4249 }
4250 else
4251 {
4252 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4253 fragP->fr_offset, 1, NO_RELOC);
4254 fragP->fr_fix += 4;
4255 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4256 frag_wane (fragP);
4257 }
4258 break;
4259 } /* TAB(FBRANCH,SZ_UNDEF) */
4260
4261 case TAB (PCREL, SZ_UNDEF):
4262 {
4263 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4264 || flag_short_refs
4265 || cpu_of_arch (current_architecture) < m68020)
4266 {
4267 fragP->fr_subtype = TAB (PCREL, SHORT);
4268 fragP->fr_var += 2;
4269 }
4270 else
4271 {
4272 fragP->fr_subtype = TAB (PCREL, LONG);
4273 fragP->fr_var += 4;
4274 }
4275 break;
4276 } /* TAB(PCREL,SZ_UNDEF) */
4277
4278 case TAB (BCC68000, SZ_UNDEF):
4279 {
4280 if ((fragP->fr_symbol != NULL)
4281 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4282 {
4283 fragP->fr_subtype = TAB (BCC68000, BYTE);
4284 break;
4285 }
4286 /* only Bcc 68000 instructions can come here */
4287 /* change bcc into b!cc/jmp absl long */
4288 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4289 if (flag_short_refs)
4290 {
4291 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4292 /* JF: these were fr_opcode[2,3] */
4293 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4294 buffer_address[1] = (char) 0xf8;
4295 fragP->fr_fix += 2; /* account for jmp instruction */
4296 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4297 fragP->fr_offset, 0, NO_RELOC);
4298 fragP->fr_fix += 2;
4299 }
4300 else
4301 {
4302 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4303 /* JF: these were fr_opcode[2,3] */
4304 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4305 buffer_address[1] = (char) 0xf9;
4306 fragP->fr_fix += 2; /* account for jmp instruction */
4307 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4308 fragP->fr_offset, 0, NO_RELOC);
4309 fragP->fr_fix += 4;
4310 }
4311 frag_wane (fragP);
4312 break;
4313 } /* case TAB(BCC68000,SZ_UNDEF) */
4314
4315 case TAB (DBCC, SZ_UNDEF):
4316 {
4317 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4318 {
4319 fragP->fr_subtype = TAB (DBCC, SHORT);
4320 fragP->fr_var += 2;
4321 break;
4322 }
4323 /* only DBcc 68000 instructions can come here */
4324 /* change dbcc into dbcc/jmp absl long */
4325 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4326 buffer_address[0] = 0x00; /* branch offset = 4 */
4327 buffer_address[1] = 0x04;
4328 buffer_address[2] = 0x60; /* put in bra pc + ... */
4329
4330 if (flag_short_refs)
4331 {
4332 /* JF: these were fr_opcode[5-7] */
4333 buffer_address[3] = 0x04; /* plus 4 */
4334 buffer_address[4] = 0x4e; /* Put in Jump Word */
4335 buffer_address[5] = (char) 0xf8;
4336 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4337 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4338 fragP->fr_offset, 0, NO_RELOC);
4339 fragP->fr_fix += 2;
4340 }
4341 else
4342 {
4343 /* JF: these were fr_opcode[5-7] */
4344 buffer_address[3] = 0x06; /* Plus 6 */
4345 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4346 buffer_address[5] = (char) 0xf9;
4347 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4348 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4349 fragP->fr_offset, 0, NO_RELOC);
4350 fragP->fr_fix += 4;
4351 }
4352
4353 frag_wane (fragP);
4354 break;
4355 } /* case TAB(DBCC,SZ_UNDEF) */
4356
4357 case TAB (PCLEA, SZ_UNDEF):
4358 {
4359 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4360 || flag_short_refs
4361 || cpu_of_arch (current_architecture) < m68020)
4362 {
4363 fragP->fr_subtype = TAB (PCLEA, SHORT);
4364 fragP->fr_var += 2;
4365 }
4366 else
4367 {
4368 fragP->fr_subtype = TAB (PCLEA, LONG);
4369 fragP->fr_var += 6;
4370 }
4371 break;
4372 } /* TAB(PCLEA,SZ_UNDEF) */
4373
4374 case TAB (PCINDEX, SZ_UNDEF):
4375 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4376 || cpu_of_arch (current_architecture) < m68020)
4377 {
4378 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4379 }
4380 else
4381 {
4382 fragP->fr_subtype = TAB (PCINDEX, LONG);
4383 fragP->fr_var += 4;
4384 }
4385 break;
4386
4387 default:
4388 break;
4389 }
4390
4391 /* now that SZ_UNDEF are taken care of, check others */
4392 switch (fragP->fr_subtype)
4393 {
4394 case TAB (BCC68000, BYTE):
4395 case TAB (ABRANCH, BYTE):
4396 /* We can't do a short jump to the next instruction, so in that
4397 case we force word mode. At this point S_GET_VALUE should
4398 return the offset of the symbol within its frag. If the
4399 symbol is at the start of a frag, and it is the next frag
4400 with any data in it (usually this is just the next frag, but
4401 assembler listings may introduce empty frags), we must use
4402 word mode. */
4403 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4404 {
4405 fragS *l;
4406
4407 for (l = fragP->fr_next;
4408 l != fragP->fr_symbol->sy_frag;
4409 l = l->fr_next)
4410 if (l->fr_fix + l->fr_var != 0)
4411 break;
4412 if (l == fragP->fr_symbol->sy_frag)
4413 {
4414 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4415 fragP->fr_var += 2;
4416 }
4417 }
4418 break;
4419 default:
4420 break;
4421 }
4422 return fragP->fr_var + fragP->fr_fix - old_fix;
4423 }
4424
4425 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4426 /* the bit-field entries in the relocation_info struct plays hell
4427 with the byte-order problems of cross-assembly. So as a hack,
4428 I added this mach. dependent ri twiddler. Ugly, but it gets
4429 you there. -KWK */
4430 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4431 are symbolnum, most sig. byte first. Last byte is broken up with
4432 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4433 nibble as nuthin. (on Sun 3 at least) */
4434 /* Translate the internal relocation information into target-specific
4435 format. */
4436 #ifdef comment
4437 void
4438 md_ri_to_chars (the_bytes, ri)
4439 char *the_bytes;
4440 struct reloc_info_generic *ri;
4441 {
4442 /* this is easy */
4443 md_number_to_chars (the_bytes, ri->r_address, 4);
4444 /* now the fun stuff */
4445 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4446 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4447 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4448 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4449 ((ri->r_extern << 4) & 0x10));
4450 }
4451
4452 #endif /* comment */
4453
4454 #ifndef BFD_ASSEMBLER
4455 void
4456 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4457 char *where;
4458 fixS *fixP;
4459 relax_addressT segment_address_in_file;
4460 {
4461 /*
4462 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4463 * Out: GNU LD relocation length code: 0, 1, or 2.
4464 */
4465
4466 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4467 long r_symbolnum;
4468
4469 know (fixP->fx_addsy != NULL);
4470
4471 md_number_to_chars (where,
4472 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4473 4);
4474
4475 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4476 ? S_GET_TYPE (fixP->fx_addsy)
4477 : fixP->fx_addsy->sy_number);
4478
4479 where[4] = (r_symbolnum >> 16) & 0x0ff;
4480 where[5] = (r_symbolnum >> 8) & 0x0ff;
4481 where[6] = r_symbolnum & 0x0ff;
4482 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4483 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4484 }
4485 #endif
4486
4487 #endif /* OBJ_AOUT or OBJ_BOUT */
4488
4489 #ifndef WORKING_DOT_WORD
4490 CONST int md_short_jump_size = 4;
4491 CONST int md_long_jump_size = 6;
4492
4493 void
4494 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4495 char *ptr;
4496 addressT from_addr, to_addr;
4497 fragS *frag;
4498 symbolS *to_symbol;
4499 {
4500 valueT offset;
4501
4502 offset = to_addr - (from_addr + 2);
4503
4504 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4505 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4506 }
4507
4508 void
4509 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4510 char *ptr;
4511 addressT from_addr, to_addr;
4512 fragS *frag;
4513 symbolS *to_symbol;
4514 {
4515 valueT offset;
4516
4517 if (cpu_of_arch (current_architecture) < m68020)
4518 {
4519 offset = to_addr - S_GET_VALUE (to_symbol);
4520 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4521 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4522 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4523 0, NO_RELOC);
4524 }
4525 else
4526 {
4527 offset = to_addr - (from_addr + 2);
4528 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4529 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4530 }
4531 }
4532
4533 #endif
4534
4535 /* Different values of OK tell what its OK to return. Things that
4536 aren't OK are an error (what a shock, no?)
4537
4538 0: Everything is OK
4539 10: Absolute 1:8 only
4540 20: Absolute 0:7 only
4541 30: absolute 0:15 only
4542 40: Absolute 0:31 only
4543 50: absolute 0:127 only
4544 55: absolute -64:63 only
4545 60: absolute -128:127 only
4546 70: absolute 0:4095 only
4547 80: No bignums
4548
4549 */
4550
4551 static int
4552 get_num (exp, ok)
4553 struct m68k_exp *exp;
4554 int ok;
4555 {
4556 if (exp->exp.X_op == O_absent)
4557 {
4558 /* Do the same thing the VAX asm does */
4559 op (exp) = O_constant;
4560 adds (exp) = 0;
4561 subs (exp) = 0;
4562 offs (exp) = 0;
4563 if (ok == 10)
4564 {
4565 as_warn ("expression out of range: defaulting to 1");
4566 offs (exp) = 1;
4567 }
4568 }
4569 else if (exp->exp.X_op == O_constant)
4570 {
4571 switch (ok)
4572 {
4573 case 10:
4574 if (offs (exp) < 1 || offs (exp) > 8)
4575 {
4576 as_warn ("expression out of range: defaulting to 1");
4577 offs (exp) = 1;
4578 }
4579 break;
4580 case 20:
4581 if (offs (exp) < 0 || offs (exp) > 7)
4582 goto outrange;
4583 break;
4584 case 30:
4585 if (offs (exp) < 0 || offs (exp) > 15)
4586 goto outrange;
4587 break;
4588 case 40:
4589 if (offs (exp) < 0 || offs (exp) > 32)
4590 goto outrange;
4591 break;
4592 case 50:
4593 if (offs (exp) < 0 || offs (exp) > 127)
4594 goto outrange;
4595 break;
4596 case 55:
4597 if (offs (exp) < -64 || offs (exp) > 63)
4598 goto outrange;
4599 break;
4600 case 60:
4601 if (offs (exp) < -128 || offs (exp) > 127)
4602 goto outrange;
4603 break;
4604 case 70:
4605 if (offs (exp) < 0 || offs (exp) > 4095)
4606 {
4607 outrange:
4608 as_warn ("expression out of range: defaulting to 0");
4609 offs (exp) = 0;
4610 }
4611 break;
4612 default:
4613 break;
4614 }
4615 }
4616 else if (exp->exp.X_op == O_big)
4617 {
4618 if (offs (exp) <= 0 /* flonum */
4619 && (ok == 80 /* no bignums */
4620 || (ok > 10 /* small-int ranges including 0 ok */
4621 /* If we have a flonum zero, a zero integer should
4622 do as well (e.g., in moveq). */
4623 && generic_floating_point_number.exponent == 0
4624 && generic_floating_point_number.low[0] == 0)))
4625 {
4626 /* HACK! Turn it into a long */
4627 LITTLENUM_TYPE words[6];
4628
4629 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4630 op (exp) = O_constant;
4631 adds (exp) = 0;
4632 subs (exp) = 0;
4633 offs (exp) = words[1] | (words[0] << 16);
4634 }
4635 else if (ok != 0)
4636 {
4637 op (exp) = O_constant;
4638 adds (exp) = 0;
4639 subs (exp) = 0;
4640 offs (exp) = (ok == 10) ? 1 : 0;
4641 as_warn ("Can't deal with expression; defaulting to %ld",
4642 offs (exp));
4643 }
4644 }
4645 else
4646 {
4647 if (ok >= 10 && ok <= 70)
4648 {
4649 op (exp) = O_constant;
4650 adds (exp) = 0;
4651 subs (exp) = 0;
4652 offs (exp) = (ok == 10) ? 1 : 0;
4653 as_warn ("Can't deal with expression; defaulting to %ld",
4654 offs (exp));
4655 }
4656 }
4657
4658 if (exp->size != SIZE_UNSPEC)
4659 {
4660 switch (exp->size)
4661 {
4662 case SIZE_UNSPEC:
4663 case SIZE_LONG:
4664 break;
4665 case SIZE_BYTE:
4666 if (!isbyte (offs (exp)))
4667 as_warn ("expression doesn't fit in BYTE");
4668 break;
4669 case SIZE_WORD:
4670 if (!isword (offs (exp)))
4671 as_warn ("expression doesn't fit in WORD");
4672 break;
4673 }
4674 }
4675
4676 return offs (exp);
4677 }
4678
4679 /* These are the back-ends for the various machine dependent pseudo-ops. */
4680 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4681
4682 static void
4683 s_data1 (ignore)
4684 int ignore;
4685 {
4686 subseg_set (data_section, 1);
4687 demand_empty_rest_of_line ();
4688 }
4689
4690 static void
4691 s_data2 (ignore)
4692 int ignore;
4693 {
4694 subseg_set (data_section, 2);
4695 demand_empty_rest_of_line ();
4696 }
4697
4698 static void
4699 s_bss (ignore)
4700 int ignore;
4701 {
4702 /* We don't support putting frags in the BSS segment, we fake it
4703 by marking in_bss, then looking at s_skip for clues. */
4704
4705 subseg_set (bss_section, 0);
4706 demand_empty_rest_of_line ();
4707 }
4708
4709 static void
4710 s_even (ignore)
4711 int ignore;
4712 {
4713 register int temp;
4714 register long temp_fill;
4715
4716 temp = 1; /* JF should be 2? */
4717 temp_fill = get_absolute_expression ();
4718 if (!need_pass_2) /* Never make frag if expect extra pass. */
4719 frag_align (temp, (int) temp_fill);
4720 demand_empty_rest_of_line ();
4721 }
4722
4723 static void
4724 s_proc (ignore)
4725 int ignore;
4726 {
4727 demand_empty_rest_of_line ();
4728 }
4729 \f
4730 /* Pseudo-ops handled for MRI compatibility. */
4731
4732 /* This function returns non-zero if the argument is a conditional
4733 pseudo-op. This is called when checking whether a pending
4734 alignment is needed. */
4735
4736 int
4737 m68k_conditional_pseudoop (pop)
4738 pseudo_typeS *pop;
4739 {
4740 return (pop->poc_handler == s_mri_if
4741 || pop->poc_handler == s_mri_else);
4742 }
4743
4744 /* Handle an MRI style chip specification. */
4745
4746 static void
4747 mri_chip ()
4748 {
4749 char *s;
4750 char c;
4751 int i;
4752
4753 s = input_line_pointer;
4754 c = get_symbol_end ();
4755 for (i = 0; i < n_archs; i++)
4756 if (strcasecmp (s, archs[i].name) == 0)
4757 break;
4758 if (i >= n_archs)
4759 {
4760 as_bad ("%s: unrecognized processor name", s);
4761 *input_line_pointer = c;
4762 ignore_rest_of_line ();
4763 return;
4764 }
4765 *input_line_pointer = c;
4766
4767 if (*input_line_pointer == '/')
4768 current_architecture = 0;
4769 else
4770 current_architecture &= m68881 | m68851;
4771 current_architecture |= archs[i].arch;
4772
4773 while (*input_line_pointer == '/')
4774 {
4775 ++input_line_pointer;
4776 s = input_line_pointer;
4777 c = get_symbol_end ();
4778 if (strcmp (s, "68881") == 0)
4779 current_architecture |= m68881;
4780 else if (strcmp (s, "68851") == 0)
4781 current_architecture |= m68851;
4782 *input_line_pointer = c;
4783 }
4784
4785 /* Update info about available control registers. */
4786 select_control_regs ();
4787 }
4788
4789 /* The MRI CHIP pseudo-op. */
4790
4791 static void
4792 s_chip (ignore)
4793 int ignore;
4794 {
4795 char *stop = NULL;
4796 char stopc;
4797
4798 if (flag_mri)
4799 stop = mri_comment_field (&stopc);
4800 mri_chip ();
4801 if (flag_mri)
4802 mri_comment_end (stop, stopc);
4803 demand_empty_rest_of_line ();
4804 }
4805
4806 /* The MRI FOPT pseudo-op. */
4807
4808 static void
4809 s_fopt (ignore)
4810 int ignore;
4811 {
4812 SKIP_WHITESPACE ();
4813
4814 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4815 {
4816 int temp;
4817
4818 input_line_pointer += 3;
4819 temp = get_absolute_expression ();
4820 if (temp < 0 || temp > 7)
4821 as_bad ("bad coprocessor id");
4822 else
4823 m68k_float_copnum = COP0 + temp;
4824 }
4825 else
4826 {
4827 as_bad ("unrecognized fopt option");
4828 ignore_rest_of_line ();
4829 return;
4830 }
4831
4832 demand_empty_rest_of_line ();
4833 }
4834
4835 /* The structure used to handle the MRI OPT pseudo-op. */
4836
4837 struct opt_action
4838 {
4839 /* The name of the option. */
4840 const char *name;
4841
4842 /* If this is not NULL, just call this function. The first argument
4843 is the ARG field of this structure, the second argument is
4844 whether the option was negated. */
4845 void (*pfn) PARAMS ((int arg, int on));
4846
4847 /* If this is not NULL, and the PFN field is NULL, set the variable
4848 this points to. Set it to the ARG field if the option was not
4849 negated, and the NOTARG field otherwise. */
4850 int *pvar;
4851
4852 /* The value to pass to PFN or to assign to *PVAR. */
4853 int arg;
4854
4855 /* The value to assign to *PVAR if the option is negated. If PFN is
4856 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4857 the option may not be negated. */
4858 int notarg;
4859 };
4860
4861 /* The table used to handle the MRI OPT pseudo-op. */
4862
4863 static void skip_to_comma PARAMS ((int, int));
4864 static void opt_nest PARAMS ((int, int));
4865 static void opt_chip PARAMS ((int, int));
4866 static void opt_list PARAMS ((int, int));
4867 static void opt_list_symbols PARAMS ((int, int));
4868
4869 static const struct opt_action opt_table[] =
4870 {
4871 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4872
4873 /* We do relaxing, so there is little use for these options. */
4874 { "b", 0, 0, 0, 0 },
4875 { "brs", 0, 0, 0, 0 },
4876 { "brb", 0, 0, 0, 0 },
4877 { "brl", 0, 0, 0, 0 },
4878 { "brw", 0, 0, 0, 0 },
4879
4880 { "c", 0, 0, 0, 0 },
4881 { "cex", 0, 0, 0, 0 },
4882 { "case", 0, &symbols_case_sensitive, 1, 0 },
4883 { "cl", 0, 0, 0, 0 },
4884 { "cre", 0, 0, 0, 0 },
4885 { "d", 0, &flag_keep_locals, 1, 0 },
4886 { "e", 0, 0, 0, 0 },
4887 { "f", 0, &flag_short_refs, 1, 0 },
4888 { "frs", 0, &flag_short_refs, 1, 0 },
4889 { "frl", 0, &flag_short_refs, 0, 1 },
4890 { "g", 0, 0, 0, 0 },
4891 { "i", 0, 0, 0, 0 },
4892 { "m", 0, 0, 0, 0 },
4893 { "mex", 0, 0, 0, 0 },
4894 { "mc", 0, 0, 0, 0 },
4895 { "md", 0, 0, 0, 0 },
4896 { "nest", opt_nest, 0, 0, 0 },
4897 { "next", skip_to_comma, 0, 0, 0 },
4898 { "o", 0, 0, 0, 0 },
4899 { "old", 0, 0, 0, 0 },
4900 { "op", skip_to_comma, 0, 0, 0 },
4901 { "pco", 0, 0, 0, 0 },
4902 { "p", opt_chip, 0, 0, 0 },
4903 { "pcr", 0, 0, 0, 0 },
4904 { "pcs", 0, 0, 0, 0 },
4905 { "r", 0, 0, 0, 0 },
4906 { "quick", 0, &m68k_quick, 1, 0 },
4907 { "rel32", 0, &m68k_rel32, 1, 0 },
4908 { "s", opt_list, 0, 0, 0 },
4909 { "t", opt_list_symbols, 0, 0, 0 },
4910 { "w", 0, &flag_no_warnings, 0, 1 },
4911 { "x", 0, 0, 0, 0 }
4912 };
4913
4914 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4915
4916 /* The MRI OPT pseudo-op. */
4917
4918 static void
4919 s_opt (ignore)
4920 int ignore;
4921 {
4922 do
4923 {
4924 int t;
4925 char *s;
4926 char c;
4927 int i;
4928 const struct opt_action *o;
4929
4930 SKIP_WHITESPACE ();
4931
4932 t = 1;
4933 if (*input_line_pointer == '-')
4934 {
4935 ++input_line_pointer;
4936 t = 0;
4937 }
4938 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4939 {
4940 input_line_pointer += 2;
4941 t = 0;
4942 }
4943
4944 s = input_line_pointer;
4945 c = get_symbol_end ();
4946
4947 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4948 {
4949 if (strcasecmp (s, o->name) == 0)
4950 {
4951 if (o->pfn)
4952 {
4953 /* Restore input_line_pointer now in case the option
4954 takes arguments. */
4955 *input_line_pointer = c;
4956 (*o->pfn) (o->arg, t);
4957 }
4958 else if (o->pvar != NULL)
4959 {
4960 if (! t && o->arg == o->notarg)
4961 as_bad ("option `%s' may not be negated", s);
4962 *input_line_pointer = c;
4963 *o->pvar = t ? o->arg : o->notarg;
4964 }
4965 else
4966 *input_line_pointer = c;
4967 break;
4968 }
4969 }
4970 if (i >= OPTCOUNT)
4971 {
4972 as_bad ("option `%s' not recognized", s);
4973 *input_line_pointer = c;
4974 }
4975 }
4976 while (*input_line_pointer++ == ',');
4977
4978 /* Move back to terminating character. */
4979 --input_line_pointer;
4980 demand_empty_rest_of_line ();
4981 }
4982
4983 /* Skip ahead to a comma. This is used for OPT options which we do
4984 not suppor tand which take arguments. */
4985
4986 static void
4987 skip_to_comma (arg, on)
4988 int arg;
4989 int on;
4990 {
4991 while (*input_line_pointer != ','
4992 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4993 ++input_line_pointer;
4994 }
4995
4996 /* Handle the OPT NEST=depth option. */
4997
4998 static void
4999 opt_nest (arg, on)
5000 int arg;
5001 int on;
5002 {
5003 if (*input_line_pointer != '=')
5004 {
5005 as_bad ("bad format of OPT NEST=depth");
5006 return;
5007 }
5008
5009 ++input_line_pointer;
5010 max_macro_nest = get_absolute_expression ();
5011 }
5012
5013 /* Handle the OPT P=chip option. */
5014
5015 static void
5016 opt_chip (arg, on)
5017 int arg;
5018 int on;
5019 {
5020 if (*input_line_pointer != '=')
5021 {
5022 /* This is just OPT P, which we do not support. */
5023 return;
5024 }
5025
5026 ++input_line_pointer;
5027 mri_chip ();
5028 }
5029
5030 /* Handle the OPT S option. */
5031
5032 static void
5033 opt_list (arg, on)
5034 int arg;
5035 int on;
5036 {
5037 listing_list (on);
5038 }
5039
5040 /* Handle the OPT T option. */
5041
5042 static void
5043 opt_list_symbols (arg, on)
5044 int arg;
5045 int on;
5046 {
5047 if (on)
5048 listing |= LISTING_SYMBOLS;
5049 else
5050 listing &=~ LISTING_SYMBOLS;
5051 }
5052
5053 /* Handle the MRI REG pseudo-op. */
5054
5055 static void
5056 s_reg (ignore)
5057 int ignore;
5058 {
5059 char *s;
5060 int c;
5061 struct m68k_op rop;
5062 unsigned long mask;
5063 char *stop = NULL;
5064 char stopc;
5065
5066 if (line_label == NULL)
5067 {
5068 as_bad ("missing label");
5069 ignore_rest_of_line ();
5070 return;
5071 }
5072
5073 if (flag_mri)
5074 stop = mri_comment_field (&stopc);
5075
5076 SKIP_WHITESPACE ();
5077
5078 s = input_line_pointer;
5079 while (isalnum ((unsigned char) *input_line_pointer)
5080 #ifdef REGISTER_PREFIX
5081 || *input_line_pointer == REGISTER_PREFIX
5082 #endif
5083 || *input_line_pointer == '/'
5084 || *input_line_pointer == '-')
5085 ++input_line_pointer;
5086 c = *input_line_pointer;
5087 *input_line_pointer = '\0';
5088
5089 if (m68k_ip_op (s, &rop) != 0)
5090 {
5091 if (rop.error == NULL)
5092 as_bad ("bad register list");
5093 else
5094 as_bad ("bad register list: %s", rop.error);
5095 *input_line_pointer = c;
5096 ignore_rest_of_line ();
5097 return;
5098 }
5099
5100 *input_line_pointer = c;
5101
5102 if (rop.mode == REGLST)
5103 mask = rop.mask;
5104 else if (rop.mode == DREG)
5105 mask = 1 << (rop.reg - DATA0);
5106 else if (rop.mode == AREG)
5107 mask = 1 << (rop.reg - ADDR0 + 8);
5108 else if (rop.mode == FPREG)
5109 mask = 1 << (rop.reg - FP0 + 16);
5110 else if (rop.mode == CONTROL
5111 && rop.reg == FPI)
5112 mask = 1 << 24;
5113 else if (rop.mode == CONTROL
5114 && rop.reg == FPS)
5115 mask = 1 << 25;
5116 else if (rop.mode == CONTROL
5117 && rop.reg == FPC)
5118 mask = 1 << 26;
5119 else
5120 {
5121 as_bad ("bad register list");
5122 ignore_rest_of_line ();
5123 return;
5124 }
5125
5126 S_SET_SEGMENT (line_label, absolute_section);
5127 S_SET_VALUE (line_label, mask);
5128 line_label->sy_frag = &zero_address_frag;
5129
5130 if (flag_mri)
5131 mri_comment_end (stop, stopc);
5132
5133 demand_empty_rest_of_line ();
5134 }
5135
5136 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5137
5138 struct save_opts
5139 {
5140 struct save_opts *next;
5141 int abspcadd;
5142 int symbols_case_sensitive;
5143 int keep_locals;
5144 int short_refs;
5145 int architecture;
5146 int quick;
5147 int rel32;
5148 int listing;
5149 int no_warnings;
5150 /* FIXME: We don't save OPT S. */
5151 };
5152
5153 /* This variable holds the stack of saved options. */
5154
5155 static struct save_opts *save_stack;
5156
5157 /* The MRI SAVE pseudo-op. */
5158
5159 static void
5160 s_save (ignore)
5161 int ignore;
5162 {
5163 struct save_opts *s;
5164
5165 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5166 s->abspcadd = m68k_abspcadd;
5167 s->symbols_case_sensitive = symbols_case_sensitive;
5168 s->keep_locals = flag_keep_locals;
5169 s->short_refs = flag_short_refs;
5170 s->architecture = current_architecture;
5171 s->quick = m68k_quick;
5172 s->rel32 = m68k_rel32;
5173 s->listing = listing;
5174 s->no_warnings = flag_no_warnings;
5175
5176 s->next = save_stack;
5177 save_stack = s;
5178
5179 demand_empty_rest_of_line ();
5180 }
5181
5182 /* The MRI RESTORE pseudo-op. */
5183
5184 static void
5185 s_restore (ignore)
5186 int ignore;
5187 {
5188 struct save_opts *s;
5189
5190 if (save_stack == NULL)
5191 {
5192 as_bad ("restore without save");
5193 ignore_rest_of_line ();
5194 return;
5195 }
5196
5197 s = save_stack;
5198 save_stack = s->next;
5199
5200 m68k_abspcadd = s->abspcadd;
5201 symbols_case_sensitive = s->symbols_case_sensitive;
5202 flag_keep_locals = s->keep_locals;
5203 flag_short_refs = s->short_refs;
5204 current_architecture = s->architecture;
5205 m68k_quick = s->quick;
5206 m68k_rel32 = s->rel32;
5207 listing = s->listing;
5208 flag_no_warnings = s->no_warnings;
5209
5210 free (s);
5211
5212 demand_empty_rest_of_line ();
5213 }
5214
5215 /* Types of MRI structured control directives. */
5216
5217 enum mri_control_type
5218 {
5219 mri_for,
5220 mri_if,
5221 mri_repeat,
5222 mri_while
5223 };
5224
5225 /* This structure is used to stack the MRI structured control
5226 directives. */
5227
5228 struct mri_control_info
5229 {
5230 /* The directive within which this one is enclosed. */
5231 struct mri_control_info *outer;
5232
5233 /* The type of directive. */
5234 enum mri_control_type type;
5235
5236 /* Whether an ELSE has been in an IF. */
5237 int else_seen;
5238
5239 /* The add or sub statement at the end of a FOR. */
5240 char *incr;
5241
5242 /* The label of the top of a FOR or REPEAT loop. */
5243 char *top;
5244
5245 /* The label to jump to for the next iteration, or the else
5246 expression of a conditional. */
5247 char *next;
5248
5249 /* The label to jump to to break out of the loop, or the label past
5250 the end of a conditional. */
5251 char *bottom;
5252 };
5253
5254 /* The stack of MRI structured control directives. */
5255
5256 static struct mri_control_info *mri_control_stack;
5257
5258 /* The current MRI structured control directive index number, used to
5259 generate label names. */
5260
5261 static int mri_control_index;
5262
5263 /* Some function prototypes. */
5264
5265 static char *mri_control_label PARAMS ((void));
5266 static struct mri_control_info *push_mri_control
5267 PARAMS ((enum mri_control_type));
5268 static void pop_mri_control PARAMS ((void));
5269 static int parse_mri_condition PARAMS ((int *));
5270 static int parse_mri_control_operand
5271 PARAMS ((int *, char **, char **, char **, char **));
5272 static int swap_mri_condition PARAMS ((int));
5273 static int reverse_mri_condition PARAMS ((int));
5274 static void build_mri_control_operand
5275 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5276 const char *, int));
5277 static void parse_mri_control_expression
5278 PARAMS ((char *, int, const char *, const char *, int));
5279
5280 /* Generate a new MRI label structured control directive label name. */
5281
5282 static char *
5283 mri_control_label ()
5284 {
5285 char *n;
5286
5287 n = (char *) xmalloc (20);
5288 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5289 ++mri_control_index;
5290 return n;
5291 }
5292
5293 /* Create a new MRI structured control directive. */
5294
5295 static struct mri_control_info *
5296 push_mri_control (type)
5297 enum mri_control_type type;
5298 {
5299 struct mri_control_info *n;
5300
5301 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5302
5303 n->type = type;
5304 n->else_seen = 0;
5305 if (type == mri_if || type == mri_while)
5306 n->top = NULL;
5307 else
5308 n->top = mri_control_label ();
5309 n->next = mri_control_label ();
5310 n->bottom = mri_control_label ();
5311
5312 n->outer = mri_control_stack;
5313 mri_control_stack = n;
5314
5315 return n;
5316 }
5317
5318 /* Pop off the stack of MRI structured control directives. */
5319
5320 static void
5321 pop_mri_control ()
5322 {
5323 struct mri_control_info *n;
5324
5325 n = mri_control_stack;
5326 mri_control_stack = n->outer;
5327 if (n->top != NULL)
5328 free (n->top);
5329 free (n->next);
5330 free (n->bottom);
5331 free (n);
5332 }
5333
5334 /* Recognize a condition code in an MRI structured control expression. */
5335
5336 static int
5337 parse_mri_condition (pcc)
5338 int *pcc;
5339 {
5340 char c1, c2;
5341
5342 know (*input_line_pointer == '<');
5343
5344 ++input_line_pointer;
5345 c1 = *input_line_pointer++;
5346 c2 = *input_line_pointer++;
5347
5348 if (*input_line_pointer != '>')
5349 {
5350 as_bad ("syntax error in structured control directive");
5351 return 0;
5352 }
5353
5354 ++input_line_pointer;
5355 SKIP_WHITESPACE ();
5356
5357 if (isupper (c1))
5358 c1 = tolower (c1);
5359 if (isupper (c2))
5360 c2 = tolower (c2);
5361
5362 *pcc = (c1 << 8) | c2;
5363
5364 return 1;
5365 }
5366
5367 /* Parse a single operand in an MRI structured control expression. */
5368
5369 static int
5370 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5371 int *pcc;
5372 char **leftstart;
5373 char **leftstop;
5374 char **rightstart;
5375 char **rightstop;
5376 {
5377 char *s;
5378
5379 SKIP_WHITESPACE ();
5380
5381 *pcc = -1;
5382 *leftstart = NULL;
5383 *leftstop = NULL;
5384 *rightstart = NULL;
5385 *rightstop = NULL;
5386
5387 if (*input_line_pointer == '<')
5388 {
5389 /* It's just a condition code. */
5390 return parse_mri_condition (pcc);
5391 }
5392
5393 /* Look ahead for the condition code. */
5394 for (s = input_line_pointer; *s != '\0'; ++s)
5395 {
5396 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5397 break;
5398 }
5399 if (*s == '\0')
5400 {
5401 as_bad ("missing condition code in structured control directive");
5402 return 0;
5403 }
5404
5405 *leftstart = input_line_pointer;
5406 *leftstop = s;
5407 if (*leftstop > *leftstart
5408 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5409 --*leftstop;
5410
5411 input_line_pointer = s;
5412 if (! parse_mri_condition (pcc))
5413 return 0;
5414
5415 /* Look ahead for AND or OR or end of line. */
5416 for (s = input_line_pointer; *s != '\0'; ++s)
5417 {
5418 if ((strncasecmp (s, "AND", 3) == 0
5419 && (s[3] == '.' || ! is_part_of_name (s[3])))
5420 || (strncasecmp (s, "OR", 2) == 0
5421 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5422 break;
5423 }
5424
5425 *rightstart = input_line_pointer;
5426 *rightstop = s;
5427 if (*rightstop > *rightstart
5428 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5429 --*rightstop;
5430
5431 input_line_pointer = s;
5432
5433 return 1;
5434 }
5435
5436 #define MCC(b1, b2) (((b1) << 8) | (b2))
5437
5438 /* Swap the sense of a condition. This changes the condition so that
5439 it generates the same result when the operands are swapped. */
5440
5441 static int
5442 swap_mri_condition (cc)
5443 int cc;
5444 {
5445 switch (cc)
5446 {
5447 case MCC ('h', 'i'): return MCC ('c', 's');
5448 case MCC ('l', 's'): return MCC ('c', 'c');
5449 case MCC ('c', 'c'): return MCC ('l', 's');
5450 case MCC ('c', 's'): return MCC ('h', 'i');
5451 case MCC ('p', 'l'): return MCC ('m', 'i');
5452 case MCC ('m', 'i'): return MCC ('p', 'l');
5453 case MCC ('g', 'e'): return MCC ('l', 'e');
5454 case MCC ('l', 't'): return MCC ('g', 't');
5455 case MCC ('g', 't'): return MCC ('l', 't');
5456 case MCC ('l', 'e'): return MCC ('g', 'e');
5457 }
5458 return cc;
5459 }
5460
5461 /* Reverse the sense of a condition. */
5462
5463 static int
5464 reverse_mri_condition (cc)
5465 int cc;
5466 {
5467 switch (cc)
5468 {
5469 case MCC ('h', 'i'): return MCC ('l', 's');
5470 case MCC ('l', 's'): return MCC ('h', 'i');
5471 case MCC ('c', 'c'): return MCC ('c', 's');
5472 case MCC ('c', 's'): return MCC ('c', 'c');
5473 case MCC ('n', 'e'): return MCC ('e', 'q');
5474 case MCC ('e', 'q'): return MCC ('n', 'e');
5475 case MCC ('v', 'c'): return MCC ('v', 's');
5476 case MCC ('v', 's'): return MCC ('v', 'c');
5477 case MCC ('p', 'l'): return MCC ('m', 'i');
5478 case MCC ('m', 'i'): return MCC ('p', 'l');
5479 case MCC ('g', 'e'): return MCC ('l', 't');
5480 case MCC ('l', 't'): return MCC ('g', 'e');
5481 case MCC ('g', 't'): return MCC ('l', 'e');
5482 case MCC ('l', 'e'): return MCC ('g', 't');
5483 }
5484 return cc;
5485 }
5486
5487 /* Build an MRI structured control expression. This generates test
5488 and branch instructions. It goes to TRUELAB if the condition is
5489 true, and to FALSELAB if the condition is false. Exactly one of
5490 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5491 is the size qualifier for the expression. EXTENT is the size to
5492 use for the branch. */
5493
5494 static void
5495 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5496 rightstop, truelab, falselab, extent)
5497 int qual;
5498 int cc;
5499 char *leftstart;
5500 char *leftstop;
5501 char *rightstart;
5502 char *rightstop;
5503 const char *truelab;
5504 const char *falselab;
5505 int extent;
5506 {
5507 char *buf;
5508 char *s;
5509
5510 if (leftstart != NULL)
5511 {
5512 struct m68k_op leftop, rightop;
5513 char c;
5514
5515 /* Swap the compare operands, if necessary, to produce a legal
5516 m68k compare instruction. Comparing a register operand with
5517 a non-register operand requires the register to be on the
5518 right (cmp, cmpa). Comparing an immediate value with
5519 anything requires the immediate value to be on the left
5520 (cmpi). */
5521
5522 c = *leftstop;
5523 *leftstop = '\0';
5524 (void) m68k_ip_op (leftstart, &leftop);
5525 *leftstop = c;
5526
5527 c = *rightstop;
5528 *rightstop = '\0';
5529 (void) m68k_ip_op (rightstart, &rightop);
5530 *rightstop = c;
5531
5532 if (rightop.mode == IMMED
5533 || ((leftop.mode == DREG || leftop.mode == AREG)
5534 && (rightop.mode != DREG && rightop.mode != AREG)))
5535 {
5536 char *temp;
5537
5538 cc = swap_mri_condition (cc);
5539 temp = leftstart;
5540 leftstart = rightstart;
5541 rightstart = temp;
5542 temp = leftstop;
5543 leftstop = rightstop;
5544 rightstop = temp;
5545 }
5546 }
5547
5548 if (truelab == NULL)
5549 {
5550 cc = reverse_mri_condition (cc);
5551 truelab = falselab;
5552 }
5553
5554 if (leftstart != NULL)
5555 {
5556 buf = (char *) xmalloc (20
5557 + (leftstop - leftstart)
5558 + (rightstop - rightstart));
5559 s = buf;
5560 *s++ = 'c';
5561 *s++ = 'm';
5562 *s++ = 'p';
5563 if (qual != '\0')
5564 *s++ = qual;
5565 *s++ = ' ';
5566 memcpy (s, leftstart, leftstop - leftstart);
5567 s += leftstop - leftstart;
5568 *s++ = ',';
5569 memcpy (s, rightstart, rightstop - rightstart);
5570 s += rightstop - rightstart;
5571 *s = '\0';
5572 md_assemble (buf);
5573 free (buf);
5574 }
5575
5576 buf = (char *) xmalloc (20 + strlen (truelab));
5577 s = buf;
5578 *s++ = 'b';
5579 *s++ = cc >> 8;
5580 *s++ = cc & 0xff;
5581 if (extent != '\0')
5582 *s++ = extent;
5583 *s++ = ' ';
5584 strcpy (s, truelab);
5585 md_assemble (buf);
5586 free (buf);
5587 }
5588
5589 /* Parse an MRI structured control expression. This generates test
5590 and branch instructions. STOP is where the expression ends. It
5591 goes to TRUELAB if the condition is true, and to FALSELAB if the
5592 condition is false. Exactly one of TRUELAB and FALSELAB will be
5593 NULL, meaning to fall through. QUAL is the size qualifier for the
5594 expression. EXTENT is the size to use for the branch. */
5595
5596 static void
5597 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5598 char *stop;
5599 int qual;
5600 const char *truelab;
5601 const char *falselab;
5602 int extent;
5603 {
5604 int c;
5605 int cc;
5606 char *leftstart;
5607 char *leftstop;
5608 char *rightstart;
5609 char *rightstop;
5610
5611 c = *stop;
5612 *stop = '\0';
5613
5614 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5615 &rightstart, &rightstop))
5616 {
5617 *stop = c;
5618 return;
5619 }
5620
5621 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5622 {
5623 const char *flab;
5624
5625 if (falselab != NULL)
5626 flab = falselab;
5627 else
5628 flab = mri_control_label ();
5629
5630 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5631 rightstop, (const char *) NULL, flab, extent);
5632
5633 input_line_pointer += 3;
5634 if (*input_line_pointer != '.'
5635 || input_line_pointer[1] == '\0')
5636 qual = '\0';
5637 else
5638 {
5639 qual = input_line_pointer[1];
5640 input_line_pointer += 2;
5641 }
5642
5643 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5644 &rightstart, &rightstop))
5645 {
5646 *stop = c;
5647 return;
5648 }
5649
5650 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5651 rightstop, truelab, falselab, extent);
5652
5653 if (falselab == NULL)
5654 colon (flab);
5655 }
5656 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5657 {
5658 const char *tlab;
5659
5660 if (truelab != NULL)
5661 tlab = truelab;
5662 else
5663 tlab = mri_control_label ();
5664
5665 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5666 rightstop, tlab, (const char *) NULL, extent);
5667
5668 input_line_pointer += 2;
5669 if (*input_line_pointer != '.'
5670 || input_line_pointer[1] == '\0')
5671 qual = '\0';
5672 else
5673 {
5674 qual = input_line_pointer[1];
5675 input_line_pointer += 2;
5676 }
5677
5678 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5679 &rightstart, &rightstop))
5680 {
5681 *stop = c;
5682 return;
5683 }
5684
5685 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5686 rightstop, truelab, falselab, extent);
5687
5688 if (truelab == NULL)
5689 colon (tlab);
5690 }
5691 else
5692 {
5693 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5694 rightstop, truelab, falselab, extent);
5695 }
5696
5697 *stop = c;
5698 if (input_line_pointer != stop)
5699 as_bad ("syntax error in structured control directive");
5700 }
5701
5702 /* Handle the MRI IF pseudo-op. This may be a structured control
5703 directive, or it may be a regular assembler conditional, depending
5704 on its operands. */
5705
5706 static void
5707 s_mri_if (qual)
5708 int qual;
5709 {
5710 char *s;
5711 int c;
5712 struct mri_control_info *n;
5713
5714 /* A structured control directive must end with THEN with an
5715 optional qualifier. */
5716 s = input_line_pointer;
5717 while (! is_end_of_line[(unsigned char) *s]
5718 && (! flag_mri || *s != '*'))
5719 ++s;
5720 --s;
5721 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5722 --s;
5723
5724 if (s - input_line_pointer > 1
5725 && s[-1] == '.')
5726 s -= 2;
5727
5728 if (s - input_line_pointer < 3
5729 || strncasecmp (s - 3, "THEN", 4) != 0)
5730 {
5731 if (qual != '\0')
5732 {
5733 as_bad ("missing then");
5734 ignore_rest_of_line ();
5735 return;
5736 }
5737
5738 /* It's a conditional. */
5739 s_if (O_ne);
5740 return;
5741 }
5742
5743 /* Since this might be a conditional if, this pseudo-op will be
5744 called even if we are supported to be ignoring input. Double
5745 check now. Clobber *input_line_pointer so that ignore_input
5746 thinks that this is not a special pseudo-op. */
5747 c = *input_line_pointer;
5748 *input_line_pointer = 0;
5749 if (ignore_input ())
5750 {
5751 *input_line_pointer = c;
5752 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5753 ++input_line_pointer;
5754 demand_empty_rest_of_line ();
5755 return;
5756 }
5757 *input_line_pointer = c;
5758
5759 n = push_mri_control (mri_if);
5760
5761 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5762 n->next, s[1] == '.' ? s[2] : '\0');
5763
5764 if (s[1] == '.')
5765 input_line_pointer = s + 3;
5766 else
5767 input_line_pointer = s + 1;
5768
5769 if (flag_mri)
5770 {
5771 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5772 ++input_line_pointer;
5773 }
5774
5775 demand_empty_rest_of_line ();
5776 }
5777
5778 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5779 structured IF, associate the ELSE with the IF. Otherwise, assume
5780 it is a conditional else. */
5781
5782 static void
5783 s_mri_else (qual)
5784 int qual;
5785 {
5786 int c;
5787 char *buf;
5788 char q[2];
5789
5790 if (qual == '\0'
5791 && (mri_control_stack == NULL
5792 || mri_control_stack->type != mri_if
5793 || mri_control_stack->else_seen))
5794 {
5795 s_else (0);
5796 return;
5797 }
5798
5799 c = *input_line_pointer;
5800 *input_line_pointer = 0;
5801 if (ignore_input ())
5802 {
5803 *input_line_pointer = c;
5804 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5805 ++input_line_pointer;
5806 demand_empty_rest_of_line ();
5807 return;
5808 }
5809 *input_line_pointer = c;
5810
5811 if (mri_control_stack == NULL
5812 || mri_control_stack->type != mri_if
5813 || mri_control_stack->else_seen)
5814 {
5815 as_bad ("else without matching if");
5816 ignore_rest_of_line ();
5817 return;
5818 }
5819
5820 mri_control_stack->else_seen = 1;
5821
5822 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5823 q[0] = qual;
5824 q[1] = '\0';
5825 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5826 md_assemble (buf);
5827 free (buf);
5828
5829 colon (mri_control_stack->next);
5830
5831 if (flag_mri)
5832 {
5833 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5834 ++input_line_pointer;
5835 }
5836
5837 demand_empty_rest_of_line ();
5838 }
5839
5840 /* Handle the MRI ENDI pseudo-op. */
5841
5842 static void
5843 s_mri_endi (ignore)
5844 int ignore;
5845 {
5846 if (mri_control_stack == NULL
5847 || mri_control_stack->type != mri_if)
5848 {
5849 as_bad ("endi without matching if");
5850 ignore_rest_of_line ();
5851 return;
5852 }
5853
5854 /* ignore_input will not return true for ENDI, so we don't need to
5855 worry about checking it again here. */
5856
5857 if (! mri_control_stack->else_seen)
5858 colon (mri_control_stack->next);
5859 colon (mri_control_stack->bottom);
5860
5861 pop_mri_control ();
5862
5863 if (flag_mri)
5864 {
5865 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5866 ++input_line_pointer;
5867 }
5868
5869 demand_empty_rest_of_line ();
5870 }
5871
5872 /* Handle the MRI BREAK pseudo-op. */
5873
5874 static void
5875 s_mri_break (extent)
5876 int extent;
5877 {
5878 struct mri_control_info *n;
5879 char *buf;
5880 char ex[2];
5881
5882 n = mri_control_stack;
5883 while (n != NULL
5884 && n->type != mri_for
5885 && n->type != mri_repeat
5886 && n->type != mri_while)
5887 n = n->outer;
5888 if (n == NULL)
5889 {
5890 as_bad ("break outside of structured loop");
5891 ignore_rest_of_line ();
5892 return;
5893 }
5894
5895 buf = (char *) xmalloc (20 + strlen (n->bottom));
5896 ex[0] = extent;
5897 ex[1] = '\0';
5898 sprintf (buf, "bra%s %s", ex, n->bottom);
5899 md_assemble (buf);
5900 free (buf);
5901
5902 if (flag_mri)
5903 {
5904 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5905 ++input_line_pointer;
5906 }
5907
5908 demand_empty_rest_of_line ();
5909 }
5910
5911 /* Handle the MRI NEXT pseudo-op. */
5912
5913 static void
5914 s_mri_next (extent)
5915 int extent;
5916 {
5917 struct mri_control_info *n;
5918 char *buf;
5919 char ex[2];
5920
5921 n = mri_control_stack;
5922 while (n != NULL
5923 && n->type != mri_for
5924 && n->type != mri_repeat
5925 && n->type != mri_while)
5926 n = n->outer;
5927 if (n == NULL)
5928 {
5929 as_bad ("next outside of structured loop");
5930 ignore_rest_of_line ();
5931 return;
5932 }
5933
5934 buf = (char *) xmalloc (20 + strlen (n->next));
5935 ex[0] = extent;
5936 ex[1] = '\0';
5937 sprintf (buf, "bra%s %s", ex, n->next);
5938 md_assemble (buf);
5939 free (buf);
5940
5941 if (flag_mri)
5942 {
5943 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5944 ++input_line_pointer;
5945 }
5946
5947 demand_empty_rest_of_line ();
5948 }
5949
5950 /* Handle the MRI FOR pseudo-op. */
5951
5952 static void
5953 s_mri_for (qual)
5954 int qual;
5955 {
5956 const char *varstart, *varstop;
5957 const char *initstart, *initstop;
5958 const char *endstart, *endstop;
5959 const char *bystart, *bystop;
5960 int up;
5961 int by;
5962 int extent;
5963 struct mri_control_info *n;
5964 char *buf;
5965 char *s;
5966 char ex[2];
5967
5968 /* The syntax is
5969 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5970 */
5971
5972 SKIP_WHITESPACE ();
5973 varstart = input_line_pointer;
5974
5975 /* Look for the '='. */
5976 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5977 && *input_line_pointer != '=')
5978 ++input_line_pointer;
5979 if (*input_line_pointer != '=')
5980 {
5981 as_bad ("missing =");
5982 ignore_rest_of_line ();
5983 return;
5984 }
5985
5986 varstop = input_line_pointer;
5987 if (varstop > varstart
5988 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5989 --varstop;
5990
5991 ++input_line_pointer;
5992
5993 initstart = input_line_pointer;
5994
5995 /* Look for TO or DOWNTO. */
5996 up = 1;
5997 initstop = NULL;
5998 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5999 {
6000 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6001 && ! is_part_of_name (input_line_pointer[2]))
6002 {
6003 initstop = input_line_pointer;
6004 input_line_pointer += 2;
6005 break;
6006 }
6007 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6008 && ! is_part_of_name (input_line_pointer[6]))
6009 {
6010 initstop = input_line_pointer;
6011 up = 0;
6012 input_line_pointer += 6;
6013 break;
6014 }
6015 ++input_line_pointer;
6016 }
6017 if (initstop == NULL)
6018 {
6019 as_bad ("missing to or downto");
6020 ignore_rest_of_line ();
6021 return;
6022 }
6023 if (initstop > initstart
6024 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6025 --initstop;
6026
6027 SKIP_WHITESPACE ();
6028 endstart = input_line_pointer;
6029
6030 /* Look for BY or DO. */
6031 by = 0;
6032 endstop = NULL;
6033 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6034 {
6035 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6036 && ! is_part_of_name (input_line_pointer[2]))
6037 {
6038 endstop = input_line_pointer;
6039 by = 1;
6040 input_line_pointer += 2;
6041 break;
6042 }
6043 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6044 && (input_line_pointer[2] == '.'
6045 || ! is_part_of_name (input_line_pointer[2])))
6046 {
6047 endstop = input_line_pointer;
6048 input_line_pointer += 2;
6049 break;
6050 }
6051 ++input_line_pointer;
6052 }
6053 if (endstop == NULL)
6054 {
6055 as_bad ("missing do");
6056 ignore_rest_of_line ();
6057 return;
6058 }
6059 if (endstop > endstart
6060 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6061 --endstop;
6062
6063 if (! by)
6064 {
6065 bystart = "#1";
6066 bystop = bystart + 2;
6067 }
6068 else
6069 {
6070 SKIP_WHITESPACE ();
6071 bystart = input_line_pointer;
6072
6073 /* Look for DO. */
6074 bystop = NULL;
6075 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6076 {
6077 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6078 && (input_line_pointer[2] == '.'
6079 || ! is_part_of_name (input_line_pointer[2])))
6080 {
6081 bystop = input_line_pointer;
6082 input_line_pointer += 2;
6083 break;
6084 }
6085 ++input_line_pointer;
6086 }
6087 if (bystop == NULL)
6088 {
6089 as_bad ("missing do");
6090 ignore_rest_of_line ();
6091 return;
6092 }
6093 if (bystop > bystart
6094 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6095 --bystop;
6096 }
6097
6098 if (*input_line_pointer != '.')
6099 extent = '\0';
6100 else
6101 {
6102 extent = input_line_pointer[1];
6103 input_line_pointer += 2;
6104 }
6105
6106 /* We have fully parsed the FOR operands. Now build the loop. */
6107
6108 n = push_mri_control (mri_for);
6109
6110 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6111
6112 /* move init,var */
6113 s = buf;
6114 *s++ = 'm';
6115 *s++ = 'o';
6116 *s++ = 'v';
6117 *s++ = 'e';
6118 if (qual != '\0')
6119 *s++ = qual;
6120 *s++ = ' ';
6121 memcpy (s, initstart, initstop - initstart);
6122 s += initstop - initstart;
6123 *s++ = ',';
6124 memcpy (s, varstart, varstop - varstart);
6125 s += varstop - varstart;
6126 *s = '\0';
6127 md_assemble (buf);
6128
6129 colon (n->top);
6130
6131 /* cmp end,var */
6132 s = buf;
6133 *s++ = 'c';
6134 *s++ = 'm';
6135 *s++ = 'p';
6136 if (qual != '\0')
6137 *s++ = qual;
6138 *s++ = ' ';
6139 memcpy (s, endstart, endstop - endstart);
6140 s += endstop - endstart;
6141 *s++ = ',';
6142 memcpy (s, varstart, varstop - varstart);
6143 s += varstop - varstart;
6144 *s = '\0';
6145 md_assemble (buf);
6146
6147 /* bcc bottom */
6148 ex[0] = extent;
6149 ex[1] = '\0';
6150 if (up)
6151 sprintf (buf, "blt%s %s", ex, n->bottom);
6152 else
6153 sprintf (buf, "bgt%s %s", ex, n->bottom);
6154 md_assemble (buf);
6155
6156 /* Put together the add or sub instruction used by ENDF. */
6157 s = buf;
6158 if (up)
6159 strcpy (s, "add");
6160 else
6161 strcpy (s, "sub");
6162 s += 3;
6163 if (qual != '\0')
6164 *s++ = qual;
6165 *s++ = ' ';
6166 memcpy (s, bystart, bystop - bystart);
6167 s += bystop - bystart;
6168 *s++ = ',';
6169 memcpy (s, varstart, varstop - varstart);
6170 s += varstop - varstart;
6171 *s = '\0';
6172 n->incr = buf;
6173
6174 if (flag_mri)
6175 {
6176 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6177 ++input_line_pointer;
6178 }
6179
6180 demand_empty_rest_of_line ();
6181 }
6182
6183 /* Handle the MRI ENDF pseudo-op. */
6184
6185 static void
6186 s_mri_endf (ignore)
6187 int ignore;
6188 {
6189 if (mri_control_stack == NULL
6190 || mri_control_stack->type != mri_for)
6191 {
6192 as_bad ("endf without for");
6193 ignore_rest_of_line ();
6194 return;
6195 }
6196
6197 colon (mri_control_stack->next);
6198
6199 md_assemble (mri_control_stack->incr);
6200
6201 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6202 md_assemble (mri_control_stack->incr);
6203
6204 free (mri_control_stack->incr);
6205
6206 colon (mri_control_stack->bottom);
6207
6208 pop_mri_control ();
6209
6210 if (flag_mri)
6211 {
6212 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6213 ++input_line_pointer;
6214 }
6215
6216 demand_empty_rest_of_line ();
6217 }
6218
6219 /* Handle the MRI REPEAT pseudo-op. */
6220
6221 static void
6222 s_mri_repeat (ignore)
6223 int ignore;
6224 {
6225 struct mri_control_info *n;
6226
6227 n = push_mri_control (mri_repeat);
6228 colon (n->top);
6229 if (flag_mri)
6230 {
6231 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6232 ++input_line_pointer;
6233 }
6234 demand_empty_rest_of_line ();
6235 }
6236
6237 /* Handle the MRI UNTIL pseudo-op. */
6238
6239 static void
6240 s_mri_until (qual)
6241 int qual;
6242 {
6243 char *s;
6244
6245 if (mri_control_stack == NULL
6246 || mri_control_stack->type != mri_repeat)
6247 {
6248 as_bad ("until without repeat");
6249 ignore_rest_of_line ();
6250 return;
6251 }
6252
6253 colon (mri_control_stack->next);
6254
6255 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6256 ;
6257
6258 parse_mri_control_expression (s, qual, (const char *) NULL,
6259 mri_control_stack->top, '\0');
6260
6261 colon (mri_control_stack->bottom);
6262
6263 input_line_pointer = s;
6264
6265 pop_mri_control ();
6266
6267 if (flag_mri)
6268 {
6269 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6270 ++input_line_pointer;
6271 }
6272
6273 demand_empty_rest_of_line ();
6274 }
6275
6276 /* Handle the MRI WHILE pseudo-op. */
6277
6278 static void
6279 s_mri_while (qual)
6280 int qual;
6281 {
6282 char *s;
6283
6284 struct mri_control_info *n;
6285
6286 s = input_line_pointer;
6287 while (! is_end_of_line[(unsigned char) *s]
6288 && (! flag_mri || *s != '*'))
6289 s++;
6290 --s;
6291 while (*s == ' ' || *s == '\t')
6292 --s;
6293 if (s - input_line_pointer > 1
6294 && s[-1] == '.')
6295 s -= 2;
6296 if (s - input_line_pointer < 2
6297 || strncasecmp (s - 1, "DO", 2) != 0)
6298 {
6299 as_bad ("missing do");
6300 ignore_rest_of_line ();
6301 return;
6302 }
6303
6304 n = push_mri_control (mri_while);
6305
6306 colon (n->next);
6307
6308 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6309 s[1] == '.' ? s[2] : '\0');
6310
6311 input_line_pointer = s + 1;
6312 if (*input_line_pointer == '.')
6313 input_line_pointer += 2;
6314
6315 if (flag_mri)
6316 {
6317 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6318 ++input_line_pointer;
6319 }
6320
6321 demand_empty_rest_of_line ();
6322 }
6323
6324 /* Handle the MRI ENDW pseudo-op. */
6325
6326 static void
6327 s_mri_endw (ignore)
6328 int ignore;
6329 {
6330 char *buf;
6331
6332 if (mri_control_stack == NULL
6333 || mri_control_stack->type != mri_while)
6334 {
6335 as_bad ("endw without while");
6336 ignore_rest_of_line ();
6337 return;
6338 }
6339
6340 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6341 sprintf (buf, "bra %s", mri_control_stack->next);
6342 md_assemble (buf);
6343 free (buf);
6344
6345 colon (mri_control_stack->bottom);
6346
6347 pop_mri_control ();
6348
6349 if (flag_mri)
6350 {
6351 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6352 ++input_line_pointer;
6353 }
6354
6355 demand_empty_rest_of_line ();
6356 }
6357 \f
6358 /*
6359 * md_parse_option
6360 * Invocation line includes a switch not recognized by the base assembler.
6361 * See if it's a processor-specific option. These are:
6362 *
6363 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6364 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6365 * Select the architecture. Instructions or features not
6366 * supported by the selected architecture cause fatal
6367 * errors. More than one may be specified. The default is
6368 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6369 * for -m68000, and -m68882 is a synonym for -m68881.
6370 * -[A]m[c]no-68851, -[A]m[c]no-68881
6371 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6372 * so don't use or document it, but that's the way the parsing
6373 * works).
6374 *
6375 * -pic Indicates PIC.
6376 * -k Indicates PIC. (Sun 3 only.)
6377 *
6378 * --bitwise-or
6379 * Permit `|' to be used in expressions.
6380 *
6381 */
6382
6383 #ifdef OBJ_ELF
6384 CONST char *md_shortopts = "lSA:m:kQ:V";
6385 #else
6386 CONST char *md_shortopts = "lSA:m:k";
6387 #endif
6388
6389 struct option md_longopts[] = {
6390 #define OPTION_PIC (OPTION_MD_BASE)
6391 {"pic", no_argument, NULL, OPTION_PIC},
6392 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6393 {"register-prefix-optional", no_argument, NULL,
6394 OPTION_REGISTER_PREFIX_OPTIONAL},
6395 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6396 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6397 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6398 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6399 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6400 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6401 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6402 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6403 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6404 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6405 {NULL, no_argument, NULL, 0}
6406 };
6407 size_t md_longopts_size = sizeof(md_longopts);
6408
6409 int
6410 md_parse_option (c, arg)
6411 int c;
6412 char *arg;
6413 {
6414 switch (c)
6415 {
6416 case 'l': /* -l means keep external to 2 bit offset
6417 rather than 16 bit one */
6418 flag_short_refs = 1;
6419 break;
6420
6421 case 'S': /* -S means that jbsr's always turn into
6422 jsr's. */
6423 flag_long_jumps = 1;
6424 break;
6425
6426 case 'A':
6427 if (*arg == 'm')
6428 arg++;
6429 /* intentional fall-through */
6430 case 'm':
6431
6432 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6433 {
6434 int i;
6435 unsigned long arch;
6436 const char *oarg = arg;
6437
6438 arg += 3;
6439 if (*arg == 'm')
6440 {
6441 arg++;
6442 if (arg[0] == 'c' && arg[1] == '6')
6443 arg++;
6444 }
6445 for (i = 0; i < n_archs; i++)
6446 if (!strcmp (arg, archs[i].name))
6447 break;
6448 if (i == n_archs)
6449 {
6450 unknown:
6451 as_bad ("unrecognized option `%s'", oarg);
6452 return 0;
6453 }
6454 arch = archs[i].arch;
6455 if (arch == m68881)
6456 no_68881 = 1;
6457 else if (arch == m68851)
6458 no_68851 = 1;
6459 else
6460 goto unknown;
6461 }
6462 else
6463 {
6464 int i;
6465
6466 if (arg[0] == 'c' && arg[1] == '6')
6467 arg++;
6468
6469 for (i = 0; i < n_archs; i++)
6470 if (!strcmp (arg, archs[i].name))
6471 {
6472 unsigned long arch = archs[i].arch;
6473 if (cpu_of_arch (arch))
6474 /* It's a cpu spec. */
6475 {
6476 current_architecture &= ~m68000up;
6477 current_architecture |= arch;
6478 }
6479 else if (arch == m68881)
6480 {
6481 current_architecture |= m68881;
6482 no_68881 = 0;
6483 }
6484 else if (arch == m68851)
6485 {
6486 current_architecture |= m68851;
6487 no_68851 = 0;
6488 }
6489 else
6490 /* ??? */
6491 abort ();
6492 break;
6493 }
6494 if (i == n_archs)
6495 {
6496 as_bad ("unrecognized architecture specification `%s'", arg);
6497 return 0;
6498 }
6499 }
6500 break;
6501
6502 case OPTION_PIC:
6503 case 'k':
6504 flag_want_pic = 1;
6505 break; /* -pic, Position Independent Code */
6506
6507 case OPTION_REGISTER_PREFIX_OPTIONAL:
6508 flag_reg_prefix_optional = 1;
6509 reg_prefix_optional_seen = 1;
6510 break;
6511
6512 /* -V: SVR4 argument to print version ID. */
6513 case 'V':
6514 print_version_id ();
6515 break;
6516
6517 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6518 should be emitted or not. FIXME: Not implemented. */
6519 case 'Q':
6520 break;
6521
6522 case OPTION_BITWISE_OR:
6523 {
6524 char *n, *t;
6525 const char *s;
6526
6527 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6528 t = n;
6529 for (s = m68k_comment_chars; *s != '\0'; s++)
6530 if (*s != '|')
6531 *t++ = *s;
6532 *t = '\0';
6533 m68k_comment_chars = n;
6534 }
6535 break;
6536
6537 case OPTION_BASE_SIZE_DEFAULT_16:
6538 m68k_index_width_default = SIZE_WORD;
6539 break;
6540
6541 case OPTION_BASE_SIZE_DEFAULT_32:
6542 m68k_index_width_default = SIZE_LONG;
6543 break;
6544
6545 case OPTION_DISP_SIZE_DEFAULT_16:
6546 m68k_rel32 = 0;
6547 m68k_rel32_from_cmdline = 1;
6548 break;
6549
6550 case OPTION_DISP_SIZE_DEFAULT_32:
6551 m68k_rel32 = 1;
6552 m68k_rel32_from_cmdline = 1;
6553 break;
6554
6555 default:
6556 return 0;
6557 }
6558
6559 return 1;
6560 }
6561
6562 void
6563 md_show_usage (stream)
6564 FILE *stream;
6565 {
6566 fprintf(stream, "\
6567 680X0 options:\n\
6568 -l use 1 word for refs to undefined symbols [default 2]\n\
6569 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6570 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6571 | -mcpu32 | -m5200\n\
6572 specify variant of 680X0 architecture [default 68020]\n\
6573 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6574 target has/lacks floating-point coprocessor\n\
6575 [default yes for 68020, 68030, and cpu32]\n");
6576 fprintf(stream, "\
6577 -m68851 | -mno-68851\n\
6578 target has/lacks memory-management unit coprocessor\n\
6579 [default yes for 68020 and up]\n\
6580 -pic, -k generate position independent code\n\
6581 -S turn jbsr into jsr\n\
6582 --register-prefix-optional\n\
6583 recognize register names without prefix character\n\
6584 --bitwise-or do not treat `|' as a comment character\n");
6585 fprintf (stream, "\
6586 --base-size-default-16 base reg without size is 16 bits\n\
6587 --base-size-default-32 base reg without size is 32 bits (default)\n\
6588 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6589 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n");
6590 }
6591 \f
6592 #ifdef TEST2
6593
6594 /* TEST2: Test md_assemble() */
6595 /* Warning, this routine probably doesn't work anymore */
6596
6597 main ()
6598 {
6599 struct m68k_it the_ins;
6600 char buf[120];
6601 char *cp;
6602 int n;
6603
6604 m68k_ip_begin ();
6605 for (;;)
6606 {
6607 if (!gets (buf) || !*buf)
6608 break;
6609 if (buf[0] == '|' || buf[1] == '.')
6610 continue;
6611 for (cp = buf; *cp; cp++)
6612 if (*cp == '\t')
6613 *cp = ' ';
6614 if (is_label (buf))
6615 continue;
6616 memset (&the_ins, '\0', sizeof (the_ins));
6617 m68k_ip (&the_ins, buf);
6618 if (the_ins.error)
6619 {
6620 printf ("Error %s in %s\n", the_ins.error, buf);
6621 }
6622 else
6623 {
6624 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6625 for (n = 0; n < the_ins.numo; n++)
6626 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6627 printf (" ");
6628 print_the_insn (&the_ins.opcode[0], stdout);
6629 (void) putchar ('\n');
6630 }
6631 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6632 {
6633 if (the_ins.operands[n].error)
6634 {
6635 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6636 continue;
6637 }
6638 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6639 if (the_ins.operands[n].b_const)
6640 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6641 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6642 if (the_ins.operands[n].b_iadd)
6643 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6644 (void) putchar ('\n');
6645 }
6646 }
6647 m68k_ip_end ();
6648 return 0;
6649 }
6650
6651 is_label (str)
6652 char *str;
6653 {
6654 while (*str == ' ')
6655 str++;
6656 while (*str && *str != ' ')
6657 str++;
6658 if (str[-1] == ':' || str[1] == '=')
6659 return 1;
6660 return 0;
6661 }
6662
6663 #endif
6664
6665 /* Possible states for relaxation:
6666
6667 0 0 branch offset byte (bra, etc)
6668 0 1 word
6669 0 2 long
6670
6671 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6672 1 1 word
6673 1 2 long
6674
6675 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6676 2 1 word-long
6677 2 2 long-word
6678 2 3 long-long
6679
6680 */
6681
6682 /* We have no need to default values of symbols. */
6683
6684 /* ARGSUSED */
6685 symbolS *
6686 md_undefined_symbol (name)
6687 char *name;
6688 {
6689 return 0;
6690 }
6691
6692 /* Round up a section size to the appropriate boundary. */
6693 valueT
6694 md_section_align (segment, size)
6695 segT segment;
6696 valueT size;
6697 {
6698 return size; /* Byte alignment is fine */
6699 }
6700
6701 /* Exactly what point is a PC-relative offset relative TO?
6702 On the 68k, it is relative to the address of the first extension
6703 word. The difference between the addresses of the offset and the
6704 first extension word is stored in fx_pcrel_adjust. */
6705 long
6706 md_pcrel_from (fixP)
6707 fixS *fixP;
6708 {
6709 int adjust;
6710
6711 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6712 -1 as 64. */
6713 adjust = fixP->fx_pcrel_adjust;
6714 if (adjust == 64)
6715 adjust = -1;
6716 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6717 }
6718
6719 #ifndef BFD_ASSEMBLER
6720 /*ARGSUSED*/
6721 void
6722 tc_coff_symbol_emit_hook (ignore)
6723 symbolS *ignore;
6724 {
6725 }
6726
6727 int
6728 tc_coff_sizemachdep (frag)
6729 fragS *frag;
6730 {
6731 switch (frag->fr_subtype & 0x3)
6732 {
6733 case BYTE:
6734 return 1;
6735 case SHORT:
6736 return 2;
6737 case LONG:
6738 return 4;
6739 default:
6740 abort ();
6741 return 0;
6742 }
6743 }
6744 #endif
6745
6746 /* end of tc-m68k.c */
GDB Binutils - Deliverables
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