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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 #include "as.h"
24 #include "safe-ctype.h"
25 #include "obstack.h"
26 #include "subsegs.h"
27 #include "dwarf2dbg.h"
28 #include "dw2gencfi.h"
29
30 #include "opcode/m68k.h"
31 #include "m68k-parse.h"
32
33 #if defined (OBJ_ELF)
34 #include "elf/m68k.h"
35 #endif
36
37 #ifdef M68KCOFF
38 #include "obj-coff.h"
39 #endif
40
41 #ifdef OBJ_ELF
42 static void m68k_elf_cons (int);
43 #endif
44
45 /* This string holds the chars that always start a comment. If the
46 pre-processor is disabled, these aren't very useful. The macro
47 tc_comment_chars points to this. We use this, rather than the
48 usual comment_chars, so that the --bitwise-or option will work. */
49 #if defined (TE_SVR4) || defined (TE_DELTA)
50 const char *m68k_comment_chars = "|#";
51 #else
52 const char *m68k_comment_chars = "|";
53 #endif
54
55 /* This array holds the chars that only start a comment at the beginning of
56 a line. If the line seems to have the form '# 123 filename'
57 .line and .file directives will appear in the pre-processed output */
58 /* Note that input_file.c hand checks for '#' at the beginning of the
59 first line of the input file. This is because the compiler outputs
60 #NO_APP at the beginning of its output. */
61 /* Also note that comments like this one will always work. */
62 const char line_comment_chars[] = "#*";
63
64 const char line_separator_chars[] = ";";
65
66 /* Chars that can be used to separate mant from exp in floating point nums. */
67 const char EXP_CHARS[] = "eE";
68
69 /* Chars that mean this number is a floating point constant, as
70 in "0f12.456" or "0d1.2345e12". */
71
72 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
73
74 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
75 changed in read.c . Ideally it shouldn't have to know about it at all,
76 but nothing is ideal around here. */
77
78 /* Are we trying to generate PIC code? If so, absolute references
79 ought to be made into linkage table references or pc-relative
80 references. Not implemented. For ELF there are other means
81 to denote pic relocations. */
82 int flag_want_pic;
83
84 static int flag_short_refs; /* -l option. */
85 static int flag_long_jumps; /* -S option. */
86 static int flag_keep_pcrel; /* --pcrel option. */
87
88 #ifdef REGISTER_PREFIX_OPTIONAL
89 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
90 #else
91 int flag_reg_prefix_optional;
92 #endif
93
94 /* Whether --register-prefix-optional was used on the command line. */
95 static int reg_prefix_optional_seen;
96
97 /* The floating point coprocessor to use by default. */
98 static enum m68k_register m68k_float_copnum = COP1;
99
100 /* If this is non-zero, then references to number(%pc) will be taken
101 to refer to number, rather than to %pc + number. */
102 static int m68k_abspcadd;
103
104 /* If this is non-zero, then the quick forms of the move, add, and sub
105 instructions are used when possible. */
106 static int m68k_quick = 1;
107
108 /* If this is non-zero, then if the size is not specified for a base
109 or outer displacement, the assembler assumes that the size should
110 be 32 bits. */
111 static int m68k_rel32 = 1;
112
113 /* This is non-zero if m68k_rel32 was set from the command line. */
114 static int m68k_rel32_from_cmdline;
115
116 /* The default width to use for an index register when using a base
117 displacement. */
118 static enum m68k_size m68k_index_width_default = SIZE_LONG;
119
120 /* We want to warn if any text labels are misaligned. In order to get
121 the right line number, we need to record the line number for each
122 label. */
123 struct label_line
124 {
125 struct label_line *next;
126 symbolS *label;
127 char *file;
128 unsigned int line;
129 int text;
130 };
131
132 /* The list of labels. */
133
134 static struct label_line *labels;
135
136 /* The current label. */
137
138 static struct label_line *current_label;
139
140 /* Pointer to list holding the opcodes sorted by name. */
141 static struct m68k_opcode const ** m68k_sorted_opcodes;
142
143 /* Its an arbitrary name: This means I don't approve of it.
144 See flames below. */
145 static struct obstack robyn;
146
147 struct m68k_incant
148 {
149 const char *m_operands;
150 unsigned long m_opcode;
151 short m_opnum;
152 short m_codenum;
153 int m_arch;
154 struct m68k_incant *m_next;
155 };
156
157 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
158 #define gettwo(x) (((x)->m_opcode)&0xffff)
159
160 static const enum m68k_register m68000_ctrl[] = { 0 };
161 static const enum m68k_register m68010_ctrl[] = {
162 SFC, DFC, USP, VBR,
163 0
164 };
165 static const enum m68k_register m68020_ctrl[] = {
166 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
167 0
168 };
169 static const enum m68k_register m68040_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
171 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
172 0
173 };
174 static const enum m68k_register m68060_ctrl[] = {
175 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
176 USP, VBR, URP, SRP, PCR,
177 0
178 };
179 static const enum m68k_register mcf_ctrl[] = {
180 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
181 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
182 0
183 };
184 static const enum m68k_register mcf51_ctrl[] = {
185 VBR, CPUCR,
186 0
187 };
188 static const enum m68k_register mcf5206_ctrl[] = {
189 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
190 0
191 };
192 static const enum m68k_register mcf5208_ctrl[] = {
193 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
194 0
195 };
196 static const enum m68k_register mcf5210a_ctrl[] = {
197 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
198 0
199 };
200 static const enum m68k_register mcf5213_ctrl[] = {
201 VBR, RAMBAR, RAMBAR1, FLASHBAR,
202 0
203 };
204 static const enum m68k_register mcf5216_ctrl[] = {
205 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
206 0
207 };
208 static const enum m68k_register mcf5221x_ctrl[] = {
209 VBR, FLASHBAR, RAMBAR, RAMBAR1,
210 0
211 };
212 static const enum m68k_register mcf52223_ctrl[] = {
213 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
214 0
215 };
216 static const enum m68k_register mcf52235_ctrl[] = {
217 VBR, FLASHBAR, RAMBAR, RAMBAR1,
218 0
219 };
220 static const enum m68k_register mcf5225_ctrl[] = {
221 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
222 0
223 };
224 static const enum m68k_register mcf52259_ctrl[] = {
225 VBR, FLASHBAR, RAMBAR, RAMBAR1,
226 0
227 };
228 static const enum m68k_register mcf52277_ctrl[] = {
229 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
230 0
231 };
232 static const enum m68k_register mcf5235_ctrl[] = {
233 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
234 0
235 };
236 static const enum m68k_register mcf5249_ctrl[] = {
237 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
238 0
239 };
240 static const enum m68k_register mcf5250_ctrl[] = {
241 VBR,
242 0
243 };
244 static const enum m68k_register mcf5253_ctrl[] = {
245 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
246 0
247 };
248 static const enum m68k_register mcf5271_ctrl[] = {
249 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
250 0
251 };
252 static const enum m68k_register mcf5272_ctrl[] = {
253 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
254 0
255 };
256 static const enum m68k_register mcf5275_ctrl[] = {
257 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
258 0
259 };
260 static const enum m68k_register mcf5282_ctrl[] = {
261 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
262 0
263 };
264 static const enum m68k_register mcf53017_ctrl[] = {
265 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
266 0
267 };
268 static const enum m68k_register mcf5307_ctrl[] = {
269 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR,
270 0
271 };
272 static const enum m68k_register mcf5329_ctrl[] = {
273 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
274 0
275 };
276 static const enum m68k_register mcf5373_ctrl[] = {
277 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
278 0
279 };
280 static const enum m68k_register mcfv4e_ctrl[] = {
281 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
282 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
283 MBAR, SECMBAR,
284 MPCR /* Multiprocessor Control register */,
285 EDRAMBAR /* Embedded DRAM Base Address Register */,
286 /* Permutation control registers. */
287 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
288 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
289 /* Legacy names */
290 TC /* ASID */, BUSCR /* MMUBAR */,
291 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
292 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
293 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
294 0
295 };
296 static const enum m68k_register mcf5407_ctrl[] = {
297 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
298 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
299 /* Legacy names */
300 TC /* ASID */,
301 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
302 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
303 0
304 };
305 static const enum m68k_register mcf54455_ctrl[] = {
306 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
307 VBR, PC, RAMBAR1, MBAR,
308 /* Legacy names */
309 TC /* ASID */, BUSCR /* MMUBAR */,
310 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
311 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
312 0
313 };
314 static const enum m68k_register mcf5475_ctrl[] = {
315 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
316 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
317 /* Legacy names */
318 TC /* ASID */, BUSCR /* MMUBAR */,
319 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
320 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
321 0
322 };
323 static const enum m68k_register mcf5485_ctrl[] = {
324 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
325 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
326 /* Legacy names */
327 TC /* ASID */, BUSCR /* MMUBAR */,
328 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
329 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
330 0
331 };
332 static const enum m68k_register fido_ctrl[] = {
333 SFC, DFC, USP, VBR, CAC, MBO,
334 0
335 };
336 #define cpu32_ctrl m68010_ctrl
337
338 static const enum m68k_register *control_regs;
339
340 /* Internal form of a 68020 instruction. */
341 struct m68k_it
342 {
343 const char *error;
344 const char *args; /* List of opcode info. */
345 int numargs;
346
347 int numo; /* Number of shorts in opcode. */
348 short opcode[11];
349
350 struct m68k_op operands[6];
351
352 int nexp; /* Number of exprs in use. */
353 struct m68k_exp exprs[4];
354
355 int nfrag; /* Number of frags we have to produce. */
356 struct
357 {
358 int fragoff; /* Where in the current opcode the frag ends. */
359 symbolS *fadd;
360 offsetT foff;
361 int fragty;
362 }
363 fragb[4];
364
365 int nrel; /* Num of reloc strucs in use. */
366 struct
367 {
368 int n;
369 expressionS exp;
370 char wid;
371 char pcrel;
372 /* In a pc relative address the difference between the address
373 of the offset and the address that the offset is relative
374 to. This depends on the addressing mode. Basically this
375 is the value to put in the offset field to address the
376 first byte of the offset, without regarding the special
377 significance of some values (in the branch instruction, for
378 example). */
379 int pcrel_fix;
380 #ifdef OBJ_ELF
381 /* Whether this expression needs special pic relocation, and if
382 so, which. */
383 enum pic_relocation pic_reloc;
384 #endif
385 }
386 reloc[5]; /* Five is enough??? */
387 };
388
389 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
390 #define float_of_arch(x) ((x) & mfloat)
391 #define mmu_of_arch(x) ((x) & mmmu)
392 #define arch_coldfire_p(x) ((x) & mcfisa_a)
393 #define arch_coldfire_fpu(x) ((x) & cfloat)
394
395 /* Macros for determining if cpu supports a specific addressing mode. */
396 #define HAVE_LONG_DISP(x) \
397 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
398 #define HAVE_LONG_CALL(x) \
399 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
400 #define HAVE_LONG_COND(x) \
401 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
402 #define HAVE_LONG_BRANCH(x) \
403 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
404 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
405
406 static struct m68k_it the_ins; /* The instruction being assembled. */
407
408 #define op(ex) ((ex)->exp.X_op)
409 #define adds(ex) ((ex)->exp.X_add_symbol)
410 #define subs(ex) ((ex)->exp.X_op_symbol)
411 #define offs(ex) ((ex)->exp.X_add_number)
412
413 /* Macros for adding things to the m68k_it struct. */
414 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
415
416 /* Like addword, but goes BEFORE general operands. */
417
418 static void
419 insop (int w, const struct m68k_incant *opcode)
420 {
421 int z;
422 for (z = the_ins.numo; z > opcode->m_codenum; --z)
423 the_ins.opcode[z] = the_ins.opcode[z - 1];
424 for (z = 0; z < the_ins.nrel; z++)
425 the_ins.reloc[z].n += 2;
426 for (z = 0; z < the_ins.nfrag; z++)
427 the_ins.fragb[z].fragoff++;
428 the_ins.opcode[opcode->m_codenum] = w;
429 the_ins.numo++;
430 }
431
432 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
433 Blecch. */
434 static void
435 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
436 {
437 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
438 ? the_ins.numo * 2 - 1
439 : (width == 'b'
440 ? the_ins.numo * 2 + 1
441 : the_ins.numo * 2));
442 the_ins.reloc[the_ins.nrel].exp = exp->exp;
443 the_ins.reloc[the_ins.nrel].wid = width;
444 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
445 #ifdef OBJ_ELF
446 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
447 #endif
448 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
449 }
450
451 /* Cause an extra frag to be generated here, inserting up to 10 bytes
452 (that value is chosen in the frag_var call in md_assemble). TYPE
453 is the subtype of the frag to be generated; its primary type is
454 rs_machine_dependent.
455
456 The TYPE parameter is also used by md_convert_frag_1 and
457 md_estimate_size_before_relax. The appropriate type of fixup will
458 be emitted by md_convert_frag_1.
459
460 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
461 static void
462 add_frag (symbolS *add, offsetT off, int type)
463 {
464 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
465 the_ins.fragb[the_ins.nfrag].fadd = add;
466 the_ins.fragb[the_ins.nfrag].foff = off;
467 the_ins.fragb[the_ins.nfrag++].fragty = type;
468 }
469
470 #define isvar(ex) \
471 (op (ex) != O_constant && op (ex) != O_big)
472
473 static char *crack_operand (char *str, struct m68k_op *opP);
474 static int get_num (struct m68k_exp *exp, int ok);
475 static int reverse_16_bits (int in);
476 static int reverse_8_bits (int in);
477 static void install_gen_operand (int mode, int val);
478 static void install_operand (int mode, int val);
479 static void s_bss (int);
480 static void s_data1 (int);
481 static void s_data2 (int);
482 static void s_even (int);
483 static void s_proc (int);
484 static void s_chip (int);
485 static void s_fopt (int);
486 static void s_opt (int);
487 static void s_reg (int);
488 static void s_restore (int);
489 static void s_save (int);
490 static void s_mri_if (int);
491 static void s_mri_else (int);
492 static void s_mri_endi (int);
493 static void s_mri_break (int);
494 static void s_mri_next (int);
495 static void s_mri_for (int);
496 static void s_mri_endf (int);
497 static void s_mri_repeat (int);
498 static void s_mri_until (int);
499 static void s_mri_while (int);
500 static void s_mri_endw (int);
501 static void s_m68k_cpu (int);
502 static void s_m68k_arch (int);
503
504 struct m68k_cpu
505 {
506 unsigned long arch; /* Architecture features. */
507 const enum m68k_register *control_regs; /* Control regs on chip */
508 const char *name; /* Name */
509 int alias; /* Alias for a cannonical name. If 1, then
510 succeeds canonical name, if -1 then
511 succeeds canonical name, if <-1 ||>1 this is a
512 deprecated name, and the next/previous name
513 should be used. */
514 };
515
516 /* We hold flags for features explicitly enabled and explicitly
517 disabled. */
518 static int current_architecture;
519 static int not_current_architecture;
520 static const struct m68k_cpu *selected_arch;
521 static const struct m68k_cpu *selected_cpu;
522 static int initialized;
523
524 /* Architecture models. */
525 static const struct m68k_cpu m68k_archs[] =
526 {
527 {m68000, m68000_ctrl, "68000", 0},
528 {m68010, m68010_ctrl, "68010", 0},
529 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
530 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
531 {m68040, m68040_ctrl, "68040", 0},
532 {m68060, m68060_ctrl, "68060", 0},
533 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
534 {fido_a, fido_ctrl, "fidoa", 0},
535 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
536 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
537 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
538 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
539 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
540 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
541 {0,0,NULL, 0}
542 };
543
544 /* For -mno-mac we want to turn off all types of mac. */
545 static const unsigned no_mac = mcfmac | mcfemac;
546
547 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
548 for either. */
549 static const struct m68k_cpu m68k_extensions[] =
550 {
551 {m68851, NULL, "68851", -1},
552 {m68881, NULL, "68881", -1},
553 {m68881, NULL, "68882", -1},
554
555 {cfloat|m68881, NULL, "float", 0},
556
557 {mcfhwdiv, NULL, "div", 1},
558 {mcfusp, NULL, "usp", 1},
559 {mcfmac, (void *)&no_mac, "mac", 1},
560 {mcfemac, NULL, "emac", 1},
561
562 {0,NULL,NULL, 0}
563 };
564
565 /* Processor list */
566 static const struct m68k_cpu m68k_cpus[] =
567 {
568 {m68000, m68000_ctrl, "68000", 0},
569 {m68000, m68000_ctrl, "68ec000", 1},
570 {m68000, m68000_ctrl, "68hc000", 1},
571 {m68000, m68000_ctrl, "68hc001", 1},
572 {m68000, m68000_ctrl, "68008", 1},
573 {m68000, m68000_ctrl, "68302", 1},
574 {m68000, m68000_ctrl, "68306", 1},
575 {m68000, m68000_ctrl, "68307", 1},
576 {m68000, m68000_ctrl, "68322", 1},
577 {m68000, m68000_ctrl, "68356", 1},
578 {m68010, m68010_ctrl, "68010", 0},
579 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
580 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
581 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
582 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
583 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
584 {m68040, m68040_ctrl, "68040", 0},
585 {m68040, m68040_ctrl, "68ec040", 1},
586 {m68060, m68060_ctrl, "68060", 0},
587 {m68060, m68060_ctrl, "68ec060", 1},
588
589 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
590 {cpu32|m68881, cpu32_ctrl, "68330", 1},
591 {cpu32|m68881, cpu32_ctrl, "68331", 1},
592 {cpu32|m68881, cpu32_ctrl, "68332", 1},
593 {cpu32|m68881, cpu32_ctrl, "68333", 1},
594 {cpu32|m68881, cpu32_ctrl, "68334", 1},
595 {cpu32|m68881, cpu32_ctrl, "68336", 1},
596 {cpu32|m68881, cpu32_ctrl, "68340", 1},
597 {cpu32|m68881, cpu32_ctrl, "68341", 1},
598 {cpu32|m68881, cpu32_ctrl, "68349", 1},
599 {cpu32|m68881, cpu32_ctrl, "68360", 1},
600
601 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0},
602 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1},
603 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1},
604 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1},
605 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1},
606 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1},
607
608 {mcfisa_a, mcf_ctrl, "5200", 0},
609 {mcfisa_a, mcf_ctrl, "5202", 1},
610 {mcfisa_a, mcf_ctrl, "5204", 1},
611 {mcfisa_a, mcf5206_ctrl, "5206", 1},
612
613 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
614
615 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
617
618 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
619 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
620
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
623 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
624
625 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
628
629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0},
630
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
633
634 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
638
639 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
641
642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1},
643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0},
644
645 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
646 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
649 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
650
651 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
652 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
653 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
654
655 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1},
656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1},
657 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1},
658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1},
659 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1},
660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0},
661
662 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
663 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
664
665 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
666
667 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
668 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
669
670 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
673 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
674
675 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1},
676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1},
677 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1},
678 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1},
679 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1},
680 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1},
681 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0},
682
683 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
684
685 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
686 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
687 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
688 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
689
690 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
691 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
692 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
693
694 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
695
696 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
697 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
698 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
699 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
700 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
701 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
702
703 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
704 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
705 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
706 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
707 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
708 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
709 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
710
711 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
712 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
713 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
714 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
715 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
716 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
717 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
718
719 {fido_a, fido_ctrl, "fidoa", 0},
720 {fido_a, fido_ctrl, "fido", 1},
721
722 {0,NULL,NULL, 0}
723 };
724
725 static const struct m68k_cpu *m68k_lookup_cpu
726 (const char *, const struct m68k_cpu *, int, int *);
727 static int m68k_set_arch (const char *, int, int);
728 static int m68k_set_cpu (const char *, int, int);
729 static int m68k_set_extension (const char *, int, int);
730 static void m68k_init_arch (void);
731
732 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
733 architecture and we have a lot of relaxation modes. */
734
735 /* Macros used in the relaxation code. */
736 #define TAB(x,y) (((x) << 2) + (y))
737 #define TABTYPE(x) ((x) >> 2)
738
739 /* Relaxation states. */
740 #define BYTE 0
741 #define SHORT 1
742 #define LONG 2
743 #define SZ_UNDEF 3
744
745 /* Here are all the relaxation modes we support. First we can relax ordinary
746 branches. On 68020 and higher and on CPU32 all branch instructions take
747 three forms, so on these CPUs all branches always remain as such. When we
748 have to expand to the LONG form on a 68000, though, we substitute an
749 absolute jump instead. This is a direct replacement for unconditional
750 branches and a branch over a jump for conditional branches. However, if the
751 user requires PIC and disables this with --pcrel, we can only relax between
752 BYTE and SHORT forms, punting if that isn't enough. This gives us four
753 different relaxation modes for branches: */
754
755 #define BRANCHBWL 0 /* Branch byte, word, or long. */
756 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
757 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
758 #define BRANCHBW 3 /* Branch byte or word. */
759
760 /* We also relax coprocessor branches and DBcc's. All CPUs that support
761 coprocessor branches support them in word and long forms, so we have only
762 one relaxation mode for them. DBcc's are word only on all CPUs. We can
763 relax them to the LONG form with a branch-around sequence. This sequence
764 can use a long branch (if available) or an absolute jump (if acceptable).
765 This gives us two relaxation modes. If long branches are not available and
766 absolute jumps are not acceptable, we don't relax DBcc's. */
767
768 #define FBRANCH 4 /* Coprocessor branch. */
769 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
770 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
771
772 /* That's all for instruction relaxation. However, we also relax PC-relative
773 operands. Specifically, we have three operand relaxation modes. On the
774 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
775 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
776 two. Also PC+displacement+index operands in their simple form (with a non-
777 suppressed index without memory indirection) are supported on all CPUs, but
778 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
779 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
780 form of the PC+displacement+index operand. Finally, some absolute operands
781 can be relaxed down to 16-bit PC-relative. */
782
783 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
784 #define PCINDEX 8 /* PC + displacement + index. */
785 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
786
787 /* This relaxation is required for branches where there is no long
788 branch and we are in pcrel mode. We generate a bne/beq pair. */
789 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs
790 */
791
792 /* Note that calls to frag_var need to specify the maximum expansion
793 needed; this is currently 12 bytes for bne/beq pair. */
794 #define FRAG_VAR_SIZE 12
795
796 /* The fields are:
797 How far Forward this mode will reach:
798 How far Backward this mode will reach:
799 How many bytes this mode will add to the size of the frag
800 Which mode to go to if the offset won't fit in this one
801
802 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
803 relax_typeS md_relax_table[] =
804 {
805 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
806 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
807 { 0, 0, 4, 0 },
808 { 1, 1, 0, 0 },
809
810 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
811 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
812 { 0, 0, 4, 0 },
813 { 1, 1, 0, 0 },
814
815 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
816 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
817 { 0, 0, 6, 0 },
818 { 1, 1, 0, 0 },
819
820 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
821 { 0, 0, 2, 0 },
822 { 1, 1, 0, 0 },
823 { 1, 1, 0, 0 },
824
825 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
826 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
827 { 0, 0, 4, 0 },
828 { 1, 1, 0, 0 },
829
830 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
831 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
832 { 0, 0, 10, 0 },
833 { 1, 1, 0, 0 },
834
835 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
836 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
837 { 0, 0, 10, 0 },
838 { 1, 1, 0, 0 },
839
840 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
841 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
842 { 0, 0, 6, 0 },
843 { 1, 1, 0, 0 },
844
845 { 125, -130, 0, TAB (PCINDEX, SHORT) },
846 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
847 { 0, 0, 4, 0 },
848 { 1, 1, 0, 0 },
849
850 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
851 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
852 { 0, 0, 4, 0 },
853 { 1, 1, 0, 0 },
854
855 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
856 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
857 { 0, 0, 10, 0 },
858 { 1, 1, 0, 0 },
859 };
860
861 /* These are the machine dependent pseudo-ops. These are included so
862 the assembler can work on the output from the SUN C compiler, which
863 generates these. */
864
865 /* This table describes all the machine specific pseudo-ops the assembler
866 has to support. The fields are:
867 pseudo-op name without dot
868 function to call to execute this pseudo-op
869 Integer arg to pass to the function. */
870 const pseudo_typeS md_pseudo_table[] =
871 {
872 {"data1", s_data1, 0},
873 {"data2", s_data2, 0},
874 {"bss", s_bss, 0},
875 {"even", s_even, 0},
876 {"skip", s_space, 0},
877 {"proc", s_proc, 0},
878 #if defined (TE_SUN3) || defined (OBJ_ELF)
879 {"align", s_align_bytes, 0},
880 #endif
881 #ifdef OBJ_ELF
882 {"swbeg", s_ignore, 0},
883 {"long", m68k_elf_cons, 4},
884 #endif
885 {"extend", float_cons, 'x'},
886 {"ldouble", float_cons, 'x'},
887
888 {"arch", s_m68k_arch, 0},
889 {"cpu", s_m68k_cpu, 0},
890
891 /* The following pseudo-ops are supported for MRI compatibility. */
892 {"chip", s_chip, 0},
893 {"comline", s_space, 1},
894 {"fopt", s_fopt, 0},
895 {"mask2", s_ignore, 0},
896 {"opt", s_opt, 0},
897 {"reg", s_reg, 0},
898 {"restore", s_restore, 0},
899 {"save", s_save, 0},
900
901 {"if", s_mri_if, 0},
902 {"if.b", s_mri_if, 'b'},
903 {"if.w", s_mri_if, 'w'},
904 {"if.l", s_mri_if, 'l'},
905 {"else", s_mri_else, 0},
906 {"else.s", s_mri_else, 's'},
907 {"else.l", s_mri_else, 'l'},
908 {"endi", s_mri_endi, 0},
909 {"break", s_mri_break, 0},
910 {"break.s", s_mri_break, 's'},
911 {"break.l", s_mri_break, 'l'},
912 {"next", s_mri_next, 0},
913 {"next.s", s_mri_next, 's'},
914 {"next.l", s_mri_next, 'l'},
915 {"for", s_mri_for, 0},
916 {"for.b", s_mri_for, 'b'},
917 {"for.w", s_mri_for, 'w'},
918 {"for.l", s_mri_for, 'l'},
919 {"endf", s_mri_endf, 0},
920 {"repeat", s_mri_repeat, 0},
921 {"until", s_mri_until, 0},
922 {"until.b", s_mri_until, 'b'},
923 {"until.w", s_mri_until, 'w'},
924 {"until.l", s_mri_until, 'l'},
925 {"while", s_mri_while, 0},
926 {"while.b", s_mri_while, 'b'},
927 {"while.w", s_mri_while, 'w'},
928 {"while.l", s_mri_while, 'l'},
929 {"endw", s_mri_endw, 0},
930
931 {0, 0, 0}
932 };
933
934 /* The mote pseudo ops are put into the opcode table, since they
935 don't start with a . they look like opcodes to gas. */
936
937 const pseudo_typeS mote_pseudo_table[] =
938 {
939
940 {"dcl", cons, 4},
941 {"dc", cons, 2},
942 {"dcw", cons, 2},
943 {"dcb", cons, 1},
944
945 {"dsl", s_space, 4},
946 {"ds", s_space, 2},
947 {"dsw", s_space, 2},
948 {"dsb", s_space, 1},
949
950 {"xdef", s_globl, 0},
951 #ifdef OBJ_ELF
952 {"align", s_align_bytes, 0},
953 #else
954 {"align", s_align_ptwo, 0},
955 #endif
956 #ifdef M68KCOFF
957 {"sect", obj_coff_section, 0},
958 {"section", obj_coff_section, 0},
959 #endif
960 {0, 0, 0}
961 };
962
963 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
964 gives identical results to a 32-bit host. */
965 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
966 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
967
968 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
969 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
970 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
971 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
972
973 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
974 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
975 #define islong(x) (1)
976
977 static char notend_table[256];
978 static char alt_notend_table[256];
979 #define notend(s) \
980 (! (notend_table[(unsigned char) *s] \
981 || (*s == ':' \
982 && alt_notend_table[(unsigned char) s[1]])))
983
984 #ifdef OBJ_ELF
985
986 /* Return zero if the reference to SYMBOL from within the same segment may
987 be relaxed. */
988
989 /* On an ELF system, we can't relax an externally visible symbol,
990 because it may be overridden by a shared library. However, if
991 TARGET_OS is "elf", then we presume that we are assembling for an
992 embedded system, in which case we don't have to worry about shared
993 libraries, and we can relax any external sym. */
994
995 #define relaxable_symbol(symbol) \
996 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
997 || S_IS_WEAK (symbol)))
998
999 /* Compute the relocation code for a fixup of SIZE bytes, using pc
1000 relative relocation if PCREL is non-zero. PIC says whether a special
1001 pic relocation was requested. */
1002
1003 static bfd_reloc_code_real_type
1004 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
1005 {
1006 switch (pic)
1007 {
1008 case pic_got_pcrel:
1009 switch (size)
1010 {
1011 case 1:
1012 return BFD_RELOC_8_GOT_PCREL;
1013 case 2:
1014 return BFD_RELOC_16_GOT_PCREL;
1015 case 4:
1016 return BFD_RELOC_32_GOT_PCREL;
1017 }
1018 break;
1019
1020 case pic_got_off:
1021 switch (size)
1022 {
1023 case 1:
1024 return BFD_RELOC_8_GOTOFF;
1025 case 2:
1026 return BFD_RELOC_16_GOTOFF;
1027 case 4:
1028 return BFD_RELOC_32_GOTOFF;
1029 }
1030 break;
1031
1032 case pic_plt_pcrel:
1033 switch (size)
1034 {
1035 case 1:
1036 return BFD_RELOC_8_PLT_PCREL;
1037 case 2:
1038 return BFD_RELOC_16_PLT_PCREL;
1039 case 4:
1040 return BFD_RELOC_32_PLT_PCREL;
1041 }
1042 break;
1043
1044 case pic_plt_off:
1045 switch (size)
1046 {
1047 case 1:
1048 return BFD_RELOC_8_PLTOFF;
1049 case 2:
1050 return BFD_RELOC_16_PLTOFF;
1051 case 4:
1052 return BFD_RELOC_32_PLTOFF;
1053 }
1054 break;
1055
1056 case pic_tls_gd:
1057 switch (size)
1058 {
1059 case 1:
1060 return BFD_RELOC_68K_TLS_GD8;
1061 case 2:
1062 return BFD_RELOC_68K_TLS_GD16;
1063 case 4:
1064 return BFD_RELOC_68K_TLS_GD32;
1065 }
1066 break;
1067
1068 case pic_tls_ldm:
1069 switch (size)
1070 {
1071 case 1:
1072 return BFD_RELOC_68K_TLS_LDM8;
1073 case 2:
1074 return BFD_RELOC_68K_TLS_LDM16;
1075 case 4:
1076 return BFD_RELOC_68K_TLS_LDM32;
1077 }
1078 break;
1079
1080 case pic_tls_ldo:
1081 switch (size)
1082 {
1083 case 1:
1084 return BFD_RELOC_68K_TLS_LDO8;
1085 case 2:
1086 return BFD_RELOC_68K_TLS_LDO16;
1087 case 4:
1088 return BFD_RELOC_68K_TLS_LDO32;
1089 }
1090 break;
1091
1092 case pic_tls_ie:
1093 switch (size)
1094 {
1095 case 1:
1096 return BFD_RELOC_68K_TLS_IE8;
1097 case 2:
1098 return BFD_RELOC_68K_TLS_IE16;
1099 case 4:
1100 return BFD_RELOC_68K_TLS_IE32;
1101 }
1102 break;
1103
1104 case pic_tls_le:
1105 switch (size)
1106 {
1107 case 1:
1108 return BFD_RELOC_68K_TLS_LE8;
1109 case 2:
1110 return BFD_RELOC_68K_TLS_LE16;
1111 case 4:
1112 return BFD_RELOC_68K_TLS_LE32;
1113 }
1114 break;
1115
1116 case pic_none:
1117 if (pcrel)
1118 {
1119 switch (size)
1120 {
1121 case 1:
1122 return BFD_RELOC_8_PCREL;
1123 case 2:
1124 return BFD_RELOC_16_PCREL;
1125 case 4:
1126 return BFD_RELOC_32_PCREL;
1127 }
1128 }
1129 else
1130 {
1131 switch (size)
1132 {
1133 case 1:
1134 return BFD_RELOC_8;
1135 case 2:
1136 return BFD_RELOC_16;
1137 case 4:
1138 return BFD_RELOC_32;
1139 }
1140 }
1141 }
1142
1143 if (pcrel)
1144 {
1145 if (pic == pic_none)
1146 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1147 else
1148 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1149 }
1150 else
1151 {
1152 if (pic == pic_none)
1153 as_bad (_("Can not do %d byte relocation"), size);
1154 else
1155 as_bad (_("Can not do %d byte pic relocation"), size);
1156 }
1157
1158 return BFD_RELOC_NONE;
1159 }
1160
1161 /* Here we decide which fixups can be adjusted to make them relative
1162 to the beginning of the section instead of the symbol. Basically
1163 we need to make sure that the dynamic relocations are done
1164 correctly, so in some cases we force the original symbol to be
1165 used. */
1166 int
1167 tc_m68k_fix_adjustable (fixS *fixP)
1168 {
1169 /* Adjust_reloc_syms doesn't know about the GOT. */
1170 switch (fixP->fx_r_type)
1171 {
1172 case BFD_RELOC_8_GOT_PCREL:
1173 case BFD_RELOC_16_GOT_PCREL:
1174 case BFD_RELOC_32_GOT_PCREL:
1175 case BFD_RELOC_8_GOTOFF:
1176 case BFD_RELOC_16_GOTOFF:
1177 case BFD_RELOC_32_GOTOFF:
1178 case BFD_RELOC_8_PLT_PCREL:
1179 case BFD_RELOC_16_PLT_PCREL:
1180 case BFD_RELOC_32_PLT_PCREL:
1181 case BFD_RELOC_8_PLTOFF:
1182 case BFD_RELOC_16_PLTOFF:
1183 case BFD_RELOC_32_PLTOFF:
1184 case BFD_RELOC_68K_TLS_GD32:
1185 case BFD_RELOC_68K_TLS_GD16:
1186 case BFD_RELOC_68K_TLS_GD8:
1187 case BFD_RELOC_68K_TLS_LDM32:
1188 case BFD_RELOC_68K_TLS_LDM16:
1189 case BFD_RELOC_68K_TLS_LDM8:
1190 case BFD_RELOC_68K_TLS_LDO32:
1191 case BFD_RELOC_68K_TLS_LDO16:
1192 case BFD_RELOC_68K_TLS_LDO8:
1193 case BFD_RELOC_68K_TLS_IE32:
1194 case BFD_RELOC_68K_TLS_IE16:
1195 case BFD_RELOC_68K_TLS_IE8:
1196 case BFD_RELOC_68K_TLS_LE32:
1197 case BFD_RELOC_68K_TLS_LE16:
1198 case BFD_RELOC_68K_TLS_LE8:
1199 return 0;
1200
1201 case BFD_RELOC_VTABLE_INHERIT:
1202 case BFD_RELOC_VTABLE_ENTRY:
1203 return 0;
1204
1205 default:
1206 return 1;
1207 }
1208 }
1209
1210 #else /* !OBJ_ELF */
1211
1212 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1213
1214 /* PR gas/3041 Weak symbols are not relaxable
1215 because they must be treated as extern. */
1216 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1217
1218 #endif /* OBJ_ELF */
1219
1220 arelent *
1221 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1222 {
1223 arelent *reloc;
1224 bfd_reloc_code_real_type code;
1225
1226 /* If the tcbit is set, then this was a fixup of a negative value
1227 that was never resolved. We do not have a reloc to handle this,
1228 so just return. We assume that other code will have detected this
1229 situation and produced a helpful error message, so we just tell the
1230 user that the reloc cannot be produced. */
1231 if (fixp->fx_tcbit)
1232 {
1233 if (fixp->fx_addsy)
1234 as_bad_where (fixp->fx_file, fixp->fx_line,
1235 _("Unable to produce reloc against symbol '%s'"),
1236 S_GET_NAME (fixp->fx_addsy));
1237 return NULL;
1238 }
1239
1240 if (fixp->fx_r_type != BFD_RELOC_NONE)
1241 {
1242 code = fixp->fx_r_type;
1243
1244 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1245 that fixup_segment converted a non-PC relative reloc into a
1246 PC relative reloc. In such a case, we need to convert the
1247 reloc code. */
1248 if (fixp->fx_pcrel)
1249 {
1250 switch (code)
1251 {
1252 case BFD_RELOC_8:
1253 code = BFD_RELOC_8_PCREL;
1254 break;
1255 case BFD_RELOC_16:
1256 code = BFD_RELOC_16_PCREL;
1257 break;
1258 case BFD_RELOC_32:
1259 code = BFD_RELOC_32_PCREL;
1260 break;
1261 case BFD_RELOC_8_PCREL:
1262 case BFD_RELOC_16_PCREL:
1263 case BFD_RELOC_32_PCREL:
1264 case BFD_RELOC_8_GOT_PCREL:
1265 case BFD_RELOC_16_GOT_PCREL:
1266 case BFD_RELOC_32_GOT_PCREL:
1267 case BFD_RELOC_8_GOTOFF:
1268 case BFD_RELOC_16_GOTOFF:
1269 case BFD_RELOC_32_GOTOFF:
1270 case BFD_RELOC_8_PLT_PCREL:
1271 case BFD_RELOC_16_PLT_PCREL:
1272 case BFD_RELOC_32_PLT_PCREL:
1273 case BFD_RELOC_8_PLTOFF:
1274 case BFD_RELOC_16_PLTOFF:
1275 case BFD_RELOC_32_PLTOFF:
1276 case BFD_RELOC_68K_TLS_GD32:
1277 case BFD_RELOC_68K_TLS_GD16:
1278 case BFD_RELOC_68K_TLS_GD8:
1279 case BFD_RELOC_68K_TLS_LDM32:
1280 case BFD_RELOC_68K_TLS_LDM16:
1281 case BFD_RELOC_68K_TLS_LDM8:
1282 case BFD_RELOC_68K_TLS_LDO32:
1283 case BFD_RELOC_68K_TLS_LDO16:
1284 case BFD_RELOC_68K_TLS_LDO8:
1285 case BFD_RELOC_68K_TLS_IE32:
1286 case BFD_RELOC_68K_TLS_IE16:
1287 case BFD_RELOC_68K_TLS_IE8:
1288 case BFD_RELOC_68K_TLS_LE32:
1289 case BFD_RELOC_68K_TLS_LE16:
1290 case BFD_RELOC_68K_TLS_LE8:
1291 break;
1292 default:
1293 as_bad_where (fixp->fx_file, fixp->fx_line,
1294 _("Cannot make %s relocation PC relative"),
1295 bfd_get_reloc_code_name (code));
1296 }
1297 }
1298 }
1299 else
1300 {
1301 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1302 switch (F (fixp->fx_size, fixp->fx_pcrel))
1303 {
1304 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1305 MAP (1, 0, BFD_RELOC_8);
1306 MAP (2, 0, BFD_RELOC_16);
1307 MAP (4, 0, BFD_RELOC_32);
1308 MAP (1, 1, BFD_RELOC_8_PCREL);
1309 MAP (2, 1, BFD_RELOC_16_PCREL);
1310 MAP (4, 1, BFD_RELOC_32_PCREL);
1311 default:
1312 abort ();
1313 }
1314 }
1315 #undef F
1316 #undef MAP
1317
1318 reloc = (arelent *) xmalloc (sizeof (arelent));
1319 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1320 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1321 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1322 #ifndef OBJ_ELF
1323 if (fixp->fx_pcrel)
1324 reloc->addend = fixp->fx_addnumber;
1325 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1326 && fixp->fx_addsy
1327 && S_IS_WEAK (fixp->fx_addsy)
1328 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1329 {
1330 /* PR gas/3041 References to weak symbols must be treated as extern
1331 in order to be overridable by the linker, even if they are defined
1332 in the same object file. So the original addend must be written
1333 "as is" into the output section without further processing.
1334 The addend value must be hacked here in order to force
1335 bfd_install_relocation() to write the original value into the
1336 output section.
1337 1) MD_APPLY_SYM_VALUE() is set to 1 for m68k/a.out, so the symbol
1338 value has already been added to the addend in fixup_segment(). We
1339 have to remove it.
1340 2) bfd_install_relocation() will incorrectly treat this symbol as
1341 resolved, so it will write the symbol value plus its addend and
1342 section VMA. As a workaround we can tweak the addend value here in
1343 order to get the original value in the section after the call to
1344 bfd_install_relocation(). */
1345 reloc->addend = fixp->fx_addnumber
1346 /* Fix because of MD_APPLY_SYM_VALUE() */
1347 - S_GET_VALUE (fixp->fx_addsy)
1348 /* Fix for bfd_install_relocation() */
1349 - (S_GET_VALUE (fixp->fx_addsy)
1350 + S_GET_SEGMENT (fixp->fx_addsy)->vma);
1351 }
1352 else
1353 reloc->addend = 0;
1354 #else
1355 if (!fixp->fx_pcrel)
1356 reloc->addend = fixp->fx_addnumber;
1357 else
1358 reloc->addend = (section->vma
1359 /* Explicit sign extension in case char is
1360 unsigned. */
1361 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1362 + fixp->fx_addnumber
1363 + md_pcrel_from (fixp));
1364 #endif
1365
1366 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1367 gas_assert (reloc->howto != 0);
1368
1369 return reloc;
1370 }
1371
1372 /* Handle of the OPCODE hash table. NULL means any use before
1373 m68k_ip_begin() will crash. */
1374 static struct hash_control *op_hash;
1375 \f
1376 /* Assemble an m68k instruction. */
1377
1378 static void
1379 m68k_ip (char *instring)
1380 {
1381 register char *p;
1382 register struct m68k_op *opP;
1383 register const struct m68k_incant *opcode;
1384 register const char *s;
1385 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1386 char *pdot, *pdotmove;
1387 enum m68k_size siz1, siz2;
1388 char c;
1389 int losing;
1390 int opsfound;
1391 struct m68k_op operands_backup[6];
1392 LITTLENUM_TYPE words[6];
1393 LITTLENUM_TYPE *wordp;
1394 unsigned long ok_arch = 0;
1395
1396 if (*instring == ' ')
1397 instring++; /* Skip leading whitespace. */
1398
1399 /* Scan up to end of operation-code, which MUST end in end-of-string
1400 or exactly 1 space. */
1401 pdot = 0;
1402 for (p = instring; *p != '\0'; p++)
1403 {
1404 if (*p == ' ')
1405 break;
1406 if (*p == '.')
1407 pdot = p;
1408 }
1409
1410 if (p == instring)
1411 {
1412 the_ins.error = _("No operator");
1413 return;
1414 }
1415
1416 /* p now points to the end of the opcode name, probably whitespace.
1417 Make sure the name is null terminated by clobbering the
1418 whitespace, look it up in the hash table, then fix it back.
1419 Remove a dot, first, since the opcode tables have none. */
1420 if (pdot != NULL)
1421 {
1422 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1423 *pdotmove = pdotmove[1];
1424 p--;
1425 }
1426
1427 c = *p;
1428 *p = '\0';
1429 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1430 *p = c;
1431
1432 if (pdot != NULL)
1433 {
1434 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1435 *pdotmove = pdotmove[-1];
1436 *pdot = '.';
1437 ++p;
1438 }
1439
1440 if (opcode == NULL)
1441 {
1442 the_ins.error = _("Unknown operator");
1443 return;
1444 }
1445
1446 /* Found a legitimate opcode, start matching operands. */
1447 while (*p == ' ')
1448 ++p;
1449
1450 if (opcode->m_operands == 0)
1451 {
1452 char *old = input_line_pointer;
1453 *old = '\n';
1454 input_line_pointer = p;
1455 /* Ahh - it's a motorola style psuedo op. */
1456 mote_pseudo_table[opcode->m_opnum].poc_handler
1457 (mote_pseudo_table[opcode->m_opnum].poc_val);
1458 input_line_pointer = old;
1459 *old = 0;
1460
1461 return;
1462 }
1463
1464 if (flag_mri && opcode->m_opnum == 0)
1465 {
1466 /* In MRI mode, random garbage is allowed after an instruction
1467 which accepts no operands. */
1468 the_ins.args = opcode->m_operands;
1469 the_ins.numargs = opcode->m_opnum;
1470 the_ins.numo = opcode->m_codenum;
1471 the_ins.opcode[0] = getone (opcode);
1472 the_ins.opcode[1] = gettwo (opcode);
1473 return;
1474 }
1475
1476 for (opP = &the_ins.operands[0]; *p; opP++)
1477 {
1478 p = crack_operand (p, opP);
1479
1480 if (opP->error)
1481 {
1482 the_ins.error = opP->error;
1483 return;
1484 }
1485 }
1486
1487 opsfound = opP - &the_ins.operands[0];
1488
1489 /* This ugly hack is to support the floating pt opcodes in their
1490 standard form. Essentially, we fake a first enty of type COP#1 */
1491 if (opcode->m_operands[0] == 'I')
1492 {
1493 int n;
1494
1495 for (n = opsfound; n > 0; --n)
1496 the_ins.operands[n] = the_ins.operands[n - 1];
1497
1498 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1499 the_ins.operands[0].mode = CONTROL;
1500 the_ins.operands[0].reg = m68k_float_copnum;
1501 opsfound++;
1502 }
1503
1504 /* We've got the operands. Find an opcode that'll accept them. */
1505 for (losing = 0;;)
1506 {
1507 /* If we didn't get the right number of ops, or we have no
1508 common model with this pattern then reject this pattern. */
1509
1510 ok_arch |= opcode->m_arch;
1511 if (opsfound != opcode->m_opnum
1512 || ((opcode->m_arch & current_architecture) == 0))
1513 ++losing;
1514 else
1515 {
1516 int i;
1517
1518 /* Make a copy of the operands of this insn so that
1519 we can modify them safely, should we want to. */
1520 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1521 for (i = 0; i < opsfound; i++)
1522 operands_backup[i] = the_ins.operands[i];
1523
1524 for (s = opcode->m_operands, opP = &operands_backup[0];
1525 *s && !losing;
1526 s += 2, opP++)
1527 {
1528 /* Warning: this switch is huge! */
1529 /* I've tried to organize the cases into this order:
1530 non-alpha first, then alpha by letter. Lower-case
1531 goes directly before uppercase counterpart. */
1532 /* Code with multiple case ...: gets sorted by the lowest
1533 case ... it belongs to. I hope this makes sense. */
1534 switch (*s)
1535 {
1536 case '!':
1537 switch (opP->mode)
1538 {
1539 case IMMED:
1540 case DREG:
1541 case AREG:
1542 case FPREG:
1543 case CONTROL:
1544 case AINC:
1545 case ADEC:
1546 case REGLST:
1547 losing++;
1548 break;
1549 default:
1550 break;
1551 }
1552 break;
1553
1554 case '<':
1555 switch (opP->mode)
1556 {
1557 case DREG:
1558 case AREG:
1559 case FPREG:
1560 case CONTROL:
1561 case IMMED:
1562 case ADEC:
1563 case REGLST:
1564 losing++;
1565 break;
1566 default:
1567 break;
1568 }
1569 break;
1570
1571 case '>':
1572 switch (opP->mode)
1573 {
1574 case DREG:
1575 case AREG:
1576 case FPREG:
1577 case CONTROL:
1578 case IMMED:
1579 case AINC:
1580 case REGLST:
1581 losing++;
1582 break;
1583 case ABSL:
1584 break;
1585 default:
1586 if (opP->reg == PC
1587 || opP->reg == ZPC)
1588 losing++;
1589 break;
1590 }
1591 break;
1592
1593 case 'm':
1594 switch (opP->mode)
1595 {
1596 case DREG:
1597 case AREG:
1598 case AINDR:
1599 case AINC:
1600 case ADEC:
1601 break;
1602 default:
1603 losing++;
1604 }
1605 break;
1606
1607 case 'n':
1608 switch (opP->mode)
1609 {
1610 case DISP:
1611 break;
1612 default:
1613 losing++;
1614 }
1615 break;
1616
1617 case 'o':
1618 switch (opP->mode)
1619 {
1620 case BASE:
1621 case ABSL:
1622 case IMMED:
1623 break;
1624 default:
1625 losing++;
1626 }
1627 break;
1628
1629 case 'p':
1630 switch (opP->mode)
1631 {
1632 case DREG:
1633 case AREG:
1634 case AINDR:
1635 case AINC:
1636 case ADEC:
1637 break;
1638 case DISP:
1639 if (opP->reg == PC || opP->reg == ZPC)
1640 losing++;
1641 break;
1642 default:
1643 losing++;
1644 }
1645 break;
1646
1647 case 'q':
1648 switch (opP->mode)
1649 {
1650 case DREG:
1651 case AINDR:
1652 case AINC:
1653 case ADEC:
1654 break;
1655 case DISP:
1656 if (opP->reg == PC || opP->reg == ZPC)
1657 losing++;
1658 break;
1659 default:
1660 losing++;
1661 break;
1662 }
1663 break;
1664
1665 case 'v':
1666 switch (opP->mode)
1667 {
1668 case DREG:
1669 case AINDR:
1670 case AINC:
1671 case ADEC:
1672 case ABSL:
1673 break;
1674 case DISP:
1675 if (opP->reg == PC || opP->reg == ZPC)
1676 losing++;
1677 break;
1678 default:
1679 losing++;
1680 break;
1681 }
1682 break;
1683
1684 case '#':
1685 if (opP->mode != IMMED)
1686 losing++;
1687 else if (s[1] == 'b'
1688 && ! isvar (&opP->disp)
1689 && (opP->disp.exp.X_op != O_constant
1690 || ! isbyte (opP->disp.exp.X_add_number)))
1691 losing++;
1692 else if (s[1] == 'B'
1693 && ! isvar (&opP->disp)
1694 && (opP->disp.exp.X_op != O_constant
1695 || ! issbyte (opP->disp.exp.X_add_number)))
1696 losing++;
1697 else if (s[1] == 'w'
1698 && ! isvar (&opP->disp)
1699 && (opP->disp.exp.X_op != O_constant
1700 || ! isword (opP->disp.exp.X_add_number)))
1701 losing++;
1702 else if (s[1] == 'W'
1703 && ! isvar (&opP->disp)
1704 && (opP->disp.exp.X_op != O_constant
1705 || ! issword (opP->disp.exp.X_add_number)))
1706 losing++;
1707 break;
1708
1709 case '^':
1710 case 'T':
1711 if (opP->mode != IMMED)
1712 losing++;
1713 break;
1714
1715 case '$':
1716 if (opP->mode == AREG
1717 || opP->mode == CONTROL
1718 || opP->mode == FPREG
1719 || opP->mode == IMMED
1720 || opP->mode == REGLST
1721 || (opP->mode != ABSL
1722 && (opP->reg == PC
1723 || opP->reg == ZPC)))
1724 losing++;
1725 break;
1726
1727 case '%':
1728 if (opP->mode == CONTROL
1729 || opP->mode == FPREG
1730 || opP->mode == REGLST
1731 || opP->mode == IMMED
1732 || (opP->mode != ABSL
1733 && (opP->reg == PC
1734 || opP->reg == ZPC)))
1735 losing++;
1736 break;
1737
1738 case '&':
1739 switch (opP->mode)
1740 {
1741 case DREG:
1742 case AREG:
1743 case FPREG:
1744 case CONTROL:
1745 case IMMED:
1746 case AINC:
1747 case ADEC:
1748 case REGLST:
1749 losing++;
1750 break;
1751 case ABSL:
1752 break;
1753 default:
1754 if (opP->reg == PC
1755 || opP->reg == ZPC)
1756 losing++;
1757 break;
1758 }
1759 break;
1760
1761 case '*':
1762 if (opP->mode == CONTROL
1763 || opP->mode == FPREG
1764 || opP->mode == REGLST)
1765 losing++;
1766 break;
1767
1768 case '+':
1769 if (opP->mode != AINC)
1770 losing++;
1771 break;
1772
1773 case '-':
1774 if (opP->mode != ADEC)
1775 losing++;
1776 break;
1777
1778 case '/':
1779 switch (opP->mode)
1780 {
1781 case AREG:
1782 case CONTROL:
1783 case FPREG:
1784 case AINC:
1785 case ADEC:
1786 case IMMED:
1787 case REGLST:
1788 losing++;
1789 break;
1790 default:
1791 break;
1792 }
1793 break;
1794
1795 case ';':
1796 switch (opP->mode)
1797 {
1798 case AREG:
1799 case CONTROL:
1800 case FPREG:
1801 case REGLST:
1802 losing++;
1803 break;
1804 default:
1805 break;
1806 }
1807 break;
1808
1809 case '?':
1810 switch (opP->mode)
1811 {
1812 case AREG:
1813 case CONTROL:
1814 case FPREG:
1815 case AINC:
1816 case ADEC:
1817 case IMMED:
1818 case REGLST:
1819 losing++;
1820 break;
1821 case ABSL:
1822 break;
1823 default:
1824 if (opP->reg == PC || opP->reg == ZPC)
1825 losing++;
1826 break;
1827 }
1828 break;
1829
1830 case '@':
1831 switch (opP->mode)
1832 {
1833 case AREG:
1834 case CONTROL:
1835 case FPREG:
1836 case IMMED:
1837 case REGLST:
1838 losing++;
1839 break;
1840 default:
1841 break;
1842 }
1843 break;
1844
1845 case '~': /* For now! (JF FOO is this right?) */
1846 switch (opP->mode)
1847 {
1848 case DREG:
1849 case AREG:
1850 case CONTROL:
1851 case FPREG:
1852 case IMMED:
1853 case REGLST:
1854 losing++;
1855 break;
1856 case ABSL:
1857 break;
1858 default:
1859 if (opP->reg == PC
1860 || opP->reg == ZPC)
1861 losing++;
1862 break;
1863 }
1864 break;
1865
1866 case '3':
1867 if (opP->mode != CONTROL
1868 || (opP->reg != TT0 && opP->reg != TT1))
1869 losing++;
1870 break;
1871
1872 case 'A':
1873 if (opP->mode != AREG)
1874 losing++;
1875 break;
1876
1877 case 'a':
1878 if (opP->mode != AINDR)
1879 ++losing;
1880 break;
1881
1882 case '4':
1883 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1884 && (opP->mode != DISP
1885 || opP->reg < ADDR0
1886 || opP->reg > ADDR7))
1887 ++losing;
1888 break;
1889
1890 case 'B': /* FOO */
1891 if (opP->mode != ABSL
1892 || (flag_long_jumps
1893 && strncmp (instring, "jbsr", 4) == 0))
1894 losing++;
1895 break;
1896
1897 case 'b':
1898 switch (opP->mode)
1899 {
1900 case IMMED:
1901 case ABSL:
1902 case AREG:
1903 case FPREG:
1904 case CONTROL:
1905 case POST:
1906 case PRE:
1907 case REGLST:
1908 losing++;
1909 break;
1910 default:
1911 break;
1912 }
1913 break;
1914
1915 case 'C':
1916 if (opP->mode != CONTROL || opP->reg != CCR)
1917 losing++;
1918 break;
1919
1920 case 'd':
1921 if (opP->mode != DISP
1922 || opP->reg < ADDR0
1923 || opP->reg > ADDR7)
1924 losing++;
1925 break;
1926
1927 case 'D':
1928 if (opP->mode != DREG)
1929 losing++;
1930 break;
1931
1932 case 'E':
1933 if (opP->reg != ACC)
1934 losing++;
1935 break;
1936
1937 case 'e':
1938 if (opP->reg != ACC && opP->reg != ACC1
1939 && opP->reg != ACC2 && opP->reg != ACC3)
1940 losing++;
1941 break;
1942
1943 case 'F':
1944 if (opP->mode != FPREG)
1945 losing++;
1946 break;
1947
1948 case 'G':
1949 if (opP->reg != MACSR)
1950 losing++;
1951 break;
1952
1953 case 'g':
1954 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1955 losing++;
1956 break;
1957
1958 case 'H':
1959 if (opP->reg != MASK)
1960 losing++;
1961 break;
1962
1963 case 'I':
1964 if (opP->mode != CONTROL
1965 || opP->reg < COP0
1966 || opP->reg > COP7)
1967 losing++;
1968 break;
1969
1970 case 'i':
1971 if (opP->mode != LSH && opP->mode != RSH)
1972 losing++;
1973 break;
1974
1975 case 'J':
1976 if (opP->mode != CONTROL
1977 || opP->reg < USP
1978 || opP->reg > last_movec_reg
1979 || !control_regs)
1980 losing++;
1981 else
1982 {
1983 const enum m68k_register *rp;
1984
1985 for (rp = control_regs; *rp; rp++)
1986 {
1987 if (*rp == opP->reg)
1988 break;
1989 /* In most CPUs RAMBAR refers to control reg
1990 c05 (RAMBAR1), but a few CPUs have it
1991 refer to c04 (RAMBAR0). */
1992 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1993 {
1994 opP->reg = RAMBAR_ALT;
1995 break;
1996 }
1997 }
1998 if (*rp == 0)
1999 losing++;
2000 }
2001 break;
2002
2003 case 'k':
2004 if (opP->mode != IMMED)
2005 losing++;
2006 break;
2007
2008 case 'l':
2009 case 'L':
2010 if (opP->mode == DREG
2011 || opP->mode == AREG
2012 || opP->mode == FPREG)
2013 {
2014 if (s[1] == '8')
2015 losing++;
2016 else
2017 {
2018 switch (opP->mode)
2019 {
2020 case DREG:
2021 opP->mask = 1 << (opP->reg - DATA0);
2022 break;
2023 case AREG:
2024 opP->mask = 1 << (opP->reg - ADDR0 + 8);
2025 break;
2026 case FPREG:
2027 opP->mask = 1 << (opP->reg - FP0 + 16);
2028 break;
2029 default:
2030 abort ();
2031 }
2032 opP->mode = REGLST;
2033 }
2034 }
2035 else if (opP->mode == CONTROL)
2036 {
2037 if (s[1] != '8')
2038 losing++;
2039 else
2040 {
2041 switch (opP->reg)
2042 {
2043 case FPI:
2044 opP->mask = 1 << 24;
2045 break;
2046 case FPS:
2047 opP->mask = 1 << 25;
2048 break;
2049 case FPC:
2050 opP->mask = 1 << 26;
2051 break;
2052 default:
2053 losing++;
2054 break;
2055 }
2056 opP->mode = REGLST;
2057 }
2058 }
2059 else if (opP->mode != REGLST)
2060 losing++;
2061 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
2062 losing++;
2063 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
2064 losing++;
2065 break;
2066
2067 case 'M':
2068 if (opP->mode != IMMED)
2069 losing++;
2070 else if (opP->disp.exp.X_op != O_constant
2071 || ! issbyte (opP->disp.exp.X_add_number))
2072 losing++;
2073 else if (! m68k_quick
2074 && instring[3] != 'q'
2075 && instring[4] != 'q')
2076 losing++;
2077 break;
2078
2079 case 'O':
2080 if (opP->mode != DREG
2081 && opP->mode != IMMED
2082 && opP->mode != ABSL)
2083 losing++;
2084 break;
2085
2086 case 'Q':
2087 if (opP->mode != IMMED)
2088 losing++;
2089 else if (opP->disp.exp.X_op != O_constant
2090 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2091 losing++;
2092 else if (! m68k_quick
2093 && (strncmp (instring, "add", 3) == 0
2094 || strncmp (instring, "sub", 3) == 0)
2095 && instring[3] != 'q')
2096 losing++;
2097 break;
2098
2099 case 'R':
2100 if (opP->mode != DREG && opP->mode != AREG)
2101 losing++;
2102 break;
2103
2104 case 'r':
2105 if (opP->mode != AINDR
2106 && (opP->mode != BASE
2107 || (opP->reg != 0
2108 && opP->reg != ZADDR0)
2109 || opP->disp.exp.X_op != O_absent
2110 || ((opP->index.reg < DATA0
2111 || opP->index.reg > DATA7)
2112 && (opP->index.reg < ADDR0
2113 || opP->index.reg > ADDR7))
2114 || opP->index.size != SIZE_UNSPEC
2115 || opP->index.scale != 1))
2116 losing++;
2117 break;
2118
2119 case 's':
2120 if (opP->mode != CONTROL
2121 || ! (opP->reg == FPI
2122 || opP->reg == FPS
2123 || opP->reg == FPC))
2124 losing++;
2125 break;
2126
2127 case 'S':
2128 if (opP->mode != CONTROL || opP->reg != SR)
2129 losing++;
2130 break;
2131
2132 case 't':
2133 if (opP->mode != IMMED)
2134 losing++;
2135 else if (opP->disp.exp.X_op != O_constant
2136 || TRUNC (opP->disp.exp.X_add_number) > 7)
2137 losing++;
2138 break;
2139
2140 case 'U':
2141 if (opP->mode != CONTROL || opP->reg != USP)
2142 losing++;
2143 break;
2144
2145 case 'x':
2146 if (opP->mode != IMMED)
2147 losing++;
2148 else if (opP->disp.exp.X_op != O_constant
2149 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
2150 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
2151 losing++;
2152 break;
2153
2154 case 'j':
2155 if (opP->mode != IMMED)
2156 losing++;
2157 else if (opP->disp.exp.X_op != O_constant
2158 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2159 losing++;
2160 break;
2161
2162 case 'K':
2163 if (opP->mode != IMMED)
2164 losing++;
2165 else if (opP->disp.exp.X_op != O_constant
2166 || TRUNC (opP->disp.exp.X_add_number) > 511)
2167 losing++;
2168 break;
2169
2170 /* JF these are out of order. We could put them
2171 in order if we were willing to put up with
2172 bunches of #ifdef m68851s in the code.
2173
2174 Don't forget that you need these operands
2175 to use 68030 MMU instructions. */
2176 #ifndef NO_68851
2177 /* Memory addressing mode used by pflushr. */
2178 case '|':
2179 if (opP->mode == CONTROL
2180 || opP->mode == FPREG
2181 || opP->mode == DREG
2182 || opP->mode == AREG
2183 || opP->mode == REGLST)
2184 losing++;
2185 /* We should accept immediate operands, but they
2186 supposedly have to be quad word, and we don't
2187 handle that. I would like to see what a Motorola
2188 assembler does before doing something here. */
2189 if (opP->mode == IMMED)
2190 losing++;
2191 break;
2192
2193 case 'f':
2194 if (opP->mode != CONTROL
2195 || (opP->reg != SFC && opP->reg != DFC))
2196 losing++;
2197 break;
2198
2199 case '0':
2200 if (opP->mode != CONTROL || opP->reg != TC)
2201 losing++;
2202 break;
2203
2204 case '1':
2205 if (opP->mode != CONTROL || opP->reg != AC)
2206 losing++;
2207 break;
2208
2209 case '2':
2210 if (opP->mode != CONTROL
2211 || (opP->reg != CAL
2212 && opP->reg != VAL
2213 && opP->reg != SCC))
2214 losing++;
2215 break;
2216
2217 case 'V':
2218 if (opP->mode != CONTROL
2219 || opP->reg != VAL)
2220 losing++;
2221 break;
2222
2223 case 'W':
2224 if (opP->mode != CONTROL
2225 || (opP->reg != DRP
2226 && opP->reg != SRP
2227 && opP->reg != CRP))
2228 losing++;
2229 break;
2230
2231 case 'w':
2232 switch (opP->mode)
2233 {
2234 case IMMED:
2235 case ABSL:
2236 case AREG:
2237 case DREG:
2238 case FPREG:
2239 case CONTROL:
2240 case POST:
2241 case PRE:
2242 case REGLST:
2243 losing++;
2244 break;
2245 default:
2246 break;
2247 }
2248 break;
2249
2250 case 'X':
2251 if (opP->mode != CONTROL
2252 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2253 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2254 losing++;
2255 break;
2256
2257 case 'Y':
2258 if (opP->mode != CONTROL || opP->reg != PSR)
2259 losing++;
2260 break;
2261
2262 case 'Z':
2263 if (opP->mode != CONTROL || opP->reg != PCSR)
2264 losing++;
2265 break;
2266 #endif
2267 case 'c':
2268 if (opP->mode != CONTROL
2269 || (opP->reg != NC
2270 && opP->reg != IC
2271 && opP->reg != DC
2272 && opP->reg != BC))
2273 losing++;
2274 break;
2275
2276 case '_':
2277 if (opP->mode != ABSL)
2278 ++losing;
2279 break;
2280
2281 case 'u':
2282 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2283 losing++;
2284 /* FIXME: kludge instead of fixing parser:
2285 upper/lower registers are *not* CONTROL
2286 registers, but ordinary ones. */
2287 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2288 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2289 opP->mode = DREG;
2290 else
2291 opP->mode = AREG;
2292 break;
2293
2294 case 'y':
2295 if (!(opP->mode == AINDR
2296 || (opP->mode == DISP
2297 && !(opP->reg == PC || opP->reg == ZPC))))
2298 losing++;
2299 break;
2300
2301 case 'z':
2302 if (!(opP->mode == AINDR || opP->mode == DISP))
2303 losing++;
2304 break;
2305
2306 default:
2307 abort ();
2308 }
2309
2310 if (losing)
2311 break;
2312 }
2313
2314 /* Since we have found the correct instruction, copy
2315 in the modifications that we may have made. */
2316 if (!losing)
2317 for (i = 0; i < opsfound; i++)
2318 the_ins.operands[i] = operands_backup[i];
2319 }
2320
2321 if (!losing)
2322 break;
2323
2324 opcode = opcode->m_next;
2325
2326 if (!opcode)
2327 {
2328 if (ok_arch
2329 && !(ok_arch & current_architecture))
2330 {
2331 const struct m68k_cpu *cpu;
2332 int any = 0;
2333 size_t space = 400;
2334 char *buf = xmalloc (space + 1);
2335 size_t len;
2336 int paren = 1;
2337
2338 the_ins.error = buf;
2339 /* Make sure there's a NUL at the end of the buffer -- strncpy
2340 won't write one when it runs out of buffer. */
2341 buf[space] = 0;
2342 #define APPEND(STRING) \
2343 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2344
2345 APPEND (_("invalid instruction for this architecture; needs "));
2346 switch (ok_arch)
2347 {
2348 case mcfisa_a:
2349 APPEND ("ColdFire ISA_A");
2350 break;
2351 case mcfhwdiv:
2352 APPEND ("ColdFire ");
2353 APPEND (_("hardware divide"));
2354 break;
2355 case mcfisa_aa:
2356 APPEND ("ColdFire ISA_A+");
2357 break;
2358 case mcfisa_b:
2359 APPEND ("ColdFire ISA_B");
2360 break;
2361 case mcfisa_c:
2362 APPEND ("ColdFire ISA_C");
2363 break;
2364 case cfloat:
2365 APPEND ("ColdFire fpu");
2366 break;
2367 case mfloat:
2368 APPEND ("M68K fpu");
2369 break;
2370 case mmmu:
2371 APPEND ("M68K mmu");
2372 break;
2373 case m68020up:
2374 APPEND ("68020 ");
2375 APPEND (_("or higher"));
2376 break;
2377 case m68000up:
2378 APPEND ("68000 ");
2379 APPEND (_("or higher"));
2380 break;
2381 case m68010up:
2382 APPEND ("68010 ");
2383 APPEND (_("or higher"));
2384 break;
2385 default:
2386 paren = 0;
2387 }
2388 if (paren)
2389 APPEND (" (");
2390
2391 for (cpu = m68k_cpus; cpu->name; cpu++)
2392 if (!cpu->alias && (cpu->arch & ok_arch))
2393 {
2394 const struct m68k_cpu *alias;
2395 int seen_master = 0;
2396
2397 if (any)
2398 APPEND (", ");
2399 any = 0;
2400 APPEND (cpu->name);
2401 for (alias = cpu; alias != m68k_cpus; alias--)
2402 if (alias[-1].alias >= 0)
2403 break;
2404 for (; !seen_master || alias->alias > 0; alias++)
2405 {
2406 if (!alias->alias)
2407 seen_master = 1;
2408 else
2409 {
2410 if (any)
2411 APPEND (", ");
2412 else
2413 APPEND (" [");
2414 APPEND (alias->name);
2415 any = 1;
2416 }
2417 }
2418 if (any)
2419 APPEND ("]");
2420 any = 1;
2421 }
2422 if (paren)
2423 APPEND (")");
2424 #undef APPEND
2425 if (!space)
2426 {
2427 /* We ran out of space, so replace the end of the list
2428 with ellipsis. */
2429 buf -= 4;
2430 while (*buf != ' ')
2431 buf--;
2432 strcpy (buf, " ...");
2433 }
2434 }
2435 else
2436 the_ins.error = _("operands mismatch");
2437 return;
2438 }
2439
2440 losing = 0;
2441 }
2442
2443 /* Now assemble it. */
2444 the_ins.args = opcode->m_operands;
2445 the_ins.numargs = opcode->m_opnum;
2446 the_ins.numo = opcode->m_codenum;
2447 the_ins.opcode[0] = getone (opcode);
2448 the_ins.opcode[1] = gettwo (opcode);
2449
2450 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2451 {
2452 int have_disp = 0;
2453 int use_pl = 0;
2454
2455 /* This switch is a doozy.
2456 Watch the first step; its a big one! */
2457 switch (s[0])
2458 {
2459
2460 case '*':
2461 case '~':
2462 case '%':
2463 case ';':
2464 case '@':
2465 case '!':
2466 case '&':
2467 case '$':
2468 case '?':
2469 case '/':
2470 case '<':
2471 case '>':
2472 case 'b':
2473 case 'm':
2474 case 'n':
2475 case 'o':
2476 case 'p':
2477 case 'q':
2478 case 'v':
2479 case 'w':
2480 case 'y':
2481 case 'z':
2482 case '4':
2483 #ifndef NO_68851
2484 case '|':
2485 #endif
2486 switch (opP->mode)
2487 {
2488 case IMMED:
2489 tmpreg = 0x3c; /* 7.4 */
2490 if (strchr ("bwl", s[1]))
2491 nextword = get_num (&opP->disp, 90);
2492 else
2493 nextword = get_num (&opP->disp, 0);
2494 if (isvar (&opP->disp))
2495 add_fix (s[1], &opP->disp, 0, 0);
2496 switch (s[1])
2497 {
2498 case 'b':
2499 if (!isbyte (nextword))
2500 opP->error = _("operand out of range");
2501 addword (nextword);
2502 baseo = 0;
2503 break;
2504 case 'w':
2505 if (!isword (nextword))
2506 opP->error = _("operand out of range");
2507 addword (nextword);
2508 baseo = 0;
2509 break;
2510 case 'W':
2511 if (!issword (nextword))
2512 opP->error = _("operand out of range");
2513 addword (nextword);
2514 baseo = 0;
2515 break;
2516 case 'l':
2517 addword (nextword >> 16);
2518 addword (nextword);
2519 baseo = 0;
2520 break;
2521
2522 case 'f':
2523 baseo = 2;
2524 outro = 8;
2525 break;
2526 case 'F':
2527 baseo = 4;
2528 outro = 11;
2529 break;
2530 case 'x':
2531 baseo = 6;
2532 outro = 15;
2533 break;
2534 case 'p':
2535 baseo = 6;
2536 outro = -1;
2537 break;
2538 default:
2539 abort ();
2540 }
2541 if (!baseo)
2542 break;
2543
2544 /* We gotta put out some float. */
2545 if (op (&opP->disp) != O_big)
2546 {
2547 valueT val;
2548 int gencnt;
2549
2550 /* Can other cases happen here? */
2551 if (op (&opP->disp) != O_constant)
2552 abort ();
2553
2554 val = (valueT) offs (&opP->disp);
2555 gencnt = 0;
2556 do
2557 {
2558 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2559 val >>= LITTLENUM_NUMBER_OF_BITS;
2560 ++gencnt;
2561 }
2562 while (val != 0);
2563 offs (&opP->disp) = gencnt;
2564 }
2565 if (offs (&opP->disp) > 0)
2566 {
2567 if (offs (&opP->disp) > baseo)
2568 {
2569 as_warn (_("Bignum too big for %c format; truncated"),
2570 s[1]);
2571 offs (&opP->disp) = baseo;
2572 }
2573 baseo -= offs (&opP->disp);
2574 while (baseo--)
2575 addword (0);
2576 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2577 offs (&opP->disp)--;
2578 --wordp)
2579 addword (*wordp);
2580 break;
2581 }
2582 gen_to_words (words, baseo, (long) outro);
2583 for (wordp = words; baseo--; wordp++)
2584 addword (*wordp);
2585 break;
2586 case DREG:
2587 tmpreg = opP->reg - DATA; /* 0.dreg */
2588 break;
2589 case AREG:
2590 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2591 break;
2592 case AINDR:
2593 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2594 break;
2595 case ADEC:
2596 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2597 break;
2598 case AINC:
2599 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2600 break;
2601 case DISP:
2602
2603 nextword = get_num (&opP->disp, 90);
2604
2605 /* Convert mode 5 addressing with a zero offset into
2606 mode 2 addressing to reduce the instruction size by a
2607 word. */
2608 if (! isvar (&opP->disp)
2609 && (nextword == 0)
2610 && (opP->disp.size == SIZE_UNSPEC)
2611 && (opP->reg >= ADDR0)
2612 && (opP->reg <= ADDR7))
2613 {
2614 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2615 break;
2616 }
2617
2618 if (opP->reg == PC
2619 && ! isvar (&opP->disp)
2620 && m68k_abspcadd)
2621 {
2622 opP->disp.exp.X_op = O_symbol;
2623 opP->disp.exp.X_add_symbol =
2624 section_symbol (absolute_section);
2625 }
2626
2627 /* Force into index mode. Hope this works. */
2628
2629 /* We do the first bit for 32-bit displacements, and the
2630 second bit for 16 bit ones. It is possible that we
2631 should make the default be WORD instead of LONG, but
2632 I think that'd break GCC, so we put up with a little
2633 inefficiency for the sake of working output. */
2634
2635 if (!issword (nextword)
2636 || (isvar (&opP->disp)
2637 && ((opP->disp.size == SIZE_UNSPEC
2638 && flag_short_refs == 0
2639 && cpu_of_arch (current_architecture) >= m68020
2640 && ! arch_coldfire_p (current_architecture))
2641 || opP->disp.size == SIZE_LONG)))
2642 {
2643 if (cpu_of_arch (current_architecture) < m68020
2644 || arch_coldfire_p (current_architecture))
2645 opP->error =
2646 _("displacement too large for this architecture; needs 68020 or higher");
2647 if (opP->reg == PC)
2648 tmpreg = 0x3B; /* 7.3 */
2649 else
2650 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2651 if (isvar (&opP->disp))
2652 {
2653 if (opP->reg == PC)
2654 {
2655 if (opP->disp.size == SIZE_LONG
2656 #ifdef OBJ_ELF
2657 /* If the displacement needs pic
2658 relocation it cannot be relaxed. */
2659 || opP->disp.pic_reloc != pic_none
2660 #endif
2661 )
2662 {
2663 addword (0x0170);
2664 add_fix ('l', &opP->disp, 1, 2);
2665 }
2666 else
2667 {
2668 add_frag (adds (&opP->disp),
2669 SEXT (offs (&opP->disp)),
2670 TAB (PCREL1632, SZ_UNDEF));
2671 break;
2672 }
2673 }
2674 else
2675 {
2676 addword (0x0170);
2677 add_fix ('l', &opP->disp, 0, 0);
2678 }
2679 }
2680 else
2681 addword (0x0170);
2682 addword (nextword >> 16);
2683 }
2684 else
2685 {
2686 if (opP->reg == PC)
2687 tmpreg = 0x3A; /* 7.2 */
2688 else
2689 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2690
2691 if (isvar (&opP->disp))
2692 {
2693 if (opP->reg == PC)
2694 {
2695 add_fix ('w', &opP->disp, 1, 0);
2696 }
2697 else
2698 add_fix ('w', &opP->disp, 0, 0);
2699 }
2700 }
2701 addword (nextword);
2702 break;
2703
2704 case POST:
2705 case PRE:
2706 case BASE:
2707 nextword = 0;
2708 baseo = get_num (&opP->disp, 90);
2709 if (opP->mode == POST || opP->mode == PRE)
2710 outro = get_num (&opP->odisp, 90);
2711 /* Figure out the `addressing mode'.
2712 Also turn on the BASE_DISABLE bit, if needed. */
2713 if (opP->reg == PC || opP->reg == ZPC)
2714 {
2715 tmpreg = 0x3b; /* 7.3 */
2716 if (opP->reg == ZPC)
2717 nextword |= 0x80;
2718 }
2719 else if (opP->reg == 0)
2720 {
2721 nextword |= 0x80;
2722 tmpreg = 0x30; /* 6.garbage */
2723 }
2724 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2725 {
2726 nextword |= 0x80;
2727 tmpreg = 0x30 + opP->reg - ZADDR0;
2728 }
2729 else
2730 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2731
2732 siz1 = opP->disp.size;
2733 if (opP->mode == POST || opP->mode == PRE)
2734 siz2 = opP->odisp.size;
2735 else
2736 siz2 = SIZE_UNSPEC;
2737
2738 /* Index register stuff. */
2739 if (opP->index.reg != 0
2740 && opP->index.reg >= DATA
2741 && opP->index.reg <= ADDR7)
2742 {
2743 nextword |= (opP->index.reg - DATA) << 12;
2744
2745 if (opP->index.size == SIZE_LONG
2746 || (opP->index.size == SIZE_UNSPEC
2747 && m68k_index_width_default == SIZE_LONG))
2748 nextword |= 0x800;
2749
2750 if ((opP->index.scale != 1
2751 && cpu_of_arch (current_architecture) < m68020)
2752 || (opP->index.scale == 8
2753 && (arch_coldfire_p (current_architecture)
2754 && !arch_coldfire_fpu (current_architecture))))
2755 {
2756 opP->error =
2757 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2758 }
2759
2760 if (arch_coldfire_p (current_architecture)
2761 && opP->index.size == SIZE_WORD)
2762 opP->error = _("invalid index size for coldfire");
2763
2764 switch (opP->index.scale)
2765 {
2766 case 1:
2767 break;
2768 case 2:
2769 nextword |= 0x200;
2770 break;
2771 case 4:
2772 nextword |= 0x400;
2773 break;
2774 case 8:
2775 nextword |= 0x600;
2776 break;
2777 default:
2778 abort ();
2779 }
2780 /* IF its simple,
2781 GET US OUT OF HERE! */
2782
2783 /* Must be INDEX, with an index register. Address
2784 register cannot be ZERO-PC, and either :b was
2785 forced, or we know it will fit. For a 68000 or
2786 68010, force this mode anyways, because the
2787 larger modes aren't supported. */
2788 if (opP->mode == BASE
2789 && ((opP->reg >= ADDR0
2790 && opP->reg <= ADDR7)
2791 || opP->reg == PC))
2792 {
2793 if (siz1 == SIZE_BYTE
2794 || cpu_of_arch (current_architecture) < m68020
2795 || arch_coldfire_p (current_architecture)
2796 || (siz1 == SIZE_UNSPEC
2797 && ! isvar (&opP->disp)
2798 && issbyte (baseo)))
2799 {
2800 nextword += baseo & 0xff;
2801 addword (nextword);
2802 if (isvar (&opP->disp))
2803 {
2804 /* Do a byte relocation. If it doesn't
2805 fit (possible on m68000) let the
2806 fixup processing complain later. */
2807 if (opP->reg == PC)
2808 add_fix ('B', &opP->disp, 1, 1);
2809 else
2810 add_fix ('B', &opP->disp, 0, 0);
2811 }
2812 else if (siz1 != SIZE_BYTE)
2813 {
2814 if (siz1 != SIZE_UNSPEC)
2815 as_warn (_("Forcing byte displacement"));
2816 if (! issbyte (baseo))
2817 opP->error = _("byte displacement out of range");
2818 }
2819
2820 break;
2821 }
2822 else if (siz1 == SIZE_UNSPEC
2823 && opP->reg == PC
2824 && isvar (&opP->disp)
2825 && subs (&opP->disp) == NULL
2826 #ifdef OBJ_ELF
2827 /* If the displacement needs pic
2828 relocation it cannot be relaxed. */
2829 && opP->disp.pic_reloc == pic_none
2830 #endif
2831 )
2832 {
2833 /* The code in md_convert_frag_1 needs to be
2834 able to adjust nextword. Call frag_grow
2835 to ensure that we have enough space in
2836 the frag obstack to make all the bytes
2837 contiguous. */
2838 frag_grow (14);
2839 nextword += baseo & 0xff;
2840 addword (nextword);
2841 add_frag (adds (&opP->disp),
2842 SEXT (offs (&opP->disp)),
2843 TAB (PCINDEX, SZ_UNDEF));
2844
2845 break;
2846 }
2847 }
2848 }
2849 else
2850 {
2851 nextword |= 0x40; /* No index reg. */
2852 if (opP->index.reg >= ZDATA0
2853 && opP->index.reg <= ZDATA7)
2854 nextword |= (opP->index.reg - ZDATA0) << 12;
2855 else if (opP->index.reg >= ZADDR0
2856 || opP->index.reg <= ZADDR7)
2857 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2858 }
2859
2860 /* It isn't simple. */
2861
2862 if (cpu_of_arch (current_architecture) < m68020
2863 || arch_coldfire_p (current_architecture))
2864 opP->error =
2865 _("invalid operand mode for this architecture; needs 68020 or higher");
2866
2867 nextword |= 0x100;
2868 /* If the guy specified a width, we assume that it is
2869 wide enough. Maybe it isn't. If so, we lose. */
2870 switch (siz1)
2871 {
2872 case SIZE_UNSPEC:
2873 if (isvar (&opP->disp)
2874 ? m68k_rel32
2875 : ! issword (baseo))
2876 {
2877 siz1 = SIZE_LONG;
2878 nextword |= 0x30;
2879 }
2880 else if (! isvar (&opP->disp) && baseo == 0)
2881 nextword |= 0x10;
2882 else
2883 {
2884 nextword |= 0x20;
2885 siz1 = SIZE_WORD;
2886 }
2887 break;
2888 case SIZE_BYTE:
2889 as_warn (_(":b not permitted; defaulting to :w"));
2890 /* Fall through. */
2891 case SIZE_WORD:
2892 nextword |= 0x20;
2893 break;
2894 case SIZE_LONG:
2895 nextword |= 0x30;
2896 break;
2897 }
2898
2899 /* Figure out inner displacement stuff. */
2900 if (opP->mode == POST || opP->mode == PRE)
2901 {
2902 if (cpu_of_arch (current_architecture) & cpu32)
2903 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2904 switch (siz2)
2905 {
2906 case SIZE_UNSPEC:
2907 if (isvar (&opP->odisp)
2908 ? m68k_rel32
2909 : ! issword (outro))
2910 {
2911 siz2 = SIZE_LONG;
2912 nextword |= 0x3;
2913 }
2914 else if (! isvar (&opP->odisp) && outro == 0)
2915 nextword |= 0x1;
2916 else
2917 {
2918 nextword |= 0x2;
2919 siz2 = SIZE_WORD;
2920 }
2921 break;
2922 case 1:
2923 as_warn (_(":b not permitted; defaulting to :w"));
2924 /* Fall through. */
2925 case 2:
2926 nextword |= 0x2;
2927 break;
2928 case 3:
2929 nextword |= 0x3;
2930 break;
2931 }
2932 if (opP->mode == POST
2933 && (nextword & 0x40) == 0)
2934 nextword |= 0x04;
2935 }
2936 addword (nextword);
2937
2938 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2939 {
2940 if (opP->reg == PC || opP->reg == ZPC)
2941 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2942 else
2943 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2944 }
2945 if (siz1 == SIZE_LONG)
2946 addword (baseo >> 16);
2947 if (siz1 != SIZE_UNSPEC)
2948 addword (baseo);
2949
2950 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2951 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2952 if (siz2 == SIZE_LONG)
2953 addword (outro >> 16);
2954 if (siz2 != SIZE_UNSPEC)
2955 addword (outro);
2956
2957 break;
2958
2959 case ABSL:
2960 nextword = get_num (&opP->disp, 90);
2961 switch (opP->disp.size)
2962 {
2963 default:
2964 abort ();
2965 case SIZE_UNSPEC:
2966 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2967 {
2968 tmpreg = 0x38; /* 7.0 */
2969 addword (nextword);
2970 break;
2971 }
2972 if (isvar (&opP->disp)
2973 && !subs (&opP->disp)
2974 && adds (&opP->disp)
2975 #ifdef OBJ_ELF
2976 /* If the displacement needs pic relocation it
2977 cannot be relaxed. */
2978 && opP->disp.pic_reloc == pic_none
2979 #endif
2980 && !flag_long_jumps
2981 && !strchr ("~%&$?", s[0]))
2982 {
2983 tmpreg = 0x3A; /* 7.2 */
2984 add_frag (adds (&opP->disp),
2985 SEXT (offs (&opP->disp)),
2986 TAB (ABSTOPCREL, SZ_UNDEF));
2987 break;
2988 }
2989 /* Fall through into long. */
2990 case SIZE_LONG:
2991 if (isvar (&opP->disp))
2992 add_fix ('l', &opP->disp, 0, 0);
2993
2994 tmpreg = 0x39;/* 7.1 mode */
2995 addword (nextword >> 16);
2996 addword (nextword);
2997 break;
2998
2999 case SIZE_BYTE:
3000 as_bad (_("unsupported byte value; use a different suffix"));
3001 /* Fall through. */
3002
3003 case SIZE_WORD:
3004 if (isvar (&opP->disp))
3005 add_fix ('w', &opP->disp, 0, 0);
3006
3007 tmpreg = 0x38;/* 7.0 mode */
3008 addword (nextword);
3009 break;
3010 }
3011 break;
3012 case CONTROL:
3013 case FPREG:
3014 default:
3015 as_bad (_("unknown/incorrect operand"));
3016 /* abort (); */
3017 }
3018
3019 /* If s[0] is '4', then this is for the mac instructions
3020 that can have a trailing_ampersand set. If so, set 0x100
3021 bit on tmpreg so install_gen_operand can check for it and
3022 set the appropriate bit (word2, bit 5). */
3023 if (s[0] == '4')
3024 {
3025 if (opP->trailing_ampersand)
3026 tmpreg |= 0x100;
3027 }
3028 install_gen_operand (s[1], tmpreg);
3029 break;
3030
3031 case '#':
3032 case '^':
3033 switch (s[1])
3034 { /* JF: I hate floating point! */
3035 case 'j':
3036 tmpreg = 70;
3037 break;
3038 case '8':
3039 tmpreg = 20;
3040 break;
3041 case 'C':
3042 tmpreg = 50;
3043 break;
3044 case '3':
3045 default:
3046 tmpreg = 90;
3047 break;
3048 }
3049 tmpreg = get_num (&opP->disp, tmpreg);
3050 if (isvar (&opP->disp))
3051 add_fix (s[1], &opP->disp, 0, 0);
3052 switch (s[1])
3053 {
3054 case 'b': /* Danger: These do no check for
3055 certain types of overflow.
3056 user beware! */
3057 if (!isbyte (tmpreg))
3058 opP->error = _("out of range");
3059 insop (tmpreg, opcode);
3060 if (isvar (&opP->disp))
3061 the_ins.reloc[the_ins.nrel - 1].n =
3062 (opcode->m_codenum) * 2 + 1;
3063 break;
3064 case 'B':
3065 if (!issbyte (tmpreg))
3066 opP->error = _("out of range");
3067 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
3068 if (isvar (&opP->disp))
3069 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
3070 break;
3071 case 'w':
3072 if (!isword (tmpreg))
3073 opP->error = _("out of range");
3074 insop (tmpreg, opcode);
3075 if (isvar (&opP->disp))
3076 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3077 break;
3078 case 'W':
3079 if (!issword (tmpreg))
3080 opP->error = _("out of range");
3081 insop (tmpreg, opcode);
3082 if (isvar (&opP->disp))
3083 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3084 break;
3085 case 'l':
3086 /* Because of the way insop works, we put these two out
3087 backwards. */
3088 insop (tmpreg, opcode);
3089 insop (tmpreg >> 16, opcode);
3090 if (isvar (&opP->disp))
3091 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3092 break;
3093 case '3':
3094 tmpreg &= 0xFF;
3095 case '8':
3096 case 'C':
3097 case 'j':
3098 install_operand (s[1], tmpreg);
3099 break;
3100 default:
3101 abort ();
3102 }
3103 break;
3104
3105 case '+':
3106 case '-':
3107 case 'A':
3108 case 'a':
3109 install_operand (s[1], opP->reg - ADDR);
3110 break;
3111
3112 case 'B':
3113 tmpreg = get_num (&opP->disp, 90);
3114
3115 switch (s[1])
3116 {
3117 case 'B':
3118 add_fix ('B', &opP->disp, 1, -1);
3119 break;
3120 case 'W':
3121 add_fix ('w', &opP->disp, 1, 0);
3122 addword (0);
3123 break;
3124 case 'L':
3125 long_branch:
3126 the_ins.opcode[0] |= 0xff;
3127 add_fix ('l', &opP->disp, 1, 0);
3128 addword (0);
3129 addword (0);
3130 break;
3131 case 'g': /* Conditional branch */
3132 have_disp = HAVE_LONG_CALL (current_architecture);
3133 goto var_branch;
3134
3135 case 'b': /* Unconditional branch */
3136 have_disp = HAVE_LONG_BRANCH (current_architecture);
3137 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
3138 goto var_branch;
3139
3140 case 's': /* Unconditional subroutine */
3141 have_disp = HAVE_LONG_CALL (current_architecture);
3142
3143 var_branch:
3144 if (subs (&opP->disp) /* We can't relax it. */
3145 #ifdef OBJ_ELF
3146 /* If the displacement needs pic relocation it cannot be
3147 relaxed. */
3148 || opP->disp.pic_reloc != pic_none
3149 #endif
3150 || 0)
3151 {
3152 if (!have_disp)
3153 as_warn (_("Can't use long branches on this architecture"));
3154 goto long_branch;
3155 }
3156
3157 /* This could either be a symbol, or an absolute
3158 address. If it's an absolute address, turn it into
3159 an absolute jump right here and keep it out of the
3160 relaxer. */
3161 if (adds (&opP->disp) == 0)
3162 {
3163 if (the_ins.opcode[0] == 0x6000) /* jbra */
3164 the_ins.opcode[0] = 0x4EF9;
3165 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
3166 the_ins.opcode[0] = 0x4EB9;
3167 else /* jCC */
3168 {
3169 the_ins.opcode[0] ^= 0x0100;
3170 the_ins.opcode[0] |= 0x0006;
3171 addword (0x4EF9);
3172 }
3173 add_fix ('l', &opP->disp, 0, 0);
3174 addword (0);
3175 addword (0);
3176 break;
3177 }
3178
3179 /* Now we know it's going into the relaxer. Now figure
3180 out which mode. We try in this order of preference:
3181 long branch, absolute jump, byte/word branches only. */
3182 if (have_disp)
3183 add_frag (adds (&opP->disp),
3184 SEXT (offs (&opP->disp)),
3185 TAB (BRANCHBWL, SZ_UNDEF));
3186 else if (! flag_keep_pcrel)
3187 {
3188 if ((the_ins.opcode[0] == 0x6000)
3189 || (the_ins.opcode[0] == 0x6100))
3190 add_frag (adds (&opP->disp),
3191 SEXT (offs (&opP->disp)),
3192 TAB (BRABSJUNC, SZ_UNDEF));
3193 else
3194 add_frag (adds (&opP->disp),
3195 SEXT (offs (&opP->disp)),
3196 TAB (BRABSJCOND, SZ_UNDEF));
3197 }
3198 else
3199 add_frag (adds (&opP->disp),
3200 SEXT (offs (&opP->disp)),
3201 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3202 : TAB (BRANCHBW, SZ_UNDEF)));
3203 break;
3204 case 'w':
3205 if (isvar (&opP->disp))
3206 {
3207 /* Check for DBcc instructions. We can relax them,
3208 but only if we have long branches and/or absolute
3209 jumps. */
3210 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3211 && (HAVE_LONG_BRANCH (current_architecture)
3212 || ! flag_keep_pcrel))
3213 {
3214 if (HAVE_LONG_BRANCH (current_architecture))
3215 add_frag (adds (&opP->disp),
3216 SEXT (offs (&opP->disp)),
3217 TAB (DBCCLBR, SZ_UNDEF));
3218 else
3219 add_frag (adds (&opP->disp),
3220 SEXT (offs (&opP->disp)),
3221 TAB (DBCCABSJ, SZ_UNDEF));
3222 break;
3223 }
3224 add_fix ('w', &opP->disp, 1, 0);
3225 }
3226 addword (0);
3227 break;
3228 case 'C': /* Fixed size LONG coproc branches. */
3229 add_fix ('l', &opP->disp, 1, 0);
3230 addword (0);
3231 addword (0);
3232 break;
3233 case 'c': /* Var size Coprocesssor branches. */
3234 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3235 {
3236 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3237 add_fix ('l', &opP->disp, 1, 0);
3238 addword (0);
3239 addword (0);
3240 }
3241 else
3242 add_frag (adds (&opP->disp),
3243 SEXT (offs (&opP->disp)),
3244 TAB (FBRANCH, SZ_UNDEF));
3245 break;
3246 default:
3247 abort ();
3248 }
3249 break;
3250
3251 case 'C': /* Ignore it. */
3252 break;
3253
3254 case 'd': /* JF this is a kludge. */
3255 install_operand ('s', opP->reg - ADDR);
3256 tmpreg = get_num (&opP->disp, 90);
3257 if (!issword (tmpreg))
3258 {
3259 as_warn (_("Expression out of range, using 0"));
3260 tmpreg = 0;
3261 }
3262 addword (tmpreg);
3263 break;
3264
3265 case 'D':
3266 install_operand (s[1], opP->reg - DATA);
3267 break;
3268
3269 case 'e': /* EMAC ACCx, reg/reg. */
3270 install_operand (s[1], opP->reg - ACC);
3271 break;
3272
3273 case 'E': /* Ignore it. */
3274 break;
3275
3276 case 'F':
3277 install_operand (s[1], opP->reg - FP0);
3278 break;
3279
3280 case 'g': /* EMAC ACCEXTx. */
3281 install_operand (s[1], opP->reg - ACCEXT01);
3282 break;
3283
3284 case 'G': /* Ignore it. */
3285 case 'H':
3286 break;
3287
3288 case 'I':
3289 tmpreg = opP->reg - COP0;
3290 install_operand (s[1], tmpreg);
3291 break;
3292
3293 case 'i': /* MAC/EMAC scale factor. */
3294 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3295 break;
3296
3297 case 'J': /* JF foo. */
3298 switch (opP->reg)
3299 {
3300 case SFC:
3301 tmpreg = 0x000;
3302 break;
3303 case DFC:
3304 tmpreg = 0x001;
3305 break;
3306 case CACR:
3307 tmpreg = 0x002;
3308 break;
3309 case TC:
3310 case ASID:
3311 tmpreg = 0x003;
3312 break;
3313 case ACR0:
3314 case ITT0:
3315 tmpreg = 0x004;
3316 break;
3317 case ACR1:
3318 case ITT1:
3319 tmpreg = 0x005;
3320 break;
3321 case ACR2:
3322 case DTT0:
3323 tmpreg = 0x006;
3324 break;
3325 case ACR3:
3326 case DTT1:
3327 tmpreg = 0x007;
3328 break;
3329 case BUSCR:
3330 case MMUBAR:
3331 tmpreg = 0x008;
3332 break;
3333
3334 case USP:
3335 tmpreg = 0x800;
3336 break;
3337 case VBR:
3338 tmpreg = 0x801;
3339 break;
3340 case CAAR:
3341 case CPUCR:
3342 tmpreg = 0x802;
3343 break;
3344 case MSP:
3345 tmpreg = 0x803;
3346 break;
3347 case ISP:
3348 tmpreg = 0x804;
3349 break;
3350 case MMUSR:
3351 tmpreg = 0x805;
3352 break;
3353 case URP:
3354 tmpreg = 0x806;
3355 break;
3356 case SRP:
3357 tmpreg = 0x807;
3358 break;
3359 case PCR:
3360 tmpreg = 0x808;
3361 break;
3362 case ROMBAR:
3363 case ROMBAR0:
3364 tmpreg = 0xC00;
3365 break;
3366 case ROMBAR1:
3367 tmpreg = 0xC01;
3368 break;
3369 case FLASHBAR:
3370 case RAMBAR0:
3371 case RAMBAR_ALT:
3372 tmpreg = 0xC04;
3373 break;
3374 case RAMBAR:
3375 case RAMBAR1:
3376 tmpreg = 0xC05;
3377 break;
3378 case MPCR:
3379 tmpreg = 0xC0C;
3380 break;
3381 case EDRAMBAR:
3382 tmpreg = 0xC0D;
3383 break;
3384 case MBAR0:
3385 case MBAR2:
3386 case SECMBAR:
3387 tmpreg = 0xC0E;
3388 break;
3389 case MBAR1:
3390 case MBAR:
3391 tmpreg = 0xC0F;
3392 break;
3393 case PCR1U0:
3394 tmpreg = 0xD02;
3395 break;
3396 case PCR1L0:
3397 tmpreg = 0xD03;
3398 break;
3399 case PCR2U0:
3400 tmpreg = 0xD04;
3401 break;
3402 case PCR2L0:
3403 tmpreg = 0xD05;
3404 break;
3405 case PCR3U0:
3406 tmpreg = 0xD06;
3407 break;
3408 case PCR3L0:
3409 tmpreg = 0xD07;
3410 break;
3411 case PCR1L1:
3412 tmpreg = 0xD0A;
3413 break;
3414 case PCR1U1:
3415 tmpreg = 0xD0B;
3416 break;
3417 case PCR2L1:
3418 tmpreg = 0xD0C;
3419 break;
3420 case PCR2U1:
3421 tmpreg = 0xD0D;
3422 break;
3423 case PCR3L1:
3424 tmpreg = 0xD0E;
3425 break;
3426 case PCR3U1:
3427 tmpreg = 0xD0F;
3428 break;
3429 case CAC:
3430 tmpreg = 0xFFE;
3431 break;
3432 case MBO:
3433 tmpreg = 0xFFF;
3434 break;
3435 default:
3436 abort ();
3437 }
3438 install_operand (s[1], tmpreg);
3439 break;
3440
3441 case 'k':
3442 tmpreg = get_num (&opP->disp, 55);
3443 install_operand (s[1], tmpreg & 0x7f);
3444 break;
3445
3446 case 'l':
3447 tmpreg = opP->mask;
3448 if (s[1] == 'w')
3449 {
3450 if (tmpreg & 0x7FF0000)
3451 as_bad (_("Floating point register in register list"));
3452 insop (reverse_16_bits (tmpreg), opcode);
3453 }
3454 else
3455 {
3456 if (tmpreg & 0x700FFFF)
3457 as_bad (_("Wrong register in floating-point reglist"));
3458 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3459 }
3460 break;
3461
3462 case 'L':
3463 tmpreg = opP->mask;
3464 if (s[1] == 'w')
3465 {
3466 if (tmpreg & 0x7FF0000)
3467 as_bad (_("Floating point register in register list"));
3468 insop (tmpreg, opcode);
3469 }
3470 else if (s[1] == '8')
3471 {
3472 if (tmpreg & 0x0FFFFFF)
3473 as_bad (_("incorrect register in reglist"));
3474 install_operand (s[1], tmpreg >> 24);
3475 }
3476 else
3477 {
3478 if (tmpreg & 0x700FFFF)
3479 as_bad (_("wrong register in floating-point reglist"));
3480 else
3481 install_operand (s[1], tmpreg >> 16);
3482 }
3483 break;
3484
3485 case 'M':
3486 install_operand (s[1], get_num (&opP->disp, 60));
3487 break;
3488
3489 case 'O':
3490 tmpreg = ((opP->mode == DREG)
3491 ? 0x20 + (int) (opP->reg - DATA)
3492 : (get_num (&opP->disp, 40) & 0x1F));
3493 install_operand (s[1], tmpreg);
3494 break;
3495
3496 case 'Q':
3497 tmpreg = get_num (&opP->disp, 10);
3498 if (tmpreg == 8)
3499 tmpreg = 0;
3500 install_operand (s[1], tmpreg);
3501 break;
3502
3503 case 'R':
3504 /* This depends on the fact that ADDR registers are eight
3505 more than their corresponding DATA regs, so the result
3506 will have the ADDR_REG bit set. */
3507 install_operand (s[1], opP->reg - DATA);
3508 break;
3509
3510 case 'r':
3511 if (opP->mode == AINDR)
3512 install_operand (s[1], opP->reg - DATA);
3513 else
3514 install_operand (s[1], opP->index.reg - DATA);
3515 break;
3516
3517 case 's':
3518 if (opP->reg == FPI)
3519 tmpreg = 0x1;
3520 else if (opP->reg == FPS)
3521 tmpreg = 0x2;
3522 else if (opP->reg == FPC)
3523 tmpreg = 0x4;
3524 else
3525 abort ();
3526 install_operand (s[1], tmpreg);
3527 break;
3528
3529 case 'S': /* Ignore it. */
3530 break;
3531
3532 case 'T':
3533 install_operand (s[1], get_num (&opP->disp, 30));
3534 break;
3535
3536 case 'U': /* Ignore it. */
3537 break;
3538
3539 case 'c':
3540 switch (opP->reg)
3541 {
3542 case NC:
3543 tmpreg = 0;
3544 break;
3545 case DC:
3546 tmpreg = 1;
3547 break;
3548 case IC:
3549 tmpreg = 2;
3550 break;
3551 case BC:
3552 tmpreg = 3;
3553 break;
3554 default:
3555 as_fatal (_("failed sanity check"));
3556 } /* switch on cache token. */
3557 install_operand (s[1], tmpreg);
3558 break;
3559 #ifndef NO_68851
3560 /* JF: These are out of order, I fear. */
3561 case 'f':
3562 switch (opP->reg)
3563 {
3564 case SFC:
3565 tmpreg = 0;
3566 break;
3567 case DFC:
3568 tmpreg = 1;
3569 break;
3570 default:
3571 abort ();
3572 }
3573 install_operand (s[1], tmpreg);
3574 break;
3575
3576 case '0':
3577 case '1':
3578 case '2':
3579 switch (opP->reg)
3580 {
3581 case TC:
3582 tmpreg = 0;
3583 break;
3584 case CAL:
3585 tmpreg = 4;
3586 break;
3587 case VAL:
3588 tmpreg = 5;
3589 break;
3590 case SCC:
3591 tmpreg = 6;
3592 break;
3593 case AC:
3594 tmpreg = 7;
3595 break;
3596 default:
3597 abort ();
3598 }
3599 install_operand (s[1], tmpreg);
3600 break;
3601
3602 case 'V':
3603 if (opP->reg == VAL)
3604 break;
3605 abort ();
3606
3607 case 'W':
3608 switch (opP->reg)
3609 {
3610 case DRP:
3611 tmpreg = 1;
3612 break;
3613 case SRP:
3614 tmpreg = 2;
3615 break;
3616 case CRP:
3617 tmpreg = 3;
3618 break;
3619 default:
3620 abort ();
3621 }
3622 install_operand (s[1], tmpreg);
3623 break;
3624
3625 case 'X':
3626 switch (opP->reg)
3627 {
3628 case BAD:
3629 case BAD + 1:
3630 case BAD + 2:
3631 case BAD + 3:
3632 case BAD + 4:
3633 case BAD + 5:
3634 case BAD + 6:
3635 case BAD + 7:
3636 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3637 break;
3638
3639 case BAC:
3640 case BAC + 1:
3641 case BAC + 2:
3642 case BAC + 3:
3643 case BAC + 4:
3644 case BAC + 5:
3645 case BAC + 6:
3646 case BAC + 7:
3647 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3648 break;
3649
3650 default:
3651 abort ();
3652 }
3653 install_operand (s[1], tmpreg);
3654 break;
3655 case 'Y':
3656 know (opP->reg == PSR);
3657 break;
3658 case 'Z':
3659 know (opP->reg == PCSR);
3660 break;
3661 #endif /* m68851 */
3662 case '3':
3663 switch (opP->reg)
3664 {
3665 case TT0:
3666 tmpreg = 2;
3667 break;
3668 case TT1:
3669 tmpreg = 3;
3670 break;
3671 default:
3672 abort ();
3673 }
3674 install_operand (s[1], tmpreg);
3675 break;
3676 case 't':
3677 tmpreg = get_num (&opP->disp, 20);
3678 install_operand (s[1], tmpreg);
3679 break;
3680 case '_': /* used only for move16 absolute 32-bit address. */
3681 if (isvar (&opP->disp))
3682 add_fix ('l', &opP->disp, 0, 0);
3683 tmpreg = get_num (&opP->disp, 90);
3684 addword (tmpreg >> 16);
3685 addword (tmpreg & 0xFFFF);
3686 break;
3687 case 'u':
3688 install_operand (s[1], opP->reg - DATA0L);
3689 opP->reg -= (DATA0L);
3690 opP->reg &= 0x0F; /* remove upper/lower bit. */
3691 break;
3692 case 'x':
3693 tmpreg = get_num (&opP->disp, 80);
3694 if (tmpreg == -1)
3695 tmpreg = 0;
3696 install_operand (s[1], tmpreg);
3697 break;
3698 case 'j':
3699 tmpreg = get_num (&opP->disp, 10);
3700 install_operand (s[1], tmpreg - 1);
3701 break;
3702 case 'K':
3703 tmpreg = get_num (&opP->disp, 65);
3704 install_operand (s[1], tmpreg);
3705 break;
3706 default:
3707 abort ();
3708 }
3709 }
3710
3711 /* By the time whe get here (FINALLY) the_ins contains the complete
3712 instruction, ready to be emitted. . . */
3713 }
3714
3715 static int
3716 reverse_16_bits (int in)
3717 {
3718 int out = 0;
3719 int n;
3720
3721 static int mask[16] =
3722 {
3723 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3724 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3725 };
3726 for (n = 0; n < 16; n++)
3727 {
3728 if (in & mask[n])
3729 out |= mask[15 - n];
3730 }
3731 return out;
3732 } /* reverse_16_bits() */
3733
3734 static int
3735 reverse_8_bits (int in)
3736 {
3737 int out = 0;
3738 int n;
3739
3740 static int mask[8] =
3741 {
3742 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3743 };
3744
3745 for (n = 0; n < 8; n++)
3746 {
3747 if (in & mask[n])
3748 out |= mask[7 - n];
3749 }
3750 return out;
3751 } /* reverse_8_bits() */
3752
3753 /* Cause an extra frag to be generated here, inserting up to
3754 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3755 generated; its primary type is rs_machine_dependent.
3756
3757 The TYPE parameter is also used by md_convert_frag_1 and
3758 md_estimate_size_before_relax. The appropriate type of fixup will
3759 be emitted by md_convert_frag_1.
3760
3761 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3762 static void
3763 install_operand (int mode, int val)
3764 {
3765 switch (mode)
3766 {
3767 case 's':
3768 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3769 break;
3770 case 'd':
3771 the_ins.opcode[0] |= val << 9;
3772 break;
3773 case 'E':
3774 the_ins.opcode[1] |= val << 9;
3775 break;
3776 case '1':
3777 the_ins.opcode[1] |= val << 12;
3778 break;
3779 case '2':
3780 the_ins.opcode[1] |= val << 6;
3781 break;
3782 case '3':
3783 the_ins.opcode[1] |= val;
3784 break;
3785 case '4':
3786 the_ins.opcode[2] |= val << 12;
3787 break;
3788 case '5':
3789 the_ins.opcode[2] |= val << 6;
3790 break;
3791 case '6':
3792 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3793 three words long! */
3794 the_ins.numo++;
3795 the_ins.opcode[2] |= val;
3796 break;
3797 case '7':
3798 the_ins.opcode[1] |= val << 7;
3799 break;
3800 case '8':
3801 the_ins.opcode[1] |= val << 10;
3802 break;
3803 #ifndef NO_68851
3804 case '9':
3805 the_ins.opcode[1] |= val << 5;
3806 break;
3807 #endif
3808
3809 case 't':
3810 the_ins.opcode[1] |= (val << 10) | (val << 7);
3811 break;
3812 case 'D':
3813 the_ins.opcode[1] |= (val << 12) | val;
3814 break;
3815 case 'g':
3816 the_ins.opcode[0] |= val = 0xff;
3817 break;
3818 case 'i':
3819 the_ins.opcode[0] |= val << 9;
3820 break;
3821 case 'C':
3822 the_ins.opcode[1] |= val;
3823 break;
3824 case 'j':
3825 the_ins.opcode[1] |= val;
3826 the_ins.numo++; /* What a hack. */
3827 break;
3828 case 'k':
3829 the_ins.opcode[1] |= val << 4;
3830 break;
3831 case 'b':
3832 case 'w':
3833 case 'W':
3834 case 'l':
3835 break;
3836 case 'e':
3837 the_ins.opcode[0] |= (val << 6);
3838 break;
3839 case 'L':
3840 the_ins.opcode[1] = (val >> 16);
3841 the_ins.opcode[2] = val & 0xffff;
3842 break;
3843 case 'm':
3844 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3845 the_ins.opcode[0] |= ((val & 0x7) << 9);
3846 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3847 break;
3848 case 'n': /* MAC/EMAC Rx on !load. */
3849 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3850 the_ins.opcode[0] |= ((val & 0x7) << 9);
3851 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3852 break;
3853 case 'o': /* MAC/EMAC Rx on load. */
3854 the_ins.opcode[1] |= val << 12;
3855 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3856 break;
3857 case 'M': /* MAC/EMAC Ry on !load. */
3858 the_ins.opcode[0] |= (val & 0xF);
3859 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3860 break;
3861 case 'N': /* MAC/EMAC Ry on load. */
3862 the_ins.opcode[1] |= (val & 0xF);
3863 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3864 break;
3865 case 'h':
3866 the_ins.opcode[1] |= ((val != 1) << 10);
3867 break;
3868 case 'F':
3869 the_ins.opcode[0] |= ((val & 0x3) << 9);
3870 break;
3871 case 'f':
3872 the_ins.opcode[0] |= ((val & 0x3) << 0);
3873 break;
3874 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3875 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3876 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3877 break;
3878 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3879 the_ins.opcode[0] |= ((val & 0x1) << 7);
3880 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3881 break;
3882 case 'I':
3883 the_ins.opcode[1] |= ((val & 0x3) << 9);
3884 break;
3885 case ']':
3886 the_ins.opcode[0] |= (val & 0x1) <<10;
3887 break;
3888 case 'c':
3889 default:
3890 as_fatal (_("failed sanity check."));
3891 }
3892 }
3893
3894 static void
3895 install_gen_operand (int mode, int val)
3896 {
3897 switch (mode)
3898 {
3899 case '/': /* Special for mask loads for mac/msac insns with
3900 possible mask; trailing_ampersend set in bit 8. */
3901 the_ins.opcode[0] |= (val & 0x3f);
3902 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3903 break;
3904 case 's':
3905 the_ins.opcode[0] |= val;
3906 break;
3907 case 'd':
3908 /* This is a kludge!!! */
3909 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3910 break;
3911 case 'b':
3912 case 'w':
3913 case 'l':
3914 case 'f':
3915 case 'F':
3916 case 'x':
3917 case 'p':
3918 the_ins.opcode[0] |= val;
3919 break;
3920 /* more stuff goes here. */
3921 default:
3922 as_fatal (_("failed sanity check."));
3923 }
3924 }
3925
3926 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3927 then deal with the bitfield hack. */
3928
3929 static char *
3930 crack_operand (char *str, struct m68k_op *opP)
3931 {
3932 register int parens;
3933 register int c;
3934 register char *beg_str;
3935 int inquote = 0;
3936
3937 if (!str)
3938 {
3939 return str;
3940 }
3941 beg_str = str;
3942 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3943 {
3944 if (! inquote)
3945 {
3946 if (*str == '(')
3947 parens++;
3948 else if (*str == ')')
3949 {
3950 if (!parens)
3951 { /* ERROR. */
3952 opP->error = _("Extra )");
3953 return str;
3954 }
3955 --parens;
3956 }
3957 }
3958 if (flag_mri && *str == '\'')
3959 inquote = ! inquote;
3960 }
3961 if (!*str && parens)
3962 { /* ERROR. */
3963 opP->error = _("Missing )");
3964 return str;
3965 }
3966 c = *str;
3967 *str = '\0';
3968 if (m68k_ip_op (beg_str, opP) != 0)
3969 {
3970 *str = c;
3971 return str;
3972 }
3973 *str = c;
3974 if (c == '}')
3975 c = *++str; /* JF bitfield hack. */
3976 if (c)
3977 {
3978 c = *++str;
3979 if (!c)
3980 as_bad (_("Missing operand"));
3981 }
3982
3983 /* Detect MRI REG symbols and convert them to REGLSTs. */
3984 if (opP->mode == CONTROL && (int)opP->reg < 0)
3985 {
3986 opP->mode = REGLST;
3987 opP->mask = ~(int)opP->reg;
3988 opP->reg = 0;
3989 }
3990
3991 return str;
3992 }
3993
3994 /* This is the guts of the machine-dependent assembler. STR points to a
3995 machine dependent instruction. This function is supposed to emit
3996 the frags/bytes it assembles to.
3997 */
3998
3999 static void
4000 insert_reg (const char *regname, int regnum)
4001 {
4002 char buf[100];
4003 int i;
4004
4005 #ifdef REGISTER_PREFIX
4006 if (!flag_reg_prefix_optional)
4007 {
4008 buf[0] = REGISTER_PREFIX;
4009 strcpy (buf + 1, regname);
4010 regname = buf;
4011 }
4012 #endif
4013
4014 symbol_table_insert (symbol_new (regname, reg_section, regnum,
4015 &zero_address_frag));
4016
4017 for (i = 0; regname[i]; i++)
4018 buf[i] = TOUPPER (regname[i]);
4019 buf[i] = '\0';
4020
4021 symbol_table_insert (symbol_new (buf, reg_section, regnum,
4022 &zero_address_frag));
4023 }
4024
4025 struct init_entry
4026 {
4027 const char *name;
4028 int number;
4029 };
4030
4031 static const struct init_entry init_table[] =
4032 {
4033 { "d0", DATA0 },
4034 { "d1", DATA1 },
4035 { "d2", DATA2 },
4036 { "d3", DATA3 },
4037 { "d4", DATA4 },
4038 { "d5", DATA5 },
4039 { "d6", DATA6 },
4040 { "d7", DATA7 },
4041 { "a0", ADDR0 },
4042 { "a1", ADDR1 },
4043 { "a2", ADDR2 },
4044 { "a3", ADDR3 },
4045 { "a4", ADDR4 },
4046 { "a5", ADDR5 },
4047 { "a6", ADDR6 },
4048 { "fp", ADDR6 },
4049 { "a7", ADDR7 },
4050 { "sp", ADDR7 },
4051 { "ssp", ADDR7 },
4052 { "fp0", FP0 },
4053 { "fp1", FP1 },
4054 { "fp2", FP2 },
4055 { "fp3", FP3 },
4056 { "fp4", FP4 },
4057 { "fp5", FP5 },
4058 { "fp6", FP6 },
4059 { "fp7", FP7 },
4060 { "fpi", FPI },
4061 { "fpiar", FPI },
4062 { "fpc", FPI },
4063 { "fps", FPS },
4064 { "fpsr", FPS },
4065 { "fpc", FPC },
4066 { "fpcr", FPC },
4067 { "control", FPC },
4068 { "status", FPS },
4069 { "iaddr", FPI },
4070
4071 { "cop0", COP0 },
4072 { "cop1", COP1 },
4073 { "cop2", COP2 },
4074 { "cop3", COP3 },
4075 { "cop4", COP4 },
4076 { "cop5", COP5 },
4077 { "cop6", COP6 },
4078 { "cop7", COP7 },
4079 { "pc", PC },
4080 { "zpc", ZPC },
4081 { "sr", SR },
4082
4083 { "ccr", CCR },
4084 { "cc", CCR },
4085
4086 { "acc", ACC },
4087 { "acc0", ACC },
4088 { "acc1", ACC1 },
4089 { "acc2", ACC2 },
4090 { "acc3", ACC3 },
4091 { "accext01", ACCEXT01 },
4092 { "accext23", ACCEXT23 },
4093 { "macsr", MACSR },
4094 { "mask", MASK },
4095
4096 /* Control registers. */
4097 { "sfc", SFC }, /* Source Function Code. */
4098 { "sfcr", SFC },
4099 { "dfc", DFC }, /* Destination Function Code. */
4100 { "dfcr", DFC },
4101 { "cacr", CACR }, /* Cache Control Register. */
4102 { "caar", CAAR }, /* Cache Address Register. */
4103 { "cpucr", CPUCR }, /* CPU Control Register. */
4104
4105 { "usp", USP }, /* User Stack Pointer. */
4106 { "vbr", VBR }, /* Vector Base Register. */
4107 { "msp", MSP }, /* Master Stack Pointer. */
4108 { "isp", ISP }, /* Interrupt Stack Pointer. */
4109
4110 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
4111 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
4112 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
4113 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
4114
4115 /* 68ec040 versions of same */
4116 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
4117 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
4118 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
4119 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
4120
4121 /* Coldfire versions of same. The ColdFire programmer's reference
4122 manual indicated that the order is 2,3,0,1, but Ken Rose
4123 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
4124 { "acr0", ACR0 }, /* Access Control Unit 0. */
4125 { "acr1", ACR1 }, /* Access Control Unit 1. */
4126 { "acr2", ACR2 }, /* Access Control Unit 2. */
4127 { "acr3", ACR3 }, /* Access Control Unit 3. */
4128
4129 { "tc", TC }, /* MMU Translation Control Register. */
4130 { "tcr", TC },
4131 { "asid", ASID },
4132
4133 { "mmusr", MMUSR }, /* MMU Status Register. */
4134 { "srp", SRP }, /* User Root Pointer. */
4135 { "urp", URP }, /* Supervisor Root Pointer. */
4136
4137 { "buscr", BUSCR },
4138 { "mmubar", MMUBAR },
4139 { "pcr", PCR },
4140
4141 { "rombar", ROMBAR }, /* ROM Base Address Register. */
4142 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
4143 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
4144 { "mbar", MBAR }, /* Module Base Address Register. */
4145
4146 { "mbar0", MBAR0 }, /* mcfv4e registers. */
4147 { "mbar1", MBAR1 }, /* mcfv4e registers. */
4148 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
4149 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
4150 { "mpcr", MPCR }, /* mcfv4e registers. */
4151 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
4152 { "secmbar", SECMBAR }, /* mcfv4e registers. */
4153 { "asid", TC }, /* mcfv4e registers. */
4154 { "mmubar", BUSCR }, /* mcfv4e registers. */
4155 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
4156 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
4157 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
4158 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
4159 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
4160 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
4161 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
4162 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
4163 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
4164 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4165 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4166 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4167
4168 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4169 { "rambar", RAMBAR }, /* mcf528x registers. */
4170
4171 { "mbar2", MBAR2 }, /* mcf5249 registers. */
4172
4173 { "cac", CAC }, /* fido registers. */
4174 { "mbb", MBO }, /* fido registers (obsolete). */
4175 { "mbo", MBO }, /* fido registers. */
4176 /* End of control registers. */
4177
4178 { "ac", AC },
4179 { "bc", BC },
4180 { "cal", CAL },
4181 { "crp", CRP },
4182 { "drp", DRP },
4183 { "pcsr", PCSR },
4184 { "psr", PSR },
4185 { "scc", SCC },
4186 { "val", VAL },
4187 { "bad0", BAD0 },
4188 { "bad1", BAD1 },
4189 { "bad2", BAD2 },
4190 { "bad3", BAD3 },
4191 { "bad4", BAD4 },
4192 { "bad5", BAD5 },
4193 { "bad6", BAD6 },
4194 { "bad7", BAD7 },
4195 { "bac0", BAC0 },
4196 { "bac1", BAC1 },
4197 { "bac2", BAC2 },
4198 { "bac3", BAC3 },
4199 { "bac4", BAC4 },
4200 { "bac5", BAC5 },
4201 { "bac6", BAC6 },
4202 { "bac7", BAC7 },
4203
4204 { "ic", IC },
4205 { "dc", DC },
4206 { "nc", NC },
4207
4208 { "tt0", TT0 },
4209 { "tt1", TT1 },
4210 /* 68ec030 versions of same. */
4211 { "ac0", TT0 },
4212 { "ac1", TT1 },
4213 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4214 { "acusr", PSR },
4215
4216 /* Suppressed data and address registers. */
4217 { "zd0", ZDATA0 },
4218 { "zd1", ZDATA1 },
4219 { "zd2", ZDATA2 },
4220 { "zd3", ZDATA3 },
4221 { "zd4", ZDATA4 },
4222 { "zd5", ZDATA5 },
4223 { "zd6", ZDATA6 },
4224 { "zd7", ZDATA7 },
4225 { "za0", ZADDR0 },
4226 { "za1", ZADDR1 },
4227 { "za2", ZADDR2 },
4228 { "za3", ZADDR3 },
4229 { "za4", ZADDR4 },
4230 { "za5", ZADDR5 },
4231 { "za6", ZADDR6 },
4232 { "za7", ZADDR7 },
4233
4234 /* Upper and lower data and address registers, used by macw and msacw. */
4235 { "d0l", DATA0L },
4236 { "d1l", DATA1L },
4237 { "d2l", DATA2L },
4238 { "d3l", DATA3L },
4239 { "d4l", DATA4L },
4240 { "d5l", DATA5L },
4241 { "d6l", DATA6L },
4242 { "d7l", DATA7L },
4243
4244 { "a0l", ADDR0L },
4245 { "a1l", ADDR1L },
4246 { "a2l", ADDR2L },
4247 { "a3l", ADDR3L },
4248 { "a4l", ADDR4L },
4249 { "a5l", ADDR5L },
4250 { "a6l", ADDR6L },
4251 { "a7l", ADDR7L },
4252
4253 { "d0u", DATA0U },
4254 { "d1u", DATA1U },
4255 { "d2u", DATA2U },
4256 { "d3u", DATA3U },
4257 { "d4u", DATA4U },
4258 { "d5u", DATA5U },
4259 { "d6u", DATA6U },
4260 { "d7u", DATA7U },
4261
4262 { "a0u", ADDR0U },
4263 { "a1u", ADDR1U },
4264 { "a2u", ADDR2U },
4265 { "a3u", ADDR3U },
4266 { "a4u", ADDR4U },
4267 { "a5u", ADDR5U },
4268 { "a6u", ADDR6U },
4269 { "a7u", ADDR7U },
4270
4271 { 0, 0 }
4272 };
4273
4274 static void
4275 init_regtable (void)
4276 {
4277 int i;
4278 for (i = 0; init_table[i].name; i++)
4279 insert_reg (init_table[i].name, init_table[i].number);
4280 }
4281
4282 void
4283 md_assemble (char *str)
4284 {
4285 const char *er;
4286 short *fromP;
4287 char *toP = NULL;
4288 int m, n = 0;
4289 char *to_beg_P;
4290 int shorts_this_frag;
4291 fixS *fixP;
4292
4293 if (!selected_cpu && !selected_arch)
4294 {
4295 /* We've not selected an architecture yet. Set the default
4296 now. We do this lazily so that an initial .cpu or .arch directive
4297 can specify. */
4298 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4299 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4300 }
4301 if (!initialized)
4302 m68k_init_arch ();
4303
4304 /* In MRI mode, the instruction and operands are separated by a
4305 space. Anything following the operands is a comment. The label
4306 has already been removed. */
4307 if (flag_mri)
4308 {
4309 char *s;
4310 int fields = 0;
4311 int infield = 0;
4312 int inquote = 0;
4313
4314 for (s = str; *s != '\0'; s++)
4315 {
4316 if ((*s == ' ' || *s == '\t') && ! inquote)
4317 {
4318 if (infield)
4319 {
4320 ++fields;
4321 if (fields >= 2)
4322 {
4323 *s = '\0';
4324 break;
4325 }
4326 infield = 0;
4327 }
4328 }
4329 else
4330 {
4331 if (! infield)
4332 infield = 1;
4333 if (*s == '\'')
4334 inquote = ! inquote;
4335 }
4336 }
4337 }
4338
4339 memset (&the_ins, '\0', sizeof (the_ins));
4340 m68k_ip (str);
4341 er = the_ins.error;
4342 if (!er)
4343 {
4344 for (n = 0; n < the_ins.numargs; n++)
4345 if (the_ins.operands[n].error)
4346 {
4347 er = the_ins.operands[n].error;
4348 break;
4349 }
4350 }
4351 if (er)
4352 {
4353 as_bad (_("%s -- statement `%s' ignored"), er, str);
4354 return;
4355 }
4356
4357 /* If there is a current label, record that it marks an instruction. */
4358 if (current_label != NULL)
4359 {
4360 current_label->text = 1;
4361 current_label = NULL;
4362 }
4363
4364 #ifdef OBJ_ELF
4365 /* Tie dwarf2 debug info to the address at the start of the insn. */
4366 dwarf2_emit_insn (0);
4367 #endif
4368
4369 if (the_ins.nfrag == 0)
4370 {
4371 /* No frag hacking involved; just put it out. */
4372 toP = frag_more (2 * the_ins.numo);
4373 fromP = &the_ins.opcode[0];
4374 for (m = the_ins.numo; m; --m)
4375 {
4376 md_number_to_chars (toP, (long) (*fromP), 2);
4377 toP += 2;
4378 fromP++;
4379 }
4380 /* Put out symbol-dependent info. */
4381 for (m = 0; m < the_ins.nrel; m++)
4382 {
4383 switch (the_ins.reloc[m].wid)
4384 {
4385 case 'B':
4386 n = 1;
4387 break;
4388 case 'b':
4389 n = 1;
4390 break;
4391 case '3':
4392 n = 1;
4393 break;
4394 case 'w':
4395 case 'W':
4396 n = 2;
4397 break;
4398 case 'l':
4399 n = 4;
4400 break;
4401 default:
4402 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4403 the_ins.reloc[m].wid);
4404 }
4405
4406 fixP = fix_new_exp (frag_now,
4407 ((toP - frag_now->fr_literal)
4408 - the_ins.numo * 2 + the_ins.reloc[m].n),
4409 n,
4410 &the_ins.reloc[m].exp,
4411 the_ins.reloc[m].pcrel,
4412 get_reloc_code (n, the_ins.reloc[m].pcrel,
4413 the_ins.reloc[m].pic_reloc));
4414 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4415 if (the_ins.reloc[m].wid == 'B')
4416 fixP->fx_signed = 1;
4417 }
4418 return;
4419 }
4420
4421 /* There's some frag hacking. */
4422 {
4423 /* Calculate the max frag size. */
4424 int wid;
4425
4426 wid = 2 * the_ins.fragb[0].fragoff;
4427 for (n = 1; n < the_ins.nfrag; n++)
4428 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4429 /* frag_var part. */
4430 wid += FRAG_VAR_SIZE;
4431 /* Make sure the whole insn fits in one chunk, in particular that
4432 the var part is attached, as we access one byte before the
4433 variable frag for byte branches. */
4434 frag_grow (wid);
4435 }
4436
4437 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4438 {
4439 int wid;
4440
4441 if (n == 0)
4442 wid = 2 * the_ins.fragb[n].fragoff;
4443 else
4444 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4445 toP = frag_more (wid);
4446 to_beg_P = toP;
4447 shorts_this_frag = 0;
4448 for (m = wid / 2; m; --m)
4449 {
4450 md_number_to_chars (toP, (long) (*fromP), 2);
4451 toP += 2;
4452 fromP++;
4453 shorts_this_frag++;
4454 }
4455 for (m = 0; m < the_ins.nrel; m++)
4456 {
4457 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4458 {
4459 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4460 break;
4461 }
4462 wid = the_ins.reloc[m].wid;
4463 if (wid == 0)
4464 continue;
4465 the_ins.reloc[m].wid = 0;
4466 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4467
4468 fixP = fix_new_exp (frag_now,
4469 ((toP - frag_now->fr_literal)
4470 - the_ins.numo * 2 + the_ins.reloc[m].n),
4471 wid,
4472 &the_ins.reloc[m].exp,
4473 the_ins.reloc[m].pcrel,
4474 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4475 the_ins.reloc[m].pic_reloc));
4476 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4477 }
4478 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
4479 (relax_substateT) (the_ins.fragb[n].fragty),
4480 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4481 }
4482 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4483 shorts_this_frag = 0;
4484 if (n)
4485 {
4486 toP = frag_more (n * 2);
4487 while (n--)
4488 {
4489 md_number_to_chars (toP, (long) (*fromP), 2);
4490 toP += 2;
4491 fromP++;
4492 shorts_this_frag++;
4493 }
4494 }
4495 for (m = 0; m < the_ins.nrel; m++)
4496 {
4497 int wid;
4498
4499 wid = the_ins.reloc[m].wid;
4500 if (wid == 0)
4501 continue;
4502 the_ins.reloc[m].wid = 0;
4503 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4504
4505 fixP = fix_new_exp (frag_now,
4506 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4507 - shorts_this_frag * 2),
4508 wid,
4509 &the_ins.reloc[m].exp,
4510 the_ins.reloc[m].pcrel,
4511 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4512 the_ins.reloc[m].pic_reloc));
4513 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4514 }
4515 }
4516
4517 /* Comparison function used by qsort to rank the opcode entries by name. */
4518
4519 static int
4520 m68k_compare_opcode (const void * v1, const void * v2)
4521 {
4522 struct m68k_opcode * op1, * op2;
4523 int ret;
4524
4525 if (v1 == v2)
4526 return 0;
4527
4528 op1 = *(struct m68k_opcode **) v1;
4529 op2 = *(struct m68k_opcode **) v2;
4530
4531 /* Compare the two names. If different, return the comparison.
4532 If the same, return the order they are in the opcode table. */
4533 ret = strcmp (op1->name, op2->name);
4534 if (ret)
4535 return ret;
4536 if (op1 < op2)
4537 return -1;
4538 return 1;
4539 }
4540
4541 void
4542 md_begin (void)
4543 {
4544 const struct m68k_opcode *ins;
4545 struct m68k_incant *hack, *slak;
4546 const char *retval = 0; /* Empty string, or error msg text. */
4547 int i;
4548
4549 /* Set up hash tables with 68000 instructions.
4550 similar to what the vax assembler does. */
4551 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4552 a copy of it at runtime, adding in the information we want but isn't
4553 there. I think it'd be better to have an awk script hack the table
4554 at compile time. Or even just xstr the table and use it as-is. But
4555 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4556 names. */
4557
4558 if (flag_mri)
4559 {
4560 flag_reg_prefix_optional = 1;
4561 m68k_abspcadd = 1;
4562 if (! m68k_rel32_from_cmdline)
4563 m68k_rel32 = 0;
4564 }
4565
4566 /* First sort the opcode table into alphabetical order to seperate
4567 the order that the assembler wants to see the opcodes from the
4568 order that the disassembler wants to see them. */
4569 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4570 if (!m68k_sorted_opcodes)
4571 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4572 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4573
4574 for (i = m68k_numopcodes; i--;)
4575 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4576
4577 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4578 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4579
4580 op_hash = hash_new ();
4581
4582 obstack_begin (&robyn, 4000);
4583 for (i = 0; i < m68k_numopcodes; i++)
4584 {
4585 hack = slak = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4586 do
4587 {
4588 ins = m68k_sorted_opcodes[i];
4589
4590 /* We must enter all insns into the table, because .arch and
4591 .cpu directives can change things. */
4592 slak->m_operands = ins->args;
4593 slak->m_arch = ins->arch;
4594 slak->m_opcode = ins->opcode;
4595
4596 /* In most cases we can determine the number of opcode words
4597 by checking the second word of the mask. Unfortunately
4598 some instructions have 2 opcode words, but no fixed bits
4599 in the second word. A leading dot in the operands
4600 string also indicates 2 opcodes. */
4601 if (*slak->m_operands == '.')
4602 {
4603 slak->m_operands++;
4604 slak->m_codenum = 2;
4605 }
4606 else if (ins->match & 0xffffL)
4607 slak->m_codenum = 2;
4608 else
4609 slak->m_codenum = 1;
4610 slak->m_opnum = strlen (slak->m_operands) / 2;
4611
4612 if (i + 1 != m68k_numopcodes
4613 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4614 {
4615 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4616 i++;
4617 }
4618 else
4619 slak->m_next = 0;
4620 slak = slak->m_next;
4621 }
4622 while (slak);
4623
4624 retval = hash_insert (op_hash, ins->name, (char *) hack);
4625 if (retval)
4626 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4627 }
4628
4629 for (i = 0; i < m68k_numaliases; i++)
4630 {
4631 const char *name = m68k_opcode_aliases[i].primary;
4632 const char *alias = m68k_opcode_aliases[i].alias;
4633 void *val = hash_find (op_hash, name);
4634
4635 if (!val)
4636 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4637 retval = hash_insert (op_hash, alias, val);
4638 if (retval)
4639 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4640 }
4641
4642 /* In MRI mode, all unsized branches are variable sized. Normally,
4643 they are word sized. */
4644 if (flag_mri)
4645 {
4646 static struct m68k_opcode_alias mri_aliases[] =
4647 {
4648 { "bhi", "jhi", },
4649 { "bls", "jls", },
4650 { "bcc", "jcc", },
4651 { "bcs", "jcs", },
4652 { "bne", "jne", },
4653 { "beq", "jeq", },
4654 { "bvc", "jvc", },
4655 { "bvs", "jvs", },
4656 { "bpl", "jpl", },
4657 { "bmi", "jmi", },
4658 { "bge", "jge", },
4659 { "blt", "jlt", },
4660 { "bgt", "jgt", },
4661 { "ble", "jle", },
4662 { "bra", "jra", },
4663 { "bsr", "jbsr", },
4664 };
4665
4666 for (i = 0;
4667 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4668 i++)
4669 {
4670 const char *name = mri_aliases[i].primary;
4671 const char *alias = mri_aliases[i].alias;
4672 void *val = hash_find (op_hash, name);
4673
4674 if (!val)
4675 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4676 retval = hash_jam (op_hash, alias, val);
4677 if (retval)
4678 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4679 }
4680 }
4681
4682 for (i = 0; i < (int) sizeof (notend_table); i++)
4683 {
4684 notend_table[i] = 0;
4685 alt_notend_table[i] = 0;
4686 }
4687
4688 notend_table[','] = 1;
4689 notend_table['{'] = 1;
4690 notend_table['}'] = 1;
4691 alt_notend_table['a'] = 1;
4692 alt_notend_table['A'] = 1;
4693 alt_notend_table['d'] = 1;
4694 alt_notend_table['D'] = 1;
4695 alt_notend_table['#'] = 1;
4696 alt_notend_table['&'] = 1;
4697 alt_notend_table['f'] = 1;
4698 alt_notend_table['F'] = 1;
4699 #ifdef REGISTER_PREFIX
4700 alt_notend_table[REGISTER_PREFIX] = 1;
4701 #endif
4702
4703 /* We need to put '(' in alt_notend_table to handle
4704 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4705 alt_notend_table['('] = 1;
4706
4707 /* We need to put '@' in alt_notend_table to handle
4708 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4709 alt_notend_table['@'] = 1;
4710
4711 /* We need to put digits in alt_notend_table to handle
4712 bfextu %d0{24:1},%d0 */
4713 alt_notend_table['0'] = 1;
4714 alt_notend_table['1'] = 1;
4715 alt_notend_table['2'] = 1;
4716 alt_notend_table['3'] = 1;
4717 alt_notend_table['4'] = 1;
4718 alt_notend_table['5'] = 1;
4719 alt_notend_table['6'] = 1;
4720 alt_notend_table['7'] = 1;
4721 alt_notend_table['8'] = 1;
4722 alt_notend_table['9'] = 1;
4723
4724 #ifndef MIT_SYNTAX_ONLY
4725 /* Insert pseudo ops, these have to go into the opcode table since
4726 gas expects pseudo ops to start with a dot. */
4727 {
4728 int n = 0;
4729
4730 while (mote_pseudo_table[n].poc_name)
4731 {
4732 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4733 hash_insert (op_hash,
4734 mote_pseudo_table[n].poc_name, (char *) hack);
4735 hack->m_operands = 0;
4736 hack->m_opnum = n;
4737 n++;
4738 }
4739 }
4740 #endif
4741
4742 init_regtable ();
4743
4744 #ifdef OBJ_ELF
4745 record_alignment (text_section, 2);
4746 record_alignment (data_section, 2);
4747 record_alignment (bss_section, 2);
4748 #endif
4749 }
4750
4751 \f
4752 /* This is called when a label is defined. */
4753
4754 void
4755 m68k_frob_label (symbolS *sym)
4756 {
4757 struct label_line *n;
4758
4759 n = (struct label_line *) xmalloc (sizeof *n);
4760 n->next = labels;
4761 n->label = sym;
4762 as_where (&n->file, &n->line);
4763 n->text = 0;
4764 labels = n;
4765 current_label = n;
4766
4767 #ifdef OBJ_ELF
4768 dwarf2_emit_label (sym);
4769 #endif
4770 }
4771
4772 /* This is called when a value that is not an instruction is emitted. */
4773
4774 void
4775 m68k_flush_pending_output (void)
4776 {
4777 current_label = NULL;
4778 }
4779
4780 /* This is called at the end of the assembly, when the final value of
4781 the label is known. We warn if this is a text symbol aligned at an
4782 odd location. */
4783
4784 void
4785 m68k_frob_symbol (symbolS *sym)
4786 {
4787 if (S_GET_SEGMENT (sym) == reg_section
4788 && (int) S_GET_VALUE (sym) < 0)
4789 {
4790 S_SET_SEGMENT (sym, absolute_section);
4791 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4792 }
4793 else if ((S_GET_VALUE (sym) & 1) != 0)
4794 {
4795 struct label_line *l;
4796
4797 for (l = labels; l != NULL; l = l->next)
4798 {
4799 if (l->label == sym)
4800 {
4801 if (l->text)
4802 as_warn_where (l->file, l->line,
4803 _("text label `%s' aligned to odd boundary"),
4804 S_GET_NAME (sym));
4805 break;
4806 }
4807 }
4808 }
4809 }
4810 \f
4811 /* This is called if we go in or out of MRI mode because of the .mri
4812 pseudo-op. */
4813
4814 void
4815 m68k_mri_mode_change (int on)
4816 {
4817 if (on)
4818 {
4819 if (! flag_reg_prefix_optional)
4820 {
4821 flag_reg_prefix_optional = 1;
4822 #ifdef REGISTER_PREFIX
4823 init_regtable ();
4824 #endif
4825 }
4826 m68k_abspcadd = 1;
4827 if (! m68k_rel32_from_cmdline)
4828 m68k_rel32 = 0;
4829 }
4830 else
4831 {
4832 if (! reg_prefix_optional_seen)
4833 {
4834 #ifdef REGISTER_PREFIX_OPTIONAL
4835 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4836 #else
4837 flag_reg_prefix_optional = 0;
4838 #endif
4839 #ifdef REGISTER_PREFIX
4840 init_regtable ();
4841 #endif
4842 }
4843 m68k_abspcadd = 0;
4844 if (! m68k_rel32_from_cmdline)
4845 m68k_rel32 = 1;
4846 }
4847 }
4848
4849 char *
4850 md_atof (int type, char *litP, int *sizeP)
4851 {
4852 return ieee_md_atof (type, litP, sizeP, TRUE);
4853 }
4854
4855 void
4856 md_number_to_chars (char *buf, valueT val, int n)
4857 {
4858 number_to_chars_bigendian (buf, val, n);
4859 }
4860
4861 void
4862 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4863 {
4864 offsetT val = *valP;
4865 addressT upper_limit;
4866 offsetT lower_limit;
4867
4868 /* This is unnecessary but it convinces the native rs6000 compiler
4869 to generate the code we want. */
4870 char *buf = fixP->fx_frag->fr_literal;
4871 buf += fixP->fx_where;
4872 /* End ibm compiler workaround. */
4873
4874 val = SEXT (val);
4875
4876 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4877 fixP->fx_done = 1;
4878
4879 #ifdef OBJ_ELF
4880 if (fixP->fx_addsy)
4881 {
4882 memset (buf, 0, fixP->fx_size);
4883 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4884
4885 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4886 && !S_IS_DEFINED (fixP->fx_addsy)
4887 && !S_IS_WEAK (fixP->fx_addsy))
4888 S_SET_WEAK (fixP->fx_addsy);
4889
4890 switch (fixP->fx_r_type)
4891 {
4892 case BFD_RELOC_68K_TLS_GD32:
4893 case BFD_RELOC_68K_TLS_GD16:
4894 case BFD_RELOC_68K_TLS_GD8:
4895 case BFD_RELOC_68K_TLS_LDM32:
4896 case BFD_RELOC_68K_TLS_LDM16:
4897 case BFD_RELOC_68K_TLS_LDM8:
4898 case BFD_RELOC_68K_TLS_LDO32:
4899 case BFD_RELOC_68K_TLS_LDO16:
4900 case BFD_RELOC_68K_TLS_LDO8:
4901 case BFD_RELOC_68K_TLS_IE32:
4902 case BFD_RELOC_68K_TLS_IE16:
4903 case BFD_RELOC_68K_TLS_IE8:
4904 case BFD_RELOC_68K_TLS_LE32:
4905 case BFD_RELOC_68K_TLS_LE16:
4906 case BFD_RELOC_68K_TLS_LE8:
4907 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4908 break;
4909
4910 default:
4911 break;
4912 }
4913
4914 return;
4915 }
4916 #elif defined(OBJ_AOUT)
4917 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4918 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4919 {
4920 memset (buf, 0, fixP->fx_size);
4921 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4922 return;
4923 }
4924 #endif
4925
4926 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4927 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4928 return;
4929
4930 switch (fixP->fx_size)
4931 {
4932 /* The cast to offsetT below are necessary to make code
4933 correct for machines where ints are smaller than offsetT. */
4934 case 1:
4935 *buf++ = val;
4936 upper_limit = 0x7f;
4937 lower_limit = - (offsetT) 0x80;
4938 break;
4939 case 2:
4940 *buf++ = (val >> 8);
4941 *buf++ = val;
4942 upper_limit = 0x7fff;
4943 lower_limit = - (offsetT) 0x8000;
4944 break;
4945 case 4:
4946 *buf++ = (val >> 24);
4947 *buf++ = (val >> 16);
4948 *buf++ = (val >> 8);
4949 *buf++ = val;
4950 upper_limit = 0x7fffffff;
4951 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4952 break;
4953 default:
4954 BAD_CASE (fixP->fx_size);
4955 }
4956
4957 /* Fix up a negative reloc. */
4958 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4959 {
4960 fixP->fx_addsy = fixP->fx_subsy;
4961 fixP->fx_subsy = NULL;
4962 fixP->fx_tcbit = 1;
4963 }
4964
4965 /* For non-pc-relative values, it's conceivable we might get something
4966 like "0xff" for a byte field. So extend the upper part of the range
4967 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4968 so that we can do any range checking at all. */
4969 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4970 upper_limit = upper_limit * 2 + 1;
4971
4972 if ((addressT) val > upper_limit
4973 && (val > 0 || val < lower_limit))
4974 as_bad_where (fixP->fx_file, fixP->fx_line,
4975 _("value %ld out of range"), (long)val);
4976
4977 /* A one byte PC-relative reloc means a short branch. We can't use
4978 a short branch with a value of 0 or -1, because those indicate
4979 different opcodes (branches with longer offsets). fixup_segment
4980 in write.c may have clobbered fx_pcrel, so we need to examine the
4981 reloc type. */
4982 if ((fixP->fx_pcrel
4983 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4984 && fixP->fx_size == 1
4985 && (fixP->fx_addsy == NULL
4986 || S_IS_DEFINED (fixP->fx_addsy))
4987 && (val == 0 || val == -1))
4988 as_bad_where (fixP->fx_file, fixP->fx_line,
4989 _("invalid byte branch offset"));
4990 }
4991
4992 /* *fragP has been relaxed to its final size, and now needs to have
4993 the bytes inside it modified to conform to the new size There is UGLY
4994 MAGIC here. ..
4995 */
4996 static void
4997 md_convert_frag_1 (fragS *fragP)
4998 {
4999 long disp;
5000 fixS *fixP = NULL;
5001
5002 /* Address in object code of the displacement. */
5003 register int object_address = fragP->fr_fix + fragP->fr_address;
5004
5005 /* Address in gas core of the place to store the displacement. */
5006 /* This convinces the native rs6000 compiler to generate the code we
5007 want. */
5008 register char *buffer_address = fragP->fr_literal;
5009 buffer_address += fragP->fr_fix;
5010 /* End ibm compiler workaround. */
5011
5012 /* The displacement of the address, from current location. */
5013 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
5014 disp = (disp + fragP->fr_offset) - object_address;
5015
5016 switch (fragP->fr_subtype)
5017 {
5018 case TAB (BRANCHBWL, BYTE):
5019 case TAB (BRABSJUNC, BYTE):
5020 case TAB (BRABSJCOND, BYTE):
5021 case TAB (BRANCHBW, BYTE):
5022 case TAB (BRANCHBWPL, BYTE):
5023 know (issbyte (disp));
5024 if (disp == 0)
5025 as_bad_where (fragP->fr_file, fragP->fr_line,
5026 _("short branch with zero offset: use :w"));
5027 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5028 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5029 fixP->fx_pcrel_adjust = -1;
5030 break;
5031 case TAB (BRANCHBWL, SHORT):
5032 case TAB (BRABSJUNC, SHORT):
5033 case TAB (BRABSJCOND, SHORT):
5034 case TAB (BRANCHBW, SHORT):
5035 case TAB (BRANCHBWPL, SHORT):
5036 fragP->fr_opcode[1] = 0x00;
5037 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5038 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5039 fragP->fr_fix += 2;
5040 break;
5041 case TAB (BRANCHBWL, LONG):
5042 fragP->fr_opcode[1] = (char) 0xFF;
5043 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5044 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5045 fragP->fr_fix += 4;
5046 break;
5047 case TAB (BRANCHBWPL, LONG):
5048 /* Here we are converting an unconditional branch into a pair of
5049 conditional branches, in order to get the range. */
5050 fragP->fr_opcode[0] = 0x66; /* bne */
5051 fragP->fr_opcode[1] = 0xFF;
5052 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5053 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5054 fixP->fx_file = fragP->fr_file;
5055 fixP->fx_line = fragP->fr_line;
5056 fragP->fr_fix += 4; /* Skip first offset */
5057 buffer_address += 4;
5058 *buffer_address++ = 0x67; /* beq */
5059 *buffer_address++ = 0xff;
5060 fragP->fr_fix += 2; /* Skip second branch opcode */
5061 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5062 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5063 fragP->fr_fix += 4;
5064 break;
5065 case TAB (BRABSJUNC, LONG):
5066 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
5067 {
5068 if (flag_keep_pcrel)
5069 as_bad_where (fragP->fr_file, fragP->fr_line,
5070 _("Conversion of PC relative BSR to absolute JSR"));
5071 fragP->fr_opcode[0] = 0x4E;
5072 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
5073 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5074 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5075 fragP->fr_fix += 4;
5076 }
5077 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
5078 {
5079 if (flag_keep_pcrel)
5080 as_bad_where (fragP->fr_file, fragP->fr_line,
5081 _("Conversion of PC relative branch to absolute jump"));
5082 fragP->fr_opcode[0] = 0x4E;
5083 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
5084 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5085 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5086 fragP->fr_fix += 4;
5087 }
5088 else
5089 {
5090 /* This cannot happen, because jbsr and jbra are the only two
5091 unconditional branches. */
5092 abort ();
5093 }
5094 break;
5095 case TAB (BRABSJCOND, LONG):
5096 if (flag_keep_pcrel)
5097 as_bad_where (fragP->fr_file, fragP->fr_line,
5098 _("Conversion of PC relative conditional branch to absolute jump"));
5099
5100 /* Only Bcc 68000 instructions can come here
5101 Change bcc into b!cc/jmp absl long. */
5102 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
5103 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
5104
5105 /* JF: these used to be fr_opcode[2,3], but they may be in a
5106 different frag, in which case referring to them is a no-no.
5107 Only fr_opcode[0,1] are guaranteed to work. */
5108 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
5109 *buffer_address++ = (char) 0xf9;
5110 fragP->fr_fix += 2; /* Account for jmp instruction. */
5111 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5112 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5113 fragP->fr_fix += 4;
5114 break;
5115 case TAB (FBRANCH, SHORT):
5116 know ((fragP->fr_opcode[1] & 0x40) == 0);
5117 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5118 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5119 fragP->fr_fix += 2;
5120 break;
5121 case TAB (FBRANCH, LONG):
5122 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
5123 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5124 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5125 fragP->fr_fix += 4;
5126 break;
5127 case TAB (DBCCLBR, SHORT):
5128 case TAB (DBCCABSJ, SHORT):
5129 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5130 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5131 fragP->fr_fix += 2;
5132 break;
5133 case TAB (DBCCLBR, LONG):
5134 /* Only DBcc instructions can come here.
5135 Change dbcc into dbcc/bral.
5136 JF: these used to be fr_opcode[2-7], but that's wrong. */
5137 if (flag_keep_pcrel)
5138 as_bad_where (fragP->fr_file, fragP->fr_line,
5139 _("Conversion of DBcc to absolute jump"));
5140
5141 *buffer_address++ = 0x00; /* Branch offset = 4. */
5142 *buffer_address++ = 0x04;
5143 *buffer_address++ = 0x60; /* Put in bra pc+6. */
5144 *buffer_address++ = 0x06;
5145 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5146 *buffer_address++ = (char) 0xff;
5147
5148 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5149 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5150 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5151 fragP->fr_fix += 4;
5152 break;
5153 case TAB (DBCCABSJ, LONG):
5154 /* Only DBcc instructions can come here.
5155 Change dbcc into dbcc/jmp.
5156 JF: these used to be fr_opcode[2-7], but that's wrong. */
5157 if (flag_keep_pcrel)
5158 as_bad_where (fragP->fr_file, fragP->fr_line,
5159 _("Conversion of PC relative conditional branch to absolute jump"));
5160
5161 *buffer_address++ = 0x00; /* Branch offset = 4. */
5162 *buffer_address++ = 0x04;
5163 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
5164 *buffer_address++ = 0x06;
5165 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
5166 *buffer_address++ = (char) 0xf9;
5167
5168 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5169 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5170 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5171 fragP->fr_fix += 4;
5172 break;
5173 case TAB (PCREL1632, SHORT):
5174 fragP->fr_opcode[1] &= ~0x3F;
5175 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
5176 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5177 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5178 fragP->fr_fix += 2;
5179 break;
5180 case TAB (PCREL1632, LONG):
5181 /* Already set to mode 7.3; this indicates: PC indirect with
5182 suppressed index, 32-bit displacement. */
5183 *buffer_address++ = 0x01;
5184 *buffer_address++ = 0x70;
5185 fragP->fr_fix += 2;
5186 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5187 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5188 fixP->fx_pcrel_adjust = 2;
5189 fragP->fr_fix += 4;
5190 break;
5191 case TAB (PCINDEX, BYTE):
5192 gas_assert (fragP->fr_fix >= 2);
5193 buffer_address[-2] &= ~1;
5194 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5195 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5196 fixP->fx_pcrel_adjust = 1;
5197 break;
5198 case TAB (PCINDEX, SHORT):
5199 gas_assert (fragP->fr_fix >= 2);
5200 buffer_address[-2] |= 0x1;
5201 buffer_address[-1] = 0x20;
5202 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5203 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5204 fixP->fx_pcrel_adjust = 2;
5205 fragP->fr_fix += 2;
5206 break;
5207 case TAB (PCINDEX, LONG):
5208 gas_assert (fragP->fr_fix >= 2);
5209 buffer_address[-2] |= 0x1;
5210 buffer_address[-1] = 0x30;
5211 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5212 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5213 fixP->fx_pcrel_adjust = 2;
5214 fragP->fr_fix += 4;
5215 break;
5216 case TAB (ABSTOPCREL, SHORT):
5217 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5218 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5219 fragP->fr_fix += 2;
5220 break;
5221 case TAB (ABSTOPCREL, LONG):
5222 if (flag_keep_pcrel)
5223 as_bad_where (fragP->fr_file, fragP->fr_line,
5224 _("Conversion of PC relative displacement to absolute"));
5225 /* The thing to do here is force it to ABSOLUTE LONG, since
5226 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5227 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5228 abort ();
5229 fragP->fr_opcode[1] &= ~0x3F;
5230 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
5231 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5232 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5233 fragP->fr_fix += 4;
5234 break;
5235 }
5236 if (fixP)
5237 {
5238 fixP->fx_file = fragP->fr_file;
5239 fixP->fx_line = fragP->fr_line;
5240 }
5241 }
5242
5243 void
5244 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5245 segT sec ATTRIBUTE_UNUSED,
5246 fragS *fragP)
5247 {
5248 md_convert_frag_1 (fragP);
5249 }
5250
5251 /* Force truly undefined symbols to their maximum size, and generally set up
5252 the frag list to be relaxed
5253 */
5254 int
5255 md_estimate_size_before_relax (fragS *fragP, segT segment)
5256 {
5257 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5258 switch (fragP->fr_subtype)
5259 {
5260 case TAB (BRANCHBWL, SZ_UNDEF):
5261 case TAB (BRANCHBWPL, SZ_UNDEF):
5262 case TAB (BRABSJUNC, SZ_UNDEF):
5263 case TAB (BRABSJCOND, SZ_UNDEF):
5264 {
5265 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5266 && relaxable_symbol (fragP->fr_symbol))
5267 {
5268 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5269 }
5270 else if (flag_short_refs)
5271 {
5272 /* Symbol is undefined and we want short ref. */
5273 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5274 }
5275 else
5276 {
5277 /* Symbol is still undefined. Make it LONG. */
5278 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5279 }
5280 break;
5281 }
5282
5283 case TAB (BRANCHBW, SZ_UNDEF):
5284 {
5285 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5286 && relaxable_symbol (fragP->fr_symbol))
5287 {
5288 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5289 }
5290 else
5291 {
5292 /* Symbol is undefined and we don't have long branches. */
5293 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5294 }
5295 break;
5296 }
5297
5298 case TAB (FBRANCH, SZ_UNDEF):
5299 case TAB (DBCCLBR, SZ_UNDEF):
5300 case TAB (DBCCABSJ, SZ_UNDEF):
5301 case TAB (PCREL1632, SZ_UNDEF):
5302 {
5303 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5304 && relaxable_symbol (fragP->fr_symbol))
5305 || flag_short_refs)
5306 {
5307 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5308 }
5309 else
5310 {
5311 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5312 }
5313 break;
5314 }
5315
5316 case TAB (PCINDEX, SZ_UNDEF):
5317 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5318 && relaxable_symbol (fragP->fr_symbol)))
5319 {
5320 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5321 }
5322 else
5323 {
5324 fragP->fr_subtype = TAB (PCINDEX, LONG);
5325 }
5326 break;
5327
5328 case TAB (ABSTOPCREL, SZ_UNDEF):
5329 {
5330 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5331 && relaxable_symbol (fragP->fr_symbol)))
5332 {
5333 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5334 }
5335 else
5336 {
5337 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5338 }
5339 break;
5340 }
5341
5342 default:
5343 break;
5344 }
5345
5346 /* Now that SZ_UNDEF are taken care of, check others. */
5347 switch (fragP->fr_subtype)
5348 {
5349 case TAB (BRANCHBWL, BYTE):
5350 case TAB (BRABSJUNC, BYTE):
5351 case TAB (BRABSJCOND, BYTE):
5352 case TAB (BRANCHBW, BYTE):
5353 /* We can't do a short jump to the next instruction, so in that
5354 case we force word mode. If the symbol is at the start of a
5355 frag, and it is the next frag with any data in it (usually
5356 this is just the next frag, but assembler listings may
5357 introduce empty frags), we must use word mode. */
5358 if (fragP->fr_symbol)
5359 {
5360 fragS *sym_frag;
5361
5362 sym_frag = symbol_get_frag (fragP->fr_symbol);
5363 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5364 {
5365 fragS *l;
5366
5367 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5368 if (l->fr_fix != 0)
5369 break;
5370 if (l == sym_frag)
5371 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5372 }
5373 }
5374 break;
5375 default:
5376 break;
5377 }
5378 return md_relax_table[fragP->fr_subtype].rlx_length;
5379 }
5380
5381 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5382 /* the bit-field entries in the relocation_info struct plays hell
5383 with the byte-order problems of cross-assembly. So as a hack,
5384 I added this mach. dependent ri twiddler. Ugly, but it gets
5385 you there. -KWK */
5386 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5387 are symbolnum, most sig. byte first. Last byte is broken up with
5388 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5389 nibble as nuthin. (on Sun 3 at least) */
5390 /* Translate the internal relocation information into target-specific
5391 format. */
5392 #ifdef comment
5393 void
5394 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5395 {
5396 /* This is easy. */
5397 md_number_to_chars (the_bytes, ri->r_address, 4);
5398 /* Now the fun stuff. */
5399 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5400 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5401 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5402 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5403 | ((ri->r_length << 5) & 0x60)
5404 | ((ri->r_extern << 4) & 0x10));
5405 }
5406
5407 #endif
5408
5409 #endif /* OBJ_AOUT or OBJ_BOUT */
5410
5411 #ifndef WORKING_DOT_WORD
5412 int md_short_jump_size = 4;
5413 int md_long_jump_size = 6;
5414
5415 void
5416 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5417 fragS *frag ATTRIBUTE_UNUSED,
5418 symbolS *to_symbol ATTRIBUTE_UNUSED)
5419 {
5420 valueT offset;
5421
5422 offset = to_addr - (from_addr + 2);
5423
5424 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5425 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5426 }
5427
5428 void
5429 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5430 fragS *frag, symbolS *to_symbol)
5431 {
5432 valueT offset;
5433
5434 if (!HAVE_LONG_BRANCH (current_architecture))
5435 {
5436 if (flag_keep_pcrel)
5437 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5438 offset = to_addr - S_GET_VALUE (to_symbol);
5439 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5440 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5441 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5442 0, NO_RELOC);
5443 }
5444 else
5445 {
5446 offset = to_addr - (from_addr + 2);
5447 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5448 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5449 }
5450 }
5451
5452 #endif
5453
5454 /* Different values of OK tell what its OK to return. Things that
5455 aren't OK are an error (what a shock, no?)
5456
5457 0: Everything is OK
5458 10: Absolute 1:8 only
5459 20: Absolute 0:7 only
5460 30: absolute 0:15 only
5461 40: Absolute 0:31 only
5462 50: absolute 0:127 only
5463 55: absolute -64:63 only
5464 60: absolute -128:127 only
5465 65: absolute 0:511 only
5466 70: absolute 0:4095 only
5467 80: absolute -1, 1:7 only
5468 90: No bignums. */
5469
5470 static int
5471 get_num (struct m68k_exp *exp, int ok)
5472 {
5473 if (exp->exp.X_op == O_absent)
5474 {
5475 /* Do the same thing the VAX asm does. */
5476 op (exp) = O_constant;
5477 adds (exp) = 0;
5478 subs (exp) = 0;
5479 offs (exp) = 0;
5480 if (ok == 10)
5481 {
5482 as_warn (_("expression out of range: defaulting to 1"));
5483 offs (exp) = 1;
5484 }
5485 }
5486 else if (exp->exp.X_op == O_constant)
5487 {
5488 switch (ok)
5489 {
5490 case 10:
5491 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5492 {
5493 as_warn (_("expression out of range: defaulting to 1"));
5494 offs (exp) = 1;
5495 }
5496 break;
5497 case 20:
5498 if ((valueT) TRUNC (offs (exp)) > 7)
5499 goto outrange;
5500 break;
5501 case 30:
5502 if ((valueT) TRUNC (offs (exp)) > 15)
5503 goto outrange;
5504 break;
5505 case 40:
5506 if ((valueT) TRUNC (offs (exp)) > 32)
5507 goto outrange;
5508 break;
5509 case 50:
5510 if ((valueT) TRUNC (offs (exp)) > 127)
5511 goto outrange;
5512 break;
5513 case 55:
5514 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5515 goto outrange;
5516 break;
5517 case 60:
5518 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5519 goto outrange;
5520 break;
5521 case 65:
5522 if ((valueT) TRUNC (offs (exp)) > 511)
5523 goto outrange;
5524 break;
5525 case 70:
5526 if ((valueT) TRUNC (offs (exp)) > 4095)
5527 {
5528 outrange:
5529 as_warn (_("expression out of range: defaulting to 0"));
5530 offs (exp) = 0;
5531 }
5532 break;
5533 case 80:
5534 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5535 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5536 {
5537 as_warn (_("expression out of range: defaulting to 1"));
5538 offs (exp) = 1;
5539 }
5540 break;
5541 default:
5542 break;
5543 }
5544 }
5545 else if (exp->exp.X_op == O_big)
5546 {
5547 if (offs (exp) <= 0 /* flonum. */
5548 && (ok == 90 /* no bignums */
5549 || (ok > 10 /* Small-int ranges including 0 ok. */
5550 /* If we have a flonum zero, a zero integer should
5551 do as well (e.g., in moveq). */
5552 && generic_floating_point_number.exponent == 0
5553 && generic_floating_point_number.low[0] == 0)))
5554 {
5555 /* HACK! Turn it into a long. */
5556 LITTLENUM_TYPE words[6];
5557
5558 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5559 op (exp) = O_constant;
5560 adds (exp) = 0;
5561 subs (exp) = 0;
5562 offs (exp) = words[1] | (words[0] << 16);
5563 }
5564 else if (ok != 0)
5565 {
5566 op (exp) = O_constant;
5567 adds (exp) = 0;
5568 subs (exp) = 0;
5569 offs (exp) = (ok == 10) ? 1 : 0;
5570 as_warn (_("Can't deal with expression; defaulting to %ld"),
5571 (long) offs (exp));
5572 }
5573 }
5574 else
5575 {
5576 if (ok >= 10 && ok <= 80)
5577 {
5578 op (exp) = O_constant;
5579 adds (exp) = 0;
5580 subs (exp) = 0;
5581 offs (exp) = (ok == 10) ? 1 : 0;
5582 as_warn (_("Can't deal with expression; defaulting to %ld"),
5583 (long) offs (exp));
5584 }
5585 }
5586
5587 if (exp->size != SIZE_UNSPEC)
5588 {
5589 switch (exp->size)
5590 {
5591 case SIZE_UNSPEC:
5592 case SIZE_LONG:
5593 break;
5594 case SIZE_BYTE:
5595 if (!isbyte (offs (exp)))
5596 as_warn (_("expression doesn't fit in BYTE"));
5597 break;
5598 case SIZE_WORD:
5599 if (!isword (offs (exp)))
5600 as_warn (_("expression doesn't fit in WORD"));
5601 break;
5602 }
5603 }
5604
5605 return offs (exp);
5606 }
5607
5608 /* These are the back-ends for the various machine dependent pseudo-ops. */
5609
5610 static void
5611 s_data1 (int ignore ATTRIBUTE_UNUSED)
5612 {
5613 subseg_set (data_section, 1);
5614 demand_empty_rest_of_line ();
5615 }
5616
5617 static void
5618 s_data2 (int ignore ATTRIBUTE_UNUSED)
5619 {
5620 subseg_set (data_section, 2);
5621 demand_empty_rest_of_line ();
5622 }
5623
5624 static void
5625 s_bss (int ignore ATTRIBUTE_UNUSED)
5626 {
5627 /* We don't support putting frags in the BSS segment, we fake it
5628 by marking in_bss, then looking at s_skip for clues. */
5629
5630 subseg_set (bss_section, 0);
5631 demand_empty_rest_of_line ();
5632 }
5633
5634 static void
5635 s_even (int ignore ATTRIBUTE_UNUSED)
5636 {
5637 register int temp;
5638 register long temp_fill;
5639
5640 temp = 1; /* JF should be 2? */
5641 temp_fill = get_absolute_expression ();
5642 if (!need_pass_2) /* Never make frag if expect extra pass. */
5643 frag_align (temp, (int) temp_fill, 0);
5644 demand_empty_rest_of_line ();
5645 record_alignment (now_seg, temp);
5646 }
5647
5648 static void
5649 s_proc (int ignore ATTRIBUTE_UNUSED)
5650 {
5651 demand_empty_rest_of_line ();
5652 }
5653 \f
5654 /* Pseudo-ops handled for MRI compatibility. */
5655
5656 /* This function returns non-zero if the argument is a conditional
5657 pseudo-op. This is called when checking whether a pending
5658 alignment is needed. */
5659
5660 int
5661 m68k_conditional_pseudoop (pseudo_typeS *pop)
5662 {
5663 return (pop->poc_handler == s_mri_if
5664 || pop->poc_handler == s_mri_else);
5665 }
5666
5667 /* Handle an MRI style chip specification. */
5668
5669 static void
5670 mri_chip (void)
5671 {
5672 char *s;
5673 char c;
5674 int i;
5675
5676 s = input_line_pointer;
5677 /* We can't use get_symbol_end since the processor names are not proper
5678 symbols. */
5679 while (is_part_of_name (c = *input_line_pointer++))
5680 ;
5681 *--input_line_pointer = 0;
5682 for (i = 0; m68k_cpus[i].name; i++)
5683 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5684 break;
5685 if (!m68k_cpus[i].name)
5686 {
5687 as_bad (_("%s: unrecognized processor name"), s);
5688 *input_line_pointer = c;
5689 ignore_rest_of_line ();
5690 return;
5691 }
5692 *input_line_pointer = c;
5693
5694 if (*input_line_pointer == '/')
5695 current_architecture = 0;
5696 else
5697 current_architecture &= m68881 | m68851;
5698 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5699 control_regs = m68k_cpus[i].control_regs;
5700
5701 while (*input_line_pointer == '/')
5702 {
5703 ++input_line_pointer;
5704 s = input_line_pointer;
5705 /* We can't use get_symbol_end since the processor names are not
5706 proper symbols. */
5707 while (is_part_of_name (c = *input_line_pointer++))
5708 ;
5709 *--input_line_pointer = 0;
5710 if (strcmp (s, "68881") == 0)
5711 current_architecture |= m68881;
5712 else if (strcmp (s, "68851") == 0)
5713 current_architecture |= m68851;
5714 *input_line_pointer = c;
5715 }
5716 }
5717
5718 /* The MRI CHIP pseudo-op. */
5719
5720 static void
5721 s_chip (int ignore ATTRIBUTE_UNUSED)
5722 {
5723 char *stop = NULL;
5724 char stopc;
5725
5726 if (flag_mri)
5727 stop = mri_comment_field (&stopc);
5728 mri_chip ();
5729 if (flag_mri)
5730 mri_comment_end (stop, stopc);
5731 demand_empty_rest_of_line ();
5732 }
5733
5734 /* The MRI FOPT pseudo-op. */
5735
5736 static void
5737 s_fopt (int ignore ATTRIBUTE_UNUSED)
5738 {
5739 SKIP_WHITESPACE ();
5740
5741 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5742 {
5743 int temp;
5744
5745 input_line_pointer += 3;
5746 temp = get_absolute_expression ();
5747 if (temp < 0 || temp > 7)
5748 as_bad (_("bad coprocessor id"));
5749 else
5750 m68k_float_copnum = COP0 + temp;
5751 }
5752 else
5753 {
5754 as_bad (_("unrecognized fopt option"));
5755 ignore_rest_of_line ();
5756 return;
5757 }
5758
5759 demand_empty_rest_of_line ();
5760 }
5761
5762 /* The structure used to handle the MRI OPT pseudo-op. */
5763
5764 struct opt_action
5765 {
5766 /* The name of the option. */
5767 const char *name;
5768
5769 /* If this is not NULL, just call this function. The first argument
5770 is the ARG field of this structure, the second argument is
5771 whether the option was negated. */
5772 void (*pfn) (int arg, int on);
5773
5774 /* If this is not NULL, and the PFN field is NULL, set the variable
5775 this points to. Set it to the ARG field if the option was not
5776 negated, and the NOTARG field otherwise. */
5777 int *pvar;
5778
5779 /* The value to pass to PFN or to assign to *PVAR. */
5780 int arg;
5781
5782 /* The value to assign to *PVAR if the option is negated. If PFN is
5783 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5784 the option may not be negated. */
5785 int notarg;
5786 };
5787
5788 /* The table used to handle the MRI OPT pseudo-op. */
5789
5790 static void skip_to_comma (int, int);
5791 static void opt_nest (int, int);
5792 static void opt_chip (int, int);
5793 static void opt_list (int, int);
5794 static void opt_list_symbols (int, int);
5795
5796 static const struct opt_action opt_table[] =
5797 {
5798 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5799
5800 /* We do relaxing, so there is little use for these options. */
5801 { "b", 0, 0, 0, 0 },
5802 { "brs", 0, 0, 0, 0 },
5803 { "brb", 0, 0, 0, 0 },
5804 { "brl", 0, 0, 0, 0 },
5805 { "brw", 0, 0, 0, 0 },
5806
5807 { "c", 0, 0, 0, 0 },
5808 { "cex", 0, 0, 0, 0 },
5809 { "case", 0, &symbols_case_sensitive, 1, 0 },
5810 { "cl", 0, 0, 0, 0 },
5811 { "cre", 0, 0, 0, 0 },
5812 { "d", 0, &flag_keep_locals, 1, 0 },
5813 { "e", 0, 0, 0, 0 },
5814 { "f", 0, &flag_short_refs, 1, 0 },
5815 { "frs", 0, &flag_short_refs, 1, 0 },
5816 { "frl", 0, &flag_short_refs, 0, 1 },
5817 { "g", 0, 0, 0, 0 },
5818 { "i", 0, 0, 0, 0 },
5819 { "m", 0, 0, 0, 0 },
5820 { "mex", 0, 0, 0, 0 },
5821 { "mc", 0, 0, 0, 0 },
5822 { "md", 0, 0, 0, 0 },
5823 { "nest", opt_nest, 0, 0, 0 },
5824 { "next", skip_to_comma, 0, 0, 0 },
5825 { "o", 0, 0, 0, 0 },
5826 { "old", 0, 0, 0, 0 },
5827 { "op", skip_to_comma, 0, 0, 0 },
5828 { "pco", 0, 0, 0, 0 },
5829 { "p", opt_chip, 0, 0, 0 },
5830 { "pcr", 0, 0, 0, 0 },
5831 { "pcs", 0, 0, 0, 0 },
5832 { "r", 0, 0, 0, 0 },
5833 { "quick", 0, &m68k_quick, 1, 0 },
5834 { "rel32", 0, &m68k_rel32, 1, 0 },
5835 { "s", opt_list, 0, 0, 0 },
5836 { "t", opt_list_symbols, 0, 0, 0 },
5837 { "w", 0, &flag_no_warnings, 0, 1 },
5838 { "x", 0, 0, 0, 0 }
5839 };
5840
5841 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5842
5843 /* The MRI OPT pseudo-op. */
5844
5845 static void
5846 s_opt (int ignore ATTRIBUTE_UNUSED)
5847 {
5848 do
5849 {
5850 int t;
5851 char *s;
5852 char c;
5853 int i;
5854 const struct opt_action *o;
5855
5856 SKIP_WHITESPACE ();
5857
5858 t = 1;
5859 if (*input_line_pointer == '-')
5860 {
5861 ++input_line_pointer;
5862 t = 0;
5863 }
5864 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5865 {
5866 input_line_pointer += 2;
5867 t = 0;
5868 }
5869
5870 s = input_line_pointer;
5871 c = get_symbol_end ();
5872
5873 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5874 {
5875 if (strcasecmp (s, o->name) == 0)
5876 {
5877 if (o->pfn)
5878 {
5879 /* Restore input_line_pointer now in case the option
5880 takes arguments. */
5881 *input_line_pointer = c;
5882 (*o->pfn) (o->arg, t);
5883 }
5884 else if (o->pvar != NULL)
5885 {
5886 if (! t && o->arg == o->notarg)
5887 as_bad (_("option `%s' may not be negated"), s);
5888 *input_line_pointer = c;
5889 *o->pvar = t ? o->arg : o->notarg;
5890 }
5891 else
5892 *input_line_pointer = c;
5893 break;
5894 }
5895 }
5896 if (i >= OPTCOUNT)
5897 {
5898 as_bad (_("option `%s' not recognized"), s);
5899 *input_line_pointer = c;
5900 }
5901 }
5902 while (*input_line_pointer++ == ',');
5903
5904 /* Move back to terminating character. */
5905 --input_line_pointer;
5906 demand_empty_rest_of_line ();
5907 }
5908
5909 /* Skip ahead to a comma. This is used for OPT options which we do
5910 not support and which take arguments. */
5911
5912 static void
5913 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5914 {
5915 while (*input_line_pointer != ','
5916 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5917 ++input_line_pointer;
5918 }
5919
5920 /* Handle the OPT NEST=depth option. */
5921
5922 static void
5923 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5924 {
5925 if (*input_line_pointer != '=')
5926 {
5927 as_bad (_("bad format of OPT NEST=depth"));
5928 return;
5929 }
5930
5931 ++input_line_pointer;
5932 max_macro_nest = get_absolute_expression ();
5933 }
5934
5935 /* Handle the OPT P=chip option. */
5936
5937 static void
5938 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5939 {
5940 if (*input_line_pointer != '=')
5941 {
5942 /* This is just OPT P, which we do not support. */
5943 return;
5944 }
5945
5946 ++input_line_pointer;
5947 mri_chip ();
5948 }
5949
5950 /* Handle the OPT S option. */
5951
5952 static void
5953 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5954 {
5955 listing_list (on);
5956 }
5957
5958 /* Handle the OPT T option. */
5959
5960 static void
5961 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5962 {
5963 if (on)
5964 listing |= LISTING_SYMBOLS;
5965 else
5966 listing &= ~LISTING_SYMBOLS;
5967 }
5968
5969 /* Handle the MRI REG pseudo-op. */
5970
5971 static void
5972 s_reg (int ignore ATTRIBUTE_UNUSED)
5973 {
5974 char *s;
5975 int c;
5976 struct m68k_op rop;
5977 int mask;
5978 char *stop = NULL;
5979 char stopc;
5980
5981 if (line_label == NULL)
5982 {
5983 as_bad (_("missing label"));
5984 ignore_rest_of_line ();
5985 return;
5986 }
5987
5988 if (flag_mri)
5989 stop = mri_comment_field (&stopc);
5990
5991 SKIP_WHITESPACE ();
5992
5993 s = input_line_pointer;
5994 while (ISALNUM (*input_line_pointer)
5995 #ifdef REGISTER_PREFIX
5996 || *input_line_pointer == REGISTER_PREFIX
5997 #endif
5998 || *input_line_pointer == '/'
5999 || *input_line_pointer == '-')
6000 ++input_line_pointer;
6001 c = *input_line_pointer;
6002 *input_line_pointer = '\0';
6003
6004 if (m68k_ip_op (s, &rop) != 0)
6005 {
6006 if (rop.error == NULL)
6007 as_bad (_("bad register list"));
6008 else
6009 as_bad (_("bad register list: %s"), rop.error);
6010 *input_line_pointer = c;
6011 ignore_rest_of_line ();
6012 return;
6013 }
6014
6015 *input_line_pointer = c;
6016
6017 if (rop.mode == REGLST)
6018 mask = rop.mask;
6019 else if (rop.mode == DREG)
6020 mask = 1 << (rop.reg - DATA0);
6021 else if (rop.mode == AREG)
6022 mask = 1 << (rop.reg - ADDR0 + 8);
6023 else if (rop.mode == FPREG)
6024 mask = 1 << (rop.reg - FP0 + 16);
6025 else if (rop.mode == CONTROL
6026 && rop.reg == FPI)
6027 mask = 1 << 24;
6028 else if (rop.mode == CONTROL
6029 && rop.reg == FPS)
6030 mask = 1 << 25;
6031 else if (rop.mode == CONTROL
6032 && rop.reg == FPC)
6033 mask = 1 << 26;
6034 else
6035 {
6036 as_bad (_("bad register list"));
6037 ignore_rest_of_line ();
6038 return;
6039 }
6040
6041 S_SET_SEGMENT (line_label, reg_section);
6042 S_SET_VALUE (line_label, ~mask);
6043 symbol_set_frag (line_label, &zero_address_frag);
6044
6045 if (flag_mri)
6046 mri_comment_end (stop, stopc);
6047
6048 demand_empty_rest_of_line ();
6049 }
6050
6051 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
6052
6053 struct save_opts
6054 {
6055 struct save_opts *next;
6056 int abspcadd;
6057 int symbols_case_sensitive;
6058 int keep_locals;
6059 int short_refs;
6060 int architecture;
6061 const enum m68k_register *control_regs;
6062 int quick;
6063 int rel32;
6064 int listing;
6065 int no_warnings;
6066 /* FIXME: We don't save OPT S. */
6067 };
6068
6069 /* This variable holds the stack of saved options. */
6070
6071 static struct save_opts *save_stack;
6072
6073 /* The MRI SAVE pseudo-op. */
6074
6075 static void
6076 s_save (int ignore ATTRIBUTE_UNUSED)
6077 {
6078 struct save_opts *s;
6079
6080 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
6081 s->abspcadd = m68k_abspcadd;
6082 s->symbols_case_sensitive = symbols_case_sensitive;
6083 s->keep_locals = flag_keep_locals;
6084 s->short_refs = flag_short_refs;
6085 s->architecture = current_architecture;
6086 s->control_regs = control_regs;
6087 s->quick = m68k_quick;
6088 s->rel32 = m68k_rel32;
6089 s->listing = listing;
6090 s->no_warnings = flag_no_warnings;
6091
6092 s->next = save_stack;
6093 save_stack = s;
6094
6095 demand_empty_rest_of_line ();
6096 }
6097
6098 /* The MRI RESTORE pseudo-op. */
6099
6100 static void
6101 s_restore (int ignore ATTRIBUTE_UNUSED)
6102 {
6103 struct save_opts *s;
6104
6105 if (save_stack == NULL)
6106 {
6107 as_bad (_("restore without save"));
6108 ignore_rest_of_line ();
6109 return;
6110 }
6111
6112 s = save_stack;
6113 save_stack = s->next;
6114
6115 m68k_abspcadd = s->abspcadd;
6116 symbols_case_sensitive = s->symbols_case_sensitive;
6117 flag_keep_locals = s->keep_locals;
6118 flag_short_refs = s->short_refs;
6119 current_architecture = s->architecture;
6120 control_regs = s->control_regs;
6121 m68k_quick = s->quick;
6122 m68k_rel32 = s->rel32;
6123 listing = s->listing;
6124 flag_no_warnings = s->no_warnings;
6125
6126 free (s);
6127
6128 demand_empty_rest_of_line ();
6129 }
6130
6131 /* Types of MRI structured control directives. */
6132
6133 enum mri_control_type
6134 {
6135 mri_for,
6136 mri_if,
6137 mri_repeat,
6138 mri_while
6139 };
6140
6141 /* This structure is used to stack the MRI structured control
6142 directives. */
6143
6144 struct mri_control_info
6145 {
6146 /* The directive within which this one is enclosed. */
6147 struct mri_control_info *outer;
6148
6149 /* The type of directive. */
6150 enum mri_control_type type;
6151
6152 /* Whether an ELSE has been in an IF. */
6153 int else_seen;
6154
6155 /* The add or sub statement at the end of a FOR. */
6156 char *incr;
6157
6158 /* The label of the top of a FOR or REPEAT loop. */
6159 char *top;
6160
6161 /* The label to jump to for the next iteration, or the else
6162 expression of a conditional. */
6163 char *next;
6164
6165 /* The label to jump to to break out of the loop, or the label past
6166 the end of a conditional. */
6167 char *bottom;
6168 };
6169
6170 /* The stack of MRI structured control directives. */
6171
6172 static struct mri_control_info *mri_control_stack;
6173
6174 /* The current MRI structured control directive index number, used to
6175 generate label names. */
6176
6177 static int mri_control_index;
6178
6179 /* Assemble an instruction for an MRI structured control directive. */
6180
6181 static void
6182 mri_assemble (char *str)
6183 {
6184 char *s;
6185
6186 /* md_assemble expects the opcode to be in lower case. */
6187 for (s = str; *s != ' ' && *s != '\0'; s++)
6188 *s = TOLOWER (*s);
6189
6190 md_assemble (str);
6191 }
6192
6193 /* Generate a new MRI label structured control directive label name. */
6194
6195 static char *
6196 mri_control_label (void)
6197 {
6198 char *n;
6199
6200 n = (char *) xmalloc (20);
6201 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6202 ++mri_control_index;
6203 return n;
6204 }
6205
6206 /* Create a new MRI structured control directive. */
6207
6208 static struct mri_control_info *
6209 push_mri_control (enum mri_control_type type)
6210 {
6211 struct mri_control_info *n;
6212
6213 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6214
6215 n->type = type;
6216 n->else_seen = 0;
6217 if (type == mri_if || type == mri_while)
6218 n->top = NULL;
6219 else
6220 n->top = mri_control_label ();
6221 n->next = mri_control_label ();
6222 n->bottom = mri_control_label ();
6223
6224 n->outer = mri_control_stack;
6225 mri_control_stack = n;
6226
6227 return n;
6228 }
6229
6230 /* Pop off the stack of MRI structured control directives. */
6231
6232 static void
6233 pop_mri_control (void)
6234 {
6235 struct mri_control_info *n;
6236
6237 n = mri_control_stack;
6238 mri_control_stack = n->outer;
6239 if (n->top != NULL)
6240 free (n->top);
6241 free (n->next);
6242 free (n->bottom);
6243 free (n);
6244 }
6245
6246 /* Recognize a condition code in an MRI structured control expression. */
6247
6248 static int
6249 parse_mri_condition (int *pcc)
6250 {
6251 char c1, c2;
6252
6253 know (*input_line_pointer == '<');
6254
6255 ++input_line_pointer;
6256 c1 = *input_line_pointer++;
6257 c2 = *input_line_pointer++;
6258
6259 if (*input_line_pointer != '>')
6260 {
6261 as_bad (_("syntax error in structured control directive"));
6262 return 0;
6263 }
6264
6265 ++input_line_pointer;
6266 SKIP_WHITESPACE ();
6267
6268 c1 = TOLOWER (c1);
6269 c2 = TOLOWER (c2);
6270
6271 *pcc = (c1 << 8) | c2;
6272
6273 return 1;
6274 }
6275
6276 /* Parse a single operand in an MRI structured control expression. */
6277
6278 static int
6279 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6280 char **rightstart, char **rightstop)
6281 {
6282 char *s;
6283
6284 SKIP_WHITESPACE ();
6285
6286 *pcc = -1;
6287 *leftstart = NULL;
6288 *leftstop = NULL;
6289 *rightstart = NULL;
6290 *rightstop = NULL;
6291
6292 if (*input_line_pointer == '<')
6293 {
6294 /* It's just a condition code. */
6295 return parse_mri_condition (pcc);
6296 }
6297
6298 /* Look ahead for the condition code. */
6299 for (s = input_line_pointer; *s != '\0'; ++s)
6300 {
6301 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6302 break;
6303 }
6304 if (*s == '\0')
6305 {
6306 as_bad (_("missing condition code in structured control directive"));
6307 return 0;
6308 }
6309
6310 *leftstart = input_line_pointer;
6311 *leftstop = s;
6312 if (*leftstop > *leftstart
6313 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6314 --*leftstop;
6315
6316 input_line_pointer = s;
6317 if (! parse_mri_condition (pcc))
6318 return 0;
6319
6320 /* Look ahead for AND or OR or end of line. */
6321 for (s = input_line_pointer; *s != '\0'; ++s)
6322 {
6323 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6324 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6325 ^^^ ^^ */
6326 if ((s == input_line_pointer
6327 || *(s-1) == ' '
6328 || *(s-1) == '\t')
6329 && ((strncasecmp (s, "AND", 3) == 0
6330 && (s[3] == '.' || ! is_part_of_name (s[3])))
6331 || (strncasecmp (s, "OR", 2) == 0
6332 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6333 break;
6334 }
6335
6336 *rightstart = input_line_pointer;
6337 *rightstop = s;
6338 if (*rightstop > *rightstart
6339 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6340 --*rightstop;
6341
6342 input_line_pointer = s;
6343
6344 return 1;
6345 }
6346
6347 #define MCC(b1, b2) (((b1) << 8) | (b2))
6348
6349 /* Swap the sense of a condition. This changes the condition so that
6350 it generates the same result when the operands are swapped. */
6351
6352 static int
6353 swap_mri_condition (int cc)
6354 {
6355 switch (cc)
6356 {
6357 case MCC ('h', 'i'): return MCC ('c', 's');
6358 case MCC ('l', 's'): return MCC ('c', 'c');
6359 /* <HS> is an alias for <CC>. */
6360 case MCC ('h', 's'):
6361 case MCC ('c', 'c'): return MCC ('l', 's');
6362 /* <LO> is an alias for <CS>. */
6363 case MCC ('l', 'o'):
6364 case MCC ('c', 's'): return MCC ('h', 'i');
6365 case MCC ('p', 'l'): return MCC ('m', 'i');
6366 case MCC ('m', 'i'): return MCC ('p', 'l');
6367 case MCC ('g', 'e'): return MCC ('l', 'e');
6368 case MCC ('l', 't'): return MCC ('g', 't');
6369 case MCC ('g', 't'): return MCC ('l', 't');
6370 case MCC ('l', 'e'): return MCC ('g', 'e');
6371 /* Issue a warning for conditions we can not swap. */
6372 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6373 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
6374 case MCC ('v', 'c'):
6375 case MCC ('v', 's'):
6376 default :
6377 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6378 (char) (cc >> 8), (char) (cc));
6379 break;
6380 }
6381 return cc;
6382 }
6383
6384 /* Reverse the sense of a condition. */
6385
6386 static int
6387 reverse_mri_condition (int cc)
6388 {
6389 switch (cc)
6390 {
6391 case MCC ('h', 'i'): return MCC ('l', 's');
6392 case MCC ('l', 's'): return MCC ('h', 'i');
6393 /* <HS> is an alias for <CC> */
6394 case MCC ('h', 's'): return MCC ('l', 'o');
6395 case MCC ('c', 'c'): return MCC ('c', 's');
6396 /* <LO> is an alias for <CS> */
6397 case MCC ('l', 'o'): return MCC ('h', 's');
6398 case MCC ('c', 's'): return MCC ('c', 'c');
6399 case MCC ('n', 'e'): return MCC ('e', 'q');
6400 case MCC ('e', 'q'): return MCC ('n', 'e');
6401 case MCC ('v', 'c'): return MCC ('v', 's');
6402 case MCC ('v', 's'): return MCC ('v', 'c');
6403 case MCC ('p', 'l'): return MCC ('m', 'i');
6404 case MCC ('m', 'i'): return MCC ('p', 'l');
6405 case MCC ('g', 'e'): return MCC ('l', 't');
6406 case MCC ('l', 't'): return MCC ('g', 'e');
6407 case MCC ('g', 't'): return MCC ('l', 'e');
6408 case MCC ('l', 'e'): return MCC ('g', 't');
6409 }
6410 return cc;
6411 }
6412
6413 /* Build an MRI structured control expression. This generates test
6414 and branch instructions. It goes to TRUELAB if the condition is
6415 true, and to FALSELAB if the condition is false. Exactly one of
6416 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6417 is the size qualifier for the expression. EXTENT is the size to
6418 use for the branch. */
6419
6420 static void
6421 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6422 char *rightstart, char *rightstop,
6423 const char *truelab, const char *falselab,
6424 int extent)
6425 {
6426 char *buf;
6427 char *s;
6428
6429 if (leftstart != NULL)
6430 {
6431 struct m68k_op leftop, rightop;
6432 char c;
6433
6434 /* Swap the compare operands, if necessary, to produce a legal
6435 m68k compare instruction. Comparing a register operand with
6436 a non-register operand requires the register to be on the
6437 right (cmp, cmpa). Comparing an immediate value with
6438 anything requires the immediate value to be on the left
6439 (cmpi). */
6440
6441 c = *leftstop;
6442 *leftstop = '\0';
6443 (void) m68k_ip_op (leftstart, &leftop);
6444 *leftstop = c;
6445
6446 c = *rightstop;
6447 *rightstop = '\0';
6448 (void) m68k_ip_op (rightstart, &rightop);
6449 *rightstop = c;
6450
6451 if (rightop.mode == IMMED
6452 || ((leftop.mode == DREG || leftop.mode == AREG)
6453 && (rightop.mode != DREG && rightop.mode != AREG)))
6454 {
6455 char *temp;
6456
6457 /* Correct conditional handling:
6458 if #1 <lt> d0 then ;means if (1 < d0)
6459 ...
6460 endi
6461
6462 should assemble to:
6463
6464 cmp #1,d0 if we do *not* swap the operands
6465 bgt true we need the swapped condition!
6466 ble false
6467 true:
6468 ...
6469 false:
6470 */
6471 temp = leftstart;
6472 leftstart = rightstart;
6473 rightstart = temp;
6474 temp = leftstop;
6475 leftstop = rightstop;
6476 rightstop = temp;
6477 }
6478 else
6479 {
6480 cc = swap_mri_condition (cc);
6481 }
6482 }
6483
6484 if (truelab == NULL)
6485 {
6486 cc = reverse_mri_condition (cc);
6487 truelab = falselab;
6488 }
6489
6490 if (leftstart != NULL)
6491 {
6492 buf = (char *) xmalloc (20
6493 + (leftstop - leftstart)
6494 + (rightstop - rightstart));
6495 s = buf;
6496 *s++ = 'c';
6497 *s++ = 'm';
6498 *s++ = 'p';
6499 if (qual != '\0')
6500 *s++ = TOLOWER (qual);
6501 *s++ = ' ';
6502 memcpy (s, leftstart, leftstop - leftstart);
6503 s += leftstop - leftstart;
6504 *s++ = ',';
6505 memcpy (s, rightstart, rightstop - rightstart);
6506 s += rightstop - rightstart;
6507 *s = '\0';
6508 mri_assemble (buf);
6509 free (buf);
6510 }
6511
6512 buf = (char *) xmalloc (20 + strlen (truelab));
6513 s = buf;
6514 *s++ = 'b';
6515 *s++ = cc >> 8;
6516 *s++ = cc & 0xff;
6517 if (extent != '\0')
6518 *s++ = TOLOWER (extent);
6519 *s++ = ' ';
6520 strcpy (s, truelab);
6521 mri_assemble (buf);
6522 free (buf);
6523 }
6524
6525 /* Parse an MRI structured control expression. This generates test
6526 and branch instructions. STOP is where the expression ends. It
6527 goes to TRUELAB if the condition is true, and to FALSELAB if the
6528 condition is false. Exactly one of TRUELAB and FALSELAB will be
6529 NULL, meaning to fall through. QUAL is the size qualifier for the
6530 expression. EXTENT is the size to use for the branch. */
6531
6532 static void
6533 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6534 const char *falselab, int extent)
6535 {
6536 int c;
6537 int cc;
6538 char *leftstart;
6539 char *leftstop;
6540 char *rightstart;
6541 char *rightstop;
6542
6543 c = *stop;
6544 *stop = '\0';
6545
6546 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6547 &rightstart, &rightstop))
6548 {
6549 *stop = c;
6550 return;
6551 }
6552
6553 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6554 {
6555 const char *flab;
6556
6557 if (falselab != NULL)
6558 flab = falselab;
6559 else
6560 flab = mri_control_label ();
6561
6562 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6563 rightstop, (const char *) NULL, flab, extent);
6564
6565 input_line_pointer += 3;
6566 if (*input_line_pointer != '.'
6567 || input_line_pointer[1] == '\0')
6568 qual = '\0';
6569 else
6570 {
6571 qual = input_line_pointer[1];
6572 input_line_pointer += 2;
6573 }
6574
6575 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6576 &rightstart, &rightstop))
6577 {
6578 *stop = c;
6579 return;
6580 }
6581
6582 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6583 rightstop, truelab, falselab, extent);
6584
6585 if (falselab == NULL)
6586 colon (flab);
6587 }
6588 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6589 {
6590 const char *tlab;
6591
6592 if (truelab != NULL)
6593 tlab = truelab;
6594 else
6595 tlab = mri_control_label ();
6596
6597 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6598 rightstop, tlab, (const char *) NULL, extent);
6599
6600 input_line_pointer += 2;
6601 if (*input_line_pointer != '.'
6602 || input_line_pointer[1] == '\0')
6603 qual = '\0';
6604 else
6605 {
6606 qual = input_line_pointer[1];
6607 input_line_pointer += 2;
6608 }
6609
6610 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6611 &rightstart, &rightstop))
6612 {
6613 *stop = c;
6614 return;
6615 }
6616
6617 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6618 rightstop, truelab, falselab, extent);
6619
6620 if (truelab == NULL)
6621 colon (tlab);
6622 }
6623 else
6624 {
6625 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6626 rightstop, truelab, falselab, extent);
6627 }
6628
6629 *stop = c;
6630 if (input_line_pointer != stop)
6631 as_bad (_("syntax error in structured control directive"));
6632 }
6633
6634 /* Handle the MRI IF pseudo-op. This may be a structured control
6635 directive, or it may be a regular assembler conditional, depending
6636 on its operands. */
6637
6638 static void
6639 s_mri_if (int qual)
6640 {
6641 char *s;
6642 int c;
6643 struct mri_control_info *n;
6644
6645 /* A structured control directive must end with THEN with an
6646 optional qualifier. */
6647 s = input_line_pointer;
6648 /* We only accept '*' as introduction of comments if preceded by white space
6649 or at first column of a line (I think this can't actually happen here?)
6650 This is important when assembling:
6651 if d0 <ne> 12(a0,d0*2) then
6652 if d0 <ne> #CONST*20 then. */
6653 while (! (is_end_of_line[(unsigned char) *s]
6654 || (flag_mri
6655 && *s == '*'
6656 && (s == input_line_pointer
6657 || *(s-1) == ' '
6658 || *(s-1) == '\t'))))
6659 ++s;
6660 --s;
6661 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6662 --s;
6663
6664 if (s - input_line_pointer > 1
6665 && s[-1] == '.')
6666 s -= 2;
6667
6668 if (s - input_line_pointer < 3
6669 || strncasecmp (s - 3, "THEN", 4) != 0)
6670 {
6671 if (qual != '\0')
6672 {
6673 as_bad (_("missing then"));
6674 ignore_rest_of_line ();
6675 return;
6676 }
6677
6678 /* It's a conditional. */
6679 s_if (O_ne);
6680 return;
6681 }
6682
6683 /* Since this might be a conditional if, this pseudo-op will be
6684 called even if we are supported to be ignoring input. Double
6685 check now. Clobber *input_line_pointer so that ignore_input
6686 thinks that this is not a special pseudo-op. */
6687 c = *input_line_pointer;
6688 *input_line_pointer = 0;
6689 if (ignore_input ())
6690 {
6691 *input_line_pointer = c;
6692 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6693 ++input_line_pointer;
6694 demand_empty_rest_of_line ();
6695 return;
6696 }
6697 *input_line_pointer = c;
6698
6699 n = push_mri_control (mri_if);
6700
6701 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6702 n->next, s[1] == '.' ? s[2] : '\0');
6703
6704 if (s[1] == '.')
6705 input_line_pointer = s + 3;
6706 else
6707 input_line_pointer = s + 1;
6708
6709 if (flag_mri)
6710 {
6711 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6712 ++input_line_pointer;
6713 }
6714
6715 demand_empty_rest_of_line ();
6716 }
6717
6718 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6719 structured IF, associate the ELSE with the IF. Otherwise, assume
6720 it is a conditional else. */
6721
6722 static void
6723 s_mri_else (int qual)
6724 {
6725 int c;
6726 char *buf;
6727 char q[2];
6728
6729 if (qual == '\0'
6730 && (mri_control_stack == NULL
6731 || mri_control_stack->type != mri_if
6732 || mri_control_stack->else_seen))
6733 {
6734 s_else (0);
6735 return;
6736 }
6737
6738 c = *input_line_pointer;
6739 *input_line_pointer = 0;
6740 if (ignore_input ())
6741 {
6742 *input_line_pointer = c;
6743 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6744 ++input_line_pointer;
6745 demand_empty_rest_of_line ();
6746 return;
6747 }
6748 *input_line_pointer = c;
6749
6750 if (mri_control_stack == NULL
6751 || mri_control_stack->type != mri_if
6752 || mri_control_stack->else_seen)
6753 {
6754 as_bad (_("else without matching if"));
6755 ignore_rest_of_line ();
6756 return;
6757 }
6758
6759 mri_control_stack->else_seen = 1;
6760
6761 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6762 q[0] = TOLOWER (qual);
6763 q[1] = '\0';
6764 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6765 mri_assemble (buf);
6766 free (buf);
6767
6768 colon (mri_control_stack->next);
6769
6770 if (flag_mri)
6771 {
6772 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6773 ++input_line_pointer;
6774 }
6775
6776 demand_empty_rest_of_line ();
6777 }
6778
6779 /* Handle the MRI ENDI pseudo-op. */
6780
6781 static void
6782 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6783 {
6784 if (mri_control_stack == NULL
6785 || mri_control_stack->type != mri_if)
6786 {
6787 as_bad (_("endi without matching if"));
6788 ignore_rest_of_line ();
6789 return;
6790 }
6791
6792 /* ignore_input will not return true for ENDI, so we don't need to
6793 worry about checking it again here. */
6794
6795 if (! mri_control_stack->else_seen)
6796 colon (mri_control_stack->next);
6797 colon (mri_control_stack->bottom);
6798
6799 pop_mri_control ();
6800
6801 if (flag_mri)
6802 {
6803 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6804 ++input_line_pointer;
6805 }
6806
6807 demand_empty_rest_of_line ();
6808 }
6809
6810 /* Handle the MRI BREAK pseudo-op. */
6811
6812 static void
6813 s_mri_break (int extent)
6814 {
6815 struct mri_control_info *n;
6816 char *buf;
6817 char ex[2];
6818
6819 n = mri_control_stack;
6820 while (n != NULL
6821 && n->type != mri_for
6822 && n->type != mri_repeat
6823 && n->type != mri_while)
6824 n = n->outer;
6825 if (n == NULL)
6826 {
6827 as_bad (_("break outside of structured loop"));
6828 ignore_rest_of_line ();
6829 return;
6830 }
6831
6832 buf = (char *) xmalloc (20 + strlen (n->bottom));
6833 ex[0] = TOLOWER (extent);
6834 ex[1] = '\0';
6835 sprintf (buf, "bra%s %s", ex, n->bottom);
6836 mri_assemble (buf);
6837 free (buf);
6838
6839 if (flag_mri)
6840 {
6841 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6842 ++input_line_pointer;
6843 }
6844
6845 demand_empty_rest_of_line ();
6846 }
6847
6848 /* Handle the MRI NEXT pseudo-op. */
6849
6850 static void
6851 s_mri_next (int extent)
6852 {
6853 struct mri_control_info *n;
6854 char *buf;
6855 char ex[2];
6856
6857 n = mri_control_stack;
6858 while (n != NULL
6859 && n->type != mri_for
6860 && n->type != mri_repeat
6861 && n->type != mri_while)
6862 n = n->outer;
6863 if (n == NULL)
6864 {
6865 as_bad (_("next outside of structured loop"));
6866 ignore_rest_of_line ();
6867 return;
6868 }
6869
6870 buf = (char *) xmalloc (20 + strlen (n->next));
6871 ex[0] = TOLOWER (extent);
6872 ex[1] = '\0';
6873 sprintf (buf, "bra%s %s", ex, n->next);
6874 mri_assemble (buf);
6875 free (buf);
6876
6877 if (flag_mri)
6878 {
6879 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6880 ++input_line_pointer;
6881 }
6882
6883 demand_empty_rest_of_line ();
6884 }
6885
6886 /* Handle the MRI FOR pseudo-op. */
6887
6888 static void
6889 s_mri_for (int qual)
6890 {
6891 const char *varstart, *varstop;
6892 const char *initstart, *initstop;
6893 const char *endstart, *endstop;
6894 const char *bystart, *bystop;
6895 int up;
6896 int by;
6897 int extent;
6898 struct mri_control_info *n;
6899 char *buf;
6900 char *s;
6901 char ex[2];
6902
6903 /* The syntax is
6904 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6905 */
6906
6907 SKIP_WHITESPACE ();
6908 varstart = input_line_pointer;
6909
6910 /* Look for the '='. */
6911 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6912 && *input_line_pointer != '=')
6913 ++input_line_pointer;
6914 if (*input_line_pointer != '=')
6915 {
6916 as_bad (_("missing ="));
6917 ignore_rest_of_line ();
6918 return;
6919 }
6920
6921 varstop = input_line_pointer;
6922 if (varstop > varstart
6923 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6924 --varstop;
6925
6926 ++input_line_pointer;
6927
6928 initstart = input_line_pointer;
6929
6930 /* Look for TO or DOWNTO. */
6931 up = 1;
6932 initstop = NULL;
6933 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6934 {
6935 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6936 && ! is_part_of_name (input_line_pointer[2]))
6937 {
6938 initstop = input_line_pointer;
6939 input_line_pointer += 2;
6940 break;
6941 }
6942 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6943 && ! is_part_of_name (input_line_pointer[6]))
6944 {
6945 initstop = input_line_pointer;
6946 up = 0;
6947 input_line_pointer += 6;
6948 break;
6949 }
6950 ++input_line_pointer;
6951 }
6952 if (initstop == NULL)
6953 {
6954 as_bad (_("missing to or downto"));
6955 ignore_rest_of_line ();
6956 return;
6957 }
6958 if (initstop > initstart
6959 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6960 --initstop;
6961
6962 SKIP_WHITESPACE ();
6963 endstart = input_line_pointer;
6964
6965 /* Look for BY or DO. */
6966 by = 0;
6967 endstop = NULL;
6968 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6969 {
6970 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6971 && ! is_part_of_name (input_line_pointer[2]))
6972 {
6973 endstop = input_line_pointer;
6974 by = 1;
6975 input_line_pointer += 2;
6976 break;
6977 }
6978 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6979 && (input_line_pointer[2] == '.'
6980 || ! is_part_of_name (input_line_pointer[2])))
6981 {
6982 endstop = input_line_pointer;
6983 input_line_pointer += 2;
6984 break;
6985 }
6986 ++input_line_pointer;
6987 }
6988 if (endstop == NULL)
6989 {
6990 as_bad (_("missing do"));
6991 ignore_rest_of_line ();
6992 return;
6993 }
6994 if (endstop > endstart
6995 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6996 --endstop;
6997
6998 if (! by)
6999 {
7000 bystart = "#1";
7001 bystop = bystart + 2;
7002 }
7003 else
7004 {
7005 SKIP_WHITESPACE ();
7006 bystart = input_line_pointer;
7007
7008 /* Look for DO. */
7009 bystop = NULL;
7010 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7011 {
7012 if (strncasecmp (input_line_pointer, "DO", 2) == 0
7013 && (input_line_pointer[2] == '.'
7014 || ! is_part_of_name (input_line_pointer[2])))
7015 {
7016 bystop = input_line_pointer;
7017 input_line_pointer += 2;
7018 break;
7019 }
7020 ++input_line_pointer;
7021 }
7022 if (bystop == NULL)
7023 {
7024 as_bad (_("missing do"));
7025 ignore_rest_of_line ();
7026 return;
7027 }
7028 if (bystop > bystart
7029 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
7030 --bystop;
7031 }
7032
7033 if (*input_line_pointer != '.')
7034 extent = '\0';
7035 else
7036 {
7037 extent = input_line_pointer[1];
7038 input_line_pointer += 2;
7039 }
7040
7041 /* We have fully parsed the FOR operands. Now build the loop. */
7042 n = push_mri_control (mri_for);
7043
7044 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
7045
7046 /* Move init,var. */
7047 s = buf;
7048 *s++ = 'm';
7049 *s++ = 'o';
7050 *s++ = 'v';
7051 *s++ = 'e';
7052 if (qual != '\0')
7053 *s++ = TOLOWER (qual);
7054 *s++ = ' ';
7055 memcpy (s, initstart, initstop - initstart);
7056 s += initstop - initstart;
7057 *s++ = ',';
7058 memcpy (s, varstart, varstop - varstart);
7059 s += varstop - varstart;
7060 *s = '\0';
7061 mri_assemble (buf);
7062
7063 colon (n->top);
7064
7065 /* cmp end,var. */
7066 s = buf;
7067 *s++ = 'c';
7068 *s++ = 'm';
7069 *s++ = 'p';
7070 if (qual != '\0')
7071 *s++ = TOLOWER (qual);
7072 *s++ = ' ';
7073 memcpy (s, endstart, endstop - endstart);
7074 s += endstop - endstart;
7075 *s++ = ',';
7076 memcpy (s, varstart, varstop - varstart);
7077 s += varstop - varstart;
7078 *s = '\0';
7079 mri_assemble (buf);
7080
7081 /* bcc bottom. */
7082 ex[0] = TOLOWER (extent);
7083 ex[1] = '\0';
7084 if (up)
7085 sprintf (buf, "blt%s %s", ex, n->bottom);
7086 else
7087 sprintf (buf, "bgt%s %s", ex, n->bottom);
7088 mri_assemble (buf);
7089
7090 /* Put together the add or sub instruction used by ENDF. */
7091 s = buf;
7092 if (up)
7093 strcpy (s, "add");
7094 else
7095 strcpy (s, "sub");
7096 s += 3;
7097 if (qual != '\0')
7098 *s++ = TOLOWER (qual);
7099 *s++ = ' ';
7100 memcpy (s, bystart, bystop - bystart);
7101 s += bystop - bystart;
7102 *s++ = ',';
7103 memcpy (s, varstart, varstop - varstart);
7104 s += varstop - varstart;
7105 *s = '\0';
7106 n->incr = buf;
7107
7108 if (flag_mri)
7109 {
7110 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7111 ++input_line_pointer;
7112 }
7113
7114 demand_empty_rest_of_line ();
7115 }
7116
7117 /* Handle the MRI ENDF pseudo-op. */
7118
7119 static void
7120 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
7121 {
7122 if (mri_control_stack == NULL
7123 || mri_control_stack->type != mri_for)
7124 {
7125 as_bad (_("endf without for"));
7126 ignore_rest_of_line ();
7127 return;
7128 }
7129
7130 colon (mri_control_stack->next);
7131
7132 mri_assemble (mri_control_stack->incr);
7133
7134 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
7135 mri_assemble (mri_control_stack->incr);
7136
7137 free (mri_control_stack->incr);
7138
7139 colon (mri_control_stack->bottom);
7140
7141 pop_mri_control ();
7142
7143 if (flag_mri)
7144 {
7145 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7146 ++input_line_pointer;
7147 }
7148
7149 demand_empty_rest_of_line ();
7150 }
7151
7152 /* Handle the MRI REPEAT pseudo-op. */
7153
7154 static void
7155 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
7156 {
7157 struct mri_control_info *n;
7158
7159 n = push_mri_control (mri_repeat);
7160 colon (n->top);
7161 if (flag_mri)
7162 {
7163 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7164 ++input_line_pointer;
7165 }
7166 demand_empty_rest_of_line ();
7167 }
7168
7169 /* Handle the MRI UNTIL pseudo-op. */
7170
7171 static void
7172 s_mri_until (int qual)
7173 {
7174 char *s;
7175
7176 if (mri_control_stack == NULL
7177 || mri_control_stack->type != mri_repeat)
7178 {
7179 as_bad (_("until without repeat"));
7180 ignore_rest_of_line ();
7181 return;
7182 }
7183
7184 colon (mri_control_stack->next);
7185
7186 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7187 ;
7188
7189 parse_mri_control_expression (s, qual, (const char *) NULL,
7190 mri_control_stack->top, '\0');
7191
7192 colon (mri_control_stack->bottom);
7193
7194 input_line_pointer = s;
7195
7196 pop_mri_control ();
7197
7198 if (flag_mri)
7199 {
7200 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7201 ++input_line_pointer;
7202 }
7203
7204 demand_empty_rest_of_line ();
7205 }
7206
7207 /* Handle the MRI WHILE pseudo-op. */
7208
7209 static void
7210 s_mri_while (int qual)
7211 {
7212 char *s;
7213
7214 struct mri_control_info *n;
7215
7216 s = input_line_pointer;
7217 /* We only accept '*' as introduction of comments if preceded by white space
7218 or at first column of a line (I think this can't actually happen here?)
7219 This is important when assembling:
7220 while d0 <ne> 12(a0,d0*2) do
7221 while d0 <ne> #CONST*20 do. */
7222 while (! (is_end_of_line[(unsigned char) *s]
7223 || (flag_mri
7224 && *s == '*'
7225 && (s == input_line_pointer
7226 || *(s-1) == ' '
7227 || *(s-1) == '\t'))))
7228 s++;
7229 --s;
7230 while (*s == ' ' || *s == '\t')
7231 --s;
7232 if (s - input_line_pointer > 1
7233 && s[-1] == '.')
7234 s -= 2;
7235 if (s - input_line_pointer < 2
7236 || strncasecmp (s - 1, "DO", 2) != 0)
7237 {
7238 as_bad (_("missing do"));
7239 ignore_rest_of_line ();
7240 return;
7241 }
7242
7243 n = push_mri_control (mri_while);
7244
7245 colon (n->next);
7246
7247 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7248 s[1] == '.' ? s[2] : '\0');
7249
7250 input_line_pointer = s + 1;
7251 if (*input_line_pointer == '.')
7252 input_line_pointer += 2;
7253
7254 if (flag_mri)
7255 {
7256 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7257 ++input_line_pointer;
7258 }
7259
7260 demand_empty_rest_of_line ();
7261 }
7262
7263 /* Handle the MRI ENDW pseudo-op. */
7264
7265 static void
7266 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7267 {
7268 char *buf;
7269
7270 if (mri_control_stack == NULL
7271 || mri_control_stack->type != mri_while)
7272 {
7273 as_bad (_("endw without while"));
7274 ignore_rest_of_line ();
7275 return;
7276 }
7277
7278 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7279 sprintf (buf, "bra %s", mri_control_stack->next);
7280 mri_assemble (buf);
7281 free (buf);
7282
7283 colon (mri_control_stack->bottom);
7284
7285 pop_mri_control ();
7286
7287 if (flag_mri)
7288 {
7289 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7290 ++input_line_pointer;
7291 }
7292
7293 demand_empty_rest_of_line ();
7294 }
7295 \f
7296 /* Parse a .cpu directive. */
7297
7298 static void
7299 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7300 {
7301 char saved_char;
7302 char *name;
7303
7304 if (initialized)
7305 {
7306 as_bad (_("already assembled instructions"));
7307 ignore_rest_of_line ();
7308 return;
7309 }
7310
7311 name = input_line_pointer;
7312 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7313 input_line_pointer++;
7314 saved_char = *input_line_pointer;
7315 *input_line_pointer = 0;
7316
7317 m68k_set_cpu (name, 1, 0);
7318
7319 *input_line_pointer = saved_char;
7320 demand_empty_rest_of_line ();
7321 return;
7322 }
7323
7324 /* Parse a .arch directive. */
7325
7326 static void
7327 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7328 {
7329 char saved_char;
7330 char *name;
7331
7332 if (initialized)
7333 {
7334 as_bad (_("already assembled instructions"));
7335 ignore_rest_of_line ();
7336 return;
7337 }
7338
7339 name = input_line_pointer;
7340 while (*input_line_pointer && *input_line_pointer != ','
7341 && !ISSPACE (*input_line_pointer))
7342 input_line_pointer++;
7343 saved_char = *input_line_pointer;
7344 *input_line_pointer = 0;
7345
7346 if (m68k_set_arch (name, 1, 0))
7347 {
7348 /* Scan extensions. */
7349 do
7350 {
7351 *input_line_pointer++ = saved_char;
7352 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7353 break;
7354 name = input_line_pointer;
7355 while (*input_line_pointer && *input_line_pointer != ','
7356 && !ISSPACE (*input_line_pointer))
7357 input_line_pointer++;
7358 saved_char = *input_line_pointer;
7359 *input_line_pointer = 0;
7360 }
7361 while (m68k_set_extension (name, 1, 0));
7362 }
7363
7364 *input_line_pointer = saved_char;
7365 demand_empty_rest_of_line ();
7366 return;
7367 }
7368 \f
7369 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7370 if none is found, the caller is responsible for emitting an error
7371 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7372 cpu name, if it begins with a '6' (possibly skipping an intervening
7373 'c'. We also allow a 'c' in the same place. if NEGATED is
7374 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7375 the option is indeed negated. */
7376
7377 static const struct m68k_cpu *
7378 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7379 int allow_m, int *negated)
7380 {
7381 /* allow negated value? */
7382 if (negated)
7383 {
7384 *negated = 0;
7385
7386 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7387 {
7388 arg += 3;
7389 *negated = 1;
7390 }
7391 }
7392
7393 /* Remove 'm' or 'mc' prefix from 68k variants. */
7394 if (allow_m)
7395 {
7396 if (arg[0] == 'm')
7397 {
7398 if (arg[1] == '6')
7399 arg += 1;
7400 else if (arg[1] == 'c' && arg[2] == '6')
7401 arg += 2;
7402 }
7403 }
7404 else if (arg[0] == 'c' && arg[1] == '6')
7405 arg += 1;
7406
7407 for (; table->name; table++)
7408 if (!strcmp (arg, table->name))
7409 {
7410 if (table->alias < -1 || table->alias > 1)
7411 as_bad (_("`%s' is deprecated, use `%s'"),
7412 table->name, table[table->alias < 0 ? 1 : -1].name);
7413 return table;
7414 }
7415 return 0;
7416 }
7417
7418 /* Set the cpu, issuing errors if it is unrecognized. */
7419
7420 static int
7421 m68k_set_cpu (char const *name, int allow_m, int silent)
7422 {
7423 const struct m68k_cpu *cpu;
7424
7425 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7426
7427 if (!cpu)
7428 {
7429 if (!silent)
7430 as_bad (_("cpu `%s' unrecognized"), name);
7431 return 0;
7432 }
7433 selected_cpu = cpu;
7434 return 1;
7435 }
7436
7437 /* Set the architecture, issuing errors if it is unrecognized. */
7438
7439 static int
7440 m68k_set_arch (char const *name, int allow_m, int silent)
7441 {
7442 const struct m68k_cpu *arch;
7443
7444 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7445
7446 if (!arch)
7447 {
7448 if (!silent)
7449 as_bad (_("architecture `%s' unrecognized"), name);
7450 return 0;
7451 }
7452 selected_arch = arch;
7453 return 1;
7454 }
7455
7456 /* Set the architecture extension, issuing errors if it is
7457 unrecognized, or invalid */
7458
7459 static int
7460 m68k_set_extension (char const *name, int allow_m, int silent)
7461 {
7462 int negated;
7463 const struct m68k_cpu *ext;
7464
7465 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7466
7467 if (!ext)
7468 {
7469 if (!silent)
7470 as_bad (_("extension `%s' unrecognized"), name);
7471 return 0;
7472 }
7473
7474 if (negated)
7475 not_current_architecture |= (ext->control_regs
7476 ? *(unsigned *)ext->control_regs: ext->arch);
7477 else
7478 current_architecture |= ext->arch;
7479 return 1;
7480 }
7481
7482 /* md_parse_option
7483 Invocation line includes a switch not recognized by the base assembler.
7484 */
7485
7486 #ifdef OBJ_ELF
7487 const char *md_shortopts = "lSA:m:kQ:V";
7488 #else
7489 const char *md_shortopts = "lSA:m:k";
7490 #endif
7491
7492 struct option md_longopts[] = {
7493 #define OPTION_PIC (OPTION_MD_BASE)
7494 {"pic", no_argument, NULL, OPTION_PIC},
7495 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7496 {"register-prefix-optional", no_argument, NULL,
7497 OPTION_REGISTER_PREFIX_OPTIONAL},
7498 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7499 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7500 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7501 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7502 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7503 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7504 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7505 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7506 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7507 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7508 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7509 {"pcrel", no_argument, NULL, OPTION_PCREL},
7510 {NULL, no_argument, NULL, 0}
7511 };
7512 size_t md_longopts_size = sizeof (md_longopts);
7513
7514 int
7515 md_parse_option (int c, char *arg)
7516 {
7517 switch (c)
7518 {
7519 case 'l': /* -l means keep external to 2 bit offset
7520 rather than 16 bit one. */
7521 flag_short_refs = 1;
7522 break;
7523
7524 case 'S': /* -S means that jbsr's always turn into
7525 jsr's. */
7526 flag_long_jumps = 1;
7527 break;
7528
7529 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7530 branches into absolute jumps. */
7531 flag_keep_pcrel = 1;
7532 break;
7533
7534 case OPTION_PIC:
7535 case 'k':
7536 flag_want_pic = 1;
7537 break; /* -pic, Position Independent Code. */
7538
7539 case OPTION_REGISTER_PREFIX_OPTIONAL:
7540 flag_reg_prefix_optional = 1;
7541 reg_prefix_optional_seen = 1;
7542 break;
7543
7544 /* -V: SVR4 argument to print version ID. */
7545 case 'V':
7546 print_version_id ();
7547 break;
7548
7549 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7550 should be emitted or not. FIXME: Not implemented. */
7551 case 'Q':
7552 break;
7553
7554 case OPTION_BITWISE_OR:
7555 {
7556 char *n, *t;
7557 const char *s;
7558
7559 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7560 t = n;
7561 for (s = m68k_comment_chars; *s != '\0'; s++)
7562 if (*s != '|')
7563 *t++ = *s;
7564 *t = '\0';
7565 m68k_comment_chars = n;
7566 }
7567 break;
7568
7569 case OPTION_BASE_SIZE_DEFAULT_16:
7570 m68k_index_width_default = SIZE_WORD;
7571 break;
7572
7573 case OPTION_BASE_SIZE_DEFAULT_32:
7574 m68k_index_width_default = SIZE_LONG;
7575 break;
7576
7577 case OPTION_DISP_SIZE_DEFAULT_16:
7578 m68k_rel32 = 0;
7579 m68k_rel32_from_cmdline = 1;
7580 break;
7581
7582 case OPTION_DISP_SIZE_DEFAULT_32:
7583 m68k_rel32 = 1;
7584 m68k_rel32_from_cmdline = 1;
7585 break;
7586
7587 case 'A':
7588 #if WARN_DEPRECATED
7589 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7590 arg, arg));
7591 #endif
7592 /* Intentional fall-through. */
7593 case 'm':
7594 if (!strncmp (arg, "arch=", 5))
7595 m68k_set_arch (arg + 5, 1, 0);
7596 else if (!strncmp (arg, "cpu=", 4))
7597 m68k_set_cpu (arg + 4, 1, 0);
7598 else if (m68k_set_extension (arg, 0, 1))
7599 ;
7600 else if (m68k_set_arch (arg, 0, 1))
7601 ;
7602 else if (m68k_set_cpu (arg, 0, 1))
7603 ;
7604 else
7605 return 0;
7606 break;
7607
7608 default:
7609 return 0;
7610 }
7611
7612 return 1;
7613 }
7614
7615 /* Setup tables from the selected arch and/or cpu */
7616
7617 static void
7618 m68k_init_arch (void)
7619 {
7620 if (not_current_architecture & current_architecture)
7621 {
7622 as_bad (_("architecture features both enabled and disabled"));
7623 not_current_architecture &= ~current_architecture;
7624 }
7625 if (selected_arch)
7626 {
7627 current_architecture |= selected_arch->arch;
7628 control_regs = selected_arch->control_regs;
7629 }
7630 else
7631 current_architecture |= selected_cpu->arch;
7632
7633 current_architecture &= ~not_current_architecture;
7634
7635 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7636 {
7637 /* Determine which float is really meant. */
7638 if (current_architecture & (m68k_mask & ~m68881))
7639 current_architecture ^= cfloat;
7640 else
7641 current_architecture ^= m68881;
7642 }
7643
7644 if (selected_cpu)
7645 {
7646 control_regs = selected_cpu->control_regs;
7647 if (current_architecture & ~selected_cpu->arch)
7648 {
7649 as_bad (_("selected processor does not have all features of selected architecture"));
7650 current_architecture
7651 = selected_cpu->arch & ~not_current_architecture;
7652 }
7653 }
7654
7655 if ((current_architecture & m68k_mask)
7656 && (current_architecture & ~m68k_mask))
7657 {
7658 as_bad (_ ("m68k and cf features both selected"));
7659 if (current_architecture & m68k_mask)
7660 current_architecture &= m68k_mask;
7661 else
7662 current_architecture &= ~m68k_mask;
7663 }
7664
7665 /* Permit m68881 specification with all cpus; those that can't work
7666 with a coprocessor could be doing emulation. */
7667 if (current_architecture & m68851)
7668 {
7669 if (current_architecture & m68040)
7670 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7671 }
7672 /* What other incompatibilities could we check for? */
7673
7674 if (cpu_of_arch (current_architecture) < m68020
7675 || arch_coldfire_p (current_architecture))
7676 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7677
7678 initialized = 1;
7679 }
7680
7681 void
7682 md_show_usage (FILE *stream)
7683 {
7684 const char *default_cpu = TARGET_CPU;
7685 int i;
7686 unsigned int default_arch;
7687
7688 /* Get the canonical name for the default target CPU. */
7689 if (*default_cpu == 'm')
7690 default_cpu++;
7691 for (i = 0; m68k_cpus[i].name; i++)
7692 {
7693 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7694 {
7695 default_arch = m68k_cpus[i].arch;
7696 while (m68k_cpus[i].alias > 0)
7697 i--;
7698 while (m68k_cpus[i].alias < 0)
7699 i++;
7700 default_cpu = m68k_cpus[i].name;
7701 }
7702 }
7703
7704 fprintf (stream, _("\
7705 -march=<arch> set architecture\n\
7706 -mcpu=<cpu> set cpu [default %s]\n\
7707 "), default_cpu);
7708 for (i = 0; m68k_extensions[i].name; i++)
7709 fprintf (stream, _("\
7710 -m[no-]%-16s enable/disable%s architecture extension\n\
7711 "), m68k_extensions[i].name,
7712 m68k_extensions[i].alias > 0 ? " ColdFire"
7713 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7714
7715 fprintf (stream, _("\
7716 -l use 1 word for refs to undefined symbols [default 2]\n\
7717 -pic, -k generate position independent code\n\
7718 -S turn jbsr into jsr\n\
7719 --pcrel never turn PC-relative branches into absolute jumps\n\
7720 --register-prefix-optional\n\
7721 recognize register names without prefix character\n\
7722 --bitwise-or do not treat `|' as a comment character\n\
7723 --base-size-default-16 base reg without size is 16 bits\n\
7724 --base-size-default-32 base reg without size is 32 bits (default)\n\
7725 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7726 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7727 "));
7728
7729 fprintf (stream, _("Architecture variants are: "));
7730 for (i = 0; m68k_archs[i].name; i++)
7731 {
7732 if (i)
7733 fprintf (stream, " | ");
7734 fprintf (stream, "%s", m68k_archs[i].name);
7735 }
7736 fprintf (stream, "\n");
7737
7738 fprintf (stream, _("Processor variants are: "));
7739 for (i = 0; m68k_cpus[i].name; i++)
7740 {
7741 if (i)
7742 fprintf (stream, " | ");
7743 fprintf (stream, "%s", m68k_cpus[i].name);
7744 }
7745 fprintf (stream, _("\n"));
7746 }
7747 \f
7748 #ifdef TEST2
7749
7750 /* TEST2: Test md_assemble() */
7751 /* Warning, this routine probably doesn't work anymore. */
7752 int
7753 main (void)
7754 {
7755 struct m68k_it the_ins;
7756 char buf[120];
7757 char *cp;
7758 int n;
7759
7760 m68k_ip_begin ();
7761 for (;;)
7762 {
7763 if (!gets (buf) || !*buf)
7764 break;
7765 if (buf[0] == '|' || buf[1] == '.')
7766 continue;
7767 for (cp = buf; *cp; cp++)
7768 if (*cp == '\t')
7769 *cp = ' ';
7770 if (is_label (buf))
7771 continue;
7772 memset (&the_ins, '\0', sizeof (the_ins));
7773 m68k_ip (&the_ins, buf);
7774 if (the_ins.error)
7775 {
7776 printf (_("Error %s in %s\n"), the_ins.error, buf);
7777 }
7778 else
7779 {
7780 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7781 for (n = 0; n < the_ins.numo; n++)
7782 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7783 printf (" ");
7784 print_the_insn (&the_ins.opcode[0], stdout);
7785 (void) putchar ('\n');
7786 }
7787 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7788 {
7789 if (the_ins.operands[n].error)
7790 {
7791 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7792 continue;
7793 }
7794 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7795 the_ins.operands[n].reg);
7796 if (the_ins.operands[n].b_const)
7797 printf ("Constant: '%.*s', ",
7798 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7799 the_ins.operands[n].b_const);
7800 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7801 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7802 if (the_ins.operands[n].b_iadd)
7803 printf ("Iadd: '%.*s',",
7804 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7805 the_ins.operands[n].b_iadd);
7806 putchar ('\n');
7807 }
7808 }
7809 m68k_ip_end ();
7810 return 0;
7811 }
7812
7813 int
7814 is_label (char *str)
7815 {
7816 while (*str == ' ')
7817 str++;
7818 while (*str && *str != ' ')
7819 str++;
7820 if (str[-1] == ':' || str[1] == '=')
7821 return 1;
7822 return 0;
7823 }
7824
7825 #endif
7826
7827 /* Possible states for relaxation:
7828
7829 0 0 branch offset byte (bra, etc)
7830 0 1 word
7831 0 2 long
7832
7833 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7834 1 1 word
7835 1 2 long
7836
7837 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7838 2 1 word-long
7839 2 2 long-word
7840 2 3 long-long
7841
7842 */
7843
7844 /* We have no need to default values of symbols. */
7845
7846 symbolS *
7847 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7848 {
7849 return 0;
7850 }
7851
7852 /* Round up a section size to the appropriate boundary. */
7853 valueT
7854 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7855 {
7856 #ifdef OBJ_AOUT
7857 /* For a.out, force the section size to be aligned. If we don't do
7858 this, BFD will align it for us, but it will not write out the
7859 final bytes of the section. This may be a bug in BFD, but it is
7860 easier to fix it here since that is how the other a.out targets
7861 work. */
7862 int align;
7863
7864 align = bfd_get_section_alignment (stdoutput, segment);
7865 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7866 #endif
7867
7868 return size;
7869 }
7870
7871 /* Exactly what point is a PC-relative offset relative TO?
7872 On the 68k, it is relative to the address of the first extension
7873 word. The difference between the addresses of the offset and the
7874 first extension word is stored in fx_pcrel_adjust. */
7875 long
7876 md_pcrel_from (fixS *fixP)
7877 {
7878 int adjust;
7879
7880 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7881 sign extend the value here. */
7882 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7883 if (adjust == 64)
7884 adjust = -1;
7885 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7886 }
7887
7888 #ifdef OBJ_ELF
7889 void
7890 m68k_elf_final_processing (void)
7891 {
7892 unsigned flags = 0;
7893
7894 if (arch_coldfire_fpu (current_architecture))
7895 flags |= EF_M68K_CFV4E;
7896 /* Set file-specific flags if this is a cpu32 processor. */
7897 if (cpu_of_arch (current_architecture) & cpu32)
7898 flags |= EF_M68K_CPU32;
7899 else if (cpu_of_arch (current_architecture) & fido_a)
7900 flags |= EF_M68K_FIDO;
7901 else if ((cpu_of_arch (current_architecture) & m68000up)
7902 && !(cpu_of_arch (current_architecture) & m68020up))
7903 flags |= EF_M68K_M68000;
7904
7905 if (current_architecture & mcfisa_a)
7906 {
7907 static const unsigned isa_features[][2] =
7908 {
7909 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7910 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7911 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7912 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7913 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7914 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7915 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
7916 {0,0},
7917 };
7918 static const unsigned mac_features[][2] =
7919 {
7920 {EF_M68K_CF_MAC, mcfmac},
7921 {EF_M68K_CF_EMAC, mcfemac},
7922 {0,0},
7923 };
7924 unsigned ix;
7925 unsigned pattern;
7926
7927 pattern = (current_architecture
7928 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7929 for (ix = 0; isa_features[ix][1]; ix++)
7930 {
7931 if (pattern == isa_features[ix][1])
7932 {
7933 flags |= isa_features[ix][0];
7934 break;
7935 }
7936 }
7937 if (!isa_features[ix][1])
7938 {
7939 cf_bad:
7940 as_warn (_("Not a defined coldfire architecture"));
7941 }
7942 else
7943 {
7944 if (current_architecture & cfloat)
7945 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7946
7947 pattern = current_architecture & (mcfmac|mcfemac);
7948 if (pattern)
7949 {
7950 for (ix = 0; mac_features[ix][1]; ix++)
7951 {
7952 if (pattern == mac_features[ix][1])
7953 {
7954 flags |= mac_features[ix][0];
7955 break;
7956 }
7957 }
7958 if (!mac_features[ix][1])
7959 goto cf_bad;
7960 }
7961 }
7962 }
7963 elf_elfheader (stdoutput)->e_flags |= flags;
7964 }
7965
7966 /* Parse @TLSLDO and return the desired relocation. */
7967 static bfd_reloc_code_real_type
7968 m68k_elf_suffix (char **str_p, expressionS *exp_p)
7969 {
7970 char ident[20];
7971 char *str = *str_p;
7972 char *str2;
7973 int ch;
7974 int len;
7975
7976 if (*str++ != '@')
7977 return BFD_RELOC_UNUSED;
7978
7979 for (ch = *str, str2 = ident;
7980 (str2 < ident + sizeof (ident) - 1
7981 && (ISALNUM (ch) || ch == '@'));
7982 ch = *++str)
7983 {
7984 *str2++ = ch;
7985 }
7986
7987 *str2 = '\0';
7988 len = str2 - ident;
7989
7990 if (strncmp (ident, "TLSLDO", 6) == 0
7991 && len == 6)
7992 {
7993 /* Now check for identifier@suffix+constant. */
7994 if (*str == '-' || *str == '+')
7995 {
7996 char *orig_line = input_line_pointer;
7997 expressionS new_exp;
7998
7999 input_line_pointer = str;
8000 expression (&new_exp);
8001 if (new_exp.X_op == O_constant)
8002 {
8003 exp_p->X_add_number += new_exp.X_add_number;
8004 str = input_line_pointer;
8005 }
8006
8007 if (&input_line_pointer != str_p)
8008 input_line_pointer = orig_line;
8009 }
8010 *str_p = str;
8011
8012 return BFD_RELOC_68K_TLS_LDO32;
8013 }
8014
8015 return BFD_RELOC_UNUSED;
8016 }
8017
8018 /* Handles .long <tls_symbol>+0x8000 debug info.
8019 Clobbers input_line_pointer, checks end-of-line.
8020 Adapted from tc-ppc.c:ppc_elf_cons. */
8021 static void
8022 m68k_elf_cons (int nbytes /* 4=.long */)
8023 {
8024 if (is_it_end_of_statement ())
8025 {
8026 demand_empty_rest_of_line ();
8027 return;
8028 }
8029
8030 do
8031 {
8032 expressionS exp;
8033 bfd_reloc_code_real_type reloc;
8034
8035 expression (&exp);
8036 if (exp.X_op == O_symbol
8037 && *input_line_pointer == '@'
8038 && (reloc = m68k_elf_suffix (&input_line_pointer,
8039 &exp)) != BFD_RELOC_UNUSED)
8040 {
8041 reloc_howto_type *reloc_howto;
8042 int size;
8043
8044 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
8045 size = bfd_get_reloc_size (reloc_howto);
8046
8047 if (size > nbytes)
8048 {
8049 as_bad (_("%s relocations do not fit in %d bytes\n"),
8050 reloc_howto->name, nbytes);
8051 }
8052 else
8053 {
8054 char *p;
8055 int offset;
8056
8057 p = frag_more (nbytes);
8058 offset = 0;
8059 if (target_big_endian)
8060 offset = nbytes - size;
8061 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
8062 &exp, 0, reloc);
8063 }
8064 }
8065 else
8066 emit_expr (&exp, (unsigned int) nbytes);
8067 }
8068 while (*input_line_pointer++ == ',');
8069
8070 /* Put terminator back into stream. */
8071 input_line_pointer--;
8072 demand_empty_rest_of_line ();
8073 }
8074 #endif
8075
8076 int
8077 tc_m68k_regname_to_dw2regnum (char *regname)
8078 {
8079 unsigned int regnum;
8080 static const char *const regnames[] =
8081 {
8082 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
8083 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
8084 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
8085 "pc"
8086 };
8087
8088 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
8089 if (strcmp (regname, regnames[regnum]) == 0)
8090 return regnum;
8091
8092 return -1;
8093 }
8094
8095 void
8096 tc_m68k_frame_initial_instructions (void)
8097 {
8098 static int sp_regno = -1;
8099
8100 if (sp_regno < 0)
8101 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
8102
8103 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
8104 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
8105 }
GDB Binutils - Deliverables
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