projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Don't explicitly include config.h. Deleted a bunch of "#if 0" code and useless
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* All the m68k specific stuff in one convenient, huge, slow to
2 compile, easy to find file.
3
4 Copyright (C) 1987, 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21
22 #include <ctype.h>
23 #define NO_RELOC 0
24 #include "as.h"
25 #include "obstack.h"
26
27 /* The opcode table is too big for some versions of gcc, which require
28 exponential(?) space at compile time for initialized arrays. */
29 #ifdef __GNUC__
30 #define DO_BREAK_UP_BIG_DECL
31 #define BREAK_UP_BIG_DECL }; struct m68k_opcode m68k_opcodes_2[] = {
32 #define AND_OTHER_PART sizeof (m68k_opcodes_2)
33 #endif
34
35 /* Note that this file includes real declarations and thus can only be
36 included by one source file per executable. */
37 #include "opcode/m68k.h"
38
39 /* This array holds the chars that always start a comment. If the
40 pre-processor is disabled, these aren't very useful */
41 CONST char comment_chars[] = "|";
42
43 /* This array holds the chars that only start a comment at the beginning of
44 a line. If the line seems to have the form '# 123 filename'
45 .line and .file directives will appear in the pre-processed output */
46 /* Note that input_file.c hand checks for '#' at the beginning of the
47 first line of the input file. This is because the compiler outputs
48 #NO_APP at the beginning of its output. */
49 /* Also note that comments like this one will always work. */
50 CONST char line_comment_chars[] = "#";
51
52 CONST char line_separator_chars[] = "";
53
54 /* Chars that can be used to separate mant from exp in floating point nums */
55 CONST char EXP_CHARS[] = "eE";
56
57 /* Chars that mean this number is a floating point constant, as
58 in "0f12.456" or "0d1.2345e12". */
59
60 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
61
62 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
63 changed in read.c . Ideally it shouldn't have to know about it at all,
64 but nothing is ideal around here. */
65
66 const int md_reloc_size = 8; /* Size of relocation record */
67
68 /* Are we trying to generate PIC code? If so, absolute references
69 ought to be made into linkage table references or pc-relative
70 references. */
71 int flag_want_pic;
72
73 static int flag_short_refs; /* -l option */
74 static int flag_long_jumps; /* -S option */
75
76 #ifdef REGISTER_PREFIX_OPTIONAL
77 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
78 #else
79 int flag_reg_prefix_optional;
80 #endif
81
82 /* Its an arbitrary name: This means I don't approve of it */
83 /* See flames below */
84 static struct obstack robyn;
85
86 #define TAB(x,y) (((x)<<2)+(y))
87 #define TABTYPE(xy) ((xy) >> 2)
88 #define BYTE 0
89 #define SHORT 1
90 #define LONG 2
91 #define SZ_UNDEF 3
92 #undef BRANCH
93 #define ABRANCH 1
94 #define FBRANCH 2
95 #define PCREL 3
96 #define BCC68000 4
97 #define DBCC 5
98 #define PCLEA 6
99
100 struct m68k_incant
101 {
102 char *m_operands;
103 unsigned long m_opcode;
104 short m_opnum;
105 short m_codenum;
106 int m_arch;
107 struct m68k_incant *m_next;
108 };
109
110 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
111 #define gettwo(x) (((x)->m_opcode)&0xffff)
112
113 /* Operands we can parse: (And associated modes)
114
115 numb: 8 bit num
116 numw: 16 bit num
117 numl: 32 bit num
118 dreg: data reg 0-7
119 reg: address or data register
120 areg: address register
121 apc: address register, PC, ZPC or empty string
122 num: 16 or 32 bit num
123 num2: like num
124 sz: w or l if omitted, l assumed
125 scale: 1 2 4 or 8 if omitted, 1 assumed
126
127 7.4 IMMED #num --> NUM
128 0.? DREG dreg --> dreg
129 1.? AREG areg --> areg
130 2.? AINDR areg@ --> *(areg)
131 3.? AINC areg@+ --> *(areg++)
132 4.? ADEC areg@- --> *(--areg)
133 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
134 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
135 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
136 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
137 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
138 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
139 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
140 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
141 7.0 ABSL num:sz --> *(num)
142 num --> *(num) (sz L assumed)
143 *** MSCR otherreg --> Magic
144 With -l option
145 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
146 ?.? DINDR dreg@ --> (dreg) -- cas2 only
147
148 examples:
149 #foo #0x35 #12
150 d2
151 a4
152 a3@
153 a5@+
154 a6@-
155 a2@(12) pc@(14)
156 a1@(5,d2:w:1) @(45,d6:l:4)
157 pc@(a2) @(d4)
158 etc . . .
159
160
161 #name@(numw) -->turn into PC rel mode
162 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
163
164 */
165
166 enum operand_type
167 {
168 IMMED = 1,
169 DREG,
170 AREG,
171 AINDR,
172 ADEC,
173 AINC,
174 AOFF,
175 AINDX,
176 APODX,
177 AMIND,
178 APRDX,
179 ABSL,
180 MSCR,
181 REGLST,
182 DINDR
183 };
184
185
186 struct m68k_exp
187 {
188 char *e_beg;
189 char *e_end;
190 segT e_seg;
191 expressionS e_exp;
192 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
193 };
194
195 /* DATA and ADDR have to be contiguous, so that reg-DATA gives
196 0-7==data reg, 8-15==addr reg for operands that take both types.
197
198 We don't use forms like "ADDR0 = ADDR" here because this file is
199 likely to be used on an Apollo, and the broken Apollo compiler
200 gives an `undefined variable' error if we do that, according to
201 troy@cbme.unsw.edu.au. */
202
203 #define DATA DATA0
204 #define ADDR ADDR0
205 #define SP ADDR7
206 #define FPREG FP0
207 #define COPNUM COP0
208 #define BAD BAD0
209 #define BAC BAC0
210
211 enum _register
212 {
213 DATA0 = 1, /* 1- 8 == data registers 0-7 */
214 DATA1,
215 DATA2,
216 DATA3,
217 DATA4,
218 DATA5,
219 DATA6,
220 DATA7,
221
222 ADDR0,
223 ADDR1,
224 ADDR2,
225 ADDR3,
226 ADDR4,
227 ADDR5,
228 ADDR6,
229 ADDR7,
230
231 FP0, /* Eight FP registers */
232 FP1,
233 FP2,
234 FP3,
235 FP4,
236 FP5,
237 FP6,
238 FP7,
239
240 /* Note that COP0==processor #1 -- COP0+7==#8, which stores as 000 */
241 /* I think. . . */
242
243 COP0, /* Co-processor #1-#8 */
244 COP1,
245 COP2,
246 COP3,
247 COP4,
248 COP5,
249 COP6,
250 COP7,
251
252 PC, /* Program counter */
253 ZPC, /* Hack for Program space, but 0 addressing */
254 SR, /* Status Reg */
255 CCR, /* Condition code Reg */
256
257 /* These have to be grouped together for the movec instruction to work. */
258 USP, /* User Stack Pointer */
259 ISP, /* Interrupt stack pointer */
260 SFC,
261 DFC,
262 CACR,
263 VBR,
264 CAAR,
265 MSP,
266 ITT0,
267 ITT1,
268 DTT0,
269 DTT1,
270 MMUSR,
271 TC,
272 SRP,
273 URP,
274 BUSCR, /* 68060 added these */
275 PCR,
276 #define last_movec_reg PCR
277 /* end of movec ordering constraints */
278
279 FPI,
280 FPS,
281 FPC,
282
283 DRP, /* 68851 or 68030 MMU regs */
284 CRP,
285 CAL,
286 VAL,
287 SCC,
288 AC,
289 BAD0,
290 BAD1,
291 BAD2,
292 BAD3,
293 BAD4,
294 BAD5,
295 BAD6,
296 BAD7,
297 BAC0,
298 BAC1,
299 BAC2,
300 BAC3,
301 BAC4,
302 BAC5,
303 BAC6,
304 BAC7,
305 PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040)
306 and ACUSR on 68ec030 */
307 PCSR,
308
309 IC, /* instruction cache token */
310 DC, /* data cache token */
311 NC, /* no cache token */
312 BC, /* both caches token */
313
314 TT0, /* 68030 access control unit regs */
315 TT1,
316 };
317
318 static const enum _register m68000_control_regs[] = { 0 };
319 static const enum _register m68010_control_regs[] = {
320 SFC, DFC, USP, VBR,
321 0
322 };
323 static const enum _register m68020_control_regs[] = {
324 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
325 0
326 };
327 static const enum _register m68040_control_regs[] = {
328 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
329 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
330 0
331 };
332 static const enum _register m68060_control_regs[] = {
333 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
334 USP, VBR, URP, SRP, PCR,
335 0
336 };
337 #define cpu32_control_regs m68010_control_regs
338
339 static const enum _register *control_regs;
340
341 /* Internal form of an operand. */
342 struct m68k_op
343 {
344 char *error; /* Couldn't parse it */
345 enum operand_type mode; /* What mode this instruction is in. */
346 enum _register reg; /* Base register */
347 struct m68k_exp *con1;
348 int ireg; /* Index register */
349 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
350 int imul; /* Multipy ireg by this (1,2,4,or 8) */
351 struct m68k_exp *con2;
352 };
353
354 /* internal form of a 68020 instruction */
355 struct m68k_it
356 {
357 char *error;
358 char *args; /* list of opcode info */
359 int numargs;
360
361 int numo; /* Number of shorts in opcode */
362 short opcode[11];
363
364 struct m68k_op operands[6];
365
366 int nexp; /* number of exprs in use */
367 struct m68k_exp exprs[4];
368
369 int nfrag; /* Number of frags we have to produce */
370 struct
371 {
372 int fragoff; /* Where in the current opcode[] the frag ends */
373 symbolS *fadd;
374 long foff;
375 int fragty;
376 }
377 fragb[4];
378
379 int nrel; /* Num of reloc strucs in use */
380 struct
381 {
382 int n;
383 expressionS exp;
384 char wid;
385 char pcrel;
386 }
387 reloc[5]; /* Five is enough??? */
388 };
389
390 #define cpu_of_arch(x) ((x) & m68000up)
391 #define float_of_arch(x) ((x) & mfloat)
392 #define mmu_of_arch(x) ((x) & mmmu)
393
394 static struct m68k_it the_ins; /* the instruction being assembled */
395
396 #define seg(exp) ((exp)->e_seg)
397 #define op(exp) ((exp)->e_exp.X_op)
398 #define adds(exp) ((exp)->e_exp.X_add_symbol)
399 #define subs(exp) ((exp)->e_exp.X_op_symbol)
400 #define offs(exp) ((exp)->e_exp.X_add_number)
401
402 /* Macros for adding things to the m68k_it struct */
403
404 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
405
406 /* Like addword, but goes BEFORE general operands */
407 static void
408 insop (w, opcode)
409 int w;
410 struct m68k_incant *opcode;
411 {
412 int z;
413 for(z=the_ins.numo;z>opcode->m_codenum;--z)
414 the_ins.opcode[z]=the_ins.opcode[z-1];
415 for(z=0;z<the_ins.nrel;z++)
416 the_ins.reloc[z].n+=2;
417 the_ins.opcode[opcode->m_codenum]=w;
418 the_ins.numo++;
419 }
420
421 static struct m68k_exp *
422 add_exp (beg, end)
423 char *beg;
424 char *end;
425 {
426 the_ins.exprs[the_ins.nexp].e_beg=beg;
427 the_ins.exprs[the_ins.nexp].e_end=end;
428 return &the_ins.exprs[the_ins.nexp++];
429 }
430
431
432 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
433 Blecch. */
434 static void
435 add_fix (width, exp, pc_rel)
436 char width;
437 struct m68k_exp *exp;
438 int pc_rel;
439 {
440 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
441 ? (the_ins.numo*2-1)
442 : (((width)=='b')
443 ? ((the_ins.numo-1)*2)
444 : (the_ins.numo*2)));
445 the_ins.reloc[the_ins.nrel].exp = exp->e_exp;
446 the_ins.reloc[the_ins.nrel].wid = width;
447 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
448 }
449
450 static void
451 add_frag(add,off,type)
452 symbolS *add;
453 long off;
454 int type;
455 {
456 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
457 the_ins.fragb[the_ins.nfrag].fadd=add;
458 the_ins.fragb[the_ins.nfrag].foff=off;
459 the_ins.fragb[the_ins.nfrag++].fragty=type;
460 }
461
462 #define isvar(exp) \
463 ((exp) && op (exp) != O_constant && op (exp) != O_big)
464
465 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
466 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
467 static int get_regs PARAMS ((int i, char *str, struct m68k_op *opP));
468 static int reverse_16_bits PARAMS ((int in));
469 static int reverse_8_bits PARAMS ((int in));
470 static int try_index PARAMS ((char **s, struct m68k_op *opP));
471 static void install_gen_operand PARAMS ((int mode, int val));
472 static void install_operand PARAMS ((int mode, int val));
473 static void s_bss PARAMS ((int));
474 static void s_data1 PARAMS ((int));
475 static void s_data2 PARAMS ((int));
476 static void s_even PARAMS ((int));
477 static void s_proc PARAMS ((int));
478
479 static int current_architecture;
480
481 struct m68k_cpu {
482 unsigned long arch;
483 const char *name;
484 };
485
486 static const struct m68k_cpu archs[] = {
487 { m68000, "68000" },
488 { m68010, "68010" },
489 { m68020, "68020" },
490 { m68030, "68030" },
491 { m68040, "68040" },
492 { m68060, "68060" },
493 { cpu32, "cpu32" },
494 { m68881, "68881" },
495 { m68851, "68851" },
496 /* Aliases (effectively, so far as gas is concerned) for the above
497 cpus. */
498 { m68020, "68k" },
499 { m68000, "68302" },
500 { m68000, "68008" },
501 { cpu32, "68331" },
502 { cpu32, "68332" },
503 { cpu32, "68333" },
504 { cpu32, "68340" },
505 { m68881, "68882" },
506 };
507
508 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
509
510 /* BCC68000 is for patching in an extra jmp instruction for long offsets
511 on the 68000. The 68000 doesn't support long branches with branchs */
512
513 /* This table desribes how you change sizes for the various types of variable
514 size expressions. This version only supports two kinds. */
515
516 /* Note that calls to frag_var need to specify the maximum expansion
517 needed; this is currently 10 bytes for DBCC. */
518
519 /* The fields are:
520 How far Forward this mode will reach:
521 How far Backward this mode will reach:
522 How many bytes this mode will add to the size of the frag
523 Which mode to go to if the offset won't fit in this one
524 */
525 CONST relax_typeS md_relax_table[] =
526 {
527 {1, 1, 0, 0}, /* First entries aren't used */
528 {1, 1, 0, 0}, /* For no good reason except */
529 {1, 1, 0, 0}, /* that the VAX doesn't either */
530 {1, 1, 0, 0},
531
532 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
533 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
534 {0, 0, 4, 0},
535 {1, 1, 0, 0},
536
537 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
538 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
539 {0, 0, 4, 0},
540 {1, 1, 0, 0},
541
542 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
543 {(32767), (-32768), 2, TAB (PCREL, LONG)},
544 {0, 0, 4, 0},
545 {1, 1, 0, 0},
546
547 {(127), (-128), 0, TAB (BCC68000, SHORT)},
548 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
549 {0, 0, 6, 0}, /* jmp long space */
550 {1, 1, 0, 0},
551
552 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
553 {(32767), (-32768), 2, TAB (DBCC, LONG)},
554 {0, 0, 10, 0}, /* bra/jmp long space */
555 {1, 1, 0, 0},
556
557 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
558 {32767, -32768, 2, TAB (PCLEA, LONG)},
559 {0, 0, 6, 0},
560 {1, 1, 0, 0},
561
562 };
563
564 /* These are the machine dependent pseudo-ops. These are included so
565 the assembler can work on the output from the SUN C compiler, which
566 generates these.
567 */
568
569 /* This table describes all the machine specific pseudo-ops the assembler
570 has to support. The fields are:
571 pseudo-op name without dot
572 function to call to execute this pseudo-op
573 Integer arg to pass to the function
574 */
575 CONST pseudo_typeS md_pseudo_table[] =
576 {
577 {"data1", s_data1, 0},
578 {"data2", s_data2, 0},
579 {"bss", s_bss, 0},
580 {"even", s_even, 0},
581 {"skip", s_space, 0},
582 {"proc", s_proc, 0},
583 #ifdef TE_SUN3
584 {"align", s_align_bytes, 0},
585 #endif
586 {0, 0, 0}
587 };
588
589
590 /* The mote pseudo ops are put into the opcode table, since they
591 don't start with a . they look like opcodes to gas.
592 */
593 extern void obj_coff_section ();
594
595 CONST pseudo_typeS mote_pseudo_table[] =
596 {
597
598 {"dcl", cons, 4},
599 {"dc", cons, 2},
600 {"dcw", cons, 2},
601 {"dcb", cons, 1},
602
603 {"dsl", s_space, 4},
604 {"ds", s_space, 2},
605 {"dsw", s_space, 2},
606 {"dsb", s_space, 1},
607
608 {"xdef", s_globl, 0},
609 {"align", s_align_ptwo, 0},
610 #ifdef M68KCOFF
611 {"sect", obj_coff_section, 0},
612 {"section", obj_coff_section, 0},
613 #endif
614 {0, 0, 0}
615 };
616
617 #define issbyte(x) ((x)>=-128 && (x)<=127)
618 #define isubyte(x) ((x)>=0 && (x)<=255)
619 #define issword(x) ((x)>=-32768 && (x)<=32767)
620 #define isuword(x) ((x)>=0 && (x)<=65535)
621
622 #define isbyte(x) ((x)>= -255 && (x)<=255)
623 #define isword(x) ((x)>=-32768 && (x)<=65535)
624 #define islong(x) (1)
625
626 extern char *input_line_pointer;
627
628 enum
629 {
630 FAIL = 0,
631 OK = 1,
632 };
633
634 static char mklower_table[256];
635 #define mklower(c) (mklower_table[(unsigned char)(c)])
636 static char notend_table[256];
637 static char alt_notend_table[256];
638 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
639 alt_notend_table[(unsigned char)(s[1])])))
640
641 /* JF modified this to handle cases where the first part of a symbol name
642 looks like a register */
643
644 /*
645 * m68k_reg_parse() := if it looks like a register, return it's token &
646 * advance the pointer.
647 */
648
649 enum _register
650 m68k_reg_parse (ccp)
651 register char **ccp;
652 {
653 char *start = *ccp;
654 char c;
655 char *p;
656 symbolS *symbolP;
657
658 if (flag_reg_prefix_optional)
659 {
660 if (*start == REGISTER_PREFIX)
661 start++;
662 p = start;
663 }
664 else
665 {
666 if (*start != REGISTER_PREFIX)
667 return FAIL;
668 p = start + 1;
669 }
670
671 if (!isalpha (*p) || !is_name_beginner (*p))
672 return FAIL;
673
674 c = *p++;
675 while (isalpha (c) || isdigit (c) || c == '_')
676 {
677 c = *p++;
678 }
679
680 *--p = 0;
681 symbolP = symbol_find (start);
682 *p = c;
683
684 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
685 {
686 *ccp = p;
687 return S_GET_VALUE (symbolP);
688 }
689
690 return FAIL;
691 }
692
693 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
694 #define SKIP_W() { ss++; if(*ss==' ') ss++;}
695
696 /* Parse an index specification using Motorola syntax. */
697
698 static int
699 try_moto_index (s, opP)
700 char **s;
701 struct m68k_op *opP;
702 {
703 register int i;
704 char *ss;
705
706 ss = *s;
707 /* SKIP_W(); */
708 if (*ss == ' ')
709 ss++;
710 i = m68k_reg_parse (&ss);
711 if (!(i >= DATA + 0 && i <= ADDR + 7))
712 { /* if i is not DATA or ADDR reg */
713 opP->error = "Invalid index register";
714 *s = ss;
715 return FAIL;
716 }
717 opP->ireg = i;
718 /* SKIP_W(); */
719 if (*ss == ')')
720 {
721 opP->isiz = 0;
722 opP->imul = 1;
723 SKIP_W ();
724 *s = ss;
725 return OK;
726 }
727 if (*ss != '.')
728 {
729 opP->error = "Missing . in index register";
730 *s = ss;
731 return FAIL;
732 }
733 SKIP_W ();
734 if (mklower (*ss) == 'w')
735 opP->isiz = 2;
736 else if (mklower (*ss) == 'l')
737 opP->isiz = 3;
738 else
739 {
740 opP->error = "Size spec not .W or .L";
741 *s = ss;
742 return FAIL;
743 }
744 SKIP_W ();
745 if (*ss == '.' || *ss == '*')
746 {
747 SKIP_W ();
748 switch (*ss)
749 {
750 case '1':
751 case '2':
752 case '4':
753 case '8':
754 opP->imul = *ss - '0';
755 break;
756 default:
757 opP->error = "index multiplier not 1, 2, 4 or 8";
758 *s = ss;
759 return FAIL;
760 }
761 SKIP_W ();
762 }
763 else
764 opP->imul = 1;
765 if (*ss != ')')
766 {
767 opP->error = "Missing )";
768 *s = ss;
769 return FAIL;
770 }
771 SKIP_W ();
772 *s = ss;
773 return OK;
774 }
775
776 /*
777 *
778 * try_index := data_or_address_register + ')' + SKIP_W
779 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
780 *
781 * multiplier := <empty>
782 * | ':' + multiplier_number
783 * ;
784 *
785 * multiplier_number := '1' | '2' | '4' | '8' ;
786 *
787 * size_spec := 'l' | 'L' | 'w' | 'W' ;
788 *
789 * SKIP_W := <empty> | ' ' ;
790 *
791 */
792
793 static int
794 try_index (s, opP)
795 char **s;
796 struct m68k_op *opP;
797 {
798 register int i;
799 char *ss;
800
801 ss = *s;
802 /* SKIP_W(); */
803 i = m68k_reg_parse (&ss);
804 if (!(i >= DATA + 0 && i <= ADDR + 7))
805 { /* if i is not DATA or ADDR reg */
806 *s = ss;
807 return FAIL;
808 }
809 opP->ireg = i;
810 /* SKIP_W(); */
811 if (*ss == ')')
812 {
813 opP->isiz = 0;
814 opP->imul = 1;
815 SKIP_W ();
816 *s = ss;
817 return OK;
818 }
819 if (*ss != ':')
820 {
821 opP->error = "Missing : in index register";
822 *s = ss;
823 return FAIL;
824 }
825 SKIP_W ();
826 switch (*ss)
827 {
828 case 'w':
829 case 'W':
830 opP->isiz = 2;
831 break;
832 case 'l':
833 case 'L':
834 opP->isiz = 3;
835 break;
836 default:
837 opP->error = "Index register size spec not :w or :l";
838 *s = ss;
839 return FAIL;
840 }
841 SKIP_W ();
842 if (*ss == ':')
843 {
844 SKIP_W ();
845 switch (*ss)
846 {
847 case '1':
848 case '2':
849 case '4':
850 case '8':
851 if (cpu_of_arch (current_architecture) < m68020)
852 {
853 opP->error = "no index scaling in pre-68020's";
854 *s = ss;
855 return FAIL;
856 }
857 opP->imul = *ss - '0';
858 break;
859 default:
860 opP->error = "index multiplier not 1, 2, 4 or 8";
861 *s = ss;
862 return FAIL;
863 }
864 SKIP_W ();
865 }
866 else
867 opP->imul = 1;
868 if (*ss != ')')
869 {
870 opP->error = "Missing )";
871 *s = ss;
872 return FAIL;
873 }
874 SKIP_W ();
875 *s = ss;
876 return OK;
877 } /* try_index() */
878
879 /* Ian Taylor expanded this function to accept both MIT and Motorola
880 syntax. I removed the old comment, since it was wrong. The syntax
881 this accepted even before my changes was complex and undocumented.
882 I mainly added a large case when the operand string does not
883 contain an '@', since the Motorola syntax does not use the '@'
884 character. */
885
886 int
887 m68k_ip_op (str, opP)
888 char *str;
889 register struct m68k_op *opP;
890 {
891 char *strend;
892 long i;
893 char *parse_index ();
894 int needp;
895
896 if (*str == ' ')
897 {
898 str++;
899 } /* Find the beginning of the string */
900
901 if (!*str)
902 {
903 opP->error = "Missing operand";
904 return FAIL;
905 } /* Out of gas */
906
907 for (strend = str; *strend; strend++)
908 ;
909 --strend;
910
911 if (*str == '#' || *str == '&')
912 {
913 str++;
914 opP->con1 = add_exp (str, strend);
915 opP->mode = IMMED;
916 return OK;
917 } /* Guess what: A constant. Shar and enjoy */
918
919 i = m68k_reg_parse (&str);
920
921 if (i != FAIL)
922 {
923 if (*str == '/' || *str == '-')
924 {
925 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
926 opP->mode = REGLST;
927 return get_regs (i, str, opP);
928 }
929 if (*str == '\0')
930 {
931 opP->reg = i;
932 /* "Rn" Register Direct mode */
933 if (i >= DATA + 0 && i <= DATA + 7)
934 opP->mode = DREG;
935 else if (i >= ADDR + 0 && i <= ADDR + 7)
936 opP->mode = AREG;
937 else
938 opP->mode = MSCR;
939 return OK;
940 }
941 }
942
943 if (*str != '@')
944 {
945 char *stmp;
946
947 if ((stmp = strchr (str, '@')) != 0)
948 {
949 opP->con1 = add_exp (str, stmp - 1);
950 if (stmp == strend)
951 {
952 opP->mode = AINDX;
953 return (OK);
954 }
955
956 if ((current_architecture & m68020up) == 0)
957 {
958 return (FAIL);
959 } /* if target is not a '20 or better */
960
961 stmp++;
962 if (*stmp++ != '(' || *strend-- != ')')
963 {
964 opP->error = "Malformed operand";
965 return (FAIL);
966 }
967 i = try_index (&stmp, opP);
968 opP->con2 = add_exp (stmp, strend);
969
970 if (i == FAIL)
971 {
972 opP->mode = AMIND;
973 }
974 else
975 {
976 opP->mode = APODX;
977 }
978 return (OK);
979 } /* if there's an '@' */
980
981 #ifndef MIT_SYNTAX_ONLY
982 /* The operand has no '@'. Try to parse it using
983 Motorola syntax. */
984 /* Logic of the parsing switch(*str):
985 case opP->mode =
986 ---- -----------
987 #anything IMMED 1
988 REG AREG or DREG or MSCR 3 or 2 or 13
989 REG- or REG/ REGLST 14
990 (REG) AINDR 4
991 (REG)+ AINC 6
992 (REG,INDX) AINDX 8
993 (EXPR,REG) AOFF 7
994 (EXPR,REG,INDX) AINDX 8
995 -(REG) ADEC 5
996 EXP2(REG) AOFF 7
997 EXP2(REG,INDX) AINDX 8
998 EXP2 ABSL 12
999
1000 REG means truth(m68k_reg_parse(&str))
1001 INDX means truth(try_moto_index(&str,opP))
1002 EXPR means not REG
1003 EXP2 means not REG and not '(' and not '-('
1004 */
1005
1006 if (*str == '(')
1007 {
1008 str++;
1009 i = m68k_reg_parse (&str);
1010 if ((i < ADDR + 0 || i > ADDR + 7)
1011 && (i < DATA + 0 || i > DATA + 7
1012 || *str != ')' || str[1] != '0')
1013 && i != PC && i != ZPC && i != FAIL)
1014 {
1015 /* Can't indirect off non address regs */
1016 opP->error = "Invalid indirect register";
1017 return FAIL;
1018 }
1019 if (i != FAIL)
1020 {
1021 opP->reg = i;
1022 if (*str == ')')
1023 {
1024 str++;
1025 if (*str == '\0')
1026 {
1027 /* "(An)" Address Register Indirect mode
1028 or "(Dn)" for cas2. */
1029 if (i >= DATA + 0 && i <= DATA + 7)
1030 opP->mode = DINDR;
1031 else
1032 opP->mode = AINDR;
1033 return OK;
1034 }
1035 if (*str == '+')
1036 {
1037 if (str[1] == '\0')
1038 {
1039 /* "(An)+" Register Indirect w Postincrement */
1040 opP->mode = AINC;
1041 return OK;
1042 }
1043 }
1044 opP->error = "Junk after indirect";
1045 return FAIL;
1046 }
1047 if (*str == ',')
1048 {
1049 str++;
1050 i = try_moto_index (&str, opP);
1051 if (i == FAIL)
1052 return FAIL;
1053 /* "(An,Rn)" Register Indirect with Index mode*/
1054 opP->mode = AINDX;
1055 return OK;
1056 }
1057 else
1058 {
1059 opP->error = "Bad indirect syntax";
1060 return FAIL;
1061 }
1062 }
1063 else
1064 {
1065 /* "(EXPR,..." , a displacement */
1066 char *stmp;
1067
1068 if ((stmp = strchr (str, ',')) != NULL)
1069 {
1070 opP->con1 = add_exp (str, stmp - 1);
1071 str = stmp;
1072 SKIP_WHITE ();
1073 i = m68k_reg_parse (&str);
1074 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC)
1075 {
1076 /* Can't indirect off non address regs */
1077 opP->error = "Invalid indirect register";
1078 return FAIL;
1079 }
1080 if (i != FAIL)
1081 {
1082 opP->reg = i;
1083 if (*str == ')')
1084 {
1085 /* "(d,An)" Register Indirect w Displacement */
1086 opP->mode = AOFF;
1087 return OK;
1088 }
1089 if (*str == ',')
1090 {
1091 str++;
1092 i = try_moto_index (&str, opP);
1093 if (i == FAIL)
1094 return FAIL;
1095 /* "(d,An,Rn)" Register Indirect with Index */
1096 opP->mode = AINDX;
1097 return OK;
1098 }
1099 else
1100 {
1101 opP->error = "Bad indirect syntax";
1102 return FAIL;
1103 }
1104 }
1105 else
1106 {
1107 opP->error = "Invalid register";
1108 return FAIL;
1109 }
1110 }
1111 else
1112 {
1113 opP->mode = ABSL;
1114 opP->con1 = add_exp (str - 1, strend);
1115 return OK;
1116 }
1117 }
1118 }
1119
1120 if (*str == '-')
1121 {
1122 if (str[1] == '(')
1123 {
1124 str = str + 2;
1125 i = m68k_reg_parse (&str);
1126 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL)
1127 {
1128 /* Can't indirect off non address regs */
1129 opP->error = "Invalid indirect register";
1130 return FAIL;
1131 }
1132 if (i != FAIL)
1133 {
1134 opP->reg = i;
1135 if (*str == ')')
1136 {
1137 str++;
1138 if (*str == '\0')
1139 {
1140 /* "-(An)" Register Indirect with Predecrement */
1141 opP->mode = ADEC;
1142 return OK;
1143 }
1144 opP->error = "Junk after indirect";
1145 return FAIL;
1146 }
1147 opP->error = "Bad indirect syntax";
1148 return FAIL;
1149 }
1150 opP->mode = ABSL;
1151 opP->con1 = add_exp (str - 2, strend);
1152 return OK;
1153 }
1154 /* if '-' but not "-(', do nothing */
1155 }
1156
1157 /* whether *str=='-' or not */
1158 {
1159 /* "EXP2" or "EXP2(REG..." */
1160 char *stmp;
1161 if ((stmp = strchr (str, '(')) != NULL)
1162 {
1163 char *ostr = str;
1164
1165 opP->con1 = add_exp (str, stmp - 1);
1166 str = stmp + 1;
1167 i = m68k_reg_parse (&str);
1168 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC
1169 && i != ZPC && i != FAIL)
1170 {
1171 /* Can't indirect off non address regs */
1172 opP->error = "Invalid indirect register";
1173 return FAIL;
1174 }
1175 if (i != FAIL)
1176 {
1177 opP->reg = i;
1178 if (*str == ')')
1179 {
1180 /* "d(An)" Register Indirect w Displacement */
1181 opP->mode = AOFF;
1182 return OK;
1183 }
1184 if (*str == ',')
1185 {
1186 str++;
1187 i = try_moto_index (&str, opP);
1188 if (i == FAIL)
1189 return FAIL;
1190 /* "d(An,Rn)" Register Indirect with Index */
1191 opP->mode = AINDX;
1192 return OK;
1193 }
1194 else
1195 {
1196 opP->error = "Bad indirect syntax";
1197 return FAIL;
1198 }
1199 }
1200 else
1201 {
1202 opP->mode = ABSL;
1203 opP->con1 = add_exp (ostr, strend);
1204 return OK;
1205 }
1206 }
1207 else
1208 {
1209 /* "EXP2" Absolute */
1210 opP->mode = ABSL;
1211 opP->isiz = 0;
1212 if (strend[-1] == '.' || strend[-1] == ':')
1213 {
1214 /* mode ==foo.[wl] */
1215 switch (*strend)
1216 {
1217 case 'w':
1218 case 'W':
1219 opP->isiz = 2;
1220 break;
1221 case 'l':
1222 case 'L':
1223 opP->isiz = 3;
1224 break;
1225 }
1226 }
1227 opP->con1 = add_exp (str, strend);
1228 return OK;
1229 }
1230 }
1231 /*NOTREACHED*/
1232 #else /* defined (MIT_SYNTAX_ONLY) */
1233 opP->mode = ABSL;
1234 opP->con1 = add_exp (str, strend);
1235 return OK;
1236 #endif /* defined (MIT_SYNTAX_ONLY) */
1237 }
1238
1239 opP->reg = i;
1240
1241 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1242 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL
1243 && (str[1] != '\0' || i < DATA + 0 || i > DATA + 7))
1244 {
1245 opP->error = "Invalid indirect register";
1246 return FAIL;
1247 }
1248 know (*str == '@');
1249
1250 str++;
1251 switch (*str)
1252 {
1253 case '\0':
1254 if (i < DATA + 0 || i > DATA + 7)
1255 opP->mode = AINDR;
1256 else
1257 opP->mode = DINDR;
1258 return OK;
1259 case '-':
1260 opP->mode = ADEC;
1261 return OK;
1262 case '+':
1263 opP->mode = AINC;
1264 return OK;
1265 case '(':
1266 str++;
1267 break;
1268 default:
1269 opP->error = "Junk after indirect";
1270 return FAIL;
1271 }
1272 /* Some kind of indexing involved. Lets find out how bad it is */
1273 i = try_index (&str, opP);
1274 /* Didn't start with an index reg, maybe its offset or offset,reg */
1275 if (i == FAIL)
1276 {
1277 char *beg_str;
1278
1279 beg_str = str;
1280 for (i = 1; i;)
1281 {
1282 switch (*str++)
1283 {
1284 case '\0':
1285 opP->error = "Missing )";
1286 return FAIL;
1287 case ',':
1288 i = 0;
1289 break;
1290 case '(':
1291 i++;
1292 break;
1293 case ')':
1294 --i;
1295 break;
1296 }
1297 }
1298 opP->con1 = add_exp (beg_str, str - 2);
1299 /* Should be offset,reg */
1300 if (str[-1] == ',')
1301 {
1302 i = try_index (&str, opP);
1303 if (i == FAIL)
1304 {
1305 opP->error = "Malformed index reg";
1306 return FAIL;
1307 }
1308 }
1309 }
1310 /* We've now got offset) offset,reg) or reg) */
1311
1312 if (*str == '\0')
1313 {
1314 /* Th-the-thats all folks */
1315 if (opP->reg == FAIL)
1316 opP->mode = AINDX; /* Other form of indirect */
1317 else if (opP->ireg == FAIL)
1318 opP->mode = AOFF;
1319 else
1320 opP->mode = AINDX;
1321 return (OK);
1322 }
1323 /* Next thing had better be another @ */
1324 if (*str == '@')
1325 {
1326 if (str[1] == '(')
1327 {
1328 needp = 1;
1329 str += 2;
1330 }
1331 else
1332 {
1333 needp = 0;
1334 str++;
1335 }
1336 }
1337
1338 if ((current_architecture & m68020up) == 0)
1339 {
1340 return (FAIL);
1341 } /* if target is not a '20 or better */
1342
1343
1344 if (opP->ireg != FAIL)
1345 {
1346 opP->mode = APRDX;
1347
1348 i = try_index (&str, opP);
1349 if (i != FAIL)
1350 {
1351 opP->error = "Two index registers! not allowed!";
1352 return (FAIL);
1353 }
1354 }
1355 else
1356 {
1357 i = try_index (&str, opP);
1358 }
1359
1360 if (i == FAIL)
1361 {
1362 char *beg_str;
1363
1364 beg_str = str;
1365
1366 for (i = 1; i;)
1367 {
1368 switch (*str++)
1369 {
1370 case '\0':
1371 if (needp)
1372 opP->error = "Missing )";
1373 return (FAIL);
1374 break;
1375 case ',':
1376 i = 0;
1377 break;
1378 case '(':
1379 i++;
1380 break;
1381 case ')':
1382 --i;
1383 break;
1384 }
1385 }
1386
1387 opP->con2 = add_exp (beg_str, str - 2);
1388
1389 if (str[-1] == ',')
1390 {
1391 if (opP->ireg != FAIL)
1392 {
1393 opP->error = "Can't have two index regs";
1394 return (FAIL);
1395 }
1396
1397 i = try_index (&str, opP);
1398
1399 if (i == FAIL)
1400 {
1401 opP->error = "malformed index reg";
1402 return (FAIL);
1403 }
1404
1405 opP->mode = APODX;
1406 }
1407 else if (opP->ireg != FAIL)
1408 {
1409 opP->mode = APRDX;
1410 }
1411 else
1412 {
1413 opP->mode = AMIND;
1414 }
1415 }
1416 else
1417 {
1418 opP->mode = APODX;
1419 }
1420
1421 if (*str != '\0')
1422 {
1423 opP->error = "Junk after indirect";
1424 return FAIL;
1425 }
1426 return (OK);
1427 }
1428
1429
1430 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
1431
1432 #ifdef NO_PCREL_RELOCS
1433
1434 int
1435 make_pcrel_absolute(fixP, add_number)
1436 fixS *fixP;
1437 long *add_number;
1438 {
1439 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
1440
1441 /* rewrite the PC relative instructions to absolute address ones.
1442 * these are rumoured to be faster, and the apollo linker refuses
1443 * to deal with the PC relative relocations.
1444 */
1445 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
1446 {
1447 opcode[0] = 0x4e;
1448 opcode[1] = 0xf9;
1449 }
1450 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
1451 {
1452 opcode[0] = 0x4e;
1453 opcode[1] = 0xb9;
1454 }
1455 else
1456 as_fatal ("Unknown PC relative instruction");
1457 *add_number -= 4;
1458 return 0;
1459 }
1460
1461 #endif /* NO_PCREL_RELOCS */
1462
1463 short
1464 tc_coff_fix2rtype (fixP)
1465 fixS *fixP;
1466 {
1467 #ifdef NO_PCREL_RELOCS
1468 know (fixP->fx_pcrel == 0);
1469 return (fixP->fx_size == 1 ? R_RELBYTE
1470 : fixP->fx_size == 2 ? R_DIR16
1471 : R_DIR32);
1472 #else
1473 return (fixP->fx_pcrel ?
1474 (fixP->fx_size == 1 ? R_PCRBYTE :
1475 fixP->fx_size == 2 ? R_PCRWORD :
1476 R_PCRLONG) :
1477 (fixP->fx_size == 1 ? R_RELBYTE :
1478 fixP->fx_size == 2 ? R_RELWORD :
1479 R_RELLONG));
1480 #endif
1481 }
1482
1483 #endif
1484
1485 #ifdef BFD_ASSEMBLER
1486
1487 arelent *
1488 tc_gen_reloc (section, fixp)
1489 asection *section;
1490 fixS *fixp;
1491 {
1492 arelent *reloc;
1493 bfd_reloc_code_real_type code;
1494
1495 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1496 switch (F (fixp->fx_size, fixp->fx_pcrel))
1497 {
1498 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1499 MAP (1, 0, BFD_RELOC_8);
1500 MAP (2, 0, BFD_RELOC_16);
1501 MAP (4, 0, BFD_RELOC_32);
1502 MAP (1, 1, BFD_RELOC_8_PCREL);
1503 MAP (2, 1, BFD_RELOC_16_PCREL);
1504 MAP (4, 1, BFD_RELOC_32_PCREL);
1505 default:
1506 abort ();
1507 }
1508
1509 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
1510 assert (reloc != 0);
1511 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
1512 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1513 if (fixp->fx_pcrel)
1514 reloc->addend = fixp->fx_addnumber;
1515 else
1516 reloc->addend = 0;
1517
1518 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1519 assert (reloc->howto != 0);
1520
1521 return reloc;
1522 }
1523
1524 #endif /* BFD_ASSEMBLER */
1525
1526 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1527 main ()
1528 {
1529 char buf[128];
1530 struct m68k_op thark;
1531
1532 for (;;)
1533 {
1534 if (!gets (buf))
1535 break;
1536 memset (&thark, '\0', sizeof (thark));
1537 if (!m68k_ip_op (buf, &thark))
1538 printf ("FAIL:");
1539 if (thark.error)
1540 printf ("op1 error %s in %s\n", thark.error, buf);
1541 printf ("mode %d, reg %d, ", thark.mode, thark.reg);
1542 if (thark.b_const)
1543 printf ("Constant: '%.*s',", 1 + thark.e_const - thark.b_const, thark.b_const);
1544 printf ("ireg %d, isiz %d, imul %d ", thark.ireg, thark.isiz, thark.imul);
1545 if (thark.b_iadd)
1546 printf ("Iadd: '%.*s'", 1 + thark.e_iadd - thark.b_iadd, thark.b_iadd);
1547 printf ("\n");
1548 }
1549 exit (EXIT_SUCCESS);
1550 }
1551
1552 #endif
1553
1554
1555 /* Handle of the OPCODE hash table. NULL means any use before
1556 m68k_ip_begin() will crash. */
1557 static struct hash_control *op_hash;
1558 \f
1559
1560 /*
1561 * m 6 8 k _ i p ( )
1562 *
1563 * This converts a string into a 68k instruction.
1564 * The string must be a bare single instruction in sun format
1565 * with RMS-style 68020 indirects
1566 * (example: )
1567 *
1568 * It provides some error messages: at most one fatal error message (which
1569 * stops the scan) and at most one warning message for each operand.
1570 * The 68k instruction is returned in exploded form, since we have no
1571 * knowledge of how you parse (or evaluate) your expressions.
1572 * We do however strip off and decode addressing modes and operation
1573 * mnemonic.
1574 *
1575 * This function's value is a string. If it is not "" then an internal
1576 * logic error was found: read this code to assign meaning to the string.
1577 * No argument string should generate such an error string:
1578 * it means a bug in our code, not in the user's text.
1579 *
1580 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1581 * this function.
1582 */
1583
1584 /* JF this function no longer returns a useful value. Sorry */
1585 void
1586 m68k_ip (instring)
1587 char *instring;
1588 {
1589 register char *p;
1590 register struct m68k_op *opP;
1591 register struct m68k_incant *opcode;
1592 register char *s;
1593 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1594 char *pdot, *pdotmove;
1595 int siz1, siz2;
1596 char c;
1597 int losing;
1598 int opsfound;
1599 char *crack_operand ();
1600 LITTLENUM_TYPE words[6];
1601 LITTLENUM_TYPE *wordp;
1602 unsigned long ok_arch = 0;
1603
1604 if (*instring == ' ')
1605 instring++; /* skip leading whitespace */
1606
1607 /* Scan up to end of operation-code, which MUST end in end-of-string
1608 or exactly 1 space. */
1609 pdot = 0;
1610 for (p = instring; *p != '\0'; p++)
1611 {
1612 if (*p == ' ')
1613 break;
1614 if (*p == '.')
1615 pdot = p;
1616 }
1617
1618 if (p == instring)
1619 {
1620 the_ins.error = "No operator";
1621 the_ins.opcode[0] = 0;
1622 /* the_ins.numo=1; */
1623 return;
1624 }
1625
1626 /* p now points to the end of the opcode name, probably whitespace.
1627 make sure the name is null terminated by clobbering the whitespace,
1628 look it up in the hash table, then fix it back.
1629 Remove a dot, first, since the opcode tables have none. */
1630 if (pdot != NULL)
1631 {
1632 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1633 *pdotmove = pdotmove[1];
1634 p--;
1635 }
1636
1637 c = *p;
1638 *p = '\0';
1639 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
1640 *p = c;
1641
1642 if (pdot != NULL)
1643 {
1644 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1645 *pdotmove = pdotmove[-1];
1646 *pdot = '.';
1647 ++p;
1648 }
1649
1650 if (opcode == NULL)
1651 {
1652 the_ins.error = "Unknown operator";
1653 the_ins.opcode[0] = 0;
1654 /* the_ins.numo=1; */
1655 return;
1656 }
1657
1658 /* found a legitimate opcode, start matching operands */
1659 while (*p == ' ')
1660 ++p;
1661
1662
1663 if (opcode->m_operands == 0)
1664 {
1665 char *old = input_line_pointer;
1666 *old = '\n';
1667 input_line_pointer = p;
1668 /* Ahh - it's a motorola style psuedo op */
1669 mote_pseudo_table[opcode->m_opnum].poc_handler
1670 (mote_pseudo_table[opcode->m_opnum].poc_val);
1671 input_line_pointer = old;
1672 *old = 0;
1673
1674 return;
1675 }
1676
1677 for (opP = &the_ins.operands[0]; *p; opP++)
1678 {
1679
1680 p = crack_operand (p, opP);
1681
1682 if (opP->error)
1683 {
1684 the_ins.error = opP->error;
1685 return;
1686 }
1687 }
1688
1689 opsfound = opP - &the_ins.operands[0];
1690
1691 /* This ugly hack is to support the floating pt opcodes in their standard form */
1692 /* Essentially, we fake a first enty of type COP#1 */
1693 if (opcode->m_operands[0] == 'I')
1694 {
1695 int n;
1696
1697 for (n = opsfound; n > 0; --n)
1698 the_ins.operands[n] = the_ins.operands[n - 1];
1699
1700 memset ((char *) (&the_ins.operands[0]), '\0', sizeof (the_ins.operands[0]));
1701 the_ins.operands[0].mode = MSCR;
1702 the_ins.operands[0].reg = COPNUM; /* COP #1 */
1703 opsfound++;
1704 }
1705
1706 /* We've got the operands. Find an opcode that'll accept them */
1707 for (losing = 0;;)
1708 {
1709 /* If we didn't get the right number of ops, or we have no
1710 common model with this pattern then reject this pattern. */
1711
1712 if (opsfound != opcode->m_opnum
1713 || ((opcode->m_arch & current_architecture) == 0))
1714 {
1715 ++losing;
1716 ok_arch |= opcode->m_arch;
1717 }
1718 else
1719 {
1720 for (s = opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++)
1721 {
1722 /* Warning: this switch is huge! */
1723 /* I've tried to organize the cases into this order:
1724 non-alpha first, then alpha by letter. Lower-case
1725 goes directly before uppercase counterpart. */
1726 /* Code with multiple case ...: gets sorted by the lowest
1727 case ... it belongs to. I hope this makes sense. */
1728 switch (*s)
1729 {
1730 case '!':
1731 if (opP->mode == MSCR || opP->mode == IMMED
1732 || opP->mode == DREG || opP->mode == AREG
1733 || opP->mode == AINC || opP->mode == ADEC
1734 || opP->mode == REGLST)
1735 losing++;
1736 break;
1737
1738 case '`':
1739 switch (opP->mode)
1740 {
1741 case MSCR:
1742 case IMMED:
1743 case DREG:
1744 case AREG:
1745 case AINC:
1746 case REGLST:
1747 case AINDR:
1748 losing++;
1749 break;
1750 default:
1751 break;
1752 }
1753 break;
1754
1755 case '#':
1756 if (opP->mode != IMMED)
1757 losing++;
1758 else
1759 {
1760 long t;
1761
1762 t = get_num (opP->con1, 80);
1763 if (s[1] == 'b' && !isbyte (t))
1764 losing++;
1765 else if (s[1] == 'w' && !isword (t))
1766 losing++;
1767 }
1768 break;
1769
1770 case '^':
1771 case 'T':
1772 if (opP->mode != IMMED)
1773 losing++;
1774 break;
1775
1776 case '$':
1777 if (opP->mode == MSCR || opP->mode == AREG ||
1778 opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1779 losing++;
1780 break;
1781
1782 case '%':
1783 if (opP->mode == MSCR || opP->reg == PC ||
1784 opP->reg == ZPC || opP->mode == REGLST)
1785 losing++;
1786 break;
1787
1788
1789 case '&':
1790 if (opP->mode == MSCR || opP->mode == DREG ||
1791 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC ||
1792 opP->mode == AINC || opP->mode == ADEC || opP->mode == REGLST)
1793 losing++;
1794 break;
1795
1796 case '*':
1797 if (opP->mode == MSCR || opP->mode == REGLST)
1798 losing++;
1799 break;
1800
1801 case '+':
1802 if (opP->mode != AINC)
1803 losing++;
1804 break;
1805
1806 case '-':
1807 if (opP->mode != ADEC)
1808 losing++;
1809 break;
1810
1811 case '/':
1812 if (opP->mode == MSCR || opP->mode == AREG ||
1813 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->mode == REGLST)
1814 losing++;
1815 break;
1816
1817 case ';':
1818 if (opP->mode == MSCR || opP->mode == AREG || opP->mode == REGLST)
1819 losing++;
1820 break;
1821
1822 case '?':
1823 if (opP->mode == MSCR || opP->mode == AREG ||
1824 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->reg == PC ||
1825 opP->reg == ZPC || opP->mode == REGLST)
1826 losing++;
1827 break;
1828
1829 case '@':
1830 if (opP->mode == MSCR || opP->mode == AREG ||
1831 opP->mode == IMMED || opP->mode == REGLST)
1832 losing++;
1833 break;
1834
1835 case '~': /* For now! (JF FOO is this right?) */
1836 if (opP->mode == MSCR || opP->mode == DREG ||
1837 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1838 losing++;
1839 break;
1840
1841 case '3':
1842 if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1))
1843 losing++;
1844 break;
1845
1846 case 'A':
1847 if (opP->mode != AREG)
1848 losing++;
1849 break;
1850 case 'a':
1851 if (opP->mode != AINDR)
1852 {
1853 ++losing;
1854 } /* if not address register indirect */
1855 break;
1856 case 'B': /* FOO */
1857 if (opP->mode != ABSL || (flag_long_jumps && instring[0] == 'j'
1858 && instring[1] == 'b'
1859 && instring[2] == 's'
1860 && instring[3] == 'r'))
1861 losing++;
1862 break;
1863
1864 case 'C':
1865 if (opP->mode != MSCR || opP->reg != CCR)
1866 losing++;
1867 break;
1868
1869 case 'd': /* FOO This mode is a KLUDGE!! */
1870 if (opP->mode != AOFF && (opP->mode != ABSL ||
1871 opP->con1->e_beg[0] != '(' || opP->con1->e_end[0] != ')'))
1872 losing++;
1873 break;
1874
1875 case 'D':
1876 if (opP->mode != DREG)
1877 losing++;
1878 break;
1879
1880 case 'F':
1881 if (opP->mode != MSCR || opP->reg < (FPREG + 0) || opP->reg > (FPREG + 7))
1882 losing++;
1883 break;
1884
1885 case 'I':
1886 if (opP->mode != MSCR || opP->reg < COPNUM ||
1887 opP->reg >= COPNUM + 7)
1888 losing++;
1889 break;
1890
1891 case 'J':
1892 if (opP->mode != MSCR
1893 || opP->reg < USP
1894 || opP->reg > last_movec_reg)
1895 losing++;
1896 else
1897 {
1898 const enum _register *rp;
1899 for (rp = control_regs; *rp; rp++)
1900 if (*rp == opP->reg)
1901 break;
1902 if (*rp == 0)
1903 losing++;
1904 }
1905 break;
1906
1907 case 'k':
1908 if (opP->mode != IMMED)
1909 losing++;
1910 break;
1911
1912 case 'l':
1913 case 'L':
1914 if (opP->mode == DREG || opP->mode == AREG || opP->mode == FPREG)
1915 {
1916 if (s[1] == '8')
1917 losing++;
1918 else
1919 {
1920 opP->mode = REGLST;
1921 opP->reg = 1 << (opP->reg - DATA);
1922 }
1923 }
1924 else if (opP->mode != REGLST)
1925 {
1926 losing++;
1927 }
1928 else if (s[1] == '8' && opP->reg & 0x0FFffFF)
1929 losing++;
1930 else if (s[1] == '3' && opP->reg & 0x7000000)
1931 losing++;
1932 break;
1933
1934 case 'M':
1935 if (opP->mode != IMMED)
1936 losing++;
1937 else
1938 {
1939 long t;
1940
1941 t = get_num (opP->con1, 0);
1942 if (!issbyte (t)
1943 || isvar (opP->con1))
1944 losing++;
1945 }
1946 break;
1947
1948 case 'O':
1949 if (opP->mode != DREG && opP->mode != IMMED)
1950 losing++;
1951 break;
1952
1953 case 'Q':
1954 if (opP->mode != IMMED)
1955 losing++;
1956 else
1957 {
1958 long t;
1959
1960 t = get_num (opP->con1, 80);
1961 if (t < 1 || t > 8 || isvar (opP->con1))
1962 losing++;
1963 }
1964 break;
1965
1966 case 'R':
1967 if (opP->mode != DREG && opP->mode != AREG)
1968 losing++;
1969 break;
1970
1971 case 'r':
1972 if (opP->mode != AINDR && opP->mode != DINDR)
1973 losing++;
1974 break;
1975
1976 case 's':
1977 if (opP->mode != MSCR || !(opP->reg == FPI || opP->reg == FPS || opP->reg == FPC))
1978 losing++;
1979 break;
1980
1981 case 'S':
1982 if (opP->mode != MSCR || opP->reg != SR)
1983 losing++;
1984 break;
1985
1986 case 't':
1987 if (opP->mode != IMMED)
1988 losing++;
1989 else
1990 {
1991 long t = get_num (opP->con1, 80);
1992 if (t < 0 || t > 7 || isvar (opP->con1))
1993 losing++;
1994 }
1995 break;
1996
1997 case 'U':
1998 if (opP->mode != MSCR || opP->reg != USP)
1999 losing++;
2000 break;
2001
2002 /* JF these are out of order. We could put them
2003 in order if we were willing to put up with
2004 bunches of #ifdef m68851s in the code.
2005
2006 Don't forget that you need these operands
2007 to use 68030 MMU instructions. */
2008 #ifndef NO_68851
2009 /* Memory addressing mode used by pflushr */
2010 case '|':
2011 if (opP->mode == MSCR || opP->mode == DREG ||
2012 opP->mode == AREG || opP->mode == REGLST)
2013 losing++;
2014 break;
2015
2016 case 'f':
2017 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
2018 losing++;
2019 break;
2020
2021 case 'P':
2022 if (opP->mode != MSCR
2023 || (opP->reg != TC && opP->reg != CAL
2024 && opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
2025 losing++;
2026 break;
2027
2028 case 'V':
2029 if (opP->reg != VAL)
2030 losing++;
2031 break;
2032
2033 case 'W':
2034 if (opP->mode != MSCR
2035 || (opP->reg != DRP && opP->reg != SRP
2036 && opP->reg != CRP))
2037 losing++;
2038 break;
2039
2040 case 'X':
2041 if (opP->mode != MSCR ||
2042 (!(opP->reg >= BAD && opP->reg <= BAD + 7) &&
2043 !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2044 losing++;
2045 break;
2046
2047 case 'Y':
2048 if (opP->reg != PSR)
2049 losing++;
2050 break;
2051
2052 case 'Z':
2053 if (opP->reg != PCSR)
2054 losing++;
2055 break;
2056 #endif
2057 case 'c':
2058 if (opP->reg != NC
2059 && opP->reg != IC
2060 && opP->reg != DC
2061 && opP->reg != BC)
2062 {
2063 losing++;
2064 } /* not a cache specifier. */
2065 break;
2066
2067 case '_':
2068 if (opP->mode != ABSL)
2069 {
2070 ++losing;
2071 } /* not absolute */
2072 break;
2073
2074 default:
2075 as_fatal ("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
2076 *s, __LINE__, __FILE__);
2077 } /* switch on type of operand */
2078
2079 if (losing)
2080 break;
2081 } /* for each operand */
2082 } /* if immediately wrong */
2083
2084 if (!losing)
2085 {
2086 break;
2087 } /* got it. */
2088
2089 opcode = opcode->m_next;
2090
2091 if (!opcode)
2092 {
2093 if (ok_arch
2094 && !(ok_arch & current_architecture))
2095 {
2096 char buf[200], *cp;
2097 int len;
2098 strcpy (buf, "invalid instruction for this architecture; needs ");
2099 cp = buf + strlen (buf);
2100 switch (ok_arch)
2101 {
2102 case mfloat:
2103 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
2104 break;
2105 case mmmu:
2106 strcpy (cp, "mmu (68030 or 68851)");
2107 break;
2108 case m68020up:
2109 strcpy (cp, "68020 or higher");
2110 break;
2111 case m68000up:
2112 strcpy (cp, "68000 or higher");
2113 break;
2114 case m68010up:
2115 strcpy (cp, "68010 or higher");
2116 break;
2117 default:
2118 {
2119 int got_one = 0, idx;
2120 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]); idx++)
2121 {
2122 if (archs[idx].arch & ok_arch)
2123 {
2124 if (got_one)
2125 {
2126 strcpy (cp, " or ");
2127 cp += strlen (cp);
2128 }
2129 got_one = 1;
2130 strcpy (cp, archs[idx].name);
2131 cp += strlen (cp);
2132 }
2133 }
2134 }
2135 }
2136 len = cp - buf + 1;
2137 cp = malloc (len);
2138 strcpy (cp, buf);
2139 the_ins.error = cp;
2140 }
2141 else
2142 the_ins.error = "operands mismatch";
2143 return;
2144 } /* Fell off the end */
2145
2146 losing = 0;
2147 }
2148
2149 /* now assemble it */
2150
2151 the_ins.args = opcode->m_operands;
2152 the_ins.numargs = opcode->m_opnum;
2153 the_ins.numo = opcode->m_codenum;
2154 the_ins.opcode[0] = getone (opcode);
2155 the_ins.opcode[1] = gettwo (opcode);
2156
2157 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2158 {
2159 /* This switch is a doozy.
2160 Watch the first step; its a big one! */
2161 switch (s[0])
2162 {
2163
2164 case '*':
2165 case '~':
2166 case '%':
2167 case ';':
2168 case '@':
2169 case '!':
2170 case '&':
2171 case '$':
2172 case '?':
2173 case '/':
2174 case '`':
2175 #ifndef NO_68851
2176 case '|':
2177 #endif
2178 switch (opP->mode)
2179 {
2180 case IMMED:
2181 tmpreg = 0x3c; /* 7.4 */
2182 if (strchr ("bwl", s[1]))
2183 nextword = get_num (opP->con1, 80);
2184 else
2185 nextword = get_num (opP->con1, 0);
2186 if (isvar (opP->con1))
2187 add_fix (s[1], opP->con1, 0);
2188 switch (s[1])
2189 {
2190 case 'b':
2191 if (!isbyte (nextword))
2192 opP->error = "operand out of range";
2193 addword (nextword);
2194 baseo = 0;
2195 break;
2196 case 'w':
2197 if (!isword (nextword))
2198 opP->error = "operand out of range";
2199 addword (nextword);
2200 baseo = 0;
2201 break;
2202 case 'l':
2203 addword (nextword >> 16);
2204 addword (nextword);
2205 baseo = 0;
2206 break;
2207
2208 case 'f':
2209 baseo = 2;
2210 outro = 8;
2211 break;
2212 case 'F':
2213 baseo = 4;
2214 outro = 11;
2215 break;
2216 case 'x':
2217 baseo = 6;
2218 outro = 15;
2219 break;
2220 case 'p':
2221 baseo = 6;
2222 outro = -1;
2223 break;
2224 default:
2225 as_fatal ("Internal error: Can't decode %c%c in line %d of file \"%s\"",
2226 *s, s[1], __LINE__, __FILE__);
2227 }
2228 if (!baseo)
2229 break;
2230
2231 /* We gotta put out some float */
2232 if (op (opP->con1) != O_big)
2233 {
2234 valueT val;
2235 int gencnt;
2236
2237 /* Can other cases happen here? */
2238 if (op (opP->con1) != O_constant)
2239 abort ();
2240
2241 val = (valueT) offs (opP->con1);
2242 gencnt = 0;
2243 do
2244 {
2245 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2246 val >>= LITTLENUM_NUMBER_OF_BITS;
2247 ++gencnt;
2248 }
2249 while (val != 0);
2250 offs (opP->con1) = gencnt;
2251 }
2252 if (offs (opP->con1) > 0)
2253 {
2254 if (offs (opP->con1) > baseo)
2255 {
2256 as_warn ("Bignum too big for %c format; truncated", s[1]);
2257 offs (opP->con1) = baseo;
2258 }
2259 baseo -= offs (opP->con1);
2260 while (baseo--)
2261 addword (0);
2262 for (wordp = generic_bignum + offs (opP->con1) - 1; offs (opP->con1)--; --wordp)
2263 addword (*wordp);
2264 break;
2265 }
2266 gen_to_words (words, baseo, (long) outro);
2267 for (wordp = words; baseo--; wordp++)
2268 addword (*wordp);
2269 break;
2270 case DREG:
2271 tmpreg = opP->reg - DATA; /* 0.dreg */
2272 break;
2273 case AREG:
2274 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2275 break;
2276 case AINDR:
2277 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2278 break;
2279 case ADEC:
2280 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2281 break;
2282 case AINC:
2283 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2284 break;
2285 case AOFF:
2286
2287 nextword = get_num (opP->con1, 80);
2288 /* Force into index mode. Hope this works */
2289
2290 /* We do the first bit for 32-bit displacements, and the
2291 second bit for 16 bit ones. It is possible that we
2292 should make the default be WORD instead of LONG, but
2293 I think that'd break GCC, so we put up with a little
2294 inefficiency for the sake of working output. */
2295
2296 if (!issword (nextword)
2297 || (isvar (opP->con1)
2298 && ((opP->con1->e_siz == 0
2299 && flag_short_refs == 0
2300 && cpu_of_arch (current_architecture) >= m68020)
2301 || opP->con1->e_siz == 3)))
2302 {
2303
2304 if (opP->reg == PC)
2305 tmpreg = 0x3B; /* 7.3 */
2306 else
2307 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2308 if (isvar (opP->con1))
2309 {
2310 if (opP->reg == PC)
2311 {
2312 addword (0x0170);
2313 opP->con1->e_exp.X_add_number += 6;
2314 add_fix ('l', opP->con1, 1);
2315 addword (0), addword (0);
2316 break;
2317 }
2318 else
2319 {
2320 addword (0x0170);
2321 add_fix ('l', opP->con1, 0);
2322 }
2323 }
2324 else
2325 addword (0x0170);
2326 addword (nextword >> 16);
2327 }
2328 else
2329 {
2330 if (opP->reg == PC)
2331 tmpreg = 0x3A; /* 7.2 */
2332 else
2333 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2334
2335 if (isvar (opP->con1))
2336 {
2337 if (opP->reg == PC)
2338 {
2339 opP->con1->e_exp.X_add_number += 2;
2340 add_fix ('w', opP->con1, 1);
2341 }
2342 else
2343 add_fix ('w', opP->con1, 0);
2344 }
2345 }
2346 addword (nextword);
2347 break;
2348
2349 case APODX:
2350 case AMIND:
2351 case APRDX:
2352 know (current_architecture & m68020up);
2353 /* intentional fall-through */
2354 case AINDX:
2355 nextword = 0;
2356 baseo = get_num (opP->con1, 80);
2357 outro = get_num (opP->con2, 80);
2358 /* Figure out the `addressing mode'.
2359 Also turn on the BASE_DISABLE bit, if needed. */
2360 if (opP->reg == PC || opP->reg == ZPC)
2361 {
2362 tmpreg = 0x3b;/* 7.3 */
2363 if (opP->reg == ZPC)
2364 nextword |= 0x80;
2365 }
2366 else if (opP->reg == FAIL)
2367 {
2368 nextword |= 0x80;
2369 tmpreg = 0x30;/* 6.garbage */
2370 }
2371 else
2372 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2373
2374 siz1 = (opP->con1) ? opP->con1->e_siz : 0;
2375 siz2 = (opP->con2) ? opP->con2->e_siz : 0;
2376
2377 /* Index register stuff */
2378 if (opP->ireg >= DATA + 0 && opP->ireg <= ADDR + 7)
2379 {
2380 nextword |= (opP->ireg - DATA) << 12;
2381
2382 if (opP->isiz == 0 || opP->isiz == 3)
2383 nextword |= 0x800;
2384 switch (opP->imul)
2385 {
2386 case 1:
2387 break;
2388 case 2:
2389 nextword |= 0x200;
2390 break;
2391 case 4:
2392 nextword |= 0x400;
2393 break;
2394 case 8:
2395 nextword |= 0x600;
2396 break;
2397 default:
2398 as_fatal ("failed sanity check.");
2399 }
2400 /* IF its simple,
2401 GET US OUT OF HERE! */
2402
2403 /* Must be INDEX, with an index
2404 register. Address register
2405 cannot be ZERO-PC, and either
2406 :b was forced, or we know
2407 it will fit */
2408 if (opP->mode == AINDX
2409 && opP->reg != FAIL
2410 && opP->reg != ZPC
2411 && (siz1 == 1
2412 || cpu_of_arch (current_architecture) < m68020
2413 || (issbyte (baseo)
2414 && !isvar (opP->con1))))
2415 {
2416 nextword += baseo & 0xff;
2417 addword (nextword);
2418 if (isvar (opP->con1))
2419 add_fix ('B', opP->con1, 0);
2420 break;
2421 }
2422 }
2423 else
2424 nextword |= 0x40; /* No index reg */
2425
2426 /* It isn't simple. */
2427 nextword |= 0x100;
2428 /* If the guy specified a width, we assume that it is
2429 wide enough. Maybe it isn't. If so, we lose. */
2430 switch (siz1)
2431 {
2432 case 0:
2433 if (isvar (opP->con1) || !issword (baseo))
2434 {
2435 siz1 = 3;
2436 nextword |= 0x30;
2437 }
2438 else if (baseo == 0)
2439 nextword |= 0x10;
2440 else
2441 {
2442 nextword |= 0x20;
2443 siz1 = 2;
2444 }
2445 break;
2446 case 1:
2447 as_warn ("Byte dispacement won't work. Defaulting to :w");
2448 case 2:
2449 nextword |= 0x20;
2450 break;
2451 case 3:
2452 nextword |= 0x30;
2453 break;
2454 }
2455
2456 /* Figure out innner displacement stuff */
2457 if (opP->mode != AINDX)
2458 {
2459 switch (siz2)
2460 {
2461 case 0:
2462 if (isvar (opP->con2) || !issword (outro))
2463 {
2464 siz2 = 3;
2465 nextword |= 0x3;
2466 }
2467 else if (outro == 0)
2468 nextword |= 0x1;
2469 else
2470 {
2471 nextword |= 0x2;
2472 siz2 = 2;
2473 }
2474 break;
2475 case 1:
2476 as_warn ("Byte dispacement won't work. Defaulting to :w");
2477 case 2:
2478 nextword |= 0x2;
2479 break;
2480 case 3:
2481 nextword |= 0x3;
2482 break;
2483 }
2484 if (opP->mode == APODX)
2485 nextword |= 0x04;
2486 else if (opP->mode == AMIND)
2487 nextword |= 0x40;
2488 }
2489 addword (nextword);
2490
2491 if (isvar (opP->con1))
2492 {
2493 if (opP->reg == PC || opP->reg == ZPC)
2494 {
2495 opP->con1->e_exp.X_add_number += 6;
2496 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 1);
2497 }
2498 else
2499 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 0);
2500 }
2501 if (siz1 == 3)
2502 addword (baseo >> 16);
2503 if (siz1)
2504 addword (baseo);
2505
2506 if (isvar (opP->con2))
2507 {
2508 if (opP->reg == PC || opP->reg == ZPC)
2509 {
2510 opP->con1->e_exp.X_add_number += 6;
2511 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 1);
2512 }
2513 else
2514 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 0);
2515 }
2516 if (siz2 == 3)
2517 addword (outro >> 16);
2518 if (siz2)
2519 addword (outro);
2520
2521 break;
2522
2523 case ABSL:
2524 nextword = get_num (opP->con1, 80);
2525 switch (opP->con1->e_siz)
2526 {
2527 default:
2528 as_warn ("Unknown size for absolute reference");
2529 case 0:
2530 if (!isvar (opP->con1) && issword (offs (opP->con1)))
2531 {
2532 tmpreg = 0x38; /* 7.0 */
2533 addword (nextword);
2534 break;
2535 }
2536 /* Don't generate pc relative code on 68010 and
2537 68000. */
2538 if (isvar (opP->con1)
2539 && !subs (opP->con1)
2540 && seg (opP->con1) == text_section
2541 && now_seg == text_section
2542 && cpu_of_arch (current_architecture) >= m68020
2543 && !flag_long_jumps
2544 && !strchr ("~%&$?", s[0]))
2545 {
2546 tmpreg = 0x3A; /* 7.2 */
2547 add_frag (adds (opP->con1),
2548 offs (opP->con1),
2549 TAB (PCREL, SZ_UNDEF));
2550 break;
2551 }
2552 case 3: /* Fall through into long */
2553 if (isvar (opP->con1))
2554 add_fix ('l', opP->con1, 0);
2555
2556 tmpreg = 0x39;/* 7.1 mode */
2557 addword (nextword >> 16);
2558 addword (nextword);
2559 break;
2560
2561 case 2: /* Word */
2562 if (isvar (opP->con1))
2563 add_fix ('w', opP->con1, 0);
2564
2565 tmpreg = 0x38;/* 7.0 mode */
2566 addword (nextword);
2567 break;
2568 }
2569 break;
2570 case DINDR:
2571 as_bad ("invalid indirect register");
2572 break;
2573 case MSCR:
2574 default:
2575 as_bad ("unknown/incorrect operand");
2576 /* abort(); */
2577 }
2578 install_gen_operand (s[1], tmpreg);
2579 break;
2580
2581 case '#':
2582 case '^':
2583 switch (s[1])
2584 { /* JF: I hate floating point! */
2585 case 'j':
2586 tmpreg = 70;
2587 break;
2588 case '8':
2589 tmpreg = 20;
2590 break;
2591 case 'C':
2592 tmpreg = 50;
2593 break;
2594 case '3':
2595 default:
2596 tmpreg = 80;
2597 break;
2598 }
2599 tmpreg = get_num (opP->con1, tmpreg);
2600 if (isvar (opP->con1))
2601 add_fix (s[1], opP->con1, 0);
2602 switch (s[1])
2603 {
2604 case 'b': /* Danger: These do no check for
2605 certain types of overflow.
2606 user beware! */
2607 if (!isbyte (tmpreg))
2608 opP->error = "out of range";
2609 insop (tmpreg, opcode);
2610 if (isvar (opP->con1))
2611 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2612 break;
2613 case 'w':
2614 if (!isword (tmpreg))
2615 opP->error = "out of range";
2616 insop (tmpreg, opcode);
2617 if (isvar (opP->con1))
2618 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2619 break;
2620 case 'l':
2621 /* Because of the way insop works, we put these two out
2622 backwards. */
2623 insop (tmpreg, opcode);
2624 insop (tmpreg >> 16, opcode);
2625 if (isvar (opP->con1))
2626 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2627 break;
2628 case '3':
2629 tmpreg &= 0xFF;
2630 case '8':
2631 case 'C':
2632 install_operand (s[1], tmpreg);
2633 break;
2634 default:
2635 as_fatal ("Internal error: Unknown mode #%c in line %d of file \"%s\"", s[1], __LINE__, __FILE__);
2636 }
2637 break;
2638
2639 case '+':
2640 case '-':
2641 case 'A':
2642 case 'a':
2643 install_operand (s[1], opP->reg - ADDR);
2644 break;
2645
2646 case 'B':
2647 tmpreg = get_num (opP->con1, 80);
2648 switch (s[1])
2649 {
2650 case 'B':
2651 /* Needs no offsetting */
2652 add_fix ('B', opP->con1, 1);
2653 break;
2654 case 'W':
2655 /* Offset the displacement to be relative to byte disp location */
2656 opP->con1->e_exp.X_add_number += 2;
2657 add_fix ('w', opP->con1, 1);
2658 addword (0);
2659 break;
2660 case 'L':
2661 long_branch:
2662 if (cpu_of_arch (current_architecture) < m68020) /* 68000 or 010 */
2663 as_warn ("Can't use long branches on 68000/68010");
2664 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2665 /* Offset the displacement to be relative to byte disp location */
2666 opP->con1->e_exp.X_add_number += 4;
2667 add_fix ('l', opP->con1, 1);
2668 addword (0);
2669 addword (0);
2670 break;
2671 case 'g':
2672 if (subs (opP->con1)) /* We can't relax it */
2673 goto long_branch;
2674
2675 /* This could either be a symbol, or an
2676 absolute address. No matter, the
2677 frag hacking will finger it out.
2678 Not quite: it can't switch from
2679 BRANCH to BCC68000 for the case
2680 where opnd is absolute (it needs
2681 to use the 68000 hack since no
2682 conditional abs jumps). */
2683 if (((cpu_of_arch (current_architecture) < m68020)
2684 || (0 == adds (opP->con1)))
2685 && (the_ins.opcode[0] >= 0x6200)
2686 && (the_ins.opcode[0] <= 0x6f00))
2687 {
2688 add_frag (adds (opP->con1), offs (opP->con1), TAB (BCC68000, SZ_UNDEF));
2689 }
2690 else
2691 {
2692 add_frag (adds (opP->con1), offs (opP->con1), TAB (ABRANCH, SZ_UNDEF));
2693 }
2694 break;
2695 case 'w':
2696 if (isvar (opP->con1))
2697 {
2698 #if 1
2699 /* check for DBcc instruction */
2700 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2701 {
2702 /* size varies if patch */
2703 /* needed for long form */
2704 add_frag (adds (opP->con1), offs (opP->con1),
2705 TAB (DBCC, SZ_UNDEF));
2706 break;
2707 }
2708 #endif
2709 /* Don't ask! */
2710 opP->con1->e_exp.X_add_number += 2;
2711 add_fix ('w', opP->con1, 1);
2712 }
2713 addword (0);
2714 break;
2715 case 'C': /* Fixed size LONG coproc branches */
2716 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2717 /* Offset the displacement to be relative to byte disp location */
2718 /* Coproc branches don't have a byte disp option, but they are
2719 compatible with the ordinary branches, which do... */
2720 opP->con1->e_exp.X_add_number += 4;
2721 add_fix ('l', opP->con1, 1);
2722 addword (0);
2723 addword (0);
2724 break;
2725 case 'c': /* Var size Coprocesssor branches */
2726 if (subs (opP->con1))
2727 {
2728 add_fix ('l', opP->con1, 1);
2729 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2730 }
2731 else if (adds (opP->con1))
2732 {
2733 add_frag (adds (opP->con1), offs (opP->con1), TAB (FBRANCH, SZ_UNDEF));
2734 }
2735 else
2736 {
2737 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2738 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2739 add_fix ('l', opP->con1, 1);
2740 addword (0);
2741 addword (4);
2742 }
2743 break;
2744 default:
2745 as_fatal ("Internal error: operand type B%c unknown in line %d of file \"%s\"",
2746 s[1], __LINE__, __FILE__);
2747 }
2748 break;
2749
2750 case 'C': /* Ignore it */
2751 break;
2752
2753 case 'd': /* JF this is a kludge */
2754 if (opP->mode == AOFF)
2755 {
2756 install_operand ('s', opP->reg - ADDR);
2757 }
2758 else
2759 {
2760 char *tmpP;
2761
2762 tmpP = opP->con1->e_end - 2;
2763 opP->con1->e_beg++;
2764 opP->con1->e_end -= 4; /* point to the , */
2765 baseo = m68k_reg_parse (&tmpP);
2766 if (baseo < ADDR + 0 || baseo > ADDR + 7)
2767 {
2768 as_bad ("Unknown address reg, using A0");
2769 baseo = 0;
2770 }
2771 else
2772 baseo -= ADDR;
2773 install_operand ('s', baseo);
2774 }
2775 tmpreg = get_num (opP->con1, 80);
2776 if (!issword (tmpreg))
2777 {
2778 as_warn ("Expression out of range, using 0");
2779 tmpreg = 0;
2780 }
2781 addword (tmpreg);
2782 break;
2783
2784 case 'D':
2785 install_operand (s[1], opP->reg - DATA);
2786 break;
2787
2788 case 'F':
2789 install_operand (s[1], opP->reg - FPREG);
2790 break;
2791
2792 case 'I':
2793 tmpreg = 1 + opP->reg - COPNUM;
2794 if (tmpreg == 8)
2795 tmpreg = 0;
2796 install_operand (s[1], tmpreg);
2797 break;
2798
2799 case 'J': /* JF foo */
2800 switch (opP->reg)
2801 {
2802 case SFC:
2803 tmpreg = 0x000;
2804 break;
2805 case DFC:
2806 tmpreg = 0x001;
2807 break;
2808 case CACR:
2809 tmpreg = 0x002;
2810 break;
2811 case TC:
2812 tmpreg = 0x003;
2813 break;
2814 case ITT0:
2815 tmpreg = 0x004;
2816 break;
2817 case ITT1:
2818 tmpreg = 0x005;
2819 break;
2820 case DTT0:
2821 tmpreg = 0x006;
2822 break;
2823 case DTT1:
2824 tmpreg = 0x007;
2825 break;
2826 case BUSCR:
2827 tmpreg = 0x008;
2828 break;
2829
2830 case USP:
2831 tmpreg = 0x800;
2832 break;
2833 case VBR:
2834 tmpreg = 0x801;
2835 break;
2836 case CAAR:
2837 tmpreg = 0x802;
2838 break;
2839 case MSP:
2840 tmpreg = 0x803;
2841 break;
2842 case ISP:
2843 tmpreg = 0x804;
2844 break;
2845 case MMUSR:
2846 tmpreg = 0x805;
2847 break;
2848 case URP:
2849 tmpreg = 0x806;
2850 break;
2851 case SRP:
2852 tmpreg = 0x807;
2853 break;
2854 case PCR:
2855 tmpreg = 0x808;
2856 break;
2857 default:
2858 as_fatal ("failed sanity check.");
2859 }
2860 install_operand (s[1], tmpreg);
2861 break;
2862
2863 case 'k':
2864 tmpreg = get_num (opP->con1, 55);
2865 install_operand (s[1], tmpreg & 0x7f);
2866 break;
2867
2868 case 'l':
2869 tmpreg = opP->reg;
2870 if (s[1] == 'w')
2871 {
2872 if (tmpreg & 0x7FF0000)
2873 as_bad ("Floating point register in register list");
2874 insop (reverse_16_bits (tmpreg), opcode);
2875 }
2876 else
2877 {
2878 if (tmpreg & 0x700FFFF)
2879 as_bad ("Wrong register in floating-point reglist");
2880 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2881 }
2882 break;
2883
2884 case 'L':
2885 tmpreg = opP->reg;
2886 if (s[1] == 'w')
2887 {
2888 if (tmpreg & 0x7FF0000)
2889 as_bad ("Floating point register in register list");
2890 insop (tmpreg, opcode);
2891 }
2892 else if (s[1] == '8')
2893 {
2894 if (tmpreg & 0x0FFFFFF)
2895 as_bad ("incorrect register in reglist");
2896 install_operand (s[1], tmpreg >> 24);
2897 }
2898 else
2899 {
2900 if (tmpreg & 0x700FFFF)
2901 as_bad ("wrong register in floating-point reglist");
2902 else
2903 install_operand (s[1], tmpreg >> 16);
2904 }
2905 break;
2906
2907 case 'M':
2908 install_operand (s[1], get_num (opP->con1, 60));
2909 break;
2910
2911 case 'O':
2912 tmpreg = (opP->mode == DREG)
2913 ? 0x20 + opP->reg - DATA
2914 : (get_num (opP->con1, 40) & 0x1F);
2915 install_operand (s[1], tmpreg);
2916 break;
2917
2918 case 'Q':
2919 tmpreg = get_num (opP->con1, 10);
2920 if (tmpreg == 8)
2921 tmpreg = 0;
2922 install_operand (s[1], tmpreg);
2923 break;
2924
2925 case 'R':
2926 case 'r':
2927 /* This depends on the fact that ADDR registers are
2928 eight more than their corresponding DATA regs, so
2929 the result will have the ADDR_REG bit set */
2930 install_operand (s[1], opP->reg - DATA);
2931 break;
2932
2933 case 's':
2934 if (opP->reg == FPI)
2935 tmpreg = 0x1;
2936 else if (opP->reg == FPS)
2937 tmpreg = 0x2;
2938 else if (opP->reg == FPC)
2939 tmpreg = 0x4;
2940 else
2941 as_fatal ("failed sanity check.");
2942 install_operand (s[1], tmpreg);
2943 break;
2944
2945 case 'S': /* Ignore it */
2946 break;
2947
2948 case 'T':
2949 install_operand (s[1], get_num (opP->con1, 30));
2950 break;
2951
2952 case 'U': /* Ignore it */
2953 break;
2954
2955 case 'c':
2956 switch (opP->reg)
2957 {
2958 case NC:
2959 tmpreg = 0;
2960 break;
2961 case DC:
2962 tmpreg = 1;
2963 break;
2964 case IC:
2965 tmpreg = 2;
2966 break;
2967 case BC:
2968 tmpreg = 3;
2969 break;
2970 default:
2971 as_fatal ("failed sanity check");
2972 } /* switch on cache token */
2973 install_operand (s[1], tmpreg);
2974 break;
2975 #ifndef NO_68851
2976 /* JF: These are out of order, I fear. */
2977 case 'f':
2978 switch (opP->reg)
2979 {
2980 case SFC:
2981 tmpreg = 0;
2982 break;
2983 case DFC:
2984 tmpreg = 1;
2985 break;
2986 default:
2987 as_fatal ("failed sanity check.");
2988 }
2989 install_operand (s[1], tmpreg);
2990 break;
2991
2992 case 'P':
2993 switch (opP->reg)
2994 {
2995 case TC:
2996 tmpreg = 0;
2997 break;
2998 case CAL:
2999 tmpreg = 4;
3000 break;
3001 case VAL:
3002 tmpreg = 5;
3003 break;
3004 case SCC:
3005 tmpreg = 6;
3006 break;
3007 case AC:
3008 tmpreg = 7;
3009 break;
3010 default:
3011 as_fatal ("failed sanity check.");
3012 }
3013 install_operand (s[1], tmpreg);
3014 break;
3015
3016 case 'V':
3017 if (opP->reg == VAL)
3018 break;
3019 as_fatal ("failed sanity check.");
3020
3021 case 'W':
3022 switch (opP->reg)
3023 {
3024
3025 case DRP:
3026 tmpreg = 1;
3027 break;
3028 case SRP:
3029 tmpreg = 2;
3030 break;
3031 case CRP:
3032 tmpreg = 3;
3033 break;
3034 default:
3035 as_fatal ("failed sanity check.");
3036 }
3037 install_operand (s[1], tmpreg);
3038 break;
3039
3040 case 'X':
3041 switch (opP->reg)
3042 {
3043 case BAD:
3044 case BAD + 1:
3045 case BAD + 2:
3046 case BAD + 3:
3047 case BAD + 4:
3048 case BAD + 5:
3049 case BAD + 6:
3050 case BAD + 7:
3051 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3052 break;
3053
3054 case BAC:
3055 case BAC + 1:
3056 case BAC + 2:
3057 case BAC + 3:
3058 case BAC + 4:
3059 case BAC + 5:
3060 case BAC + 6:
3061 case BAC + 7:
3062 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3063 break;
3064
3065 default:
3066 as_fatal ("failed sanity check.");
3067 }
3068 install_operand (s[1], tmpreg);
3069 break;
3070 case 'Y':
3071 know (opP->reg == PSR);
3072 break;
3073 case 'Z':
3074 know (opP->reg == PCSR);
3075 break;
3076 #endif /* m68851 */
3077 case '3':
3078 switch (opP->reg)
3079 {
3080 case TT0:
3081 tmpreg = 2;
3082 break;
3083 case TT1:
3084 tmpreg = 3;
3085 break;
3086 default:
3087 as_fatal ("failed sanity check");
3088 }
3089 install_operand (s[1], tmpreg);
3090 break;
3091 case 't':
3092 tmpreg = get_num (opP->con1, 20);
3093 install_operand (s[1], tmpreg);
3094 break;
3095 case '_': /* used only for move16 absolute 32-bit address */
3096 tmpreg = get_num (opP->con1, 80);
3097 addword (tmpreg >> 16);
3098 addword (tmpreg & 0xFFFF);
3099 break;
3100 default:
3101 as_fatal ("Internal error: Operand type %c unknown in line %d of file \"%s\"",
3102 s[0], __LINE__, __FILE__);
3103 }
3104 }
3105
3106 /* By the time whe get here (FINALLY) the_ins contains the complete
3107 instruction, ready to be emitted. . . */
3108 } /* m68k_ip() */
3109
3110 /*
3111 * get_regs := '/' + ?
3112 * | '-' + <register>
3113 * | '-' + <register> + ?
3114 * | <empty>
3115 * ;
3116 *
3117
3118 * The idea here must be to scan in a set of registers but I don't
3119 * understand it. Looks awfully sloppy to me but I don't have any doc on
3120 * this format so...
3121
3122 *
3123 *
3124 */
3125
3126 static int
3127 get_regs (i, str, opP)
3128 int i;
3129 struct m68k_op *opP;
3130 char *str;
3131 {
3132 /* 26, 25, 24, 23-16, 15-8, 0-7 */
3133 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
3134 unsigned long cur_regs = 0;
3135 int reg1, reg2;
3136
3137 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
3138 else if(x==FPS) cur_regs|=(1<<25);\
3139 else if(x==FPC) cur_regs|=(1<<26);\
3140 else cur_regs|=(1<<(x-1)); }
3141
3142 reg1 = i;
3143 for (;;)
3144 {
3145 if (*str == '/')
3146 {
3147 ADD_REG (reg1);
3148 str++;
3149 }
3150 else if (*str == '-')
3151 {
3152 str++;
3153 reg2 = m68k_reg_parse (&str);
3154 if (reg2 < DATA || reg2 >= FPREG + 8 || reg1 == FPI || reg1 == FPS || reg1 == FPC)
3155 {
3156 opP->error = "unknown register in register list";
3157 return FAIL;
3158 }
3159 while (reg1 <= reg2)
3160 {
3161 ADD_REG (reg1);
3162 reg1++;
3163 }
3164 if (*str == '\0')
3165 break;
3166 }
3167 else if (*str == '\0')
3168 {
3169 ADD_REG (reg1);
3170 break;
3171 }
3172 else
3173 {
3174 opP->error = "unknow character in register list";
3175 return FAIL;
3176 }
3177 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
3178 if (*str == '/')
3179 str++;
3180 reg1 = m68k_reg_parse (&str);
3181 if ((reg1 < DATA || reg1 >= FPREG + 8) && !(reg1 == FPI || reg1 == FPS || reg1 == FPC))
3182 {
3183 opP->error = "unknown register in register list";
3184 return FAIL;
3185 }
3186 }
3187 opP->reg = cur_regs;
3188 return OK;
3189 } /* get_regs() */
3190
3191 static int
3192 reverse_16_bits (in)
3193 int in;
3194 {
3195 int out = 0;
3196 int n;
3197
3198 static int mask[16] =
3199 {
3200 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3201 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3202 };
3203 for (n = 0; n < 16; n++)
3204 {
3205 if (in & mask[n])
3206 out |= mask[15 - n];
3207 }
3208 return out;
3209 } /* reverse_16_bits() */
3210
3211 static int
3212 reverse_8_bits (in)
3213 int in;
3214 {
3215 int out = 0;
3216 int n;
3217
3218 static int mask[8] =
3219 {
3220 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3221 };
3222
3223 for (n = 0; n < 8; n++)
3224 {
3225 if (in & mask[n])
3226 out |= mask[7 - n];
3227 }
3228 return out;
3229 } /* reverse_8_bits() */
3230
3231 static void
3232 install_operand (mode, val)
3233 int mode;
3234 int val;
3235 {
3236 switch (mode)
3237 {
3238 case 's':
3239 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3240 break;
3241 case 'd':
3242 the_ins.opcode[0] |= val << 9;
3243 break;
3244 case '1':
3245 the_ins.opcode[1] |= val << 12;
3246 break;
3247 case '2':
3248 the_ins.opcode[1] |= val << 6;
3249 break;
3250 case '3':
3251 the_ins.opcode[1] |= val;
3252 break;
3253 case '4':
3254 the_ins.opcode[2] |= val << 12;
3255 break;
3256 case '5':
3257 the_ins.opcode[2] |= val << 6;
3258 break;
3259 case '6':
3260 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3261 three words long! */
3262 the_ins.numo++;
3263 the_ins.opcode[2] |= val;
3264 break;
3265 case '7':
3266 the_ins.opcode[1] |= val << 7;
3267 break;
3268 case '8':
3269 the_ins.opcode[1] |= val << 10;
3270 break;
3271 #ifndef NO_68851
3272 case '9':
3273 the_ins.opcode[1] |= val << 5;
3274 break;
3275 #endif
3276
3277 case 't':
3278 the_ins.opcode[1] |= (val << 10) | (val << 7);
3279 break;
3280 case 'D':
3281 the_ins.opcode[1] |= (val << 12) | val;
3282 break;
3283 case 'g':
3284 the_ins.opcode[0] |= val = 0xff;
3285 break;
3286 case 'i':
3287 the_ins.opcode[0] |= val << 9;
3288 break;
3289 case 'C':
3290 the_ins.opcode[1] |= val;
3291 break;
3292 case 'j':
3293 the_ins.opcode[1] |= val;
3294 the_ins.numo++; /* What a hack */
3295 break;
3296 case 'k':
3297 the_ins.opcode[1] |= val << 4;
3298 break;
3299 case 'b':
3300 case 'w':
3301 case 'l':
3302 break;
3303 case 'e':
3304 the_ins.opcode[0] |= (val << 6);
3305 break;
3306 case 'L':
3307 the_ins.opcode[1] = (val >> 16);
3308 the_ins.opcode[2] = val & 0xffff;
3309 break;
3310 case 'c':
3311 default:
3312 as_fatal ("failed sanity check.");
3313 }
3314 } /* install_operand() */
3315
3316 static void
3317 install_gen_operand (mode, val)
3318 int mode;
3319 int val;
3320 {
3321 switch (mode)
3322 {
3323 case 's':
3324 the_ins.opcode[0] |= val;
3325 break;
3326 case 'd':
3327 /* This is a kludge!!! */
3328 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3329 break;
3330 case 'b':
3331 case 'w':
3332 case 'l':
3333 case 'f':
3334 case 'F':
3335 case 'x':
3336 case 'p':
3337 the_ins.opcode[0] |= val;
3338 break;
3339 /* more stuff goes here */
3340 default:
3341 as_fatal ("failed sanity check.");
3342 }
3343 } /* install_gen_operand() */
3344
3345 /*
3346 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3347 * then deal with the bitfield hack.
3348 */
3349
3350 static char *
3351 crack_operand (str, opP)
3352 register char *str;
3353 register struct m68k_op *opP;
3354 {
3355 register int parens;
3356 register int c;
3357 register char *beg_str;
3358
3359 if (!str)
3360 {
3361 return str;
3362 }
3363 beg_str = str;
3364 for (parens = 0; *str && (parens > 0 || notend (str)); str++)
3365 {
3366 if (*str == '(')
3367 parens++;
3368 else if (*str == ')')
3369 {
3370 if (!parens)
3371 { /* ERROR */
3372 opP->error = "Extra )";
3373 return str;
3374 }
3375 --parens;
3376 }
3377 }
3378 if (!*str && parens)
3379 { /* ERROR */
3380 opP->error = "Missing )";
3381 return str;
3382 }
3383 c = *str;
3384 *str = '\0';
3385 if (m68k_ip_op (beg_str, opP) == FAIL)
3386 {
3387 *str = c;
3388 return str;
3389 }
3390 *str = c;
3391 if (c == '}')
3392 c = *++str; /* JF bitfield hack */
3393 if (c)
3394 {
3395 c = *++str;
3396 if (!c)
3397 as_bad ("Missing operand");
3398 }
3399 return str;
3400 }
3401
3402 /* This is the guts of the machine-dependent assembler. STR points to a
3403 machine dependent instruction. This function is supposed to emit
3404 the frags/bytes it assembles to.
3405 */
3406
3407 void
3408 insert_reg (regname, regnum)
3409 char *regname;
3410 int regnum;
3411 {
3412 char buf[100];
3413 int i;
3414
3415 #ifdef REGISTER_PREFIX
3416 if (!flag_reg_prefix_optional)
3417 {
3418 buf[0] = REGISTER_PREFIX;
3419 strcpy (buf + 1, regname);
3420 regname = buf;
3421 }
3422 #endif
3423
3424 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3425 &zero_address_frag));
3426
3427 for (i = 0; regname[i]; i++)
3428 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3429 buf[i] = '\0';
3430
3431 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3432 &zero_address_frag));
3433 }
3434
3435 struct init_entry
3436 {
3437 const char *name;
3438 int number;
3439 };
3440
3441 static const struct init_entry init_table[] =
3442 {
3443 { "d0", DATA0 },
3444 { "d1", DATA1 },
3445 { "d2", DATA2 },
3446 { "d3", DATA3 },
3447 { "d4", DATA4 },
3448 { "d5", DATA5 },
3449 { "d6", DATA6 },
3450 { "d7", DATA7 },
3451 { "a0", ADDR0 },
3452 { "a1", ADDR1 },
3453 { "a2", ADDR2 },
3454 { "a3", ADDR3 },
3455 { "a4", ADDR4 },
3456 { "a5", ADDR5 },
3457 { "a6", ADDR6 },
3458 { "fp", ADDR6 },
3459 { "a7", ADDR7 },
3460 { "sp", ADDR7 },
3461 { "fp0", FP0 },
3462 { "fp1", FP1 },
3463 { "fp2", FP2 },
3464 { "fp3", FP3 },
3465 { "fp4", FP4 },
3466 { "fp5", FP5 },
3467 { "fp6", FP6 },
3468 { "fp7", FP7 },
3469 { "fpi", FPI },
3470 { "fpiar", FPI },
3471 { "fpc", FPI },
3472 { "fps", FPS },
3473 { "fpsr", FPS },
3474 { "fpc", FPC },
3475 { "fpcr", FPC },
3476
3477 { "cop0", COP0 },
3478 { "cop1", COP1 },
3479 { "cop2", COP2 },
3480 { "cop3", COP3 },
3481 { "cop4", COP4 },
3482 { "cop5", COP5 },
3483 { "cop6", COP6 },
3484 { "cop7", COP7 },
3485 { "pc", PC },
3486 { "zpc", ZPC },
3487 { "sr", SR },
3488
3489 { "ccr", CCR },
3490 { "cc", CCR },
3491
3492 { "usp", USP },
3493 { "isp", ISP },
3494 { "sfc", SFC },
3495 { "dfc", DFC },
3496 { "cacr", CACR },
3497 { "caar", CAAR },
3498
3499 { "vbr", VBR },
3500
3501 { "msp", MSP },
3502 { "itt0", ITT0 },
3503 { "itt1", ITT1 },
3504 { "dtt0", DTT0 },
3505 { "dtt1", DTT1 },
3506 { "mmusr", MMUSR },
3507 { "tc", TC },
3508 { "srp", SRP },
3509 { "urp", URP },
3510 { "buscr", BUSCR },
3511 { "pcr", PCR },
3512
3513 { "ac", AC },
3514 { "bc", BC },
3515 { "cal", CAL },
3516 { "crp", CRP },
3517 { "drp", DRP },
3518 { "pcsr", PCSR },
3519 { "psr", PSR },
3520 { "scc", SCC },
3521 { "val", VAL },
3522 { "bad0", BAD0 },
3523 { "bad1", BAD1 },
3524 { "bad2", BAD2 },
3525 { "bad3", BAD3 },
3526 { "bad4", BAD4 },
3527 { "bad5", BAD5 },
3528 { "bad6", BAD6 },
3529 { "bad7", BAD7 },
3530 { "bac0", BAC0 },
3531 { "bac1", BAC1 },
3532 { "bac2", BAC2 },
3533 { "bac3", BAC3 },
3534 { "bac4", BAC4 },
3535 { "bac5", BAC5 },
3536 { "bac6", BAC6 },
3537 { "bac7", BAC7 },
3538
3539 { "ic", IC },
3540 { "dc", DC },
3541 { "nc", NC },
3542
3543 { "tt0", TT0 },
3544 { "tt1", TT1 },
3545 /* 68ec030 versions of same */
3546 { "ac0", TT0 },
3547 { "ac1", TT1 },
3548 /* 68ec030 access control unit, identical to 030 MMU status reg */
3549 { "acusr", PSR },
3550
3551 { 0, 0 }
3552 };
3553
3554 void
3555 init_regtable ()
3556 {
3557 int i;
3558 for (i = 0; init_table[i].name; i++)
3559 insert_reg (init_table[i].name, init_table[i].number);
3560 }
3561
3562 static int no_68851, no_68881;
3563
3564 #ifdef OBJ_AOUT
3565 /* a.out machine type. Default to 68020. */
3566 int m68k_aout_machtype = 2;
3567 #endif
3568
3569 void
3570 md_assemble (str)
3571 char *str;
3572 {
3573 char *er;
3574 short *fromP;
3575 char *toP = NULL;
3576 int m, n = 0;
3577 char *to_beg_P;
3578 int shorts_this_frag;
3579
3580 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3581 m68k_ip (str);
3582 er = the_ins.error;
3583 if (!er)
3584 {
3585 for (n = the_ins.numargs; n; --n)
3586 if (the_ins.operands[n].error)
3587 {
3588 er = the_ins.operands[n].error;
3589 break;
3590 }
3591 }
3592 if (er)
3593 {
3594 as_bad ("%s -- statement `%s' ignored", er, str);
3595 return;
3596 }
3597
3598 if (the_ins.nfrag == 0)
3599 {
3600 /* No frag hacking involved; just put it out */
3601 toP = frag_more (2 * the_ins.numo);
3602 fromP = &the_ins.opcode[0];
3603 for (m = the_ins.numo; m; --m)
3604 {
3605 md_number_to_chars (toP, (long) (*fromP), 2);
3606 toP += 2;
3607 fromP++;
3608 }
3609 /* put out symbol-dependent info */
3610 for (m = 0; m < the_ins.nrel; m++)
3611 {
3612 switch (the_ins.reloc[m].wid)
3613 {
3614 case 'B':
3615 n = 1;
3616 break;
3617 case 'b':
3618 n = 1;
3619 break;
3620 case '3':
3621 n = 2;
3622 break;
3623 case 'w':
3624 n = 2;
3625 break;
3626 case 'l':
3627 n = 4;
3628 break;
3629 default:
3630 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3631 the_ins.reloc[m].wid);
3632 }
3633
3634 fix_new_exp (frag_now,
3635 ((toP - frag_now->fr_literal)
3636 - the_ins.numo * 2 + the_ins.reloc[m].n),
3637 n,
3638 &the_ins.reloc[m].exp,
3639 the_ins.reloc[m].pcrel,
3640 NO_RELOC);
3641 }
3642 return;
3643 }
3644
3645 /* There's some frag hacking */
3646 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3647 {
3648 int wid;
3649
3650 if (n == 0)
3651 wid = 2 * the_ins.fragb[n].fragoff;
3652 else
3653 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3654 toP = frag_more (wid);
3655 to_beg_P = toP;
3656 shorts_this_frag = 0;
3657 for (m = wid / 2; m; --m)
3658 {
3659 md_number_to_chars (toP, (long) (*fromP), 2);
3660 toP += 2;
3661 fromP++;
3662 shorts_this_frag++;
3663 }
3664 for (m = 0; m < the_ins.nrel; m++)
3665 {
3666 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3667 {
3668 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3669 break;
3670 }
3671 wid = the_ins.reloc[m].wid;
3672 if (wid == 0)
3673 continue;
3674 the_ins.reloc[m].wid = 0;
3675 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3676
3677 fix_new_exp (frag_now,
3678 ((toP - frag_now->fr_literal)
3679 - the_ins.numo * 2 + the_ins.reloc[m].n),
3680 wid,
3681 &the_ins.reloc[m].exp,
3682 the_ins.reloc[m].pcrel,
3683 NO_RELOC);
3684 }
3685 (void) frag_var (rs_machine_dependent, 10, 0,
3686 (relax_substateT) (the_ins.fragb[n].fragty),
3687 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3688 }
3689 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3690 shorts_this_frag = 0;
3691 if (n)
3692 {
3693 toP = frag_more (n * sizeof (short));
3694 while (n--)
3695 {
3696 md_number_to_chars (toP, (long) (*fromP), 2);
3697 toP += 2;
3698 fromP++;
3699 shorts_this_frag++;
3700 }
3701 }
3702 for (m = 0; m < the_ins.nrel; m++)
3703 {
3704 int wid;
3705
3706 wid = the_ins.reloc[m].wid;
3707 if (wid == 0)
3708 continue;
3709 the_ins.reloc[m].wid = 0;
3710 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3711
3712 fix_new_exp (frag_now,
3713 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3714 - shorts_this_frag * 2),
3715 wid,
3716 &the_ins.reloc[m].exp,
3717 the_ins.reloc[m].pcrel,
3718 NO_RELOC);
3719 }
3720 }
3721
3722 /* See BREAK_UP_BIG_DECL definition, above. */
3723 static const struct m68k_opcode *
3724 opcode_ptr (i)
3725 int i;
3726 {
3727 #ifdef DO_BREAK_UP_BIG_DECL
3728 int lim1 = sizeof (m68k_opcodes) / sizeof (m68k_opcodes[0]);
3729 if (i >= lim1)
3730 return m68k_opcodes_2 + (i - lim1);
3731 #endif
3732 return m68k_opcodes + i;
3733 }
3734
3735 void
3736 md_begin ()
3737 {
3738 /*
3739 * md_begin -- set up hash tables with 68000 instructions.
3740 * similar to what the vax assembler does. ---phr
3741 */
3742 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3743 a copy of it at runtime, adding in the information we want but isn't
3744 there. I think it'd be better to have an awk script hack the table
3745 at compile time. Or even just xstr the table and use it as-is. But
3746 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3747 names. */
3748
3749 register const struct m68k_opcode *ins;
3750 register struct m68k_incant *hack, *slak;
3751 register const char *retval = 0; /* empty string, or error msg text */
3752 register unsigned int i;
3753 register char c;
3754
3755 op_hash = hash_new ();
3756
3757 obstack_begin (&robyn, 4000);
3758 for (i = 0; i < numopcodes; i++)
3759 {
3760 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3761 do
3762 {
3763 ins = opcode_ptr (i);
3764 /* We *could* ignore insns that don't match our arch here
3765 but just leaving them out of the hash. */
3766 slak->m_operands = ins->args;
3767 slak->m_opnum = strlen (slak->m_operands) / 2;
3768 slak->m_arch = ins->arch;
3769 slak->m_opcode = ins->opcode;
3770 /* This is kludgey */
3771 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3772 if (i + 1 != numopcodes
3773 && !strcmp (ins->name, opcode_ptr (i + 1)->name))
3774 {
3775 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3776 i++;
3777 }
3778 else
3779 slak->m_next = 0;
3780 slak = slak->m_next;
3781 }
3782 while (slak);
3783
3784 retval = hash_insert (op_hash, ins->name, (char *) hack);
3785 if (retval)
3786 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3787 }
3788
3789 for (i = 0; i < numaliases; i++)
3790 {
3791 const char *name = m68k_opcode_aliases[i].primary;
3792 const char *alias = m68k_opcode_aliases[i].alias;
3793 PTR val = hash_find (op_hash, name);
3794 if (!val)
3795 as_fatal ("Internal Error: Can't find %s in hash table", name);
3796 retval = hash_insert (op_hash, alias, val);
3797 if (retval)
3798 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3799 }
3800
3801 for (i = 0; i < sizeof (mklower_table); i++)
3802 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3803
3804 for (i = 0; i < sizeof (notend_table); i++)
3805 {
3806 notend_table[i] = 0;
3807 alt_notend_table[i] = 0;
3808 }
3809 notend_table[','] = 1;
3810 notend_table['{'] = 1;
3811 notend_table['}'] = 1;
3812 alt_notend_table['a'] = 1;
3813 alt_notend_table['A'] = 1;
3814 alt_notend_table['d'] = 1;
3815 alt_notend_table['D'] = 1;
3816 alt_notend_table['#'] = 1;
3817 alt_notend_table['f'] = 1;
3818 alt_notend_table['F'] = 1;
3819 #ifdef REGISTER_PREFIX
3820 alt_notend_table[REGISTER_PREFIX] = 1;
3821 #endif
3822
3823 #ifndef MIT_SYNTAX_ONLY
3824 /* Insert pseudo ops, these have to go into the opcode table since
3825 gas expects pseudo ops to start with a dot */
3826 {
3827 int n = 0;
3828 while (mote_pseudo_table[n].poc_name)
3829 {
3830 hack = (struct m68k_incant *)
3831 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3832 hash_insert (op_hash,
3833 mote_pseudo_table[n].poc_name, (char *) hack);
3834 hack->m_operands = 0;
3835 hack->m_opnum = n;
3836 n++;
3837 }
3838 }
3839 #endif
3840
3841 init_regtable ();
3842 }
3843
3844 void
3845 m68k_init_after_args ()
3846 {
3847 if (cpu_of_arch (current_architecture) == 0)
3848 {
3849 int cpu_type, i;
3850 const char *default_cpu = TARGET_CPU;
3851
3852 if (*default_cpu == 'm')
3853 default_cpu++;
3854 for (i = 0; i < n_archs; i++)
3855 if (!strcmp (default_cpu, archs[i].name))
3856 break;
3857 if (i == n_archs)
3858 {
3859 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3860 current_architecture |= m68020;
3861 }
3862 else
3863 current_architecture |= archs[i].arch;
3864 }
3865 /* Permit m68881 specification with all cpus; those that can't work
3866 with a coprocessor could be doing emulation. */
3867 if (current_architecture & m68851)
3868 {
3869 if (current_architecture & m68040)
3870 {
3871 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3872 }
3873 }
3874 /* What other incompatibilities could we check for? */
3875
3876 /* Toss in some default assumptions about coprocessors. */
3877 if (!no_68881
3878 && (cpu_of_arch (current_architecture)
3879 /* Can CPU32 have a 68881 coprocessor?? */
3880 & (m68020 | m68030 | cpu32)))
3881 {
3882 current_architecture |= m68881;
3883 }
3884 if (!no_68851
3885 && (cpu_of_arch (current_architecture) & m68020up) != 0
3886 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3887 {
3888 current_architecture |= m68851;
3889 }
3890 if (no_68881 && (current_architecture & m68881))
3891 as_bad ("options for 68881 and no-68881 both given");
3892 if (no_68851 && (current_architecture & m68851))
3893 as_bad ("options for 68851 and no-68851 both given");
3894
3895 #ifdef OBJ_AOUT
3896 /* Work out the magic number. This isn't very general. */
3897 if (current_architecture & m68000)
3898 m68k_aout_machtype = 0;
3899 else if (current_architecture & m68010)
3900 m68k_aout_machtype = 1;
3901 else if (current_architecture & m68020)
3902 m68k_aout_machtype = 2;
3903 else
3904 m68k_aout_machtype = 2;
3905 #endif
3906
3907 /* Note which set of "movec" control registers is available. */
3908 switch (cpu_of_arch (current_architecture))
3909 {
3910 case m68000:
3911 control_regs = m68000_control_regs;
3912 break;
3913 case m68010:
3914 control_regs = m68010_control_regs;
3915 break;
3916 case m68020:
3917 case m68030:
3918 control_regs = m68020_control_regs;
3919 break;
3920 case m68040:
3921 control_regs = m68040_control_regs;
3922 break;
3923 case m68060:
3924 control_regs = m68060_control_regs;
3925 break;
3926 case cpu32:
3927 control_regs = cpu32_control_regs;
3928 break;
3929 default:
3930 abort ();
3931 }
3932 }
3933
3934 /* Equal to MAX_PRECISION in atof-ieee.c */
3935 #define MAX_LITTLENUMS 6
3936
3937 /* Turn a string in input_line_pointer into a floating point constant of type
3938 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3939 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
3940 */
3941 char *
3942 md_atof (type, litP, sizeP)
3943 char type;
3944 char *litP;
3945 int *sizeP;
3946 {
3947 int prec;
3948 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3949 LITTLENUM_TYPE *wordP;
3950 char *t;
3951 char *atof_ieee ();
3952
3953 switch (type)
3954 {
3955 case 'f':
3956 case 'F':
3957 case 's':
3958 case 'S':
3959 prec = 2;
3960 break;
3961
3962 case 'd':
3963 case 'D':
3964 case 'r':
3965 case 'R':
3966 prec = 4;
3967 break;
3968
3969 case 'x':
3970 case 'X':
3971 prec = 6;
3972 break;
3973
3974 case 'p':
3975 case 'P':
3976 prec = 6;
3977 break;
3978
3979 default:
3980 *sizeP = 0;
3981 return "Bad call to MD_ATOF()";
3982 }
3983 t = atof_ieee (input_line_pointer, type, words);
3984 if (t)
3985 input_line_pointer = t;
3986
3987 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3988 for (wordP = words; prec--;)
3989 {
3990 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3991 litP += sizeof (LITTLENUM_TYPE);
3992 }
3993 return 0;
3994 }
3995
3996 void
3997 md_number_to_chars (buf, val, n)
3998 char *buf;
3999 valueT val;
4000 int n;
4001 {
4002 number_to_chars_bigendian (buf, val, n);
4003 }
4004
4005 static void
4006 md_apply_fix_2 (fixP, val)
4007 fixS *fixP;
4008 offsetT val;
4009 {
4010 addressT upper_limit;
4011 offsetT lower_limit;
4012
4013 /* This is unnecessary but it convinces the native rs6000 compiler
4014 to generate the code we want. */
4015 char *buf = fixP->fx_frag->fr_literal;
4016 buf += fixP->fx_where;
4017 /* end ibm compiler workaround */
4018
4019 if (val & 0x80000000)
4020 val |= ~(addressT)0x7fffffff;
4021 else
4022 val &= 0x7fffffff;
4023
4024 switch (fixP->fx_size)
4025 {
4026 /* The cast to offsetT below are necessary to make code correct for
4027 machines where ints are smaller than offsetT */
4028 case 1:
4029 *buf++ = val;
4030 upper_limit = 0x7f;
4031 lower_limit = - (offsetT) 0x80;
4032 break;
4033 case 2:
4034 *buf++ = (val >> 8);
4035 *buf++ = val;
4036 upper_limit = 0x7fff;
4037 lower_limit = - (offsetT) 0x8000;
4038 break;
4039 case 4:
4040 *buf++ = (val >> 24);
4041 *buf++ = (val >> 16);
4042 *buf++ = (val >> 8);
4043 *buf++ = val;
4044 upper_limit = 0x7fffffff;
4045 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4046 break;
4047 default:
4048 BAD_CASE (fixP->fx_size);
4049 }
4050
4051 /* For non-pc-relative values, it's conceivable we might get something
4052 like "0xff" for a byte field. So extend the upper part of the range
4053 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4054 so that we can do any range checking at all. */
4055 if (!fixP->fx_pcrel)
4056 upper_limit = upper_limit * 2 + 1;
4057
4058 if ((addressT) val > upper_limit
4059 && (val > 0 || val < lower_limit))
4060 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
4061
4062 /* A one byte PC-relative reloc means a short branch. We can't use
4063 a short branch with a value of 0 or -1, because those indicate
4064 different opcodes (branches with longer offsets). */
4065 if (fixP->fx_pcrel
4066 && fixP->fx_size == 1
4067 && (fixP->fx_addsy == NULL
4068 || S_IS_DEFINED (fixP->fx_addsy))
4069 && (val == 0 || val == -1))
4070 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
4071 }
4072
4073 #ifdef BFD_ASSEMBLER
4074 int
4075 md_apply_fix (fixP, valp)
4076 fixS *fixP;
4077 long *valp;
4078 {
4079 md_apply_fix_2 (fixP, (addressT) *valp);
4080 return 1;
4081 }
4082 #else
4083 void md_apply_fix (fixP, val)
4084 fixS *fixP;
4085 long val;
4086 {
4087 md_apply_fix_2 (fixP, (addressT) val);
4088 }
4089 #endif
4090
4091 /* *fragP has been relaxed to its final size, and now needs to have
4092 the bytes inside it modified to conform to the new size There is UGLY
4093 MAGIC here. ..
4094 */
4095 void
4096 md_convert_frag_1 (fragP)
4097 register fragS *fragP;
4098 {
4099 long disp;
4100 long ext = 0;
4101
4102 /* Address in object code of the displacement. */
4103 register int object_address = fragP->fr_fix + fragP->fr_address;
4104
4105 /* Address in gas core of the place to store the displacement. */
4106 /* This convinces the native rs6000 compiler to generate the code we
4107 want. */
4108 register char *buffer_address = fragP->fr_literal;
4109 buffer_address += fragP->fr_fix;
4110 /* end ibm compiler workaround */
4111
4112 /* The displacement of the address, from current location. */
4113 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4114 disp = (disp + fragP->fr_offset) - object_address;
4115
4116 switch (fragP->fr_subtype)
4117 {
4118 case TAB (BCC68000, BYTE):
4119 case TAB (ABRANCH, BYTE):
4120 know (issbyte (disp));
4121 if (disp == 0)
4122 as_bad ("short branch with zero offset: use :w");
4123 fragP->fr_opcode[1] = disp;
4124 ext = 0;
4125 break;
4126 case TAB (DBCC, SHORT):
4127 know (issword (disp));
4128 ext = 2;
4129 break;
4130 case TAB (BCC68000, SHORT):
4131 case TAB (ABRANCH, SHORT):
4132 know (issword (disp));
4133 fragP->fr_opcode[1] = 0x00;
4134 ext = 2;
4135 break;
4136 case TAB (ABRANCH, LONG):
4137 if (cpu_of_arch (current_architecture) < m68020)
4138 {
4139 if (fragP->fr_opcode[0] == 0x61)
4140 {
4141 fragP->fr_opcode[0] = 0x4E;
4142 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4143 subseg_change (text_section, 0); /* @@ */
4144
4145 fix_new (fragP,
4146 fragP->fr_fix,
4147 4,
4148 fragP->fr_symbol,
4149 fragP->fr_offset,
4150 0,
4151 NO_RELOC);
4152
4153 fragP->fr_fix += 4;
4154 ext = 0;
4155 }
4156 else if (fragP->fr_opcode[0] == 0x60)
4157 {
4158 fragP->fr_opcode[0] = 0x4E;
4159 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4160 subseg_change (text_section, 0); /* @@ */
4161 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4162 fragP->fr_offset, 0, NO_RELOC);
4163 fragP->fr_fix += 4;
4164 ext = 0;
4165 }
4166 else
4167 {
4168 as_bad ("Long branch offset not supported.");
4169 }
4170 }
4171 else
4172 {
4173 fragP->fr_opcode[1] = (char) 0xff;
4174 ext = 4;
4175 }
4176 break;
4177 case TAB (BCC68000, LONG):
4178 /* only Bcc 68000 instructions can come here */
4179 /* change bcc into b!cc/jmp absl long */
4180 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4181 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4182
4183 /* JF: these used to be fr_opcode[2,3], but they may be in a
4184 different frag, in which case refering to them is a no-no.
4185 Only fr_opcode[0,1] are guaranteed to work. */
4186 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4187 *buffer_address++ = (char) 0xf9;
4188 fragP->fr_fix += 2; /* account for jmp instruction */
4189 subseg_change (text_section, 0);
4190 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4191 fragP->fr_offset, 0, NO_RELOC);
4192 fragP->fr_fix += 4;
4193 ext = 0;
4194 break;
4195 case TAB (DBCC, LONG):
4196 /* only DBcc 68000 instructions can come here */
4197 /* change dbcc into dbcc/jmp absl long */
4198 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4199 *buffer_address++ = 0x00; /* branch offset = 4 */
4200 *buffer_address++ = 0x04;
4201 *buffer_address++ = 0x60; /* put in bra pc+6 */
4202 *buffer_address++ = 0x06;
4203 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4204 *buffer_address++ = (char) 0xf9;
4205
4206 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4207 subseg_change (text_section, 0);
4208 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4209 fragP->fr_offset, 0, NO_RELOC);
4210 fragP->fr_fix += 4;
4211 ext = 0;
4212 break;
4213 case TAB (FBRANCH, SHORT):
4214 know ((fragP->fr_opcode[1] & 0x40) == 0);
4215 ext = 2;
4216 break;
4217 case TAB (FBRANCH, LONG):
4218 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4219 ext = 4;
4220 break;
4221 case TAB (PCREL, SHORT):
4222 ext = 2;
4223 break;
4224 case TAB (PCREL, LONG):
4225 /* The thing to do here is force it to ABSOLUTE LONG, since
4226 PCREL is really trying to shorten an ABSOLUTE address anyway */
4227 /* JF FOO This code has not been tested */
4228 subseg_change (text_section, 0);
4229 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4230 0, NO_RELOC);
4231 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4232 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4233 (unsigned) fragP->fr_opcode[0],
4234 (unsigned long) fragP->fr_address);
4235 fragP->fr_opcode[1] &= ~0x3F;
4236 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4237 fragP->fr_fix += 4;
4238 ext = 0;
4239 break;
4240 case TAB (PCLEA, SHORT):
4241 subseg_change (text_section, 0);
4242 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4243 fragP->fr_offset, 1, NO_RELOC);
4244 fragP->fr_opcode[1] &= ~0x3F;
4245 fragP->fr_opcode[1] |= 0x3A;
4246 ext = 2;
4247 break;
4248 case TAB (PCLEA, LONG):
4249 subseg_change (text_section, 0);
4250 fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4251 fragP->fr_offset + 2, 1, NO_RELOC);
4252 *buffer_address++ = 0x01;
4253 *buffer_address++ = 0x70;
4254 fragP->fr_fix += 2;
4255 ext = 4;
4256 break;
4257 }
4258
4259 if (ext)
4260 {
4261 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4262 fragP->fr_fix += ext;
4263 }
4264 }
4265
4266 #ifndef BFD_ASSEMBLER
4267
4268 void
4269 md_convert_frag (headers, fragP)
4270 object_headers *headers;
4271 fragS *fragP;
4272 {
4273 md_convert_frag_1 (fragP);
4274 }
4275
4276 #else
4277
4278 void
4279 md_convert_frag (abfd, sec, fragP)
4280 bfd *abfd;
4281 asection sec;
4282 fragS *fragP;
4283 {
4284 md_convert_frag_1 (fragP);
4285 }
4286 #endif
4287
4288 /* Force truly undefined symbols to their maximum size, and generally set up
4289 the frag list to be relaxed
4290 */
4291 int
4292 md_estimate_size_before_relax (fragP, segment)
4293 register fragS *fragP;
4294 segT segment;
4295 {
4296 int old_fix;
4297 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4298
4299 old_fix = fragP->fr_fix;
4300
4301 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4302 switch (fragP->fr_subtype)
4303 {
4304
4305 case TAB (ABRANCH, SZ_UNDEF):
4306 {
4307 if ((fragP->fr_symbol != NULL) /* Not absolute */
4308 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4309 {
4310 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4311 break;
4312 }
4313 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4314 {
4315 /* On 68000, or for absolute value, switch to abs long */
4316 /* FIXME, we should check abs val, pick short or long */
4317 if (fragP->fr_opcode[0] == 0x61)
4318 {
4319 fragP->fr_opcode[0] = 0x4E;
4320 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4321 subseg_change (text_section, 0);
4322 fix_new (fragP, fragP->fr_fix, 4,
4323 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4324 fragP->fr_fix += 4;
4325 frag_wane (fragP);
4326 }
4327 else if (fragP->fr_opcode[0] == 0x60)
4328 {
4329 fragP->fr_opcode[0] = 0x4E;
4330 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4331 subseg_change (text_section, 0);
4332 fix_new (fragP, fragP->fr_fix, 4,
4333 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4334 fragP->fr_fix += 4;
4335 frag_wane (fragP);
4336 }
4337 else
4338 {
4339 as_warn ("Long branch offset to extern symbol not supported.");
4340 }
4341 }
4342 else
4343 { /* Symbol is still undefined. Make it simple */
4344 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4345 fragP->fr_offset + 4, 1, NO_RELOC);
4346 fragP->fr_fix += 4;
4347 fragP->fr_opcode[1] = (char) 0xff;
4348 frag_wane (fragP);
4349 break;
4350 }
4351
4352 break;
4353 } /* case TAB(ABRANCH,SZ_UNDEF) */
4354
4355 case TAB (FBRANCH, SZ_UNDEF):
4356 {
4357 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4358 {
4359 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4360 fragP->fr_var += 2;
4361 }
4362 else
4363 {
4364 fragP->fr_subtype = TAB (FBRANCH, LONG);
4365 fragP->fr_var += 4;
4366 }
4367 break;
4368 } /* TAB(FBRANCH,SZ_UNDEF) */
4369
4370 case TAB (PCREL, SZ_UNDEF):
4371 {
4372 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4373 || flag_short_refs
4374 || cpu_of_arch (current_architecture) < m68020)
4375 {
4376 fragP->fr_subtype = TAB (PCREL, SHORT);
4377 fragP->fr_var += 2;
4378 }
4379 else
4380 {
4381 fragP->fr_subtype = TAB (PCREL, LONG);
4382 fragP->fr_var += 4;
4383 }
4384 break;
4385 } /* TAB(PCREL,SZ_UNDEF) */
4386
4387 case TAB (BCC68000, SZ_UNDEF):
4388 {
4389 if ((fragP->fr_symbol != NULL)
4390 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4391 {
4392 fragP->fr_subtype = TAB (BCC68000, BYTE);
4393 break;
4394 }
4395 /* only Bcc 68000 instructions can come here */
4396 /* change bcc into b!cc/jmp absl long */
4397 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4398 if (flag_short_refs)
4399 {
4400 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4401 /* JF: these were fr_opcode[2,3] */
4402 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4403 buffer_address[1] = (char) 0xf8;
4404 fragP->fr_fix += 2; /* account for jmp instruction */
4405 subseg_change (text_section, 0);
4406 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4407 fragP->fr_offset, 0, NO_RELOC);
4408 fragP->fr_fix += 2;
4409 }
4410 else
4411 {
4412 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4413 /* JF: these were fr_opcode[2,3] */
4414 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4415 buffer_address[1] = (char) 0xf9;
4416 fragP->fr_fix += 2; /* account for jmp instruction */
4417 subseg_change (text_section, 0);
4418 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4419 fragP->fr_offset, 0, NO_RELOC);
4420 fragP->fr_fix += 4;
4421 }
4422 frag_wane (fragP);
4423 break;
4424 } /* case TAB(BCC68000,SZ_UNDEF) */
4425
4426 case TAB (DBCC, SZ_UNDEF):
4427 {
4428 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4429 {
4430 fragP->fr_subtype = TAB (DBCC, SHORT);
4431 fragP->fr_var += 2;
4432 break;
4433 }
4434 /* only DBcc 68000 instructions can come here */
4435 /* change dbcc into dbcc/jmp absl long */
4436 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4437 buffer_address[0] = 0x00; /* branch offset = 4 */
4438 buffer_address[1] = 0x04;
4439 buffer_address[2] = 0x60; /* put in bra pc + ... */
4440
4441 if (flag_short_refs)
4442 {
4443 /* JF: these were fr_opcode[5-7] */
4444 buffer_address[3] = 0x04; /* plus 4 */
4445 buffer_address[4] = 0x4e; /* Put in Jump Word */
4446 buffer_address[5] = (char) 0xf8;
4447 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4448 subseg_change (text_section, 0);
4449 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4450 fragP->fr_offset, 0, NO_RELOC);
4451 fragP->fr_fix += 2;
4452 }
4453 else
4454 {
4455 /* JF: these were fr_opcode[5-7] */
4456 buffer_address[3] = 0x06; /* Plus 6 */
4457 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4458 buffer_address[5] = (char) 0xf9;
4459 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4460 subseg_change (text_section, 0);
4461 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4462 fragP->fr_offset, 0, NO_RELOC);
4463 fragP->fr_fix += 4;
4464 }
4465
4466 frag_wane (fragP);
4467 break;
4468 } /* case TAB(DBCC,SZ_UNDEF) */
4469
4470 case TAB (PCLEA, SZ_UNDEF):
4471 {
4472 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4473 || flag_short_refs
4474 || cpu_of_arch (current_architecture) < m68020)
4475 {
4476 fragP->fr_subtype = TAB (PCLEA, SHORT);
4477 fragP->fr_var += 2;
4478 }
4479 else
4480 {
4481 fragP->fr_subtype = TAB (PCLEA, LONG);
4482 fragP->fr_var += 6;
4483 }
4484 break;
4485 } /* TAB(PCLEA,SZ_UNDEF) */
4486
4487 default:
4488 break;
4489
4490 } /* switch on subtype looking for SZ_UNDEF's. */
4491
4492 /* now that SZ_UNDEF are taken care of, check others */
4493 switch (fragP->fr_subtype)
4494 {
4495 case TAB (BCC68000, BYTE):
4496 case TAB (ABRANCH, BYTE):
4497 /* We can't do a short jump to the next instruction,
4498 so we force word mode. */
4499 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
4500 fragP->fr_symbol->sy_frag == fragP->fr_next)
4501 {
4502 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4503 fragP->fr_var += 2;
4504 }
4505 break;
4506 default:
4507 break;
4508 }
4509 return fragP->fr_var + fragP->fr_fix - old_fix;
4510 }
4511
4512 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4513 /* the bit-field entries in the relocation_info struct plays hell
4514 with the byte-order problems of cross-assembly. So as a hack,
4515 I added this mach. dependent ri twiddler. Ugly, but it gets
4516 you there. -KWK */
4517 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4518 are symbolnum, most sig. byte first. Last byte is broken up with
4519 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4520 nibble as nuthin. (on Sun 3 at least) */
4521 /* Translate the internal relocation information into target-specific
4522 format. */
4523 #ifdef comment
4524 void
4525 md_ri_to_chars (the_bytes, ri)
4526 char *the_bytes;
4527 struct reloc_info_generic *ri;
4528 {
4529 /* this is easy */
4530 md_number_to_chars (the_bytes, ri->r_address, 4);
4531 /* now the fun stuff */
4532 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4533 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4534 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4535 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4536 ((ri->r_extern << 4) & 0x10));
4537 }
4538
4539 #endif /* comment */
4540
4541 #ifndef BFD_ASSEMBLER
4542 void
4543 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4544 char *where;
4545 fixS *fixP;
4546 relax_addressT segment_address_in_file;
4547 {
4548 /*
4549 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4550 * Out: GNU LD relocation length code: 0, 1, or 2.
4551 */
4552
4553 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4554 long r_symbolnum;
4555
4556 know (fixP->fx_addsy != NULL);
4557
4558 md_number_to_chars (where,
4559 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4560 4);
4561
4562 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4563 ? S_GET_TYPE (fixP->fx_addsy)
4564 : fixP->fx_addsy->sy_number);
4565
4566 where[4] = (r_symbolnum >> 16) & 0x0ff;
4567 where[5] = (r_symbolnum >> 8) & 0x0ff;
4568 where[6] = r_symbolnum & 0x0ff;
4569 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4570 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4571 }
4572 #endif
4573
4574 #endif /* OBJ_AOUT or OBJ_BOUT */
4575
4576 #ifndef WORKING_DOT_WORD
4577 CONST int md_short_jump_size = 4;
4578 CONST int md_long_jump_size = 6;
4579
4580 void
4581 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4582 char *ptr;
4583 addressT from_addr, to_addr;
4584 fragS *frag;
4585 symbolS *to_symbol;
4586 {
4587 valueT offset;
4588
4589 offset = to_addr - (from_addr + 2);
4590
4591 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4592 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4593 }
4594
4595 void
4596 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4597 char *ptr;
4598 addressT from_addr, to_addr;
4599 fragS *frag;
4600 symbolS *to_symbol;
4601 {
4602 valueT offset;
4603
4604 if (cpu_of_arch (current_architecture) < m68020)
4605 {
4606 offset = to_addr - S_GET_VALUE (to_symbol);
4607 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4608 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4609 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4610 0, NO_RELOC);
4611 }
4612 else
4613 {
4614 offset = to_addr - (from_addr + 2);
4615 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4616 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4617 }
4618 }
4619
4620 #endif
4621 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
4622
4623 0: Everything is OK
4624 10: Absolute 1:8 only
4625 20: Absolute 0:7 only
4626 30: absolute 0:15 only
4627 40: Absolute 0:31 only
4628 50: absolute 0:127 only
4629 55: absolute -64:63 only
4630 60: absolute -128:127 only
4631 70: absolute 0:4095 only
4632 80: No bignums
4633
4634 */
4635
4636 static int
4637 get_num (exp, ok)
4638 struct m68k_exp *exp;
4639 int ok;
4640 {
4641 #ifdef TEST2
4642 long l = 0;
4643
4644 if (!exp->e_beg)
4645 return 0;
4646 if (*exp->e_beg == '0')
4647 {
4648 if (exp->e_beg[1] == 'x')
4649 sscanf (exp->e_beg + 2, "%x", &l);
4650 else
4651 sscanf (exp->e_beg + 1, "%O", &l);
4652 return l;
4653 }
4654 return atol (exp->e_beg);
4655 #else
4656 char *save_in;
4657 char c_save;
4658 segT section;
4659
4660 if (!exp)
4661 {
4662 /* Can't do anything */
4663 return 0;
4664 }
4665 if (!exp->e_beg || !exp->e_end)
4666 {
4667 seg (exp) = absolute_section;
4668 adds (exp) = 0;
4669 subs (exp) = 0;
4670 offs (exp) = (ok == 10) ? 1 : 0;
4671 as_warn ("Null expression defaults to %ld", offs (exp));
4672 return 0;
4673 }
4674
4675 exp->e_siz = 0;
4676 if ( /* ok!=80 && */ (exp->e_end[-1] == ':' || exp->e_end[-1] == '.')
4677 && (exp->e_end - exp->e_beg) >= 2)
4678 {
4679 switch (exp->e_end[0])
4680 {
4681 case 's':
4682 case 'S':
4683 case 'b':
4684 case 'B':
4685 exp->e_siz = 1;
4686 exp->e_end -= 2;
4687 break;
4688 case 'w':
4689 case 'W':
4690 exp->e_siz = 2;
4691 exp->e_end -= 2;
4692 break;
4693 case 'l':
4694 case 'L':
4695 exp->e_siz = 3;
4696 exp->e_end -= 2;
4697 break;
4698 default:
4699 if (exp->e_end[-1] == ':')
4700 as_bad ("Unknown size for expression \"%c\"", exp->e_end[0]);
4701 break;
4702 }
4703 }
4704 c_save = exp->e_end[1];
4705 exp->e_end[1] = '\0';
4706 save_in = input_line_pointer;
4707 input_line_pointer = exp->e_beg;
4708 section = expression (&exp->e_exp);
4709 seg (exp) = section;
4710 if (exp->e_exp.X_op == O_absent)
4711 {
4712 /* Do the same thing the VAX asm does */
4713 seg (exp) = absolute_section;
4714 op (exp) = O_constant;
4715 adds (exp) = 0;
4716 subs (exp) = 0;
4717 offs (exp) = 0;
4718 if (ok == 10)
4719 {
4720 as_warn ("expression out of range: defaulting to 1");
4721 offs (exp) = 1;
4722 }
4723 }
4724 else if (exp->e_exp.X_op == O_constant)
4725 {
4726 switch (ok)
4727 {
4728 case 10:
4729 if (offs (exp) < 1 || offs (exp) > 8)
4730 {
4731 as_warn ("expression out of range: defaulting to 1");
4732 offs (exp) = 1;
4733 }
4734 break;
4735 case 20:
4736 if (offs (exp) < 0 || offs (exp) > 7)
4737 goto outrange;
4738 break;
4739 case 30:
4740 if (offs (exp) < 0 || offs (exp) > 15)
4741 goto outrange;
4742 break;
4743 case 40:
4744 if (offs (exp) < 0 || offs (exp) > 32)
4745 goto outrange;
4746 break;
4747 case 50:
4748 if (offs (exp) < 0 || offs (exp) > 127)
4749 goto outrange;
4750 break;
4751 case 55:
4752 if (offs (exp) < -64 || offs (exp) > 63)
4753 goto outrange;
4754 break;
4755 case 60:
4756 if (offs (exp) < -128 || offs (exp) > 127)
4757 goto outrange;
4758 break;
4759 case 70:
4760 if (offs (exp) < 0 || offs (exp) > 4095)
4761 {
4762 outrange:
4763 as_warn ("expression out of range: defaulting to 0");
4764 offs (exp) = 0;
4765 }
4766 break;
4767 default:
4768 break;
4769 }
4770 }
4771 else if (exp->e_exp.X_op == O_big)
4772 {
4773 if (offs (exp) <= 0 /* flonum */
4774 && (ok == 80 /* no bignums */
4775 || (ok > 10 /* small-int ranges including 0 ok */
4776 /* If we have a flonum zero, a zero integer should
4777 do as well (e.g., in moveq). */
4778 && generic_floating_point_number.exponent == 0
4779 && generic_floating_point_number.low[0] == 0)))
4780 {
4781 /* HACK! Turn it into a long */
4782 LITTLENUM_TYPE words[6];
4783
4784 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4785 seg (exp) = absolute_section;
4786 op (exp) = O_constant;
4787 adds (exp) = 0;
4788 subs (exp) = 0;
4789 offs (exp) = words[1] | (words[0] << 16);
4790 }
4791 else if (ok != 0)
4792 {
4793 seg (exp) = absolute_section;
4794 op (exp) = O_constant;
4795 adds (exp) = 0;
4796 subs (exp) = 0;
4797 offs (exp) = (ok == 10) ? 1 : 0;
4798 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4799 }
4800 }
4801 else
4802 {
4803 if (ok >= 10 && ok <= 70)
4804 {
4805 seg (exp) = absolute_section;
4806 op (exp) = O_constant;
4807 adds (exp) = 0;
4808 subs (exp) = 0;
4809 offs (exp) = (ok == 10) ? 1 : 0;
4810 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4811 }
4812 }
4813
4814 if (input_line_pointer != exp->e_end + 1)
4815 as_bad ("Ignoring junk after expression");
4816 exp->e_end[1] = c_save;
4817 input_line_pointer = save_in;
4818 if (exp->e_siz)
4819 {
4820 switch (exp->e_siz)
4821 {
4822 case 1:
4823 if (!isbyte (offs (exp)))
4824 as_warn ("expression doesn't fit in BYTE");
4825 break;
4826 case 2:
4827 if (!isword (offs (exp)))
4828 as_warn ("expression doesn't fit in WORD");
4829 break;
4830 }
4831 }
4832 return offs (exp);
4833 #endif
4834 }
4835
4836 /* These are the back-ends for the various machine dependent pseudo-ops. */
4837 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4838
4839 static void
4840 s_data1 (ignore)
4841 int ignore;
4842 {
4843 subseg_set (data_section, 1);
4844 demand_empty_rest_of_line ();
4845 }
4846
4847 static void
4848 s_data2 (ignore)
4849 int ignore;
4850 {
4851 subseg_set (data_section, 2);
4852 demand_empty_rest_of_line ();
4853 }
4854
4855 static void
4856 s_bss (ignore)
4857 int ignore;
4858 {
4859 /* We don't support putting frags in the BSS segment, we fake it
4860 by marking in_bss, then looking at s_skip for clues. */
4861
4862 subseg_set (bss_section, 0);
4863 demand_empty_rest_of_line ();
4864 }
4865
4866 static void
4867 s_even (ignore)
4868 int ignore;
4869 {
4870 register int temp;
4871 register long temp_fill;
4872
4873 temp = 1; /* JF should be 2? */
4874 temp_fill = get_absolute_expression ();
4875 if (!need_pass_2) /* Never make frag if expect extra pass. */
4876 frag_align (temp, (int) temp_fill);
4877 demand_empty_rest_of_line ();
4878 }
4879
4880 static void
4881 s_proc (ignore)
4882 int ignore;
4883 {
4884 demand_empty_rest_of_line ();
4885 }
4886
4887 /* s_space is defined in read.c .skip is simply an alias to it. */
4888
4889 \f
4890 /*
4891 * md_parse_option
4892 * Invocation line includes a switch not recognized by the base assembler.
4893 * See if it's a processor-specific option. These are:
4894 *
4895 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4896 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4897 * Select the architecture. Instructions or features not
4898 * supported by the selected architecture cause fatal
4899 * errors. More than one may be specified. The default is
4900 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4901 * for -m68000, and -m68882 is a synonym for -m68881.
4902 * -[A]m[c]no-68851, -[A]m[c]no-68881
4903 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4904 * so don't use or document it, but that's the way the parsing
4905 * works).
4906 *
4907 * -pic Indicates PIC.
4908 * -k Indicates PIC. (Sun 3 only.)
4909 *
4910 */
4911
4912 CONST char *md_shortopts = "lSA:m:k";
4913 struct option md_longopts[] = {
4914 #define OPTION_PIC (OPTION_MD_BASE)
4915 {"pic", no_argument, NULL, OPTION_PIC},
4916 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
4917 {"register-prefix-optional", no_argument, NULL,
4918 OPTION_REGISTER_PREFIX_OPTIONAL},
4919 {NULL, no_argument, NULL, 0}
4920 };
4921 size_t md_longopts_size = sizeof(md_longopts);
4922
4923 int
4924 md_parse_option (c, arg)
4925 int c;
4926 char *arg;
4927 {
4928 int i;
4929 unsigned long arch;
4930
4931 switch (c)
4932 {
4933 case 'l': /* -l means keep external to 2 bit offset
4934 rather than 16 bit one */
4935 flag_short_refs = 1;
4936 break;
4937
4938 case 'S': /* -S means that jbsr's always turn into
4939 jsr's. */
4940 flag_long_jumps = 1;
4941 break;
4942
4943 case 'A':
4944 if (*arg == 'm')
4945 arg++;
4946 /* intentional fall-through */
4947 case 'm':
4948
4949 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
4950 {
4951 int i, arch;
4952 const char *oarg = arg;
4953
4954 arg += 3;
4955 if (*arg == 'm')
4956 {
4957 arg++;
4958 if (arg[0] == 'c' && arg[1] == '6')
4959 arg++;
4960 }
4961 for (i = 0; i < n_archs; i++)
4962 if (!strcmp (arg, archs[i].name))
4963 break;
4964 if (i == n_archs)
4965 {
4966 unknown:
4967 as_bad ("unrecognized option `%s'", oarg);
4968 return 0;
4969 }
4970 arch = archs[i].arch;
4971 if (arch == m68881)
4972 no_68881 = 1;
4973 else if (arch == m68851)
4974 no_68851 = 1;
4975 else
4976 goto unknown;
4977 }
4978 else
4979 {
4980 int i;
4981
4982 if (arg[0] == 'c' && arg[1] == '6')
4983 arg++;
4984
4985 for (i = 0; i < n_archs; i++)
4986 if (!strcmp (arg, archs[i].name))
4987 {
4988 unsigned long arch = archs[i].arch;
4989 if (cpu_of_arch (arch))
4990 /* It's a cpu spec. */
4991 {
4992 current_architecture &= ~m68000up;
4993 current_architecture |= arch;
4994 }
4995 else if (arch == m68881)
4996 {
4997 current_architecture |= m68881;
4998 no_68881 = 0;
4999 }
5000 else if (arch == m68851)
5001 {
5002 current_architecture |= m68851;
5003 no_68851 = 0;
5004 }
5005 else
5006 /* ??? */
5007 abort ();
5008 break;
5009 }
5010 if (i == n_archs)
5011 {
5012 as_bad ("unrecognized architecture specification `%s'", arg);
5013 return 0;
5014 }
5015 }
5016 break;
5017
5018 case OPTION_PIC:
5019 case 'k':
5020 flag_want_pic = 1;
5021 break; /* -pic, Position Independent Code */
5022
5023 case OPTION_REGISTER_PREFIX_OPTIONAL:
5024 flag_reg_prefix_optional = 1;
5025 break;
5026
5027 default:
5028 return 0;
5029 }
5030
5031 return 1;
5032 }
5033
5034 void
5035 md_show_usage (stream)
5036 FILE *stream;
5037 {
5038 fprintf(stream, "\
5039 680X0 options:\n\
5040 -l use 1 word for refs to undefined symbols [default 2]\n\
5041 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040\n\
5042 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32\n\
5043 specify variant of 680X0 architecture [default 68020]\n\
5044 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
5045 target has/lacks floating-point coprocessor\n\
5046 [default yes for 68020, 68030, and cpu32]\n\
5047 -m68851 | -mno-68851\n\
5048 target has/lacks memory-management unit coprocessor\n\
5049 [default yes for 68020 and up]\n\
5050 -pic, -k generate position independent code\n\
5051 -S turn jbsr into jsr\n\
5052 --register-prefix-optional\n\
5053 recognize register names without prefix character\n");
5054 }
5055 \f
5056 #ifdef TEST2
5057
5058 /* TEST2: Test md_assemble() */
5059 /* Warning, this routine probably doesn't work anymore */
5060
5061 main ()
5062 {
5063 struct m68k_it the_ins;
5064 char buf[120];
5065 char *cp;
5066 int n;
5067
5068 m68k_ip_begin ();
5069 for (;;)
5070 {
5071 if (!gets (buf) || !*buf)
5072 break;
5073 if (buf[0] == '|' || buf[1] == '.')
5074 continue;
5075 for (cp = buf; *cp; cp++)
5076 if (*cp == '\t')
5077 *cp = ' ';
5078 if (is_label (buf))
5079 continue;
5080 memset (&the_ins, '\0', sizeof (the_ins));
5081 m68k_ip (&the_ins, buf);
5082 if (the_ins.error)
5083 {
5084 printf ("Error %s in %s\n", the_ins.error, buf);
5085 }
5086 else
5087 {
5088 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
5089 for (n = 0; n < the_ins.numo; n++)
5090 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
5091 printf (" ");
5092 print_the_insn (&the_ins.opcode[0], stdout);
5093 (void) putchar ('\n');
5094 }
5095 for (n = 0; n < strlen (the_ins.args) / 2; n++)
5096 {
5097 if (the_ins.operands[n].error)
5098 {
5099 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
5100 continue;
5101 }
5102 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
5103 if (the_ins.operands[n].b_const)
5104 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
5105 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
5106 if (the_ins.operands[n].b_iadd)
5107 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
5108 (void) putchar ('\n');
5109 }
5110 }
5111 m68k_ip_end ();
5112 return 0;
5113 }
5114
5115 is_label (str)
5116 char *str;
5117 {
5118 while (*str == ' ')
5119 str++;
5120 while (*str && *str != ' ')
5121 str++;
5122 if (str[-1] == ':' || str[1] == '=')
5123 return 1;
5124 return 0;
5125 }
5126
5127 #endif
5128
5129 /* Possible states for relaxation:
5130
5131 0 0 branch offset byte (bra, etc)
5132 0 1 word
5133 0 2 long
5134
5135 1 0 indexed offsets byte a0@(32,d4:w:1) etc
5136 1 1 word
5137 1 2 long
5138
5139 2 0 two-offset index word-word a0@(32,d4)@(45) etc
5140 2 1 word-long
5141 2 2 long-word
5142 2 3 long-long
5143
5144 */
5145
5146 /* We have no need to default values of symbols. */
5147
5148 /* ARGSUSED */
5149 symbolS *
5150 md_undefined_symbol (name)
5151 char *name;
5152 {
5153 return 0;
5154 }
5155
5156 /* Round up a section size to the appropriate boundary. */
5157 valueT
5158 md_section_align (segment, size)
5159 segT segment;
5160 valueT size;
5161 {
5162 return size; /* Byte alignment is fine */
5163 }
5164
5165 /* Exactly what point is a PC-relative offset relative TO?
5166 On the 68k, they're relative to the address of the offset, plus
5167 its size. (??? Is this right? FIXME-SOON!) */
5168 long
5169 md_pcrel_from (fixP)
5170 fixS *fixP;
5171 {
5172 return (fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address);
5173 }
5174
5175 #ifndef BFD_ASSEMBLER
5176 /*ARGSUSED*/
5177 void
5178 tc_coff_symbol_emit_hook (ignore)
5179 symbolS *ignore;
5180 {
5181 }
5182
5183 int
5184 tc_coff_sizemachdep (frag)
5185 fragS *frag;
5186 {
5187 switch (frag->fr_subtype & 0x3)
5188 {
5189 case BYTE:
5190 return 1;
5191 case SHORT:
5192 return 2;
5193 case LONG:
5194 return 4;
5195 default:
5196 abort ();
5197 }
5198 }
5199 #endif
5200
5201 /* end of tc-m68k.c */
GDB Binutils - Deliverables
This page took 0.132742 seconds and 5 git commands to generate.