projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Moved struct m68k_incant and related macros earlier in the file.
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
2 slow to compile, easy to find file.
3
4 Copyright (C) 1987, 1991, 1992, 1993 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21
22 #include <ctype.h>
23 #define NO_RELOC 0
24 #include "as.h"
25
26 /* need TARGET_CPU */
27 #include "config.h"
28
29 #include "obstack.h"
30
31 /* The opcode table is too big for gcc, which (currently) requires
32 exponential space at compile time for initialized arrays. */
33 #ifdef __GNUC__
34 #define DO_BREAK_UP_BIG_DECL
35 #define BREAK_UP_BIG_DECL }; struct m68k_opcode m68k_opcodes_2[] = {
36 #define AND_OTHER_PART sizeof (m68k_opcodes_2)
37 #endif
38
39 /* Note that this file includes real declarations and thus can only be
40 included by one source file per executable. */
41 #include "opcode/m68k.h"
42
43 #ifndef BFD_ASSEMBLER
44 #ifdef TE_SUN
45 /* This variable contains the value to write out at the beginning of
46 the a.out file. The 2<<16 means that this is a 68020 file instead
47 of an old-style 68000 file */
48
49 long omagic = 2 << 16 | OMAGIC; /* Magic byte for header file */
50 #else
51 long omagic = OMAGIC;
52 #endif
53 #endif
54
55 /* This array holds the chars that always start a comment. If the
56 pre-processor is disabled, these aren't very useful */
57 CONST char comment_chars[] = "|";
58
59 /* This array holds the chars that only start a comment at the beginning of
60 a line. If the line seems to have the form '# 123 filename'
61 .line and .file directives will appear in the pre-processed output */
62 /* Note that input_file.c hand checks for '#' at the beginning of the
63 first line of the input file. This is because the compiler outputs
64 #NO_APP at the beginning of its output. */
65 /* Also note that comments like this one will always work. */
66 CONST char line_comment_chars[] = "#";
67
68 CONST char line_separator_chars[] = "";
69
70 /* Chars that can be used to separate mant from exp in floating point nums */
71 CONST char EXP_CHARS[] = "eE";
72
73 /* Chars that mean this number is a floating point constant, as
74 in "0f12.456" or "0d1.2345e12". */
75
76 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
77
78 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
79 changed in read.c . Ideally it shouldn't have to know about it at all,
80 but nothing is ideal around here. */
81
82 const int md_reloc_size = 8; /* Size of relocation record */
83
84 /* Its an arbitrary name: This means I don't approve of it */
85 /* See flames below */
86 static struct obstack robyn;
87
88 #define TAB(x,y) (((x)<<2)+(y))
89 #define TABTYPE(xy) ((xy) >> 2)
90 #define BYTE 0
91 #define SHORT 1
92 #define LONG 2
93 #define SZ_UNDEF 3
94 #undef BRANCH
95 #define ABRANCH 1
96 #define FBRANCH 2
97 #define PCREL 3
98 #define BCC68000 4
99 #define DBCC 5
100 #define PCLEA 6
101
102 struct m68k_incant
103 {
104 char *m_operands;
105 unsigned long m_opcode;
106 short m_opnum;
107 short m_codenum;
108 int m_arch;
109 struct m68k_incant *m_next;
110 };
111
112 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
113 #define gettwo(x) (((x)->m_opcode)&0xffff)
114
115 /* Operands we can parse: (And associated modes)
116
117 numb: 8 bit num
118 numw: 16 bit num
119 numl: 32 bit num
120 dreg: data reg 0-7
121 reg: address or data register
122 areg: address register
123 apc: address register, PC, ZPC or empty string
124 num: 16 or 32 bit num
125 num2: like num
126 sz: w or l if omitted, l assumed
127 scale: 1 2 4 or 8 if omitted, 1 assumed
128
129 7.4 IMMED #num --> NUM
130 0.? DREG dreg --> dreg
131 1.? AREG areg --> areg
132 2.? AINDR areg@ --> *(areg)
133 3.? AINC areg@+ --> *(areg++)
134 4.? ADEC areg@- --> *(--areg)
135 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
136 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
137 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
138 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
139 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
140 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
141 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
142 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
143 7.0 ABSL num:sz --> *(num)
144 num --> *(num) (sz L assumed)
145 *** MSCR otherreg --> Magic
146 With -l option
147 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
148 ?.? DINDR dreg@ --> (dreg) -- cas2 only
149
150 examples:
151 #foo #0x35 #12
152 d2
153 a4
154 a3@
155 a5@+
156 a6@-
157 a2@(12) pc@(14)
158 a1@(5,d2:w:1) @(45,d6:l:4)
159 pc@(a2) @(d4)
160 etc . . .
161
162
163 #name@(numw) -->turn into PC rel mode
164 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
165
166 */
167
168 enum operand_type
169 {
170 IMMED = 1,
171 DREG,
172 AREG,
173 AINDR,
174 ADEC,
175 AINC,
176 AOFF,
177 AINDX,
178 APODX,
179 AMIND,
180 APRDX,
181 ABSL,
182 MSCR,
183 REGLST,
184 DINDR
185 };
186
187
188 struct m68k_exp
189 {
190 char *e_beg;
191 char *e_end;
192 segT e_seg;
193 expressionS e_exp;
194 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
195 };
196
197 /* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
198 8-15==addr reg for operands that take both types */
199
200 enum _register
201 {
202 DATA = 1, /* 1- 8 == data registers 0-7 */
203 DATA0 = DATA,
204 DATA1,
205 DATA2,
206 DATA3,
207 DATA4,
208 DATA5,
209 DATA6,
210 DATA7,
211
212 ADDR,
213 ADDR0 = ADDR,
214 ADDR1,
215 ADDR2,
216 ADDR3,
217 ADDR4,
218 ADDR5,
219 ADDR6,
220 ADDR7,
221
222 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
223 /* I think. . . */
224
225 SP = ADDR7,
226
227 FPREG, /* Eight FP registers */
228 FP0 = FPREG,
229 FP1,
230 FP2,
231 FP3,
232 FP4,
233 FP5,
234 FP6,
235 FP7,
236 COPNUM = (FPREG + 8), /* Co-processor #1-#8 */
237 COP0 = COPNUM,
238 COP1,
239 COP2,
240 COP3,
241 COP4,
242 COP5,
243 COP6,
244 COP7,
245 PC, /* Program counter */
246 ZPC, /* Hack for Program space, but 0 addressing */
247 SR, /* Status Reg */
248 CCR, /* Condition code Reg */
249
250 /* These have to be in order for the movec instruction to work. */
251 USP, /* User Stack Pointer */
252 ISP, /* Interrupt stack pointer */
253 SFC,
254 DFC,
255 CACR,
256 VBR,
257 CAAR,
258 MSP,
259 ITT0,
260 ITT1,
261 DTT0,
262 DTT1,
263 MMUSR,
264 TC,
265 SRP,
266 URP,
267 /* end of movec ordering constraints */
268
269 FPI,
270 FPS,
271 FPC,
272
273 DRP, /* 68851 or 68030 MMU regs */
274 CRP,
275 CAL,
276 VAL,
277 SCC,
278 AC,
279 BAD,
280 BAD0 = BAD,
281 BAD1,
282 BAD2,
283 BAD3,
284 BAD4,
285 BAD5,
286 BAD6,
287 BAD7,
288 BAC,
289 BAC0 = BAC,
290 BAC1,
291 BAC2,
292 BAC3,
293 BAC4,
294 BAC5,
295 BAC6,
296 BAC7,
297 PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040)
298 and ACUSR on 68ec030 */
299 PCSR,
300
301 IC, /* instruction cache token */
302 DC, /* data cache token */
303 NC, /* no cache token */
304 BC, /* both caches token */
305
306 TT0, /* 68030 access control unit regs */
307 TT1,
308 };
309
310 /* Internal form of an operand. */
311 struct m68k_op
312 {
313 char *error; /* Couldn't parse it */
314 enum operand_type mode; /* What mode this instruction is in. */
315 enum _register reg; /* Base register */
316 struct m68k_exp *con1;
317 int ireg; /* Index register */
318 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
319 int imul; /* Multipy ireg by this (1,2,4,or 8) */
320 struct m68k_exp *con2;
321 };
322
323 /* internal form of a 68020 instruction */
324 struct m68k_it
325 {
326 char *error;
327 char *args; /* list of opcode info */
328 int numargs;
329
330 int numo; /* Number of shorts in opcode */
331 short opcode[11];
332
333 struct m68k_op operands[6];
334
335 int nexp; /* number of exprs in use */
336 struct m68k_exp exprs[4];
337
338 int nfrag; /* Number of frags we have to produce */
339 struct
340 {
341 int fragoff; /* Where in the current opcode[] the frag ends */
342 symbolS *fadd;
343 long foff;
344 int fragty;
345 }
346 fragb[4];
347
348 int nrel; /* Num of reloc strucs in use */
349 struct
350 {
351 int n;
352 expressionS exp;
353 char wid;
354 char pcrel;
355 }
356 reloc[5]; /* Five is enough??? */
357 };
358
359 #define cpu_of_arch(x) ((x) & m68000up)
360 #define float_of_arch(x) ((x) & mfloat)
361 #define mmu_of_arch(x) ((x) & mmmu)
362
363 static struct m68k_it the_ins; /* the instruction being assembled */
364
365 #define seg(exp) ((exp)->e_seg)
366 #define op(exp) ((exp)->e_exp.X_op)
367 #define adds(exp) ((exp)->e_exp.X_add_symbol)
368 #define subs(exp) ((exp)->e_exp.X_op_symbol)
369 #define offs(exp) ((exp)->e_exp.X_add_number)
370
371 /* Macros for adding things to the m68k_it struct */
372
373 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
374
375 /* Like addword, but goes BEFORE general operands */
376 static void
377 insop (w, opcode)
378 int w;
379 struct m68k_incant *opcode;
380 {
381 int z;
382 for(z=the_ins.numo;z>opcode->m_codenum;--z)
383 the_ins.opcode[z]=the_ins.opcode[z-1];
384 for(z=0;z<the_ins.nrel;z++)
385 the_ins.reloc[z].n+=2;
386 the_ins.opcode[opcode->m_codenum]=w;
387 the_ins.numo++;
388 }
389
390 static struct m68k_exp *
391 add_exp (beg, end)
392 char *beg;
393 char *end;
394 {
395 the_ins.exprs[the_ins.nexp].e_beg=beg;
396 the_ins.exprs[the_ins.nexp].e_end=end;
397 return &the_ins.exprs[the_ins.nexp++];
398 }
399
400
401 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
402 Blecch. */
403 static void
404 add_fix (width, exp, pc_rel)
405 char width;
406 struct m68k_exp *exp;
407 int pc_rel;
408 {
409 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
410 ? (the_ins.numo*2-1)
411 : (((width)=='b')
412 ? ((the_ins.numo-1)*2)
413 : (the_ins.numo*2)));
414 the_ins.reloc[the_ins.nrel].exp = exp->e_exp;
415 the_ins.reloc[the_ins.nrel].wid = width;
416 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
417 }
418
419 static void
420 add_frag(add,off,type)
421 symbolS *add;
422 long off;
423 int type;
424 {
425 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
426 the_ins.fragb[the_ins.nfrag].fadd=add;
427 the_ins.fragb[the_ins.nfrag].foff=off;
428 the_ins.fragb[the_ins.nfrag++].fragty=type;
429 }
430
431 #define isvar(exp) \
432 ((exp) && op (exp) != O_constant && op (exp) != O_big)
433
434 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
435 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
436 static int get_regs PARAMS ((int i, char *str, struct m68k_op *opP));
437 static int reverse_16_bits PARAMS ((int in));
438 static int reverse_8_bits PARAMS ((int in));
439 static int try_index PARAMS ((char **s, struct m68k_op *opP));
440 static void install_gen_operand PARAMS ((int mode, int val));
441 static void install_operand PARAMS ((int mode, int val));
442 static void s_bss PARAMS ((int));
443 static void s_data1 PARAMS ((int));
444 static void s_data2 PARAMS ((int));
445 static void s_even PARAMS ((int));
446 static void s_proc PARAMS ((int));
447
448 static int current_architecture;
449
450 /* BCC68000 is for patching in an extra jmp instruction for long offsets
451 on the 68000. The 68000 doesn't support long branches with branchs */
452
453 /* This table desribes how you change sizes for the various types of variable
454 size expressions. This version only supports two kinds. */
455
456 /* Note that calls to frag_var need to specify the maximum expansion
457 needed; this is currently 10 bytes for DBCC. */
458
459 /* The fields are:
460 How far Forward this mode will reach:
461 How far Backward this mode will reach:
462 How many bytes this mode will add to the size of the frag
463 Which mode to go to if the offset won't fit in this one
464 */
465 CONST relax_typeS md_relax_table[] =
466 {
467 {1, 1, 0, 0}, /* First entries aren't used */
468 {1, 1, 0, 0}, /* For no good reason except */
469 {1, 1, 0, 0}, /* that the VAX doesn't either */
470 {1, 1, 0, 0},
471
472 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
473 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
474 {0, 0, 4, 0},
475 {1, 1, 0, 0},
476
477 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
478 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
479 {0, 0, 4, 0},
480 {1, 1, 0, 0},
481
482 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
483 {(32767), (-32768), 2, TAB (PCREL, LONG)},
484 {0, 0, 4, 0},
485 {1, 1, 0, 0},
486
487 {(127), (-128), 0, TAB (BCC68000, SHORT)},
488 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
489 {0, 0, 6, 0}, /* jmp long space */
490 {1, 1, 0, 0},
491
492 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
493 {(32767), (-32768), 2, TAB (DBCC, LONG)},
494 {0, 0, 10, 0}, /* bra/jmp long space */
495 {1, 1, 0, 0},
496
497 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
498 {32767, -32768, 2, TAB (PCLEA, LONG)},
499 {0, 0, 6, 0},
500 {1, 1, 0, 0},
501
502 };
503
504 /* These are the machine dependent pseudo-ops. These are included so
505 the assembler can work on the output from the SUN C compiler, which
506 generates these.
507 */
508
509 /* This table describes all the machine specific pseudo-ops the assembler
510 has to support. The fields are:
511 pseudo-op name without dot
512 function to call to execute this pseudo-op
513 Integer arg to pass to the function
514 */
515 CONST pseudo_typeS md_pseudo_table[] =
516 {
517 {"data1", s_data1, 0},
518 {"data2", s_data2, 0},
519 {"bss", s_bss, 0},
520 {"even", s_even, 0},
521 {"skip", s_space, 0},
522 {"proc", s_proc, 0},
523 #ifdef TE_SUN3
524 {"align", s_align_bytes, 0},
525 #endif
526 {0, 0, 0}
527 };
528
529
530 /* The mote pseudo ops are put into the opcode table, since they
531 don't start with a . they look like opcodes to gas.
532 */
533 extern void obj_coff_section ();
534
535 CONST pseudo_typeS mote_pseudo_table[] =
536 {
537
538 {"dc.l", cons, 4},
539 {"dc", cons, 2},
540 {"dc.w", cons, 2},
541 {"dc.b", cons, 1},
542
543 {"ds.l", s_space, 4},
544 {"ds", s_space, 2},
545 {"ds.w", s_space, 2},
546 {"ds.b", s_space, 1},
547
548 {"xdef", s_globl, 0},
549 {"align", s_align_ptwo, 0},
550 #ifdef M68KCOFF
551 {"sect", obj_coff_section, 0},
552 {"section", obj_coff_section, 0},
553 #endif
554 {0, 0, 0}
555 };
556
557 #define issbyte(x) ((x)>=-128 && (x)<=127)
558 #define isubyte(x) ((x)>=0 && (x)<=255)
559 #define issword(x) ((x)>=-32768 && (x)<=32767)
560 #define isuword(x) ((x)>=0 && (x)<=65535)
561
562 #define isbyte(x) ((x)>= -255 && (x)<=255)
563 #define isword(x) ((x)>=-32768 && (x)<=65535)
564 #define islong(x) (1)
565
566 extern char *input_line_pointer;
567
568 enum
569 {
570 FAIL = 0,
571 OK = 1,
572 };
573
574 /* JF these tables here are for speed at the expense of size */
575 /* You can replace them with the #if 0 versions if you really
576 need space and don't mind it running a bit slower */
577
578 static char mklower_table[256];
579 #define mklower(c) (mklower_table[(unsigned char)(c)])
580 static char notend_table[256];
581 static char alt_notend_table[256];
582 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
583 alt_notend_table[(unsigned char)(s[1])])))
584
585 #if 0
586 #define mklower(c) (isupper(c) ? tolower(c) : c)
587 #endif
588
589
590 /* JF modified this to handle cases where the first part of a symbol name
591 looks like a register */
592
593 /*
594 * m68k_reg_parse() := if it looks like a register, return it's token &
595 * advance the pointer.
596 */
597
598 enum _register
599 m68k_reg_parse (ccp)
600 register char **ccp;
601 {
602 char *start = *ccp;
603 char c;
604 char *p;
605 symbolS *symbolP;
606
607 #ifdef REGISTER_PREFIX
608 if (*start != REGISTER_PREFIX)
609 return FAIL;
610 p = start + 1;
611 #else
612 p = start;
613 if (*p == OPTIONAL_REGISTER_PREFIX)
614 p++, start++;
615 #endif
616 if (!isalpha (*p) || !is_name_beginner (*p))
617 return FAIL;
618
619 c = *p++;
620 while (isalpha (c) || isdigit (c) || c == '_')
621 {
622 c = *p++;
623 }
624
625 *--p = 0;
626 symbolP = symbol_find (start);
627 *p = c;
628
629 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
630 {
631 *ccp = p;
632 return S_GET_VALUE (symbolP);
633 }
634
635 return FAIL;
636 }
637
638 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
639 #define SKIP_W() { ss++; if(*ss==' ') ss++;}
640
641 /* Parse an index specification using Motorola syntax. */
642
643 static int
644 try_moto_index (s, opP)
645 char **s;
646 struct m68k_op *opP;
647 {
648 register int i;
649 char *ss;
650
651 ss = *s;
652 /* SKIP_W(); */
653 if (*ss == ' ')
654 ss++;
655 i = m68k_reg_parse (&ss);
656 if (!(i >= DATA + 0 && i <= ADDR + 7))
657 { /* if i is not DATA or ADDR reg */
658 opP->error = "Invalid index register";
659 *s = ss;
660 return FAIL;
661 }
662 opP->ireg = i;
663 /* SKIP_W(); */
664 if (*ss == ')')
665 {
666 opP->isiz = 0;
667 opP->imul = 1;
668 SKIP_W ();
669 *s = ss;
670 return OK;
671 }
672 if (*ss != '.')
673 {
674 opP->error = "Missing . in index register";
675 *s = ss;
676 return FAIL;
677 }
678 SKIP_W ();
679 if (mklower (*ss) == 'w')
680 opP->isiz = 2;
681 else if (mklower (*ss) == 'l')
682 opP->isiz = 3;
683 else
684 {
685 opP->error = "Size spec not .W or .L";
686 *s = ss;
687 return FAIL;
688 }
689 SKIP_W ();
690 if (*ss == '.' || *ss == '*')
691 {
692 SKIP_W ();
693 switch (*ss)
694 {
695 case '1':
696 case '2':
697 case '4':
698 case '8':
699 opP->imul = *ss - '0';
700 break;
701 default:
702 opP->error = "index multiplier not 1, 2, 4 or 8";
703 *s = ss;
704 return FAIL;
705 }
706 SKIP_W ();
707 }
708 else
709 opP->imul = 1;
710 if (*ss != ')')
711 {
712 opP->error = "Missing )";
713 *s = ss;
714 return FAIL;
715 }
716 SKIP_W ();
717 *s = ss;
718 return OK;
719 }
720
721 /*
722 *
723 * try_index := data_or_address_register + ')' + SKIP_W
724 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
725 *
726 * multiplier := <empty>
727 * | ':' + multiplier_number
728 * ;
729 *
730 * multiplier_number := '1' | '2' | '4' | '8' ;
731 *
732 * size_spec := 'l' | 'L' | 'w' | 'W' ;
733 *
734 * SKIP_W := <empty> | ' ' ;
735 *
736 */
737
738 static int
739 try_index (s, opP)
740 char **s;
741 struct m68k_op *opP;
742 {
743 register int i;
744 char *ss;
745
746 ss = *s;
747 /* SKIP_W(); */
748 i = m68k_reg_parse (&ss);
749 if (!(i >= DATA + 0 && i <= ADDR + 7))
750 { /* if i is not DATA or ADDR reg */
751 *s = ss;
752 return FAIL;
753 }
754 opP->ireg = i;
755 /* SKIP_W(); */
756 if (*ss == ')')
757 {
758 opP->isiz = 0;
759 opP->imul = 1;
760 SKIP_W ();
761 *s = ss;
762 return OK;
763 }
764 if (*ss != ':')
765 {
766 opP->error = "Missing : in index register";
767 *s = ss;
768 return FAIL;
769 }
770 SKIP_W ();
771 switch (*ss)
772 {
773 case 'w':
774 case 'W':
775 opP->isiz = 2;
776 break;
777 case 'l':
778 case 'L':
779 opP->isiz = 3;
780 break;
781 default:
782 opP->error = "Index register size spec not :w or :l";
783 *s = ss;
784 return FAIL;
785 }
786 SKIP_W ();
787 if (*ss == ':')
788 {
789 SKIP_W ();
790 switch (*ss)
791 {
792 case '1':
793 case '2':
794 case '4':
795 case '8':
796 if (cpu_of_arch (current_architecture) < m68020)
797 {
798 opP->error = "no index scaling in pre-68020's";
799 *s = ss;
800 return FAIL;
801 }
802 opP->imul = *ss - '0';
803 break;
804 default:
805 opP->error = "index multiplier not 1, 2, 4 or 8";
806 *s = ss;
807 return FAIL;
808 }
809 SKIP_W ();
810 }
811 else
812 opP->imul = 1;
813 if (*ss != ')')
814 {
815 opP->error = "Missing )";
816 *s = ss;
817 return FAIL;
818 }
819 SKIP_W ();
820 *s = ss;
821 return OK;
822 } /* try_index() */
823
824 /* Ian Taylor expanded this function to accept both MIT and Motorola
825 syntax. I removed the old comment, since it was wrong. The syntax
826 this accepted even before my changes was complex and undocumented.
827 I mainly added a large case when the operand string does not
828 contain an '@', since the Motorola syntax does not use the '@'
829 character. */
830
831 int
832 m68k_ip_op (str, opP)
833 char *str;
834 register struct m68k_op *opP;
835 {
836 char *strend;
837 long i;
838 char *parse_index ();
839 int needp;
840
841 if (*str == ' ')
842 {
843 str++;
844 } /* Find the beginning of the string */
845
846 if (!*str)
847 {
848 opP->error = "Missing operand";
849 return FAIL;
850 } /* Out of gas */
851
852 for (strend = str; *strend; strend++)
853 ;
854 --strend;
855
856 if (*str == '#')
857 {
858 str++;
859 opP->con1 = add_exp (str, strend);
860 opP->mode = IMMED;
861 return OK;
862 } /* Guess what: A constant. Shar and enjoy */
863
864 i = m68k_reg_parse (&str);
865
866 if (i != FAIL)
867 {
868 if (*str == '/' || *str == '-')
869 {
870 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
871 opP->mode = REGLST;
872 return get_regs (i, str, opP);
873 }
874 if (*str == '\0')
875 {
876 opP->reg = i;
877 /* "Rn" Register Direct mode */
878 if (i >= DATA + 0 && i <= DATA + 7)
879 opP->mode = DREG;
880 else if (i >= ADDR + 0 && i <= ADDR + 7)
881 opP->mode = AREG;
882 else
883 opP->mode = MSCR;
884 return OK;
885 }
886 }
887
888 if (*str != '@')
889 {
890 char *stmp;
891
892 if ((stmp = strchr (str, '@')) != 0)
893 {
894 opP->con1 = add_exp (str, stmp - 1);
895 if (stmp == strend)
896 {
897 opP->mode = AINDX;
898 return (OK);
899 }
900
901 if ((current_architecture & m68020up) == 0)
902 {
903 return (FAIL);
904 } /* if target is not a '20 or better */
905
906 stmp++;
907 if (*stmp++ != '(' || *strend-- != ')')
908 {
909 opP->error = "Malformed operand";
910 return (FAIL);
911 }
912 i = try_index (&stmp, opP);
913 opP->con2 = add_exp (stmp, strend);
914
915 if (i == FAIL)
916 {
917 opP->mode = AMIND;
918 }
919 else
920 {
921 opP->mode = APODX;
922 }
923 return (OK);
924 } /* if there's an '@' */
925
926 #ifndef MIT_SYNTAX_ONLY
927 /* The operand has no '@'. Try to parse it using
928 Motorola syntax. */
929 /* Logic of the parsing switch(*str):
930 case opP->mode =
931 ---- -----------
932 #anything IMMED 1
933 REG AREG or DREG or MSCR 3 or 2 or 13
934 REG- or REG/ REGLST 14
935 (REG) AINDR 4
936 (REG)+ AINC 6
937 (REG,INDX) AINDX 8
938 (EXPR,REG) AOFF 7
939 (EXPR,REG,INDX) AINDX 8
940 -(REG) ADEC 5
941 EXP2(REG) AOFF 7
942 EXP2(REG,INDX) AINDX 8
943 EXP2 ABSL 12
944
945 REG means truth(m68k_reg_parse(&str))
946 INDX means truth(try_moto_index(&str,opP))
947 EXPR means not REG
948 EXP2 means not REG and not '(' and not '-('
949 */
950
951 if (*str == '(')
952 {
953 str++;
954 i = m68k_reg_parse (&str);
955 if ((i < ADDR + 0 || i > ADDR + 7)
956 && (i < DATA + 0 || i > DATA + 7
957 || *str != ')' || str[1] != '0')
958 && i != PC && i != ZPC && i != FAIL)
959 {
960 /* Can't indirect off non address regs */
961 opP->error = "Invalid indirect register";
962 return FAIL;
963 }
964 if (i != FAIL)
965 {
966 opP->reg = i;
967 if (*str == ')')
968 {
969 str++;
970 if (*str == '\0')
971 {
972 /* "(An)" Address Register Indirect mode
973 or "(Dn)" for cas2. */
974 if (i >= DATA + 0 && i <= DATA + 7)
975 opP->mode = DINDR;
976 else
977 opP->mode = AINDR;
978 return OK;
979 }
980 if (*str == '+')
981 {
982 if (str[1] == '\0')
983 {
984 /* "(An)+" Register Indirect w Postincrement */
985 opP->mode = AINC;
986 return OK;
987 }
988 }
989 opP->error = "Junk after indirect";
990 return FAIL;
991 }
992 if (*str == ',')
993 {
994 str++;
995 i = try_moto_index (&str, opP);
996 if (i == FAIL)
997 return FAIL;
998 /* "(An,Rn)" Register Indirect with Index mode*/
999 opP->mode = AINDX;
1000 return OK;
1001 }
1002 else
1003 {
1004 opP->error = "Bad indirect syntax";
1005 return FAIL;
1006 }
1007 }
1008 else
1009 {
1010 /* "(EXPR,..." , a displacement */
1011 char *stmp;
1012 char *index ();
1013
1014 if ((stmp = index (str, ',')) != NULL)
1015 {
1016 opP->con1 = add_exp (str, stmp - 1);
1017 str = stmp;
1018 SKIP_WHITE ();
1019 i = m68k_reg_parse (&str);
1020 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC)
1021 {
1022 /* Can't indirect off non address regs */
1023 opP->error = "Invalid indirect register";
1024 return FAIL;
1025 }
1026 if (i != FAIL)
1027 {
1028 opP->reg = i;
1029 if (*str == ')')
1030 {
1031 /* "(d,An)" Register Indirect w Displacement */
1032 opP->mode = AOFF;
1033 return OK;
1034 }
1035 if (*str == ',')
1036 {
1037 str++;
1038 i = try_moto_index (&str, opP);
1039 if (i == FAIL)
1040 return FAIL;
1041 /* "(d,An,Rn)" Register Indirect with Index */
1042 opP->mode = AINDX;
1043 return OK;
1044 }
1045 else
1046 {
1047 opP->error = "Bad indirect syntax";
1048 return FAIL;
1049 }
1050 }
1051 else
1052 {
1053 opP->error = "Invalid register";
1054 return FAIL;
1055 }
1056 }
1057 else
1058 {
1059 opP->mode = ABSL;
1060 opP->con1 = add_exp (str - 1, strend);
1061 return OK;
1062 }
1063 }
1064 }
1065
1066 if (*str == '-')
1067 {
1068 if (str[1] == '(')
1069 {
1070 str = str + 2;
1071 i = m68k_reg_parse (&str);
1072 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL)
1073 {
1074 /* Can't indirect off non address regs */
1075 opP->error = "Invalid indirect register";
1076 return FAIL;
1077 }
1078 if (i != FAIL)
1079 {
1080 opP->reg = i;
1081 if (*str == ')')
1082 {
1083 str++;
1084 if (*str == '\0')
1085 {
1086 /* "-(An)" Register Indirect with Predecrement */
1087 opP->mode = ADEC;
1088 return OK;
1089 }
1090 opP->error = "Junk after indirect";
1091 return FAIL;
1092 }
1093 opP->error = "Bad indirect syntax";
1094 return FAIL;
1095 }
1096 opP->mode = ABSL;
1097 opP->con1 = add_exp (str - 2, strend);
1098 return OK;
1099 }
1100 /* if '-' but not "-(', do nothing */
1101 }
1102
1103 /* whether *str=='-' or not */
1104 {
1105 /* "EXP2" or "EXP2(REG..." */
1106 char *stmp;
1107 char *index ();
1108 if ((stmp = index (str, '(')) != NULL)
1109 {
1110 char *ostr = str;
1111
1112 opP->con1 = add_exp (str, stmp - 1);
1113 str = stmp + 1;
1114 i = m68k_reg_parse (&str);
1115 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC
1116 && i != ZPC && i != FAIL)
1117 {
1118 /* Can't indirect off non address regs */
1119 opP->error = "Invalid indirect register";
1120 return FAIL;
1121 }
1122 if (i != FAIL)
1123 {
1124 opP->reg = i;
1125 if (*str == ')')
1126 {
1127 /* "d(An)" Register Indirect w Displacement */
1128 opP->mode = AOFF;
1129 return OK;
1130 }
1131 if (*str == ',')
1132 {
1133 str++;
1134 i = try_moto_index (&str, opP);
1135 if (i == FAIL)
1136 return FAIL;
1137 /* "d(An,Rn)" Register Indirect with Index */
1138 opP->mode = AINDX;
1139 return OK;
1140 }
1141 else
1142 {
1143 opP->error = "Bad indirect syntax";
1144 return FAIL;
1145 }
1146 }
1147 else
1148 {
1149 opP->mode = ABSL;
1150 opP->con1 = add_exp (ostr, strend);
1151 return OK;
1152 }
1153 }
1154 else
1155 {
1156 /* "EXP2" Absolute */
1157 opP->mode = ABSL;
1158 opP->isiz = 0;
1159 if (strend[-1] == '.' || strend[-1] == ':')
1160 {
1161 /* mode ==foo.[wl] */
1162 switch (*strend)
1163 {
1164 case 'w':
1165 case 'W':
1166 opP->isiz = 2;
1167 break;
1168 case 'l':
1169 case 'L':
1170 opP->isiz = 3;
1171 break;
1172 }
1173 }
1174 opP->con1 = add_exp (str, strend);
1175 return OK;
1176 }
1177 }
1178 /*NOTREACHED*/
1179 #else /* defined (MIT_SYNTAX_ONLY) */
1180 opP->mode = ABSL;
1181 opP->con1 = add_exp (str, strend);
1182 return OK;
1183 #endif /* defined (MIT_SYNTAX_ONLY) */
1184 }
1185
1186 opP->reg = i;
1187
1188 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1189 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL
1190 && (str[1] != '\0' || i < DATA + 0 || i > DATA + 7))
1191 {
1192 opP->error = "Invalid indirect register";
1193 return FAIL;
1194 }
1195 know (*str == '@');
1196
1197 str++;
1198 switch (*str)
1199 {
1200 case '\0':
1201 if (i < DATA + 0 || i > DATA + 7)
1202 opP->mode = AINDR;
1203 else
1204 opP->mode = DINDR;
1205 return OK;
1206 case '-':
1207 opP->mode = ADEC;
1208 return OK;
1209 case '+':
1210 opP->mode = AINC;
1211 return OK;
1212 case '(':
1213 str++;
1214 break;
1215 default:
1216 opP->error = "Junk after indirect";
1217 return FAIL;
1218 }
1219 /* Some kind of indexing involved. Lets find out how bad it is */
1220 i = try_index (&str, opP);
1221 /* Didn't start with an index reg, maybe its offset or offset,reg */
1222 if (i == FAIL)
1223 {
1224 char *beg_str;
1225
1226 beg_str = str;
1227 for (i = 1; i;)
1228 {
1229 switch (*str++)
1230 {
1231 case '\0':
1232 opP->error = "Missing )";
1233 return FAIL;
1234 case ',':
1235 i = 0;
1236 break;
1237 case '(':
1238 i++;
1239 break;
1240 case ')':
1241 --i;
1242 break;
1243 }
1244 }
1245 #if 0
1246 if (str[-3]==':')
1247 {
1248 int siz;
1249
1250 switch (str[-2])
1251 {
1252 case 'b':
1253 case 'B':
1254 siz=1;
1255 break;
1256 case 'w':
1257 case 'W':
1258 siz=2;
1259 break;
1260 case 'l':
1261 case 'L':
1262 siz=3;
1263 break;
1264 default:
1265 opP->error="Specified size isn't :w or :l";
1266 return FAIL;
1267 }
1268 opP->con1=add_exp(beg_str,str-4);
1269 opP->con1->e_siz=siz;
1270 }
1271 else
1272 #endif
1273 opP->con1 = add_exp (beg_str, str - 2);
1274 /* Should be offset,reg */
1275 if (str[-1] == ',')
1276 {
1277 i = try_index (&str, opP);
1278 if (i == FAIL)
1279 {
1280 opP->error = "Malformed index reg";
1281 return FAIL;
1282 }
1283 }
1284 }
1285 /* We've now got offset) offset,reg) or reg) */
1286
1287 if (*str == '\0')
1288 {
1289 /* Th-the-thats all folks */
1290 if (opP->reg == FAIL)
1291 opP->mode = AINDX; /* Other form of indirect */
1292 else if (opP->ireg == FAIL)
1293 opP->mode = AOFF;
1294 else
1295 opP->mode = AINDX;
1296 return (OK);
1297 }
1298 /* Next thing had better be another @ */
1299 if (*str == '@')
1300 {
1301 if (str[1] == '(')
1302 {
1303 needp = 1;
1304 str += 2;
1305 }
1306 else
1307 {
1308 needp = 0;
1309 str++;
1310 }
1311 }
1312
1313 if ((current_architecture & m68020up) == 0)
1314 {
1315 return (FAIL);
1316 } /* if target is not a '20 or better */
1317
1318
1319 if (opP->ireg != FAIL)
1320 {
1321 opP->mode = APRDX;
1322
1323 i = try_index (&str, opP);
1324 if (i != FAIL)
1325 {
1326 opP->error = "Two index registers! not allowed!";
1327 return (FAIL);
1328 }
1329 }
1330 else
1331 {
1332 i = try_index (&str, opP);
1333 }
1334
1335 if (i == FAIL)
1336 {
1337 char *beg_str;
1338
1339 beg_str = str;
1340
1341 for (i = 1; i;)
1342 {
1343 switch (*str++)
1344 {
1345 case '\0':
1346 if (needp)
1347 opP->error = "Missing )";
1348 return (FAIL);
1349 break;
1350 case ',':
1351 i = 0;
1352 break;
1353 case '(':
1354 i++;
1355 break;
1356 case ')':
1357 --i;
1358 break;
1359 }
1360 }
1361
1362 opP->con2 = add_exp (beg_str, str - 2);
1363
1364 if (str[-1] == ',')
1365 {
1366 if (opP->ireg != FAIL)
1367 {
1368 opP->error = "Can't have two index regs";
1369 return (FAIL);
1370 }
1371
1372 i = try_index (&str, opP);
1373
1374 if (i == FAIL)
1375 {
1376 opP->error = "malformed index reg";
1377 return (FAIL);
1378 }
1379
1380 opP->mode = APODX;
1381 }
1382 else if (opP->ireg != FAIL)
1383 {
1384 opP->mode = APRDX;
1385 }
1386 else
1387 {
1388 opP->mode = AMIND;
1389 }
1390 }
1391 else
1392 {
1393 opP->mode = APODX;
1394 }
1395
1396 if (*str != '\0')
1397 {
1398 opP->error = "Junk after indirect";
1399 return FAIL;
1400 }
1401 return (OK);
1402 } /* m68k_ip_op() */
1403
1404
1405 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
1406
1407 short
1408 tc_coff_fix2rtype (fixP)
1409 fixS *fixP;
1410 {
1411 return (fixP->fx_pcrel ?
1412 (fixP->fx_size == 1 ? R_PCRBYTE :
1413 fixP->fx_size == 2 ? R_PCRWORD :
1414 R_PCRLONG) :
1415 (fixP->fx_size == 1 ? R_RELBYTE :
1416 fixP->fx_size == 2 ? R_RELWORD :
1417 R_RELLONG));
1418
1419
1420 }
1421
1422 #endif
1423
1424 #ifdef BFD_ASSEMBLER
1425
1426 arelent *
1427 tc_gen_reloc (section, fixp)
1428 asection *section;
1429 fixS *fixp;
1430 {
1431 arelent *reloc;
1432 bfd_reloc_code_real_type code;
1433
1434 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1435 switch (F (fixp->fx_size, fixp->fx_pcrel))
1436 {
1437 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1438 MAP (1, 0, BFD_RELOC_8);
1439 MAP (2, 0, BFD_RELOC_16);
1440 MAP (4, 0, BFD_RELOC_32);
1441 MAP (1, 1, BFD_RELOC_8_PCREL);
1442 MAP (2, 1, BFD_RELOC_16_PCREL);
1443 MAP (4, 1, BFD_RELOC_32_PCREL);
1444 default:
1445 abort ();
1446 }
1447
1448 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
1449 assert (reloc != 0);
1450 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
1451 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1452 if (fixp->fx_pcrel)
1453 reloc->addend = fixp->fx_addnumber;
1454 else
1455 reloc->addend = 0;
1456
1457 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1458 assert (reloc->howto != 0);
1459
1460 return reloc;
1461 }
1462
1463 #endif /* BFD_ASSEMBLER */
1464
1465 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1466 main ()
1467 {
1468 char buf[128];
1469 struct m68k_op thark;
1470
1471 for (;;)
1472 {
1473 if (!gets (buf))
1474 break;
1475 memset (&thark, '\0', sizeof (thark));
1476 if (!m68k_ip_op (buf, &thark))
1477 printf ("FAIL:");
1478 if (thark.error)
1479 printf ("op1 error %s in %s\n", thark.error, buf);
1480 printf ("mode %d, reg %d, ", thark.mode, thark.reg);
1481 if (thark.b_const)
1482 printf ("Constant: '%.*s',", 1 + thark.e_const - thark.b_const, thark.b_const);
1483 printf ("ireg %d, isiz %d, imul %d ", thark.ireg, thark.isiz, thark.imul);
1484 if (thark.b_iadd)
1485 printf ("Iadd: '%.*s'", 1 + thark.e_iadd - thark.b_iadd, thark.b_iadd);
1486 printf ("\n");
1487 }
1488 exit (0);
1489 }
1490
1491 #endif
1492
1493
1494 /* Handle of the OPCODE hash table. NULL means any use before
1495 m68k_ip_begin() will crash. */
1496 static struct hash_control *op_hash;
1497 \f
1498
1499 /*
1500 * m 6 8 k _ i p ( )
1501 *
1502 * This converts a string into a 68k instruction.
1503 * The string must be a bare single instruction in sun format
1504 * with RMS-style 68020 indirects
1505 * (example: )
1506 *
1507 * It provides some error messages: at most one fatal error message (which
1508 * stops the scan) and at most one warning message for each operand.
1509 * The 68k instruction is returned in exploded form, since we have no
1510 * knowledge of how you parse (or evaluate) your expressions.
1511 * We do however strip off and decode addressing modes and operation
1512 * mnemonic.
1513 *
1514 * This function's value is a string. If it is not "" then an internal
1515 * logic error was found: read this code to assign meaning to the string.
1516 * No argument string should generate such an error string:
1517 * it means a bug in our code, not in the user's text.
1518 *
1519 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1520 * this function.
1521 */
1522
1523 /* JF this function no longer returns a useful value. Sorry */
1524 void
1525 m68k_ip (instring)
1526 char *instring;
1527 {
1528 register char *p;
1529 register struct m68k_op *opP;
1530 register struct m68k_incant *opcode;
1531 register char *s;
1532 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1533 char *pdot, *pdotmove;
1534 int siz1, siz2;
1535 char c;
1536 int losing;
1537 int opsfound;
1538 char *crack_operand ();
1539 LITTLENUM_TYPE words[6];
1540 LITTLENUM_TYPE *wordp;
1541 unsigned long ok_arch = 0;
1542
1543 if (*instring == ' ')
1544 instring++; /* skip leading whitespace */
1545
1546 /* Scan up to end of operation-code, which MUST end in end-of-string
1547 or exactly 1 space. */
1548 pdot = 0;
1549 for (p = instring; *p != '\0'; p++)
1550 {
1551 if (*p == ' ')
1552 break;
1553 if (*p == '.')
1554 pdot = p;
1555 }
1556
1557 if (p == instring)
1558 {
1559 the_ins.error = "No operator";
1560 the_ins.opcode[0] = 0;
1561 /* the_ins.numo=1; */
1562 return;
1563 }
1564
1565 /* p now points to the end of the opcode name, probably whitespace.
1566 make sure the name is null terminated by clobbering the whitespace,
1567 look it up in the hash table, then fix it back.
1568 Remove a dot, first, since the opcode tables have none. */
1569 if (pdot != NULL)
1570 {
1571 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1572 *pdotmove = pdotmove[1];
1573 p--;
1574 }
1575
1576 c = *p;
1577 *p = '\0';
1578 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
1579 *p = c;
1580
1581 if (pdot != NULL)
1582 {
1583 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1584 *pdotmove = pdotmove[-1];
1585 *pdot = '.';
1586 ++p;
1587 }
1588
1589 if (opcode == NULL)
1590 {
1591 the_ins.error = "Unknown operator";
1592 the_ins.opcode[0] = 0;
1593 /* the_ins.numo=1; */
1594 return;
1595 }
1596
1597 /* found a legitimate opcode, start matching operands */
1598 while (*p == ' ')
1599 ++p;
1600
1601
1602 if (opcode->m_operands == 0)
1603 {
1604 char *old = input_line_pointer;
1605 *old = '\n';
1606 input_line_pointer = p;
1607 /* Ahh - it's a motorola style psuedo op */
1608 mote_pseudo_table[opcode->m_opnum].poc_handler
1609 (mote_pseudo_table[opcode->m_opnum].poc_val);
1610 input_line_pointer = old;
1611 *old = 0;
1612
1613 return;
1614 }
1615
1616 for (opP = &the_ins.operands[0]; *p; opP++)
1617 {
1618
1619 p = crack_operand (p, opP);
1620
1621 if (opP->error)
1622 {
1623 the_ins.error = opP->error;
1624 return;
1625 }
1626 }
1627
1628 opsfound = opP - &the_ins.operands[0];
1629
1630 /* This ugly hack is to support the floating pt opcodes in their standard form */
1631 /* Essentially, we fake a first enty of type COP#1 */
1632 if (opcode->m_operands[0] == 'I')
1633 {
1634 int n;
1635
1636 for (n = opsfound; n > 0; --n)
1637 the_ins.operands[n] = the_ins.operands[n - 1];
1638
1639 memset ((char *) (&the_ins.operands[0]), '\0', sizeof (the_ins.operands[0]));
1640 the_ins.operands[0].mode = MSCR;
1641 the_ins.operands[0].reg = COPNUM; /* COP #1 */
1642 opsfound++;
1643 }
1644
1645 /* We've got the operands. Find an opcode that'll accept them */
1646 for (losing = 0;;)
1647 {
1648 /* If we didn't get the right number of ops, or we have no
1649 common model with this pattern then reject this pattern. */
1650
1651 if (opsfound != opcode->m_opnum
1652 || ((opcode->m_arch & current_architecture) == 0))
1653 {
1654 ++losing;
1655 ok_arch |= opcode->m_arch;
1656 }
1657 else
1658 {
1659 for (s = opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++)
1660 {
1661 /* Warning: this switch is huge! */
1662 /* I've tried to organize the cases into this order:
1663 non-alpha first, then alpha by letter. Lower-case
1664 goes directly before uppercase counterpart. */
1665 /* Code with multiple case ...: gets sorted by the lowest
1666 case ... it belongs to. I hope this makes sense. */
1667 switch (*s)
1668 {
1669 case '!':
1670 if (opP->mode == MSCR || opP->mode == IMMED
1671 || opP->mode == DREG || opP->mode == AREG
1672 || opP->mode == AINC || opP->mode == ADEC
1673 || opP->mode == REGLST)
1674 losing++;
1675 break;
1676
1677 case '`':
1678 switch (opP->mode)
1679 {
1680 case MSCR:
1681 case IMMED:
1682 case DREG:
1683 case AREG:
1684 case AINC:
1685 case REGLST:
1686 case AINDR:
1687 losing++;
1688 break;
1689 default:
1690 break;
1691 }
1692 break;
1693
1694 case '#':
1695 if (opP->mode != IMMED)
1696 losing++;
1697 else
1698 {
1699 long t;
1700
1701 t = get_num (opP->con1, 80);
1702 if (s[1] == 'b' && !isbyte (t))
1703 losing++;
1704 else if (s[1] == 'w' && !isword (t))
1705 losing++;
1706 }
1707 break;
1708
1709 case '^':
1710 case 'T':
1711 if (opP->mode != IMMED)
1712 losing++;
1713 break;
1714
1715 case '$':
1716 if (opP->mode == MSCR || opP->mode == AREG ||
1717 opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1718 losing++;
1719 break;
1720
1721 case '%':
1722 if (opP->mode == MSCR || opP->reg == PC ||
1723 opP->reg == ZPC || opP->mode == REGLST)
1724 losing++;
1725 break;
1726
1727
1728 case '&':
1729 if (opP->mode == MSCR || opP->mode == DREG ||
1730 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC ||
1731 opP->mode == AINC || opP->mode == ADEC || opP->mode == REGLST)
1732 losing++;
1733 break;
1734
1735 case '*':
1736 if (opP->mode == MSCR || opP->mode == REGLST)
1737 losing++;
1738 break;
1739
1740 case '+':
1741 if (opP->mode != AINC)
1742 losing++;
1743 break;
1744
1745 case '-':
1746 if (opP->mode != ADEC)
1747 losing++;
1748 break;
1749
1750 case '/':
1751 if (opP->mode == MSCR || opP->mode == AREG ||
1752 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->mode == REGLST)
1753 losing++;
1754 break;
1755
1756 case ';':
1757 if (opP->mode == MSCR || opP->mode == AREG || opP->mode == REGLST)
1758 losing++;
1759 break;
1760
1761 case '?':
1762 if (opP->mode == MSCR || opP->mode == AREG ||
1763 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->reg == PC ||
1764 opP->reg == ZPC || opP->mode == REGLST)
1765 losing++;
1766 break;
1767
1768 case '@':
1769 if (opP->mode == MSCR || opP->mode == AREG ||
1770 opP->mode == IMMED || opP->mode == REGLST)
1771 losing++;
1772 break;
1773
1774 case '~': /* For now! (JF FOO is this right?) */
1775 if (opP->mode == MSCR || opP->mode == DREG ||
1776 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1777 losing++;
1778 break;
1779
1780 case '3':
1781 if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1))
1782 losing++;
1783 break;
1784
1785 case 'A':
1786 if (opP->mode != AREG)
1787 losing++;
1788 break;
1789 case 'a':
1790 if (opP->mode != AINDR)
1791 {
1792 ++losing;
1793 } /* if not address register indirect */
1794 break;
1795 case 'B': /* FOO */
1796 if (opP->mode != ABSL || (flagseen['S'] && instring[0] == 'j'
1797 && instring[1] == 'b'
1798 && instring[2] == 's'
1799 && instring[3] == 'r'))
1800 losing++;
1801 break;
1802
1803 case 'C':
1804 if (opP->mode != MSCR || opP->reg != CCR)
1805 losing++;
1806 break;
1807
1808 case 'd': /* FOO This mode is a KLUDGE!! */
1809 if (opP->mode != AOFF && (opP->mode != ABSL ||
1810 opP->con1->e_beg[0] != '(' || opP->con1->e_end[0] != ')'))
1811 losing++;
1812 break;
1813
1814 case 'D':
1815 if (opP->mode != DREG)
1816 losing++;
1817 break;
1818
1819 case 'F':
1820 if (opP->mode != MSCR || opP->reg < (FPREG + 0) || opP->reg > (FPREG + 7))
1821 losing++;
1822 break;
1823
1824 case 'I':
1825 if (opP->mode != MSCR || opP->reg < COPNUM ||
1826 opP->reg >= COPNUM + 7)
1827 losing++;
1828 break;
1829
1830 case 'J':
1831 if (opP->mode != MSCR
1832 || opP->reg < USP
1833 || opP->reg > URP
1834 || cpu_of_arch (current_architecture) < m68010 /* before 68010 had none */
1835 || (cpu_of_arch (current_architecture) < m68020
1836 && opP->reg != SFC
1837 && opP->reg != DFC
1838 && opP->reg != USP
1839 && opP->reg != VBR) /* 68010's had only these */
1840 || (cpu_of_arch (current_architecture) < m68040
1841 && opP->reg != SFC
1842 && opP->reg != DFC
1843 && opP->reg != USP
1844 && opP->reg != VBR
1845 && opP->reg != CACR
1846 && opP->reg != CAAR
1847 && opP->reg != MSP
1848 && opP->reg != ISP) /* 680[23]0's have only these */
1849 || (cpu_of_arch (current_architecture) == m68040 /* 68040 has all but this */
1850 && opP->reg == CAAR))
1851 {
1852 losing++;
1853 } /* doesn't cut it */
1854 break;
1855
1856 case 'k':
1857 if (opP->mode != IMMED)
1858 losing++;
1859 break;
1860
1861 case 'l':
1862 case 'L':
1863 if (opP->mode == DREG || opP->mode == AREG || opP->mode == FPREG)
1864 {
1865 if (s[1] == '8')
1866 losing++;
1867 else
1868 {
1869 opP->mode = REGLST;
1870 opP->reg = 1 << (opP->reg - DATA);
1871 }
1872 }
1873 else if (opP->mode != REGLST)
1874 {
1875 losing++;
1876 }
1877 else if (s[1] == '8' && opP->reg & 0x0FFffFF)
1878 losing++;
1879 else if (s[1] == '3' && opP->reg & 0x7000000)
1880 losing++;
1881 break;
1882
1883 case 'M':
1884 if (opP->mode != IMMED)
1885 losing++;
1886 else
1887 {
1888 long t;
1889
1890 t = get_num (opP->con1, 0);
1891 if (!issbyte (t)
1892 || isvar (opP->con1))
1893 losing++;
1894 }
1895 break;
1896
1897 case 'O':
1898 if (opP->mode != DREG && opP->mode != IMMED)
1899 losing++;
1900 break;
1901
1902 case 'Q':
1903 if (opP->mode != IMMED)
1904 losing++;
1905 else
1906 {
1907 long t;
1908
1909 t = get_num (opP->con1, 80);
1910 if (t < 1 || t > 8 || isvar (opP->con1))
1911 losing++;
1912 }
1913 break;
1914
1915 case 'R':
1916 if (opP->mode != DREG && opP->mode != AREG)
1917 losing++;
1918 break;
1919
1920 case 'r':
1921 if (opP->mode != AINDR && opP->mode != DINDR)
1922 losing++;
1923 break;
1924
1925 case 's':
1926 if (opP->mode != MSCR || !(opP->reg == FPI || opP->reg == FPS || opP->reg == FPC))
1927 losing++;
1928 break;
1929
1930 case 'S':
1931 if (opP->mode != MSCR || opP->reg != SR)
1932 losing++;
1933 break;
1934
1935 case 't':
1936 if (opP->mode != IMMED)
1937 losing++;
1938 else
1939 {
1940 long t = get_num (opP->con1, 80);
1941 if (t < 0 || t > 7 || isvar (opP->con1))
1942 losing++;
1943 }
1944 break;
1945
1946 case 'U':
1947 if (opP->mode != MSCR || opP->reg != USP)
1948 losing++;
1949 break;
1950
1951 /* JF these are out of order. We could put them
1952 in order if we were willing to put up with
1953 bunches of #ifdef m68851s in the code.
1954
1955 Don't forget that you need these operands
1956 to use 68030 MMU instructions. */
1957 #ifndef NO_68851
1958 /* Memory addressing mode used by pflushr */
1959 case '|':
1960 if (opP->mode == MSCR || opP->mode == DREG ||
1961 opP->mode == AREG || opP->mode == REGLST)
1962 losing++;
1963 break;
1964
1965 case 'f':
1966 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
1967 losing++;
1968 break;
1969
1970 case 'P':
1971 if (opP->mode != MSCR
1972 || (opP->reg != TC && opP->reg != CAL
1973 && opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
1974 losing++;
1975 break;
1976
1977 case 'V':
1978 if (opP->reg != VAL)
1979 losing++;
1980 break;
1981
1982 case 'W':
1983 if (opP->mode != MSCR
1984 || (opP->reg != DRP && opP->reg != SRP
1985 && opP->reg != CRP))
1986 losing++;
1987 break;
1988
1989 case 'X':
1990 if (opP->mode != MSCR ||
1991 (!(opP->reg >= BAD && opP->reg <= BAD + 7) &&
1992 !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1993 losing++;
1994 break;
1995
1996 case 'Y':
1997 if (opP->reg != PSR)
1998 losing++;
1999 break;
2000
2001 case 'Z':
2002 if (opP->reg != PCSR)
2003 losing++;
2004 break;
2005 #endif
2006 case 'c':
2007 if (opP->reg != NC
2008 && opP->reg != IC
2009 && opP->reg != DC
2010 && opP->reg != BC)
2011 {
2012 losing++;
2013 } /* not a cache specifier. */
2014 break;
2015
2016 case '_':
2017 if (opP->mode != ABSL)
2018 {
2019 ++losing;
2020 } /* not absolute */
2021 break;
2022
2023 default:
2024 as_fatal ("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
2025 *s, __LINE__, __FILE__);
2026 } /* switch on type of operand */
2027
2028 if (losing)
2029 break;
2030 } /* for each operand */
2031 } /* if immediately wrong */
2032
2033 if (!losing)
2034 {
2035 break;
2036 } /* got it. */
2037
2038 opcode = opcode->m_next;
2039
2040 if (!opcode)
2041 {
2042 if (ok_arch
2043 && !(ok_arch & current_architecture))
2044 {
2045 char buf[200], *cp;
2046 int len;
2047 strcpy (buf, "invalid instruction for this architecture; needs ");
2048 cp = buf + strlen (buf);
2049 switch (ok_arch)
2050 {
2051 case mfloat:
2052 strcpy (cp, "fpu (68040 or 68881/68882)");
2053 break;
2054 case mmmu:
2055 strcpy (cp, "mmu (68030 or 68851)");
2056 break;
2057 case m68020up:
2058 strcpy (cp, "68020 or higher");
2059 break;
2060 case m68000up:
2061 strcpy (cp, "68000 or higher");
2062 break;
2063 case m68010up:
2064 strcpy (cp, "68010 or higher");
2065 break;
2066 default:
2067 {
2068 int got_one = 0, idx;
2069 static const struct
2070 {
2071 int arch;
2072 const char *name;
2073 }
2074 archs[] =
2075 {
2076 { m68000, "68000" },
2077 { m68010, "68010" },
2078 { m68020, "68020" },
2079 { m68030, "68030" },
2080 { m68040, "68040" },
2081 { cpu32, "cpu32" },
2082 { m68881, "68881" },
2083 { m68851, "68851" }
2084 };
2085 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]); idx++)
2086 {
2087 if (archs[idx].arch & ok_arch)
2088 {
2089 if (got_one)
2090 {
2091 strcpy (cp, " or ");
2092 cp += strlen (cp);
2093 }
2094 got_one = 1;
2095 strcpy (cp, archs[idx].name);
2096 cp += strlen (cp);
2097 }
2098 }
2099 }
2100 }
2101 len = cp - buf + 1;
2102 cp = malloc (len);
2103 strcpy (cp, buf);
2104 the_ins.error = cp;
2105 }
2106 else
2107 the_ins.error = "operands mismatch";
2108 return;
2109 } /* Fell off the end */
2110
2111 losing = 0;
2112 }
2113
2114 /* now assemble it */
2115
2116 the_ins.args = opcode->m_operands;
2117 the_ins.numargs = opcode->m_opnum;
2118 the_ins.numo = opcode->m_codenum;
2119 the_ins.opcode[0] = getone (opcode);
2120 the_ins.opcode[1] = gettwo (opcode);
2121
2122 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2123 {
2124 /* This switch is a doozy.
2125 Watch the first step; its a big one! */
2126 switch (s[0])
2127 {
2128
2129 case '*':
2130 case '~':
2131 case '%':
2132 case ';':
2133 case '@':
2134 case '!':
2135 case '&':
2136 case '$':
2137 case '?':
2138 case '/':
2139 case '`':
2140 #ifndef NO_68851
2141 case '|':
2142 #endif
2143 switch (opP->mode)
2144 {
2145 case IMMED:
2146 tmpreg = 0x3c; /* 7.4 */
2147 if (strchr ("bwl", s[1]))
2148 nextword = get_num (opP->con1, 80);
2149 else
2150 nextword = get_num (opP->con1, 0);
2151 if (isvar (opP->con1))
2152 add_fix (s[1], opP->con1, 0);
2153 switch (s[1])
2154 {
2155 case 'b':
2156 if (!isbyte (nextword))
2157 opP->error = "operand out of range";
2158 addword (nextword);
2159 baseo = 0;
2160 break;
2161 case 'w':
2162 if (!isword (nextword))
2163 opP->error = "operand out of range";
2164 addword (nextword);
2165 baseo = 0;
2166 break;
2167 case 'l':
2168 addword (nextword >> 16);
2169 addword (nextword);
2170 baseo = 0;
2171 break;
2172
2173 case 'f':
2174 baseo = 2;
2175 outro = 8;
2176 break;
2177 case 'F':
2178 baseo = 4;
2179 outro = 11;
2180 break;
2181 case 'x':
2182 baseo = 6;
2183 outro = 15;
2184 break;
2185 case 'p':
2186 baseo = 6;
2187 outro = -1;
2188 break;
2189 default:
2190 as_fatal ("Internal error: Can't decode %c%c in line %d of file \"%s\"",
2191 *s, s[1], __LINE__, __FILE__);
2192 }
2193 if (!baseo)
2194 break;
2195
2196 /* We gotta put out some float */
2197 if (op (opP->con1) != O_big)
2198 {
2199 valueT val;
2200 int gencnt;
2201
2202 /* Can other cases happen here? */
2203 if (op (opP->con1) != O_constant)
2204 abort ();
2205
2206 val = (valueT) offs (opP->con1);
2207 gencnt = 0;
2208 do
2209 {
2210 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2211 val >>= LITTLENUM_NUMBER_OF_BITS;
2212 ++gencnt;
2213 }
2214 while (val != 0);
2215 offs (opP->con1) = gencnt;
2216 }
2217 if (offs (opP->con1) > 0)
2218 {
2219 if (offs (opP->con1) > baseo)
2220 {
2221 as_warn ("Bignum too big for %c format; truncated", s[1]);
2222 offs (opP->con1) = baseo;
2223 }
2224 baseo -= offs (opP->con1);
2225 while (baseo--)
2226 addword (0);
2227 for (wordp = generic_bignum + offs (opP->con1) - 1; offs (opP->con1)--; --wordp)
2228 addword (*wordp);
2229 break;
2230 }
2231 gen_to_words (words, baseo, (long) outro);
2232 for (wordp = words; baseo--; wordp++)
2233 addword (*wordp);
2234 break;
2235 case DREG:
2236 tmpreg = opP->reg - DATA; /* 0.dreg */
2237 break;
2238 case AREG:
2239 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2240 break;
2241 case AINDR:
2242 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2243 break;
2244 case ADEC:
2245 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2246 break;
2247 case AINC:
2248 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2249 break;
2250 case AOFF:
2251
2252 nextword = get_num (opP->con1, 80);
2253 /* Force into index mode. Hope this works */
2254
2255 /* We do the first bit for 32-bit displacements, and the
2256 second bit for 16 bit ones. It is possible that we
2257 should make the default be WORD instead of LONG, but
2258 I think that'd break GCC, so we put up with a little
2259 inefficiency for the sake of working output. */
2260
2261 if (!issword (nextword)
2262 || (isvar (opP->con1)
2263 && ((opP->con1->e_siz == 0
2264 && flagseen['l'] == 0)
2265 || opP->con1->e_siz == 3)))
2266 {
2267
2268 if (opP->reg == PC)
2269 tmpreg = 0x3B; /* 7.3 */
2270 else
2271 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2272 if (isvar (opP->con1))
2273 {
2274 if (opP->reg == PC)
2275 {
2276 add_frag (adds (opP->con1),
2277 offs (opP->con1) + 2,
2278 TAB (PCLEA, SZ_UNDEF));
2279 break;
2280 }
2281 else
2282 {
2283 addword (0x0170);
2284 add_fix ('l', opP->con1, 0);
2285 }
2286 }
2287 else
2288 addword (0x0170);
2289 addword (nextword >> 16);
2290 }
2291 else
2292 {
2293 if (opP->reg == PC)
2294 tmpreg = 0x3A; /* 7.2 */
2295 else
2296 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2297
2298 if (isvar (opP->con1))
2299 {
2300 if (opP->reg == PC)
2301 {
2302 add_fix ('w', opP->con1, 1);
2303 }
2304 else
2305 add_fix ('w', opP->con1, 0);
2306 }
2307 }
2308 addword (nextword);
2309 break;
2310
2311 case APODX:
2312 case AMIND:
2313 case APRDX:
2314 know (current_architecture & m68020up);
2315 /* intentional fall-through */
2316 case AINDX:
2317 nextword = 0;
2318 baseo = get_num (opP->con1, 80);
2319 outro = get_num (opP->con2, 80);
2320 /* Figure out the `addressing mode'.
2321 Also turn on the BASE_DISABLE bit, if needed. */
2322 if (opP->reg == PC || opP->reg == ZPC)
2323 {
2324 tmpreg = 0x3b;/* 7.3 */
2325 if (opP->reg == ZPC)
2326 nextword |= 0x80;
2327 }
2328 else if (opP->reg == FAIL)
2329 {
2330 nextword |= 0x80;
2331 tmpreg = 0x30;/* 6.garbage */
2332 }
2333 else
2334 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2335
2336 siz1 = (opP->con1) ? opP->con1->e_siz : 0;
2337 siz2 = (opP->con2) ? opP->con2->e_siz : 0;
2338
2339 /* Index register stuff */
2340 if (opP->ireg >= DATA + 0 && opP->ireg <= ADDR + 7)
2341 {
2342 nextword |= (opP->ireg - DATA) << 12;
2343
2344 if (opP->isiz == 0 || opP->isiz == 3)
2345 nextword |= 0x800;
2346 switch (opP->imul)
2347 {
2348 case 1:
2349 break;
2350 case 2:
2351 nextword |= 0x200;
2352 break;
2353 case 4:
2354 nextword |= 0x400;
2355 break;
2356 case 8:
2357 nextword |= 0x600;
2358 break;
2359 default:
2360 as_fatal ("failed sanity check.");
2361 }
2362 /* IF its simple,
2363 GET US OUT OF HERE! */
2364
2365 /* Must be INDEX, with an index
2366 register. Address register
2367 cannot be ZERO-PC, and either
2368 :b was forced, or we know
2369 it will fit */
2370 if (opP->mode == AINDX
2371 && opP->reg != FAIL
2372 && opP->reg != ZPC
2373 && (siz1 == 1
2374 || (issbyte (baseo)
2375 && !isvar (opP->con1))))
2376 {
2377 nextword += baseo & 0xff;
2378 addword (nextword);
2379 if (isvar (opP->con1))
2380 add_fix ('B', opP->con1, 0);
2381 break;
2382 }
2383 }
2384 else
2385 nextword |= 0x40; /* No index reg */
2386
2387 /* It isn't simple. */
2388 nextword |= 0x100;
2389 /* If the guy specified a width, we assume that it is
2390 wide enough. Maybe it isn't. If so, we lose. */
2391 switch (siz1)
2392 {
2393 case 0:
2394 if (isvar (opP->con1) || !issword (baseo))
2395 {
2396 siz1 = 3;
2397 nextword |= 0x30;
2398 }
2399 else if (baseo == 0)
2400 nextword |= 0x10;
2401 else
2402 {
2403 nextword |= 0x20;
2404 siz1 = 2;
2405 }
2406 break;
2407 case 1:
2408 as_warn ("Byte dispacement won't work. Defaulting to :w");
2409 case 2:
2410 nextword |= 0x20;
2411 break;
2412 case 3:
2413 nextword |= 0x30;
2414 break;
2415 }
2416
2417 /* Figure out innner displacement stuff */
2418 if (opP->mode != AINDX)
2419 {
2420 switch (siz2)
2421 {
2422 case 0:
2423 if (isvar (opP->con2) || !issword (outro))
2424 {
2425 siz2 = 3;
2426 nextword |= 0x3;
2427 }
2428 else if (outro == 0)
2429 nextword |= 0x1;
2430 else
2431 {
2432 nextword |= 0x2;
2433 siz2 = 2;
2434 }
2435 break;
2436 case 1:
2437 as_warn ("Byte dispacement won't work. Defaulting to :w");
2438 case 2:
2439 nextword |= 0x2;
2440 break;
2441 case 3:
2442 nextword |= 0x3;
2443 break;
2444 }
2445 if (opP->mode == APODX)
2446 nextword |= 0x04;
2447 else if (opP->mode == AMIND)
2448 nextword |= 0x40;
2449 }
2450 addword (nextword);
2451
2452 if (isvar (opP->con1))
2453 {
2454 if (opP->reg == PC || opP->reg == ZPC)
2455 {
2456 opP->con1->e_exp.X_add_number += 6;
2457 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 1);
2458 }
2459 else
2460 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 0);
2461 }
2462 if (siz1 == 3)
2463 addword (baseo >> 16);
2464 if (siz1)
2465 addword (baseo);
2466
2467 if (isvar (opP->con2))
2468 {
2469 if (opP->reg == PC || opP->reg == ZPC)
2470 {
2471 opP->con1->e_exp.X_add_number += 6;
2472 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 1);
2473 }
2474 else
2475 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 0);
2476 }
2477 if (siz2 == 3)
2478 addword (outro >> 16);
2479 if (siz2)
2480 addword (outro);
2481
2482 break;
2483
2484 case ABSL:
2485 nextword = get_num (opP->con1, 80);
2486 switch (opP->con1->e_siz)
2487 {
2488 default:
2489 as_warn ("Unknown size for absolute reference");
2490 case 0:
2491 if (!isvar (opP->con1) && issword (offs (opP->con1)))
2492 {
2493 tmpreg = 0x38; /* 7.0 */
2494 addword (nextword);
2495 break;
2496 }
2497 /* Don't generate pc relative code on 68010 and
2498 68000. */
2499 if (isvar (opP->con1)
2500 && !subs (opP->con1)
2501 && seg (opP->con1) == text_section
2502 && now_seg == text_section
2503 && cpu_of_arch (current_architecture) >= m68020
2504 && !flagseen['S']
2505 && !strchr ("~%&$?", s[0]))
2506 {
2507 tmpreg = 0x3A; /* 7.2 */
2508 add_frag (adds (opP->con1),
2509 offs (opP->con1),
2510 TAB (PCREL, SZ_UNDEF));
2511 break;
2512 }
2513 case 3: /* Fall through into long */
2514 if (isvar (opP->con1))
2515 add_fix ('l', opP->con1, 0);
2516
2517 tmpreg = 0x39;/* 7.1 mode */
2518 addword (nextword >> 16);
2519 addword (nextword);
2520 break;
2521
2522 case 2: /* Word */
2523 if (isvar (opP->con1))
2524 add_fix ('w', opP->con1, 0);
2525
2526 tmpreg = 0x38;/* 7.0 mode */
2527 addword (nextword);
2528 break;
2529 }
2530 break;
2531 case DINDR:
2532 as_bad ("invalid indirect register");
2533 break;
2534 case MSCR:
2535 default:
2536 as_bad ("unknown/incorrect operand");
2537 /* abort(); */
2538 }
2539 install_gen_operand (s[1], tmpreg);
2540 break;
2541
2542 case '#':
2543 case '^':
2544 switch (s[1])
2545 { /* JF: I hate floating point! */
2546 case 'j':
2547 tmpreg = 70;
2548 break;
2549 case '8':
2550 tmpreg = 20;
2551 break;
2552 case 'C':
2553 tmpreg = 50;
2554 break;
2555 case '3':
2556 default:
2557 tmpreg = 80;
2558 break;
2559 }
2560 tmpreg = get_num (opP->con1, tmpreg);
2561 if (isvar (opP->con1))
2562 add_fix (s[1], opP->con1, 0);
2563 switch (s[1])
2564 {
2565 case 'b': /* Danger: These do no check for
2566 certain types of overflow.
2567 user beware! */
2568 if (!isbyte (tmpreg))
2569 opP->error = "out of range";
2570 insop (tmpreg, opcode);
2571 if (isvar (opP->con1))
2572 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2573 break;
2574 case 'w':
2575 if (!isword (tmpreg))
2576 opP->error = "out of range";
2577 insop (tmpreg, opcode);
2578 if (isvar (opP->con1))
2579 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2580 break;
2581 case 'l':
2582 /* Because of the way insop works, we put these two out
2583 backwards. */
2584 insop (tmpreg, opcode);
2585 insop (tmpreg >> 16, opcode);
2586 if (isvar (opP->con1))
2587 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2588 break;
2589 case '3':
2590 tmpreg &= 0xFF;
2591 case '8':
2592 case 'C':
2593 install_operand (s[1], tmpreg);
2594 break;
2595 default:
2596 as_fatal ("Internal error: Unknown mode #%c in line %d of file \"%s\"", s[1], __LINE__, __FILE__);
2597 }
2598 break;
2599
2600 case '+':
2601 case '-':
2602 case 'A':
2603 case 'a':
2604 install_operand (s[1], opP->reg - ADDR);
2605 break;
2606
2607 case 'B':
2608 tmpreg = get_num (opP->con1, 80);
2609 switch (s[1])
2610 {
2611 case 'B':
2612 /* Needs no offsetting */
2613 add_fix ('B', opP->con1, 1);
2614 break;
2615 case 'W':
2616 /* Offset the displacement to be relative to byte disp location */
2617 opP->con1->e_exp.X_add_number += 2;
2618 add_fix ('w', opP->con1, 1);
2619 addword (0);
2620 break;
2621 case 'L':
2622 long_branch:
2623 if (cpu_of_arch (current_architecture) < m68020) /* 68000 or 010 */
2624 as_warn ("Can't use long branches on 68000/68010");
2625 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2626 /* Offset the displacement to be relative to byte disp location */
2627 opP->con1->e_exp.X_add_number += 4;
2628 add_fix ('l', opP->con1, 1);
2629 addword (0);
2630 addword (0);
2631 break;
2632 case 'g':
2633 if (subs (opP->con1)) /* We can't relax it */
2634 goto long_branch;
2635
2636 /* This could either be a symbol, or an
2637 absolute address. No matter, the
2638 frag hacking will finger it out.
2639 Not quite: it can't switch from
2640 BRANCH to BCC68000 for the case
2641 where opnd is absolute (it needs
2642 to use the 68000 hack since no
2643 conditional abs jumps). */
2644 if (((cpu_of_arch (current_architecture) < m68020) || (0 == adds (opP->con1)))
2645 && (the_ins.opcode[0] >= 0x6200)
2646 && (the_ins.opcode[0] <= 0x6f00))
2647 {
2648 add_frag (adds (opP->con1), offs (opP->con1), TAB (BCC68000, SZ_UNDEF));
2649 }
2650 else
2651 {
2652 add_frag (adds (opP->con1), offs (opP->con1), TAB (ABRANCH, SZ_UNDEF));
2653 }
2654 break;
2655 case 'w':
2656 if (isvar (opP->con1))
2657 {
2658 #if 1
2659 /* check for DBcc instruction */
2660 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2661 {
2662 /* size varies if patch */
2663 /* needed for long form */
2664 add_frag (adds (opP->con1), offs (opP->con1), TAB (DBCC, SZ_UNDEF));
2665 break;
2666 }
2667 #endif
2668 /* Don't ask! */
2669 opP->con1->e_exp.X_add_number += 2;
2670 add_fix ('w', opP->con1, 1);
2671 }
2672 addword (0);
2673 break;
2674 case 'C': /* Fixed size LONG coproc branches */
2675 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2676 /* Offset the displacement to be relative to byte disp location */
2677 /* Coproc branches don't have a byte disp option, but they are
2678 compatible with the ordinary branches, which do... */
2679 opP->con1->e_exp.X_add_number += 4;
2680 add_fix ('l', opP->con1, 1);
2681 addword (0);
2682 addword (0);
2683 break;
2684 case 'c': /* Var size Coprocesssor branches */
2685 if (subs (opP->con1))
2686 {
2687 add_fix ('l', opP->con1, 1);
2688 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2689 }
2690 else if (adds (opP->con1))
2691 {
2692 add_frag (adds (opP->con1), offs (opP->con1), TAB (FBRANCH, SZ_UNDEF));
2693 }
2694 else
2695 {
2696 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2697 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2698 add_fix ('l', opP->con1, 1);
2699 addword (0);
2700 addword (4);
2701 }
2702 break;
2703 default:
2704 as_fatal ("Internal error: operand type B%c unknown in line %d of file \"%s\"",
2705 s[1], __LINE__, __FILE__);
2706 }
2707 break;
2708
2709 case 'C': /* Ignore it */
2710 break;
2711
2712 case 'd': /* JF this is a kludge */
2713 if (opP->mode == AOFF)
2714 {
2715 install_operand ('s', opP->reg - ADDR);
2716 }
2717 else
2718 {
2719 char *tmpP;
2720
2721 tmpP = opP->con1->e_end - 2;
2722 opP->con1->e_beg++;
2723 opP->con1->e_end -= 4; /* point to the , */
2724 baseo = m68k_reg_parse (&tmpP);
2725 if (baseo < ADDR + 0 || baseo > ADDR + 7)
2726 {
2727 as_bad ("Unknown address reg, using A0");
2728 baseo = 0;
2729 }
2730 else
2731 baseo -= ADDR;
2732 install_operand ('s', baseo);
2733 }
2734 tmpreg = get_num (opP->con1, 80);
2735 if (!issword (tmpreg))
2736 {
2737 as_warn ("Expression out of range, using 0");
2738 tmpreg = 0;
2739 }
2740 addword (tmpreg);
2741 break;
2742
2743 case 'D':
2744 install_operand (s[1], opP->reg - DATA);
2745 break;
2746
2747 case 'F':
2748 install_operand (s[1], opP->reg - FPREG);
2749 break;
2750
2751 case 'I':
2752 tmpreg = 1 + opP->reg - COPNUM;
2753 if (tmpreg == 8)
2754 tmpreg = 0;
2755 install_operand (s[1], tmpreg);
2756 break;
2757
2758 case 'J': /* JF foo */
2759 switch (opP->reg)
2760 {
2761 case SFC:
2762 tmpreg = 0x000;
2763 break;
2764 case DFC:
2765 tmpreg = 0x001;
2766 break;
2767 case CACR:
2768 tmpreg = 0x002;
2769 break;
2770 case TC:
2771 tmpreg = 0x003;
2772 break;
2773 case ITT0:
2774 tmpreg = 0x004;
2775 break;
2776 case ITT1:
2777 tmpreg = 0x005;
2778 break;
2779 case DTT0:
2780 tmpreg = 0x006;
2781 break;
2782 case DTT1:
2783 tmpreg = 0x007;
2784 break;
2785
2786 case USP:
2787 tmpreg = 0x800;
2788 break;
2789 case VBR:
2790 tmpreg = 0x801;
2791 break;
2792 case CAAR:
2793 tmpreg = 0x802;
2794 break;
2795 case MSP:
2796 tmpreg = 0x803;
2797 break;
2798 case ISP:
2799 tmpreg = 0x804;
2800 break;
2801 case MMUSR:
2802 tmpreg = 0x805;
2803 break;
2804 case URP:
2805 tmpreg = 0x806;
2806 break;
2807 case SRP:
2808 tmpreg = 0x807;
2809 break;
2810 default:
2811 as_fatal ("failed sanity check.");
2812 }
2813 install_operand (s[1], tmpreg);
2814 break;
2815
2816 case 'k':
2817 tmpreg = get_num (opP->con1, 55);
2818 install_operand (s[1], tmpreg & 0x7f);
2819 break;
2820
2821 case 'l':
2822 tmpreg = opP->reg;
2823 if (s[1] == 'w')
2824 {
2825 if (tmpreg & 0x7FF0000)
2826 as_bad ("Floating point register in register list");
2827 insop (reverse_16_bits (tmpreg), opcode);
2828 }
2829 else
2830 {
2831 if (tmpreg & 0x700FFFF)
2832 as_bad ("Wrong register in floating-point reglist");
2833 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2834 }
2835 break;
2836
2837 case 'L':
2838 tmpreg = opP->reg;
2839 if (s[1] == 'w')
2840 {
2841 if (tmpreg & 0x7FF0000)
2842 as_bad ("Floating point register in register list");
2843 insop (tmpreg, opcode);
2844 }
2845 else if (s[1] == '8')
2846 {
2847 if (tmpreg & 0x0FFFFFF)
2848 as_bad ("incorrect register in reglist");
2849 install_operand (s[1], tmpreg >> 24);
2850 }
2851 else
2852 {
2853 if (tmpreg & 0x700FFFF)
2854 as_bad ("wrong register in floating-point reglist");
2855 else
2856 install_operand (s[1], tmpreg >> 16);
2857 }
2858 break;
2859
2860 case 'M':
2861 install_operand (s[1], get_num (opP->con1, 60));
2862 break;
2863
2864 case 'O':
2865 tmpreg = (opP->mode == DREG)
2866 ? 0x20 + opP->reg - DATA
2867 : (get_num (opP->con1, 40) & 0x1F);
2868 install_operand (s[1], tmpreg);
2869 break;
2870
2871 case 'Q':
2872 tmpreg = get_num (opP->con1, 10);
2873 if (tmpreg == 8)
2874 tmpreg = 0;
2875 install_operand (s[1], tmpreg);
2876 break;
2877
2878 case 'R':
2879 case 'r':
2880 /* This depends on the fact that ADDR registers are
2881 eight more than their corresponding DATA regs, so
2882 the result will have the ADDR_REG bit set */
2883 install_operand (s[1], opP->reg - DATA);
2884 break;
2885
2886 case 's':
2887 if (opP->reg == FPI)
2888 tmpreg = 0x1;
2889 else if (opP->reg == FPS)
2890 tmpreg = 0x2;
2891 else if (opP->reg == FPC)
2892 tmpreg = 0x4;
2893 else
2894 as_fatal ("failed sanity check.");
2895 install_operand (s[1], tmpreg);
2896 break;
2897
2898 case 'S': /* Ignore it */
2899 break;
2900
2901 case 'T':
2902 install_operand (s[1], get_num (opP->con1, 30));
2903 break;
2904
2905 case 'U': /* Ignore it */
2906 break;
2907
2908 case 'c':
2909 switch (opP->reg)
2910 {
2911 case NC:
2912 tmpreg = 0;
2913 break;
2914 case DC:
2915 tmpreg = 1;
2916 break;
2917 case IC:
2918 tmpreg = 2;
2919 break;
2920 case BC:
2921 tmpreg = 3;
2922 break;
2923 default:
2924 as_fatal ("failed sanity check");
2925 } /* switch on cache token */
2926 install_operand (s[1], tmpreg);
2927 break;
2928 #ifndef NO_68851
2929 /* JF: These are out of order, I fear. */
2930 case 'f':
2931 switch (opP->reg)
2932 {
2933 case SFC:
2934 tmpreg = 0;
2935 break;
2936 case DFC:
2937 tmpreg = 1;
2938 break;
2939 default:
2940 as_fatal ("failed sanity check.");
2941 }
2942 install_operand (s[1], tmpreg);
2943 break;
2944
2945 case 'P':
2946 switch (opP->reg)
2947 {
2948 case TC:
2949 tmpreg = 0;
2950 break;
2951 case CAL:
2952 tmpreg = 4;
2953 break;
2954 case VAL:
2955 tmpreg = 5;
2956 break;
2957 case SCC:
2958 tmpreg = 6;
2959 break;
2960 case AC:
2961 tmpreg = 7;
2962 break;
2963 default:
2964 as_fatal ("failed sanity check.");
2965 }
2966 install_operand (s[1], tmpreg);
2967 break;
2968
2969 case 'V':
2970 if (opP->reg == VAL)
2971 break;
2972 as_fatal ("failed sanity check.");
2973
2974 case 'W':
2975 switch (opP->reg)
2976 {
2977
2978 case DRP:
2979 tmpreg = 1;
2980 break;
2981 case SRP:
2982 tmpreg = 2;
2983 break;
2984 case CRP:
2985 tmpreg = 3;
2986 break;
2987 default:
2988 as_fatal ("failed sanity check.");
2989 }
2990 install_operand (s[1], tmpreg);
2991 break;
2992
2993 case 'X':
2994 switch (opP->reg)
2995 {
2996 case BAD:
2997 case BAD + 1:
2998 case BAD + 2:
2999 case BAD + 3:
3000 case BAD + 4:
3001 case BAD + 5:
3002 case BAD + 6:
3003 case BAD + 7:
3004 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3005 break;
3006
3007 case BAC:
3008 case BAC + 1:
3009 case BAC + 2:
3010 case BAC + 3:
3011 case BAC + 4:
3012 case BAC + 5:
3013 case BAC + 6:
3014 case BAC + 7:
3015 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3016 break;
3017
3018 default:
3019 as_fatal ("failed sanity check.");
3020 }
3021 install_operand (s[1], tmpreg);
3022 break;
3023 case 'Y':
3024 know (opP->reg == PSR);
3025 break;
3026 case 'Z':
3027 know (opP->reg == PCSR);
3028 break;
3029 #endif /* m68851 */
3030 case '3':
3031 switch (opP->reg)
3032 {
3033 case TT0:
3034 tmpreg = 2;
3035 break;
3036 case TT1:
3037 tmpreg = 3;
3038 break;
3039 default:
3040 as_fatal ("failed sanity check");
3041 }
3042 install_operand (s[1], tmpreg);
3043 break;
3044 case 't':
3045 tmpreg = get_num (opP->con1, 20);
3046 install_operand (s[1], tmpreg);
3047 break;
3048 case '_': /* used only for move16 absolute 32-bit address */
3049 tmpreg = get_num (opP->con1, 80);
3050 addword (tmpreg >> 16);
3051 addword (tmpreg & 0xFFFF);
3052 break;
3053 default:
3054 as_fatal ("Internal error: Operand type %c unknown in line %d of file \"%s\"",
3055 s[0], __LINE__, __FILE__);
3056 }
3057 }
3058
3059 /* By the time whe get here (FINALLY) the_ins contains the complete
3060 instruction, ready to be emitted. . . */
3061 } /* m68k_ip() */
3062
3063 /*
3064 * get_regs := '/' + ?
3065 * | '-' + <register>
3066 * | '-' + <register> + ?
3067 * | <empty>
3068 * ;
3069 *
3070
3071 * The idea here must be to scan in a set of registers but I don't
3072 * understand it. Looks awfully sloppy to me but I don't have any doc on
3073 * this format so...
3074
3075 *
3076 *
3077 */
3078
3079 static int
3080 get_regs (i, str, opP)
3081 int i;
3082 struct m68k_op *opP;
3083 char *str;
3084 {
3085 /* 26, 25, 24, 23-16, 15-8, 0-7 */
3086 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
3087 unsigned long cur_regs = 0;
3088 int reg1, reg2;
3089
3090 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
3091 else if(x==FPS) cur_regs|=(1<<25);\
3092 else if(x==FPC) cur_regs|=(1<<26);\
3093 else cur_regs|=(1<<(x-1)); }
3094
3095 reg1 = i;
3096 for (;;)
3097 {
3098 if (*str == '/')
3099 {
3100 ADD_REG (reg1);
3101 str++;
3102 }
3103 else if (*str == '-')
3104 {
3105 str++;
3106 reg2 = m68k_reg_parse (&str);
3107 if (reg2 < DATA || reg2 >= FPREG + 8 || reg1 == FPI || reg1 == FPS || reg1 == FPC)
3108 {
3109 opP->error = "unknown register in register list";
3110 return FAIL;
3111 }
3112 while (reg1 <= reg2)
3113 {
3114 ADD_REG (reg1);
3115 reg1++;
3116 }
3117 if (*str == '\0')
3118 break;
3119 }
3120 else if (*str == '\0')
3121 {
3122 ADD_REG (reg1);
3123 break;
3124 }
3125 else
3126 {
3127 opP->error = "unknow character in register list";
3128 return FAIL;
3129 }
3130 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
3131 if (*str == '/')
3132 str++;
3133 reg1 = m68k_reg_parse (&str);
3134 if ((reg1 < DATA || reg1 >= FPREG + 8) && !(reg1 == FPI || reg1 == FPS || reg1 == FPC))
3135 {
3136 opP->error = "unknown register in register list";
3137 return FAIL;
3138 }
3139 }
3140 opP->reg = cur_regs;
3141 return OK;
3142 } /* get_regs() */
3143
3144 static int
3145 reverse_16_bits (in)
3146 int in;
3147 {
3148 int out = 0;
3149 int n;
3150
3151 static int mask[16] =
3152 {
3153 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3154 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3155 };
3156 for (n = 0; n < 16; n++)
3157 {
3158 if (in & mask[n])
3159 out |= mask[15 - n];
3160 }
3161 return out;
3162 } /* reverse_16_bits() */
3163
3164 static int
3165 reverse_8_bits (in)
3166 int in;
3167 {
3168 int out = 0;
3169 int n;
3170
3171 static int mask[8] =
3172 {
3173 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3174 };
3175
3176 for (n = 0; n < 8; n++)
3177 {
3178 if (in & mask[n])
3179 out |= mask[7 - n];
3180 }
3181 return out;
3182 } /* reverse_8_bits() */
3183
3184 static void
3185 install_operand (mode, val)
3186 int mode;
3187 int val;
3188 {
3189 switch (mode)
3190 {
3191 case 's':
3192 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3193 break;
3194 case 'd':
3195 the_ins.opcode[0] |= val << 9;
3196 break;
3197 case '1':
3198 the_ins.opcode[1] |= val << 12;
3199 break;
3200 case '2':
3201 the_ins.opcode[1] |= val << 6;
3202 break;
3203 case '3':
3204 the_ins.opcode[1] |= val;
3205 break;
3206 case '4':
3207 the_ins.opcode[2] |= val << 12;
3208 break;
3209 case '5':
3210 the_ins.opcode[2] |= val << 6;
3211 break;
3212 case '6':
3213 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3214 three words long! */
3215 the_ins.numo++;
3216 the_ins.opcode[2] |= val;
3217 break;
3218 case '7':
3219 the_ins.opcode[1] |= val << 7;
3220 break;
3221 case '8':
3222 the_ins.opcode[1] |= val << 10;
3223 break;
3224 #ifndef NO_68851
3225 case '9':
3226 the_ins.opcode[1] |= val << 5;
3227 break;
3228 #endif
3229
3230 case 't':
3231 the_ins.opcode[1] |= (val << 10) | (val << 7);
3232 break;
3233 case 'D':
3234 the_ins.opcode[1] |= (val << 12) | val;
3235 break;
3236 case 'g':
3237 the_ins.opcode[0] |= val = 0xff;
3238 break;
3239 case 'i':
3240 the_ins.opcode[0] |= val << 9;
3241 break;
3242 case 'C':
3243 the_ins.opcode[1] |= val;
3244 break;
3245 case 'j':
3246 the_ins.opcode[1] |= val;
3247 the_ins.numo++; /* What a hack */
3248 break;
3249 case 'k':
3250 the_ins.opcode[1] |= val << 4;
3251 break;
3252 case 'b':
3253 case 'w':
3254 case 'l':
3255 break;
3256 case 'e':
3257 the_ins.opcode[0] |= (val << 6);
3258 break;
3259 case 'L':
3260 the_ins.opcode[1] = (val >> 16);
3261 the_ins.opcode[2] = val & 0xffff;
3262 break;
3263 case 'c':
3264 default:
3265 as_fatal ("failed sanity check.");
3266 }
3267 } /* install_operand() */
3268
3269 static void
3270 install_gen_operand (mode, val)
3271 int mode;
3272 int val;
3273 {
3274 switch (mode)
3275 {
3276 case 's':
3277 the_ins.opcode[0] |= val;
3278 break;
3279 case 'd':
3280 /* This is a kludge!!! */
3281 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3282 break;
3283 case 'b':
3284 case 'w':
3285 case 'l':
3286 case 'f':
3287 case 'F':
3288 case 'x':
3289 case 'p':
3290 the_ins.opcode[0] |= val;
3291 break;
3292 /* more stuff goes here */
3293 default:
3294 as_fatal ("failed sanity check.");
3295 }
3296 } /* install_gen_operand() */
3297
3298 /*
3299 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3300 * then deal with the bitfield hack.
3301 */
3302
3303 static char *
3304 crack_operand (str, opP)
3305 register char *str;
3306 register struct m68k_op *opP;
3307 {
3308 register int parens;
3309 register int c;
3310 register char *beg_str;
3311
3312 if (!str)
3313 {
3314 return str;
3315 }
3316 beg_str = str;
3317 for (parens = 0; *str && (parens > 0 || notend (str)); str++)
3318 {
3319 if (*str == '(')
3320 parens++;
3321 else if (*str == ')')
3322 {
3323 if (!parens)
3324 { /* ERROR */
3325 opP->error = "Extra )";
3326 return str;
3327 }
3328 --parens;
3329 }
3330 }
3331 if (!*str && parens)
3332 { /* ERROR */
3333 opP->error = "Missing )";
3334 return str;
3335 }
3336 c = *str;
3337 *str = '\0';
3338 if (m68k_ip_op (beg_str, opP) == FAIL)
3339 {
3340 *str = c;
3341 return str;
3342 }
3343 *str = c;
3344 if (c == '}')
3345 c = *++str; /* JF bitfield hack */
3346 if (c)
3347 {
3348 c = *++str;
3349 if (!c)
3350 as_bad ("Missing operand");
3351 }
3352 return str;
3353 }
3354
3355 /* See the comment up above where the #define notend(... is */
3356 #if 0
3357 notend (s)
3358 char *s;
3359 {
3360 if (*s == ',')
3361 return 0;
3362 if (*s == '{' || *s == '}')
3363 return 0;
3364 if (*s != ':')
3365 return 1;
3366 /* This kludge here is for the division cmd, which is a kludge */
3367 if (index ("aAdD#", s[1]))
3368 return 0;
3369 return 1;
3370 }
3371
3372 #endif
3373
3374 /* This is the guts of the machine-dependent assembler. STR points to a
3375 machine dependent instruction. This function is supposed to emit
3376 the frags/bytes it assembles to.
3377 */
3378
3379 void
3380 insert_reg (regname, regnum)
3381 char *regname;
3382 int regnum;
3383 {
3384 char buf[100];
3385 int i;
3386 symbolS *s;
3387
3388 #ifdef REGISTER_PREFIX
3389 buf[0] = REGISTER_PREFIX;
3390 strcpy (buf + 1, regname);
3391 regname = buf;
3392 #endif
3393
3394 symbol_table_insert (s = symbol_new (regname, reg_section, regnum, &zero_address_frag));
3395
3396 verify_symbol_chain_2 (s);
3397
3398 for (i = 0; regname[i]; i++)
3399 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3400 buf[i] = '\0';
3401
3402 symbol_table_insert (s = symbol_new (buf, reg_section, regnum, &zero_address_frag));
3403 verify_symbol_chain_2 (s);
3404 }
3405
3406 struct init_entry
3407 {
3408 const char *name;
3409 int number;
3410 };
3411
3412 static const struct init_entry init_table[] =
3413 {
3414 { "d0", DATA0 },
3415 { "d1", DATA1 },
3416 { "d2", DATA2 },
3417 { "d3", DATA3 },
3418 { "d4", DATA4 },
3419 { "d5", DATA5 },
3420 { "d6", DATA6 },
3421 { "d7", DATA7 },
3422 { "a0", ADDR0 },
3423 { "a1", ADDR1 },
3424 { "a2", ADDR2 },
3425 { "a3", ADDR3 },
3426 { "a4", ADDR4 },
3427 { "a5", ADDR5 },
3428 { "a6", ADDR6 },
3429 { "fp", ADDR6 },
3430 { "a7", ADDR7 },
3431 { "sp", ADDR7 },
3432 { "fp0", FP0 },
3433 { "fp1", FP1 },
3434 { "fp2", FP2 },
3435 { "fp3", FP3 },
3436 { "fp4", FP4 },
3437 { "fp5", FP5 },
3438 { "fp6", FP6 },
3439 { "fp7", FP7 },
3440 { "fpi", FPI },
3441 { "fpiar", FPI },
3442 { "fpc", FPI },
3443 { "fps", FPS },
3444 { "fpsr", FPS },
3445 { "fpc", FPC },
3446 { "fpcr", FPC },
3447
3448 { "cop0", COP0 },
3449 { "cop1", COP1 },
3450 { "cop2", COP2 },
3451 { "cop3", COP3 },
3452 { "cop4", COP4 },
3453 { "cop5", COP5 },
3454 { "cop6", COP6 },
3455 { "cop7", COP7 },
3456 { "pc", PC },
3457 { "zpc", ZPC },
3458 { "sr", SR },
3459
3460 { "ccr", CCR },
3461 { "cc", CCR },
3462
3463 { "usp", USP },
3464 { "isp", ISP },
3465 { "sfc", SFC },
3466 { "dfc", DFC },
3467 { "cacr", CACR },
3468 { "caar", CAAR },
3469
3470 { "vbr", VBR },
3471
3472 { "msp", MSP },
3473 { "itt0", ITT0 },
3474 { "itt1", ITT1 },
3475 { "dtt0", DTT0 },
3476 { "dtt1", DTT1 },
3477 { "mmusr", MMUSR },
3478 { "tc", TC },
3479 { "srp", SRP },
3480 { "urp", URP },
3481
3482 { "ac", AC },
3483 { "bc", BC },
3484 { "cal", CAL },
3485 { "crp", CRP },
3486 { "drp", DRP },
3487 { "pcsr", PCSR },
3488 { "psr", PSR },
3489 { "scc", SCC },
3490 { "val", VAL },
3491 { "bad0", BAD0 },
3492 { "bad1", BAD1 },
3493 { "bad2", BAD2 },
3494 { "bad3", BAD3 },
3495 { "bad4", BAD4 },
3496 { "bad5", BAD5 },
3497 { "bad6", BAD6 },
3498 { "bad7", BAD7 },
3499 { "bac0", BAC0 },
3500 { "bac1", BAC1 },
3501 { "bac2", BAC2 },
3502 { "bac3", BAC3 },
3503 { "bac4", BAC4 },
3504 { "bac5", BAC5 },
3505 { "bac6", BAC6 },
3506 { "bac7", BAC7 },
3507
3508 { "ic", IC },
3509 { "dc", DC },
3510 { "nc", NC },
3511
3512 { "tt0", TT0 },
3513 { "tt1", TT1 },
3514 /* 68ec030 versions of same */
3515 { "ac0", TT0 },
3516 { "ac1", TT1 },
3517 /* 68ec030 access control unit, identical to 030 MMU status reg */
3518 { "acusr", PSR },
3519
3520 { 0, 0 }
3521 };
3522
3523 void
3524 init_regtable ()
3525 {
3526 int i;
3527 for (i = 0; init_table[i].name; i++)
3528 insert_reg (init_table[i].name, init_table[i].number);
3529 }
3530
3531 static int no_68851, no_68881;
3532
3533 void
3534 md_assemble (str)
3535 char *str;
3536 {
3537 char *er;
3538 short *fromP;
3539 char *toP = NULL;
3540 int m, n = 0;
3541 char *to_beg_P;
3542 int shorts_this_frag;
3543 static int done_first_time;
3544
3545 if (!done_first_time)
3546 {
3547 done_first_time = 1;
3548
3549 if (cpu_of_arch (current_architecture) == 0)
3550 {
3551 int cpu_type;
3552
3553 if (strcmp (TARGET_CPU, "m68000") == 0
3554 || strcmp (TARGET_CPU, "m68302") == 0)
3555 cpu_type = m68000;
3556 else if (strcmp (TARGET_CPU, "m68010") == 0)
3557 cpu_type = m68010;
3558 else if (strcmp (TARGET_CPU, "m68020") == 0
3559 || strcmp (TARGET_CPU, "m68k") == 0)
3560 cpu_type = m68020;
3561 else if (strcmp (TARGET_CPU, "m68030") == 0)
3562 cpu_type = m68030;
3563 else if (strcmp (TARGET_CPU, "m68040") == 0)
3564 cpu_type = m68040;
3565 else if (strcmp (TARGET_CPU, "cpu32") == 0
3566 || strcmp (TARGET_CPU, "m68331") == 0
3567 || strcmp (TARGET_CPU, "m68332") == 0
3568 || strcmp (TARGET_CPU, "m68333") == 0
3569 || strcmp (TARGET_CPU, "m68340") == 0)
3570 cpu_type = cpu32;
3571 else
3572 cpu_type = m68020;
3573
3574 current_architecture |= cpu_type;
3575 }
3576 #if 0 /* Could be doing emulation. */
3577 if (current_architecture & m68881)
3578 {
3579 if (current_architecture & m68000)
3580 as_bad ("incompatible processors 68000 and 68881/2 specified");
3581 if (current_architecture & m68010)
3582 as_bad ("incompatible processors 68010 and 68881/2 specified");
3583 if (current_architecture & m68040)
3584 as_bad ("incompatible processors 68040 and 68881/2 specified");
3585 }
3586 #endif
3587 /* What other incompatibilities could we check for? */
3588
3589 /* Toss in some default assumptions about coprocessors. */
3590 if (!no_68881
3591 && (cpu_of_arch (current_architecture)
3592 /* Can CPU32 have a 68881 coprocessor?? */
3593 & (m68020 | m68030 | cpu32)))
3594 {
3595 current_architecture |= m68881;
3596 }
3597 if (!no_68851
3598 && (cpu_of_arch (current_architecture) & m68020up) != 0
3599 && cpu_of_arch (current_architecture) != m68040)
3600 {
3601 current_architecture |= m68851;
3602 }
3603 if (no_68881 && (current_architecture & m68881))
3604 as_bad ("options for 68881 and no-68881 both given");
3605 if (no_68851 && (current_architecture & m68851))
3606 as_bad ("options for 68851 and no-68851 both given");
3607 done_first_time = 1;
3608 }
3609
3610 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3611 m68k_ip (str);
3612 er = the_ins.error;
3613 if (!er)
3614 {
3615 for (n = the_ins.numargs; n; --n)
3616 if (the_ins.operands[n].error)
3617 {
3618 er = the_ins.operands[n].error;
3619 break;
3620 }
3621 }
3622 if (er)
3623 {
3624 as_bad ("%s -- statement `%s' ignored", er, str);
3625 return;
3626 }
3627
3628 if (the_ins.nfrag == 0)
3629 {
3630 /* No frag hacking involved; just put it out */
3631 toP = frag_more (2 * the_ins.numo);
3632 fromP = &the_ins.opcode[0];
3633 for (m = the_ins.numo; m; --m)
3634 {
3635 md_number_to_chars (toP, (long) (*fromP), 2);
3636 toP += 2;
3637 fromP++;
3638 }
3639 /* put out symbol-dependent info */
3640 for (m = 0; m < the_ins.nrel; m++)
3641 {
3642 switch (the_ins.reloc[m].wid)
3643 {
3644 case 'B':
3645 n = 1;
3646 break;
3647 case 'b':
3648 n = 1;
3649 break;
3650 case '3':
3651 n = 2;
3652 break;
3653 case 'w':
3654 n = 2;
3655 break;
3656 case 'l':
3657 n = 4;
3658 break;
3659 default:
3660 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3661 the_ins.reloc[m].wid);
3662 }
3663
3664 fix_new_exp (frag_now,
3665 ((toP - frag_now->fr_literal)
3666 - the_ins.numo * 2 + the_ins.reloc[m].n),
3667 n,
3668 &the_ins.reloc[m].exp,
3669 the_ins.reloc[m].pcrel,
3670 NO_RELOC);
3671 }
3672 return;
3673 }
3674
3675 /* There's some frag hacking */
3676 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3677 {
3678 int wid;
3679
3680 if (n == 0)
3681 wid = 2 * the_ins.fragb[n].fragoff;
3682 else
3683 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3684 toP = frag_more (wid);
3685 to_beg_P = toP;
3686 shorts_this_frag = 0;
3687 for (m = wid / 2; m; --m)
3688 {
3689 md_number_to_chars (toP, (long) (*fromP), 2);
3690 toP += 2;
3691 fromP++;
3692 shorts_this_frag++;
3693 }
3694 for (m = 0; m < the_ins.nrel; m++)
3695 {
3696 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3697 {
3698 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3699 break;
3700 }
3701 wid = the_ins.reloc[m].wid;
3702 if (wid == 0)
3703 continue;
3704 the_ins.reloc[m].wid = 0;
3705 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3706
3707 fix_new_exp (frag_now,
3708 ((toP - frag_now->fr_literal)
3709 - the_ins.numo * 2 + the_ins.reloc[m].n),
3710 wid,
3711 &the_ins.reloc[m].exp,
3712 the_ins.reloc[m].pcrel,
3713 NO_RELOC);
3714 }
3715 (void) frag_var (rs_machine_dependent, 10, 0,
3716 (relax_substateT) (the_ins.fragb[n].fragty),
3717 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3718 }
3719 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3720 shorts_this_frag = 0;
3721 if (n)
3722 {
3723 toP = frag_more (n * sizeof (short));
3724 while (n--)
3725 {
3726 md_number_to_chars (toP, (long) (*fromP), 2);
3727 toP += 2;
3728 fromP++;
3729 shorts_this_frag++;
3730 }
3731 }
3732 for (m = 0; m < the_ins.nrel; m++)
3733 {
3734 int wid;
3735
3736 wid = the_ins.reloc[m].wid;
3737 if (wid == 0)
3738 continue;
3739 the_ins.reloc[m].wid = 0;
3740 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3741
3742 fix_new_exp (frag_now,
3743 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3744 - shorts_this_frag * 2),
3745 wid,
3746 &the_ins.reloc[m].exp,
3747 the_ins.reloc[m].pcrel,
3748 NO_RELOC);
3749 }
3750 }
3751
3752 /* See BREAK_UP_BIG_DECL definition, above. */
3753 static struct m68k_opcode *
3754 opcode_ptr (i)
3755 int i;
3756 {
3757 #ifdef DO_BREAK_UP_BIG_DECL
3758 int lim1 = sizeof (m68k_opcodes) / sizeof (m68k_opcodes[0]);
3759 if (i >= lim1)
3760 return m68k_opcodes_2 + (i - lim1);
3761 #endif
3762 return m68k_opcodes + i;
3763 }
3764
3765 void
3766 md_begin ()
3767 {
3768 /*
3769 * md_begin -- set up hash tables with 68000 instructions.
3770 * similar to what the vax assembler does. ---phr
3771 */
3772 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3773 a copy of it at runtime, adding in the information we want but isn't
3774 there. I think it'd be better to have an awk script hack the table
3775 at compile time. Or even just xstr the table and use it as-is. But
3776 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3777 names. */
3778
3779 register CONST struct m68k_opcode *ins;
3780 register struct m68k_incant *hack, *slak;
3781 register const char *retval = 0; /* empty string, or error msg text */
3782 register unsigned int i;
3783 register char c;
3784
3785 if ((op_hash = hash_new ()) == NULL)
3786 as_fatal ("Virtual memory exhausted");
3787
3788 obstack_begin (&robyn, 4000);
3789 for (i = 0; i < numopcodes; i++)
3790 {
3791 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3792 do
3793 {
3794 ins = opcode_ptr (i);
3795 /* We *could* ignore insns that don't match our arch here
3796 but just leaving them out of the hash. */
3797 slak->m_operands = ins->args;
3798 slak->m_opnum = strlen (slak->m_operands) / 2;
3799 slak->m_arch = ins->arch;
3800 slak->m_opcode = ins->opcode;
3801 /* This is kludgey */
3802 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3803 if (i + 1 != numopcodes
3804 && !strcmp (ins->name, opcode_ptr (i + 1)->name))
3805 {
3806 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3807 i++;
3808 }
3809 else
3810 slak->m_next = 0;
3811 slak = slak->m_next;
3812 }
3813 while (slak);
3814
3815 retval = hash_insert (op_hash, ins->name, (char *) hack);
3816 /* Didn't his mommy tell him about null pointers? */
3817 if (retval && *retval)
3818 as_bad ("Internal Error: Can't hash %s: %s", ins->name, retval);
3819 }
3820
3821 for (i = 0; i < sizeof (mklower_table); i++)
3822 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3823
3824 for (i = 0; i < sizeof (notend_table); i++)
3825 {
3826 notend_table[i] = 0;
3827 alt_notend_table[i] = 0;
3828 }
3829 notend_table[','] = 1;
3830 notend_table['{'] = 1;
3831 notend_table['}'] = 1;
3832 alt_notend_table['a'] = 1;
3833 alt_notend_table['A'] = 1;
3834 alt_notend_table['d'] = 1;
3835 alt_notend_table['D'] = 1;
3836 alt_notend_table['#'] = 1;
3837 alt_notend_table['f'] = 1;
3838 alt_notend_table['F'] = 1;
3839 #ifdef REGISTER_PREFIX
3840 alt_notend_table[REGISTER_PREFIX] = 1;
3841 #endif
3842 #ifdef OPTIONAL_REGISTER_PREFIX
3843 alt_notend_table[OPTIONAL_REGISTER_PREFIX] = 1;
3844 #endif
3845
3846 #ifndef MIT_SYNTAX_ONLY
3847 /* Insert pseudo ops, these have to go into the opcode table since
3848 gas expects pseudo ops to start with a dot */
3849 {
3850 int n = 0;
3851 while (mote_pseudo_table[n].poc_name)
3852 {
3853 hack = (struct m68k_incant *)
3854 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3855 hash_insert (op_hash,
3856 mote_pseudo_table[n].poc_name, (char *) hack);
3857 hack->m_operands = 0;
3858 hack->m_opnum = n;
3859 n++;
3860 }
3861 }
3862 #endif
3863
3864 init_regtable ();
3865 }
3866
3867 #if 0
3868 #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
3869 || (*s == ':' && strchr("aAdD#", s[1]))) \
3870 ? 0 : 1)
3871 #endif
3872
3873 /* This funciton is called once, before the assembler exits. It is
3874 supposed to do any final cleanup for this part of the assembler.
3875 */
3876 void
3877 md_end ()
3878 {
3879 }
3880
3881 /* Equal to MAX_PRECISION in atof-ieee.c */
3882 #define MAX_LITTLENUMS 6
3883
3884 /* Turn a string in input_line_pointer into a floating point constant of type
3885 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3886 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
3887 */
3888 char *
3889 md_atof (type, litP, sizeP)
3890 char type;
3891 char *litP;
3892 int *sizeP;
3893 {
3894 int prec;
3895 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3896 LITTLENUM_TYPE *wordP;
3897 char *t;
3898 char *atof_ieee ();
3899
3900 switch (type)
3901 {
3902 case 'f':
3903 case 'F':
3904 case 's':
3905 case 'S':
3906 prec = 2;
3907 break;
3908
3909 case 'd':
3910 case 'D':
3911 case 'r':
3912 case 'R':
3913 prec = 4;
3914 break;
3915
3916 case 'x':
3917 case 'X':
3918 prec = 6;
3919 break;
3920
3921 case 'p':
3922 case 'P':
3923 prec = 6;
3924 break;
3925
3926 default:
3927 *sizeP = 0;
3928 return "Bad call to MD_ATOF()";
3929 }
3930 t = atof_ieee (input_line_pointer, type, words);
3931 if (t)
3932 input_line_pointer = t;
3933
3934 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3935 for (wordP = words; prec--;)
3936 {
3937 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3938 litP += sizeof (LITTLENUM_TYPE);
3939 }
3940 return 0;
3941 }
3942
3943 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3944 for use in the a.out file, and stores them in the array pointed to by buf.
3945 This knows about the endian-ness of the target machine and does
3946 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3947 2 (short) and 4 (long) Floating numbers are put out as a series of
3948 LITTLENUMS (shorts, here at least)
3949 */
3950 void
3951 md_number_to_chars (buf, val, n)
3952 char *buf;
3953 valueT val;
3954 int n;
3955 {
3956 switch (n)
3957 {
3958 case 1:
3959 *buf++ = val;
3960 break;
3961 case 2:
3962 *buf++ = (val >> 8);
3963 *buf++ = val;
3964 break;
3965 case 4:
3966 *buf++ = (val >> 24);
3967 *buf++ = (val >> 16);
3968 *buf++ = (val >> 8);
3969 *buf++ = val;
3970 break;
3971 default:
3972 as_fatal ("failed sanity check.");
3973 }
3974 }
3975
3976 static void
3977 md_apply_fix_2 (fixP, val)
3978 fixS *fixP;
3979 long val;
3980 {
3981 unsigned long upper_limit;
3982 long lower_limit;
3983
3984 #ifdef IBM_COMPILER_SUX
3985 /* This is unnecessary but it convinces the native rs6000
3986 compiler to generate the code we want. */
3987 char *buf = fixP->fx_frag->fr_literal;
3988 buf += fixP->fx_where;
3989 #else /* IBM_COMPILER_SUX */
3990 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3991 #endif /* IBM_COMPILER_SUX */
3992
3993 switch (fixP->fx_size)
3994 {
3995 case 1:
3996 *buf++ = val;
3997 upper_limit = 0x7f;
3998 lower_limit = -0x80;
3999 break;
4000 case 2:
4001 *buf++ = (val >> 8);
4002 *buf++ = val;
4003 upper_limit = 0x7fff;
4004 lower_limit = -0x8000;
4005 break;
4006 case 4:
4007 *buf++ = (val >> 24);
4008 *buf++ = (val >> 16);
4009 *buf++ = (val >> 8);
4010 *buf++ = val;
4011 upper_limit = 0x7fffffff;
4012 lower_limit = -0x80000000;
4013 break;
4014 default:
4015 BAD_CASE (fixP->fx_size);
4016 }
4017
4018 /* For non-pc-relative values, it's conceivable we might get something
4019 like "0xff" for a byte field. So extend the upper part of the range
4020 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4021 so that we can do any range checking at all. */
4022 if (!fixP->fx_pcrel)
4023 upper_limit = upper_limit * 2 + 1;
4024
4025 if ((unsigned) val > upper_limit && (val > 0 || val < lower_limit))
4026 as_bad ("value out of range");
4027 }
4028
4029 #ifdef BFD_ASSEMBLER
4030 int
4031 md_apply_fix (fixP, valp)
4032 fixS *fixP;
4033 long *valp;
4034 {
4035 md_apply_fix_2 (fixP, *valp);
4036 return 1;
4037 }
4038 #else
4039 void md_apply_fix (fixP, val)
4040 fixS *fixP;
4041 long val;
4042 {
4043 md_apply_fix_2 (fixP, val);
4044 }
4045 #endif
4046
4047 /* *fragP has been relaxed to its final size, and now needs to have
4048 the bytes inside it modified to conform to the new size There is UGLY
4049 MAGIC here. ..
4050 */
4051 void
4052 md_convert_frag_1 (fragP)
4053 register fragS *fragP;
4054 {
4055 long disp;
4056 long ext = 0;
4057
4058 /* Address in object code of the displacement. */
4059 register int object_address = fragP->fr_fix + fragP->fr_address;
4060
4061 #ifdef IBM_COMPILER_SUX
4062 /* This is wrong but it convinces the native rs6000 compiler to
4063 generate the code we want. */
4064 register char *buffer_address = fragP->fr_literal;
4065 buffer_address += fragP->fr_fix;
4066 #else /* IBM_COMPILER_SUX */
4067 /* Address in gas core of the place to store the displacement. */
4068 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4069 #endif /* IBM_COMPILER_SUX */
4070
4071 /* No longer true: know(fragP->fr_symbol); */
4072
4073 /* The displacement of the address, from current location. */
4074 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4075 disp = (disp + fragP->fr_offset) - object_address;
4076
4077 switch (fragP->fr_subtype)
4078 {
4079 case TAB (BCC68000, BYTE):
4080 case TAB (ABRANCH, BYTE):
4081 know (issbyte (disp));
4082 if (disp == 0)
4083 as_bad ("short branch with zero offset: use :w");
4084 fragP->fr_opcode[1] = disp;
4085 ext = 0;
4086 break;
4087 case TAB (DBCC, SHORT):
4088 know (issword (disp));
4089 ext = 2;
4090 break;
4091 case TAB (BCC68000, SHORT):
4092 case TAB (ABRANCH, SHORT):
4093 know (issword (disp));
4094 fragP->fr_opcode[1] = 0x00;
4095 ext = 2;
4096 break;
4097 case TAB (ABRANCH, LONG):
4098 if (cpu_of_arch (current_architecture) < m68020)
4099 {
4100 if (fragP->fr_opcode[0] == 0x61)
4101 {
4102 fragP->fr_opcode[0] = 0x4E;
4103 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4104 subseg_change (text_section, 0); /* @@ */
4105
4106 fix_new (fragP,
4107 fragP->fr_fix,
4108 4,
4109 fragP->fr_symbol,
4110 fragP->fr_offset,
4111 0,
4112 NO_RELOC);
4113
4114 fragP->fr_fix += 4;
4115 ext = 0;
4116 }
4117 else if (fragP->fr_opcode[0] == 0x60)
4118 {
4119 fragP->fr_opcode[0] = 0x4E;
4120 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4121 subseg_change (text_section, 0); /* @@ */
4122 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4123 fragP->fr_offset, 0, NO_RELOC);
4124 fragP->fr_fix += 4;
4125 ext = 0;
4126 }
4127 else
4128 {
4129 as_bad ("Long branch offset not supported.");
4130 }
4131 }
4132 else
4133 {
4134 fragP->fr_opcode[1] = (char) 0xff;
4135 ext = 4;
4136 }
4137 break;
4138 case TAB (BCC68000, LONG):
4139 /* only Bcc 68000 instructions can come here */
4140 /* change bcc into b!cc/jmp absl long */
4141 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4142 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4143
4144 /* JF: these used to be fr_opcode[2,3], but they may be in a
4145 different frag, in which case refering to them is a no-no.
4146 Only fr_opcode[0,1] are guaranteed to work. */
4147 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4148 *buffer_address++ = (char) 0xf9;
4149 fragP->fr_fix += 2; /* account for jmp instruction */
4150 subseg_change (text_section, 0);
4151 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4152 fragP->fr_offset, 0, NO_RELOC);
4153 fragP->fr_fix += 4;
4154 ext = 0;
4155 break;
4156 case TAB (DBCC, LONG):
4157 /* only DBcc 68000 instructions can come here */
4158 /* change dbcc into dbcc/jmp absl long */
4159 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4160 *buffer_address++ = 0x00; /* branch offset = 4 */
4161 *buffer_address++ = 0x04;
4162 *buffer_address++ = 0x60; /* put in bra pc+6 */
4163 *buffer_address++ = 0x06;
4164 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4165 *buffer_address++ = (char) 0xf9;
4166
4167 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4168 subseg_change (text_section, 0);
4169 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4170 fragP->fr_offset, 0, NO_RELOC);
4171 fragP->fr_fix += 4;
4172 ext = 0;
4173 break;
4174 case TAB (FBRANCH, SHORT):
4175 know ((fragP->fr_opcode[1] & 0x40) == 0);
4176 ext = 2;
4177 break;
4178 case TAB (FBRANCH, LONG):
4179 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4180 ext = 4;
4181 break;
4182 case TAB (PCREL, SHORT):
4183 ext = 2;
4184 break;
4185 case TAB (PCREL, LONG):
4186 /* The thing to do here is force it to ABSOLUTE LONG, since
4187 PCREL is really trying to shorten an ABSOLUTE address anyway */
4188 /* JF FOO This code has not been tested */
4189 subseg_change (text_section, 0);
4190 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4191 0, NO_RELOC);
4192 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4193 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4194 (unsigned) fragP->fr_opcode[0],
4195 (unsigned long) fragP->fr_address);
4196 fragP->fr_opcode[1] &= ~0x3F;
4197 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4198 fragP->fr_fix += 4;
4199 ext = 0;
4200 break;
4201 case TAB (PCLEA, SHORT):
4202 subseg_change (text_section, 0);
4203 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4204 fragP->fr_offset, 1, NO_RELOC);
4205 fragP->fr_opcode[1] &= ~0x3F;
4206 fragP->fr_opcode[1] |= 0x3A;
4207 ext = 2;
4208 break;
4209 case TAB (PCLEA, LONG):
4210 subseg_change (text_section, 0);
4211 fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4212 fragP->fr_offset + 2, 1, NO_RELOC);
4213 *buffer_address++ = 0x01;
4214 *buffer_address++ = 0x70;
4215 fragP->fr_fix += 2;
4216 ext = 4;
4217 break;
4218 }
4219
4220 if (ext)
4221 {
4222 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4223 fragP->fr_fix += ext;
4224 }
4225 }
4226
4227 #ifndef BFD_ASSEMBLER
4228
4229 void
4230 md_convert_frag (headers, fragP)
4231 object_headers *headers;
4232 fragS *fragP;
4233 {
4234 md_convert_frag_1 (fragP);
4235 }
4236
4237 #else
4238
4239 void
4240 md_convert_frag (abfd, sec, fragP)
4241 bfd *abfd;
4242 asection sec;
4243 fragS *fragP;
4244 {
4245 md_convert_frag_1 (fragP);
4246 }
4247 #endif
4248
4249 /* Force truly undefined symbols to their maximum size, and generally set up
4250 the frag list to be relaxed
4251 */
4252 int
4253 md_estimate_size_before_relax (fragP, segment)
4254 register fragS *fragP;
4255 segT segment;
4256 {
4257 int old_fix;
4258 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4259
4260 old_fix = fragP->fr_fix;
4261
4262 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4263 switch (fragP->fr_subtype)
4264 {
4265
4266 case TAB (ABRANCH, SZ_UNDEF):
4267 {
4268 if ((fragP->fr_symbol != NULL) /* Not absolute */
4269 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4270 {
4271 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4272 break;
4273 }
4274 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4275 {
4276 /* On 68000, or for absolute value, switch to abs long */
4277 /* FIXME, we should check abs val, pick short or long */
4278 if (fragP->fr_opcode[0] == 0x61)
4279 {
4280 fragP->fr_opcode[0] = 0x4E;
4281 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4282 subseg_change (text_section, 0);
4283 fix_new (fragP, fragP->fr_fix, 4,
4284 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4285 fragP->fr_fix += 4;
4286 frag_wane (fragP);
4287 }
4288 else if (fragP->fr_opcode[0] == 0x60)
4289 {
4290 fragP->fr_opcode[0] = 0x4E;
4291 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4292 subseg_change (text_section, 0);
4293 fix_new (fragP, fragP->fr_fix, 4,
4294 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4295 fragP->fr_fix += 4;
4296 frag_wane (fragP);
4297 }
4298 else
4299 {
4300 as_warn ("Long branch offset to extern symbol not supported.");
4301 }
4302 }
4303 else
4304 { /* Symbol is still undefined. Make it simple */
4305 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4306 fragP->fr_offset + 4, 1, NO_RELOC);
4307 fragP->fr_fix += 4;
4308 fragP->fr_opcode[1] = (char) 0xff;
4309 frag_wane (fragP);
4310 break;
4311 }
4312
4313 break;
4314 } /* case TAB(ABRANCH,SZ_UNDEF) */
4315
4316 case TAB (FBRANCH, SZ_UNDEF):
4317 {
4318 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flagseen['l'])
4319 {
4320 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4321 fragP->fr_var += 2;
4322 }
4323 else
4324 {
4325 fragP->fr_subtype = TAB (FBRANCH, LONG);
4326 fragP->fr_var += 4;
4327 }
4328 break;
4329 } /* TAB(FBRANCH,SZ_UNDEF) */
4330
4331 case TAB (PCREL, SZ_UNDEF):
4332 {
4333 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flagseen['l'])
4334 {
4335 fragP->fr_subtype = TAB (PCREL, SHORT);
4336 fragP->fr_var += 2;
4337 }
4338 else
4339 {
4340 fragP->fr_subtype = TAB (PCREL, LONG);
4341 fragP->fr_var += 4;
4342 }
4343 break;
4344 } /* TAB(PCREL,SZ_UNDEF) */
4345
4346 case TAB (BCC68000, SZ_UNDEF):
4347 {
4348 if ((fragP->fr_symbol != NULL)
4349 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4350 {
4351 fragP->fr_subtype = TAB (BCC68000, BYTE);
4352 break;
4353 }
4354 /* only Bcc 68000 instructions can come here */
4355 /* change bcc into b!cc/jmp absl long */
4356 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4357 if (flagseen['l'])
4358 {
4359 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4360 /* JF: these were fr_opcode[2,3] */
4361 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4362 buffer_address[1] = (char) 0xf8;
4363 fragP->fr_fix += 2; /* account for jmp instruction */
4364 subseg_change (text_section, 0);
4365 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4366 fragP->fr_offset, 0, NO_RELOC);
4367 fragP->fr_fix += 2;
4368 }
4369 else
4370 {
4371 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4372 /* JF: these were fr_opcode[2,3] */
4373 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4374 buffer_address[1] = (char) 0xf9;
4375 fragP->fr_fix += 2; /* account for jmp instruction */
4376 subseg_change (text_section, 0);
4377 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4378 fragP->fr_offset, 0, NO_RELOC);
4379 fragP->fr_fix += 4;
4380 }
4381 frag_wane (fragP);
4382 break;
4383 } /* case TAB(BCC68000,SZ_UNDEF) */
4384
4385 case TAB (DBCC, SZ_UNDEF):
4386 {
4387 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4388 {
4389 fragP->fr_subtype = TAB (DBCC, SHORT);
4390 fragP->fr_var += 2;
4391 break;
4392 }
4393 /* only DBcc 68000 instructions can come here */
4394 /* change dbcc into dbcc/jmp absl long */
4395 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4396 buffer_address[0] = 0x00; /* branch offset = 4 */
4397 buffer_address[1] = 0x04;
4398 buffer_address[2] = 0x60; /* put in bra pc + ... */
4399
4400 if (flagseen['l'])
4401 {
4402 /* JF: these were fr_opcode[5-7] */
4403 buffer_address[3] = 0x04; /* plus 4 */
4404 buffer_address[4] = 0x4e; /* Put in Jump Word */
4405 buffer_address[5] = (char) 0xf8;
4406 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4407 subseg_change (text_section, 0);
4408 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4409 fragP->fr_offset, 0, NO_RELOC);
4410 fragP->fr_fix += 2;
4411 }
4412 else
4413 {
4414 /* JF: these were fr_opcode[5-7] */
4415 buffer_address[3] = 0x06; /* Plus 6 */
4416 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4417 buffer_address[5] = (char) 0xf9;
4418 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4419 subseg_change (text_section, 0);
4420 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4421 fragP->fr_offset, 0, NO_RELOC);
4422 fragP->fr_fix += 4;
4423 }
4424
4425 frag_wane (fragP);
4426 break;
4427 } /* case TAB(DBCC,SZ_UNDEF) */
4428
4429 case TAB (PCLEA, SZ_UNDEF):
4430 {
4431 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment || flagseen['l'])
4432 {
4433 fragP->fr_subtype = TAB (PCLEA, SHORT);
4434 fragP->fr_var += 2;
4435 }
4436 else
4437 {
4438 fragP->fr_subtype = TAB (PCLEA, LONG);
4439 fragP->fr_var += 6;
4440 }
4441 break;
4442 } /* TAB(PCLEA,SZ_UNDEF) */
4443
4444 default:
4445 break;
4446
4447 } /* switch on subtype looking for SZ_UNDEF's. */
4448
4449 /* now that SZ_UNDEF are taken care of, check others */
4450 switch (fragP->fr_subtype)
4451 {
4452 case TAB (BCC68000, BYTE):
4453 case TAB (ABRANCH, BYTE):
4454 /* We can't do a short jump to the next instruction,
4455 so we force word mode. */
4456 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
4457 fragP->fr_symbol->sy_frag == fragP->fr_next)
4458 {
4459 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4460 fragP->fr_var += 2;
4461 }
4462 break;
4463 default:
4464 break;
4465 }
4466 return fragP->fr_var + fragP->fr_fix - old_fix;
4467 }
4468
4469 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4470 /* the bit-field entries in the relocation_info struct plays hell
4471 with the byte-order problems of cross-assembly. So as a hack,
4472 I added this mach. dependent ri twiddler. Ugly, but it gets
4473 you there. -KWK */
4474 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4475 are symbolnum, most sig. byte first. Last byte is broken up with
4476 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4477 nibble as nuthin. (on Sun 3 at least) */
4478 /* Translate the internal relocation information into target-specific
4479 format. */
4480 #ifdef comment
4481 void
4482 md_ri_to_chars (the_bytes, ri)
4483 char *the_bytes;
4484 struct reloc_info_generic *ri;
4485 {
4486 /* this is easy */
4487 md_number_to_chars (the_bytes, ri->r_address, 4);
4488 /* now the fun stuff */
4489 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4490 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4491 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4492 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4493 ((ri->r_extern << 4) & 0x10));
4494 }
4495
4496 #endif /* comment */
4497
4498 #ifndef BFD_ASSEMBLER
4499 void
4500 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4501 char *where;
4502 fixS *fixP;
4503 relax_addressT segment_address_in_file;
4504 {
4505 /*
4506 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4507 * Out: GNU LD relocation length code: 0, 1, or 2.
4508 */
4509
4510 static CONST unsigned char nbytes_r_length[] =
4511 {42, 0, 1, 42, 2};
4512 long r_symbolnum;
4513
4514 know (fixP->fx_addsy != NULL);
4515
4516 md_number_to_chars (where,
4517 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4518 4);
4519
4520 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4521 ? S_GET_TYPE (fixP->fx_addsy)
4522 : fixP->fx_addsy->sy_number);
4523
4524 where[4] = (r_symbolnum >> 16) & 0x0ff;
4525 where[5] = (r_symbolnum >> 8) & 0x0ff;
4526 where[6] = r_symbolnum & 0x0ff;
4527 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4528 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4529
4530 return;
4531 }
4532 #endif
4533
4534 #endif /* OBJ_AOUT or OBJ_BOUT */
4535
4536 #ifndef WORKING_DOT_WORD
4537 CONST int md_short_jump_size = 4;
4538 CONST int md_long_jump_size = 6;
4539
4540 void
4541 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4542 char *ptr;
4543 addressT from_addr, to_addr;
4544 fragS *frag;
4545 symbolS *to_symbol;
4546 {
4547 valueT offset;
4548
4549 offset = to_addr - (from_addr + 2);
4550
4551 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4552 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4553 }
4554
4555 void
4556 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4557 char *ptr;
4558 addressT from_addr, to_addr;
4559 fragS *frag;
4560 symbolS *to_symbol;
4561 {
4562 valueT offset;
4563
4564 if (cpu_of_arch (current_architecture) < m68020)
4565 {
4566 offset = to_addr - S_GET_VALUE (to_symbol);
4567 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4568 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4569 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4570 0, NO_RELOC);
4571 }
4572 else
4573 {
4574 offset = to_addr - (from_addr + 2);
4575 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4576 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4577 }
4578 }
4579
4580 #endif
4581 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
4582
4583 0: Everything is OK
4584 10: Absolute 1:8 only
4585 20: Absolute 0:7 only
4586 30: absolute 0:15 only
4587 40: Absolute 0:31 only
4588 50: absolute 0:127 only
4589 55: absolute -64:63 only
4590 60: absolute -128:127 only
4591 70: absolute 0:4095 only
4592 80: No bignums
4593
4594 */
4595
4596 static int
4597 get_num (exp, ok)
4598 struct m68k_exp *exp;
4599 int ok;
4600 {
4601 #ifdef TEST2
4602 long l = 0;
4603
4604 if (!exp->e_beg)
4605 return 0;
4606 if (*exp->e_beg == '0')
4607 {
4608 if (exp->e_beg[1] == 'x')
4609 sscanf (exp->e_beg + 2, "%x", &l);
4610 else
4611 sscanf (exp->e_beg + 1, "%O", &l);
4612 return l;
4613 }
4614 return atol (exp->e_beg);
4615 #else
4616 char *save_in;
4617 char c_save;
4618 segT section;
4619
4620 if (!exp)
4621 {
4622 /* Can't do anything */
4623 return 0;
4624 }
4625 if (!exp->e_beg || !exp->e_end)
4626 {
4627 seg (exp) = absolute_section;
4628 adds (exp) = 0;
4629 subs (exp) = 0;
4630 offs (exp) = (ok == 10) ? 1 : 0;
4631 as_warn ("Null expression defaults to %ld", offs (exp));
4632 return 0;
4633 }
4634
4635 exp->e_siz = 0;
4636 if ( /* ok!=80 && */ (exp->e_end[-1] == ':' || exp->e_end[-1] == '.')
4637 && (exp->e_end - exp->e_beg) >= 2)
4638 {
4639 switch (exp->e_end[0])
4640 {
4641 case 's':
4642 case 'S':
4643 case 'b':
4644 case 'B':
4645 exp->e_siz = 1;
4646 exp->e_end -= 2;
4647 break;
4648 case 'w':
4649 case 'W':
4650 exp->e_siz = 2;
4651 exp->e_end -= 2;
4652 break;
4653 case 'l':
4654 case 'L':
4655 exp->e_siz = 3;
4656 exp->e_end -= 2;
4657 break;
4658 default:
4659 if (exp->e_end[-1] == ':')
4660 as_bad ("Unknown size for expression \"%c\"", exp->e_end[0]);
4661 break;
4662 }
4663 }
4664 c_save = exp->e_end[1];
4665 exp->e_end[1] = '\0';
4666 save_in = input_line_pointer;
4667 input_line_pointer = exp->e_beg;
4668 section = expression (&exp->e_exp);
4669 seg (exp) = section;
4670 if (exp->e_exp.X_op == O_absent)
4671 {
4672 /* Do the same thing the VAX asm does */
4673 seg (exp) = absolute_section;
4674 op (exp) = O_constant;
4675 adds (exp) = 0;
4676 subs (exp) = 0;
4677 offs (exp) = 0;
4678 if (ok == 10)
4679 {
4680 as_warn ("expression out of range: defaulting to 1");
4681 offs (exp) = 1;
4682 }
4683 }
4684 else if (exp->e_exp.X_op == O_constant)
4685 {
4686 switch (ok)
4687 {
4688 case 10:
4689 if (offs (exp) < 1 || offs (exp) > 8)
4690 {
4691 as_warn ("expression out of range: defaulting to 1");
4692 offs (exp) = 1;
4693 }
4694 break;
4695 case 20:
4696 if (offs (exp) < 0 || offs (exp) > 7)
4697 goto outrange;
4698 break;
4699 case 30:
4700 if (offs (exp) < 0 || offs (exp) > 15)
4701 goto outrange;
4702 break;
4703 case 40:
4704 if (offs (exp) < 0 || offs (exp) > 32)
4705 goto outrange;
4706 break;
4707 case 50:
4708 if (offs (exp) < 0 || offs (exp) > 127)
4709 goto outrange;
4710 break;
4711 case 55:
4712 if (offs (exp) < -64 || offs (exp) > 63)
4713 goto outrange;
4714 break;
4715 case 60:
4716 if (offs (exp) < -128 || offs (exp) > 127)
4717 goto outrange;
4718 break;
4719 case 70:
4720 if (offs (exp) < 0 || offs (exp) > 4095)
4721 {
4722 outrange:
4723 as_warn ("expression out of range: defaulting to 0");
4724 offs (exp) = 0;
4725 }
4726 break;
4727 default:
4728 break;
4729 }
4730 }
4731 else if (exp->e_exp.X_op == O_big)
4732 {
4733 if (offs (exp) <= 0 /* flonum */
4734 && (ok == 80 /* no bignums */
4735 || (ok > 10 /* small-int ranges including 0 ok */
4736 /* If we have a flonum zero, a zero integer should
4737 do as well (e.g., in moveq). */
4738 && generic_floating_point_number.exponent == 0
4739 && generic_floating_point_number.low[0] == 0)))
4740 {
4741 /* HACK! Turn it into a long */
4742 LITTLENUM_TYPE words[6];
4743
4744 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4745 seg (exp) = absolute_section;
4746 op (exp) = O_constant;
4747 adds (exp) = 0;
4748 subs (exp) = 0;
4749 offs (exp) = words[1] | (words[0] << 16);
4750 }
4751 else if (ok != 0)
4752 {
4753 seg (exp) = absolute_section;
4754 op (exp) = O_constant;
4755 adds (exp) = 0;
4756 subs (exp) = 0;
4757 offs (exp) = (ok == 10) ? 1 : 0;
4758 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4759 }
4760 }
4761 else
4762 {
4763 if (ok >= 10 && ok <= 70)
4764 {
4765 seg (exp) = absolute_section;
4766 op (exp) = O_constant;
4767 adds (exp) = 0;
4768 subs (exp) = 0;
4769 offs (exp) = (ok == 10) ? 1 : 0;
4770 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4771 }
4772 }
4773
4774 if (input_line_pointer != exp->e_end + 1)
4775 as_bad ("Ignoring junk after expression");
4776 exp->e_end[1] = c_save;
4777 input_line_pointer = save_in;
4778 if (exp->e_siz)
4779 {
4780 switch (exp->e_siz)
4781 {
4782 case 1:
4783 if (!isbyte (offs (exp)))
4784 as_warn ("expression doesn't fit in BYTE");
4785 break;
4786 case 2:
4787 if (!isword (offs (exp)))
4788 as_warn ("expression doesn't fit in WORD");
4789 break;
4790 }
4791 }
4792 return offs (exp);
4793 #endif
4794 }
4795
4796 /* These are the back-ends for the various machine dependent pseudo-ops. */
4797 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4798
4799 static void
4800 s_data1 (ignore)
4801 int ignore;
4802 {
4803 subseg_set (data_section, 1);
4804 demand_empty_rest_of_line ();
4805 }
4806
4807 static void
4808 s_data2 (ignore)
4809 int ignore;
4810 {
4811 subseg_set (data_section, 2);
4812 demand_empty_rest_of_line ();
4813 }
4814
4815 static void
4816 s_bss (ignore)
4817 int ignore;
4818 {
4819 /* We don't support putting frags in the BSS segment, we fake it
4820 by marking in_bss, then looking at s_skip for clues. */
4821
4822 subseg_set (bss_section, 0);
4823 demand_empty_rest_of_line ();
4824 }
4825
4826 static void
4827 s_even (ignore)
4828 int ignore;
4829 {
4830 register int temp;
4831 register long temp_fill;
4832
4833 temp = 1; /* JF should be 2? */
4834 temp_fill = get_absolute_expression ();
4835 if (!need_pass_2) /* Never make frag if expect extra pass. */
4836 frag_align (temp, (int) temp_fill);
4837 demand_empty_rest_of_line ();
4838 }
4839
4840 static void
4841 s_proc (ignore)
4842 int ignore;
4843 {
4844 demand_empty_rest_of_line ();
4845 }
4846
4847 /* s_space is defined in read.c .skip is simply an alias to it. */
4848
4849 /*
4850 * md_parse_option
4851 * Invocation line includes a switch not recognized by the base assembler.
4852 * See if it's a processor-specific option. These are:
4853 *
4854 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4855 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4856 * Select the architecture. Instructions or features not
4857 * supported by the selected architecture cause fatal
4858 * errors. More than one may be specified. The default is
4859 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4860 * for -m68000, and -m68882 is a synonym for -m68881.
4861 * -[A]m[c]no-68851, -[A]m[c]no-68881
4862 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4863 * so don't use or document it, but that's the way the parsing
4864 * works).
4865 *
4866 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4867 * (e.g. m68020) also requests that float instructions be included. This
4868 * is the default setup, mostly to avoid hassling users. A better
4869 * rearrangement of this structure would be to add an option to DENY
4870 * floating point opcodes, for people who want to really know there's none
4871 * of that funny floaty stuff going on. FIXME-later.
4872 */
4873 #ifndef MAYBE_FLOAT_TOO
4874 #define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */
4875 #endif
4876
4877 int
4878 md_parse_option (argP, cntP, vecP)
4879 char **argP;
4880 int *cntP;
4881 char ***vecP;
4882 {
4883 switch (**argP)
4884 {
4885 case 'l': /* -l means keep external to 2 bit offset
4886 rather than 16 bit one */
4887 break;
4888
4889 case 'S': /* -S means that jbsr's always turn into
4890 jsr's. */
4891 break;
4892
4893 case 'A':
4894 (*argP)++;
4895 /* intentional fall-through */
4896 case 'm':
4897 (*argP)++;
4898
4899 if (**argP == 'c')
4900 {
4901 (*argP)++;
4902 } /* allow an optional "c" */
4903
4904 if (!strcmp (*argP, "68000")
4905 || !strcmp (*argP, "68008")
4906 || !strcmp (*argP, "68302"))
4907 {
4908 current_architecture |= m68000;
4909 }
4910 else if (!strcmp (*argP, "68010"))
4911 {
4912 #ifdef TE_SUN
4913 omagic = 1 << 16 | OMAGIC;
4914 #endif
4915 current_architecture |= m68010;
4916 }
4917 else if (!strcmp (*argP, "68020"))
4918 {
4919 current_architecture |= m68020 | MAYBE_FLOAT_TOO;
4920 }
4921 else if (!strcmp (*argP, "68030"))
4922 {
4923 current_architecture |= m68030 | MAYBE_FLOAT_TOO;
4924 }
4925 else if (!strcmp (*argP, "68040"))
4926 {
4927 current_architecture |= m68040 | MAYBE_FLOAT_TOO;
4928 }
4929 #ifndef NO_68881
4930 else if (!strcmp (*argP, "68881"))
4931 {
4932 current_architecture |= m68881;
4933 }
4934 else if (!strcmp (*argP, "68882"))
4935 {
4936 current_architecture |= m68882;
4937 }
4938 #endif /* NO_68881 */
4939 /* Even if we aren't configured to support the processor,
4940 it should still be possible to assert that the user
4941 doesn't have it... */
4942 else if (!strcmp (*argP, "no-68881")
4943 || !strcmp (*argP, "no-68882"))
4944 {
4945 no_68881 = 1;
4946 }
4947 #ifndef NO_68851
4948 else if (!strcmp (*argP, "68851"))
4949 {
4950 current_architecture |= m68851;
4951 }
4952 #endif /* NO_68851 */
4953 else if (!strcmp (*argP, "no-68851"))
4954 {
4955 no_68851 = 1;
4956 }
4957 else if (!strcmp (*argP, "pu32") /* "cpu32" minus 'c' */
4958 || !strcmp (*argP, "68331")
4959 || !strcmp (*argP, "68332")
4960 || !strcmp (*argP, "68333")
4961 || !strcmp (*argP, "68340"))
4962 {
4963 current_architecture |= cpu32;
4964 }
4965 else
4966 {
4967 as_warn ("Unknown architecture, \"%s\". option ignored", *argP);
4968 } /* switch on architecture */
4969
4970 while (**argP)
4971 (*argP)++;
4972
4973 break;
4974
4975 case 'p':
4976 if (!strcmp (*argP, "pic"))
4977 {
4978 (*argP) += 3;
4979 break; /* -pic, Position Independent Code */
4980 }
4981 else
4982 {
4983 return 0;
4984 } /* pic or not */
4985
4986 default:
4987 return 0;
4988 }
4989 return 1;
4990 }
4991
4992
4993 #ifdef TEST2
4994
4995 /* TEST2: Test md_assemble() */
4996 /* Warning, this routine probably doesn't work anymore */
4997
4998 main ()
4999 {
5000 struct m68k_it the_ins;
5001 char buf[120];
5002 char *cp;
5003 int n;
5004
5005 m68k_ip_begin ();
5006 for (;;)
5007 {
5008 if (!gets (buf) || !*buf)
5009 break;
5010 if (buf[0] == '|' || buf[1] == '.')
5011 continue;
5012 for (cp = buf; *cp; cp++)
5013 if (*cp == '\t')
5014 *cp = ' ';
5015 if (is_label (buf))
5016 continue;
5017 memset (&the_ins, '\0', sizeof (the_ins));
5018 m68k_ip (&the_ins, buf);
5019 if (the_ins.error)
5020 {
5021 printf ("Error %s in %s\n", the_ins.error, buf);
5022 }
5023 else
5024 {
5025 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
5026 for (n = 0; n < the_ins.numo; n++)
5027 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
5028 printf (" ");
5029 print_the_insn (&the_ins.opcode[0], stdout);
5030 (void) putchar ('\n');
5031 }
5032 for (n = 0; n < strlen (the_ins.args) / 2; n++)
5033 {
5034 if (the_ins.operands[n].error)
5035 {
5036 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
5037 continue;
5038 }
5039 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
5040 if (the_ins.operands[n].b_const)
5041 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
5042 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
5043 if (the_ins.operands[n].b_iadd)
5044 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
5045 (void) putchar ('\n');
5046 }
5047 }
5048 m68k_ip_end ();
5049 return 0;
5050 }
5051
5052 is_label (str)
5053 char *str;
5054 {
5055 while (*str == ' ')
5056 str++;
5057 while (*str && *str != ' ')
5058 str++;
5059 if (str[-1] == ':' || str[1] == '=')
5060 return 1;
5061 return 0;
5062 }
5063
5064 #endif
5065
5066 /* Possible states for relaxation:
5067
5068 0 0 branch offset byte (bra, etc)
5069 0 1 word
5070 0 2 long
5071
5072 1 0 indexed offsets byte a0@(32,d4:w:1) etc
5073 1 1 word
5074 1 2 long
5075
5076 2 0 two-offset index word-word a0@(32,d4)@(45) etc
5077 2 1 word-long
5078 2 2 long-word
5079 2 3 long-long
5080
5081 */
5082
5083 /* We have no need to default values of symbols. */
5084
5085 /* ARGSUSED */
5086 symbolS *
5087 md_undefined_symbol (name)
5088 char *name;
5089 {
5090 return 0;
5091 }
5092
5093 /* Parse an operand that is machine-specific.
5094 We just return without modifying the expression if we have nothing
5095 to do. */
5096
5097 /* ARGSUSED */
5098 void
5099 md_operand (expressionP)
5100 expressionS *expressionP;
5101 {
5102 }
5103
5104 /* Round up a section size to the appropriate boundary. */
5105 valueT
5106 md_section_align (segment, size)
5107 segT segment;
5108 valueT size;
5109 {
5110 return size; /* Byte alignment is fine */
5111 }
5112
5113 /* Exactly what point is a PC-relative offset relative TO?
5114 On the 68k, they're relative to the address of the offset, plus
5115 its size. (??? Is this right? FIXME-SOON!) */
5116 long
5117 md_pcrel_from (fixP)
5118 fixS *fixP;
5119 {
5120 return (fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address);
5121 }
5122
5123 #ifndef BFD_ASSEMBLER
5124 void
5125 tc_coff_symbol_emit_hook ()
5126 {
5127 }
5128
5129 int
5130 tc_coff_sizemachdep (frag)
5131 fragS *frag;
5132 {
5133 switch (frag->fr_subtype & 0x3)
5134 {
5135 case BYTE:
5136 return 1;
5137 case SHORT:
5138 return 2;
5139 case LONG:
5140 return 4;
5141 default:
5142 abort ();
5143 }
5144 }
5145 #endif
5146
5147 /* end of tc-m68k.c */
GDB Binutils - Deliverables
This page took 0.143119 seconds and 5 git commands to generate.