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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
177 0
178 };
179 static const enum m68k_register mcf51qe_ctrl[] = {
180 VBR,
181 0
182 };
183 static const enum m68k_register mcf5206_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
185 0
186 };
187 static const enum m68k_register mcf5208_ctrl[] = {
188 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
189 0
190 };
191 static const enum m68k_register mcf5210a_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
193 0
194 };
195 static const enum m68k_register mcf5213_ctrl[] = {
196 VBR, RAMBAR, RAMBAR1, FLASHBAR,
197 0
198 };
199 static const enum m68k_register mcf5216_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
201 0
202 };
203 static const enum m68k_register mcf52223_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
205 0
206 };
207 static const enum m68k_register mcf52235_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
209 0
210 };
211 static const enum m68k_register mcf5225_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
213 0
214 };
215 static const enum m68k_register mcf5235_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
217 0
218 };
219 static const enum m68k_register mcf5249_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
221 0
222 };
223 static const enum m68k_register mcf5250_ctrl[] = {
224 VBR,
225 0
226 };
227 static const enum m68k_register mcf5253_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
229 0
230 };
231 static const enum m68k_register mcf5271_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
233 0
234 };
235 static const enum m68k_register mcf5272_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
237 0
238 };
239 static const enum m68k_register mcf5275_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
241 0
242 };
243 static const enum m68k_register mcf5282_ctrl[] = {
244 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
245 0
246 };
247 static const enum m68k_register mcf5307_ctrl[] = {
248 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
249 0
250 };
251 static const enum m68k_register mcf5329_ctrl[] = {
252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
253 0
254 };
255 static const enum m68k_register mcf5373_ctrl[] = {
256 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
257 0
258 };
259 static const enum m68k_register mcfv4e_ctrl[] = {
260 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
261 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
262 MBAR, SECMBAR,
263 MPCR /* Multiprocessor Control register */,
264 EDRAMBAR /* Embedded DRAM Base Address Register */,
265 /* Permutation control registers. */
266 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
267 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
268 /* Legacy names */
269 TC /* ASID */, BUSCR /* MMUBAR */,
270 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
271 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
272 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
273 0
274 };
275 static const enum m68k_register mcf5407_ctrl[] = {
276 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
277 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
278 /* Legacy names */
279 TC /* ASID */,
280 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
281 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
282 0
283 };
284 static const enum m68k_register mcf54455_ctrl[] = {
285 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
286 VBR, PC, RAMBAR1, MBAR,
287 /* Legacy names */
288 TC /* ASID */, BUSCR /* MMUBAR */,
289 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
290 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
291 0
292 };
293 static const enum m68k_register mcf5475_ctrl[] = {
294 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
295 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
296 /* Legacy names */
297 TC /* ASID */, BUSCR /* MMUBAR */,
298 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
299 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
300 0
301 };
302 static const enum m68k_register mcf5485_ctrl[] = {
303 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
304 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
305 /* Legacy names */
306 TC /* ASID */, BUSCR /* MMUBAR */,
307 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
308 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
309 0
310 };
311 static const enum m68k_register fido_ctrl[] = {
312 SFC, DFC, USP, VBR, CAC, MBO,
313 0
314 };
315 #define cpu32_ctrl m68010_ctrl
316
317 static const enum m68k_register *control_regs;
318
319 /* Internal form of a 68020 instruction. */
320 struct m68k_it
321 {
322 const char *error;
323 const char *args; /* List of opcode info. */
324 int numargs;
325
326 int numo; /* Number of shorts in opcode. */
327 short opcode[11];
328
329 struct m68k_op operands[6];
330
331 int nexp; /* Number of exprs in use. */
332 struct m68k_exp exprs[4];
333
334 int nfrag; /* Number of frags we have to produce. */
335 struct
336 {
337 int fragoff; /* Where in the current opcode the frag ends. */
338 symbolS *fadd;
339 offsetT foff;
340 int fragty;
341 }
342 fragb[4];
343
344 int nrel; /* Num of reloc strucs in use. */
345 struct
346 {
347 int n;
348 expressionS exp;
349 char wid;
350 char pcrel;
351 /* In a pc relative address the difference between the address
352 of the offset and the address that the offset is relative
353 to. This depends on the addressing mode. Basically this
354 is the value to put in the offset field to address the
355 first byte of the offset, without regarding the special
356 significance of some values (in the branch instruction, for
357 example). */
358 int pcrel_fix;
359 #ifdef OBJ_ELF
360 /* Whether this expression needs special pic relocation, and if
361 so, which. */
362 enum pic_relocation pic_reloc;
363 #endif
364 }
365 reloc[5]; /* Five is enough??? */
366 };
367
368 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
369 #define float_of_arch(x) ((x) & mfloat)
370 #define mmu_of_arch(x) ((x) & mmmu)
371 #define arch_coldfire_p(x) ((x) & mcfisa_a)
372 #define arch_coldfire_fpu(x) ((x) & cfloat)
373
374 /* Macros for determining if cpu supports a specific addressing mode. */
375 #define HAVE_LONG_DISP(x) \
376 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
377 #define HAVE_LONG_CALL(x) \
378 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
379 #define HAVE_LONG_COND(x) \
380 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
381 #define HAVE_LONG_BRANCH(x) \
382 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
383 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
384
385 static struct m68k_it the_ins; /* The instruction being assembled. */
386
387 #define op(ex) ((ex)->exp.X_op)
388 #define adds(ex) ((ex)->exp.X_add_symbol)
389 #define subs(ex) ((ex)->exp.X_op_symbol)
390 #define offs(ex) ((ex)->exp.X_add_number)
391
392 /* Macros for adding things to the m68k_it struct. */
393 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
394
395 /* Like addword, but goes BEFORE general operands. */
396
397 static void
398 insop (int w, const struct m68k_incant *opcode)
399 {
400 int z;
401 for (z = the_ins.numo; z > opcode->m_codenum; --z)
402 the_ins.opcode[z] = the_ins.opcode[z - 1];
403 for (z = 0; z < the_ins.nrel; z++)
404 the_ins.reloc[z].n += 2;
405 for (z = 0; z < the_ins.nfrag; z++)
406 the_ins.fragb[z].fragoff++;
407 the_ins.opcode[opcode->m_codenum] = w;
408 the_ins.numo++;
409 }
410
411 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
412 Blecch. */
413 static void
414 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
415 {
416 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
417 ? the_ins.numo * 2 - 1
418 : (width == 'b'
419 ? the_ins.numo * 2 + 1
420 : the_ins.numo * 2));
421 the_ins.reloc[the_ins.nrel].exp = exp->exp;
422 the_ins.reloc[the_ins.nrel].wid = width;
423 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
424 #ifdef OBJ_ELF
425 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
426 #endif
427 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
428 }
429
430 /* Cause an extra frag to be generated here, inserting up to 10 bytes
431 (that value is chosen in the frag_var call in md_assemble). TYPE
432 is the subtype of the frag to be generated; its primary type is
433 rs_machine_dependent.
434
435 The TYPE parameter is also used by md_convert_frag_1 and
436 md_estimate_size_before_relax. The appropriate type of fixup will
437 be emitted by md_convert_frag_1.
438
439 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
440 static void
441 add_frag (symbolS *add, offsetT off, int type)
442 {
443 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
444 the_ins.fragb[the_ins.nfrag].fadd = add;
445 the_ins.fragb[the_ins.nfrag].foff = off;
446 the_ins.fragb[the_ins.nfrag++].fragty = type;
447 }
448
449 #define isvar(ex) \
450 (op (ex) != O_constant && op (ex) != O_big)
451
452 static char *crack_operand (char *str, struct m68k_op *opP);
453 static int get_num (struct m68k_exp *exp, int ok);
454 static int reverse_16_bits (int in);
455 static int reverse_8_bits (int in);
456 static void install_gen_operand (int mode, int val);
457 static void install_operand (int mode, int val);
458 static void s_bss (int);
459 static void s_data1 (int);
460 static void s_data2 (int);
461 static void s_even (int);
462 static void s_proc (int);
463 static void s_chip (int);
464 static void s_fopt (int);
465 static void s_opt (int);
466 static void s_reg (int);
467 static void s_restore (int);
468 static void s_save (int);
469 static void s_mri_if (int);
470 static void s_mri_else (int);
471 static void s_mri_endi (int);
472 static void s_mri_break (int);
473 static void s_mri_next (int);
474 static void s_mri_for (int);
475 static void s_mri_endf (int);
476 static void s_mri_repeat (int);
477 static void s_mri_until (int);
478 static void s_mri_while (int);
479 static void s_mri_endw (int);
480 static void s_m68k_cpu (int);
481 static void s_m68k_arch (int);
482
483 struct m68k_cpu
484 {
485 unsigned long arch; /* Architecture features. */
486 const enum m68k_register *control_regs; /* Control regs on chip */
487 const char *name; /* Name */
488 int alias; /* Alias for a cannonical name. If 1, then
489 succeeds canonical name, if -1 then
490 succeeds canonical name, if <-1 ||>1 this is a
491 deprecated name, and the next/previous name
492 should be used. */
493 };
494
495 /* We hold flags for features explicitly enabled and explicitly
496 disabled. */
497 static int current_architecture;
498 static int not_current_architecture;
499 static const struct m68k_cpu *selected_arch;
500 static const struct m68k_cpu *selected_cpu;
501 static int initialized;
502
503 /* Architecture models. */
504 static const struct m68k_cpu m68k_archs[] =
505 {
506 {m68000, m68000_ctrl, "68000", 0},
507 {m68010, m68010_ctrl, "68010", 0},
508 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
509 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
510 {m68040, m68040_ctrl, "68040", 0},
511 {m68060, m68060_ctrl, "68060", 0},
512 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
513 {fido_a, fido_ctrl, "fidoa", 0},
514 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
515 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
516 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
517 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
518 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
519 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
520 {0,0,NULL, 0}
521 };
522
523 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
524 for either. */
525 static const struct m68k_cpu m68k_extensions[] =
526 {
527 {m68851, NULL, "68851", -1},
528 {m68881, NULL, "68881", -1},
529 {m68881, NULL, "68882", -1},
530
531 {cfloat|m68881, NULL, "float", 0},
532
533 {mcfhwdiv, NULL, "div", 1},
534 {mcfusp, NULL, "usp", 1},
535 {mcfmac, NULL, "mac", 1},
536 {mcfemac, NULL, "emac", 1},
537
538 {0,NULL,NULL, 0}
539 };
540
541 /* Processor list */
542 static const struct m68k_cpu m68k_cpus[] =
543 {
544 {m68000, m68000_ctrl, "68000", 0},
545 {m68000, m68000_ctrl, "68ec000", 1},
546 {m68000, m68000_ctrl, "68hc000", 1},
547 {m68000, m68000_ctrl, "68hc001", 1},
548 {m68000, m68000_ctrl, "68008", 1},
549 {m68000, m68000_ctrl, "68302", 1},
550 {m68000, m68000_ctrl, "68306", 1},
551 {m68000, m68000_ctrl, "68307", 1},
552 {m68000, m68000_ctrl, "68322", 1},
553 {m68000, m68000_ctrl, "68356", 1},
554 {m68010, m68010_ctrl, "68010", 0},
555 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
556 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
557 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
558 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
559 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
560 {m68040, m68040_ctrl, "68040", 0},
561 {m68040, m68040_ctrl, "68ec040", 1},
562 {m68060, m68060_ctrl, "68060", 0},
563 {m68060, m68060_ctrl, "68ec060", 1},
564
565 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
566 {cpu32|m68881, cpu32_ctrl, "68330", 1},
567 {cpu32|m68881, cpu32_ctrl, "68331", 1},
568 {cpu32|m68881, cpu32_ctrl, "68332", 1},
569 {cpu32|m68881, cpu32_ctrl, "68333", 1},
570 {cpu32|m68881, cpu32_ctrl, "68334", 1},
571 {cpu32|m68881, cpu32_ctrl, "68336", 1},
572 {cpu32|m68881, cpu32_ctrl, "68340", 1},
573 {cpu32|m68881, cpu32_ctrl, "68341", 1},
574 {cpu32|m68881, cpu32_ctrl, "68349", 1},
575 {cpu32|m68881, cpu32_ctrl, "68360", 1},
576
577 {mcfisa_a|mcfisa_c|mcfusp, mcf51qe_ctrl, "51qe", 0},
578
579 {mcfisa_a, mcf_ctrl, "5200", 0},
580 {mcfisa_a, mcf_ctrl, "5202", 1},
581 {mcfisa_a, mcf_ctrl, "5204", 1},
582 {mcfisa_a, mcf5206_ctrl, "5206", 1},
583
584 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
585
586 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
587 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
588
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
590 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
591
592 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
594 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
595
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
599
600 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
601 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
602
603 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
604 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
607
608 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
609 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
610
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
612 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
613 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
615 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
616
617 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
618 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
619 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
620
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
623
624 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
625
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
628
629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
633
634 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
635
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
639 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
640
641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
644
645 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
646
647 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
648 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
649 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
650 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
651 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
652 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
653
654 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
655 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
656 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
657 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
658 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
659 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
660 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
661
662 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
663 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
664 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
665 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
666 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
667 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
668 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
669
670 {fido_a, fido_ctrl, "fidoa", 0},
671 {fido_a, fido_ctrl, "fido", 1},
672
673 {0,NULL,NULL, 0}
674 };
675
676 static const struct m68k_cpu *m68k_lookup_cpu
677 (const char *, const struct m68k_cpu *, int, int *);
678 static int m68k_set_arch (const char *, int, int);
679 static int m68k_set_cpu (const char *, int, int);
680 static int m68k_set_extension (const char *, int, int);
681 static void m68k_init_arch (void);
682
683 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
684 architecture and we have a lot of relaxation modes. */
685
686 /* Macros used in the relaxation code. */
687 #define TAB(x,y) (((x) << 2) + (y))
688 #define TABTYPE(x) ((x) >> 2)
689
690 /* Relaxation states. */
691 #define BYTE 0
692 #define SHORT 1
693 #define LONG 2
694 #define SZ_UNDEF 3
695
696 /* Here are all the relaxation modes we support. First we can relax ordinary
697 branches. On 68020 and higher and on CPU32 all branch instructions take
698 three forms, so on these CPUs all branches always remain as such. When we
699 have to expand to the LONG form on a 68000, though, we substitute an
700 absolute jump instead. This is a direct replacement for unconditional
701 branches and a branch over a jump for conditional branches. However, if the
702 user requires PIC and disables this with --pcrel, we can only relax between
703 BYTE and SHORT forms, punting if that isn't enough. This gives us four
704 different relaxation modes for branches: */
705
706 #define BRANCHBWL 0 /* Branch byte, word, or long. */
707 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
708 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
709 #define BRANCHBW 3 /* Branch byte or word. */
710
711 /* We also relax coprocessor branches and DBcc's. All CPUs that support
712 coprocessor branches support them in word and long forms, so we have only
713 one relaxation mode for them. DBcc's are word only on all CPUs. We can
714 relax them to the LONG form with a branch-around sequence. This sequence
715 can use a long branch (if available) or an absolute jump (if acceptable).
716 This gives us two relaxation modes. If long branches are not available and
717 absolute jumps are not acceptable, we don't relax DBcc's. */
718
719 #define FBRANCH 4 /* Coprocessor branch. */
720 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
721 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
722
723 /* That's all for instruction relaxation. However, we also relax PC-relative
724 operands. Specifically, we have three operand relaxation modes. On the
725 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
726 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
727 two. Also PC+displacement+index operands in their simple form (with a non-
728 suppressed index without memory indirection) are supported on all CPUs, but
729 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
730 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
731 form of the PC+displacement+index operand. Finally, some absolute operands
732 can be relaxed down to 16-bit PC-relative. */
733
734 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
735 #define PCINDEX 8 /* PC + displacement + index. */
736 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
737
738 /* This relaxation is required for branches where there is no long
739 branch and we are in pcrel mode. We generate a bne/beq pair. */
740 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs
741 */
742
743 /* Note that calls to frag_var need to specify the maximum expansion
744 needed; this is currently 12 bytes for bne/beq pair. */
745 #define FRAG_VAR_SIZE 12
746
747 /* The fields are:
748 How far Forward this mode will reach:
749 How far Backward this mode will reach:
750 How many bytes this mode will add to the size of the frag
751 Which mode to go to if the offset won't fit in this one
752
753 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
754 relax_typeS md_relax_table[] =
755 {
756 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
757 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
758 { 0, 0, 4, 0 },
759 { 1, 1, 0, 0 },
760
761 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
762 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
763 { 0, 0, 4, 0 },
764 { 1, 1, 0, 0 },
765
766 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
767 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
768 { 0, 0, 6, 0 },
769 { 1, 1, 0, 0 },
770
771 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
772 { 0, 0, 2, 0 },
773 { 1, 1, 0, 0 },
774 { 1, 1, 0, 0 },
775
776 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
777 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
778 { 0, 0, 4, 0 },
779 { 1, 1, 0, 0 },
780
781 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
782 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
783 { 0, 0, 10, 0 },
784 { 1, 1, 0, 0 },
785
786 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
787 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
788 { 0, 0, 10, 0 },
789 { 1, 1, 0, 0 },
790
791 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
792 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
793 { 0, 0, 6, 0 },
794 { 1, 1, 0, 0 },
795
796 { 125, -130, 0, TAB (PCINDEX, SHORT) },
797 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
798 { 0, 0, 4, 0 },
799 { 1, 1, 0, 0 },
800
801 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
802 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
803 { 0, 0, 4, 0 },
804 { 1, 1, 0, 0 },
805
806 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
807 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
808 { 0, 0, 10, 0 },
809 { 1, 1, 0, 0 },
810 };
811
812 /* These are the machine dependent pseudo-ops. These are included so
813 the assembler can work on the output from the SUN C compiler, which
814 generates these. */
815
816 /* This table describes all the machine specific pseudo-ops the assembler
817 has to support. The fields are:
818 pseudo-op name without dot
819 function to call to execute this pseudo-op
820 Integer arg to pass to the function. */
821 const pseudo_typeS md_pseudo_table[] =
822 {
823 {"data1", s_data1, 0},
824 {"data2", s_data2, 0},
825 {"bss", s_bss, 0},
826 {"even", s_even, 0},
827 {"skip", s_space, 0},
828 {"proc", s_proc, 0},
829 #if defined (TE_SUN3) || defined (OBJ_ELF)
830 {"align", s_align_bytes, 0},
831 #endif
832 #ifdef OBJ_ELF
833 {"swbeg", s_ignore, 0},
834 #endif
835 {"extend", float_cons, 'x'},
836 {"ldouble", float_cons, 'x'},
837
838 {"arch", s_m68k_arch, 0},
839 {"cpu", s_m68k_cpu, 0},
840
841 /* The following pseudo-ops are supported for MRI compatibility. */
842 {"chip", s_chip, 0},
843 {"comline", s_space, 1},
844 {"fopt", s_fopt, 0},
845 {"mask2", s_ignore, 0},
846 {"opt", s_opt, 0},
847 {"reg", s_reg, 0},
848 {"restore", s_restore, 0},
849 {"save", s_save, 0},
850
851 {"if", s_mri_if, 0},
852 {"if.b", s_mri_if, 'b'},
853 {"if.w", s_mri_if, 'w'},
854 {"if.l", s_mri_if, 'l'},
855 {"else", s_mri_else, 0},
856 {"else.s", s_mri_else, 's'},
857 {"else.l", s_mri_else, 'l'},
858 {"endi", s_mri_endi, 0},
859 {"break", s_mri_break, 0},
860 {"break.s", s_mri_break, 's'},
861 {"break.l", s_mri_break, 'l'},
862 {"next", s_mri_next, 0},
863 {"next.s", s_mri_next, 's'},
864 {"next.l", s_mri_next, 'l'},
865 {"for", s_mri_for, 0},
866 {"for.b", s_mri_for, 'b'},
867 {"for.w", s_mri_for, 'w'},
868 {"for.l", s_mri_for, 'l'},
869 {"endf", s_mri_endf, 0},
870 {"repeat", s_mri_repeat, 0},
871 {"until", s_mri_until, 0},
872 {"until.b", s_mri_until, 'b'},
873 {"until.w", s_mri_until, 'w'},
874 {"until.l", s_mri_until, 'l'},
875 {"while", s_mri_while, 0},
876 {"while.b", s_mri_while, 'b'},
877 {"while.w", s_mri_while, 'w'},
878 {"while.l", s_mri_while, 'l'},
879 {"endw", s_mri_endw, 0},
880
881 {0, 0, 0}
882 };
883
884 /* The mote pseudo ops are put into the opcode table, since they
885 don't start with a . they look like opcodes to gas. */
886
887 const pseudo_typeS mote_pseudo_table[] =
888 {
889
890 {"dcl", cons, 4},
891 {"dc", cons, 2},
892 {"dcw", cons, 2},
893 {"dcb", cons, 1},
894
895 {"dsl", s_space, 4},
896 {"ds", s_space, 2},
897 {"dsw", s_space, 2},
898 {"dsb", s_space, 1},
899
900 {"xdef", s_globl, 0},
901 #ifdef OBJ_ELF
902 {"align", s_align_bytes, 0},
903 #else
904 {"align", s_align_ptwo, 0},
905 #endif
906 #ifdef M68KCOFF
907 {"sect", obj_coff_section, 0},
908 {"section", obj_coff_section, 0},
909 #endif
910 {0, 0, 0}
911 };
912
913 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
914 gives identical results to a 32-bit host. */
915 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
916 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
917
918 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
919 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
920 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
921 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
922
923 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
924 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
925 #define islong(x) (1)
926
927 static char notend_table[256];
928 static char alt_notend_table[256];
929 #define notend(s) \
930 (! (notend_table[(unsigned char) *s] \
931 || (*s == ':' \
932 && alt_notend_table[(unsigned char) s[1]])))
933
934 #ifdef OBJ_ELF
935
936 /* Return zero if the reference to SYMBOL from within the same segment may
937 be relaxed. */
938
939 /* On an ELF system, we can't relax an externally visible symbol,
940 because it may be overridden by a shared library. However, if
941 TARGET_OS is "elf", then we presume that we are assembling for an
942 embedded system, in which case we don't have to worry about shared
943 libraries, and we can relax any external sym. */
944
945 #define relaxable_symbol(symbol) \
946 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
947 || S_IS_WEAK (symbol)))
948
949 /* Compute the relocation code for a fixup of SIZE bytes, using pc
950 relative relocation if PCREL is non-zero. PIC says whether a special
951 pic relocation was requested. */
952
953 static bfd_reloc_code_real_type
954 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
955 {
956 switch (pic)
957 {
958 case pic_got_pcrel:
959 switch (size)
960 {
961 case 1:
962 return BFD_RELOC_8_GOT_PCREL;
963 case 2:
964 return BFD_RELOC_16_GOT_PCREL;
965 case 4:
966 return BFD_RELOC_32_GOT_PCREL;
967 }
968 break;
969
970 case pic_got_off:
971 switch (size)
972 {
973 case 1:
974 return BFD_RELOC_8_GOTOFF;
975 case 2:
976 return BFD_RELOC_16_GOTOFF;
977 case 4:
978 return BFD_RELOC_32_GOTOFF;
979 }
980 break;
981
982 case pic_plt_pcrel:
983 switch (size)
984 {
985 case 1:
986 return BFD_RELOC_8_PLT_PCREL;
987 case 2:
988 return BFD_RELOC_16_PLT_PCREL;
989 case 4:
990 return BFD_RELOC_32_PLT_PCREL;
991 }
992 break;
993
994 case pic_plt_off:
995 switch (size)
996 {
997 case 1:
998 return BFD_RELOC_8_PLTOFF;
999 case 2:
1000 return BFD_RELOC_16_PLTOFF;
1001 case 4:
1002 return BFD_RELOC_32_PLTOFF;
1003 }
1004 break;
1005
1006 case pic_none:
1007 if (pcrel)
1008 {
1009 switch (size)
1010 {
1011 case 1:
1012 return BFD_RELOC_8_PCREL;
1013 case 2:
1014 return BFD_RELOC_16_PCREL;
1015 case 4:
1016 return BFD_RELOC_32_PCREL;
1017 }
1018 }
1019 else
1020 {
1021 switch (size)
1022 {
1023 case 1:
1024 return BFD_RELOC_8;
1025 case 2:
1026 return BFD_RELOC_16;
1027 case 4:
1028 return BFD_RELOC_32;
1029 }
1030 }
1031 }
1032
1033 if (pcrel)
1034 {
1035 if (pic == pic_none)
1036 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1037 else
1038 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1039 }
1040 else
1041 {
1042 if (pic == pic_none)
1043 as_bad (_("Can not do %d byte relocation"), size);
1044 else
1045 as_bad (_("Can not do %d byte pic relocation"), size);
1046 }
1047
1048 return BFD_RELOC_NONE;
1049 }
1050
1051 /* Here we decide which fixups can be adjusted to make them relative
1052 to the beginning of the section instead of the symbol. Basically
1053 we need to make sure that the dynamic relocations are done
1054 correctly, so in some cases we force the original symbol to be
1055 used. */
1056 int
1057 tc_m68k_fix_adjustable (fixS *fixP)
1058 {
1059 /* Adjust_reloc_syms doesn't know about the GOT. */
1060 switch (fixP->fx_r_type)
1061 {
1062 case BFD_RELOC_8_GOT_PCREL:
1063 case BFD_RELOC_16_GOT_PCREL:
1064 case BFD_RELOC_32_GOT_PCREL:
1065 case BFD_RELOC_8_GOTOFF:
1066 case BFD_RELOC_16_GOTOFF:
1067 case BFD_RELOC_32_GOTOFF:
1068 case BFD_RELOC_8_PLT_PCREL:
1069 case BFD_RELOC_16_PLT_PCREL:
1070 case BFD_RELOC_32_PLT_PCREL:
1071 case BFD_RELOC_8_PLTOFF:
1072 case BFD_RELOC_16_PLTOFF:
1073 case BFD_RELOC_32_PLTOFF:
1074 return 0;
1075
1076 case BFD_RELOC_VTABLE_INHERIT:
1077 case BFD_RELOC_VTABLE_ENTRY:
1078 return 0;
1079
1080 default:
1081 return 1;
1082 }
1083 }
1084
1085 #else /* !OBJ_ELF */
1086
1087 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1088
1089 /* PR gas/3041 Weak symbols are not relaxable
1090 because they must be treated as extern. */
1091 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1092
1093 #endif /* OBJ_ELF */
1094
1095 arelent *
1096 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1097 {
1098 arelent *reloc;
1099 bfd_reloc_code_real_type code;
1100
1101 /* If the tcbit is set, then this was a fixup of a negative value
1102 that was never resolved. We do not have a reloc to handle this,
1103 so just return. We assume that other code will have detected this
1104 situation and produced a helpful error message, so we just tell the
1105 user that the reloc cannot be produced. */
1106 if (fixp->fx_tcbit)
1107 {
1108 if (fixp->fx_addsy)
1109 as_bad_where (fixp->fx_file, fixp->fx_line,
1110 _("Unable to produce reloc against symbol '%s'"),
1111 S_GET_NAME (fixp->fx_addsy));
1112 return NULL;
1113 }
1114
1115 if (fixp->fx_r_type != BFD_RELOC_NONE)
1116 {
1117 code = fixp->fx_r_type;
1118
1119 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1120 that fixup_segment converted a non-PC relative reloc into a
1121 PC relative reloc. In such a case, we need to convert the
1122 reloc code. */
1123 if (fixp->fx_pcrel)
1124 {
1125 switch (code)
1126 {
1127 case BFD_RELOC_8:
1128 code = BFD_RELOC_8_PCREL;
1129 break;
1130 case BFD_RELOC_16:
1131 code = BFD_RELOC_16_PCREL;
1132 break;
1133 case BFD_RELOC_32:
1134 code = BFD_RELOC_32_PCREL;
1135 break;
1136 case BFD_RELOC_8_PCREL:
1137 case BFD_RELOC_16_PCREL:
1138 case BFD_RELOC_32_PCREL:
1139 case BFD_RELOC_8_GOT_PCREL:
1140 case BFD_RELOC_16_GOT_PCREL:
1141 case BFD_RELOC_32_GOT_PCREL:
1142 case BFD_RELOC_8_GOTOFF:
1143 case BFD_RELOC_16_GOTOFF:
1144 case BFD_RELOC_32_GOTOFF:
1145 case BFD_RELOC_8_PLT_PCREL:
1146 case BFD_RELOC_16_PLT_PCREL:
1147 case BFD_RELOC_32_PLT_PCREL:
1148 case BFD_RELOC_8_PLTOFF:
1149 case BFD_RELOC_16_PLTOFF:
1150 case BFD_RELOC_32_PLTOFF:
1151 break;
1152 default:
1153 as_bad_where (fixp->fx_file, fixp->fx_line,
1154 _("Cannot make %s relocation PC relative"),
1155 bfd_get_reloc_code_name (code));
1156 }
1157 }
1158 }
1159 else
1160 {
1161 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1162 switch (F (fixp->fx_size, fixp->fx_pcrel))
1163 {
1164 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1165 MAP (1, 0, BFD_RELOC_8);
1166 MAP (2, 0, BFD_RELOC_16);
1167 MAP (4, 0, BFD_RELOC_32);
1168 MAP (1, 1, BFD_RELOC_8_PCREL);
1169 MAP (2, 1, BFD_RELOC_16_PCREL);
1170 MAP (4, 1, BFD_RELOC_32_PCREL);
1171 default:
1172 abort ();
1173 }
1174 }
1175 #undef F
1176 #undef MAP
1177
1178 reloc = (arelent *) xmalloc (sizeof (arelent));
1179 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1180 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1181 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1182 #ifndef OBJ_ELF
1183 if (fixp->fx_pcrel)
1184 reloc->addend = fixp->fx_addnumber;
1185 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1186 && fixp->fx_addsy
1187 && S_IS_WEAK (fixp->fx_addsy)
1188 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1189 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1190 to put the symbol offset into frags referencing a weak symbol. */
1191 reloc->addend = fixp->fx_addnumber
1192 - (S_GET_VALUE (fixp->fx_addsy) * 2);
1193 else
1194 reloc->addend = 0;
1195 #else
1196 if (!fixp->fx_pcrel)
1197 reloc->addend = fixp->fx_addnumber;
1198 else
1199 reloc->addend = (section->vma
1200 /* Explicit sign extension in case char is
1201 unsigned. */
1202 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1203 + fixp->fx_addnumber
1204 + md_pcrel_from (fixp));
1205 #endif
1206
1207 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1208 assert (reloc->howto != 0);
1209
1210 return reloc;
1211 }
1212
1213 /* Handle of the OPCODE hash table. NULL means any use before
1214 m68k_ip_begin() will crash. */
1215 static struct hash_control *op_hash;
1216 \f
1217 /* Assemble an m68k instruction. */
1218
1219 static void
1220 m68k_ip (char *instring)
1221 {
1222 register char *p;
1223 register struct m68k_op *opP;
1224 register const struct m68k_incant *opcode;
1225 register const char *s;
1226 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1227 char *pdot, *pdotmove;
1228 enum m68k_size siz1, siz2;
1229 char c;
1230 int losing;
1231 int opsfound;
1232 struct m68k_op operands_backup[6];
1233 LITTLENUM_TYPE words[6];
1234 LITTLENUM_TYPE *wordp;
1235 unsigned long ok_arch = 0;
1236
1237 if (*instring == ' ')
1238 instring++; /* Skip leading whitespace. */
1239
1240 /* Scan up to end of operation-code, which MUST end in end-of-string
1241 or exactly 1 space. */
1242 pdot = 0;
1243 for (p = instring; *p != '\0'; p++)
1244 {
1245 if (*p == ' ')
1246 break;
1247 if (*p == '.')
1248 pdot = p;
1249 }
1250
1251 if (p == instring)
1252 {
1253 the_ins.error = _("No operator");
1254 return;
1255 }
1256
1257 /* p now points to the end of the opcode name, probably whitespace.
1258 Make sure the name is null terminated by clobbering the
1259 whitespace, look it up in the hash table, then fix it back.
1260 Remove a dot, first, since the opcode tables have none. */
1261 if (pdot != NULL)
1262 {
1263 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1264 *pdotmove = pdotmove[1];
1265 p--;
1266 }
1267
1268 c = *p;
1269 *p = '\0';
1270 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1271 *p = c;
1272
1273 if (pdot != NULL)
1274 {
1275 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1276 *pdotmove = pdotmove[-1];
1277 *pdot = '.';
1278 ++p;
1279 }
1280
1281 if (opcode == NULL)
1282 {
1283 the_ins.error = _("Unknown operator");
1284 return;
1285 }
1286
1287 /* Found a legitimate opcode, start matching operands. */
1288 while (*p == ' ')
1289 ++p;
1290
1291 if (opcode->m_operands == 0)
1292 {
1293 char *old = input_line_pointer;
1294 *old = '\n';
1295 input_line_pointer = p;
1296 /* Ahh - it's a motorola style psuedo op. */
1297 mote_pseudo_table[opcode->m_opnum].poc_handler
1298 (mote_pseudo_table[opcode->m_opnum].poc_val);
1299 input_line_pointer = old;
1300 *old = 0;
1301
1302 return;
1303 }
1304
1305 if (flag_mri && opcode->m_opnum == 0)
1306 {
1307 /* In MRI mode, random garbage is allowed after an instruction
1308 which accepts no operands. */
1309 the_ins.args = opcode->m_operands;
1310 the_ins.numargs = opcode->m_opnum;
1311 the_ins.numo = opcode->m_codenum;
1312 the_ins.opcode[0] = getone (opcode);
1313 the_ins.opcode[1] = gettwo (opcode);
1314 return;
1315 }
1316
1317 for (opP = &the_ins.operands[0]; *p; opP++)
1318 {
1319 p = crack_operand (p, opP);
1320
1321 if (opP->error)
1322 {
1323 the_ins.error = opP->error;
1324 return;
1325 }
1326 }
1327
1328 opsfound = opP - &the_ins.operands[0];
1329
1330 /* This ugly hack is to support the floating pt opcodes in their
1331 standard form. Essentially, we fake a first enty of type COP#1 */
1332 if (opcode->m_operands[0] == 'I')
1333 {
1334 int n;
1335
1336 for (n = opsfound; n > 0; --n)
1337 the_ins.operands[n] = the_ins.operands[n - 1];
1338
1339 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1340 the_ins.operands[0].mode = CONTROL;
1341 the_ins.operands[0].reg = m68k_float_copnum;
1342 opsfound++;
1343 }
1344
1345 /* We've got the operands. Find an opcode that'll accept them. */
1346 for (losing = 0;;)
1347 {
1348 /* If we didn't get the right number of ops, or we have no
1349 common model with this pattern then reject this pattern. */
1350
1351 ok_arch |= opcode->m_arch;
1352 if (opsfound != opcode->m_opnum
1353 || ((opcode->m_arch & current_architecture) == 0))
1354 ++losing;
1355 else
1356 {
1357 int i;
1358
1359 /* Make a copy of the operands of this insn so that
1360 we can modify them safely, should we want to. */
1361 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1362 for (i = 0; i < opsfound; i++)
1363 operands_backup[i] = the_ins.operands[i];
1364
1365 for (s = opcode->m_operands, opP = &operands_backup[0];
1366 *s && !losing;
1367 s += 2, opP++)
1368 {
1369 /* Warning: this switch is huge! */
1370 /* I've tried to organize the cases into this order:
1371 non-alpha first, then alpha by letter. Lower-case
1372 goes directly before uppercase counterpart. */
1373 /* Code with multiple case ...: gets sorted by the lowest
1374 case ... it belongs to. I hope this makes sense. */
1375 switch (*s)
1376 {
1377 case '!':
1378 switch (opP->mode)
1379 {
1380 case IMMED:
1381 case DREG:
1382 case AREG:
1383 case FPREG:
1384 case CONTROL:
1385 case AINC:
1386 case ADEC:
1387 case REGLST:
1388 losing++;
1389 break;
1390 default:
1391 break;
1392 }
1393 break;
1394
1395 case '<':
1396 switch (opP->mode)
1397 {
1398 case DREG:
1399 case AREG:
1400 case FPREG:
1401 case CONTROL:
1402 case IMMED:
1403 case ADEC:
1404 case REGLST:
1405 losing++;
1406 break;
1407 default:
1408 break;
1409 }
1410 break;
1411
1412 case '>':
1413 switch (opP->mode)
1414 {
1415 case DREG:
1416 case AREG:
1417 case FPREG:
1418 case CONTROL:
1419 case IMMED:
1420 case AINC:
1421 case REGLST:
1422 losing++;
1423 break;
1424 case ABSL:
1425 break;
1426 default:
1427 if (opP->reg == PC
1428 || opP->reg == ZPC)
1429 losing++;
1430 break;
1431 }
1432 break;
1433
1434 case 'm':
1435 switch (opP->mode)
1436 {
1437 case DREG:
1438 case AREG:
1439 case AINDR:
1440 case AINC:
1441 case ADEC:
1442 break;
1443 default:
1444 losing++;
1445 }
1446 break;
1447
1448 case 'n':
1449 switch (opP->mode)
1450 {
1451 case DISP:
1452 break;
1453 default:
1454 losing++;
1455 }
1456 break;
1457
1458 case 'o':
1459 switch (opP->mode)
1460 {
1461 case BASE:
1462 case ABSL:
1463 case IMMED:
1464 break;
1465 default:
1466 losing++;
1467 }
1468 break;
1469
1470 case 'p':
1471 switch (opP->mode)
1472 {
1473 case DREG:
1474 case AREG:
1475 case AINDR:
1476 case AINC:
1477 case ADEC:
1478 break;
1479 case DISP:
1480 if (opP->reg == PC || opP->reg == ZPC)
1481 losing++;
1482 break;
1483 default:
1484 losing++;
1485 }
1486 break;
1487
1488 case 'q':
1489 switch (opP->mode)
1490 {
1491 case DREG:
1492 case AINDR:
1493 case AINC:
1494 case ADEC:
1495 break;
1496 case DISP:
1497 if (opP->reg == PC || opP->reg == ZPC)
1498 losing++;
1499 break;
1500 default:
1501 losing++;
1502 break;
1503 }
1504 break;
1505
1506 case 'v':
1507 switch (opP->mode)
1508 {
1509 case DREG:
1510 case AINDR:
1511 case AINC:
1512 case ADEC:
1513 case ABSL:
1514 break;
1515 case DISP:
1516 if (opP->reg == PC || opP->reg == ZPC)
1517 losing++;
1518 break;
1519 default:
1520 losing++;
1521 break;
1522 }
1523 break;
1524
1525 case '#':
1526 if (opP->mode != IMMED)
1527 losing++;
1528 else if (s[1] == 'b'
1529 && ! isvar (&opP->disp)
1530 && (opP->disp.exp.X_op != O_constant
1531 || ! isbyte (opP->disp.exp.X_add_number)))
1532 losing++;
1533 else if (s[1] == 'B'
1534 && ! isvar (&opP->disp)
1535 && (opP->disp.exp.X_op != O_constant
1536 || ! issbyte (opP->disp.exp.X_add_number)))
1537 losing++;
1538 else if (s[1] == 'w'
1539 && ! isvar (&opP->disp)
1540 && (opP->disp.exp.X_op != O_constant
1541 || ! isword (opP->disp.exp.X_add_number)))
1542 losing++;
1543 else if (s[1] == 'W'
1544 && ! isvar (&opP->disp)
1545 && (opP->disp.exp.X_op != O_constant
1546 || ! issword (opP->disp.exp.X_add_number)))
1547 losing++;
1548 break;
1549
1550 case '^':
1551 case 'T':
1552 if (opP->mode != IMMED)
1553 losing++;
1554 break;
1555
1556 case '$':
1557 if (opP->mode == AREG
1558 || opP->mode == CONTROL
1559 || opP->mode == FPREG
1560 || opP->mode == IMMED
1561 || opP->mode == REGLST
1562 || (opP->mode != ABSL
1563 && (opP->reg == PC
1564 || opP->reg == ZPC)))
1565 losing++;
1566 break;
1567
1568 case '%':
1569 if (opP->mode == CONTROL
1570 || opP->mode == FPREG
1571 || opP->mode == REGLST
1572 || opP->mode == IMMED
1573 || (opP->mode != ABSL
1574 && (opP->reg == PC
1575 || opP->reg == ZPC)))
1576 losing++;
1577 break;
1578
1579 case '&':
1580 switch (opP->mode)
1581 {
1582 case DREG:
1583 case AREG:
1584 case FPREG:
1585 case CONTROL:
1586 case IMMED:
1587 case AINC:
1588 case ADEC:
1589 case REGLST:
1590 losing++;
1591 break;
1592 case ABSL:
1593 break;
1594 default:
1595 if (opP->reg == PC
1596 || opP->reg == ZPC)
1597 losing++;
1598 break;
1599 }
1600 break;
1601
1602 case '*':
1603 if (opP->mode == CONTROL
1604 || opP->mode == FPREG
1605 || opP->mode == REGLST)
1606 losing++;
1607 break;
1608
1609 case '+':
1610 if (opP->mode != AINC)
1611 losing++;
1612 break;
1613
1614 case '-':
1615 if (opP->mode != ADEC)
1616 losing++;
1617 break;
1618
1619 case '/':
1620 switch (opP->mode)
1621 {
1622 case AREG:
1623 case CONTROL:
1624 case FPREG:
1625 case AINC:
1626 case ADEC:
1627 case IMMED:
1628 case REGLST:
1629 losing++;
1630 break;
1631 default:
1632 break;
1633 }
1634 break;
1635
1636 case ';':
1637 switch (opP->mode)
1638 {
1639 case AREG:
1640 case CONTROL:
1641 case FPREG:
1642 case REGLST:
1643 losing++;
1644 break;
1645 default:
1646 break;
1647 }
1648 break;
1649
1650 case '?':
1651 switch (opP->mode)
1652 {
1653 case AREG:
1654 case CONTROL:
1655 case FPREG:
1656 case AINC:
1657 case ADEC:
1658 case IMMED:
1659 case REGLST:
1660 losing++;
1661 break;
1662 case ABSL:
1663 break;
1664 default:
1665 if (opP->reg == PC || opP->reg == ZPC)
1666 losing++;
1667 break;
1668 }
1669 break;
1670
1671 case '@':
1672 switch (opP->mode)
1673 {
1674 case AREG:
1675 case CONTROL:
1676 case FPREG:
1677 case IMMED:
1678 case REGLST:
1679 losing++;
1680 break;
1681 default:
1682 break;
1683 }
1684 break;
1685
1686 case '~': /* For now! (JF FOO is this right?) */
1687 switch (opP->mode)
1688 {
1689 case DREG:
1690 case AREG:
1691 case CONTROL:
1692 case FPREG:
1693 case IMMED:
1694 case REGLST:
1695 losing++;
1696 break;
1697 case ABSL:
1698 break;
1699 default:
1700 if (opP->reg == PC
1701 || opP->reg == ZPC)
1702 losing++;
1703 break;
1704 }
1705 break;
1706
1707 case '3':
1708 if (opP->mode != CONTROL
1709 || (opP->reg != TT0 && opP->reg != TT1))
1710 losing++;
1711 break;
1712
1713 case 'A':
1714 if (opP->mode != AREG)
1715 losing++;
1716 break;
1717
1718 case 'a':
1719 if (opP->mode != AINDR)
1720 ++losing;
1721 break;
1722
1723 case '4':
1724 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1725 && (opP->mode != DISP
1726 || opP->reg < ADDR0
1727 || opP->reg > ADDR7))
1728 ++losing;
1729 break;
1730
1731 case 'B': /* FOO */
1732 if (opP->mode != ABSL
1733 || (flag_long_jumps
1734 && strncmp (instring, "jbsr", 4) == 0))
1735 losing++;
1736 break;
1737
1738 case 'b':
1739 switch (opP->mode)
1740 {
1741 case IMMED:
1742 case ABSL:
1743 case AREG:
1744 case FPREG:
1745 case CONTROL:
1746 case POST:
1747 case PRE:
1748 case REGLST:
1749 losing++;
1750 break;
1751 default:
1752 break;
1753 }
1754 break;
1755
1756 case 'C':
1757 if (opP->mode != CONTROL || opP->reg != CCR)
1758 losing++;
1759 break;
1760
1761 case 'd':
1762 if (opP->mode != DISP
1763 || opP->reg < ADDR0
1764 || opP->reg > ADDR7)
1765 losing++;
1766 break;
1767
1768 case 'D':
1769 if (opP->mode != DREG)
1770 losing++;
1771 break;
1772
1773 case 'E':
1774 if (opP->reg != ACC)
1775 losing++;
1776 break;
1777
1778 case 'e':
1779 if (opP->reg != ACC && opP->reg != ACC1
1780 && opP->reg != ACC2 && opP->reg != ACC3)
1781 losing++;
1782 break;
1783
1784 case 'F':
1785 if (opP->mode != FPREG)
1786 losing++;
1787 break;
1788
1789 case 'G':
1790 if (opP->reg != MACSR)
1791 losing++;
1792 break;
1793
1794 case 'g':
1795 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1796 losing++;
1797 break;
1798
1799 case 'H':
1800 if (opP->reg != MASK)
1801 losing++;
1802 break;
1803
1804 case 'I':
1805 if (opP->mode != CONTROL
1806 || opP->reg < COP0
1807 || opP->reg > COP7)
1808 losing++;
1809 break;
1810
1811 case 'i':
1812 if (opP->mode != LSH && opP->mode != RSH)
1813 losing++;
1814 break;
1815
1816 case 'J':
1817 if (opP->mode != CONTROL
1818 || opP->reg < USP
1819 || opP->reg > last_movec_reg
1820 || !control_regs)
1821 losing++;
1822 else
1823 {
1824 const enum m68k_register *rp;
1825
1826 for (rp = control_regs; *rp; rp++)
1827 {
1828 if (*rp == opP->reg)
1829 break;
1830 /* In most CPUs RAMBAR refers to control reg
1831 c05 (RAMBAR1), but a few CPUs have it
1832 refer to c04 (RAMBAR0). */
1833 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1834 {
1835 opP->reg = RAMBAR_ALT;
1836 break;
1837 }
1838 }
1839 if (*rp == 0)
1840 losing++;
1841 }
1842 break;
1843
1844 case 'k':
1845 if (opP->mode != IMMED)
1846 losing++;
1847 break;
1848
1849 case 'l':
1850 case 'L':
1851 if (opP->mode == DREG
1852 || opP->mode == AREG
1853 || opP->mode == FPREG)
1854 {
1855 if (s[1] == '8')
1856 losing++;
1857 else
1858 {
1859 switch (opP->mode)
1860 {
1861 case DREG:
1862 opP->mask = 1 << (opP->reg - DATA0);
1863 break;
1864 case AREG:
1865 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1866 break;
1867 case FPREG:
1868 opP->mask = 1 << (opP->reg - FP0 + 16);
1869 break;
1870 default:
1871 abort ();
1872 }
1873 opP->mode = REGLST;
1874 }
1875 }
1876 else if (opP->mode == CONTROL)
1877 {
1878 if (s[1] != '8')
1879 losing++;
1880 else
1881 {
1882 switch (opP->reg)
1883 {
1884 case FPI:
1885 opP->mask = 1 << 24;
1886 break;
1887 case FPS:
1888 opP->mask = 1 << 25;
1889 break;
1890 case FPC:
1891 opP->mask = 1 << 26;
1892 break;
1893 default:
1894 losing++;
1895 break;
1896 }
1897 opP->mode = REGLST;
1898 }
1899 }
1900 else if (opP->mode != REGLST)
1901 losing++;
1902 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1903 losing++;
1904 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1905 losing++;
1906 break;
1907
1908 case 'M':
1909 if (opP->mode != IMMED)
1910 losing++;
1911 else if (opP->disp.exp.X_op != O_constant
1912 || ! issbyte (opP->disp.exp.X_add_number))
1913 losing++;
1914 else if (! m68k_quick
1915 && instring[3] != 'q'
1916 && instring[4] != 'q')
1917 losing++;
1918 break;
1919
1920 case 'O':
1921 if (opP->mode != DREG
1922 && opP->mode != IMMED
1923 && opP->mode != ABSL)
1924 losing++;
1925 break;
1926
1927 case 'Q':
1928 if (opP->mode != IMMED)
1929 losing++;
1930 else if (opP->disp.exp.X_op != O_constant
1931 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1932 losing++;
1933 else if (! m68k_quick
1934 && (strncmp (instring, "add", 3) == 0
1935 || strncmp (instring, "sub", 3) == 0)
1936 && instring[3] != 'q')
1937 losing++;
1938 break;
1939
1940 case 'R':
1941 if (opP->mode != DREG && opP->mode != AREG)
1942 losing++;
1943 break;
1944
1945 case 'r':
1946 if (opP->mode != AINDR
1947 && (opP->mode != BASE
1948 || (opP->reg != 0
1949 && opP->reg != ZADDR0)
1950 || opP->disp.exp.X_op != O_absent
1951 || ((opP->index.reg < DATA0
1952 || opP->index.reg > DATA7)
1953 && (opP->index.reg < ADDR0
1954 || opP->index.reg > ADDR7))
1955 || opP->index.size != SIZE_UNSPEC
1956 || opP->index.scale != 1))
1957 losing++;
1958 break;
1959
1960 case 's':
1961 if (opP->mode != CONTROL
1962 || ! (opP->reg == FPI
1963 || opP->reg == FPS
1964 || opP->reg == FPC))
1965 losing++;
1966 break;
1967
1968 case 'S':
1969 if (opP->mode != CONTROL || opP->reg != SR)
1970 losing++;
1971 break;
1972
1973 case 't':
1974 if (opP->mode != IMMED)
1975 losing++;
1976 else if (opP->disp.exp.X_op != O_constant
1977 || TRUNC (opP->disp.exp.X_add_number) > 7)
1978 losing++;
1979 break;
1980
1981 case 'U':
1982 if (opP->mode != CONTROL || opP->reg != USP)
1983 losing++;
1984 break;
1985
1986 case 'x':
1987 if (opP->mode != IMMED)
1988 losing++;
1989 else if (opP->disp.exp.X_op != O_constant
1990 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1991 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1992 losing++;
1993 break;
1994
1995 case 'j':
1996 if (opP->mode != IMMED)
1997 losing++;
1998 else if (opP->disp.exp.X_op != O_constant
1999 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2000 losing++;
2001 break;
2002
2003 case 'K':
2004 if (opP->mode != IMMED)
2005 losing++;
2006 else if (opP->disp.exp.X_op != O_constant
2007 || TRUNC (opP->disp.exp.X_add_number) > 511)
2008 losing++;
2009 break;
2010
2011 /* JF these are out of order. We could put them
2012 in order if we were willing to put up with
2013 bunches of #ifdef m68851s in the code.
2014
2015 Don't forget that you need these operands
2016 to use 68030 MMU instructions. */
2017 #ifndef NO_68851
2018 /* Memory addressing mode used by pflushr. */
2019 case '|':
2020 if (opP->mode == CONTROL
2021 || opP->mode == FPREG
2022 || opP->mode == DREG
2023 || opP->mode == AREG
2024 || opP->mode == REGLST)
2025 losing++;
2026 /* We should accept immediate operands, but they
2027 supposedly have to be quad word, and we don't
2028 handle that. I would like to see what a Motorola
2029 assembler does before doing something here. */
2030 if (opP->mode == IMMED)
2031 losing++;
2032 break;
2033
2034 case 'f':
2035 if (opP->mode != CONTROL
2036 || (opP->reg != SFC && opP->reg != DFC))
2037 losing++;
2038 break;
2039
2040 case '0':
2041 if (opP->mode != CONTROL || opP->reg != TC)
2042 losing++;
2043 break;
2044
2045 case '1':
2046 if (opP->mode != CONTROL || opP->reg != AC)
2047 losing++;
2048 break;
2049
2050 case '2':
2051 if (opP->mode != CONTROL
2052 || (opP->reg != CAL
2053 && opP->reg != VAL
2054 && opP->reg != SCC))
2055 losing++;
2056 break;
2057
2058 case 'V':
2059 if (opP->mode != CONTROL
2060 || opP->reg != VAL)
2061 losing++;
2062 break;
2063
2064 case 'W':
2065 if (opP->mode != CONTROL
2066 || (opP->reg != DRP
2067 && opP->reg != SRP
2068 && opP->reg != CRP))
2069 losing++;
2070 break;
2071
2072 case 'w':
2073 switch (opP->mode)
2074 {
2075 case IMMED:
2076 case ABSL:
2077 case AREG:
2078 case DREG:
2079 case FPREG:
2080 case CONTROL:
2081 case POST:
2082 case PRE:
2083 case REGLST:
2084 losing++;
2085 break;
2086 default:
2087 break;
2088 }
2089 break;
2090
2091 case 'X':
2092 if (opP->mode != CONTROL
2093 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2094 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2095 losing++;
2096 break;
2097
2098 case 'Y':
2099 if (opP->mode != CONTROL || opP->reg != PSR)
2100 losing++;
2101 break;
2102
2103 case 'Z':
2104 if (opP->mode != CONTROL || opP->reg != PCSR)
2105 losing++;
2106 break;
2107 #endif
2108 case 'c':
2109 if (opP->mode != CONTROL
2110 || (opP->reg != NC
2111 && opP->reg != IC
2112 && opP->reg != DC
2113 && opP->reg != BC))
2114 losing++;
2115 break;
2116
2117 case '_':
2118 if (opP->mode != ABSL)
2119 ++losing;
2120 break;
2121
2122 case 'u':
2123 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2124 losing++;
2125 /* FIXME: kludge instead of fixing parser:
2126 upper/lower registers are *not* CONTROL
2127 registers, but ordinary ones. */
2128 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2129 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2130 opP->mode = DREG;
2131 else
2132 opP->mode = AREG;
2133 break;
2134
2135 case 'y':
2136 if (!(opP->mode == AINDR
2137 || (opP->mode == DISP
2138 && !(opP->reg == PC || opP->reg == ZPC))))
2139 losing++;
2140 break;
2141
2142 case 'z':
2143 if (!(opP->mode == AINDR || opP->mode == DISP))
2144 losing++;
2145 break;
2146
2147 default:
2148 abort ();
2149 }
2150
2151 if (losing)
2152 break;
2153 }
2154
2155 /* Since we have found the correct instruction, copy
2156 in the modifications that we may have made. */
2157 if (!losing)
2158 for (i = 0; i < opsfound; i++)
2159 the_ins.operands[i] = operands_backup[i];
2160 }
2161
2162 if (!losing)
2163 break;
2164
2165 opcode = opcode->m_next;
2166
2167 if (!opcode)
2168 {
2169 if (ok_arch
2170 && !(ok_arch & current_architecture))
2171 {
2172 const struct m68k_cpu *cpu;
2173 int any = 0;
2174 size_t space = 400;
2175 char *buf = xmalloc (space + 1);
2176 size_t len;
2177 int paren = 1;
2178
2179 the_ins.error = buf;
2180 /* Make sure there's a NUL at the end of the buffer -- strncpy
2181 won't write one when it runs out of buffer */
2182 buf[space] = 0;
2183 #define APPEND(STRING) \
2184 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2185
2186 APPEND (_("invalid instruction for this architecture; needs "));
2187 switch (ok_arch)
2188 {
2189 case mcfisa_a:
2190 APPEND (_("ColdFire ISA_A"));
2191 break;
2192 case mcfhwdiv:
2193 APPEND (_("ColdFire hardware divide"));
2194 break;
2195 case mcfisa_aa:
2196 APPEND (_("ColdFire ISA_A+"));
2197 break;
2198 case mcfisa_b:
2199 APPEND (_("ColdFire ISA_B"));
2200 break;
2201 case mcfisa_c:
2202 APPEND (_("ColdFire ISA_C"));
2203 break;
2204 case cfloat:
2205 APPEND (_("ColdFire fpu"));
2206 break;
2207 case mfloat:
2208 APPEND (_("M68K fpu"));
2209 break;
2210 case mmmu:
2211 APPEND (_("M68K mmu"));
2212 break;
2213 case m68020up:
2214 APPEND (_("68020 or higher"));
2215 break;
2216 case m68000up:
2217 APPEND (_("68000 or higher"));
2218 break;
2219 case m68010up:
2220 APPEND (_("68010 or higher"));
2221 break;
2222 default:
2223 paren = 0;
2224 }
2225 if (paren)
2226 APPEND (" (");
2227
2228 for (cpu = m68k_cpus; cpu->name; cpu++)
2229 if (!cpu->alias && (cpu->arch & ok_arch))
2230 {
2231 const struct m68k_cpu *alias;
2232 int seen_master = 0;
2233
2234 if (any)
2235 APPEND (", ");
2236 any = 0;
2237 APPEND (cpu->name);
2238 for (alias = cpu; alias != m68k_cpus; alias--)
2239 if (alias[-1].alias >= 0)
2240 break;
2241 for (; !seen_master || alias->alias > 0; alias++)
2242 {
2243 if (!alias->alias)
2244 seen_master = 1;
2245 else
2246 {
2247 if (any)
2248 APPEND (", ");
2249 else
2250 APPEND (" [");
2251 APPEND (alias->name);
2252 any = 1;
2253 }
2254 }
2255 if (any)
2256 APPEND ("]");
2257 any = 1;
2258 }
2259 if (paren)
2260 APPEND (")");
2261 #undef APPEND
2262 if (!space)
2263 {
2264 /* we ran out of space, so replace the end of the list
2265 with ellipsis. */
2266 buf -= 4;
2267 while (*buf != ' ')
2268 buf--;
2269 strcpy (buf, " ...");
2270 }
2271 }
2272 else
2273 the_ins.error = _("operands mismatch");
2274 return;
2275 }
2276
2277 losing = 0;
2278 }
2279
2280 /* Now assemble it. */
2281 the_ins.args = opcode->m_operands;
2282 the_ins.numargs = opcode->m_opnum;
2283 the_ins.numo = opcode->m_codenum;
2284 the_ins.opcode[0] = getone (opcode);
2285 the_ins.opcode[1] = gettwo (opcode);
2286
2287 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2288 {
2289 int have_disp = 0;
2290 int use_pl = 0;
2291
2292 /* This switch is a doozy.
2293 Watch the first step; its a big one! */
2294 switch (s[0])
2295 {
2296
2297 case '*':
2298 case '~':
2299 case '%':
2300 case ';':
2301 case '@':
2302 case '!':
2303 case '&':
2304 case '$':
2305 case '?':
2306 case '/':
2307 case '<':
2308 case '>':
2309 case 'b':
2310 case 'm':
2311 case 'n':
2312 case 'o':
2313 case 'p':
2314 case 'q':
2315 case 'v':
2316 case 'w':
2317 case 'y':
2318 case 'z':
2319 case '4':
2320 #ifndef NO_68851
2321 case '|':
2322 #endif
2323 switch (opP->mode)
2324 {
2325 case IMMED:
2326 tmpreg = 0x3c; /* 7.4 */
2327 if (strchr ("bwl", s[1]))
2328 nextword = get_num (&opP->disp, 90);
2329 else
2330 nextword = get_num (&opP->disp, 0);
2331 if (isvar (&opP->disp))
2332 add_fix (s[1], &opP->disp, 0, 0);
2333 switch (s[1])
2334 {
2335 case 'b':
2336 if (!isbyte (nextword))
2337 opP->error = _("operand out of range");
2338 addword (nextword);
2339 baseo = 0;
2340 break;
2341 case 'w':
2342 if (!isword (nextword))
2343 opP->error = _("operand out of range");
2344 addword (nextword);
2345 baseo = 0;
2346 break;
2347 case 'W':
2348 if (!issword (nextword))
2349 opP->error = _("operand out of range");
2350 addword (nextword);
2351 baseo = 0;
2352 break;
2353 case 'l':
2354 addword (nextword >> 16);
2355 addword (nextword);
2356 baseo = 0;
2357 break;
2358
2359 case 'f':
2360 baseo = 2;
2361 outro = 8;
2362 break;
2363 case 'F':
2364 baseo = 4;
2365 outro = 11;
2366 break;
2367 case 'x':
2368 baseo = 6;
2369 outro = 15;
2370 break;
2371 case 'p':
2372 baseo = 6;
2373 outro = -1;
2374 break;
2375 default:
2376 abort ();
2377 }
2378 if (!baseo)
2379 break;
2380
2381 /* We gotta put out some float. */
2382 if (op (&opP->disp) != O_big)
2383 {
2384 valueT val;
2385 int gencnt;
2386
2387 /* Can other cases happen here? */
2388 if (op (&opP->disp) != O_constant)
2389 abort ();
2390
2391 val = (valueT) offs (&opP->disp);
2392 gencnt = 0;
2393 do
2394 {
2395 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2396 val >>= LITTLENUM_NUMBER_OF_BITS;
2397 ++gencnt;
2398 }
2399 while (val != 0);
2400 offs (&opP->disp) = gencnt;
2401 }
2402 if (offs (&opP->disp) > 0)
2403 {
2404 if (offs (&opP->disp) > baseo)
2405 {
2406 as_warn (_("Bignum too big for %c format; truncated"),
2407 s[1]);
2408 offs (&opP->disp) = baseo;
2409 }
2410 baseo -= offs (&opP->disp);
2411 while (baseo--)
2412 addword (0);
2413 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2414 offs (&opP->disp)--;
2415 --wordp)
2416 addword (*wordp);
2417 break;
2418 }
2419 gen_to_words (words, baseo, (long) outro);
2420 for (wordp = words; baseo--; wordp++)
2421 addword (*wordp);
2422 break;
2423 case DREG:
2424 tmpreg = opP->reg - DATA; /* 0.dreg */
2425 break;
2426 case AREG:
2427 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2428 break;
2429 case AINDR:
2430 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2431 break;
2432 case ADEC:
2433 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2434 break;
2435 case AINC:
2436 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2437 break;
2438 case DISP:
2439
2440 nextword = get_num (&opP->disp, 90);
2441
2442 /* Convert mode 5 addressing with a zero offset into
2443 mode 2 addressing to reduce the instruction size by a
2444 word. */
2445 if (! isvar (&opP->disp)
2446 && (nextword == 0)
2447 && (opP->disp.size == SIZE_UNSPEC)
2448 && (opP->reg >= ADDR0)
2449 && (opP->reg <= ADDR7))
2450 {
2451 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2452 break;
2453 }
2454
2455 if (opP->reg == PC
2456 && ! isvar (&opP->disp)
2457 && m68k_abspcadd)
2458 {
2459 opP->disp.exp.X_op = O_symbol;
2460 opP->disp.exp.X_add_symbol =
2461 section_symbol (absolute_section);
2462 }
2463
2464 /* Force into index mode. Hope this works. */
2465
2466 /* We do the first bit for 32-bit displacements, and the
2467 second bit for 16 bit ones. It is possible that we
2468 should make the default be WORD instead of LONG, but
2469 I think that'd break GCC, so we put up with a little
2470 inefficiency for the sake of working output. */
2471
2472 if (!issword (nextword)
2473 || (isvar (&opP->disp)
2474 && ((opP->disp.size == SIZE_UNSPEC
2475 && flag_short_refs == 0
2476 && cpu_of_arch (current_architecture) >= m68020
2477 && ! arch_coldfire_p (current_architecture))
2478 || opP->disp.size == SIZE_LONG)))
2479 {
2480 if (cpu_of_arch (current_architecture) < m68020
2481 || arch_coldfire_p (current_architecture))
2482 opP->error =
2483 _("displacement too large for this architecture; needs 68020 or higher");
2484 if (opP->reg == PC)
2485 tmpreg = 0x3B; /* 7.3 */
2486 else
2487 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2488 if (isvar (&opP->disp))
2489 {
2490 if (opP->reg == PC)
2491 {
2492 if (opP->disp.size == SIZE_LONG
2493 #ifdef OBJ_ELF
2494 /* If the displacement needs pic
2495 relocation it cannot be relaxed. */
2496 || opP->disp.pic_reloc != pic_none
2497 #endif
2498 )
2499 {
2500 addword (0x0170);
2501 add_fix ('l', &opP->disp, 1, 2);
2502 }
2503 else
2504 {
2505 add_frag (adds (&opP->disp),
2506 SEXT (offs (&opP->disp)),
2507 TAB (PCREL1632, SZ_UNDEF));
2508 break;
2509 }
2510 }
2511 else
2512 {
2513 addword (0x0170);
2514 add_fix ('l', &opP->disp, 0, 0);
2515 }
2516 }
2517 else
2518 addword (0x0170);
2519 addword (nextword >> 16);
2520 }
2521 else
2522 {
2523 if (opP->reg == PC)
2524 tmpreg = 0x3A; /* 7.2 */
2525 else
2526 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2527
2528 if (isvar (&opP->disp))
2529 {
2530 if (opP->reg == PC)
2531 {
2532 add_fix ('w', &opP->disp, 1, 0);
2533 }
2534 else
2535 add_fix ('w', &opP->disp, 0, 0);
2536 }
2537 }
2538 addword (nextword);
2539 break;
2540
2541 case POST:
2542 case PRE:
2543 case BASE:
2544 nextword = 0;
2545 baseo = get_num (&opP->disp, 90);
2546 if (opP->mode == POST || opP->mode == PRE)
2547 outro = get_num (&opP->odisp, 90);
2548 /* Figure out the `addressing mode'.
2549 Also turn on the BASE_DISABLE bit, if needed. */
2550 if (opP->reg == PC || opP->reg == ZPC)
2551 {
2552 tmpreg = 0x3b; /* 7.3 */
2553 if (opP->reg == ZPC)
2554 nextword |= 0x80;
2555 }
2556 else if (opP->reg == 0)
2557 {
2558 nextword |= 0x80;
2559 tmpreg = 0x30; /* 6.garbage */
2560 }
2561 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2562 {
2563 nextword |= 0x80;
2564 tmpreg = 0x30 + opP->reg - ZADDR0;
2565 }
2566 else
2567 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2568
2569 siz1 = opP->disp.size;
2570 if (opP->mode == POST || opP->mode == PRE)
2571 siz2 = opP->odisp.size;
2572 else
2573 siz2 = SIZE_UNSPEC;
2574
2575 /* Index register stuff. */
2576 if (opP->index.reg != 0
2577 && opP->index.reg >= DATA
2578 && opP->index.reg <= ADDR7)
2579 {
2580 nextword |= (opP->index.reg - DATA) << 12;
2581
2582 if (opP->index.size == SIZE_LONG
2583 || (opP->index.size == SIZE_UNSPEC
2584 && m68k_index_width_default == SIZE_LONG))
2585 nextword |= 0x800;
2586
2587 if ((opP->index.scale != 1
2588 && cpu_of_arch (current_architecture) < m68020)
2589 || (opP->index.scale == 8
2590 && (arch_coldfire_p (current_architecture)
2591 && !arch_coldfire_fpu (current_architecture))))
2592 {
2593 opP->error =
2594 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2595 }
2596
2597 if (arch_coldfire_p (current_architecture)
2598 && opP->index.size == SIZE_WORD)
2599 opP->error = _("invalid index size for coldfire");
2600
2601 switch (opP->index.scale)
2602 {
2603 case 1:
2604 break;
2605 case 2:
2606 nextword |= 0x200;
2607 break;
2608 case 4:
2609 nextword |= 0x400;
2610 break;
2611 case 8:
2612 nextword |= 0x600;
2613 break;
2614 default:
2615 abort ();
2616 }
2617 /* IF its simple,
2618 GET US OUT OF HERE! */
2619
2620 /* Must be INDEX, with an index register. Address
2621 register cannot be ZERO-PC, and either :b was
2622 forced, or we know it will fit. For a 68000 or
2623 68010, force this mode anyways, because the
2624 larger modes aren't supported. */
2625 if (opP->mode == BASE
2626 && ((opP->reg >= ADDR0
2627 && opP->reg <= ADDR7)
2628 || opP->reg == PC))
2629 {
2630 if (siz1 == SIZE_BYTE
2631 || cpu_of_arch (current_architecture) < m68020
2632 || arch_coldfire_p (current_architecture)
2633 || (siz1 == SIZE_UNSPEC
2634 && ! isvar (&opP->disp)
2635 && issbyte (baseo)))
2636 {
2637 nextword += baseo & 0xff;
2638 addword (nextword);
2639 if (isvar (&opP->disp))
2640 {
2641 /* Do a byte relocation. If it doesn't
2642 fit (possible on m68000) let the
2643 fixup processing complain later. */
2644 if (opP->reg == PC)
2645 add_fix ('B', &opP->disp, 1, 1);
2646 else
2647 add_fix ('B', &opP->disp, 0, 0);
2648 }
2649 else if (siz1 != SIZE_BYTE)
2650 {
2651 if (siz1 != SIZE_UNSPEC)
2652 as_warn (_("Forcing byte displacement"));
2653 if (! issbyte (baseo))
2654 opP->error = _("byte displacement out of range");
2655 }
2656
2657 break;
2658 }
2659 else if (siz1 == SIZE_UNSPEC
2660 && opP->reg == PC
2661 && isvar (&opP->disp)
2662 && subs (&opP->disp) == NULL
2663 #ifdef OBJ_ELF
2664 /* If the displacement needs pic
2665 relocation it cannot be relaxed. */
2666 && opP->disp.pic_reloc == pic_none
2667 #endif
2668 )
2669 {
2670 /* The code in md_convert_frag_1 needs to be
2671 able to adjust nextword. Call frag_grow
2672 to ensure that we have enough space in
2673 the frag obstack to make all the bytes
2674 contiguous. */
2675 frag_grow (14);
2676 nextword += baseo & 0xff;
2677 addword (nextword);
2678 add_frag (adds (&opP->disp),
2679 SEXT (offs (&opP->disp)),
2680 TAB (PCINDEX, SZ_UNDEF));
2681
2682 break;
2683 }
2684 }
2685 }
2686 else
2687 {
2688 nextword |= 0x40; /* No index reg. */
2689 if (opP->index.reg >= ZDATA0
2690 && opP->index.reg <= ZDATA7)
2691 nextword |= (opP->index.reg - ZDATA0) << 12;
2692 else if (opP->index.reg >= ZADDR0
2693 || opP->index.reg <= ZADDR7)
2694 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2695 }
2696
2697 /* It isn't simple. */
2698
2699 if (cpu_of_arch (current_architecture) < m68020
2700 || arch_coldfire_p (current_architecture))
2701 opP->error =
2702 _("invalid operand mode for this architecture; needs 68020 or higher");
2703
2704 nextword |= 0x100;
2705 /* If the guy specified a width, we assume that it is
2706 wide enough. Maybe it isn't. If so, we lose. */
2707 switch (siz1)
2708 {
2709 case SIZE_UNSPEC:
2710 if (isvar (&opP->disp)
2711 ? m68k_rel32
2712 : ! issword (baseo))
2713 {
2714 siz1 = SIZE_LONG;
2715 nextword |= 0x30;
2716 }
2717 else if (! isvar (&opP->disp) && baseo == 0)
2718 nextword |= 0x10;
2719 else
2720 {
2721 nextword |= 0x20;
2722 siz1 = SIZE_WORD;
2723 }
2724 break;
2725 case SIZE_BYTE:
2726 as_warn (_(":b not permitted; defaulting to :w"));
2727 /* Fall through. */
2728 case SIZE_WORD:
2729 nextword |= 0x20;
2730 break;
2731 case SIZE_LONG:
2732 nextword |= 0x30;
2733 break;
2734 }
2735
2736 /* Figure out inner displacement stuff. */
2737 if (opP->mode == POST || opP->mode == PRE)
2738 {
2739 if (cpu_of_arch (current_architecture) & cpu32)
2740 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2741 switch (siz2)
2742 {
2743 case SIZE_UNSPEC:
2744 if (isvar (&opP->odisp)
2745 ? m68k_rel32
2746 : ! issword (outro))
2747 {
2748 siz2 = SIZE_LONG;
2749 nextword |= 0x3;
2750 }
2751 else if (! isvar (&opP->odisp) && outro == 0)
2752 nextword |= 0x1;
2753 else
2754 {
2755 nextword |= 0x2;
2756 siz2 = SIZE_WORD;
2757 }
2758 break;
2759 case 1:
2760 as_warn (_(":b not permitted; defaulting to :w"));
2761 /* Fall through. */
2762 case 2:
2763 nextword |= 0x2;
2764 break;
2765 case 3:
2766 nextword |= 0x3;
2767 break;
2768 }
2769 if (opP->mode == POST
2770 && (nextword & 0x40) == 0)
2771 nextword |= 0x04;
2772 }
2773 addword (nextword);
2774
2775 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2776 {
2777 if (opP->reg == PC || opP->reg == ZPC)
2778 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2779 else
2780 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2781 }
2782 if (siz1 == SIZE_LONG)
2783 addword (baseo >> 16);
2784 if (siz1 != SIZE_UNSPEC)
2785 addword (baseo);
2786
2787 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2788 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2789 if (siz2 == SIZE_LONG)
2790 addword (outro >> 16);
2791 if (siz2 != SIZE_UNSPEC)
2792 addword (outro);
2793
2794 break;
2795
2796 case ABSL:
2797 nextword = get_num (&opP->disp, 90);
2798 switch (opP->disp.size)
2799 {
2800 default:
2801 abort ();
2802 case SIZE_UNSPEC:
2803 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2804 {
2805 tmpreg = 0x38; /* 7.0 */
2806 addword (nextword);
2807 break;
2808 }
2809 if (isvar (&opP->disp)
2810 && !subs (&opP->disp)
2811 && adds (&opP->disp)
2812 #ifdef OBJ_ELF
2813 /* If the displacement needs pic relocation it
2814 cannot be relaxed. */
2815 && opP->disp.pic_reloc == pic_none
2816 #endif
2817 && !flag_long_jumps
2818 && !strchr ("~%&$?", s[0]))
2819 {
2820 tmpreg = 0x3A; /* 7.2 */
2821 add_frag (adds (&opP->disp),
2822 SEXT (offs (&opP->disp)),
2823 TAB (ABSTOPCREL, SZ_UNDEF));
2824 break;
2825 }
2826 /* Fall through into long. */
2827 case SIZE_LONG:
2828 if (isvar (&opP->disp))
2829 add_fix ('l', &opP->disp, 0, 0);
2830
2831 tmpreg = 0x39;/* 7.1 mode */
2832 addword (nextword >> 16);
2833 addword (nextword);
2834 break;
2835
2836 case SIZE_BYTE:
2837 as_bad (_("unsupported byte value; use a different suffix"));
2838 /* Fall through. */
2839
2840 case SIZE_WORD:
2841 if (isvar (&opP->disp))
2842 add_fix ('w', &opP->disp, 0, 0);
2843
2844 tmpreg = 0x38;/* 7.0 mode */
2845 addword (nextword);
2846 break;
2847 }
2848 break;
2849 case CONTROL:
2850 case FPREG:
2851 default:
2852 as_bad (_("unknown/incorrect operand"));
2853 /* abort (); */
2854 }
2855
2856 /* If s[0] is '4', then this is for the mac instructions
2857 that can have a trailing_ampersand set. If so, set 0x100
2858 bit on tmpreg so install_gen_operand can check for it and
2859 set the appropriate bit (word2, bit 5). */
2860 if (s[0] == '4')
2861 {
2862 if (opP->trailing_ampersand)
2863 tmpreg |= 0x100;
2864 }
2865 install_gen_operand (s[1], tmpreg);
2866 break;
2867
2868 case '#':
2869 case '^':
2870 switch (s[1])
2871 { /* JF: I hate floating point! */
2872 case 'j':
2873 tmpreg = 70;
2874 break;
2875 case '8':
2876 tmpreg = 20;
2877 break;
2878 case 'C':
2879 tmpreg = 50;
2880 break;
2881 case '3':
2882 default:
2883 tmpreg = 90;
2884 break;
2885 }
2886 tmpreg = get_num (&opP->disp, tmpreg);
2887 if (isvar (&opP->disp))
2888 add_fix (s[1], &opP->disp, 0, 0);
2889 switch (s[1])
2890 {
2891 case 'b': /* Danger: These do no check for
2892 certain types of overflow.
2893 user beware! */
2894 if (!isbyte (tmpreg))
2895 opP->error = _("out of range");
2896 insop (tmpreg, opcode);
2897 if (isvar (&opP->disp))
2898 the_ins.reloc[the_ins.nrel - 1].n =
2899 (opcode->m_codenum) * 2 + 1;
2900 break;
2901 case 'B':
2902 if (!issbyte (tmpreg))
2903 opP->error = _("out of range");
2904 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2905 if (isvar (&opP->disp))
2906 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2907 break;
2908 case 'w':
2909 if (!isword (tmpreg))
2910 opP->error = _("out of range");
2911 insop (tmpreg, opcode);
2912 if (isvar (&opP->disp))
2913 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2914 break;
2915 case 'W':
2916 if (!issword (tmpreg))
2917 opP->error = _("out of range");
2918 insop (tmpreg, opcode);
2919 if (isvar (&opP->disp))
2920 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2921 break;
2922 case 'l':
2923 /* Because of the way insop works, we put these two out
2924 backwards. */
2925 insop (tmpreg, opcode);
2926 insop (tmpreg >> 16, opcode);
2927 if (isvar (&opP->disp))
2928 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2929 break;
2930 case '3':
2931 tmpreg &= 0xFF;
2932 case '8':
2933 case 'C':
2934 case 'j':
2935 install_operand (s[1], tmpreg);
2936 break;
2937 default:
2938 abort ();
2939 }
2940 break;
2941
2942 case '+':
2943 case '-':
2944 case 'A':
2945 case 'a':
2946 install_operand (s[1], opP->reg - ADDR);
2947 break;
2948
2949 case 'B':
2950 tmpreg = get_num (&opP->disp, 90);
2951
2952 switch (s[1])
2953 {
2954 case 'B':
2955 add_fix ('B', &opP->disp, 1, -1);
2956 break;
2957 case 'W':
2958 add_fix ('w', &opP->disp, 1, 0);
2959 addword (0);
2960 break;
2961 case 'L':
2962 long_branch:
2963 the_ins.opcode[0] |= 0xff;
2964 add_fix ('l', &opP->disp, 1, 0);
2965 addword (0);
2966 addword (0);
2967 break;
2968 case 'g': /* Conditional branch */
2969 have_disp = HAVE_LONG_CALL (current_architecture);
2970 goto var_branch;
2971
2972 case 'b': /* Unconditional branch */
2973 have_disp = HAVE_LONG_BRANCH (current_architecture);
2974 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
2975 goto var_branch;
2976
2977 case 's': /* Unconditional subroutine */
2978 have_disp = HAVE_LONG_CALL (current_architecture);
2979
2980 var_branch:
2981 if (subs (&opP->disp) /* We can't relax it. */
2982 #ifdef OBJ_ELF
2983 /* If the displacement needs pic relocation it cannot be
2984 relaxed. */
2985 || opP->disp.pic_reloc != pic_none
2986 #endif
2987 || 0)
2988 {
2989 if (!have_disp)
2990 as_warn (_("Can't use long branches on this architecture"));
2991 goto long_branch;
2992 }
2993
2994 /* This could either be a symbol, or an absolute
2995 address. If it's an absolute address, turn it into
2996 an absolute jump right here and keep it out of the
2997 relaxer. */
2998 if (adds (&opP->disp) == 0)
2999 {
3000 if (the_ins.opcode[0] == 0x6000) /* jbra */
3001 the_ins.opcode[0] = 0x4EF9;
3002 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
3003 the_ins.opcode[0] = 0x4EB9;
3004 else /* jCC */
3005 {
3006 the_ins.opcode[0] ^= 0x0100;
3007 the_ins.opcode[0] |= 0x0006;
3008 addword (0x4EF9);
3009 }
3010 add_fix ('l', &opP->disp, 0, 0);
3011 addword (0);
3012 addword (0);
3013 break;
3014 }
3015
3016 /* Now we know it's going into the relaxer. Now figure
3017 out which mode. We try in this order of preference:
3018 long branch, absolute jump, byte/word branches only. */
3019 if (have_disp)
3020 add_frag (adds (&opP->disp),
3021 SEXT (offs (&opP->disp)),
3022 TAB (BRANCHBWL, SZ_UNDEF));
3023 else if (! flag_keep_pcrel)
3024 {
3025 if ((the_ins.opcode[0] == 0x6000)
3026 || (the_ins.opcode[0] == 0x6100))
3027 add_frag (adds (&opP->disp),
3028 SEXT (offs (&opP->disp)),
3029 TAB (BRABSJUNC, SZ_UNDEF));
3030 else
3031 add_frag (adds (&opP->disp),
3032 SEXT (offs (&opP->disp)),
3033 TAB (BRABSJCOND, SZ_UNDEF));
3034 }
3035 else
3036 add_frag (adds (&opP->disp),
3037 SEXT (offs (&opP->disp)),
3038 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3039 : TAB (BRANCHBW, SZ_UNDEF)));
3040 break;
3041 case 'w':
3042 if (isvar (&opP->disp))
3043 {
3044 /* Check for DBcc instructions. We can relax them,
3045 but only if we have long branches and/or absolute
3046 jumps. */
3047 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3048 && (HAVE_LONG_BRANCH (current_architecture)
3049 || ! flag_keep_pcrel))
3050 {
3051 if (HAVE_LONG_BRANCH (current_architecture))
3052 add_frag (adds (&opP->disp),
3053 SEXT (offs (&opP->disp)),
3054 TAB (DBCCLBR, SZ_UNDEF));
3055 else
3056 add_frag (adds (&opP->disp),
3057 SEXT (offs (&opP->disp)),
3058 TAB (DBCCABSJ, SZ_UNDEF));
3059 break;
3060 }
3061 add_fix ('w', &opP->disp, 1, 0);
3062 }
3063 addword (0);
3064 break;
3065 case 'C': /* Fixed size LONG coproc branches. */
3066 add_fix ('l', &opP->disp, 1, 0);
3067 addword (0);
3068 addword (0);
3069 break;
3070 case 'c': /* Var size Coprocesssor branches. */
3071 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3072 {
3073 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3074 add_fix ('l', &opP->disp, 1, 0);
3075 addword (0);
3076 addword (0);
3077 }
3078 else
3079 add_frag (adds (&opP->disp),
3080 SEXT (offs (&opP->disp)),
3081 TAB (FBRANCH, SZ_UNDEF));
3082 break;
3083 default:
3084 abort ();
3085 }
3086 break;
3087
3088 case 'C': /* Ignore it. */
3089 break;
3090
3091 case 'd': /* JF this is a kludge. */
3092 install_operand ('s', opP->reg - ADDR);
3093 tmpreg = get_num (&opP->disp, 90);
3094 if (!issword (tmpreg))
3095 {
3096 as_warn (_("Expression out of range, using 0"));
3097 tmpreg = 0;
3098 }
3099 addword (tmpreg);
3100 break;
3101
3102 case 'D':
3103 install_operand (s[1], opP->reg - DATA);
3104 break;
3105
3106 case 'e': /* EMAC ACCx, reg/reg. */
3107 install_operand (s[1], opP->reg - ACC);
3108 break;
3109
3110 case 'E': /* Ignore it. */
3111 break;
3112
3113 case 'F':
3114 install_operand (s[1], opP->reg - FP0);
3115 break;
3116
3117 case 'g': /* EMAC ACCEXTx. */
3118 install_operand (s[1], opP->reg - ACCEXT01);
3119 break;
3120
3121 case 'G': /* Ignore it. */
3122 case 'H':
3123 break;
3124
3125 case 'I':
3126 tmpreg = opP->reg - COP0;
3127 install_operand (s[1], tmpreg);
3128 break;
3129
3130 case 'i': /* MAC/EMAC scale factor. */
3131 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3132 break;
3133
3134 case 'J': /* JF foo. */
3135 switch (opP->reg)
3136 {
3137 case SFC:
3138 tmpreg = 0x000;
3139 break;
3140 case DFC:
3141 tmpreg = 0x001;
3142 break;
3143 case CACR:
3144 tmpreg = 0x002;
3145 break;
3146 case TC:
3147 case ASID:
3148 tmpreg = 0x003;
3149 break;
3150 case ACR0:
3151 case ITT0:
3152 tmpreg = 0x004;
3153 break;
3154 case ACR1:
3155 case ITT1:
3156 tmpreg = 0x005;
3157 break;
3158 case ACR2:
3159 case DTT0:
3160 tmpreg = 0x006;
3161 break;
3162 case ACR3:
3163 case DTT1:
3164 tmpreg = 0x007;
3165 break;
3166 case BUSCR:
3167 case MMUBAR:
3168 tmpreg = 0x008;
3169 break;
3170
3171 case USP:
3172 tmpreg = 0x800;
3173 break;
3174 case VBR:
3175 tmpreg = 0x801;
3176 break;
3177 case CAAR:
3178 tmpreg = 0x802;
3179 break;
3180 case MSP:
3181 tmpreg = 0x803;
3182 break;
3183 case ISP:
3184 tmpreg = 0x804;
3185 break;
3186 case MMUSR:
3187 tmpreg = 0x805;
3188 break;
3189 case URP:
3190 tmpreg = 0x806;
3191 break;
3192 case SRP:
3193 tmpreg = 0x807;
3194 break;
3195 case PCR:
3196 tmpreg = 0x808;
3197 break;
3198 case ROMBAR:
3199 case ROMBAR0:
3200 tmpreg = 0xC00;
3201 break;
3202 case ROMBAR1:
3203 tmpreg = 0xC01;
3204 break;
3205 case FLASHBAR:
3206 case RAMBAR0:
3207 case RAMBAR_ALT:
3208 tmpreg = 0xC04;
3209 break;
3210 case RAMBAR:
3211 case RAMBAR1:
3212 tmpreg = 0xC05;
3213 break;
3214 case MPCR:
3215 tmpreg = 0xC0C;
3216 break;
3217 case EDRAMBAR:
3218 tmpreg = 0xC0D;
3219 break;
3220 case MBAR0:
3221 case MBAR2:
3222 case SECMBAR:
3223 tmpreg = 0xC0E;
3224 break;
3225 case MBAR1:
3226 case MBAR:
3227 tmpreg = 0xC0F;
3228 break;
3229 case PCR1U0:
3230 tmpreg = 0xD02;
3231 break;
3232 case PCR1L0:
3233 tmpreg = 0xD03;
3234 break;
3235 case PCR2U0:
3236 tmpreg = 0xD04;
3237 break;
3238 case PCR2L0:
3239 tmpreg = 0xD05;
3240 break;
3241 case PCR3U0:
3242 tmpreg = 0xD06;
3243 break;
3244 case PCR3L0:
3245 tmpreg = 0xD07;
3246 break;
3247 case PCR1L1:
3248 tmpreg = 0xD0A;
3249 break;
3250 case PCR1U1:
3251 tmpreg = 0xD0B;
3252 break;
3253 case PCR2L1:
3254 tmpreg = 0xD0C;
3255 break;
3256 case PCR2U1:
3257 tmpreg = 0xD0D;
3258 break;
3259 case PCR3L1:
3260 tmpreg = 0xD0E;
3261 break;
3262 case PCR3U1:
3263 tmpreg = 0xD0F;
3264 break;
3265 case CAC:
3266 tmpreg = 0xFFE;
3267 break;
3268 case MBO:
3269 tmpreg = 0xFFF;
3270 break;
3271 default:
3272 abort ();
3273 }
3274 install_operand (s[1], tmpreg);
3275 break;
3276
3277 case 'k':
3278 tmpreg = get_num (&opP->disp, 55);
3279 install_operand (s[1], tmpreg & 0x7f);
3280 break;
3281
3282 case 'l':
3283 tmpreg = opP->mask;
3284 if (s[1] == 'w')
3285 {
3286 if (tmpreg & 0x7FF0000)
3287 as_bad (_("Floating point register in register list"));
3288 insop (reverse_16_bits (tmpreg), opcode);
3289 }
3290 else
3291 {
3292 if (tmpreg & 0x700FFFF)
3293 as_bad (_("Wrong register in floating-point reglist"));
3294 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3295 }
3296 break;
3297
3298 case 'L':
3299 tmpreg = opP->mask;
3300 if (s[1] == 'w')
3301 {
3302 if (tmpreg & 0x7FF0000)
3303 as_bad (_("Floating point register in register list"));
3304 insop (tmpreg, opcode);
3305 }
3306 else if (s[1] == '8')
3307 {
3308 if (tmpreg & 0x0FFFFFF)
3309 as_bad (_("incorrect register in reglist"));
3310 install_operand (s[1], tmpreg >> 24);
3311 }
3312 else
3313 {
3314 if (tmpreg & 0x700FFFF)
3315 as_bad (_("wrong register in floating-point reglist"));
3316 else
3317 install_operand (s[1], tmpreg >> 16);
3318 }
3319 break;
3320
3321 case 'M':
3322 install_operand (s[1], get_num (&opP->disp, 60));
3323 break;
3324
3325 case 'O':
3326 tmpreg = ((opP->mode == DREG)
3327 ? 0x20 + (int) (opP->reg - DATA)
3328 : (get_num (&opP->disp, 40) & 0x1F));
3329 install_operand (s[1], tmpreg);
3330 break;
3331
3332 case 'Q':
3333 tmpreg = get_num (&opP->disp, 10);
3334 if (tmpreg == 8)
3335 tmpreg = 0;
3336 install_operand (s[1], tmpreg);
3337 break;
3338
3339 case 'R':
3340 /* This depends on the fact that ADDR registers are eight
3341 more than their corresponding DATA regs, so the result
3342 will have the ADDR_REG bit set. */
3343 install_operand (s[1], opP->reg - DATA);
3344 break;
3345
3346 case 'r':
3347 if (opP->mode == AINDR)
3348 install_operand (s[1], opP->reg - DATA);
3349 else
3350 install_operand (s[1], opP->index.reg - DATA);
3351 break;
3352
3353 case 's':
3354 if (opP->reg == FPI)
3355 tmpreg = 0x1;
3356 else if (opP->reg == FPS)
3357 tmpreg = 0x2;
3358 else if (opP->reg == FPC)
3359 tmpreg = 0x4;
3360 else
3361 abort ();
3362 install_operand (s[1], tmpreg);
3363 break;
3364
3365 case 'S': /* Ignore it. */
3366 break;
3367
3368 case 'T':
3369 install_operand (s[1], get_num (&opP->disp, 30));
3370 break;
3371
3372 case 'U': /* Ignore it. */
3373 break;
3374
3375 case 'c':
3376 switch (opP->reg)
3377 {
3378 case NC:
3379 tmpreg = 0;
3380 break;
3381 case DC:
3382 tmpreg = 1;
3383 break;
3384 case IC:
3385 tmpreg = 2;
3386 break;
3387 case BC:
3388 tmpreg = 3;
3389 break;
3390 default:
3391 as_fatal (_("failed sanity check"));
3392 } /* switch on cache token. */
3393 install_operand (s[1], tmpreg);
3394 break;
3395 #ifndef NO_68851
3396 /* JF: These are out of order, I fear. */
3397 case 'f':
3398 switch (opP->reg)
3399 {
3400 case SFC:
3401 tmpreg = 0;
3402 break;
3403 case DFC:
3404 tmpreg = 1;
3405 break;
3406 default:
3407 abort ();
3408 }
3409 install_operand (s[1], tmpreg);
3410 break;
3411
3412 case '0':
3413 case '1':
3414 case '2':
3415 switch (opP->reg)
3416 {
3417 case TC:
3418 tmpreg = 0;
3419 break;
3420 case CAL:
3421 tmpreg = 4;
3422 break;
3423 case VAL:
3424 tmpreg = 5;
3425 break;
3426 case SCC:
3427 tmpreg = 6;
3428 break;
3429 case AC:
3430 tmpreg = 7;
3431 break;
3432 default:
3433 abort ();
3434 }
3435 install_operand (s[1], tmpreg);
3436 break;
3437
3438 case 'V':
3439 if (opP->reg == VAL)
3440 break;
3441 abort ();
3442
3443 case 'W':
3444 switch (opP->reg)
3445 {
3446 case DRP:
3447 tmpreg = 1;
3448 break;
3449 case SRP:
3450 tmpreg = 2;
3451 break;
3452 case CRP:
3453 tmpreg = 3;
3454 break;
3455 default:
3456 abort ();
3457 }
3458 install_operand (s[1], tmpreg);
3459 break;
3460
3461 case 'X':
3462 switch (opP->reg)
3463 {
3464 case BAD:
3465 case BAD + 1:
3466 case BAD + 2:
3467 case BAD + 3:
3468 case BAD + 4:
3469 case BAD + 5:
3470 case BAD + 6:
3471 case BAD + 7:
3472 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3473 break;
3474
3475 case BAC:
3476 case BAC + 1:
3477 case BAC + 2:
3478 case BAC + 3:
3479 case BAC + 4:
3480 case BAC + 5:
3481 case BAC + 6:
3482 case BAC + 7:
3483 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3484 break;
3485
3486 default:
3487 abort ();
3488 }
3489 install_operand (s[1], tmpreg);
3490 break;
3491 case 'Y':
3492 know (opP->reg == PSR);
3493 break;
3494 case 'Z':
3495 know (opP->reg == PCSR);
3496 break;
3497 #endif /* m68851 */
3498 case '3':
3499 switch (opP->reg)
3500 {
3501 case TT0:
3502 tmpreg = 2;
3503 break;
3504 case TT1:
3505 tmpreg = 3;
3506 break;
3507 default:
3508 abort ();
3509 }
3510 install_operand (s[1], tmpreg);
3511 break;
3512 case 't':
3513 tmpreg = get_num (&opP->disp, 20);
3514 install_operand (s[1], tmpreg);
3515 break;
3516 case '_': /* used only for move16 absolute 32-bit address. */
3517 if (isvar (&opP->disp))
3518 add_fix ('l', &opP->disp, 0, 0);
3519 tmpreg = get_num (&opP->disp, 90);
3520 addword (tmpreg >> 16);
3521 addword (tmpreg & 0xFFFF);
3522 break;
3523 case 'u':
3524 install_operand (s[1], opP->reg - DATA0L);
3525 opP->reg -= (DATA0L);
3526 opP->reg &= 0x0F; /* remove upper/lower bit. */
3527 break;
3528 case 'x':
3529 tmpreg = get_num (&opP->disp, 80);
3530 if (tmpreg == -1)
3531 tmpreg = 0;
3532 install_operand (s[1], tmpreg);
3533 break;
3534 case 'j':
3535 tmpreg = get_num (&opP->disp, 10);
3536 install_operand (s[1], tmpreg - 1);
3537 break;
3538 case 'K':
3539 tmpreg = get_num (&opP->disp, 65);
3540 install_operand (s[1], tmpreg);
3541 break;
3542 default:
3543 abort ();
3544 }
3545 }
3546
3547 /* By the time whe get here (FINALLY) the_ins contains the complete
3548 instruction, ready to be emitted. . . */
3549 }
3550
3551 static int
3552 reverse_16_bits (int in)
3553 {
3554 int out = 0;
3555 int n;
3556
3557 static int mask[16] =
3558 {
3559 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3560 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3561 };
3562 for (n = 0; n < 16; n++)
3563 {
3564 if (in & mask[n])
3565 out |= mask[15 - n];
3566 }
3567 return out;
3568 } /* reverse_16_bits() */
3569
3570 static int
3571 reverse_8_bits (int in)
3572 {
3573 int out = 0;
3574 int n;
3575
3576 static int mask[8] =
3577 {
3578 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3579 };
3580
3581 for (n = 0; n < 8; n++)
3582 {
3583 if (in & mask[n])
3584 out |= mask[7 - n];
3585 }
3586 return out;
3587 } /* reverse_8_bits() */
3588
3589 /* Cause an extra frag to be generated here, inserting up to
3590 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3591 generated; its primary type is rs_machine_dependent.
3592
3593 The TYPE parameter is also used by md_convert_frag_1 and
3594 md_estimate_size_before_relax. The appropriate type of fixup will
3595 be emitted by md_convert_frag_1.
3596
3597 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3598 static void
3599 install_operand (int mode, int val)
3600 {
3601 switch (mode)
3602 {
3603 case 's':
3604 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3605 break;
3606 case 'd':
3607 the_ins.opcode[0] |= val << 9;
3608 break;
3609 case 'E':
3610 the_ins.opcode[1] |= val << 9;
3611 break;
3612 case '1':
3613 the_ins.opcode[1] |= val << 12;
3614 break;
3615 case '2':
3616 the_ins.opcode[1] |= val << 6;
3617 break;
3618 case '3':
3619 the_ins.opcode[1] |= val;
3620 break;
3621 case '4':
3622 the_ins.opcode[2] |= val << 12;
3623 break;
3624 case '5':
3625 the_ins.opcode[2] |= val << 6;
3626 break;
3627 case '6':
3628 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3629 three words long! */
3630 the_ins.numo++;
3631 the_ins.opcode[2] |= val;
3632 break;
3633 case '7':
3634 the_ins.opcode[1] |= val << 7;
3635 break;
3636 case '8':
3637 the_ins.opcode[1] |= val << 10;
3638 break;
3639 #ifndef NO_68851
3640 case '9':
3641 the_ins.opcode[1] |= val << 5;
3642 break;
3643 #endif
3644
3645 case 't':
3646 the_ins.opcode[1] |= (val << 10) | (val << 7);
3647 break;
3648 case 'D':
3649 the_ins.opcode[1] |= (val << 12) | val;
3650 break;
3651 case 'g':
3652 the_ins.opcode[0] |= val = 0xff;
3653 break;
3654 case 'i':
3655 the_ins.opcode[0] |= val << 9;
3656 break;
3657 case 'C':
3658 the_ins.opcode[1] |= val;
3659 break;
3660 case 'j':
3661 the_ins.opcode[1] |= val;
3662 the_ins.numo++; /* What a hack. */
3663 break;
3664 case 'k':
3665 the_ins.opcode[1] |= val << 4;
3666 break;
3667 case 'b':
3668 case 'w':
3669 case 'W':
3670 case 'l':
3671 break;
3672 case 'e':
3673 the_ins.opcode[0] |= (val << 6);
3674 break;
3675 case 'L':
3676 the_ins.opcode[1] = (val >> 16);
3677 the_ins.opcode[2] = val & 0xffff;
3678 break;
3679 case 'm':
3680 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3681 the_ins.opcode[0] |= ((val & 0x7) << 9);
3682 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3683 break;
3684 case 'n': /* MAC/EMAC Rx on !load. */
3685 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3686 the_ins.opcode[0] |= ((val & 0x7) << 9);
3687 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3688 break;
3689 case 'o': /* MAC/EMAC Rx on load. */
3690 the_ins.opcode[1] |= val << 12;
3691 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3692 break;
3693 case 'M': /* MAC/EMAC Ry on !load. */
3694 the_ins.opcode[0] |= (val & 0xF);
3695 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3696 break;
3697 case 'N': /* MAC/EMAC Ry on load. */
3698 the_ins.opcode[1] |= (val & 0xF);
3699 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3700 break;
3701 case 'h':
3702 the_ins.opcode[1] |= ((val != 1) << 10);
3703 break;
3704 case 'F':
3705 the_ins.opcode[0] |= ((val & 0x3) << 9);
3706 break;
3707 case 'f':
3708 the_ins.opcode[0] |= ((val & 0x3) << 0);
3709 break;
3710 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3711 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3712 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3713 break;
3714 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3715 the_ins.opcode[0] |= ((val & 0x1) << 7);
3716 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3717 break;
3718 case 'I':
3719 the_ins.opcode[1] |= ((val & 0x3) << 9);
3720 break;
3721 case ']':
3722 the_ins.opcode[0] |= (val & 0x1) <<10;
3723 break;
3724 case 'c':
3725 default:
3726 as_fatal (_("failed sanity check."));
3727 }
3728 }
3729
3730 static void
3731 install_gen_operand (int mode, int val)
3732 {
3733 switch (mode)
3734 {
3735 case '/': /* Special for mask loads for mac/msac insns with
3736 possible mask; trailing_ampersend set in bit 8. */
3737 the_ins.opcode[0] |= (val & 0x3f);
3738 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3739 break;
3740 case 's':
3741 the_ins.opcode[0] |= val;
3742 break;
3743 case 'd':
3744 /* This is a kludge!!! */
3745 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3746 break;
3747 case 'b':
3748 case 'w':
3749 case 'l':
3750 case 'f':
3751 case 'F':
3752 case 'x':
3753 case 'p':
3754 the_ins.opcode[0] |= val;
3755 break;
3756 /* more stuff goes here. */
3757 default:
3758 as_fatal (_("failed sanity check."));
3759 }
3760 }
3761
3762 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3763 then deal with the bitfield hack. */
3764
3765 static char *
3766 crack_operand (char *str, struct m68k_op *opP)
3767 {
3768 register int parens;
3769 register int c;
3770 register char *beg_str;
3771 int inquote = 0;
3772
3773 if (!str)
3774 {
3775 return str;
3776 }
3777 beg_str = str;
3778 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3779 {
3780 if (! inquote)
3781 {
3782 if (*str == '(')
3783 parens++;
3784 else if (*str == ')')
3785 {
3786 if (!parens)
3787 { /* ERROR. */
3788 opP->error = _("Extra )");
3789 return str;
3790 }
3791 --parens;
3792 }
3793 }
3794 if (flag_mri && *str == '\'')
3795 inquote = ! inquote;
3796 }
3797 if (!*str && parens)
3798 { /* ERROR. */
3799 opP->error = _("Missing )");
3800 return str;
3801 }
3802 c = *str;
3803 *str = '\0';
3804 if (m68k_ip_op (beg_str, opP) != 0)
3805 {
3806 *str = c;
3807 return str;
3808 }
3809 *str = c;
3810 if (c == '}')
3811 c = *++str; /* JF bitfield hack. */
3812 if (c)
3813 {
3814 c = *++str;
3815 if (!c)
3816 as_bad (_("Missing operand"));
3817 }
3818
3819 /* Detect MRI REG symbols and convert them to REGLSTs. */
3820 if (opP->mode == CONTROL && (int)opP->reg < 0)
3821 {
3822 opP->mode = REGLST;
3823 opP->mask = ~(int)opP->reg;
3824 opP->reg = 0;
3825 }
3826
3827 return str;
3828 }
3829
3830 /* This is the guts of the machine-dependent assembler. STR points to a
3831 machine dependent instruction. This function is supposed to emit
3832 the frags/bytes it assembles to.
3833 */
3834
3835 static void
3836 insert_reg (const char *regname, int regnum)
3837 {
3838 char buf[100];
3839 int i;
3840
3841 #ifdef REGISTER_PREFIX
3842 if (!flag_reg_prefix_optional)
3843 {
3844 buf[0] = REGISTER_PREFIX;
3845 strcpy (buf + 1, regname);
3846 regname = buf;
3847 }
3848 #endif
3849
3850 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3851 &zero_address_frag));
3852
3853 for (i = 0; regname[i]; i++)
3854 buf[i] = TOUPPER (regname[i]);
3855 buf[i] = '\0';
3856
3857 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3858 &zero_address_frag));
3859 }
3860
3861 struct init_entry
3862 {
3863 const char *name;
3864 int number;
3865 };
3866
3867 static const struct init_entry init_table[] =
3868 {
3869 { "d0", DATA0 },
3870 { "d1", DATA1 },
3871 { "d2", DATA2 },
3872 { "d3", DATA3 },
3873 { "d4", DATA4 },
3874 { "d5", DATA5 },
3875 { "d6", DATA6 },
3876 { "d7", DATA7 },
3877 { "a0", ADDR0 },
3878 { "a1", ADDR1 },
3879 { "a2", ADDR2 },
3880 { "a3", ADDR3 },
3881 { "a4", ADDR4 },
3882 { "a5", ADDR5 },
3883 { "a6", ADDR6 },
3884 { "fp", ADDR6 },
3885 { "a7", ADDR7 },
3886 { "sp", ADDR7 },
3887 { "ssp", ADDR7 },
3888 { "fp0", FP0 },
3889 { "fp1", FP1 },
3890 { "fp2", FP2 },
3891 { "fp3", FP3 },
3892 { "fp4", FP4 },
3893 { "fp5", FP5 },
3894 { "fp6", FP6 },
3895 { "fp7", FP7 },
3896 { "fpi", FPI },
3897 { "fpiar", FPI },
3898 { "fpc", FPI },
3899 { "fps", FPS },
3900 { "fpsr", FPS },
3901 { "fpc", FPC },
3902 { "fpcr", FPC },
3903 { "control", FPC },
3904 { "status", FPS },
3905 { "iaddr", FPI },
3906
3907 { "cop0", COP0 },
3908 { "cop1", COP1 },
3909 { "cop2", COP2 },
3910 { "cop3", COP3 },
3911 { "cop4", COP4 },
3912 { "cop5", COP5 },
3913 { "cop6", COP6 },
3914 { "cop7", COP7 },
3915 { "pc", PC },
3916 { "zpc", ZPC },
3917 { "sr", SR },
3918
3919 { "ccr", CCR },
3920 { "cc", CCR },
3921
3922 { "acc", ACC },
3923 { "acc0", ACC },
3924 { "acc1", ACC1 },
3925 { "acc2", ACC2 },
3926 { "acc3", ACC3 },
3927 { "accext01", ACCEXT01 },
3928 { "accext23", ACCEXT23 },
3929 { "macsr", MACSR },
3930 { "mask", MASK },
3931
3932 /* Control registers. */
3933 { "sfc", SFC }, /* Source Function Code. */
3934 { "sfcr", SFC },
3935 { "dfc", DFC }, /* Destination Function Code. */
3936 { "dfcr", DFC },
3937 { "cacr", CACR }, /* Cache Control Register. */
3938 { "caar", CAAR }, /* Cache Address Register. */
3939
3940 { "usp", USP }, /* User Stack Pointer. */
3941 { "vbr", VBR }, /* Vector Base Register. */
3942 { "msp", MSP }, /* Master Stack Pointer. */
3943 { "isp", ISP }, /* Interrupt Stack Pointer. */
3944
3945 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3946 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3947 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3948 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3949
3950 /* 68ec040 versions of same */
3951 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3952 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3953 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3954 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3955
3956 /* Coldfire versions of same. The ColdFire programmer's reference
3957 manual indicated that the order is 2,3,0,1, but Ken Rose
3958 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3959 { "acr0", ACR0 }, /* Access Control Unit 0. */
3960 { "acr1", ACR1 }, /* Access Control Unit 1. */
3961 { "acr2", ACR2 }, /* Access Control Unit 2. */
3962 { "acr3", ACR3 }, /* Access Control Unit 3. */
3963
3964 { "tc", TC }, /* MMU Translation Control Register. */
3965 { "tcr", TC },
3966 { "asid", ASID },
3967
3968 { "mmusr", MMUSR }, /* MMU Status Register. */
3969 { "srp", SRP }, /* User Root Pointer. */
3970 { "urp", URP }, /* Supervisor Root Pointer. */
3971
3972 { "buscr", BUSCR },
3973 { "mmubar", MMUBAR },
3974 { "pcr", PCR },
3975
3976 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3977 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3978 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3979 { "mbar", MBAR }, /* Module Base Address Register. */
3980
3981 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3982 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3983 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3984 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3985 { "mpcr", MPCR }, /* mcfv4e registers. */
3986 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3987 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3988 { "asid", TC }, /* mcfv4e registers. */
3989 { "mmubar", BUSCR }, /* mcfv4e registers. */
3990 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3991 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3992 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3993 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3994 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3995 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3996 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3997 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3998 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3999 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4000 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4001 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4002
4003 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4004 { "rambar", RAMBAR }, /* mcf528x registers. */
4005
4006 { "mbar2", MBAR2 }, /* mcf5249 registers. */
4007
4008 { "cac", CAC }, /* fido registers. */
4009 { "mbb", MBO }, /* fido registers (obsolete). */
4010 { "mbo", MBO }, /* fido registers. */
4011 /* End of control registers. */
4012
4013 { "ac", AC },
4014 { "bc", BC },
4015 { "cal", CAL },
4016 { "crp", CRP },
4017 { "drp", DRP },
4018 { "pcsr", PCSR },
4019 { "psr", PSR },
4020 { "scc", SCC },
4021 { "val", VAL },
4022 { "bad0", BAD0 },
4023 { "bad1", BAD1 },
4024 { "bad2", BAD2 },
4025 { "bad3", BAD3 },
4026 { "bad4", BAD4 },
4027 { "bad5", BAD5 },
4028 { "bad6", BAD6 },
4029 { "bad7", BAD7 },
4030 { "bac0", BAC0 },
4031 { "bac1", BAC1 },
4032 { "bac2", BAC2 },
4033 { "bac3", BAC3 },
4034 { "bac4", BAC4 },
4035 { "bac5", BAC5 },
4036 { "bac6", BAC6 },
4037 { "bac7", BAC7 },
4038
4039 { "ic", IC },
4040 { "dc", DC },
4041 { "nc", NC },
4042
4043 { "tt0", TT0 },
4044 { "tt1", TT1 },
4045 /* 68ec030 versions of same. */
4046 { "ac0", TT0 },
4047 { "ac1", TT1 },
4048 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4049 { "acusr", PSR },
4050
4051 /* Suppressed data and address registers. */
4052 { "zd0", ZDATA0 },
4053 { "zd1", ZDATA1 },
4054 { "zd2", ZDATA2 },
4055 { "zd3", ZDATA3 },
4056 { "zd4", ZDATA4 },
4057 { "zd5", ZDATA5 },
4058 { "zd6", ZDATA6 },
4059 { "zd7", ZDATA7 },
4060 { "za0", ZADDR0 },
4061 { "za1", ZADDR1 },
4062 { "za2", ZADDR2 },
4063 { "za3", ZADDR3 },
4064 { "za4", ZADDR4 },
4065 { "za5", ZADDR5 },
4066 { "za6", ZADDR6 },
4067 { "za7", ZADDR7 },
4068
4069 /* Upper and lower data and address registers, used by macw and msacw. */
4070 { "d0l", DATA0L },
4071 { "d1l", DATA1L },
4072 { "d2l", DATA2L },
4073 { "d3l", DATA3L },
4074 { "d4l", DATA4L },
4075 { "d5l", DATA5L },
4076 { "d6l", DATA6L },
4077 { "d7l", DATA7L },
4078
4079 { "a0l", ADDR0L },
4080 { "a1l", ADDR1L },
4081 { "a2l", ADDR2L },
4082 { "a3l", ADDR3L },
4083 { "a4l", ADDR4L },
4084 { "a5l", ADDR5L },
4085 { "a6l", ADDR6L },
4086 { "a7l", ADDR7L },
4087
4088 { "d0u", DATA0U },
4089 { "d1u", DATA1U },
4090 { "d2u", DATA2U },
4091 { "d3u", DATA3U },
4092 { "d4u", DATA4U },
4093 { "d5u", DATA5U },
4094 { "d6u", DATA6U },
4095 { "d7u", DATA7U },
4096
4097 { "a0u", ADDR0U },
4098 { "a1u", ADDR1U },
4099 { "a2u", ADDR2U },
4100 { "a3u", ADDR3U },
4101 { "a4u", ADDR4U },
4102 { "a5u", ADDR5U },
4103 { "a6u", ADDR6U },
4104 { "a7u", ADDR7U },
4105
4106 { 0, 0 }
4107 };
4108
4109 static void
4110 init_regtable (void)
4111 {
4112 int i;
4113 for (i = 0; init_table[i].name; i++)
4114 insert_reg (init_table[i].name, init_table[i].number);
4115 }
4116
4117 void
4118 md_assemble (char *str)
4119 {
4120 const char *er;
4121 short *fromP;
4122 char *toP = NULL;
4123 int m, n = 0;
4124 char *to_beg_P;
4125 int shorts_this_frag;
4126 fixS *fixP;
4127
4128 if (!selected_cpu && !selected_arch)
4129 {
4130 /* We've not selected an architecture yet. Set the default
4131 now. We do this lazily so that an initial .cpu or .arch directive
4132 can specify. */
4133 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4134 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4135 }
4136 if (!initialized)
4137 m68k_init_arch ();
4138
4139 /* In MRI mode, the instruction and operands are separated by a
4140 space. Anything following the operands is a comment. The label
4141 has already been removed. */
4142 if (flag_mri)
4143 {
4144 char *s;
4145 int fields = 0;
4146 int infield = 0;
4147 int inquote = 0;
4148
4149 for (s = str; *s != '\0'; s++)
4150 {
4151 if ((*s == ' ' || *s == '\t') && ! inquote)
4152 {
4153 if (infield)
4154 {
4155 ++fields;
4156 if (fields >= 2)
4157 {
4158 *s = '\0';
4159 break;
4160 }
4161 infield = 0;
4162 }
4163 }
4164 else
4165 {
4166 if (! infield)
4167 infield = 1;
4168 if (*s == '\'')
4169 inquote = ! inquote;
4170 }
4171 }
4172 }
4173
4174 memset (&the_ins, '\0', sizeof (the_ins));
4175 m68k_ip (str);
4176 er = the_ins.error;
4177 if (!er)
4178 {
4179 for (n = 0; n < the_ins.numargs; n++)
4180 if (the_ins.operands[n].error)
4181 {
4182 er = the_ins.operands[n].error;
4183 break;
4184 }
4185 }
4186 if (er)
4187 {
4188 as_bad (_("%s -- statement `%s' ignored"), er, str);
4189 return;
4190 }
4191
4192 /* If there is a current label, record that it marks an instruction. */
4193 if (current_label != NULL)
4194 {
4195 current_label->text = 1;
4196 current_label = NULL;
4197 }
4198
4199 #ifdef OBJ_ELF
4200 /* Tie dwarf2 debug info to the address at the start of the insn. */
4201 dwarf2_emit_insn (0);
4202 #endif
4203
4204 if (the_ins.nfrag == 0)
4205 {
4206 /* No frag hacking involved; just put it out. */
4207 toP = frag_more (2 * the_ins.numo);
4208 fromP = &the_ins.opcode[0];
4209 for (m = the_ins.numo; m; --m)
4210 {
4211 md_number_to_chars (toP, (long) (*fromP), 2);
4212 toP += 2;
4213 fromP++;
4214 }
4215 /* Put out symbol-dependent info. */
4216 for (m = 0; m < the_ins.nrel; m++)
4217 {
4218 switch (the_ins.reloc[m].wid)
4219 {
4220 case 'B':
4221 n = 1;
4222 break;
4223 case 'b':
4224 n = 1;
4225 break;
4226 case '3':
4227 n = 1;
4228 break;
4229 case 'w':
4230 case 'W':
4231 n = 2;
4232 break;
4233 case 'l':
4234 n = 4;
4235 break;
4236 default:
4237 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4238 the_ins.reloc[m].wid);
4239 }
4240
4241 fixP = fix_new_exp (frag_now,
4242 ((toP - frag_now->fr_literal)
4243 - the_ins.numo * 2 + the_ins.reloc[m].n),
4244 n,
4245 &the_ins.reloc[m].exp,
4246 the_ins.reloc[m].pcrel,
4247 get_reloc_code (n, the_ins.reloc[m].pcrel,
4248 the_ins.reloc[m].pic_reloc));
4249 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4250 if (the_ins.reloc[m].wid == 'B')
4251 fixP->fx_signed = 1;
4252 }
4253 return;
4254 }
4255
4256 /* There's some frag hacking. */
4257 {
4258 /* Calculate the max frag size. */
4259 int wid;
4260
4261 wid = 2 * the_ins.fragb[0].fragoff;
4262 for (n = 1; n < the_ins.nfrag; n++)
4263 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4264 /* frag_var part. */
4265 wid += FRAG_VAR_SIZE;
4266 /* Make sure the whole insn fits in one chunk, in particular that
4267 the var part is attached, as we access one byte before the
4268 variable frag for byte branches. */
4269 frag_grow (wid);
4270 }
4271
4272 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4273 {
4274 int wid;
4275
4276 if (n == 0)
4277 wid = 2 * the_ins.fragb[n].fragoff;
4278 else
4279 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4280 toP = frag_more (wid);
4281 to_beg_P = toP;
4282 shorts_this_frag = 0;
4283 for (m = wid / 2; m; --m)
4284 {
4285 md_number_to_chars (toP, (long) (*fromP), 2);
4286 toP += 2;
4287 fromP++;
4288 shorts_this_frag++;
4289 }
4290 for (m = 0; m < the_ins.nrel; m++)
4291 {
4292 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4293 {
4294 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4295 break;
4296 }
4297 wid = the_ins.reloc[m].wid;
4298 if (wid == 0)
4299 continue;
4300 the_ins.reloc[m].wid = 0;
4301 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4302
4303 fixP = fix_new_exp (frag_now,
4304 ((toP - frag_now->fr_literal)
4305 - the_ins.numo * 2 + the_ins.reloc[m].n),
4306 wid,
4307 &the_ins.reloc[m].exp,
4308 the_ins.reloc[m].pcrel,
4309 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4310 the_ins.reloc[m].pic_reloc));
4311 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4312 }
4313 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
4314 (relax_substateT) (the_ins.fragb[n].fragty),
4315 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4316 }
4317 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4318 shorts_this_frag = 0;
4319 if (n)
4320 {
4321 toP = frag_more (n * 2);
4322 while (n--)
4323 {
4324 md_number_to_chars (toP, (long) (*fromP), 2);
4325 toP += 2;
4326 fromP++;
4327 shorts_this_frag++;
4328 }
4329 }
4330 for (m = 0; m < the_ins.nrel; m++)
4331 {
4332 int wid;
4333
4334 wid = the_ins.reloc[m].wid;
4335 if (wid == 0)
4336 continue;
4337 the_ins.reloc[m].wid = 0;
4338 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4339
4340 fixP = fix_new_exp (frag_now,
4341 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4342 - shorts_this_frag * 2),
4343 wid,
4344 &the_ins.reloc[m].exp,
4345 the_ins.reloc[m].pcrel,
4346 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4347 the_ins.reloc[m].pic_reloc));
4348 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4349 }
4350 }
4351
4352 /* Comparison function used by qsort to rank the opcode entries by name. */
4353
4354 static int
4355 m68k_compare_opcode (const void * v1, const void * v2)
4356 {
4357 struct m68k_opcode * op1, * op2;
4358 int ret;
4359
4360 if (v1 == v2)
4361 return 0;
4362
4363 op1 = *(struct m68k_opcode **) v1;
4364 op2 = *(struct m68k_opcode **) v2;
4365
4366 /* Compare the two names. If different, return the comparison.
4367 If the same, return the order they are in the opcode table. */
4368 ret = strcmp (op1->name, op2->name);
4369 if (ret)
4370 return ret;
4371 if (op1 < op2)
4372 return -1;
4373 return 1;
4374 }
4375
4376 void
4377 md_begin (void)
4378 {
4379 const struct m68k_opcode *ins;
4380 struct m68k_incant *hack, *slak;
4381 const char *retval = 0; /* Empty string, or error msg text. */
4382 int i;
4383
4384 /* Set up hash tables with 68000 instructions.
4385 similar to what the vax assembler does. */
4386 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4387 a copy of it at runtime, adding in the information we want but isn't
4388 there. I think it'd be better to have an awk script hack the table
4389 at compile time. Or even just xstr the table and use it as-is. But
4390 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4391 names. */
4392
4393 if (flag_mri)
4394 {
4395 flag_reg_prefix_optional = 1;
4396 m68k_abspcadd = 1;
4397 if (! m68k_rel32_from_cmdline)
4398 m68k_rel32 = 0;
4399 }
4400
4401 /* First sort the opcode table into alphabetical order to seperate
4402 the order that the assembler wants to see the opcodes from the
4403 order that the disassembler wants to see them. */
4404 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4405 if (!m68k_sorted_opcodes)
4406 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4407 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4408
4409 for (i = m68k_numopcodes; i--;)
4410 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4411
4412 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4413 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4414
4415 op_hash = hash_new ();
4416
4417 obstack_begin (&robyn, 4000);
4418 for (i = 0; i < m68k_numopcodes; i++)
4419 {
4420 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4421 do
4422 {
4423 ins = m68k_sorted_opcodes[i];
4424
4425 /* We must enter all insns into the table, because .arch and
4426 .cpu directives can change things. */
4427 slak->m_operands = ins->args;
4428 slak->m_arch = ins->arch;
4429 slak->m_opcode = ins->opcode;
4430
4431 /* In most cases we can determine the number of opcode words
4432 by checking the second word of the mask. Unfortunately
4433 some instructions have 2 opcode words, but no fixed bits
4434 in the second word. A leading dot in the operands
4435 string also indicates 2 opcodes. */
4436 if (*slak->m_operands == '.')
4437 {
4438 slak->m_operands++;
4439 slak->m_codenum = 2;
4440 }
4441 else if (ins->match & 0xffffL)
4442 slak->m_codenum = 2;
4443 else
4444 slak->m_codenum = 1;
4445 slak->m_opnum = strlen (slak->m_operands) / 2;
4446
4447 if (i + 1 != m68k_numopcodes
4448 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4449 {
4450 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4451 i++;
4452 }
4453 else
4454 slak->m_next = 0;
4455 slak = slak->m_next;
4456 }
4457 while (slak);
4458
4459 retval = hash_insert (op_hash, ins->name, (char *) hack);
4460 if (retval)
4461 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4462 }
4463
4464 for (i = 0; i < m68k_numaliases; i++)
4465 {
4466 const char *name = m68k_opcode_aliases[i].primary;
4467 const char *alias = m68k_opcode_aliases[i].alias;
4468 PTR val = hash_find (op_hash, name);
4469
4470 if (!val)
4471 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4472 retval = hash_insert (op_hash, alias, val);
4473 if (retval)
4474 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4475 }
4476
4477 /* In MRI mode, all unsized branches are variable sized. Normally,
4478 they are word sized. */
4479 if (flag_mri)
4480 {
4481 static struct m68k_opcode_alias mri_aliases[] =
4482 {
4483 { "bhi", "jhi", },
4484 { "bls", "jls", },
4485 { "bcc", "jcc", },
4486 { "bcs", "jcs", },
4487 { "bne", "jne", },
4488 { "beq", "jeq", },
4489 { "bvc", "jvc", },
4490 { "bvs", "jvs", },
4491 { "bpl", "jpl", },
4492 { "bmi", "jmi", },
4493 { "bge", "jge", },
4494 { "blt", "jlt", },
4495 { "bgt", "jgt", },
4496 { "ble", "jle", },
4497 { "bra", "jra", },
4498 { "bsr", "jbsr", },
4499 };
4500
4501 for (i = 0;
4502 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4503 i++)
4504 {
4505 const char *name = mri_aliases[i].primary;
4506 const char *alias = mri_aliases[i].alias;
4507 PTR val = hash_find (op_hash, name);
4508
4509 if (!val)
4510 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4511 retval = hash_jam (op_hash, alias, val);
4512 if (retval)
4513 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4514 }
4515 }
4516
4517 for (i = 0; i < (int) sizeof (notend_table); i++)
4518 {
4519 notend_table[i] = 0;
4520 alt_notend_table[i] = 0;
4521 }
4522
4523 notend_table[','] = 1;
4524 notend_table['{'] = 1;
4525 notend_table['}'] = 1;
4526 alt_notend_table['a'] = 1;
4527 alt_notend_table['A'] = 1;
4528 alt_notend_table['d'] = 1;
4529 alt_notend_table['D'] = 1;
4530 alt_notend_table['#'] = 1;
4531 alt_notend_table['&'] = 1;
4532 alt_notend_table['f'] = 1;
4533 alt_notend_table['F'] = 1;
4534 #ifdef REGISTER_PREFIX
4535 alt_notend_table[REGISTER_PREFIX] = 1;
4536 #endif
4537
4538 /* We need to put '(' in alt_notend_table to handle
4539 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4540 alt_notend_table['('] = 1;
4541
4542 /* We need to put '@' in alt_notend_table to handle
4543 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4544 alt_notend_table['@'] = 1;
4545
4546 /* We need to put digits in alt_notend_table to handle
4547 bfextu %d0{24:1},%d0 */
4548 alt_notend_table['0'] = 1;
4549 alt_notend_table['1'] = 1;
4550 alt_notend_table['2'] = 1;
4551 alt_notend_table['3'] = 1;
4552 alt_notend_table['4'] = 1;
4553 alt_notend_table['5'] = 1;
4554 alt_notend_table['6'] = 1;
4555 alt_notend_table['7'] = 1;
4556 alt_notend_table['8'] = 1;
4557 alt_notend_table['9'] = 1;
4558
4559 #ifndef MIT_SYNTAX_ONLY
4560 /* Insert pseudo ops, these have to go into the opcode table since
4561 gas expects pseudo ops to start with a dot. */
4562 {
4563 int n = 0;
4564
4565 while (mote_pseudo_table[n].poc_name)
4566 {
4567 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4568 hash_insert (op_hash,
4569 mote_pseudo_table[n].poc_name, (char *) hack);
4570 hack->m_operands = 0;
4571 hack->m_opnum = n;
4572 n++;
4573 }
4574 }
4575 #endif
4576
4577 init_regtable ();
4578
4579 #ifdef OBJ_ELF
4580 record_alignment (text_section, 2);
4581 record_alignment (data_section, 2);
4582 record_alignment (bss_section, 2);
4583 #endif
4584 }
4585
4586 \f
4587 /* This is called when a label is defined. */
4588
4589 void
4590 m68k_frob_label (symbolS *sym)
4591 {
4592 struct label_line *n;
4593
4594 n = (struct label_line *) xmalloc (sizeof *n);
4595 n->next = labels;
4596 n->label = sym;
4597 as_where (&n->file, &n->line);
4598 n->text = 0;
4599 labels = n;
4600 current_label = n;
4601
4602 #ifdef OBJ_ELF
4603 dwarf2_emit_label (sym);
4604 #endif
4605 }
4606
4607 /* This is called when a value that is not an instruction is emitted. */
4608
4609 void
4610 m68k_flush_pending_output (void)
4611 {
4612 current_label = NULL;
4613 }
4614
4615 /* This is called at the end of the assembly, when the final value of
4616 the label is known. We warn if this is a text symbol aligned at an
4617 odd location. */
4618
4619 void
4620 m68k_frob_symbol (symbolS *sym)
4621 {
4622 if (S_GET_SEGMENT (sym) == reg_section
4623 && (int) S_GET_VALUE (sym) < 0)
4624 {
4625 S_SET_SEGMENT (sym, absolute_section);
4626 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4627 }
4628 else if ((S_GET_VALUE (sym) & 1) != 0)
4629 {
4630 struct label_line *l;
4631
4632 for (l = labels; l != NULL; l = l->next)
4633 {
4634 if (l->label == sym)
4635 {
4636 if (l->text)
4637 as_warn_where (l->file, l->line,
4638 _("text label `%s' aligned to odd boundary"),
4639 S_GET_NAME (sym));
4640 break;
4641 }
4642 }
4643 }
4644 }
4645 \f
4646 /* This is called if we go in or out of MRI mode because of the .mri
4647 pseudo-op. */
4648
4649 void
4650 m68k_mri_mode_change (int on)
4651 {
4652 if (on)
4653 {
4654 if (! flag_reg_prefix_optional)
4655 {
4656 flag_reg_prefix_optional = 1;
4657 #ifdef REGISTER_PREFIX
4658 init_regtable ();
4659 #endif
4660 }
4661 m68k_abspcadd = 1;
4662 if (! m68k_rel32_from_cmdline)
4663 m68k_rel32 = 0;
4664 }
4665 else
4666 {
4667 if (! reg_prefix_optional_seen)
4668 {
4669 #ifdef REGISTER_PREFIX_OPTIONAL
4670 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4671 #else
4672 flag_reg_prefix_optional = 0;
4673 #endif
4674 #ifdef REGISTER_PREFIX
4675 init_regtable ();
4676 #endif
4677 }
4678 m68k_abspcadd = 0;
4679 if (! m68k_rel32_from_cmdline)
4680 m68k_rel32 = 1;
4681 }
4682 }
4683
4684 /* Equal to MAX_PRECISION in atof-ieee.c. */
4685 #define MAX_LITTLENUMS 6
4686
4687 /* Turn a string in input_line_pointer into a floating point constant
4688 of type TYPE, and store the appropriate bytes in *LITP. The number
4689 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4690 returned, or NULL on OK. */
4691
4692 char *
4693 md_atof (int type, char *litP, int *sizeP)
4694 {
4695 int prec;
4696 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4697 LITTLENUM_TYPE *wordP;
4698 char *t;
4699
4700 switch (type)
4701 {
4702 case 'f':
4703 case 'F':
4704 case 's':
4705 case 'S':
4706 prec = 2;
4707 break;
4708
4709 case 'd':
4710 case 'D':
4711 case 'r':
4712 case 'R':
4713 prec = 4;
4714 break;
4715
4716 case 'x':
4717 case 'X':
4718 prec = 6;
4719 break;
4720
4721 case 'p':
4722 case 'P':
4723 prec = 6;
4724 break;
4725
4726 default:
4727 *sizeP = 0;
4728 return _("Bad call to MD_ATOF()");
4729 }
4730 t = atof_ieee (input_line_pointer, type, words);
4731 if (t)
4732 input_line_pointer = t;
4733
4734 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4735 for (wordP = words; prec--;)
4736 {
4737 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4738 litP += sizeof (LITTLENUM_TYPE);
4739 }
4740 return 0;
4741 }
4742
4743 void
4744 md_number_to_chars (char *buf, valueT val, int n)
4745 {
4746 number_to_chars_bigendian (buf, val, n);
4747 }
4748
4749 void
4750 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4751 {
4752 offsetT val = *valP;
4753 addressT upper_limit;
4754 offsetT lower_limit;
4755
4756 /* This is unnecessary but it convinces the native rs6000 compiler
4757 to generate the code we want. */
4758 char *buf = fixP->fx_frag->fr_literal;
4759 buf += fixP->fx_where;
4760 /* End ibm compiler workaround. */
4761
4762 val = SEXT (val);
4763
4764 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4765 fixP->fx_done = 1;
4766
4767 #ifdef OBJ_ELF
4768 if (fixP->fx_addsy)
4769 {
4770 memset (buf, 0, fixP->fx_size);
4771 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4772
4773 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4774 && !S_IS_DEFINED (fixP->fx_addsy)
4775 && !S_IS_WEAK (fixP->fx_addsy))
4776 S_SET_WEAK (fixP->fx_addsy);
4777 return;
4778 }
4779 #elif defined(OBJ_AOUT)
4780 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4781 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4782 {
4783 memset (buf, 0, fixP->fx_size);
4784 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4785 return;
4786 }
4787 #endif
4788
4789 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4790 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4791 return;
4792
4793 switch (fixP->fx_size)
4794 {
4795 /* The cast to offsetT below are necessary to make code
4796 correct for machines where ints are smaller than offsetT. */
4797 case 1:
4798 *buf++ = val;
4799 upper_limit = 0x7f;
4800 lower_limit = - (offsetT) 0x80;
4801 break;
4802 case 2:
4803 *buf++ = (val >> 8);
4804 *buf++ = val;
4805 upper_limit = 0x7fff;
4806 lower_limit = - (offsetT) 0x8000;
4807 break;
4808 case 4:
4809 *buf++ = (val >> 24);
4810 *buf++ = (val >> 16);
4811 *buf++ = (val >> 8);
4812 *buf++ = val;
4813 upper_limit = 0x7fffffff;
4814 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4815 break;
4816 default:
4817 BAD_CASE (fixP->fx_size);
4818 }
4819
4820 /* Fix up a negative reloc. */
4821 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4822 {
4823 fixP->fx_addsy = fixP->fx_subsy;
4824 fixP->fx_subsy = NULL;
4825 fixP->fx_tcbit = 1;
4826 }
4827
4828 /* For non-pc-relative values, it's conceivable we might get something
4829 like "0xff" for a byte field. So extend the upper part of the range
4830 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4831 so that we can do any range checking at all. */
4832 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4833 upper_limit = upper_limit * 2 + 1;
4834
4835 if ((addressT) val > upper_limit
4836 && (val > 0 || val < lower_limit))
4837 as_bad_where (fixP->fx_file, fixP->fx_line,
4838 _("value %ld out of range"), (long)val);
4839
4840 /* A one byte PC-relative reloc means a short branch. We can't use
4841 a short branch with a value of 0 or -1, because those indicate
4842 different opcodes (branches with longer offsets). fixup_segment
4843 in write.c may have clobbered fx_pcrel, so we need to examine the
4844 reloc type. */
4845 if ((fixP->fx_pcrel
4846 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4847 && fixP->fx_size == 1
4848 && (fixP->fx_addsy == NULL
4849 || S_IS_DEFINED (fixP->fx_addsy))
4850 && (val == 0 || val == -1))
4851 as_bad_where (fixP->fx_file, fixP->fx_line,
4852 _("invalid byte branch offset"));
4853 }
4854
4855 /* *fragP has been relaxed to its final size, and now needs to have
4856 the bytes inside it modified to conform to the new size There is UGLY
4857 MAGIC here. ..
4858 */
4859 static void
4860 md_convert_frag_1 (fragS *fragP)
4861 {
4862 long disp;
4863 fixS *fixP = NULL;
4864
4865 /* Address in object code of the displacement. */
4866 register int object_address = fragP->fr_fix + fragP->fr_address;
4867
4868 /* Address in gas core of the place to store the displacement. */
4869 /* This convinces the native rs6000 compiler to generate the code we
4870 want. */
4871 register char *buffer_address = fragP->fr_literal;
4872 buffer_address += fragP->fr_fix;
4873 /* End ibm compiler workaround. */
4874
4875 /* The displacement of the address, from current location. */
4876 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4877 disp = (disp + fragP->fr_offset) - object_address;
4878
4879 switch (fragP->fr_subtype)
4880 {
4881 case TAB (BRANCHBWL, BYTE):
4882 case TAB (BRABSJUNC, BYTE):
4883 case TAB (BRABSJCOND, BYTE):
4884 case TAB (BRANCHBW, BYTE):
4885 case TAB (BRANCHBWPL, BYTE):
4886 know (issbyte (disp));
4887 if (disp == 0)
4888 as_bad_where (fragP->fr_file, fragP->fr_line,
4889 _("short branch with zero offset: use :w"));
4890 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4891 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4892 fixP->fx_pcrel_adjust = -1;
4893 break;
4894 case TAB (BRANCHBWL, SHORT):
4895 case TAB (BRABSJUNC, SHORT):
4896 case TAB (BRABSJCOND, SHORT):
4897 case TAB (BRANCHBW, SHORT):
4898 case TAB (BRANCHBWPL, SHORT):
4899 fragP->fr_opcode[1] = 0x00;
4900 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4901 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4902 fragP->fr_fix += 2;
4903 break;
4904 case TAB (BRANCHBWL, LONG):
4905 fragP->fr_opcode[1] = (char) 0xFF;
4906 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4907 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4908 fragP->fr_fix += 4;
4909 break;
4910 case TAB (BRANCHBWPL, LONG):
4911 /* Here we are converting an unconditional branch into a pair of
4912 conditional branches, in order to get the range. */
4913 fragP->fr_opcode[0] = 0x66; /* bne */
4914 fragP->fr_opcode[1] = 0xFF;
4915 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4916 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4917 fixP->fx_file = fragP->fr_file;
4918 fixP->fx_line = fragP->fr_line;
4919 fragP->fr_fix += 4; /* Skip first offset */
4920 buffer_address += 4;
4921 *buffer_address++ = 0x67; /* beq */
4922 *buffer_address++ = 0xff;
4923 fragP->fr_fix += 2; /* Skip second branch opcode */
4924 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4925 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4926 fragP->fr_fix += 4;
4927 break;
4928 case TAB (BRABSJUNC, LONG):
4929 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4930 {
4931 if (flag_keep_pcrel)
4932 as_bad_where (fragP->fr_file, fragP->fr_line,
4933 _("Conversion of PC relative BSR to absolute JSR"));
4934 fragP->fr_opcode[0] = 0x4E;
4935 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4936 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4937 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4938 fragP->fr_fix += 4;
4939 }
4940 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4941 {
4942 if (flag_keep_pcrel)
4943 as_bad_where (fragP->fr_file, fragP->fr_line,
4944 _("Conversion of PC relative branch to absolute jump"));
4945 fragP->fr_opcode[0] = 0x4E;
4946 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4947 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4948 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4949 fragP->fr_fix += 4;
4950 }
4951 else
4952 {
4953 /* This cannot happen, because jbsr and jbra are the only two
4954 unconditional branches. */
4955 abort ();
4956 }
4957 break;
4958 case TAB (BRABSJCOND, LONG):
4959 if (flag_keep_pcrel)
4960 as_bad_where (fragP->fr_file, fragP->fr_line,
4961 _("Conversion of PC relative conditional branch to absolute jump"));
4962
4963 /* Only Bcc 68000 instructions can come here
4964 Change bcc into b!cc/jmp absl long. */
4965 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4966 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4967
4968 /* JF: these used to be fr_opcode[2,3], but they may be in a
4969 different frag, in which case referring to them is a no-no.
4970 Only fr_opcode[0,1] are guaranteed to work. */
4971 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4972 *buffer_address++ = (char) 0xf9;
4973 fragP->fr_fix += 2; /* Account for jmp instruction. */
4974 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4975 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4976 fragP->fr_fix += 4;
4977 break;
4978 case TAB (FBRANCH, SHORT):
4979 know ((fragP->fr_opcode[1] & 0x40) == 0);
4980 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4981 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4982 fragP->fr_fix += 2;
4983 break;
4984 case TAB (FBRANCH, LONG):
4985 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4986 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4987 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4988 fragP->fr_fix += 4;
4989 break;
4990 case TAB (DBCCLBR, SHORT):
4991 case TAB (DBCCABSJ, SHORT):
4992 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4993 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4994 fragP->fr_fix += 2;
4995 break;
4996 case TAB (DBCCLBR, LONG):
4997 /* Only DBcc instructions can come here.
4998 Change dbcc into dbcc/bral.
4999 JF: these used to be fr_opcode[2-7], but that's wrong. */
5000 if (flag_keep_pcrel)
5001 as_bad_where (fragP->fr_file, fragP->fr_line,
5002 _("Conversion of DBcc to absolute jump"));
5003
5004 *buffer_address++ = 0x00; /* Branch offset = 4. */
5005 *buffer_address++ = 0x04;
5006 *buffer_address++ = 0x60; /* Put in bra pc+6. */
5007 *buffer_address++ = 0x06;
5008 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5009 *buffer_address++ = (char) 0xff;
5010
5011 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5012 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5013 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5014 fragP->fr_fix += 4;
5015 break;
5016 case TAB (DBCCABSJ, LONG):
5017 /* Only DBcc instructions can come here.
5018 Change dbcc into dbcc/jmp.
5019 JF: these used to be fr_opcode[2-7], but that's wrong. */
5020 if (flag_keep_pcrel)
5021 as_bad_where (fragP->fr_file, fragP->fr_line,
5022 _("Conversion of PC relative conditional branch to absolute jump"));
5023
5024 *buffer_address++ = 0x00; /* Branch offset = 4. */
5025 *buffer_address++ = 0x04;
5026 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
5027 *buffer_address++ = 0x06;
5028 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
5029 *buffer_address++ = (char) 0xf9;
5030
5031 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5032 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5033 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5034 fragP->fr_fix += 4;
5035 break;
5036 case TAB (PCREL1632, SHORT):
5037 fragP->fr_opcode[1] &= ~0x3F;
5038 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
5039 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5040 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5041 fragP->fr_fix += 2;
5042 break;
5043 case TAB (PCREL1632, LONG):
5044 /* Already set to mode 7.3; this indicates: PC indirect with
5045 suppressed index, 32-bit displacement. */
5046 *buffer_address++ = 0x01;
5047 *buffer_address++ = 0x70;
5048 fragP->fr_fix += 2;
5049 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5050 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5051 fixP->fx_pcrel_adjust = 2;
5052 fragP->fr_fix += 4;
5053 break;
5054 case TAB (PCINDEX, BYTE):
5055 assert (fragP->fr_fix >= 2);
5056 buffer_address[-2] &= ~1;
5057 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5058 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5059 fixP->fx_pcrel_adjust = 1;
5060 break;
5061 case TAB (PCINDEX, SHORT):
5062 assert (fragP->fr_fix >= 2);
5063 buffer_address[-2] |= 0x1;
5064 buffer_address[-1] = 0x20;
5065 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5066 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5067 fixP->fx_pcrel_adjust = 2;
5068 fragP->fr_fix += 2;
5069 break;
5070 case TAB (PCINDEX, LONG):
5071 assert (fragP->fr_fix >= 2);
5072 buffer_address[-2] |= 0x1;
5073 buffer_address[-1] = 0x30;
5074 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5075 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5076 fixP->fx_pcrel_adjust = 2;
5077 fragP->fr_fix += 4;
5078 break;
5079 case TAB (ABSTOPCREL, SHORT):
5080 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5081 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5082 fragP->fr_fix += 2;
5083 break;
5084 case TAB (ABSTOPCREL, LONG):
5085 if (flag_keep_pcrel)
5086 as_fatal (_("Conversion of PC relative displacement to absolute"));
5087 /* The thing to do here is force it to ABSOLUTE LONG, since
5088 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5089 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5090 abort ();
5091 fragP->fr_opcode[1] &= ~0x3F;
5092 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
5093 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5094 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5095 fragP->fr_fix += 4;
5096 break;
5097 }
5098 if (fixP)
5099 {
5100 fixP->fx_file = fragP->fr_file;
5101 fixP->fx_line = fragP->fr_line;
5102 }
5103 }
5104
5105 void
5106 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5107 segT sec ATTRIBUTE_UNUSED,
5108 fragS *fragP)
5109 {
5110 md_convert_frag_1 (fragP);
5111 }
5112
5113 /* Force truly undefined symbols to their maximum size, and generally set up
5114 the frag list to be relaxed
5115 */
5116 int
5117 md_estimate_size_before_relax (fragS *fragP, segT segment)
5118 {
5119 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5120 switch (fragP->fr_subtype)
5121 {
5122 case TAB (BRANCHBWL, SZ_UNDEF):
5123 case TAB (BRANCHBWPL, SZ_UNDEF):
5124 case TAB (BRABSJUNC, SZ_UNDEF):
5125 case TAB (BRABSJCOND, SZ_UNDEF):
5126 {
5127 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5128 && relaxable_symbol (fragP->fr_symbol))
5129 {
5130 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5131 }
5132 else if (flag_short_refs)
5133 {
5134 /* Symbol is undefined and we want short ref. */
5135 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5136 }
5137 else
5138 {
5139 /* Symbol is still undefined. Make it LONG. */
5140 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5141 }
5142 break;
5143 }
5144
5145 case TAB (BRANCHBW, SZ_UNDEF):
5146 {
5147 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5148 && relaxable_symbol (fragP->fr_symbol))
5149 {
5150 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5151 }
5152 else
5153 {
5154 /* Symbol is undefined and we don't have long branches. */
5155 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5156 }
5157 break;
5158 }
5159
5160 case TAB (FBRANCH, SZ_UNDEF):
5161 case TAB (DBCCLBR, SZ_UNDEF):
5162 case TAB (DBCCABSJ, SZ_UNDEF):
5163 case TAB (PCREL1632, SZ_UNDEF):
5164 {
5165 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5166 && relaxable_symbol (fragP->fr_symbol))
5167 || flag_short_refs)
5168 {
5169 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5170 }
5171 else
5172 {
5173 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5174 }
5175 break;
5176 }
5177
5178 case TAB (PCINDEX, SZ_UNDEF):
5179 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5180 && relaxable_symbol (fragP->fr_symbol)))
5181 {
5182 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5183 }
5184 else
5185 {
5186 fragP->fr_subtype = TAB (PCINDEX, LONG);
5187 }
5188 break;
5189
5190 case TAB (ABSTOPCREL, SZ_UNDEF):
5191 {
5192 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5193 && relaxable_symbol (fragP->fr_symbol)))
5194 {
5195 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5196 }
5197 else
5198 {
5199 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5200 }
5201 break;
5202 }
5203
5204 default:
5205 break;
5206 }
5207
5208 /* Now that SZ_UNDEF are taken care of, check others. */
5209 switch (fragP->fr_subtype)
5210 {
5211 case TAB (BRANCHBWL, BYTE):
5212 case TAB (BRABSJUNC, BYTE):
5213 case TAB (BRABSJCOND, BYTE):
5214 case TAB (BRANCHBW, BYTE):
5215 /* We can't do a short jump to the next instruction, so in that
5216 case we force word mode. If the symbol is at the start of a
5217 frag, and it is the next frag with any data in it (usually
5218 this is just the next frag, but assembler listings may
5219 introduce empty frags), we must use word mode. */
5220 if (fragP->fr_symbol)
5221 {
5222 fragS *sym_frag;
5223
5224 sym_frag = symbol_get_frag (fragP->fr_symbol);
5225 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5226 {
5227 fragS *l;
5228
5229 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5230 if (l->fr_fix != 0)
5231 break;
5232 if (l == sym_frag)
5233 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5234 }
5235 }
5236 break;
5237 default:
5238 break;
5239 }
5240 return md_relax_table[fragP->fr_subtype].rlx_length;
5241 }
5242
5243 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5244 /* the bit-field entries in the relocation_info struct plays hell
5245 with the byte-order problems of cross-assembly. So as a hack,
5246 I added this mach. dependent ri twiddler. Ugly, but it gets
5247 you there. -KWK */
5248 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5249 are symbolnum, most sig. byte first. Last byte is broken up with
5250 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5251 nibble as nuthin. (on Sun 3 at least) */
5252 /* Translate the internal relocation information into target-specific
5253 format. */
5254 #ifdef comment
5255 void
5256 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5257 {
5258 /* This is easy. */
5259 md_number_to_chars (the_bytes, ri->r_address, 4);
5260 /* Now the fun stuff. */
5261 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5262 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5263 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5264 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5265 | ((ri->r_length << 5) & 0x60)
5266 | ((ri->r_extern << 4) & 0x10));
5267 }
5268
5269 #endif
5270
5271 #endif /* OBJ_AOUT or OBJ_BOUT */
5272
5273 #ifndef WORKING_DOT_WORD
5274 int md_short_jump_size = 4;
5275 int md_long_jump_size = 6;
5276
5277 void
5278 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5279 fragS *frag ATTRIBUTE_UNUSED,
5280 symbolS *to_symbol ATTRIBUTE_UNUSED)
5281 {
5282 valueT offset;
5283
5284 offset = to_addr - (from_addr + 2);
5285
5286 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5287 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5288 }
5289
5290 void
5291 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5292 fragS *frag, symbolS *to_symbol)
5293 {
5294 valueT offset;
5295
5296 if (!HAVE_LONG_BRANCH (current_architecture))
5297 {
5298 if (flag_keep_pcrel)
5299 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5300 offset = to_addr - S_GET_VALUE (to_symbol);
5301 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5302 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5303 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5304 0, NO_RELOC);
5305 }
5306 else
5307 {
5308 offset = to_addr - (from_addr + 2);
5309 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5310 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5311 }
5312 }
5313
5314 #endif
5315
5316 /* Different values of OK tell what its OK to return. Things that
5317 aren't OK are an error (what a shock, no?)
5318
5319 0: Everything is OK
5320 10: Absolute 1:8 only
5321 20: Absolute 0:7 only
5322 30: absolute 0:15 only
5323 40: Absolute 0:31 only
5324 50: absolute 0:127 only
5325 55: absolute -64:63 only
5326 60: absolute -128:127 only
5327 65: absolute 0:511 only
5328 70: absolute 0:4095 only
5329 80: absolute -1, 1:7 only
5330 90: No bignums. */
5331
5332 static int
5333 get_num (struct m68k_exp *exp, int ok)
5334 {
5335 if (exp->exp.X_op == O_absent)
5336 {
5337 /* Do the same thing the VAX asm does. */
5338 op (exp) = O_constant;
5339 adds (exp) = 0;
5340 subs (exp) = 0;
5341 offs (exp) = 0;
5342 if (ok == 10)
5343 {
5344 as_warn (_("expression out of range: defaulting to 1"));
5345 offs (exp) = 1;
5346 }
5347 }
5348 else if (exp->exp.X_op == O_constant)
5349 {
5350 switch (ok)
5351 {
5352 case 10:
5353 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5354 {
5355 as_warn (_("expression out of range: defaulting to 1"));
5356 offs (exp) = 1;
5357 }
5358 break;
5359 case 20:
5360 if ((valueT) TRUNC (offs (exp)) > 7)
5361 goto outrange;
5362 break;
5363 case 30:
5364 if ((valueT) TRUNC (offs (exp)) > 15)
5365 goto outrange;
5366 break;
5367 case 40:
5368 if ((valueT) TRUNC (offs (exp)) > 32)
5369 goto outrange;
5370 break;
5371 case 50:
5372 if ((valueT) TRUNC (offs (exp)) > 127)
5373 goto outrange;
5374 break;
5375 case 55:
5376 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5377 goto outrange;
5378 break;
5379 case 60:
5380 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5381 goto outrange;
5382 break;
5383 case 65:
5384 if ((valueT) TRUNC (offs (exp)) > 511)
5385 goto outrange;
5386 break;
5387 case 70:
5388 if ((valueT) TRUNC (offs (exp)) > 4095)
5389 {
5390 outrange:
5391 as_warn (_("expression out of range: defaulting to 0"));
5392 offs (exp) = 0;
5393 }
5394 break;
5395 case 80:
5396 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5397 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5398 {
5399 as_warn (_("expression out of range: defaulting to 1"));
5400 offs (exp) = 1;
5401 }
5402 break;
5403 default:
5404 break;
5405 }
5406 }
5407 else if (exp->exp.X_op == O_big)
5408 {
5409 if (offs (exp) <= 0 /* flonum. */
5410 && (ok == 90 /* no bignums */
5411 || (ok > 10 /* Small-int ranges including 0 ok. */
5412 /* If we have a flonum zero, a zero integer should
5413 do as well (e.g., in moveq). */
5414 && generic_floating_point_number.exponent == 0
5415 && generic_floating_point_number.low[0] == 0)))
5416 {
5417 /* HACK! Turn it into a long. */
5418 LITTLENUM_TYPE words[6];
5419
5420 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5421 op (exp) = O_constant;
5422 adds (exp) = 0;
5423 subs (exp) = 0;
5424 offs (exp) = words[1] | (words[0] << 16);
5425 }
5426 else if (ok != 0)
5427 {
5428 op (exp) = O_constant;
5429 adds (exp) = 0;
5430 subs (exp) = 0;
5431 offs (exp) = (ok == 10) ? 1 : 0;
5432 as_warn (_("Can't deal with expression; defaulting to %ld"),
5433 (long) offs (exp));
5434 }
5435 }
5436 else
5437 {
5438 if (ok >= 10 && ok <= 80)
5439 {
5440 op (exp) = O_constant;
5441 adds (exp) = 0;
5442 subs (exp) = 0;
5443 offs (exp) = (ok == 10) ? 1 : 0;
5444 as_warn (_("Can't deal with expression; defaulting to %ld"),
5445 (long) offs (exp));
5446 }
5447 }
5448
5449 if (exp->size != SIZE_UNSPEC)
5450 {
5451 switch (exp->size)
5452 {
5453 case SIZE_UNSPEC:
5454 case SIZE_LONG:
5455 break;
5456 case SIZE_BYTE:
5457 if (!isbyte (offs (exp)))
5458 as_warn (_("expression doesn't fit in BYTE"));
5459 break;
5460 case SIZE_WORD:
5461 if (!isword (offs (exp)))
5462 as_warn (_("expression doesn't fit in WORD"));
5463 break;
5464 }
5465 }
5466
5467 return offs (exp);
5468 }
5469
5470 /* These are the back-ends for the various machine dependent pseudo-ops. */
5471
5472 static void
5473 s_data1 (int ignore ATTRIBUTE_UNUSED)
5474 {
5475 subseg_set (data_section, 1);
5476 demand_empty_rest_of_line ();
5477 }
5478
5479 static void
5480 s_data2 (int ignore ATTRIBUTE_UNUSED)
5481 {
5482 subseg_set (data_section, 2);
5483 demand_empty_rest_of_line ();
5484 }
5485
5486 static void
5487 s_bss (int ignore ATTRIBUTE_UNUSED)
5488 {
5489 /* We don't support putting frags in the BSS segment, we fake it
5490 by marking in_bss, then looking at s_skip for clues. */
5491
5492 subseg_set (bss_section, 0);
5493 demand_empty_rest_of_line ();
5494 }
5495
5496 static void
5497 s_even (int ignore ATTRIBUTE_UNUSED)
5498 {
5499 register int temp;
5500 register long temp_fill;
5501
5502 temp = 1; /* JF should be 2? */
5503 temp_fill = get_absolute_expression ();
5504 if (!need_pass_2) /* Never make frag if expect extra pass. */
5505 frag_align (temp, (int) temp_fill, 0);
5506 demand_empty_rest_of_line ();
5507 record_alignment (now_seg, temp);
5508 }
5509
5510 static void
5511 s_proc (int ignore ATTRIBUTE_UNUSED)
5512 {
5513 demand_empty_rest_of_line ();
5514 }
5515 \f
5516 /* Pseudo-ops handled for MRI compatibility. */
5517
5518 /* This function returns non-zero if the argument is a conditional
5519 pseudo-op. This is called when checking whether a pending
5520 alignment is needed. */
5521
5522 int
5523 m68k_conditional_pseudoop (pseudo_typeS *pop)
5524 {
5525 return (pop->poc_handler == s_mri_if
5526 || pop->poc_handler == s_mri_else);
5527 }
5528
5529 /* Handle an MRI style chip specification. */
5530
5531 static void
5532 mri_chip (void)
5533 {
5534 char *s;
5535 char c;
5536 int i;
5537
5538 s = input_line_pointer;
5539 /* We can't use get_symbol_end since the processor names are not proper
5540 symbols. */
5541 while (is_part_of_name (c = *input_line_pointer++))
5542 ;
5543 *--input_line_pointer = 0;
5544 for (i = 0; m68k_cpus[i].name; i++)
5545 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5546 break;
5547 if (!m68k_cpus[i].name)
5548 {
5549 as_bad (_("%s: unrecognized processor name"), s);
5550 *input_line_pointer = c;
5551 ignore_rest_of_line ();
5552 return;
5553 }
5554 *input_line_pointer = c;
5555
5556 if (*input_line_pointer == '/')
5557 current_architecture = 0;
5558 else
5559 current_architecture &= m68881 | m68851;
5560 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5561 control_regs = m68k_cpus[i].control_regs;
5562
5563 while (*input_line_pointer == '/')
5564 {
5565 ++input_line_pointer;
5566 s = input_line_pointer;
5567 /* We can't use get_symbol_end since the processor names are not
5568 proper symbols. */
5569 while (is_part_of_name (c = *input_line_pointer++))
5570 ;
5571 *--input_line_pointer = 0;
5572 if (strcmp (s, "68881") == 0)
5573 current_architecture |= m68881;
5574 else if (strcmp (s, "68851") == 0)
5575 current_architecture |= m68851;
5576 *input_line_pointer = c;
5577 }
5578 }
5579
5580 /* The MRI CHIP pseudo-op. */
5581
5582 static void
5583 s_chip (int ignore ATTRIBUTE_UNUSED)
5584 {
5585 char *stop = NULL;
5586 char stopc;
5587
5588 if (flag_mri)
5589 stop = mri_comment_field (&stopc);
5590 mri_chip ();
5591 if (flag_mri)
5592 mri_comment_end (stop, stopc);
5593 demand_empty_rest_of_line ();
5594 }
5595
5596 /* The MRI FOPT pseudo-op. */
5597
5598 static void
5599 s_fopt (int ignore ATTRIBUTE_UNUSED)
5600 {
5601 SKIP_WHITESPACE ();
5602
5603 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5604 {
5605 int temp;
5606
5607 input_line_pointer += 3;
5608 temp = get_absolute_expression ();
5609 if (temp < 0 || temp > 7)
5610 as_bad (_("bad coprocessor id"));
5611 else
5612 m68k_float_copnum = COP0 + temp;
5613 }
5614 else
5615 {
5616 as_bad (_("unrecognized fopt option"));
5617 ignore_rest_of_line ();
5618 return;
5619 }
5620
5621 demand_empty_rest_of_line ();
5622 }
5623
5624 /* The structure used to handle the MRI OPT pseudo-op. */
5625
5626 struct opt_action
5627 {
5628 /* The name of the option. */
5629 const char *name;
5630
5631 /* If this is not NULL, just call this function. The first argument
5632 is the ARG field of this structure, the second argument is
5633 whether the option was negated. */
5634 void (*pfn) (int arg, int on);
5635
5636 /* If this is not NULL, and the PFN field is NULL, set the variable
5637 this points to. Set it to the ARG field if the option was not
5638 negated, and the NOTARG field otherwise. */
5639 int *pvar;
5640
5641 /* The value to pass to PFN or to assign to *PVAR. */
5642 int arg;
5643
5644 /* The value to assign to *PVAR if the option is negated. If PFN is
5645 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5646 the option may not be negated. */
5647 int notarg;
5648 };
5649
5650 /* The table used to handle the MRI OPT pseudo-op. */
5651
5652 static void skip_to_comma (int, int);
5653 static void opt_nest (int, int);
5654 static void opt_chip (int, int);
5655 static void opt_list (int, int);
5656 static void opt_list_symbols (int, int);
5657
5658 static const struct opt_action opt_table[] =
5659 {
5660 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5661
5662 /* We do relaxing, so there is little use for these options. */
5663 { "b", 0, 0, 0, 0 },
5664 { "brs", 0, 0, 0, 0 },
5665 { "brb", 0, 0, 0, 0 },
5666 { "brl", 0, 0, 0, 0 },
5667 { "brw", 0, 0, 0, 0 },
5668
5669 { "c", 0, 0, 0, 0 },
5670 { "cex", 0, 0, 0, 0 },
5671 { "case", 0, &symbols_case_sensitive, 1, 0 },
5672 { "cl", 0, 0, 0, 0 },
5673 { "cre", 0, 0, 0, 0 },
5674 { "d", 0, &flag_keep_locals, 1, 0 },
5675 { "e", 0, 0, 0, 0 },
5676 { "f", 0, &flag_short_refs, 1, 0 },
5677 { "frs", 0, &flag_short_refs, 1, 0 },
5678 { "frl", 0, &flag_short_refs, 0, 1 },
5679 { "g", 0, 0, 0, 0 },
5680 { "i", 0, 0, 0, 0 },
5681 { "m", 0, 0, 0, 0 },
5682 { "mex", 0, 0, 0, 0 },
5683 { "mc", 0, 0, 0, 0 },
5684 { "md", 0, 0, 0, 0 },
5685 { "nest", opt_nest, 0, 0, 0 },
5686 { "next", skip_to_comma, 0, 0, 0 },
5687 { "o", 0, 0, 0, 0 },
5688 { "old", 0, 0, 0, 0 },
5689 { "op", skip_to_comma, 0, 0, 0 },
5690 { "pco", 0, 0, 0, 0 },
5691 { "p", opt_chip, 0, 0, 0 },
5692 { "pcr", 0, 0, 0, 0 },
5693 { "pcs", 0, 0, 0, 0 },
5694 { "r", 0, 0, 0, 0 },
5695 { "quick", 0, &m68k_quick, 1, 0 },
5696 { "rel32", 0, &m68k_rel32, 1, 0 },
5697 { "s", opt_list, 0, 0, 0 },
5698 { "t", opt_list_symbols, 0, 0, 0 },
5699 { "w", 0, &flag_no_warnings, 0, 1 },
5700 { "x", 0, 0, 0, 0 }
5701 };
5702
5703 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5704
5705 /* The MRI OPT pseudo-op. */
5706
5707 static void
5708 s_opt (int ignore ATTRIBUTE_UNUSED)
5709 {
5710 do
5711 {
5712 int t;
5713 char *s;
5714 char c;
5715 int i;
5716 const struct opt_action *o;
5717
5718 SKIP_WHITESPACE ();
5719
5720 t = 1;
5721 if (*input_line_pointer == '-')
5722 {
5723 ++input_line_pointer;
5724 t = 0;
5725 }
5726 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5727 {
5728 input_line_pointer += 2;
5729 t = 0;
5730 }
5731
5732 s = input_line_pointer;
5733 c = get_symbol_end ();
5734
5735 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5736 {
5737 if (strcasecmp (s, o->name) == 0)
5738 {
5739 if (o->pfn)
5740 {
5741 /* Restore input_line_pointer now in case the option
5742 takes arguments. */
5743 *input_line_pointer = c;
5744 (*o->pfn) (o->arg, t);
5745 }
5746 else if (o->pvar != NULL)
5747 {
5748 if (! t && o->arg == o->notarg)
5749 as_bad (_("option `%s' may not be negated"), s);
5750 *input_line_pointer = c;
5751 *o->pvar = t ? o->arg : o->notarg;
5752 }
5753 else
5754 *input_line_pointer = c;
5755 break;
5756 }
5757 }
5758 if (i >= OPTCOUNT)
5759 {
5760 as_bad (_("option `%s' not recognized"), s);
5761 *input_line_pointer = c;
5762 }
5763 }
5764 while (*input_line_pointer++ == ',');
5765
5766 /* Move back to terminating character. */
5767 --input_line_pointer;
5768 demand_empty_rest_of_line ();
5769 }
5770
5771 /* Skip ahead to a comma. This is used for OPT options which we do
5772 not support and which take arguments. */
5773
5774 static void
5775 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5776 {
5777 while (*input_line_pointer != ','
5778 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5779 ++input_line_pointer;
5780 }
5781
5782 /* Handle the OPT NEST=depth option. */
5783
5784 static void
5785 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5786 {
5787 if (*input_line_pointer != '=')
5788 {
5789 as_bad (_("bad format of OPT NEST=depth"));
5790 return;
5791 }
5792
5793 ++input_line_pointer;
5794 max_macro_nest = get_absolute_expression ();
5795 }
5796
5797 /* Handle the OPT P=chip option. */
5798
5799 static void
5800 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5801 {
5802 if (*input_line_pointer != '=')
5803 {
5804 /* This is just OPT P, which we do not support. */
5805 return;
5806 }
5807
5808 ++input_line_pointer;
5809 mri_chip ();
5810 }
5811
5812 /* Handle the OPT S option. */
5813
5814 static void
5815 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5816 {
5817 listing_list (on);
5818 }
5819
5820 /* Handle the OPT T option. */
5821
5822 static void
5823 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5824 {
5825 if (on)
5826 listing |= LISTING_SYMBOLS;
5827 else
5828 listing &= ~LISTING_SYMBOLS;
5829 }
5830
5831 /* Handle the MRI REG pseudo-op. */
5832
5833 static void
5834 s_reg (int ignore ATTRIBUTE_UNUSED)
5835 {
5836 char *s;
5837 int c;
5838 struct m68k_op rop;
5839 int mask;
5840 char *stop = NULL;
5841 char stopc;
5842
5843 if (line_label == NULL)
5844 {
5845 as_bad (_("missing label"));
5846 ignore_rest_of_line ();
5847 return;
5848 }
5849
5850 if (flag_mri)
5851 stop = mri_comment_field (&stopc);
5852
5853 SKIP_WHITESPACE ();
5854
5855 s = input_line_pointer;
5856 while (ISALNUM (*input_line_pointer)
5857 #ifdef REGISTER_PREFIX
5858 || *input_line_pointer == REGISTER_PREFIX
5859 #endif
5860 || *input_line_pointer == '/'
5861 || *input_line_pointer == '-')
5862 ++input_line_pointer;
5863 c = *input_line_pointer;
5864 *input_line_pointer = '\0';
5865
5866 if (m68k_ip_op (s, &rop) != 0)
5867 {
5868 if (rop.error == NULL)
5869 as_bad (_("bad register list"));
5870 else
5871 as_bad (_("bad register list: %s"), rop.error);
5872 *input_line_pointer = c;
5873 ignore_rest_of_line ();
5874 return;
5875 }
5876
5877 *input_line_pointer = c;
5878
5879 if (rop.mode == REGLST)
5880 mask = rop.mask;
5881 else if (rop.mode == DREG)
5882 mask = 1 << (rop.reg - DATA0);
5883 else if (rop.mode == AREG)
5884 mask = 1 << (rop.reg - ADDR0 + 8);
5885 else if (rop.mode == FPREG)
5886 mask = 1 << (rop.reg - FP0 + 16);
5887 else if (rop.mode == CONTROL
5888 && rop.reg == FPI)
5889 mask = 1 << 24;
5890 else if (rop.mode == CONTROL
5891 && rop.reg == FPS)
5892 mask = 1 << 25;
5893 else if (rop.mode == CONTROL
5894 && rop.reg == FPC)
5895 mask = 1 << 26;
5896 else
5897 {
5898 as_bad (_("bad register list"));
5899 ignore_rest_of_line ();
5900 return;
5901 }
5902
5903 S_SET_SEGMENT (line_label, reg_section);
5904 S_SET_VALUE (line_label, ~mask);
5905 symbol_set_frag (line_label, &zero_address_frag);
5906
5907 if (flag_mri)
5908 mri_comment_end (stop, stopc);
5909
5910 demand_empty_rest_of_line ();
5911 }
5912
5913 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5914
5915 struct save_opts
5916 {
5917 struct save_opts *next;
5918 int abspcadd;
5919 int symbols_case_sensitive;
5920 int keep_locals;
5921 int short_refs;
5922 int architecture;
5923 const enum m68k_register *control_regs;
5924 int quick;
5925 int rel32;
5926 int listing;
5927 int no_warnings;
5928 /* FIXME: We don't save OPT S. */
5929 };
5930
5931 /* This variable holds the stack of saved options. */
5932
5933 static struct save_opts *save_stack;
5934
5935 /* The MRI SAVE pseudo-op. */
5936
5937 static void
5938 s_save (int ignore ATTRIBUTE_UNUSED)
5939 {
5940 struct save_opts *s;
5941
5942 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5943 s->abspcadd = m68k_abspcadd;
5944 s->symbols_case_sensitive = symbols_case_sensitive;
5945 s->keep_locals = flag_keep_locals;
5946 s->short_refs = flag_short_refs;
5947 s->architecture = current_architecture;
5948 s->control_regs = control_regs;
5949 s->quick = m68k_quick;
5950 s->rel32 = m68k_rel32;
5951 s->listing = listing;
5952 s->no_warnings = flag_no_warnings;
5953
5954 s->next = save_stack;
5955 save_stack = s;
5956
5957 demand_empty_rest_of_line ();
5958 }
5959
5960 /* The MRI RESTORE pseudo-op. */
5961
5962 static void
5963 s_restore (int ignore ATTRIBUTE_UNUSED)
5964 {
5965 struct save_opts *s;
5966
5967 if (save_stack == NULL)
5968 {
5969 as_bad (_("restore without save"));
5970 ignore_rest_of_line ();
5971 return;
5972 }
5973
5974 s = save_stack;
5975 save_stack = s->next;
5976
5977 m68k_abspcadd = s->abspcadd;
5978 symbols_case_sensitive = s->symbols_case_sensitive;
5979 flag_keep_locals = s->keep_locals;
5980 flag_short_refs = s->short_refs;
5981 current_architecture = s->architecture;
5982 control_regs = s->control_regs;
5983 m68k_quick = s->quick;
5984 m68k_rel32 = s->rel32;
5985 listing = s->listing;
5986 flag_no_warnings = s->no_warnings;
5987
5988 free (s);
5989
5990 demand_empty_rest_of_line ();
5991 }
5992
5993 /* Types of MRI structured control directives. */
5994
5995 enum mri_control_type
5996 {
5997 mri_for,
5998 mri_if,
5999 mri_repeat,
6000 mri_while
6001 };
6002
6003 /* This structure is used to stack the MRI structured control
6004 directives. */
6005
6006 struct mri_control_info
6007 {
6008 /* The directive within which this one is enclosed. */
6009 struct mri_control_info *outer;
6010
6011 /* The type of directive. */
6012 enum mri_control_type type;
6013
6014 /* Whether an ELSE has been in an IF. */
6015 int else_seen;
6016
6017 /* The add or sub statement at the end of a FOR. */
6018 char *incr;
6019
6020 /* The label of the top of a FOR or REPEAT loop. */
6021 char *top;
6022
6023 /* The label to jump to for the next iteration, or the else
6024 expression of a conditional. */
6025 char *next;
6026
6027 /* The label to jump to to break out of the loop, or the label past
6028 the end of a conditional. */
6029 char *bottom;
6030 };
6031
6032 /* The stack of MRI structured control directives. */
6033
6034 static struct mri_control_info *mri_control_stack;
6035
6036 /* The current MRI structured control directive index number, used to
6037 generate label names. */
6038
6039 static int mri_control_index;
6040
6041 /* Assemble an instruction for an MRI structured control directive. */
6042
6043 static void
6044 mri_assemble (char *str)
6045 {
6046 char *s;
6047
6048 /* md_assemble expects the opcode to be in lower case. */
6049 for (s = str; *s != ' ' && *s != '\0'; s++)
6050 *s = TOLOWER (*s);
6051
6052 md_assemble (str);
6053 }
6054
6055 /* Generate a new MRI label structured control directive label name. */
6056
6057 static char *
6058 mri_control_label (void)
6059 {
6060 char *n;
6061
6062 n = (char *) xmalloc (20);
6063 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6064 ++mri_control_index;
6065 return n;
6066 }
6067
6068 /* Create a new MRI structured control directive. */
6069
6070 static struct mri_control_info *
6071 push_mri_control (enum mri_control_type type)
6072 {
6073 struct mri_control_info *n;
6074
6075 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6076
6077 n->type = type;
6078 n->else_seen = 0;
6079 if (type == mri_if || type == mri_while)
6080 n->top = NULL;
6081 else
6082 n->top = mri_control_label ();
6083 n->next = mri_control_label ();
6084 n->bottom = mri_control_label ();
6085
6086 n->outer = mri_control_stack;
6087 mri_control_stack = n;
6088
6089 return n;
6090 }
6091
6092 /* Pop off the stack of MRI structured control directives. */
6093
6094 static void
6095 pop_mri_control (void)
6096 {
6097 struct mri_control_info *n;
6098
6099 n = mri_control_stack;
6100 mri_control_stack = n->outer;
6101 if (n->top != NULL)
6102 free (n->top);
6103 free (n->next);
6104 free (n->bottom);
6105 free (n);
6106 }
6107
6108 /* Recognize a condition code in an MRI structured control expression. */
6109
6110 static int
6111 parse_mri_condition (int *pcc)
6112 {
6113 char c1, c2;
6114
6115 know (*input_line_pointer == '<');
6116
6117 ++input_line_pointer;
6118 c1 = *input_line_pointer++;
6119 c2 = *input_line_pointer++;
6120
6121 if (*input_line_pointer != '>')
6122 {
6123 as_bad (_("syntax error in structured control directive"));
6124 return 0;
6125 }
6126
6127 ++input_line_pointer;
6128 SKIP_WHITESPACE ();
6129
6130 c1 = TOLOWER (c1);
6131 c2 = TOLOWER (c2);
6132
6133 *pcc = (c1 << 8) | c2;
6134
6135 return 1;
6136 }
6137
6138 /* Parse a single operand in an MRI structured control expression. */
6139
6140 static int
6141 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6142 char **rightstart, char **rightstop)
6143 {
6144 char *s;
6145
6146 SKIP_WHITESPACE ();
6147
6148 *pcc = -1;
6149 *leftstart = NULL;
6150 *leftstop = NULL;
6151 *rightstart = NULL;
6152 *rightstop = NULL;
6153
6154 if (*input_line_pointer == '<')
6155 {
6156 /* It's just a condition code. */
6157 return parse_mri_condition (pcc);
6158 }
6159
6160 /* Look ahead for the condition code. */
6161 for (s = input_line_pointer; *s != '\0'; ++s)
6162 {
6163 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6164 break;
6165 }
6166 if (*s == '\0')
6167 {
6168 as_bad (_("missing condition code in structured control directive"));
6169 return 0;
6170 }
6171
6172 *leftstart = input_line_pointer;
6173 *leftstop = s;
6174 if (*leftstop > *leftstart
6175 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6176 --*leftstop;
6177
6178 input_line_pointer = s;
6179 if (! parse_mri_condition (pcc))
6180 return 0;
6181
6182 /* Look ahead for AND or OR or end of line. */
6183 for (s = input_line_pointer; *s != '\0'; ++s)
6184 {
6185 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6186 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6187 ^^^ ^^ */
6188 if ((s == input_line_pointer
6189 || *(s-1) == ' '
6190 || *(s-1) == '\t')
6191 && ((strncasecmp (s, "AND", 3) == 0
6192 && (s[3] == '.' || ! is_part_of_name (s[3])))
6193 || (strncasecmp (s, "OR", 2) == 0
6194 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6195 break;
6196 }
6197
6198 *rightstart = input_line_pointer;
6199 *rightstop = s;
6200 if (*rightstop > *rightstart
6201 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6202 --*rightstop;
6203
6204 input_line_pointer = s;
6205
6206 return 1;
6207 }
6208
6209 #define MCC(b1, b2) (((b1) << 8) | (b2))
6210
6211 /* Swap the sense of a condition. This changes the condition so that
6212 it generates the same result when the operands are swapped. */
6213
6214 static int
6215 swap_mri_condition (int cc)
6216 {
6217 switch (cc)
6218 {
6219 case MCC ('h', 'i'): return MCC ('c', 's');
6220 case MCC ('l', 's'): return MCC ('c', 'c');
6221 /* <HS> is an alias for <CC>. */
6222 case MCC ('h', 's'):
6223 case MCC ('c', 'c'): return MCC ('l', 's');
6224 /* <LO> is an alias for <CS>. */
6225 case MCC ('l', 'o'):
6226 case MCC ('c', 's'): return MCC ('h', 'i');
6227 case MCC ('p', 'l'): return MCC ('m', 'i');
6228 case MCC ('m', 'i'): return MCC ('p', 'l');
6229 case MCC ('g', 'e'): return MCC ('l', 'e');
6230 case MCC ('l', 't'): return MCC ('g', 't');
6231 case MCC ('g', 't'): return MCC ('l', 't');
6232 case MCC ('l', 'e'): return MCC ('g', 'e');
6233 /* Issue a warning for conditions we can not swap. */
6234 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6235 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6236 case MCC ('v', 'c'):
6237 case MCC ('v', 's'):
6238 default :
6239 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6240 (char) (cc >> 8), (char) (cc));
6241 break;
6242 }
6243 return cc;
6244 }
6245
6246 /* Reverse the sense of a condition. */
6247
6248 static int
6249 reverse_mri_condition (int cc)
6250 {
6251 switch (cc)
6252 {
6253 case MCC ('h', 'i'): return MCC ('l', 's');
6254 case MCC ('l', 's'): return MCC ('h', 'i');
6255 /* <HS> is an alias for <CC> */
6256 case MCC ('h', 's'): return MCC ('l', 'o');
6257 case MCC ('c', 'c'): return MCC ('c', 's');
6258 /* <LO> is an alias for <CS> */
6259 case MCC ('l', 'o'): return MCC ('h', 's');
6260 case MCC ('c', 's'): return MCC ('c', 'c');
6261 case MCC ('n', 'e'): return MCC ('e', 'q');
6262 case MCC ('e', 'q'): return MCC ('n', 'e');
6263 case MCC ('v', 'c'): return MCC ('v', 's');
6264 case MCC ('v', 's'): return MCC ('v', 'c');
6265 case MCC ('p', 'l'): return MCC ('m', 'i');
6266 case MCC ('m', 'i'): return MCC ('p', 'l');
6267 case MCC ('g', 'e'): return MCC ('l', 't');
6268 case MCC ('l', 't'): return MCC ('g', 'e');
6269 case MCC ('g', 't'): return MCC ('l', 'e');
6270 case MCC ('l', 'e'): return MCC ('g', 't');
6271 }
6272 return cc;
6273 }
6274
6275 /* Build an MRI structured control expression. This generates test
6276 and branch instructions. It goes to TRUELAB if the condition is
6277 true, and to FALSELAB if the condition is false. Exactly one of
6278 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6279 is the size qualifier for the expression. EXTENT is the size to
6280 use for the branch. */
6281
6282 static void
6283 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6284 char *rightstart, char *rightstop,
6285 const char *truelab, const char *falselab,
6286 int extent)
6287 {
6288 char *buf;
6289 char *s;
6290
6291 if (leftstart != NULL)
6292 {
6293 struct m68k_op leftop, rightop;
6294 char c;
6295
6296 /* Swap the compare operands, if necessary, to produce a legal
6297 m68k compare instruction. Comparing a register operand with
6298 a non-register operand requires the register to be on the
6299 right (cmp, cmpa). Comparing an immediate value with
6300 anything requires the immediate value to be on the left
6301 (cmpi). */
6302
6303 c = *leftstop;
6304 *leftstop = '\0';
6305 (void) m68k_ip_op (leftstart, &leftop);
6306 *leftstop = c;
6307
6308 c = *rightstop;
6309 *rightstop = '\0';
6310 (void) m68k_ip_op (rightstart, &rightop);
6311 *rightstop = c;
6312
6313 if (rightop.mode == IMMED
6314 || ((leftop.mode == DREG || leftop.mode == AREG)
6315 && (rightop.mode != DREG && rightop.mode != AREG)))
6316 {
6317 char *temp;
6318
6319 /* Correct conditional handling:
6320 if #1 <lt> d0 then ;means if (1 < d0)
6321 ...
6322 endi
6323
6324 should assemble to:
6325
6326 cmp #1,d0 if we do *not* swap the operands
6327 bgt true we need the swapped condition!
6328 ble false
6329 true:
6330 ...
6331 false:
6332 */
6333 temp = leftstart;
6334 leftstart = rightstart;
6335 rightstart = temp;
6336 temp = leftstop;
6337 leftstop = rightstop;
6338 rightstop = temp;
6339 }
6340 else
6341 {
6342 cc = swap_mri_condition (cc);
6343 }
6344 }
6345
6346 if (truelab == NULL)
6347 {
6348 cc = reverse_mri_condition (cc);
6349 truelab = falselab;
6350 }
6351
6352 if (leftstart != NULL)
6353 {
6354 buf = (char *) xmalloc (20
6355 + (leftstop - leftstart)
6356 + (rightstop - rightstart));
6357 s = buf;
6358 *s++ = 'c';
6359 *s++ = 'm';
6360 *s++ = 'p';
6361 if (qual != '\0')
6362 *s++ = TOLOWER (qual);
6363 *s++ = ' ';
6364 memcpy (s, leftstart, leftstop - leftstart);
6365 s += leftstop - leftstart;
6366 *s++ = ',';
6367 memcpy (s, rightstart, rightstop - rightstart);
6368 s += rightstop - rightstart;
6369 *s = '\0';
6370 mri_assemble (buf);
6371 free (buf);
6372 }
6373
6374 buf = (char *) xmalloc (20 + strlen (truelab));
6375 s = buf;
6376 *s++ = 'b';
6377 *s++ = cc >> 8;
6378 *s++ = cc & 0xff;
6379 if (extent != '\0')
6380 *s++ = TOLOWER (extent);
6381 *s++ = ' ';
6382 strcpy (s, truelab);
6383 mri_assemble (buf);
6384 free (buf);
6385 }
6386
6387 /* Parse an MRI structured control expression. This generates test
6388 and branch instructions. STOP is where the expression ends. It
6389 goes to TRUELAB if the condition is true, and to FALSELAB if the
6390 condition is false. Exactly one of TRUELAB and FALSELAB will be
6391 NULL, meaning to fall through. QUAL is the size qualifier for the
6392 expression. EXTENT is the size to use for the branch. */
6393
6394 static void
6395 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6396 const char *falselab, int extent)
6397 {
6398 int c;
6399 int cc;
6400 char *leftstart;
6401 char *leftstop;
6402 char *rightstart;
6403 char *rightstop;
6404
6405 c = *stop;
6406 *stop = '\0';
6407
6408 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6409 &rightstart, &rightstop))
6410 {
6411 *stop = c;
6412 return;
6413 }
6414
6415 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6416 {
6417 const char *flab;
6418
6419 if (falselab != NULL)
6420 flab = falselab;
6421 else
6422 flab = mri_control_label ();
6423
6424 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6425 rightstop, (const char *) NULL, flab, extent);
6426
6427 input_line_pointer += 3;
6428 if (*input_line_pointer != '.'
6429 || input_line_pointer[1] == '\0')
6430 qual = '\0';
6431 else
6432 {
6433 qual = input_line_pointer[1];
6434 input_line_pointer += 2;
6435 }
6436
6437 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6438 &rightstart, &rightstop))
6439 {
6440 *stop = c;
6441 return;
6442 }
6443
6444 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6445 rightstop, truelab, falselab, extent);
6446
6447 if (falselab == NULL)
6448 colon (flab);
6449 }
6450 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6451 {
6452 const char *tlab;
6453
6454 if (truelab != NULL)
6455 tlab = truelab;
6456 else
6457 tlab = mri_control_label ();
6458
6459 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6460 rightstop, tlab, (const char *) NULL, extent);
6461
6462 input_line_pointer += 2;
6463 if (*input_line_pointer != '.'
6464 || input_line_pointer[1] == '\0')
6465 qual = '\0';
6466 else
6467 {
6468 qual = input_line_pointer[1];
6469 input_line_pointer += 2;
6470 }
6471
6472 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6473 &rightstart, &rightstop))
6474 {
6475 *stop = c;
6476 return;
6477 }
6478
6479 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6480 rightstop, truelab, falselab, extent);
6481
6482 if (truelab == NULL)
6483 colon (tlab);
6484 }
6485 else
6486 {
6487 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6488 rightstop, truelab, falselab, extent);
6489 }
6490
6491 *stop = c;
6492 if (input_line_pointer != stop)
6493 as_bad (_("syntax error in structured control directive"));
6494 }
6495
6496 /* Handle the MRI IF pseudo-op. This may be a structured control
6497 directive, or it may be a regular assembler conditional, depending
6498 on its operands. */
6499
6500 static void
6501 s_mri_if (int qual)
6502 {
6503 char *s;
6504 int c;
6505 struct mri_control_info *n;
6506
6507 /* A structured control directive must end with THEN with an
6508 optional qualifier. */
6509 s = input_line_pointer;
6510 /* We only accept '*' as introduction of comments if preceded by white space
6511 or at first column of a line (I think this can't actually happen here?)
6512 This is important when assembling:
6513 if d0 <ne> 12(a0,d0*2) then
6514 if d0 <ne> #CONST*20 then. */
6515 while (! (is_end_of_line[(unsigned char) *s]
6516 || (flag_mri
6517 && *s == '*'
6518 && (s == input_line_pointer
6519 || *(s-1) == ' '
6520 || *(s-1) == '\t'))))
6521 ++s;
6522 --s;
6523 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6524 --s;
6525
6526 if (s - input_line_pointer > 1
6527 && s[-1] == '.')
6528 s -= 2;
6529
6530 if (s - input_line_pointer < 3
6531 || strncasecmp (s - 3, "THEN", 4) != 0)
6532 {
6533 if (qual != '\0')
6534 {
6535 as_bad (_("missing then"));
6536 ignore_rest_of_line ();
6537 return;
6538 }
6539
6540 /* It's a conditional. */
6541 s_if (O_ne);
6542 return;
6543 }
6544
6545 /* Since this might be a conditional if, this pseudo-op will be
6546 called even if we are supported to be ignoring input. Double
6547 check now. Clobber *input_line_pointer so that ignore_input
6548 thinks that this is not a special pseudo-op. */
6549 c = *input_line_pointer;
6550 *input_line_pointer = 0;
6551 if (ignore_input ())
6552 {
6553 *input_line_pointer = c;
6554 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6555 ++input_line_pointer;
6556 demand_empty_rest_of_line ();
6557 return;
6558 }
6559 *input_line_pointer = c;
6560
6561 n = push_mri_control (mri_if);
6562
6563 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6564 n->next, s[1] == '.' ? s[2] : '\0');
6565
6566 if (s[1] == '.')
6567 input_line_pointer = s + 3;
6568 else
6569 input_line_pointer = s + 1;
6570
6571 if (flag_mri)
6572 {
6573 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6574 ++input_line_pointer;
6575 }
6576
6577 demand_empty_rest_of_line ();
6578 }
6579
6580 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6581 structured IF, associate the ELSE with the IF. Otherwise, assume
6582 it is a conditional else. */
6583
6584 static void
6585 s_mri_else (int qual)
6586 {
6587 int c;
6588 char *buf;
6589 char q[2];
6590
6591 if (qual == '\0'
6592 && (mri_control_stack == NULL
6593 || mri_control_stack->type != mri_if
6594 || mri_control_stack->else_seen))
6595 {
6596 s_else (0);
6597 return;
6598 }
6599
6600 c = *input_line_pointer;
6601 *input_line_pointer = 0;
6602 if (ignore_input ())
6603 {
6604 *input_line_pointer = c;
6605 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6606 ++input_line_pointer;
6607 demand_empty_rest_of_line ();
6608 return;
6609 }
6610 *input_line_pointer = c;
6611
6612 if (mri_control_stack == NULL
6613 || mri_control_stack->type != mri_if
6614 || mri_control_stack->else_seen)
6615 {
6616 as_bad (_("else without matching if"));
6617 ignore_rest_of_line ();
6618 return;
6619 }
6620
6621 mri_control_stack->else_seen = 1;
6622
6623 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6624 q[0] = TOLOWER (qual);
6625 q[1] = '\0';
6626 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6627 mri_assemble (buf);
6628 free (buf);
6629
6630 colon (mri_control_stack->next);
6631
6632 if (flag_mri)
6633 {
6634 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6635 ++input_line_pointer;
6636 }
6637
6638 demand_empty_rest_of_line ();
6639 }
6640
6641 /* Handle the MRI ENDI pseudo-op. */
6642
6643 static void
6644 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6645 {
6646 if (mri_control_stack == NULL
6647 || mri_control_stack->type != mri_if)
6648 {
6649 as_bad (_("endi without matching if"));
6650 ignore_rest_of_line ();
6651 return;
6652 }
6653
6654 /* ignore_input will not return true for ENDI, so we don't need to
6655 worry about checking it again here. */
6656
6657 if (! mri_control_stack->else_seen)
6658 colon (mri_control_stack->next);
6659 colon (mri_control_stack->bottom);
6660
6661 pop_mri_control ();
6662
6663 if (flag_mri)
6664 {
6665 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6666 ++input_line_pointer;
6667 }
6668
6669 demand_empty_rest_of_line ();
6670 }
6671
6672 /* Handle the MRI BREAK pseudo-op. */
6673
6674 static void
6675 s_mri_break (int extent)
6676 {
6677 struct mri_control_info *n;
6678 char *buf;
6679 char ex[2];
6680
6681 n = mri_control_stack;
6682 while (n != NULL
6683 && n->type != mri_for
6684 && n->type != mri_repeat
6685 && n->type != mri_while)
6686 n = n->outer;
6687 if (n == NULL)
6688 {
6689 as_bad (_("break outside of structured loop"));
6690 ignore_rest_of_line ();
6691 return;
6692 }
6693
6694 buf = (char *) xmalloc (20 + strlen (n->bottom));
6695 ex[0] = TOLOWER (extent);
6696 ex[1] = '\0';
6697 sprintf (buf, "bra%s %s", ex, n->bottom);
6698 mri_assemble (buf);
6699 free (buf);
6700
6701 if (flag_mri)
6702 {
6703 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6704 ++input_line_pointer;
6705 }
6706
6707 demand_empty_rest_of_line ();
6708 }
6709
6710 /* Handle the MRI NEXT pseudo-op. */
6711
6712 static void
6713 s_mri_next (int extent)
6714 {
6715 struct mri_control_info *n;
6716 char *buf;
6717 char ex[2];
6718
6719 n = mri_control_stack;
6720 while (n != NULL
6721 && n->type != mri_for
6722 && n->type != mri_repeat
6723 && n->type != mri_while)
6724 n = n->outer;
6725 if (n == NULL)
6726 {
6727 as_bad (_("next outside of structured loop"));
6728 ignore_rest_of_line ();
6729 return;
6730 }
6731
6732 buf = (char *) xmalloc (20 + strlen (n->next));
6733 ex[0] = TOLOWER (extent);
6734 ex[1] = '\0';
6735 sprintf (buf, "bra%s %s", ex, n->next);
6736 mri_assemble (buf);
6737 free (buf);
6738
6739 if (flag_mri)
6740 {
6741 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6742 ++input_line_pointer;
6743 }
6744
6745 demand_empty_rest_of_line ();
6746 }
6747
6748 /* Handle the MRI FOR pseudo-op. */
6749
6750 static void
6751 s_mri_for (int qual)
6752 {
6753 const char *varstart, *varstop;
6754 const char *initstart, *initstop;
6755 const char *endstart, *endstop;
6756 const char *bystart, *bystop;
6757 int up;
6758 int by;
6759 int extent;
6760 struct mri_control_info *n;
6761 char *buf;
6762 char *s;
6763 char ex[2];
6764
6765 /* The syntax is
6766 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6767 */
6768
6769 SKIP_WHITESPACE ();
6770 varstart = input_line_pointer;
6771
6772 /* Look for the '='. */
6773 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6774 && *input_line_pointer != '=')
6775 ++input_line_pointer;
6776 if (*input_line_pointer != '=')
6777 {
6778 as_bad (_("missing ="));
6779 ignore_rest_of_line ();
6780 return;
6781 }
6782
6783 varstop = input_line_pointer;
6784 if (varstop > varstart
6785 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6786 --varstop;
6787
6788 ++input_line_pointer;
6789
6790 initstart = input_line_pointer;
6791
6792 /* Look for TO or DOWNTO. */
6793 up = 1;
6794 initstop = NULL;
6795 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6796 {
6797 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6798 && ! is_part_of_name (input_line_pointer[2]))
6799 {
6800 initstop = input_line_pointer;
6801 input_line_pointer += 2;
6802 break;
6803 }
6804 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6805 && ! is_part_of_name (input_line_pointer[6]))
6806 {
6807 initstop = input_line_pointer;
6808 up = 0;
6809 input_line_pointer += 6;
6810 break;
6811 }
6812 ++input_line_pointer;
6813 }
6814 if (initstop == NULL)
6815 {
6816 as_bad (_("missing to or downto"));
6817 ignore_rest_of_line ();
6818 return;
6819 }
6820 if (initstop > initstart
6821 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6822 --initstop;
6823
6824 SKIP_WHITESPACE ();
6825 endstart = input_line_pointer;
6826
6827 /* Look for BY or DO. */
6828 by = 0;
6829 endstop = NULL;
6830 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6831 {
6832 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6833 && ! is_part_of_name (input_line_pointer[2]))
6834 {
6835 endstop = input_line_pointer;
6836 by = 1;
6837 input_line_pointer += 2;
6838 break;
6839 }
6840 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6841 && (input_line_pointer[2] == '.'
6842 || ! is_part_of_name (input_line_pointer[2])))
6843 {
6844 endstop = input_line_pointer;
6845 input_line_pointer += 2;
6846 break;
6847 }
6848 ++input_line_pointer;
6849 }
6850 if (endstop == NULL)
6851 {
6852 as_bad (_("missing do"));
6853 ignore_rest_of_line ();
6854 return;
6855 }
6856 if (endstop > endstart
6857 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6858 --endstop;
6859
6860 if (! by)
6861 {
6862 bystart = "#1";
6863 bystop = bystart + 2;
6864 }
6865 else
6866 {
6867 SKIP_WHITESPACE ();
6868 bystart = input_line_pointer;
6869
6870 /* Look for DO. */
6871 bystop = NULL;
6872 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6873 {
6874 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6875 && (input_line_pointer[2] == '.'
6876 || ! is_part_of_name (input_line_pointer[2])))
6877 {
6878 bystop = input_line_pointer;
6879 input_line_pointer += 2;
6880 break;
6881 }
6882 ++input_line_pointer;
6883 }
6884 if (bystop == NULL)
6885 {
6886 as_bad (_("missing do"));
6887 ignore_rest_of_line ();
6888 return;
6889 }
6890 if (bystop > bystart
6891 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6892 --bystop;
6893 }
6894
6895 if (*input_line_pointer != '.')
6896 extent = '\0';
6897 else
6898 {
6899 extent = input_line_pointer[1];
6900 input_line_pointer += 2;
6901 }
6902
6903 /* We have fully parsed the FOR operands. Now build the loop. */
6904 n = push_mri_control (mri_for);
6905
6906 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6907
6908 /* Move init,var. */
6909 s = buf;
6910 *s++ = 'm';
6911 *s++ = 'o';
6912 *s++ = 'v';
6913 *s++ = 'e';
6914 if (qual != '\0')
6915 *s++ = TOLOWER (qual);
6916 *s++ = ' ';
6917 memcpy (s, initstart, initstop - initstart);
6918 s += initstop - initstart;
6919 *s++ = ',';
6920 memcpy (s, varstart, varstop - varstart);
6921 s += varstop - varstart;
6922 *s = '\0';
6923 mri_assemble (buf);
6924
6925 colon (n->top);
6926
6927 /* cmp end,var. */
6928 s = buf;
6929 *s++ = 'c';
6930 *s++ = 'm';
6931 *s++ = 'p';
6932 if (qual != '\0')
6933 *s++ = TOLOWER (qual);
6934 *s++ = ' ';
6935 memcpy (s, endstart, endstop - endstart);
6936 s += endstop - endstart;
6937 *s++ = ',';
6938 memcpy (s, varstart, varstop - varstart);
6939 s += varstop - varstart;
6940 *s = '\0';
6941 mri_assemble (buf);
6942
6943 /* bcc bottom. */
6944 ex[0] = TOLOWER (extent);
6945 ex[1] = '\0';
6946 if (up)
6947 sprintf (buf, "blt%s %s", ex, n->bottom);
6948 else
6949 sprintf (buf, "bgt%s %s", ex, n->bottom);
6950 mri_assemble (buf);
6951
6952 /* Put together the add or sub instruction used by ENDF. */
6953 s = buf;
6954 if (up)
6955 strcpy (s, "add");
6956 else
6957 strcpy (s, "sub");
6958 s += 3;
6959 if (qual != '\0')
6960 *s++ = TOLOWER (qual);
6961 *s++ = ' ';
6962 memcpy (s, bystart, bystop - bystart);
6963 s += bystop - bystart;
6964 *s++ = ',';
6965 memcpy (s, varstart, varstop - varstart);
6966 s += varstop - varstart;
6967 *s = '\0';
6968 n->incr = buf;
6969
6970 if (flag_mri)
6971 {
6972 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6973 ++input_line_pointer;
6974 }
6975
6976 demand_empty_rest_of_line ();
6977 }
6978
6979 /* Handle the MRI ENDF pseudo-op. */
6980
6981 static void
6982 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6983 {
6984 if (mri_control_stack == NULL
6985 || mri_control_stack->type != mri_for)
6986 {
6987 as_bad (_("endf without for"));
6988 ignore_rest_of_line ();
6989 return;
6990 }
6991
6992 colon (mri_control_stack->next);
6993
6994 mri_assemble (mri_control_stack->incr);
6995
6996 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6997 mri_assemble (mri_control_stack->incr);
6998
6999 free (mri_control_stack->incr);
7000
7001 colon (mri_control_stack->bottom);
7002
7003 pop_mri_control ();
7004
7005 if (flag_mri)
7006 {
7007 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7008 ++input_line_pointer;
7009 }
7010
7011 demand_empty_rest_of_line ();
7012 }
7013
7014 /* Handle the MRI REPEAT pseudo-op. */
7015
7016 static void
7017 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
7018 {
7019 struct mri_control_info *n;
7020
7021 n = push_mri_control (mri_repeat);
7022 colon (n->top);
7023 if (flag_mri)
7024 {
7025 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7026 ++input_line_pointer;
7027 }
7028 demand_empty_rest_of_line ();
7029 }
7030
7031 /* Handle the MRI UNTIL pseudo-op. */
7032
7033 static void
7034 s_mri_until (int qual)
7035 {
7036 char *s;
7037
7038 if (mri_control_stack == NULL
7039 || mri_control_stack->type != mri_repeat)
7040 {
7041 as_bad (_("until without repeat"));
7042 ignore_rest_of_line ();
7043 return;
7044 }
7045
7046 colon (mri_control_stack->next);
7047
7048 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7049 ;
7050
7051 parse_mri_control_expression (s, qual, (const char *) NULL,
7052 mri_control_stack->top, '\0');
7053
7054 colon (mri_control_stack->bottom);
7055
7056 input_line_pointer = s;
7057
7058 pop_mri_control ();
7059
7060 if (flag_mri)
7061 {
7062 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7063 ++input_line_pointer;
7064 }
7065
7066 demand_empty_rest_of_line ();
7067 }
7068
7069 /* Handle the MRI WHILE pseudo-op. */
7070
7071 static void
7072 s_mri_while (int qual)
7073 {
7074 char *s;
7075
7076 struct mri_control_info *n;
7077
7078 s = input_line_pointer;
7079 /* We only accept '*' as introduction of comments if preceded by white space
7080 or at first column of a line (I think this can't actually happen here?)
7081 This is important when assembling:
7082 while d0 <ne> 12(a0,d0*2) do
7083 while d0 <ne> #CONST*20 do. */
7084 while (! (is_end_of_line[(unsigned char) *s]
7085 || (flag_mri
7086 && *s == '*'
7087 && (s == input_line_pointer
7088 || *(s-1) == ' '
7089 || *(s-1) == '\t'))))
7090 s++;
7091 --s;
7092 while (*s == ' ' || *s == '\t')
7093 --s;
7094 if (s - input_line_pointer > 1
7095 && s[-1] == '.')
7096 s -= 2;
7097 if (s - input_line_pointer < 2
7098 || strncasecmp (s - 1, "DO", 2) != 0)
7099 {
7100 as_bad (_("missing do"));
7101 ignore_rest_of_line ();
7102 return;
7103 }
7104
7105 n = push_mri_control (mri_while);
7106
7107 colon (n->next);
7108
7109 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7110 s[1] == '.' ? s[2] : '\0');
7111
7112 input_line_pointer = s + 1;
7113 if (*input_line_pointer == '.')
7114 input_line_pointer += 2;
7115
7116 if (flag_mri)
7117 {
7118 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7119 ++input_line_pointer;
7120 }
7121
7122 demand_empty_rest_of_line ();
7123 }
7124
7125 /* Handle the MRI ENDW pseudo-op. */
7126
7127 static void
7128 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7129 {
7130 char *buf;
7131
7132 if (mri_control_stack == NULL
7133 || mri_control_stack->type != mri_while)
7134 {
7135 as_bad (_("endw without while"));
7136 ignore_rest_of_line ();
7137 return;
7138 }
7139
7140 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7141 sprintf (buf, "bra %s", mri_control_stack->next);
7142 mri_assemble (buf);
7143 free (buf);
7144
7145 colon (mri_control_stack->bottom);
7146
7147 pop_mri_control ();
7148
7149 if (flag_mri)
7150 {
7151 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7152 ++input_line_pointer;
7153 }
7154
7155 demand_empty_rest_of_line ();
7156 }
7157 \f
7158 /* Parse a .cpu directive. */
7159
7160 static void
7161 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7162 {
7163 char saved_char;
7164 char *name;
7165
7166 if (initialized)
7167 {
7168 as_bad (_("already assembled instructions"));
7169 ignore_rest_of_line ();
7170 return;
7171 }
7172
7173 name = input_line_pointer;
7174 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7175 input_line_pointer++;
7176 saved_char = *input_line_pointer;
7177 *input_line_pointer = 0;
7178
7179 m68k_set_cpu (name, 1, 0);
7180
7181 *input_line_pointer = saved_char;
7182 demand_empty_rest_of_line ();
7183 return;
7184 }
7185
7186 /* Parse a .arch directive. */
7187
7188 static void
7189 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7190 {
7191 char saved_char;
7192 char *name;
7193
7194 if (initialized)
7195 {
7196 as_bad (_("already assembled instructions"));
7197 ignore_rest_of_line ();
7198 return;
7199 }
7200
7201 name = input_line_pointer;
7202 while (*input_line_pointer && *input_line_pointer != ','
7203 && !ISSPACE (*input_line_pointer))
7204 input_line_pointer++;
7205 saved_char = *input_line_pointer;
7206 *input_line_pointer = 0;
7207
7208 if (m68k_set_arch (name, 1, 0))
7209 {
7210 /* Scan extensions. */
7211 do
7212 {
7213 *input_line_pointer++ = saved_char;
7214 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7215 break;
7216 name = input_line_pointer;
7217 while (*input_line_pointer && *input_line_pointer != ','
7218 && !ISSPACE (*input_line_pointer))
7219 input_line_pointer++;
7220 saved_char = *input_line_pointer;
7221 *input_line_pointer = 0;
7222 }
7223 while (m68k_set_extension (name, 1, 0));
7224 }
7225
7226 *input_line_pointer = saved_char;
7227 demand_empty_rest_of_line ();
7228 return;
7229 }
7230 \f
7231 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7232 if none is found, the caller is responsible for emitting an error
7233 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7234 cpu name, if it begins with a '6' (possibly skipping an intervening
7235 'c'. We also allow a 'c' in the same place. if NEGATED is
7236 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7237 the option is indeed negated. */
7238
7239 static const struct m68k_cpu *
7240 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7241 int allow_m, int *negated)
7242 {
7243 /* allow negated value? */
7244 if (negated)
7245 {
7246 *negated = 0;
7247
7248 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7249 {
7250 arg += 3;
7251 *negated = 1;
7252 }
7253 }
7254
7255 /* Remove 'm' or 'mc' prefix from 68k variants. */
7256 if (allow_m)
7257 {
7258 if (arg[0] == 'm')
7259 {
7260 if (arg[1] == '6')
7261 arg += 1;
7262 else if (arg[1] == 'c' && arg[2] == '6')
7263 arg += 2;
7264 }
7265 }
7266 else if (arg[0] == 'c' && arg[1] == '6')
7267 arg += 1;
7268
7269 for (; table->name; table++)
7270 if (!strcmp (arg, table->name))
7271 {
7272 if (table->alias < -1 || table->alias > 1)
7273 as_bad (_("`%s' is deprecated, use `%s'"),
7274 table->name, table[table->alias < 0 ? 1 : -1].name);
7275 return table;
7276 }
7277 return 0;
7278 }
7279
7280 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7281
7282 static int
7283 m68k_set_cpu (char const *name, int allow_m, int silent)
7284 {
7285 const struct m68k_cpu *cpu;
7286
7287 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7288
7289 if (!cpu)
7290 {
7291 if (!silent)
7292 as_bad (_("cpu `%s' unrecognized"), name);
7293 return 0;
7294 }
7295
7296 if (selected_cpu && selected_cpu != cpu)
7297 {
7298 as_bad (_("already selected `%s' processor"),
7299 selected_cpu->name);
7300 return 0;
7301 }
7302 selected_cpu = cpu;
7303 return 1;
7304 }
7305
7306 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7307
7308 static int
7309 m68k_set_arch (char const *name, int allow_m, int silent)
7310 {
7311 const struct m68k_cpu *arch;
7312
7313 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7314
7315 if (!arch)
7316 {
7317 if (!silent)
7318 as_bad (_("architecture `%s' unrecognized"), name);
7319 return 0;
7320 }
7321
7322 if (selected_arch && selected_arch != arch)
7323 {
7324 as_bad (_("already selected `%s' architecture"),
7325 selected_arch->name);
7326 return 0;
7327 }
7328
7329 selected_arch = arch;
7330 return 1;
7331 }
7332
7333 /* Set the architecture extension, issuing errors if it is
7334 unrecognized, or invalid */
7335
7336 static int
7337 m68k_set_extension (char const *name, int allow_m, int silent)
7338 {
7339 int negated;
7340 const struct m68k_cpu *ext;
7341
7342 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7343
7344 if (!ext)
7345 {
7346 if (!silent)
7347 as_bad (_("extension `%s' unrecognized"), name);
7348 return 0;
7349 }
7350
7351 if (negated)
7352 not_current_architecture |= ext->arch;
7353 else
7354 current_architecture |= ext->arch;
7355 return 1;
7356 }
7357
7358 /* md_parse_option
7359 Invocation line includes a switch not recognized by the base assembler.
7360 */
7361
7362 #ifdef OBJ_ELF
7363 const char *md_shortopts = "lSA:m:kQ:V";
7364 #else
7365 const char *md_shortopts = "lSA:m:k";
7366 #endif
7367
7368 struct option md_longopts[] = {
7369 #define OPTION_PIC (OPTION_MD_BASE)
7370 {"pic", no_argument, NULL, OPTION_PIC},
7371 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7372 {"register-prefix-optional", no_argument, NULL,
7373 OPTION_REGISTER_PREFIX_OPTIONAL},
7374 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7375 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7376 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7377 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7378 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7379 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7380 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7381 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7382 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7383 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7384 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7385 {"pcrel", no_argument, NULL, OPTION_PCREL},
7386 {NULL, no_argument, NULL, 0}
7387 };
7388 size_t md_longopts_size = sizeof (md_longopts);
7389
7390 int
7391 md_parse_option (int c, char *arg)
7392 {
7393 switch (c)
7394 {
7395 case 'l': /* -l means keep external to 2 bit offset
7396 rather than 16 bit one. */
7397 flag_short_refs = 1;
7398 break;
7399
7400 case 'S': /* -S means that jbsr's always turn into
7401 jsr's. */
7402 flag_long_jumps = 1;
7403 break;
7404
7405 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7406 branches into absolute jumps. */
7407 flag_keep_pcrel = 1;
7408 break;
7409
7410 case OPTION_PIC:
7411 case 'k':
7412 flag_want_pic = 1;
7413 break; /* -pic, Position Independent Code. */
7414
7415 case OPTION_REGISTER_PREFIX_OPTIONAL:
7416 flag_reg_prefix_optional = 1;
7417 reg_prefix_optional_seen = 1;
7418 break;
7419
7420 /* -V: SVR4 argument to print version ID. */
7421 case 'V':
7422 print_version_id ();
7423 break;
7424
7425 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7426 should be emitted or not. FIXME: Not implemented. */
7427 case 'Q':
7428 break;
7429
7430 case OPTION_BITWISE_OR:
7431 {
7432 char *n, *t;
7433 const char *s;
7434
7435 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7436 t = n;
7437 for (s = m68k_comment_chars; *s != '\0'; s++)
7438 if (*s != '|')
7439 *t++ = *s;
7440 *t = '\0';
7441 m68k_comment_chars = n;
7442 }
7443 break;
7444
7445 case OPTION_BASE_SIZE_DEFAULT_16:
7446 m68k_index_width_default = SIZE_WORD;
7447 break;
7448
7449 case OPTION_BASE_SIZE_DEFAULT_32:
7450 m68k_index_width_default = SIZE_LONG;
7451 break;
7452
7453 case OPTION_DISP_SIZE_DEFAULT_16:
7454 m68k_rel32 = 0;
7455 m68k_rel32_from_cmdline = 1;
7456 break;
7457
7458 case OPTION_DISP_SIZE_DEFAULT_32:
7459 m68k_rel32 = 1;
7460 m68k_rel32_from_cmdline = 1;
7461 break;
7462
7463 case 'A':
7464 #if WARN_DEPRECATED
7465 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7466 arg, arg));
7467 #endif
7468 /* Intentional fall-through. */
7469 case 'm':
7470 if (!strncmp (arg, "arch=", 5))
7471 m68k_set_arch (arg + 5, 1, 0);
7472 else if (!strncmp (arg, "cpu=", 4))
7473 m68k_set_cpu (arg + 4, 1, 0);
7474 else if (m68k_set_extension (arg, 0, 1))
7475 ;
7476 else if (m68k_set_arch (arg, 0, 1))
7477 ;
7478 else if (m68k_set_cpu (arg, 0, 1))
7479 ;
7480 else
7481 return 0;
7482 break;
7483
7484 default:
7485 return 0;
7486 }
7487
7488 return 1;
7489 }
7490
7491 /* Setup tables from the selected arch and/or cpu */
7492
7493 static void
7494 m68k_init_arch (void)
7495 {
7496 if (not_current_architecture & current_architecture)
7497 {
7498 as_bad (_("architecture features both enabled and disabled"));
7499 not_current_architecture &= ~current_architecture;
7500 }
7501 if (selected_arch)
7502 {
7503 current_architecture |= selected_arch->arch;
7504 control_regs = selected_arch->control_regs;
7505 }
7506 else
7507 current_architecture |= selected_cpu->arch;
7508
7509 current_architecture &= ~not_current_architecture;
7510
7511 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7512 {
7513 /* Determine which float is really meant. */
7514 if (current_architecture & (m68k_mask & ~m68881))
7515 current_architecture ^= cfloat;
7516 else
7517 current_architecture ^= m68881;
7518 }
7519
7520 if (selected_cpu)
7521 {
7522 control_regs = selected_cpu->control_regs;
7523 if (current_architecture & ~selected_cpu->arch)
7524 {
7525 as_bad (_("selected processor does not have all features of selected architecture"));
7526 current_architecture
7527 = selected_cpu->arch & ~not_current_architecture;
7528 }
7529 }
7530
7531 if ((current_architecture & m68k_mask)
7532 && (current_architecture & ~m68k_mask))
7533 {
7534 as_bad (_ ("m68k and cf features both selected"));
7535 if (current_architecture & m68k_mask)
7536 current_architecture &= m68k_mask;
7537 else
7538 current_architecture &= ~m68k_mask;
7539 }
7540
7541 /* Permit m68881 specification with all cpus; those that can't work
7542 with a coprocessor could be doing emulation. */
7543 if (current_architecture & m68851)
7544 {
7545 if (current_architecture & m68040)
7546 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7547 }
7548 /* What other incompatibilities could we check for? */
7549
7550 if (cpu_of_arch (current_architecture) < m68020
7551 || arch_coldfire_p (current_architecture))
7552 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7553
7554 initialized = 1;
7555 }
7556
7557 void
7558 md_show_usage (FILE *stream)
7559 {
7560 const char *default_cpu = TARGET_CPU;
7561 int i;
7562 unsigned int default_arch;
7563
7564 /* Get the canonical name for the default target CPU. */
7565 if (*default_cpu == 'm')
7566 default_cpu++;
7567 for (i = 0; m68k_cpus[i].name; i++)
7568 {
7569 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7570 {
7571 default_arch = m68k_cpus[i].arch;
7572 while (m68k_cpus[i].alias > 0)
7573 i--;
7574 while (m68k_cpus[i].alias < 0)
7575 i++;
7576 default_cpu = m68k_cpus[i].name;
7577 }
7578 }
7579
7580 fprintf (stream, _("\
7581 -march=<arch> set architecture\n\
7582 -mcpu=<cpu> set cpu [default %s]\n\
7583 "), default_cpu);
7584 for (i = 0; m68k_extensions[i].name; i++)
7585 fprintf (stream, _("\
7586 -m[no-]%-16s enable/disable%s architecture extension\n\
7587 "), m68k_extensions[i].name,
7588 m68k_extensions[i].alias > 0 ? " ColdFire"
7589 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7590
7591 fprintf (stream, _("\
7592 -l use 1 word for refs to undefined symbols [default 2]\n\
7593 -pic, -k generate position independent code\n\
7594 -S turn jbsr into jsr\n\
7595 --pcrel never turn PC-relative branches into absolute jumps\n\
7596 --register-prefix-optional\n\
7597 recognize register names without prefix character\n\
7598 --bitwise-or do not treat `|' as a comment character\n\
7599 --base-size-default-16 base reg without size is 16 bits\n\
7600 --base-size-default-32 base reg without size is 32 bits (default)\n\
7601 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7602 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7603 "));
7604
7605 fprintf (stream, _("Architecture variants are: "));
7606 for (i = 0; m68k_archs[i].name; i++)
7607 {
7608 if (i)
7609 fprintf (stream, " | ");
7610 fprintf (stream, m68k_archs[i].name);
7611 }
7612 fprintf (stream, "\n");
7613
7614 fprintf (stream, _("Processor variants are: "));
7615 for (i = 0; m68k_cpus[i].name; i++)
7616 {
7617 if (i)
7618 fprintf (stream, " | ");
7619 fprintf (stream, m68k_cpus[i].name);
7620 }
7621 fprintf (stream, _("\n"));
7622 }
7623 \f
7624 #ifdef TEST2
7625
7626 /* TEST2: Test md_assemble() */
7627 /* Warning, this routine probably doesn't work anymore. */
7628 int
7629 main (void)
7630 {
7631 struct m68k_it the_ins;
7632 char buf[120];
7633 char *cp;
7634 int n;
7635
7636 m68k_ip_begin ();
7637 for (;;)
7638 {
7639 if (!gets (buf) || !*buf)
7640 break;
7641 if (buf[0] == '|' || buf[1] == '.')
7642 continue;
7643 for (cp = buf; *cp; cp++)
7644 if (*cp == '\t')
7645 *cp = ' ';
7646 if (is_label (buf))
7647 continue;
7648 memset (&the_ins, '\0', sizeof (the_ins));
7649 m68k_ip (&the_ins, buf);
7650 if (the_ins.error)
7651 {
7652 printf (_("Error %s in %s\n"), the_ins.error, buf);
7653 }
7654 else
7655 {
7656 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7657 for (n = 0; n < the_ins.numo; n++)
7658 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7659 printf (" ");
7660 print_the_insn (&the_ins.opcode[0], stdout);
7661 (void) putchar ('\n');
7662 }
7663 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7664 {
7665 if (the_ins.operands[n].error)
7666 {
7667 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7668 continue;
7669 }
7670 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7671 the_ins.operands[n].reg);
7672 if (the_ins.operands[n].b_const)
7673 printf ("Constant: '%.*s', ",
7674 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7675 the_ins.operands[n].b_const);
7676 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7677 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7678 if (the_ins.operands[n].b_iadd)
7679 printf ("Iadd: '%.*s',",
7680 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7681 the_ins.operands[n].b_iadd);
7682 putchar ('\n');
7683 }
7684 }
7685 m68k_ip_end ();
7686 return 0;
7687 }
7688
7689 int
7690 is_label (char *str)
7691 {
7692 while (*str == ' ')
7693 str++;
7694 while (*str && *str != ' ')
7695 str++;
7696 if (str[-1] == ':' || str[1] == '=')
7697 return 1;
7698 return 0;
7699 }
7700
7701 #endif
7702
7703 /* Possible states for relaxation:
7704
7705 0 0 branch offset byte (bra, etc)
7706 0 1 word
7707 0 2 long
7708
7709 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7710 1 1 word
7711 1 2 long
7712
7713 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7714 2 1 word-long
7715 2 2 long-word
7716 2 3 long-long
7717
7718 */
7719
7720 /* We have no need to default values of symbols. */
7721
7722 symbolS *
7723 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7724 {
7725 return 0;
7726 }
7727
7728 /* Round up a section size to the appropriate boundary. */
7729 valueT
7730 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7731 {
7732 #ifdef OBJ_AOUT
7733 /* For a.out, force the section size to be aligned. If we don't do
7734 this, BFD will align it for us, but it will not write out the
7735 final bytes of the section. This may be a bug in BFD, but it is
7736 easier to fix it here since that is how the other a.out targets
7737 work. */
7738 int align;
7739
7740 align = bfd_get_section_alignment (stdoutput, segment);
7741 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7742 #endif
7743
7744 return size;
7745 }
7746
7747 /* Exactly what point is a PC-relative offset relative TO?
7748 On the 68k, it is relative to the address of the first extension
7749 word. The difference between the addresses of the offset and the
7750 first extension word is stored in fx_pcrel_adjust. */
7751 long
7752 md_pcrel_from (fixS *fixP)
7753 {
7754 int adjust;
7755
7756 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7757 sign extend the value here. */
7758 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7759 if (adjust == 64)
7760 adjust = -1;
7761 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7762 }
7763
7764 #ifdef OBJ_ELF
7765 void
7766 m68k_elf_final_processing (void)
7767 {
7768 unsigned flags = 0;
7769
7770 if (arch_coldfire_fpu (current_architecture))
7771 flags |= EF_M68K_CFV4E;
7772 /* Set file-specific flags if this is a cpu32 processor. */
7773 if (cpu_of_arch (current_architecture) & cpu32)
7774 flags |= EF_M68K_CPU32;
7775 else if (cpu_of_arch (current_architecture) & fido_a)
7776 flags |= EF_M68K_FIDO;
7777 else if ((cpu_of_arch (current_architecture) & m68000up)
7778 && !(cpu_of_arch (current_architecture) & m68020up))
7779 flags |= EF_M68K_M68000;
7780
7781 if (current_architecture & mcfisa_a)
7782 {
7783 static const unsigned isa_features[][2] =
7784 {
7785 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7786 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7787 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7788 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7789 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7790 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7791 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
7792 {0,0},
7793 };
7794 static const unsigned mac_features[][2] =
7795 {
7796 {EF_M68K_CF_MAC, mcfmac},
7797 {EF_M68K_CF_EMAC, mcfemac},
7798 {0,0},
7799 };
7800 unsigned ix;
7801 unsigned pattern;
7802
7803 pattern = (current_architecture
7804 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7805 for (ix = 0; isa_features[ix][1]; ix++)
7806 {
7807 if (pattern == isa_features[ix][1])
7808 {
7809 flags |= isa_features[ix][0];
7810 break;
7811 }
7812 }
7813 if (!isa_features[ix][1])
7814 {
7815 cf_bad:
7816 as_warn (_("Not a defined coldfire architecture"));
7817 }
7818 else
7819 {
7820 if (current_architecture & cfloat)
7821 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7822
7823 pattern = current_architecture & (mcfmac|mcfemac);
7824 if (pattern)
7825 {
7826 for (ix = 0; mac_features[ix][1]; ix++)
7827 {
7828 if (pattern == mac_features[ix][1])
7829 {
7830 flags |= mac_features[ix][0];
7831 break;
7832 }
7833 }
7834 if (!mac_features[ix][1])
7835 goto cf_bad;
7836 }
7837 }
7838 }
7839 elf_elfheader (stdoutput)->e_flags |= flags;
7840 }
7841 #endif
7842
7843 int
7844 tc_m68k_regname_to_dw2regnum (char *regname)
7845 {
7846 unsigned int regnum;
7847 static const char *const regnames[] =
7848 {
7849 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7850 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7851 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7852 "pc"
7853 };
7854
7855 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7856 if (strcmp (regname, regnames[regnum]) == 0)
7857 return regnum;
7858
7859 return -1;
7860 }
7861
7862 void
7863 tc_m68k_frame_initial_instructions (void)
7864 {
7865 static int sp_regno = -1;
7866
7867 if (sp_regno < 0)
7868 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7869
7870 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7871 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7872 }
GDB Binutils - Deliverables
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