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cpu32 and -mno-688?1 support from p3
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
2 slow to compile, easy to find file.
3
4 Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21
22 #include <ctype.h>
23 #define NO_RELOC 0
24 #include "as.h"
25 #include "read.h"
26
27 #include "obstack.h"
28
29 /* note that this file includes real declarations and thus can only be included by one source file per executable. */
30 #include "opcode/m68k.h"
31
32 #ifdef TE_SUN
33 /* This variable contains the value to write out at the beginning of
34 the a.out file. The 2<<16 means that this is a 68020 file instead
35 of an old-style 68000 file */
36
37 long omagic = 2<<16|OMAGIC; /* Magic byte for header file */
38 #else
39 long omagic = OMAGIC;
40 #endif
41
42 /* This array holds the chars that always start a comment. If the
43 pre-processor is disabled, these aren't very useful */
44 const char comment_chars[] = "|";
45
46 /* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49 /* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52 /* Also note that comments like this one will always work. */
53 const char line_comment_chars[] = "#";
54
55 /* Chars that can be used to separate mant from exp in floating point nums */
56 const char EXP_CHARS[] = "eE";
57
58 /* Chars that mean this number is a floating point constant */
59 /* As in 0f12.456 */
60 /* or 0d1.2345e12 */
61
62 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
63
64 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
65 changed in read.c . Ideally it shouldn't have to know about it at all,
66 but nothing is ideal around here.
67 */
68
69 int md_reloc_size = 8; /* Size of relocation record */
70
71 /* Its an arbitrary name: This means I don't approve of it */
72 /* See flames below */
73 static struct obstack robyn;
74
75 #define TAB(x,y) (((x)<<2)+(y))
76 #define TABTYPE(xy) ((xy) >> 2)
77 #define BYTE 0
78 #define SHORT 1
79 #define LONG 2
80 #define SZ_UNDEF 3
81 #undef BRANCH
82 #define ABRANCH 1
83 #define FBRANCH 2
84 #define PCREL 3
85 #define BCC68000 4
86 #define DBCC 5
87 #define PCLEA 6
88
89 /* Operands we can parse: (And associated modes)
90
91 numb: 8 bit num
92 numw: 16 bit num
93 numl: 32 bit num
94 dreg: data reg 0-7
95 reg: address or data register
96 areg: address register
97 apc: address register, PC, ZPC or empty string
98 num: 16 or 32 bit num
99 num2: like num
100 sz: w or l if omitted, l assumed
101 scale: 1 2 4 or 8 if omitted, 1 assumed
102
103 7.4 IMMED #num --> NUM
104 0.? DREG dreg --> dreg
105 1.? AREG areg --> areg
106 2.? AINDR areg@ --> *(areg)
107 3.? AINC areg@+ --> *(areg++)
108 4.? ADEC areg@- --> *(--areg)
109 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
110 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
111 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
112 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
113 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
114 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
115 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
116 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
117 7.0 ABSL num:sz --> *(num)
118 num --> *(num) (sz L assumed)
119 *** MSCR otherreg --> Magic
120 With -l option
121 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
122 ?.? DINDR dreg@ --> (dreg) -- cas2 only
123
124 examples:
125 #foo #0x35 #12
126 d2
127 a4
128 a3@
129 a5@+
130 a6@-
131 a2@(12) pc@(14)
132 a1@(5,d2:w:1) @(45,d6:l:4)
133 pc@(a2) @(d4)
134 etc . . .
135
136
137 #name@(numw) -->turn into PC rel mode
138 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
139
140 */
141
142 enum operand_type {
143 IMMED = 1,
144 DREG,
145 AREG,
146 AINDR,
147 ADEC,
148 AINC,
149 AOFF,
150 AINDX,
151 APODX,
152 AMIND,
153 APRDX,
154 ABSL,
155 MSCR,
156 REGLST,
157 DINDR
158 };
159
160
161 struct m68k_exp {
162 char *e_beg;
163 char *e_end;
164 expressionS e_exp;
165 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
166 };
167
168 /* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
169 8-15==addr reg for operands that take both types */
170
171 enum _register {
172 DATA = 1, /* 1- 8 == data registers 0-7 */
173 DATA0 = DATA,
174 DATA1,
175 DATA2,
176 DATA3,
177 DATA4,
178 DATA5,
179 DATA6,
180 DATA7,
181
182 ADDR,
183 ADDR0 = ADDR,
184 ADDR1,
185 ADDR2,
186 ADDR3,
187 ADDR4,
188 ADDR5,
189 ADDR6,
190 ADDR7,
191
192 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
193 /* I think. . . */
194
195 SP = ADDR7,
196
197 FPREG, /* Eight FP registers */
198 FP0 = FPREG,
199 FP1,
200 FP2,
201 FP3,
202 FP4,
203 FP5,
204 FP6,
205 FP7,
206 COPNUM = (FPREG+8), /* Co-processor #1-#8 */
207 COP0 = COPNUM,
208 COP1,
209 COP2,
210 COP3,
211 COP4,
212 COP5,
213 COP6,
214 COP7,
215 PC, /* Program counter */
216 ZPC, /* Hack for Program space, but 0 addressing */
217 SR, /* Status Reg */
218 CCR, /* Condition code Reg */
219
220 /* These have to be in order for the movec instruction to work. */
221 USP, /* User Stack Pointer */
222 ISP, /* Interrupt stack pointer */
223 SFC,
224 DFC,
225 CACR,
226 VBR,
227 CAAR,
228 MSP,
229 ITT0,
230 ITT1,
231 DTT0,
232 DTT1,
233 MMUSR,
234 TC,
235 SRP,
236 URP,
237 /* end of movec ordering constraints */
238
239 FPI,
240 FPS,
241 FPC,
242
243 DRP, /* 68851 or 68030 MMU regs */
244 CRP,
245 CAL,
246 VAL,
247 SCC,
248 AC,
249 BAD,
250 BAD0 = BAD,
251 BAD1,
252 BAD2,
253 BAD3,
254 BAD4,
255 BAD5,
256 BAD6,
257 BAD7,
258 BAC,
259 BAC0 = BAC,
260 BAC1,
261 BAC2,
262 BAC3,
263 BAC4,
264 BAC5,
265 BAC6,
266 BAC7,
267 PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040)
268 and ACUSR on 68ec030 */
269 PCSR,
270
271 IC, /* instruction cache token */
272 DC, /* data cache token */
273 NC, /* no cache token */
274 BC, /* both caches token */
275
276 TT0, /* 68030 access control unit regs */
277 TT1,
278 };
279
280 /* Internal form of an operand. */
281 struct m68k_op {
282 char *error; /* Couldn't parse it */
283 enum operand_type mode; /* What mode this instruction is in. */
284 enum _register reg; /* Base register */
285 struct m68k_exp *con1;
286 int ireg; /* Index register */
287 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
288 int imul; /* Multipy ireg by this (1,2,4,or 8) */
289 struct m68k_exp *con2;
290 };
291
292 /* internal form of a 68020 instruction */
293 struct m68k_it {
294 char *error;
295 char *args; /* list of opcode info */
296 int numargs;
297
298 int numo; /* Number of shorts in opcode */
299 short opcode[11];
300
301 struct m68k_op operands[6];
302
303 int nexp; /* number of exprs in use */
304 struct m68k_exp exprs[4];
305
306 int nfrag; /* Number of frags we have to produce */
307 struct {
308 int fragoff; /* Where in the current opcode[] the frag ends */
309 symbolS *fadd;
310 long foff;
311 int fragty;
312 } fragb[4];
313
314 int nrel; /* Num of reloc strucs in use */
315 struct {
316 int n;
317 symbolS *add,
318 *sub;
319 long off;
320 char wid;
321 char pcrel;
322 } reloc[5]; /* Five is enough??? */
323 };
324
325 #define cpu_of_arch(x) ((x) & m68000up)
326 #define float_of_arch(x) ((x) & mfloat)
327 #define mmu_of_arch(x) ((x) & mmmu)
328
329 static struct m68k_it the_ins; /* the instruction being assembled */
330
331 /* Macros for adding things to the m68k_it struct */
332
333 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
334
335 /* Like addword, but goes BEFORE general operands */
336 #define insop(w) {int z;\
337 for(z=the_ins.numo;z>opcode->m_codenum;--z)\
338 the_ins.opcode[z]=the_ins.opcode[z-1];\
339 for(z=0;z<the_ins.nrel;z++)\
340 the_ins.reloc[z].n+=2;\
341 the_ins.opcode[opcode->m_codenum]=w;\
342 the_ins.numo++;\
343 }
344
345
346 #define add_exp(beg,end) (\
347 the_ins.exprs[the_ins.nexp].e_beg=beg,\
348 the_ins.exprs[the_ins.nexp].e_end=end,\
349 &the_ins.exprs[the_ins.nexp++]\
350 )
351
352
353 /* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/
354 #define add_fix(width,exp,pc_rel) {\
355 the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \
356 (((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\
357 the_ins.reloc[the_ins.nrel].add=adds((exp));\
358 the_ins.reloc[the_ins.nrel].sub=subs((exp));\
359 the_ins.reloc[the_ins.nrel].off=offs((exp));\
360 the_ins.reloc[the_ins.nrel].wid=width;\
361 the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\
362 }
363
364 #define add_frag(add,off,type) {\
365 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\
366 the_ins.fragb[the_ins.nfrag].fadd=add;\
367 the_ins.fragb[the_ins.nfrag].foff=off;\
368 the_ins.fragb[the_ins.nfrag++].fragty=type;\
369 }
370
371 #define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
372
373 #define seg(exp) ((exp)->e_exp.X_seg)
374 #define adds(exp) ((exp)->e_exp.X_add_symbol)
375 #define subs(exp) ((exp)->e_exp.X_subtract_symbol)
376 #define offs(exp) ((exp)->e_exp.X_add_number)
377
378
379 struct m68k_incant {
380 char *m_operands;
381 unsigned long m_opcode;
382 short m_opnum;
383 short m_codenum;
384 int m_arch;
385 struct m68k_incant *m_next;
386 };
387
388
389
390 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
391 #define gettwo(x) (((x)->m_opcode)&0xffff)
392
393
394 #if __STDC__ == 1
395
396 static char *crack_operand(char *str, struct m68k_op *opP);
397 static int get_num(struct m68k_exp *exp, int ok);
398 static int get_regs(int i, char *str, struct m68k_op *opP);
399 static int reverse_16_bits(int in);
400 static int reverse_8_bits(int in);
401 static int try_index(char **s, struct m68k_op *opP);
402 static void install_gen_operand(int mode, int val);
403 static void install_operand(int mode, int val);
404 static void s_bss(void);
405 static void s_data1(void);
406 static void s_data2(void);
407 static void s_even(void);
408 static void s_proc(void);
409
410 #else /* not __STDC__ */
411
412 static char *crack_operand();
413 static int get_num();
414 static int get_regs();
415 static int reverse_16_bits();
416 static int reverse_8_bits();
417 static int try_index();
418 static void install_gen_operand();
419 static void install_operand();
420 static void s_bss();
421 void s_align_bytes();
422 static void s_data1();
423 static void s_data2();
424 static void s_even();
425 static void s_proc();
426
427 #endif /* not __STDC__ */
428
429 static int current_architecture = 0;
430
431 /* BCC68000 is for patching in an extra jmp instruction for long offsets
432 on the 68000. The 68000 doesn't support long branches with branchs */
433
434 /* This table desribes how you change sizes for the various types of variable
435 size expressions. This version only supports two kinds. */
436
437 /* Note that calls to frag_var need to specify the maximum expansion needed */
438 /* This is currently 10 bytes for DBCC */
439
440 /* The fields are:
441 How far Forward this mode will reach:
442 How far Backward this mode will reach:
443 How many bytes this mode will add to the size of the frag
444 Which mode to go to if the offset won't fit in this one
445 */
446 const relax_typeS
447 md_relax_table[] = {
448 { 1, 1, 0, 0 }, /* First entries aren't used */
449 { 1, 1, 0, 0 }, /* For no good reason except */
450 { 1, 1, 0, 0 }, /* that the VAX doesn't either */
451 { 1, 1, 0, 0 },
452
453 { (127), (-128), 0, TAB(ABRANCH,SHORT)},
454 { (32767), (-32768), 2, TAB(ABRANCH,LONG) },
455 { 0, 0, 4, 0 },
456 { 1, 1, 0, 0 },
457
458 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
459 { (32767), (-32768), 2, TAB(FBRANCH,LONG)},
460 { 0, 0, 4, 0 },
461 { 1, 1, 0, 0 },
462
463 { 1, 1, 0, 0 }, /* PCREL doesn't come BYTE */
464 { (32767), (-32768), 2, TAB(PCREL,LONG)},
465 { 0, 0, 4, 0 },
466 { 1, 1, 0, 0 },
467
468 { (127), (-128), 0, TAB(BCC68000,SHORT)},
469 { (32767), (-32768), 2, TAB(BCC68000,LONG) },
470 { 0, 0, 6, 0 }, /* jmp long space */
471 { 1, 1, 0, 0 },
472
473 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
474 { (32767), (-32768), 2, TAB(DBCC,LONG) },
475 { 0, 0, 10, 0 }, /* bra/jmp long space */
476 { 1, 1, 0, 0 },
477
478 { 1, 1, 0, 0 }, /* PCLEA doesn't come BYTE */
479 { 32767, -32768, 2, TAB(PCLEA,LONG) },
480 { 0, 0, 6, 0 },
481 { 1, 1, 0, 0 },
482
483 };
484
485 /* These are the machine dependent pseudo-ops. These are included so
486 the assembler can work on the output from the SUN C compiler, which
487 generates these.
488 */
489
490 /* This table describes all the machine specific pseudo-ops the assembler
491 has to support. The fields are:
492 pseudo-op name without dot
493 function to call to execute this pseudo-op
494 Integer arg to pass to the function
495 */
496 const pseudo_typeS md_pseudo_table[] = {
497 { "data1", s_data1, 0 },
498 { "data2", s_data2, 0 },
499 { "bss", s_bss, 0 },
500 { "even", s_even, 0 },
501 { "skip", s_space, 0 },
502 { "proc", s_proc, 0 },
503 #ifdef TE_SUN3
504 { "align", s_align_bytes, 0 },
505 #endif
506 { 0, 0, 0 }
507 };
508
509
510 /* The mote pseudo ops are put into the opcode table, since they
511 don't start with a . they look like opcodes to gas.
512 */
513 extern void obj_coff_section();
514
515 const pseudo_typeS mote_pseudo_table[] =
516 {
517
518 { "dc.l", cons,4},
519 { "dc", cons,2},
520 { "dc.w", cons,2},
521 { "dc.b", cons,1},
522
523 { "ds.l", s_space,4},
524 { "ds", s_space,2},
525 { "ds.w", s_space,2},
526 { "ds.b", s_space,1},
527
528 { "xdef", s_globl, 0},
529 { "align", s_align_ptwo, 0},
530 #ifdef M68KCOFF
531 { "sect", obj_coff_section,0},
532 { "section", obj_coff_section,0},
533 #endif
534 0,
535 };
536
537 /* #define isbyte(x) ((x)>=-128 && (x)<=127) */
538 /* #define isword(x) ((x)>=-32768 && (x)<=32767) */
539
540 #define issbyte(x) ((x)>=-128 && (x)<=127)
541 #define isubyte(x) ((x)>=0 && (x)<=255)
542 #define issword(x) ((x)>=-32768 && (x)<=32767)
543 #define isuword(x) ((x)>=0 && (x)<=65535)
544
545 #define isbyte(x) ((x)>=-128 && (x)<=255)
546 #define isword(x) ((x)>=-32768 && (x)<=65535)
547 #define islong(x) (1)
548
549 extern char *input_line_pointer;
550
551 enum {
552 FAIL = 0,
553 OK = 1,
554 };
555
556 /* JF these tables here are for speed at the expense of size */
557 /* You can replace them with the #if 0 versions if you really
558 need space and don't mind it running a bit slower */
559
560 static char mklower_table[256];
561 #define mklower(c) (mklower_table[(unsigned char)(c)])
562 static char notend_table[256];
563 static char alt_notend_table[256];
564 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
565 alt_notend_table[(unsigned char)(s[1])])))
566
567 #if 0
568 #define mklower(c) (isupper(c) ? tolower(c) : c)
569 #endif
570
571
572 /* JF modified this to handle cases where the first part of a symbol name
573 looks like a register */
574
575 /*
576 * m68k_reg_parse() := if it looks like a register, return it's token &
577 * advance the pointer.
578 */
579
580 enum _register m68k_reg_parse(ccp)
581 register char **ccp;
582 {
583 char *start = *ccp;
584
585 if (isalpha(*start) && is_name_beginner(*start))
586 {
587 char c;
588 char *p = start;
589 symbolS *symbolP;
590
591 c = *p++;
592 while (isalpha(c) || isdigit(c))
593 {
594 c = *p++;
595 }
596
597 ;
598 * -- p = 0;
599 symbolP = symbol_find(start);
600 *p = c;
601
602 if (symbolP && S_GET_SEGMENT(symbolP) == SEG_REGISTER)
603 {
604 *ccp = p;
605 return S_GET_VALUE(symbolP);
606 }
607 }
608 return FAIL;
609
610
611 }
612
613 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
614 #define SKIP_W() { ss++; if(*ss==' ') ss++;}
615
616 /* Parse an index specification using Motorola syntax. */
617
618 static int
619 try_moto_index(s,opP)
620 char **s;
621 struct m68k_op *opP;
622 {
623 register int i;
624 char *ss;
625
626 ss= *s;
627 /* SKIP_W(); */
628 if(*ss==' ') ss++;
629 i=m68k_reg_parse(&ss);
630 if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */
631 opP->error="Invalid index register";
632 *s=ss;
633 return FAIL;
634 }
635 opP->ireg=i;
636 /* SKIP_W(); */
637 if(*ss==')') {
638 opP->isiz=0;
639 opP->imul=1;
640 SKIP_W();
641 *s=ss;
642 return OK;
643 }
644 if(*ss!='.') {
645 opP->error="Missing . in index register";
646 *s=ss;
647 return FAIL;
648 }
649 SKIP_W();
650 if(mklower(*ss)=='w') opP->isiz=2;
651 else if(mklower(*ss)=='l') opP->isiz=3;
652 else {
653 opP->error="Size spec not .W or .L";
654 *s=ss;
655 return FAIL;
656 }
657 SKIP_W();
658 if(*ss=='.' || *ss=='*') {
659 SKIP_W();
660 switch(*ss) {
661 case '1':
662 case '2':
663 case '4':
664 case '8':
665 opP->imul= *ss-'0';
666 break;
667 default:
668 opP->error="index multiplier not 1, 2, 4 or 8";
669 *s=ss;
670 return FAIL;
671 }
672 SKIP_W();
673 } else opP->imul=1;
674 if(*ss!=')') {
675 opP->error="Missing )";
676 *s=ss;
677 return FAIL;
678 }
679 SKIP_W();
680 *s=ss;
681 return OK;
682 }
683
684 /*
685 *
686 * try_index := data_or_address_register + ')' + SKIP_W
687 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
688 *
689 * multiplier := <empty>
690 * | ':' + multiplier_number
691 * ;
692 *
693 * multiplier_number := '1' | '2' | '4' | '8' ;
694 *
695 * size_spec := 'l' | 'L' | 'w' | 'W' ;
696 *
697 * SKIP_W := <empty> | ' ' ;
698 *
699 */
700
701 static int try_index(s,opP)
702 char **s;
703 struct m68k_op *opP;
704 {
705 register int i;
706 char *ss;
707
708 ss= *s;
709 /* SKIP_W(); */
710 i=m68k_reg_parse(&ss);
711 if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */
712 *s=ss;
713 return FAIL;
714 }
715 opP->ireg=i;
716 /* SKIP_W(); */
717 if(*ss==')') {
718 opP->isiz=0;
719 opP->imul=1;
720 SKIP_W();
721 *s=ss;
722 return OK;
723 }
724 if(*ss!=':') {
725 opP->error="Missing : in index register";
726 *s=ss;
727 return FAIL;
728 }
729 SKIP_W();
730 switch(*ss) {
731 case 'w':
732 case 'W':
733 opP->isiz=2;
734 break;
735 case 'l':
736 case 'L':
737 opP->isiz=3;
738 break;
739 default:
740 opP->error="Index register size spec not :w or :l";
741 *s=ss;
742 return FAIL;
743 }
744 SKIP_W();
745 if(*ss==':') {
746 SKIP_W();
747 switch(*ss) {
748 case '1':
749 case '2':
750 case '4':
751 case '8':
752 if (cpu_of_arch(current_architecture) < m68020) {
753 opP->error="no index scaling in pre-68020's";
754 *s=ss;
755 return FAIL;
756 }
757 opP->imul= *ss-'0';
758 break;
759 default:
760 opP->error="index multiplier not 1, 2, 4 or 8";
761 *s=ss;
762 return FAIL;
763 }
764 SKIP_W();
765 } else opP->imul=1;
766 if(*ss!=')') {
767 opP->error="Missing )";
768 *s=ss;
769 return FAIL;
770 }
771 SKIP_W();
772 *s=ss;
773 return OK;
774 } /* try_index() */
775
776 /* Ian Taylor expanded this function to accept both MIT and Motorola
777 syntax. I removed the old comment, since it was wrong. The syntax
778 this accepted even before my changes was complex and undocumented.
779 I mainly added a large case when the operand string does not
780 contain an '@', since the Motorola syntax does not use the '@'
781 character. */
782
783 int
784 m68k_ip_op(str,opP)
785 char *str;
786 register struct m68k_op *opP;
787 {
788 char *strend;
789 long i;
790 char *parse_index();
791 int needp;
792
793 if (*str==' ') {
794 str++;
795 } /* Find the beginning of the string */
796
797 if(!*str) {
798 opP->error="Missing operand";
799 return FAIL;
800 } /* Out of gas */
801
802 for(strend = str; *strend; strend++)
803 ;
804 --strend;
805
806 if(*str=='#') {
807 str++;
808 opP->con1=add_exp(str,strend);
809 opP->mode=IMMED;
810 return OK;
811 } /* Guess what: A constant. Shar and enjoy */
812
813 i = m68k_reg_parse(&str);
814
815 if (i!=FAIL) {
816 if(*str=='/' || *str=='-') {
817 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
818 opP->mode=REGLST;
819 return get_regs(i,str,opP);
820 }
821 if(*str=='\0') {
822 opP->reg=i;
823 /* "Rn" Register Direct mode */
824 if(i>=DATA+0 && i<=DATA+7)
825 opP->mode=DREG;
826 else if(i>=ADDR+0 && i<=ADDR+7)
827 opP->mode=AREG;
828 else
829 opP->mode=MSCR;
830 return OK;
831 }
832 }
833
834 if (*str!='@') {
835 char *stmp;
836
837 if ((stmp=strchr(str,'@')) != 0) {
838 opP->con1=add_exp(str,stmp-1);
839 if(stmp==strend) {
840 opP->mode=AINDX;
841 return(OK);
842 }
843
844 if ((current_architecture & m68020up) == 0) {
845 return(FAIL);
846 } /* if target is not a '20 or better */
847
848 stmp++;
849 if(*stmp++!='(' || *strend--!=')') {
850 opP->error="Malformed operand";
851 return(FAIL);
852 }
853 i=try_index(&stmp,opP);
854 opP->con2=add_exp(stmp,strend);
855
856 if (i == FAIL) {
857 opP->mode=AMIND;
858 } else {
859 opP->mode=APODX;
860 }
861 return(OK);
862 } /* if there's an '@' */
863
864 #ifndef MIT_SYNTAX_ONLY
865 /* The operand has no '@'. Try to parse it using
866 Motorola syntax. */
867 /* Logic of the parsing switch(*str):
868 case opP->mode =
869 ---- -----------
870 #anything IMMED 1
871 REG AREG or DREG or MSCR 3 or 2 or 13
872 REG- or REG/ REGLST 14
873 (REG) AINDR 4
874 (REG)+ AINC 6
875 (REG,INDX) AINDX 8
876 (EXPR,REG) AOFF 7
877 (EXPR,REG,INDX) AINDX 8
878 -(REG) ADEC 5
879 EXP2(REG) AOFF 7
880 EXP2(REG,INDX) AINDX 8
881 EXP2 ABSL 12
882
883 REG means truth(m68k_reg_parse(&str))
884 INDX means truth(try_moto_index(&str,opP))
885 EXPR means not REG
886 EXP2 means not REG and not '(' and not '-('
887 */
888
889 if(*str=='(') {
890 str++;
891 i=m68k_reg_parse(&str);
892 if((i<ADDR+0 || i>ADDR+7)
893 && (i<DATA+0 || i>DATA+7
894 || *str != ')' || str[1] != '0')
895 && i!=PC && i!=ZPC && i!=FAIL) {
896 /* Can't indirect off non address regs */
897 opP->error="Invalid indirect register";
898 return FAIL;
899 }
900 if(i!=FAIL) {
901 opP->reg=i;
902 if(*str==')') {
903 str++;
904 if(*str=='\0') {
905 /* "(An)" Address Register Indirect mode
906 or "(Dn)" for cas2. */
907 if (i>=DATA+0 && i<=DATA+7)
908 opP->mode=DINDR;
909 else
910 opP->mode=AINDR;
911 return OK;
912 }
913 if(*str=='+') {
914 if(str[1]=='\0') {
915 /* "(An)+" Register Indirect w Postincrement */
916 opP->mode=AINC;
917 return OK;
918 }
919 }
920 opP->error="Junk after indirect";
921 return FAIL;
922 }
923 if(*str==',') {
924 str++;
925 i=try_moto_index(&str,opP);
926 if(i==FAIL) return FAIL;
927 /* "(An,Rn)" Register Indirect with Index mode*/
928 opP->mode=AINDX;
929 return OK;
930 }
931 else {
932 opP->error="Bad indirect syntax";
933 return FAIL;
934 }
935 }
936 else {
937 /* "(EXPR,..." , a displacement */
938 char *stmp;
939 char *index();
940
941 if(stmp=index(str,',')) {
942 opP->con1=add_exp(str,stmp-1);
943 str=stmp;
944 SKIP_WHITE();
945 i=m68k_reg_parse(&str);
946 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC) {
947 /* Can't indirect off non address regs */
948 opP->error="Invalid indirect register";
949 return FAIL;
950 }
951 if(i!=FAIL) {
952 opP->reg=i;
953 if(*str==')') {
954 /* "(d,An)" Register Indirect w Displacement */
955 opP->mode=AOFF;
956 return OK;
957 }
958 if(*str==',') {
959 str++;
960 i=try_moto_index(&str,opP);
961 if(i==FAIL) return FAIL;
962 /* "(d,An,Rn)" Register Indirect with Index */
963 opP->mode=AINDX;
964 return OK;
965 }
966 else {
967 opP->error="Bad indirect syntax";
968 return FAIL;
969 }
970 }
971 else {
972 opP->error="Invalid register";
973 return FAIL;
974 }
975 }
976 else {
977 opP->mode = ABSL;
978 opP->con1 = add_exp(str-1,strend);
979 return OK;
980 }
981 }
982 }
983
984 if(*str=='-') {
985 if(str[1]=='(') {
986 str = str+2;
987 i=m68k_reg_parse(&str);
988 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL) {
989 /* Can't indirect off non address regs */
990 opP->error="Invalid indirect register";
991 return FAIL;
992 }
993 if(i!=FAIL) {
994 opP->reg=i;
995 if(*str==')') {
996 str++;
997 if(*str=='\0') {
998 /* "-(An)" Register Indirect with Predecrement */
999 opP->mode=ADEC;
1000 return OK;
1001 }
1002 opP->error="Junk after indirect";
1003 return FAIL;
1004 }
1005 opP->error="Bad indirect syntax";
1006 return FAIL;
1007 }
1008 opP->mode = ABSL;
1009 opP->con1 = add_exp(str-2,strend);
1010 return OK;
1011 }
1012 /* if '-' but not "-(', do nothing */
1013 }
1014
1015 /* whether *str=='-' or not */
1016 {
1017 /* "EXP2" or "EXP2(REG..." */
1018 char *stmp;
1019 char *index();
1020 if(stmp=index(str,'(')) {
1021 char *ostr=str;
1022
1023 opP->con1=add_exp(str,stmp-1);
1024 str=stmp+1;
1025 i=m68k_reg_parse(&str);
1026 if((i<ADDR+0 || i>ADDR+7) && i!=PC
1027 && i!=ZPC && i!=FAIL) {
1028 /* Can't indirect off non address regs */
1029 opP->error="Invalid indirect register";
1030 return FAIL;
1031 }
1032 if(i!=FAIL) {
1033 opP->reg=i;
1034 if(*str==')') {
1035 /* "d(An)" Register Indirect w Displacement */
1036 opP->mode=AOFF;
1037 return OK;
1038 }
1039 if(*str==',') {
1040 str++;
1041 i=try_moto_index(&str,opP);
1042 if(i==FAIL) return FAIL;
1043 /* "d(An,Rn)" Register Indirect with Index */
1044 opP->mode=AINDX;
1045 return OK;
1046 }
1047 else {
1048 opP->error="Bad indirect syntax";
1049 return FAIL;
1050 }
1051 }
1052 else {
1053 opP->mode = ABSL;
1054 opP->con1 = add_exp(ostr,strend);
1055 return OK;
1056 }
1057 }
1058 else {
1059 /* "EXP2" Absolute */
1060 opP->mode=ABSL;
1061 opP->isiz=0;
1062 if(strend[-1]=='.' || strend[-1]==':') {
1063 /* mode ==foo.[wl] */
1064 switch(*strend) {
1065 case 'w':
1066 case 'W':
1067 opP->isiz=2;
1068 strend-=2;
1069 break;
1070 case 'l':
1071 case 'L':
1072 opP->isiz=3;
1073 strend-=2;
1074 break;
1075 }
1076 }
1077 opP->con1=add_exp(str,strend);
1078 return OK;
1079 }
1080 }
1081 /*NOTREACHED*/
1082 #else /* defined (MIT_SYNTAX_ONLY) */
1083 opP->mode=ABSL;
1084 opP->con1=add_exp(str,strend);
1085 return OK;
1086 #endif /* defined (MIT_SYNTAX_ONLY) */
1087 }
1088
1089 opP->reg=i;
1090
1091 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1092 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL
1093 && (str[1] != '\0' || i<DATA+0 || i>DATA+7)) {
1094 opP->error="Invalid indirect register";
1095 return FAIL;
1096 }
1097 know(*str == '@');
1098
1099 str++;
1100 switch(*str) {
1101 case '\0':
1102 if (i<DATA+0 || i>DATA+7)
1103 opP->mode=AINDR;
1104 else
1105 opP->mode=DINDR;
1106 return OK;
1107 case '-':
1108 opP->mode=ADEC;
1109 return OK;
1110 case '+':
1111 opP->mode=AINC;
1112 return OK;
1113 case '(':
1114 str++;
1115 break;
1116 default:
1117 opP->error="Junk after indirect";
1118 return FAIL;
1119 }
1120 /* Some kind of indexing involved. Lets find out how bad it is */
1121 i=try_index(&str,opP);
1122 /* Didn't start with an index reg, maybe its offset or offset,reg */
1123 if(i==FAIL) {
1124 char *beg_str;
1125
1126 beg_str=str;
1127 for(i=1;i;) {
1128 switch(*str++) {
1129 case '\0':
1130 opP->error="Missing )";
1131 return FAIL;
1132 case ',': i=0; break;
1133 case '(': i++; break;
1134 case ')': --i; break;
1135 }
1136 }
1137 /* if(str[-3]==':') {
1138 int siz;
1139
1140 switch(str[-2]) {
1141 case 'b':
1142 case 'B':
1143 siz=1;
1144 break;
1145 case 'w':
1146 case 'W':
1147 siz=2;
1148 break;
1149 case 'l':
1150 case 'L':
1151 siz=3;
1152 break;
1153 default:
1154 opP->error="Specified size isn't :w or :l";
1155 return FAIL;
1156 }
1157 opP->con1=add_exp(beg_str,str-4);
1158 opP->con1->e_siz=siz;
1159 } else */
1160 opP->con1=add_exp(beg_str,str-2);
1161 /* Should be offset,reg */
1162 if(str[-1]==',') {
1163 i=try_index(&str,opP);
1164 if(i==FAIL) {
1165 opP->error="Malformed index reg";
1166 return FAIL;
1167 }
1168 }
1169 }
1170 /* We've now got offset) offset,reg) or reg) */
1171
1172 if (*str == '\0') {
1173 /* Th-the-thats all folks */
1174 if (opP->reg == FAIL) opP->mode = AINDX; /* Other form of indirect */
1175 else if(opP->ireg == FAIL) opP->mode = AOFF;
1176 else opP->mode = AINDX;
1177 return(OK);
1178 }
1179 /* Next thing had better be another @ */
1180 if (*str == '@') {
1181 if (str[1] == '(') {
1182 needp = 1;
1183 str+=2;
1184 }
1185 else {
1186 needp = 0;
1187 str++;
1188 }
1189 }
1190
1191 if ((current_architecture & m68020up) == 0) {
1192 return(FAIL);
1193 } /* if target is not a '20 or better */
1194
1195
1196 if(opP->ireg != FAIL) {
1197 opP->mode = APRDX;
1198
1199 i = try_index(&str, opP);
1200 if (i != FAIL) {
1201 opP->error = "Two index registers! not allowed!";
1202 return(FAIL);
1203 }
1204 } else {
1205 i = try_index(&str, opP);
1206 }
1207
1208 if (i == FAIL) {
1209 char *beg_str;
1210
1211 beg_str = str;
1212
1213 for (i = 1; i; ) {
1214 switch(*str++) {
1215 case '\0':
1216 if (needp)
1217 opP->error="Missing )";
1218 return(FAIL);
1219 break;
1220 case ',': i=0; break;
1221 case '(': i++; break;
1222 case ')': --i; break;
1223 }
1224 }
1225
1226 opP->con2=add_exp(beg_str,str-2);
1227
1228 if (str[-1] == ',') {
1229 if (opP->ireg != FAIL) {
1230 opP->error = "Can't have two index regs";
1231 return(FAIL);
1232 }
1233
1234 i = try_index(&str, opP);
1235
1236 if (i == FAIL) {
1237 opP->error = "malformed index reg";
1238 return(FAIL);
1239 }
1240
1241 opP->mode = APODX;
1242 } else if (opP->ireg != FAIL) {
1243 opP->mode = APRDX;
1244 } else {
1245 opP->mode = AMIND;
1246 }
1247 } else {
1248 opP->mode = APODX;
1249 }
1250
1251 if(*str!='\0') {
1252 opP->error="Junk after indirect";
1253 return FAIL;
1254 }
1255 return(OK);
1256 } /* m68k_ip_op() */
1257
1258
1259 #ifdef M68KCOFF
1260
1261 short tc_coff_fix2rtype(fixP)
1262 fixS *fixP;
1263 {
1264 return (fixP->fx_pcrel ?
1265 (fixP->fx_size == 1 ? R_PCRBYTE :
1266 fixP->fx_size == 2 ? R_PCRWORD :
1267 R_PCRLONG):
1268 (fixP->fx_size == 1 ? R_RELBYTE :
1269 fixP->fx_size == 2 ? R_RELWORD :
1270 R_RELLONG));
1271
1272
1273 }
1274
1275 #endif
1276
1277 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1278 main()
1279 {
1280 char buf[128];
1281 struct m68k_op thark;
1282
1283 for(;;) {
1284 if(!gets(buf))
1285 break;
1286 memset(&thark, '\0', sizeof(thark));
1287 if(!m68k_ip_op(buf,&thark)) printf("FAIL:");
1288 if(thark.error)
1289 printf("op1 error %s in %s\n",thark.error,buf);
1290 printf("mode %d, reg %d, ",thark.mode,thark.reg);
1291 if(thark.b_const)
1292 printf("Constant: '%.*s',",1+thark.e_const-thark.b_const,thark.b_const);
1293 printf("ireg %d, isiz %d, imul %d ",thark.ireg,thark.isiz,thark.imul);
1294 if(thark.b_iadd)
1295 printf("Iadd: '%.*s'",1+thark.e_iadd-thark.b_iadd,thark.b_iadd);
1296 printf("\n");
1297 }
1298 exit(0);
1299 }
1300
1301 #endif
1302
1303
1304 static struct hash_control* op_hash = NULL; /* handle of the OPCODE hash table
1305 NULL means any use before m68k_ip_begin()
1306 will crash */
1307
1308 \f
1309 /*
1310 * m 6 8 k _ i p ( )
1311 *
1312 * This converts a string into a 68k instruction.
1313 * The string must be a bare single instruction in sun format
1314 * with RMS-style 68020 indirects
1315 * (example: )
1316 *
1317 * It provides some error messages: at most one fatal error message (which
1318 * stops the scan) and at most one warning message for each operand.
1319 * The 68k instruction is returned in exploded form, since we have no
1320 * knowledge of how you parse (or evaluate) your expressions.
1321 * We do however strip off and decode addressing modes and operation
1322 * mnemonic.
1323 *
1324 * This function's value is a string. If it is not "" then an internal
1325 * logic error was found: read this code to assign meaning to the string.
1326 * No argument string should generate such an error string:
1327 * it means a bug in our code, not in the user's text.
1328 *
1329 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1330 * this function.
1331 */
1332
1333 /* JF this function no longer returns a useful value. Sorry */
1334 void m68k_ip (instring)
1335 char *instring;
1336 {
1337 register char *p;
1338 register struct m68k_op *opP;
1339 register struct m68k_incant *opcode;
1340 register char *s;
1341 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1342 char *pdot, *pdotmove;
1343 int siz1, siz2;
1344 char c;
1345 int losing;
1346 int opsfound;
1347 char *crack_operand();
1348 LITTLENUM_TYPE words[6];
1349 LITTLENUM_TYPE *wordp;
1350 unsigned long ok_arch = 0;
1351
1352 if (*instring == ' ')
1353 instring++; /* skip leading whitespace */
1354
1355 /* Scan up to end of operation-code, which MUST end in end-of-string
1356 or exactly 1 space. */
1357 pdot = 0;
1358 for (p = instring; *p != '\0'; p++) {
1359 if (*p == ' ')
1360 break;
1361 if (*p == '.')
1362 pdot = p;
1363 }
1364
1365 if (p == instring) {
1366 the_ins.error = "No operator";
1367 the_ins.opcode[0] = NULL;
1368 /* the_ins.numo=1; */
1369 return;
1370 }
1371
1372 /* p now points to the end of the opcode name, probably whitespace.
1373 make sure the name is null terminated by clobbering the whitespace,
1374 look it up in the hash table, then fix it back.
1375 Remove a dot, first, since the opcode tables have none. */
1376 if (pdot != NULL) {
1377 for (pdotmove=pdot; pdotmove<p; pdotmove++)
1378 *pdotmove=pdotmove[1];
1379 p--;
1380 }
1381
1382 c = *p;
1383 *p = '\0';
1384 opcode = (struct m68k_incant *)hash_find (op_hash, instring);
1385 *p = c;
1386
1387 if (pdot != NULL) {
1388 for (pdotmove=p; pdotmove>pdot; pdotmove--)
1389 *pdotmove=pdotmove[-1];
1390 *pdot='.';
1391 ++p;
1392 }
1393
1394 if (opcode == NULL) {
1395 the_ins.error = "Unknown operator";
1396 the_ins.opcode[0] = NULL;
1397 /* the_ins.numo=1; */
1398 return;
1399 }
1400
1401 /* found a legitimate opcode, start matching operands */
1402 while (*p == ' ') ++p;
1403
1404
1405 if (opcode->m_operands == 0) {
1406 char *old = input_line_pointer;
1407 *old = '\n';
1408 input_line_pointer = p;
1409 /* Ahh - it's a motorola style psuedo op */
1410 mote_pseudo_table[opcode->m_opnum].poc_handler
1411 ( mote_pseudo_table[opcode->m_opnum].poc_val);
1412 input_line_pointer = old;
1413 *old = 0;
1414
1415 return;
1416 }
1417
1418 for(opP = &the_ins.operands[0]; *p; opP++) {
1419
1420 p = crack_operand(p, opP);
1421
1422 if (opP->error) {
1423 the_ins.error=opP->error;
1424 return;
1425 }
1426 }
1427
1428 opsfound = opP - &the_ins.operands[0];
1429
1430 /* This ugly hack is to support the floating pt opcodes in their standard form */
1431 /* Essentially, we fake a first enty of type COP#1 */
1432 if (opcode->m_operands[0]=='I') {
1433 int n;
1434
1435 for(n=opsfound;n>0;--n)
1436 the_ins.operands[n]=the_ins.operands[n-1];
1437
1438 memset((char *)(&the_ins.operands[0]), '\0', sizeof(the_ins.operands[0]));
1439 the_ins.operands[0].mode=MSCR;
1440 the_ins.operands[0].reg=COPNUM; /* COP #1 */
1441 opsfound++;
1442 }
1443
1444 /* We've got the operands. Find an opcode that'll accept them */
1445 for (losing = 0; ; ) {
1446 /* if we didn't get the right number of ops,
1447 or we have no common model with this pattern
1448 then reject this pattern. */
1449
1450 if (opsfound != opcode->m_opnum
1451 || ((opcode->m_arch & current_architecture) == 0))
1452 {
1453 ++losing;
1454 ok_arch |= opcode->m_arch;
1455 }
1456 else {
1457 for (s=opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++) {
1458 /* Warning: this switch is huge! */
1459 /* I've tried to organize the cases into this order:
1460 non-alpha first, then alpha by letter. lower-case goes directly
1461 before uppercase counterpart. */
1462 /* Code with multiple case ...: gets sorted by the lowest case ...
1463 it belongs to. I hope this makes sense. */
1464 switch(*s) {
1465 case '!':
1466 if (opP->mode == MSCR || opP->mode == IMMED
1467 || opP->mode == DREG || opP->mode == AREG
1468 || opP->mode == AINC || opP->mode == ADEC
1469 || opP->mode == REGLST)
1470 losing++;
1471 break;
1472
1473 case '`':
1474 switch (opP->mode) {
1475 case MSCR: case IMMED: case DREG: case AREG:
1476 case AINC: case REGLST: case AINDR:
1477 losing++;
1478 }
1479 break;
1480
1481 case '#':
1482 if(opP->mode!=IMMED)
1483 losing++;
1484 else {
1485 long t;
1486
1487 t=get_num(opP->con1,80);
1488 if(s[1]=='b' && !isbyte(t))
1489 losing++;
1490 else if(s[1]=='w' && !isword(t))
1491 losing++;
1492 }
1493 break;
1494
1495 case '^':
1496 case 'T':
1497 if(opP->mode!=IMMED)
1498 losing++;
1499 break;
1500
1501 case '$':
1502 if(opP->mode==MSCR || opP->mode==AREG ||
1503 opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1504 losing++;
1505 break;
1506
1507 case '%':
1508 if(opP->mode==MSCR || opP->reg==PC ||
1509 opP->reg==ZPC || opP->mode==REGLST)
1510 losing++;
1511 break;
1512
1513
1514 case '&':
1515 if(opP->mode==MSCR || opP->mode==DREG ||
1516 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC ||
1517 opP->mode==AINC || opP->mode==ADEC || opP->mode==REGLST)
1518 losing++;
1519 break;
1520
1521 case '*':
1522 if(opP->mode==MSCR || opP->mode==REGLST)
1523 losing++;
1524 break;
1525
1526 case '+':
1527 if(opP->mode!=AINC)
1528 losing++;
1529 break;
1530
1531 case '-':
1532 if(opP->mode!=ADEC)
1533 losing++;
1534 break;
1535
1536 case '/':
1537 if(opP->mode==MSCR || opP->mode==AREG ||
1538 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->mode==REGLST)
1539 losing++;
1540 break;
1541
1542 case ';':
1543 if(opP->mode==MSCR || opP->mode==AREG || opP->mode==REGLST)
1544 losing++;
1545 break;
1546
1547 case '?':
1548 if(opP->mode==MSCR || opP->mode==AREG ||
1549 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->reg==PC ||
1550 opP->reg==ZPC || opP->mode==REGLST)
1551 losing++;
1552 break;
1553
1554 case '@':
1555 if(opP->mode==MSCR || opP->mode==AREG ||
1556 opP->mode==IMMED || opP->mode==REGLST)
1557 losing++;
1558 break;
1559
1560 case '~': /* For now! (JF FOO is this right?) */
1561 if(opP->mode==MSCR || opP->mode==DREG ||
1562 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1563 losing++;
1564 break;
1565
1566 case '3':
1567 if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1))
1568 losing++;
1569 break;
1570
1571 case 'A':
1572 if(opP->mode!=AREG)
1573 losing++;
1574 break;
1575 case 'a':
1576 if (opP->mode != AINDR) {
1577 ++losing;
1578 } /* if not address register indirect */
1579 break;
1580 case 'B': /* FOO */
1581 if(opP->mode!=ABSL || (flagseen['S'] && instring[0] == 'j'
1582 && instring[1] == 'b'
1583 && instring[2] == 's'
1584 && instring[3] == 'r'))
1585 losing++;
1586 break;
1587
1588 case 'C':
1589 if(opP->mode!=MSCR || opP->reg!=CCR)
1590 losing++;
1591 break;
1592
1593 case 'd': /* FOO This mode is a KLUDGE!! */
1594 if(opP->mode!=AOFF && (opP->mode!=ABSL ||
1595 opP->con1->e_beg[0]!='(' || opP->con1->e_end[0]!=')'))
1596 losing++;
1597 break;
1598
1599 case 'D':
1600 if(opP->mode!=DREG)
1601 losing++;
1602 break;
1603
1604 case 'F':
1605 if(opP->mode!=MSCR || opP->reg<(FPREG+0) || opP->reg>(FPREG+7))
1606 losing++;
1607 break;
1608
1609 case 'I':
1610 if(opP->mode!=MSCR || opP->reg<COPNUM ||
1611 opP->reg>=COPNUM+7)
1612 losing++;
1613 break;
1614
1615 case 'J':
1616 if (opP->mode != MSCR
1617 || opP->reg < USP
1618 || opP->reg > URP
1619 || cpu_of_arch(current_architecture) < m68010 /* before 68010 had none */
1620 || (cpu_of_arch(current_architecture) < m68020
1621 && opP->reg != SFC
1622 && opP->reg != DFC
1623 && opP->reg != USP
1624 && opP->reg != VBR) /* 68010's had only these */
1625 || (cpu_of_arch(current_architecture) < m68040
1626 && opP->reg != SFC
1627 && opP->reg != DFC
1628 && opP->reg != USP
1629 && opP->reg != VBR
1630 && opP->reg != CACR
1631 && opP->reg != CAAR
1632 && opP->reg != MSP
1633 && opP->reg != ISP) /* 680[23]0's have only these */
1634 || (cpu_of_arch(current_architecture) == m68040 /* 68040 has all but this */
1635 && opP->reg == CAAR)) {
1636 losing++;
1637 } /* doesn't cut it */
1638 break;
1639
1640 case 'k':
1641 if(opP->mode!=IMMED)
1642 losing++;
1643 break;
1644
1645 case 'l':
1646 case 'L':
1647 if(opP->mode==DREG || opP->mode==AREG || opP->mode==FPREG) {
1648 if(s[1]=='8')
1649 losing++;
1650 else {
1651 opP->mode=REGLST;
1652 opP->reg=1<<(opP->reg-DATA);
1653 }
1654 } else if(opP->mode!=REGLST) {
1655 losing++;
1656 } else if(s[1]=='8' && opP->reg&0x0FFffFF)
1657 losing++;
1658 else if(s[1]=='3' && opP->reg&0x7000000)
1659 losing++;
1660 break;
1661
1662 case 'M':
1663 if(opP->mode!=IMMED)
1664 losing++;
1665 else {
1666 long t;
1667
1668 t=get_num(opP->con1,80);
1669 if(!issbyte(t) || isvar(opP->con1))
1670 losing++;
1671 }
1672 break;
1673
1674 case 'O':
1675 if(opP->mode!=DREG && opP->mode!=IMMED)
1676 losing++;
1677 break;
1678
1679 case 'Q':
1680 if(opP->mode!=IMMED)
1681 losing++;
1682 else {
1683 long t;
1684
1685 t=get_num(opP->con1,80);
1686 if(t<1 || t>8 || isvar(opP->con1))
1687 losing++;
1688 }
1689 break;
1690
1691 case 'R':
1692 if(opP->mode!=DREG && opP->mode!=AREG)
1693 losing++;
1694 break;
1695
1696 case 'r':
1697 if (opP->mode!=AINDR && opP->mode!=DINDR)
1698 losing++;
1699 break;
1700
1701 case 's':
1702 if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC))
1703 losing++;
1704 break;
1705
1706 case 'S':
1707 if(opP->mode!=MSCR || opP->reg!=SR)
1708 losing++;
1709 break;
1710
1711 case 't':
1712 if (opP->mode != IMMED)
1713 losing++;
1714 else
1715 {
1716 long t = get_num (opP->con1, 80);
1717 if (t < 0 || t > 7 || isvar (opP->con1))
1718 losing++;
1719 }
1720 break;
1721
1722 case 'U':
1723 if(opP->mode!=MSCR || opP->reg!=USP)
1724 losing++;
1725 break;
1726
1727 /* JF these are out of order. We could put them
1728 in order if we were willing to put up with
1729 bunches of #ifdef m68851s in the code.
1730
1731 Don't forget that you need these operands
1732 to use 68030 MMU instructions. */
1733 #ifndef NO_68851
1734 /* Memory addressing mode used by pflushr */
1735 case '|':
1736 if(opP->mode==MSCR || opP->mode==DREG ||
1737 opP->mode==AREG || opP->mode==REGLST)
1738 losing++;
1739 break;
1740
1741 case 'f':
1742 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
1743 losing++;
1744 break;
1745
1746 case 'P':
1747 if (opP->mode != MSCR
1748 || (opP->reg != TC && opP->reg != CAL
1749 && opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
1750 losing++;
1751 break;
1752
1753 case 'V':
1754 if (opP->reg != VAL)
1755 losing++;
1756 break;
1757
1758 case 'W':
1759 if (opP->mode != MSCR
1760 || (opP->reg != DRP && opP->reg != SRP
1761 && opP->reg != CRP))
1762 losing++;
1763 break;
1764
1765 case 'X':
1766 if (opP->mode != MSCR ||
1767 (!(opP->reg >= BAD && opP->reg <= BAD+7) &&
1768 !(opP->reg >= BAC && opP->reg <= BAC+7)))
1769 losing++;
1770 break;
1771
1772 case 'Y':
1773 if (opP->reg != PSR)
1774 losing++;
1775 break;
1776
1777 case 'Z':
1778 if (opP->reg != PCSR)
1779 losing++;
1780 break;
1781 #endif
1782 case 'c':
1783 if (opP->reg != NC
1784 && opP->reg != IC
1785 && opP->reg != DC
1786 && opP->reg != BC) {
1787 losing++;
1788 } /* not a cache specifier. */
1789 break;
1790
1791 case '_':
1792 if (opP->mode != ABSL) {
1793 ++losing;
1794 } /* not absolute */
1795 break;
1796
1797 default:
1798 as_fatal("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
1799 *s, __LINE__, __FILE__);
1800 } /* switch on type of operand */
1801
1802 if (losing)
1803 break;
1804 } /* for each operand */
1805 } /* if immediately wrong */
1806
1807 if (!losing) {
1808 break;
1809 } /* got it. */
1810
1811 opcode = opcode->m_next;
1812
1813 if (!opcode) {
1814 if (ok_arch
1815 && !(ok_arch & current_architecture))
1816 {
1817 char buf[200], *cp;
1818 int len;
1819 strcpy (buf, "invalid instruction for this architecture; needs ");
1820 cp = buf + strlen (buf);
1821 switch (ok_arch)
1822 {
1823 case mfloat:
1824 strcpy (cp, "fpu (68040 or 68881/68882)");
1825 break;
1826 case mmmu:
1827 strcpy (cp, "mmu (68030 or 68851)");
1828 break;
1829 case m68020up:
1830 strcpy (cp, "68020 or higher");
1831 break;
1832 case m68000up:
1833 strcpy (cp, "68000 or higher");
1834 break;
1835 case m68010up:
1836 strcpy (cp, "68010 or higher");
1837 break;
1838 default:
1839 {
1840 int got_one = 0, idx;
1841 const static struct {
1842 int arch;
1843 const char *name;
1844 } archs[] = {
1845 m68000, "68000",
1846 m68010, "68010",
1847 m68020, "68020",
1848 m68030, "68030",
1849 m68040, "68040",
1850 cpu32, "cpu32",
1851 m68881, "68881",
1852 m68851, "68851",
1853 };
1854 for (idx = 0; idx < sizeof (archs)/sizeof (archs[0]); idx++)
1855 {
1856 if (archs[idx].arch & ok_arch)
1857 {
1858 if (got_one)
1859 {
1860 strcpy (cp, " or ");
1861 cp += strlen (cp);
1862 }
1863 got_one = 1;
1864 strcpy (cp, archs[idx].name);
1865 cp += strlen (cp);
1866 }
1867 }
1868 }
1869 }
1870 len = cp - buf + 1;
1871 cp = malloc (len);
1872 strcpy (cp, buf);
1873 the_ins.error = cp;
1874 }
1875 else
1876 the_ins.error = "operands mismatch";
1877 return;
1878 } /* Fell off the end */
1879
1880 losing = 0;
1881 }
1882
1883 /* now assemble it */
1884
1885 the_ins.args=opcode->m_operands;
1886 the_ins.numargs=opcode->m_opnum;
1887 the_ins.numo=opcode->m_codenum;
1888 the_ins.opcode[0]=getone(opcode);
1889 the_ins.opcode[1]=gettwo(opcode);
1890
1891 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) {
1892 /* This switch is a doozy.
1893 Watch the first step; its a big one! */
1894 switch(s[0]) {
1895
1896 case '*':
1897 case '~':
1898 case '%':
1899 case ';':
1900 case '@':
1901 case '!':
1902 case '&':
1903 case '$':
1904 case '?':
1905 case '/':
1906 case '`':
1907 #ifndef NO_68851
1908 case '|':
1909 #endif
1910 switch(opP->mode) {
1911 case IMMED:
1912 tmpreg=0x3c; /* 7.4 */
1913 if (strchr("bwl",s[1])) nextword=get_num(opP->con1,80);
1914 else nextword=nextword=get_num(opP->con1,0);
1915 if(isvar(opP->con1))
1916 add_fix(s[1],opP->con1,0);
1917 switch(s[1]) {
1918 case 'b':
1919 if(!isbyte(nextword))
1920 opP->error="operand out of range";
1921 addword(nextword);
1922 baseo=0;
1923 break;
1924 case 'w':
1925 if(!isword(nextword))
1926 opP->error="operand out of range";
1927 addword(nextword);
1928 baseo=0;
1929 break;
1930 case 'l':
1931 addword(nextword>>16);
1932 addword(nextword);
1933 baseo=0;
1934 break;
1935
1936 case 'f':
1937 baseo=2;
1938 outro=8;
1939 break;
1940 case 'F':
1941 baseo=4;
1942 outro=11;
1943 break;
1944 case 'x':
1945 baseo=6;
1946 outro=15;
1947 break;
1948 case 'p':
1949 baseo=6;
1950 outro= -1;
1951 break;
1952 default:
1953 as_fatal("Internal error: Can't decode %c%c in line %s of file \"%s\"",
1954 *s, s[1], __LINE__, __FILE__);
1955 }
1956 if(!baseo)
1957 break;
1958
1959 /* We gotta put out some float */
1960 if(seg(opP->con1)!=SEG_BIG) {
1961 int_to_gen(nextword);
1962 gen_to_words(words,baseo,(long int)outro);
1963 for(wordp=words;baseo--;wordp++)
1964 addword(*wordp);
1965 break;
1966 } /* Its BIG */
1967 if(offs(opP->con1)>0) {
1968 as_warn("Bignum assumed to be binary bit-pattern");
1969 if(offs(opP->con1)>baseo) {
1970 as_warn("Bignum too big for %c format; truncated",s[1]);
1971 offs(opP->con1)=baseo;
1972 }
1973 baseo-=offs(opP->con1);
1974 for(wordp=generic_bignum+offs(opP->con1)-1;offs(opP->con1)--;--wordp)
1975 addword(*wordp);
1976 while(baseo--)
1977 addword(0);
1978 break;
1979 }
1980 gen_to_words(words,baseo,(long)outro);
1981 for (wordp=words;baseo--;wordp++)
1982 addword(*wordp);
1983 break;
1984 case DREG:
1985 tmpreg=opP->reg-DATA; /* 0.dreg */
1986 break;
1987 case AREG:
1988 tmpreg=0x08+opP->reg-ADDR; /* 1.areg */
1989 break;
1990 case AINDR:
1991 tmpreg=0x10+opP->reg-ADDR; /* 2.areg */
1992 break;
1993 case ADEC:
1994 tmpreg=0x20+opP->reg-ADDR; /* 4.areg */
1995 break;
1996 case AINC:
1997 tmpreg=0x18+opP->reg-ADDR; /* 3.areg */
1998 break;
1999 case AOFF:
2000
2001 nextword=get_num(opP->con1,80);
2002 /* Force into index mode. Hope this works */
2003
2004 /* We do the first bit for 32-bit displacements,
2005 and the second bit for 16 bit ones. It is
2006 possible that we should make the default be
2007 WORD instead of LONG, but I think that'd
2008 break GCC, so we put up with a little
2009 inefficiency for the sake of working output.
2010 */
2011
2012 if( !issword(nextword)
2013 || ( isvar(opP->con1)
2014 && ( ( opP->con1->e_siz==0
2015 && flagseen['l']==0)
2016 || opP->con1->e_siz==3))) {
2017
2018 if(opP->reg==PC)
2019 tmpreg=0x3B; /* 7.3 */
2020 else
2021 tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
2022 if(isvar(opP->con1)) {
2023 if(opP->reg==PC) {
2024 add_frag(adds(opP->con1),
2025 offs(opP->con1),
2026 TAB(PCLEA,SZ_UNDEF));
2027 break;
2028 } else {
2029 addword(0x0170);
2030 add_fix('l',opP->con1,0);
2031 }
2032 } else
2033 addword(0x0170);
2034 addword(nextword>>16);
2035 } else {
2036 if(opP->reg==PC)
2037 tmpreg=0x3A; /* 7.2 */
2038 else
2039 tmpreg=0x28+opP->reg-ADDR; /* 5.areg */
2040
2041 if(isvar(opP->con1)) {
2042 if(opP->reg==PC) {
2043 add_fix('w',opP->con1,1);
2044 } else
2045 add_fix('w',opP->con1,0);
2046 }
2047 }
2048 addword(nextword);
2049 break;
2050
2051 case APODX:
2052 case AMIND:
2053 case APRDX:
2054 know(current_architecture & m68020up);
2055 /* intentional fall-through */
2056 case AINDX:
2057 nextword=0;
2058 baseo=get_num(opP->con1,80);
2059 outro=get_num(opP->con2,80);
2060 /* Figure out the 'addressing mode' */
2061 /* Also turn on the BASE_DISABLE bit, if needed */
2062 if(opP->reg==PC || opP->reg==ZPC) {
2063 tmpreg=0x3b; /* 7.3 */
2064 if(opP->reg==ZPC)
2065 nextword|=0x80;
2066 } else if(opP->reg==FAIL) {
2067 nextword|=0x80;
2068 tmpreg=0x30; /* 6.garbage */
2069 } else tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
2070
2071 siz1= (opP->con1) ? opP->con1->e_siz : 0;
2072 siz2= (opP->con2) ? opP->con2->e_siz : 0;
2073
2074 /* Index register stuff */
2075 if(opP->ireg>=DATA+0 && opP->ireg<=ADDR+7) {
2076 nextword|=(opP->ireg-DATA)<<12;
2077
2078 if(opP->isiz==0 || opP->isiz==3)
2079 nextword|=0x800;
2080 switch(opP->imul) {
2081 case 1: break;
2082 case 2: nextword|=0x200; break;
2083 case 4: nextword|=0x400; break;
2084 case 8: nextword|=0x600; break;
2085 default: as_fatal("failed sanity check.");
2086 }
2087 /* IF its simple,
2088 GET US OUT OF HERE! */
2089
2090 /* Must be INDEX, with an index
2091 register. Address register
2092 cannot be ZERO-PC, and either
2093 :b was forced, or we know
2094 it will fit */
2095 if( opP->mode==AINDX
2096 && opP->reg!=FAIL
2097 && opP->reg!=ZPC
2098 && ( siz1==1
2099 || ( issbyte(baseo)
2100 && !isvar(opP->con1)))) {
2101 nextword +=baseo&0xff;
2102 addword(nextword);
2103 if(isvar(opP->con1))
2104 add_fix('B',opP->con1,0);
2105 break;
2106 }
2107 } else
2108 nextword|=0x40; /* No index reg */
2109
2110 /* It aint simple */
2111 nextword|=0x100;
2112 /* If the guy specified a width, we assume that
2113 it is wide enough. Maybe it isn't. If so, we lose
2114 */
2115 switch(siz1) {
2116 case 0:
2117 if(isvar(opP->con1) || !issword(baseo)) {
2118 siz1=3;
2119 nextword|=0x30;
2120 } else if(baseo==0)
2121 nextword|=0x10;
2122 else {
2123 nextword|=0x20;
2124 siz1=2;
2125 }
2126 break;
2127 case 1:
2128 as_warn("Byte dispacement won't work. Defaulting to :w");
2129 case 2:
2130 nextword|=0x20;
2131 break;
2132 case 3:
2133 nextword|=0x30;
2134 break;
2135 }
2136
2137 /* Figure out innner displacement stuff */
2138 if(opP->mode!=AINDX) {
2139 switch(siz2) {
2140 case 0:
2141 if(isvar(opP->con2) || !issword(outro)) {
2142 siz2=3;
2143 nextword|=0x3;
2144 } else if(outro==0)
2145 nextword|=0x1;
2146 else {
2147 nextword|=0x2;
2148 siz2=2;
2149 }
2150 break;
2151 case 1:
2152 as_warn("Byte dispacement won't work. Defaulting to :w");
2153 case 2:
2154 nextword|=0x2;
2155 break;
2156 case 3:
2157 nextword|=0x3;
2158 break;
2159 }
2160 if(opP->mode==APODX) nextword|=0x04;
2161 else if(opP->mode==AMIND) nextword|=0x40;
2162 }
2163 addword(nextword);
2164
2165 if(isvar(opP->con1)) {
2166 if(opP->reg==PC || opP->reg==ZPC) {
2167 add_fix(siz1==3 ? 'l' : 'w',opP->con1,1);
2168 opP->con1->e_exp.X_add_number+=6;
2169 } else
2170 add_fix(siz1==3 ? 'l' : 'w',opP->con1,0);
2171 }
2172 if(siz1==3)
2173 addword(baseo>>16);
2174 if(siz1)
2175 addword(baseo);
2176
2177 if(isvar(opP->con2)) {
2178 if(opP->reg==PC || opP->reg==ZPC) {
2179 add_fix(siz2==3 ? 'l' : 'w',opP->con2,1);
2180 opP->con1->e_exp.X_add_number+=6;
2181 } else
2182 add_fix(siz2==3 ? 'l' : 'w',opP->con2,0);
2183 }
2184 if(siz2==3)
2185 addword(outro>>16);
2186 if(siz2)
2187 addword(outro);
2188
2189 break;
2190
2191 case ABSL:
2192 nextword=get_num(opP->con1,80);
2193 switch(opP->con1->e_siz) {
2194 default:
2195 as_warn("Unknown size for absolute reference");
2196 case 0:
2197 if(!isvar(opP->con1) && issword(offs(opP->con1))) {
2198 tmpreg=0x38; /* 7.0 */
2199 addword(nextword);
2200 break;
2201 }
2202 /* Don't generate pc relative code
2203 on 68010 and 68000 */
2204 if(isvar(opP->con1)
2205 && !subs(opP->con1)
2206 && seg(opP->con1) == SEG_TEXT
2207 && now_seg == SEG_TEXT
2208 && cpu_of_arch(current_architecture) >= m68020
2209 && !flagseen['S']
2210 && !strchr("~%&$?", s[0])) {
2211 tmpreg=0x3A; /* 7.2 */
2212 add_frag(adds(opP->con1),
2213 offs(opP->con1),
2214 TAB(PCREL,SZ_UNDEF));
2215 break;
2216 }
2217 case 3: /* Fall through into long */
2218 if(isvar(opP->con1))
2219 add_fix('l',opP->con1,0);
2220
2221 tmpreg=0x39; /* 7.1 mode */
2222 addword(nextword>>16);
2223 addword(nextword);
2224 break;
2225
2226 case 2: /* Word */
2227 if(isvar(opP->con1))
2228 add_fix('w',opP->con1,0);
2229
2230 tmpreg=0x38; /* 7.0 mode */
2231 addword(nextword);
2232 break;
2233 }
2234 break;
2235 case DINDR:
2236 as_bad("invalid indirect register");
2237 break;
2238 case MSCR:
2239 default:
2240 as_bad("unknown/incorrect operand");
2241 /* abort(); */
2242 }
2243 install_gen_operand(s[1],tmpreg);
2244 break;
2245
2246 case '#':
2247 case '^':
2248 switch(s[1]) { /* JF: I hate floating point! */
2249 case 'j':
2250 tmpreg=70;
2251 break;
2252 case '8':
2253 tmpreg=20;
2254 break;
2255 case 'C':
2256 tmpreg=50;
2257 break;
2258 case '3':
2259 default:
2260 tmpreg=80;
2261 break;
2262 }
2263 tmpreg=get_num(opP->con1,tmpreg);
2264 if(isvar(opP->con1))
2265 add_fix(s[1],opP->con1,0);
2266 switch(s[1]) {
2267 case 'b': /* Danger: These do no check for
2268 certain types of overflow.
2269 user beware! */
2270 if(!isbyte(tmpreg))
2271 opP->error="out of range";
2272 insop(tmpreg);
2273 if(isvar(opP->con1))
2274 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2275 break;
2276 case 'w':
2277 if(!isword(tmpreg))
2278 opP->error="out of range";
2279 insop(tmpreg);
2280 if(isvar(opP->con1))
2281 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2282 break;
2283 case 'l':
2284 insop(tmpreg); /* Because of the way insop works, we put these two out backwards */
2285 insop(tmpreg>>16);
2286 if(isvar(opP->con1))
2287 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2288 break;
2289 case '3':
2290 tmpreg&=0xFF;
2291 case '8':
2292 case 'C':
2293 install_operand(s[1],tmpreg);
2294 break;
2295 default:
2296 as_fatal("Internal error: Unknown mode #%c in line %s of file \"%s\"", s[1], __LINE__, __FILE__);
2297 }
2298 break;
2299
2300 case '+':
2301 case '-':
2302 case 'A':
2303 case 'a':
2304 install_operand(s[1],opP->reg-ADDR);
2305 break;
2306
2307 case 'B':
2308 tmpreg=get_num(opP->con1,80);
2309 switch(s[1]) {
2310 case 'B':
2311 /* Needs no offsetting */
2312 add_fix('B',opP->con1,1);
2313 break;
2314 case 'W':
2315 /* Offset the displacement to be relative to byte disp location */
2316 opP->con1->e_exp.X_add_number+=2;
2317 add_fix('w',opP->con1,1);
2318 addword(0);
2319 break;
2320 case 'L':
2321 long_branch:
2322 if (cpu_of_arch(current_architecture) < m68020) /* 68000 or 010 */
2323 as_warn("Can't use long branches on 68000/68010");
2324 the_ins.opcode[the_ins.numo-1]|=0xff;
2325 /* Offset the displacement to be relative to byte disp location */
2326 opP->con1->e_exp.X_add_number+=4;
2327 add_fix('l',opP->con1,1);
2328 addword(0);
2329 addword(0);
2330 break;
2331 case 'g':
2332 if(subs(opP->con1)) /* We can't relax it */
2333 goto long_branch;
2334
2335 /* This could either be a symbol, or an
2336 absolute address. No matter, the
2337 frag hacking will finger it out.
2338 Not quite: it can't switch from
2339 BRANCH to BCC68000 for the case
2340 where opnd is absolute (it needs
2341 to use the 68000 hack since no
2342 conditional abs jumps). */
2343 if (((cpu_of_arch(current_architecture) < m68020) || (0==adds(opP->con1)))
2344 && (the_ins.opcode[0] >= 0x6200)
2345 && (the_ins.opcode[0] <= 0x6f00)) {
2346 add_frag(adds(opP->con1),offs(opP->con1),TAB(BCC68000,SZ_UNDEF));
2347 } else {
2348 add_frag(adds(opP->con1),offs(opP->con1),TAB(ABRANCH,SZ_UNDEF));
2349 }
2350 break;
2351 case 'w':
2352 if(isvar(opP->con1)) {
2353 /* check for DBcc instruction */
2354 if ((the_ins.opcode[0] & 0xf0f8) ==0x50c8) {
2355 /* size varies if patch */
2356 /* needed for long form */
2357 add_frag(adds(opP->con1),offs(opP->con1),TAB(DBCC,SZ_UNDEF));
2358 break;
2359 }
2360
2361 /* Don't ask! */
2362 opP->con1->e_exp.X_add_number+=2;
2363 add_fix('w',opP->con1,1);
2364 }
2365 addword(0);
2366 break;
2367 case 'C': /* Fixed size LONG coproc branches */
2368 the_ins.opcode[the_ins.numo-1]|=0x40;
2369 /* Offset the displacement to be relative to byte disp location */
2370 /* Coproc branches don't have a byte disp option, but they are
2371 compatible with the ordinary branches, which do... */
2372 opP->con1->e_exp.X_add_number+=4;
2373 add_fix('l',opP->con1,1);
2374 addword(0);
2375 addword(0);
2376 break;
2377 case 'c': /* Var size Coprocesssor branches */
2378 if(subs(opP->con1)) {
2379 add_fix('l',opP->con1,1);
2380 add_frag((symbolS *)0,(long)0,TAB(FBRANCH,LONG));
2381 } else if(adds(opP->con1)) {
2382 add_frag(adds(opP->con1),offs(opP->con1),TAB(FBRANCH,SZ_UNDEF));
2383 } else {
2384 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2385 the_ins.opcode[the_ins.numo-1]|=0x40;
2386 add_fix('l',opP->con1,1);
2387 addword(0);
2388 addword(4);
2389 }
2390 break;
2391 default:
2392 as_fatal("Internal error: operand type B%c unknown in line %s of file \"%s\"",
2393 s[1], __LINE__, __FILE__);
2394 }
2395 break;
2396
2397 case 'C': /* Ignore it */
2398 break;
2399
2400 case 'd': /* JF this is a kludge */
2401 if(opP->mode==AOFF) {
2402 install_operand('s',opP->reg-ADDR);
2403 } else {
2404 char *tmpP;
2405
2406 tmpP=opP->con1->e_end-2;
2407 opP->con1->e_beg++;
2408 opP->con1->e_end-=4; /* point to the , */
2409 baseo=m68k_reg_parse(&tmpP);
2410 if(baseo<ADDR+0 || baseo>ADDR+7) {
2411 as_bad("Unknown address reg, using A0");
2412 baseo=0;
2413 } else baseo-=ADDR;
2414 install_operand('s',baseo);
2415 }
2416 tmpreg=get_num(opP->con1,80);
2417 if(!issword(tmpreg)) {
2418 as_warn("Expression out of range, using 0");
2419 tmpreg=0;
2420 }
2421 addword(tmpreg);
2422 break;
2423
2424 case 'D':
2425 install_operand(s[1],opP->reg-DATA);
2426 break;
2427
2428 case 'F':
2429 install_operand(s[1],opP->reg-FPREG);
2430 break;
2431
2432 case 'I':
2433 tmpreg=1+opP->reg-COPNUM;
2434 if(tmpreg==8)
2435 tmpreg=0;
2436 install_operand(s[1],tmpreg);
2437 break;
2438
2439 case 'J': /* JF foo */
2440 switch(opP->reg) {
2441 case SFC: tmpreg=0x000; break;
2442 case DFC: tmpreg=0x001; break;
2443 case CACR: tmpreg=0x002; break;
2444 case TC: tmpreg=0x003; break;
2445 case ITT0: tmpreg=0x004; break;
2446 case ITT1: tmpreg=0x005; break;
2447 case DTT0: tmpreg=0x006; break;
2448 case DTT1: tmpreg=0x007; break;
2449
2450 case USP: tmpreg=0x800; break;
2451 case VBR: tmpreg=0x801; break;
2452 case CAAR: tmpreg=0x802; break;
2453 case MSP: tmpreg=0x803; break;
2454 case ISP: tmpreg=0x804; break;
2455 case MMUSR: tmpreg=0x805; break;
2456 case URP: tmpreg=0x806; break;
2457 case SRP: tmpreg=0x807; break;
2458 default:
2459 as_fatal("failed sanity check.");
2460 }
2461 install_operand(s[1],tmpreg);
2462 break;
2463
2464 case 'k':
2465 tmpreg=get_num(opP->con1,55);
2466 install_operand(s[1],tmpreg&0x7f);
2467 break;
2468
2469 case 'l':
2470 tmpreg=opP->reg;
2471 if(s[1]=='w') {
2472 if(tmpreg&0x7FF0000)
2473 as_bad("Floating point register in register list");
2474 insop(reverse_16_bits(tmpreg));
2475 } else {
2476 if(tmpreg&0x700FFFF)
2477 as_bad("Wrong register in floating-point reglist");
2478 install_operand(s[1],reverse_8_bits(tmpreg>>16));
2479 }
2480 break;
2481
2482 case 'L':
2483 tmpreg=opP->reg;
2484 if(s[1]=='w') {
2485 if(tmpreg&0x7FF0000)
2486 as_bad("Floating point register in register list");
2487 insop(tmpreg);
2488 } else if(s[1]=='8') {
2489 if(tmpreg&0x0FFFFFF)
2490 as_bad("incorrect register in reglist");
2491 install_operand(s[1],tmpreg>>24);
2492 } else {
2493 if(tmpreg&0x700FFFF)
2494 as_bad("wrong register in floating-point reglist");
2495 else
2496 install_operand(s[1],tmpreg>>16);
2497 }
2498 break;
2499
2500 case 'M':
2501 install_operand(s[1],get_num(opP->con1,60));
2502 break;
2503
2504 case 'O':
2505 tmpreg= (opP->mode==DREG)
2506 ? 0x20+opP->reg-DATA
2507 : (get_num(opP->con1,40)&0x1F);
2508 install_operand(s[1],tmpreg);
2509 break;
2510
2511 case 'Q':
2512 tmpreg=get_num(opP->con1,10);
2513 if(tmpreg==8)
2514 tmpreg=0;
2515 install_operand(s[1],tmpreg);
2516 break;
2517
2518 case 'R':
2519 case 'r':
2520 /* This depends on the fact that ADDR registers are
2521 eight more than their corresponding DATA regs, so
2522 the result will have the ADDR_REG bit set */
2523 install_operand(s[1],opP->reg-DATA);
2524 break;
2525
2526 case 's':
2527 if(opP->reg==FPI) tmpreg=0x1;
2528 else if(opP->reg==FPS) tmpreg=0x2;
2529 else if(opP->reg==FPC) tmpreg=0x4;
2530 else as_fatal("failed sanity check.");
2531 install_operand(s[1],tmpreg);
2532 break;
2533
2534 case 'S': /* Ignore it */
2535 break;
2536
2537 case 'T':
2538 install_operand(s[1],get_num(opP->con1,30));
2539 break;
2540
2541 case 'U': /* Ignore it */
2542 break;
2543
2544 case 'c':
2545 switch (opP->reg) {
2546 case NC: tmpreg = 0; break;
2547 case DC: tmpreg = 1; break;
2548 case IC: tmpreg = 2; break;
2549 case BC: tmpreg = 3; break;
2550 default:
2551 as_fatal("failed sanity check");
2552 } /* switch on cache token */
2553 install_operand(s[1], tmpreg);
2554 break;
2555 #ifndef NO_68851
2556 /* JF: These are out of order, I fear. */
2557 case 'f':
2558 switch (opP->reg) {
2559 case SFC:
2560 tmpreg=0;
2561 break;
2562 case DFC:
2563 tmpreg=1;
2564 break;
2565 default:
2566 as_fatal("failed sanity check.");
2567 }
2568 install_operand(s[1],tmpreg);
2569 break;
2570
2571 case 'P':
2572 switch(opP->reg) {
2573 case TC:
2574 tmpreg=0;
2575 break;
2576 case CAL:
2577 tmpreg=4;
2578 break;
2579 case VAL:
2580 tmpreg=5;
2581 break;
2582 case SCC:
2583 tmpreg=6;
2584 break;
2585 case AC:
2586 tmpreg=7;
2587 break;
2588 default:
2589 as_fatal("failed sanity check.");
2590 }
2591 install_operand(s[1],tmpreg);
2592 break;
2593
2594 case 'V':
2595 if (opP->reg == VAL)
2596 break;
2597 as_fatal("failed sanity check.");
2598
2599 case 'W':
2600 switch(opP->reg) {
2601
2602 case DRP:
2603 tmpreg=1;
2604 break;
2605 case SRP:
2606 tmpreg=2;
2607 break;
2608 case CRP:
2609 tmpreg=3;
2610 break;
2611 default:
2612 as_fatal("failed sanity check.");
2613 }
2614 install_operand(s[1],tmpreg);
2615 break;
2616
2617 case 'X':
2618 switch (opP->reg) {
2619 case BAD: case BAD+1: case BAD+2: case BAD+3:
2620 case BAD+4: case BAD+5: case BAD+6: case BAD+7:
2621 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2622 break;
2623
2624 case BAC: case BAC+1: case BAC+2: case BAC+3:
2625 case BAC+4: case BAC+5: case BAC+6: case BAC+7:
2626 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2627 break;
2628
2629 default:
2630 as_fatal("failed sanity check.");
2631 }
2632 install_operand(s[1], tmpreg);
2633 break;
2634 case 'Y':
2635 know(opP->reg == PSR);
2636 break;
2637 case 'Z':
2638 know(opP->reg == PCSR);
2639 break;
2640 #endif /* m68851 */
2641 case '3':
2642 switch (opP->reg)
2643 {
2644 case TT0:
2645 tmpreg = 2;
2646 break;
2647 case TT1:
2648 tmpreg = 3;
2649 break;
2650 default:
2651 as_fatal ("failed sanity check");
2652 }
2653 install_operand (s[1], tmpreg);
2654 break;
2655 case 't':
2656 tmpreg = get_num (opP->con1, 20);
2657 install_operand (s[1], tmpreg);
2658 break;
2659 case '_': /* used only for move16 absolute 32-bit address */
2660 tmpreg=get_num(opP->con1,80);
2661 addword (tmpreg >> 16);
2662 addword (tmpreg & 0xFFFF);
2663 break;
2664 default:
2665 as_fatal("Internal error: Operand type %c unknown in line %d of file \"%s\"",
2666 s[0], __LINE__, __FILE__);
2667 }
2668 }
2669
2670 /* By the time whe get here (FINALLY) the_ins contains the complete
2671 instruction, ready to be emitted. . . */
2672 } /* m68k_ip() */
2673
2674 /*
2675 * get_regs := '/' + ?
2676 * | '-' + <register>
2677 * | '-' + <register> + ?
2678 * | <empty>
2679 * ;
2680 *
2681
2682 * The idea here must be to scan in a set of registers but I don't
2683 * understand it. Looks awfully sloppy to me but I don't have any doc on
2684 * this format so...
2685
2686 *
2687 *
2688 */
2689
2690 static int get_regs(i,str,opP)
2691 int i;
2692 struct m68k_op *opP;
2693 char *str;
2694 {
2695 /* 26, 25, 24, 23-16, 15-8, 0-7 */
2696 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
2697 unsigned long cur_regs = 0;
2698 int reg1,
2699 reg2;
2700
2701 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
2702 else if(x==FPS) cur_regs|=(1<<25);\
2703 else if(x==FPC) cur_regs|=(1<<26);\
2704 else cur_regs|=(1<<(x-1)); }
2705
2706 reg1=i;
2707 for(;;) {
2708 if(*str=='/') {
2709 ADD_REG(reg1);
2710 str++;
2711 } else if(*str=='-') {
2712 str++;
2713 reg2=m68k_reg_parse(&str);
2714 if(reg2<DATA || reg2>=FPREG+8 || reg1==FPI || reg1==FPS || reg1==FPC) {
2715 opP->error="unknown register in register list";
2716 return FAIL;
2717 }
2718 while(reg1<=reg2) {
2719 ADD_REG(reg1);
2720 reg1++;
2721 }
2722 if(*str=='\0')
2723 break;
2724 } else if(*str=='\0') {
2725 ADD_REG(reg1);
2726 break;
2727 } else {
2728 opP->error="unknow character in register list";
2729 return FAIL;
2730 }
2731 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
2732 if (*str=='/')
2733 str ++;
2734 reg1=m68k_reg_parse(&str);
2735 if((reg1<DATA || reg1>=FPREG+8) && !(reg1==FPI || reg1==FPS || reg1==FPC)) {
2736 opP->error="unknown register in register list";
2737 return FAIL;
2738 }
2739 }
2740 opP->reg=cur_regs;
2741 return OK;
2742 } /* get_regs() */
2743
2744 static int reverse_16_bits(in)
2745 int in;
2746 {
2747 int out=0;
2748 int n;
2749
2750 static int mask[16] = {
2751 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2752 0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000
2753 };
2754 for(n=0;n<16;n++) {
2755 if(in&mask[n])
2756 out|=mask[15-n];
2757 }
2758 return out;
2759 } /* reverse_16_bits() */
2760
2761 static int reverse_8_bits(in)
2762 int in;
2763 {
2764 int out=0;
2765 int n;
2766
2767 static int mask[8] = {
2768 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2769 };
2770
2771 for(n=0;n<8;n++) {
2772 if(in&mask[n])
2773 out|=mask[7-n];
2774 }
2775 return out;
2776 } /* reverse_8_bits() */
2777
2778 static void install_operand(mode,val)
2779 int mode;
2780 int val;
2781 {
2782 switch(mode) {
2783 case 's':
2784 the_ins.opcode[0]|=val & 0xFF; /* JF FF is for M kludge */
2785 break;
2786 case 'd':
2787 the_ins.opcode[0]|=val<<9;
2788 break;
2789 case '1':
2790 the_ins.opcode[1]|=val<<12;
2791 break;
2792 case '2':
2793 the_ins.opcode[1]|=val<<6;
2794 break;
2795 case '3':
2796 the_ins.opcode[1]|=val;
2797 break;
2798 case '4':
2799 the_ins.opcode[2]|=val<<12;
2800 break;
2801 case '5':
2802 the_ins.opcode[2]|=val<<6;
2803 break;
2804 case '6':
2805 /* DANGER! This is a hack to force cas2l and cas2w cmds
2806 to be three words long! */
2807 the_ins.numo++;
2808 the_ins.opcode[2]|=val;
2809 break;
2810 case '7':
2811 the_ins.opcode[1]|=val<<7;
2812 break;
2813 case '8':
2814 the_ins.opcode[1]|=val<<10;
2815 break;
2816 #ifndef NO_68851
2817 case '9':
2818 the_ins.opcode[1]|=val<<5;
2819 break;
2820 #endif
2821
2822 case 't':
2823 the_ins.opcode[1]|=(val<<10)|(val<<7);
2824 break;
2825 case 'D':
2826 the_ins.opcode[1]|=(val<<12)|val;
2827 break;
2828 case 'g':
2829 the_ins.opcode[0]|=val=0xff;
2830 break;
2831 case 'i':
2832 the_ins.opcode[0]|=val<<9;
2833 break;
2834 case 'C':
2835 the_ins.opcode[1]|=val;
2836 break;
2837 case 'j':
2838 the_ins.opcode[1]|=val;
2839 the_ins.numo++; /* What a hack */
2840 break;
2841 case 'k':
2842 the_ins.opcode[1]|=val<<4;
2843 break;
2844 case 'b':
2845 case 'w':
2846 case 'l':
2847 break;
2848 case 'e':
2849 the_ins.opcode[0] |= (val << 6);
2850 break;
2851 case 'L':
2852 the_ins.opcode[1] = (val >> 16);
2853 the_ins.opcode[2] = val & 0xffff;
2854 break;
2855 case 'c':
2856 default:
2857 as_fatal("failed sanity check.");
2858 }
2859 } /* install_operand() */
2860
2861 static void install_gen_operand(mode,val)
2862 int mode;
2863 int val;
2864 {
2865 switch(mode) {
2866 case 's':
2867 the_ins.opcode[0]|=val;
2868 break;
2869 case 'd':
2870 /* This is a kludge!!! */
2871 the_ins.opcode[0]|=(val&0x07)<<9|(val&0x38)<<3;
2872 break;
2873 case 'b':
2874 case 'w':
2875 case 'l':
2876 case 'f':
2877 case 'F':
2878 case 'x':
2879 case 'p':
2880 the_ins.opcode[0]|=val;
2881 break;
2882 /* more stuff goes here */
2883 default:
2884 as_fatal("failed sanity check.");
2885 }
2886 } /* install_gen_operand() */
2887
2888 /*
2889 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2890 * then deal with the bitfield hack.
2891 */
2892
2893 static char *crack_operand(str,opP)
2894 register char *str;
2895 register struct m68k_op *opP;
2896 {
2897 register int parens;
2898 register int c;
2899 register char *beg_str;
2900
2901 if(!str) {
2902 return str;
2903 }
2904 beg_str=str;
2905 for(parens=0;*str && (parens>0 || notend(str));str++) {
2906 if(*str=='(') parens++;
2907 else if(*str==')') {
2908 if(!parens) { /* ERROR */
2909 opP->error="Extra )";
2910 return str;
2911 }
2912 --parens;
2913 }
2914 }
2915 if(!*str && parens) { /* ERROR */
2916 opP->error="Missing )";
2917 return str;
2918 }
2919 c= *str;
2920 *str='\0';
2921 if(m68k_ip_op(beg_str,opP)==FAIL) {
2922 *str=c;
2923 return str;
2924 }
2925 *str=c;
2926 if(c=='}')
2927 c= *++str; /* JF bitfield hack */
2928 if(c) {
2929 c= *++str;
2930 if(!c)
2931 as_bad("Missing operand");
2932 }
2933 return str;
2934 }
2935
2936 /* See the comment up above where the #define notend(... is */
2937 #if 0
2938 notend(s)
2939 char *s;
2940 {
2941 if(*s==',') return 0;
2942 if(*s=='{' || *s=='}')
2943 return 0;
2944 if(*s!=':') return 1;
2945 /* This kludge here is for the division cmd, which is a kludge */
2946 if(index("aAdD#",s[1])) return 0;
2947 return 1;
2948 }
2949 #endif
2950
2951 /* This is the guts of the machine-dependent assembler. STR points to a
2952 machine dependent instruction. This function is supposed to emit
2953 the frags/bytes it assembles to.
2954 */
2955
2956 void
2957 insert_reg(regname, regnum)
2958 char *regname;
2959 int regnum;
2960 {
2961 char buf[100];
2962 int i;
2963 symbol_table_insert(symbol_new(regname, SEG_REGISTER, regnum, &zero_address_frag));
2964
2965 for (i = 0; regname[i]; i++)
2966 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2967 buf[i] = '\0';
2968
2969 symbol_table_insert(symbol_new(buf, SEG_REGISTER, regnum, &zero_address_frag));
2970 }
2971
2972 static const struct {
2973 char *name;
2974 int number;
2975 } init_table[] = {
2976 "d0", DATA0,
2977 "d1", DATA1,
2978 "d2", DATA2,
2979 "d3", DATA3,
2980 "d4", DATA4,
2981 "d5", DATA5,
2982 "d6", DATA6,
2983 "d7", DATA7,
2984 "a0", ADDR0,
2985 "a1", ADDR1,
2986 "a2", ADDR2,
2987 "a3", ADDR3,
2988 "a4", ADDR4,
2989 "a5", ADDR5,
2990 "a6", ADDR6,
2991 "fp", ADDR6,
2992 "a7", ADDR7,
2993 "sp", ADDR7,
2994 "fp0", FP0,
2995 "fp1", FP1,
2996 "fp2", FP2,
2997 "fp3", FP3,
2998 "fp4", FP4,
2999 "fp5", FP5,
3000 "fp6", FP6,
3001 "fp7", FP7,
3002 "fpi", FPI,
3003 "fpiar", FPI,
3004 "fpc", FPI,
3005 "fps", FPS,
3006 "fpsr", FPS,
3007 "fpc", FPC,
3008 "fpcr", FPC,
3009
3010 "cop0", COP0,
3011 "cop1", COP1,
3012 "cop2", COP2,
3013 "cop3", COP3,
3014 "cop4", COP4,
3015 "cop5", COP5,
3016 "cop6", COP6,
3017 "cop7", COP7,
3018 "pc", PC,
3019 "zpc", ZPC,
3020 "sr", SR,
3021
3022 "ccr", CCR,
3023 "cc", CCR,
3024
3025 "usp", USP,
3026 "isp", ISP,
3027 "sfc", SFC,
3028 "dfc", DFC,
3029 "cacr", CACR,
3030 "caar", CAAR,
3031
3032 "vbr", VBR,
3033
3034 "msp", MSP,
3035 "itt0", ITT0,
3036 "itt1", ITT1,
3037 "dtt0", DTT0,
3038 "dtt1", DTT1,
3039 "mmusr", MMUSR,
3040 "tc", TC,
3041 "srp", SRP,
3042 "urp", URP,
3043
3044 "ac", AC,
3045 "bc", BC,
3046 "cal", CAL,
3047 "crp", CRP,
3048 "drp", DRP,
3049 "pcsr", PCSR,
3050 "psr", PSR,
3051 "scc", SCC,
3052 "val", VAL,
3053 "bad0", BAD0,
3054 "bad1", BAD1,
3055 "bad2", BAD2,
3056 "bad3", BAD3,
3057 "bad4", BAD4,
3058 "bad5", BAD5,
3059 "bad6", BAD6,
3060 "bad7", BAD7,
3061 "bac0", BAC0,
3062 "bac1", BAC1,
3063 "bac2", BAC2,
3064 "bac3", BAC3,
3065 "bac4", BAC4,
3066 "bac5", BAC5,
3067 "bac6", BAC6,
3068 "bac7", BAC7,
3069
3070 "ic", IC,
3071 "dc", DC,
3072 "nc", NC,
3073
3074 "tt0", TT0,
3075 "tt1", TT1,
3076 /* 68ec030 versions of same */
3077 "ac0", TT0,
3078 "ac1", TT1,
3079 /* 68ec030 access control unit, identical to 030 MMU status reg */
3080 "acusr", PSR,
3081
3082 0,
3083
3084 };
3085
3086
3087 void
3088 init_regtable()
3089 {
3090 int i;
3091 for (i = 0; init_table[i].name; i++)
3092 insert_reg(init_table[i].name, init_table[i].number);
3093 }
3094
3095 static int no_68851, no_68881;
3096
3097 void
3098 md_assemble(str)
3099 char *str;
3100 {
3101 char *er;
3102 short *fromP;
3103 char *toP = NULL;
3104 int m,n = 0;
3105 char *to_beg_P;
3106 int shorts_this_frag;
3107 static int done_first_time;
3108
3109 if (!done_first_time)
3110 {
3111 done_first_time = 1;
3112
3113 if (cpu_of_arch (current_architecture) == 0)
3114 {
3115 int cpu_type;
3116
3117 #ifndef TARGET_CPU
3118 cpu_type = m68020;
3119 #else
3120 if (strcmp (TARGET_CPU, "m68000") == 0)
3121 cpu_type = m68000;
3122 else if (strcmp (TARGET_CPU, "m68010") == 0)
3123 cpu_type = m68010;
3124 else if (strcmp (TARGET_CPU, "m68020") == 0
3125 || strcmp (TARGET_CPU, "m68k") == 0)
3126 cpu_type = m68020;
3127 else if (strcmp (TARGET_CPU, "m68030") == 0)
3128 cpu_type = m68030;
3129 else if (strcmp (TARGET_CPU, "m68040") == 0)
3130 cpu_type = m68040;
3131 else if (strcmp (TARGET_CPU, "cpu32") == 0)
3132 cpu_type = cpu32;
3133 else
3134 cpu_type = m68020;
3135 #endif
3136
3137 current_architecture |= cpu_type;
3138 }
3139 if (current_architecture & m68881)
3140 {
3141 if (current_architecture & m68000)
3142 as_bad ("incompatible processors 68000 and 68881/2 specified");
3143 if (current_architecture & m68010)
3144 as_bad ("incompatible processors 68010 and 68881/2 specified");
3145 if (current_architecture & m68040)
3146 as_bad ("incompatible processors 68040 and 68881/2 specified");
3147 }
3148 /* What other incompatibilities ought we to check for? */
3149
3150 /* Toss in some default assumptions about coprocessors. */
3151 if (!no_68881
3152 && (cpu_of_arch (current_architecture)
3153 /* Can CPU32 have a 68881 coprocessor?? */
3154 & (m68020 | m68030 | cpu32)))
3155 {
3156 current_architecture |= m68881;
3157 }
3158 if (!no_68851
3159 && (cpu_of_arch (current_architecture) & m68020up) != 0)
3160 {
3161 current_architecture |= m68851;
3162 }
3163 if (no_68881 && (current_architecture & m68881))
3164 as_bad ("options for 68881 and no-68881 both given");
3165 if (no_68851 && (current_architecture & m68851))
3166 as_bad ("options for 68851 and no-68851 both given");
3167 done_first_time = 1;
3168 }
3169
3170 memset((char *)(&the_ins), '\0', sizeof(the_ins)); /* JF for paranoia sake */
3171 m68k_ip(str);
3172 er=the_ins.error;
3173 if(!er) {
3174 for(n=the_ins.numargs;n;--n)
3175 if(the_ins.operands[n].error) {
3176 er=the_ins.operands[n].error;
3177 break;
3178 }
3179 }
3180 if(er) {
3181 as_bad("%s -- statement `%s' ignored",er,str);
3182 return;
3183 }
3184
3185 if(the_ins.nfrag==0) { /* No frag hacking involved; just put it out */
3186 toP=frag_more(2*the_ins.numo);
3187 fromP= &the_ins.opcode[0];
3188 for(m=the_ins.numo;m;--m) {
3189 md_number_to_chars(toP,(long)(*fromP),2);
3190 toP+=2;
3191 fromP++;
3192 }
3193 /* put out symbol-dependent info */
3194 for(m=0;m<the_ins.nrel;m++) {
3195 switch(the_ins.reloc[m].wid) {
3196 case 'B':
3197 n=1;
3198 break;
3199 case 'b':
3200 n=1;
3201 break;
3202 case '3':
3203 n=2;
3204 break;
3205 case 'w':
3206 n=2;
3207 break;
3208 case 'l':
3209 n=4;
3210 break;
3211 default:
3212 as_fatal("Don't know how to figure width of %c in md_assemble()",the_ins.reloc[m].wid);
3213 }
3214
3215 fix_new(frag_now,
3216 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
3217 n,
3218 the_ins.reloc[m].add,
3219 the_ins.reloc[m].sub,
3220 the_ins.reloc[m].off,
3221 the_ins.reloc[m].pcrel,
3222 NO_RELOC);
3223 }
3224 return;
3225 }
3226
3227 /* There's some frag hacking */
3228 for(n=0,fromP= &the_ins.opcode[0];n<the_ins.nfrag;n++) {
3229 int wid;
3230
3231 if(n==0) wid=2*the_ins.fragb[n].fragoff;
3232 else wid=2*(the_ins.numo-the_ins.fragb[n-1].fragoff);
3233 toP=frag_more(wid);
3234 to_beg_P=toP;
3235 shorts_this_frag=0;
3236 for(m=wid/2;m;--m) {
3237 md_number_to_chars(toP,(long)(*fromP),2);
3238 toP+=2;
3239 fromP++;
3240 shorts_this_frag++;
3241 }
3242 for(m=0;m<the_ins.nrel;m++) {
3243 if((the_ins.reloc[m].n)>= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */) {
3244 the_ins.reloc[m].n-= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */;
3245 break;
3246 }
3247 wid=the_ins.reloc[m].wid;
3248 if(wid==0)
3249 continue;
3250 the_ins.reloc[m].wid=0;
3251 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
3252
3253 fix_new(frag_now,
3254 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
3255 wid,
3256 the_ins.reloc[m].add,
3257 the_ins.reloc[m].sub,
3258 the_ins.reloc[m].off,
3259 the_ins.reloc[m].pcrel,
3260 NO_RELOC);
3261 }
3262 /* know(the_ins.fragb[n].fadd); */
3263 (void)frag_var(rs_machine_dependent,10,0,(relax_substateT)(the_ins.fragb[n].fragty),
3264 the_ins.fragb[n].fadd,the_ins.fragb[n].foff,to_beg_P);
3265 }
3266 n=(the_ins.numo-the_ins.fragb[n-1].fragoff);
3267 shorts_this_frag=0;
3268 if(n) {
3269 toP=frag_more(n*sizeof(short));
3270 while(n--) {
3271 md_number_to_chars(toP,(long)(*fromP),2);
3272 toP+=2;
3273 fromP++;
3274 shorts_this_frag++;
3275 }
3276 }
3277 for(m=0;m<the_ins.nrel;m++) {
3278 int wid;
3279
3280 wid=the_ins.reloc[m].wid;
3281 if(wid==0)
3282 continue;
3283 the_ins.reloc[m].wid=0;
3284 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
3285
3286 fix_new(frag_now,
3287 (the_ins.reloc[m].n + toP-frag_now->fr_literal)-/* the_ins.numo */ shorts_this_frag*2,
3288 wid,
3289 the_ins.reloc[m].add,
3290 the_ins.reloc[m].sub,
3291 the_ins.reloc[m].off,
3292 the_ins.reloc[m].pcrel,
3293 NO_RELOC);
3294 }
3295 }
3296
3297
3298
3299 void
3300 md_begin()
3301 {
3302 /*
3303 * md_begin -- set up hash tables with 68000 instructions.
3304 * similar to what the vax assembler does. ---phr
3305 */
3306 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3307 a copy of it at runtime, adding in the information we want but isn't
3308 there. I think it'd be better to have an awk script hack the table
3309 at compile time. Or even just xstr the table and use it as-is. But
3310 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3311 names. */
3312
3313 register const struct m68k_opcode *ins;
3314 register struct m68k_incant *hack,
3315 *slak;
3316 register char *retval = 0; /* empty string, or error msg text */
3317 register unsigned int i;
3318 register char c;
3319
3320 if ((op_hash = hash_new()) == NULL)
3321 as_fatal("Virtual memory exhausted");
3322
3323 obstack_begin(&robyn,4000);
3324 for (ins = m68k_opcodes; ins < endop; ins++) {
3325 hack=slak=(struct m68k_incant *)obstack_alloc(&robyn,sizeof(struct m68k_incant));
3326 do {
3327 /* we *could* ignore insns that don't match our
3328 arch here but just leaving them out of the
3329 hash. */
3330 slak->m_operands=ins->args;
3331 slak->m_opnum=strlen(slak->m_operands)/2;
3332 slak->m_arch = ins->arch;
3333 slak->m_opcode=ins->opcode;
3334 /* This is kludgey */
3335 slak->m_codenum=((ins->match)&0xffffL) ? 2 : 1;
3336 if((ins+1)!=endop && !strcmp(ins->name,(ins+1)->name)) {
3337 slak->m_next=(struct m68k_incant *) obstack_alloc(&robyn,sizeof(struct m68k_incant));
3338 ins++;
3339 } else
3340 slak->m_next=0;
3341 slak=slak->m_next;
3342 } while(slak);
3343
3344 retval = hash_insert (op_hash, ins->name,(char *)hack);
3345 /* Didn't his mommy tell him about null pointers? */
3346 if(retval && *retval)
3347 as_bad("Internal Error: Can't hash %s: %s",ins->name,retval);
3348 }
3349
3350 for (i = 0; i < sizeof(mklower_table) ; i++)
3351 mklower_table[i] = (isupper(c = (char) i)) ? tolower(c) : c;
3352
3353 for (i = 0 ; i < sizeof(notend_table) ; i++) {
3354 notend_table[i] = 0;
3355 alt_notend_table[i] = 0;
3356 }
3357 notend_table[','] = 1;
3358 notend_table['{'] = 1;
3359 notend_table['}'] = 1;
3360 alt_notend_table['a'] = 1;
3361 alt_notend_table['A'] = 1;
3362 alt_notend_table['d'] = 1;
3363 alt_notend_table['D'] = 1;
3364 alt_notend_table['#'] = 1;
3365 alt_notend_table['f'] = 1;
3366 alt_notend_table['F'] = 1;
3367 #ifdef REGISTER_PREFIX
3368 alt_notend_table[REGISTER_PREFIX] = 1;
3369 #endif
3370
3371 #ifndef MIT_SYNTAX_ONLY
3372 /* Insert pseudo ops, these have to go into the opcode table since
3373 gas expects pseudo ops to start with a dot */
3374 {
3375 int n = 0;
3376 while (mote_pseudo_table[n].poc_name)
3377 {
3378 hack=(struct m68k_incant *)
3379 obstack_alloc(&robyn,sizeof(struct m68k_incant));
3380 hash_insert(op_hash,
3381 mote_pseudo_table[n].poc_name, (char *)hack);
3382 hack->m_operands = 0;
3383 hack->m_opnum = n;
3384 n++;
3385 }
3386 }
3387 #endif
3388
3389 init_regtable();
3390 }
3391
3392 #if 0
3393 #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
3394 || (*s == ':' && strchr("aAdD#", s[1]))) \
3395 ? 0 : 1)
3396 #endif
3397
3398 /* This funciton is called once, before the assembler exits. It is
3399 supposed to do any final cleanup for this part of the assembler.
3400 */
3401 void
3402 md_end()
3403 {
3404 }
3405
3406 /* Equal to MAX_PRECISION in atof-ieee.c */
3407 #define MAX_LITTLENUMS 6
3408
3409 /* Turn a string in input_line_pointer into a floating point constant of type
3410 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3411 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
3412 */
3413 char *
3414 md_atof(type,litP,sizeP)
3415 char type;
3416 char *litP;
3417 int *sizeP;
3418 {
3419 int prec;
3420 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3421 LITTLENUM_TYPE *wordP;
3422 char *t;
3423 char *atof_ieee();
3424
3425 switch(type) {
3426 case 'f':
3427 case 'F':
3428 case 's':
3429 case 'S':
3430 prec = 2;
3431 break;
3432
3433 case 'd':
3434 case 'D':
3435 case 'r':
3436 case 'R':
3437 prec = 4;
3438 break;
3439
3440 case 'x':
3441 case 'X':
3442 prec = 6;
3443 break;
3444
3445 case 'p':
3446 case 'P':
3447 prec = 6;
3448 break;
3449
3450 default:
3451 *sizeP=0;
3452 return "Bad call to MD_ATOF()";
3453 }
3454 t=atof_ieee(input_line_pointer,type,words);
3455 if(t)
3456 input_line_pointer=t;
3457
3458 *sizeP=prec * sizeof(LITTLENUM_TYPE);
3459 for(wordP=words;prec--;) {
3460 md_number_to_chars(litP,(long)(*wordP++),sizeof(LITTLENUM_TYPE));
3461 litP+=sizeof(LITTLENUM_TYPE);
3462 }
3463 return ""; /* Someone should teach Dean about null pointers */
3464 }
3465
3466 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3467 for use in the a.out file, and stores them in the array pointed to by buf.
3468 This knows about the endian-ness of the target machine and does
3469 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3470 2 (short) and 4 (long) Floating numbers are put out as a series of
3471 LITTLENUMS (shorts, here at least)
3472 */
3473 void
3474 md_number_to_chars(buf,val,n)
3475 char *buf;
3476 long val;
3477 int n;
3478 {
3479 switch(n) {
3480 case 1:
3481 *buf++=val;
3482 break;
3483 case 2:
3484 *buf++=(val>>8);
3485 *buf++=val;
3486 break;
3487 case 4:
3488 *buf++=(val>>24);
3489 *buf++=(val>>16);
3490 *buf++=(val>>8);
3491 *buf++=val;
3492 break;
3493 default:
3494 as_fatal("failed sanity check.");
3495 }
3496 }
3497
3498 void
3499 md_apply_fix(fixP, val)
3500 fixS *fixP;
3501 long val;
3502 {
3503 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3504
3505 switch(fixP->fx_size) {
3506 case 1:
3507 *buf++=val;
3508 break;
3509 case 2:
3510 *buf++=(val>>8);
3511 *buf++=val;
3512 break;
3513 case 4:
3514 *buf++=(val>>24);
3515 *buf++=(val>>16);
3516 *buf++=(val>>8);
3517 *buf++=val;
3518 break;
3519 default:
3520 BAD_CASE (fixP->fx_size);
3521 }
3522 }
3523
3524
3525 /* *fragP has been relaxed to its final size, and now needs to have
3526 the bytes inside it modified to conform to the new size There is UGLY
3527 MAGIC here. ..
3528 */
3529 void
3530 md_convert_frag(headers, fragP)
3531 object_headers *headers;
3532 register fragS *fragP;
3533 {
3534 long disp;
3535 long ext = 0;
3536
3537 /* Address in object code of the displacement. */
3538 register int object_address = fragP -> fr_fix + fragP -> fr_address;
3539
3540 #ifdef IBM_COMPILER_SUX
3541 /* This is wrong but it convinces the native rs6000 compiler to
3542 generate the code we want. */
3543 register char *buffer_address = fragP -> fr_literal;
3544 buffer_address += fragP -> fr_fix;
3545 #else /* IBM_COMPILER_SUX */
3546 /* Address in gas core of the place to store the displacement. */
3547 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3548 #endif /* IBM_COMPILER_SUX */
3549
3550 /* No longer true: know(fragP->fr_symbol); */
3551
3552 /* The displacement of the address, from current location. */
3553 disp = fragP->fr_symbol ? S_GET_VALUE(fragP->fr_symbol) : 0;
3554 disp = (disp + fragP->fr_offset) - object_address;
3555
3556 switch(fragP->fr_subtype) {
3557 case TAB(BCC68000,BYTE):
3558 case TAB(ABRANCH,BYTE):
3559 know(issbyte(disp));
3560 if(disp==0)
3561 as_bad("short branch with zero offset: use :w");
3562 fragP->fr_opcode[1]=disp;
3563 ext=0;
3564 break;
3565 case TAB(DBCC,SHORT):
3566 know(issword(disp));
3567 ext=2;
3568 break;
3569 case TAB(BCC68000,SHORT):
3570 case TAB(ABRANCH,SHORT):
3571 know(issword(disp));
3572 fragP->fr_opcode[1]=0x00;
3573 ext=2;
3574 break;
3575 case TAB(ABRANCH,LONG):
3576 if (cpu_of_arch(current_architecture) < m68020) {
3577 if (fragP->fr_opcode[0]==0x61) {
3578 fragP->fr_opcode[0]= 0x4E;
3579 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3580 subseg_change(SEG_TEXT, 0);
3581
3582 fix_new(fragP,
3583 fragP->fr_fix,
3584 4,
3585 fragP->fr_symbol,
3586 0,
3587 fragP->fr_offset,
3588 0,
3589 NO_RELOC);
3590
3591 fragP->fr_fix+=4;
3592 ext=0;
3593 } else if (fragP->fr_opcode[0]==0x60) {
3594 fragP->fr_opcode[0]= 0x4E;
3595 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3596 subseg_change(SEG_TEXT, 0);
3597 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset,0,
3598 NO_RELOC);
3599 fragP->fr_fix+=4;
3600 ext=0;
3601 } else {
3602 as_bad("Long branch offset not supported.");
3603 }
3604 } else {
3605 fragP->fr_opcode[1]=0xff;
3606 ext=4;
3607 }
3608 break;
3609 case TAB(BCC68000,LONG):
3610 /* only Bcc 68000 instructions can come here */
3611 /* change bcc into b!cc/jmp absl long */
3612 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3613 fragP->fr_opcode[1] = 0x6; /* branch offset = 6 */
3614
3615 /* JF: these used to be fr_opcode[2,3], but they may be in a
3616 different frag, in which case refering to them is a no-no.
3617 Only fr_opcode[0,1] are guaranteed to work. */
3618 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3619 *buffer_address++ = 0xf9;
3620 fragP->fr_fix += 2; /* account for jmp instruction */
3621 subseg_change(SEG_TEXT,0);
3622 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3623 fragP->fr_offset,0,
3624 NO_RELOC);
3625 fragP->fr_fix += 4;
3626 ext=0;
3627 break;
3628 case TAB(DBCC,LONG):
3629 /* only DBcc 68000 instructions can come here */
3630 /* change dbcc into dbcc/jmp absl long */
3631 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3632 *buffer_address++ = 0x00; /* branch offset = 4 */
3633 *buffer_address++ = 0x04;
3634 *buffer_address++ = 0x60; /* put in bra pc+6 */
3635 *buffer_address++ = 0x06;
3636 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3637 *buffer_address++ = 0xf9;
3638
3639 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3640 subseg_change(SEG_TEXT,0);
3641 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3642 fragP->fr_offset,0,
3643 NO_RELOC);
3644 fragP->fr_fix += 4;
3645 ext=0;
3646 break;
3647 case TAB(FBRANCH,SHORT):
3648 know((fragP->fr_opcode[1]&0x40)==0);
3649 ext=2;
3650 break;
3651 case TAB(FBRANCH,LONG):
3652 fragP->fr_opcode[1]|=0x40; /* Turn on LONG bit */
3653 ext=4;
3654 break;
3655 case TAB(PCREL,SHORT):
3656 ext=2;
3657 break;
3658 case TAB(PCREL,LONG):
3659 /* The thing to do here is force it to ABSOLUTE LONG, since
3660 PCREL is really trying to shorten an ABSOLUTE address anyway */
3661 /* JF FOO This code has not been tested */
3662 subseg_change(SEG_TEXT,0);
3663 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3664 if((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3665 as_bad("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
3666 fragP->fr_opcode[0],fragP->fr_address);
3667 fragP->fr_opcode[1]&= ~0x3F;
3668 fragP->fr_opcode[1]|=0x39; /* Mode 7.1 */
3669 fragP->fr_fix+=4;
3670 /* md_number_to_chars(buffer_address,
3671 (long)(fragP->fr_symbol->sy_value + fragP->fr_offset),
3672 4); */
3673 ext=0;
3674 break;
3675 case TAB(PCLEA,SHORT):
3676 subseg_change(SEG_TEXT,0);
3677 fix_new(fragP,(int)(fragP->fr_fix),2,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset,1,
3678 NO_RELOC);
3679 fragP->fr_opcode[1] &= ~0x3F;
3680 fragP->fr_opcode[1] |= 0x3A;
3681 ext=2;
3682 break;
3683 case TAB(PCLEA,LONG):
3684 subseg_change(SEG_TEXT,0);
3685 fix_new(fragP,(int)(fragP->fr_fix)+2,4,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset+2,1,
3686 NO_RELOC);
3687 *buffer_address++ = 0x01;
3688 *buffer_address++ = 0x70;
3689 fragP->fr_fix+=2;
3690 /* buffer_address+=2; */
3691 ext=4;
3692 break;
3693
3694 } /* switch on subtype */
3695
3696 if (ext) {
3697 md_number_to_chars(buffer_address, (long) disp, (int) ext);
3698 fragP->fr_fix += ext;
3699 /* H_SET_TEXT_SIZE(headers, H_GET_TEXT_SIZE(headers) + ext); */
3700 } /* if extending */
3701
3702 return;
3703 } /* md_convert_frag() */
3704
3705 /* Force truly undefined symbols to their maximum size, and generally set up
3706 the frag list to be relaxed
3707 */
3708 int md_estimate_size_before_relax(fragP, segment)
3709 register fragS *fragP;
3710 segT segment;
3711 {
3712 int old_fix;
3713 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3714
3715 old_fix = fragP->fr_fix;
3716
3717 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3718 switch (fragP->fr_subtype) {
3719
3720 case TAB(ABRANCH,SZ_UNDEF): {
3721 if((fragP->fr_symbol != NULL) /* Not absolute */
3722 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3723 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),BYTE);
3724 break;
3725 } else if((fragP->fr_symbol == 0) || (cpu_of_arch(current_architecture) < m68020)) {
3726 /* On 68000, or for absolute value, switch to abs long */
3727 /* FIXME, we should check abs val, pick short or long */
3728 if(fragP->fr_opcode[0]==0x61) {
3729 fragP->fr_opcode[0]= 0x4E;
3730 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3731 subseg_change(SEG_TEXT, 0);
3732 fix_new(fragP, fragP->fr_fix, 4,
3733 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3734 fragP->fr_fix+=4;
3735 frag_wane(fragP);
3736 } else if(fragP->fr_opcode[0]==0x60) {
3737 fragP->fr_opcode[0]= 0x4E;
3738 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3739 subseg_change(SEG_TEXT, 0);
3740 fix_new(fragP, fragP->fr_fix, 4,
3741 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3742 fragP->fr_fix+=4;
3743 frag_wane(fragP);
3744 } else {
3745 as_warn("Long branch offset to extern symbol not supported.");
3746 }
3747 } else { /* Symbol is still undefined. Make it simple */
3748 fix_new(fragP, (int)(fragP->fr_fix), 4, fragP->fr_symbol,
3749 (symbolS *)0, fragP->fr_offset+4, 1, NO_RELOC);
3750 fragP->fr_fix+=4;
3751 fragP->fr_opcode[1]=0xff;
3752 frag_wane(fragP);
3753 break;
3754 }
3755
3756 break;
3757 } /* case TAB(ABRANCH,SZ_UNDEF) */
3758
3759 case TAB(FBRANCH,SZ_UNDEF): {
3760 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3761 fragP->fr_subtype = TAB(FBRANCH,SHORT);
3762 fragP->fr_var += 2;
3763 } else {
3764 fragP->fr_subtype = TAB(FBRANCH,LONG);
3765 fragP->fr_var += 4;
3766 }
3767 break;
3768 } /* TAB(FBRANCH,SZ_UNDEF) */
3769
3770 case TAB(PCREL,SZ_UNDEF): {
3771 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3772 fragP->fr_subtype = TAB(PCREL,SHORT);
3773 fragP->fr_var += 2;
3774 } else {
3775 fragP->fr_subtype = TAB(PCREL,LONG);
3776 fragP->fr_var += 4;
3777 }
3778 break;
3779 } /* TAB(PCREL,SZ_UNDEF) */
3780
3781 case TAB(BCC68000,SZ_UNDEF): {
3782 if((fragP->fr_symbol != NULL)
3783 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3784 fragP->fr_subtype=TAB(BCC68000,BYTE);
3785 break;
3786 }
3787 /* only Bcc 68000 instructions can come here */
3788 /* change bcc into b!cc/jmp absl long */
3789 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3790 if(flagseen['l']) {
3791 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3792 /* JF: these were fr_opcode[2,3] */
3793 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3794 buffer_address[1] = 0xf8;
3795 fragP->fr_fix += 2; /* account for jmp instruction */
3796 subseg_change(SEG_TEXT,0);
3797 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
3798 fragP->fr_offset, 0, NO_RELOC);
3799 fragP->fr_fix += 2;
3800 } else {
3801 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3802 /* JF: these were fr_opcode[2,3] */
3803 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3804 buffer_address[1] = 0xf9;
3805 fragP->fr_fix += 2; /* account for jmp instruction */
3806 subseg_change(SEG_TEXT,0);
3807 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3808 fragP->fr_offset, 0, NO_RELOC);
3809 fragP->fr_fix += 4;
3810 }
3811 frag_wane(fragP);
3812 break;
3813 } /* case TAB(BCC68000,SZ_UNDEF) */
3814
3815 case TAB(DBCC,SZ_UNDEF): {
3816 if (fragP->fr_symbol != NULL && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3817 fragP->fr_subtype=TAB(DBCC,SHORT);
3818 fragP->fr_var+=2;
3819 break;
3820 }
3821 /* only DBcc 68000 instructions can come here */
3822 /* change dbcc into dbcc/jmp absl long */
3823 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3824 buffer_address[0] = 0x00; /* branch offset = 4 */
3825 buffer_address[1] = 0x04;
3826 buffer_address[2] = 0x60; /* put in bra pc + ... */
3827
3828 if(flagseen['l']) {
3829 /* JF: these were fr_opcode[5-7] */
3830 buffer_address[3] = 0x04; /* plus 4 */
3831 buffer_address[4] = 0x4e;/* Put in Jump Word */
3832 buffer_address[5] = 0xf8;
3833 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3834 subseg_change(SEG_TEXT,0);
3835 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
3836
3837
3838 fragP->fr_offset, 0, NO_RELOC);
3839 fragP->fr_fix += 2;
3840 } else {
3841 /* JF: these were fr_opcode[5-7] */
3842 buffer_address[3] = 0x06; /* Plus 6 */
3843 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3844 buffer_address[5] = 0xf9;
3845 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3846 subseg_change(SEG_TEXT,0);
3847 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3848 fragP->fr_offset, 0, NO_RELOC);
3849 fragP->fr_fix += 4;
3850 }
3851
3852 frag_wane(fragP);
3853 break;
3854 } /* case TAB(DBCC,SZ_UNDEF) */
3855
3856 case TAB(PCLEA,SZ_UNDEF): {
3857 if ((S_GET_SEGMENT(fragP->fr_symbol))==segment || flagseen['l']) {
3858 fragP->fr_subtype=TAB(PCLEA,SHORT);
3859 fragP->fr_var+=2;
3860 } else {
3861 fragP->fr_subtype=TAB(PCLEA,LONG);
3862 fragP->fr_var+=6;
3863 }
3864 break;
3865 } /* TAB(PCLEA,SZ_UNDEF) */
3866
3867 default:
3868 break;
3869
3870 } /* switch on subtype looking for SZ_UNDEF's. */
3871
3872 /* now that SZ_UNDEF are taken care of, check others */
3873 switch (fragP->fr_subtype) {
3874 case TAB(BCC68000,BYTE):
3875 case TAB(ABRANCH,BYTE):
3876 /* We can't do a short jump to the next instruction,
3877 so we force word mode. */
3878 if (fragP->fr_symbol && S_GET_VALUE(fragP->fr_symbol)==0 &&
3879 fragP->fr_symbol->sy_frag==fragP->fr_next) {
3880 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),SHORT);
3881 fragP->fr_var+=2;
3882 }
3883 break;
3884 default:
3885 break;
3886 }
3887 return fragP->fr_var + fragP->fr_fix - old_fix;
3888 }
3889
3890 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3891 /* the bit-field entries in the relocation_info struct plays hell
3892 with the byte-order problems of cross-assembly. So as a hack,
3893 I added this mach. dependent ri twiddler. Ugly, but it gets
3894 you there. -KWK */
3895 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3896 are symbolnum, most sig. byte first. Last byte is broken up with
3897 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3898 nibble as nuthin. (on Sun 3 at least) */
3899 /* Translate the internal relocation information into target-specific
3900 format. */
3901 #ifdef comment
3902 void
3903 md_ri_to_chars(the_bytes, ri)
3904 char *the_bytes;
3905 struct reloc_info_generic *ri;
3906 {
3907 /* this is easy */
3908 md_number_to_chars(the_bytes, ri->r_address, 4);
3909 /* now the fun stuff */
3910 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3911 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3912 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3913 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3914 ((ri->r_extern << 4) & 0x10));
3915 }
3916 #endif /* comment */
3917
3918 void tc_aout_fix_to_chars(where, fixP, segment_address_in_file)
3919 char *where;
3920 fixS *fixP;
3921 relax_addressT segment_address_in_file;
3922 {
3923 /*
3924 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3925 * Out: GNU LD relocation length code: 0, 1, or 2.
3926 */
3927
3928 static unsigned char nbytes_r_length [] = { 42, 0, 1, 42, 2 };
3929 long r_symbolnum;
3930
3931 know(fixP->fx_addsy != NULL);
3932
3933 md_number_to_chars(where,
3934 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3935 4);
3936
3937 r_symbolnum = (S_IS_DEFINED(fixP->fx_addsy)
3938 ? S_GET_TYPE(fixP->fx_addsy)
3939 : fixP->fx_addsy->sy_number);
3940
3941 where[4] = (r_symbolnum >> 16) & 0x0ff;
3942 where[5] = (r_symbolnum >> 8) & 0x0ff;
3943 where[6] = r_symbolnum & 0x0ff;
3944 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3945 (((!S_IS_DEFINED(fixP->fx_addsy)) << 4) & 0x10));
3946
3947 return;
3948 } /* tc_aout_fix_to_chars() */
3949
3950 #endif /* OBJ_AOUT or OBJ_BOUT */
3951
3952 #ifndef WORKING_DOT_WORD
3953 const int md_short_jump_size = 4;
3954 const int md_long_jump_size = 6;
3955
3956 void
3957 md_create_short_jump(ptr,from_addr,to_addr,frag,to_symbol)
3958 char *ptr;
3959 long from_addr,
3960 to_addr;
3961 fragS *frag;
3962 symbolS *to_symbol;
3963 {
3964 long offset;
3965
3966 offset = to_addr - (from_addr+2);
3967
3968 md_number_to_chars(ptr ,(long)0x6000,2);
3969 md_number_to_chars(ptr+2,(long)offset,2);
3970 }
3971
3972 void
3973 md_create_long_jump(ptr,from_addr,to_addr,frag,to_symbol)
3974 char *ptr;
3975 long from_addr,
3976 to_addr;
3977 fragS *frag;
3978 symbolS *to_symbol;
3979 {
3980 long offset;
3981
3982 if (cpu_of_arch(current_architecture) < m68020) {
3983 offset=to_addr-S_GET_VALUE(to_symbol);
3984 md_number_to_chars(ptr ,(long)0x4EF9,2);
3985 md_number_to_chars(ptr+2,(long)offset,4);
3986 fix_new(frag,(ptr+2)-frag->fr_literal,4,to_symbol,(symbolS *)0,(long)0,0,
3987 NO_RELOC);
3988 } else {
3989 offset=to_addr - (from_addr+2);
3990 md_number_to_chars(ptr ,(long)0x60ff,2);
3991 md_number_to_chars(ptr+2,(long)offset,4);
3992 }
3993 }
3994
3995 #endif
3996 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
3997
3998 0: Everything is OK
3999 10: Absolute 1:8 only
4000 20: Absolute 0:7 only
4001 30: absolute 0:15 only
4002 40: Absolute 0:31 only
4003 50: absolute 0:127 only
4004 55: absolute -64:63 only
4005 60: absolute -128:127 only
4006 70: absolute 0:4095 only
4007 80: No bignums
4008
4009 */
4010
4011 static int get_num(exp,ok)
4012 struct m68k_exp *exp;
4013 int ok;
4014 {
4015 #ifdef TEST2
4016 long l = 0;
4017
4018 if(!exp->e_beg)
4019 return 0;
4020 if(*exp->e_beg=='0') {
4021 if(exp->e_beg[1]=='x')
4022 sscanf(exp->e_beg+2,"%x",&l);
4023 else
4024 sscanf(exp->e_beg+1,"%O",&l);
4025 return l;
4026 }
4027 return atol(exp->e_beg);
4028 #else
4029 char *save_in;
4030 char c_save;
4031
4032 if(!exp) {
4033 /* Can't do anything */
4034 return 0;
4035 }
4036 if(!exp->e_beg || !exp->e_end) {
4037 seg(exp)=SEG_ABSOLUTE;
4038 adds(exp)=0;
4039 subs(exp)=0;
4040 offs(exp)= (ok==10) ? 1 : 0;
4041 as_warn("Null expression defaults to %ld",offs(exp));
4042 return 0;
4043 }
4044
4045 exp->e_siz=0;
4046 if(/* ok!=80 && */ (exp->e_end[-1]==':' || exp->e_end[-1]=='.')
4047 && (exp->e_end-exp->e_beg)>=2) {
4048 switch(exp->e_end[0]) {
4049 case 's':
4050 case 'S':
4051 case 'b':
4052 case 'B':
4053 exp->e_siz=1;
4054 exp->e_end-=2;
4055 break;
4056 case 'w':
4057 case 'W':
4058 exp->e_siz=2;
4059 exp->e_end-=2;
4060 break;
4061 case 'l':
4062 case 'L':
4063 exp->e_siz=3;
4064 exp->e_end-=2;
4065 break;
4066 default:
4067 if (exp->e_end[-1] == ':')
4068 as_bad("Unknown size for expression \"%c\"",exp->e_end[0]);
4069 break;
4070 }
4071 }
4072 c_save=exp->e_end[1];
4073 exp->e_end[1]='\0';
4074 save_in=input_line_pointer;
4075 input_line_pointer=exp->e_beg;
4076 switch(expression(&(exp->e_exp))) {
4077 case SEG_PASS1:
4078 seg(exp)=SEG_ABSOLUTE;
4079 adds(exp)=0;
4080 subs(exp)=0;
4081 offs(exp)= (ok==10) ? 1 : 0;
4082 as_warn("Unknown expression: '%s' defaulting to %d",exp->e_beg,offs(exp));
4083 break;
4084
4085 case SEG_ABSENT:
4086 /* Do the same thing the VAX asm does */
4087 seg(exp)=SEG_ABSOLUTE;
4088 adds(exp)=0;
4089 subs(exp)=0;
4090 offs(exp)=0;
4091 if(ok==10) {
4092 as_warn("expression out of range: defaulting to 1");
4093 offs(exp)=1;
4094 }
4095 break;
4096 case SEG_ABSOLUTE:
4097 switch(ok) {
4098 case 10:
4099 if(offs(exp)<1 || offs(exp)>8) {
4100 as_warn("expression out of range: defaulting to 1");
4101 offs(exp)=1;
4102 }
4103 break;
4104 case 20:
4105 if(offs(exp)<0 || offs(exp)>7)
4106 goto outrange;
4107 break;
4108 case 30:
4109 if(offs(exp)<0 || offs(exp)>15)
4110 goto outrange;
4111 break;
4112 case 40:
4113 if(offs(exp)<0 || offs(exp)>32)
4114 goto outrange;
4115 break;
4116 case 50:
4117 if(offs(exp)<0 || offs(exp)>127)
4118 goto outrange;
4119 break;
4120 case 55:
4121 if(offs(exp)<-64 || offs(exp)>63)
4122 goto outrange;
4123 break;
4124 case 60:
4125 if(offs(exp)<-128 || offs(exp)>127)
4126 goto outrange;
4127 break;
4128 case 70:
4129 if(offs(exp)<0 || offs(exp)>4095) {
4130 outrange:
4131 as_warn("expression out of range: defaulting to 0");
4132 offs(exp)=0;
4133 }
4134 break;
4135 default:
4136 break;
4137 }
4138 break;
4139 case SEG_TEXT:
4140 case SEG_DATA:
4141 case SEG_BSS:
4142 case SEG_UNKNOWN:
4143 case SEG_DIFFERENCE:
4144 if(ok>=10 && ok<=70) {
4145 seg(exp)=SEG_ABSOLUTE;
4146 adds(exp)=0;
4147 subs(exp)=0;
4148 offs(exp)= (ok==10) ? 1 : 0;
4149 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
4150 }
4151 break;
4152 case SEG_BIG:
4153 if (offs (exp) < 0 /* flonum */
4154 && (ok == 80 /* no bignums */
4155 || (ok > 10 /* small-int ranges including 0 ok */
4156 /* If we have a flonum zero, a zero integer should
4157 do as well (e.g., in moveq). */
4158 && generic_floating_point_number.exponent == 0
4159 && generic_floating_point_number.low[0] == 0)))
4160 {
4161 /* HACK! Turn it into a long */
4162 LITTLENUM_TYPE words[6];
4163
4164 gen_to_words(words,2,8L);/* These numbers are magic! */
4165 seg(exp)=SEG_ABSOLUTE;
4166 adds(exp)=0;
4167 subs(exp)=0;
4168 offs(exp)=words[1]|(words[0]<<16);
4169 }
4170 else if(ok!=0) {
4171 seg(exp)=SEG_ABSOLUTE;
4172 adds(exp)=0;
4173 subs(exp)=0;
4174 offs(exp)= (ok==10) ? 1 : 0;
4175 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
4176 }
4177 break;
4178 default:
4179 as_fatal("failed sanity check.");
4180 }
4181 if(input_line_pointer!=exp->e_end+1)
4182 as_bad("Ignoring junk after expression");
4183 exp->e_end[1]=c_save;
4184 input_line_pointer=save_in;
4185 if(exp->e_siz) {
4186 switch(exp->e_siz) {
4187 case 1:
4188 if(!isbyte(offs(exp)))
4189 as_warn("expression doesn't fit in BYTE");
4190 break;
4191 case 2:
4192 if(!isword(offs(exp)))
4193 as_warn("expression doesn't fit in WORD");
4194 break;
4195 }
4196 }
4197 return offs(exp);
4198 #endif
4199 } /* get_num() */
4200
4201 /* These are the back-ends for the various machine dependent pseudo-ops. */
4202 void demand_empty_rest_of_line(); /* Hate those extra verbose names */
4203
4204 static void s_data1() {
4205 subseg_new(SEG_DATA,1);
4206 demand_empty_rest_of_line();
4207 } /* s_data1() */
4208
4209 static void s_data2() {
4210 subseg_new(SEG_DATA,2);
4211 demand_empty_rest_of_line();
4212 } /* s_data2() */
4213
4214 static void s_bss()
4215 {
4216 /* We don't support putting frags in the BSS segment, we fake it
4217 by marking in_bss, then looking at s_skip for clues */
4218
4219 subseg_new(SEG_BSS, 0);
4220 demand_empty_rest_of_line();
4221 } /* s_bss() */
4222
4223 static void s_even() {
4224 register int temp;
4225 register long temp_fill;
4226
4227 temp = 1; /* JF should be 2? */
4228 temp_fill = get_absolute_expression ();
4229 if ( ! need_pass_2 ) /* Never make frag if expect extra pass. */
4230 frag_align (temp, (int)temp_fill);
4231 demand_empty_rest_of_line();
4232 } /* s_even() */
4233
4234 static void s_proc() {
4235 demand_empty_rest_of_line();
4236 } /* s_proc() */
4237
4238 /* s_space is defined in read.c .skip is simply an alias to it. */
4239
4240 /*
4241 * md_parse_option
4242 * Invocation line includes a switch not recognized by the base assembler.
4243 * See if it's a processor-specific option. These are:
4244 *
4245 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4246 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4247 * Select the architecture. Instructions or features not
4248 * supported by the selected architecture cause fatal
4249 * errors. More than one may be specified. The default is
4250 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4251 * for -m68000, and -m68882 is a synonym for -m68881.
4252 * -[A]m[c]no-68851, -[A]m[c]no-68881
4253 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4254 * so don't use or document it, but that's the way the parsing
4255 * works).
4256 *
4257 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4258 * (e.g. m68020) also requests that float instructions be included. This
4259 * is the default setup, mostly to avoid hassling users. A better
4260 * rearrangement of this structure would be to add an option to DENY
4261 * floating point opcodes, for people who want to really know there's none
4262 * of that funny floaty stuff going on. FIXME-later.
4263 */
4264 #ifndef MAYBE_FLOAT_TOO
4265 #define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */
4266 #endif
4267
4268 int md_parse_option(argP,cntP,vecP)
4269 char **argP;
4270 int *cntP;
4271 char ***vecP;
4272 {
4273 switch(**argP) {
4274 case 'l': /* -l means keep external to 2 bit offset
4275 rather than 16 bit one */
4276 break;
4277
4278 case 'S': /* -S means that jbsr's always turn into jsr's. */
4279 break;
4280
4281 case 'A':
4282 (*argP)++;
4283 /* intentional fall-through */
4284 case 'm':
4285 (*argP)++;
4286
4287 if (**argP=='c') {
4288 (*argP)++;
4289 } /* allow an optional "c" */
4290
4291 if (!strcmp(*argP, "68000")
4292 || !strcmp(*argP, "68008")) {
4293 current_architecture |= m68000;
4294 } else if (!strcmp(*argP, "68010")) {
4295 #ifdef TE_SUN
4296 omagic= 1<<16|OMAGIC;
4297 #endif
4298 current_architecture |= m68010;
4299
4300 } else if (!strcmp(*argP, "68020")) {
4301 current_architecture |= m68020 | MAYBE_FLOAT_TOO;
4302
4303 } else if (!strcmp(*argP, "68030")) {
4304 current_architecture |= m68030 | MAYBE_FLOAT_TOO;
4305
4306 } else if (!strcmp(*argP, "68040")) {
4307 current_architecture |= m68040 | MAYBE_FLOAT_TOO;
4308
4309 #ifndef NO_68881
4310 } else if (!strcmp(*argP, "68881")) {
4311 current_architecture |= m68881;
4312
4313 } else if (!strcmp(*argP, "68882")) {
4314 current_architecture |= m68882;
4315 #endif /* NO_68881 */
4316 /* Even if we aren't configured to support the processor,
4317 it should still be possible to assert that the user
4318 doesn't have it... */
4319 } else if (!strcmp (*argP, "no-68881")
4320 || !strcmp (*argP, "no-68882")) {
4321 no_68881 = 1;
4322 #ifndef NO_68851
4323 } else if (!strcmp(*argP,"68851")) {
4324 current_architecture |= m68851;
4325 #endif /* NO_68851 */
4326 } else if (!strcmp (*argP, "no-68851")) {
4327 no_68851 = 1;
4328 } else if (!strcmp (*argP, "pu32")) { /* "-mcpu32" */
4329 current_architecture |= cpu32;
4330 } else {
4331 as_warn("Unknown architecture, \"%s\". option ignored", *argP);
4332 } /* switch on architecture */
4333
4334 while(**argP) (*argP)++;
4335
4336 break;
4337
4338 case 'p':
4339 if (!strcmp(*argP,"pic")) {
4340 (*argP) += 3;
4341 break; /* -pic, Position Independent Code */
4342 } else {
4343 return(0);
4344 } /* pic or not */
4345
4346 default:
4347 return 0;
4348 }
4349 return 1;
4350 }
4351
4352
4353 #ifdef TEST2
4354
4355 /* TEST2: Test md_assemble() */
4356 /* Warning, this routine probably doesn't work anymore */
4357
4358 main()
4359 {
4360 struct m68k_it the_ins;
4361 char buf[120];
4362 char *cp;
4363 int n;
4364
4365 m68k_ip_begin();
4366 for(;;) {
4367 if(!gets(buf) || !*buf)
4368 break;
4369 if(buf[0]=='|' || buf[1]=='.')
4370 continue;
4371 for(cp=buf;*cp;cp++)
4372 if(*cp=='\t')
4373 *cp=' ';
4374 if(is_label(buf))
4375 continue;
4376 memset(&the_ins, '\0', sizeof(the_ins));
4377 m68k_ip(&the_ins,buf);
4378 if(the_ins.error) {
4379 printf("Error %s in %s\n",the_ins.error,buf);
4380 } else {
4381 printf("Opcode(%d.%s): ",the_ins.numo,the_ins.args);
4382 for(n=0;n<the_ins.numo;n++)
4383 printf(" 0x%x",the_ins.opcode[n]&0xffff);
4384 printf(" ");
4385 print_the_insn(&the_ins.opcode[0],stdout);
4386 (void)putchar('\n');
4387 }
4388 for(n=0;n<strlen(the_ins.args)/2;n++) {
4389 if(the_ins.operands[n].error) {
4390 printf("op%d Error %s in %s\n",n,the_ins.operands[n].error,buf);
4391 continue;
4392 }
4393 printf("mode %d, reg %d, ",the_ins.operands[n].mode,the_ins.operands[n].reg);
4394 if(the_ins.operands[n].b_const)
4395 printf("Constant: '%.*s', ",1+the_ins.operands[n].e_const-the_ins.operands[n].b_const,the_ins.operands[n].b_const);
4396 printf("ireg %d, isiz %d, imul %d, ",the_ins.operands[n].ireg,the_ins.operands[n].isiz,the_ins.operands[n].imul);
4397 if(the_ins.operands[n].b_iadd)
4398 printf("Iadd: '%.*s',",1+the_ins.operands[n].e_iadd-the_ins.operands[n].b_iadd,the_ins.operands[n].b_iadd);
4399 (void)putchar('\n');
4400 }
4401 }
4402 m68k_ip_end();
4403 return 0;
4404 }
4405
4406 is_label(str)
4407 char *str;
4408 {
4409 while(*str==' ')
4410 str++;
4411 while(*str && *str!=' ')
4412 str++;
4413 if(str[-1]==':' || str[1]=='=')
4414 return 1;
4415 return 0;
4416 }
4417
4418 #endif
4419
4420 /* Possible states for relaxation:
4421
4422 0 0 branch offset byte (bra, etc)
4423 0 1 word
4424 0 2 long
4425
4426 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4427 1 1 word
4428 1 2 long
4429
4430 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4431 2 1 word-long
4432 2 2 long-word
4433 2 3 long-long
4434
4435 */
4436
4437
4438
4439 #ifdef DONTDEF
4440 abort()
4441 {
4442 printf("ABORT!\n");
4443 exit(12);
4444 }
4445
4446 print_frags()
4447 {
4448 fragS *fragP;
4449 extern fragS *text_frag_root;
4450
4451 for(fragP=text_frag_root;fragP;fragP=fragP->fr_next) {
4452 printf("addr %lu next 0x%x fix %ld var %ld symbol 0x%x offset %ld\n",
4453 fragP->fr_address,fragP->fr_next,fragP->fr_fix,fragP->fr_var,fragP->fr_symbol,fragP->fr_offset);
4454 printf("opcode 0x%x type %d subtype %d\n\n",fragP->fr_opcode,fragP->fr_type,fragP->fr_subtype);
4455 }
4456 fflush(stdout);
4457 return 0;
4458 }
4459 #endif
4460
4461 #ifdef DONTDEF
4462 /*VARARGS1*/
4463 panic(format,args)
4464 char *format;
4465 {
4466 fputs("Internal error:",stderr);
4467 _doprnt(format,&args,stderr);
4468 (void)putc('\n',stderr);
4469 as_where();
4470 abort();
4471 }
4472 #endif
4473
4474 /* We have no need to default values of symbols. */
4475
4476 /* ARGSUSED */
4477 symbolS *
4478 md_undefined_symbol (name)
4479 char *name;
4480 {
4481 return 0;
4482 }
4483
4484 /* Parse an operand that is machine-specific.
4485 We just return without modifying the expression if we have nothing
4486 to do. */
4487
4488 /* ARGSUSED */
4489 void
4490 md_operand (expressionP)
4491 expressionS *expressionP;
4492 {
4493 }
4494
4495 /* Round up a section size to the appropriate boundary. */
4496 long
4497 md_section_align (segment, size)
4498 segT segment;
4499 long size;
4500 {
4501 return size; /* Byte alignment is fine */
4502 }
4503
4504 /* Exactly what point is a PC-relative offset relative TO?
4505 On the 68k, they're relative to the address of the offset, plus
4506 its size. (??? Is this right? FIXME-SOON!) */
4507 long
4508 md_pcrel_from (fixP)
4509 fixS *fixP;
4510 {
4511 return(fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address);
4512 }
4513
4514 void
4515 tc_coff_symbol_emit_hook ()
4516 {
4517 }
4518
4519 int
4520 tc_coff_sizemachdep(frag)
4521 fragS *frag;
4522 {
4523 switch (frag->fr_subtype & 0x3)
4524 {
4525 case BYTE: return 1;
4526 case SHORT: return 2;
4527 case LONG: return 4;
4528 default: abort();
4529 }
4530
4531 }
4532 /*
4533 * Local Variables:
4534 * comment-column: 0
4535 * fill-column: 131
4536 * End:
4537 */
4538
4539 /* end of tc-m68k.c */
4540
GDB Binutils - Deliverables
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