1 /* tc-mep.c -- Assembler for the Toshiba Media Processor.
2 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2007
3 Free Software Foundation. Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "dwarf2dbg.h"
27 #include "opcodes/mep-desc.h"
28 #include "opcodes/mep-opc.h"
30 #include "elf/common.h"
35 /* Structure to hold all of the different components describing
36 an individual instruction. */
39 const CGEN_INSN
* insn
;
40 const CGEN_INSN
* orig_insn
;
43 CGEN_INSN_INT buffer
[1];
44 #define INSN_VALUE(buf) (*(buf))
46 unsigned char buffer
[CGEN_MAX_INSN_SIZE
];
47 #define INSN_VALUE(buf) (buf)
52 fixS
* fixups
[GAS_CGEN_MAX_FIXUPS
];
53 int indices
[MAX_OPERAND_INSTANCES
];
56 static int mode
= CORE
; /* Start in core mode. */
57 static int pluspresent
= 0;
58 static int allow_disabled_registers
= 0;
59 static int library_flag
= 0;
61 /* We're going to need to store all of the instructions along with
62 their fixups so that we can parallelization grouping rules. */
64 static mep_insn saved_insns
[MAX_SAVED_FIXUP_CHAINS
];
65 static int num_insns_saved
= 0;
67 const char comment_chars
[] = "#";
68 const char line_comment_chars
[] = ";#";
69 const char line_separator_chars
[] = ";";
70 const char EXP_CHARS
[] = "eE";
71 const char FLT_CHARS
[] = "dD";
73 static void mep_switch_to_vliw_mode (int);
74 static void mep_switch_to_core_mode (int);
75 static void mep_s_vtext (int);
76 static void mep_noregerr (int);
78 /* The target specific pseudo-ops which we support. */
79 const pseudo_typeS md_pseudo_table
[] =
82 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
83 { "loc", dwarf2_directive_loc
, 0 },
84 { "vliw", mep_switch_to_vliw_mode
, 0 },
85 { "core", mep_switch_to_core_mode
, 0 },
86 { "vtext", mep_s_vtext
, 0 },
87 { "noregerr", mep_noregerr
, 0 },
91 /* Relocations against symbols are done in two
92 parts, with a HI relocation and a LO relocation. Each relocation
93 has only 16 bits of space to store an addend. This means that in
94 order for the linker to handle carries correctly, it must be able
95 to locate both the HI and the LO relocation. This means that the
96 relocations must appear in order in the relocation table.
98 In order to implement this, we keep track of each unmatched HI
99 relocation. We then sort them so that they immediately precede the
100 corresponding LO relocation. */
104 struct mep_hi_fixup
* next
; /* Next HI fixup. */
105 fixS
* fixp
; /* This fixup. */
106 segT seg
; /* The section this fixup is in. */
109 /* The list of unmatched HI relocs. */
110 static struct mep_hi_fixup
* mep_hi_fixup_list
;
113 #define OPTION_EB (OPTION_MD_BASE + 0)
114 #define OPTION_EL (OPTION_MD_BASE + 1)
115 #define OPTION_CONFIG (OPTION_MD_BASE + 2)
116 #define OPTION_AVERAGE (OPTION_MD_BASE + 3)
117 #define OPTION_NOAVERAGE (OPTION_MD_BASE + 4)
118 #define OPTION_MULT (OPTION_MD_BASE + 5)
119 #define OPTION_NOMULT (OPTION_MD_BASE + 6)
120 #define OPTION_DIV (OPTION_MD_BASE + 7)
121 #define OPTION_NODIV (OPTION_MD_BASE + 8)
122 #define OPTION_BITOPS (OPTION_MD_BASE + 9)
123 #define OPTION_NOBITOPS (OPTION_MD_BASE + 10)
124 #define OPTION_LEADZ (OPTION_MD_BASE + 11)
125 #define OPTION_NOLEADZ (OPTION_MD_BASE + 12)
126 #define OPTION_ABSDIFF (OPTION_MD_BASE + 13)
127 #define OPTION_NOABSDIFF (OPTION_MD_BASE + 14)
128 #define OPTION_MINMAX (OPTION_MD_BASE + 15)
129 #define OPTION_NOMINMAX (OPTION_MD_BASE + 16)
130 #define OPTION_CLIP (OPTION_MD_BASE + 17)
131 #define OPTION_NOCLIP (OPTION_MD_BASE + 18)
132 #define OPTION_SATUR (OPTION_MD_BASE + 19)
133 #define OPTION_NOSATUR (OPTION_MD_BASE + 20)
134 #define OPTION_COP32 (OPTION_MD_BASE + 21)
135 #define OPTION_REPEAT (OPTION_MD_BASE + 25)
136 #define OPTION_NOREPEAT (OPTION_MD_BASE + 26)
137 #define OPTION_DEBUG (OPTION_MD_BASE + 27)
138 #define OPTION_NODEBUG (OPTION_MD_BASE + 28)
139 #define OPTION_UCI (OPTION_MD_BASE + 29)
140 #define OPTION_NOUCI (OPTION_MD_BASE + 30)
141 #define OPTION_DSP (OPTION_MD_BASE + 31)
142 #define OPTION_NODSP (OPTION_MD_BASE + 32)
143 #define OPTION_LIBRARY (OPTION_MD_BASE + 33)
145 struct option md_longopts
[] = {
146 { "EB", no_argument
, NULL
, OPTION_EB
},
147 { "EL", no_argument
, NULL
, OPTION_EL
},
148 { "mconfig", required_argument
, NULL
, OPTION_CONFIG
},
149 { "maverage", no_argument
, NULL
, OPTION_AVERAGE
},
150 { "mno-average", no_argument
, NULL
, OPTION_NOAVERAGE
},
151 { "mmult", no_argument
, NULL
, OPTION_MULT
},
152 { "mno-mult", no_argument
, NULL
, OPTION_NOMULT
},
153 { "mdiv", no_argument
, NULL
, OPTION_DIV
},
154 { "mno-div", no_argument
, NULL
, OPTION_NODIV
},
155 { "mbitops", no_argument
, NULL
, OPTION_BITOPS
},
156 { "mno-bitops", no_argument
, NULL
, OPTION_NOBITOPS
},
157 { "mleadz", no_argument
, NULL
, OPTION_LEADZ
},
158 { "mno-leadz", no_argument
, NULL
, OPTION_NOLEADZ
},
159 { "mabsdiff", no_argument
, NULL
, OPTION_ABSDIFF
},
160 { "mno-absdiff", no_argument
, NULL
, OPTION_NOABSDIFF
},
161 { "mminmax", no_argument
, NULL
, OPTION_MINMAX
},
162 { "mno-minmax", no_argument
, NULL
, OPTION_NOMINMAX
},
163 { "mclip", no_argument
, NULL
, OPTION_CLIP
},
164 { "mno-clip", no_argument
, NULL
, OPTION_NOCLIP
},
165 { "msatur", no_argument
, NULL
, OPTION_SATUR
},
166 { "mno-satur", no_argument
, NULL
, OPTION_NOSATUR
},
167 { "mcop32", no_argument
, NULL
, OPTION_COP32
},
168 { "mdebug", no_argument
, NULL
, OPTION_DEBUG
},
169 { "mno-debug", no_argument
, NULL
, OPTION_NODEBUG
},
170 { "muci", no_argument
, NULL
, OPTION_UCI
},
171 { "mno-uci", no_argument
, NULL
, OPTION_NOUCI
},
172 { "mdsp", no_argument
, NULL
, OPTION_DSP
},
173 { "mno-dsp", no_argument
, NULL
, OPTION_NODSP
},
174 { "mlibrary", no_argument
, NULL
, OPTION_LIBRARY
},
175 { NULL
, 0, NULL
, 0 } };
176 size_t md_longopts_size
= sizeof (md_longopts
);
178 const char * md_shortopts
= "";
179 static int optbits
= 0;
180 static int optbitset
= 0;
183 md_parse_option (int c
, char *arg ATTRIBUTE_UNUSED
)
189 target_big_endian
= 1;
192 target_big_endian
= 0;
196 for (i
=1; mep_config_map
[i
].name
; i
++)
197 if (strcmp (mep_config_map
[i
].name
, arg
) == 0)
204 fprintf (stderr
, "Error: unknown configuration %s\n", arg
);
207 mep_config_index
= idx
;
208 target_big_endian
= mep_config_map
[idx
].big_endian
;
211 optbits
|= 1 << CGEN_INSN_OPTIONAL_AVE_INSN
;
212 optbitset
|= 1 << CGEN_INSN_OPTIONAL_AVE_INSN
;
214 case OPTION_NOAVERAGE
:
215 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_AVE_INSN
);
216 optbitset
|= 1 << CGEN_INSN_OPTIONAL_AVE_INSN
;
219 optbits
|= 1 << CGEN_INSN_OPTIONAL_MUL_INSN
;
220 optbitset
|= 1 << CGEN_INSN_OPTIONAL_MUL_INSN
;
223 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_MUL_INSN
);
224 optbitset
|= 1 << CGEN_INSN_OPTIONAL_MUL_INSN
;
227 optbits
|= 1 << CGEN_INSN_OPTIONAL_DIV_INSN
;
228 optbitset
|= 1 << CGEN_INSN_OPTIONAL_DIV_INSN
;
231 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_DIV_INSN
);
232 optbitset
|= 1 << CGEN_INSN_OPTIONAL_DIV_INSN
;
235 optbits
|= 1 << CGEN_INSN_OPTIONAL_BIT_INSN
;
236 optbitset
|= 1 << CGEN_INSN_OPTIONAL_BIT_INSN
;
238 case OPTION_NOBITOPS
:
239 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_BIT_INSN
);
240 optbitset
|= 1 << CGEN_INSN_OPTIONAL_BIT_INSN
;
243 optbits
|= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN
;
244 optbitset
|= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN
;
247 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_LDZ_INSN
);
248 optbitset
|= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN
;
251 optbits
|= 1 << CGEN_INSN_OPTIONAL_ABS_INSN
;
252 optbitset
|= 1 << CGEN_INSN_OPTIONAL_ABS_INSN
;
254 case OPTION_NOABSDIFF
:
255 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_ABS_INSN
);
256 optbitset
|= 1 << CGEN_INSN_OPTIONAL_ABS_INSN
;
259 optbits
|= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN
;
260 optbitset
|= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN
;
262 case OPTION_NOMINMAX
:
263 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_MINMAX_INSN
);
264 optbitset
|= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN
;
267 optbits
|= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN
;
268 optbitset
|= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN
;
271 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_CLIP_INSN
);
272 optbitset
|= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN
;
275 optbits
|= 1 << CGEN_INSN_OPTIONAL_SAT_INSN
;
276 optbitset
|= 1 << CGEN_INSN_OPTIONAL_SAT_INSN
;
279 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_SAT_INSN
);
280 optbitset
|= 1 << CGEN_INSN_OPTIONAL_SAT_INSN
;
283 optbits
|= 1 << CGEN_INSN_OPTIONAL_CP_INSN
;
284 optbitset
|= 1 << CGEN_INSN_OPTIONAL_CP_INSN
;
287 optbits
|= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN
;
288 optbitset
|= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN
;
291 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_DEBUG_INSN
);
292 optbitset
|= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN
;
295 optbits
|= 1 << CGEN_INSN_OPTIONAL_UCI_INSN
;
296 optbitset
|= 1 << CGEN_INSN_OPTIONAL_UCI_INSN
;
299 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_UCI_INSN
);
300 optbitset
|= 1 << CGEN_INSN_OPTIONAL_UCI_INSN
;
303 optbits
|= 1 << CGEN_INSN_OPTIONAL_DSP_INSN
;
304 optbitset
|= 1 << CGEN_INSN_OPTIONAL_DSP_INSN
;
307 optbits
&= ~(1 << CGEN_INSN_OPTIONAL_DSP_INSN
);
308 optbitset
|= 1 << CGEN_INSN_OPTIONAL_DSP_INSN
;
311 library_flag
= EF_MEP_LIBRARY
;
314 case OPTION_NOREPEAT
:
323 md_show_usage (FILE *stream
)
325 fprintf (stream
, _("MeP specific command line options:\n\
326 -EB assemble for a big endian system\n\
327 -EL assemble for a little endian system (default)\n\
328 -mconfig=<name> specify a chip configuration to use\n\
329 -maverage -mno-average -mmult -mno-mult -mdiv -mno-div\n\
330 -mbitops -mno-bitops -mleadz -mno-leadz -mabsdiff -mno-absdiff\n\
331 -mminmax -mno-minmax -mclip -mno-clip -msatur -mno-satur -mcop32\n\
332 enable/disable the given opcodes\n\
334 If -mconfig is given, the other -m options modify it. Otherwise,\n\
335 if no -m options are given, all core opcodes are enabled;\n\
336 if any enabling -m options are given, only those are enabled;\n\
337 if only disabling -m options are given, only those are disabled.\n\
339 if (mep_config_map
[1].name
)
342 fprintf (stream
, " -mconfig=STR specify the configuration to use\n");
343 fprintf (stream
, " Configurations:");
344 for (i
=0; mep_config_map
[i
].name
; i
++)
345 fprintf (stream
, " %s", mep_config_map
[i
].name
);
346 fprintf (stream
, "\n");
353 mep_check_for_disabled_registers (mep_insn
*insn
)
355 static int initted
= 0;
356 static int has_mul_div
= 0;
357 static int has_cop
= 0;
358 static int has_debug
= 0;
361 if (allow_disabled_registers
)
365 if (target_big_endian
)
366 b
= insn
->buffer
[0] * 256 + insn
->buffer
[1];
368 b
= insn
->buffer
[1] * 256 + insn
->buffer
[0];
373 if ((b
& 0xfffff00e) == 0x7008 /* stc */
374 || (b
& 0xfffff00e) == 0x700a /* ldc */)
379 if ((MEP_OMASK
& (1 << CGEN_INSN_OPTIONAL_MUL_INSN
))
380 || (MEP_OMASK
& (1 << CGEN_INSN_OPTIONAL_DIV_INSN
)))
382 if (MEP_OMASK
& (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN
))
384 if (MEP_OMASK
& (1 << CGEN_INSN_OPTIONAL_CP_INSN
))
388 r
= ((b
& 0x00f0) >> 4) | ((b
& 0x0001) << 4);
394 as_bad ("$hi and $lo are disabled when MUL and DIV are off");
401 as_bad ("$mb0, $me0, $mb1, and $me1 are disabled when COP is off");
406 as_bad ("$dbg and $depc are disabled when DEBUG is off");
418 case EF_MEP_CPU_C2
: return bfd_mach_mep
;
419 case EF_MEP_CPU_C3
: return bfd_mach_mep
;
420 case EF_MEP_CPU_C4
: return bfd_mach_mep
;
421 case EF_MEP_CPU_C5
: return bfd_mach_mep_c5
;
422 case EF_MEP_CPU_H1
: return bfd_mach_mep_h1
;
428 /* The MeP version of the cgen parse_operand function. The only difference
429 from the standard version is that we want to avoid treating '$foo' and
430 '($foo...)' as references to a symbol called '$foo'. The chances are
431 that '$foo' is really a misspelt register. */
434 mep_parse_operand (CGEN_CPU_DESC cd
, enum cgen_parse_operand_type want
,
435 const char **strP
, int opindex
, int opinfo
,
436 enum cgen_parse_operand_result
*resultP
, bfd_vma
*valueP
)
438 if (want
== CGEN_PARSE_OPERAND_INTEGER
|| want
== CGEN_PARSE_OPERAND_ADDRESS
)
446 return "Not a valid literal";
448 return gas_cgen_parse_operand (cd
, want
, strP
, opindex
, opinfo
,
455 /* Initialize the `cgen' interface. */
457 /* If the user specifies no options, we default to allowing
458 everything. If the user specifies any enabling options, we
459 default to allowing only what is specified. If the user
460 specifies only disabling options, we only disable what is
461 specified. If the user specifies options and a config, the
462 options modify the config. */
463 if (optbits
&& mep_config_index
== 0)
466 MEP_OMASK
= (MEP_OMASK
& ~optbitset
) | optbits
;
468 /* Set the machine number and endian. */
469 gas_cgen_cpu_desc
= mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS
, 0,
470 CGEN_CPU_OPEN_ENDIAN
,
473 : CGEN_ENDIAN_LITTLE
,
474 CGEN_CPU_OPEN_ISAS
, 0,
476 mep_cgen_init_asm (gas_cgen_cpu_desc
);
478 /* This is a callback from cgen to gas to parse operands. */
479 cgen_set_parse_operand_fn (gas_cgen_cpu_desc
, mep_parse_operand
);
481 /* Identify the architecture. */
482 bfd_default_set_arch_mach (stdoutput
, bfd_arch_mep
, mep_machine ());
484 /* Store the configuration number and core. */
485 bfd_set_private_flags (stdoutput
, MEP_CPU
| MEP_CONFIG
| library_flag
);
487 /* Initialize the array we'll be using to store fixups. */
488 gas_cgen_initialize_saved_fixups_array();
491 /* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a
492 coprocessor instruction, if possible, into FIELDS, BUF, and INSN. */
494 static const CGEN_INSN
*
495 mep_cgen_assemble_cop_insn (CGEN_CPU_DESC cd
,
498 CGEN_INSN_BYTES_PTR buf
,
499 const struct cgen_insn
*pinsn
)
502 CGEN_INSN_LIST
*ilist
;
503 const char *errmsg
= NULL
;
505 /* The instructions are stored in hashed lists. */
506 ilist
= CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc
,
507 CGEN_INSN_MNEMONIC (pinsn
));
510 for ( ; ilist
!= NULL
; ilist
= CGEN_ASM_NEXT_INSN (ilist
))
512 const CGEN_INSN
*insn
= ilist
->insn
;
513 if (strcmp (CGEN_INSN_MNEMONIC (ilist
->insn
),
514 CGEN_INSN_MNEMONIC (pinsn
)) == 0
515 && MEP_INSN_COP_P (ilist
->insn
)
516 && mep_cgen_insn_supported (cd
, insn
))
520 /* skip this insn if str doesn't look right lexically */
521 if (CGEN_INSN_RX (insn
) != NULL
&&
522 regexec ((regex_t
*) CGEN_INSN_RX (insn
), str
, 0, NULL
, 0) == REG_NOMATCH
)
525 /* Allow parse/insert handlers to obtain length of insn. */
526 CGEN_FIELDS_BITSIZE (fields
) = CGEN_INSN_BITSIZE (insn
);
528 errmsg
= CGEN_PARSE_FN (cd
, insn
) (cd
, insn
, & str
, fields
);
532 errmsg
= CGEN_INSERT_FN (cd
, insn
) (cd
, insn
, fields
, buf
,
544 mep_save_insn (mep_insn insn
)
546 /* Consider change MAX_SAVED_FIXUP_CHAINS to MAX_PARALLEL_INSNS. */
547 if (num_insns_saved
< 0 || num_insns_saved
>= MAX_SAVED_FIXUP_CHAINS
)
549 as_fatal("index into saved_insns[] out of bounds.");
552 saved_insns
[num_insns_saved
] = insn
;
553 gas_cgen_save_fixups(num_insns_saved
);
558 mep_check_parallel32_scheduling (void)
560 int insn0iscopro
, insn1iscopro
, insn0length
, insn1length
;
562 /* More than two instructions means that either someone is referring to
563 an internally parallel core or an internally parallel coprocessor,
564 neither of which are supported at this time. */
565 if ( num_insns_saved
> 2 )
566 as_fatal("Internally paralled cores and coprocessors not supported.");
568 /* If there are no insns saved, that's ok. Just return. This will
569 happen when mep_process_saved_insns is called when the end of the
570 source file is reached and there are no insns left to be processed. */
571 if (num_insns_saved
== 0)
574 /* Check some of the attributes of the first insn. */
575 insn0iscopro
= MEP_INSN_COP_P (saved_insns
[0].insn
);
576 insn0length
= CGEN_FIELDS_BITSIZE (& saved_insns
[0].fields
);
578 if (num_insns_saved
== 2)
580 /* Check some of the attributes of the first insn. */
581 insn1iscopro
= MEP_INSN_COP_P (saved_insns
[1].insn
);
582 insn1length
= CGEN_FIELDS_BITSIZE (& saved_insns
[1].fields
);
584 if ((insn0iscopro
&& !insn1iscopro
)
585 || (insn1iscopro
&& !insn0iscopro
))
587 /* We have one core and one copro insn. If their sizes
588 add up to 32, then the combination is valid. */
589 if (insn0length
+ insn1length
== 32)
592 as_bad ("core and copro insn lengths must total 32 bits.");
595 as_bad ("vliw group must consist of 1 core and 1 copro insn.");
599 /* If we arrive here, we have one saved instruction. There are a
600 number of possible cases:
602 1. The instruction is a 32 bit core or coprocessor insn and
603 can be executed by itself. Valid.
605 2. The instrucion is a core instruction for which a cop nop
606 exists. In this case, insert the cop nop into the saved
607 insn array after the core insn and return. Valid.
609 3. The instruction is a coprocessor insn for which a core nop
610 exists. In this case, move the coprocessor insn to the
611 second element of the array and put the nop in the first
612 element then return. Valid.
614 4. The instruction is a core or coprocessor instruction for
615 which there is no matching coprocessor or core nop to use
616 to form a valid vliw insn combination. In this case, we
619 if (insn0length
> 32)
620 as_fatal ("Cannot use 48- or 64-bit insns with a 32 bit datapath.");
622 if (insn0length
== 32)
625 /* Insn is smaller than datapath. If there are no matching
626 nops for this insn, then terminate assembly. */
627 if (CGEN_INSN_ATTR_VALUE (saved_insns
[0].insn
,
628 CGEN_INSN_VLIW32_NO_MATCHING_NOP
))
629 as_fatal ("No valid nop.");
631 /* At this point we know that we have a single 16-bit insn that has
632 a matching nop. We have to assemble it and put it into the saved
633 insn and fixup chain arrays. */
640 /* Move the insn and it's fixups to the second element of the
641 saved insns arrary and insert a 16 bit core nope into the
643 insn
.insn
= mep_cgen_assemble_insn (gas_cgen_cpu_desc
, "nop",
644 &insn
.fields
, insn
.buffer
,
648 as_bad ("%s", errmsg
);
652 /* Move the insn in element 0 to element 1 and insert the
653 nop into element 0. Move the fixups in element 0 to
654 element 1 and save the current fixups to element 0.
655 Really there aren't any fixups at this point because we're
656 inserting a nop but we might as well be general so that
657 if there's ever a need to insert a general insn, we'll
659 saved_insns
[1] = saved_insns
[0];
660 saved_insns
[0] = insn
;
662 gas_cgen_swap_fixups (0);
663 gas_cgen_save_fixups (1);
669 int insn_num
= saved_insns
[0].insn
->base
->num
;
671 /* Use 32 bit branches and skip the nop. */
672 if (insn_num
== MEP_INSN_BSR12
673 || insn_num
== MEP_INSN_BEQZ
674 || insn_num
== MEP_INSN_BNEZ
)
677 /* Insert a 16-bit coprocessor nop. Note that at the time */
678 /* this was done, no 16-bit coprocessor nop was defined. */
679 insn
.insn
= mep_cgen_assemble_insn (gas_cgen_cpu_desc
, "cpnop16",
680 &insn
.fields
, insn
.buffer
,
684 as_bad ("%s", errmsg
);
688 /* Now put the insn and fixups into the arrays. */
689 mep_save_insn (insn
);
695 mep_check_parallel64_scheduling (void)
697 int insn0iscopro
, insn1iscopro
, insn0length
, insn1length
;
699 /* More than two instructions means that someone is referring to an
700 internally parallel core or an internally parallel coprocessor. */
701 /* These are not currently supported. */
702 if (num_insns_saved
> 2)
703 as_fatal ("Internally parallel cores of coprocessors not supported.");
705 /* If there are no insns saved, that's ok. Just return. This will
706 happen when mep_process_saved_insns is called when the end of the
707 source file is reached and there are no insns left to be processed. */
708 if (num_insns_saved
== 0)
711 /* Check some of the attributes of the first insn. */
712 insn0iscopro
= MEP_INSN_COP_P (saved_insns
[0].insn
);
713 insn0length
= CGEN_FIELDS_BITSIZE (& saved_insns
[0].fields
);
715 if (num_insns_saved
== 2)
717 /* Check some of the attributes of the first insn. */
718 insn1iscopro
= MEP_INSN_COP_P (saved_insns
[1].insn
);
719 insn1length
= CGEN_FIELDS_BITSIZE (& saved_insns
[1].fields
);
721 if ((insn0iscopro
&& !insn1iscopro
)
722 || (insn1iscopro
&& !insn0iscopro
))
724 /* We have one core and one copro insn. If their sizes
725 add up to 64, then the combination is valid. */
726 if (insn0length
+ insn1length
== 64)
729 as_bad ("core and copro insn lengths must total 64 bits.");
732 as_bad ("vliw group must consist of 1 core and 1 copro insn.");
736 /* If we arrive here, we have one saved instruction. There are a
737 number of possible cases:
739 1. The instruction is a 64 bit coprocessor insn and can be
740 executed by itself. Valid.
742 2. The instrucion is a core instruction for which a cop nop
743 exists. In this case, insert the cop nop into the saved
744 insn array after the core insn and return. Valid.
746 3. The instruction is a coprocessor insn for which a core nop
747 exists. In this case, move the coprocessor insn to the
748 second element of the array and put the nop in the first
749 element then return. Valid.
751 4. The instruction is a core or coprocessor instruction for
752 which there is no matching coprocessor or core nop to use
753 to form a valid vliw insn combination. In this case, we
756 /* If the insn is 64 bits long, it can run alone. The size check
757 is done indepependantly of whether the insn is core or copro
758 in case 64 bit coprocessor insns are added later. */
759 if (insn0length
== 64)
762 /* Insn is smaller than datapath. If there are no matching
763 nops for this insn, then terminate assembly. */
764 if (CGEN_INSN_ATTR_VALUE (saved_insns
[0].insn
,
765 CGEN_INSN_VLIW64_NO_MATCHING_NOP
))
766 as_fatal ("No valid nop.");
774 /* Initialize the insn buffer. */
775 for (i
= 0; i
< 64; i
++)
776 insn
.buffer
[i
] = '\0';
778 /* We have a coprocessor insn. At this point in time there
779 are is 32-bit core nop. There is only a 16-bit core
780 nop. The idea is to allow for a relatively arbitrary
781 coprocessor to be specified. We aren't looking at
782 trying to cover future changes in the core at this time
783 since it is assumed that the core will remain fairly
784 static. If there ever are 32 or 48 bit core nops added,
785 they will require entries below. */
787 if (insn0length
== 48)
789 /* Move the insn and fixups to the second element of the
790 arrays then assemble and insert a 16 bit core nop. */
791 insn
.insn
= mep_cgen_assemble_insn (gas_cgen_cpu_desc
, "nop",
792 & insn
.fields
, insn
.buffer
,
797 /* If this is reached, then we have a single coprocessor
798 insn that is not 48 bits long, but for which the assembler
799 thinks there is a matching core nop. If a 32-bit core
800 nop has been added, then make the necessary changes and
801 handle its assembly and insertion here. Otherwise,
802 go figure out why either:
804 1. The assembler thinks that there is a 32-bit core nop
805 to match a 32-bit coprocessor insn, or
806 2. The assembler thinks that there is a 48-bit core nop
807 to match a 16-bit coprocessor insn. */
809 as_fatal ("Assembler expects a non-existent core nop.");
814 as_bad ("%s", errmsg
);
818 /* Move the insn in element 0 to element 1 and insert the
819 nop into element 0. Move the fixups in element 0 to
820 element 1 and save the current fixups to element 0.
821 Really there aren't any fixups at this point because we're
822 inserting a nop but we might as well be general so that
823 if there's ever a need to insert a general insn, we'll
826 saved_insns
[1] = saved_insns
[0];
827 saved_insns
[0] = insn
;
829 gas_cgen_swap_fixups(0);
830 gas_cgen_save_fixups(1);
839 /* Initialize the insn buffer */
840 for (i
= 0; i
< 64; i
++)
841 insn
.buffer
[i
] = '\0';
843 /* We have a core insn. We have to handle all possible nop
844 lengths. If a coprocessor doesn't have a nop of a certain
845 length but there exists core insns that when combined with
846 a nop of that length would fill the datapath, those core
847 insns will be flagged with the VLIW_NO_CORRESPONDING_NOP
848 attribute. That will ensure that when used in a way that
849 requires a nop to be inserted, assembly will terminate
850 before reaching this section of code. This guarantees
851 that cases below which would result in the attempted
852 insertion of nop that doesn't exist will never be entered. */
853 if (insn0length
== 16)
855 /* Insert 48 bit coprocessor nop. */
856 /* Assemble it and put it into the arrays. */
857 insn
.insn
= mep_cgen_assemble_insn (gas_cgen_cpu_desc
, "cpnop48",
858 &insn
.fields
, insn
.buffer
,
861 else if (insn0length
== 32)
863 /* Insert 32 bit coprocessor nop. */
864 insn
.insn
= mep_cgen_assemble_insn (gas_cgen_cpu_desc
, "cpnop32",
865 &insn
.fields
, insn
.buffer
,
868 else if (insn0length
== 48)
870 /* Insert 16 bit coprocessor nop. */
871 insn
.insn
= mep_cgen_assemble_insn (gas_cgen_cpu_desc
, "cpnop16",
872 &insn
.fields
, insn
.buffer
,
876 /* Core insn has an invalid length. Something has gone wrong. */
877 as_fatal ("Core insn has invalid length! Something is wrong!");
881 as_bad ("%s", errmsg
);
885 /* Now put the insn and fixups into the arrays. */
886 mep_save_insn (insn
);
891 /* The scheduling functions are just filters for invalid combinations.
892 If there is a violation, they terminate assembly. Otherise they
893 just fall through. Succesful combinations cause no side effects
894 other than valid nop insertion. */
897 mep_check_parallel_scheduling (void)
899 /* This is where we will eventually read the config information
900 and choose which scheduling checking function to call. */
902 mep_check_parallel64_scheduling ();
904 mep_check_parallel32_scheduling ();
908 mep_process_saved_insns (void)
912 gas_cgen_save_fixups (MAX_SAVED_FIXUP_CHAINS
- 1);
914 /* We have to check for valid scheduling here. */
915 mep_check_parallel_scheduling ();
917 /* If the last call didn't cause assembly to terminate, we have
918 a valid vliw insn/insn pair saved. Restore this instructions'
919 fixups and process the insns. */
920 for (i
= 0;i
<num_insns_saved
;i
++)
922 gas_cgen_restore_fixups (i
);
923 gas_cgen_finish_insn (saved_insns
[i
].insn
, saved_insns
[i
].buffer
,
924 CGEN_FIELDS_BITSIZE (& saved_insns
[i
].fields
),
927 gas_cgen_restore_fixups (MAX_SAVED_FIXUP_CHAINS
- 1);
929 /* Clear the fixups and reset the number insn saved to 0. */
930 gas_cgen_initialize_saved_fixups_array ();
932 listing_prev_line ();
936 md_assemble (char * str
)
938 static CGEN_BITSET
* isas
= NULL
;
941 /* Initialize GAS's cgen interface for a new instruction. */
942 gas_cgen_init_parse ();
944 /* There are two possible modes: core and vliw. We have to assemble
945 differently for each.
947 Core Mode: We assemble normally. All instructions are on a
948 single line and are made up of one mnemonic and one
950 VLIW Mode: Vliw combinations are indicated as follows:
955 We want to handle the general case where more than
956 one instruction can be preceeded by a +. This will
957 happen later if we add support for internally parallel
958 coprocessors. We'll make the parsing nice and general
959 so that it can handle an arbitrary number of insns
960 with leading +'s. The actual checking for valid
961 combinations is done elsewhere. */
963 /* Initialize the isa to refer to the core. */
965 isas
= cgen_bitset_copy (& MEP_CORE_ISA
);
968 cgen_bitset_clear (isas
);
969 cgen_bitset_union (isas
, & MEP_CORE_ISA
, isas
);
971 gas_cgen_cpu_desc
->isas
= isas
;
977 int thisInsnIsCopro
= 0;
981 /* Initialize the insn buffer */
983 if (! CGEN_INT_INSN_P
)
984 for (i
=0; i
< CGEN_MAX_INSN_SIZE
; i
++)
987 /* Can't tell core / copro insns apart at parse time! */
988 cgen_bitset_union (isas
, & MEP_COP_ISA
, isas
);
990 /* Assemble the insn so we can examine its attributes. */
991 insn
.insn
= mep_cgen_assemble_insn (gas_cgen_cpu_desc
, str
,
992 &insn
.fields
, insn
.buffer
,
996 as_bad ("%s", errmsg
);
999 mep_check_for_disabled_registers (&insn
);
1001 /* Check to see if it's a coprocessor instruction. */
1002 thisInsnIsCopro
= MEP_INSN_COP_P (insn
.insn
);
1004 if (!thisInsnIsCopro
)
1006 insn
.insn
= mep_cgen_assemble_cop_insn (gas_cgen_cpu_desc
, str
,
1007 &insn
.fields
, insn
.buffer
,
1009 thisInsnIsCopro
= MEP_INSN_COP_P (insn
.insn
);
1010 mep_check_for_disabled_registers (&insn
);
1015 /* A plus was present. */
1016 /* Check for a + with a core insn and abort if found. */
1017 if (!thisInsnIsCopro
)
1019 as_fatal("A core insn cannot be preceeded by a +.\n");
1023 if (num_insns_saved
> 0)
1025 /* There are insns in the queue. Add this one. */
1026 mep_save_insn (insn
);
1030 /* There are no insns in the queue and a plus is present.
1031 This is a syntax error. Let's not tolerate this.
1032 We can relax this later if necessary. */
1033 as_bad (_("Invalid use of parallelization operator."));
1039 /* No plus was present. */
1040 if (num_insns_saved
> 0)
1042 /* There are insns saved and we came across an insn without a
1043 leading +. That's the signal to process the saved insns
1044 before proceeding then treat the current insn as the first
1045 in a new vliw group. */
1046 mep_process_saved_insns ();
1047 num_insns_saved
= 0;
1048 /* mep_save_insn (insn); */
1050 mep_save_insn (insn
);
1055 /* Core Insn. Add it to the beginning of the queue. */
1056 mep_save_insn (insn
);
1057 /* gas_cgen_save_fixups(num_insns_saved); */
1068 /* Only single instructions are assembled in core mode. */
1071 /* If a leading '+' was present, issue an error.
1072 That's not allowed in core mode. */
1075 as_bad (_("Leading plus sign not allowed in core mode"));
1079 insn
.insn
= mep_cgen_assemble_insn
1080 (gas_cgen_cpu_desc
, str
, & insn
.fields
, insn
.buffer
, & errmsg
);
1084 as_bad ("%s", errmsg
);
1087 gas_cgen_finish_insn (insn
.insn
, insn
.buffer
,
1088 CGEN_FIELDS_BITSIZE (& insn
.fields
), 1, NULL
);
1089 mep_check_for_disabled_registers (&insn
);
1094 md_section_align (segT segment
, valueT size
)
1096 int align
= bfd_get_section_alignment (stdoutput
, segment
);
1097 return ((size
+ (1 << align
) - 1) & (-1 << align
));
1102 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
1107 /* Interface to relax_segment. */
1110 const relax_typeS md_relax_table
[] =
1113 1) most positive reach of this state,
1114 2) most negative reach of this state,
1115 3) how many bytes this mode will have in the variable part of the frag
1116 4) which index into the table to try if we can't fit into this one. */
1117 /* Note that we use "beq" because "jmp" has a peculiarity - it cannot
1118 jump to addresses with any bits 27..24 set. So, we use beq as a
1119 17-bit pc-relative branch to avoid using jmp, just in case. */
1121 /* 0 */ { 0, 0, 0, 0 }, /* unused */
1122 /* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */
1124 /* 2 */ { 2047, -2048, 0, 3 }, /* bsr12 */
1125 /* 3 */ { 0, 0, 2, 0 }, /* bsr16 */
1127 /* 4 */ { 2047, -2048, 0, 5 }, /* bra */
1128 /* 5 */ { 65535, -65536, 2, 6 }, /* beq $0,$0 */
1129 /* 6 */ { 0, 0, 2, 0 }, /* jmp24 */
1131 /* 7 */ { 65535, -65536, 0, 8 }, /* beqi */
1132 /* 8 */ { 0, 0, 4, 0 }, /* bnei/jmp */
1134 /* 9 */ { 127, -128, 0, 10 }, /* beqz */
1135 /* 10 */ { 65535, -65536, 2, 11 }, /* beqi */
1136 /* 11 */ { 0, 0, 4, 0 }, /* bnei/jmp */
1138 /* 12 */ { 65535, -65536, 0, 13 }, /* bnei */
1139 /* 13 */ { 0, 0, 4, 0 }, /* beqi/jmp */
1141 /* 14 */ { 127, -128, 0, 15 }, /* bnez */
1142 /* 15 */ { 65535, -65536, 2, 16 }, /* bnei */
1143 /* 16 */ { 0, 0, 4, 0 }, /* beqi/jmp */
1145 /* 17 */ { 65535, -65536, 0, 13 }, /* bgei */
1146 /* 18 */ { 0, 0, 4, 0 },
1147 /* 19 */ { 65535, -65536, 0, 13 }, /* blti */
1148 /* 20 */ { 0, 0, 4, 0 },
1149 /* 19 */ { 65535, -65536, 0, 13 }, /* bcpeq */
1150 /* 20 */ { 0, 0, 4, 0 },
1151 /* 19 */ { 65535, -65536, 0, 13 }, /* bcpne */
1152 /* 20 */ { 0, 0, 4, 0 },
1153 /* 19 */ { 65535, -65536, 0, 13 }, /* bcpat */
1154 /* 20 */ { 0, 0, 4, 0 },
1155 /* 19 */ { 65535, -65536, 0, 13 }, /* bcpaf */
1156 /* 20 */ { 0, 0, 4, 0 }
1159 /* Pseudo-values for 64 bit "insns" which are combinations of two 32
1163 MEP_PSEUDO64_16BITCC
,
1164 MEP_PSEUDO64_32BITCC
,
1165 } MepPseudo64Values
;
1170 int insn_for_extern
;
1171 } subtype_mappings
[] = {
1174 { MEP_INSN_BSR12
, 0, MEP_INSN_BSR24
},
1175 { MEP_INSN_BSR24
, 2, MEP_INSN_BSR24
},
1176 { MEP_INSN_BRA
, 0, MEP_INSN_BRA
},
1177 { MEP_INSN_BEQ
, 2, MEP_INSN_BEQ
},
1178 { MEP_INSN_JMP
, 2, MEP_INSN_JMP
},
1179 { MEP_INSN_BEQI
, 0, MEP_INSN_BEQI
},
1180 { -1, 4, MEP_PSEUDO64_32BITCC
},
1181 { MEP_INSN_BEQZ
, 0, MEP_INSN_BEQZ
},
1182 { MEP_INSN_BEQI
, 2, MEP_INSN_BEQI
},
1183 { -1, 4, MEP_PSEUDO64_16BITCC
},
1184 { MEP_INSN_BNEI
, 0, MEP_INSN_BNEI
},
1185 { -1, 4, MEP_PSEUDO64_32BITCC
},
1186 { MEP_INSN_BNEZ
, 0, MEP_INSN_BNEZ
},
1187 { MEP_INSN_BNEI
, 2, MEP_INSN_BNEI
},
1188 { -1, 4, MEP_PSEUDO64_16BITCC
},
1189 { MEP_INSN_BGEI
, 0, MEP_INSN_BGEI
},
1190 { -1, 4, MEP_PSEUDO64_32BITCC
},
1191 { MEP_INSN_BLTI
, 0, MEP_INSN_BLTI
},
1192 { -1, 4, MEP_PSEUDO64_32BITCC
},
1193 { MEP_INSN_BCPEQ
, 0, MEP_INSN_BCPEQ
},
1194 { -1, 4, MEP_PSEUDO64_32BITCC
},
1195 { MEP_INSN_BCPNE
, 0, MEP_INSN_BCPNE
},
1196 { -1, 4, MEP_PSEUDO64_32BITCC
},
1197 { MEP_INSN_BCPAT
, 0, MEP_INSN_BCPAT
},
1198 { -1, 4, MEP_PSEUDO64_32BITCC
},
1199 { MEP_INSN_BCPAF
, 0, MEP_INSN_BCPAF
},
1200 { -1, 4, MEP_PSEUDO64_32BITCC
}
1202 #define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
1205 mep_prepare_relax_scan (fragS
*fragP
, offsetT
*aim
, relax_substateT this_state
)
1207 symbolS
*symbolP
= fragP
->fr_symbol
;
1208 if (symbolP
&& !S_IS_DEFINED (symbolP
))
1210 /* Adjust for MeP pcrel not being relative to the next opcode. */
1211 *aim
+= 2 + md_relax_table
[this_state
].rlx_length
;
1215 insn_to_subtype (int insn
)
1218 for (i
=0; i
<NUM_MAPPINGS
; i
++)
1219 if (insn
== subtype_mappings
[i
].insn
)
1224 /* Return an initial guess of the length by which a fragment must grow
1225 to hold a branch to reach its destination. Also updates fr_type
1226 and fr_subtype as necessary.
1228 Called just before doing relaxation. Any symbol that is now
1229 undefined will not become defined. The guess for fr_var is
1230 ACTUALLY the growth beyond fr_fix. Whatever we do to grow fr_fix
1231 or fr_var contributes to our returned value. Although it may not
1232 be explicit in the frag, pretend fr_var starts with a 0 value. */
1235 md_estimate_size_before_relax (fragS
* fragP
, segT segment
)
1237 if (fragP
->fr_subtype
== 1)
1238 fragP
->fr_subtype
= insn_to_subtype (fragP
->fr_cgen
.insn
->base
->num
);
1240 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1244 new_insn
= subtype_mappings
[fragP
->fr_subtype
].insn_for_extern
;
1245 fragP
->fr_subtype
= insn_to_subtype (new_insn
);
1248 if (MEP_VLIW
&& ! MEP_VLIW64
1249 && (bfd_get_section_flags (stdoutput
, segment
) & SEC_MEP_VLIW
))
1251 /* Use 32 bit branches for vliw32 so the vliw word is not split. */
1252 switch (fragP
->fr_cgen
.insn
->base
->num
)
1254 case MEP_INSN_BSR12
:
1255 fragP
->fr_subtype
= insn_to_subtype
1256 (subtype_mappings
[fragP
->fr_subtype
].insn_for_extern
);
1259 fragP
->fr_subtype
++;
1262 fragP
->fr_subtype
++;
1267 if (fragP
->fr_cgen
.insn
->base
1268 && fragP
->fr_cgen
.insn
->base
->num
1269 != subtype_mappings
[fragP
->fr_subtype
].insn
)
1271 int new_insn
= subtype_mappings
[fragP
->fr_subtype
].insn
;
1274 fragP
->fr_cgen
.insn
= (fragP
->fr_cgen
.insn
1275 - fragP
->fr_cgen
.insn
->base
->num
1280 return subtype_mappings
[fragP
->fr_subtype
].growth
;
1283 /* *fragP has been relaxed to its final size, and now needs to have
1284 the bytes inside it modified to conform to the new size.
1286 Called after relaxation is finished.
1287 fragP->fr_type == rs_machine_dependent.
1288 fragP->fr_subtype is the subtype of what the address relaxed to. */
1291 target_address_for (fragS
*frag
)
1293 int rv
= frag
->fr_offset
;
1294 symbolS
*sym
= frag
->fr_symbol
;
1297 rv
+= S_GET_VALUE (sym
);
1303 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
1304 segT sec ATTRIBUTE_UNUSED
,
1307 int addend
, rn
, bit
= 0;
1309 int where
= fragP
->fr_opcode
- fragP
->fr_literal
;
1310 int e
= target_big_endian
? 0 : 1;
1312 addend
= target_address_for (fragP
) - (fragP
->fr_address
+ where
);
1314 if (subtype_mappings
[fragP
->fr_subtype
].insn
== -1)
1316 fragP
->fr_fix
+= subtype_mappings
[fragP
->fr_subtype
].growth
;
1317 switch (subtype_mappings
[fragP
->fr_subtype
].insn_for_extern
)
1319 case MEP_PSEUDO64_16BITCC
:
1320 fragP
->fr_opcode
[1^e
] = ((fragP
->fr_opcode
[1^e
] & 1) ^ 1) | 0x06;
1321 fragP
->fr_opcode
[2^e
] = 0xd8;
1322 fragP
->fr_opcode
[3^e
] = 0x08;
1323 fragP
->fr_opcode
[4^e
] = 0;
1324 fragP
->fr_opcode
[5^e
] = 0;
1327 case MEP_PSEUDO64_32BITCC
:
1328 if (fragP
->fr_opcode
[0^e
] & 0x10)
1329 fragP
->fr_opcode
[1^e
] ^= 0x01;
1331 fragP
->fr_opcode
[1^e
] ^= 0x04;
1332 fragP
->fr_opcode
[2^e
] = 0;
1333 fragP
->fr_opcode
[3^e
] = 4;
1334 fragP
->fr_opcode
[4^e
] = 0xd8;
1335 fragP
->fr_opcode
[5^e
] = 0x08;
1336 fragP
->fr_opcode
[6^e
] = 0;
1337 fragP
->fr_opcode
[7^e
] = 0;
1343 fragP
->fr_cgen
.insn
= (fragP
->fr_cgen
.insn
1344 - fragP
->fr_cgen
.insn
->base
->num
1346 operand
= MEP_OPERAND_PCABS24A2
;
1349 switch (fragP
->fr_cgen
.insn
->base
->num
)
1351 case MEP_INSN_BSR12
:
1352 fragP
->fr_opcode
[0^e
] = 0xb0 | ((addend
>> 8) & 0x0f);
1353 fragP
->fr_opcode
[1^e
] = 0x01 | (addend
& 0xfe);
1354 operand
= MEP_OPERAND_PCREL12A2
;
1357 case MEP_INSN_BSR24
:
1359 fragP
->fr_opcode
[0^e
] = 0xd8 | ((addend
>> 5) & 0x07);
1360 fragP
->fr_opcode
[1^e
] = 0x09 | ((addend
<< 3) & 0xf0);
1361 fragP
->fr_opcode
[2^e
] = 0x00 | ((addend
>>16) & 0xff);
1362 fragP
->fr_opcode
[3^e
] = 0x00 | ((addend
>> 8) & 0xff);
1363 operand
= MEP_OPERAND_PCREL24A2
;
1367 fragP
->fr_opcode
[0^e
] = 0xb0 | ((addend
>> 8) & 0x0f);
1368 fragP
->fr_opcode
[1^e
] = 0x00 | (addend
& 0xfe);
1369 operand
= MEP_OPERAND_PCREL12A2
;
1373 /* The default relax_frag doesn't change the state if there is no
1374 growth, so we must manually handle converting out-of-range BEQ
1375 instructions to JMP. */
1376 if (addend
<= 65535 && addend
>= -65536)
1379 fragP
->fr_opcode
[0^e
] = 0xe0;
1380 fragP
->fr_opcode
[1^e
] = 0x01;
1381 fragP
->fr_opcode
[2^e
] = 0x00 | ((addend
>> 9) & 0xff);
1382 fragP
->fr_opcode
[3^e
] = 0x00 | ((addend
>> 1) & 0xff);
1383 operand
= MEP_OPERAND_PCREL17A2
;
1386 /* ...FALLTHROUGH... */
1389 addend
= target_address_for (fragP
);
1391 fragP
->fr_opcode
[0^e
] = 0xd8 | ((addend
>> 5) & 0x07);
1392 fragP
->fr_opcode
[1^e
] = 0x08 | ((addend
<< 3) & 0xf0);
1393 fragP
->fr_opcode
[2^e
] = 0x00 | ((addend
>>16) & 0xff);
1394 fragP
->fr_opcode
[3^e
] = 0x00 | ((addend
>> 8) & 0xff);
1395 operand
= MEP_OPERAND_PCABS24A2
;
1401 fragP
->fr_opcode
[1^e
] = bit
| (addend
& 0xfe);
1402 operand
= MEP_OPERAND_PCREL8A2
;
1408 if (subtype_mappings
[fragP
->fr_subtype
].growth
)
1410 fragP
->fr_fix
+= subtype_mappings
[fragP
->fr_subtype
].growth
;
1411 rn
= fragP
->fr_opcode
[0^e
] & 0x0f;
1412 fragP
->fr_opcode
[0^e
] = 0xe0 | rn
;
1413 fragP
->fr_opcode
[1^e
] = bit
;
1415 fragP
->fr_opcode
[2^e
] = 0x00 | ((addend
>> 9) & 0xff);
1416 fragP
->fr_opcode
[3^e
] = 0x00 | ((addend
>> 1) & 0xff);
1417 operand
= MEP_OPERAND_PCREL17A2
;
1422 case MEP_INSN_BCPEQ
:
1423 case MEP_INSN_BCPNE
:
1424 case MEP_INSN_BCPAT
:
1425 case MEP_INSN_BCPAF
:
1426 /* No opcode change needed, just operand. */
1427 fragP
->fr_opcode
[2^e
] = (addend
>> 9) & 0xff;
1428 fragP
->fr_opcode
[3^e
] = (addend
>> 1) & 0xff;
1429 operand
= MEP_OPERAND_PCREL17A2
;
1436 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
1437 || operand
== MEP_OPERAND_PCABS24A2
)
1439 assert (fragP
->fr_cgen
.insn
!= 0);
1440 gas_cgen_record_fixup (fragP
,
1442 fragP
->fr_cgen
.insn
,
1443 (fragP
->fr_fix
- where
) * 8,
1444 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1446 fragP
->fr_cgen
.opinfo
,
1447 fragP
->fr_symbol
, fragP
->fr_offset
);
1452 /* Functions concerning relocs. */
1455 mep_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
1457 /* If we already know the fixup value, adjust it in the same
1458 way that the linker would have done. */
1459 if (fixP
->fx_addsy
== 0)
1460 switch (fixP
->fx_cgen
.opinfo
)
1462 case BFD_RELOC_MEP_LOW16
:
1463 *valP
= ((long)(*valP
& 0xffff)) << 16 >> 16;
1465 case BFD_RELOC_MEP_HI16U
:
1468 case BFD_RELOC_MEP_HI16S
:
1469 *valP
= (*valP
+ 0x8000) >> 16;
1473 /* Now call cgen's md_aply_fix. */
1474 gas_cgen_md_apply_fix (fixP
, valP
, seg
);
1478 md_pcrel_from_section (fixS
*fixP
, segT sec
)
1480 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1481 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1482 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1483 /* The symbol is undefined (or is defined but not in this section).
1484 Let the linker figure it out. */
1487 /* Return the address of the opcode - cgen adjusts for opcode size
1488 itself, to be consistent with the disassembler, which must do
1490 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
1493 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1494 Returns BFD_RELOC_NONE if no reloc type can be found.
1495 *FIXP may be modified if desired. */
1497 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1498 #define MAP(n) case MEP_OPERAND_##n: return BFD_RELOC_MEP_##n;
1500 #define MAP(n) case MEP_OPERAND_/**/n: return BFD_RELOC_MEP_/**/n;
1503 bfd_reloc_code_real_type
1504 md_cgen_lookup_reloc (const CGEN_INSN
*insn ATTRIBUTE_UNUSED
,
1505 const CGEN_OPERAND
*operand
,
1508 enum bfd_reloc_code_real reloc
= fixP
->fx_cgen
.opinfo
;
1509 static char printed
[MEP_OPERAND_MAX
] = { 0 };
1511 /* If there's a reloc here, it's because the parser saw a %foo() and
1512 is giving us the correct reloc to use, or because we converted to
1513 a different size reloc below and want to avoid "converting" more
1515 if (reloc
&& reloc
!= BFD_RELOC_NONE
)
1518 switch (operand
->type
)
1520 MAP (PCREL8A2
); /* beqz */
1521 MAP (PCREL12A2
); /* bsr16 */
1522 MAP (PCREL17A2
); /* beqi */
1523 MAP (PCREL24A2
); /* bsr24 */
1524 MAP (PCABS24A2
); /* jmp */
1525 MAP (UIMM24
); /* mov */
1526 MAP (ADDR24A4
); /* sw/lw */
1528 /* The rest of the relocs should be generated by the parser,
1529 for things such as %tprel(), etc. */
1530 case MEP_OPERAND_SIMM16
:
1531 #ifdef OBJ_COMPLEX_RELC
1532 /* coalescing this into RELOC_MEP_16 is actually a bug,
1533 since it's a signed operand. let the relc code handle it. */
1534 return BFD_RELOC_RELC
;
1537 case MEP_OPERAND_UIMM16
:
1538 case MEP_OPERAND_SDISP16
:
1539 case MEP_OPERAND_CODE16
:
1540 fixP
->fx_where
+= 2;
1541 /* to avoid doing the above add twice */
1542 fixP
->fx_cgen
.opinfo
= BFD_RELOC_MEP_16
;
1543 return BFD_RELOC_MEP_16
;
1546 #ifdef OBJ_COMPLEX_RELC
1547 /* this is not an error, yet.
1548 pass it to the linker. */
1549 return BFD_RELOC_RELC
;
1551 if (printed
[operand
->type
])
1552 return BFD_RELOC_NONE
;
1553 printed
[operand
->type
] = 1;
1555 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1556 _("Don't know how to relocate plain operands of type %s"),
1559 /* Print some helpful hints for the user. */
1560 switch (operand
->type
)
1562 case MEP_OPERAND_UDISP7
:
1563 case MEP_OPERAND_UDISP7A2
:
1564 case MEP_OPERAND_UDISP7A4
:
1565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1566 _("Perhaps you are missing %%tpoff()?"));
1571 return BFD_RELOC_NONE
;
1575 /* Called while parsing an instruction to create a fixup.
1576 We need to check for HI16 relocs and queue them up for later sorting. */
1579 mep_cgen_record_fixup_exp (fragS
*frag
,
1581 const CGEN_INSN
*insn
,
1583 const CGEN_OPERAND
*operand
,
1587 fixS
* fixP
= gas_cgen_record_fixup_exp (frag
, where
, insn
, length
,
1588 operand
, opinfo
, exp
);
1592 /* Return BFD reloc type from opinfo field in a fixS.
1593 It's tricky using fx_r_type in mep_frob_file because the values
1594 are BFD_RELOC_UNUSED + operand number. */
1595 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
1597 /* Sort any unmatched HI16 relocs so that they immediately precede
1598 the corresponding LO16 reloc. This is called before md_apply_fix and
1604 struct mep_hi_fixup
* l
;
1606 for (l
= mep_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1608 segment_info_type
* seginfo
;
1611 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_HI16
1612 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_LO16
);
1614 /* Check quickly whether the next fixup happens to be a matching low. */
1615 if (l
->fixp
->fx_next
!= NULL
1616 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_LO16
1617 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1618 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1621 /* Look through the fixups for this segment for a matching
1622 `low'. When we find one, move the high just in front of it.
1623 We do this in two passes. In the first pass, we try to find
1624 a unique `low'. In the second pass, we permit multiple
1625 high's relocs for a single `low'. */
1626 seginfo
= seg_info (l
->seg
);
1627 for (pass
= 0; pass
< 2; pass
++)
1633 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1635 /* Check whether this is a `low' fixup which matches l->fixp. */
1636 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_LO16
1637 && f
->fx_addsy
== l
->fixp
->fx_addsy
1638 && f
->fx_offset
== l
->fixp
->fx_offset
1641 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_HI16
)
1642 || prev
->fx_addsy
!= f
->fx_addsy
1643 || prev
->fx_offset
!= f
->fx_offset
))
1647 /* Move l->fixp before f. */
1648 for (pf
= &seginfo
->fix_root
;
1650 pf
= & (* pf
)->fx_next
)
1651 assert (* pf
!= NULL
);
1653 * pf
= l
->fixp
->fx_next
;
1655 l
->fixp
->fx_next
= f
;
1657 seginfo
->fix_root
= l
->fixp
;
1659 prev
->fx_next
= l
->fixp
;
1671 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1672 _("Unmatched high relocation"));
1677 /* See whether we need to force a relocation into the output file. */
1680 mep_force_relocation (fixS
*fixp
)
1682 if ( fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1683 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1686 /* Allow branches to global symbols to be resolved at assembly time.
1687 This is consistent with way relaxable branches are handled, since
1688 branches to both global and local symbols are relaxed. It also
1689 corresponds to the assumptions made in md_pcrel_from_section. */
1690 return S_FORCE_RELOC (fixp
->fx_addsy
, !fixp
->fx_pcrel
);
1693 /* Write a value out to the object file, using the appropriate endianness. */
1696 md_number_to_chars (char *buf
, valueT val
, int n
)
1698 if (target_big_endian
)
1699 number_to_chars_bigendian (buf
, val
, n
);
1701 number_to_chars_littleendian (buf
, val
, n
);
1705 md_atof (int type
, char *litP
, int *sizeP
)
1707 return ieee_md_atof (type
, litP
, sizeP
, TRUE
);
1711 mep_fix_adjustable (fixS
*fixP
)
1713 bfd_reloc_code_real_type reloc_type
;
1715 if ((int) fixP
->fx_r_type
>= (int) BFD_RELOC_UNUSED
)
1717 const CGEN_INSN
*insn
= NULL
;
1718 int opindex
= (int) fixP
->fx_r_type
- (int) BFD_RELOC_UNUSED
;
1719 const CGEN_OPERAND
*operand
1720 = cgen_operand_lookup_by_num(gas_cgen_cpu_desc
, opindex
);
1721 reloc_type
= md_cgen_lookup_reloc (insn
, operand
, fixP
);
1724 reloc_type
= fixP
->fx_r_type
;
1726 if (fixP
->fx_addsy
== NULL
)
1729 /* Prevent all adjustments to global symbols. */
1730 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
1733 if (S_IS_WEAK (fixP
->fx_addsy
))
1736 /* We need the symbol name for the VTABLE entries */
1737 if (reloc_type
== BFD_RELOC_VTABLE_INHERIT
1738 || reloc_type
== BFD_RELOC_VTABLE_ENTRY
)
1745 mep_elf_section_letter (int letter
, char **ptrmsg
)
1748 return SHF_MEP_VLIW
;
1750 *ptrmsg
= _("Bad .section directive: want a,v,w,x,M,S in string");
1755 mep_elf_section_flags (flagword flags
, bfd_vma attr
, int type ATTRIBUTE_UNUSED
)
1757 if (attr
& SHF_MEP_VLIW
)
1758 flags
|= SEC_MEP_VLIW
;
1762 /* In vliw mode, the default section is .vtext. We have to be able
1763 to switch into .vtext using only the .vtext directive. */
1766 mep_vtext_section (void)
1768 static segT vtext_section
;
1770 if (! vtext_section
)
1772 flagword applicable
= bfd_applicable_section_flags (stdoutput
);
1773 vtext_section
= subseg_new (VTEXT_SECTION_NAME
, 0);
1774 bfd_set_section_flags (stdoutput
, vtext_section
,
1775 applicable
& (SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
1776 | SEC_CODE
| SEC_READONLY
1780 return vtext_section
;
1784 mep_s_vtext (int ignore ATTRIBUTE_UNUSED
)
1788 /* Record previous_section and previous_subsection. */
1789 obj_elf_section_change_hook ();
1791 temp
= get_absolute_expression ();
1792 subseg_set (mep_vtext_section (), (subsegT
) temp
);
1793 demand_empty_rest_of_line ();
1797 mep_switch_to_core_mode (int dummy ATTRIBUTE_UNUSED
)
1799 mep_process_saved_insns ();
1805 mep_switch_to_vliw_mode (int dummy ATTRIBUTE_UNUSED
)
1808 as_bad (_(".vliw unavailable when VLIW is disabled."));
1810 /* Switch into .vtext here too. */
1811 /* mep_s_vtext(); */
1814 /* This is an undocumented pseudo-op used to disable gas's
1815 "disabled_registers" check. Used for code which checks for those
1816 registers at runtime. */
1818 mep_noregerr (int i ATTRIBUTE_UNUSED
)
1820 allow_disabled_registers
= 1;
1823 /* mep_unrecognized_line: This is called when a line that can't be parsed
1824 is encountered. We use it to check for a leading '+' sign which indicates
1825 that the current instruction is a coprocessor instruction that is to be
1826 parallelized with a previous core insn. This function accepts the '+' and
1827 rejects all other characters that might indicate garbage at the beginning
1828 of the line. The '+' character gets lost as the calling loop continues,
1829 so we need to indicate that we saw it. */
1832 mep_unrecognized_line (int ch
)
1838 return 1; /* '+' indicates an instruction to be parallelized. */
1840 return 0; /* If it's not a '+', the line can't be parsed. */
1847 /* Take care of any insns left to be parallelized when the file ends.
1848 This is mainly here to handle the case where the file ends with an
1849 insn preceeded by a + or the file ends unexpectedly. */
1851 mep_process_saved_insns ();
1855 mep_flush_pending_output (void)
1859 mep_process_saved_insns ();