1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
116 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* The ABI to use. */
135 /* MIPS ABI we are using for this output file. */
136 static enum mips_abi_level mips_abi
= NO_ABI
;
138 /* Whether or not we have code that can call pic code. */
139 int mips_abicalls
= FALSE
;
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Enabled Application Specific Extensions (ASEs). These are set to -1
152 if they have not been initialized. Changed by `.set <asename>', by
153 command line options, and based on the default architecture. */
156 /* Whether we are assembling for the mips16 processor. 0 if we are
157 not, 1 if we are, and -1 if the value has not been initialized.
158 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
159 -nomips16 command line options, and the default CPU. */
161 /* Non-zero if we should not reorder instructions. Changed by `.set
162 reorder' and `.set noreorder'. */
164 /* Non-zero if we should not permit the $at ($1) register to be used
165 in instructions. Changed by `.set at' and `.set noat'. */
167 /* Non-zero if we should warn when a macro instruction expands into
168 more than one machine instruction. Changed by `.set nomacro' and
170 int warn_about_macros
;
171 /* Non-zero if we should not move instructions. Changed by `.set
172 move', `.set volatile', `.set nomove', and `.set novolatile'. */
174 /* Non-zero if we should not optimize branches by moving the target
175 of the branch into the delay slot. Actually, we don't perform
176 this optimization anyhow. Changed by `.set bopt' and `.set
179 /* Non-zero if we should not autoextend mips16 instructions.
180 Changed by `.set autoextend' and `.set noautoextend'. */
182 /* Restrict general purpose registers and floating point registers
183 to 32 bit. This is initially determined when -mgp32 or -mfp32
184 is passed but can changed if the assembler code uses .set mipsN. */
187 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
188 command line option, and the default CPU. */
192 /* True if -mgp32 was passed. */
193 static int file_mips_gp32
= -1;
195 /* True if -mfp32 was passed. */
196 static int file_mips_fp32
= -1;
198 /* This is the struct we use to hold the current set of options. Note
199 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
200 -1 to indicate that they have not been initialized. */
202 static struct mips_set_options mips_opts
=
204 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
207 /* These variables are filled in with the masks of registers used.
208 The object format code reads them and puts them in the appropriate
210 unsigned long mips_gprmask
;
211 unsigned long mips_cprmask
[4];
213 /* MIPS ISA we are using for this output file. */
214 static int file_mips_isa
= ISA_UNKNOWN
;
216 /* True if -mips16 was passed or implied by arguments passed on the
217 command line (e.g., by -march). */
218 static int file_ase_mips16
;
220 /* True if -mips3d was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222 static int file_ase_mips3d
;
224 /* True if -mdmx was passed or implied by arguments passed on the
225 command line (e.g., by -march). */
226 static int file_ase_mdmx
;
228 /* The argument of the -march= flag. The architecture we are assembling. */
229 static int file_mips_arch
= CPU_UNKNOWN
;
230 static const char *mips_arch_string
;
232 /* The argument of the -mtune= flag. The architecture for which we
234 static int mips_tune
= CPU_UNKNOWN
;
235 static const char *mips_tune_string
;
237 /* True when generating 32-bit code for a 64-bit processor. */
238 static int mips_32bitmode
= 0;
240 /* True if the given ABI requires 32-bit registers. */
241 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
243 /* Likewise 64-bit registers. */
244 #define ABI_NEEDS_64BIT_REGS(ABI) \
246 || (ABI) == N64_ABI \
249 /* Return true if ISA supports 64 bit gp register instructions. */
250 #define ISA_HAS_64BIT_REGS(ISA) ( \
252 || (ISA) == ISA_MIPS4 \
253 || (ISA) == ISA_MIPS5 \
254 || (ISA) == ISA_MIPS64 \
255 || (ISA) == ISA_MIPS64R2 \
258 /* Return true if ISA supports 64-bit right rotate (dror et al.)
260 #define ISA_HAS_DROR(ISA) ( \
261 (ISA) == ISA_MIPS64R2 \
264 /* Return true if ISA supports 32-bit right rotate (ror et al.)
266 #define ISA_HAS_ROR(ISA) ( \
267 (ISA) == ISA_MIPS32R2 \
268 || (ISA) == ISA_MIPS64R2 \
271 #define HAVE_32BIT_GPRS \
272 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
274 #define HAVE_32BIT_FPRS \
275 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
277 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
278 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
280 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
282 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
284 /* We can only have 64bit addresses if the object file format
286 #define HAVE_32BIT_ADDRESSES \
288 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
289 || ! HAVE_64BIT_OBJECTS) \
290 && mips_pic != EMBEDDED_PIC))
292 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
294 /* Addresses are loaded in different ways, depending on the address size
295 in use. The n32 ABI Documentation also mandates the use of additions
296 with overflow checking, but existing implementations don't follow it. */
297 #define ADDRESS_ADD_INSN \
298 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
300 #define ADDRESS_ADDI_INSN \
301 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
303 #define ADDRESS_LOAD_INSN \
304 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
306 #define ADDRESS_STORE_INSN \
307 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
309 /* Return true if the given CPU supports the MIPS16 ASE. */
310 #define CPU_HAS_MIPS16(cpu) \
311 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
312 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
314 /* Return true if the given CPU supports the MIPS3D ASE. */
315 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
318 /* Return true if the given CPU supports the MDMX ASE. */
319 #define CPU_HAS_MDMX(cpu) (FALSE \
322 /* True if CPU has a dror instruction. */
323 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
325 /* True if CPU has a ror instruction. */
326 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
328 /* Whether the processor uses hardware interlocks to protect
329 reads from the HI and LO registers, and thus does not
330 require nops to be inserted. */
332 #define hilo_interlocks (mips_opts.arch == CPU_R4010 \
333 || mips_opts.arch == CPU_VR5500 \
334 || mips_opts.arch == CPU_RM7000 \
335 || mips_opts.arch == CPU_SB1 \
338 /* Whether the processor uses hardware interlocks to protect reads
339 from the GPRs after they are loaded from memory, and thus does not
340 require nops to be inserted. This applies to instructions marked
341 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
343 #define gpr_interlocks \
344 (mips_opts.isa != ISA_MIPS1 \
345 || mips_opts.arch == CPU_VR5400 \
346 || mips_opts.arch == CPU_VR5500 \
347 || mips_opts.arch == CPU_R3900)
349 /* Whether the processor uses hardware interlocks to avoid delays
350 required by coprocessor instructions, and thus does not require
351 nops to be inserted. This applies to instructions marked
352 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
353 between instructions marked INSN_WRITE_COND_CODE and ones marked
354 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
355 levels I, II, and III. */
356 /* Itbl support may require additional care here. */
357 #define cop_interlocks \
358 ((mips_opts.isa != ISA_MIPS1 \
359 && mips_opts.isa != ISA_MIPS2 \
360 && mips_opts.isa != ISA_MIPS3) \
361 || mips_opts.arch == CPU_R4300 \
362 || mips_opts.arch == CPU_VR5400 \
363 || mips_opts.arch == CPU_VR5500 \
364 || mips_opts.arch == CPU_SB1 \
367 /* Whether the processor uses hardware interlocks to protect reads
368 from coprocessor registers after they are loaded from memory, and
369 thus does not require nops to be inserted. This applies to
370 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
371 requires at MIPS ISA level I. */
372 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
374 /* Is this a mfhi or mflo instruction? */
375 #define MF_HILO_INSN(PINFO) \
376 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
378 /* MIPS PIC level. */
380 enum mips_pic_level mips_pic
;
382 /* Warn about all NOPS that the assembler generates. */
383 static int warn_nops
= 0;
385 /* 1 if we should generate 32 bit offsets from the $gp register in
386 SVR4_PIC mode. Currently has no meaning in other modes. */
387 static int mips_big_got
= 0;
389 /* 1 if trap instructions should used for overflow rather than break
391 static int mips_trap
= 0;
393 /* 1 if double width floating point constants should not be constructed
394 by assembling two single width halves into two single width floating
395 point registers which just happen to alias the double width destination
396 register. On some architectures this aliasing can be disabled by a bit
397 in the status register, and the setting of this bit cannot be determined
398 automatically at assemble time. */
399 static int mips_disable_float_construction
;
401 /* Non-zero if any .set noreorder directives were used. */
403 static int mips_any_noreorder
;
405 /* Non-zero if nops should be inserted when the register referenced in
406 an mfhi/mflo instruction is read in the next two instructions. */
407 static int mips_7000_hilo_fix
;
409 /* The size of the small data section. */
410 static unsigned int g_switch_value
= 8;
411 /* Whether the -G option was used. */
412 static int g_switch_seen
= 0;
417 /* If we can determine in advance that GP optimization won't be
418 possible, we can skip the relaxation stuff that tries to produce
419 GP-relative references. This makes delay slot optimization work
422 This function can only provide a guess, but it seems to work for
423 gcc output. It needs to guess right for gcc, otherwise gcc
424 will put what it thinks is a GP-relative instruction in a branch
427 I don't know if a fix is needed for the SVR4_PIC mode. I've only
428 fixed it for the non-PIC mode. KR 95/04/07 */
429 static int nopic_need_relax (symbolS
*, int);
431 /* handle of the OPCODE hash table */
432 static struct hash_control
*op_hash
= NULL
;
434 /* The opcode hash table we use for the mips16. */
435 static struct hash_control
*mips16_op_hash
= NULL
;
437 /* This array holds the chars that always start a comment. If the
438 pre-processor is disabled, these aren't very useful */
439 const char comment_chars
[] = "#";
441 /* This array holds the chars that only start a comment at the beginning of
442 a line. If the line seems to have the form '# 123 filename'
443 .line and .file directives will appear in the pre-processed output */
444 /* Note that input_file.c hand checks for '#' at the beginning of the
445 first line of the input file. This is because the compiler outputs
446 #NO_APP at the beginning of its output. */
447 /* Also note that C style comments are always supported. */
448 const char line_comment_chars
[] = "#";
450 /* This array holds machine specific line separator characters. */
451 const char line_separator_chars
[] = ";";
453 /* Chars that can be used to separate mant from exp in floating point nums */
454 const char EXP_CHARS
[] = "eE";
456 /* Chars that mean this number is a floating point constant */
459 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
461 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
462 changed in read.c . Ideally it shouldn't have to know about it at all,
463 but nothing is ideal around here.
466 static char *insn_error
;
468 static int auto_align
= 1;
470 /* When outputting SVR4 PIC code, the assembler needs to know the
471 offset in the stack frame from which to restore the $gp register.
472 This is set by the .cprestore pseudo-op, and saved in this
474 static offsetT mips_cprestore_offset
= -1;
476 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
477 more optimizations, it can use a register value instead of a memory-saved
478 offset and even an other register than $gp as global pointer. */
479 static offsetT mips_cpreturn_offset
= -1;
480 static int mips_cpreturn_register
= -1;
481 static int mips_gp_register
= GP
;
482 static int mips_gprel_offset
= 0;
484 /* Whether mips_cprestore_offset has been set in the current function
485 (or whether it has already been warned about, if not). */
486 static int mips_cprestore_valid
= 0;
488 /* This is the register which holds the stack frame, as set by the
489 .frame pseudo-op. This is needed to implement .cprestore. */
490 static int mips_frame_reg
= SP
;
492 /* Whether mips_frame_reg has been set in the current function
493 (or whether it has already been warned about, if not). */
494 static int mips_frame_reg_valid
= 0;
496 /* To output NOP instructions correctly, we need to keep information
497 about the previous two instructions. */
499 /* Whether we are optimizing. The default value of 2 means to remove
500 unneeded NOPs and swap branch instructions when possible. A value
501 of 1 means to not swap branches. A value of 0 means to always
503 static int mips_optimize
= 2;
505 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
506 equivalent to seeing no -g option at all. */
507 static int mips_debug
= 0;
509 /* The previous instruction. */
510 static struct mips_cl_insn prev_insn
;
512 /* The instruction before prev_insn. */
513 static struct mips_cl_insn prev_prev_insn
;
515 /* If we don't want information for prev_insn or prev_prev_insn, we
516 point the insn_mo field at this dummy integer. */
517 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
519 /* Non-zero if prev_insn is valid. */
520 static int prev_insn_valid
;
522 /* The frag for the previous instruction. */
523 static struct frag
*prev_insn_frag
;
525 /* The offset into prev_insn_frag for the previous instruction. */
526 static long prev_insn_where
;
528 /* The reloc type for the previous instruction, if any. */
529 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
531 /* The reloc for the previous instruction, if any. */
532 static fixS
*prev_insn_fixp
[3];
534 /* Non-zero if the previous instruction was in a delay slot. */
535 static int prev_insn_is_delay_slot
;
537 /* Non-zero if the previous instruction was in a .set noreorder. */
538 static int prev_insn_unreordered
;
540 /* Non-zero if the previous instruction uses an extend opcode (if
542 static int prev_insn_extended
;
544 /* Non-zero if the previous previous instruction was in a .set
546 static int prev_prev_insn_unreordered
;
548 /* If this is set, it points to a frag holding nop instructions which
549 were inserted before the start of a noreorder section. If those
550 nops turn out to be unnecessary, the size of the frag can be
552 static fragS
*prev_nop_frag
;
554 /* The number of nop instructions we created in prev_nop_frag. */
555 static int prev_nop_frag_holds
;
557 /* The number of nop instructions that we know we need in
559 static int prev_nop_frag_required
;
561 /* The number of instructions we've seen since prev_nop_frag. */
562 static int prev_nop_frag_since
;
564 /* For ECOFF and ELF, relocations against symbols are done in two
565 parts, with a HI relocation and a LO relocation. Each relocation
566 has only 16 bits of space to store an addend. This means that in
567 order for the linker to handle carries correctly, it must be able
568 to locate both the HI and the LO relocation. This means that the
569 relocations must appear in order in the relocation table.
571 In order to implement this, we keep track of each unmatched HI
572 relocation. We then sort them so that they immediately precede the
573 corresponding LO relocation. */
578 struct mips_hi_fixup
*next
;
581 /* The section this fixup is in. */
585 /* The list of unmatched HI relocs. */
587 static struct mips_hi_fixup
*mips_hi_fixup_list
;
589 /* The frag containing the last explicit relocation operator.
590 Null if explicit relocations have not been used. */
592 static fragS
*prev_reloc_op_frag
;
594 /* Map normal MIPS register numbers to mips16 register numbers. */
596 #define X ILLEGAL_REG
597 static const int mips32_to_16_reg_map
[] =
599 X
, X
, 2, 3, 4, 5, 6, 7,
600 X
, X
, X
, X
, X
, X
, X
, X
,
601 0, 1, X
, X
, X
, X
, X
, X
,
602 X
, X
, X
, X
, X
, X
, X
, X
606 /* Map mips16 register numbers to normal MIPS register numbers. */
608 static const unsigned int mips16_to_32_reg_map
[] =
610 16, 17, 2, 3, 4, 5, 6, 7
613 static int mips_fix_4122_bugs
;
615 /* We don't relax branches by default, since this causes us to expand
616 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
617 fail to compute the offset before expanding the macro to the most
618 efficient expansion. */
620 static int mips_relax_branch
;
622 /* Since the MIPS does not have multiple forms of PC relative
623 instructions, we do not have to do relaxing as is done on other
624 platforms. However, we do have to handle GP relative addressing
625 correctly, which turns out to be a similar problem.
627 Every macro that refers to a symbol can occur in (at least) two
628 forms, one with GP relative addressing and one without. For
629 example, loading a global variable into a register generally uses
630 a macro instruction like this:
632 If i can be addressed off the GP register (this is true if it is in
633 the .sbss or .sdata section, or if it is known to be smaller than
634 the -G argument) this will generate the following instruction:
636 This instruction will use a GPREL reloc. If i can not be addressed
637 off the GP register, the following instruction sequence will be used:
640 In this case the first instruction will have a HI16 reloc, and the
641 second reloc will have a LO16 reloc. Both relocs will be against
644 The issue here is that we may not know whether i is GP addressable
645 until after we see the instruction that uses it. Therefore, we
646 want to be able to choose the final instruction sequence only at
647 the end of the assembly. This is similar to the way other
648 platforms choose the size of a PC relative instruction only at the
651 When generating position independent code we do not use GP
652 addressing in quite the same way, but the issue still arises as
653 external symbols and local symbols must be handled differently.
655 We handle these issues by actually generating both possible
656 instruction sequences. The longer one is put in a frag_var with
657 type rs_machine_dependent. We encode what to do with the frag in
658 the subtype field. We encode (1) the number of existing bytes to
659 replace, (2) the number of new bytes to use, (3) the offset from
660 the start of the existing bytes to the first reloc we must generate
661 (that is, the offset is applied from the start of the existing
662 bytes after they are replaced by the new bytes, if any), (4) the
663 offset from the start of the existing bytes to the second reloc,
664 (5) whether a third reloc is needed (the third reloc is always four
665 bytes after the second reloc), and (6) whether to warn if this
666 variant is used (this is sometimes needed if .set nomacro or .set
667 noat is in effect). All these numbers are reasonably small.
669 Generating two instruction sequences must be handled carefully to
670 ensure that delay slots are handled correctly. Fortunately, there
671 are a limited number of cases. When the second instruction
672 sequence is generated, append_insn is directed to maintain the
673 existing delay slot information, so it continues to apply to any
674 code after the second instruction sequence. This means that the
675 second instruction sequence must not impose any requirements not
676 required by the first instruction sequence.
678 These variant frags are then handled in functions called by the
679 machine independent code. md_estimate_size_before_relax returns
680 the final size of the frag. md_convert_frag sets up the final form
681 of the frag. tc_gen_reloc adjust the first reloc and adds a second
683 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
687 | (((reloc1) + 64) << 9) \
688 | (((reloc2) + 64) << 2) \
689 | ((reloc3) ? (1 << 1) : 0) \
691 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
692 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
693 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
694 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
695 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
696 #define RELAX_WARN(i) ((i) & 1)
698 /* Branch without likely bit. If label is out of range, we turn:
700 beq reg1, reg2, label
710 with the following opcode replacements:
717 bltzal <-> bgezal (with jal label instead of j label)
719 Even though keeping the delay slot instruction in the delay slot of
720 the branch would be more efficient, it would be very tricky to do
721 correctly, because we'd have to introduce a variable frag *after*
722 the delay slot instruction, and expand that instead. Let's do it
723 the easy way for now, even if the branch-not-taken case now costs
724 one additional instruction. Out-of-range branches are not supposed
725 to be common, anyway.
727 Branch likely. If label is out of range, we turn:
729 beql reg1, reg2, label
730 delay slot (annulled if branch not taken)
739 delay slot (executed only if branch taken)
742 It would be possible to generate a shorter sequence by losing the
743 likely bit, generating something like:
748 delay slot (executed only if branch taken)
760 bltzall -> bgezal (with jal label instead of j label)
761 bgezall -> bltzal (ditto)
764 but it's not clear that it would actually improve performance. */
765 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
768 | ((toofar) ? 1 : 0) \
770 | ((likely) ? 4 : 0) \
771 | ((uncond) ? 8 : 0)))
772 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
773 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
774 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
775 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
776 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
778 /* For mips16 code, we use an entirely different form of relaxation.
779 mips16 supports two versions of most instructions which take
780 immediate values: a small one which takes some small value, and a
781 larger one which takes a 16 bit value. Since branches also follow
782 this pattern, relaxing these values is required.
784 We can assemble both mips16 and normal MIPS code in a single
785 object. Therefore, we need to support this type of relaxation at
786 the same time that we support the relaxation described above. We
787 use the high bit of the subtype field to distinguish these cases.
789 The information we store for this type of relaxation is the
790 argument code found in the opcode file for this relocation, whether
791 the user explicitly requested a small or extended form, and whether
792 the relocation is in a jump or jal delay slot. That tells us the
793 size of the value, and how it should be stored. We also store
794 whether the fragment is considered to be extended or not. We also
795 store whether this is known to be a branch to a different section,
796 whether we have tried to relax this frag yet, and whether we have
797 ever extended a PC relative fragment because of a shift count. */
798 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
801 | ((small) ? 0x100 : 0) \
802 | ((ext) ? 0x200 : 0) \
803 | ((dslot) ? 0x400 : 0) \
804 | ((jal_dslot) ? 0x800 : 0))
805 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
806 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
807 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
808 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
809 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
810 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
811 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
812 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
813 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
814 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
815 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
816 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
818 /* Is the given value a sign-extended 32-bit value? */
819 #define IS_SEXT_32BIT_NUM(x) \
820 (((x) &~ (offsetT) 0x7fffffff) == 0 \
821 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
823 /* Is the given value a sign-extended 16-bit value? */
824 #define IS_SEXT_16BIT_NUM(x) \
825 (((x) &~ (offsetT) 0x7fff) == 0 \
826 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
829 /* Prototypes for static functions. */
831 #define internalError() \
832 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
834 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
836 static void append_insn
837 (char *place
, struct mips_cl_insn
*ip
, expressionS
*p
,
838 bfd_reloc_code_real_type
*r
);
839 static void mips_no_prev_insn (int);
840 static void mips16_macro_build
841 (char *, int *, expressionS
*, const char *, const char *, va_list);
842 static void load_register (int *, int, expressionS
*, int);
843 static void macro (struct mips_cl_insn
* ip
);
844 static void mips16_macro (struct mips_cl_insn
* ip
);
845 #ifdef LOSING_COMPILER
846 static void macro2 (struct mips_cl_insn
* ip
);
848 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
849 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
850 static void mips16_immed
851 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
852 unsigned long *, bfd_boolean
*, unsigned short *);
853 static size_t my_getSmallExpression
854 (expressionS
*, bfd_reloc_code_real_type
*, char *);
855 static void my_getExpression (expressionS
*, char *);
856 static void s_align (int);
857 static void s_change_sec (int);
858 static void s_change_section (int);
859 static void s_cons (int);
860 static void s_float_cons (int);
861 static void s_mips_globl (int);
862 static void s_option (int);
863 static void s_mipsset (int);
864 static void s_abicalls (int);
865 static void s_cpload (int);
866 static void s_cpsetup (int);
867 static void s_cplocal (int);
868 static void s_cprestore (int);
869 static void s_cpreturn (int);
870 static void s_gpvalue (int);
871 static void s_gpword (int);
872 static void s_gpdword (int);
873 static void s_cpadd (int);
874 static void s_insn (int);
875 static void md_obj_begin (void);
876 static void md_obj_end (void);
877 static void s_mips_ent (int);
878 static void s_mips_end (int);
879 static void s_mips_frame (int);
880 static void s_mips_mask (int reg_type
);
881 static void s_mips_stab (int);
882 static void s_mips_weakext (int);
883 static void s_mips_file (int);
884 static void s_mips_loc (int);
885 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
886 static int relaxed_branch_length (fragS
*, asection
*, int);
887 static int validate_mips_insn (const struct mips_opcode
*);
889 /* Table and functions used to map between CPU/ISA names, and
890 ISA levels, and CPU numbers. */
894 const char *name
; /* CPU or ISA name. */
895 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
896 int isa
; /* ISA level. */
897 int cpu
; /* CPU number (default CPU if ISA). */
900 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
901 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
902 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
906 The following pseudo-ops from the Kane and Heinrich MIPS book
907 should be defined here, but are currently unsupported: .alias,
908 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
910 The following pseudo-ops from the Kane and Heinrich MIPS book are
911 specific to the type of debugging information being generated, and
912 should be defined by the object format: .aent, .begin, .bend,
913 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
916 The following pseudo-ops from the Kane and Heinrich MIPS book are
917 not MIPS CPU specific, but are also not specific to the object file
918 format. This file is probably the best place to define them, but
919 they are not currently supported: .asm0, .endr, .lab, .repeat,
922 static const pseudo_typeS mips_pseudo_table
[] =
924 /* MIPS specific pseudo-ops. */
925 {"option", s_option
, 0},
926 {"set", s_mipsset
, 0},
927 {"rdata", s_change_sec
, 'r'},
928 {"sdata", s_change_sec
, 's'},
929 {"livereg", s_ignore
, 0},
930 {"abicalls", s_abicalls
, 0},
931 {"cpload", s_cpload
, 0},
932 {"cpsetup", s_cpsetup
, 0},
933 {"cplocal", s_cplocal
, 0},
934 {"cprestore", s_cprestore
, 0},
935 {"cpreturn", s_cpreturn
, 0},
936 {"gpvalue", s_gpvalue
, 0},
937 {"gpword", s_gpword
, 0},
938 {"gpdword", s_gpdword
, 0},
939 {"cpadd", s_cpadd
, 0},
942 /* Relatively generic pseudo-ops that happen to be used on MIPS
944 {"asciiz", stringer
, 1},
945 {"bss", s_change_sec
, 'b'},
948 {"dword", s_cons
, 3},
949 {"weakext", s_mips_weakext
, 0},
951 /* These pseudo-ops are defined in read.c, but must be overridden
952 here for one reason or another. */
953 {"align", s_align
, 0},
955 {"data", s_change_sec
, 'd'},
956 {"double", s_float_cons
, 'd'},
957 {"float", s_float_cons
, 'f'},
958 {"globl", s_mips_globl
, 0},
959 {"global", s_mips_globl
, 0},
960 {"hword", s_cons
, 1},
965 {"section", s_change_section
, 0},
966 {"short", s_cons
, 1},
967 {"single", s_float_cons
, 'f'},
968 {"stabn", s_mips_stab
, 'n'},
969 {"text", s_change_sec
, 't'},
972 { "extern", ecoff_directive_extern
, 0},
977 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
979 /* These pseudo-ops should be defined by the object file format.
980 However, a.out doesn't support them, so we have versions here. */
981 {"aent", s_mips_ent
, 1},
982 {"bgnb", s_ignore
, 0},
983 {"end", s_mips_end
, 0},
984 {"endb", s_ignore
, 0},
985 {"ent", s_mips_ent
, 0},
986 {"file", s_mips_file
, 0},
987 {"fmask", s_mips_mask
, 'F'},
988 {"frame", s_mips_frame
, 0},
989 {"loc", s_mips_loc
, 0},
990 {"mask", s_mips_mask
, 'R'},
991 {"verstamp", s_ignore
, 0},
995 extern void pop_insert (const pseudo_typeS
*);
998 mips_pop_insert (void)
1000 pop_insert (mips_pseudo_table
);
1001 if (! ECOFF_DEBUGGING
)
1002 pop_insert (mips_nonecoff_pseudo_table
);
1005 /* Symbols labelling the current insn. */
1007 struct insn_label_list
1009 struct insn_label_list
*next
;
1013 static struct insn_label_list
*insn_labels
;
1014 static struct insn_label_list
*free_insn_labels
;
1016 static void mips_clear_insn_labels (void);
1019 mips_clear_insn_labels (void)
1021 register struct insn_label_list
**pl
;
1023 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1029 static char *expr_end
;
1031 /* Expressions which appear in instructions. These are set by
1034 static expressionS imm_expr
;
1035 static expressionS imm2_expr
;
1036 static expressionS offset_expr
;
1038 /* Relocs associated with imm_expr and offset_expr. */
1040 static bfd_reloc_code_real_type imm_reloc
[3]
1041 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1042 static bfd_reloc_code_real_type offset_reloc
[3]
1043 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1045 /* These are set by mips16_ip if an explicit extension is used. */
1047 static bfd_boolean mips16_small
, mips16_ext
;
1050 /* The pdr segment for per procedure frame/regmask info. Not used for
1053 static segT pdr_seg
;
1056 /* The default target format to use. */
1059 mips_target_format (void)
1061 switch (OUTPUT_FLAVOR
)
1063 case bfd_target_aout_flavour
:
1064 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
1065 case bfd_target_ecoff_flavour
:
1066 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1067 case bfd_target_coff_flavour
:
1069 case bfd_target_elf_flavour
:
1071 /* This is traditional mips. */
1072 return (target_big_endian
1073 ? (HAVE_64BIT_OBJECTS
1074 ? "elf64-tradbigmips"
1076 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1077 : (HAVE_64BIT_OBJECTS
1078 ? "elf64-tradlittlemips"
1080 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1082 return (target_big_endian
1083 ? (HAVE_64BIT_OBJECTS
1086 ? "elf32-nbigmips" : "elf32-bigmips"))
1087 : (HAVE_64BIT_OBJECTS
1088 ? "elf64-littlemips"
1090 ? "elf32-nlittlemips" : "elf32-littlemips")));
1098 /* This function is called once, at assembler startup time. It should
1099 set up all the tables, etc. that the MD part of the assembler will need. */
1104 register const char *retval
= NULL
;
1108 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1109 as_warn (_("Could not set architecture and machine"));
1111 op_hash
= hash_new ();
1113 for (i
= 0; i
< NUMOPCODES
;)
1115 const char *name
= mips_opcodes
[i
].name
;
1117 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1120 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1121 mips_opcodes
[i
].name
, retval
);
1122 /* Probably a memory allocation problem? Give up now. */
1123 as_fatal (_("Broken assembler. No assembly attempted."));
1127 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1129 if (!validate_mips_insn (&mips_opcodes
[i
]))
1134 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1137 mips16_op_hash
= hash_new ();
1140 while (i
< bfd_mips16_num_opcodes
)
1142 const char *name
= mips16_opcodes
[i
].name
;
1144 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1146 as_fatal (_("internal: can't hash `%s': %s"),
1147 mips16_opcodes
[i
].name
, retval
);
1150 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1151 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1152 != mips16_opcodes
[i
].match
))
1154 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1155 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1160 while (i
< bfd_mips16_num_opcodes
1161 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1165 as_fatal (_("Broken assembler. No assembly attempted."));
1167 /* We add all the general register names to the symbol table. This
1168 helps us detect invalid uses of them. */
1169 for (i
= 0; i
< 32; i
++)
1173 sprintf (buf
, "$%d", i
);
1174 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1175 &zero_address_frag
));
1177 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1178 &zero_address_frag
));
1179 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1180 &zero_address_frag
));
1181 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1182 &zero_address_frag
));
1183 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1184 &zero_address_frag
));
1185 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1186 &zero_address_frag
));
1187 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1188 &zero_address_frag
));
1189 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1190 &zero_address_frag
));
1191 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1192 &zero_address_frag
));
1193 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1194 &zero_address_frag
));
1196 /* If we don't add these register names to the symbol table, they
1197 may end up being added as regular symbols by operand(), and then
1198 make it to the object file as undefined in case they're not
1199 regarded as local symbols. They're local in o32, since `$' is a
1200 local symbol prefix, but not in n32 or n64. */
1201 for (i
= 0; i
< 8; i
++)
1205 sprintf (buf
, "$fcc%i", i
);
1206 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1207 &zero_address_frag
));
1210 mips_no_prev_insn (FALSE
);
1213 mips_cprmask
[0] = 0;
1214 mips_cprmask
[1] = 0;
1215 mips_cprmask
[2] = 0;
1216 mips_cprmask
[3] = 0;
1218 /* set the default alignment for the text section (2**2) */
1219 record_alignment (text_section
, 2);
1221 if (USE_GLOBAL_POINTER_OPT
)
1222 bfd_set_gp_size (stdoutput
, g_switch_value
);
1224 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1226 /* On a native system, sections must be aligned to 16 byte
1227 boundaries. When configured for an embedded ELF target, we
1229 if (strcmp (TARGET_OS
, "elf") != 0)
1231 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1232 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1233 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1236 /* Create a .reginfo section for register masks and a .mdebug
1237 section for debugging information. */
1245 subseg
= now_subseg
;
1247 /* The ABI says this section should be loaded so that the
1248 running program can access it. However, we don't load it
1249 if we are configured for an embedded target */
1250 flags
= SEC_READONLY
| SEC_DATA
;
1251 if (strcmp (TARGET_OS
, "elf") != 0)
1252 flags
|= SEC_ALLOC
| SEC_LOAD
;
1254 if (mips_abi
!= N64_ABI
)
1256 sec
= subseg_new (".reginfo", (subsegT
) 0);
1258 bfd_set_section_flags (stdoutput
, sec
, flags
);
1259 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1262 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1267 /* The 64-bit ABI uses a .MIPS.options section rather than
1268 .reginfo section. */
1269 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1270 bfd_set_section_flags (stdoutput
, sec
, flags
);
1271 bfd_set_section_alignment (stdoutput
, sec
, 3);
1274 /* Set up the option header. */
1276 Elf_Internal_Options opthdr
;
1279 opthdr
.kind
= ODK_REGINFO
;
1280 opthdr
.size
= (sizeof (Elf_External_Options
)
1281 + sizeof (Elf64_External_RegInfo
));
1284 f
= frag_more (sizeof (Elf_External_Options
));
1285 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1286 (Elf_External_Options
*) f
);
1288 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1293 if (ECOFF_DEBUGGING
)
1295 sec
= subseg_new (".mdebug", (subsegT
) 0);
1296 (void) bfd_set_section_flags (stdoutput
, sec
,
1297 SEC_HAS_CONTENTS
| SEC_READONLY
);
1298 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1301 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1303 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1304 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1305 SEC_READONLY
| SEC_RELOC
1307 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1311 subseg_set (seg
, subseg
);
1315 if (! ECOFF_DEBUGGING
)
1322 if (! ECOFF_DEBUGGING
)
1327 md_assemble (char *str
)
1329 struct mips_cl_insn insn
;
1330 bfd_reloc_code_real_type unused_reloc
[3]
1331 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1333 imm_expr
.X_op
= O_absent
;
1334 imm2_expr
.X_op
= O_absent
;
1335 offset_expr
.X_op
= O_absent
;
1336 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1337 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1338 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1339 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1340 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1341 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1343 if (mips_opts
.mips16
)
1344 mips16_ip (str
, &insn
);
1347 mips_ip (str
, &insn
);
1348 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1349 str
, insn
.insn_opcode
));
1354 as_bad ("%s `%s'", insn_error
, str
);
1358 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1360 if (mips_opts
.mips16
)
1361 mips16_macro (&insn
);
1367 if (imm_expr
.X_op
!= O_absent
)
1368 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
);
1369 else if (offset_expr
.X_op
!= O_absent
)
1370 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
);
1372 append_insn (NULL
, &insn
, NULL
, unused_reloc
);
1376 /* Return true if the given relocation might need a matching %lo().
1377 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1378 applied to local symbols. */
1380 static inline bfd_boolean
1381 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1383 return (reloc
== BFD_RELOC_HI16_S
1384 || reloc
== BFD_RELOC_MIPS_GOT16
);
1387 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1390 static inline bfd_boolean
1391 fixup_has_matching_lo_p (fixS
*fixp
)
1393 return (fixp
->fx_next
!= NULL
1394 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1395 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1396 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1399 /* See whether instruction IP reads register REG. CLASS is the type
1403 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1404 enum mips_regclass
class)
1406 if (class == MIPS16_REG
)
1408 assert (mips_opts
.mips16
);
1409 reg
= mips16_to_32_reg_map
[reg
];
1410 class = MIPS_GR_REG
;
1413 /* Don't report on general register ZERO, since it never changes. */
1414 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1417 if (class == MIPS_FP_REG
)
1419 assert (! mips_opts
.mips16
);
1420 /* If we are called with either $f0 or $f1, we must check $f0.
1421 This is not optimal, because it will introduce an unnecessary
1422 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1423 need to distinguish reading both $f0 and $f1 or just one of
1424 them. Note that we don't have to check the other way,
1425 because there is no instruction that sets both $f0 and $f1
1426 and requires a delay. */
1427 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1428 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1429 == (reg
&~ (unsigned) 1)))
1431 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1432 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1433 == (reg
&~ (unsigned) 1)))
1436 else if (! mips_opts
.mips16
)
1438 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1439 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1441 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1442 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1447 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1448 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1449 & MIPS16OP_MASK_RX
)]
1452 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1453 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1454 & MIPS16OP_MASK_RY
)]
1457 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1458 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1459 & MIPS16OP_MASK_MOVE32Z
)]
1462 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1464 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1466 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1468 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1469 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1470 & MIPS16OP_MASK_REGR32
) == reg
)
1477 /* This function returns true if modifying a register requires a
1481 reg_needs_delay (unsigned int reg
)
1483 unsigned long prev_pinfo
;
1485 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1486 if (! mips_opts
.noreorder
1487 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1488 && ! gpr_interlocks
)
1489 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1490 && ! cop_interlocks
)))
1492 /* A load from a coprocessor or from memory. All load delays
1493 delay the use of general register rt for one instruction. */
1494 /* Itbl support may require additional care here. */
1495 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1496 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1503 /* Mark instruction labels in mips16 mode. This permits the linker to
1504 handle them specially, such as generating jalx instructions when
1505 needed. We also make them odd for the duration of the assembly, in
1506 order to generate the right sort of code. We will make them even
1507 in the adjust_symtab routine, while leaving them marked. This is
1508 convenient for the debugger and the disassembler. The linker knows
1509 to make them odd again. */
1512 mips16_mark_labels (void)
1514 if (mips_opts
.mips16
)
1516 struct insn_label_list
*l
;
1519 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1522 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1523 S_SET_OTHER (l
->label
, STO_MIPS16
);
1525 val
= S_GET_VALUE (l
->label
);
1527 S_SET_VALUE (l
->label
, val
+ 1);
1532 /* Output an instruction. PLACE is where to put the instruction; if
1533 it is NULL, this uses frag_more to get room. IP is the instruction
1534 information. ADDRESS_EXPR is an operand of the instruction to be
1535 used with RELOC_TYPE. */
1538 append_insn (char *place
, struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1539 bfd_reloc_code_real_type
*reloc_type
)
1541 register unsigned long prev_pinfo
, pinfo
;
1545 bfd_boolean force_new_frag
= FALSE
;
1547 /* Mark instruction labels in mips16 mode. */
1548 mips16_mark_labels ();
1550 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1551 pinfo
= ip
->insn_mo
->pinfo
;
1553 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1557 /* If the previous insn required any delay slots, see if we need
1558 to insert a NOP or two. There are eight kinds of possible
1559 hazards, of which an instruction can have at most one type.
1560 (1) a load from memory delay
1561 (2) a load from a coprocessor delay
1562 (3) an unconditional branch delay
1563 (4) a conditional branch delay
1564 (5) a move to coprocessor register delay
1565 (6) a load coprocessor register from memory delay
1566 (7) a coprocessor condition code delay
1567 (8) a HI/LO special register delay
1569 There are a lot of optimizations we could do that we don't.
1570 In particular, we do not, in general, reorder instructions.
1571 If you use gcc with optimization, it will reorder
1572 instructions and generally do much more optimization then we
1573 do here; repeating all that work in the assembler would only
1574 benefit hand written assembly code, and does not seem worth
1577 /* This is how a NOP is emitted. */
1578 #define emit_nop() \
1580 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1581 : md_number_to_chars (frag_more (4), 0, 4))
1583 /* The previous insn might require a delay slot, depending upon
1584 the contents of the current insn. */
1585 if (! mips_opts
.mips16
1586 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1587 && ! gpr_interlocks
)
1588 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1589 && ! cop_interlocks
)))
1591 /* A load from a coprocessor or from memory. All load
1592 delays delay the use of general register rt for one
1594 /* Itbl support may require additional care here. */
1595 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1596 if (mips_optimize
== 0
1597 || insn_uses_reg (ip
,
1598 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1603 else if (! mips_opts
.mips16
1604 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1605 && ! cop_interlocks
)
1606 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1607 && ! cop_mem_interlocks
)))
1609 /* A generic coprocessor delay. The previous instruction
1610 modified a coprocessor general or control register. If
1611 it modified a control register, we need to avoid any
1612 coprocessor instruction (this is probably not always
1613 required, but it sometimes is). If it modified a general
1614 register, we avoid using that register.
1616 This case is not handled very well. There is no special
1617 knowledge of CP0 handling, and the coprocessors other
1618 than the floating point unit are not distinguished at
1620 /* Itbl support may require additional care here. FIXME!
1621 Need to modify this to include knowledge about
1622 user specified delays! */
1623 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1625 if (mips_optimize
== 0
1626 || insn_uses_reg (ip
,
1627 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1632 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1634 if (mips_optimize
== 0
1635 || insn_uses_reg (ip
,
1636 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1643 /* We don't know exactly what the previous instruction
1644 does. If the current instruction uses a coprocessor
1645 register, we must insert a NOP. If previous
1646 instruction may set the condition codes, and the
1647 current instruction uses them, we must insert two
1649 /* Itbl support may require additional care here. */
1650 if (mips_optimize
== 0
1651 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1652 && (pinfo
& INSN_READ_COND_CODE
)))
1654 else if (pinfo
& INSN_COP
)
1658 else if (! mips_opts
.mips16
1659 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1660 && ! cop_interlocks
)
1662 /* The previous instruction sets the coprocessor condition
1663 codes, but does not require a general coprocessor delay
1664 (this means it is a floating point comparison
1665 instruction). If this instruction uses the condition
1666 codes, we need to insert a single NOP. */
1667 /* Itbl support may require additional care here. */
1668 if (mips_optimize
== 0
1669 || (pinfo
& INSN_READ_COND_CODE
))
1673 /* If we're fixing up mfhi/mflo for the r7000 and the
1674 previous insn was an mfhi/mflo and the current insn
1675 reads the register that the mfhi/mflo wrote to, then
1678 else if (mips_7000_hilo_fix
1679 && MF_HILO_INSN (prev_pinfo
)
1680 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1687 /* If we're fixing up mfhi/mflo for the r7000 and the
1688 2nd previous insn was an mfhi/mflo and the current insn
1689 reads the register that the mfhi/mflo wrote to, then
1692 else if (mips_7000_hilo_fix
1693 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1694 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1702 else if (prev_pinfo
& INSN_READ_LO
)
1704 /* The previous instruction reads the LO register; if the
1705 current instruction writes to the LO register, we must
1706 insert two NOPS. Some newer processors have interlocks.
1707 Also the tx39's multiply instructions can be executed
1708 immediately after a read from HI/LO (without the delay),
1709 though the tx39's divide insns still do require the
1711 if (! (hilo_interlocks
1712 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1713 && (mips_optimize
== 0
1714 || (pinfo
& INSN_WRITE_LO
)))
1716 /* Most mips16 branch insns don't have a delay slot.
1717 If a read from LO is immediately followed by a branch
1718 to a write to LO we have a read followed by a write
1719 less than 2 insns away. We assume the target of
1720 a branch might be a write to LO, and insert a nop
1721 between a read and an immediately following branch. */
1722 else if (mips_opts
.mips16
1723 && (mips_optimize
== 0
1724 || (pinfo
& MIPS16_INSN_BRANCH
)))
1727 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1729 /* The previous instruction reads the HI register; if the
1730 current instruction writes to the HI register, we must
1731 insert a NOP. Some newer processors have interlocks.
1732 Also the note tx39's multiply above. */
1733 if (! (hilo_interlocks
1734 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1735 && (mips_optimize
== 0
1736 || (pinfo
& INSN_WRITE_HI
)))
1738 /* Most mips16 branch insns don't have a delay slot.
1739 If a read from HI is immediately followed by a branch
1740 to a write to HI we have a read followed by a write
1741 less than 2 insns away. We assume the target of
1742 a branch might be a write to HI, and insert a nop
1743 between a read and an immediately following branch. */
1744 else if (mips_opts
.mips16
1745 && (mips_optimize
== 0
1746 || (pinfo
& MIPS16_INSN_BRANCH
)))
1750 /* If the previous instruction was in a noreorder section, then
1751 we don't want to insert the nop after all. */
1752 /* Itbl support may require additional care here. */
1753 if (prev_insn_unreordered
)
1756 /* There are two cases which require two intervening
1757 instructions: 1) setting the condition codes using a move to
1758 coprocessor instruction which requires a general coprocessor
1759 delay and then reading the condition codes 2) reading the HI
1760 or LO register and then writing to it (except on processors
1761 which have interlocks). If we are not already emitting a NOP
1762 instruction, we must check for these cases compared to the
1763 instruction previous to the previous instruction. */
1764 if ((! mips_opts
.mips16
1765 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1766 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1767 && (pinfo
& INSN_READ_COND_CODE
)
1768 && ! cop_interlocks
)
1769 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1770 && (pinfo
& INSN_WRITE_LO
)
1771 && ! (hilo_interlocks
1772 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1773 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1774 && (pinfo
& INSN_WRITE_HI
)
1775 && ! (hilo_interlocks
1776 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1781 if (prev_prev_insn_unreordered
)
1784 if (prev_prev_nop
&& nops
== 0)
1787 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
1789 /* We're out of bits in pinfo, so we must resort to string
1790 ops here. Shortcuts are selected based on opcodes being
1791 limited to the VR4122 instruction set. */
1793 const char *pn
= prev_insn
.insn_mo
->name
;
1794 const char *tn
= ip
->insn_mo
->name
;
1795 if (strncmp(pn
, "macc", 4) == 0
1796 || strncmp(pn
, "dmacc", 5) == 0)
1798 /* Errata 21 - [D]DIV[U] after [D]MACC */
1799 if (strstr (tn
, "div"))
1804 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1805 if (pn
[0] == 'd' /* dmacc */
1806 && (strncmp(tn
, "dmult", 5) == 0
1807 || strncmp(tn
, "dmacc", 5) == 0))
1812 /* Errata 24 - MT{LO,HI} after [D]MACC */
1813 if (strcmp (tn
, "mtlo") == 0
1814 || strcmp (tn
, "mthi") == 0)
1820 else if (strncmp(pn
, "dmult", 5) == 0
1821 && (strncmp(tn
, "dmult", 5) == 0
1822 || strncmp(tn
, "dmacc", 5) == 0))
1824 /* Here is the rest of errata 23. */
1827 if (nops
< min_nops
)
1831 /* If we are being given a nop instruction, don't bother with
1832 one of the nops we would otherwise output. This will only
1833 happen when a nop instruction is used with mips_optimize set
1836 && ! mips_opts
.noreorder
1837 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1840 /* Now emit the right number of NOP instructions. */
1841 if (nops
> 0 && ! mips_opts
.noreorder
)
1844 unsigned long old_frag_offset
;
1846 struct insn_label_list
*l
;
1848 old_frag
= frag_now
;
1849 old_frag_offset
= frag_now_fix ();
1851 for (i
= 0; i
< nops
; i
++)
1856 listing_prev_line ();
1857 /* We may be at the start of a variant frag. In case we
1858 are, make sure there is enough space for the frag
1859 after the frags created by listing_prev_line. The
1860 argument to frag_grow here must be at least as large
1861 as the argument to all other calls to frag_grow in
1862 this file. We don't have to worry about being in the
1863 middle of a variant frag, because the variants insert
1864 all needed nop instructions themselves. */
1868 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1872 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1873 symbol_set_frag (l
->label
, frag_now
);
1874 val
= (valueT
) frag_now_fix ();
1875 /* mips16 text labels are stored as odd. */
1876 if (mips_opts
.mips16
)
1878 S_SET_VALUE (l
->label
, val
);
1881 #ifndef NO_ECOFF_DEBUGGING
1882 if (ECOFF_DEBUGGING
)
1883 ecoff_fix_loc (old_frag
, old_frag_offset
);
1886 else if (prev_nop_frag
!= NULL
)
1888 /* We have a frag holding nops we may be able to remove. If
1889 we don't need any nops, we can decrease the size of
1890 prev_nop_frag by the size of one instruction. If we do
1891 need some nops, we count them in prev_nops_required. */
1892 if (prev_nop_frag_since
== 0)
1896 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1897 --prev_nop_frag_holds
;
1900 prev_nop_frag_required
+= nops
;
1904 if (prev_prev_nop
== 0)
1906 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1907 --prev_nop_frag_holds
;
1910 ++prev_nop_frag_required
;
1913 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1914 prev_nop_frag
= NULL
;
1916 ++prev_nop_frag_since
;
1918 /* Sanity check: by the time we reach the second instruction
1919 after prev_nop_frag, we should have used up all the nops
1920 one way or another. */
1921 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1927 && *reloc_type
== BFD_RELOC_16_PCREL_S2
1928 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
1929 || pinfo
& INSN_COND_BRANCH_LIKELY
)
1930 && mips_relax_branch
1931 /* Don't try branch relaxation within .set nomacro, or within
1932 .set noat if we use $at for PIC computations. If it turns
1933 out that the branch was out-of-range, we'll get an error. */
1934 && !mips_opts
.warn_about_macros
1935 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
1936 && !mips_opts
.mips16
)
1938 f
= frag_var (rs_machine_dependent
,
1939 relaxed_branch_length
1941 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
1942 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
1944 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
1945 pinfo
& INSN_COND_BRANCH_LIKELY
,
1946 pinfo
& INSN_WRITE_GPR_31
,
1948 address_expr
->X_add_symbol
,
1949 address_expr
->X_add_number
,
1951 *reloc_type
= BFD_RELOC_UNUSED
;
1953 else if (*reloc_type
> BFD_RELOC_UNUSED
)
1955 /* We need to set up a variant frag. */
1956 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1957 f
= frag_var (rs_machine_dependent
, 4, 0,
1958 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
1959 mips16_small
, mips16_ext
,
1961 & INSN_UNCOND_BRANCH_DELAY
),
1962 (*prev_insn_reloc_type
1963 == BFD_RELOC_MIPS16_JMP
)),
1964 make_expr_symbol (address_expr
), 0, NULL
);
1966 else if (place
!= NULL
)
1968 else if (mips_opts
.mips16
1970 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1972 /* Make sure there is enough room to swap this instruction with
1973 a following jump instruction. */
1979 if (mips_opts
.mips16
1980 && mips_opts
.noreorder
1981 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1982 as_warn (_("extended instruction in delay slot"));
1987 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
1988 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
1990 if (address_expr
->X_op
== O_constant
)
1994 switch (*reloc_type
)
1997 ip
->insn_opcode
|= address_expr
->X_add_number
;
2000 case BFD_RELOC_MIPS_HIGHEST
:
2001 tmp
= (address_expr
->X_add_number
2002 + ((valueT
) 0x8000 << 32) + 0x80008000) >> 16;
2004 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2007 case BFD_RELOC_MIPS_HIGHER
:
2008 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2009 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2012 case BFD_RELOC_HI16_S
:
2013 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2017 case BFD_RELOC_HI16
:
2018 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2021 case BFD_RELOC_LO16
:
2022 case BFD_RELOC_MIPS_GOT_DISP
:
2023 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2026 case BFD_RELOC_MIPS_JMP
:
2027 if ((address_expr
->X_add_number
& 3) != 0)
2028 as_bad (_("jump to misaligned address (0x%lx)"),
2029 (unsigned long) address_expr
->X_add_number
);
2030 if (address_expr
->X_add_number
& ~0xfffffff)
2031 as_bad (_("jump address range overflow (0x%lx)"),
2032 (unsigned long) address_expr
->X_add_number
);
2033 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2036 case BFD_RELOC_MIPS16_JMP
:
2037 if ((address_expr
->X_add_number
& 3) != 0)
2038 as_bad (_("jump to misaligned address (0x%lx)"),
2039 (unsigned long) address_expr
->X_add_number
);
2040 if (address_expr
->X_add_number
& ~0xfffffff)
2041 as_bad (_("jump address range overflow (0x%lx)"),
2042 (unsigned long) address_expr
->X_add_number
);
2044 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2045 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2046 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2049 case BFD_RELOC_16_PCREL_S2
:
2059 /* Don't generate a reloc if we are writing into a variant frag. */
2062 reloc_howto_type
*howto
;
2065 /* In a compound relocation, it is the final (outermost)
2066 operator that determines the relocated field. */
2067 for (i
= 1; i
< 3; i
++)
2068 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2071 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2072 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2073 bfd_get_reloc_size(howto
),
2075 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2078 /* These relocations can have an addend that won't fit in
2079 4 octets for 64bit assembly. */
2081 && ! howto
->partial_inplace
2082 && (reloc_type
[0] == BFD_RELOC_16
2083 || reloc_type
[0] == BFD_RELOC_32
2084 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2085 || reloc_type
[0] == BFD_RELOC_HI16_S
2086 || reloc_type
[0] == BFD_RELOC_LO16
2087 || reloc_type
[0] == BFD_RELOC_GPREL16
2088 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2089 || reloc_type
[0] == BFD_RELOC_GPREL32
2090 || reloc_type
[0] == BFD_RELOC_64
2091 || reloc_type
[0] == BFD_RELOC_CTOR
2092 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2093 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2094 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2095 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2096 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2097 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
))
2098 fixp
[0]->fx_no_overflow
= 1;
2100 if (reloc_needs_lo_p (*reloc_type
))
2102 struct mips_hi_fixup
*hi_fixup
;
2104 /* Reuse the last entry if it already has a matching %lo. */
2105 hi_fixup
= mips_hi_fixup_list
;
2107 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2109 hi_fixup
= ((struct mips_hi_fixup
*)
2110 xmalloc (sizeof (struct mips_hi_fixup
)));
2111 hi_fixup
->next
= mips_hi_fixup_list
;
2112 mips_hi_fixup_list
= hi_fixup
;
2114 hi_fixup
->fixp
= fixp
[0];
2115 hi_fixup
->seg
= now_seg
;
2118 /* Add fixups for the second and third relocations, if given.
2119 Note that the ABI allows the second relocation to be
2120 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2121 moment we only use RSS_UNDEF, but we could add support
2122 for the others if it ever becomes necessary. */
2123 for (i
= 1; i
< 3; i
++)
2124 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2126 address_expr
->X_op
= O_absent
;
2127 address_expr
->X_add_symbol
= 0;
2128 address_expr
->X_add_number
= 0;
2130 fixp
[i
] = fix_new_exp (frag_now
, fixp
[0]->fx_where
,
2131 fixp
[0]->fx_size
, address_expr
,
2132 FALSE
, reloc_type
[i
]);
2138 if (! mips_opts
.mips16
)
2140 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2142 dwarf2_emit_insn (4);
2145 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2147 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2148 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2150 dwarf2_emit_insn (4);
2157 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2160 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2162 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2166 /* Update the register mask information. */
2167 if (! mips_opts
.mips16
)
2169 if (pinfo
& INSN_WRITE_GPR_D
)
2170 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2171 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2172 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2173 if (pinfo
& INSN_READ_GPR_S
)
2174 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2175 if (pinfo
& INSN_WRITE_GPR_31
)
2176 mips_gprmask
|= 1 << RA
;
2177 if (pinfo
& INSN_WRITE_FPR_D
)
2178 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2179 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2180 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2181 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2182 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2183 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2184 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2185 if (pinfo
& INSN_COP
)
2187 /* We don't keep enough information to sort these cases out.
2188 The itbl support does keep this information however, although
2189 we currently don't support itbl fprmats as part of the cop
2190 instruction. May want to add this support in the future. */
2192 /* Never set the bit for $0, which is always zero. */
2193 mips_gprmask
&= ~1 << 0;
2197 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2198 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2199 & MIPS16OP_MASK_RX
);
2200 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2201 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2202 & MIPS16OP_MASK_RY
);
2203 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2204 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2205 & MIPS16OP_MASK_RZ
);
2206 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2207 mips_gprmask
|= 1 << TREG
;
2208 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2209 mips_gprmask
|= 1 << SP
;
2210 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2211 mips_gprmask
|= 1 << RA
;
2212 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2213 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2214 if (pinfo
& MIPS16_INSN_READ_Z
)
2215 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2216 & MIPS16OP_MASK_MOVE32Z
);
2217 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2218 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2219 & MIPS16OP_MASK_REGR32
);
2222 if (place
== NULL
&& ! mips_opts
.noreorder
)
2224 /* Filling the branch delay slot is more complex. We try to
2225 switch the branch with the previous instruction, which we can
2226 do if the previous instruction does not set up a condition
2227 that the branch tests and if the branch is not itself the
2228 target of any branch. */
2229 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2230 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2232 if (mips_optimize
< 2
2233 /* If we have seen .set volatile or .set nomove, don't
2235 || mips_opts
.nomove
!= 0
2236 /* If we had to emit any NOP instructions, then we
2237 already know we can not swap. */
2239 /* If we don't even know the previous insn, we can not
2241 || ! prev_insn_valid
2242 /* If the previous insn is already in a branch delay
2243 slot, then we can not swap. */
2244 || prev_insn_is_delay_slot
2245 /* If the previous previous insn was in a .set
2246 noreorder, we can't swap. Actually, the MIPS
2247 assembler will swap in this situation. However, gcc
2248 configured -with-gnu-as will generate code like
2254 in which we can not swap the bne and INSN. If gcc is
2255 not configured -with-gnu-as, it does not output the
2256 .set pseudo-ops. We don't have to check
2257 prev_insn_unreordered, because prev_insn_valid will
2258 be 0 in that case. We don't want to use
2259 prev_prev_insn_valid, because we do want to be able
2260 to swap at the start of a function. */
2261 || prev_prev_insn_unreordered
2262 /* If the branch is itself the target of a branch, we
2263 can not swap. We cheat on this; all we check for is
2264 whether there is a label on this instruction. If
2265 there are any branches to anything other than a
2266 label, users must use .set noreorder. */
2267 || insn_labels
!= NULL
2268 /* If the previous instruction is in a variant frag, we
2269 can not do the swap. This does not apply to the
2270 mips16, which uses variant frags for different
2272 || (! mips_opts
.mips16
2273 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2274 /* If the branch reads the condition codes, we don't
2275 even try to swap, because in the sequence
2280 we can not swap, and I don't feel like handling that
2282 || (! mips_opts
.mips16
2283 && (pinfo
& INSN_READ_COND_CODE
)
2284 && ! cop_interlocks
)
2285 /* We can not swap with an instruction that requires a
2286 delay slot, because the target of the branch might
2287 interfere with that instruction. */
2288 || (! mips_opts
.mips16
2290 /* Itbl support may require additional care here. */
2291 & (INSN_LOAD_COPROC_DELAY
2292 | INSN_COPROC_MOVE_DELAY
2293 | INSN_WRITE_COND_CODE
))
2294 && ! cop_interlocks
)
2295 || (! (hilo_interlocks
2296 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2300 || (! mips_opts
.mips16
2301 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2302 && ! gpr_interlocks
)
2303 || (! mips_opts
.mips16
2304 /* Itbl support may require additional care here. */
2305 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2306 && ! cop_mem_interlocks
)
2307 /* We can not swap with a branch instruction. */
2309 & (INSN_UNCOND_BRANCH_DELAY
2310 | INSN_COND_BRANCH_DELAY
2311 | INSN_COND_BRANCH_LIKELY
))
2312 /* We do not swap with a trap instruction, since it
2313 complicates trap handlers to have the trap
2314 instruction be in a delay slot. */
2315 || (prev_pinfo
& INSN_TRAP
)
2316 /* If the branch reads a register that the previous
2317 instruction sets, we can not swap. */
2318 || (! mips_opts
.mips16
2319 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2320 && insn_uses_reg (ip
,
2321 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2324 || (! mips_opts
.mips16
2325 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2326 && insn_uses_reg (ip
,
2327 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2330 || (mips_opts
.mips16
2331 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2332 && insn_uses_reg (ip
,
2333 ((prev_insn
.insn_opcode
2335 & MIPS16OP_MASK_RX
),
2337 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2338 && insn_uses_reg (ip
,
2339 ((prev_insn
.insn_opcode
2341 & MIPS16OP_MASK_RY
),
2343 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2344 && insn_uses_reg (ip
,
2345 ((prev_insn
.insn_opcode
2347 & MIPS16OP_MASK_RZ
),
2349 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2350 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2351 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2352 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2353 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2354 && insn_uses_reg (ip
,
2355 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2358 /* If the branch writes a register that the previous
2359 instruction sets, we can not swap (we know that
2360 branches write only to RD or to $31). */
2361 || (! mips_opts
.mips16
2362 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2363 && (((pinfo
& INSN_WRITE_GPR_D
)
2364 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2365 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2366 || ((pinfo
& INSN_WRITE_GPR_31
)
2367 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2370 || (! mips_opts
.mips16
2371 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2372 && (((pinfo
& INSN_WRITE_GPR_D
)
2373 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2374 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2375 || ((pinfo
& INSN_WRITE_GPR_31
)
2376 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2379 || (mips_opts
.mips16
2380 && (pinfo
& MIPS16_INSN_WRITE_31
)
2381 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2382 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2383 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2385 /* If the branch writes a register that the previous
2386 instruction reads, we can not swap (we know that
2387 branches only write to RD or to $31). */
2388 || (! mips_opts
.mips16
2389 && (pinfo
& INSN_WRITE_GPR_D
)
2390 && insn_uses_reg (&prev_insn
,
2391 ((ip
->insn_opcode
>> OP_SH_RD
)
2394 || (! mips_opts
.mips16
2395 && (pinfo
& INSN_WRITE_GPR_31
)
2396 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2397 || (mips_opts
.mips16
2398 && (pinfo
& MIPS16_INSN_WRITE_31
)
2399 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2400 /* If we are generating embedded PIC code, the branch
2401 might be expanded into a sequence which uses $at, so
2402 we can't swap with an instruction which reads it. */
2403 || (mips_pic
== EMBEDDED_PIC
2404 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2405 /* If the previous previous instruction has a load
2406 delay, and sets a register that the branch reads, we
2408 || (! mips_opts
.mips16
2409 /* Itbl support may require additional care here. */
2410 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2411 && ! cop_interlocks
)
2412 || ((prev_prev_insn
.insn_mo
->pinfo
2413 & INSN_LOAD_MEMORY_DELAY
)
2414 && ! gpr_interlocks
))
2415 && insn_uses_reg (ip
,
2416 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2419 /* If one instruction sets a condition code and the
2420 other one uses a condition code, we can not swap. */
2421 || ((pinfo
& INSN_READ_COND_CODE
)
2422 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2423 || ((pinfo
& INSN_WRITE_COND_CODE
)
2424 && (prev_pinfo
& INSN_READ_COND_CODE
))
2425 /* If the previous instruction uses the PC, we can not
2427 || (mips_opts
.mips16
2428 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2429 /* If the previous instruction was extended, we can not
2431 || (mips_opts
.mips16
&& prev_insn_extended
)
2432 /* If the previous instruction had a fixup in mips16
2433 mode, we can not swap. This normally means that the
2434 previous instruction was a 4 byte branch anyhow. */
2435 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2436 /* If the previous instruction is a sync, sync.l, or
2437 sync.p, we can not swap. */
2438 || (prev_pinfo
& INSN_SYNC
))
2440 /* We could do even better for unconditional branches to
2441 portions of this object file; we could pick up the
2442 instruction at the destination, put it in the delay
2443 slot, and bump the destination address. */
2445 /* Update the previous insn information. */
2446 prev_prev_insn
= *ip
;
2447 prev_insn
.insn_mo
= &dummy_opcode
;
2451 /* It looks like we can actually do the swap. */
2452 if (! mips_opts
.mips16
)
2457 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2458 memcpy (temp
, prev_f
, 4);
2459 memcpy (prev_f
, f
, 4);
2460 memcpy (f
, temp
, 4);
2461 if (prev_insn_fixp
[0])
2463 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2464 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2466 if (prev_insn_fixp
[1])
2468 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2469 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2471 if (prev_insn_fixp
[2])
2473 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2474 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2476 if (prev_insn_fixp
[0] && HAVE_NEWABI
2477 && prev_insn_frag
!= frag_now
2478 && (prev_insn_fixp
[0]->fx_r_type
2479 == BFD_RELOC_MIPS_GOT_DISP
2480 || (prev_insn_fixp
[0]->fx_r_type
2481 == BFD_RELOC_MIPS_CALL16
)))
2483 /* To avoid confusion in tc_gen_reloc, we must
2484 ensure that this does not become a variant
2486 force_new_frag
= TRUE
;
2490 fixp
[0]->fx_frag
= prev_insn_frag
;
2491 fixp
[0]->fx_where
= prev_insn_where
;
2495 fixp
[1]->fx_frag
= prev_insn_frag
;
2496 fixp
[1]->fx_where
= prev_insn_where
;
2500 fixp
[2]->fx_frag
= prev_insn_frag
;
2501 fixp
[2]->fx_where
= prev_insn_where
;
2509 assert (prev_insn_fixp
[0] == NULL
);
2510 assert (prev_insn_fixp
[1] == NULL
);
2511 assert (prev_insn_fixp
[2] == NULL
);
2512 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2513 memcpy (temp
, prev_f
, 2);
2514 memcpy (prev_f
, f
, 2);
2515 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2517 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2518 memcpy (f
, temp
, 2);
2522 memcpy (f
, f
+ 2, 2);
2523 memcpy (f
+ 2, temp
, 2);
2527 fixp
[0]->fx_frag
= prev_insn_frag
;
2528 fixp
[0]->fx_where
= prev_insn_where
;
2532 fixp
[1]->fx_frag
= prev_insn_frag
;
2533 fixp
[1]->fx_where
= prev_insn_where
;
2537 fixp
[2]->fx_frag
= prev_insn_frag
;
2538 fixp
[2]->fx_where
= prev_insn_where
;
2542 /* Update the previous insn information; leave prev_insn
2544 prev_prev_insn
= *ip
;
2546 prev_insn_is_delay_slot
= 1;
2548 /* If that was an unconditional branch, forget the previous
2549 insn information. */
2550 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2552 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2553 prev_insn
.insn_mo
= &dummy_opcode
;
2556 prev_insn_fixp
[0] = NULL
;
2557 prev_insn_fixp
[1] = NULL
;
2558 prev_insn_fixp
[2] = NULL
;
2559 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2560 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2561 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2562 prev_insn_extended
= 0;
2564 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2566 /* We don't yet optimize a branch likely. What we should do
2567 is look at the target, copy the instruction found there
2568 into the delay slot, and increment the branch to jump to
2569 the next instruction. */
2571 /* Update the previous insn information. */
2572 prev_prev_insn
= *ip
;
2573 prev_insn
.insn_mo
= &dummy_opcode
;
2574 prev_insn_fixp
[0] = NULL
;
2575 prev_insn_fixp
[1] = NULL
;
2576 prev_insn_fixp
[2] = NULL
;
2577 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2578 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2579 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2580 prev_insn_extended
= 0;
2584 /* Update the previous insn information. */
2586 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2588 prev_prev_insn
= prev_insn
;
2591 /* Any time we see a branch, we always fill the delay slot
2592 immediately; since this insn is not a branch, we know it
2593 is not in a delay slot. */
2594 prev_insn_is_delay_slot
= 0;
2596 prev_insn_fixp
[0] = fixp
[0];
2597 prev_insn_fixp
[1] = fixp
[1];
2598 prev_insn_fixp
[2] = fixp
[2];
2599 prev_insn_reloc_type
[0] = reloc_type
[0];
2600 prev_insn_reloc_type
[1] = reloc_type
[1];
2601 prev_insn_reloc_type
[2] = reloc_type
[2];
2602 if (mips_opts
.mips16
)
2603 prev_insn_extended
= (ip
->use_extend
2604 || *reloc_type
> BFD_RELOC_UNUSED
);
2607 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2608 prev_insn_unreordered
= 0;
2609 prev_insn_frag
= frag_now
;
2610 prev_insn_where
= f
- frag_now
->fr_literal
;
2611 prev_insn_valid
= 1;
2613 else if (place
== NULL
)
2615 /* We need to record a bit of information even when we are not
2616 reordering, in order to determine the base address for mips16
2617 PC relative relocs. */
2618 prev_prev_insn
= prev_insn
;
2620 prev_insn_reloc_type
[0] = reloc_type
[0];
2621 prev_insn_reloc_type
[1] = reloc_type
[1];
2622 prev_insn_reloc_type
[2] = reloc_type
[2];
2623 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2624 prev_insn_unreordered
= 1;
2627 /* We just output an insn, so the next one doesn't have a label. */
2628 mips_clear_insn_labels ();
2630 /* We must ensure that the frag to which an instruction that was
2631 moved from a non-variant frag doesn't become a variant frag,
2632 otherwise tc_gen_reloc may get confused. */
2635 frag_wane (frag_now
);
2640 /* This function forgets that there was any previous instruction or
2641 label. If PRESERVE is non-zero, it remembers enough information to
2642 know whether nops are needed before a noreorder section. */
2645 mips_no_prev_insn (int preserve
)
2649 prev_insn
.insn_mo
= &dummy_opcode
;
2650 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2651 prev_nop_frag
= NULL
;
2652 prev_nop_frag_holds
= 0;
2653 prev_nop_frag_required
= 0;
2654 prev_nop_frag_since
= 0;
2656 prev_insn_valid
= 0;
2657 prev_insn_is_delay_slot
= 0;
2658 prev_insn_unreordered
= 0;
2659 prev_insn_extended
= 0;
2660 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2661 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2662 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2663 prev_prev_insn_unreordered
= 0;
2664 mips_clear_insn_labels ();
2667 /* This function must be called whenever we turn on noreorder or emit
2668 something other than instructions. It inserts any NOPS which might
2669 be needed by the previous instruction, and clears the information
2670 kept for the previous instructions. The INSNS parameter is true if
2671 instructions are to follow. */
2674 mips_emit_delays (bfd_boolean insns
)
2676 if (! mips_opts
.noreorder
)
2681 if ((! mips_opts
.mips16
2682 && ((prev_insn
.insn_mo
->pinfo
2683 & (INSN_LOAD_COPROC_DELAY
2684 | INSN_COPROC_MOVE_DELAY
2685 | INSN_WRITE_COND_CODE
))
2686 && ! cop_interlocks
))
2687 || (! hilo_interlocks
2688 && (prev_insn
.insn_mo
->pinfo
2691 || (! mips_opts
.mips16
2692 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2693 && ! gpr_interlocks
)
2694 || (! mips_opts
.mips16
2695 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2696 && ! cop_mem_interlocks
))
2698 /* Itbl support may require additional care here. */
2700 if ((! mips_opts
.mips16
2701 && ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2702 && ! cop_interlocks
))
2703 || (! hilo_interlocks
2704 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2705 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2708 if (prev_insn_unreordered
)
2711 else if ((! mips_opts
.mips16
2712 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2713 && ! cop_interlocks
))
2714 || (! hilo_interlocks
2715 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2716 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2718 /* Itbl support may require additional care here. */
2719 if (! prev_prev_insn_unreordered
)
2723 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
2726 const char *pn
= prev_insn
.insn_mo
->name
;
2727 if (strncmp(pn
, "macc", 4) == 0
2728 || strncmp(pn
, "dmacc", 5) == 0
2729 || strncmp(pn
, "dmult", 5) == 0)
2733 if (nops
< min_nops
)
2739 struct insn_label_list
*l
;
2743 /* Record the frag which holds the nop instructions, so
2744 that we can remove them if we don't need them. */
2745 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2746 prev_nop_frag
= frag_now
;
2747 prev_nop_frag_holds
= nops
;
2748 prev_nop_frag_required
= 0;
2749 prev_nop_frag_since
= 0;
2752 for (; nops
> 0; --nops
)
2757 /* Move on to a new frag, so that it is safe to simply
2758 decrease the size of prev_nop_frag. */
2759 frag_wane (frag_now
);
2763 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2767 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2768 symbol_set_frag (l
->label
, frag_now
);
2769 val
= (valueT
) frag_now_fix ();
2770 /* mips16 text labels are stored as odd. */
2771 if (mips_opts
.mips16
)
2773 S_SET_VALUE (l
->label
, val
);
2778 /* Mark instruction labels in mips16 mode. */
2780 mips16_mark_labels ();
2782 mips_no_prev_insn (insns
);
2785 /* Build an instruction created by a macro expansion. This is passed
2786 a pointer to the count of instructions created so far, an
2787 expression, the name of the instruction to build, an operand format
2788 string, and corresponding arguments. */
2791 macro_build (char *place
, int *counter
, expressionS
*ep
, const char *name
,
2792 const char *fmt
, ...)
2794 struct mips_cl_insn insn
;
2795 bfd_reloc_code_real_type r
[3];
2798 va_start (args
, fmt
);
2801 * If the macro is about to expand into a second instruction,
2802 * print a warning if needed. We need to pass ip as a parameter
2803 * to generate a better warning message here...
2805 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2806 as_warn (_("Macro instruction expanded into multiple instructions"));
2809 * If the macro is about to expand into a second instruction,
2810 * and it is in a delay slot, print a warning.
2814 && mips_opts
.noreorder
2815 && (prev_prev_insn
.insn_mo
->pinfo
2816 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2817 | INSN_COND_BRANCH_LIKELY
)) != 0)
2818 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2821 ++*counter
; /* bump instruction counter */
2823 if (mips_opts
.mips16
)
2825 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2830 r
[0] = BFD_RELOC_UNUSED
;
2831 r
[1] = BFD_RELOC_UNUSED
;
2832 r
[2] = BFD_RELOC_UNUSED
;
2833 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2834 assert (insn
.insn_mo
);
2835 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2837 /* Search until we get a match for NAME. */
2840 /* It is assumed here that macros will never generate
2841 MDMX or MIPS-3D instructions. */
2842 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2843 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2844 && OPCODE_IS_MEMBER (insn
.insn_mo
,
2846 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2848 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2852 assert (insn
.insn_mo
->name
);
2853 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2856 insn
.insn_opcode
= insn
.insn_mo
->match
;
2874 insn
.insn_opcode
|= (va_arg (args
, int)
2875 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
2880 /* Note that in the macro case, these arguments are already
2881 in MSB form. (When handling the instruction in the
2882 non-macro case, these arguments are sizes from which
2883 MSB values must be calculated.) */
2884 insn
.insn_opcode
|= (va_arg (args
, int)
2885 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
2891 /* Note that in the macro case, these arguments are already
2892 in MSBD form. (When handling the instruction in the
2893 non-macro case, these arguments are sizes from which
2894 MSBD values must be calculated.) */
2895 insn
.insn_opcode
|= (va_arg (args
, int)
2896 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
2907 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2911 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2916 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2922 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2927 int tmp
= va_arg (args
, int);
2929 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2930 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2936 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2943 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2947 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2951 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2955 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2959 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
2966 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
2972 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2973 assert (*r
== BFD_RELOC_GPREL16
2974 || *r
== BFD_RELOC_MIPS_LITERAL
2975 || *r
== BFD_RELOC_MIPS_HIGHER
2976 || *r
== BFD_RELOC_HI16_S
2977 || *r
== BFD_RELOC_LO16
2978 || *r
== BFD_RELOC_MIPS_GOT16
2979 || *r
== BFD_RELOC_MIPS_CALL16
2980 || *r
== BFD_RELOC_MIPS_GOT_DISP
2981 || *r
== BFD_RELOC_MIPS_GOT_PAGE
2982 || *r
== BFD_RELOC_MIPS_GOT_OFST
2983 || *r
== BFD_RELOC_MIPS_GOT_LO16
2984 || *r
== BFD_RELOC_MIPS_CALL_LO16
2985 || (ep
->X_op
== O_subtract
2986 && *r
== BFD_RELOC_PCREL_LO16
));
2990 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2992 && (ep
->X_op
== O_constant
2993 || (ep
->X_op
== O_symbol
2994 && (*r
== BFD_RELOC_MIPS_HIGHEST
2995 || *r
== BFD_RELOC_HI16_S
2996 || *r
== BFD_RELOC_HI16
2997 || *r
== BFD_RELOC_GPREL16
2998 || *r
== BFD_RELOC_MIPS_GOT_HI16
2999 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3000 || (ep
->X_op
== O_subtract
3001 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3005 assert (ep
!= NULL
);
3007 * This allows macro() to pass an immediate expression for
3008 * creating short branches without creating a symbol.
3009 * Note that the expression still might come from the assembly
3010 * input, in which case the value is not checked for range nor
3011 * is a relocation entry generated (yuck).
3013 if (ep
->X_op
== O_constant
)
3015 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3019 *r
= BFD_RELOC_16_PCREL_S2
;
3023 assert (ep
!= NULL
);
3024 *r
= BFD_RELOC_MIPS_JMP
;
3028 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3037 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3039 append_insn (place
, &insn
, ep
, r
);
3043 mips16_macro_build (char *place
, int *counter ATTRIBUTE_UNUSED
,
3044 expressionS
*ep
, const char *name
, const char *fmt
,
3047 struct mips_cl_insn insn
;
3048 bfd_reloc_code_real_type r
[3]
3049 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3051 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3052 assert (insn
.insn_mo
);
3053 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3055 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3056 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3059 assert (insn
.insn_mo
->name
);
3060 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3063 insn
.insn_opcode
= insn
.insn_mo
->match
;
3064 insn
.use_extend
= FALSE
;
3083 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3088 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3092 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3096 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3106 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3113 regno
= va_arg (args
, int);
3114 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3115 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3136 assert (ep
!= NULL
);
3138 if (ep
->X_op
!= O_constant
)
3139 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3142 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3143 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3146 *r
= BFD_RELOC_UNUSED
;
3152 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3159 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3161 append_insn (place
, &insn
, ep
, r
);
3165 * Generate a "jalr" instruction with a relocation hint to the called
3166 * function. This occurs in NewABI PIC code.
3169 macro_build_jalr (int icnt
, expressionS
*ep
)
3178 macro_build (NULL
, &icnt
, NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3180 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3181 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3185 * Generate a "lui" instruction.
3188 macro_build_lui (char *place
, int *counter
, expressionS
*ep
, int regnum
)
3190 expressionS high_expr
;
3191 struct mips_cl_insn insn
;
3192 bfd_reloc_code_real_type r
[3]
3193 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3194 const char *name
= "lui";
3195 const char *fmt
= "t,u";
3197 assert (! mips_opts
.mips16
);
3203 high_expr
.X_op
= O_constant
;
3204 high_expr
.X_add_number
= ep
->X_add_number
;
3207 if (high_expr
.X_op
== O_constant
)
3209 /* we can compute the instruction now without a relocation entry */
3210 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3212 *r
= BFD_RELOC_UNUSED
;
3216 assert (ep
->X_op
== O_symbol
);
3217 /* _gp_disp is a special case, used from s_cpload. */
3218 assert (mips_pic
== NO_PIC
3220 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0));
3221 *r
= BFD_RELOC_HI16_S
;
3225 * If the macro is about to expand into a second instruction,
3226 * print a warning if needed. We need to pass ip as a parameter
3227 * to generate a better warning message here...
3229 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3230 as_warn (_("Macro instruction expanded into multiple instructions"));
3233 ++*counter
; /* bump instruction counter */
3235 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3236 assert (insn
.insn_mo
);
3237 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3238 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3240 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3241 if (*r
== BFD_RELOC_UNUSED
)
3243 insn
.insn_opcode
|= high_expr
.X_add_number
;
3244 append_insn (place
, &insn
, NULL
, r
);
3247 append_insn (place
, &insn
, &high_expr
, r
);
3250 /* Generate a sequence of instructions to do a load or store from a constant
3251 offset off of a base register (breg) into/from a target register (treg),
3252 using AT if necessary. */
3254 macro_build_ldst_constoffset (char *place
, int *counter
, expressionS
*ep
,
3255 const char *op
, int treg
, int breg
, int dbl
)
3257 assert (ep
->X_op
== O_constant
);
3259 /* Sign-extending 32-bit constants makes their handling easier. */
3260 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3261 == ~((bfd_vma
) 0x7fffffff)))
3263 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3264 as_bad (_("constant too large"));
3266 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3270 /* Right now, this routine can only handle signed 32-bit constants. */
3271 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3272 as_warn (_("operand overflow"));
3274 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3276 /* Signed 16-bit offset will fit in the op. Easy! */
3277 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
,
3282 /* 32-bit offset, need multiple instructions and AT, like:
3283 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3284 addu $tempreg,$tempreg,$breg
3285 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3286 to handle the complete offset. */
3287 macro_build_lui (place
, counter
, ep
, AT
);
3290 macro_build (place
, counter
, NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
,
3294 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
,
3298 as_warn (_("Macro used $at after \".set noat\""));
3303 * Generates code to set the $at register to true (one)
3304 * if reg is less than the immediate expression.
3307 set_at (int *counter
, int reg
, int unsignedp
)
3309 if (imm_expr
.X_op
== O_constant
3310 && imm_expr
.X_add_number
>= -0x8000
3311 && imm_expr
.X_add_number
< 0x8000)
3312 macro_build (NULL
, counter
, &imm_expr
, unsignedp
? "sltiu" : "slti",
3313 "t,r,j", AT
, reg
, BFD_RELOC_LO16
);
3316 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3317 macro_build (NULL
, counter
, NULL
, unsignedp
? "sltu" : "slt",
3318 "d,v,t", AT
, reg
, AT
);
3323 normalize_constant_expr (expressionS
*ex
)
3325 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3326 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3330 /* Warn if an expression is not a constant. */
3333 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3335 if (ex
->X_op
== O_big
)
3336 as_bad (_("unsupported large constant"));
3337 else if (ex
->X_op
!= O_constant
)
3338 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3340 normalize_constant_expr (ex
);
3343 /* Count the leading zeroes by performing a binary chop. This is a
3344 bulky bit of source, but performance is a LOT better for the
3345 majority of values than a simple loop to count the bits:
3346 for (lcnt = 0; (lcnt < 32); lcnt++)
3347 if ((v) & (1 << (31 - lcnt)))
3349 However it is not code size friendly, and the gain will drop a bit
3350 on certain cached systems.
3352 #define COUNT_TOP_ZEROES(v) \
3353 (((v) & ~0xffff) == 0 \
3354 ? ((v) & ~0xff) == 0 \
3355 ? ((v) & ~0xf) == 0 \
3356 ? ((v) & ~0x3) == 0 \
3357 ? ((v) & ~0x1) == 0 \
3362 : ((v) & ~0x7) == 0 \
3365 : ((v) & ~0x3f) == 0 \
3366 ? ((v) & ~0x1f) == 0 \
3369 : ((v) & ~0x7f) == 0 \
3372 : ((v) & ~0xfff) == 0 \
3373 ? ((v) & ~0x3ff) == 0 \
3374 ? ((v) & ~0x1ff) == 0 \
3377 : ((v) & ~0x7ff) == 0 \
3380 : ((v) & ~0x3fff) == 0 \
3381 ? ((v) & ~0x1fff) == 0 \
3384 : ((v) & ~0x7fff) == 0 \
3387 : ((v) & ~0xffffff) == 0 \
3388 ? ((v) & ~0xfffff) == 0 \
3389 ? ((v) & ~0x3ffff) == 0 \
3390 ? ((v) & ~0x1ffff) == 0 \
3393 : ((v) & ~0x7ffff) == 0 \
3396 : ((v) & ~0x3fffff) == 0 \
3397 ? ((v) & ~0x1fffff) == 0 \
3400 : ((v) & ~0x7fffff) == 0 \
3403 : ((v) & ~0xfffffff) == 0 \
3404 ? ((v) & ~0x3ffffff) == 0 \
3405 ? ((v) & ~0x1ffffff) == 0 \
3408 : ((v) & ~0x7ffffff) == 0 \
3411 : ((v) & ~0x3fffffff) == 0 \
3412 ? ((v) & ~0x1fffffff) == 0 \
3415 : ((v) & ~0x7fffffff) == 0 \
3420 * This routine generates the least number of instructions necessary to load
3421 * an absolute expression value into a register.
3424 load_register (int *counter
, int reg
, expressionS
*ep
, int dbl
)
3427 expressionS hi32
, lo32
;
3429 if (ep
->X_op
!= O_big
)
3431 assert (ep
->X_op
== O_constant
);
3433 /* Sign-extending 32-bit constants makes their handling easier. */
3434 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3435 == ~((bfd_vma
) 0x7fffffff)))
3437 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3438 as_bad (_("constant too large"));
3440 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3444 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3446 /* We can handle 16 bit signed values with an addiu to
3447 $zero. No need to ever use daddiu here, since $zero and
3448 the result are always correct in 32 bit mode. */
3449 macro_build (NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3453 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3455 /* We can handle 16 bit unsigned values with an ori to
3457 macro_build (NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3461 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3463 /* 32 bit values require an lui. */
3464 macro_build (NULL
, counter
, ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3465 if ((ep
->X_add_number
& 0xffff) != 0)
3466 macro_build (NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3472 /* The value is larger than 32 bits. */
3474 if (HAVE_32BIT_GPRS
)
3476 as_bad (_("Number (0x%lx) larger than 32 bits"),
3477 (unsigned long) ep
->X_add_number
);
3478 macro_build (NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3483 if (ep
->X_op
!= O_big
)
3486 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3487 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3488 hi32
.X_add_number
&= 0xffffffff;
3490 lo32
.X_add_number
&= 0xffffffff;
3494 assert (ep
->X_add_number
> 2);
3495 if (ep
->X_add_number
== 3)
3496 generic_bignum
[3] = 0;
3497 else if (ep
->X_add_number
> 4)
3498 as_bad (_("Number larger than 64 bits"));
3499 lo32
.X_op
= O_constant
;
3500 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3501 hi32
.X_op
= O_constant
;
3502 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3505 if (hi32
.X_add_number
== 0)
3510 unsigned long hi
, lo
;
3512 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3514 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3516 macro_build (NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
3520 if (lo32
.X_add_number
& 0x80000000)
3522 macro_build (NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3524 if (lo32
.X_add_number
& 0xffff)
3525 macro_build (NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
3531 /* Check for 16bit shifted constant. We know that hi32 is
3532 non-zero, so start the mask on the first bit of the hi32
3537 unsigned long himask
, lomask
;
3541 himask
= 0xffff >> (32 - shift
);
3542 lomask
= (0xffff << shift
) & 0xffffffff;
3546 himask
= 0xffff << (shift
- 32);
3549 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3550 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3554 tmp
.X_op
= O_constant
;
3556 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3557 | (lo32
.X_add_number
>> shift
));
3559 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3560 macro_build (NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3562 macro_build (NULL
, counter
, NULL
,
3563 (shift
>= 32) ? "dsll32" : "dsll",
3565 (shift
>= 32) ? shift
- 32 : shift
);
3570 while (shift
<= (64 - 16));
3572 /* Find the bit number of the lowest one bit, and store the
3573 shifted value in hi/lo. */
3574 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3575 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3579 while ((lo
& 1) == 0)
3584 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3590 while ((hi
& 1) == 0)
3599 /* Optimize if the shifted value is a (power of 2) - 1. */
3600 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3601 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3603 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3608 /* This instruction will set the register to be all
3610 tmp
.X_op
= O_constant
;
3611 tmp
.X_add_number
= (offsetT
) -1;
3612 macro_build (NULL
, counter
, &tmp
, "addiu", "t,r,j", reg
, 0,
3617 macro_build (NULL
, counter
, NULL
,
3618 (bit
>= 32) ? "dsll32" : "dsll",
3620 (bit
>= 32) ? bit
- 32 : bit
);
3622 macro_build (NULL
, counter
, NULL
,
3623 (shift
>= 32) ? "dsrl32" : "dsrl",
3625 (shift
>= 32) ? shift
- 32 : shift
);
3630 /* Sign extend hi32 before calling load_register, because we can
3631 generally get better code when we load a sign extended value. */
3632 if ((hi32
.X_add_number
& 0x80000000) != 0)
3633 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3634 load_register (counter
, reg
, &hi32
, 0);
3637 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3641 macro_build (NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3649 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3651 macro_build (NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3653 macro_build (NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3659 macro_build (NULL
, counter
, NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3663 mid16
.X_add_number
>>= 16;
3664 macro_build (NULL
, counter
, &mid16
, "ori", "t,r,i", reg
, freg
,
3666 macro_build (NULL
, counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3669 if ((lo32
.X_add_number
& 0xffff) != 0)
3670 macro_build (NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3674 /* Load an address into a register. */
3677 load_address (int *counter
, int reg
, expressionS
*ep
, int *used_at
)
3681 if (ep
->X_op
!= O_constant
3682 && ep
->X_op
!= O_symbol
)
3684 as_bad (_("expression too complex"));
3685 ep
->X_op
= O_constant
;
3688 if (ep
->X_op
== O_constant
)
3690 load_register (counter
, reg
, ep
, HAVE_64BIT_ADDRESSES
);
3694 if (mips_pic
== NO_PIC
)
3696 /* If this is a reference to a GP relative symbol, we want
3697 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3699 lui $reg,<sym> (BFD_RELOC_HI16_S)
3700 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3701 If we have an addend, we always use the latter form.
3703 With 64bit address space and a usable $at we want
3704 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3705 lui $at,<sym> (BFD_RELOC_HI16_S)
3706 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3707 daddiu $at,<sym> (BFD_RELOC_LO16)
3711 If $at is already in use, we use a path which is suboptimal
3712 on superscalar processors.
3713 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3714 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3716 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3718 daddiu $reg,<sym> (BFD_RELOC_LO16)
3720 if (HAVE_64BIT_ADDRESSES
)
3722 /* We don't do GP optimization for now because RELAX_ENCODE can't
3723 hold the data for such large chunks. */
3725 if (*used_at
== 0 && ! mips_opts
.noat
)
3727 macro_build (p
, counter
, ep
, "lui", "t,u",
3728 reg
, BFD_RELOC_MIPS_HIGHEST
);
3729 macro_build (p
, counter
, ep
, "lui", "t,u",
3730 AT
, BFD_RELOC_HI16_S
);
3731 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3732 reg
, reg
, BFD_RELOC_MIPS_HIGHER
);
3733 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3734 AT
, AT
, BFD_RELOC_LO16
);
3735 macro_build (p
, counter
, NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3736 macro_build (p
, counter
, NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3741 macro_build (p
, counter
, ep
, "lui", "t,u",
3742 reg
, BFD_RELOC_MIPS_HIGHEST
);
3743 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3744 reg
, reg
, BFD_RELOC_MIPS_HIGHER
);
3745 macro_build (p
, counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3746 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3747 reg
, reg
, BFD_RELOC_HI16_S
);
3748 macro_build (p
, counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3749 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3750 reg
, reg
, BFD_RELOC_LO16
);
3755 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3756 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3759 macro_build (NULL
, counter
, ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3760 mips_gp_register
, BFD_RELOC_GPREL16
);
3761 p
= frag_var (rs_machine_dependent
, 8, 0,
3762 RELAX_ENCODE (4, 8, 0, 4, 0,
3763 mips_opts
.warn_about_macros
),
3764 ep
->X_add_symbol
, 0, NULL
);
3766 macro_build_lui (p
, counter
, ep
, reg
);
3769 macro_build (p
, counter
, ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3773 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3777 /* If this is a reference to an external symbol, we want
3778 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3780 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3782 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3783 If there is a constant, it must be added in after.
3785 If we have NewABI, we want
3786 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3787 unless we're referencing a global symbol with a non-zero
3788 offset, in which case cst must be added separately. */
3793 if (ep
->X_add_number
)
3795 frag_now
->tc_frag_data
.tc_fr_offset
=
3796 ex
.X_add_number
= ep
->X_add_number
;
3797 ep
->X_add_number
= 0;
3798 macro_build (NULL
, counter
, ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3799 reg
, BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3800 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3801 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3802 ex
.X_op
= O_constant
;
3803 macro_build (NULL
, counter
, &ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3804 reg
, reg
, BFD_RELOC_LO16
);
3805 p
= frag_var (rs_machine_dependent
, 8, 0,
3806 RELAX_ENCODE (8, 4, 0, 0, 0,
3807 mips_opts
.warn_about_macros
),
3808 ep
->X_add_symbol
, 0, NULL
);
3809 ep
->X_add_number
= ex
.X_add_number
;
3812 macro_build (p
, counter
, ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3813 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3817 /* To avoid confusion in tc_gen_reloc, we must ensure
3818 that this does not become a variant frag. */
3819 frag_wane (frag_now
);
3825 ex
.X_add_number
= ep
->X_add_number
;
3826 ep
->X_add_number
= 0;
3828 macro_build (NULL
, counter
, ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3829 BFD_RELOC_MIPS_GOT16
,
3831 macro_build (NULL
, counter
, NULL
, "nop", "");
3832 p
= frag_var (rs_machine_dependent
, 4, 0,
3833 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3834 ep
->X_add_symbol
, 0, NULL
);
3835 macro_build (p
, counter
, ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3838 if (ex
.X_add_number
!= 0)
3840 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3841 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3842 ex
.X_op
= O_constant
;
3843 macro_build (NULL
, counter
, &ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3844 reg
, reg
, BFD_RELOC_LO16
);
3848 else if (mips_pic
== SVR4_PIC
)
3853 /* This is the large GOT case. If this is a reference to an
3854 external symbol, we want
3855 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3857 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3859 Otherwise, for a reference to a local symbol in old ABI, we want
3860 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3862 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3863 If there is a constant, it must be added in after.
3865 In the NewABI, for local symbols, with or without offsets, we want:
3866 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3867 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3873 frag_now
->tc_frag_data
.tc_fr_offset
=
3874 ex
.X_add_number
= ep
->X_add_number
;
3875 ep
->X_add_number
= 0;
3876 macro_build (NULL
, counter
, ep
, "lui", "t,u", reg
,
3877 BFD_RELOC_MIPS_GOT_HI16
);
3878 macro_build (NULL
, counter
, NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
,
3879 reg
, mips_gp_register
);
3880 macro_build (NULL
, counter
, ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3881 BFD_RELOC_MIPS_GOT_LO16
, reg
);
3882 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3883 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3884 else if (ex
.X_add_number
)
3886 ex
.X_op
= O_constant
;
3887 macro_build (NULL
, counter
, &ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3888 reg
, reg
, BFD_RELOC_LO16
);
3891 ep
->X_add_number
= ex
.X_add_number
;
3892 p
= frag_var (rs_machine_dependent
, 8, 0,
3893 RELAX_ENCODE (ex
.X_add_number
? 16 : 12, 8, 0, 4, 0,
3894 mips_opts
.warn_about_macros
),
3895 ep
->X_add_symbol
, 0, NULL
);
3896 macro_build (p
, counter
, ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3897 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3898 macro_build (p
+ 4, counter
, ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3899 reg
, BFD_RELOC_MIPS_GOT_OFST
);
3903 ex
.X_add_number
= ep
->X_add_number
;
3904 ep
->X_add_number
= 0;
3905 if (reg_needs_delay (mips_gp_register
))
3910 macro_build (NULL
, counter
, ep
, "lui", "t,u", reg
,
3911 BFD_RELOC_MIPS_GOT_HI16
);
3912 macro_build (NULL
, counter
, NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
,
3913 reg
, mips_gp_register
);
3914 macro_build (NULL
, counter
, ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3915 BFD_RELOC_MIPS_GOT_LO16
, reg
);
3916 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3917 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3918 mips_opts
.warn_about_macros
),
3919 ep
->X_add_symbol
, 0, NULL
);
3922 /* We need a nop before loading from $gp. This special
3923 check is required because the lui which starts the main
3924 instruction stream does not refer to $gp, and so will not
3925 insert the nop which may be required. */
3926 macro_build (p
, counter
, NULL
, "nop", "");
3929 macro_build (p
, counter
, ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3930 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3932 macro_build (p
, counter
, NULL
, "nop", "");
3934 macro_build (p
, counter
, ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3937 if (ex
.X_add_number
!= 0)
3939 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3940 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3941 ex
.X_op
= O_constant
;
3942 macro_build (NULL
, counter
, &ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3943 reg
, reg
, BFD_RELOC_LO16
);
3947 else if (mips_pic
== EMBEDDED_PIC
)
3950 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3952 macro_build (NULL
, counter
, ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3953 mips_gp_register
, BFD_RELOC_GPREL16
);
3959 /* Move the contents of register SOURCE into register DEST. */
3962 move_register (int *counter
, int dest
, int source
)
3964 macro_build (NULL
, counter
, NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu",
3965 "d,v,t", dest
, source
, 0);
3970 * This routine implements the seemingly endless macro or synthesized
3971 * instructions and addressing modes in the mips assembly language. Many
3972 * of these macros are simple and are similar to each other. These could
3973 * probably be handled by some kind of table or grammar approach instead of
3974 * this verbose method. Others are not simple macros but are more like
3975 * optimizing code generation.
3976 * One interesting optimization is when several store macros appear
3977 * consecutively that would load AT with the upper half of the same address.
3978 * The ensuing load upper instructions are ommited. This implies some kind
3979 * of global optimization. We currently only optimize within a single macro.
3980 * For many of the load and store macros if the address is specified as a
3981 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3982 * first load register 'at' with zero and use it as the base register. The
3983 * mips assembler simply uses register $zero. Just one tiny optimization
3987 macro (struct mips_cl_insn
*ip
)
3989 register int treg
, sreg
, dreg
, breg
;
4006 bfd_reloc_code_real_type r
;
4007 int hold_mips_optimize
;
4009 assert (! mips_opts
.mips16
);
4011 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4012 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4013 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4014 mask
= ip
->insn_mo
->mask
;
4016 expr1
.X_op
= O_constant
;
4017 expr1
.X_op_symbol
= NULL
;
4018 expr1
.X_add_symbol
= NULL
;
4019 expr1
.X_add_number
= 1;
4021 /* Unmatched fixups should not be put in the same frag as a relaxable
4022 macro. For example, suppose we have:
4026 addiu $4,$4,%lo(l1) # 3
4028 If instructions 1 and 2 were put in the same frag, md_frob_file would
4029 move the fixup for #1 after the fixups for the "unrelaxed" version of
4030 #2. This would confuse tc_gen_reloc, which expects the relocations
4031 for #2 to be the last for that frag.
4033 Also, if tc_gen_reloc sees certain relocations in a variant frag,
4034 it assumes that they belong to a relaxable macro. We mustn't put
4035 other uses of such relocations into a variant frag.
4037 To avoid both problems, finish the current frag it contains a
4038 %reloc() operator. The macro then goes into a new frag. */
4039 if (prev_reloc_op_frag
== frag_now
)
4041 frag_wane (frag_now
);
4055 mips_emit_delays (TRUE
);
4056 ++mips_opts
.noreorder
;
4057 mips_any_noreorder
= 1;
4059 expr1
.X_add_number
= 8;
4060 macro_build (NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
4062 macro_build (NULL
, &icnt
, NULL
, "nop", "", 0);
4064 move_register (&icnt
, dreg
, sreg
);
4065 macro_build (NULL
, &icnt
, NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0,
4068 --mips_opts
.noreorder
;
4089 if (imm_expr
.X_op
== O_constant
4090 && imm_expr
.X_add_number
>= -0x8000
4091 && imm_expr
.X_add_number
< 0x8000)
4093 macro_build (NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
4097 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4098 macro_build (NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4117 if (imm_expr
.X_op
== O_constant
4118 && imm_expr
.X_add_number
>= 0
4119 && imm_expr
.X_add_number
< 0x10000)
4121 if (mask
!= M_NOR_I
)
4122 macro_build (NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
, sreg
,
4126 macro_build (NULL
, &icnt
, &imm_expr
, "ori", "t,r,i", treg
, sreg
,
4128 macro_build (NULL
, &icnt
, NULL
, "nor", "d,v,t", treg
, treg
, 0);
4133 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4134 macro_build (NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4151 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4153 macro_build (NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, 0);
4156 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4157 macro_build (NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
4165 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bgezl" : "bgez",
4171 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "blezl" : "blez",
4175 macro_build (NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4176 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "beql" : "beq",
4183 /* check for > max integer */
4184 maxnum
= 0x7fffffff;
4185 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4192 if (imm_expr
.X_op
== O_constant
4193 && imm_expr
.X_add_number
>= maxnum
4194 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4197 /* result is always false */
4201 as_warn (_("Branch %s is always false (nop)"),
4203 macro_build (NULL
, &icnt
, NULL
, "nop", "", 0);
4208 as_warn (_("Branch likely %s is always false"),
4210 macro_build (NULL
, &icnt
, &offset_expr
, "bnel", "s,t,p", 0, 0);
4214 if (imm_expr
.X_op
!= O_constant
)
4215 as_bad (_("Unsupported large constant"));
4216 ++imm_expr
.X_add_number
;
4220 if (mask
== M_BGEL_I
)
4222 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4224 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bgezl" : "bgez",
4228 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4230 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bgtzl" : "bgtz",
4234 maxnum
= 0x7fffffff;
4235 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4242 maxnum
= - maxnum
- 1;
4243 if (imm_expr
.X_op
== O_constant
4244 && imm_expr
.X_add_number
<= maxnum
4245 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4248 /* result is always true */
4249 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4250 macro_build (NULL
, &icnt
, &offset_expr
, "b", "p");
4253 set_at (&icnt
, sreg
, 0);
4254 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "beql" : "beq",
4265 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "beql" : "beq",
4269 macro_build (NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4270 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "beql" : "beq",
4279 && imm_expr
.X_op
== O_constant
4280 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4282 if (imm_expr
.X_op
!= O_constant
)
4283 as_bad (_("Unsupported large constant"));
4284 ++imm_expr
.X_add_number
;
4288 if (mask
== M_BGEUL_I
)
4290 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4292 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4294 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bnel" : "bne",
4298 set_at (&icnt
, sreg
, 1);
4299 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "beql" : "beq",
4308 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bgtzl" : "bgtz",
4314 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bltzl" : "bltz",
4318 macro_build (NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4319 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bnel" : "bne",
4328 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bnel" : "bne",
4334 macro_build (NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4335 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bnel" : "bne",
4344 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "blezl" : "blez",
4350 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bgezl" : "bgez",
4354 macro_build (NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4355 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "beql" : "beq",
4362 maxnum
= 0x7fffffff;
4363 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4370 if (imm_expr
.X_op
== O_constant
4371 && imm_expr
.X_add_number
>= maxnum
4372 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4374 if (imm_expr
.X_op
!= O_constant
)
4375 as_bad (_("Unsupported large constant"));
4376 ++imm_expr
.X_add_number
;
4380 if (mask
== M_BLTL_I
)
4382 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4384 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bltzl" : "bltz",
4388 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4390 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "blezl" : "blez",
4394 set_at (&icnt
, sreg
, 0);
4395 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bnel" : "bne",
4404 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "beql" : "beq",
4410 macro_build (NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4411 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "beql" : "beq",
4420 && imm_expr
.X_op
== O_constant
4421 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4423 if (imm_expr
.X_op
!= O_constant
)
4424 as_bad (_("Unsupported large constant"));
4425 ++imm_expr
.X_add_number
;
4429 if (mask
== M_BLTUL_I
)
4431 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4433 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4435 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "beql" : "beq",
4439 set_at (&icnt
, sreg
, 1);
4440 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bnel" : "bne",
4449 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bltzl" : "bltz",
4455 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bgtzl" : "bgtz",
4459 macro_build (NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4460 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bnel" : "bne",
4471 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bnel" : "bne",
4475 macro_build (NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4476 macro_build (NULL
, &icnt
, &offset_expr
, likely
? "bnel" : "bne",
4485 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4487 as_bad (_("Unsupported large constant"));
4492 pos
= (unsigned long) imm_expr
.X_add_number
;
4493 size
= (unsigned long) imm2_expr
.X_add_number
;
4498 as_bad (_("Improper position (%lu)"), pos
);
4501 if (size
== 0 || size
> 64
4502 || (pos
+ size
- 1) > 63)
4504 as_bad (_("Improper extract size (%lu, position %lu)"),
4509 if (size
<= 32 && pos
< 32)
4514 else if (size
<= 32)
4524 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
4525 fmt
, treg
, sreg
, pos
, size
- 1);
4534 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4536 as_bad (_("Unsupported large constant"));
4541 pos
= (unsigned long) imm_expr
.X_add_number
;
4542 size
= (unsigned long) imm2_expr
.X_add_number
;
4547 as_bad (_("Improper position (%lu)"), pos
);
4550 if (size
== 0 || size
> 64
4551 || (pos
+ size
- 1) > 63)
4553 as_bad (_("Improper insert size (%lu, position %lu)"),
4558 if (pos
< 32 && (pos
+ size
- 1) < 32)
4573 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
4574 fmt
, treg
, sreg
, pos
, pos
+ size
- 1);
4590 as_warn (_("Divide by zero."));
4592 macro_build (NULL
, &icnt
, NULL
, "teq", "s,t,q", 0, 0, 7);
4594 macro_build (NULL
, &icnt
, NULL
, "break", "c", 7);
4598 mips_emit_delays (TRUE
);
4599 ++mips_opts
.noreorder
;
4600 mips_any_noreorder
= 1;
4603 macro_build (NULL
, &icnt
, NULL
, "teq", "s,t,q", treg
, 0, 7);
4604 macro_build (NULL
, &icnt
, NULL
, dbl
? "ddiv" : "div", "z,s,t",
4609 expr1
.X_add_number
= 8;
4610 macro_build (NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4611 macro_build (NULL
, &icnt
, NULL
, dbl
? "ddiv" : "div", "z,s,t",
4613 macro_build (NULL
, &icnt
, NULL
, "break", "c", 7);
4615 expr1
.X_add_number
= -1;
4616 macro_build (NULL
, &icnt
, &expr1
, dbl
? "daddiu" : "addiu", "t,r,j",
4617 AT
, 0, BFD_RELOC_LO16
);
4618 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4619 macro_build (NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4622 expr1
.X_add_number
= 1;
4623 macro_build (NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4625 macro_build (NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4629 expr1
.X_add_number
= 0x80000000;
4630 macro_build (NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4635 macro_build (NULL
, &icnt
, NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4636 /* We want to close the noreorder block as soon as possible, so
4637 that later insns are available for delay slot filling. */
4638 --mips_opts
.noreorder
;
4642 expr1
.X_add_number
= 8;
4643 macro_build (NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4644 macro_build (NULL
, &icnt
, NULL
, "nop", "", 0);
4646 /* We want to close the noreorder block as soon as possible, so
4647 that later insns are available for delay slot filling. */
4648 --mips_opts
.noreorder
;
4650 macro_build (NULL
, &icnt
, NULL
, "break", "c", 6);
4652 macro_build (NULL
, &icnt
, NULL
, s
, "d", dreg
);
4691 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4693 as_warn (_("Divide by zero."));
4695 macro_build (NULL
, &icnt
, NULL
, "teq", "s,t,q", 0, 0, 7);
4697 macro_build (NULL
, &icnt
, NULL
, "break", "c", 7);
4700 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4702 if (strcmp (s2
, "mflo") == 0)
4703 move_register (&icnt
, dreg
, sreg
);
4705 move_register (&icnt
, dreg
, 0);
4708 if (imm_expr
.X_op
== O_constant
4709 && imm_expr
.X_add_number
== -1
4710 && s
[strlen (s
) - 1] != 'u')
4712 if (strcmp (s2
, "mflo") == 0)
4714 macro_build (NULL
, &icnt
, NULL
, dbl
? "dneg" : "neg", "d,w",
4718 move_register (&icnt
, dreg
, 0);
4722 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4723 macro_build (NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4724 macro_build (NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4743 mips_emit_delays (TRUE
);
4744 ++mips_opts
.noreorder
;
4745 mips_any_noreorder
= 1;
4748 macro_build (NULL
, &icnt
, NULL
, "teq", "s,t,q", treg
, 0, 7);
4749 macro_build (NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4750 /* We want to close the noreorder block as soon as possible, so
4751 that later insns are available for delay slot filling. */
4752 --mips_opts
.noreorder
;
4756 expr1
.X_add_number
= 8;
4757 macro_build (NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4758 macro_build (NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4760 /* We want to close the noreorder block as soon as possible, so
4761 that later insns are available for delay slot filling. */
4762 --mips_opts
.noreorder
;
4763 macro_build (NULL
, &icnt
, NULL
, "break", "c", 7);
4765 macro_build (NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4777 /* Load the address of a symbol into a register. If breg is not
4778 zero, we then add a base register to it. */
4780 if (dbl
&& HAVE_32BIT_GPRS
)
4781 as_warn (_("dla used to load 32-bit register"));
4783 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4784 as_warn (_("la used to load 64-bit address"));
4786 if (offset_expr
.X_op
== O_constant
4787 && offset_expr
.X_add_number
>= -0x8000
4788 && offset_expr
.X_add_number
< 0x8000)
4790 macro_build (NULL
, &icnt
, &offset_expr
,
4791 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4792 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4807 /* When generating embedded PIC code, we permit expressions of
4810 la $treg,foo-bar($breg)
4811 where bar is an address in the current section. These are used
4812 when getting the addresses of functions. We don't permit
4813 X_add_number to be non-zero, because if the symbol is
4814 external the relaxing code needs to know that any addend is
4815 purely the offset to X_op_symbol. */
4816 if (mips_pic
== EMBEDDED_PIC
4817 && offset_expr
.X_op
== O_subtract
4818 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4819 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4820 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4822 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4825 && (offset_expr
.X_add_number
== 0
4826 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4832 macro_build (NULL
, &icnt
, &offset_expr
, "lui", "t,u", tempreg
,
4833 BFD_RELOC_PCREL_HI16_S
);
4837 macro_build (NULL
, &icnt
, &offset_expr
, "lui", "t,u", tempreg
,
4838 BFD_RELOC_PCREL_HI16_S
);
4839 macro_build (NULL
, &icnt
, NULL
,
4840 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4841 "d,v,t", tempreg
, tempreg
, breg
);
4843 macro_build (NULL
, &icnt
, &offset_expr
,
4844 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4845 "t,r,j", treg
, tempreg
, BFD_RELOC_PCREL_LO16
);
4851 if (offset_expr
.X_op
!= O_symbol
4852 && offset_expr
.X_op
!= O_constant
)
4854 as_bad (_("expression too complex"));
4855 offset_expr
.X_op
= O_constant
;
4858 if (offset_expr
.X_op
== O_constant
)
4859 load_register (&icnt
, tempreg
, &offset_expr
,
4860 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4861 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4862 : HAVE_64BIT_ADDRESSES
));
4863 else if (mips_pic
== NO_PIC
)
4865 /* If this is a reference to a GP relative symbol, we want
4866 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4868 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4869 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4870 If we have a constant, we need two instructions anyhow,
4871 so we may as well always use the latter form.
4873 With 64bit address space and a usable $at we want
4874 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4875 lui $at,<sym> (BFD_RELOC_HI16_S)
4876 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4877 daddiu $at,<sym> (BFD_RELOC_LO16)
4879 daddu $tempreg,$tempreg,$at
4881 If $at is already in use, we use a path which is suboptimal
4882 on superscalar processors.
4883 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4884 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4886 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4888 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4891 if (HAVE_64BIT_ADDRESSES
)
4893 /* We don't do GP optimization for now because RELAX_ENCODE can't
4894 hold the data for such large chunks. */
4896 if (used_at
== 0 && ! mips_opts
.noat
)
4898 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4899 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4900 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4901 AT
, BFD_RELOC_HI16_S
);
4902 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4903 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4904 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4905 AT
, AT
, BFD_RELOC_LO16
);
4906 macro_build (p
, &icnt
, NULL
, "dsll32", "d,w,<",
4907 tempreg
, tempreg
, 0);
4908 macro_build (p
, &icnt
, NULL
, "daddu", "d,v,t",
4909 tempreg
, tempreg
, AT
);
4914 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4915 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4916 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4917 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4918 macro_build (p
, &icnt
, NULL
, "dsll", "d,w,<",
4919 tempreg
, tempreg
, 16);
4920 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4921 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4922 macro_build (p
, &icnt
, NULL
, "dsll", "d,w,<",
4923 tempreg
, tempreg
, 16);
4924 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4925 tempreg
, tempreg
, BFD_RELOC_LO16
);
4930 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4931 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4934 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
,
4935 "t,r,j", tempreg
, mips_gp_register
,
4937 p
= frag_var (rs_machine_dependent
, 8, 0,
4938 RELAX_ENCODE (4, 8, 0, 4, 0,
4939 mips_opts
.warn_about_macros
),
4940 offset_expr
.X_add_symbol
, 0, NULL
);
4942 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4945 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
,
4946 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
4949 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4951 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4953 /* If this is a reference to an external symbol, and there
4954 is no constant, we want
4955 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4956 or for lca or if tempreg is PIC_CALL_REG
4957 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4958 For a local symbol, we want
4959 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4961 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4963 If we have a small constant, and this is a reference to
4964 an external symbol, we want
4965 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4967 addiu $tempreg,$tempreg,<constant>
4968 For a local symbol, we want the same instruction
4969 sequence, but we output a BFD_RELOC_LO16 reloc on the
4972 If we have a large constant, and this is a reference to
4973 an external symbol, we want
4974 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4975 lui $at,<hiconstant>
4976 addiu $at,$at,<loconstant>
4977 addu $tempreg,$tempreg,$at
4978 For a local symbol, we want the same instruction
4979 sequence, but we output a BFD_RELOC_LO16 reloc on the
4983 expr1
.X_add_number
= offset_expr
.X_add_number
;
4984 offset_expr
.X_add_number
= 0;
4986 if (expr1
.X_add_number
== 0 && breg
== 0
4987 && (call
|| tempreg
== PIC_CALL_REG
))
4988 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4989 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
4990 tempreg
, lw_reloc_type
, mips_gp_register
);
4991 if (expr1
.X_add_number
== 0)
5000 /* We're going to put in an addu instruction using
5001 tempreg, so we may as well insert the nop right
5003 macro_build (NULL
, &icnt
, NULL
, "nop", "");
5006 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
5007 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
5009 ? mips_opts
.warn_about_macros
5011 offset_expr
.X_add_symbol
, 0, NULL
);
5014 macro_build (p
, &icnt
, NULL
, "nop", "");
5017 macro_build (p
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5018 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
5019 /* FIXME: If breg == 0, and the next instruction uses
5020 $tempreg, then if this variant case is used an extra
5021 nop will be generated. */
5023 else if (expr1
.X_add_number
>= -0x8000
5024 && expr1
.X_add_number
< 0x8000)
5026 macro_build (NULL
, &icnt
, NULL
, "nop", "");
5027 macro_build (NULL
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5028 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
5029 frag_var (rs_machine_dependent
, 0, 0,
5030 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
5031 offset_expr
.X_add_symbol
, 0, NULL
);
5037 /* If we are going to add in a base register, and the
5038 target register and the base register are the same,
5039 then we are using AT as a temporary register. Since
5040 we want to load the constant into AT, we add our
5041 current AT (from the global offset table) and the
5042 register into the register now, and pretend we were
5043 not using a base register. */
5048 macro_build (NULL
, &icnt
, NULL
, "nop", "");
5049 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5056 /* Set mips_optimize around the lui instruction to avoid
5057 inserting an unnecessary nop after the lw. */
5058 hold_mips_optimize
= mips_optimize
;
5060 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5061 mips_optimize
= hold_mips_optimize
;
5063 macro_build (NULL
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5064 AT
, AT
, BFD_RELOC_LO16
);
5065 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5066 tempreg
, tempreg
, AT
);
5067 frag_var (rs_machine_dependent
, 0, 0,
5068 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
5069 offset_expr
.X_add_symbol
, 0, NULL
);
5073 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5076 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5079 /* If this is a reference to an external, and there is no
5080 constant, or local symbol (*), with or without a
5082 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5083 or for lca or if tempreg is PIC_CALL_REG
5084 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5086 If we have a small constant, and this is a reference to
5087 an external symbol, we want
5088 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5089 addiu $tempreg,$tempreg,<constant>
5091 If we have a large constant, and this is a reference to
5092 an external symbol, we want
5093 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5094 lui $at,<hiconstant>
5095 addiu $at,$at,<loconstant>
5096 addu $tempreg,$tempreg,$at
5098 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5099 local symbols, even though it introduces an additional
5103 if (offset_expr
.X_add_number
== 0 && breg
== 0
5104 && (call
|| tempreg
== PIC_CALL_REG
))
5105 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5106 if (offset_expr
.X_add_number
)
5108 frag_now
->tc_frag_data
.tc_fr_offset
=
5109 expr1
.X_add_number
= offset_expr
.X_add_number
;
5110 offset_expr
.X_add_number
= 0;
5112 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5113 "t,o(b)", tempreg
, lw_reloc_type
,
5116 if (expr1
.X_add_number
>= -0x8000
5117 && expr1
.X_add_number
< 0x8000)
5119 macro_build (NULL
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5120 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
5121 p
= frag_var (rs_machine_dependent
, 4, 0,
5122 RELAX_ENCODE (8, 4, 0, 0, 0, 0),
5123 offset_expr
.X_add_symbol
, 0, NULL
);
5125 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5129 /* If we are going to add in a base register, and the
5130 target register and the base register are the same,
5131 then we are using AT as a temporary register. Since
5132 we want to load the constant into AT, we add our
5133 current AT (from the global offset table) and the
5134 register into the register now, and pretend we were
5135 not using a base register. */
5140 assert (tempreg
== AT
);
5141 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
,
5142 "d,v,t", treg
, AT
, breg
);
5147 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5148 macro_build (NULL
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5149 "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
5150 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5153 p
= frag_var (rs_machine_dependent
, 4 + adj
, 0,
5154 RELAX_ENCODE (16 + adj
, 4 + adj
,
5156 offset_expr
.X_add_symbol
, 0, NULL
);
5161 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5163 offset_expr
.X_add_number
= expr1
.X_add_number
;
5165 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5166 "t,o(b)", tempreg
, BFD_RELOC_MIPS_GOT_DISP
,
5170 macro_build (p
+ 4, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5171 treg
, tempreg
, breg
);
5178 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5179 "t,o(b)", tempreg
, lw_reloc_type
,
5181 if (lw_reloc_type
!= BFD_RELOC_MIPS_GOT_DISP
)
5182 p
= frag_var (rs_machine_dependent
, 0, 0,
5183 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5184 offset_expr
.X_add_symbol
, 0, NULL
);
5189 /* To avoid confusion in tc_gen_reloc, we must ensure
5190 that this does not become a variant frag. */
5191 frag_wane (frag_now
);
5195 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5199 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5200 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5201 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5203 /* This is the large GOT case. If this is a reference to an
5204 external symbol, and there is no constant, we want
5205 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5206 addu $tempreg,$tempreg,$gp
5207 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5208 or for lca or if tempreg is PIC_CALL_REG
5209 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5210 addu $tempreg,$tempreg,$gp
5211 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5212 For a local symbol, we want
5213 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5215 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5217 If we have a small constant, and this is a reference to
5218 an external symbol, we want
5219 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5220 addu $tempreg,$tempreg,$gp
5221 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5223 addiu $tempreg,$tempreg,<constant>
5224 For a local symbol, we want
5225 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5227 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5229 If we have a large constant, and this is a reference to
5230 an external symbol, we want
5231 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5232 addu $tempreg,$tempreg,$gp
5233 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5234 lui $at,<hiconstant>
5235 addiu $at,$at,<loconstant>
5236 addu $tempreg,$tempreg,$at
5237 For a local symbol, we want
5238 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5239 lui $at,<hiconstant>
5240 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5241 addu $tempreg,$tempreg,$at
5244 expr1
.X_add_number
= offset_expr
.X_add_number
;
5245 offset_expr
.X_add_number
= 0;
5247 if (reg_needs_delay (mips_gp_register
))
5251 if (expr1
.X_add_number
== 0 && breg
== 0
5252 && (call
|| tempreg
== PIC_CALL_REG
))
5254 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5255 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5257 macro_build (NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5258 tempreg
, lui_reloc_type
);
5259 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5260 tempreg
, tempreg
, mips_gp_register
);
5261 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5262 tempreg
, lw_reloc_type
, tempreg
);
5263 if (expr1
.X_add_number
== 0)
5271 /* We're going to put in an addu instruction using
5272 tempreg, so we may as well insert the nop right
5274 macro_build (NULL
, &icnt
, NULL
, "nop", "");
5278 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5279 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
5282 ? mips_opts
.warn_about_macros
5284 offset_expr
.X_add_symbol
, 0, NULL
);
5286 else if (expr1
.X_add_number
>= -0x8000
5287 && expr1
.X_add_number
< 0x8000)
5289 macro_build (NULL
, &icnt
, NULL
, "nop", "");
5290 macro_build (NULL
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5291 tempreg
, tempreg
, BFD_RELOC_LO16
);
5293 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5294 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
5296 ? mips_opts
.warn_about_macros
5298 offset_expr
.X_add_symbol
, 0, NULL
);
5304 /* If we are going to add in a base register, and the
5305 target register and the base register are the same,
5306 then we are using AT as a temporary register. Since
5307 we want to load the constant into AT, we add our
5308 current AT (from the global offset table) and the
5309 register into the register now, and pretend we were
5310 not using a base register. */
5318 assert (tempreg
== AT
);
5319 macro_build (NULL
, &icnt
, NULL
, "nop", "");
5320 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5326 /* Set mips_optimize around the lui instruction to avoid
5327 inserting an unnecessary nop after the lw. */
5328 hold_mips_optimize
= mips_optimize
;
5330 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5331 mips_optimize
= hold_mips_optimize
;
5333 macro_build (NULL
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5334 AT
, AT
, BFD_RELOC_LO16
);
5335 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5338 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
5339 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
5342 ? mips_opts
.warn_about_macros
5344 offset_expr
.X_add_symbol
, 0, NULL
);
5351 /* This is needed because this instruction uses $gp, but
5352 the first instruction on the main stream does not. */
5353 macro_build (p
, &icnt
, NULL
, "nop", "");
5357 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5358 tempreg
, local_reloc_type
, mips_gp_register
);
5360 if (expr1
.X_add_number
>= -0x8000
5361 && expr1
.X_add_number
< 0x8000)
5363 macro_build (p
, &icnt
, NULL
, "nop", "");
5365 macro_build (p
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5366 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
5367 /* FIXME: If add_number is 0, and there was no base
5368 register, the external symbol case ended with a load,
5369 so if the symbol turns out to not be external, and
5370 the next instruction uses tempreg, an unnecessary nop
5371 will be inserted. */
5377 /* We must add in the base register now, as in the
5378 external symbol case. */
5379 assert (tempreg
== AT
);
5380 macro_build (p
, &icnt
, NULL
, "nop", "");
5382 macro_build (p
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5386 /* We set breg to 0 because we have arranged to add
5387 it in in both cases. */
5391 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5393 macro_build (p
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5394 AT
, AT
, BFD_RELOC_LO16
);
5396 macro_build (p
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5397 tempreg
, tempreg
, AT
);
5401 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5404 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5405 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5408 /* This is the large GOT case. If this is a reference to an
5409 external symbol, and there is no constant, we want
5410 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5411 add $tempreg,$tempreg,$gp
5412 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5413 or for lca or if tempreg is PIC_CALL_REG
5414 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5415 add $tempreg,$tempreg,$gp
5416 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5418 If we have a small constant, and this is a reference to
5419 an external symbol, we want
5420 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5421 add $tempreg,$tempreg,$gp
5422 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5423 addi $tempreg,$tempreg,<constant>
5425 If we have a large constant, and this is a reference to
5426 an external symbol, we want
5427 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5428 addu $tempreg,$tempreg,$gp
5429 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5430 lui $at,<hiconstant>
5431 addi $at,$at,<loconstant>
5432 add $tempreg,$tempreg,$at
5434 If we have NewABI, and we know it's a local symbol, we want
5435 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5436 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5437 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5441 frag_now
->tc_frag_data
.tc_fr_offset
=
5442 expr1
.X_add_number
= offset_expr
.X_add_number
;
5443 offset_expr
.X_add_number
= 0;
5445 if (expr1
.X_add_number
== 0 && breg
== 0
5446 && (call
|| tempreg
== PIC_CALL_REG
))
5448 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5449 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5451 macro_build (NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5452 tempreg
, lui_reloc_type
);
5453 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5454 tempreg
, tempreg
, mips_gp_register
);
5455 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5456 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
5458 if (expr1
.X_add_number
== 0)
5460 p
= frag_var (rs_machine_dependent
, 8, 0,
5461 RELAX_ENCODE (12, 8, 0, 4, 0,
5462 mips_opts
.warn_about_macros
),
5463 offset_expr
.X_add_symbol
, 0, NULL
);
5465 else if (expr1
.X_add_number
>= -0x8000
5466 && expr1
.X_add_number
< 0x8000)
5468 macro_build (NULL
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5469 tempreg
, tempreg
, BFD_RELOC_LO16
);
5470 p
= frag_var (rs_machine_dependent
, 8, 0,
5471 RELAX_ENCODE (16, 8, 0, 4, 0,
5472 mips_opts
.warn_about_macros
),
5473 offset_expr
.X_add_symbol
, 0, NULL
);
5475 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5479 /* If we are going to add in a base register, and the
5480 target register and the base register are the same,
5481 then we are using AT as a temporary register. Since
5482 we want to load the constant into AT, we add our
5483 current AT (from the global offset table) and the
5484 register into the register now, and pretend we were
5485 not using a base register. */
5490 assert (tempreg
== AT
);
5491 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5497 /* Set mips_optimize around the lui instruction to avoid
5498 inserting an unnecessary nop after the lw. */
5499 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5500 macro_build (NULL
, &icnt
, &expr1
, ADDRESS_ADDI_INSN
,
5501 "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
5502 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5505 p
= frag_var (rs_machine_dependent
, 8 + adj
, 0,
5506 RELAX_ENCODE (24 + adj
, 8 + adj
,
5509 ? mips_opts
.warn_about_macros
5511 offset_expr
.X_add_symbol
, 0, NULL
);
5516 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5518 offset_expr
.X_add_number
= expr1
.X_add_number
;
5519 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5520 tempreg
, BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5521 macro_build (p
+ 4, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5522 tempreg
, tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5525 macro_build (p
+ 8, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5526 treg
, tempreg
, breg
);
5531 else if (mips_pic
== EMBEDDED_PIC
)
5534 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5536 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5537 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5546 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5547 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5549 s
= ADDRESS_ADD_INSN
;
5551 macro_build (NULL
, &icnt
, NULL
, s
, "d,v,t", treg
, tempreg
, breg
);
5560 /* The j instruction may not be used in PIC code, since it
5561 requires an absolute address. We convert it to a b
5563 if (mips_pic
== NO_PIC
)
5564 macro_build (NULL
, &icnt
, &offset_expr
, "j", "a");
5566 macro_build (NULL
, &icnt
, &offset_expr
, "b", "p");
5569 /* The jal instructions must be handled as macros because when
5570 generating PIC code they expand to multi-instruction
5571 sequences. Normally they are simple instructions. */
5576 if (mips_pic
== NO_PIC
5577 || mips_pic
== EMBEDDED_PIC
)
5578 macro_build (NULL
, &icnt
, NULL
, "jalr", "d,s", dreg
, sreg
);
5579 else if (mips_pic
== SVR4_PIC
)
5581 if (sreg
!= PIC_CALL_REG
)
5582 as_warn (_("MIPS PIC call to register other than $25"));
5584 macro_build (NULL
, &icnt
, NULL
, "jalr", "d,s", dreg
, sreg
);
5587 if (mips_cprestore_offset
< 0)
5588 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5591 if (! mips_frame_reg_valid
)
5593 as_warn (_("No .frame pseudo-op used in PIC code"));
5594 /* Quiet this warning. */
5595 mips_frame_reg_valid
= 1;
5597 if (! mips_cprestore_valid
)
5599 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5600 /* Quiet this warning. */
5601 mips_cprestore_valid
= 1;
5603 expr1
.X_add_number
= mips_cprestore_offset
;
5604 macro_build_ldst_constoffset (NULL
, &icnt
, &expr1
,
5608 HAVE_64BIT_ADDRESSES
);
5618 if (mips_pic
== NO_PIC
)
5619 macro_build (NULL
, &icnt
, &offset_expr
, "jal", "a");
5620 else if (mips_pic
== SVR4_PIC
)
5624 /* If this is a reference to an external symbol, and we are
5625 using a small GOT, we want
5626 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5630 lw $gp,cprestore($sp)
5631 The cprestore value is set using the .cprestore
5632 pseudo-op. If we are using a big GOT, we want
5633 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5635 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5639 lw $gp,cprestore($sp)
5640 If the symbol is not external, we want
5641 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5643 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5646 lw $gp,cprestore($sp)
5648 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5649 sequences above, minus nops, unless the symbol is local,
5650 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5657 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5658 "t,o(b)", PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5660 frag_var (rs_machine_dependent
, 0, 0,
5661 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5662 offset_expr
.X_add_symbol
, 0, NULL
);
5667 macro_build (NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5668 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_HI16
);
5669 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5670 PIC_CALL_REG
, PIC_CALL_REG
, mips_gp_register
);
5671 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5672 "t,o(b)", PIC_CALL_REG
,
5673 BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5674 p
= frag_var (rs_machine_dependent
, 8, 0,
5675 RELAX_ENCODE (12, 8, 0, 4, 0, 0),
5676 offset_expr
.X_add_symbol
, 0, NULL
);
5677 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5678 "t,o(b)", PIC_CALL_REG
,
5679 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5680 macro_build (p
+ 4, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
,
5681 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5682 BFD_RELOC_MIPS_GOT_OFST
);
5685 macro_build_jalr (icnt
, &offset_expr
);
5692 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5693 "t,o(b)", PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5695 macro_build (NULL
, &icnt
, NULL
, "nop", "");
5696 p
= frag_var (rs_machine_dependent
, 4, 0,
5697 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5698 offset_expr
.X_add_symbol
, 0, NULL
);
5704 if (reg_needs_delay (mips_gp_register
))
5708 macro_build (NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5709 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_HI16
);
5710 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5711 PIC_CALL_REG
, PIC_CALL_REG
, mips_gp_register
);
5712 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5713 "t,o(b)", PIC_CALL_REG
,
5714 BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5715 macro_build (NULL
, &icnt
, NULL
, "nop", "");
5716 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5717 RELAX_ENCODE (16, 12 + gpdel
, gpdel
,
5719 offset_expr
.X_add_symbol
, 0, NULL
);
5722 macro_build (p
, &icnt
, NULL
, "nop", "");
5725 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
5726 "t,o(b)", PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5729 macro_build (p
, &icnt
, NULL
, "nop", "");
5732 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
,
5733 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5735 macro_build_jalr (icnt
, &offset_expr
);
5737 if (mips_cprestore_offset
< 0)
5738 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5741 if (! mips_frame_reg_valid
)
5743 as_warn (_("No .frame pseudo-op used in PIC code"));
5744 /* Quiet this warning. */
5745 mips_frame_reg_valid
= 1;
5747 if (! mips_cprestore_valid
)
5749 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5750 /* Quiet this warning. */
5751 mips_cprestore_valid
= 1;
5753 if (mips_opts
.noreorder
)
5754 macro_build (NULL
, &icnt
, NULL
, "nop", "");
5755 expr1
.X_add_number
= mips_cprestore_offset
;
5756 macro_build_ldst_constoffset (NULL
, &icnt
, &expr1
,
5760 HAVE_64BIT_ADDRESSES
);
5764 else if (mips_pic
== EMBEDDED_PIC
)
5766 macro_build (NULL
, &icnt
, &offset_expr
, "bal", "p");
5767 /* The linker may expand the call to a longer sequence which
5768 uses $at, so we must break rather than return. */
5793 /* Itbl support may require additional care here. */
5798 /* Itbl support may require additional care here. */
5803 /* Itbl support may require additional care here. */
5808 /* Itbl support may require additional care here. */
5820 if (mips_opts
.arch
== CPU_R4650
)
5822 as_bad (_("opcode not supported on this processor"));
5826 /* Itbl support may require additional care here. */
5831 /* Itbl support may require additional care here. */
5836 /* Itbl support may require additional care here. */
5856 if (breg
== treg
|| coproc
|| lr
)
5878 /* Itbl support may require additional care here. */
5883 /* Itbl support may require additional care here. */
5888 /* Itbl support may require additional care here. */
5893 /* Itbl support may require additional care here. */
5909 if (mips_opts
.arch
== CPU_R4650
)
5911 as_bad (_("opcode not supported on this processor"));
5916 /* Itbl support may require additional care here. */
5920 /* Itbl support may require additional care here. */
5925 /* Itbl support may require additional care here. */
5937 /* Itbl support may require additional care here. */
5938 if (mask
== M_LWC1_AB
5939 || mask
== M_SWC1_AB
5940 || mask
== M_LDC1_AB
5941 || mask
== M_SDC1_AB
5950 /* Sign-extending 32-bit constants makes their handling easier.
5951 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5953 if ((! HAVE_64BIT_ADDRESSES
5954 && (! HAVE_64BIT_GPRS
&& offset_expr
.X_op
== O_constant
))
5955 && (offset_expr
.X_op
== O_constant
)
5956 && ! ((offset_expr
.X_add_number
& ~((bfd_vma
) 0x7fffffff))
5957 == ~((bfd_vma
) 0x7fffffff)))
5959 if (offset_expr
.X_add_number
& ~((bfd_vma
) 0xffffffff))
5960 as_bad (_("constant too large"));
5962 offset_expr
.X_add_number
= (((offset_expr
.X_add_number
& 0xffffffff)
5963 ^ 0x80000000) - 0x80000000);
5966 /* For embedded PIC, we allow loads where the offset is calculated
5967 by subtracting a symbol in the current segment from an unknown
5968 symbol, relative to a base register, e.g.:
5969 <op> $treg, <sym>-<localsym>($breg)
5970 This is used by the compiler for switch statements. */
5971 if (mips_pic
== EMBEDDED_PIC
5972 && offset_expr
.X_op
== O_subtract
5973 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5974 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5975 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5977 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5981 && (offset_expr
.X_add_number
== 0
5982 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5984 /* For this case, we output the instructions:
5985 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5986 addiu $tempreg,$tempreg,$breg
5987 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5988 If the relocation would fit entirely in 16 bits, it would be
5990 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5991 instead, but that seems quite difficult. */
5992 macro_build (NULL
, &icnt
, &offset_expr
, "lui", "t,u", tempreg
,
5993 BFD_RELOC_PCREL_HI16_S
);
5994 macro_build (NULL
, &icnt
, NULL
,
5995 ((bfd_arch_bits_per_address (stdoutput
) == 32
5996 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5997 ? "addu" : "daddu"),
5998 "d,v,t", tempreg
, tempreg
, breg
);
5999 macro_build (NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6000 BFD_RELOC_PCREL_LO16
, tempreg
);
6006 if (offset_expr
.X_op
!= O_constant
6007 && offset_expr
.X_op
!= O_symbol
)
6009 as_bad (_("expression too complex"));
6010 offset_expr
.X_op
= O_constant
;
6013 /* A constant expression in PIC code can be handled just as it
6014 is in non PIC code. */
6015 if (mips_pic
== NO_PIC
6016 || offset_expr
.X_op
== O_constant
)
6020 /* If this is a reference to a GP relative symbol, and there
6021 is no base register, we want
6022 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6023 Otherwise, if there is no base register, we want
6024 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6025 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6026 If we have a constant, we need two instructions anyhow,
6027 so we always use the latter form.
6029 If we have a base register, and this is a reference to a
6030 GP relative symbol, we want
6031 addu $tempreg,$breg,$gp
6032 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6034 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6035 addu $tempreg,$tempreg,$breg
6036 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6037 With a constant we always use the latter case.
6039 With 64bit address space and no base register and $at usable,
6041 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6042 lui $at,<sym> (BFD_RELOC_HI16_S)
6043 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6046 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6047 If we have a base register, we want
6048 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6049 lui $at,<sym> (BFD_RELOC_HI16_S)
6050 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6054 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6056 Without $at we can't generate the optimal path for superscalar
6057 processors here since this would require two temporary registers.
6058 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6059 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6061 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6063 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6064 If we have a base register, we want
6065 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6066 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6068 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6070 daddu $tempreg,$tempreg,$breg
6071 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6073 If we have 64-bit addresses, as an optimization, for
6074 addresses which are 32-bit constants (e.g. kseg0/kseg1
6075 addresses) we fall back to the 32-bit address generation
6076 mechanism since it is more efficient. Note that due to
6077 the signed offset used by memory operations, the 32-bit
6078 range is shifted down by 32768 here. This code should
6079 probably attempt to generate 64-bit constants more
6080 efficiently in general.
6082 As an extension for architectures with 64-bit registers,
6083 we don't truncate 64-bit addresses given as literal
6084 constants down to 32 bits, to support existing practice
6085 in the mips64 Linux (the kernel), that compiles source
6086 files with -mabi=64, assembling them as o32 or n32 (with
6087 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6088 the whole kernel is loaded into a memory region that is
6089 addressable with sign-extended 32-bit addresses, it is
6090 wasteful to compute the upper 32 bits of every
6091 non-literal address, that takes more space and time.
6092 Some day this should probably be implemented as an
6093 assembler option, such that the kernel doesn't have to
6094 use such ugly hacks, even though it will still have to
6095 end up converting the binary to ELF32 for a number of
6096 platforms whose boot loaders don't support ELF64
6098 if ((HAVE_64BIT_ADDRESSES
6099 && ! (offset_expr
.X_op
== O_constant
6100 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
6102 && offset_expr
.X_op
== O_constant
6103 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
6107 /* We don't do GP optimization for now because RELAX_ENCODE can't
6108 hold the data for such large chunks. */
6110 if (used_at
== 0 && ! mips_opts
.noat
)
6112 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
6113 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
6114 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
6115 AT
, BFD_RELOC_HI16_S
);
6116 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
6117 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
6119 macro_build (p
, &icnt
, NULL
, "daddu", "d,v,t",
6121 macro_build (p
, &icnt
, NULL
, "dsll32", "d,w,<",
6122 tempreg
, tempreg
, 0);
6123 macro_build (p
, &icnt
, NULL
, "daddu", "d,v,t",
6124 tempreg
, tempreg
, AT
);
6125 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6126 BFD_RELOC_LO16
, tempreg
);
6131 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
6132 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
6133 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
6134 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
6135 macro_build (p
, &icnt
, NULL
, "dsll", "d,w,<",
6136 tempreg
, tempreg
, 16);
6137 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
6138 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
6139 macro_build (p
, &icnt
, NULL
, "dsll", "d,w,<",
6140 tempreg
, tempreg
, 16);
6142 macro_build (p
, &icnt
, NULL
, "daddu", "d,v,t",
6143 tempreg
, tempreg
, breg
);
6144 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6145 BFD_RELOC_LO16
, tempreg
);
6151 if (offset_expr
.X_op
== O_constant
6152 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000))
6153 as_bad (_("load/store address overflow (max 32 bits)"));
6157 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6158 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6163 macro_build (NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6164 BFD_RELOC_GPREL16
, mips_gp_register
);
6165 p
= frag_var (rs_machine_dependent
, 8, 0,
6166 RELAX_ENCODE (4, 8, 0, 4, 0,
6167 (mips_opts
.warn_about_macros
6169 && mips_opts
.noat
))),
6170 offset_expr
.X_add_symbol
, 0, NULL
);
6173 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
6176 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6177 BFD_RELOC_LO16
, tempreg
);
6181 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6182 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6187 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6188 tempreg
, breg
, mips_gp_register
);
6189 macro_build (NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6190 BFD_RELOC_GPREL16
, tempreg
);
6191 p
= frag_var (rs_machine_dependent
, 12, 0,
6192 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
6193 offset_expr
.X_add_symbol
, 0, NULL
);
6195 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
6198 macro_build (p
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6199 tempreg
, tempreg
, breg
);
6202 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6203 BFD_RELOC_LO16
, tempreg
);
6206 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6209 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6211 /* If this is a reference to an external symbol, we want
6212 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6214 <op> $treg,0($tempreg)
6216 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6218 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6219 <op> $treg,0($tempreg)
6222 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6223 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6225 If there is a base register, we add it to $tempreg before
6226 the <op>. If there is a constant, we stick it in the
6227 <op> instruction. We don't handle constants larger than
6228 16 bits, because we have no way to load the upper 16 bits
6229 (actually, we could handle them for the subset of cases
6230 in which we are not using $at). */
6231 assert (offset_expr
.X_op
== O_symbol
);
6234 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
6235 "t,o(b)", tempreg
, BFD_RELOC_MIPS_GOT_PAGE
,
6238 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6239 tempreg
, tempreg
, breg
);
6240 macro_build (NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6241 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6248 expr1
.X_add_number
= offset_expr
.X_add_number
;
6249 offset_expr
.X_add_number
= 0;
6250 if (expr1
.X_add_number
< -0x8000
6251 || expr1
.X_add_number
>= 0x8000)
6252 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6254 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6255 tempreg
, lw_reloc_type
, mips_gp_register
);
6256 macro_build (NULL
, &icnt
, NULL
, "nop", "");
6257 p
= frag_var (rs_machine_dependent
, 4, 0,
6258 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
6259 offset_expr
.X_add_symbol
, 0, NULL
);
6260 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
,
6261 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
6263 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6264 tempreg
, tempreg
, breg
);
6265 macro_build (NULL
, &icnt
, &expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6268 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6273 /* If this is a reference to an external symbol, we want
6274 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6275 addu $tempreg,$tempreg,$gp
6276 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6277 <op> $treg,0($tempreg)
6279 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6281 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6282 <op> $treg,0($tempreg)
6283 If there is a base register, we add it to $tempreg before
6284 the <op>. If there is a constant, we stick it in the
6285 <op> instruction. We don't handle constants larger than
6286 16 bits, because we have no way to load the upper 16 bits
6287 (actually, we could handle them for the subset of cases
6288 in which we are not using $at). */
6289 assert (offset_expr
.X_op
== O_symbol
);
6290 expr1
.X_add_number
= offset_expr
.X_add_number
;
6291 offset_expr
.X_add_number
= 0;
6292 if (expr1
.X_add_number
< -0x8000
6293 || expr1
.X_add_number
>= 0x8000)
6294 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6295 if (reg_needs_delay (mips_gp_register
))
6300 macro_build (NULL
, &icnt
, &offset_expr
, "lui", "t,u", tempreg
,
6301 BFD_RELOC_MIPS_GOT_HI16
);
6302 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6303 tempreg
, tempreg
, mips_gp_register
);
6304 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6305 tempreg
, BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6306 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
6307 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
6308 offset_expr
.X_add_symbol
, 0, NULL
);
6311 macro_build (p
, &icnt
, NULL
, "nop", "");
6314 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6315 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6317 macro_build (p
, &icnt
, NULL
, "nop", "");
6319 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6320 tempreg
, tempreg
, BFD_RELOC_LO16
);
6322 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6323 tempreg
, tempreg
, breg
);
6324 macro_build (NULL
, &icnt
, &expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6327 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6330 int bregsz
= breg
!= 0 ? 4 : 0;
6332 /* If this is a reference to an external symbol, we want
6333 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6334 add $tempreg,$tempreg,$gp
6335 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6336 <op> $treg,<ofst>($tempreg)
6337 Otherwise, for local symbols, we want:
6338 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6339 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6340 assert (offset_expr
.X_op
== O_symbol
);
6342 frag_now
->tc_frag_data
.tc_fr_offset
=
6343 expr1
.X_add_number
= offset_expr
.X_add_number
;
6344 offset_expr
.X_add_number
= 0;
6345 if (expr1
.X_add_number
< -0x8000
6346 || expr1
.X_add_number
>= 0x8000)
6347 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6348 macro_build (NULL
, &icnt
, &offset_expr
, "lui", "t,u", tempreg
,
6349 BFD_RELOC_MIPS_GOT_HI16
);
6350 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6351 tempreg
, tempreg
, mips_gp_register
);
6352 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6353 tempreg
, BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6355 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6356 tempreg
, tempreg
, breg
);
6357 macro_build (NULL
, &icnt
, &expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6360 offset_expr
.X_add_number
= expr1
.X_add_number
;
6361 p
= frag_var (rs_machine_dependent
, 12 + bregsz
, 0,
6362 RELAX_ENCODE (16 + bregsz
, 8 + bregsz
,
6363 0, 4 + bregsz
, 0, 0),
6364 offset_expr
.X_add_symbol
, 0, NULL
);
6365 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6366 tempreg
, BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6368 macro_build (p
+ 4, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6369 tempreg
, tempreg
, breg
);
6370 macro_build (p
+ 4 + bregsz
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6371 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6373 else if (mips_pic
== EMBEDDED_PIC
)
6375 /* If there is no base register, we want
6376 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6377 If there is a base register, we want
6378 addu $tempreg,$breg,$gp
6379 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6381 assert (offset_expr
.X_op
== O_symbol
);
6384 macro_build (NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6385 BFD_RELOC_GPREL16
, mips_gp_register
);
6390 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6391 tempreg
, breg
, mips_gp_register
);
6392 macro_build (NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
6393 BFD_RELOC_GPREL16
, tempreg
);
6406 load_register (&icnt
, treg
, &imm_expr
, 0);
6410 load_register (&icnt
, treg
, &imm_expr
, 1);
6414 if (imm_expr
.X_op
== O_constant
)
6416 load_register (&icnt
, AT
, &imm_expr
, 0);
6417 macro_build (NULL
, &icnt
, NULL
, "mtc1", "t,G", AT
, treg
);
6422 assert (offset_expr
.X_op
== O_symbol
6423 && strcmp (segment_name (S_GET_SEGMENT
6424 (offset_expr
.X_add_symbol
)),
6426 && offset_expr
.X_add_number
== 0);
6427 macro_build (NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)", treg
,
6428 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6433 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6434 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6435 order 32 bits of the value and the low order 32 bits are either
6436 zero or in OFFSET_EXPR. */
6437 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6439 if (HAVE_64BIT_GPRS
)
6440 load_register (&icnt
, treg
, &imm_expr
, 1);
6445 if (target_big_endian
)
6457 load_register (&icnt
, hreg
, &imm_expr
, 0);
6460 if (offset_expr
.X_op
== O_absent
)
6461 move_register (&icnt
, lreg
, 0);
6464 assert (offset_expr
.X_op
== O_constant
);
6465 load_register (&icnt
, lreg
, &offset_expr
, 0);
6472 /* We know that sym is in the .rdata section. First we get the
6473 upper 16 bits of the address. */
6474 if (mips_pic
== NO_PIC
)
6476 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6478 else if (mips_pic
== SVR4_PIC
)
6480 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6481 AT
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6483 else if (mips_pic
== EMBEDDED_PIC
)
6485 /* For embedded PIC we pick up the entire address off $gp in
6486 a single instruction. */
6487 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6488 AT
, mips_gp_register
, BFD_RELOC_GPREL16
);
6489 offset_expr
.X_op
= O_constant
;
6490 offset_expr
.X_add_number
= 0;
6495 /* Now we load the register(s). */
6496 if (HAVE_64BIT_GPRS
)
6497 macro_build (NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)", treg
,
6498 BFD_RELOC_LO16
, AT
);
6501 macro_build (NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)", treg
,
6502 BFD_RELOC_LO16
, AT
);
6505 /* FIXME: How in the world do we deal with the possible
6507 offset_expr
.X_add_number
+= 4;
6508 macro_build (NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6509 treg
+ 1, BFD_RELOC_LO16
, AT
);
6513 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6514 does not become a variant frag. */
6515 frag_wane (frag_now
);
6521 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6522 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6523 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6524 the value and the low order 32 bits are either zero or in
6526 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6528 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6529 if (HAVE_64BIT_FPRS
)
6531 assert (HAVE_64BIT_GPRS
);
6532 macro_build (NULL
, &icnt
, NULL
, "dmtc1", "t,S", AT
, treg
);
6536 macro_build (NULL
, &icnt
, NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6537 if (offset_expr
.X_op
== O_absent
)
6538 macro_build (NULL
, &icnt
, NULL
, "mtc1", "t,G", 0, treg
);
6541 assert (offset_expr
.X_op
== O_constant
);
6542 load_register (&icnt
, AT
, &offset_expr
, 0);
6543 macro_build (NULL
, &icnt
, NULL
, "mtc1", "t,G", AT
, treg
);
6549 assert (offset_expr
.X_op
== O_symbol
6550 && offset_expr
.X_add_number
== 0);
6551 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6552 if (strcmp (s
, ".lit8") == 0)
6554 if (mips_opts
.isa
!= ISA_MIPS1
)
6556 macro_build (NULL
, &icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
,
6557 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6560 breg
= mips_gp_register
;
6561 r
= BFD_RELOC_MIPS_LITERAL
;
6566 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6567 if (mips_pic
== SVR4_PIC
)
6568 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
,
6569 "t,o(b)", AT
, BFD_RELOC_MIPS_GOT16
,
6573 /* FIXME: This won't work for a 64 bit address. */
6574 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6577 if (mips_opts
.isa
!= ISA_MIPS1
)
6579 macro_build (NULL
, &icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
,
6580 BFD_RELOC_LO16
, AT
);
6582 /* To avoid confusion in tc_gen_reloc, we must ensure
6583 that this does not become a variant frag. */
6584 frag_wane (frag_now
);
6595 if (mips_opts
.arch
== CPU_R4650
)
6597 as_bad (_("opcode not supported on this processor"));
6600 /* Even on a big endian machine $fn comes before $fn+1. We have
6601 to adjust when loading from memory. */
6604 assert (mips_opts
.isa
== ISA_MIPS1
);
6605 macro_build (NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6606 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6607 /* FIXME: A possible overflow which I don't know how to deal
6609 offset_expr
.X_add_number
+= 4;
6610 macro_build (NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6611 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6613 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6614 does not become a variant frag. */
6615 frag_wane (frag_now
);
6624 * The MIPS assembler seems to check for X_add_number not
6625 * being double aligned and generating:
6628 * addiu at,at,%lo(foo+1)
6631 * But, the resulting address is the same after relocation so why
6632 * generate the extra instruction?
6634 if (mips_opts
.arch
== CPU_R4650
)
6636 as_bad (_("opcode not supported on this processor"));
6639 /* Itbl support may require additional care here. */
6641 if (mips_opts
.isa
!= ISA_MIPS1
)
6652 if (mips_opts
.arch
== CPU_R4650
)
6654 as_bad (_("opcode not supported on this processor"));
6658 if (mips_opts
.isa
!= ISA_MIPS1
)
6666 /* Itbl support may require additional care here. */
6671 if (HAVE_64BIT_GPRS
)
6682 if (HAVE_64BIT_GPRS
)
6692 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6693 loads for the case of doing a pair of loads to simulate an 'ld'.
6694 This is not currently done by the compiler, and assembly coders
6695 writing embedded-pic code can cope. */
6697 if (offset_expr
.X_op
!= O_symbol
6698 && offset_expr
.X_op
!= O_constant
)
6700 as_bad (_("expression too complex"));
6701 offset_expr
.X_op
= O_constant
;
6704 /* Even on a big endian machine $fn comes before $fn+1. We have
6705 to adjust when loading from memory. We set coproc if we must
6706 load $fn+1 first. */
6707 /* Itbl support may require additional care here. */
6708 if (! target_big_endian
)
6711 if (mips_pic
== NO_PIC
6712 || offset_expr
.X_op
== O_constant
)
6716 /* If this is a reference to a GP relative symbol, we want
6717 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6718 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6719 If we have a base register, we use this
6721 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6722 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6723 If this is not a GP relative symbol, we want
6724 lui $at,<sym> (BFD_RELOC_HI16_S)
6725 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6726 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6727 If there is a base register, we add it to $at after the
6728 lui instruction. If there is a constant, we always use
6730 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6731 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6743 tempreg
= mips_gp_register
;
6750 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6751 AT
, breg
, mips_gp_register
);
6757 /* Itbl support may require additional care here. */
6758 macro_build (NULL
, &icnt
, &offset_expr
, s
, fmt
,
6759 coproc
? treg
+ 1 : treg
,
6760 BFD_RELOC_GPREL16
, tempreg
);
6761 offset_expr
.X_add_number
+= 4;
6763 /* Set mips_optimize to 2 to avoid inserting an
6765 hold_mips_optimize
= mips_optimize
;
6767 /* Itbl support may require additional care here. */
6768 macro_build (NULL
, &icnt
, &offset_expr
, s
, fmt
,
6769 coproc
? treg
: treg
+ 1,
6770 BFD_RELOC_GPREL16
, tempreg
);
6771 mips_optimize
= hold_mips_optimize
;
6773 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6774 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6775 used_at
&& mips_opts
.noat
),
6776 offset_expr
.X_add_symbol
, 0, NULL
);
6778 /* We just generated two relocs. When tc_gen_reloc
6779 handles this case, it will skip the first reloc and
6780 handle the second. The second reloc already has an
6781 extra addend of 4, which we added above. We must
6782 subtract it out, and then subtract another 4 to make
6783 the first reloc come out right. The second reloc
6784 will come out right because we are going to add 4 to
6785 offset_expr when we build its instruction below.
6787 If we have a symbol, then we don't want to include
6788 the offset, because it will wind up being included
6789 when we generate the reloc. */
6791 if (offset_expr
.X_op
== O_constant
)
6792 offset_expr
.X_add_number
-= 8;
6795 offset_expr
.X_add_number
= -4;
6796 offset_expr
.X_op
= O_constant
;
6799 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6804 macro_build (p
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6809 /* Itbl support may require additional care here. */
6810 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6811 coproc
? treg
+ 1 : treg
,
6812 BFD_RELOC_LO16
, AT
);
6815 /* FIXME: How do we handle overflow here? */
6816 offset_expr
.X_add_number
+= 4;
6817 /* Itbl support may require additional care here. */
6818 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6819 coproc
? treg
: treg
+ 1,
6820 BFD_RELOC_LO16
, AT
);
6822 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6826 /* If this is a reference to an external symbol, we want
6827 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6832 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6834 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6835 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6836 If there is a base register we add it to $at before the
6837 lwc1 instructions. If there is a constant we include it
6838 in the lwc1 instructions. */
6840 expr1
.X_add_number
= offset_expr
.X_add_number
;
6841 offset_expr
.X_add_number
= 0;
6842 if (expr1
.X_add_number
< -0x8000
6843 || expr1
.X_add_number
>= 0x8000 - 4)
6844 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6849 frag_grow (24 + off
);
6850 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6851 AT
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6852 macro_build (NULL
, &icnt
, NULL
, "nop", "");
6854 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6856 /* Itbl support may require additional care here. */
6857 macro_build (NULL
, &icnt
, &expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6858 BFD_RELOC_LO16
, AT
);
6859 expr1
.X_add_number
+= 4;
6861 /* Set mips_optimize to 2 to avoid inserting an undesired
6863 hold_mips_optimize
= mips_optimize
;
6865 /* Itbl support may require additional care here. */
6866 macro_build (NULL
, &icnt
, &expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6867 BFD_RELOC_LO16
, AT
);
6868 mips_optimize
= hold_mips_optimize
;
6870 (void) frag_var (rs_machine_dependent
, 0, 0,
6871 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6872 offset_expr
.X_add_symbol
, 0, NULL
);
6874 else if (mips_pic
== SVR4_PIC
)
6879 /* If this is a reference to an external symbol, we want
6880 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6882 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6887 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6889 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6890 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6891 If there is a base register we add it to $at before the
6892 lwc1 instructions. If there is a constant we include it
6893 in the lwc1 instructions. */
6895 expr1
.X_add_number
= offset_expr
.X_add_number
;
6896 offset_expr
.X_add_number
= 0;
6897 if (expr1
.X_add_number
< -0x8000
6898 || expr1
.X_add_number
>= 0x8000 - 4)
6899 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6900 if (reg_needs_delay (mips_gp_register
))
6909 macro_build (NULL
, &icnt
, &offset_expr
, "lui", "t,u", AT
,
6910 BFD_RELOC_MIPS_GOT_HI16
);
6911 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6912 AT
, AT
, mips_gp_register
);
6913 macro_build (NULL
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6914 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6915 macro_build (NULL
, &icnt
, NULL
, "nop", "");
6917 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6919 /* Itbl support may require additional care here. */
6920 macro_build (NULL
, &icnt
, &expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6921 BFD_RELOC_LO16
, AT
);
6922 expr1
.X_add_number
+= 4;
6924 /* Set mips_optimize to 2 to avoid inserting an undesired
6926 hold_mips_optimize
= mips_optimize
;
6928 /* Itbl support may require additional care here. */
6929 macro_build (NULL
, &icnt
, &expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6930 BFD_RELOC_LO16
, AT
);
6931 mips_optimize
= hold_mips_optimize
;
6932 expr1
.X_add_number
-= 4;
6934 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6935 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6936 8 + gpdel
+ off
, 1, 0),
6937 offset_expr
.X_add_symbol
, 0, NULL
);
6940 macro_build (p
, &icnt
, NULL
, "nop", "");
6943 macro_build (p
, &icnt
, &offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6944 AT
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6946 macro_build (p
, &icnt
, NULL
, "nop", "");
6950 macro_build (p
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6954 /* Itbl support may require additional care here. */
6955 macro_build (p
, &icnt
, &expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6956 BFD_RELOC_LO16
, AT
);
6958 expr1
.X_add_number
+= 4;
6960 /* Set mips_optimize to 2 to avoid inserting an undesired
6962 hold_mips_optimize
= mips_optimize
;
6964 /* Itbl support may require additional care here. */
6965 macro_build (p
, &icnt
, &expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6966 BFD_RELOC_LO16
, AT
);
6967 mips_optimize
= hold_mips_optimize
;
6969 else if (mips_pic
== EMBEDDED_PIC
)
6971 /* If there is no base register, we use
6972 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6973 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6974 If we have a base register, we use
6976 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6977 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6981 tempreg
= mips_gp_register
;
6986 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6987 AT
, breg
, mips_gp_register
);
6992 /* Itbl support may require additional care here. */
6993 macro_build (NULL
, &icnt
, &offset_expr
, s
, fmt
,
6994 coproc
? treg
+ 1 : treg
,
6995 BFD_RELOC_GPREL16
, tempreg
);
6996 offset_expr
.X_add_number
+= 4;
6997 /* Itbl support may require additional care here. */
6998 macro_build (NULL
, &icnt
, &offset_expr
, s
, fmt
,
6999 coproc
? treg
: treg
+ 1,
7000 BFD_RELOC_GPREL16
, tempreg
);
7016 assert (HAVE_32BIT_ADDRESSES
);
7017 macro_build (NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7018 BFD_RELOC_LO16
, breg
);
7019 offset_expr
.X_add_number
+= 4;
7020 macro_build (NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
7021 BFD_RELOC_LO16
, breg
);
7024 /* New code added to support COPZ instructions.
7025 This code builds table entries out of the macros in mip_opcodes.
7026 R4000 uses interlocks to handle coproc delays.
7027 Other chips (like the R3000) require nops to be inserted for delays.
7029 FIXME: Currently, we require that the user handle delays.
7030 In order to fill delay slots for non-interlocked chips,
7031 we must have a way to specify delays based on the coprocessor.
7032 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7033 What are the side-effects of the cop instruction?
7034 What cache support might we have and what are its effects?
7035 Both coprocessor & memory require delays. how long???
7036 What registers are read/set/modified?
7038 If an itbl is provided to interpret cop instructions,
7039 this knowledge can be encoded in the itbl spec. */
7053 /* For now we just do C (same as Cz). The parameter will be
7054 stored in insn_opcode by mips_ip. */
7055 macro_build (NULL
, &icnt
, NULL
, s
, "C", ip
->insn_opcode
);
7059 move_register (&icnt
, dreg
, sreg
);
7062 #ifdef LOSING_COMPILER
7064 /* Try and see if this is a new itbl instruction.
7065 This code builds table entries out of the macros in mip_opcodes.
7066 FIXME: For now we just assemble the expression and pass it's
7067 value along as a 32-bit immediate.
7068 We may want to have the assembler assemble this value,
7069 so that we gain the assembler's knowledge of delay slots,
7071 Would it be more efficient to use mask (id) here? */
7072 if (itbl_have_entries
7073 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7075 s
= ip
->insn_mo
->name
;
7077 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7078 macro_build (NULL
, &icnt
, &immed_expr
, s
, "C");
7085 as_warn (_("Macro used $at after \".set noat\""));
7089 macro2 (struct mips_cl_insn
*ip
)
7091 register int treg
, sreg
, dreg
, breg
;
7107 bfd_reloc_code_real_type r
;
7110 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7111 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7112 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7113 mask
= ip
->insn_mo
->mask
;
7115 expr1
.X_op
= O_constant
;
7116 expr1
.X_op_symbol
= NULL
;
7117 expr1
.X_add_symbol
= NULL
;
7118 expr1
.X_add_number
= 1;
7122 #endif /* LOSING_COMPILER */
7127 macro_build (NULL
, &icnt
, NULL
, dbl
? "dmultu" : "multu", "s,t",
7129 macro_build (NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
7135 /* The MIPS assembler some times generates shifts and adds. I'm
7136 not trying to be that fancy. GCC should do this for us
7138 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7139 macro_build (NULL
, &icnt
, NULL
, dbl
? "dmult" : "mult", "s,t",
7141 macro_build (NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
7154 mips_emit_delays (TRUE
);
7155 ++mips_opts
.noreorder
;
7156 mips_any_noreorder
= 1;
7158 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7159 macro_build (NULL
, &icnt
, NULL
, dbl
? "dmult" : "mult", "s,t",
7160 sreg
, imm
? AT
: treg
);
7161 macro_build (NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
7162 macro_build (NULL
, &icnt
, NULL
, dbl
? "dsra32" : "sra", "d,w,<",
7164 macro_build (NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
7166 macro_build (NULL
, &icnt
, NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7169 expr1
.X_add_number
= 8;
7170 macro_build (NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
7171 macro_build (NULL
, &icnt
, NULL
, "nop", "", 0);
7172 macro_build (NULL
, &icnt
, NULL
, "break", "c", 6);
7174 --mips_opts
.noreorder
;
7175 macro_build (NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
7188 mips_emit_delays (TRUE
);
7189 ++mips_opts
.noreorder
;
7190 mips_any_noreorder
= 1;
7192 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7193 macro_build (NULL
, &icnt
, NULL
, dbl
? "dmultu" : "multu", "s,t",
7194 sreg
, imm
? AT
: treg
);
7195 macro_build (NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
7196 macro_build (NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
7198 macro_build (NULL
, &icnt
, NULL
, "tne", "s,t,q", AT
, 0, 6);
7201 expr1
.X_add_number
= 8;
7202 macro_build (NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
7203 macro_build (NULL
, &icnt
, NULL
, "nop", "", 0);
7204 macro_build (NULL
, &icnt
, NULL
, "break", "c", 6);
7206 --mips_opts
.noreorder
;
7210 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7222 macro_build (NULL
, &icnt
, NULL
, "dnegu", "d,w", tempreg
, treg
);
7223 macro_build (NULL
, &icnt
, NULL
, "drorv", "d,t,s", dreg
, sreg
,
7229 macro_build (NULL
, &icnt
, NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7230 macro_build (NULL
, &icnt
, NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7231 macro_build (NULL
, &icnt
, NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7232 macro_build (NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7236 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7248 macro_build (NULL
, &icnt
, NULL
, "negu", "d,w", tempreg
, treg
);
7249 macro_build (NULL
, &icnt
, NULL
, "rorv", "d,t,s", dreg
, sreg
,
7255 macro_build (NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
7256 macro_build (NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7257 macro_build (NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7258 macro_build (NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7266 if (imm_expr
.X_op
!= O_constant
)
7267 as_bad (_("Improper rotate count"));
7268 rot
= imm_expr
.X_add_number
& 0x3f;
7269 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7271 rot
= (64 - rot
) & 0x3f;
7273 macro_build (NULL
, &icnt
, NULL
, "dror32", "d,w,<",
7274 dreg
, sreg
, rot
- 32);
7276 macro_build (NULL
, &icnt
, NULL
, "dror", "d,w,<",
7282 macro_build (NULL
, &icnt
, NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7285 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7286 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7288 macro_build (NULL
, &icnt
, NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7289 macro_build (NULL
, &icnt
, NULL
, r
, "d,w,<", dreg
, sreg
,
7290 (0x20 - rot
) & 0x1f);
7291 macro_build (NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7299 if (imm_expr
.X_op
!= O_constant
)
7300 as_bad (_("Improper rotate count"));
7301 rot
= imm_expr
.X_add_number
& 0x1f;
7302 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7304 macro_build (NULL
, &icnt
, NULL
, "ror", "d,w,<", dreg
, sreg
,
7310 macro_build (NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7313 macro_build (NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7314 macro_build (NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
7315 (0x20 - rot
) & 0x1f);
7316 macro_build (NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7321 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7323 macro_build (NULL
, &icnt
, NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7326 macro_build (NULL
, &icnt
, NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7327 macro_build (NULL
, &icnt
, NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7328 macro_build (NULL
, &icnt
, NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7329 macro_build (NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7333 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7335 macro_build (NULL
, &icnt
, NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7338 macro_build (NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
7339 macro_build (NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7340 macro_build (NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7341 macro_build (NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7349 if (imm_expr
.X_op
!= O_constant
)
7350 as_bad (_("Improper rotate count"));
7351 rot
= imm_expr
.X_add_number
& 0x3f;
7352 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7355 macro_build (NULL
, &icnt
, NULL
, "dror32", "d,w,<",
7356 dreg
, sreg
, rot
- 32);
7358 macro_build (NULL
, &icnt
, NULL
, "dror", "d,w,<",
7364 macro_build (NULL
, &icnt
, NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7367 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7368 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7370 macro_build (NULL
, &icnt
, NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7371 macro_build (NULL
, &icnt
, NULL
, l
, "d,w,<", dreg
, sreg
,
7372 (0x20 - rot
) & 0x1f);
7373 macro_build (NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7381 if (imm_expr
.X_op
!= O_constant
)
7382 as_bad (_("Improper rotate count"));
7383 rot
= imm_expr
.X_add_number
& 0x1f;
7384 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7386 macro_build (NULL
, &icnt
, NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7391 macro_build (NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7394 macro_build (NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7395 macro_build (NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
7396 (0x20 - rot
) & 0x1f);
7397 macro_build (NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7402 if (mips_opts
.arch
== CPU_R4650
)
7404 as_bad (_("opcode not supported on this processor"));
7407 assert (mips_opts
.isa
== ISA_MIPS1
);
7408 /* Even on a big endian machine $fn comes before $fn+1. We have
7409 to adjust when storing to memory. */
7410 macro_build (NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7411 target_big_endian
? treg
+ 1 : treg
,
7412 BFD_RELOC_LO16
, breg
);
7413 offset_expr
.X_add_number
+= 4;
7414 macro_build (NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7415 target_big_endian
? treg
: treg
+ 1,
7416 BFD_RELOC_LO16
, breg
);
7421 macro_build (NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, treg
,
7424 macro_build (NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
,
7428 macro_build (NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7429 macro_build (NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
7435 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7437 macro_build (NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
,
7443 as_warn (_("Instruction %s: result is always false"),
7445 move_register (&icnt
, dreg
, 0);
7448 if (imm_expr
.X_op
== O_constant
7449 && imm_expr
.X_add_number
>= 0
7450 && imm_expr
.X_add_number
< 0x10000)
7452 macro_build (NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
,
7456 else if (imm_expr
.X_op
== O_constant
7457 && imm_expr
.X_add_number
> -0x8000
7458 && imm_expr
.X_add_number
< 0)
7460 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7461 macro_build (NULL
, &icnt
, &imm_expr
,
7462 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7463 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7468 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7469 macro_build (NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7472 macro_build (NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
7478 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7484 macro_build (NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7485 macro_build (NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7489 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7491 if (imm_expr
.X_op
== O_constant
7492 && imm_expr
.X_add_number
>= -0x8000
7493 && imm_expr
.X_add_number
< 0x8000)
7495 macro_build (NULL
, &icnt
, &imm_expr
,
7496 mask
== M_SGE_I
? "slti" : "sltiu",
7497 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7502 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7503 macro_build (NULL
, &icnt
, NULL
, mask
== M_SGE_I
? "slt" : "sltu",
7504 "d,v,t", dreg
, sreg
, AT
);
7507 macro_build (NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7513 case M_SGT
: /* sreg > treg <==> treg < sreg */
7519 macro_build (NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7522 case M_SGT_I
: /* sreg > I <==> I < sreg */
7528 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7529 macro_build (NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7532 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7538 macro_build (NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7539 macro_build (NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7543 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7549 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7550 macro_build (NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7551 macro_build (NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7556 if (imm_expr
.X_op
== O_constant
7557 && imm_expr
.X_add_number
>= -0x8000
7558 && imm_expr
.X_add_number
< 0x8000)
7560 macro_build (NULL
, &icnt
, &imm_expr
, "slti", "t,r,j", dreg
, sreg
,
7564 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7565 macro_build (NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7569 if (imm_expr
.X_op
== O_constant
7570 && imm_expr
.X_add_number
>= -0x8000
7571 && imm_expr
.X_add_number
< 0x8000)
7573 macro_build (NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7577 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7578 macro_build (NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7583 macro_build (NULL
, &icnt
, NULL
, "sltu","d,v,t", dreg
, 0, treg
);
7585 macro_build (NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7588 macro_build (NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7589 macro_build (NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7594 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7596 macro_build (NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7601 as_warn (_("Instruction %s: result is always true"),
7603 macro_build (NULL
, &icnt
, &expr1
,
7604 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7605 "t,r,j", dreg
, 0, BFD_RELOC_LO16
);
7608 if (imm_expr
.X_op
== O_constant
7609 && imm_expr
.X_add_number
>= 0
7610 && imm_expr
.X_add_number
< 0x10000)
7612 macro_build (NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
,
7616 else if (imm_expr
.X_op
== O_constant
7617 && imm_expr
.X_add_number
> -0x8000
7618 && imm_expr
.X_add_number
< 0)
7620 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7621 macro_build (NULL
, &icnt
, &imm_expr
,
7622 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7623 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7628 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7629 macro_build (NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7632 macro_build (NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7640 if (imm_expr
.X_op
== O_constant
7641 && imm_expr
.X_add_number
> -0x8000
7642 && imm_expr
.X_add_number
<= 0x8000)
7644 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7645 macro_build (NULL
, &icnt
, &imm_expr
, dbl
? "daddi" : "addi",
7646 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7649 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7650 macro_build (NULL
, &icnt
, NULL
, dbl
? "dsub" : "sub", "d,v,t",
7657 if (imm_expr
.X_op
== O_constant
7658 && imm_expr
.X_add_number
> -0x8000
7659 && imm_expr
.X_add_number
<= 0x8000)
7661 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7662 macro_build (NULL
, &icnt
, &imm_expr
, dbl
? "daddiu" : "addiu",
7663 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7666 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7667 macro_build (NULL
, &icnt
, NULL
, dbl
? "dsubu" : "subu", "d,v,t",
7689 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7690 macro_build (NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
7695 assert (mips_opts
.isa
== ISA_MIPS1
);
7696 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7697 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7700 * Is the double cfc1 instruction a bug in the mips assembler;
7701 * or is there a reason for it?
7703 mips_emit_delays (TRUE
);
7704 ++mips_opts
.noreorder
;
7705 mips_any_noreorder
= 1;
7706 macro_build (NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, RA
);
7707 macro_build (NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, RA
);
7708 macro_build (NULL
, &icnt
, NULL
, "nop", "");
7709 expr1
.X_add_number
= 3;
7710 macro_build (NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7712 expr1
.X_add_number
= 2;
7713 macro_build (NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7715 macro_build (NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, RA
);
7716 macro_build (NULL
, &icnt
, NULL
, "nop", "");
7717 macro_build (NULL
, &icnt
, NULL
,
7718 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s",
7720 macro_build (NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, RA
);
7721 macro_build (NULL
, &icnt
, NULL
, "nop", "");
7722 --mips_opts
.noreorder
;
7731 if (offset_expr
.X_add_number
>= 0x7fff)
7732 as_bad (_("operand overflow"));
7733 if (! target_big_endian
)
7734 ++offset_expr
.X_add_number
;
7735 macro_build (NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", AT
,
7736 BFD_RELOC_LO16
, breg
);
7737 if (! target_big_endian
)
7738 --offset_expr
.X_add_number
;
7740 ++offset_expr
.X_add_number
;
7741 macro_build (NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", treg
,
7742 BFD_RELOC_LO16
, breg
);
7743 macro_build (NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, AT
, 8);
7744 macro_build (NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
7757 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7758 as_bad (_("operand overflow"));
7763 if (! target_big_endian
)
7764 offset_expr
.X_add_number
+= off
;
7765 macro_build (NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", tempreg
,
7766 BFD_RELOC_LO16
, breg
);
7767 if (! target_big_endian
)
7768 offset_expr
.X_add_number
-= off
;
7770 offset_expr
.X_add_number
+= off
;
7771 macro_build (NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", tempreg
,
7772 BFD_RELOC_LO16
, breg
);
7774 /* If necessary, move the result in tempreg the final destination. */
7775 if (treg
== tempreg
)
7777 /* Protect second load's delay slot. */
7778 if (!gpr_interlocks
)
7779 macro_build (NULL
, &icnt
, NULL
, "nop", "");
7780 move_register (&icnt
, treg
, tempreg
);
7794 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7796 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7798 if (! target_big_endian
)
7799 expr1
.X_add_number
= off
;
7801 expr1
.X_add_number
= 0;
7802 macro_build (NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7803 BFD_RELOC_LO16
, AT
);
7804 if (! target_big_endian
)
7805 expr1
.X_add_number
= 0;
7807 expr1
.X_add_number
= off
;
7808 macro_build (NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7809 BFD_RELOC_LO16
, AT
);
7815 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7817 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7819 if (target_big_endian
)
7820 expr1
.X_add_number
= 0;
7821 macro_build (NULL
, &icnt
, &expr1
,
7822 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7823 treg
, BFD_RELOC_LO16
, AT
);
7824 if (target_big_endian
)
7825 expr1
.X_add_number
= 1;
7827 expr1
.X_add_number
= 0;
7828 macro_build (NULL
, &icnt
, &expr1
, "lbu", "t,o(b)",
7829 AT
, BFD_RELOC_LO16
, AT
);
7830 macro_build (NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
7831 macro_build (NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
7835 if (offset_expr
.X_add_number
>= 0x7fff)
7836 as_bad (_("operand overflow"));
7837 if (target_big_endian
)
7838 ++offset_expr
.X_add_number
;
7839 macro_build (NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7840 BFD_RELOC_LO16
, breg
);
7841 macro_build (NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
7842 if (target_big_endian
)
7843 --offset_expr
.X_add_number
;
7845 ++offset_expr
.X_add_number
;
7846 macro_build (NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7847 BFD_RELOC_LO16
, breg
);
7860 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7861 as_bad (_("operand overflow"));
7862 if (! target_big_endian
)
7863 offset_expr
.X_add_number
+= off
;
7864 macro_build (NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7865 BFD_RELOC_LO16
, breg
);
7866 if (! target_big_endian
)
7867 offset_expr
.X_add_number
-= off
;
7869 offset_expr
.X_add_number
+= off
;
7870 macro_build (NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7871 BFD_RELOC_LO16
, breg
);
7885 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7887 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7889 if (! target_big_endian
)
7890 expr1
.X_add_number
= off
;
7892 expr1
.X_add_number
= 0;
7893 macro_build (NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7894 BFD_RELOC_LO16
, AT
);
7895 if (! target_big_endian
)
7896 expr1
.X_add_number
= 0;
7898 expr1
.X_add_number
= off
;
7899 macro_build (NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7900 BFD_RELOC_LO16
, AT
);
7905 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7907 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7909 if (! target_big_endian
)
7910 expr1
.X_add_number
= 0;
7911 macro_build (NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7912 BFD_RELOC_LO16
, AT
);
7913 macro_build (NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
, treg
, 8);
7914 if (! target_big_endian
)
7915 expr1
.X_add_number
= 1;
7917 expr1
.X_add_number
= 0;
7918 macro_build (NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7919 BFD_RELOC_LO16
, AT
);
7920 if (! target_big_endian
)
7921 expr1
.X_add_number
= 0;
7923 expr1
.X_add_number
= 1;
7924 macro_build (NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7925 BFD_RELOC_LO16
, AT
);
7926 macro_build (NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
7927 macro_build (NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
7931 /* FIXME: Check if this is one of the itbl macros, since they
7932 are added dynamically. */
7933 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7937 as_warn (_("Macro used $at after \".set noat\""));
7940 /* Implement macros in mips16 mode. */
7943 mips16_macro (struct mips_cl_insn
*ip
)
7946 int xreg
, yreg
, zreg
, tmp
;
7950 const char *s
, *s2
, *s3
;
7952 mask
= ip
->insn_mo
->mask
;
7954 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7955 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7956 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7960 expr1
.X_op
= O_constant
;
7961 expr1
.X_op_symbol
= NULL
;
7962 expr1
.X_add_symbol
= NULL
;
7963 expr1
.X_add_number
= 1;
7982 mips_emit_delays (TRUE
);
7983 ++mips_opts
.noreorder
;
7984 mips_any_noreorder
= 1;
7985 macro_build (NULL
, &icnt
, NULL
, dbl
? "ddiv" : "div", "0,x,y",
7987 expr1
.X_add_number
= 2;
7988 macro_build (NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7989 macro_build (NULL
, &icnt
, NULL
, "break", "6", 7);
7991 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7992 since that causes an overflow. We should do that as well,
7993 but I don't see how to do the comparisons without a temporary
7995 --mips_opts
.noreorder
;
7996 macro_build (NULL
, &icnt
, NULL
, s
, "x", zreg
);
8015 mips_emit_delays (TRUE
);
8016 ++mips_opts
.noreorder
;
8017 mips_any_noreorder
= 1;
8018 macro_build (NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
8019 expr1
.X_add_number
= 2;
8020 macro_build (NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
8021 macro_build (NULL
, &icnt
, NULL
, "break", "6", 7);
8022 --mips_opts
.noreorder
;
8023 macro_build (NULL
, &icnt
, NULL
, s2
, "x", zreg
);
8029 macro_build (NULL
, &icnt
, NULL
, dbl
? "dmultu" : "multu", "x,y",
8031 macro_build (NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
8039 if (imm_expr
.X_op
!= O_constant
)
8040 as_bad (_("Unsupported large constant"));
8041 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8042 macro_build (NULL
, &icnt
, &imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4",
8047 if (imm_expr
.X_op
!= O_constant
)
8048 as_bad (_("Unsupported large constant"));
8049 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8050 macro_build (NULL
, &icnt
, &imm_expr
, "addiu", "x,k", xreg
);
8054 if (imm_expr
.X_op
!= O_constant
)
8055 as_bad (_("Unsupported large constant"));
8056 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8057 macro_build (NULL
, &icnt
, &imm_expr
, "daddiu", "y,j", yreg
);
8079 goto do_reverse_branch
;
8083 goto do_reverse_branch
;
8095 goto do_reverse_branch
;
8106 macro_build (NULL
, &icnt
, NULL
, s
, "x,y", xreg
, yreg
);
8107 macro_build (NULL
, &icnt
, &offset_expr
, s2
, "p");
8134 goto do_addone_branch_i
;
8139 goto do_addone_branch_i
;
8154 goto do_addone_branch_i
;
8161 if (imm_expr
.X_op
!= O_constant
)
8162 as_bad (_("Unsupported large constant"));
8163 ++imm_expr
.X_add_number
;
8166 macro_build (NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
8167 macro_build (NULL
, &icnt
, &offset_expr
, s2
, "p");
8171 expr1
.X_add_number
= 0;
8172 macro_build (NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
8174 move_register (&icnt
, xreg
, yreg
);
8175 expr1
.X_add_number
= 2;
8176 macro_build (NULL
, &icnt
, &expr1
, "bteqz", "p");
8177 macro_build (NULL
, &icnt
, NULL
, "neg", "x,w", xreg
, xreg
);
8181 /* For consistency checking, verify that all bits are specified either
8182 by the match/mask part of the instruction definition, or by the
8185 validate_mips_insn (const struct mips_opcode
*opc
)
8187 const char *p
= opc
->args
;
8189 unsigned long used_bits
= opc
->mask
;
8191 if ((used_bits
& opc
->match
) != opc
->match
)
8193 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8194 opc
->name
, opc
->args
);
8197 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8207 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8208 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8209 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8210 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8211 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8212 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8213 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8214 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8215 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8218 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8219 c
, opc
->name
, opc
->args
);
8223 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8224 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8226 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8227 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8228 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8229 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8231 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8232 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8234 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8235 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8237 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8238 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8239 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8240 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8241 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8242 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8243 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8244 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8245 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8246 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8247 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8248 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8249 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8250 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8251 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8252 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8253 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8255 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8256 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8257 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8258 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8260 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8261 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8262 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8263 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8264 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8265 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8266 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8267 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8268 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8271 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8272 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8273 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8274 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8275 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8279 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8280 c
, opc
->name
, opc
->args
);
8284 if (used_bits
!= 0xffffffff)
8286 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8287 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8293 /* This routine assembles an instruction into its binary format. As a
8294 side effect, it sets one of the global variables imm_reloc or
8295 offset_reloc to the type of relocation to do if one of the operands
8296 is an address expression. */
8299 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8304 struct mips_opcode
*insn
;
8307 unsigned int lastregno
= 0;
8308 unsigned int lastpos
= 0;
8309 unsigned int limlo
, limhi
;
8315 /* If the instruction contains a '.', we first try to match an instruction
8316 including the '.'. Then we try again without the '.'. */
8318 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8321 /* If we stopped on whitespace, then replace the whitespace with null for
8322 the call to hash_find. Save the character we replaced just in case we
8323 have to re-parse the instruction. */
8330 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8332 /* If we didn't find the instruction in the opcode table, try again, but
8333 this time with just the instruction up to, but not including the
8337 /* Restore the character we overwrite above (if any). */
8341 /* Scan up to the first '.' or whitespace. */
8343 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8347 /* If we did not find a '.', then we can quit now. */
8350 insn_error
= "unrecognized opcode";
8354 /* Lookup the instruction in the hash table. */
8356 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8358 insn_error
= "unrecognized opcode";
8368 assert (strcmp (insn
->name
, str
) == 0);
8370 if (OPCODE_IS_MEMBER (insn
,
8372 | (file_ase_mips16
? INSN_MIPS16
: 0)
8373 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8374 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8380 if (insn
->pinfo
!= INSN_MACRO
)
8382 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8388 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8389 && strcmp (insn
->name
, insn
[1].name
) == 0)
8398 static char buf
[100];
8400 _("opcode not supported on this processor: %s (%s)"),
8401 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8402 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8412 ip
->insn_opcode
= insn
->match
;
8414 for (args
= insn
->args
;; ++args
)
8418 s
+= strspn (s
, " \t");
8422 case '\0': /* end of args */
8435 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8439 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8443 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8447 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8453 /* Handle optional base register.
8454 Either the base register is omitted or
8455 we must have a left paren. */
8456 /* This is dependent on the next operand specifier
8457 is a base register specification. */
8458 assert (args
[1] == 'b' || args
[1] == '5'
8459 || args
[1] == '-' || args
[1] == '4');
8463 case ')': /* these must match exactly */
8470 case '+': /* Opcode extension character. */
8473 case 'A': /* ins/ext position, becomes LSB. */
8482 my_getExpression (&imm_expr
, s
);
8483 check_absolute_expr (ip
, &imm_expr
);
8484 if ((unsigned long) imm_expr
.X_add_number
< limlo
8485 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8487 as_bad (_("Improper position (%lu)"),
8488 (unsigned long) imm_expr
.X_add_number
);
8489 imm_expr
.X_add_number
= limlo
;
8491 lastpos
= imm_expr
.X_add_number
;
8492 ip
->insn_opcode
|= (imm_expr
.X_add_number
8493 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8494 imm_expr
.X_op
= O_absent
;
8498 case 'B': /* ins size, becomes MSB. */
8507 my_getExpression (&imm_expr
, s
);
8508 check_absolute_expr (ip
, &imm_expr
);
8509 /* Check for negative input so that small negative numbers
8510 will not succeed incorrectly. The checks against
8511 (pos+size) transitively check "size" itself,
8512 assuming that "pos" is reasonable. */
8513 if ((long) imm_expr
.X_add_number
< 0
8514 || ((unsigned long) imm_expr
.X_add_number
8516 || ((unsigned long) imm_expr
.X_add_number
8519 as_bad (_("Improper insert size (%lu, position %lu)"),
8520 (unsigned long) imm_expr
.X_add_number
,
8521 (unsigned long) lastpos
);
8522 imm_expr
.X_add_number
= limlo
- lastpos
;
8524 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8525 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8526 imm_expr
.X_op
= O_absent
;
8530 case 'C': /* ext size, becomes MSBD. */
8543 my_getExpression (&imm_expr
, s
);
8544 check_absolute_expr (ip
, &imm_expr
);
8545 /* Check for negative input so that small negative numbers
8546 will not succeed incorrectly. The checks against
8547 (pos+size) transitively check "size" itself,
8548 assuming that "pos" is reasonable. */
8549 if ((long) imm_expr
.X_add_number
< 0
8550 || ((unsigned long) imm_expr
.X_add_number
8552 || ((unsigned long) imm_expr
.X_add_number
8555 as_bad (_("Improper extract size (%lu, position %lu)"),
8556 (unsigned long) imm_expr
.X_add_number
,
8557 (unsigned long) lastpos
);
8558 imm_expr
.X_add_number
= limlo
- lastpos
;
8560 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8561 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8562 imm_expr
.X_op
= O_absent
;
8567 /* +D is for disassembly only; never match. */
8571 /* "+I" is like "I", except that imm2_expr is used. */
8572 my_getExpression (&imm2_expr
, s
);
8573 if (imm2_expr
.X_op
!= O_big
8574 && imm2_expr
.X_op
!= O_constant
)
8575 insn_error
= _("absolute expression required");
8576 normalize_constant_expr (&imm2_expr
);
8581 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8582 *args
, insn
->name
, insn
->args
);
8583 /* Further processing is fruitless. */
8588 case '<': /* must be at least one digit */
8590 * According to the manual, if the shift amount is greater
8591 * than 31 or less than 0, then the shift amount should be
8592 * mod 32. In reality the mips assembler issues an error.
8593 * We issue a warning and mask out all but the low 5 bits.
8595 my_getExpression (&imm_expr
, s
);
8596 check_absolute_expr (ip
, &imm_expr
);
8597 if ((unsigned long) imm_expr
.X_add_number
> 31)
8599 as_warn (_("Improper shift amount (%lu)"),
8600 (unsigned long) imm_expr
.X_add_number
);
8601 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8603 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8604 imm_expr
.X_op
= O_absent
;
8608 case '>': /* shift amount minus 32 */
8609 my_getExpression (&imm_expr
, s
);
8610 check_absolute_expr (ip
, &imm_expr
);
8611 if ((unsigned long) imm_expr
.X_add_number
< 32
8612 || (unsigned long) imm_expr
.X_add_number
> 63)
8614 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8615 imm_expr
.X_op
= O_absent
;
8619 case 'k': /* cache code */
8620 case 'h': /* prefx code */
8621 my_getExpression (&imm_expr
, s
);
8622 check_absolute_expr (ip
, &imm_expr
);
8623 if ((unsigned long) imm_expr
.X_add_number
> 31)
8625 as_warn (_("Invalid value for `%s' (%lu)"),
8627 (unsigned long) imm_expr
.X_add_number
);
8628 imm_expr
.X_add_number
&= 0x1f;
8631 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8633 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8634 imm_expr
.X_op
= O_absent
;
8638 case 'c': /* break code */
8639 my_getExpression (&imm_expr
, s
);
8640 check_absolute_expr (ip
, &imm_expr
);
8641 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8643 as_warn (_("Illegal break code (%lu)"),
8644 (unsigned long) imm_expr
.X_add_number
);
8645 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8647 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8648 imm_expr
.X_op
= O_absent
;
8652 case 'q': /* lower break code */
8653 my_getExpression (&imm_expr
, s
);
8654 check_absolute_expr (ip
, &imm_expr
);
8655 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8657 as_warn (_("Illegal lower break code (%lu)"),
8658 (unsigned long) imm_expr
.X_add_number
);
8659 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8661 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8662 imm_expr
.X_op
= O_absent
;
8666 case 'B': /* 20-bit syscall/break code. */
8667 my_getExpression (&imm_expr
, s
);
8668 check_absolute_expr (ip
, &imm_expr
);
8669 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8670 as_warn (_("Illegal 20-bit code (%lu)"),
8671 (unsigned long) imm_expr
.X_add_number
);
8672 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8673 imm_expr
.X_op
= O_absent
;
8677 case 'C': /* Coprocessor code */
8678 my_getExpression (&imm_expr
, s
);
8679 check_absolute_expr (ip
, &imm_expr
);
8680 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8682 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8683 (unsigned long) imm_expr
.X_add_number
);
8684 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8686 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8687 imm_expr
.X_op
= O_absent
;
8691 case 'J': /* 19-bit wait code. */
8692 my_getExpression (&imm_expr
, s
);
8693 check_absolute_expr (ip
, &imm_expr
);
8694 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8695 as_warn (_("Illegal 19-bit code (%lu)"),
8696 (unsigned long) imm_expr
.X_add_number
);
8697 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8698 imm_expr
.X_op
= O_absent
;
8702 case 'P': /* Performance register */
8703 my_getExpression (&imm_expr
, s
);
8704 check_absolute_expr (ip
, &imm_expr
);
8705 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8707 as_warn (_("Invalid performance register (%lu)"),
8708 (unsigned long) imm_expr
.X_add_number
);
8709 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8711 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8712 imm_expr
.X_op
= O_absent
;
8716 case 'b': /* base register */
8717 case 'd': /* destination register */
8718 case 's': /* source register */
8719 case 't': /* target register */
8720 case 'r': /* both target and source */
8721 case 'v': /* both dest and source */
8722 case 'w': /* both dest and target */
8723 case 'E': /* coprocessor target register */
8724 case 'G': /* coprocessor destination register */
8725 case 'K': /* 'rdhwr' destination register */
8726 case 'x': /* ignore register name */
8727 case 'z': /* must be zero register */
8728 case 'U': /* destination register (clo/clz). */
8743 while (ISDIGIT (*s
));
8745 as_bad (_("Invalid register number (%d)"), regno
);
8747 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8751 if (s
[1] == 'r' && s
[2] == 'a')
8756 else if (s
[1] == 'f' && s
[2] == 'p')
8761 else if (s
[1] == 's' && s
[2] == 'p')
8766 else if (s
[1] == 'g' && s
[2] == 'p')
8771 else if (s
[1] == 'a' && s
[2] == 't')
8776 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8781 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8786 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8791 else if (itbl_have_entries
)
8796 p
= s
+ 1; /* advance past '$' */
8797 n
= itbl_get_field (&p
); /* n is name */
8799 /* See if this is a register defined in an
8801 if (itbl_get_reg_val (n
, &r
))
8803 /* Get_field advances to the start of
8804 the next field, so we need to back
8805 rack to the end of the last field. */
8809 s
= strchr (s
, '\0');
8823 as_warn (_("Used $at without \".set noat\""));
8829 if (c
== 'r' || c
== 'v' || c
== 'w')
8836 /* 'z' only matches $0. */
8837 if (c
== 'z' && regno
!= 0)
8840 /* Now that we have assembled one operand, we use the args string
8841 * to figure out where it goes in the instruction. */
8848 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8853 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8856 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8857 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8862 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8865 /* This case exists because on the r3000 trunc
8866 expands into a macro which requires a gp
8867 register. On the r6000 or r4000 it is
8868 assembled into a single instruction which
8869 ignores the register. Thus the insn version
8870 is MIPS_ISA2 and uses 'x', and the macro
8871 version is MIPS_ISA1 and uses 't'. */
8874 /* This case is for the div instruction, which
8875 acts differently if the destination argument
8876 is $0. This only matches $0, and is checked
8877 outside the switch. */
8880 /* Itbl operand; not yet implemented. FIXME ?? */
8882 /* What about all other operands like 'i', which
8883 can be specified in the opcode table? */
8893 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8896 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8901 case 'O': /* MDMX alignment immediate constant. */
8902 my_getExpression (&imm_expr
, s
);
8903 check_absolute_expr (ip
, &imm_expr
);
8904 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8906 as_warn ("Improper align amount (%ld), using low bits",
8907 (long) imm_expr
.X_add_number
);
8908 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8910 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8911 imm_expr
.X_op
= O_absent
;
8915 case 'Q': /* MDMX vector, element sel, or const. */
8918 /* MDMX Immediate. */
8919 my_getExpression (&imm_expr
, s
);
8920 check_absolute_expr (ip
, &imm_expr
);
8921 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8923 as_warn (_("Invalid MDMX Immediate (%ld)"),
8924 (long) imm_expr
.X_add_number
);
8925 imm_expr
.X_add_number
&= OP_MASK_FT
;
8927 imm_expr
.X_add_number
&= OP_MASK_FT
;
8928 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8929 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8931 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8932 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8933 imm_expr
.X_op
= O_absent
;
8937 /* Not MDMX Immediate. Fall through. */
8938 case 'X': /* MDMX destination register. */
8939 case 'Y': /* MDMX source register. */
8940 case 'Z': /* MDMX target register. */
8942 case 'D': /* floating point destination register */
8943 case 'S': /* floating point source register */
8944 case 'T': /* floating point target register */
8945 case 'R': /* floating point source register */
8949 /* Accept $fN for FP and MDMX register numbers, and in
8950 addition accept $vN for MDMX register numbers. */
8951 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8952 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8963 while (ISDIGIT (*s
));
8966 as_bad (_("Invalid float register number (%d)"), regno
);
8968 if ((regno
& 1) != 0
8970 && ! (strcmp (str
, "mtc1") == 0
8971 || strcmp (str
, "mfc1") == 0
8972 || strcmp (str
, "lwc1") == 0
8973 || strcmp (str
, "swc1") == 0
8974 || strcmp (str
, "l.s") == 0
8975 || strcmp (str
, "s.s") == 0))
8976 as_warn (_("Float register should be even, was %d"),
8984 if (c
== 'V' || c
== 'W')
8995 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
9000 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
9003 /* This is like 'Z', but also needs to fix the MDMX
9004 vector/scalar select bits. Note that the
9005 scalar immediate case is handled above. */
9008 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9009 int max_el
= (is_qh
? 3 : 7);
9011 my_getExpression(&imm_expr
, s
);
9012 check_absolute_expr (ip
, &imm_expr
);
9014 if (imm_expr
.X_add_number
> max_el
)
9015 as_bad(_("Bad element selector %ld"),
9016 (long) imm_expr
.X_add_number
);
9017 imm_expr
.X_add_number
&= max_el
;
9018 ip
->insn_opcode
|= (imm_expr
.X_add_number
9022 as_warn(_("Expecting ']' found '%s'"), s
);
9028 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9029 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9032 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9039 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
9042 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
9052 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
9055 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
9061 my_getExpression (&imm_expr
, s
);
9062 if (imm_expr
.X_op
!= O_big
9063 && imm_expr
.X_op
!= O_constant
)
9064 insn_error
= _("absolute expression required");
9065 normalize_constant_expr (&imm_expr
);
9070 my_getExpression (&offset_expr
, s
);
9071 *imm_reloc
= BFD_RELOC_32
;
9084 unsigned char temp
[8];
9086 unsigned int length
;
9091 /* These only appear as the last operand in an
9092 instruction, and every instruction that accepts
9093 them in any variant accepts them in all variants.
9094 This means we don't have to worry about backing out
9095 any changes if the instruction does not match.
9097 The difference between them is the size of the
9098 floating point constant and where it goes. For 'F'
9099 and 'L' the constant is 64 bits; for 'f' and 'l' it
9100 is 32 bits. Where the constant is placed is based
9101 on how the MIPS assembler does things:
9104 f -- immediate value
9107 The .lit4 and .lit8 sections are only used if
9108 permitted by the -G argument.
9110 When generating embedded PIC code, we use the
9111 .lit8 section but not the .lit4 section (we can do
9112 .lit4 inline easily; we need to put .lit8
9113 somewhere in the data segment, and using .lit8
9114 permits the linker to eventually combine identical
9117 The code below needs to know whether the target register
9118 is 32 or 64 bits wide. It relies on the fact 'f' and
9119 'F' are used with GPR-based instructions and 'l' and
9120 'L' are used with FPR-based instructions. */
9122 f64
= *args
== 'F' || *args
== 'L';
9123 using_gprs
= *args
== 'F' || *args
== 'f';
9125 save_in
= input_line_pointer
;
9126 input_line_pointer
= s
;
9127 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9129 s
= input_line_pointer
;
9130 input_line_pointer
= save_in
;
9131 if (err
!= NULL
&& *err
!= '\0')
9133 as_bad (_("Bad floating point constant: %s"), err
);
9134 memset (temp
, '\0', sizeof temp
);
9135 length
= f64
? 8 : 4;
9138 assert (length
== (unsigned) (f64
? 8 : 4));
9142 && (! USE_GLOBAL_POINTER_OPT
9143 || mips_pic
== EMBEDDED_PIC
9144 || g_switch_value
< 4
9145 || (temp
[0] == 0 && temp
[1] == 0)
9146 || (temp
[2] == 0 && temp
[3] == 0))))
9148 imm_expr
.X_op
= O_constant
;
9149 if (! target_big_endian
)
9150 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9152 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9155 && ! mips_disable_float_construction
9156 /* Constants can only be constructed in GPRs and
9157 copied to FPRs if the GPRs are at least as wide
9158 as the FPRs. Force the constant into memory if
9159 we are using 64-bit FPRs but the GPRs are only
9162 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9163 && ((temp
[0] == 0 && temp
[1] == 0)
9164 || (temp
[2] == 0 && temp
[3] == 0))
9165 && ((temp
[4] == 0 && temp
[5] == 0)
9166 || (temp
[6] == 0 && temp
[7] == 0)))
9168 /* The value is simple enough to load with a couple of
9169 instructions. If using 32-bit registers, set
9170 imm_expr to the high order 32 bits and offset_expr to
9171 the low order 32 bits. Otherwise, set imm_expr to
9172 the entire 64 bit constant. */
9173 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9175 imm_expr
.X_op
= O_constant
;
9176 offset_expr
.X_op
= O_constant
;
9177 if (! target_big_endian
)
9179 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9180 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9184 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9185 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9187 if (offset_expr
.X_add_number
== 0)
9188 offset_expr
.X_op
= O_absent
;
9190 else if (sizeof (imm_expr
.X_add_number
) > 4)
9192 imm_expr
.X_op
= O_constant
;
9193 if (! target_big_endian
)
9194 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9196 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9200 imm_expr
.X_op
= O_big
;
9201 imm_expr
.X_add_number
= 4;
9202 if (! target_big_endian
)
9204 generic_bignum
[0] = bfd_getl16 (temp
);
9205 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9206 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9207 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9211 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9212 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9213 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9214 generic_bignum
[3] = bfd_getb16 (temp
);
9220 const char *newname
;
9223 /* Switch to the right section. */
9225 subseg
= now_subseg
;
9228 default: /* unused default case avoids warnings. */
9230 newname
= RDATA_SECTION_NAME
;
9231 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
9232 || mips_pic
== EMBEDDED_PIC
)
9236 if (mips_pic
== EMBEDDED_PIC
)
9239 newname
= RDATA_SECTION_NAME
;
9242 assert (!USE_GLOBAL_POINTER_OPT
9243 || g_switch_value
>= 4);
9247 new_seg
= subseg_new (newname
, (subsegT
) 0);
9248 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9249 bfd_set_section_flags (stdoutput
, new_seg
,
9254 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9255 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9256 && strcmp (TARGET_OS
, "elf") != 0)
9257 record_alignment (new_seg
, 4);
9259 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9261 as_bad (_("Can't use floating point insn in this section"));
9263 /* Set the argument to the current address in the
9265 offset_expr
.X_op
= O_symbol
;
9266 offset_expr
.X_add_symbol
=
9267 symbol_new ("L0\001", now_seg
,
9268 (valueT
) frag_now_fix (), frag_now
);
9269 offset_expr
.X_add_number
= 0;
9271 /* Put the floating point number into the section. */
9272 p
= frag_more ((int) length
);
9273 memcpy (p
, temp
, length
);
9275 /* Switch back to the original section. */
9276 subseg_set (seg
, subseg
);
9281 case 'i': /* 16 bit unsigned immediate */
9282 case 'j': /* 16 bit signed immediate */
9283 *imm_reloc
= BFD_RELOC_LO16
;
9284 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9287 offsetT minval
, maxval
;
9289 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9290 && strcmp (insn
->name
, insn
[1].name
) == 0);
9292 /* If the expression was written as an unsigned number,
9293 only treat it as signed if there are no more
9297 && sizeof (imm_expr
.X_add_number
) <= 4
9298 && imm_expr
.X_op
== O_constant
9299 && imm_expr
.X_add_number
< 0
9300 && imm_expr
.X_unsigned
9304 /* For compatibility with older assemblers, we accept
9305 0x8000-0xffff as signed 16-bit numbers when only
9306 signed numbers are allowed. */
9308 minval
= 0, maxval
= 0xffff;
9310 minval
= -0x8000, maxval
= 0x7fff;
9312 minval
= -0x8000, maxval
= 0xffff;
9314 if (imm_expr
.X_op
!= O_constant
9315 || imm_expr
.X_add_number
< minval
9316 || imm_expr
.X_add_number
> maxval
)
9320 if (imm_expr
.X_op
== O_constant
9321 || imm_expr
.X_op
== O_big
)
9322 as_bad (_("expression out of range"));
9328 case 'o': /* 16 bit offset */
9329 /* Check whether there is only a single bracketed expression
9330 left. If so, it must be the base register and the
9331 constant must be zero. */
9332 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9334 offset_expr
.X_op
= O_constant
;
9335 offset_expr
.X_add_number
= 0;
9339 /* If this value won't fit into a 16 bit offset, then go
9340 find a macro that will generate the 32 bit offset
9342 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9343 && (offset_expr
.X_op
!= O_constant
9344 || offset_expr
.X_add_number
>= 0x8000
9345 || offset_expr
.X_add_number
< -0x8000))
9351 case 'p': /* pc relative offset */
9352 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9353 my_getExpression (&offset_expr
, s
);
9357 case 'u': /* upper 16 bits */
9358 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9359 && imm_expr
.X_op
== O_constant
9360 && (imm_expr
.X_add_number
< 0
9361 || imm_expr
.X_add_number
>= 0x10000))
9362 as_bad (_("lui expression not in range 0..65535"));
9366 case 'a': /* 26 bit address */
9367 my_getExpression (&offset_expr
, s
);
9369 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9372 case 'N': /* 3 bit branch condition code */
9373 case 'M': /* 3 bit compare condition code */
9374 if (strncmp (s
, "$fcc", 4) != 0)
9384 while (ISDIGIT (*s
));
9386 as_bad (_("Invalid condition code register $fcc%d"), regno
);
9387 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9388 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9389 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9390 && (regno
& 1) != 0)
9391 as_warn(_("Condition code register should be even for %s, was %d"),
9393 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9394 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9395 && (regno
& 3) != 0)
9396 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9399 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9401 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9405 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9416 while (ISDIGIT (*s
));
9419 c
= 8; /* Invalid sel value. */
9422 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9423 ip
->insn_opcode
|= c
;
9427 /* Must be at least one digit. */
9428 my_getExpression (&imm_expr
, s
);
9429 check_absolute_expr (ip
, &imm_expr
);
9431 if ((unsigned long) imm_expr
.X_add_number
9432 > (unsigned long) OP_MASK_VECBYTE
)
9434 as_bad (_("bad byte vector index (%ld)"),
9435 (long) imm_expr
.X_add_number
);
9436 imm_expr
.X_add_number
= 0;
9439 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9440 imm_expr
.X_op
= O_absent
;
9445 my_getExpression (&imm_expr
, s
);
9446 check_absolute_expr (ip
, &imm_expr
);
9448 if ((unsigned long) imm_expr
.X_add_number
9449 > (unsigned long) OP_MASK_VECALIGN
)
9451 as_bad (_("bad byte vector index (%ld)"),
9452 (long) imm_expr
.X_add_number
);
9453 imm_expr
.X_add_number
= 0;
9456 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9457 imm_expr
.X_op
= O_absent
;
9462 as_bad (_("bad char = '%c'\n"), *args
);
9467 /* Args don't match. */
9468 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9469 !strcmp (insn
->name
, insn
[1].name
))
9473 insn_error
= _("illegal operands");
9478 insn_error
= _("illegal operands");
9483 /* This routine assembles an instruction into its binary format when
9484 assembling for the mips16. As a side effect, it sets one of the
9485 global variables imm_reloc or offset_reloc to the type of
9486 relocation to do if one of the operands is an address expression.
9487 It also sets mips16_small and mips16_ext if the user explicitly
9488 requested a small or extended instruction. */
9491 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9495 struct mips_opcode
*insn
;
9498 unsigned int lastregno
= 0;
9503 mips16_small
= FALSE
;
9506 for (s
= str
; ISLOWER (*s
); ++s
)
9518 if (s
[1] == 't' && s
[2] == ' ')
9521 mips16_small
= TRUE
;
9525 else if (s
[1] == 'e' && s
[2] == ' ')
9534 insn_error
= _("unknown opcode");
9538 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9539 mips16_small
= TRUE
;
9541 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9543 insn_error
= _("unrecognized opcode");
9550 assert (strcmp (insn
->name
, str
) == 0);
9553 ip
->insn_opcode
= insn
->match
;
9554 ip
->use_extend
= FALSE
;
9555 imm_expr
.X_op
= O_absent
;
9556 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9557 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9558 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9559 imm2_expr
.X_op
= O_absent
;
9560 offset_expr
.X_op
= O_absent
;
9561 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9562 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9563 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9564 for (args
= insn
->args
; 1; ++args
)
9571 /* In this switch statement we call break if we did not find
9572 a match, continue if we did find a match, or return if we
9581 /* Stuff the immediate value in now, if we can. */
9582 if (imm_expr
.X_op
== O_constant
9583 && *imm_reloc
> BFD_RELOC_UNUSED
9584 && insn
->pinfo
!= INSN_MACRO
)
9586 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9587 imm_expr
.X_add_number
, TRUE
, mips16_small
,
9588 mips16_ext
, &ip
->insn_opcode
,
9589 &ip
->use_extend
, &ip
->extend
);
9590 imm_expr
.X_op
= O_absent
;
9591 *imm_reloc
= BFD_RELOC_UNUSED
;
9605 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9608 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9624 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9626 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9653 while (ISDIGIT (*s
));
9656 as_bad (_("invalid register number (%d)"), regno
);
9662 if (s
[1] == 'r' && s
[2] == 'a')
9667 else if (s
[1] == 'f' && s
[2] == 'p')
9672 else if (s
[1] == 's' && s
[2] == 'p')
9677 else if (s
[1] == 'g' && s
[2] == 'p')
9682 else if (s
[1] == 'a' && s
[2] == 't')
9687 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9692 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9697 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9710 if (c
== 'v' || c
== 'w')
9712 regno
= mips16_to_32_reg_map
[lastregno
];
9726 regno
= mips32_to_16_reg_map
[regno
];
9731 regno
= ILLEGAL_REG
;
9736 regno
= ILLEGAL_REG
;
9741 regno
= ILLEGAL_REG
;
9746 if (regno
== AT
&& ! mips_opts
.noat
)
9747 as_warn (_("used $at without \".set noat\""));
9754 if (regno
== ILLEGAL_REG
)
9761 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9765 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9768 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9771 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9777 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9780 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9781 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9791 if (strncmp (s
, "$pc", 3) == 0)
9815 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9817 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9818 and generate the appropriate reloc. If the text
9819 inside %gprel is not a symbol name with an
9820 optional offset, then we generate a normal reloc
9821 and will probably fail later. */
9822 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9823 if (imm_expr
.X_op
== O_symbol
)
9826 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9828 ip
->use_extend
= TRUE
;
9835 /* Just pick up a normal expression. */
9836 my_getExpression (&imm_expr
, s
);
9839 if (imm_expr
.X_op
== O_register
)
9841 /* What we thought was an expression turned out to
9844 if (s
[0] == '(' && args
[1] == '(')
9846 /* It looks like the expression was omitted
9847 before a register indirection, which means
9848 that the expression is implicitly zero. We
9849 still set up imm_expr, so that we handle
9850 explicit extensions correctly. */
9851 imm_expr
.X_op
= O_constant
;
9852 imm_expr
.X_add_number
= 0;
9853 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9860 /* We need to relax this instruction. */
9861 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9870 /* We use offset_reloc rather than imm_reloc for the PC
9871 relative operands. This lets macros with both
9872 immediate and address operands work correctly. */
9873 my_getExpression (&offset_expr
, s
);
9875 if (offset_expr
.X_op
== O_register
)
9878 /* We need to relax this instruction. */
9879 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9883 case '6': /* break code */
9884 my_getExpression (&imm_expr
, s
);
9885 check_absolute_expr (ip
, &imm_expr
);
9886 if ((unsigned long) imm_expr
.X_add_number
> 63)
9888 as_warn (_("Invalid value for `%s' (%lu)"),
9890 (unsigned long) imm_expr
.X_add_number
);
9891 imm_expr
.X_add_number
&= 0x3f;
9893 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9894 imm_expr
.X_op
= O_absent
;
9898 case 'a': /* 26 bit address */
9899 my_getExpression (&offset_expr
, s
);
9901 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9902 ip
->insn_opcode
<<= 16;
9905 case 'l': /* register list for entry macro */
9906 case 'L': /* register list for exit macro */
9916 int freg
, reg1
, reg2
;
9918 while (*s
== ' ' || *s
== ',')
9922 as_bad (_("can't parse register list"));
9934 while (ISDIGIT (*s
))
9956 as_bad (_("invalid register list"));
9961 while (ISDIGIT (*s
))
9968 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9973 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9978 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9979 mask
|= (reg2
- 3) << 3;
9980 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9981 mask
|= (reg2
- 15) << 1;
9982 else if (reg1
== RA
&& reg2
== RA
)
9986 as_bad (_("invalid register list"));
9990 /* The mask is filled in in the opcode table for the
9991 benefit of the disassembler. We remove it before
9992 applying the actual mask. */
9993 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9994 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9998 case 'e': /* extend code */
9999 my_getExpression (&imm_expr
, s
);
10000 check_absolute_expr (ip
, &imm_expr
);
10001 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10003 as_warn (_("Invalid value for `%s' (%lu)"),
10005 (unsigned long) imm_expr
.X_add_number
);
10006 imm_expr
.X_add_number
&= 0x7ff;
10008 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10009 imm_expr
.X_op
= O_absent
;
10019 /* Args don't match. */
10020 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10021 strcmp (insn
->name
, insn
[1].name
) == 0)
10028 insn_error
= _("illegal operands");
10034 /* This structure holds information we know about a mips16 immediate
10037 struct mips16_immed_operand
10039 /* The type code used in the argument string in the opcode table. */
10041 /* The number of bits in the short form of the opcode. */
10043 /* The number of bits in the extended form of the opcode. */
10045 /* The amount by which the short form is shifted when it is used;
10046 for example, the sw instruction has a shift count of 2. */
10048 /* The amount by which the short form is shifted when it is stored
10049 into the instruction code. */
10051 /* Non-zero if the short form is unsigned. */
10053 /* Non-zero if the extended form is unsigned. */
10055 /* Non-zero if the value is PC relative. */
10059 /* The mips16 immediate operand types. */
10061 static const struct mips16_immed_operand mips16_immed_operands
[] =
10063 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10064 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10065 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10066 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10067 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10068 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10069 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10070 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10071 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10072 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10073 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10074 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10075 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10076 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10077 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10078 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10079 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10080 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10081 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10082 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10083 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10086 #define MIPS16_NUM_IMMED \
10087 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10089 /* Handle a mips16 instruction with an immediate value. This or's the
10090 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10091 whether an extended value is needed; if one is needed, it sets
10092 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10093 If SMALL is true, an unextended opcode was explicitly requested.
10094 If EXT is true, an extended opcode was explicitly requested. If
10095 WARN is true, warn if EXT does not match reality. */
10098 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10099 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10100 unsigned long *insn
, bfd_boolean
*use_extend
,
10101 unsigned short *extend
)
10103 register const struct mips16_immed_operand
*op
;
10104 int mintiny
, maxtiny
;
10105 bfd_boolean needext
;
10107 op
= mips16_immed_operands
;
10108 while (op
->type
!= type
)
10111 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10116 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10119 maxtiny
= 1 << op
->nbits
;
10124 maxtiny
= (1 << op
->nbits
) - 1;
10129 mintiny
= - (1 << (op
->nbits
- 1));
10130 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10133 /* Branch offsets have an implicit 0 in the lowest bit. */
10134 if (type
== 'p' || type
== 'q')
10137 if ((val
& ((1 << op
->shift
) - 1)) != 0
10138 || val
< (mintiny
<< op
->shift
)
10139 || val
> (maxtiny
<< op
->shift
))
10144 if (warn
&& ext
&& ! needext
)
10145 as_warn_where (file
, line
,
10146 _("extended operand requested but not required"));
10147 if (small
&& needext
)
10148 as_bad_where (file
, line
, _("invalid unextended operand value"));
10150 if (small
|| (! ext
&& ! needext
))
10154 *use_extend
= FALSE
;
10155 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10156 insnval
<<= op
->op_shift
;
10161 long minext
, maxext
;
10167 maxext
= (1 << op
->extbits
) - 1;
10171 minext
= - (1 << (op
->extbits
- 1));
10172 maxext
= (1 << (op
->extbits
- 1)) - 1;
10174 if (val
< minext
|| val
> maxext
)
10175 as_bad_where (file
, line
,
10176 _("operand value out of range for instruction"));
10178 *use_extend
= TRUE
;
10179 if (op
->extbits
== 16)
10181 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10184 else if (op
->extbits
== 15)
10186 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10191 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10195 *extend
= (unsigned short) extval
;
10200 static const struct percent_op_match
10203 bfd_reloc_code_real_type reloc
;
10206 {"%lo", BFD_RELOC_LO16
},
10208 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10209 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10210 {"%call16", BFD_RELOC_MIPS_CALL16
},
10211 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10212 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10213 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10214 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10215 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10216 {"%got", BFD_RELOC_MIPS_GOT16
},
10217 {"%gp_rel", BFD_RELOC_GPREL16
},
10218 {"%half", BFD_RELOC_16
},
10219 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10220 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10221 {"%neg", BFD_RELOC_MIPS_SUB
},
10223 {"%hi", BFD_RELOC_HI16_S
}
10227 /* Return true if *STR points to a relocation operator. When returning true,
10228 move *STR over the operator and store its relocation code in *RELOC.
10229 Leave both *STR and *RELOC alone when returning false. */
10232 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10236 for (i
= 0; i
< ARRAY_SIZE (percent_op
); i
++)
10237 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10239 *str
+= strlen (percent_op
[i
].str
);
10240 *reloc
= percent_op
[i
].reloc
;
10242 /* Check whether the output BFD supports this relocation.
10243 If not, issue an error and fall back on something safe. */
10244 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10246 as_bad ("relocation %s isn't supported by the current ABI",
10247 percent_op
[i
].str
);
10248 *reloc
= BFD_RELOC_LO16
;
10256 /* Parse string STR as a 16-bit relocatable operand. Store the
10257 expression in *EP and the relocations in the array starting
10258 at RELOC. Return the number of relocation operators used.
10260 On exit, EXPR_END points to the first character after the expression.
10261 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10264 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10267 bfd_reloc_code_real_type reversed_reloc
[3];
10268 size_t reloc_index
, i
;
10269 int crux_depth
, str_depth
;
10272 /* Search for the start of the main expression, recoding relocations
10273 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10274 of the main expression and with CRUX_DEPTH containing the number
10275 of open brackets at that point. */
10282 crux_depth
= str_depth
;
10284 /* Skip over whitespace and brackets, keeping count of the number
10286 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10291 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10292 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10294 my_getExpression (ep
, crux
);
10297 /* Match every open bracket. */
10298 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10302 if (crux_depth
> 0)
10303 as_bad ("unclosed '('");
10307 if (reloc_index
== 0)
10308 reloc
[0] = BFD_RELOC_LO16
;
10311 prev_reloc_op_frag
= frag_now
;
10312 for (i
= 0; i
< reloc_index
; i
++)
10313 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10316 return reloc_index
;
10320 my_getExpression (expressionS
*ep
, char *str
)
10325 save_in
= input_line_pointer
;
10326 input_line_pointer
= str
;
10328 expr_end
= input_line_pointer
;
10329 input_line_pointer
= save_in
;
10331 /* If we are in mips16 mode, and this is an expression based on `.',
10332 then we bump the value of the symbol by 1 since that is how other
10333 text symbols are handled. We don't bother to handle complex
10334 expressions, just `.' plus or minus a constant. */
10335 if (mips_opts
.mips16
10336 && ep
->X_op
== O_symbol
10337 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10338 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10339 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10340 && symbol_constant_p (ep
->X_add_symbol
)
10341 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10342 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10345 /* Turn a string in input_line_pointer into a floating point constant
10346 of type TYPE, and store the appropriate bytes in *LITP. The number
10347 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10348 returned, or NULL on OK. */
10351 md_atof (int type
, char *litP
, int *sizeP
)
10354 LITTLENUM_TYPE words
[4];
10370 return _("bad call to md_atof");
10373 t
= atof_ieee (input_line_pointer
, type
, words
);
10375 input_line_pointer
= t
;
10379 if (! target_big_endian
)
10381 for (i
= prec
- 1; i
>= 0; i
--)
10383 md_number_to_chars (litP
, words
[i
], 2);
10389 for (i
= 0; i
< prec
; i
++)
10391 md_number_to_chars (litP
, words
[i
], 2);
10400 md_number_to_chars (char *buf
, valueT val
, int n
)
10402 if (target_big_endian
)
10403 number_to_chars_bigendian (buf
, val
, n
);
10405 number_to_chars_littleendian (buf
, val
, n
);
10409 static int support_64bit_objects(void)
10411 const char **list
, **l
;
10414 list
= bfd_target_list ();
10415 for (l
= list
; *l
!= NULL
; l
++)
10417 /* This is traditional mips */
10418 if (strcmp (*l
, "elf64-tradbigmips") == 0
10419 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10421 if (strcmp (*l
, "elf64-bigmips") == 0
10422 || strcmp (*l
, "elf64-littlemips") == 0)
10425 yes
= (*l
!= NULL
);
10429 #endif /* OBJ_ELF */
10431 const char *md_shortopts
= "nO::g::G:";
10433 struct option md_longopts
[] =
10435 /* Options which specify architecture. */
10436 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10437 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10438 {"march", required_argument
, NULL
, OPTION_MARCH
},
10439 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10440 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10441 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10442 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10443 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10444 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10445 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10446 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10447 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10448 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10449 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10450 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10451 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10452 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10453 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10454 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10455 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10456 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10457 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10458 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10459 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10461 /* Options which specify Application Specific Extensions (ASEs). */
10462 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10463 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10464 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10465 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10466 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10467 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10468 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10469 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10470 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10471 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10472 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10473 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10474 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10476 /* Old-style architecture options. Don't add more of these. */
10477 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10478 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10479 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10480 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10481 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10482 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10483 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10484 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10485 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10486 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10487 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10488 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10489 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10490 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10491 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10492 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10493 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10495 /* Options which enable bug fixes. */
10496 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10497 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10498 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10499 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10500 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10501 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10502 #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
10503 #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
10504 {"mfix-vr4122-bugs", no_argument
, NULL
, OPTION_FIX_VR4122
},
10505 {"no-mfix-vr4122-bugs", no_argument
, NULL
, OPTION_NO_FIX_VR4122
},
10507 /* Miscellaneous options. */
10508 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10509 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10510 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
10511 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10512 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10513 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10514 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10515 {"break", no_argument
, NULL
, OPTION_BREAK
},
10516 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10517 #define OPTION_EB (OPTION_MISC_BASE + 3)
10518 {"EB", no_argument
, NULL
, OPTION_EB
},
10519 #define OPTION_EL (OPTION_MISC_BASE + 4)
10520 {"EL", no_argument
, NULL
, OPTION_EL
},
10521 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10522 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10523 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10524 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10525 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10526 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10527 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10528 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10529 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10530 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10531 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10532 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10533 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10534 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10535 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10536 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10538 /* ELF-specific options. */
10540 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10541 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10542 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10543 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10544 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10545 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10546 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10547 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10548 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10549 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10550 #define OPTION_32 (OPTION_ELF_BASE + 4)
10551 {"32", no_argument
, NULL
, OPTION_32
},
10552 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10553 {"n32", no_argument
, NULL
, OPTION_N32
},
10554 #define OPTION_64 (OPTION_ELF_BASE + 6)
10555 {"64", no_argument
, NULL
, OPTION_64
},
10556 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10557 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10558 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10559 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10560 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10561 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10562 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10563 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10564 #endif /* OBJ_ELF */
10566 {NULL
, no_argument
, NULL
, 0}
10568 size_t md_longopts_size
= sizeof (md_longopts
);
10570 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10571 NEW_VALUE. Warn if another value was already specified. Note:
10572 we have to defer parsing the -march and -mtune arguments in order
10573 to handle 'from-abi' correctly, since the ABI might be specified
10574 in a later argument. */
10577 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10579 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10580 as_warn (_("A different %s was already specified, is now %s"),
10581 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10584 *string_ptr
= new_value
;
10588 md_parse_option (int c
, char *arg
)
10592 case OPTION_CONSTRUCT_FLOATS
:
10593 mips_disable_float_construction
= 0;
10596 case OPTION_NO_CONSTRUCT_FLOATS
:
10597 mips_disable_float_construction
= 1;
10609 target_big_endian
= 1;
10613 target_big_endian
= 0;
10621 if (arg
&& arg
[1] == '0')
10631 mips_debug
= atoi (arg
);
10632 /* When the MIPS assembler sees -g or -g2, it does not do
10633 optimizations which limit full symbolic debugging. We take
10634 that to be equivalent to -O0. */
10635 if (mips_debug
== 2)
10640 file_mips_isa
= ISA_MIPS1
;
10644 file_mips_isa
= ISA_MIPS2
;
10648 file_mips_isa
= ISA_MIPS3
;
10652 file_mips_isa
= ISA_MIPS4
;
10656 file_mips_isa
= ISA_MIPS5
;
10659 case OPTION_MIPS32
:
10660 file_mips_isa
= ISA_MIPS32
;
10663 case OPTION_MIPS32R2
:
10664 file_mips_isa
= ISA_MIPS32R2
;
10667 case OPTION_MIPS64R2
:
10668 file_mips_isa
= ISA_MIPS64R2
;
10671 case OPTION_MIPS64
:
10672 file_mips_isa
= ISA_MIPS64
;
10676 mips_set_option_string (&mips_tune_string
, arg
);
10680 mips_set_option_string (&mips_arch_string
, arg
);
10684 mips_set_option_string (&mips_arch_string
, "4650");
10685 mips_set_option_string (&mips_tune_string
, "4650");
10688 case OPTION_NO_M4650
:
10692 mips_set_option_string (&mips_arch_string
, "4010");
10693 mips_set_option_string (&mips_tune_string
, "4010");
10696 case OPTION_NO_M4010
:
10700 mips_set_option_string (&mips_arch_string
, "4100");
10701 mips_set_option_string (&mips_tune_string
, "4100");
10704 case OPTION_NO_M4100
:
10708 mips_set_option_string (&mips_arch_string
, "3900");
10709 mips_set_option_string (&mips_tune_string
, "3900");
10712 case OPTION_NO_M3900
:
10716 mips_opts
.ase_mdmx
= 1;
10719 case OPTION_NO_MDMX
:
10720 mips_opts
.ase_mdmx
= 0;
10723 case OPTION_MIPS16
:
10724 mips_opts
.mips16
= 1;
10725 mips_no_prev_insn (FALSE
);
10728 case OPTION_NO_MIPS16
:
10729 mips_opts
.mips16
= 0;
10730 mips_no_prev_insn (FALSE
);
10733 case OPTION_MIPS3D
:
10734 mips_opts
.ase_mips3d
= 1;
10737 case OPTION_NO_MIPS3D
:
10738 mips_opts
.ase_mips3d
= 0;
10741 case OPTION_MEMBEDDED_PIC
:
10742 mips_pic
= EMBEDDED_PIC
;
10743 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10745 as_bad (_("-G may not be used with embedded PIC code"));
10748 g_switch_value
= 0x7fffffff;
10751 case OPTION_FIX_VR4122
:
10752 mips_fix_4122_bugs
= 1;
10755 case OPTION_NO_FIX_VR4122
:
10756 mips_fix_4122_bugs
= 0;
10759 case OPTION_RELAX_BRANCH
:
10760 mips_relax_branch
= 1;
10763 case OPTION_NO_RELAX_BRANCH
:
10764 mips_relax_branch
= 0;
10768 /* When generating ELF code, we permit -KPIC and -call_shared to
10769 select SVR4_PIC, and -non_shared to select no PIC. This is
10770 intended to be compatible with Irix 5. */
10771 case OPTION_CALL_SHARED
:
10772 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10774 as_bad (_("-call_shared is supported only for ELF format"));
10777 mips_pic
= SVR4_PIC
;
10778 mips_abicalls
= TRUE
;
10779 if (g_switch_seen
&& g_switch_value
!= 0)
10781 as_bad (_("-G may not be used with SVR4 PIC code"));
10784 g_switch_value
= 0;
10787 case OPTION_NON_SHARED
:
10788 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10790 as_bad (_("-non_shared is supported only for ELF format"));
10794 mips_abicalls
= FALSE
;
10797 /* The -xgot option tells the assembler to use 32 offsets when
10798 accessing the got in SVR4_PIC mode. It is for Irix
10803 #endif /* OBJ_ELF */
10806 if (! USE_GLOBAL_POINTER_OPT
)
10808 as_bad (_("-G is not supported for this configuration"));
10811 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10813 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10817 g_switch_value
= atoi (arg
);
10822 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10825 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10827 as_bad (_("-32 is supported for ELF format only"));
10830 mips_abi
= O32_ABI
;
10834 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10836 as_bad (_("-n32 is supported for ELF format only"));
10839 mips_abi
= N32_ABI
;
10843 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10845 as_bad (_("-64 is supported for ELF format only"));
10848 mips_abi
= N64_ABI
;
10849 if (! support_64bit_objects())
10850 as_fatal (_("No compiled in support for 64 bit object file format"));
10852 #endif /* OBJ_ELF */
10855 file_mips_gp32
= 1;
10859 file_mips_gp32
= 0;
10863 file_mips_fp32
= 1;
10867 file_mips_fp32
= 0;
10872 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10874 as_bad (_("-mabi is supported for ELF format only"));
10877 if (strcmp (arg
, "32") == 0)
10878 mips_abi
= O32_ABI
;
10879 else if (strcmp (arg
, "o64") == 0)
10880 mips_abi
= O64_ABI
;
10881 else if (strcmp (arg
, "n32") == 0)
10882 mips_abi
= N32_ABI
;
10883 else if (strcmp (arg
, "64") == 0)
10885 mips_abi
= N64_ABI
;
10886 if (! support_64bit_objects())
10887 as_fatal (_("No compiled in support for 64 bit object file "
10890 else if (strcmp (arg
, "eabi") == 0)
10891 mips_abi
= EABI_ABI
;
10894 as_fatal (_("invalid abi -mabi=%s"), arg
);
10898 #endif /* OBJ_ELF */
10900 case OPTION_M7000_HILO_FIX
:
10901 mips_7000_hilo_fix
= TRUE
;
10904 case OPTION_MNO_7000_HILO_FIX
:
10905 mips_7000_hilo_fix
= FALSE
;
10909 case OPTION_MDEBUG
:
10910 mips_flag_mdebug
= TRUE
;
10913 case OPTION_NO_MDEBUG
:
10914 mips_flag_mdebug
= FALSE
;
10918 mips_flag_pdr
= TRUE
;
10921 case OPTION_NO_PDR
:
10922 mips_flag_pdr
= FALSE
;
10924 #endif /* OBJ_ELF */
10933 /* Set up globals to generate code for the ISA or processor
10934 described by INFO. */
10937 mips_set_architecture (const struct mips_cpu_info
*info
)
10941 file_mips_arch
= info
->cpu
;
10942 mips_opts
.arch
= info
->cpu
;
10943 mips_opts
.isa
= info
->isa
;
10948 /* Likewise for tuning. */
10951 mips_set_tune (const struct mips_cpu_info
*info
)
10954 mips_tune
= info
->cpu
;
10959 mips_after_parse_args (void)
10961 const struct mips_cpu_info
*arch_info
= 0;
10962 const struct mips_cpu_info
*tune_info
= 0;
10964 /* GP relative stuff not working for PE */
10965 if (strncmp (TARGET_OS
, "pe", 2) == 0
10966 && g_switch_value
!= 0)
10969 as_bad (_("-G not supported in this configuration."));
10970 g_switch_value
= 0;
10973 if (mips_abi
== NO_ABI
)
10974 mips_abi
= MIPS_DEFAULT_ABI
;
10976 /* The following code determines the architecture and register size.
10977 Similar code was added to GCC 3.3 (see override_options() in
10978 config/mips/mips.c). The GAS and GCC code should be kept in sync
10979 as much as possible. */
10981 if (mips_arch_string
!= 0)
10982 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10984 if (file_mips_isa
!= ISA_UNKNOWN
)
10986 /* Handle -mipsN. At this point, file_mips_isa contains the
10987 ISA level specified by -mipsN, while arch_info->isa contains
10988 the -march selection (if any). */
10989 if (arch_info
!= 0)
10991 /* -march takes precedence over -mipsN, since it is more descriptive.
10992 There's no harm in specifying both as long as the ISA levels
10994 if (file_mips_isa
!= arch_info
->isa
)
10995 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10996 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10997 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11000 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11003 if (arch_info
== 0)
11004 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11006 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11007 as_bad ("-march=%s is not compatible with the selected ABI",
11010 mips_set_architecture (arch_info
);
11012 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11013 if (mips_tune_string
!= 0)
11014 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11016 if (tune_info
== 0)
11017 mips_set_tune (arch_info
);
11019 mips_set_tune (tune_info
);
11021 if (file_mips_gp32
>= 0)
11023 /* The user specified the size of the integer registers. Make sure
11024 it agrees with the ABI and ISA. */
11025 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11026 as_bad (_("-mgp64 used with a 32-bit processor"));
11027 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11028 as_bad (_("-mgp32 used with a 64-bit ABI"));
11029 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11030 as_bad (_("-mgp64 used with a 32-bit ABI"));
11034 /* Infer the integer register size from the ABI and processor.
11035 Restrict ourselves to 32-bit registers if that's all the
11036 processor has, or if the ABI cannot handle 64-bit registers. */
11037 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11038 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11041 /* ??? GAS treats single-float processors as though they had 64-bit
11042 float registers (although it complains when double-precision
11043 instructions are used). As things stand, saying they have 32-bit
11044 registers would lead to spurious "register must be even" messages.
11045 So here we assume float registers are always the same size as
11046 integer ones, unless the user says otherwise. */
11047 if (file_mips_fp32
< 0)
11048 file_mips_fp32
= file_mips_gp32
;
11050 /* End of GCC-shared inference code. */
11052 /* This flag is set when we have a 64-bit capable CPU but use only
11053 32-bit wide registers. Note that EABI does not use it. */
11054 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11055 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11056 || mips_abi
== O32_ABI
))
11057 mips_32bitmode
= 1;
11059 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11060 as_bad (_("trap exception not supported at ISA 1"));
11062 /* If the selected architecture includes support for ASEs, enable
11063 generation of code for them. */
11064 if (mips_opts
.mips16
== -1)
11065 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11066 if (mips_opts
.ase_mips3d
== -1)
11067 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
11068 if (mips_opts
.ase_mdmx
== -1)
11069 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
11071 file_mips_isa
= mips_opts
.isa
;
11072 file_ase_mips16
= mips_opts
.mips16
;
11073 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11074 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11075 mips_opts
.gp32
= file_mips_gp32
;
11076 mips_opts
.fp32
= file_mips_fp32
;
11078 if (mips_flag_mdebug
< 0)
11080 #ifdef OBJ_MAYBE_ECOFF
11081 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11082 mips_flag_mdebug
= 1;
11084 #endif /* OBJ_MAYBE_ECOFF */
11085 mips_flag_mdebug
= 0;
11090 mips_init_after_args (void)
11092 /* initialize opcodes */
11093 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11094 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11098 md_pcrel_from (fixS
*fixP
)
11100 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11101 switch (fixP
->fx_r_type
)
11103 case BFD_RELOC_16_PCREL_S2
:
11104 case BFD_RELOC_MIPS_JMP
:
11105 /* Return the address of the delay slot. */
11112 /* This is called before the symbol table is processed. In order to
11113 work with gcc when using mips-tfile, we must keep all local labels.
11114 However, in other cases, we want to discard them. If we were
11115 called with -g, but we didn't see any debugging information, it may
11116 mean that gcc is smuggling debugging information through to
11117 mips-tfile, in which case we must generate all local labels. */
11120 mips_frob_file_before_adjust (void)
11122 #ifndef NO_ECOFF_DEBUGGING
11123 if (ECOFF_DEBUGGING
11125 && ! ecoff_debugging_seen
)
11126 flag_keep_locals
= 1;
11130 /* Sort any unmatched HI16_S relocs so that they immediately precede
11131 the corresponding LO reloc. This is called before md_apply_fix3 and
11132 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
11133 explicit use of the %hi modifier. */
11136 mips_frob_file (void)
11138 struct mips_hi_fixup
*l
;
11140 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11142 segment_info_type
*seginfo
;
11145 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11147 /* If a GOT16 relocation turns out to be against a global symbol,
11148 there isn't supposed to be a matching LO. */
11149 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11150 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11153 /* Check quickly whether the next fixup happens to be a matching %lo. */
11154 if (fixup_has_matching_lo_p (l
->fixp
))
11157 /* Look through the fixups for this segment for a matching %lo.
11158 When we find one, move the %hi just in front of it. We do
11159 this in two passes. In the first pass, we try to find a
11160 unique %lo. In the second pass, we permit multiple %hi
11161 relocs for a single %lo (this is a GNU extension). */
11162 seginfo
= seg_info (l
->seg
);
11163 for (pass
= 0; pass
< 2; pass
++)
11168 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
11170 /* Check whether this is a %lo fixup which matches l->fixp. */
11171 if (f
->fx_r_type
== BFD_RELOC_LO16
11172 && f
->fx_addsy
== l
->fixp
->fx_addsy
11173 && f
->fx_offset
== l
->fixp
->fx_offset
11176 || !reloc_needs_lo_p (prev
->fx_r_type
)
11177 || !fixup_has_matching_lo_p (prev
)))
11181 /* Move l->fixp before f. */
11182 for (pf
= &seginfo
->fix_root
;
11184 pf
= &(*pf
)->fx_next
)
11185 assert (*pf
!= NULL
);
11187 *pf
= l
->fixp
->fx_next
;
11189 l
->fixp
->fx_next
= f
;
11191 seginfo
->fix_root
= l
->fixp
;
11193 prev
->fx_next
= l
->fixp
;
11204 #if 0 /* GCC code motion plus incomplete dead code elimination
11205 can leave a %hi without a %lo. */
11207 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
11208 _("Unmatched %%hi reloc"));
11214 /* When generating embedded PIC code we need to use a special
11215 relocation to represent the difference of two symbols in the .text
11216 section (switch tables use a difference of this sort). See
11217 include/coff/mips.h for details. This macro checks whether this
11218 fixup requires the special reloc. */
11219 #define SWITCH_TABLE(fixp) \
11220 ((fixp)->fx_r_type == BFD_RELOC_32 \
11221 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
11222 && (fixp)->fx_addsy != NULL \
11223 && (fixp)->fx_subsy != NULL \
11224 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
11225 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
11227 /* When generating embedded PIC code we must keep all PC relative
11228 relocations, in case the linker has to relax a call. We also need
11229 to keep relocations for switch table entries.
11231 We may have combined relocations without symbols in the N32/N64 ABI.
11232 We have to prevent gas from dropping them. */
11235 mips_force_relocation (fixS
*fixp
)
11237 if (generic_force_reloc (fixp
))
11241 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11242 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11243 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11244 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11247 return (mips_pic
== EMBEDDED_PIC
11249 || SWITCH_TABLE (fixp
)
11250 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
11251 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
11254 /* This hook is called before a fix is simplified. We don't really
11255 decide whether to skip a fix here. Rather, we turn global symbols
11256 used as branch targets into local symbols, such that they undergo
11257 simplification. We can only do this if the symbol is defined and
11258 it is in the same section as the branch. If this doesn't hold, we
11259 emit a better error message than just saying the relocation is not
11260 valid for the selected object format.
11262 FIXP is the fix-up we're going to try to simplify, SEG is the
11263 segment in which the fix up occurs. The return value should be
11264 non-zero to indicate the fix-up is valid for further
11265 simplifications. */
11268 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
11270 /* There's a lot of discussion on whether it should be possible to
11271 use R_MIPS_PC16 to represent branch relocations. The outcome
11272 seems to be that it can, but gas/bfd are very broken in creating
11273 RELA relocations for this, so for now we only accept branches to
11274 symbols in the same section. Anything else is of dubious value,
11275 since there's no guarantee that at link time the symbol would be
11276 in range. Even for branches to local symbols this is arguably
11277 wrong, since it we assume the symbol is not going to be
11278 overridden, which should be possible per ELF library semantics,
11279 but then, there isn't a dynamic relocation that could be used to
11280 this effect, and the target would likely be out of range as well.
11282 Unfortunately, it seems that there is too much code out there
11283 that relies on branches to symbols that are global to be resolved
11284 as if they were local, like the IRIX tools do, so we do it as
11285 well, but with a warning so that people are reminded to fix their
11286 code. If we ever get back to using R_MIPS_PC16 for branch
11287 targets, this entire block should go away (and probably the
11288 whole function). */
11290 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
11291 && (((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11292 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11293 && mips_pic
!= EMBEDDED_PIC
)
11294 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
11297 if (! S_IS_DEFINED (fixP
->fx_addsy
))
11299 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11300 _("Cannot branch to undefined symbol."));
11301 /* Avoid any further errors about this fixup. */
11304 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
11306 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11307 _("Cannot branch to symbol in another section."));
11310 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
11312 symbolS
*sym
= fixP
->fx_addsy
;
11314 if (mips_pic
== SVR4_PIC
)
11315 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
11316 _("Pretending global symbol used as branch target is local."));
11318 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
11319 S_GET_SEGMENT (sym
),
11321 symbol_get_frag (sym
));
11322 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
11323 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
11324 assert (symbol_resolved_p (sym
));
11325 symbol_mark_resolved (fixP
->fx_addsy
);
11332 /* Apply a fixup to the object file. */
11335 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11339 static int previous_fx_r_type
= 0;
11340 reloc_howto_type
*howto
;
11342 /* We ignore generic BFD relocations we don't know about. */
11343 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11347 assert (fixP
->fx_size
== 4
11348 || fixP
->fx_r_type
== BFD_RELOC_16
11349 || fixP
->fx_r_type
== BFD_RELOC_64
11350 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11351 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11352 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11353 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11355 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11357 /* We are not done if this is a composite relocation to set up gp. */
11358 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
11359 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11360 || (fixP
->fx_r_type
== BFD_RELOC_64
11361 && (previous_fx_r_type
== BFD_RELOC_GPREL32
11362 || previous_fx_r_type
== BFD_RELOC_GPREL16
))
11363 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
11364 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
11365 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
11367 previous_fx_r_type
= fixP
->fx_r_type
;
11369 switch (fixP
->fx_r_type
)
11371 case BFD_RELOC_MIPS_JMP
:
11372 case BFD_RELOC_MIPS_SHIFT5
:
11373 case BFD_RELOC_MIPS_SHIFT6
:
11374 case BFD_RELOC_MIPS_GOT_DISP
:
11375 case BFD_RELOC_MIPS_GOT_PAGE
:
11376 case BFD_RELOC_MIPS_GOT_OFST
:
11377 case BFD_RELOC_MIPS_SUB
:
11378 case BFD_RELOC_MIPS_INSERT_A
:
11379 case BFD_RELOC_MIPS_INSERT_B
:
11380 case BFD_RELOC_MIPS_DELETE
:
11381 case BFD_RELOC_MIPS_HIGHEST
:
11382 case BFD_RELOC_MIPS_HIGHER
:
11383 case BFD_RELOC_MIPS_SCN_DISP
:
11384 case BFD_RELOC_MIPS_REL16
:
11385 case BFD_RELOC_MIPS_RELGOT
:
11386 case BFD_RELOC_MIPS_JALR
:
11387 case BFD_RELOC_HI16
:
11388 case BFD_RELOC_HI16_S
:
11389 case BFD_RELOC_GPREL16
:
11390 case BFD_RELOC_MIPS_LITERAL
:
11391 case BFD_RELOC_MIPS_CALL16
:
11392 case BFD_RELOC_MIPS_GOT16
:
11393 case BFD_RELOC_GPREL32
:
11394 case BFD_RELOC_MIPS_GOT_HI16
:
11395 case BFD_RELOC_MIPS_GOT_LO16
:
11396 case BFD_RELOC_MIPS_CALL_HI16
:
11397 case BFD_RELOC_MIPS_CALL_LO16
:
11398 case BFD_RELOC_MIPS16_GPREL
:
11399 if (fixP
->fx_pcrel
)
11400 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11401 _("Invalid PC relative reloc"));
11402 /* Nothing needed to do. The value comes from the reloc entry */
11405 case BFD_RELOC_MIPS16_JMP
:
11406 /* We currently always generate a reloc against a symbol, which
11407 means that we don't want an addend even if the symbol is
11412 case BFD_RELOC_PCREL_HI16_S
:
11413 /* The addend for this is tricky if it is internal, so we just
11414 do everything here rather than in bfd_install_relocation. */
11415 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& !fixP
->fx_done
)
11418 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11420 /* For an external symbol adjust by the address to make it
11421 pcrel_offset. We use the address of the RELLO reloc
11422 which follows this one. */
11423 *valP
+= (fixP
->fx_next
->fx_frag
->fr_address
11424 + fixP
->fx_next
->fx_where
);
11426 *valP
= ((*valP
+ 0x8000) >> 16) & 0xffff;
11427 if (target_big_endian
)
11429 md_number_to_chars (buf
, *valP
, 2);
11432 case BFD_RELOC_PCREL_LO16
:
11433 /* The addend for this is tricky if it is internal, so we just
11434 do everything here rather than in bfd_install_relocation. */
11435 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& !fixP
->fx_done
)
11438 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11439 *valP
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11440 if (target_big_endian
)
11442 md_number_to_chars (buf
, *valP
, 2);
11446 /* This is handled like BFD_RELOC_32, but we output a sign
11447 extended value if we are only 32 bits. */
11449 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11451 if (8 <= sizeof (valueT
))
11452 md_number_to_chars (buf
, *valP
, 8);
11457 if ((*valP
& 0x80000000) != 0)
11461 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11463 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11469 case BFD_RELOC_RVA
:
11471 /* If we are deleting this reloc entry, we must fill in the
11472 value now. This can happen if we have a .word which is not
11473 resolved when it appears but is later defined. We also need
11474 to fill in the value if this is an embedded PIC switch table
11477 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11478 md_number_to_chars (buf
, *valP
, 4);
11482 /* If we are deleting this reloc entry, we must fill in the
11484 assert (fixP
->fx_size
== 2);
11486 md_number_to_chars (buf
, *valP
, 2);
11489 case BFD_RELOC_LO16
:
11490 /* When handling an embedded PIC switch statement, we can wind
11491 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11494 if (*valP
+ 0x8000 > 0xffff)
11495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11496 _("relocation overflow"));
11497 if (target_big_endian
)
11499 md_number_to_chars (buf
, *valP
, 2);
11503 case BFD_RELOC_16_PCREL_S2
:
11504 if ((*valP
& 0x3) != 0)
11505 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11506 _("Branch to odd address (%lx)"), (long) *valP
);
11509 * We need to save the bits in the instruction since fixup_segment()
11510 * might be deleting the relocation entry (i.e., a branch within
11511 * the current segment).
11513 if (! fixP
->fx_done
)
11516 /* update old instruction data */
11517 if (target_big_endian
)
11518 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11520 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11522 if (*valP
+ 0x20000 <= 0x3ffff)
11524 insn
|= (*valP
>> 2) & 0xffff;
11525 md_number_to_chars (buf
, insn
, 4);
11527 else if (mips_pic
== NO_PIC
11529 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11530 && (fixP
->fx_frag
->fr_address
11531 < text_section
->vma
+ text_section
->_raw_size
)
11532 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11533 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11534 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11536 /* The branch offset is too large. If this is an
11537 unconditional branch, and we are not generating PIC code,
11538 we can convert it to an absolute jump instruction. */
11539 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11540 insn
= 0x0c000000; /* jal */
11542 insn
= 0x08000000; /* j */
11543 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11545 fixP
->fx_addsy
= section_symbol (text_section
);
11546 *valP
+= md_pcrel_from (fixP
);
11547 md_number_to_chars (buf
, insn
, 4);
11551 /* If we got here, we have branch-relaxation disabled,
11552 and there's nothing we can do to fix this instruction
11553 without turning it into a longer sequence. */
11554 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11555 _("Branch out of range"));
11559 case BFD_RELOC_VTABLE_INHERIT
:
11562 && !S_IS_DEFINED (fixP
->fx_addsy
)
11563 && !S_IS_WEAK (fixP
->fx_addsy
))
11564 S_SET_WEAK (fixP
->fx_addsy
);
11567 case BFD_RELOC_VTABLE_ENTRY
:
11575 /* Remember value for tc_gen_reloc. */
11576 fixP
->fx_addnumber
= *valP
;
11581 printInsn (unsigned long oc
)
11583 const struct mips_opcode
*p
;
11584 int treg
, sreg
, dreg
, shamt
;
11589 for (i
= 0; i
< NUMOPCODES
; ++i
)
11591 p
= &mips_opcodes
[i
];
11592 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11594 printf ("%08lx %s\t", oc
, p
->name
);
11595 treg
= (oc
>> 16) & 0x1f;
11596 sreg
= (oc
>> 21) & 0x1f;
11597 dreg
= (oc
>> 11) & 0x1f;
11598 shamt
= (oc
>> 6) & 0x1f;
11600 for (args
= p
->args
;; ++args
)
11611 printf ("%c", *args
);
11615 assert (treg
== sreg
);
11616 printf ("$%d,$%d", treg
, sreg
);
11621 printf ("$%d", dreg
);
11626 printf ("$%d", treg
);
11630 printf ("0x%x", treg
);
11635 printf ("$%d", sreg
);
11639 printf ("0x%08lx", oc
& 0x1ffffff);
11646 printf ("%d", imm
);
11651 printf ("$%d", shamt
);
11662 printf (_("%08lx UNDEFINED\n"), oc
);
11673 name
= input_line_pointer
;
11674 c
= get_symbol_end ();
11675 p
= (symbolS
*) symbol_find_or_make (name
);
11676 *input_line_pointer
= c
;
11680 /* Align the current frag to a given power of two. The MIPS assembler
11681 also automatically adjusts any preceding label. */
11684 mips_align (int to
, int fill
, symbolS
*label
)
11686 mips_emit_delays (FALSE
);
11687 frag_align (to
, fill
, 0);
11688 record_alignment (now_seg
, to
);
11691 assert (S_GET_SEGMENT (label
) == now_seg
);
11692 symbol_set_frag (label
, frag_now
);
11693 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11697 /* Align to a given power of two. .align 0 turns off the automatic
11698 alignment used by the data creating pseudo-ops. */
11701 s_align (int x ATTRIBUTE_UNUSED
)
11704 register long temp_fill
;
11705 long max_alignment
= 15;
11709 o Note that the assembler pulls down any immediately preceding label
11710 to the aligned address.
11711 o It's not documented but auto alignment is reinstated by
11712 a .align pseudo instruction.
11713 o Note also that after auto alignment is turned off the mips assembler
11714 issues an error on attempt to assemble an improperly aligned data item.
11719 temp
= get_absolute_expression ();
11720 if (temp
> max_alignment
)
11721 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11724 as_warn (_("Alignment negative: 0 assumed."));
11727 if (*input_line_pointer
== ',')
11729 ++input_line_pointer
;
11730 temp_fill
= get_absolute_expression ();
11737 mips_align (temp
, (int) temp_fill
,
11738 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11745 demand_empty_rest_of_line ();
11749 mips_flush_pending_output (void)
11751 mips_emit_delays (FALSE
);
11752 mips_clear_insn_labels ();
11756 s_change_sec (int sec
)
11760 /* When generating embedded PIC code, we only use the .text, .lit8,
11761 .sdata and .sbss sections. We change the .data and .rdata
11762 pseudo-ops to use .sdata. */
11763 if (mips_pic
== EMBEDDED_PIC
11764 && (sec
== 'd' || sec
== 'r'))
11768 /* The ELF backend needs to know that we are changing sections, so
11769 that .previous works correctly. We could do something like check
11770 for an obj_section_change_hook macro, but that might be confusing
11771 as it would not be appropriate to use it in the section changing
11772 functions in read.c, since obj-elf.c intercepts those. FIXME:
11773 This should be cleaner, somehow. */
11774 obj_elf_section_change_hook ();
11777 mips_emit_delays (FALSE
);
11787 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11788 demand_empty_rest_of_line ();
11792 if (USE_GLOBAL_POINTER_OPT
)
11794 seg
= subseg_new (RDATA_SECTION_NAME
,
11795 (subsegT
) get_absolute_expression ());
11796 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11798 bfd_set_section_flags (stdoutput
, seg
,
11804 if (strcmp (TARGET_OS
, "elf") != 0)
11805 record_alignment (seg
, 4);
11807 demand_empty_rest_of_line ();
11811 as_bad (_("No read only data section in this object file format"));
11812 demand_empty_rest_of_line ();
11818 if (USE_GLOBAL_POINTER_OPT
)
11820 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11821 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11823 bfd_set_section_flags (stdoutput
, seg
,
11824 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
11826 if (strcmp (TARGET_OS
, "elf") != 0)
11827 record_alignment (seg
, 4);
11829 demand_empty_rest_of_line ();
11834 as_bad (_("Global pointers not supported; recompile -G 0"));
11835 demand_empty_rest_of_line ();
11844 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11847 char *section_name
;
11852 int section_entry_size
;
11853 int section_alignment
;
11855 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11858 section_name
= input_line_pointer
;
11859 c
= get_symbol_end ();
11861 next_c
= *(input_line_pointer
+ 1);
11863 /* Do we have .section Name<,"flags">? */
11864 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11866 /* just after name is now '\0'. */
11867 *input_line_pointer
= c
;
11868 input_line_pointer
= section_name
;
11869 obj_elf_section (ignore
);
11872 input_line_pointer
++;
11874 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11876 section_type
= get_absolute_expression ();
11879 if (*input_line_pointer
++ == ',')
11880 section_flag
= get_absolute_expression ();
11883 if (*input_line_pointer
++ == ',')
11884 section_entry_size
= get_absolute_expression ();
11886 section_entry_size
= 0;
11887 if (*input_line_pointer
++ == ',')
11888 section_alignment
= get_absolute_expression ();
11890 section_alignment
= 0;
11892 section_name
= xstrdup (section_name
);
11894 /* When using the generic form of .section (as implemented by obj-elf.c),
11895 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11896 traditionally had to fall back on the more common @progbits instead.
11898 There's nothing really harmful in this, since bfd will correct
11899 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11900 means that, for backwards compatibiltiy, the special_section entries
11901 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11903 Even so, we shouldn't force users of the MIPS .section syntax to
11904 incorrectly label the sections as SHT_PROGBITS. The best compromise
11905 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11906 generic type-checking code. */
11907 if (section_type
== SHT_MIPS_DWARF
)
11908 section_type
= SHT_PROGBITS
;
11910 obj_elf_change_section (section_name
, section_type
, section_flag
,
11911 section_entry_size
, 0, 0, 0);
11913 if (now_seg
->name
!= section_name
)
11914 free (section_name
);
11915 #endif /* OBJ_ELF */
11919 mips_enable_auto_align (void)
11925 s_cons (int log_size
)
11929 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11930 mips_emit_delays (FALSE
);
11931 if (log_size
> 0 && auto_align
)
11932 mips_align (log_size
, 0, label
);
11933 mips_clear_insn_labels ();
11934 cons (1 << log_size
);
11938 s_float_cons (int type
)
11942 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11944 mips_emit_delays (FALSE
);
11949 mips_align (3, 0, label
);
11951 mips_align (2, 0, label
);
11954 mips_clear_insn_labels ();
11959 /* Handle .globl. We need to override it because on Irix 5 you are
11962 where foo is an undefined symbol, to mean that foo should be
11963 considered to be the address of a function. */
11966 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11973 name
= input_line_pointer
;
11974 c
= get_symbol_end ();
11975 symbolP
= symbol_find_or_make (name
);
11976 *input_line_pointer
= c
;
11977 SKIP_WHITESPACE ();
11979 /* On Irix 5, every global symbol that is not explicitly labelled as
11980 being a function is apparently labelled as being an object. */
11983 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11988 secname
= input_line_pointer
;
11989 c
= get_symbol_end ();
11990 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11992 as_bad (_("%s: no such section"), secname
);
11993 *input_line_pointer
= c
;
11995 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11996 flag
= BSF_FUNCTION
;
11999 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12001 S_SET_EXTERNAL (symbolP
);
12002 demand_empty_rest_of_line ();
12006 s_option (int x ATTRIBUTE_UNUSED
)
12011 opt
= input_line_pointer
;
12012 c
= get_symbol_end ();
12016 /* FIXME: What does this mean? */
12018 else if (strncmp (opt
, "pic", 3) == 0)
12022 i
= atoi (opt
+ 3);
12027 mips_pic
= SVR4_PIC
;
12028 mips_abicalls
= TRUE
;
12031 as_bad (_(".option pic%d not supported"), i
);
12033 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
12035 if (g_switch_seen
&& g_switch_value
!= 0)
12036 as_warn (_("-G may not be used with SVR4 PIC code"));
12037 g_switch_value
= 0;
12038 bfd_set_gp_size (stdoutput
, 0);
12042 as_warn (_("Unrecognized option \"%s\""), opt
);
12044 *input_line_pointer
= c
;
12045 demand_empty_rest_of_line ();
12048 /* This structure is used to hold a stack of .set values. */
12050 struct mips_option_stack
12052 struct mips_option_stack
*next
;
12053 struct mips_set_options options
;
12056 static struct mips_option_stack
*mips_opts_stack
;
12058 /* Handle the .set pseudo-op. */
12061 s_mipsset (int x ATTRIBUTE_UNUSED
)
12063 char *name
= input_line_pointer
, ch
;
12065 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12066 ++input_line_pointer
;
12067 ch
= *input_line_pointer
;
12068 *input_line_pointer
= '\0';
12070 if (strcmp (name
, "reorder") == 0)
12072 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
12074 /* If we still have pending nops, we can discard them. The
12075 usual nop handling will insert any that are still
12077 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
12078 * (mips_opts
.mips16
? 2 : 4));
12079 prev_nop_frag
= NULL
;
12081 mips_opts
.noreorder
= 0;
12083 else if (strcmp (name
, "noreorder") == 0)
12085 mips_emit_delays (TRUE
);
12086 mips_opts
.noreorder
= 1;
12087 mips_any_noreorder
= 1;
12089 else if (strcmp (name
, "at") == 0)
12091 mips_opts
.noat
= 0;
12093 else if (strcmp (name
, "noat") == 0)
12095 mips_opts
.noat
= 1;
12097 else if (strcmp (name
, "macro") == 0)
12099 mips_opts
.warn_about_macros
= 0;
12101 else if (strcmp (name
, "nomacro") == 0)
12103 if (mips_opts
.noreorder
== 0)
12104 as_bad (_("`noreorder' must be set before `nomacro'"));
12105 mips_opts
.warn_about_macros
= 1;
12107 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12109 mips_opts
.nomove
= 0;
12111 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12113 mips_opts
.nomove
= 1;
12115 else if (strcmp (name
, "bopt") == 0)
12117 mips_opts
.nobopt
= 0;
12119 else if (strcmp (name
, "nobopt") == 0)
12121 mips_opts
.nobopt
= 1;
12123 else if (strcmp (name
, "mips16") == 0
12124 || strcmp (name
, "MIPS-16") == 0)
12125 mips_opts
.mips16
= 1;
12126 else if (strcmp (name
, "nomips16") == 0
12127 || strcmp (name
, "noMIPS-16") == 0)
12128 mips_opts
.mips16
= 0;
12129 else if (strcmp (name
, "mips3d") == 0)
12130 mips_opts
.ase_mips3d
= 1;
12131 else if (strcmp (name
, "nomips3d") == 0)
12132 mips_opts
.ase_mips3d
= 0;
12133 else if (strcmp (name
, "mdmx") == 0)
12134 mips_opts
.ase_mdmx
= 1;
12135 else if (strcmp (name
, "nomdmx") == 0)
12136 mips_opts
.ase_mdmx
= 0;
12137 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12141 /* Permit the user to change the ISA and architecture on the fly.
12142 Needless to say, misuse can cause serious problems. */
12143 if (strcmp (name
, "mips0") == 0)
12146 mips_opts
.isa
= file_mips_isa
;
12148 else if (strcmp (name
, "mips1") == 0)
12149 mips_opts
.isa
= ISA_MIPS1
;
12150 else if (strcmp (name
, "mips2") == 0)
12151 mips_opts
.isa
= ISA_MIPS2
;
12152 else if (strcmp (name
, "mips3") == 0)
12153 mips_opts
.isa
= ISA_MIPS3
;
12154 else if (strcmp (name
, "mips4") == 0)
12155 mips_opts
.isa
= ISA_MIPS4
;
12156 else if (strcmp (name
, "mips5") == 0)
12157 mips_opts
.isa
= ISA_MIPS5
;
12158 else if (strcmp (name
, "mips32") == 0)
12159 mips_opts
.isa
= ISA_MIPS32
;
12160 else if (strcmp (name
, "mips32r2") == 0)
12161 mips_opts
.isa
= ISA_MIPS32R2
;
12162 else if (strcmp (name
, "mips64") == 0)
12163 mips_opts
.isa
= ISA_MIPS64
;
12164 else if (strcmp (name
, "mips64r2") == 0)
12165 mips_opts
.isa
= ISA_MIPS64R2
;
12166 else if (strcmp (name
, "arch=default") == 0)
12169 mips_opts
.arch
= file_mips_arch
;
12170 mips_opts
.isa
= file_mips_isa
;
12172 else if (strncmp (name
, "arch=", 5) == 0)
12174 const struct mips_cpu_info
*p
;
12176 p
= mips_parse_cpu("internal use", name
+ 5);
12178 as_bad (_("unknown architecture %s"), name
+ 5);
12181 mips_opts
.arch
= p
->cpu
;
12182 mips_opts
.isa
= p
->isa
;
12186 as_bad (_("unknown ISA level %s"), name
+ 4);
12188 switch (mips_opts
.isa
)
12196 mips_opts
.gp32
= 1;
12197 mips_opts
.fp32
= 1;
12204 mips_opts
.gp32
= 0;
12205 mips_opts
.fp32
= 0;
12208 as_bad (_("unknown ISA level %s"), name
+ 4);
12213 mips_opts
.gp32
= file_mips_gp32
;
12214 mips_opts
.fp32
= file_mips_fp32
;
12217 else if (strcmp (name
, "autoextend") == 0)
12218 mips_opts
.noautoextend
= 0;
12219 else if (strcmp (name
, "noautoextend") == 0)
12220 mips_opts
.noautoextend
= 1;
12221 else if (strcmp (name
, "push") == 0)
12223 struct mips_option_stack
*s
;
12225 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12226 s
->next
= mips_opts_stack
;
12227 s
->options
= mips_opts
;
12228 mips_opts_stack
= s
;
12230 else if (strcmp (name
, "pop") == 0)
12232 struct mips_option_stack
*s
;
12234 s
= mips_opts_stack
;
12236 as_bad (_(".set pop with no .set push"));
12239 /* If we're changing the reorder mode we need to handle
12240 delay slots correctly. */
12241 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12242 mips_emit_delays (TRUE
);
12243 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12245 if (prev_nop_frag
!= NULL
)
12247 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
12248 * (mips_opts
.mips16
? 2 : 4));
12249 prev_nop_frag
= NULL
;
12253 mips_opts
= s
->options
;
12254 mips_opts_stack
= s
->next
;
12260 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12262 *input_line_pointer
= ch
;
12263 demand_empty_rest_of_line ();
12266 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12267 .option pic2. It means to generate SVR4 PIC calls. */
12270 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12272 mips_pic
= SVR4_PIC
;
12273 mips_abicalls
= TRUE
;
12274 if (USE_GLOBAL_POINTER_OPT
)
12276 if (g_switch_seen
&& g_switch_value
!= 0)
12277 as_warn (_("-G may not be used with SVR4 PIC code"));
12278 g_switch_value
= 0;
12280 bfd_set_gp_size (stdoutput
, 0);
12281 demand_empty_rest_of_line ();
12284 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12285 PIC code. It sets the $gp register for the function based on the
12286 function address, which is in the register named in the argument.
12287 This uses a relocation against _gp_disp, which is handled specially
12288 by the linker. The result is:
12289 lui $gp,%hi(_gp_disp)
12290 addiu $gp,$gp,%lo(_gp_disp)
12291 addu $gp,$gp,.cpload argument
12292 The .cpload argument is normally $25 == $t9. */
12295 s_cpload (int ignore ATTRIBUTE_UNUSED
)
12300 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12301 .cpload is ignored. */
12302 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12308 /* .cpload should be in a .set noreorder section. */
12309 if (mips_opts
.noreorder
== 0)
12310 as_warn (_(".cpload not in noreorder section"));
12312 ex
.X_op
= O_symbol
;
12313 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
12314 ex
.X_op_symbol
= NULL
;
12315 ex
.X_add_number
= 0;
12317 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12318 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12320 macro_build_lui (NULL
, &icnt
, &ex
, mips_gp_register
);
12321 macro_build (NULL
, &icnt
, &ex
, "addiu", "t,r,j", mips_gp_register
,
12322 mips_gp_register
, BFD_RELOC_LO16
);
12324 macro_build (NULL
, &icnt
, NULL
, "addu", "d,v,t", mips_gp_register
,
12325 mips_gp_register
, tc_get_register (0));
12327 demand_empty_rest_of_line ();
12330 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12331 .cpsetup $reg1, offset|$reg2, label
12333 If offset is given, this results in:
12334 sd $gp, offset($sp)
12335 lui $gp, %hi(%neg(%gp_rel(label)))
12336 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12337 daddu $gp, $gp, $reg1
12339 If $reg2 is given, this results in:
12340 daddu $reg2, $gp, $0
12341 lui $gp, %hi(%neg(%gp_rel(label)))
12342 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12343 daddu $gp, $gp, $reg1
12344 $reg1 is normally $25 == $t9. */
12346 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
12348 expressionS ex_off
;
12349 expressionS ex_sym
;
12354 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12355 We also need NewABI support. */
12356 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12362 reg1
= tc_get_register (0);
12363 SKIP_WHITESPACE ();
12364 if (*input_line_pointer
!= ',')
12366 as_bad (_("missing argument separator ',' for .cpsetup"));
12370 ++input_line_pointer
;
12371 SKIP_WHITESPACE ();
12372 if (*input_line_pointer
== '$')
12374 mips_cpreturn_register
= tc_get_register (0);
12375 mips_cpreturn_offset
= -1;
12379 mips_cpreturn_offset
= get_absolute_expression ();
12380 mips_cpreturn_register
= -1;
12382 SKIP_WHITESPACE ();
12383 if (*input_line_pointer
!= ',')
12385 as_bad (_("missing argument separator ',' for .cpsetup"));
12389 ++input_line_pointer
;
12390 SKIP_WHITESPACE ();
12391 expression (&ex_sym
);
12393 if (mips_cpreturn_register
== -1)
12395 ex_off
.X_op
= O_constant
;
12396 ex_off
.X_add_symbol
= NULL
;
12397 ex_off
.X_op_symbol
= NULL
;
12398 ex_off
.X_add_number
= mips_cpreturn_offset
;
12400 macro_build (NULL
, &icnt
, &ex_off
, "sd", "t,o(b)", mips_gp_register
,
12401 BFD_RELOC_LO16
, SP
);
12404 macro_build (NULL
, &icnt
, NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
12405 mips_gp_register
, 0);
12407 /* Ensure there's room for the next two instructions, so that `f'
12408 doesn't end up with an address in the wrong frag. */
12411 macro_build (NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
12412 BFD_RELOC_GPREL16
);
12413 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12414 8, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12415 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12416 4, NULL
, 0, 0, BFD_RELOC_HI16_S
);
12419 macro_build (NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j", mips_gp_register
,
12420 mips_gp_register
, BFD_RELOC_GPREL16
);
12421 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12422 8, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12423 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12424 4, NULL
, 0, 0, BFD_RELOC_LO16
);
12426 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
12427 mips_gp_register
, reg1
);
12429 demand_empty_rest_of_line ();
12433 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12435 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12436 .cplocal is ignored. */
12437 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12443 mips_gp_register
= tc_get_register (0);
12444 demand_empty_rest_of_line ();
12447 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12448 offset from $sp. The offset is remembered, and after making a PIC
12449 call $gp is restored from that location. */
12452 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12457 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12458 .cprestore is ignored. */
12459 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12465 mips_cprestore_offset
= get_absolute_expression ();
12466 mips_cprestore_valid
= 1;
12468 ex
.X_op
= O_constant
;
12469 ex
.X_add_symbol
= NULL
;
12470 ex
.X_op_symbol
= NULL
;
12471 ex
.X_add_number
= mips_cprestore_offset
;
12473 macro_build_ldst_constoffset (NULL
, &icnt
, &ex
, ADDRESS_STORE_INSN
,
12474 mips_gp_register
, SP
, HAVE_64BIT_ADDRESSES
);
12476 demand_empty_rest_of_line ();
12479 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12480 was given in the preceding .cpsetup, it results in:
12481 ld $gp, offset($sp)
12483 If a register $reg2 was given there, it results in:
12484 daddu $gp, $reg2, $0
12487 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12492 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12493 We also need NewABI support. */
12494 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12500 if (mips_cpreturn_register
== -1)
12502 ex
.X_op
= O_constant
;
12503 ex
.X_add_symbol
= NULL
;
12504 ex
.X_op_symbol
= NULL
;
12505 ex
.X_add_number
= mips_cpreturn_offset
;
12507 macro_build (NULL
, &icnt
, &ex
, "ld", "t,o(b)", mips_gp_register
,
12508 BFD_RELOC_LO16
, SP
);
12511 macro_build (NULL
, &icnt
, NULL
, "daddu", "d,v,t", mips_gp_register
,
12512 mips_cpreturn_register
, 0);
12514 demand_empty_rest_of_line ();
12517 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12518 code. It sets the offset to use in gp_rel relocations. */
12521 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12523 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12524 We also need NewABI support. */
12525 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12531 mips_gprel_offset
= get_absolute_expression ();
12533 demand_empty_rest_of_line ();
12536 /* Handle the .gpword pseudo-op. This is used when generating PIC
12537 code. It generates a 32 bit GP relative reloc. */
12540 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12546 /* When not generating PIC code, this is treated as .word. */
12547 if (mips_pic
!= SVR4_PIC
)
12553 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12554 mips_emit_delays (TRUE
);
12556 mips_align (2, 0, label
);
12557 mips_clear_insn_labels ();
12561 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12563 as_bad (_("Unsupported use of .gpword"));
12564 ignore_rest_of_line ();
12568 md_number_to_chars (p
, 0, 4);
12569 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12570 BFD_RELOC_GPREL32
);
12572 demand_empty_rest_of_line ();
12576 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12582 /* When not generating PIC code, this is treated as .dword. */
12583 if (mips_pic
!= SVR4_PIC
)
12589 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12590 mips_emit_delays (TRUE
);
12592 mips_align (3, 0, label
);
12593 mips_clear_insn_labels ();
12597 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12599 as_bad (_("Unsupported use of .gpdword"));
12600 ignore_rest_of_line ();
12604 md_number_to_chars (p
, 0, 8);
12605 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12606 BFD_RELOC_GPREL32
);
12608 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12609 ex
.X_op
= O_absent
;
12610 ex
.X_add_symbol
= 0;
12611 ex
.X_add_number
= 0;
12612 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12615 demand_empty_rest_of_line ();
12618 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12619 tables in SVR4 PIC code. */
12622 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12627 /* This is ignored when not generating SVR4 PIC code. */
12628 if (mips_pic
!= SVR4_PIC
)
12634 /* Add $gp to the register named as an argument. */
12635 reg
= tc_get_register (0);
12636 macro_build (NULL
, &icnt
, NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12637 reg
, reg
, mips_gp_register
);
12639 demand_empty_rest_of_line ();
12642 /* Handle the .insn pseudo-op. This marks instruction labels in
12643 mips16 mode. This permits the linker to handle them specially,
12644 such as generating jalx instructions when needed. We also make
12645 them odd for the duration of the assembly, in order to generate the
12646 right sort of code. We will make them even in the adjust_symtab
12647 routine, while leaving them marked. This is convenient for the
12648 debugger and the disassembler. The linker knows to make them odd
12652 s_insn (int ignore ATTRIBUTE_UNUSED
)
12654 mips16_mark_labels ();
12656 demand_empty_rest_of_line ();
12659 /* Handle a .stabn directive. We need these in order to mark a label
12660 as being a mips16 text label correctly. Sometimes the compiler
12661 will emit a label, followed by a .stabn, and then switch sections.
12662 If the label and .stabn are in mips16 mode, then the label is
12663 really a mips16 text label. */
12666 s_mips_stab (int type
)
12669 mips16_mark_labels ();
12674 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12678 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12685 name
= input_line_pointer
;
12686 c
= get_symbol_end ();
12687 symbolP
= symbol_find_or_make (name
);
12688 S_SET_WEAK (symbolP
);
12689 *input_line_pointer
= c
;
12691 SKIP_WHITESPACE ();
12693 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12695 if (S_IS_DEFINED (symbolP
))
12697 as_bad ("ignoring attempt to redefine symbol %s",
12698 S_GET_NAME (symbolP
));
12699 ignore_rest_of_line ();
12703 if (*input_line_pointer
== ',')
12705 ++input_line_pointer
;
12706 SKIP_WHITESPACE ();
12710 if (exp
.X_op
!= O_symbol
)
12712 as_bad ("bad .weakext directive");
12713 ignore_rest_of_line ();
12716 symbol_set_value_expression (symbolP
, &exp
);
12719 demand_empty_rest_of_line ();
12722 /* Parse a register string into a number. Called from the ECOFF code
12723 to parse .frame. The argument is non-zero if this is the frame
12724 register, so that we can record it in mips_frame_reg. */
12727 tc_get_register (int frame
)
12731 SKIP_WHITESPACE ();
12732 if (*input_line_pointer
++ != '$')
12734 as_warn (_("expected `$'"));
12737 else if (ISDIGIT (*input_line_pointer
))
12739 reg
= get_absolute_expression ();
12740 if (reg
< 0 || reg
>= 32)
12742 as_warn (_("Bad register number"));
12748 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12751 input_line_pointer
+= 2;
12753 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12756 input_line_pointer
+= 2;
12758 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12761 input_line_pointer
+= 2;
12763 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12766 input_line_pointer
+= 2;
12768 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12771 input_line_pointer
+= 2;
12773 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12776 input_line_pointer
+= 3;
12778 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12781 input_line_pointer
+= 3;
12783 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12786 input_line_pointer
+= 4;
12790 as_warn (_("Unrecognized register name"));
12792 while (ISALNUM(*input_line_pointer
))
12793 input_line_pointer
++;
12798 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12799 mips_frame_reg_valid
= 1;
12800 mips_cprestore_valid
= 0;
12806 md_section_align (asection
*seg
, valueT addr
)
12808 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12811 /* We don't need to align ELF sections to the full alignment.
12812 However, Irix 5 may prefer that we align them at least to a 16
12813 byte boundary. We don't bother to align the sections if we are
12814 targeted for an embedded system. */
12815 if (strcmp (TARGET_OS
, "elf") == 0)
12821 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12824 /* Utility routine, called from above as well. If called while the
12825 input file is still being read, it's only an approximation. (For
12826 example, a symbol may later become defined which appeared to be
12827 undefined earlier.) */
12830 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12835 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
12837 const char *symname
;
12840 /* Find out whether this symbol can be referenced off the $gp
12841 register. It can be if it is smaller than the -G size or if
12842 it is in the .sdata or .sbss section. Certain symbols can
12843 not be referenced off the $gp, although it appears as though
12845 symname
= S_GET_NAME (sym
);
12846 if (symname
!= (const char *) NULL
12847 && (strcmp (symname
, "eprol") == 0
12848 || strcmp (symname
, "etext") == 0
12849 || strcmp (symname
, "_gp") == 0
12850 || strcmp (symname
, "edata") == 0
12851 || strcmp (symname
, "_fbss") == 0
12852 || strcmp (symname
, "_fdata") == 0
12853 || strcmp (symname
, "_ftext") == 0
12854 || strcmp (symname
, "end") == 0
12855 || strcmp (symname
, "_gp_disp") == 0))
12857 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12859 #ifndef NO_ECOFF_DEBUGGING
12860 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12861 && (symbol_get_obj (sym
)->ecoff_extern_size
12862 <= g_switch_value
))
12864 /* We must defer this decision until after the whole
12865 file has been read, since there might be a .extern
12866 after the first use of this symbol. */
12867 || (before_relaxing
12868 #ifndef NO_ECOFF_DEBUGGING
12869 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12871 && S_GET_VALUE (sym
) == 0)
12872 || (S_GET_VALUE (sym
) != 0
12873 && S_GET_VALUE (sym
) <= g_switch_value
)))
12877 const char *segname
;
12879 segname
= segment_name (S_GET_SEGMENT (sym
));
12880 assert (strcmp (segname
, ".lit8") != 0
12881 && strcmp (segname
, ".lit4") != 0);
12882 change
= (strcmp (segname
, ".sdata") != 0
12883 && strcmp (segname
, ".sbss") != 0
12884 && strncmp (segname
, ".sdata.", 7) != 0
12885 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12890 /* We are not optimizing for the $gp register. */
12895 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12898 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12901 bfd_boolean linkonce
;
12903 /* Handle the case of a symbol equated to another symbol. */
12904 while (symbol_equated_reloc_p (sym
))
12908 /* It's possible to get a loop here in a badly written
12910 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12916 symsec
= S_GET_SEGMENT (sym
);
12918 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12920 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12922 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12926 /* The GNU toolchain uses an extension for ELF: a section
12927 beginning with the magic string .gnu.linkonce is a linkonce
12929 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12930 sizeof ".gnu.linkonce" - 1) == 0)
12934 /* This must duplicate the test in adjust_reloc_syms. */
12935 return (symsec
!= &bfd_und_section
12936 && symsec
!= &bfd_abs_section
12937 && ! bfd_is_com_section (symsec
)
12940 /* A global or weak symbol is treated as external. */
12941 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12942 || (! S_IS_WEAK (sym
)
12943 && (! S_IS_EXTERNAL (sym
)
12944 || mips_pic
== EMBEDDED_PIC
)))
12950 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12951 extended opcode. SEC is the section the frag is in. */
12954 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12957 register const struct mips16_immed_operand
*op
;
12959 int mintiny
, maxtiny
;
12963 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12965 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12968 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12969 op
= mips16_immed_operands
;
12970 while (op
->type
!= type
)
12973 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12978 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12981 maxtiny
= 1 << op
->nbits
;
12986 maxtiny
= (1 << op
->nbits
) - 1;
12991 mintiny
= - (1 << (op
->nbits
- 1));
12992 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12995 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12996 val
= S_GET_VALUE (fragp
->fr_symbol
);
12997 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13003 /* We won't have the section when we are called from
13004 mips_relax_frag. However, we will always have been called
13005 from md_estimate_size_before_relax first. If this is a
13006 branch to a different section, we mark it as such. If SEC is
13007 NULL, and the frag is not marked, then it must be a branch to
13008 the same section. */
13011 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13016 /* Must have been called from md_estimate_size_before_relax. */
13019 fragp
->fr_subtype
=
13020 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13022 /* FIXME: We should support this, and let the linker
13023 catch branches and loads that are out of range. */
13024 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13025 _("unsupported PC relative reference to different section"));
13029 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13030 /* Assume non-extended on the first relaxation pass.
13031 The address we have calculated will be bogus if this is
13032 a forward branch to another frag, as the forward frag
13033 will have fr_address == 0. */
13037 /* In this case, we know for sure that the symbol fragment is in
13038 the same section. If the relax_marker of the symbol fragment
13039 differs from the relax_marker of this fragment, we have not
13040 yet adjusted the symbol fragment fr_address. We want to add
13041 in STRETCH in order to get a better estimate of the address.
13042 This particularly matters because of the shift bits. */
13044 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13048 /* Adjust stretch for any alignment frag. Note that if have
13049 been expanding the earlier code, the symbol may be
13050 defined in what appears to be an earlier frag. FIXME:
13051 This doesn't handle the fr_subtype field, which specifies
13052 a maximum number of bytes to skip when doing an
13054 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13056 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13059 stretch
= - ((- stretch
)
13060 & ~ ((1 << (int) f
->fr_offset
) - 1));
13062 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13071 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13073 /* The base address rules are complicated. The base address of
13074 a branch is the following instruction. The base address of a
13075 PC relative load or add is the instruction itself, but if it
13076 is in a delay slot (in which case it can not be extended) use
13077 the address of the instruction whose delay slot it is in. */
13078 if (type
== 'p' || type
== 'q')
13082 /* If we are currently assuming that this frag should be
13083 extended, then, the current address is two bytes
13085 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13088 /* Ignore the low bit in the target, since it will be set
13089 for a text label. */
13090 if ((val
& 1) != 0)
13093 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13095 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13098 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13100 /* Branch offsets have an implicit 0 in the lowest bit. */
13101 if (type
== 'p' || type
== 'q')
13104 /* If any of the shifted bits are set, we must use an extended
13105 opcode. If the address depends on the size of this
13106 instruction, this can lead to a loop, so we arrange to always
13107 use an extended opcode. We only check this when we are in
13108 the main relaxation loop, when SEC is NULL. */
13109 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13111 fragp
->fr_subtype
=
13112 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13116 /* If we are about to mark a frag as extended because the value
13117 is precisely maxtiny + 1, then there is a chance of an
13118 infinite loop as in the following code:
13123 In this case when the la is extended, foo is 0x3fc bytes
13124 away, so the la can be shrunk, but then foo is 0x400 away, so
13125 the la must be extended. To avoid this loop, we mark the
13126 frag as extended if it was small, and is about to become
13127 extended with a value of maxtiny + 1. */
13128 if (val
== ((maxtiny
+ 1) << op
->shift
)
13129 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13132 fragp
->fr_subtype
=
13133 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13137 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13138 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13140 if ((val
& ((1 << op
->shift
) - 1)) != 0
13141 || val
< (mintiny
<< op
->shift
)
13142 || val
> (maxtiny
<< op
->shift
))
13148 /* Compute the length of a branch sequence, and adjust the
13149 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13150 worst-case length is computed, with UPDATE being used to indicate
13151 whether an unconditional (-1), branch-likely (+1) or regular (0)
13152 branch is to be computed. */
13154 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13156 bfd_boolean toofar
;
13160 && S_IS_DEFINED (fragp
->fr_symbol
)
13161 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13166 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13168 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13172 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13175 /* If the symbol is not defined or it's in a different segment,
13176 assume the user knows what's going on and emit a short
13182 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13184 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13185 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13186 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13192 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13195 if (mips_pic
!= NO_PIC
)
13197 /* Additional space for PIC loading of target address. */
13199 if (mips_opts
.isa
== ISA_MIPS1
)
13200 /* Additional space for $at-stabilizing nop. */
13204 /* If branch is conditional. */
13205 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13212 /* Estimate the size of a frag before relaxing. Unless this is the
13213 mips16, we are not really relaxing here, and the final size is
13214 encoded in the subtype information. For the mips16, we have to
13215 decide whether we are using an extended opcode or not. */
13218 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13222 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13225 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13227 return fragp
->fr_var
;
13230 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13231 /* We don't want to modify the EXTENDED bit here; it might get us
13232 into infinite loops. We change it only in mips_relax_frag(). */
13233 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13235 if (mips_pic
== NO_PIC
)
13236 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13237 else if (mips_pic
== SVR4_PIC
)
13238 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13244 /* Record the offset to the first reloc in the fr_opcode field.
13245 This lets md_convert_frag and tc_gen_reloc know that the code
13246 must be expanded. */
13247 fragp
->fr_opcode
= (fragp
->fr_literal
13249 - RELAX_OLD (fragp
->fr_subtype
)
13250 + RELAX_RELOC1 (fragp
->fr_subtype
));
13251 /* FIXME: This really needs as_warn_where. */
13252 if (RELAX_WARN (fragp
->fr_subtype
))
13253 as_warn (_("AT used after \".set noat\" or macro used after "
13254 "\".set nomacro\""));
13256 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
13262 /* This is called to see whether a reloc against a defined symbol
13263 should be converted into a reloc against a section. Don't adjust
13264 MIPS16 jump relocations, so we don't have to worry about the format
13265 of the offset in the .o file. Don't adjust relocations against
13266 mips16 symbols, so that the linker can find them if it needs to set
13270 mips_fix_adjustable (fixS
*fixp
)
13272 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13275 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13276 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13279 if (fixp
->fx_addsy
== NULL
)
13283 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13284 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13285 && fixp
->fx_subsy
== NULL
)
13292 /* Translate internal representation of relocation info to BFD target
13296 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13298 static arelent
*retval
[4];
13300 bfd_reloc_code_real_type code
;
13302 memset (retval
, 0, sizeof(retval
));
13303 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13304 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13305 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13306 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13308 if (mips_pic
== EMBEDDED_PIC
13309 && SWITCH_TABLE (fixp
))
13311 /* For a switch table entry we use a special reloc. The addend
13312 is actually the difference between the reloc address and the
13314 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13315 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
13316 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13317 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
13319 else if (fixp
->fx_pcrel
)
13321 bfd_vma pcrel_address
;
13323 /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high
13324 high-part relocs is the address of the low-part reloc. */
13325 if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
13327 assert (fixp
->fx_next
!= NULL
13328 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
13329 pcrel_address
= (fixp
->fx_next
->fx_where
13330 + fixp
->fx_next
->fx_frag
->fr_address
);
13333 pcrel_address
= reloc
->address
;
13335 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13337 /* At this point, fx_addnumber is "symbol offset - pcrel_address".
13338 Relocations want only the symbol offset. */
13339 reloc
->addend
= fixp
->fx_addnumber
+ pcrel_address
;
13341 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
13342 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
13344 /* We use a special addend for an internal RELLO or RELHI reloc. */
13345 if (symbol_section_p (fixp
->fx_addsy
))
13346 reloc
->addend
= pcrel_address
- S_GET_VALUE (fixp
->fx_subsy
);
13348 reloc
->addend
= fixp
->fx_addnumber
+ pcrel_address
;
13352 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
13353 /* A gruesome hack which is a result of the gruesome gas reloc
13355 reloc
->addend
= pcrel_address
;
13357 reloc
->addend
= -pcrel_address
;
13361 reloc
->addend
= fixp
->fx_addnumber
;
13363 /* If this is a variant frag, we may need to adjust the existing
13364 reloc and generate a new one. */
13365 if (fixp
->fx_frag
->fr_opcode
!= NULL
13366 && ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13368 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_DISP
13370 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
13371 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
13372 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13373 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
13374 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13375 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
13380 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
13382 /* If this is not the last reloc in this frag, then we have two
13383 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13384 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13385 the second one handle all of them. */
13386 if (fixp
->fx_next
!= NULL
13387 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
13389 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13390 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
13391 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13392 && (fixp
->fx_next
->fx_r_type
13393 == BFD_RELOC_MIPS_GOT_LO16
))
13394 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13395 && (fixp
->fx_next
->fx_r_type
13396 == BFD_RELOC_MIPS_CALL_LO16
)));
13401 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
13402 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13403 reloc
->addend
+= fixp
->fx_frag
->tc_frag_data
.tc_fr_offset
;
13404 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
13405 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13406 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13407 reloc2
->address
= (reloc
->address
13408 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
13409 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
13410 reloc2
->addend
= reloc
->addend
;
13411 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
13412 assert (reloc2
->howto
!= NULL
);
13414 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
13418 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
13420 reloc3
->address
+= 4;
13423 if (mips_pic
== NO_PIC
)
13425 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
13426 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
13428 else if (mips_pic
== SVR4_PIC
)
13430 switch (fixp
->fx_r_type
)
13434 case BFD_RELOC_MIPS_GOT16
:
13436 case BFD_RELOC_MIPS_GOT_LO16
:
13437 case BFD_RELOC_MIPS_CALL_LO16
:
13440 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_PAGE
;
13441 reloc2
->howto
= bfd_reloc_type_lookup
13442 (stdoutput
, BFD_RELOC_MIPS_GOT_OFST
);
13445 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13447 case BFD_RELOC_MIPS_CALL16
:
13448 case BFD_RELOC_MIPS_GOT_OFST
:
13449 case BFD_RELOC_MIPS_GOT_DISP
:
13452 /* It may seem nonsensical to relax GOT_DISP to
13453 GOT_DISP, but we're actually turning a GOT_DISP
13454 without offset into a GOT_DISP with an offset,
13455 getting rid of the separate addition, which we can
13456 do when the symbol is found to be local. */
13457 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_DISP
;
13461 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13469 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13470 entry to be used in the relocation's section offset. */
13471 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13473 reloc
->address
= reloc
->addend
;
13477 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13478 fixup_segment converted a non-PC relative reloc into a PC
13479 relative reloc. In such a case, we need to convert the reloc
13481 code
= fixp
->fx_r_type
;
13482 if (fixp
->fx_pcrel
)
13487 code
= BFD_RELOC_8_PCREL
;
13490 code
= BFD_RELOC_16_PCREL
;
13493 code
= BFD_RELOC_32_PCREL
;
13496 code
= BFD_RELOC_64_PCREL
;
13498 case BFD_RELOC_8_PCREL
:
13499 case BFD_RELOC_16_PCREL
:
13500 case BFD_RELOC_32_PCREL
:
13501 case BFD_RELOC_64_PCREL
:
13502 case BFD_RELOC_16_PCREL_S2
:
13503 case BFD_RELOC_PCREL_HI16_S
:
13504 case BFD_RELOC_PCREL_LO16
:
13507 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13508 _("Cannot make %s relocation PC relative"),
13509 bfd_get_reloc_code_name (code
));
13513 /* To support a PC relative reloc when generating embedded PIC code
13514 for ECOFF, we use a Cygnus extension. We check for that here to
13515 make sure that we don't let such a reloc escape normally. */
13516 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
13517 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13518 && code
== BFD_RELOC_16_PCREL_S2
13519 && mips_pic
!= EMBEDDED_PIC
)
13520 reloc
->howto
= NULL
;
13522 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13524 if (reloc
->howto
== NULL
)
13526 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13527 _("Can not represent %s relocation in this object file format"),
13528 bfd_get_reloc_code_name (code
));
13535 /* Relax a machine dependent frag. This returns the amount by which
13536 the current size of the frag should change. */
13539 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
13541 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13543 offsetT old_var
= fragp
->fr_var
;
13545 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13547 return fragp
->fr_var
- old_var
;
13550 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13553 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13555 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13557 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13562 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13564 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13571 /* Convert a machine dependent frag. */
13574 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
13579 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13582 unsigned long insn
;
13586 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13588 if (target_big_endian
)
13589 insn
= bfd_getb32 (buf
);
13591 insn
= bfd_getl32 (buf
);
13593 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13595 /* We generate a fixup instead of applying it right now
13596 because, if there are linker relaxations, we're going to
13597 need the relocations. */
13598 exp
.X_op
= O_symbol
;
13599 exp
.X_add_symbol
= fragp
->fr_symbol
;
13600 exp
.X_add_number
= fragp
->fr_offset
;
13602 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13604 BFD_RELOC_16_PCREL_S2
);
13605 fixp
->fx_file
= fragp
->fr_file
;
13606 fixp
->fx_line
= fragp
->fr_line
;
13608 md_number_to_chars (buf
, insn
, 4);
13615 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13616 _("relaxed out-of-range branch into a jump"));
13618 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13621 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13623 /* Reverse the branch. */
13624 switch ((insn
>> 28) & 0xf)
13627 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13628 have the condition reversed by tweaking a single
13629 bit, and their opcodes all have 0x4???????. */
13630 assert ((insn
& 0xf1000000) == 0x41000000);
13631 insn
^= 0x00010000;
13635 /* bltz 0x04000000 bgez 0x04010000
13636 bltzal 0x04100000 bgezal 0x04110000 */
13637 assert ((insn
& 0xfc0e0000) == 0x04000000);
13638 insn
^= 0x00010000;
13642 /* beq 0x10000000 bne 0x14000000
13643 blez 0x18000000 bgtz 0x1c000000 */
13644 insn
^= 0x04000000;
13652 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13654 /* Clear the and-link bit. */
13655 assert ((insn
& 0xfc1c0000) == 0x04100000);
13657 /* bltzal 0x04100000 bgezal 0x04110000
13658 bltzall 0x04120000 bgezall 0x04130000 */
13659 insn
&= ~0x00100000;
13662 /* Branch over the branch (if the branch was likely) or the
13663 full jump (not likely case). Compute the offset from the
13664 current instruction to branch to. */
13665 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13669 /* How many bytes in instructions we've already emitted? */
13670 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13671 /* How many bytes in instructions from here to the end? */
13672 i
= fragp
->fr_var
- i
;
13674 /* Convert to instruction count. */
13676 /* Branch counts from the next instruction. */
13679 /* Branch over the jump. */
13680 md_number_to_chars (buf
, insn
, 4);
13684 md_number_to_chars (buf
, 0, 4);
13687 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13689 /* beql $0, $0, 2f */
13691 /* Compute the PC offset from the current instruction to
13692 the end of the variable frag. */
13693 /* How many bytes in instructions we've already emitted? */
13694 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13695 /* How many bytes in instructions from here to the end? */
13696 i
= fragp
->fr_var
- i
;
13697 /* Convert to instruction count. */
13699 /* Don't decrement i, because we want to branch over the
13703 md_number_to_chars (buf
, insn
, 4);
13706 md_number_to_chars (buf
, 0, 4);
13711 if (mips_pic
== NO_PIC
)
13714 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13715 ? 0x0c000000 : 0x08000000);
13716 exp
.X_op
= O_symbol
;
13717 exp
.X_add_symbol
= fragp
->fr_symbol
;
13718 exp
.X_add_number
= fragp
->fr_offset
;
13720 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13721 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13722 fixp
->fx_file
= fragp
->fr_file
;
13723 fixp
->fx_line
= fragp
->fr_line
;
13725 md_number_to_chars (buf
, insn
, 4);
13730 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13731 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13732 exp
.X_op
= O_symbol
;
13733 exp
.X_add_symbol
= fragp
->fr_symbol
;
13734 exp
.X_add_number
= fragp
->fr_offset
;
13736 if (fragp
->fr_offset
)
13738 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13739 exp
.X_add_number
= 0;
13742 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13743 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13744 fixp
->fx_file
= fragp
->fr_file
;
13745 fixp
->fx_line
= fragp
->fr_line
;
13747 md_number_to_chars (buf
, insn
, 4);
13750 if (mips_opts
.isa
== ISA_MIPS1
)
13753 md_number_to_chars (buf
, 0, 4);
13757 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13758 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13760 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13761 4, &exp
, 0, BFD_RELOC_LO16
);
13762 fixp
->fx_file
= fragp
->fr_file
;
13763 fixp
->fx_line
= fragp
->fr_line
;
13765 md_number_to_chars (buf
, insn
, 4);
13769 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13774 md_number_to_chars (buf
, insn
, 4);
13779 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13780 + fragp
->fr_fix
+ fragp
->fr_var
);
13782 fragp
->fr_fix
+= fragp
->fr_var
;
13787 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13790 register const struct mips16_immed_operand
*op
;
13791 bfd_boolean small
, ext
;
13794 unsigned long insn
;
13795 bfd_boolean use_extend
;
13796 unsigned short extend
;
13798 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13799 op
= mips16_immed_operands
;
13800 while (op
->type
!= type
)
13803 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13814 resolve_symbol_value (fragp
->fr_symbol
);
13815 val
= S_GET_VALUE (fragp
->fr_symbol
);
13820 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13822 /* The rules for the base address of a PC relative reloc are
13823 complicated; see mips16_extended_frag. */
13824 if (type
== 'p' || type
== 'q')
13829 /* Ignore the low bit in the target, since it will be
13830 set for a text label. */
13831 if ((val
& 1) != 0)
13834 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13836 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13839 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13842 /* Make sure the section winds up with the alignment we have
13845 record_alignment (asec
, op
->shift
);
13849 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13850 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13851 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13852 _("extended instruction in delay slot"));
13854 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13856 if (target_big_endian
)
13857 insn
= bfd_getb16 (buf
);
13859 insn
= bfd_getl16 (buf
);
13861 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13862 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13863 small
, ext
, &insn
, &use_extend
, &extend
);
13867 md_number_to_chars (buf
, 0xf000 | extend
, 2);
13868 fragp
->fr_fix
+= 2;
13872 md_number_to_chars (buf
, insn
, 2);
13873 fragp
->fr_fix
+= 2;
13878 if (fragp
->fr_opcode
== NULL
)
13881 old
= RELAX_OLD (fragp
->fr_subtype
);
13882 new = RELAX_NEW (fragp
->fr_subtype
);
13883 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
13886 memmove (fixptr
- old
, fixptr
, new);
13888 fragp
->fr_fix
+= new - old
;
13894 /* This function is called after the relocs have been generated.
13895 We've been storing mips16 text labels as odd. Here we convert them
13896 back to even for the convenience of the debugger. */
13899 mips_frob_file_after_relocs (void)
13902 unsigned int count
, i
;
13904 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13907 syms
= bfd_get_outsymbols (stdoutput
);
13908 count
= bfd_get_symcount (stdoutput
);
13909 for (i
= 0; i
< count
; i
++, syms
++)
13911 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13912 && ((*syms
)->value
& 1) != 0)
13914 (*syms
)->value
&= ~1;
13915 /* If the symbol has an odd size, it was probably computed
13916 incorrectly, so adjust that as well. */
13917 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13918 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13925 /* This function is called whenever a label is defined. It is used
13926 when handling branch delays; if a branch has a label, we assume we
13927 can not move it. */
13930 mips_define_label (symbolS
*sym
)
13932 struct insn_label_list
*l
;
13934 if (free_insn_labels
== NULL
)
13935 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13938 l
= free_insn_labels
;
13939 free_insn_labels
= l
->next
;
13943 l
->next
= insn_labels
;
13947 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13949 /* Some special processing for a MIPS ELF file. */
13952 mips_elf_final_processing (void)
13954 /* Write out the register information. */
13955 if (mips_abi
!= N64_ABI
)
13959 s
.ri_gprmask
= mips_gprmask
;
13960 s
.ri_cprmask
[0] = mips_cprmask
[0];
13961 s
.ri_cprmask
[1] = mips_cprmask
[1];
13962 s
.ri_cprmask
[2] = mips_cprmask
[2];
13963 s
.ri_cprmask
[3] = mips_cprmask
[3];
13964 /* The gp_value field is set by the MIPS ELF backend. */
13966 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13967 ((Elf32_External_RegInfo
*)
13968 mips_regmask_frag
));
13972 Elf64_Internal_RegInfo s
;
13974 s
.ri_gprmask
= mips_gprmask
;
13976 s
.ri_cprmask
[0] = mips_cprmask
[0];
13977 s
.ri_cprmask
[1] = mips_cprmask
[1];
13978 s
.ri_cprmask
[2] = mips_cprmask
[2];
13979 s
.ri_cprmask
[3] = mips_cprmask
[3];
13980 /* The gp_value field is set by the MIPS ELF backend. */
13982 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13983 ((Elf64_External_RegInfo
*)
13984 mips_regmask_frag
));
13987 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13988 sort of BFD interface for this. */
13989 if (mips_any_noreorder
)
13990 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13991 if (mips_pic
!= NO_PIC
)
13993 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13994 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13997 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13999 /* Set MIPS ELF flags for ASEs. */
14000 if (file_ase_mips16
)
14001 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14002 #if 0 /* XXX FIXME */
14003 if (file_ase_mips3d
)
14004 elf_elfheader (stdoutput
)->e_flags
|= ???;
14007 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14009 /* Set the MIPS ELF ABI flags. */
14010 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14011 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14012 else if (mips_abi
== O64_ABI
)
14013 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14014 else if (mips_abi
== EABI_ABI
)
14016 if (!file_mips_gp32
)
14017 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14019 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14021 else if (mips_abi
== N32_ABI
)
14022 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14024 /* Nothing to do for N64_ABI. */
14026 if (mips_32bitmode
)
14027 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14030 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14032 typedef struct proc
{
14034 unsigned long reg_mask
;
14035 unsigned long reg_offset
;
14036 unsigned long fpreg_mask
;
14037 unsigned long fpreg_offset
;
14038 unsigned long frame_offset
;
14039 unsigned long frame_reg
;
14040 unsigned long pc_reg
;
14043 static procS cur_proc
;
14044 static procS
*cur_proc_ptr
;
14045 static int numprocs
;
14047 /* Fill in an rs_align_code fragment. */
14050 mips_handle_align (fragS
*fragp
)
14052 if (fragp
->fr_type
!= rs_align_code
)
14055 if (mips_opts
.mips16
)
14057 static const unsigned char be_nop
[] = { 0x65, 0x00 };
14058 static const unsigned char le_nop
[] = { 0x00, 0x65 };
14063 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14064 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14072 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
14076 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14080 md_obj_begin (void)
14087 /* check for premature end, nesting errors, etc */
14089 as_warn (_("missing .end at end of assembly"));
14098 if (*input_line_pointer
== '-')
14100 ++input_line_pointer
;
14103 if (!ISDIGIT (*input_line_pointer
))
14104 as_bad (_("expected simple number"));
14105 if (input_line_pointer
[0] == '0')
14107 if (input_line_pointer
[1] == 'x')
14109 input_line_pointer
+= 2;
14110 while (ISXDIGIT (*input_line_pointer
))
14113 val
|= hex_value (*input_line_pointer
++);
14115 return negative
? -val
: val
;
14119 ++input_line_pointer
;
14120 while (ISDIGIT (*input_line_pointer
))
14123 val
|= *input_line_pointer
++ - '0';
14125 return negative
? -val
: val
;
14128 if (!ISDIGIT (*input_line_pointer
))
14130 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14131 *input_line_pointer
, *input_line_pointer
);
14132 as_warn (_("invalid number"));
14135 while (ISDIGIT (*input_line_pointer
))
14138 val
+= *input_line_pointer
++ - '0';
14140 return negative
? -val
: val
;
14143 /* The .file directive; just like the usual .file directive, but there
14144 is an initial number which is the ECOFF file index. In the non-ECOFF
14145 case .file implies DWARF-2. */
14148 s_mips_file (int x ATTRIBUTE_UNUSED
)
14150 static int first_file_directive
= 0;
14152 if (ECOFF_DEBUGGING
)
14161 filename
= dwarf2_directive_file (0);
14163 /* Versions of GCC up to 3.1 start files with a ".file"
14164 directive even for stabs output. Make sure that this
14165 ".file" is handled. Note that you need a version of GCC
14166 after 3.1 in order to support DWARF-2 on MIPS. */
14167 if (filename
!= NULL
&& ! first_file_directive
)
14169 (void) new_logical_line (filename
, -1);
14170 s_app_file_string (filename
);
14172 first_file_directive
= 1;
14176 /* The .loc directive, implying DWARF-2. */
14179 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14181 if (!ECOFF_DEBUGGING
)
14182 dwarf2_directive_loc (0);
14185 /* The .end directive. */
14188 s_mips_end (int x ATTRIBUTE_UNUSED
)
14192 /* Following functions need their own .frame and .cprestore directives. */
14193 mips_frame_reg_valid
= 0;
14194 mips_cprestore_valid
= 0;
14196 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14199 demand_empty_rest_of_line ();
14204 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14205 as_warn (_(".end not in text section"));
14209 as_warn (_(".end directive without a preceding .ent directive."));
14210 demand_empty_rest_of_line ();
14216 assert (S_GET_NAME (p
));
14217 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
14218 as_warn (_(".end symbol does not match .ent symbol."));
14220 if (debug_type
== DEBUG_STABS
)
14221 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14225 as_warn (_(".end directive missing or unknown symbol"));
14228 /* Generate a .pdr section. */
14229 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
14232 segT saved_seg
= now_seg
;
14233 subsegT saved_subseg
= now_subseg
;
14238 dot
= frag_now_fix ();
14240 #ifdef md_flush_pending_output
14241 md_flush_pending_output ();
14245 subseg_set (pdr_seg
, 0);
14247 /* Write the symbol. */
14248 exp
.X_op
= O_symbol
;
14249 exp
.X_add_symbol
= p
;
14250 exp
.X_add_number
= 0;
14251 emit_expr (&exp
, 4);
14253 fragp
= frag_more (7 * 4);
14255 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14256 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14257 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14258 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14259 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14260 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14261 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14263 subseg_set (saved_seg
, saved_subseg
);
14265 #endif /* OBJ_ELF */
14267 cur_proc_ptr
= NULL
;
14270 /* The .aent and .ent directives. */
14273 s_mips_ent (int aent
)
14277 symbolP
= get_symbol ();
14278 if (*input_line_pointer
== ',')
14279 ++input_line_pointer
;
14280 SKIP_WHITESPACE ();
14281 if (ISDIGIT (*input_line_pointer
)
14282 || *input_line_pointer
== '-')
14285 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14286 as_warn (_(".ent or .aent not in text section."));
14288 if (!aent
&& cur_proc_ptr
)
14289 as_warn (_("missing .end"));
14293 /* This function needs its own .frame and .cprestore directives. */
14294 mips_frame_reg_valid
= 0;
14295 mips_cprestore_valid
= 0;
14297 cur_proc_ptr
= &cur_proc
;
14298 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14300 cur_proc_ptr
->isym
= symbolP
;
14302 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14306 if (debug_type
== DEBUG_STABS
)
14307 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14308 S_GET_NAME (symbolP
));
14311 demand_empty_rest_of_line ();
14314 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14315 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14316 s_mips_frame is used so that we can set the PDR information correctly.
14317 We can't use the ecoff routines because they make reference to the ecoff
14318 symbol table (in the mdebug section). */
14321 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14324 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14328 if (cur_proc_ptr
== (procS
*) NULL
)
14330 as_warn (_(".frame outside of .ent"));
14331 demand_empty_rest_of_line ();
14335 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14337 SKIP_WHITESPACE ();
14338 if (*input_line_pointer
++ != ','
14339 || get_absolute_expression_and_terminator (&val
) != ',')
14341 as_warn (_("Bad .frame directive"));
14342 --input_line_pointer
;
14343 demand_empty_rest_of_line ();
14347 cur_proc_ptr
->frame_offset
= val
;
14348 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14350 demand_empty_rest_of_line ();
14353 #endif /* OBJ_ELF */
14357 /* The .fmask and .mask directives. If the mdebug section is present
14358 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14359 embedded targets, s_mips_mask is used so that we can set the PDR
14360 information correctly. We can't use the ecoff routines because they
14361 make reference to the ecoff symbol table (in the mdebug section). */
14364 s_mips_mask (int reg_type
)
14367 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14371 if (cur_proc_ptr
== (procS
*) NULL
)
14373 as_warn (_(".mask/.fmask outside of .ent"));
14374 demand_empty_rest_of_line ();
14378 if (get_absolute_expression_and_terminator (&mask
) != ',')
14380 as_warn (_("Bad .mask/.fmask directive"));
14381 --input_line_pointer
;
14382 demand_empty_rest_of_line ();
14386 off
= get_absolute_expression ();
14388 if (reg_type
== 'F')
14390 cur_proc_ptr
->fpreg_mask
= mask
;
14391 cur_proc_ptr
->fpreg_offset
= off
;
14395 cur_proc_ptr
->reg_mask
= mask
;
14396 cur_proc_ptr
->reg_offset
= off
;
14399 demand_empty_rest_of_line ();
14402 #endif /* OBJ_ELF */
14403 s_ignore (reg_type
);
14406 /* The .loc directive. */
14416 assert (now_seg
== text_section
);
14418 lineno
= get_number ();
14419 addroff
= frag_now_fix ();
14421 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
14422 S_SET_TYPE (symbolP
, N_SLINE
);
14423 S_SET_OTHER (symbolP
, 0);
14424 S_SET_DESC (symbolP
, lineno
);
14425 symbolP
->sy_segment
= now_seg
;
14429 /* A table describing all the processors gas knows about. Names are
14430 matched in the order listed.
14432 To ease comparison, please keep this table in the same order as
14433 gcc's mips_cpu_info_table[]. */
14434 static const struct mips_cpu_info mips_cpu_info_table
[] =
14436 /* Entries for generic ISAs */
14437 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14438 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14439 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14440 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14441 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14442 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14443 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
14444 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14445 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
14448 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14449 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14450 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14453 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14456 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14457 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14458 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14459 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14460 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14461 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14462 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14463 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14464 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14465 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14466 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14467 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14470 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14471 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14472 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14473 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14474 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14475 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14476 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14477 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14478 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14479 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14480 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14481 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
14482 { "rm9000", 0, ISA_MIPS4
, CPU_RM7000
},
14485 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
14486 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14487 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14490 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14491 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14493 /* Broadcom SB-1 CPU core */
14494 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14501 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14502 with a final "000" replaced by "k". Ignore case.
14504 Note: this function is shared between GCC and GAS. */
14507 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
14509 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14510 given
++, canonical
++;
14512 return ((*given
== 0 && *canonical
== 0)
14513 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14517 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14518 CPU name. We've traditionally allowed a lot of variation here.
14520 Note: this function is shared between GCC and GAS. */
14523 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
14525 /* First see if the name matches exactly, or with a final "000"
14526 turned into "k". */
14527 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14530 /* If not, try comparing based on numerical designation alone.
14531 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14532 if (TOLOWER (*given
) == 'r')
14534 if (!ISDIGIT (*given
))
14537 /* Skip over some well-known prefixes in the canonical name,
14538 hoping to find a number there too. */
14539 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14541 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14543 else if (TOLOWER (canonical
[0]) == 'r')
14546 return mips_strict_matching_cpu_name_p (canonical
, given
);
14550 /* Parse an option that takes the name of a processor as its argument.
14551 OPTION is the name of the option and CPU_STRING is the argument.
14552 Return the corresponding processor enumeration if the CPU_STRING is
14553 recognized, otherwise report an error and return null.
14555 A similar function exists in GCC. */
14557 static const struct mips_cpu_info
*
14558 mips_parse_cpu (const char *option
, const char *cpu_string
)
14560 const struct mips_cpu_info
*p
;
14562 /* 'from-abi' selects the most compatible architecture for the given
14563 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14564 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14565 version. Look first at the -mgp options, if given, otherwise base
14566 the choice on MIPS_DEFAULT_64BIT.
14568 Treat NO_ABI like the EABIs. One reason to do this is that the
14569 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14570 architecture. This code picks MIPS I for 'mips' and MIPS III for
14571 'mips64', just as we did in the days before 'from-abi'. */
14572 if (strcasecmp (cpu_string
, "from-abi") == 0)
14574 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14575 return mips_cpu_info_from_isa (ISA_MIPS1
);
14577 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14578 return mips_cpu_info_from_isa (ISA_MIPS3
);
14580 if (file_mips_gp32
>= 0)
14581 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14583 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14588 /* 'default' has traditionally been a no-op. Probably not very useful. */
14589 if (strcasecmp (cpu_string
, "default") == 0)
14592 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14593 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14596 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14600 /* Return the canonical processor information for ISA (a member of the
14601 ISA_MIPS* enumeration). */
14603 static const struct mips_cpu_info
*
14604 mips_cpu_info_from_isa (int isa
)
14608 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14609 if (mips_cpu_info_table
[i
].is_isa
14610 && isa
== mips_cpu_info_table
[i
].isa
)
14611 return (&mips_cpu_info_table
[i
]);
14616 static const struct mips_cpu_info
*
14617 mips_cpu_info_from_arch (int arch
)
14621 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14622 if (arch
== mips_cpu_info_table
[i
].cpu
)
14623 return (&mips_cpu_info_table
[i
]);
14629 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14633 fprintf (stream
, "%24s", "");
14638 fprintf (stream
, ", ");
14642 if (*col_p
+ strlen (string
) > 72)
14644 fprintf (stream
, "\n%24s", "");
14648 fprintf (stream
, "%s", string
);
14649 *col_p
+= strlen (string
);
14655 md_show_usage (FILE *stream
)
14660 fprintf (stream
, _("\
14662 -membedded-pic generate embedded position independent code\n\
14663 -EB generate big endian output\n\
14664 -EL generate little endian output\n\
14665 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14666 -G NUM allow referencing objects up to NUM bytes\n\
14667 implicitly with the gp register [default 8]\n"));
14668 fprintf (stream
, _("\
14669 -mips1 generate MIPS ISA I instructions\n\
14670 -mips2 generate MIPS ISA II instructions\n\
14671 -mips3 generate MIPS ISA III instructions\n\
14672 -mips4 generate MIPS ISA IV instructions\n\
14673 -mips5 generate MIPS ISA V instructions\n\
14674 -mips32 generate MIPS32 ISA instructions\n\
14675 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14676 -mips64 generate MIPS64 ISA instructions\n\
14677 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14678 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14682 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14683 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14684 show (stream
, "from-abi", &column
, &first
);
14685 fputc ('\n', stream
);
14687 fprintf (stream
, _("\
14688 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14689 -no-mCPU don't generate code specific to CPU.\n\
14690 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14694 show (stream
, "3900", &column
, &first
);
14695 show (stream
, "4010", &column
, &first
);
14696 show (stream
, "4100", &column
, &first
);
14697 show (stream
, "4650", &column
, &first
);
14698 fputc ('\n', stream
);
14700 fprintf (stream
, _("\
14701 -mips16 generate mips16 instructions\n\
14702 -no-mips16 do not generate mips16 instructions\n"));
14703 fprintf (stream
, _("\
14704 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14705 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14706 -O0 remove unneeded NOPs, do not swap branches\n\
14707 -O remove unneeded NOPs and swap branches\n\
14708 -n warn about NOPs generated from macros\n\
14709 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14710 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14711 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14713 fprintf (stream
, _("\
14714 -KPIC, -call_shared generate SVR4 position independent code\n\
14715 -non_shared do not generate position independent code\n\
14716 -xgot assume a 32 bit GOT\n\
14717 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14718 -mabi=ABI create ABI conformant object file for:\n"));
14722 show (stream
, "32", &column
, &first
);
14723 show (stream
, "o64", &column
, &first
);
14724 show (stream
, "n32", &column
, &first
);
14725 show (stream
, "64", &column
, &first
);
14726 show (stream
, "eabi", &column
, &first
);
14728 fputc ('\n', stream
);
14730 fprintf (stream
, _("\
14731 -32 create o32 ABI object file (default)\n\
14732 -n32 create n32 ABI object file\n\
14733 -64 create 64 ABI object file\n"));
14738 mips_dwarf2_format (void)
14740 if (mips_abi
== N64_ABI
)
14743 return dwarf2_format_64bit_irix
;
14745 return dwarf2_format_64bit
;
14749 return dwarf2_format_32bit
;