1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* The ABI to use. */
133 /* MIPS ABI we are using for this output file. */
134 static enum mips_abi_level mips_abi
= NO_ABI
;
136 /* Whether or not we have code that can call pic code. */
137 int mips_abicalls
= FALSE
;
139 /* Whether or not we have code which can be put into a shared
141 static bfd_boolean mips_in_shared
= TRUE
;
143 /* This is the set of options which may be modified by the .set
144 pseudo-op. We use a struct so that .set push and .set pop are more
147 struct mips_set_options
149 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
150 if it has not been initialized. Changed by `.set mipsN', and the
151 -mipsN command line option, and the default CPU. */
153 /* Enabled Application Specific Extensions (ASEs). These are set to -1
154 if they have not been initialized. Changed by `.set <asename>', by
155 command line options, and based on the default architecture. */
158 /* Whether we are assembling for the mips16 processor. 0 if we are
159 not, 1 if we are, and -1 if the value has not been initialized.
160 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
161 -nomips16 command line options, and the default CPU. */
163 /* Non-zero if we should not reorder instructions. Changed by `.set
164 reorder' and `.set noreorder'. */
166 /* Non-zero if we should not permit the $at ($1) register to be used
167 in instructions. Changed by `.set at' and `.set noat'. */
169 /* Non-zero if we should warn when a macro instruction expands into
170 more than one machine instruction. Changed by `.set nomacro' and
172 int warn_about_macros
;
173 /* Non-zero if we should not move instructions. Changed by `.set
174 move', `.set volatile', `.set nomove', and `.set novolatile'. */
176 /* Non-zero if we should not optimize branches by moving the target
177 of the branch into the delay slot. Actually, we don't perform
178 this optimization anyhow. Changed by `.set bopt' and `.set
181 /* Non-zero if we should not autoextend mips16 instructions.
182 Changed by `.set autoextend' and `.set noautoextend'. */
184 /* Restrict general purpose registers and floating point registers
185 to 32 bit. This is initially determined when -mgp32 or -mfp32
186 is passed but can changed if the assembler code uses .set mipsN. */
189 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
190 command line option, and the default CPU. */
194 /* True if -mgp32 was passed. */
195 static int file_mips_gp32
= -1;
197 /* True if -mfp32 was passed. */
198 static int file_mips_fp32
= -1;
200 /* This is the struct we use to hold the current set of options. Note
201 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
202 -1 to indicate that they have not been initialized. */
204 static struct mips_set_options mips_opts
=
206 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
209 /* These variables are filled in with the masks of registers used.
210 The object format code reads them and puts them in the appropriate
212 unsigned long mips_gprmask
;
213 unsigned long mips_cprmask
[4];
215 /* MIPS ISA we are using for this output file. */
216 static int file_mips_isa
= ISA_UNKNOWN
;
218 /* True if -mips16 was passed or implied by arguments passed on the
219 command line (e.g., by -march). */
220 static int file_ase_mips16
;
222 /* True if -mips3d was passed or implied by arguments passed on the
223 command line (e.g., by -march). */
224 static int file_ase_mips3d
;
226 /* True if -mdmx was passed or implied by arguments passed on the
227 command line (e.g., by -march). */
228 static int file_ase_mdmx
;
230 /* The argument of the -march= flag. The architecture we are assembling. */
231 static int file_mips_arch
= CPU_UNKNOWN
;
232 static const char *mips_arch_string
;
234 /* The argument of the -mtune= flag. The architecture for which we
236 static int mips_tune
= CPU_UNKNOWN
;
237 static const char *mips_tune_string
;
239 /* True when generating 32-bit code for a 64-bit processor. */
240 static int mips_32bitmode
= 0;
242 /* True if the given ABI requires 32-bit registers. */
243 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
245 /* Likewise 64-bit registers. */
246 #define ABI_NEEDS_64BIT_REGS(ABI) \
248 || (ABI) == N64_ABI \
251 /* Return true if ISA supports 64 bit gp register instructions. */
252 #define ISA_HAS_64BIT_REGS(ISA) ( \
254 || (ISA) == ISA_MIPS4 \
255 || (ISA) == ISA_MIPS5 \
256 || (ISA) == ISA_MIPS64 \
257 || (ISA) == ISA_MIPS64R2 \
260 /* Return true if ISA supports 64-bit right rotate (dror et al.)
262 #define ISA_HAS_DROR(ISA) ( \
263 (ISA) == ISA_MIPS64R2 \
266 /* Return true if ISA supports 32-bit right rotate (ror et al.)
268 #define ISA_HAS_ROR(ISA) ( \
269 (ISA) == ISA_MIPS32R2 \
270 || (ISA) == ISA_MIPS64R2 \
273 #define HAVE_32BIT_GPRS \
274 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
276 #define HAVE_32BIT_FPRS \
277 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
279 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
280 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
282 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
284 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
286 /* True if relocations are stored in-place. */
287 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
289 /* We can only have 64bit addresses if the object file format supports it. */
290 #define HAVE_32BIT_ADDRESSES \
292 || (bfd_arch_bits_per_address (stdoutput) == 32 \
293 || ! HAVE_64BIT_OBJECTS)) \
295 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
297 /* Addresses are loaded in different ways, depending on the address size
298 in use. The n32 ABI Documentation also mandates the use of additions
299 with overflow checking, but existing implementations don't follow it. */
300 #define ADDRESS_ADD_INSN \
301 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
303 #define ADDRESS_ADDI_INSN \
304 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
306 #define ADDRESS_LOAD_INSN \
307 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
309 #define ADDRESS_STORE_INSN \
310 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
312 /* Return true if the given CPU supports the MIPS16 ASE. */
313 #define CPU_HAS_MIPS16(cpu) \
314 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
315 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
317 /* Return true if the given CPU supports the MIPS3D ASE. */
318 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
321 /* Return true if the given CPU supports the MDMX ASE. */
322 #define CPU_HAS_MDMX(cpu) (FALSE \
325 /* True if CPU has a dror instruction. */
326 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
328 /* True if CPU has a ror instruction. */
329 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
331 /* True if mflo and mfhi can be immediately followed by instructions
332 which write to the HI and LO registers.
334 According to MIPS specifications, MIPS ISAs I, II, and III need
335 (at least) two instructions between the reads of HI/LO and
336 instructions which write them, and later ISAs do not. Contradicting
337 the MIPS specifications, some MIPS IV processor user manuals (e.g.
338 the UM for the NEC Vr5000) document needing the instructions between
339 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
340 MIPS64 and later ISAs to have the interlocks, plus any specific
341 earlier-ISA CPUs for which CPU documentation declares that the
342 instructions are really interlocked. */
343 #define hilo_interlocks \
344 (mips_opts.isa == ISA_MIPS32 \
345 || mips_opts.isa == ISA_MIPS32R2 \
346 || mips_opts.isa == ISA_MIPS64 \
347 || mips_opts.isa == ISA_MIPS64R2 \
348 || mips_opts.arch == CPU_R4010 \
349 || mips_opts.arch == CPU_R10000 \
350 || mips_opts.arch == CPU_R12000 \
351 || mips_opts.arch == CPU_RM7000 \
352 || mips_opts.arch == CPU_VR5500 \
355 /* Whether the processor uses hardware interlocks to protect reads
356 from the GPRs after they are loaded from memory, and thus does not
357 require nops to be inserted. This applies to instructions marked
358 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
360 #define gpr_interlocks \
361 (mips_opts.isa != ISA_MIPS1 \
362 || mips_opts.arch == CPU_R3900)
364 /* Whether the processor uses hardware interlocks to avoid delays
365 required by coprocessor instructions, and thus does not require
366 nops to be inserted. This applies to instructions marked
367 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
368 between instructions marked INSN_WRITE_COND_CODE and ones marked
369 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
370 levels I, II, and III. */
371 /* Itbl support may require additional care here. */
372 #define cop_interlocks \
373 ((mips_opts.isa != ISA_MIPS1 \
374 && mips_opts.isa != ISA_MIPS2 \
375 && mips_opts.isa != ISA_MIPS3) \
376 || mips_opts.arch == CPU_R4300 \
379 /* Whether the processor uses hardware interlocks to protect reads
380 from coprocessor registers after they are loaded from memory, and
381 thus does not require nops to be inserted. This applies to
382 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
383 requires at MIPS ISA level I. */
384 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
386 /* Is this a mfhi or mflo instruction? */
387 #define MF_HILO_INSN(PINFO) \
388 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
390 /* MIPS PIC level. */
392 enum mips_pic_level mips_pic
;
394 /* 1 if we should generate 32 bit offsets from the $gp register in
395 SVR4_PIC mode. Currently has no meaning in other modes. */
396 static int mips_big_got
= 0;
398 /* 1 if trap instructions should used for overflow rather than break
400 static int mips_trap
= 0;
402 /* 1 if double width floating point constants should not be constructed
403 by assembling two single width halves into two single width floating
404 point registers which just happen to alias the double width destination
405 register. On some architectures this aliasing can be disabled by a bit
406 in the status register, and the setting of this bit cannot be determined
407 automatically at assemble time. */
408 static int mips_disable_float_construction
;
410 /* Non-zero if any .set noreorder directives were used. */
412 static int mips_any_noreorder
;
414 /* Non-zero if nops should be inserted when the register referenced in
415 an mfhi/mflo instruction is read in the next two instructions. */
416 static int mips_7000_hilo_fix
;
418 /* The size of the small data section. */
419 static unsigned int g_switch_value
= 8;
420 /* Whether the -G option was used. */
421 static int g_switch_seen
= 0;
426 /* If we can determine in advance that GP optimization won't be
427 possible, we can skip the relaxation stuff that tries to produce
428 GP-relative references. This makes delay slot optimization work
431 This function can only provide a guess, but it seems to work for
432 gcc output. It needs to guess right for gcc, otherwise gcc
433 will put what it thinks is a GP-relative instruction in a branch
436 I don't know if a fix is needed for the SVR4_PIC mode. I've only
437 fixed it for the non-PIC mode. KR 95/04/07 */
438 static int nopic_need_relax (symbolS
*, int);
440 /* handle of the OPCODE hash table */
441 static struct hash_control
*op_hash
= NULL
;
443 /* The opcode hash table we use for the mips16. */
444 static struct hash_control
*mips16_op_hash
= NULL
;
446 /* This array holds the chars that always start a comment. If the
447 pre-processor is disabled, these aren't very useful */
448 const char comment_chars
[] = "#";
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output */
453 /* Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output. */
456 /* Also note that C style comments are always supported. */
457 const char line_comment_chars
[] = "#";
459 /* This array holds machine specific line separator characters. */
460 const char line_separator_chars
[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point nums */
463 const char EXP_CHARS
[] = "eE";
465 /* Chars that mean this number is a floating point constant */
468 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
470 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
471 changed in read.c . Ideally it shouldn't have to know about it at all,
472 but nothing is ideal around here.
475 static char *insn_error
;
477 static int auto_align
= 1;
479 /* When outputting SVR4 PIC code, the assembler needs to know the
480 offset in the stack frame from which to restore the $gp register.
481 This is set by the .cprestore pseudo-op, and saved in this
483 static offsetT mips_cprestore_offset
= -1;
485 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
486 more optimizations, it can use a register value instead of a memory-saved
487 offset and even an other register than $gp as global pointer. */
488 static offsetT mips_cpreturn_offset
= -1;
489 static int mips_cpreturn_register
= -1;
490 static int mips_gp_register
= GP
;
491 static int mips_gprel_offset
= 0;
493 /* Whether mips_cprestore_offset has been set in the current function
494 (or whether it has already been warned about, if not). */
495 static int mips_cprestore_valid
= 0;
497 /* This is the register which holds the stack frame, as set by the
498 .frame pseudo-op. This is needed to implement .cprestore. */
499 static int mips_frame_reg
= SP
;
501 /* Whether mips_frame_reg has been set in the current function
502 (or whether it has already been warned about, if not). */
503 static int mips_frame_reg_valid
= 0;
505 /* To output NOP instructions correctly, we need to keep information
506 about the previous two instructions. */
508 /* Whether we are optimizing. The default value of 2 means to remove
509 unneeded NOPs and swap branch instructions when possible. A value
510 of 1 means to not swap branches. A value of 0 means to always
512 static int mips_optimize
= 2;
514 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
515 equivalent to seeing no -g option at all. */
516 static int mips_debug
= 0;
518 /* The previous instruction. */
519 static struct mips_cl_insn prev_insn
;
521 /* The instruction before prev_insn. */
522 static struct mips_cl_insn prev_prev_insn
;
524 /* If we don't want information for prev_insn or prev_prev_insn, we
525 point the insn_mo field at this dummy integer. */
526 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0, 0 };
528 /* Non-zero if prev_insn is valid. */
529 static int prev_insn_valid
;
531 /* The frag for the previous instruction. */
532 static struct frag
*prev_insn_frag
;
534 /* The offset into prev_insn_frag for the previous instruction. */
535 static long prev_insn_where
;
537 /* The reloc type for the previous instruction, if any. */
538 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
540 /* The reloc for the previous instruction, if any. */
541 static fixS
*prev_insn_fixp
[3];
543 /* Non-zero if the previous instruction was in a delay slot. */
544 static int prev_insn_is_delay_slot
;
546 /* Non-zero if the previous instruction was in a .set noreorder. */
547 static int prev_insn_unreordered
;
549 /* Non-zero if the previous instruction uses an extend opcode (if
551 static int prev_insn_extended
;
553 /* Non-zero if the previous previous instruction was in a .set
555 static int prev_prev_insn_unreordered
;
557 /* If this is set, it points to a frag holding nop instructions which
558 were inserted before the start of a noreorder section. If those
559 nops turn out to be unnecessary, the size of the frag can be
561 static fragS
*prev_nop_frag
;
563 /* The number of nop instructions we created in prev_nop_frag. */
564 static int prev_nop_frag_holds
;
566 /* The number of nop instructions that we know we need in
568 static int prev_nop_frag_required
;
570 /* The number of instructions we've seen since prev_nop_frag. */
571 static int prev_nop_frag_since
;
573 /* For ECOFF and ELF, relocations against symbols are done in two
574 parts, with a HI relocation and a LO relocation. Each relocation
575 has only 16 bits of space to store an addend. This means that in
576 order for the linker to handle carries correctly, it must be able
577 to locate both the HI and the LO relocation. This means that the
578 relocations must appear in order in the relocation table.
580 In order to implement this, we keep track of each unmatched HI
581 relocation. We then sort them so that they immediately precede the
582 corresponding LO relocation. */
587 struct mips_hi_fixup
*next
;
590 /* The section this fixup is in. */
594 /* The list of unmatched HI relocs. */
596 static struct mips_hi_fixup
*mips_hi_fixup_list
;
598 /* The frag containing the last explicit relocation operator.
599 Null if explicit relocations have not been used. */
601 static fragS
*prev_reloc_op_frag
;
603 /* Map normal MIPS register numbers to mips16 register numbers. */
605 #define X ILLEGAL_REG
606 static const int mips32_to_16_reg_map
[] =
608 X
, X
, 2, 3, 4, 5, 6, 7,
609 X
, X
, X
, X
, X
, X
, X
, X
,
610 0, 1, X
, X
, X
, X
, X
, X
,
611 X
, X
, X
, X
, X
, X
, X
, X
615 /* Map mips16 register numbers to normal MIPS register numbers. */
617 static const unsigned int mips16_to_32_reg_map
[] =
619 16, 17, 2, 3, 4, 5, 6, 7
622 static int mips_fix_vr4120
;
624 /* We don't relax branches by default, since this causes us to expand
625 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
626 fail to compute the offset before expanding the macro to the most
627 efficient expansion. */
629 static int mips_relax_branch
;
631 /* The expansion of many macros depends on the type of symbol that
632 they refer to. For example, when generating position-dependent code,
633 a macro that refers to a symbol may have two different expansions,
634 one which uses GP-relative addresses and one which uses absolute
635 addresses. When generating SVR4-style PIC, a macro may have
636 different expansions for local and global symbols.
638 We handle these situations by generating both sequences and putting
639 them in variant frags. In position-dependent code, the first sequence
640 will be the GP-relative one and the second sequence will be the
641 absolute one. In SVR4 PIC, the first sequence will be for global
642 symbols and the second will be for local symbols.
644 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
645 SECOND are the lengths of the two sequences in bytes. These fields
646 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
647 the subtype has the following flags:
650 Set if it has been decided that we should use the second
651 sequence instead of the first.
654 Set in the first variant frag if the macro's second implementation
655 is longer than its first. This refers to the macro as a whole,
656 not an individual relaxation.
659 Set in the first variant frag if the macro appeared in a .set nomacro
660 block and if one alternative requires a warning but the other does not.
663 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
666 The frag's "opcode" points to the first fixup for relaxable code.
668 Relaxable macros are generated using a sequence such as:
670 relax_start (SYMBOL);
671 ... generate first expansion ...
673 ... generate second expansion ...
676 The code and fixups for the unwanted alternative are discarded
677 by md_convert_frag. */
678 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
680 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
681 #define RELAX_SECOND(X) ((X) & 0xff)
682 #define RELAX_USE_SECOND 0x10000
683 #define RELAX_SECOND_LONGER 0x20000
684 #define RELAX_NOMACRO 0x40000
685 #define RELAX_DELAY_SLOT 0x80000
687 /* Branch without likely bit. If label is out of range, we turn:
689 beq reg1, reg2, label
699 with the following opcode replacements:
706 bltzal <-> bgezal (with jal label instead of j label)
708 Even though keeping the delay slot instruction in the delay slot of
709 the branch would be more efficient, it would be very tricky to do
710 correctly, because we'd have to introduce a variable frag *after*
711 the delay slot instruction, and expand that instead. Let's do it
712 the easy way for now, even if the branch-not-taken case now costs
713 one additional instruction. Out-of-range branches are not supposed
714 to be common, anyway.
716 Branch likely. If label is out of range, we turn:
718 beql reg1, reg2, label
719 delay slot (annulled if branch not taken)
728 delay slot (executed only if branch taken)
731 It would be possible to generate a shorter sequence by losing the
732 likely bit, generating something like:
737 delay slot (executed only if branch taken)
749 bltzall -> bgezal (with jal label instead of j label)
750 bgezall -> bltzal (ditto)
753 but it's not clear that it would actually improve performance. */
754 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
757 | ((toofar) ? 1 : 0) \
759 | ((likely) ? 4 : 0) \
760 | ((uncond) ? 8 : 0)))
761 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
762 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
763 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
764 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
765 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
767 /* For mips16 code, we use an entirely different form of relaxation.
768 mips16 supports two versions of most instructions which take
769 immediate values: a small one which takes some small value, and a
770 larger one which takes a 16 bit value. Since branches also follow
771 this pattern, relaxing these values is required.
773 We can assemble both mips16 and normal MIPS code in a single
774 object. Therefore, we need to support this type of relaxation at
775 the same time that we support the relaxation described above. We
776 use the high bit of the subtype field to distinguish these cases.
778 The information we store for this type of relaxation is the
779 argument code found in the opcode file for this relocation, whether
780 the user explicitly requested a small or extended form, and whether
781 the relocation is in a jump or jal delay slot. That tells us the
782 size of the value, and how it should be stored. We also store
783 whether the fragment is considered to be extended or not. We also
784 store whether this is known to be a branch to a different section,
785 whether we have tried to relax this frag yet, and whether we have
786 ever extended a PC relative fragment because of a shift count. */
787 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
790 | ((small) ? 0x100 : 0) \
791 | ((ext) ? 0x200 : 0) \
792 | ((dslot) ? 0x400 : 0) \
793 | ((jal_dslot) ? 0x800 : 0))
794 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
795 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
796 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
797 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
798 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
799 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
800 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
801 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
802 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
803 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
804 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
805 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
807 /* Is the given value a sign-extended 32-bit value? */
808 #define IS_SEXT_32BIT_NUM(x) \
809 (((x) &~ (offsetT) 0x7fffffff) == 0 \
810 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
812 /* Is the given value a sign-extended 16-bit value? */
813 #define IS_SEXT_16BIT_NUM(x) \
814 (((x) &~ (offsetT) 0x7fff) == 0 \
815 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
818 /* Global variables used when generating relaxable macros. See the
819 comment above RELAX_ENCODE for more details about how relaxation
822 /* 0 if we're not emitting a relaxable macro.
823 1 if we're emitting the first of the two relaxation alternatives.
824 2 if we're emitting the second alternative. */
827 /* The first relaxable fixup in the current frag. (In other words,
828 the first fixup that refers to relaxable code.) */
831 /* sizes[0] says how many bytes of the first alternative are stored in
832 the current frag. Likewise sizes[1] for the second alternative. */
833 unsigned int sizes
[2];
835 /* The symbol on which the choice of sequence depends. */
839 /* Global variables used to decide whether a macro needs a warning. */
841 /* True if the macro is in a branch delay slot. */
842 bfd_boolean delay_slot_p
;
844 /* For relaxable macros, sizes[0] is the length of the first alternative
845 in bytes and sizes[1] is the length of the second alternative.
846 For non-relaxable macros, both elements give the length of the
848 unsigned int sizes
[2];
850 /* The first variant frag for this macro. */
852 } mips_macro_warning
;
854 /* Prototypes for static functions. */
856 #define internalError() \
857 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
859 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
861 static void append_insn
862 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
863 static void mips_no_prev_insn (int);
864 static void mips16_macro_build
865 (expressionS
*, const char *, const char *, va_list);
866 static void load_register (int, expressionS
*, int);
867 static void macro_start (void);
868 static void macro_end (void);
869 static void macro (struct mips_cl_insn
* ip
);
870 static void mips16_macro (struct mips_cl_insn
* ip
);
871 #ifdef LOSING_COMPILER
872 static void macro2 (struct mips_cl_insn
* ip
);
874 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
875 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
876 static void mips16_immed
877 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
878 unsigned long *, bfd_boolean
*, unsigned short *);
879 static size_t my_getSmallExpression
880 (expressionS
*, bfd_reloc_code_real_type
*, char *);
881 static void my_getExpression (expressionS
*, char *);
882 static void s_align (int);
883 static void s_change_sec (int);
884 static void s_change_section (int);
885 static void s_cons (int);
886 static void s_float_cons (int);
887 static void s_mips_globl (int);
888 static void s_option (int);
889 static void s_mipsset (int);
890 static void s_abicalls (int);
891 static void s_cpload (int);
892 static void s_cpsetup (int);
893 static void s_cplocal (int);
894 static void s_cprestore (int);
895 static void s_cpreturn (int);
896 static void s_gpvalue (int);
897 static void s_gpword (int);
898 static void s_gpdword (int);
899 static void s_cpadd (int);
900 static void s_insn (int);
901 static void md_obj_begin (void);
902 static void md_obj_end (void);
903 static void s_mips_ent (int);
904 static void s_mips_end (int);
905 static void s_mips_frame (int);
906 static void s_mips_mask (int reg_type
);
907 static void s_mips_stab (int);
908 static void s_mips_weakext (int);
909 static void s_mips_file (int);
910 static void s_mips_loc (int);
911 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
912 static int relaxed_branch_length (fragS
*, asection
*, int);
913 static int validate_mips_insn (const struct mips_opcode
*);
915 /* Table and functions used to map between CPU/ISA names, and
916 ISA levels, and CPU numbers. */
920 const char *name
; /* CPU or ISA name. */
921 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
922 int isa
; /* ISA level. */
923 int cpu
; /* CPU number (default CPU if ISA). */
926 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
927 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
928 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
932 The following pseudo-ops from the Kane and Heinrich MIPS book
933 should be defined here, but are currently unsupported: .alias,
934 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
936 The following pseudo-ops from the Kane and Heinrich MIPS book are
937 specific to the type of debugging information being generated, and
938 should be defined by the object format: .aent, .begin, .bend,
939 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
942 The following pseudo-ops from the Kane and Heinrich MIPS book are
943 not MIPS CPU specific, but are also not specific to the object file
944 format. This file is probably the best place to define them, but
945 they are not currently supported: .asm0, .endr, .lab, .repeat,
948 static const pseudo_typeS mips_pseudo_table
[] =
950 /* MIPS specific pseudo-ops. */
951 {"option", s_option
, 0},
952 {"set", s_mipsset
, 0},
953 {"rdata", s_change_sec
, 'r'},
954 {"sdata", s_change_sec
, 's'},
955 {"livereg", s_ignore
, 0},
956 {"abicalls", s_abicalls
, 0},
957 {"cpload", s_cpload
, 0},
958 {"cpsetup", s_cpsetup
, 0},
959 {"cplocal", s_cplocal
, 0},
960 {"cprestore", s_cprestore
, 0},
961 {"cpreturn", s_cpreturn
, 0},
962 {"gpvalue", s_gpvalue
, 0},
963 {"gpword", s_gpword
, 0},
964 {"gpdword", s_gpdword
, 0},
965 {"cpadd", s_cpadd
, 0},
968 /* Relatively generic pseudo-ops that happen to be used on MIPS
970 {"asciiz", stringer
, 1},
971 {"bss", s_change_sec
, 'b'},
974 {"dword", s_cons
, 3},
975 {"weakext", s_mips_weakext
, 0},
977 /* These pseudo-ops are defined in read.c, but must be overridden
978 here for one reason or another. */
979 {"align", s_align
, 0},
981 {"data", s_change_sec
, 'd'},
982 {"double", s_float_cons
, 'd'},
983 {"float", s_float_cons
, 'f'},
984 {"globl", s_mips_globl
, 0},
985 {"global", s_mips_globl
, 0},
986 {"hword", s_cons
, 1},
991 {"section", s_change_section
, 0},
992 {"short", s_cons
, 1},
993 {"single", s_float_cons
, 'f'},
994 {"stabn", s_mips_stab
, 'n'},
995 {"text", s_change_sec
, 't'},
998 { "extern", ecoff_directive_extern
, 0},
1003 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1005 /* These pseudo-ops should be defined by the object file format.
1006 However, a.out doesn't support them, so we have versions here. */
1007 {"aent", s_mips_ent
, 1},
1008 {"bgnb", s_ignore
, 0},
1009 {"end", s_mips_end
, 0},
1010 {"endb", s_ignore
, 0},
1011 {"ent", s_mips_ent
, 0},
1012 {"file", s_mips_file
, 0},
1013 {"fmask", s_mips_mask
, 'F'},
1014 {"frame", s_mips_frame
, 0},
1015 {"loc", s_mips_loc
, 0},
1016 {"mask", s_mips_mask
, 'R'},
1017 {"verstamp", s_ignore
, 0},
1021 extern void pop_insert (const pseudo_typeS
*);
1024 mips_pop_insert (void)
1026 pop_insert (mips_pseudo_table
);
1027 if (! ECOFF_DEBUGGING
)
1028 pop_insert (mips_nonecoff_pseudo_table
);
1031 /* Symbols labelling the current insn. */
1033 struct insn_label_list
1035 struct insn_label_list
*next
;
1039 static struct insn_label_list
*insn_labels
;
1040 static struct insn_label_list
*free_insn_labels
;
1042 static void mips_clear_insn_labels (void);
1045 mips_clear_insn_labels (void)
1047 register struct insn_label_list
**pl
;
1049 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1055 static char *expr_end
;
1057 /* Expressions which appear in instructions. These are set by
1060 static expressionS imm_expr
;
1061 static expressionS imm2_expr
;
1062 static expressionS offset_expr
;
1064 /* Relocs associated with imm_expr and offset_expr. */
1066 static bfd_reloc_code_real_type imm_reloc
[3]
1067 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1068 static bfd_reloc_code_real_type offset_reloc
[3]
1069 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1071 /* These are set by mips16_ip if an explicit extension is used. */
1073 static bfd_boolean mips16_small
, mips16_ext
;
1076 /* The pdr segment for per procedure frame/regmask info. Not used for
1079 static segT pdr_seg
;
1082 /* The default target format to use. */
1085 mips_target_format (void)
1087 switch (OUTPUT_FLAVOR
)
1089 case bfd_target_ecoff_flavour
:
1090 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1091 case bfd_target_coff_flavour
:
1093 case bfd_target_elf_flavour
:
1095 /* This is traditional mips. */
1096 return (target_big_endian
1097 ? (HAVE_64BIT_OBJECTS
1098 ? "elf64-tradbigmips"
1100 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1101 : (HAVE_64BIT_OBJECTS
1102 ? "elf64-tradlittlemips"
1104 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1106 return (target_big_endian
1107 ? (HAVE_64BIT_OBJECTS
1110 ? "elf32-nbigmips" : "elf32-bigmips"))
1111 : (HAVE_64BIT_OBJECTS
1112 ? "elf64-littlemips"
1114 ? "elf32-nlittlemips" : "elf32-littlemips")));
1122 /* This function is called once, at assembler startup time. It should
1123 set up all the tables, etc. that the MD part of the assembler will need. */
1128 register const char *retval
= NULL
;
1132 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1133 as_warn (_("Could not set architecture and machine"));
1135 op_hash
= hash_new ();
1137 for (i
= 0; i
< NUMOPCODES
;)
1139 const char *name
= mips_opcodes
[i
].name
;
1141 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1144 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1145 mips_opcodes
[i
].name
, retval
);
1146 /* Probably a memory allocation problem? Give up now. */
1147 as_fatal (_("Broken assembler. No assembly attempted."));
1151 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1153 if (!validate_mips_insn (&mips_opcodes
[i
]))
1158 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1161 mips16_op_hash
= hash_new ();
1164 while (i
< bfd_mips16_num_opcodes
)
1166 const char *name
= mips16_opcodes
[i
].name
;
1168 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1170 as_fatal (_("internal: can't hash `%s': %s"),
1171 mips16_opcodes
[i
].name
, retval
);
1174 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1175 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1176 != mips16_opcodes
[i
].match
))
1178 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1179 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1184 while (i
< bfd_mips16_num_opcodes
1185 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1189 as_fatal (_("Broken assembler. No assembly attempted."));
1191 /* We add all the general register names to the symbol table. This
1192 helps us detect invalid uses of them. */
1193 for (i
= 0; i
< 32; i
++)
1197 sprintf (buf
, "$%d", i
);
1198 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1199 &zero_address_frag
));
1201 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1202 &zero_address_frag
));
1203 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1204 &zero_address_frag
));
1205 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1206 &zero_address_frag
));
1207 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1208 &zero_address_frag
));
1209 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1210 &zero_address_frag
));
1211 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1212 &zero_address_frag
));
1213 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1214 &zero_address_frag
));
1215 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1216 &zero_address_frag
));
1217 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1218 &zero_address_frag
));
1220 /* If we don't add these register names to the symbol table, they
1221 may end up being added as regular symbols by operand(), and then
1222 make it to the object file as undefined in case they're not
1223 regarded as local symbols. They're local in o32, since `$' is a
1224 local symbol prefix, but not in n32 or n64. */
1225 for (i
= 0; i
< 8; i
++)
1229 sprintf (buf
, "$fcc%i", i
);
1230 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1231 &zero_address_frag
));
1234 mips_no_prev_insn (FALSE
);
1237 mips_cprmask
[0] = 0;
1238 mips_cprmask
[1] = 0;
1239 mips_cprmask
[2] = 0;
1240 mips_cprmask
[3] = 0;
1242 /* set the default alignment for the text section (2**2) */
1243 record_alignment (text_section
, 2);
1245 bfd_set_gp_size (stdoutput
, g_switch_value
);
1247 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1249 /* On a native system, sections must be aligned to 16 byte
1250 boundaries. When configured for an embedded ELF target, we
1252 if (strcmp (TARGET_OS
, "elf") != 0)
1254 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1255 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1256 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1259 /* Create a .reginfo section for register masks and a .mdebug
1260 section for debugging information. */
1268 subseg
= now_subseg
;
1270 /* The ABI says this section should be loaded so that the
1271 running program can access it. However, we don't load it
1272 if we are configured for an embedded target */
1273 flags
= SEC_READONLY
| SEC_DATA
;
1274 if (strcmp (TARGET_OS
, "elf") != 0)
1275 flags
|= SEC_ALLOC
| SEC_LOAD
;
1277 if (mips_abi
!= N64_ABI
)
1279 sec
= subseg_new (".reginfo", (subsegT
) 0);
1281 bfd_set_section_flags (stdoutput
, sec
, flags
);
1282 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1285 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1290 /* The 64-bit ABI uses a .MIPS.options section rather than
1291 .reginfo section. */
1292 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1293 bfd_set_section_flags (stdoutput
, sec
, flags
);
1294 bfd_set_section_alignment (stdoutput
, sec
, 3);
1297 /* Set up the option header. */
1299 Elf_Internal_Options opthdr
;
1302 opthdr
.kind
= ODK_REGINFO
;
1303 opthdr
.size
= (sizeof (Elf_External_Options
)
1304 + sizeof (Elf64_External_RegInfo
));
1307 f
= frag_more (sizeof (Elf_External_Options
));
1308 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1309 (Elf_External_Options
*) f
);
1311 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1316 if (ECOFF_DEBUGGING
)
1318 sec
= subseg_new (".mdebug", (subsegT
) 0);
1319 (void) bfd_set_section_flags (stdoutput
, sec
,
1320 SEC_HAS_CONTENTS
| SEC_READONLY
);
1321 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1324 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1326 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1327 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1328 SEC_READONLY
| SEC_RELOC
1330 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1334 subseg_set (seg
, subseg
);
1338 if (! ECOFF_DEBUGGING
)
1345 if (! ECOFF_DEBUGGING
)
1350 md_assemble (char *str
)
1352 struct mips_cl_insn insn
;
1353 bfd_reloc_code_real_type unused_reloc
[3]
1354 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1356 imm_expr
.X_op
= O_absent
;
1357 imm2_expr
.X_op
= O_absent
;
1358 offset_expr
.X_op
= O_absent
;
1359 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1360 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1361 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1362 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1363 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1364 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1366 if (mips_opts
.mips16
)
1367 mips16_ip (str
, &insn
);
1370 mips_ip (str
, &insn
);
1371 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1372 str
, insn
.insn_opcode
));
1377 as_bad ("%s `%s'", insn_error
, str
);
1381 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1384 if (mips_opts
.mips16
)
1385 mips16_macro (&insn
);
1392 if (imm_expr
.X_op
!= O_absent
)
1393 append_insn (&insn
, &imm_expr
, imm_reloc
);
1394 else if (offset_expr
.X_op
!= O_absent
)
1395 append_insn (&insn
, &offset_expr
, offset_reloc
);
1397 append_insn (&insn
, NULL
, unused_reloc
);
1401 /* Return true if the given relocation might need a matching %lo().
1402 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1403 applied to local symbols. */
1405 static inline bfd_boolean
1406 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1408 return (HAVE_IN_PLACE_ADDENDS
1409 && (reloc
== BFD_RELOC_HI16_S
1410 || reloc
== BFD_RELOC_MIPS_GOT16
1411 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1414 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1417 static inline bfd_boolean
1418 fixup_has_matching_lo_p (fixS
*fixp
)
1420 return (fixp
->fx_next
!= NULL
1421 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1422 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1423 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1424 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1427 /* See whether instruction IP reads register REG. CLASS is the type
1431 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1432 enum mips_regclass
class)
1434 if (class == MIPS16_REG
)
1436 assert (mips_opts
.mips16
);
1437 reg
= mips16_to_32_reg_map
[reg
];
1438 class = MIPS_GR_REG
;
1441 /* Don't report on general register ZERO, since it never changes. */
1442 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1445 if (class == MIPS_FP_REG
)
1447 assert (! mips_opts
.mips16
);
1448 /* If we are called with either $f0 or $f1, we must check $f0.
1449 This is not optimal, because it will introduce an unnecessary
1450 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1451 need to distinguish reading both $f0 and $f1 or just one of
1452 them. Note that we don't have to check the other way,
1453 because there is no instruction that sets both $f0 and $f1
1454 and requires a delay. */
1455 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1456 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1457 == (reg
&~ (unsigned) 1)))
1459 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1460 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1461 == (reg
&~ (unsigned) 1)))
1464 else if (! mips_opts
.mips16
)
1466 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1467 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1469 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1470 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1475 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1476 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1477 & MIPS16OP_MASK_RX
)]
1480 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1481 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1482 & MIPS16OP_MASK_RY
)]
1485 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1486 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1487 & MIPS16OP_MASK_MOVE32Z
)]
1490 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1492 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1494 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1496 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1497 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1498 & MIPS16OP_MASK_REGR32
) == reg
)
1505 /* This function returns true if modifying a register requires a
1509 reg_needs_delay (unsigned int reg
)
1511 unsigned long prev_pinfo
;
1513 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1514 if (! mips_opts
.noreorder
1515 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1516 && ! gpr_interlocks
)
1517 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1518 && ! cop_interlocks
)))
1520 /* A load from a coprocessor or from memory. All load delays
1521 delay the use of general register rt for one instruction. */
1522 /* Itbl support may require additional care here. */
1523 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1524 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1531 /* Mark instruction labels in mips16 mode. This permits the linker to
1532 handle them specially, such as generating jalx instructions when
1533 needed. We also make them odd for the duration of the assembly, in
1534 order to generate the right sort of code. We will make them even
1535 in the adjust_symtab routine, while leaving them marked. This is
1536 convenient for the debugger and the disassembler. The linker knows
1537 to make them odd again. */
1540 mips16_mark_labels (void)
1542 if (mips_opts
.mips16
)
1544 struct insn_label_list
*l
;
1547 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1550 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1551 S_SET_OTHER (l
->label
, STO_MIPS16
);
1553 val
= S_GET_VALUE (l
->label
);
1555 S_SET_VALUE (l
->label
, val
+ 1);
1560 /* End the current frag. Make it a variant frag and record the
1564 relax_close_frag (void)
1566 mips_macro_warning
.first_frag
= frag_now
;
1567 frag_var (rs_machine_dependent
, 0, 0,
1568 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1569 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1571 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1572 mips_relax
.first_fixup
= 0;
1575 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1576 See the comment above RELAX_ENCODE for more details. */
1579 relax_start (symbolS
*symbol
)
1581 assert (mips_relax
.sequence
== 0);
1582 mips_relax
.sequence
= 1;
1583 mips_relax
.symbol
= symbol
;
1586 /* Start generating the second version of a relaxable sequence.
1587 See the comment above RELAX_ENCODE for more details. */
1592 assert (mips_relax
.sequence
== 1);
1593 mips_relax
.sequence
= 2;
1596 /* End the current relaxable sequence. */
1601 assert (mips_relax
.sequence
== 2);
1602 relax_close_frag ();
1603 mips_relax
.sequence
= 0;
1606 /* Output an instruction. IP is the instruction information.
1607 ADDRESS_EXPR is an operand of the instruction to be used with
1611 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1612 bfd_reloc_code_real_type
*reloc_type
)
1614 register unsigned long prev_pinfo
, pinfo
;
1618 relax_stateT prev_insn_frag_type
= 0;
1619 bfd_boolean relaxed_branch
= FALSE
;
1620 bfd_boolean force_new_frag
= FALSE
;
1622 /* Mark instruction labels in mips16 mode. */
1623 mips16_mark_labels ();
1625 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1626 pinfo
= ip
->insn_mo
->pinfo
;
1628 if (mips_relax
.sequence
!= 2
1629 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1633 /* If the previous insn required any delay slots, see if we need
1634 to insert a NOP or two. There are eight kinds of possible
1635 hazards, of which an instruction can have at most one type.
1636 (1) a load from memory delay
1637 (2) a load from a coprocessor delay
1638 (3) an unconditional branch delay
1639 (4) a conditional branch delay
1640 (5) a move to coprocessor register delay
1641 (6) a load coprocessor register from memory delay
1642 (7) a coprocessor condition code delay
1643 (8) a HI/LO special register delay
1645 There are a lot of optimizations we could do that we don't.
1646 In particular, we do not, in general, reorder instructions.
1647 If you use gcc with optimization, it will reorder
1648 instructions and generally do much more optimization then we
1649 do here; repeating all that work in the assembler would only
1650 benefit hand written assembly code, and does not seem worth
1653 /* This is how a NOP is emitted. */
1654 #define emit_nop() \
1656 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1657 : md_number_to_chars (frag_more (4), 0, 4))
1659 /* The previous insn might require a delay slot, depending upon
1660 the contents of the current insn. */
1661 if (! mips_opts
.mips16
1662 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1663 && ! gpr_interlocks
)
1664 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1665 && ! cop_interlocks
)))
1667 /* A load from a coprocessor or from memory. All load
1668 delays delay the use of general register rt for one
1670 /* Itbl support may require additional care here. */
1671 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1672 if (mips_optimize
== 0
1673 || insn_uses_reg (ip
,
1674 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1679 else if (! mips_opts
.mips16
1680 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1681 && ! cop_interlocks
)
1682 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1683 && ! cop_mem_interlocks
)))
1685 /* A generic coprocessor delay. The previous instruction
1686 modified a coprocessor general or control register. If
1687 it modified a control register, we need to avoid any
1688 coprocessor instruction (this is probably not always
1689 required, but it sometimes is). If it modified a general
1690 register, we avoid using that register.
1692 This case is not handled very well. There is no special
1693 knowledge of CP0 handling, and the coprocessors other
1694 than the floating point unit are not distinguished at
1696 /* Itbl support may require additional care here. FIXME!
1697 Need to modify this to include knowledge about
1698 user specified delays! */
1699 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1701 if (mips_optimize
== 0
1702 || insn_uses_reg (ip
,
1703 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1708 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1710 if (mips_optimize
== 0
1711 || insn_uses_reg (ip
,
1712 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1719 /* We don't know exactly what the previous instruction
1720 does. If the current instruction uses a coprocessor
1721 register, we must insert a NOP. If previous
1722 instruction may set the condition codes, and the
1723 current instruction uses them, we must insert two
1725 /* Itbl support may require additional care here. */
1726 if (mips_optimize
== 0
1727 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1728 && (pinfo
& INSN_READ_COND_CODE
)))
1730 else if (pinfo
& INSN_COP
)
1734 else if (! mips_opts
.mips16
1735 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1736 && ! cop_interlocks
)
1738 /* The previous instruction sets the coprocessor condition
1739 codes, but does not require a general coprocessor delay
1740 (this means it is a floating point comparison
1741 instruction). If this instruction uses the condition
1742 codes, we need to insert a single NOP. */
1743 /* Itbl support may require additional care here. */
1744 if (mips_optimize
== 0
1745 || (pinfo
& INSN_READ_COND_CODE
))
1749 /* If we're fixing up mfhi/mflo for the r7000 and the
1750 previous insn was an mfhi/mflo and the current insn
1751 reads the register that the mfhi/mflo wrote to, then
1754 else if (mips_7000_hilo_fix
1755 && MF_HILO_INSN (prev_pinfo
)
1756 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1763 /* If we're fixing up mfhi/mflo for the r7000 and the
1764 2nd previous insn was an mfhi/mflo and the current insn
1765 reads the register that the mfhi/mflo wrote to, then
1768 else if (mips_7000_hilo_fix
1769 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1770 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1778 else if (prev_pinfo
& INSN_READ_LO
)
1780 /* The previous instruction reads the LO register; if the
1781 current instruction writes to the LO register, we must
1782 insert two NOPS. Some newer processors have interlocks.
1783 Also the tx39's multiply instructions can be executed
1784 immediately after a read from HI/LO (without the delay),
1785 though the tx39's divide insns still do require the
1787 if (! (hilo_interlocks
1788 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1789 && (mips_optimize
== 0
1790 || (pinfo
& INSN_WRITE_LO
)))
1792 /* Most mips16 branch insns don't have a delay slot.
1793 If a read from LO is immediately followed by a branch
1794 to a write to LO we have a read followed by a write
1795 less than 2 insns away. We assume the target of
1796 a branch might be a write to LO, and insert a nop
1797 between a read and an immediately following branch. */
1798 else if (mips_opts
.mips16
1799 && (mips_optimize
== 0
1800 || (pinfo
& MIPS16_INSN_BRANCH
)))
1803 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1805 /* The previous instruction reads the HI register; if the
1806 current instruction writes to the HI register, we must
1807 insert a NOP. Some newer processors have interlocks.
1808 Also the note tx39's multiply above. */
1809 if (! (hilo_interlocks
1810 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1811 && (mips_optimize
== 0
1812 || (pinfo
& INSN_WRITE_HI
)))
1814 /* Most mips16 branch insns don't have a delay slot.
1815 If a read from HI is immediately followed by a branch
1816 to a write to HI we have a read followed by a write
1817 less than 2 insns away. We assume the target of
1818 a branch might be a write to HI, and insert a nop
1819 between a read and an immediately following branch. */
1820 else if (mips_opts
.mips16
1821 && (mips_optimize
== 0
1822 || (pinfo
& MIPS16_INSN_BRANCH
)))
1826 /* If the previous instruction was in a noreorder section, then
1827 we don't want to insert the nop after all. */
1828 /* Itbl support may require additional care here. */
1829 if (prev_insn_unreordered
)
1832 /* There are two cases which require two intervening
1833 instructions: 1) setting the condition codes using a move to
1834 coprocessor instruction which requires a general coprocessor
1835 delay and then reading the condition codes 2) reading the HI
1836 or LO register and then writing to it (except on processors
1837 which have interlocks). If we are not already emitting a NOP
1838 instruction, we must check for these cases compared to the
1839 instruction previous to the previous instruction. */
1840 if ((! mips_opts
.mips16
1841 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1842 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1843 && (pinfo
& INSN_READ_COND_CODE
)
1844 && ! cop_interlocks
)
1845 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1846 && (pinfo
& INSN_WRITE_LO
)
1847 && ! (hilo_interlocks
1848 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1849 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1850 && (pinfo
& INSN_WRITE_HI
)
1851 && ! (hilo_interlocks
1852 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1857 if (prev_prev_insn_unreordered
)
1860 if (prev_prev_nop
&& nops
== 0)
1863 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
1865 /* We're out of bits in pinfo, so we must resort to string
1866 ops here. Shortcuts are selected based on opcodes being
1867 limited to the VR4120 instruction set. */
1869 const char *pn
= prev_insn
.insn_mo
->name
;
1870 const char *tn
= ip
->insn_mo
->name
;
1871 if (strncmp (pn
, "macc", 4) == 0
1872 || strncmp (pn
, "dmacc", 5) == 0)
1874 /* Errata 21 - [D]DIV[U] after [D]MACC */
1875 if (strstr (tn
, "div"))
1878 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1879 instruction is executed immediately after a MACC or
1880 DMACC instruction, the result of [either instruction]
1882 if (strncmp (tn
, "mult", 4) == 0
1883 || strncmp (tn
, "dmult", 5) == 0)
1886 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1887 Applies on top of VR4181A MD(1) errata. */
1888 if (pn
[0] == 'd' && strncmp (tn
, "dmacc", 5) == 0)
1891 /* Errata 24 - MT{LO,HI} after [D]MACC */
1892 if (strcmp (tn
, "mtlo") == 0
1893 || strcmp (tn
, "mthi") == 0)
1896 else if (strncmp (pn
, "dmult", 5) == 0
1897 && (strncmp (tn
, "dmult", 5) == 0
1898 || strncmp (tn
, "dmacc", 5) == 0))
1900 /* Here is the rest of errata 23. */
1903 else if ((strncmp (pn
, "dmult", 5) == 0 || strstr (pn
, "div"))
1904 && (strncmp (tn
, "macc", 4) == 0
1905 || strncmp (tn
, "dmacc", 5) == 0))
1907 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1908 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1909 DDIV or DDIVU instruction, the result of the MACC or
1910 DMACC instruction is incorrect.". This partly overlaps
1911 the workaround for errata 23. */
1914 if (nops
< min_nops
)
1918 /* If we are being given a nop instruction, don't bother with
1919 one of the nops we would otherwise output. This will only
1920 happen when a nop instruction is used with mips_optimize set
1923 && ! mips_opts
.noreorder
1924 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1927 /* Now emit the right number of NOP instructions. */
1928 if (nops
> 0 && ! mips_opts
.noreorder
)
1931 unsigned long old_frag_offset
;
1933 struct insn_label_list
*l
;
1935 old_frag
= frag_now
;
1936 old_frag_offset
= frag_now_fix ();
1938 for (i
= 0; i
< nops
; i
++)
1943 listing_prev_line ();
1944 /* We may be at the start of a variant frag. In case we
1945 are, make sure there is enough space for the frag
1946 after the frags created by listing_prev_line. The
1947 argument to frag_grow here must be at least as large
1948 as the argument to all other calls to frag_grow in
1949 this file. We don't have to worry about being in the
1950 middle of a variant frag, because the variants insert
1951 all needed nop instructions themselves. */
1955 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1959 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1960 symbol_set_frag (l
->label
, frag_now
);
1961 val
= (valueT
) frag_now_fix ();
1962 /* mips16 text labels are stored as odd. */
1963 if (mips_opts
.mips16
)
1965 S_SET_VALUE (l
->label
, val
);
1968 #ifndef NO_ECOFF_DEBUGGING
1969 if (ECOFF_DEBUGGING
)
1970 ecoff_fix_loc (old_frag
, old_frag_offset
);
1973 else if (prev_nop_frag
!= NULL
)
1975 /* We have a frag holding nops we may be able to remove. If
1976 we don't need any nops, we can decrease the size of
1977 prev_nop_frag by the size of one instruction. If we do
1978 need some nops, we count them in prev_nops_required. */
1979 if (prev_nop_frag_since
== 0)
1983 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1984 --prev_nop_frag_holds
;
1987 prev_nop_frag_required
+= nops
;
1991 if (prev_prev_nop
== 0)
1993 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1994 --prev_nop_frag_holds
;
1997 ++prev_nop_frag_required
;
2000 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
2001 prev_nop_frag
= NULL
;
2003 ++prev_nop_frag_since
;
2005 /* Sanity check: by the time we reach the second instruction
2006 after prev_nop_frag, we should have used up all the nops
2007 one way or another. */
2008 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2012 /* Record the frag type before frag_var. */
2014 prev_insn_frag_type
= prev_insn_frag
->fr_type
;
2017 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2018 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2019 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2020 && mips_relax_branch
2021 /* Don't try branch relaxation within .set nomacro, or within
2022 .set noat if we use $at for PIC computations. If it turns
2023 out that the branch was out-of-range, we'll get an error. */
2024 && !mips_opts
.warn_about_macros
2025 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2026 && !mips_opts
.mips16
)
2028 relaxed_branch
= TRUE
;
2029 f
= frag_var (rs_machine_dependent
,
2030 relaxed_branch_length
2032 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2033 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2035 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2036 pinfo
& INSN_COND_BRANCH_LIKELY
,
2037 pinfo
& INSN_WRITE_GPR_31
,
2039 address_expr
->X_add_symbol
,
2040 address_expr
->X_add_number
,
2042 *reloc_type
= BFD_RELOC_UNUSED
;
2044 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2046 /* We need to set up a variant frag. */
2047 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2048 f
= frag_var (rs_machine_dependent
, 4, 0,
2049 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2050 mips16_small
, mips16_ext
,
2052 & INSN_UNCOND_BRANCH_DELAY
),
2053 (*prev_insn_reloc_type
2054 == BFD_RELOC_MIPS16_JMP
)),
2055 make_expr_symbol (address_expr
), 0, NULL
);
2057 else if (mips_opts
.mips16
2059 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2061 /* Make sure there is enough room to swap this instruction with
2062 a following jump instruction. */
2068 if (mips_opts
.mips16
2069 && mips_opts
.noreorder
2070 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2071 as_warn (_("extended instruction in delay slot"));
2073 if (mips_relax
.sequence
)
2075 /* If we've reached the end of this frag, turn it into a variant
2076 frag and record the information for the instructions we've
2078 if (frag_room () < 4)
2079 relax_close_frag ();
2080 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2083 if (mips_relax
.sequence
!= 2)
2084 mips_macro_warning
.sizes
[0] += 4;
2085 if (mips_relax
.sequence
!= 1)
2086 mips_macro_warning
.sizes
[1] += 4;
2091 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2092 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2094 if (address_expr
->X_op
== O_constant
)
2098 switch (*reloc_type
)
2101 ip
->insn_opcode
|= address_expr
->X_add_number
;
2104 case BFD_RELOC_MIPS_HIGHEST
:
2105 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2106 ip
->insn_opcode
|= tmp
& 0xffff;
2109 case BFD_RELOC_MIPS_HIGHER
:
2110 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2111 ip
->insn_opcode
|= tmp
& 0xffff;
2114 case BFD_RELOC_HI16_S
:
2115 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2116 ip
->insn_opcode
|= tmp
& 0xffff;
2119 case BFD_RELOC_HI16
:
2120 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2123 case BFD_RELOC_UNUSED
:
2124 case BFD_RELOC_LO16
:
2125 case BFD_RELOC_MIPS_GOT_DISP
:
2126 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2129 case BFD_RELOC_MIPS_JMP
:
2130 if ((address_expr
->X_add_number
& 3) != 0)
2131 as_bad (_("jump to misaligned address (0x%lx)"),
2132 (unsigned long) address_expr
->X_add_number
);
2133 if (address_expr
->X_add_number
& ~0xfffffff)
2134 as_bad (_("jump address range overflow (0x%lx)"),
2135 (unsigned long) address_expr
->X_add_number
);
2136 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2139 case BFD_RELOC_MIPS16_JMP
:
2140 if ((address_expr
->X_add_number
& 3) != 0)
2141 as_bad (_("jump to misaligned address (0x%lx)"),
2142 (unsigned long) address_expr
->X_add_number
);
2143 if (address_expr
->X_add_number
& ~0xfffffff)
2144 as_bad (_("jump address range overflow (0x%lx)"),
2145 (unsigned long) address_expr
->X_add_number
);
2147 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2148 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2149 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2152 case BFD_RELOC_16_PCREL_S2
:
2159 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2162 reloc_howto_type
*howto
;
2165 /* In a compound relocation, it is the final (outermost)
2166 operator that determines the relocated field. */
2167 for (i
= 1; i
< 3; i
++)
2168 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2171 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2172 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2173 bfd_get_reloc_size(howto
),
2175 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2178 /* These relocations can have an addend that won't fit in
2179 4 octets for 64bit assembly. */
2181 && ! howto
->partial_inplace
2182 && (reloc_type
[0] == BFD_RELOC_16
2183 || reloc_type
[0] == BFD_RELOC_32
2184 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2185 || reloc_type
[0] == BFD_RELOC_HI16_S
2186 || reloc_type
[0] == BFD_RELOC_LO16
2187 || reloc_type
[0] == BFD_RELOC_GPREL16
2188 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2189 || reloc_type
[0] == BFD_RELOC_GPREL32
2190 || reloc_type
[0] == BFD_RELOC_64
2191 || reloc_type
[0] == BFD_RELOC_CTOR
2192 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2193 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2194 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2195 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2196 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2197 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2198 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2199 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2200 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2201 fixp
[0]->fx_no_overflow
= 1;
2203 if (mips_relax
.sequence
)
2205 if (mips_relax
.first_fixup
== 0)
2206 mips_relax
.first_fixup
= fixp
[0];
2208 else if (reloc_needs_lo_p (*reloc_type
))
2210 struct mips_hi_fixup
*hi_fixup
;
2212 /* Reuse the last entry if it already has a matching %lo. */
2213 hi_fixup
= mips_hi_fixup_list
;
2215 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2217 hi_fixup
= ((struct mips_hi_fixup
*)
2218 xmalloc (sizeof (struct mips_hi_fixup
)));
2219 hi_fixup
->next
= mips_hi_fixup_list
;
2220 mips_hi_fixup_list
= hi_fixup
;
2222 hi_fixup
->fixp
= fixp
[0];
2223 hi_fixup
->seg
= now_seg
;
2226 /* Add fixups for the second and third relocations, if given.
2227 Note that the ABI allows the second relocation to be
2228 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2229 moment we only use RSS_UNDEF, but we could add support
2230 for the others if it ever becomes necessary. */
2231 for (i
= 1; i
< 3; i
++)
2232 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2234 fixp
[i
] = fix_new (frag_now
, fixp
[0]->fx_where
,
2235 fixp
[0]->fx_size
, NULL
, 0,
2236 FALSE
, reloc_type
[i
]);
2238 /* Use fx_tcbit to mark compound relocs. */
2239 fixp
[0]->fx_tcbit
= 1;
2240 fixp
[i
]->fx_tcbit
= 1;
2245 if (! mips_opts
.mips16
)
2247 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2249 dwarf2_emit_insn (4);
2252 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2254 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2255 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2257 /* The value passed to dwarf2_emit_insn is the distance between
2258 the end of the current instruction and the address that should
2259 be recorded in the debug tables. Since we want to use ISA-encoded
2260 addresses in MIPS16 debug info, the value is one byte less than
2261 the real instruction length. */
2262 dwarf2_emit_insn (3);
2269 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2272 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2274 dwarf2_emit_insn (ip
->use_extend
? 3 : 1);
2278 /* Update the register mask information. */
2279 if (! mips_opts
.mips16
)
2281 if (pinfo
& INSN_WRITE_GPR_D
)
2282 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2283 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2284 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2285 if (pinfo
& INSN_READ_GPR_S
)
2286 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2287 if (pinfo
& INSN_WRITE_GPR_31
)
2288 mips_gprmask
|= 1 << RA
;
2289 if (pinfo
& INSN_WRITE_FPR_D
)
2290 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2291 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2292 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2293 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2294 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2295 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2296 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2297 if (pinfo
& INSN_COP
)
2299 /* We don't keep enough information to sort these cases out.
2300 The itbl support does keep this information however, although
2301 we currently don't support itbl fprmats as part of the cop
2302 instruction. May want to add this support in the future. */
2304 /* Never set the bit for $0, which is always zero. */
2305 mips_gprmask
&= ~1 << 0;
2309 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2310 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2311 & MIPS16OP_MASK_RX
);
2312 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2313 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2314 & MIPS16OP_MASK_RY
);
2315 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2316 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2317 & MIPS16OP_MASK_RZ
);
2318 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2319 mips_gprmask
|= 1 << TREG
;
2320 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2321 mips_gprmask
|= 1 << SP
;
2322 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2323 mips_gprmask
|= 1 << RA
;
2324 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2325 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2326 if (pinfo
& MIPS16_INSN_READ_Z
)
2327 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2328 & MIPS16OP_MASK_MOVE32Z
);
2329 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2330 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2331 & MIPS16OP_MASK_REGR32
);
2334 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2336 /* Filling the branch delay slot is more complex. We try to
2337 switch the branch with the previous instruction, which we can
2338 do if the previous instruction does not set up a condition
2339 that the branch tests and if the branch is not itself the
2340 target of any branch. */
2341 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2342 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2344 if (mips_optimize
< 2
2345 /* If we have seen .set volatile or .set nomove, don't
2347 || mips_opts
.nomove
!= 0
2348 /* If we had to emit any NOP instructions, then we
2349 already know we can not swap. */
2351 /* If we don't even know the previous insn, we can not
2353 || ! prev_insn_valid
2354 /* If the previous insn is already in a branch delay
2355 slot, then we can not swap. */
2356 || prev_insn_is_delay_slot
2357 /* If the previous previous insn was in a .set
2358 noreorder, we can't swap. Actually, the MIPS
2359 assembler will swap in this situation. However, gcc
2360 configured -with-gnu-as will generate code like
2366 in which we can not swap the bne and INSN. If gcc is
2367 not configured -with-gnu-as, it does not output the
2368 .set pseudo-ops. We don't have to check
2369 prev_insn_unreordered, because prev_insn_valid will
2370 be 0 in that case. We don't want to use
2371 prev_prev_insn_valid, because we do want to be able
2372 to swap at the start of a function. */
2373 || prev_prev_insn_unreordered
2374 /* If the branch is itself the target of a branch, we
2375 can not swap. We cheat on this; all we check for is
2376 whether there is a label on this instruction. If
2377 there are any branches to anything other than a
2378 label, users must use .set noreorder. */
2379 || insn_labels
!= NULL
2380 /* If the previous instruction is in a variant frag
2381 other than this branch's one, we cannot do the swap.
2382 This does not apply to the mips16, which uses variant
2383 frags for different purposes. */
2384 || (! mips_opts
.mips16
2385 && prev_insn_frag_type
== rs_machine_dependent
)
2386 /* If the branch reads the condition codes, we don't
2387 even try to swap, because in the sequence
2392 we can not swap, and I don't feel like handling that
2394 || (! mips_opts
.mips16
2395 && (pinfo
& INSN_READ_COND_CODE
)
2396 && ! cop_interlocks
)
2397 /* We can not swap with an instruction that requires a
2398 delay slot, because the target of the branch might
2399 interfere with that instruction. */
2400 || (! mips_opts
.mips16
2402 /* Itbl support may require additional care here. */
2403 & (INSN_LOAD_COPROC_DELAY
2404 | INSN_COPROC_MOVE_DELAY
2405 | INSN_WRITE_COND_CODE
))
2406 && ! cop_interlocks
)
2407 || (! (hilo_interlocks
2408 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2412 || (! mips_opts
.mips16
2413 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2414 && ! gpr_interlocks
)
2415 || (! mips_opts
.mips16
2416 /* Itbl support may require additional care here. */
2417 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2418 && ! cop_mem_interlocks
)
2419 /* We can not swap with a branch instruction. */
2421 & (INSN_UNCOND_BRANCH_DELAY
2422 | INSN_COND_BRANCH_DELAY
2423 | INSN_COND_BRANCH_LIKELY
))
2424 /* We do not swap with a trap instruction, since it
2425 complicates trap handlers to have the trap
2426 instruction be in a delay slot. */
2427 || (prev_pinfo
& INSN_TRAP
)
2428 /* If the branch reads a register that the previous
2429 instruction sets, we can not swap. */
2430 || (! mips_opts
.mips16
2431 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2432 && insn_uses_reg (ip
,
2433 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2436 || (! mips_opts
.mips16
2437 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2438 && insn_uses_reg (ip
,
2439 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2442 || (mips_opts
.mips16
2443 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2444 && insn_uses_reg (ip
,
2445 ((prev_insn
.insn_opcode
2447 & MIPS16OP_MASK_RX
),
2449 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2450 && insn_uses_reg (ip
,
2451 ((prev_insn
.insn_opcode
2453 & MIPS16OP_MASK_RY
),
2455 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2456 && insn_uses_reg (ip
,
2457 ((prev_insn
.insn_opcode
2459 & MIPS16OP_MASK_RZ
),
2461 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2462 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2463 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2464 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2465 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2466 && insn_uses_reg (ip
,
2467 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2470 /* If the branch writes a register that the previous
2471 instruction sets, we can not swap (we know that
2472 branches write only to RD or to $31). */
2473 || (! mips_opts
.mips16
2474 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2475 && (((pinfo
& INSN_WRITE_GPR_D
)
2476 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2477 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2478 || ((pinfo
& INSN_WRITE_GPR_31
)
2479 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2482 || (! mips_opts
.mips16
2483 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2484 && (((pinfo
& INSN_WRITE_GPR_D
)
2485 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2486 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2487 || ((pinfo
& INSN_WRITE_GPR_31
)
2488 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2491 || (mips_opts
.mips16
2492 && (pinfo
& MIPS16_INSN_WRITE_31
)
2493 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2494 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2495 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2497 /* If the branch writes a register that the previous
2498 instruction reads, we can not swap (we know that
2499 branches only write to RD or to $31). */
2500 || (! mips_opts
.mips16
2501 && (pinfo
& INSN_WRITE_GPR_D
)
2502 && insn_uses_reg (&prev_insn
,
2503 ((ip
->insn_opcode
>> OP_SH_RD
)
2506 || (! mips_opts
.mips16
2507 && (pinfo
& INSN_WRITE_GPR_31
)
2508 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2509 || (mips_opts
.mips16
2510 && (pinfo
& MIPS16_INSN_WRITE_31
)
2511 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2512 /* If the previous previous instruction has a load
2513 delay, and sets a register that the branch reads, we
2515 || (! mips_opts
.mips16
2516 /* Itbl support may require additional care here. */
2517 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2518 && ! cop_interlocks
)
2519 || ((prev_prev_insn
.insn_mo
->pinfo
2520 & INSN_LOAD_MEMORY_DELAY
)
2521 && ! gpr_interlocks
))
2522 && insn_uses_reg (ip
,
2523 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2526 /* If one instruction sets a condition code and the
2527 other one uses a condition code, we can not swap. */
2528 || ((pinfo
& INSN_READ_COND_CODE
)
2529 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2530 || ((pinfo
& INSN_WRITE_COND_CODE
)
2531 && (prev_pinfo
& INSN_READ_COND_CODE
))
2532 /* If the previous instruction uses the PC, we can not
2534 || (mips_opts
.mips16
2535 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2536 /* If the previous instruction was extended, we can not
2538 || (mips_opts
.mips16
&& prev_insn_extended
)
2539 /* If the previous instruction had a fixup in mips16
2540 mode, we can not swap. This normally means that the
2541 previous instruction was a 4 byte branch anyhow. */
2542 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2543 /* If the previous instruction is a sync, sync.l, or
2544 sync.p, we can not swap. */
2545 || (prev_pinfo
& INSN_SYNC
))
2547 /* We could do even better for unconditional branches to
2548 portions of this object file; we could pick up the
2549 instruction at the destination, put it in the delay
2550 slot, and bump the destination address. */
2552 if (mips_relax
.sequence
)
2553 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2554 /* Update the previous insn information. */
2555 prev_prev_insn
= *ip
;
2556 prev_insn
.insn_mo
= &dummy_opcode
;
2560 /* It looks like we can actually do the swap. */
2561 if (! mips_opts
.mips16
)
2566 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2567 if (!relaxed_branch
)
2569 /* If this is not a relaxed branch, then just
2570 swap the instructions. */
2571 memcpy (temp
, prev_f
, 4);
2572 memcpy (prev_f
, f
, 4);
2573 memcpy (f
, temp
, 4);
2577 /* If this is a relaxed branch, then we move the
2578 instruction to be placed in the delay slot to
2579 the current frag, shrinking the fixed part of
2580 the originating frag. If the branch occupies
2581 the tail of the latter, we move it backwards,
2582 into the space freed by the moved instruction. */
2584 memcpy (f
, prev_f
, 4);
2585 prev_insn_frag
->fr_fix
-= 4;
2586 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2587 memmove (prev_f
, prev_f
+ 4, prev_insn_frag
->fr_var
);
2590 if (prev_insn_fixp
[0])
2592 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2593 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2595 if (prev_insn_fixp
[1])
2597 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2598 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2600 if (prev_insn_fixp
[2])
2602 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2603 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2605 if (prev_insn_fixp
[0] && HAVE_NEWABI
2606 && prev_insn_frag
!= frag_now
2607 && (prev_insn_fixp
[0]->fx_r_type
2608 == BFD_RELOC_MIPS_GOT_DISP
2609 || (prev_insn_fixp
[0]->fx_r_type
2610 == BFD_RELOC_MIPS_CALL16
)))
2612 /* To avoid confusion in tc_gen_reloc, we must
2613 ensure that this does not become a variant
2615 force_new_frag
= TRUE
;
2618 if (!relaxed_branch
)
2622 fixp
[0]->fx_frag
= prev_insn_frag
;
2623 fixp
[0]->fx_where
= prev_insn_where
;
2627 fixp
[1]->fx_frag
= prev_insn_frag
;
2628 fixp
[1]->fx_where
= prev_insn_where
;
2632 fixp
[2]->fx_frag
= prev_insn_frag
;
2633 fixp
[2]->fx_where
= prev_insn_where
;
2636 else if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2639 fixp
[0]->fx_where
-= 4;
2641 fixp
[1]->fx_where
-= 4;
2643 fixp
[2]->fx_where
-= 4;
2651 assert (prev_insn_fixp
[0] == NULL
);
2652 assert (prev_insn_fixp
[1] == NULL
);
2653 assert (prev_insn_fixp
[2] == NULL
);
2654 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2655 memcpy (temp
, prev_f
, 2);
2656 memcpy (prev_f
, f
, 2);
2657 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2659 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2660 memcpy (f
, temp
, 2);
2664 memcpy (f
, f
+ 2, 2);
2665 memcpy (f
+ 2, temp
, 2);
2669 fixp
[0]->fx_frag
= prev_insn_frag
;
2670 fixp
[0]->fx_where
= prev_insn_where
;
2674 fixp
[1]->fx_frag
= prev_insn_frag
;
2675 fixp
[1]->fx_where
= prev_insn_where
;
2679 fixp
[2]->fx_frag
= prev_insn_frag
;
2680 fixp
[2]->fx_where
= prev_insn_where
;
2684 /* Update the previous insn information; leave prev_insn
2686 prev_prev_insn
= *ip
;
2688 prev_insn_is_delay_slot
= 1;
2690 /* If that was an unconditional branch, forget the previous
2691 insn information. */
2692 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2694 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2695 prev_insn
.insn_mo
= &dummy_opcode
;
2698 prev_insn_fixp
[0] = NULL
;
2699 prev_insn_fixp
[1] = NULL
;
2700 prev_insn_fixp
[2] = NULL
;
2701 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2702 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2703 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2704 prev_insn_extended
= 0;
2706 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2708 /* We don't yet optimize a branch likely. What we should do
2709 is look at the target, copy the instruction found there
2710 into the delay slot, and increment the branch to jump to
2711 the next instruction. */
2713 /* Update the previous insn information. */
2714 prev_prev_insn
= *ip
;
2715 prev_insn
.insn_mo
= &dummy_opcode
;
2716 prev_insn_fixp
[0] = NULL
;
2717 prev_insn_fixp
[1] = NULL
;
2718 prev_insn_fixp
[2] = NULL
;
2719 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2720 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2721 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2722 prev_insn_extended
= 0;
2723 prev_insn_is_delay_slot
= 1;
2727 /* Update the previous insn information. */
2729 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2731 prev_prev_insn
= prev_insn
;
2734 /* Any time we see a branch, we always fill the delay slot
2735 immediately; since this insn is not a branch, we know it
2736 is not in a delay slot. */
2737 prev_insn_is_delay_slot
= 0;
2739 prev_insn_fixp
[0] = fixp
[0];
2740 prev_insn_fixp
[1] = fixp
[1];
2741 prev_insn_fixp
[2] = fixp
[2];
2742 prev_insn_reloc_type
[0] = reloc_type
[0];
2743 prev_insn_reloc_type
[1] = reloc_type
[1];
2744 prev_insn_reloc_type
[2] = reloc_type
[2];
2745 if (mips_opts
.mips16
)
2746 prev_insn_extended
= (ip
->use_extend
2747 || *reloc_type
> BFD_RELOC_UNUSED
);
2750 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2751 prev_insn_unreordered
= 0;
2752 prev_insn_frag
= frag_now
;
2753 prev_insn_where
= f
- frag_now
->fr_literal
;
2754 prev_insn_valid
= 1;
2756 else if (mips_relax
.sequence
!= 2)
2758 /* We need to record a bit of information even when we are not
2759 reordering, in order to determine the base address for mips16
2760 PC relative relocs. */
2761 prev_prev_insn
= prev_insn
;
2763 prev_insn_reloc_type
[0] = reloc_type
[0];
2764 prev_insn_reloc_type
[1] = reloc_type
[1];
2765 prev_insn_reloc_type
[2] = reloc_type
[2];
2766 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2767 prev_insn_unreordered
= 1;
2770 /* We just output an insn, so the next one doesn't have a label. */
2771 mips_clear_insn_labels ();
2774 /* This function forgets that there was any previous instruction or
2775 label. If PRESERVE is non-zero, it remembers enough information to
2776 know whether nops are needed before a noreorder section. */
2779 mips_no_prev_insn (int preserve
)
2783 prev_insn
.insn_mo
= &dummy_opcode
;
2784 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2785 prev_nop_frag
= NULL
;
2786 prev_nop_frag_holds
= 0;
2787 prev_nop_frag_required
= 0;
2788 prev_nop_frag_since
= 0;
2790 prev_insn_valid
= 0;
2791 prev_insn_is_delay_slot
= 0;
2792 prev_insn_unreordered
= 0;
2793 prev_insn_extended
= 0;
2794 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2795 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2796 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2797 prev_prev_insn_unreordered
= 0;
2798 mips_clear_insn_labels ();
2801 /* This function must be called whenever we turn on noreorder or emit
2802 something other than instructions. It inserts any NOPS which might
2803 be needed by the previous instruction, and clears the information
2804 kept for the previous instructions. The INSNS parameter is true if
2805 instructions are to follow. */
2808 mips_emit_delays (bfd_boolean insns
)
2810 if (! mips_opts
.noreorder
)
2815 if ((! mips_opts
.mips16
2816 && ((prev_insn
.insn_mo
->pinfo
2817 & (INSN_LOAD_COPROC_DELAY
2818 | INSN_COPROC_MOVE_DELAY
2819 | INSN_WRITE_COND_CODE
))
2820 && ! cop_interlocks
))
2821 || (! hilo_interlocks
2822 && (prev_insn
.insn_mo
->pinfo
2825 || (! mips_opts
.mips16
2826 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2827 && ! gpr_interlocks
)
2828 || (! mips_opts
.mips16
2829 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2830 && ! cop_mem_interlocks
))
2832 /* Itbl support may require additional care here. */
2834 if ((! mips_opts
.mips16
2835 && ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2836 && ! cop_interlocks
))
2837 || (! hilo_interlocks
2838 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2839 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2842 if (prev_insn_unreordered
)
2845 else if ((! mips_opts
.mips16
2846 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2847 && ! cop_interlocks
))
2848 || (! hilo_interlocks
2849 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2850 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2852 /* Itbl support may require additional care here. */
2853 if (! prev_prev_insn_unreordered
)
2857 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
2860 const char *pn
= prev_insn
.insn_mo
->name
;
2861 if (strncmp (pn
, "macc", 4) == 0
2862 || strncmp (pn
, "dmacc", 5) == 0
2863 || strncmp (pn
, "dmult", 5) == 0
2864 || strstr (pn
, "div"))
2866 if (nops
< min_nops
)
2872 struct insn_label_list
*l
;
2876 /* Record the frag which holds the nop instructions, so
2877 that we can remove them if we don't need them. */
2878 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2879 prev_nop_frag
= frag_now
;
2880 prev_nop_frag_holds
= nops
;
2881 prev_nop_frag_required
= 0;
2882 prev_nop_frag_since
= 0;
2885 for (; nops
> 0; --nops
)
2890 /* Move on to a new frag, so that it is safe to simply
2891 decrease the size of prev_nop_frag. */
2892 frag_wane (frag_now
);
2896 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2900 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2901 symbol_set_frag (l
->label
, frag_now
);
2902 val
= (valueT
) frag_now_fix ();
2903 /* mips16 text labels are stored as odd. */
2904 if (mips_opts
.mips16
)
2906 S_SET_VALUE (l
->label
, val
);
2911 /* Mark instruction labels in mips16 mode. */
2913 mips16_mark_labels ();
2915 mips_no_prev_insn (insns
);
2918 /* Set up global variables for the start of a new macro. */
2923 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2924 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2925 && (prev_insn
.insn_mo
->pinfo
2926 & (INSN_UNCOND_BRANCH_DELAY
2927 | INSN_COND_BRANCH_DELAY
2928 | INSN_COND_BRANCH_LIKELY
)) != 0);
2931 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2932 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2933 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2936 macro_warning (relax_substateT subtype
)
2938 if (subtype
& RELAX_DELAY_SLOT
)
2939 return _("Macro instruction expanded into multiple instructions"
2940 " in a branch delay slot");
2941 else if (subtype
& RELAX_NOMACRO
)
2942 return _("Macro instruction expanded into multiple instructions");
2947 /* Finish up a macro. Emit warnings as appropriate. */
2952 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2954 relax_substateT subtype
;
2956 /* Set up the relaxation warning flags. */
2958 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2959 subtype
|= RELAX_SECOND_LONGER
;
2960 if (mips_opts
.warn_about_macros
)
2961 subtype
|= RELAX_NOMACRO
;
2962 if (mips_macro_warning
.delay_slot_p
)
2963 subtype
|= RELAX_DELAY_SLOT
;
2965 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2967 /* Either the macro has a single implementation or both
2968 implementations are longer than 4 bytes. Emit the
2970 const char *msg
= macro_warning (subtype
);
2976 /* One implementation might need a warning but the other
2977 definitely doesn't. */
2978 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2983 /* Read a macro's relocation codes from *ARGS and store them in *R.
2984 The first argument in *ARGS will be either the code for a single
2985 relocation or -1 followed by the three codes that make up a
2986 composite relocation. */
2989 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2993 next
= va_arg (*args
, int);
2995 r
[0] = (bfd_reloc_code_real_type
) next
;
2997 for (i
= 0; i
< 3; i
++)
2998 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3001 /* Build an instruction created by a macro expansion. This is passed
3002 a pointer to the count of instructions created so far, an
3003 expression, the name of the instruction to build, an operand format
3004 string, and corresponding arguments. */
3007 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3009 struct mips_cl_insn insn
;
3010 bfd_reloc_code_real_type r
[3];
3013 va_start (args
, fmt
);
3015 if (mips_opts
.mips16
)
3017 mips16_macro_build (ep
, name
, fmt
, args
);
3022 r
[0] = BFD_RELOC_UNUSED
;
3023 r
[1] = BFD_RELOC_UNUSED
;
3024 r
[2] = BFD_RELOC_UNUSED
;
3025 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3026 assert (insn
.insn_mo
);
3027 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3029 /* Search until we get a match for NAME. */
3032 /* It is assumed here that macros will never generate
3033 MDMX or MIPS-3D instructions. */
3034 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
3035 && insn
.insn_mo
->pinfo
!= INSN_MACRO
3036 && OPCODE_IS_MEMBER (insn
.insn_mo
,
3038 | (file_ase_mips16
? INSN_MIPS16
: 0)),
3040 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
3044 assert (insn
.insn_mo
->name
);
3045 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3048 insn
.insn_opcode
= insn
.insn_mo
->match
;
3066 insn
.insn_opcode
|= (va_arg (args
, int)
3067 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
3072 /* Note that in the macro case, these arguments are already
3073 in MSB form. (When handling the instruction in the
3074 non-macro case, these arguments are sizes from which
3075 MSB values must be calculated.) */
3076 insn
.insn_opcode
|= (va_arg (args
, int)
3077 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
3083 /* Note that in the macro case, these arguments are already
3084 in MSBD form. (When handling the instruction in the
3085 non-macro case, these arguments are sizes from which
3086 MSBD values must be calculated.) */
3087 insn
.insn_opcode
|= (va_arg (args
, int)
3088 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
3099 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3103 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3108 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3114 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3119 int tmp
= va_arg (args
, int);
3121 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3122 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3128 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3135 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3139 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3143 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3147 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3151 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3158 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3164 macro_read_relocs (&args
, r
);
3165 assert (*r
== BFD_RELOC_GPREL16
3166 || *r
== BFD_RELOC_MIPS_LITERAL
3167 || *r
== BFD_RELOC_MIPS_HIGHER
3168 || *r
== BFD_RELOC_HI16_S
3169 || *r
== BFD_RELOC_LO16
3170 || *r
== BFD_RELOC_MIPS_GOT16
3171 || *r
== BFD_RELOC_MIPS_CALL16
3172 || *r
== BFD_RELOC_MIPS_GOT_DISP
3173 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3174 || *r
== BFD_RELOC_MIPS_GOT_OFST
3175 || *r
== BFD_RELOC_MIPS_GOT_LO16
3176 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3180 macro_read_relocs (&args
, r
);
3182 && (ep
->X_op
== O_constant
3183 || (ep
->X_op
== O_symbol
3184 && (*r
== BFD_RELOC_MIPS_HIGHEST
3185 || *r
== BFD_RELOC_HI16_S
3186 || *r
== BFD_RELOC_HI16
3187 || *r
== BFD_RELOC_GPREL16
3188 || *r
== BFD_RELOC_MIPS_GOT_HI16
3189 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3193 assert (ep
!= NULL
);
3195 * This allows macro() to pass an immediate expression for
3196 * creating short branches without creating a symbol.
3197 * Note that the expression still might come from the assembly
3198 * input, in which case the value is not checked for range nor
3199 * is a relocation entry generated (yuck).
3201 if (ep
->X_op
== O_constant
)
3203 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3207 *r
= BFD_RELOC_16_PCREL_S2
;
3211 assert (ep
!= NULL
);
3212 *r
= BFD_RELOC_MIPS_JMP
;
3216 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3225 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3227 append_insn (&insn
, ep
, r
);
3231 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3234 struct mips_cl_insn insn
;
3235 bfd_reloc_code_real_type r
[3]
3236 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3238 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3239 assert (insn
.insn_mo
);
3240 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3242 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3243 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3246 assert (insn
.insn_mo
->name
);
3247 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3250 insn
.insn_opcode
= insn
.insn_mo
->match
;
3251 insn
.use_extend
= FALSE
;
3270 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3275 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3279 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3283 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3293 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3300 regno
= va_arg (args
, int);
3301 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3302 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3323 assert (ep
!= NULL
);
3325 if (ep
->X_op
!= O_constant
)
3326 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3329 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3330 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3333 *r
= BFD_RELOC_UNUSED
;
3339 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3346 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3348 append_insn (&insn
, ep
, r
);
3352 * Generate a "jalr" instruction with a relocation hint to the called
3353 * function. This occurs in NewABI PIC code.
3356 macro_build_jalr (expressionS
*ep
)
3365 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3367 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3368 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3372 * Generate a "lui" instruction.
3375 macro_build_lui (expressionS
*ep
, int regnum
)
3377 expressionS high_expr
;
3378 struct mips_cl_insn insn
;
3379 bfd_reloc_code_real_type r
[3]
3380 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3381 const char *name
= "lui";
3382 const char *fmt
= "t,u";
3384 assert (! mips_opts
.mips16
);
3388 if (high_expr
.X_op
== O_constant
)
3390 /* we can compute the instruction now without a relocation entry */
3391 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3393 *r
= BFD_RELOC_UNUSED
;
3397 assert (ep
->X_op
== O_symbol
);
3398 /* _gp_disp is a special case, used from s_cpload. _gp is used
3399 if mips_no_shared. */
3400 assert (mips_pic
== NO_PIC
3402 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3403 || (! mips_in_shared
3404 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp") == 0));
3405 *r
= BFD_RELOC_HI16_S
;
3408 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3409 assert (insn
.insn_mo
);
3410 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3411 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3413 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3414 if (*r
== BFD_RELOC_UNUSED
)
3416 insn
.insn_opcode
|= high_expr
.X_add_number
;
3417 append_insn (&insn
, NULL
, r
);
3420 append_insn (&insn
, &high_expr
, r
);
3423 /* Generate a sequence of instructions to do a load or store from a constant
3424 offset off of a base register (breg) into/from a target register (treg),
3425 using AT if necessary. */
3427 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3428 int treg
, int breg
, int dbl
)
3430 assert (ep
->X_op
== O_constant
);
3432 /* Sign-extending 32-bit constants makes their handling easier. */
3433 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3434 == ~((bfd_vma
) 0x7fffffff)))
3436 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3437 as_bad (_("constant too large"));
3439 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3443 /* Right now, this routine can only handle signed 32-bit constants. */
3444 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3445 as_warn (_("operand overflow"));
3447 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3449 /* Signed 16-bit offset will fit in the op. Easy! */
3450 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3454 /* 32-bit offset, need multiple instructions and AT, like:
3455 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3456 addu $tempreg,$tempreg,$breg
3457 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3458 to handle the complete offset. */
3459 macro_build_lui (ep
, AT
);
3460 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3461 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3464 as_warn (_("Macro used $at after \".set noat\""));
3469 * Generates code to set the $at register to true (one)
3470 * if reg is less than the immediate expression.
3473 set_at (int reg
, int unsignedp
)
3475 if (imm_expr
.X_op
== O_constant
3476 && imm_expr
.X_add_number
>= -0x8000
3477 && imm_expr
.X_add_number
< 0x8000)
3478 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3479 AT
, reg
, BFD_RELOC_LO16
);
3482 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3483 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3488 normalize_constant_expr (expressionS
*ex
)
3490 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3491 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3495 /* Warn if an expression is not a constant. */
3498 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3500 if (ex
->X_op
== O_big
)
3501 as_bad (_("unsupported large constant"));
3502 else if (ex
->X_op
!= O_constant
)
3503 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3505 normalize_constant_expr (ex
);
3508 /* Count the leading zeroes by performing a binary chop. This is a
3509 bulky bit of source, but performance is a LOT better for the
3510 majority of values than a simple loop to count the bits:
3511 for (lcnt = 0; (lcnt < 32); lcnt++)
3512 if ((v) & (1 << (31 - lcnt)))
3514 However it is not code size friendly, and the gain will drop a bit
3515 on certain cached systems.
3517 #define COUNT_TOP_ZEROES(v) \
3518 (((v) & ~0xffff) == 0 \
3519 ? ((v) & ~0xff) == 0 \
3520 ? ((v) & ~0xf) == 0 \
3521 ? ((v) & ~0x3) == 0 \
3522 ? ((v) & ~0x1) == 0 \
3527 : ((v) & ~0x7) == 0 \
3530 : ((v) & ~0x3f) == 0 \
3531 ? ((v) & ~0x1f) == 0 \
3534 : ((v) & ~0x7f) == 0 \
3537 : ((v) & ~0xfff) == 0 \
3538 ? ((v) & ~0x3ff) == 0 \
3539 ? ((v) & ~0x1ff) == 0 \
3542 : ((v) & ~0x7ff) == 0 \
3545 : ((v) & ~0x3fff) == 0 \
3546 ? ((v) & ~0x1fff) == 0 \
3549 : ((v) & ~0x7fff) == 0 \
3552 : ((v) & ~0xffffff) == 0 \
3553 ? ((v) & ~0xfffff) == 0 \
3554 ? ((v) & ~0x3ffff) == 0 \
3555 ? ((v) & ~0x1ffff) == 0 \
3558 : ((v) & ~0x7ffff) == 0 \
3561 : ((v) & ~0x3fffff) == 0 \
3562 ? ((v) & ~0x1fffff) == 0 \
3565 : ((v) & ~0x7fffff) == 0 \
3568 : ((v) & ~0xfffffff) == 0 \
3569 ? ((v) & ~0x3ffffff) == 0 \
3570 ? ((v) & ~0x1ffffff) == 0 \
3573 : ((v) & ~0x7ffffff) == 0 \
3576 : ((v) & ~0x3fffffff) == 0 \
3577 ? ((v) & ~0x1fffffff) == 0 \
3580 : ((v) & ~0x7fffffff) == 0 \
3585 * This routine generates the least number of instructions necessary to load
3586 * an absolute expression value into a register.
3589 load_register (int reg
, expressionS
*ep
, int dbl
)
3592 expressionS hi32
, lo32
;
3594 if (ep
->X_op
!= O_big
)
3596 assert (ep
->X_op
== O_constant
);
3598 /* Sign-extending 32-bit constants makes their handling easier. */
3599 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3600 == ~((bfd_vma
) 0x7fffffff)))
3602 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3603 as_bad (_("constant too large"));
3605 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3609 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3611 /* We can handle 16 bit signed values with an addiu to
3612 $zero. No need to ever use daddiu here, since $zero and
3613 the result are always correct in 32 bit mode. */
3614 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3617 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3619 /* We can handle 16 bit unsigned values with an ori to
3621 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3624 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3626 /* 32 bit values require an lui. */
3627 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3628 if ((ep
->X_add_number
& 0xffff) != 0)
3629 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3634 /* The value is larger than 32 bits. */
3636 if (HAVE_32BIT_GPRS
)
3638 as_bad (_("Number (0x%lx) larger than 32 bits"),
3639 (unsigned long) ep
->X_add_number
);
3640 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3644 if (ep
->X_op
!= O_big
)
3647 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3648 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3649 hi32
.X_add_number
&= 0xffffffff;
3651 lo32
.X_add_number
&= 0xffffffff;
3655 assert (ep
->X_add_number
> 2);
3656 if (ep
->X_add_number
== 3)
3657 generic_bignum
[3] = 0;
3658 else if (ep
->X_add_number
> 4)
3659 as_bad (_("Number larger than 64 bits"));
3660 lo32
.X_op
= O_constant
;
3661 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3662 hi32
.X_op
= O_constant
;
3663 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3666 if (hi32
.X_add_number
== 0)
3671 unsigned long hi
, lo
;
3673 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3675 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3677 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3680 if (lo32
.X_add_number
& 0x80000000)
3682 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3683 if (lo32
.X_add_number
& 0xffff)
3684 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3689 /* Check for 16bit shifted constant. We know that hi32 is
3690 non-zero, so start the mask on the first bit of the hi32
3695 unsigned long himask
, lomask
;
3699 himask
= 0xffff >> (32 - shift
);
3700 lomask
= (0xffff << shift
) & 0xffffffff;
3704 himask
= 0xffff << (shift
- 32);
3707 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3708 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3712 tmp
.X_op
= O_constant
;
3714 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3715 | (lo32
.X_add_number
>> shift
));
3717 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3718 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3719 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3720 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3725 while (shift
<= (64 - 16));
3727 /* Find the bit number of the lowest one bit, and store the
3728 shifted value in hi/lo. */
3729 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3730 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3734 while ((lo
& 1) == 0)
3739 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3745 while ((hi
& 1) == 0)
3754 /* Optimize if the shifted value is a (power of 2) - 1. */
3755 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3756 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3758 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3763 /* This instruction will set the register to be all
3765 tmp
.X_op
= O_constant
;
3766 tmp
.X_add_number
= (offsetT
) -1;
3767 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3771 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3772 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3774 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3775 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3780 /* Sign extend hi32 before calling load_register, because we can
3781 generally get better code when we load a sign extended value. */
3782 if ((hi32
.X_add_number
& 0x80000000) != 0)
3783 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3784 load_register (reg
, &hi32
, 0);
3787 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3791 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3799 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3801 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3802 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3808 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3812 mid16
.X_add_number
>>= 16;
3813 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3814 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3817 if ((lo32
.X_add_number
& 0xffff) != 0)
3818 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3822 load_delay_nop (void)
3824 if (!gpr_interlocks
)
3825 macro_build (NULL
, "nop", "");
3828 /* Load an address into a register. */
3831 load_address (int reg
, expressionS
*ep
, int *used_at
)
3833 if (ep
->X_op
!= O_constant
3834 && ep
->X_op
!= O_symbol
)
3836 as_bad (_("expression too complex"));
3837 ep
->X_op
= O_constant
;
3840 if (ep
->X_op
== O_constant
)
3842 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3846 if (mips_pic
== NO_PIC
)
3848 /* If this is a reference to a GP relative symbol, we want
3849 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3851 lui $reg,<sym> (BFD_RELOC_HI16_S)
3852 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3853 If we have an addend, we always use the latter form.
3855 With 64bit address space and a usable $at we want
3856 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3857 lui $at,<sym> (BFD_RELOC_HI16_S)
3858 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3859 daddiu $at,<sym> (BFD_RELOC_LO16)
3863 If $at is already in use, we use a path which is suboptimal
3864 on superscalar processors.
3865 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3866 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3868 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3870 daddiu $reg,<sym> (BFD_RELOC_LO16)
3872 if (HAVE_64BIT_ADDRESSES
)
3874 /* ??? We don't provide a GP-relative alternative for these macros.
3875 It used not to be possible with the original relaxation code,
3876 but it could be done now. */
3878 if (*used_at
== 0 && !mips_opts
.noat
)
3880 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3881 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3882 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3883 BFD_RELOC_MIPS_HIGHER
);
3884 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3885 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3886 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3891 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3892 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3893 BFD_RELOC_MIPS_HIGHER
);
3894 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3895 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3896 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3897 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3902 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3903 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3905 relax_start (ep
->X_add_symbol
);
3906 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3907 mips_gp_register
, BFD_RELOC_GPREL16
);
3910 macro_build_lui (ep
, reg
);
3911 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3912 reg
, reg
, BFD_RELOC_LO16
);
3913 if (mips_relax
.sequence
)
3917 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3921 /* If this is a reference to an external symbol, we want
3922 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3924 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3926 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3927 If there is a constant, it must be added in after.
3929 If we have NewABI, we want
3930 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3931 unless we're referencing a global symbol with a non-zero
3932 offset, in which case cst must be added separately. */
3935 if (ep
->X_add_number
)
3937 ex
.X_add_number
= ep
->X_add_number
;
3938 ep
->X_add_number
= 0;
3939 relax_start (ep
->X_add_symbol
);
3940 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3941 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3942 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3943 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3944 ex
.X_op
= O_constant
;
3945 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3946 reg
, reg
, BFD_RELOC_LO16
);
3947 ep
->X_add_number
= ex
.X_add_number
;
3950 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3951 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3952 if (mips_relax
.sequence
)
3957 ex
.X_add_number
= ep
->X_add_number
;
3958 ep
->X_add_number
= 0;
3959 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3960 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3962 relax_start (ep
->X_add_symbol
);
3964 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3968 if (ex
.X_add_number
!= 0)
3970 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3971 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3972 ex
.X_op
= O_constant
;
3973 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3974 reg
, reg
, BFD_RELOC_LO16
);
3978 else if (mips_pic
== SVR4_PIC
)
3982 /* This is the large GOT case. If this is a reference to an
3983 external symbol, we want
3984 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3986 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3988 Otherwise, for a reference to a local symbol in old ABI, we want
3989 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3991 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3992 If there is a constant, it must be added in after.
3994 In the NewABI, for local symbols, with or without offsets, we want:
3995 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3996 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4000 ex
.X_add_number
= ep
->X_add_number
;
4001 ep
->X_add_number
= 0;
4002 relax_start (ep
->X_add_symbol
);
4003 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4004 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4005 reg
, reg
, mips_gp_register
);
4006 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4007 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4008 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4009 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4010 else if (ex
.X_add_number
)
4012 ex
.X_op
= O_constant
;
4013 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4017 ep
->X_add_number
= ex
.X_add_number
;
4019 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4020 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4021 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4022 BFD_RELOC_MIPS_GOT_OFST
);
4027 ex
.X_add_number
= ep
->X_add_number
;
4028 ep
->X_add_number
= 0;
4029 relax_start (ep
->X_add_symbol
);
4030 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4032 reg
, reg
, mips_gp_register
);
4033 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4034 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4036 if (reg_needs_delay (mips_gp_register
))
4038 /* We need a nop before loading from $gp. This special
4039 check is required because the lui which starts the main
4040 instruction stream does not refer to $gp, and so will not
4041 insert the nop which may be required. */
4042 macro_build (NULL
, "nop", "");
4044 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4045 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4047 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4051 if (ex
.X_add_number
!= 0)
4053 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4054 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4055 ex
.X_op
= O_constant
;
4056 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4065 /* Move the contents of register SOURCE into register DEST. */
4068 move_register (int dest
, int source
)
4070 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4074 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4075 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4076 The two alternatives are:
4078 Global symbol Local sybmol
4079 ------------- ------------
4080 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4082 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4084 load_got_offset emits the first instruction and add_got_offset
4085 emits the second for a 16-bit offset or add_got_offset_hilo emits
4086 a sequence to add a 32-bit offset using a scratch register. */
4089 load_got_offset (int dest
, expressionS
*local
)
4094 global
.X_add_number
= 0;
4096 relax_start (local
->X_add_symbol
);
4097 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4098 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4100 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4101 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4106 add_got_offset (int dest
, expressionS
*local
)
4110 global
.X_op
= O_constant
;
4111 global
.X_op_symbol
= NULL
;
4112 global
.X_add_symbol
= NULL
;
4113 global
.X_add_number
= local
->X_add_number
;
4115 relax_start (local
->X_add_symbol
);
4116 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4117 dest
, dest
, BFD_RELOC_LO16
);
4119 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4124 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4127 int hold_mips_optimize
;
4129 global
.X_op
= O_constant
;
4130 global
.X_op_symbol
= NULL
;
4131 global
.X_add_symbol
= NULL
;
4132 global
.X_add_number
= local
->X_add_number
;
4134 relax_start (local
->X_add_symbol
);
4135 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4137 /* Set mips_optimize around the lui instruction to avoid
4138 inserting an unnecessary nop after the lw. */
4139 hold_mips_optimize
= mips_optimize
;
4141 macro_build_lui (&global
, tmp
);
4142 mips_optimize
= hold_mips_optimize
;
4143 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4146 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4151 * This routine implements the seemingly endless macro or synthesized
4152 * instructions and addressing modes in the mips assembly language. Many
4153 * of these macros are simple and are similar to each other. These could
4154 * probably be handled by some kind of table or grammar approach instead of
4155 * this verbose method. Others are not simple macros but are more like
4156 * optimizing code generation.
4157 * One interesting optimization is when several store macros appear
4158 * consecutively that would load AT with the upper half of the same address.
4159 * The ensuing load upper instructions are ommited. This implies some kind
4160 * of global optimization. We currently only optimize within a single macro.
4161 * For many of the load and store macros if the address is specified as a
4162 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4163 * first load register 'at' with zero and use it as the base register. The
4164 * mips assembler simply uses register $zero. Just one tiny optimization
4168 macro (struct mips_cl_insn
*ip
)
4170 register int treg
, sreg
, dreg
, breg
;
4186 bfd_reloc_code_real_type r
;
4187 int hold_mips_optimize
;
4189 assert (! mips_opts
.mips16
);
4191 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4192 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4193 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4194 mask
= ip
->insn_mo
->mask
;
4196 expr1
.X_op
= O_constant
;
4197 expr1
.X_op_symbol
= NULL
;
4198 expr1
.X_add_symbol
= NULL
;
4199 expr1
.X_add_number
= 1;
4211 mips_emit_delays (TRUE
);
4212 ++mips_opts
.noreorder
;
4213 mips_any_noreorder
= 1;
4215 expr1
.X_add_number
= 8;
4216 macro_build (&expr1
, "bgez", "s,p", sreg
);
4218 macro_build (NULL
, "nop", "", 0);
4220 move_register (dreg
, sreg
);
4221 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4223 --mips_opts
.noreorder
;
4244 if (imm_expr
.X_op
== O_constant
4245 && imm_expr
.X_add_number
>= -0x8000
4246 && imm_expr
.X_add_number
< 0x8000)
4248 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4251 load_register (AT
, &imm_expr
, dbl
);
4252 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4271 if (imm_expr
.X_op
== O_constant
4272 && imm_expr
.X_add_number
>= 0
4273 && imm_expr
.X_add_number
< 0x10000)
4275 if (mask
!= M_NOR_I
)
4276 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4279 macro_build (&imm_expr
, "ori", "t,r,i",
4280 treg
, sreg
, BFD_RELOC_LO16
);
4281 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4286 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4287 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4304 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4306 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4309 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4310 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4318 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4323 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4326 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4327 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4333 /* check for > max integer */
4334 maxnum
= 0x7fffffff;
4335 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4342 if (imm_expr
.X_op
== O_constant
4343 && imm_expr
.X_add_number
>= maxnum
4344 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4347 /* result is always false */
4349 macro_build (NULL
, "nop", "", 0);
4351 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4354 if (imm_expr
.X_op
!= O_constant
)
4355 as_bad (_("Unsupported large constant"));
4356 ++imm_expr
.X_add_number
;
4360 if (mask
== M_BGEL_I
)
4362 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4364 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4367 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4369 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4372 maxnum
= 0x7fffffff;
4373 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4380 maxnum
= - maxnum
- 1;
4381 if (imm_expr
.X_op
== O_constant
4382 && imm_expr
.X_add_number
<= maxnum
4383 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4386 /* result is always true */
4387 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4388 macro_build (&offset_expr
, "b", "p");
4392 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4402 macro_build (&offset_expr
, likely
? "beql" : "beq",
4406 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4407 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4415 && imm_expr
.X_op
== O_constant
4416 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4418 if (imm_expr
.X_op
!= O_constant
)
4419 as_bad (_("Unsupported large constant"));
4420 ++imm_expr
.X_add_number
;
4424 if (mask
== M_BGEUL_I
)
4426 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4428 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4430 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4435 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4443 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4448 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4451 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4452 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4460 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4466 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4467 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4475 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4480 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4483 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4484 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4490 maxnum
= 0x7fffffff;
4491 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4498 if (imm_expr
.X_op
== O_constant
4499 && imm_expr
.X_add_number
>= maxnum
4500 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4502 if (imm_expr
.X_op
!= O_constant
)
4503 as_bad (_("Unsupported large constant"));
4504 ++imm_expr
.X_add_number
;
4508 if (mask
== M_BLTL_I
)
4510 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4512 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4515 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4517 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4521 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4529 macro_build (&offset_expr
, likely
? "beql" : "beq",
4535 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4536 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4544 && imm_expr
.X_op
== O_constant
4545 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4547 if (imm_expr
.X_op
!= O_constant
)
4548 as_bad (_("Unsupported large constant"));
4549 ++imm_expr
.X_add_number
;
4553 if (mask
== M_BLTUL_I
)
4555 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4557 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4559 macro_build (&offset_expr
, likely
? "beql" : "beq",
4564 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4572 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4577 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4580 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4581 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4591 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4595 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4596 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4604 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4606 as_bad (_("Unsupported large constant"));
4611 pos
= (unsigned long) imm_expr
.X_add_number
;
4612 size
= (unsigned long) imm2_expr
.X_add_number
;
4617 as_bad (_("Improper position (%lu)"), pos
);
4620 if (size
== 0 || size
> 64
4621 || (pos
+ size
- 1) > 63)
4623 as_bad (_("Improper extract size (%lu, position %lu)"),
4628 if (size
<= 32 && pos
< 32)
4633 else if (size
<= 32)
4643 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4652 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4654 as_bad (_("Unsupported large constant"));
4659 pos
= (unsigned long) imm_expr
.X_add_number
;
4660 size
= (unsigned long) imm2_expr
.X_add_number
;
4665 as_bad (_("Improper position (%lu)"), pos
);
4668 if (size
== 0 || size
> 64
4669 || (pos
+ size
- 1) > 63)
4671 as_bad (_("Improper insert size (%lu, position %lu)"),
4676 if (pos
< 32 && (pos
+ size
- 1) < 32)
4691 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4708 as_warn (_("Divide by zero."));
4710 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4712 macro_build (NULL
, "break", "c", 7);
4716 mips_emit_delays (TRUE
);
4717 ++mips_opts
.noreorder
;
4718 mips_any_noreorder
= 1;
4721 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4722 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4726 expr1
.X_add_number
= 8;
4727 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4728 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4729 macro_build (NULL
, "break", "c", 7);
4731 expr1
.X_add_number
= -1;
4732 load_register (AT
, &expr1
, dbl
);
4733 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4734 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4737 expr1
.X_add_number
= 1;
4738 load_register (AT
, &expr1
, dbl
);
4739 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4743 expr1
.X_add_number
= 0x80000000;
4744 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4748 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4749 /* We want to close the noreorder block as soon as possible, so
4750 that later insns are available for delay slot filling. */
4751 --mips_opts
.noreorder
;
4755 expr1
.X_add_number
= 8;
4756 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4757 macro_build (NULL
, "nop", "", 0);
4759 /* We want to close the noreorder block as soon as possible, so
4760 that later insns are available for delay slot filling. */
4761 --mips_opts
.noreorder
;
4763 macro_build (NULL
, "break", "c", 6);
4765 macro_build (NULL
, s
, "d", dreg
);
4804 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4806 as_warn (_("Divide by zero."));
4808 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4810 macro_build (NULL
, "break", "c", 7);
4813 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4815 if (strcmp (s2
, "mflo") == 0)
4816 move_register (dreg
, sreg
);
4818 move_register (dreg
, 0);
4821 if (imm_expr
.X_op
== O_constant
4822 && imm_expr
.X_add_number
== -1
4823 && s
[strlen (s
) - 1] != 'u')
4825 if (strcmp (s2
, "mflo") == 0)
4827 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4830 move_register (dreg
, 0);
4834 load_register (AT
, &imm_expr
, dbl
);
4835 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4836 macro_build (NULL
, s2
, "d", dreg
);
4855 mips_emit_delays (TRUE
);
4856 ++mips_opts
.noreorder
;
4857 mips_any_noreorder
= 1;
4860 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4861 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4862 /* We want to close the noreorder block as soon as possible, so
4863 that later insns are available for delay slot filling. */
4864 --mips_opts
.noreorder
;
4868 expr1
.X_add_number
= 8;
4869 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4870 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4872 /* We want to close the noreorder block as soon as possible, so
4873 that later insns are available for delay slot filling. */
4874 --mips_opts
.noreorder
;
4875 macro_build (NULL
, "break", "c", 7);
4877 macro_build (NULL
, s2
, "d", dreg
);
4889 /* Load the address of a symbol into a register. If breg is not
4890 zero, we then add a base register to it. */
4892 if (dbl
&& HAVE_32BIT_GPRS
)
4893 as_warn (_("dla used to load 32-bit register"));
4895 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4896 as_warn (_("la used to load 64-bit address"));
4898 if (offset_expr
.X_op
== O_constant
4899 && offset_expr
.X_add_number
>= -0x8000
4900 && offset_expr
.X_add_number
< 0x8000)
4902 macro_build (&offset_expr
,
4903 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4904 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4908 if (!mips_opts
.noat
&& (treg
== breg
))
4918 if (offset_expr
.X_op
!= O_symbol
4919 && offset_expr
.X_op
!= O_constant
)
4921 as_bad (_("expression too complex"));
4922 offset_expr
.X_op
= O_constant
;
4925 if (offset_expr
.X_op
== O_constant
)
4926 load_register (tempreg
, &offset_expr
,
4928 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4929 : HAVE_64BIT_ADDRESSES
));
4930 else if (mips_pic
== NO_PIC
)
4932 /* If this is a reference to a GP relative symbol, we want
4933 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4935 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4936 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4937 If we have a constant, we need two instructions anyhow,
4938 so we may as well always use the latter form.
4940 With 64bit address space and a usable $at we want
4941 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4942 lui $at,<sym> (BFD_RELOC_HI16_S)
4943 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4944 daddiu $at,<sym> (BFD_RELOC_LO16)
4946 daddu $tempreg,$tempreg,$at
4948 If $at is already in use, we use a path which is suboptimal
4949 on superscalar processors.
4950 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4951 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4953 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4955 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4957 if (HAVE_64BIT_ADDRESSES
)
4959 /* ??? We don't provide a GP-relative alternative for
4960 these macros. It used not to be possible with the
4961 original relaxation code, but it could be done now. */
4963 if (used_at
== 0 && !mips_opts
.noat
)
4965 macro_build (&offset_expr
, "lui", "t,u",
4966 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4967 macro_build (&offset_expr
, "lui", "t,u",
4968 AT
, BFD_RELOC_HI16_S
);
4969 macro_build (&offset_expr
, "daddiu", "t,r,j",
4970 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4971 macro_build (&offset_expr
, "daddiu", "t,r,j",
4972 AT
, AT
, BFD_RELOC_LO16
);
4973 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4974 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4979 macro_build (&offset_expr
, "lui", "t,u",
4980 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4981 macro_build (&offset_expr
, "daddiu", "t,r,j",
4982 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4983 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4984 macro_build (&offset_expr
, "daddiu", "t,r,j",
4985 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4986 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4987 macro_build (&offset_expr
, "daddiu", "t,r,j",
4988 tempreg
, tempreg
, BFD_RELOC_LO16
);
4993 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4994 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4996 relax_start (offset_expr
.X_add_symbol
);
4997 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4998 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5001 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5002 as_bad (_("offset too large"));
5003 macro_build_lui (&offset_expr
, tempreg
);
5004 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5005 tempreg
, tempreg
, BFD_RELOC_LO16
);
5006 if (mips_relax
.sequence
)
5010 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
5012 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5014 /* If this is a reference to an external symbol, and there
5015 is no constant, we want
5016 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5017 or for lca or if tempreg is PIC_CALL_REG
5018 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5019 For a local symbol, we want
5020 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5022 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5024 If we have a small constant, and this is a reference to
5025 an external symbol, we want
5026 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5028 addiu $tempreg,$tempreg,<constant>
5029 For a local symbol, we want the same instruction
5030 sequence, but we output a BFD_RELOC_LO16 reloc on the
5033 If we have a large constant, and this is a reference to
5034 an external symbol, we want
5035 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5036 lui $at,<hiconstant>
5037 addiu $at,$at,<loconstant>
5038 addu $tempreg,$tempreg,$at
5039 For a local symbol, we want the same instruction
5040 sequence, but we output a BFD_RELOC_LO16 reloc on the
5044 if (offset_expr
.X_add_number
== 0)
5046 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5047 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5049 relax_start (offset_expr
.X_add_symbol
);
5050 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5051 lw_reloc_type
, mips_gp_register
);
5054 /* We're going to put in an addu instruction using
5055 tempreg, so we may as well insert the nop right
5060 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5061 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5063 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5064 tempreg
, tempreg
, BFD_RELOC_LO16
);
5066 /* FIXME: If breg == 0, and the next instruction uses
5067 $tempreg, then if this variant case is used an extra
5068 nop will be generated. */
5070 else if (offset_expr
.X_add_number
>= -0x8000
5071 && offset_expr
.X_add_number
< 0x8000)
5073 load_got_offset (tempreg
, &offset_expr
);
5075 add_got_offset (tempreg
, &offset_expr
);
5079 expr1
.X_add_number
= offset_expr
.X_add_number
;
5080 offset_expr
.X_add_number
=
5081 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5082 load_got_offset (tempreg
, &offset_expr
);
5083 offset_expr
.X_add_number
= expr1
.X_add_number
;
5084 /* If we are going to add in a base register, and the
5085 target register and the base register are the same,
5086 then we are using AT as a temporary register. Since
5087 we want to load the constant into AT, we add our
5088 current AT (from the global offset table) and the
5089 register into the register now, and pretend we were
5090 not using a base register. */
5094 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5099 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5103 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5105 int add_breg_early
= 0;
5107 /* If this is a reference to an external, and there is no
5108 constant, or local symbol (*), with or without a
5110 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5111 or for lca or if tempreg is PIC_CALL_REG
5112 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5114 If we have a small constant, and this is a reference to
5115 an external symbol, we want
5116 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5117 addiu $tempreg,$tempreg,<constant>
5119 If we have a large constant, and this is a reference to
5120 an external symbol, we want
5121 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5122 lui $at,<hiconstant>
5123 addiu $at,$at,<loconstant>
5124 addu $tempreg,$tempreg,$at
5126 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5127 local symbols, even though it introduces an additional
5130 if (offset_expr
.X_add_number
)
5132 expr1
.X_add_number
= offset_expr
.X_add_number
;
5133 offset_expr
.X_add_number
= 0;
5135 relax_start (offset_expr
.X_add_symbol
);
5136 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5137 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5139 if (expr1
.X_add_number
>= -0x8000
5140 && expr1
.X_add_number
< 0x8000)
5142 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5143 tempreg
, tempreg
, BFD_RELOC_LO16
);
5145 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5149 /* If we are going to add in a base register, and the
5150 target register and the base register are the same,
5151 then we are using AT as a temporary register. Since
5152 we want to load the constant into AT, we add our
5153 current AT (from the global offset table) and the
5154 register into the register now, and pretend we were
5155 not using a base register. */
5160 assert (tempreg
== AT
);
5161 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5167 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5168 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5174 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5177 offset_expr
.X_add_number
= expr1
.X_add_number
;
5179 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5180 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5183 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5184 treg
, tempreg
, breg
);
5190 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5192 relax_start (offset_expr
.X_add_symbol
);
5193 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5194 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5196 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5197 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5202 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5203 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5206 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5209 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5210 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5211 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5213 /* This is the large GOT case. If this is a reference to an
5214 external symbol, and there is no constant, we want
5215 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5216 addu $tempreg,$tempreg,$gp
5217 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5218 or for lca or if tempreg is PIC_CALL_REG
5219 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5220 addu $tempreg,$tempreg,$gp
5221 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5222 For a local symbol, we want
5223 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5225 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5227 If we have a small constant, and this is a reference to
5228 an external symbol, we want
5229 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5230 addu $tempreg,$tempreg,$gp
5231 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5233 addiu $tempreg,$tempreg,<constant>
5234 For a local symbol, we want
5235 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5237 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5239 If we have a large constant, and this is a reference to
5240 an external symbol, we want
5241 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5242 addu $tempreg,$tempreg,$gp
5243 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5244 lui $at,<hiconstant>
5245 addiu $at,$at,<loconstant>
5246 addu $tempreg,$tempreg,$at
5247 For a local symbol, we want
5248 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5249 lui $at,<hiconstant>
5250 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5251 addu $tempreg,$tempreg,$at
5254 expr1
.X_add_number
= offset_expr
.X_add_number
;
5255 offset_expr
.X_add_number
= 0;
5256 relax_start (offset_expr
.X_add_symbol
);
5257 gpdelay
= reg_needs_delay (mips_gp_register
);
5258 if (expr1
.X_add_number
== 0 && breg
== 0
5259 && (call
|| tempreg
== PIC_CALL_REG
))
5261 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5262 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5264 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5265 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5266 tempreg
, tempreg
, mips_gp_register
);
5267 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5268 tempreg
, lw_reloc_type
, tempreg
);
5269 if (expr1
.X_add_number
== 0)
5273 /* We're going to put in an addu instruction using
5274 tempreg, so we may as well insert the nop right
5279 else if (expr1
.X_add_number
>= -0x8000
5280 && expr1
.X_add_number
< 0x8000)
5283 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5284 tempreg
, tempreg
, BFD_RELOC_LO16
);
5290 /* If we are going to add in a base register, and the
5291 target register and the base register are the same,
5292 then we are using AT as a temporary register. Since
5293 we want to load the constant into AT, we add our
5294 current AT (from the global offset table) and the
5295 register into the register now, and pretend we were
5296 not using a base register. */
5301 assert (tempreg
== AT
);
5303 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5308 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5309 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5313 offset_expr
.X_add_number
=
5314 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5319 /* This is needed because this instruction uses $gp, but
5320 the first instruction on the main stream does not. */
5321 macro_build (NULL
, "nop", "");
5324 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5325 local_reloc_type
, mips_gp_register
);
5326 if (expr1
.X_add_number
>= -0x8000
5327 && expr1
.X_add_number
< 0x8000)
5330 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5331 tempreg
, tempreg
, BFD_RELOC_LO16
);
5332 /* FIXME: If add_number is 0, and there was no base
5333 register, the external symbol case ended with a load,
5334 so if the symbol turns out to not be external, and
5335 the next instruction uses tempreg, an unnecessary nop
5336 will be inserted. */
5342 /* We must add in the base register now, as in the
5343 external symbol case. */
5344 assert (tempreg
== AT
);
5346 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5349 /* We set breg to 0 because we have arranged to add
5350 it in in both cases. */
5354 macro_build_lui (&expr1
, AT
);
5355 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5356 AT
, AT
, BFD_RELOC_LO16
);
5357 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5358 tempreg
, tempreg
, AT
);
5362 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5364 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5365 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5366 int add_breg_early
= 0;
5368 /* This is the large GOT case. If this is a reference to an
5369 external symbol, and there is no constant, we want
5370 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5371 add $tempreg,$tempreg,$gp
5372 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5373 or for lca or if tempreg is PIC_CALL_REG
5374 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5375 add $tempreg,$tempreg,$gp
5376 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5378 If we have a small constant, and this is a reference to
5379 an external symbol, we want
5380 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5381 add $tempreg,$tempreg,$gp
5382 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5383 addi $tempreg,$tempreg,<constant>
5385 If we have a large constant, and this is a reference to
5386 an external symbol, we want
5387 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5388 addu $tempreg,$tempreg,$gp
5389 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5390 lui $at,<hiconstant>
5391 addi $at,$at,<loconstant>
5392 add $tempreg,$tempreg,$at
5394 If we have NewABI, and we know it's a local symbol, we want
5395 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5396 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5397 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5399 relax_start (offset_expr
.X_add_symbol
);
5401 expr1
.X_add_number
= offset_expr
.X_add_number
;
5402 offset_expr
.X_add_number
= 0;
5404 if (expr1
.X_add_number
== 0 && breg
== 0
5405 && (call
|| tempreg
== PIC_CALL_REG
))
5407 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5408 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5410 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5411 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5412 tempreg
, tempreg
, mips_gp_register
);
5413 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5414 tempreg
, lw_reloc_type
, tempreg
);
5416 if (expr1
.X_add_number
== 0)
5418 else if (expr1
.X_add_number
>= -0x8000
5419 && expr1
.X_add_number
< 0x8000)
5421 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5422 tempreg
, tempreg
, BFD_RELOC_LO16
);
5424 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5428 /* If we are going to add in a base register, and the
5429 target register and the base register are the same,
5430 then we are using AT as a temporary register. Since
5431 we want to load the constant into AT, we add our
5432 current AT (from the global offset table) and the
5433 register into the register now, and pretend we were
5434 not using a base register. */
5439 assert (tempreg
== AT
);
5440 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5446 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5447 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5452 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5455 offset_expr
.X_add_number
= expr1
.X_add_number
;
5456 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5457 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5458 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5459 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5462 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5463 treg
, tempreg
, breg
);
5476 if (mips_pic
== NO_PIC
)
5477 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5479 s
= ADDRESS_ADD_INSN
;
5481 macro_build (NULL
, s
, "d,v,t", treg
, tempreg
, breg
);
5490 /* The j instruction may not be used in PIC code, since it
5491 requires an absolute address. We convert it to a b
5493 if (mips_pic
== NO_PIC
)
5494 macro_build (&offset_expr
, "j", "a");
5496 macro_build (&offset_expr
, "b", "p");
5499 /* The jal instructions must be handled as macros because when
5500 generating PIC code they expand to multi-instruction
5501 sequences. Normally they are simple instructions. */
5506 if (mips_pic
== NO_PIC
)
5507 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5508 else if (mips_pic
== SVR4_PIC
)
5510 if (sreg
!= PIC_CALL_REG
)
5511 as_warn (_("MIPS PIC call to register other than $25"));
5513 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5516 if (mips_cprestore_offset
< 0)
5517 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5520 if (! mips_frame_reg_valid
)
5522 as_warn (_("No .frame pseudo-op used in PIC code"));
5523 /* Quiet this warning. */
5524 mips_frame_reg_valid
= 1;
5526 if (! mips_cprestore_valid
)
5528 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5529 /* Quiet this warning. */
5530 mips_cprestore_valid
= 1;
5532 expr1
.X_add_number
= mips_cprestore_offset
;
5533 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5536 HAVE_64BIT_ADDRESSES
);
5546 if (mips_pic
== NO_PIC
)
5547 macro_build (&offset_expr
, "jal", "a");
5548 else if (mips_pic
== SVR4_PIC
)
5550 /* If this is a reference to an external symbol, and we are
5551 using a small GOT, we want
5552 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5556 lw $gp,cprestore($sp)
5557 The cprestore value is set using the .cprestore
5558 pseudo-op. If we are using a big GOT, we want
5559 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5561 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5565 lw $gp,cprestore($sp)
5566 If the symbol is not external, we want
5567 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5569 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5572 lw $gp,cprestore($sp)
5574 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5575 sequences above, minus nops, unless the symbol is local,
5576 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5582 relax_start (offset_expr
.X_add_symbol
);
5583 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5584 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5587 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5588 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5594 relax_start (offset_expr
.X_add_symbol
);
5595 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5596 BFD_RELOC_MIPS_CALL_HI16
);
5597 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5598 PIC_CALL_REG
, mips_gp_register
);
5599 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5600 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5603 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5604 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5606 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5607 PIC_CALL_REG
, PIC_CALL_REG
,
5608 BFD_RELOC_MIPS_GOT_OFST
);
5612 macro_build_jalr (&offset_expr
);
5616 relax_start (offset_expr
.X_add_symbol
);
5619 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5620 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5629 gpdelay
= reg_needs_delay (mips_gp_register
);
5630 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5631 BFD_RELOC_MIPS_CALL_HI16
);
5632 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5633 PIC_CALL_REG
, mips_gp_register
);
5634 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5635 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5640 macro_build (NULL
, "nop", "");
5642 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5643 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5646 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5647 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5649 macro_build_jalr (&offset_expr
);
5651 if (mips_cprestore_offset
< 0)
5652 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5655 if (! mips_frame_reg_valid
)
5657 as_warn (_("No .frame pseudo-op used in PIC code"));
5658 /* Quiet this warning. */
5659 mips_frame_reg_valid
= 1;
5661 if (! mips_cprestore_valid
)
5663 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5664 /* Quiet this warning. */
5665 mips_cprestore_valid
= 1;
5667 if (mips_opts
.noreorder
)
5668 macro_build (NULL
, "nop", "");
5669 expr1
.X_add_number
= mips_cprestore_offset
;
5670 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5673 HAVE_64BIT_ADDRESSES
);
5699 /* Itbl support may require additional care here. */
5704 /* Itbl support may require additional care here. */
5709 /* Itbl support may require additional care here. */
5714 /* Itbl support may require additional care here. */
5726 if (mips_opts
.arch
== CPU_R4650
)
5728 as_bad (_("opcode not supported on this processor"));
5732 /* Itbl support may require additional care here. */
5737 /* Itbl support may require additional care here. */
5742 /* Itbl support may require additional care here. */
5762 /* XXX Why don't we try to use AT for all expansions? */
5763 if (!mips_opts
.noat
&& (breg
== treg
|| coproc
|| lr
))
5768 else if (breg
== treg
5769 && (offset_expr
.X_op
!= O_constant
5770 || (offset_expr
.X_add_number
> 0x7fff
5771 || offset_expr
.X_add_number
< -0x8000)))
5773 as_bad(_("load expansion needs $at register"));
5792 /* Itbl support may require additional care here. */
5797 /* Itbl support may require additional care here. */
5802 /* Itbl support may require additional care here. */
5807 /* Itbl support may require additional care here. */
5823 if (mips_opts
.arch
== CPU_R4650
)
5825 as_bad (_("opcode not supported on this processor"));
5830 /* Itbl support may require additional care here. */
5834 /* Itbl support may require additional care here. */
5839 /* Itbl support may require additional care here. */
5848 if (!mips_opts
.noat
)
5853 else if (breg
== treg
5854 && (offset_expr
.X_op
!= O_constant
5855 || (offset_expr
.X_add_number
> 0x7fff
5856 || offset_expr
.X_add_number
< -0x8000)))
5858 as_bad(_("store expansion needs $at register"));
5866 /* Itbl support may require additional care here. */
5867 if (mask
== M_LWC1_AB
5868 || mask
== M_SWC1_AB
5869 || mask
== M_LDC1_AB
5870 || mask
== M_SDC1_AB
5879 /* Sign-extending 32-bit constants makes their handling easier.
5880 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5882 if ((! HAVE_64BIT_ADDRESSES
5883 && (! HAVE_64BIT_GPRS
&& offset_expr
.X_op
== O_constant
))
5884 && (offset_expr
.X_op
== O_constant
)
5885 && ! ((offset_expr
.X_add_number
& ~((bfd_vma
) 0x7fffffff))
5886 == ~((bfd_vma
) 0x7fffffff)))
5888 if (offset_expr
.X_add_number
& ~((bfd_vma
) 0xffffffff))
5889 as_bad (_("constant too large"));
5891 offset_expr
.X_add_number
= (((offset_expr
.X_add_number
& 0xffffffff)
5892 ^ 0x80000000) - 0x80000000);
5895 if (offset_expr
.X_op
!= O_constant
5896 && offset_expr
.X_op
!= O_symbol
)
5898 as_bad (_("expression too complex"));
5899 offset_expr
.X_op
= O_constant
;
5902 /* A constant expression in PIC code can be handled just as it
5903 is in non PIC code. */
5904 if (mips_pic
== NO_PIC
5905 || offset_expr
.X_op
== O_constant
)
5907 /* If this is a reference to a GP relative symbol, and there
5908 is no base register, we want
5909 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5910 Otherwise, if there is no base register, we want
5911 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5912 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5913 If we have a constant, we need two instructions anyhow,
5914 so we always use the latter form.
5916 If we have a base register, and this is a reference to a
5917 GP relative symbol, we want
5918 addu $tempreg,$breg,$gp
5919 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5921 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5922 addu $tempreg,$tempreg,$breg
5923 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5924 With a constant we always use the latter case.
5926 With 64bit address space and no base register and $at usable,
5928 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5929 lui $at,<sym> (BFD_RELOC_HI16_S)
5930 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5933 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5934 If we have a base register, we want
5935 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5936 lui $at,<sym> (BFD_RELOC_HI16_S)
5937 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5941 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5943 Without $at we can't generate the optimal path for superscalar
5944 processors here since this would require two temporary registers.
5945 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5946 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5948 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5950 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5951 If we have a base register, we want
5952 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5953 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5955 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5957 daddu $tempreg,$tempreg,$breg
5958 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5960 If we have 64-bit addresses, as an optimization, for
5961 addresses which are 32-bit constants (e.g. kseg0/kseg1
5962 addresses) we fall back to the 32-bit address generation
5963 mechanism since it is more efficient. Note that due to
5964 the signed offset used by memory operations, the 32-bit
5965 range is shifted down by 32768 here. This code should
5966 probably attempt to generate 64-bit constants more
5967 efficiently in general.
5969 As an extension for architectures with 64-bit registers,
5970 we don't truncate 64-bit addresses given as literal
5971 constants down to 32 bits, to support existing practice
5972 in the mips64 Linux (the kernel), that compiles source
5973 files with -mabi=64, assembling them as o32 or n32 (with
5974 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5975 the whole kernel is loaded into a memory region that is
5976 addressable with sign-extended 32-bit addresses, it is
5977 wasteful to compute the upper 32 bits of every
5978 non-literal address, that takes more space and time.
5979 Some day this should probably be implemented as an
5980 assembler option, such that the kernel doesn't have to
5981 use such ugly hacks, even though it will still have to
5982 end up converting the binary to ELF32 for a number of
5983 platforms whose boot loaders don't support ELF64
5985 if ((HAVE_64BIT_ADDRESSES
5986 && ! (offset_expr
.X_op
== O_constant
5987 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5989 && offset_expr
.X_op
== O_constant
5990 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5992 /* ??? We don't provide a GP-relative alternative for
5993 these macros. It used not to be possible with the
5994 original relaxation code, but it could be done now. */
5996 if (used_at
== 0 && !mips_opts
.noat
)
5998 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5999 BFD_RELOC_MIPS_HIGHEST
);
6000 macro_build (&offset_expr
, "lui", "t,u", AT
,
6002 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6003 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6005 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6006 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6007 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6008 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6014 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6015 BFD_RELOC_MIPS_HIGHEST
);
6016 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6017 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6018 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6019 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6020 tempreg
, BFD_RELOC_HI16_S
);
6021 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6023 macro_build (NULL
, "daddu", "d,v,t",
6024 tempreg
, tempreg
, breg
);
6025 macro_build (&offset_expr
, s
, fmt
, treg
,
6026 BFD_RELOC_LO16
, tempreg
);
6035 if (offset_expr
.X_op
== O_constant
6036 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000))
6037 as_bad (_("load/store address overflow (max 32 bits)"));
6041 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6042 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6044 relax_start (offset_expr
.X_add_symbol
);
6045 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6049 macro_build_lui (&offset_expr
, tempreg
);
6050 macro_build (&offset_expr
, s
, fmt
, treg
,
6051 BFD_RELOC_LO16
, tempreg
);
6052 if (mips_relax
.sequence
)
6057 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6058 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6060 relax_start (offset_expr
.X_add_symbol
);
6061 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6062 tempreg
, breg
, mips_gp_register
);
6063 macro_build (&offset_expr
, s
, fmt
, treg
,
6064 BFD_RELOC_GPREL16
, tempreg
);
6067 macro_build_lui (&offset_expr
, tempreg
);
6068 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6069 tempreg
, tempreg
, breg
);
6070 macro_build (&offset_expr
, s
, fmt
, treg
,
6071 BFD_RELOC_LO16
, tempreg
);
6072 if (mips_relax
.sequence
)
6076 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6078 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6080 /* If this is a reference to an external symbol, we want
6081 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6083 <op> $treg,0($tempreg)
6085 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6087 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6088 <op> $treg,0($tempreg)
6091 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6092 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6094 If there is a base register, we add it to $tempreg before
6095 the <op>. If there is a constant, we stick it in the
6096 <op> instruction. We don't handle constants larger than
6097 16 bits, because we have no way to load the upper 16 bits
6098 (actually, we could handle them for the subset of cases
6099 in which we are not using $at). */
6100 assert (offset_expr
.X_op
== O_symbol
);
6103 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6104 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6106 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6107 tempreg
, tempreg
, breg
);
6108 macro_build (&offset_expr
, s
, fmt
, treg
,
6109 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6116 expr1
.X_add_number
= offset_expr
.X_add_number
;
6117 offset_expr
.X_add_number
= 0;
6118 if (expr1
.X_add_number
< -0x8000
6119 || expr1
.X_add_number
>= 0x8000)
6120 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6121 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6122 lw_reloc_type
, mips_gp_register
);
6124 relax_start (offset_expr
.X_add_symbol
);
6126 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6127 tempreg
, BFD_RELOC_LO16
);
6130 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6131 tempreg
, tempreg
, breg
);
6132 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6134 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6138 /* If this is a reference to an external symbol, we want
6139 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6140 addu $tempreg,$tempreg,$gp
6141 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6142 <op> $treg,0($tempreg)
6144 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6146 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6147 <op> $treg,0($tempreg)
6148 If there is a base register, we add it to $tempreg before
6149 the <op>. If there is a constant, we stick it in the
6150 <op> instruction. We don't handle constants larger than
6151 16 bits, because we have no way to load the upper 16 bits
6152 (actually, we could handle them for the subset of cases
6153 in which we are not using $at). */
6154 assert (offset_expr
.X_op
== O_symbol
);
6155 expr1
.X_add_number
= offset_expr
.X_add_number
;
6156 offset_expr
.X_add_number
= 0;
6157 if (expr1
.X_add_number
< -0x8000
6158 || expr1
.X_add_number
>= 0x8000)
6159 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6160 gpdelay
= reg_needs_delay (mips_gp_register
);
6161 relax_start (offset_expr
.X_add_symbol
);
6162 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6163 BFD_RELOC_MIPS_GOT_HI16
);
6164 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6166 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6167 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6170 macro_build (NULL
, "nop", "");
6171 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6172 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6174 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6175 tempreg
, BFD_RELOC_LO16
);
6179 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6180 tempreg
, tempreg
, breg
);
6181 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6183 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6185 /* If this is a reference to an external symbol, we want
6186 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6187 add $tempreg,$tempreg,$gp
6188 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6189 <op> $treg,<ofst>($tempreg)
6190 Otherwise, for local symbols, we want:
6191 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6192 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6193 assert (offset_expr
.X_op
== O_symbol
);
6194 expr1
.X_add_number
= offset_expr
.X_add_number
;
6195 offset_expr
.X_add_number
= 0;
6196 if (expr1
.X_add_number
< -0x8000
6197 || expr1
.X_add_number
>= 0x8000)
6198 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6199 relax_start (offset_expr
.X_add_symbol
);
6200 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6201 BFD_RELOC_MIPS_GOT_HI16
);
6202 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6204 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6205 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6207 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6208 tempreg
, tempreg
, breg
);
6209 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6212 offset_expr
.X_add_number
= expr1
.X_add_number
;
6213 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6214 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6216 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6217 tempreg
, tempreg
, breg
);
6218 macro_build (&offset_expr
, s
, fmt
, treg
,
6219 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6232 load_register (treg
, &imm_expr
, 0);
6236 load_register (treg
, &imm_expr
, 1);
6240 if (imm_expr
.X_op
== O_constant
)
6242 load_register (AT
, &imm_expr
, 0);
6243 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6248 assert (offset_expr
.X_op
== O_symbol
6249 && strcmp (segment_name (S_GET_SEGMENT
6250 (offset_expr
.X_add_symbol
)),
6252 && offset_expr
.X_add_number
== 0);
6253 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6254 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6259 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6260 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6261 order 32 bits of the value and the low order 32 bits are either
6262 zero or in OFFSET_EXPR. */
6263 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6265 if (HAVE_64BIT_GPRS
)
6266 load_register (treg
, &imm_expr
, 1);
6271 if (target_big_endian
)
6283 load_register (hreg
, &imm_expr
, 0);
6286 if (offset_expr
.X_op
== O_absent
)
6287 move_register (lreg
, 0);
6290 assert (offset_expr
.X_op
== O_constant
);
6291 load_register (lreg
, &offset_expr
, 0);
6298 /* We know that sym is in the .rdata section. First we get the
6299 upper 16 bits of the address. */
6300 if (mips_pic
== NO_PIC
)
6302 macro_build_lui (&offset_expr
, AT
);
6304 else if (mips_pic
== SVR4_PIC
)
6306 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6307 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6312 /* Now we load the register(s). */
6313 if (HAVE_64BIT_GPRS
)
6314 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6317 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6320 /* FIXME: How in the world do we deal with the possible
6322 offset_expr
.X_add_number
+= 4;
6323 macro_build (&offset_expr
, "lw", "t,o(b)",
6324 treg
+ 1, BFD_RELOC_LO16
, AT
);
6330 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6331 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6332 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6333 the value and the low order 32 bits are either zero or in
6335 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6337 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6338 if (HAVE_64BIT_FPRS
)
6340 assert (HAVE_64BIT_GPRS
);
6341 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6345 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6346 if (offset_expr
.X_op
== O_absent
)
6347 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6350 assert (offset_expr
.X_op
== O_constant
);
6351 load_register (AT
, &offset_expr
, 0);
6352 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6358 assert (offset_expr
.X_op
== O_symbol
6359 && offset_expr
.X_add_number
== 0);
6360 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6361 if (strcmp (s
, ".lit8") == 0)
6363 if (mips_opts
.isa
!= ISA_MIPS1
)
6365 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6366 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6369 breg
= mips_gp_register
;
6370 r
= BFD_RELOC_MIPS_LITERAL
;
6375 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6376 if (mips_pic
== SVR4_PIC
)
6377 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6378 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6381 /* FIXME: This won't work for a 64 bit address. */
6382 macro_build_lui (&offset_expr
, AT
);
6385 if (mips_opts
.isa
!= ISA_MIPS1
)
6387 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6388 treg
, BFD_RELOC_LO16
, AT
);
6397 if (mips_opts
.arch
== CPU_R4650
)
6399 as_bad (_("opcode not supported on this processor"));
6402 /* Even on a big endian machine $fn comes before $fn+1. We have
6403 to adjust when loading from memory. */
6406 assert (mips_opts
.isa
== ISA_MIPS1
);
6407 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6408 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6409 /* FIXME: A possible overflow which I don't know how to deal
6411 offset_expr
.X_add_number
+= 4;
6412 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6413 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6421 * The MIPS assembler seems to check for X_add_number not
6422 * being double aligned and generating:
6425 * addiu at,at,%lo(foo+1)
6428 * But, the resulting address is the same after relocation so why
6429 * generate the extra instruction?
6431 if (mips_opts
.arch
== CPU_R4650
)
6433 as_bad (_("opcode not supported on this processor"));
6436 /* Itbl support may require additional care here. */
6438 if (mips_opts
.isa
!= ISA_MIPS1
)
6449 if (mips_opts
.arch
== CPU_R4650
)
6451 as_bad (_("opcode not supported on this processor"));
6455 if (mips_opts
.isa
!= ISA_MIPS1
)
6463 /* Itbl support may require additional care here. */
6468 if (HAVE_64BIT_GPRS
)
6479 if (HAVE_64BIT_GPRS
)
6489 if (offset_expr
.X_op
!= O_symbol
6490 && offset_expr
.X_op
!= O_constant
)
6492 as_bad (_("expression too complex"));
6493 offset_expr
.X_op
= O_constant
;
6496 /* Even on a big endian machine $fn comes before $fn+1. We have
6497 to adjust when loading from memory. We set coproc if we must
6498 load $fn+1 first. */
6499 /* Itbl support may require additional care here. */
6500 if (! target_big_endian
)
6503 if (mips_pic
== NO_PIC
6504 || offset_expr
.X_op
== O_constant
)
6506 /* If this is a reference to a GP relative symbol, we want
6507 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6508 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6509 If we have a base register, we use this
6511 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6512 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6513 If this is not a GP relative symbol, we want
6514 lui $at,<sym> (BFD_RELOC_HI16_S)
6515 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6516 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6517 If there is a base register, we add it to $at after the
6518 lui instruction. If there is a constant, we always use
6520 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6521 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6525 relax_start (offset_expr
.X_add_symbol
);
6528 tempreg
= mips_gp_register
;
6532 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6533 AT
, breg
, mips_gp_register
);
6538 /* Itbl support may require additional care here. */
6539 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6540 BFD_RELOC_GPREL16
, tempreg
);
6541 offset_expr
.X_add_number
+= 4;
6543 /* Set mips_optimize to 2 to avoid inserting an
6545 hold_mips_optimize
= mips_optimize
;
6547 /* Itbl support may require additional care here. */
6548 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6549 BFD_RELOC_GPREL16
, tempreg
);
6550 mips_optimize
= hold_mips_optimize
;
6554 /* We just generated two relocs. When tc_gen_reloc
6555 handles this case, it will skip the first reloc and
6556 handle the second. The second reloc already has an
6557 extra addend of 4, which we added above. We must
6558 subtract it out, and then subtract another 4 to make
6559 the first reloc come out right. The second reloc
6560 will come out right because we are going to add 4 to
6561 offset_expr when we build its instruction below.
6563 If we have a symbol, then we don't want to include
6564 the offset, because it will wind up being included
6565 when we generate the reloc. */
6567 if (offset_expr
.X_op
== O_constant
)
6568 offset_expr
.X_add_number
-= 8;
6571 offset_expr
.X_add_number
= -4;
6572 offset_expr
.X_op
= O_constant
;
6575 macro_build_lui (&offset_expr
, AT
);
6577 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6578 /* Itbl support may require additional care here. */
6579 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6580 BFD_RELOC_LO16
, AT
);
6581 /* FIXME: How do we handle overflow here? */
6582 offset_expr
.X_add_number
+= 4;
6583 /* Itbl support may require additional care here. */
6584 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6585 BFD_RELOC_LO16
, AT
);
6586 if (mips_relax
.sequence
)
6589 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6591 /* If this is a reference to an external symbol, we want
6592 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6597 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6599 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6600 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6601 If there is a base register we add it to $at before the
6602 lwc1 instructions. If there is a constant we include it
6603 in the lwc1 instructions. */
6605 expr1
.X_add_number
= offset_expr
.X_add_number
;
6606 if (expr1
.X_add_number
< -0x8000
6607 || expr1
.X_add_number
>= 0x8000 - 4)
6608 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6609 load_got_offset (AT
, &offset_expr
);
6612 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6614 /* Set mips_optimize to 2 to avoid inserting an undesired
6616 hold_mips_optimize
= mips_optimize
;
6619 /* Itbl support may require additional care here. */
6620 relax_start (offset_expr
.X_add_symbol
);
6621 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6622 BFD_RELOC_LO16
, AT
);
6623 expr1
.X_add_number
+= 4;
6624 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6625 BFD_RELOC_LO16
, AT
);
6627 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6628 BFD_RELOC_LO16
, AT
);
6629 offset_expr
.X_add_number
+= 4;
6630 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6631 BFD_RELOC_LO16
, AT
);
6634 mips_optimize
= hold_mips_optimize
;
6636 else if (mips_pic
== SVR4_PIC
)
6640 /* If this is a reference to an external symbol, we want
6641 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6643 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6648 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6650 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6651 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6652 If there is a base register we add it to $at before the
6653 lwc1 instructions. If there is a constant we include it
6654 in the lwc1 instructions. */
6656 expr1
.X_add_number
= offset_expr
.X_add_number
;
6657 offset_expr
.X_add_number
= 0;
6658 if (expr1
.X_add_number
< -0x8000
6659 || expr1
.X_add_number
>= 0x8000 - 4)
6660 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6661 gpdelay
= reg_needs_delay (mips_gp_register
);
6662 relax_start (offset_expr
.X_add_symbol
);
6663 macro_build (&offset_expr
, "lui", "t,u",
6664 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6665 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6666 AT
, AT
, mips_gp_register
);
6667 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6668 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6671 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6672 /* Itbl support may require additional care here. */
6673 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6674 BFD_RELOC_LO16
, AT
);
6675 expr1
.X_add_number
+= 4;
6677 /* Set mips_optimize to 2 to avoid inserting an undesired
6679 hold_mips_optimize
= mips_optimize
;
6681 /* Itbl support may require additional care here. */
6682 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6683 BFD_RELOC_LO16
, AT
);
6684 mips_optimize
= hold_mips_optimize
;
6685 expr1
.X_add_number
-= 4;
6688 offset_expr
.X_add_number
= expr1
.X_add_number
;
6690 macro_build (NULL
, "nop", "");
6691 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6692 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6695 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6696 /* Itbl support may require additional care here. */
6697 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6698 BFD_RELOC_LO16
, AT
);
6699 offset_expr
.X_add_number
+= 4;
6701 /* Set mips_optimize to 2 to avoid inserting an undesired
6703 hold_mips_optimize
= mips_optimize
;
6705 /* Itbl support may require additional care here. */
6706 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6707 BFD_RELOC_LO16
, AT
);
6708 mips_optimize
= hold_mips_optimize
;
6725 assert (HAVE_32BIT_ADDRESSES
);
6726 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6727 offset_expr
.X_add_number
+= 4;
6728 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6731 /* New code added to support COPZ instructions.
6732 This code builds table entries out of the macros in mip_opcodes.
6733 R4000 uses interlocks to handle coproc delays.
6734 Other chips (like the R3000) require nops to be inserted for delays.
6736 FIXME: Currently, we require that the user handle delays.
6737 In order to fill delay slots for non-interlocked chips,
6738 we must have a way to specify delays based on the coprocessor.
6739 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6740 What are the side-effects of the cop instruction?
6741 What cache support might we have and what are its effects?
6742 Both coprocessor & memory require delays. how long???
6743 What registers are read/set/modified?
6745 If an itbl is provided to interpret cop instructions,
6746 this knowledge can be encoded in the itbl spec. */
6760 /* For now we just do C (same as Cz). The parameter will be
6761 stored in insn_opcode by mips_ip. */
6762 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6766 move_register (dreg
, sreg
);
6769 #ifdef LOSING_COMPILER
6771 /* Try and see if this is a new itbl instruction.
6772 This code builds table entries out of the macros in mip_opcodes.
6773 FIXME: For now we just assemble the expression and pass it's
6774 value along as a 32-bit immediate.
6775 We may want to have the assembler assemble this value,
6776 so that we gain the assembler's knowledge of delay slots,
6778 Would it be more efficient to use mask (id) here? */
6779 if (itbl_have_entries
6780 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6782 s
= ip
->insn_mo
->name
;
6784 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6785 macro_build (&immed_expr
, s
, "C");
6792 as_warn (_("Macro used $at after \".set noat\""));
6796 macro2 (struct mips_cl_insn
*ip
)
6798 register int treg
, sreg
, dreg
, breg
;
6813 bfd_reloc_code_real_type r
;
6815 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6816 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6817 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6818 mask
= ip
->insn_mo
->mask
;
6820 expr1
.X_op
= O_constant
;
6821 expr1
.X_op_symbol
= NULL
;
6822 expr1
.X_add_symbol
= NULL
;
6823 expr1
.X_add_number
= 1;
6827 #endif /* LOSING_COMPILER */
6832 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6833 macro_build (NULL
, "mflo", "d", dreg
);
6839 /* The MIPS assembler some times generates shifts and adds. I'm
6840 not trying to be that fancy. GCC should do this for us
6842 load_register (AT
, &imm_expr
, dbl
);
6843 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6844 macro_build (NULL
, "mflo", "d", dreg
);
6857 mips_emit_delays (TRUE
);
6858 ++mips_opts
.noreorder
;
6859 mips_any_noreorder
= 1;
6861 load_register (AT
, &imm_expr
, dbl
);
6862 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6863 macro_build (NULL
, "mflo", "d", dreg
);
6864 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6865 macro_build (NULL
, "mfhi", "d", AT
);
6867 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6870 expr1
.X_add_number
= 8;
6871 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6872 macro_build (NULL
, "nop", "", 0);
6873 macro_build (NULL
, "break", "c", 6);
6875 --mips_opts
.noreorder
;
6876 macro_build (NULL
, "mflo", "d", dreg
);
6889 mips_emit_delays (TRUE
);
6890 ++mips_opts
.noreorder
;
6891 mips_any_noreorder
= 1;
6893 load_register (AT
, &imm_expr
, dbl
);
6894 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6895 sreg
, imm
? AT
: treg
);
6896 macro_build (NULL
, "mfhi", "d", AT
);
6897 macro_build (NULL
, "mflo", "d", dreg
);
6899 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6902 expr1
.X_add_number
= 8;
6903 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6904 macro_build (NULL
, "nop", "", 0);
6905 macro_build (NULL
, "break", "c", 6);
6907 --mips_opts
.noreorder
;
6911 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6922 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6923 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6928 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6929 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6930 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6931 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6935 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6946 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6947 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6952 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6953 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6954 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6955 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6963 if (imm_expr
.X_op
!= O_constant
)
6964 as_bad (_("Improper rotate count"));
6965 rot
= imm_expr
.X_add_number
& 0x3f;
6966 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6968 rot
= (64 - rot
) & 0x3f;
6970 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6972 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6977 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6980 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6981 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6983 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6984 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6985 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6993 if (imm_expr
.X_op
!= O_constant
)
6994 as_bad (_("Improper rotate count"));
6995 rot
= imm_expr
.X_add_number
& 0x1f;
6996 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6998 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7003 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7006 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7007 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7008 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7013 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7015 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7018 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7019 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7020 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7021 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7025 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7027 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7030 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7031 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7032 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7033 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7041 if (imm_expr
.X_op
!= O_constant
)
7042 as_bad (_("Improper rotate count"));
7043 rot
= imm_expr
.X_add_number
& 0x3f;
7044 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7047 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7049 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7054 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7057 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7058 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7060 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7061 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7062 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7070 if (imm_expr
.X_op
!= O_constant
)
7071 as_bad (_("Improper rotate count"));
7072 rot
= imm_expr
.X_add_number
& 0x1f;
7073 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7075 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7080 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7083 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7084 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7085 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7090 if (mips_opts
.arch
== CPU_R4650
)
7092 as_bad (_("opcode not supported on this processor"));
7095 assert (mips_opts
.isa
== ISA_MIPS1
);
7096 /* Even on a big endian machine $fn comes before $fn+1. We have
7097 to adjust when storing to memory. */
7098 macro_build (&offset_expr
, "swc1", "T,o(b)",
7099 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7100 offset_expr
.X_add_number
+= 4;
7101 macro_build (&offset_expr
, "swc1", "T,o(b)",
7102 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7107 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7109 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7112 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7113 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7118 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7120 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7125 as_warn (_("Instruction %s: result is always false"),
7127 move_register (dreg
, 0);
7130 if (imm_expr
.X_op
== O_constant
7131 && imm_expr
.X_add_number
>= 0
7132 && imm_expr
.X_add_number
< 0x10000)
7134 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7136 else if (imm_expr
.X_op
== O_constant
7137 && imm_expr
.X_add_number
> -0x8000
7138 && imm_expr
.X_add_number
< 0)
7140 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7141 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7142 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7146 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7147 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7150 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7155 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7161 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7162 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7165 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7167 if (imm_expr
.X_op
== O_constant
7168 && imm_expr
.X_add_number
>= -0x8000
7169 && imm_expr
.X_add_number
< 0x8000)
7171 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7172 dreg
, sreg
, BFD_RELOC_LO16
);
7176 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7177 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7181 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7186 case M_SGT
: /* sreg > treg <==> treg < sreg */
7192 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7195 case M_SGT_I
: /* sreg > I <==> I < sreg */
7201 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7202 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7205 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7211 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7212 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7215 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7221 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7222 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7223 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7227 if (imm_expr
.X_op
== O_constant
7228 && imm_expr
.X_add_number
>= -0x8000
7229 && imm_expr
.X_add_number
< 0x8000)
7231 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7234 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7235 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7239 if (imm_expr
.X_op
== O_constant
7240 && imm_expr
.X_add_number
>= -0x8000
7241 && imm_expr
.X_add_number
< 0x8000)
7243 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7247 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7248 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7253 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7255 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7258 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7259 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7264 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7266 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7271 as_warn (_("Instruction %s: result is always true"),
7273 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7274 dreg
, 0, BFD_RELOC_LO16
);
7277 if (imm_expr
.X_op
== O_constant
7278 && imm_expr
.X_add_number
>= 0
7279 && imm_expr
.X_add_number
< 0x10000)
7281 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7283 else if (imm_expr
.X_op
== O_constant
7284 && imm_expr
.X_add_number
> -0x8000
7285 && imm_expr
.X_add_number
< 0)
7287 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7288 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7289 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7293 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7294 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7297 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7305 if (imm_expr
.X_op
== O_constant
7306 && imm_expr
.X_add_number
> -0x8000
7307 && imm_expr
.X_add_number
<= 0x8000)
7309 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7310 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7311 dreg
, sreg
, BFD_RELOC_LO16
);
7314 load_register (AT
, &imm_expr
, dbl
);
7315 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7321 if (imm_expr
.X_op
== O_constant
7322 && imm_expr
.X_add_number
> -0x8000
7323 && imm_expr
.X_add_number
<= 0x8000)
7325 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7326 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7327 dreg
, sreg
, BFD_RELOC_LO16
);
7330 load_register (AT
, &imm_expr
, dbl
);
7331 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7352 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7353 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7358 assert (mips_opts
.isa
== ISA_MIPS1
);
7359 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7360 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7363 * Is the double cfc1 instruction a bug in the mips assembler;
7364 * or is there a reason for it?
7366 mips_emit_delays (TRUE
);
7367 ++mips_opts
.noreorder
;
7368 mips_any_noreorder
= 1;
7369 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7370 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7371 macro_build (NULL
, "nop", "");
7372 expr1
.X_add_number
= 3;
7373 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7374 expr1
.X_add_number
= 2;
7375 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7376 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7377 macro_build (NULL
, "nop", "");
7378 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7380 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7381 macro_build (NULL
, "nop", "");
7382 --mips_opts
.noreorder
;
7391 if (offset_expr
.X_add_number
>= 0x7fff)
7392 as_bad (_("operand overflow"));
7393 if (! target_big_endian
)
7394 ++offset_expr
.X_add_number
;
7395 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7396 if (! target_big_endian
)
7397 --offset_expr
.X_add_number
;
7399 ++offset_expr
.X_add_number
;
7400 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7401 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7402 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7415 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7416 as_bad (_("operand overflow"));
7421 if (! target_big_endian
)
7422 offset_expr
.X_add_number
+= off
;
7423 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7424 if (! target_big_endian
)
7425 offset_expr
.X_add_number
-= off
;
7427 offset_expr
.X_add_number
+= off
;
7428 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7430 /* If necessary, move the result in tempreg the final destination. */
7431 if (treg
== tempreg
)
7433 /* Protect second load's delay slot. */
7435 move_register (treg
, tempreg
);
7449 load_address (AT
, &offset_expr
, &used_at
);
7451 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7452 if (! target_big_endian
)
7453 expr1
.X_add_number
= off
;
7455 expr1
.X_add_number
= 0;
7456 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7457 if (! target_big_endian
)
7458 expr1
.X_add_number
= 0;
7460 expr1
.X_add_number
= off
;
7461 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7467 load_address (AT
, &offset_expr
, &used_at
);
7469 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7470 if (target_big_endian
)
7471 expr1
.X_add_number
= 0;
7472 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7473 treg
, BFD_RELOC_LO16
, AT
);
7474 if (target_big_endian
)
7475 expr1
.X_add_number
= 1;
7477 expr1
.X_add_number
= 0;
7478 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7479 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7480 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7484 if (offset_expr
.X_add_number
>= 0x7fff)
7485 as_bad (_("operand overflow"));
7486 if (target_big_endian
)
7487 ++offset_expr
.X_add_number
;
7488 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7489 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7490 if (target_big_endian
)
7491 --offset_expr
.X_add_number
;
7493 ++offset_expr
.X_add_number
;
7494 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7507 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7508 as_bad (_("operand overflow"));
7509 if (! target_big_endian
)
7510 offset_expr
.X_add_number
+= off
;
7511 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7512 if (! target_big_endian
)
7513 offset_expr
.X_add_number
-= off
;
7515 offset_expr
.X_add_number
+= off
;
7516 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7530 load_address (AT
, &offset_expr
, &used_at
);
7532 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7533 if (! target_big_endian
)
7534 expr1
.X_add_number
= off
;
7536 expr1
.X_add_number
= 0;
7537 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7538 if (! target_big_endian
)
7539 expr1
.X_add_number
= 0;
7541 expr1
.X_add_number
= off
;
7542 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7547 load_address (AT
, &offset_expr
, &used_at
);
7549 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7550 if (! target_big_endian
)
7551 expr1
.X_add_number
= 0;
7552 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7553 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7554 if (! target_big_endian
)
7555 expr1
.X_add_number
= 1;
7557 expr1
.X_add_number
= 0;
7558 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7559 if (! target_big_endian
)
7560 expr1
.X_add_number
= 0;
7562 expr1
.X_add_number
= 1;
7563 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7564 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7565 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7569 /* FIXME: Check if this is one of the itbl macros, since they
7570 are added dynamically. */
7571 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7575 as_warn (_("Macro used $at after \".set noat\""));
7578 /* Implement macros in mips16 mode. */
7581 mips16_macro (struct mips_cl_insn
*ip
)
7584 int xreg
, yreg
, zreg
, tmp
;
7587 const char *s
, *s2
, *s3
;
7589 mask
= ip
->insn_mo
->mask
;
7591 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7592 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7593 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7595 expr1
.X_op
= O_constant
;
7596 expr1
.X_op_symbol
= NULL
;
7597 expr1
.X_add_symbol
= NULL
;
7598 expr1
.X_add_number
= 1;
7617 mips_emit_delays (TRUE
);
7618 ++mips_opts
.noreorder
;
7619 mips_any_noreorder
= 1;
7620 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7621 expr1
.X_add_number
= 2;
7622 macro_build (&expr1
, "bnez", "x,p", yreg
);
7623 macro_build (NULL
, "break", "6", 7);
7625 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7626 since that causes an overflow. We should do that as well,
7627 but I don't see how to do the comparisons without a temporary
7629 --mips_opts
.noreorder
;
7630 macro_build (NULL
, s
, "x", zreg
);
7649 mips_emit_delays (TRUE
);
7650 ++mips_opts
.noreorder
;
7651 mips_any_noreorder
= 1;
7652 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7653 expr1
.X_add_number
= 2;
7654 macro_build (&expr1
, "bnez", "x,p", yreg
);
7655 macro_build (NULL
, "break", "6", 7);
7656 --mips_opts
.noreorder
;
7657 macro_build (NULL
, s2
, "x", zreg
);
7663 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7664 macro_build (NULL
, "mflo", "x", zreg
);
7672 if (imm_expr
.X_op
!= O_constant
)
7673 as_bad (_("Unsupported large constant"));
7674 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7675 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7679 if (imm_expr
.X_op
!= O_constant
)
7680 as_bad (_("Unsupported large constant"));
7681 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7682 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7686 if (imm_expr
.X_op
!= O_constant
)
7687 as_bad (_("Unsupported large constant"));
7688 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7689 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7711 goto do_reverse_branch
;
7715 goto do_reverse_branch
;
7727 goto do_reverse_branch
;
7738 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7739 macro_build (&offset_expr
, s2
, "p");
7766 goto do_addone_branch_i
;
7771 goto do_addone_branch_i
;
7786 goto do_addone_branch_i
;
7793 if (imm_expr
.X_op
!= O_constant
)
7794 as_bad (_("Unsupported large constant"));
7795 ++imm_expr
.X_add_number
;
7798 macro_build (&imm_expr
, s
, s3
, xreg
);
7799 macro_build (&offset_expr
, s2
, "p");
7803 expr1
.X_add_number
= 0;
7804 macro_build (&expr1
, "slti", "x,8", yreg
);
7806 move_register (xreg
, yreg
);
7807 expr1
.X_add_number
= 2;
7808 macro_build (&expr1
, "bteqz", "p");
7809 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7813 /* For consistency checking, verify that all bits are specified either
7814 by the match/mask part of the instruction definition, or by the
7817 validate_mips_insn (const struct mips_opcode
*opc
)
7819 const char *p
= opc
->args
;
7821 unsigned long used_bits
= opc
->mask
;
7823 if ((used_bits
& opc
->match
) != opc
->match
)
7825 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7826 opc
->name
, opc
->args
);
7829 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7839 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7840 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7841 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7842 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7843 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7844 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7845 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7846 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7847 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7850 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7851 c
, opc
->name
, opc
->args
);
7855 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7856 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7858 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7859 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7860 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7861 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7863 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7864 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7866 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7867 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7869 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7870 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7871 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7872 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7873 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7874 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7875 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7876 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7877 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7878 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7879 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7880 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7881 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7882 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7883 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7884 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7885 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7887 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7888 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7889 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7890 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7892 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7893 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7894 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7895 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7896 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7897 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7898 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7899 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7900 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7903 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7904 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7905 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7906 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7907 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7911 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7912 c
, opc
->name
, opc
->args
);
7916 if (used_bits
!= 0xffffffff)
7918 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7919 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7925 /* This routine assembles an instruction into its binary format. As a
7926 side effect, it sets one of the global variables imm_reloc or
7927 offset_reloc to the type of relocation to do if one of the operands
7928 is an address expression. */
7931 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7936 struct mips_opcode
*insn
;
7939 unsigned int lastregno
= 0;
7940 unsigned int lastpos
= 0;
7941 unsigned int limlo
, limhi
;
7947 /* If the instruction contains a '.', we first try to match an instruction
7948 including the '.'. Then we try again without the '.'. */
7950 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7953 /* If we stopped on whitespace, then replace the whitespace with null for
7954 the call to hash_find. Save the character we replaced just in case we
7955 have to re-parse the instruction. */
7962 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7964 /* If we didn't find the instruction in the opcode table, try again, but
7965 this time with just the instruction up to, but not including the
7969 /* Restore the character we overwrite above (if any). */
7973 /* Scan up to the first '.' or whitespace. */
7975 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7979 /* If we did not find a '.', then we can quit now. */
7982 insn_error
= "unrecognized opcode";
7986 /* Lookup the instruction in the hash table. */
7988 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7990 insn_error
= "unrecognized opcode";
8000 assert (strcmp (insn
->name
, str
) == 0);
8002 if (OPCODE_IS_MEMBER (insn
,
8004 | (file_ase_mips16
? INSN_MIPS16
: 0)
8005 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8006 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8012 if (insn
->pinfo
!= INSN_MACRO
)
8014 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8020 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8021 && strcmp (insn
->name
, insn
[1].name
) == 0)
8030 static char buf
[100];
8032 _("opcode not supported on this processor: %s (%s)"),
8033 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8034 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8044 ip
->insn_opcode
= insn
->match
;
8046 for (args
= insn
->args
;; ++args
)
8050 s
+= strspn (s
, " \t");
8054 case '\0': /* end of args */
8067 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8071 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8075 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8079 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8085 /* Handle optional base register.
8086 Either the base register is omitted or
8087 we must have a left paren. */
8088 /* This is dependent on the next operand specifier
8089 is a base register specification. */
8090 assert (args
[1] == 'b' || args
[1] == '5'
8091 || args
[1] == '-' || args
[1] == '4');
8095 case ')': /* these must match exactly */
8102 case '+': /* Opcode extension character. */
8105 case 'A': /* ins/ext position, becomes LSB. */
8114 my_getExpression (&imm_expr
, s
);
8115 check_absolute_expr (ip
, &imm_expr
);
8116 if ((unsigned long) imm_expr
.X_add_number
< limlo
8117 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8119 as_bad (_("Improper position (%lu)"),
8120 (unsigned long) imm_expr
.X_add_number
);
8121 imm_expr
.X_add_number
= limlo
;
8123 lastpos
= imm_expr
.X_add_number
;
8124 ip
->insn_opcode
|= (imm_expr
.X_add_number
8125 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8126 imm_expr
.X_op
= O_absent
;
8130 case 'B': /* ins size, becomes MSB. */
8139 my_getExpression (&imm_expr
, s
);
8140 check_absolute_expr (ip
, &imm_expr
);
8141 /* Check for negative input so that small negative numbers
8142 will not succeed incorrectly. The checks against
8143 (pos+size) transitively check "size" itself,
8144 assuming that "pos" is reasonable. */
8145 if ((long) imm_expr
.X_add_number
< 0
8146 || ((unsigned long) imm_expr
.X_add_number
8148 || ((unsigned long) imm_expr
.X_add_number
8151 as_bad (_("Improper insert size (%lu, position %lu)"),
8152 (unsigned long) imm_expr
.X_add_number
,
8153 (unsigned long) lastpos
);
8154 imm_expr
.X_add_number
= limlo
- lastpos
;
8156 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8157 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8158 imm_expr
.X_op
= O_absent
;
8162 case 'C': /* ext size, becomes MSBD. */
8175 my_getExpression (&imm_expr
, s
);
8176 check_absolute_expr (ip
, &imm_expr
);
8177 /* Check for negative input so that small negative numbers
8178 will not succeed incorrectly. The checks against
8179 (pos+size) transitively check "size" itself,
8180 assuming that "pos" is reasonable. */
8181 if ((long) imm_expr
.X_add_number
< 0
8182 || ((unsigned long) imm_expr
.X_add_number
8184 || ((unsigned long) imm_expr
.X_add_number
8187 as_bad (_("Improper extract size (%lu, position %lu)"),
8188 (unsigned long) imm_expr
.X_add_number
,
8189 (unsigned long) lastpos
);
8190 imm_expr
.X_add_number
= limlo
- lastpos
;
8192 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8193 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8194 imm_expr
.X_op
= O_absent
;
8199 /* +D is for disassembly only; never match. */
8203 /* "+I" is like "I", except that imm2_expr is used. */
8204 my_getExpression (&imm2_expr
, s
);
8205 if (imm2_expr
.X_op
!= O_big
8206 && imm2_expr
.X_op
!= O_constant
)
8207 insn_error
= _("absolute expression required");
8208 normalize_constant_expr (&imm2_expr
);
8213 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8214 *args
, insn
->name
, insn
->args
);
8215 /* Further processing is fruitless. */
8220 case '<': /* must be at least one digit */
8222 * According to the manual, if the shift amount is greater
8223 * than 31 or less than 0, then the shift amount should be
8224 * mod 32. In reality the mips assembler issues an error.
8225 * We issue a warning and mask out all but the low 5 bits.
8227 my_getExpression (&imm_expr
, s
);
8228 check_absolute_expr (ip
, &imm_expr
);
8229 if ((unsigned long) imm_expr
.X_add_number
> 31)
8231 as_warn (_("Improper shift amount (%lu)"),
8232 (unsigned long) imm_expr
.X_add_number
);
8233 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8235 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8236 imm_expr
.X_op
= O_absent
;
8240 case '>': /* shift amount minus 32 */
8241 my_getExpression (&imm_expr
, s
);
8242 check_absolute_expr (ip
, &imm_expr
);
8243 if ((unsigned long) imm_expr
.X_add_number
< 32
8244 || (unsigned long) imm_expr
.X_add_number
> 63)
8246 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8247 imm_expr
.X_op
= O_absent
;
8251 case 'k': /* cache code */
8252 case 'h': /* prefx code */
8253 my_getExpression (&imm_expr
, s
);
8254 check_absolute_expr (ip
, &imm_expr
);
8255 if ((unsigned long) imm_expr
.X_add_number
> 31)
8257 as_warn (_("Invalid value for `%s' (%lu)"),
8259 (unsigned long) imm_expr
.X_add_number
);
8260 imm_expr
.X_add_number
&= 0x1f;
8263 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8265 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8266 imm_expr
.X_op
= O_absent
;
8270 case 'c': /* break code */
8271 my_getExpression (&imm_expr
, s
);
8272 check_absolute_expr (ip
, &imm_expr
);
8273 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8275 as_warn (_("Illegal break code (%lu)"),
8276 (unsigned long) imm_expr
.X_add_number
);
8277 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8279 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8280 imm_expr
.X_op
= O_absent
;
8284 case 'q': /* lower break code */
8285 my_getExpression (&imm_expr
, s
);
8286 check_absolute_expr (ip
, &imm_expr
);
8287 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8289 as_warn (_("Illegal lower break code (%lu)"),
8290 (unsigned long) imm_expr
.X_add_number
);
8291 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8293 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8294 imm_expr
.X_op
= O_absent
;
8298 case 'B': /* 20-bit syscall/break code. */
8299 my_getExpression (&imm_expr
, s
);
8300 check_absolute_expr (ip
, &imm_expr
);
8301 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8302 as_warn (_("Illegal 20-bit code (%lu)"),
8303 (unsigned long) imm_expr
.X_add_number
);
8304 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8305 imm_expr
.X_op
= O_absent
;
8309 case 'C': /* Coprocessor code */
8310 my_getExpression (&imm_expr
, s
);
8311 check_absolute_expr (ip
, &imm_expr
);
8312 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8314 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8315 (unsigned long) imm_expr
.X_add_number
);
8316 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8318 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8319 imm_expr
.X_op
= O_absent
;
8323 case 'J': /* 19-bit wait code. */
8324 my_getExpression (&imm_expr
, s
);
8325 check_absolute_expr (ip
, &imm_expr
);
8326 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8327 as_warn (_("Illegal 19-bit code (%lu)"),
8328 (unsigned long) imm_expr
.X_add_number
);
8329 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8330 imm_expr
.X_op
= O_absent
;
8334 case 'P': /* Performance register */
8335 my_getExpression (&imm_expr
, s
);
8336 check_absolute_expr (ip
, &imm_expr
);
8337 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8339 as_warn (_("Invalid performance register (%lu)"),
8340 (unsigned long) imm_expr
.X_add_number
);
8341 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8343 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8344 imm_expr
.X_op
= O_absent
;
8348 case 'b': /* base register */
8349 case 'd': /* destination register */
8350 case 's': /* source register */
8351 case 't': /* target register */
8352 case 'r': /* both target and source */
8353 case 'v': /* both dest and source */
8354 case 'w': /* both dest and target */
8355 case 'E': /* coprocessor target register */
8356 case 'G': /* coprocessor destination register */
8357 case 'K': /* 'rdhwr' destination register */
8358 case 'x': /* ignore register name */
8359 case 'z': /* must be zero register */
8360 case 'U': /* destination register (clo/clz). */
8375 while (ISDIGIT (*s
));
8377 as_bad (_("Invalid register number (%d)"), regno
);
8379 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8383 if (s
[1] == 'r' && s
[2] == 'a')
8388 else if (s
[1] == 'f' && s
[2] == 'p')
8393 else if (s
[1] == 's' && s
[2] == 'p')
8398 else if (s
[1] == 'g' && s
[2] == 'p')
8403 else if (s
[1] == 'a' && s
[2] == 't')
8408 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8413 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8418 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8423 else if (itbl_have_entries
)
8428 p
= s
+ 1; /* advance past '$' */
8429 n
= itbl_get_field (&p
); /* n is name */
8431 /* See if this is a register defined in an
8433 if (itbl_get_reg_val (n
, &r
))
8435 /* Get_field advances to the start of
8436 the next field, so we need to back
8437 rack to the end of the last field. */
8441 s
= strchr (s
, '\0');
8455 as_warn (_("Used $at without \".set noat\""));
8461 if (c
== 'r' || c
== 'v' || c
== 'w')
8468 /* 'z' only matches $0. */
8469 if (c
== 'z' && regno
!= 0)
8472 /* Now that we have assembled one operand, we use the args string
8473 * to figure out where it goes in the instruction. */
8480 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8485 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8488 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8489 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8494 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8497 /* This case exists because on the r3000 trunc
8498 expands into a macro which requires a gp
8499 register. On the r6000 or r4000 it is
8500 assembled into a single instruction which
8501 ignores the register. Thus the insn version
8502 is MIPS_ISA2 and uses 'x', and the macro
8503 version is MIPS_ISA1 and uses 't'. */
8506 /* This case is for the div instruction, which
8507 acts differently if the destination argument
8508 is $0. This only matches $0, and is checked
8509 outside the switch. */
8512 /* Itbl operand; not yet implemented. FIXME ?? */
8514 /* What about all other operands like 'i', which
8515 can be specified in the opcode table? */
8525 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8528 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8533 case 'O': /* MDMX alignment immediate constant. */
8534 my_getExpression (&imm_expr
, s
);
8535 check_absolute_expr (ip
, &imm_expr
);
8536 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8538 as_warn ("Improper align amount (%ld), using low bits",
8539 (long) imm_expr
.X_add_number
);
8540 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8542 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8543 imm_expr
.X_op
= O_absent
;
8547 case 'Q': /* MDMX vector, element sel, or const. */
8550 /* MDMX Immediate. */
8551 my_getExpression (&imm_expr
, s
);
8552 check_absolute_expr (ip
, &imm_expr
);
8553 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8555 as_warn (_("Invalid MDMX Immediate (%ld)"),
8556 (long) imm_expr
.X_add_number
);
8557 imm_expr
.X_add_number
&= OP_MASK_FT
;
8559 imm_expr
.X_add_number
&= OP_MASK_FT
;
8560 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8561 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8563 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8564 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8565 imm_expr
.X_op
= O_absent
;
8569 /* Not MDMX Immediate. Fall through. */
8570 case 'X': /* MDMX destination register. */
8571 case 'Y': /* MDMX source register. */
8572 case 'Z': /* MDMX target register. */
8574 case 'D': /* floating point destination register */
8575 case 'S': /* floating point source register */
8576 case 'T': /* floating point target register */
8577 case 'R': /* floating point source register */
8581 /* Accept $fN for FP and MDMX register numbers, and in
8582 addition accept $vN for MDMX register numbers. */
8583 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8584 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8595 while (ISDIGIT (*s
));
8598 as_bad (_("Invalid float register number (%d)"), regno
);
8600 if ((regno
& 1) != 0
8602 && ! (strcmp (str
, "mtc1") == 0
8603 || strcmp (str
, "mfc1") == 0
8604 || strcmp (str
, "lwc1") == 0
8605 || strcmp (str
, "swc1") == 0
8606 || strcmp (str
, "l.s") == 0
8607 || strcmp (str
, "s.s") == 0))
8608 as_warn (_("Float register should be even, was %d"),
8616 if (c
== 'V' || c
== 'W')
8627 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8632 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8635 /* This is like 'Z', but also needs to fix the MDMX
8636 vector/scalar select bits. Note that the
8637 scalar immediate case is handled above. */
8640 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8641 int max_el
= (is_qh
? 3 : 7);
8643 my_getExpression(&imm_expr
, s
);
8644 check_absolute_expr (ip
, &imm_expr
);
8646 if (imm_expr
.X_add_number
> max_el
)
8647 as_bad(_("Bad element selector %ld"),
8648 (long) imm_expr
.X_add_number
);
8649 imm_expr
.X_add_number
&= max_el
;
8650 ip
->insn_opcode
|= (imm_expr
.X_add_number
8653 imm_expr
.X_op
= O_absent
;
8655 as_warn(_("Expecting ']' found '%s'"), s
);
8661 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8662 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8665 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8672 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8675 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8685 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8688 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8694 my_getExpression (&imm_expr
, s
);
8695 if (imm_expr
.X_op
!= O_big
8696 && imm_expr
.X_op
!= O_constant
)
8697 insn_error
= _("absolute expression required");
8698 normalize_constant_expr (&imm_expr
);
8703 my_getExpression (&offset_expr
, s
);
8704 *imm_reloc
= BFD_RELOC_32
;
8717 unsigned char temp
[8];
8719 unsigned int length
;
8724 /* These only appear as the last operand in an
8725 instruction, and every instruction that accepts
8726 them in any variant accepts them in all variants.
8727 This means we don't have to worry about backing out
8728 any changes if the instruction does not match.
8730 The difference between them is the size of the
8731 floating point constant and where it goes. For 'F'
8732 and 'L' the constant is 64 bits; for 'f' and 'l' it
8733 is 32 bits. Where the constant is placed is based
8734 on how the MIPS assembler does things:
8737 f -- immediate value
8740 The .lit4 and .lit8 sections are only used if
8741 permitted by the -G argument.
8743 The code below needs to know whether the target register
8744 is 32 or 64 bits wide. It relies on the fact 'f' and
8745 'F' are used with GPR-based instructions and 'l' and
8746 'L' are used with FPR-based instructions. */
8748 f64
= *args
== 'F' || *args
== 'L';
8749 using_gprs
= *args
== 'F' || *args
== 'f';
8751 save_in
= input_line_pointer
;
8752 input_line_pointer
= s
;
8753 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8755 s
= input_line_pointer
;
8756 input_line_pointer
= save_in
;
8757 if (err
!= NULL
&& *err
!= '\0')
8759 as_bad (_("Bad floating point constant: %s"), err
);
8760 memset (temp
, '\0', sizeof temp
);
8761 length
= f64
? 8 : 4;
8764 assert (length
== (unsigned) (f64
? 8 : 4));
8768 && (g_switch_value
< 4
8769 || (temp
[0] == 0 && temp
[1] == 0)
8770 || (temp
[2] == 0 && temp
[3] == 0))))
8772 imm_expr
.X_op
= O_constant
;
8773 if (! target_big_endian
)
8774 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8776 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8779 && ! mips_disable_float_construction
8780 /* Constants can only be constructed in GPRs and
8781 copied to FPRs if the GPRs are at least as wide
8782 as the FPRs. Force the constant into memory if
8783 we are using 64-bit FPRs but the GPRs are only
8786 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8787 && ((temp
[0] == 0 && temp
[1] == 0)
8788 || (temp
[2] == 0 && temp
[3] == 0))
8789 && ((temp
[4] == 0 && temp
[5] == 0)
8790 || (temp
[6] == 0 && temp
[7] == 0)))
8792 /* The value is simple enough to load with a couple of
8793 instructions. If using 32-bit registers, set
8794 imm_expr to the high order 32 bits and offset_expr to
8795 the low order 32 bits. Otherwise, set imm_expr to
8796 the entire 64 bit constant. */
8797 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8799 imm_expr
.X_op
= O_constant
;
8800 offset_expr
.X_op
= O_constant
;
8801 if (! target_big_endian
)
8803 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8804 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8808 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8809 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8811 if (offset_expr
.X_add_number
== 0)
8812 offset_expr
.X_op
= O_absent
;
8814 else if (sizeof (imm_expr
.X_add_number
) > 4)
8816 imm_expr
.X_op
= O_constant
;
8817 if (! target_big_endian
)
8818 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8820 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8824 imm_expr
.X_op
= O_big
;
8825 imm_expr
.X_add_number
= 4;
8826 if (! target_big_endian
)
8828 generic_bignum
[0] = bfd_getl16 (temp
);
8829 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8830 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8831 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8835 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8836 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8837 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8838 generic_bignum
[3] = bfd_getb16 (temp
);
8844 const char *newname
;
8847 /* Switch to the right section. */
8849 subseg
= now_subseg
;
8852 default: /* unused default case avoids warnings. */
8854 newname
= RDATA_SECTION_NAME
;
8855 if (g_switch_value
>= 8)
8859 newname
= RDATA_SECTION_NAME
;
8862 assert (g_switch_value
>= 4);
8866 new_seg
= subseg_new (newname
, (subsegT
) 0);
8867 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8868 bfd_set_section_flags (stdoutput
, new_seg
,
8873 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8874 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8875 && strcmp (TARGET_OS
, "elf") != 0)
8876 record_alignment (new_seg
, 4);
8878 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8880 as_bad (_("Can't use floating point insn in this section"));
8882 /* Set the argument to the current address in the
8884 offset_expr
.X_op
= O_symbol
;
8885 offset_expr
.X_add_symbol
=
8886 symbol_new ("L0\001", now_seg
,
8887 (valueT
) frag_now_fix (), frag_now
);
8888 offset_expr
.X_add_number
= 0;
8890 /* Put the floating point number into the section. */
8891 p
= frag_more ((int) length
);
8892 memcpy (p
, temp
, length
);
8894 /* Switch back to the original section. */
8895 subseg_set (seg
, subseg
);
8900 case 'i': /* 16 bit unsigned immediate */
8901 case 'j': /* 16 bit signed immediate */
8902 *imm_reloc
= BFD_RELOC_LO16
;
8903 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8906 offsetT minval
, maxval
;
8908 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8909 && strcmp (insn
->name
, insn
[1].name
) == 0);
8911 /* If the expression was written as an unsigned number,
8912 only treat it as signed if there are no more
8916 && sizeof (imm_expr
.X_add_number
) <= 4
8917 && imm_expr
.X_op
== O_constant
8918 && imm_expr
.X_add_number
< 0
8919 && imm_expr
.X_unsigned
8923 /* For compatibility with older assemblers, we accept
8924 0x8000-0xffff as signed 16-bit numbers when only
8925 signed numbers are allowed. */
8927 minval
= 0, maxval
= 0xffff;
8929 minval
= -0x8000, maxval
= 0x7fff;
8931 minval
= -0x8000, maxval
= 0xffff;
8933 if (imm_expr
.X_op
!= O_constant
8934 || imm_expr
.X_add_number
< minval
8935 || imm_expr
.X_add_number
> maxval
)
8939 if (imm_expr
.X_op
== O_constant
8940 || imm_expr
.X_op
== O_big
)
8941 as_bad (_("expression out of range"));
8947 case 'o': /* 16 bit offset */
8948 /* Check whether there is only a single bracketed expression
8949 left. If so, it must be the base register and the
8950 constant must be zero. */
8951 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8953 offset_expr
.X_op
= O_constant
;
8954 offset_expr
.X_add_number
= 0;
8958 /* If this value won't fit into a 16 bit offset, then go
8959 find a macro that will generate the 32 bit offset
8961 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8962 && (offset_expr
.X_op
!= O_constant
8963 || offset_expr
.X_add_number
>= 0x8000
8964 || offset_expr
.X_add_number
< -0x8000))
8970 case 'p': /* pc relative offset */
8971 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8972 my_getExpression (&offset_expr
, s
);
8976 case 'u': /* upper 16 bits */
8977 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8978 && imm_expr
.X_op
== O_constant
8979 && (imm_expr
.X_add_number
< 0
8980 || imm_expr
.X_add_number
>= 0x10000))
8981 as_bad (_("lui expression not in range 0..65535"));
8985 case 'a': /* 26 bit address */
8986 my_getExpression (&offset_expr
, s
);
8988 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8991 case 'N': /* 3 bit branch condition code */
8992 case 'M': /* 3 bit compare condition code */
8993 if (strncmp (s
, "$fcc", 4) != 0)
9003 while (ISDIGIT (*s
));
9005 as_bad (_("Invalid condition code register $fcc%d"), regno
);
9006 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9007 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9008 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9009 && (regno
& 1) != 0)
9010 as_warn(_("Condition code register should be even for %s, was %d"),
9012 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9013 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9014 && (regno
& 3) != 0)
9015 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9018 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9020 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9024 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9035 while (ISDIGIT (*s
));
9038 c
= 8; /* Invalid sel value. */
9041 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9042 ip
->insn_opcode
|= c
;
9046 /* Must be at least one digit. */
9047 my_getExpression (&imm_expr
, s
);
9048 check_absolute_expr (ip
, &imm_expr
);
9050 if ((unsigned long) imm_expr
.X_add_number
9051 > (unsigned long) OP_MASK_VECBYTE
)
9053 as_bad (_("bad byte vector index (%ld)"),
9054 (long) imm_expr
.X_add_number
);
9055 imm_expr
.X_add_number
= 0;
9058 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9059 imm_expr
.X_op
= O_absent
;
9064 my_getExpression (&imm_expr
, s
);
9065 check_absolute_expr (ip
, &imm_expr
);
9067 if ((unsigned long) imm_expr
.X_add_number
9068 > (unsigned long) OP_MASK_VECALIGN
)
9070 as_bad (_("bad byte vector index (%ld)"),
9071 (long) imm_expr
.X_add_number
);
9072 imm_expr
.X_add_number
= 0;
9075 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9076 imm_expr
.X_op
= O_absent
;
9081 as_bad (_("bad char = '%c'\n"), *args
);
9086 /* Args don't match. */
9087 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9088 !strcmp (insn
->name
, insn
[1].name
))
9092 insn_error
= _("illegal operands");
9097 insn_error
= _("illegal operands");
9102 /* This routine assembles an instruction into its binary format when
9103 assembling for the mips16. As a side effect, it sets one of the
9104 global variables imm_reloc or offset_reloc to the type of
9105 relocation to do if one of the operands is an address expression.
9106 It also sets mips16_small and mips16_ext if the user explicitly
9107 requested a small or extended instruction. */
9110 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9114 struct mips_opcode
*insn
;
9117 unsigned int lastregno
= 0;
9123 mips16_small
= FALSE
;
9126 for (s
= str
; ISLOWER (*s
); ++s
)
9138 if (s
[1] == 't' && s
[2] == ' ')
9141 mips16_small
= TRUE
;
9145 else if (s
[1] == 'e' && s
[2] == ' ')
9154 insn_error
= _("unknown opcode");
9158 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9159 mips16_small
= TRUE
;
9161 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9163 insn_error
= _("unrecognized opcode");
9170 assert (strcmp (insn
->name
, str
) == 0);
9173 ip
->insn_opcode
= insn
->match
;
9174 ip
->use_extend
= FALSE
;
9175 imm_expr
.X_op
= O_absent
;
9176 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9177 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9178 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9179 imm2_expr
.X_op
= O_absent
;
9180 offset_expr
.X_op
= O_absent
;
9181 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9182 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9183 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9184 for (args
= insn
->args
; 1; ++args
)
9191 /* In this switch statement we call break if we did not find
9192 a match, continue if we did find a match, or return if we
9201 /* Stuff the immediate value in now, if we can. */
9202 if (imm_expr
.X_op
== O_constant
9203 && *imm_reloc
> BFD_RELOC_UNUSED
9204 && insn
->pinfo
!= INSN_MACRO
)
9208 switch (*offset_reloc
)
9210 case BFD_RELOC_MIPS16_HI16_S
:
9211 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9214 case BFD_RELOC_MIPS16_HI16
:
9215 tmp
= imm_expr
.X_add_number
>> 16;
9218 case BFD_RELOC_MIPS16_LO16
:
9219 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9223 case BFD_RELOC_UNUSED
:
9224 tmp
= imm_expr
.X_add_number
;
9230 *offset_reloc
= BFD_RELOC_UNUSED
;
9232 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9233 tmp
, TRUE
, mips16_small
,
9234 mips16_ext
, &ip
->insn_opcode
,
9235 &ip
->use_extend
, &ip
->extend
);
9236 imm_expr
.X_op
= O_absent
;
9237 *imm_reloc
= BFD_RELOC_UNUSED
;
9251 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9254 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9270 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9272 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9299 while (ISDIGIT (*s
));
9302 as_bad (_("invalid register number (%d)"), regno
);
9308 if (s
[1] == 'r' && s
[2] == 'a')
9313 else if (s
[1] == 'f' && s
[2] == 'p')
9318 else if (s
[1] == 's' && s
[2] == 'p')
9323 else if (s
[1] == 'g' && s
[2] == 'p')
9328 else if (s
[1] == 'a' && s
[2] == 't')
9333 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9338 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9343 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9356 if (c
== 'v' || c
== 'w')
9358 regno
= mips16_to_32_reg_map
[lastregno
];
9372 regno
= mips32_to_16_reg_map
[regno
];
9377 regno
= ILLEGAL_REG
;
9382 regno
= ILLEGAL_REG
;
9387 regno
= ILLEGAL_REG
;
9392 if (regno
== AT
&& ! mips_opts
.noat
)
9393 as_warn (_("used $at without \".set noat\""));
9400 if (regno
== ILLEGAL_REG
)
9407 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9411 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9414 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9417 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9423 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9426 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9427 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9437 if (strncmp (s
, "$pc", 3) == 0)
9454 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9457 if (imm_expr
.X_op
!= O_constant
)
9460 ip
->use_extend
= TRUE
;
9465 /* We need to relax this instruction. */
9466 *offset_reloc
= *imm_reloc
;
9467 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9472 *imm_reloc
= BFD_RELOC_UNUSED
;
9480 my_getExpression (&imm_expr
, s
);
9481 if (imm_expr
.X_op
== O_register
)
9483 /* What we thought was an expression turned out to
9486 if (s
[0] == '(' && args
[1] == '(')
9488 /* It looks like the expression was omitted
9489 before a register indirection, which means
9490 that the expression is implicitly zero. We
9491 still set up imm_expr, so that we handle
9492 explicit extensions correctly. */
9493 imm_expr
.X_op
= O_constant
;
9494 imm_expr
.X_add_number
= 0;
9495 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9502 /* We need to relax this instruction. */
9503 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9512 /* We use offset_reloc rather than imm_reloc for the PC
9513 relative operands. This lets macros with both
9514 immediate and address operands work correctly. */
9515 my_getExpression (&offset_expr
, s
);
9517 if (offset_expr
.X_op
== O_register
)
9520 /* We need to relax this instruction. */
9521 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9525 case '6': /* break code */
9526 my_getExpression (&imm_expr
, s
);
9527 check_absolute_expr (ip
, &imm_expr
);
9528 if ((unsigned long) imm_expr
.X_add_number
> 63)
9530 as_warn (_("Invalid value for `%s' (%lu)"),
9532 (unsigned long) imm_expr
.X_add_number
);
9533 imm_expr
.X_add_number
&= 0x3f;
9535 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9536 imm_expr
.X_op
= O_absent
;
9540 case 'a': /* 26 bit address */
9541 my_getExpression (&offset_expr
, s
);
9543 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9544 ip
->insn_opcode
<<= 16;
9547 case 'l': /* register list for entry macro */
9548 case 'L': /* register list for exit macro */
9558 int freg
, reg1
, reg2
;
9560 while (*s
== ' ' || *s
== ',')
9564 as_bad (_("can't parse register list"));
9576 while (ISDIGIT (*s
))
9598 as_bad (_("invalid register list"));
9603 while (ISDIGIT (*s
))
9610 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9615 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9620 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9621 mask
|= (reg2
- 3) << 3;
9622 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9623 mask
|= (reg2
- 15) << 1;
9624 else if (reg1
== RA
&& reg2
== RA
)
9628 as_bad (_("invalid register list"));
9632 /* The mask is filled in in the opcode table for the
9633 benefit of the disassembler. We remove it before
9634 applying the actual mask. */
9635 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9636 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9640 case 'e': /* extend code */
9641 my_getExpression (&imm_expr
, s
);
9642 check_absolute_expr (ip
, &imm_expr
);
9643 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9645 as_warn (_("Invalid value for `%s' (%lu)"),
9647 (unsigned long) imm_expr
.X_add_number
);
9648 imm_expr
.X_add_number
&= 0x7ff;
9650 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9651 imm_expr
.X_op
= O_absent
;
9661 /* Args don't match. */
9662 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9663 strcmp (insn
->name
, insn
[1].name
) == 0)
9670 insn_error
= _("illegal operands");
9676 /* This structure holds information we know about a mips16 immediate
9679 struct mips16_immed_operand
9681 /* The type code used in the argument string in the opcode table. */
9683 /* The number of bits in the short form of the opcode. */
9685 /* The number of bits in the extended form of the opcode. */
9687 /* The amount by which the short form is shifted when it is used;
9688 for example, the sw instruction has a shift count of 2. */
9690 /* The amount by which the short form is shifted when it is stored
9691 into the instruction code. */
9693 /* Non-zero if the short form is unsigned. */
9695 /* Non-zero if the extended form is unsigned. */
9697 /* Non-zero if the value is PC relative. */
9701 /* The mips16 immediate operand types. */
9703 static const struct mips16_immed_operand mips16_immed_operands
[] =
9705 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9706 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9707 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9708 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9709 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9710 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9711 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9712 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9713 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9714 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9715 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9716 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9717 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9718 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9719 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9720 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9721 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9722 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9723 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9724 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9725 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9728 #define MIPS16_NUM_IMMED \
9729 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9731 /* Handle a mips16 instruction with an immediate value. This or's the
9732 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9733 whether an extended value is needed; if one is needed, it sets
9734 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9735 If SMALL is true, an unextended opcode was explicitly requested.
9736 If EXT is true, an extended opcode was explicitly requested. If
9737 WARN is true, warn if EXT does not match reality. */
9740 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9741 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9742 unsigned long *insn
, bfd_boolean
*use_extend
,
9743 unsigned short *extend
)
9745 register const struct mips16_immed_operand
*op
;
9746 int mintiny
, maxtiny
;
9747 bfd_boolean needext
;
9749 op
= mips16_immed_operands
;
9750 while (op
->type
!= type
)
9753 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9758 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9761 maxtiny
= 1 << op
->nbits
;
9766 maxtiny
= (1 << op
->nbits
) - 1;
9771 mintiny
= - (1 << (op
->nbits
- 1));
9772 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9775 /* Branch offsets have an implicit 0 in the lowest bit. */
9776 if (type
== 'p' || type
== 'q')
9779 if ((val
& ((1 << op
->shift
) - 1)) != 0
9780 || val
< (mintiny
<< op
->shift
)
9781 || val
> (maxtiny
<< op
->shift
))
9786 if (warn
&& ext
&& ! needext
)
9787 as_warn_where (file
, line
,
9788 _("extended operand requested but not required"));
9789 if (small
&& needext
)
9790 as_bad_where (file
, line
, _("invalid unextended operand value"));
9792 if (small
|| (! ext
&& ! needext
))
9796 *use_extend
= FALSE
;
9797 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9798 insnval
<<= op
->op_shift
;
9803 long minext
, maxext
;
9809 maxext
= (1 << op
->extbits
) - 1;
9813 minext
= - (1 << (op
->extbits
- 1));
9814 maxext
= (1 << (op
->extbits
- 1)) - 1;
9816 if (val
< minext
|| val
> maxext
)
9817 as_bad_where (file
, line
,
9818 _("operand value out of range for instruction"));
9821 if (op
->extbits
== 16)
9823 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9826 else if (op
->extbits
== 15)
9828 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9833 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9837 *extend
= (unsigned short) extval
;
9842 struct percent_op_match
9845 bfd_reloc_code_real_type reloc
;
9848 static const struct percent_op_match mips_percent_op
[] =
9850 {"%lo", BFD_RELOC_LO16
},
9852 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9853 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9854 {"%call16", BFD_RELOC_MIPS_CALL16
},
9855 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9856 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9857 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9858 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9859 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9860 {"%got", BFD_RELOC_MIPS_GOT16
},
9861 {"%gp_rel", BFD_RELOC_GPREL16
},
9862 {"%half", BFD_RELOC_16
},
9863 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9864 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9865 {"%neg", BFD_RELOC_MIPS_SUB
},
9867 {"%hi", BFD_RELOC_HI16_S
}
9870 static const struct percent_op_match mips16_percent_op
[] =
9872 {"%lo", BFD_RELOC_MIPS16_LO16
},
9873 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9874 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9878 /* Return true if *STR points to a relocation operator. When returning true,
9879 move *STR over the operator and store its relocation code in *RELOC.
9880 Leave both *STR and *RELOC alone when returning false. */
9883 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9885 const struct percent_op_match
*percent_op
;
9888 if (mips_opts
.mips16
)
9890 percent_op
= mips16_percent_op
;
9891 limit
= ARRAY_SIZE (mips16_percent_op
);
9895 percent_op
= mips_percent_op
;
9896 limit
= ARRAY_SIZE (mips_percent_op
);
9899 for (i
= 0; i
< limit
; i
++)
9900 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9902 *str
+= strlen (percent_op
[i
].str
);
9903 *reloc
= percent_op
[i
].reloc
;
9905 /* Check whether the output BFD supports this relocation.
9906 If not, issue an error and fall back on something safe. */
9907 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9909 as_bad ("relocation %s isn't supported by the current ABI",
9911 *reloc
= BFD_RELOC_UNUSED
;
9919 /* Parse string STR as a 16-bit relocatable operand. Store the
9920 expression in *EP and the relocations in the array starting
9921 at RELOC. Return the number of relocation operators used.
9923 On exit, EXPR_END points to the first character after the expression. */
9926 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9929 bfd_reloc_code_real_type reversed_reloc
[3];
9930 size_t reloc_index
, i
;
9931 int crux_depth
, str_depth
;
9934 /* Search for the start of the main expression, recoding relocations
9935 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9936 of the main expression and with CRUX_DEPTH containing the number
9937 of open brackets at that point. */
9944 crux_depth
= str_depth
;
9946 /* Skip over whitespace and brackets, keeping count of the number
9948 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9953 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9954 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9956 my_getExpression (ep
, crux
);
9959 /* Match every open bracket. */
9960 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9965 as_bad ("unclosed '('");
9969 if (reloc_index
!= 0)
9971 prev_reloc_op_frag
= frag_now
;
9972 for (i
= 0; i
< reloc_index
; i
++)
9973 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9980 my_getExpression (expressionS
*ep
, char *str
)
9985 save_in
= input_line_pointer
;
9986 input_line_pointer
= str
;
9988 expr_end
= input_line_pointer
;
9989 input_line_pointer
= save_in
;
9991 /* If we are in mips16 mode, and this is an expression based on `.',
9992 then we bump the value of the symbol by 1 since that is how other
9993 text symbols are handled. We don't bother to handle complex
9994 expressions, just `.' plus or minus a constant. */
9995 if (mips_opts
.mips16
9996 && ep
->X_op
== O_symbol
9997 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9998 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9999 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10000 && symbol_constant_p (ep
->X_add_symbol
)
10001 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10002 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10005 /* Turn a string in input_line_pointer into a floating point constant
10006 of type TYPE, and store the appropriate bytes in *LITP. The number
10007 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10008 returned, or NULL on OK. */
10011 md_atof (int type
, char *litP
, int *sizeP
)
10014 LITTLENUM_TYPE words
[4];
10030 return _("bad call to md_atof");
10033 t
= atof_ieee (input_line_pointer
, type
, words
);
10035 input_line_pointer
= t
;
10039 if (! target_big_endian
)
10041 for (i
= prec
- 1; i
>= 0; i
--)
10043 md_number_to_chars (litP
, words
[i
], 2);
10049 for (i
= 0; i
< prec
; i
++)
10051 md_number_to_chars (litP
, words
[i
], 2);
10060 md_number_to_chars (char *buf
, valueT val
, int n
)
10062 if (target_big_endian
)
10063 number_to_chars_bigendian (buf
, val
, n
);
10065 number_to_chars_littleendian (buf
, val
, n
);
10069 static int support_64bit_objects(void)
10071 const char **list
, **l
;
10074 list
= bfd_target_list ();
10075 for (l
= list
; *l
!= NULL
; l
++)
10077 /* This is traditional mips */
10078 if (strcmp (*l
, "elf64-tradbigmips") == 0
10079 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10081 if (strcmp (*l
, "elf64-bigmips") == 0
10082 || strcmp (*l
, "elf64-littlemips") == 0)
10085 yes
= (*l
!= NULL
);
10089 #endif /* OBJ_ELF */
10091 const char *md_shortopts
= "O::g::G:";
10093 struct option md_longopts
[] =
10095 /* Options which specify architecture. */
10096 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10097 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10098 {"march", required_argument
, NULL
, OPTION_MARCH
},
10099 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10100 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10101 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10102 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10103 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10104 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10105 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10106 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10107 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10108 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10109 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10110 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10111 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10112 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10113 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10114 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10115 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10116 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10117 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10118 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10119 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10121 /* Options which specify Application Specific Extensions (ASEs). */
10122 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10123 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10124 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10125 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10126 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10127 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10128 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10129 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10130 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10131 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10132 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10133 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10134 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10136 /* Old-style architecture options. Don't add more of these. */
10137 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10138 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10139 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10140 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10141 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10142 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10143 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10144 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10145 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10146 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10147 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10148 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10149 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10150 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10151 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10152 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10153 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10155 /* Options which enable bug fixes. */
10156 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10157 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10158 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10159 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10160 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10161 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10162 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10163 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10164 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10165 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10167 /* Miscellaneous options. */
10168 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10169 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10170 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10171 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10172 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10173 {"break", no_argument
, NULL
, OPTION_BREAK
},
10174 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10175 #define OPTION_EB (OPTION_MISC_BASE + 2)
10176 {"EB", no_argument
, NULL
, OPTION_EB
},
10177 #define OPTION_EL (OPTION_MISC_BASE + 3)
10178 {"EL", no_argument
, NULL
, OPTION_EL
},
10179 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10180 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10181 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10182 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10183 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10184 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10185 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10186 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10187 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10188 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10189 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10190 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10191 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10192 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10193 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10194 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10195 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10196 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10197 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10198 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10200 /* ELF-specific options. */
10202 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 14)
10203 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10204 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10205 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10206 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10207 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10208 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10209 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10210 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10211 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10212 #define OPTION_32 (OPTION_ELF_BASE + 4)
10213 {"32", no_argument
, NULL
, OPTION_32
},
10214 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10215 {"n32", no_argument
, NULL
, OPTION_N32
},
10216 #define OPTION_64 (OPTION_ELF_BASE + 6)
10217 {"64", no_argument
, NULL
, OPTION_64
},
10218 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10219 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10220 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10221 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10222 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10223 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10224 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10225 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10226 #endif /* OBJ_ELF */
10228 {NULL
, no_argument
, NULL
, 0}
10230 size_t md_longopts_size
= sizeof (md_longopts
);
10232 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10233 NEW_VALUE. Warn if another value was already specified. Note:
10234 we have to defer parsing the -march and -mtune arguments in order
10235 to handle 'from-abi' correctly, since the ABI might be specified
10236 in a later argument. */
10239 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10241 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10242 as_warn (_("A different %s was already specified, is now %s"),
10243 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10246 *string_ptr
= new_value
;
10250 md_parse_option (int c
, char *arg
)
10254 case OPTION_CONSTRUCT_FLOATS
:
10255 mips_disable_float_construction
= 0;
10258 case OPTION_NO_CONSTRUCT_FLOATS
:
10259 mips_disable_float_construction
= 1;
10271 target_big_endian
= 1;
10275 target_big_endian
= 0;
10279 if (arg
&& arg
[1] == '0')
10289 mips_debug
= atoi (arg
);
10290 /* When the MIPS assembler sees -g or -g2, it does not do
10291 optimizations which limit full symbolic debugging. We take
10292 that to be equivalent to -O0. */
10293 if (mips_debug
== 2)
10298 file_mips_isa
= ISA_MIPS1
;
10302 file_mips_isa
= ISA_MIPS2
;
10306 file_mips_isa
= ISA_MIPS3
;
10310 file_mips_isa
= ISA_MIPS4
;
10314 file_mips_isa
= ISA_MIPS5
;
10317 case OPTION_MIPS32
:
10318 file_mips_isa
= ISA_MIPS32
;
10321 case OPTION_MIPS32R2
:
10322 file_mips_isa
= ISA_MIPS32R2
;
10325 case OPTION_MIPS64R2
:
10326 file_mips_isa
= ISA_MIPS64R2
;
10329 case OPTION_MIPS64
:
10330 file_mips_isa
= ISA_MIPS64
;
10334 mips_set_option_string (&mips_tune_string
, arg
);
10338 mips_set_option_string (&mips_arch_string
, arg
);
10342 mips_set_option_string (&mips_arch_string
, "4650");
10343 mips_set_option_string (&mips_tune_string
, "4650");
10346 case OPTION_NO_M4650
:
10350 mips_set_option_string (&mips_arch_string
, "4010");
10351 mips_set_option_string (&mips_tune_string
, "4010");
10354 case OPTION_NO_M4010
:
10358 mips_set_option_string (&mips_arch_string
, "4100");
10359 mips_set_option_string (&mips_tune_string
, "4100");
10362 case OPTION_NO_M4100
:
10366 mips_set_option_string (&mips_arch_string
, "3900");
10367 mips_set_option_string (&mips_tune_string
, "3900");
10370 case OPTION_NO_M3900
:
10374 mips_opts
.ase_mdmx
= 1;
10377 case OPTION_NO_MDMX
:
10378 mips_opts
.ase_mdmx
= 0;
10381 case OPTION_MIPS16
:
10382 mips_opts
.mips16
= 1;
10383 mips_no_prev_insn (FALSE
);
10386 case OPTION_NO_MIPS16
:
10387 mips_opts
.mips16
= 0;
10388 mips_no_prev_insn (FALSE
);
10391 case OPTION_MIPS3D
:
10392 mips_opts
.ase_mips3d
= 1;
10395 case OPTION_NO_MIPS3D
:
10396 mips_opts
.ase_mips3d
= 0;
10399 case OPTION_FIX_VR4120
:
10400 mips_fix_vr4120
= 1;
10403 case OPTION_NO_FIX_VR4120
:
10404 mips_fix_vr4120
= 0;
10407 case OPTION_RELAX_BRANCH
:
10408 mips_relax_branch
= 1;
10411 case OPTION_NO_RELAX_BRANCH
:
10412 mips_relax_branch
= 0;
10415 case OPTION_MSHARED
:
10416 mips_in_shared
= TRUE
;
10419 case OPTION_MNO_SHARED
:
10420 mips_in_shared
= FALSE
;
10424 /* When generating ELF code, we permit -KPIC and -call_shared to
10425 select SVR4_PIC, and -non_shared to select no PIC. This is
10426 intended to be compatible with Irix 5. */
10427 case OPTION_CALL_SHARED
:
10428 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10430 as_bad (_("-call_shared is supported only for ELF format"));
10433 mips_pic
= SVR4_PIC
;
10434 mips_abicalls
= TRUE
;
10435 if (g_switch_seen
&& g_switch_value
!= 0)
10437 as_bad (_("-G may not be used with SVR4 PIC code"));
10440 g_switch_value
= 0;
10443 case OPTION_NON_SHARED
:
10444 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10446 as_bad (_("-non_shared is supported only for ELF format"));
10450 mips_abicalls
= FALSE
;
10453 /* The -xgot option tells the assembler to use 32 offsets when
10454 accessing the got in SVR4_PIC mode. It is for Irix
10459 #endif /* OBJ_ELF */
10462 if (mips_pic
== SVR4_PIC
)
10464 as_bad (_("-G may not be used with SVR4 PIC code"));
10468 g_switch_value
= atoi (arg
);
10473 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10476 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10478 as_bad (_("-32 is supported for ELF format only"));
10481 mips_abi
= O32_ABI
;
10485 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10487 as_bad (_("-n32 is supported for ELF format only"));
10490 mips_abi
= N32_ABI
;
10494 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10496 as_bad (_("-64 is supported for ELF format only"));
10499 mips_abi
= N64_ABI
;
10500 if (! support_64bit_objects())
10501 as_fatal (_("No compiled in support for 64 bit object file format"));
10503 #endif /* OBJ_ELF */
10506 file_mips_gp32
= 1;
10510 file_mips_gp32
= 0;
10514 file_mips_fp32
= 1;
10518 file_mips_fp32
= 0;
10523 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10525 as_bad (_("-mabi is supported for ELF format only"));
10528 if (strcmp (arg
, "32") == 0)
10529 mips_abi
= O32_ABI
;
10530 else if (strcmp (arg
, "o64") == 0)
10531 mips_abi
= O64_ABI
;
10532 else if (strcmp (arg
, "n32") == 0)
10533 mips_abi
= N32_ABI
;
10534 else if (strcmp (arg
, "64") == 0)
10536 mips_abi
= N64_ABI
;
10537 if (! support_64bit_objects())
10538 as_fatal (_("No compiled in support for 64 bit object file "
10541 else if (strcmp (arg
, "eabi") == 0)
10542 mips_abi
= EABI_ABI
;
10545 as_fatal (_("invalid abi -mabi=%s"), arg
);
10549 #endif /* OBJ_ELF */
10551 case OPTION_M7000_HILO_FIX
:
10552 mips_7000_hilo_fix
= TRUE
;
10555 case OPTION_MNO_7000_HILO_FIX
:
10556 mips_7000_hilo_fix
= FALSE
;
10560 case OPTION_MDEBUG
:
10561 mips_flag_mdebug
= TRUE
;
10564 case OPTION_NO_MDEBUG
:
10565 mips_flag_mdebug
= FALSE
;
10569 mips_flag_pdr
= TRUE
;
10572 case OPTION_NO_PDR
:
10573 mips_flag_pdr
= FALSE
;
10575 #endif /* OBJ_ELF */
10584 /* Set up globals to generate code for the ISA or processor
10585 described by INFO. */
10588 mips_set_architecture (const struct mips_cpu_info
*info
)
10592 file_mips_arch
= info
->cpu
;
10593 mips_opts
.arch
= info
->cpu
;
10594 mips_opts
.isa
= info
->isa
;
10599 /* Likewise for tuning. */
10602 mips_set_tune (const struct mips_cpu_info
*info
)
10605 mips_tune
= info
->cpu
;
10610 mips_after_parse_args (void)
10612 const struct mips_cpu_info
*arch_info
= 0;
10613 const struct mips_cpu_info
*tune_info
= 0;
10615 /* GP relative stuff not working for PE */
10616 if (strncmp (TARGET_OS
, "pe", 2) == 0
10617 && g_switch_value
!= 0)
10620 as_bad (_("-G not supported in this configuration."));
10621 g_switch_value
= 0;
10624 if (mips_abi
== NO_ABI
)
10625 mips_abi
= MIPS_DEFAULT_ABI
;
10627 /* The following code determines the architecture and register size.
10628 Similar code was added to GCC 3.3 (see override_options() in
10629 config/mips/mips.c). The GAS and GCC code should be kept in sync
10630 as much as possible. */
10632 if (mips_arch_string
!= 0)
10633 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10635 if (file_mips_isa
!= ISA_UNKNOWN
)
10637 /* Handle -mipsN. At this point, file_mips_isa contains the
10638 ISA level specified by -mipsN, while arch_info->isa contains
10639 the -march selection (if any). */
10640 if (arch_info
!= 0)
10642 /* -march takes precedence over -mipsN, since it is more descriptive.
10643 There's no harm in specifying both as long as the ISA levels
10645 if (file_mips_isa
!= arch_info
->isa
)
10646 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10647 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10648 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10651 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10654 if (arch_info
== 0)
10655 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10657 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10658 as_bad ("-march=%s is not compatible with the selected ABI",
10661 mips_set_architecture (arch_info
);
10663 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10664 if (mips_tune_string
!= 0)
10665 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10667 if (tune_info
== 0)
10668 mips_set_tune (arch_info
);
10670 mips_set_tune (tune_info
);
10672 if (file_mips_gp32
>= 0)
10674 /* The user specified the size of the integer registers. Make sure
10675 it agrees with the ABI and ISA. */
10676 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10677 as_bad (_("-mgp64 used with a 32-bit processor"));
10678 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10679 as_bad (_("-mgp32 used with a 64-bit ABI"));
10680 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10681 as_bad (_("-mgp64 used with a 32-bit ABI"));
10685 /* Infer the integer register size from the ABI and processor.
10686 Restrict ourselves to 32-bit registers if that's all the
10687 processor has, or if the ABI cannot handle 64-bit registers. */
10688 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10689 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10692 /* ??? GAS treats single-float processors as though they had 64-bit
10693 float registers (although it complains when double-precision
10694 instructions are used). As things stand, saying they have 32-bit
10695 registers would lead to spurious "register must be even" messages.
10696 So here we assume float registers are always the same size as
10697 integer ones, unless the user says otherwise. */
10698 if (file_mips_fp32
< 0)
10699 file_mips_fp32
= file_mips_gp32
;
10701 /* End of GCC-shared inference code. */
10703 /* This flag is set when we have a 64-bit capable CPU but use only
10704 32-bit wide registers. Note that EABI does not use it. */
10705 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10706 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10707 || mips_abi
== O32_ABI
))
10708 mips_32bitmode
= 1;
10710 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10711 as_bad (_("trap exception not supported at ISA 1"));
10713 /* If the selected architecture includes support for ASEs, enable
10714 generation of code for them. */
10715 if (mips_opts
.mips16
== -1)
10716 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10717 if (mips_opts
.ase_mips3d
== -1)
10718 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10719 if (mips_opts
.ase_mdmx
== -1)
10720 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10722 file_mips_isa
= mips_opts
.isa
;
10723 file_ase_mips16
= mips_opts
.mips16
;
10724 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10725 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10726 mips_opts
.gp32
= file_mips_gp32
;
10727 mips_opts
.fp32
= file_mips_fp32
;
10729 if (mips_flag_mdebug
< 0)
10731 #ifdef OBJ_MAYBE_ECOFF
10732 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10733 mips_flag_mdebug
= 1;
10735 #endif /* OBJ_MAYBE_ECOFF */
10736 mips_flag_mdebug
= 0;
10741 mips_init_after_args (void)
10743 /* initialize opcodes */
10744 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10745 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10749 md_pcrel_from (fixS
*fixP
)
10751 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10752 switch (fixP
->fx_r_type
)
10754 case BFD_RELOC_16_PCREL_S2
:
10755 case BFD_RELOC_MIPS_JMP
:
10756 /* Return the address of the delay slot. */
10763 /* This is called before the symbol table is processed. In order to
10764 work with gcc when using mips-tfile, we must keep all local labels.
10765 However, in other cases, we want to discard them. If we were
10766 called with -g, but we didn't see any debugging information, it may
10767 mean that gcc is smuggling debugging information through to
10768 mips-tfile, in which case we must generate all local labels. */
10771 mips_frob_file_before_adjust (void)
10773 #ifndef NO_ECOFF_DEBUGGING
10774 if (ECOFF_DEBUGGING
10776 && ! ecoff_debugging_seen
)
10777 flag_keep_locals
= 1;
10781 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10782 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10783 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10784 relocation operators.
10786 For our purposes, a %lo() expression matches a %got() or %hi()
10789 (a) it refers to the same symbol; and
10790 (b) the offset applied in the %lo() expression is no lower than
10791 the offset applied in the %got() or %hi().
10793 (b) allows us to cope with code like:
10796 lh $4,%lo(foo+2)($4)
10798 ...which is legal on RELA targets, and has a well-defined behaviour
10799 if the user knows that adding 2 to "foo" will not induce a carry to
10802 When several %lo()s match a particular %got() or %hi(), we use the
10803 following rules to distinguish them:
10805 (1) %lo()s with smaller offsets are a better match than %lo()s with
10808 (2) %lo()s with no matching %got() or %hi() are better than those
10809 that already have a matching %got() or %hi().
10811 (3) later %lo()s are better than earlier %lo()s.
10813 These rules are applied in order.
10815 (1) means, among other things, that %lo()s with identical offsets are
10816 chosen if they exist.
10818 (2) means that we won't associate several high-part relocations with
10819 the same low-part relocation unless there's no alternative. Having
10820 several high parts for the same low part is a GNU extension; this rule
10821 allows careful users to avoid it.
10823 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10824 with the last high-part relocation being at the front of the list.
10825 It therefore makes sense to choose the last matching low-part
10826 relocation, all other things being equal. It's also easier
10827 to code that way. */
10830 mips_frob_file (void)
10832 struct mips_hi_fixup
*l
;
10834 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10836 segment_info_type
*seginfo
;
10837 bfd_boolean matched_lo_p
;
10838 fixS
**hi_pos
, **lo_pos
, **pos
;
10840 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10842 /* If a GOT16 relocation turns out to be against a global symbol,
10843 there isn't supposed to be a matching LO. */
10844 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10845 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10848 /* Check quickly whether the next fixup happens to be a matching %lo. */
10849 if (fixup_has_matching_lo_p (l
->fixp
))
10852 seginfo
= seg_info (l
->seg
);
10854 /* Set HI_POS to the position of this relocation in the chain.
10855 Set LO_POS to the position of the chosen low-part relocation.
10856 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10857 relocation that matches an immediately-preceding high-part
10861 matched_lo_p
= FALSE
;
10862 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10864 if (*pos
== l
->fixp
)
10867 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10868 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10869 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10871 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10873 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10876 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10877 && fixup_has_matching_lo_p (*pos
));
10880 /* If we found a match, remove the high-part relocation from its
10881 current position and insert it before the low-part relocation.
10882 Make the offsets match so that fixup_has_matching_lo_p()
10885 We don't warn about unmatched high-part relocations since some
10886 versions of gcc have been known to emit dead "lui ...%hi(...)"
10888 if (lo_pos
!= NULL
)
10890 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10891 if (l
->fixp
->fx_next
!= *lo_pos
)
10893 *hi_pos
= l
->fixp
->fx_next
;
10894 l
->fixp
->fx_next
= *lo_pos
;
10901 /* We may have combined relocations without symbols in the N32/N64 ABI.
10902 We have to prevent gas from dropping them. */
10905 mips_force_relocation (fixS
*fixp
)
10907 if (generic_force_reloc (fixp
))
10911 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10912 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10913 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10914 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10920 /* This hook is called before a fix is simplified. We don't really
10921 decide whether to skip a fix here. Rather, we turn global symbols
10922 used as branch targets into local symbols, such that they undergo
10923 simplification. We can only do this if the symbol is defined and
10924 it is in the same section as the branch. If this doesn't hold, we
10925 emit a better error message than just saying the relocation is not
10926 valid for the selected object format.
10928 FIXP is the fix-up we're going to try to simplify, SEG is the
10929 segment in which the fix up occurs. The return value should be
10930 non-zero to indicate the fix-up is valid for further
10931 simplifications. */
10934 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10936 /* There's a lot of discussion on whether it should be possible to
10937 use R_MIPS_PC16 to represent branch relocations. The outcome
10938 seems to be that it can, but gas/bfd are very broken in creating
10939 RELA relocations for this, so for now we only accept branches to
10940 symbols in the same section. Anything else is of dubious value,
10941 since there's no guarantee that at link time the symbol would be
10942 in range. Even for branches to local symbols this is arguably
10943 wrong, since it we assume the symbol is not going to be
10944 overridden, which should be possible per ELF library semantics,
10945 but then, there isn't a dynamic relocation that could be used to
10946 this effect, and the target would likely be out of range as well.
10948 Unfortunately, it seems that there is too much code out there
10949 that relies on branches to symbols that are global to be resolved
10950 as if they were local, like the IRIX tools do, so we do it as
10951 well, but with a warning so that people are reminded to fix their
10952 code. If we ever get back to using R_MIPS_PC16 for branch
10953 targets, this entire block should go away (and probably the
10954 whole function). */
10956 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10957 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10958 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10959 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10962 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10965 _("Cannot branch to undefined symbol."));
10966 /* Avoid any further errors about this fixup. */
10969 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10972 _("Cannot branch to symbol in another section."));
10975 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10977 symbolS
*sym
= fixP
->fx_addsy
;
10979 if (mips_pic
== SVR4_PIC
)
10980 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10981 _("Pretending global symbol used as branch target is local."));
10983 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10984 S_GET_SEGMENT (sym
),
10986 symbol_get_frag (sym
));
10987 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10988 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10989 assert (symbol_resolved_p (sym
));
10990 symbol_mark_resolved (fixP
->fx_addsy
);
10997 /* Apply a fixup to the object file. */
11000 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11004 reloc_howto_type
*howto
;
11006 /* We ignore generic BFD relocations we don't know about. */
11007 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11011 assert (fixP
->fx_size
== 4
11012 || fixP
->fx_r_type
== BFD_RELOC_16
11013 || fixP
->fx_r_type
== BFD_RELOC_64
11014 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11015 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11016 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11017 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11019 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11021 assert (! fixP
->fx_pcrel
);
11023 /* Don't treat parts of a composite relocation as done. There are two
11026 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11027 should nevertheless be emitted if the first part is.
11029 (2) In normal usage, composite relocations are never assembly-time
11030 constants. The easiest way of dealing with the pathological
11031 exceptions is to generate a relocation against STN_UNDEF and
11032 leave everything up to the linker. */
11033 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
11036 switch (fixP
->fx_r_type
)
11038 case BFD_RELOC_MIPS_JMP
:
11039 case BFD_RELOC_MIPS_SHIFT5
:
11040 case BFD_RELOC_MIPS_SHIFT6
:
11041 case BFD_RELOC_MIPS_GOT_DISP
:
11042 case BFD_RELOC_MIPS_GOT_PAGE
:
11043 case BFD_RELOC_MIPS_GOT_OFST
:
11044 case BFD_RELOC_MIPS_SUB
:
11045 case BFD_RELOC_MIPS_INSERT_A
:
11046 case BFD_RELOC_MIPS_INSERT_B
:
11047 case BFD_RELOC_MIPS_DELETE
:
11048 case BFD_RELOC_MIPS_HIGHEST
:
11049 case BFD_RELOC_MIPS_HIGHER
:
11050 case BFD_RELOC_MIPS_SCN_DISP
:
11051 case BFD_RELOC_MIPS_REL16
:
11052 case BFD_RELOC_MIPS_RELGOT
:
11053 case BFD_RELOC_MIPS_JALR
:
11054 case BFD_RELOC_HI16
:
11055 case BFD_RELOC_HI16_S
:
11056 case BFD_RELOC_GPREL16
:
11057 case BFD_RELOC_MIPS_LITERAL
:
11058 case BFD_RELOC_MIPS_CALL16
:
11059 case BFD_RELOC_MIPS_GOT16
:
11060 case BFD_RELOC_GPREL32
:
11061 case BFD_RELOC_MIPS_GOT_HI16
:
11062 case BFD_RELOC_MIPS_GOT_LO16
:
11063 case BFD_RELOC_MIPS_CALL_HI16
:
11064 case BFD_RELOC_MIPS_CALL_LO16
:
11065 case BFD_RELOC_MIPS16_GPREL
:
11066 case BFD_RELOC_MIPS16_HI16
:
11067 case BFD_RELOC_MIPS16_HI16_S
:
11068 assert (! fixP
->fx_pcrel
);
11069 /* Nothing needed to do. The value comes from the reloc entry */
11072 case BFD_RELOC_MIPS16_JMP
:
11073 /* We currently always generate a reloc against a symbol, which
11074 means that we don't want an addend even if the symbol is
11080 /* This is handled like BFD_RELOC_32, but we output a sign
11081 extended value if we are only 32 bits. */
11084 if (8 <= sizeof (valueT
))
11085 md_number_to_chars (buf
, *valP
, 8);
11090 if ((*valP
& 0x80000000) != 0)
11094 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11096 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11102 case BFD_RELOC_RVA
:
11104 /* If we are deleting this reloc entry, we must fill in the
11105 value now. This can happen if we have a .word which is not
11106 resolved when it appears but is later defined. */
11108 md_number_to_chars (buf
, *valP
, 4);
11112 /* If we are deleting this reloc entry, we must fill in the
11115 md_number_to_chars (buf
, *valP
, 2);
11118 case BFD_RELOC_LO16
:
11119 case BFD_RELOC_MIPS16_LO16
:
11120 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11121 may be safe to remove, but if so it's not obvious. */
11122 /* When handling an embedded PIC switch statement, we can wind
11123 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11126 if (*valP
+ 0x8000 > 0xffff)
11127 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11128 _("relocation overflow"));
11129 if (target_big_endian
)
11131 md_number_to_chars (buf
, *valP
, 2);
11135 case BFD_RELOC_16_PCREL_S2
:
11136 if ((*valP
& 0x3) != 0)
11137 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11138 _("Branch to odd address (%lx)"), (long) *valP
);
11141 * We need to save the bits in the instruction since fixup_segment()
11142 * might be deleting the relocation entry (i.e., a branch within
11143 * the current segment).
11145 if (! fixP
->fx_done
)
11148 /* update old instruction data */
11149 if (target_big_endian
)
11150 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11152 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11154 if (*valP
+ 0x20000 <= 0x3ffff)
11156 insn
|= (*valP
>> 2) & 0xffff;
11157 md_number_to_chars (buf
, insn
, 4);
11159 else if (mips_pic
== NO_PIC
11161 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11162 && (fixP
->fx_frag
->fr_address
11163 < text_section
->vma
+ bfd_get_section_size (text_section
))
11164 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11165 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11166 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11168 /* The branch offset is too large. If this is an
11169 unconditional branch, and we are not generating PIC code,
11170 we can convert it to an absolute jump instruction. */
11171 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11172 insn
= 0x0c000000; /* jal */
11174 insn
= 0x08000000; /* j */
11175 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11177 fixP
->fx_addsy
= section_symbol (text_section
);
11178 *valP
+= md_pcrel_from (fixP
);
11179 md_number_to_chars (buf
, insn
, 4);
11183 /* If we got here, we have branch-relaxation disabled,
11184 and there's nothing we can do to fix this instruction
11185 without turning it into a longer sequence. */
11186 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11187 _("Branch out of range"));
11191 case BFD_RELOC_VTABLE_INHERIT
:
11194 && !S_IS_DEFINED (fixP
->fx_addsy
)
11195 && !S_IS_WEAK (fixP
->fx_addsy
))
11196 S_SET_WEAK (fixP
->fx_addsy
);
11199 case BFD_RELOC_VTABLE_ENTRY
:
11207 /* Remember value for tc_gen_reloc. */
11208 fixP
->fx_addnumber
= *valP
;
11218 name
= input_line_pointer
;
11219 c
= get_symbol_end ();
11220 p
= (symbolS
*) symbol_find_or_make (name
);
11221 *input_line_pointer
= c
;
11225 /* Align the current frag to a given power of two. The MIPS assembler
11226 also automatically adjusts any preceding label. */
11229 mips_align (int to
, int fill
, symbolS
*label
)
11231 mips_emit_delays (FALSE
);
11232 frag_align (to
, fill
, 0);
11233 record_alignment (now_seg
, to
);
11236 assert (S_GET_SEGMENT (label
) == now_seg
);
11237 symbol_set_frag (label
, frag_now
);
11238 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11242 /* Align to a given power of two. .align 0 turns off the automatic
11243 alignment used by the data creating pseudo-ops. */
11246 s_align (int x ATTRIBUTE_UNUSED
)
11249 register long temp_fill
;
11250 long max_alignment
= 15;
11254 o Note that the assembler pulls down any immediately preceding label
11255 to the aligned address.
11256 o It's not documented but auto alignment is reinstated by
11257 a .align pseudo instruction.
11258 o Note also that after auto alignment is turned off the mips assembler
11259 issues an error on attempt to assemble an improperly aligned data item.
11264 temp
= get_absolute_expression ();
11265 if (temp
> max_alignment
)
11266 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11269 as_warn (_("Alignment negative: 0 assumed."));
11272 if (*input_line_pointer
== ',')
11274 ++input_line_pointer
;
11275 temp_fill
= get_absolute_expression ();
11282 mips_align (temp
, (int) temp_fill
,
11283 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11290 demand_empty_rest_of_line ();
11294 mips_flush_pending_output (void)
11296 mips_emit_delays (FALSE
);
11297 mips_clear_insn_labels ();
11301 s_change_sec (int sec
)
11306 /* The ELF backend needs to know that we are changing sections, so
11307 that .previous works correctly. We could do something like check
11308 for an obj_section_change_hook macro, but that might be confusing
11309 as it would not be appropriate to use it in the section changing
11310 functions in read.c, since obj-elf.c intercepts those. FIXME:
11311 This should be cleaner, somehow. */
11312 obj_elf_section_change_hook ();
11315 mips_emit_delays (FALSE
);
11325 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11326 demand_empty_rest_of_line ();
11330 seg
= subseg_new (RDATA_SECTION_NAME
,
11331 (subsegT
) get_absolute_expression ());
11332 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11334 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11335 | SEC_READONLY
| SEC_RELOC
11337 if (strcmp (TARGET_OS
, "elf") != 0)
11338 record_alignment (seg
, 4);
11340 demand_empty_rest_of_line ();
11344 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11345 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11347 bfd_set_section_flags (stdoutput
, seg
,
11348 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11349 if (strcmp (TARGET_OS
, "elf") != 0)
11350 record_alignment (seg
, 4);
11352 demand_empty_rest_of_line ();
11360 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11363 char *section_name
;
11368 int section_entry_size
;
11369 int section_alignment
;
11371 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11374 section_name
= input_line_pointer
;
11375 c
= get_symbol_end ();
11377 next_c
= *(input_line_pointer
+ 1);
11379 /* Do we have .section Name<,"flags">? */
11380 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11382 /* just after name is now '\0'. */
11383 *input_line_pointer
= c
;
11384 input_line_pointer
= section_name
;
11385 obj_elf_section (ignore
);
11388 input_line_pointer
++;
11390 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11392 section_type
= get_absolute_expression ();
11395 if (*input_line_pointer
++ == ',')
11396 section_flag
= get_absolute_expression ();
11399 if (*input_line_pointer
++ == ',')
11400 section_entry_size
= get_absolute_expression ();
11402 section_entry_size
= 0;
11403 if (*input_line_pointer
++ == ',')
11404 section_alignment
= get_absolute_expression ();
11406 section_alignment
= 0;
11408 section_name
= xstrdup (section_name
);
11410 /* When using the generic form of .section (as implemented by obj-elf.c),
11411 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11412 traditionally had to fall back on the more common @progbits instead.
11414 There's nothing really harmful in this, since bfd will correct
11415 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11416 means that, for backwards compatibiltiy, the special_section entries
11417 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11419 Even so, we shouldn't force users of the MIPS .section syntax to
11420 incorrectly label the sections as SHT_PROGBITS. The best compromise
11421 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11422 generic type-checking code. */
11423 if (section_type
== SHT_MIPS_DWARF
)
11424 section_type
= SHT_PROGBITS
;
11426 obj_elf_change_section (section_name
, section_type
, section_flag
,
11427 section_entry_size
, 0, 0, 0);
11429 if (now_seg
->name
!= section_name
)
11430 free (section_name
);
11431 #endif /* OBJ_ELF */
11435 mips_enable_auto_align (void)
11441 s_cons (int log_size
)
11445 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11446 mips_emit_delays (FALSE
);
11447 if (log_size
> 0 && auto_align
)
11448 mips_align (log_size
, 0, label
);
11449 mips_clear_insn_labels ();
11450 cons (1 << log_size
);
11454 s_float_cons (int type
)
11458 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11460 mips_emit_delays (FALSE
);
11465 mips_align (3, 0, label
);
11467 mips_align (2, 0, label
);
11470 mips_clear_insn_labels ();
11475 /* Handle .globl. We need to override it because on Irix 5 you are
11478 where foo is an undefined symbol, to mean that foo should be
11479 considered to be the address of a function. */
11482 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11489 name
= input_line_pointer
;
11490 c
= get_symbol_end ();
11491 symbolP
= symbol_find_or_make (name
);
11492 *input_line_pointer
= c
;
11493 SKIP_WHITESPACE ();
11495 /* On Irix 5, every global symbol that is not explicitly labelled as
11496 being a function is apparently labelled as being an object. */
11499 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11504 secname
= input_line_pointer
;
11505 c
= get_symbol_end ();
11506 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11508 as_bad (_("%s: no such section"), secname
);
11509 *input_line_pointer
= c
;
11511 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11512 flag
= BSF_FUNCTION
;
11515 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11517 S_SET_EXTERNAL (symbolP
);
11518 demand_empty_rest_of_line ();
11522 s_option (int x ATTRIBUTE_UNUSED
)
11527 opt
= input_line_pointer
;
11528 c
= get_symbol_end ();
11532 /* FIXME: What does this mean? */
11534 else if (strncmp (opt
, "pic", 3) == 0)
11538 i
= atoi (opt
+ 3);
11543 mips_pic
= SVR4_PIC
;
11544 mips_abicalls
= TRUE
;
11547 as_bad (_(".option pic%d not supported"), i
);
11549 if (mips_pic
== SVR4_PIC
)
11551 if (g_switch_seen
&& g_switch_value
!= 0)
11552 as_warn (_("-G may not be used with SVR4 PIC code"));
11553 g_switch_value
= 0;
11554 bfd_set_gp_size (stdoutput
, 0);
11558 as_warn (_("Unrecognized option \"%s\""), opt
);
11560 *input_line_pointer
= c
;
11561 demand_empty_rest_of_line ();
11564 /* This structure is used to hold a stack of .set values. */
11566 struct mips_option_stack
11568 struct mips_option_stack
*next
;
11569 struct mips_set_options options
;
11572 static struct mips_option_stack
*mips_opts_stack
;
11574 /* Handle the .set pseudo-op. */
11577 s_mipsset (int x ATTRIBUTE_UNUSED
)
11579 char *name
= input_line_pointer
, ch
;
11581 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11582 ++input_line_pointer
;
11583 ch
= *input_line_pointer
;
11584 *input_line_pointer
= '\0';
11586 if (strcmp (name
, "reorder") == 0)
11588 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11590 /* If we still have pending nops, we can discard them. The
11591 usual nop handling will insert any that are still
11593 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11594 * (mips_opts
.mips16
? 2 : 4));
11595 prev_nop_frag
= NULL
;
11597 mips_opts
.noreorder
= 0;
11599 else if (strcmp (name
, "noreorder") == 0)
11601 mips_emit_delays (TRUE
);
11602 mips_opts
.noreorder
= 1;
11603 mips_any_noreorder
= 1;
11605 else if (strcmp (name
, "at") == 0)
11607 mips_opts
.noat
= 0;
11609 else if (strcmp (name
, "noat") == 0)
11611 mips_opts
.noat
= 1;
11613 else if (strcmp (name
, "macro") == 0)
11615 mips_opts
.warn_about_macros
= 0;
11617 else if (strcmp (name
, "nomacro") == 0)
11619 if (mips_opts
.noreorder
== 0)
11620 as_bad (_("`noreorder' must be set before `nomacro'"));
11621 mips_opts
.warn_about_macros
= 1;
11623 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11625 mips_opts
.nomove
= 0;
11627 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11629 mips_opts
.nomove
= 1;
11631 else if (strcmp (name
, "bopt") == 0)
11633 mips_opts
.nobopt
= 0;
11635 else if (strcmp (name
, "nobopt") == 0)
11637 mips_opts
.nobopt
= 1;
11639 else if (strcmp (name
, "mips16") == 0
11640 || strcmp (name
, "MIPS-16") == 0)
11641 mips_opts
.mips16
= 1;
11642 else if (strcmp (name
, "nomips16") == 0
11643 || strcmp (name
, "noMIPS-16") == 0)
11644 mips_opts
.mips16
= 0;
11645 else if (strcmp (name
, "mips3d") == 0)
11646 mips_opts
.ase_mips3d
= 1;
11647 else if (strcmp (name
, "nomips3d") == 0)
11648 mips_opts
.ase_mips3d
= 0;
11649 else if (strcmp (name
, "mdmx") == 0)
11650 mips_opts
.ase_mdmx
= 1;
11651 else if (strcmp (name
, "nomdmx") == 0)
11652 mips_opts
.ase_mdmx
= 0;
11653 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11657 /* Permit the user to change the ISA and architecture on the fly.
11658 Needless to say, misuse can cause serious problems. */
11659 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11662 mips_opts
.isa
= file_mips_isa
;
11663 mips_opts
.arch
= file_mips_arch
;
11665 else if (strncmp (name
, "arch=", 5) == 0)
11667 const struct mips_cpu_info
*p
;
11669 p
= mips_parse_cpu("internal use", name
+ 5);
11671 as_bad (_("unknown architecture %s"), name
+ 5);
11674 mips_opts
.arch
= p
->cpu
;
11675 mips_opts
.isa
= p
->isa
;
11678 else if (strncmp (name
, "mips", 4) == 0)
11680 const struct mips_cpu_info
*p
;
11682 p
= mips_parse_cpu("internal use", name
);
11684 as_bad (_("unknown ISA level %s"), name
+ 4);
11687 mips_opts
.arch
= p
->cpu
;
11688 mips_opts
.isa
= p
->isa
;
11692 as_bad (_("unknown ISA or architecture %s"), name
);
11694 switch (mips_opts
.isa
)
11702 mips_opts
.gp32
= 1;
11703 mips_opts
.fp32
= 1;
11710 mips_opts
.gp32
= 0;
11711 mips_opts
.fp32
= 0;
11714 as_bad (_("unknown ISA level %s"), name
+ 4);
11719 mips_opts
.gp32
= file_mips_gp32
;
11720 mips_opts
.fp32
= file_mips_fp32
;
11723 else if (strcmp (name
, "autoextend") == 0)
11724 mips_opts
.noautoextend
= 0;
11725 else if (strcmp (name
, "noautoextend") == 0)
11726 mips_opts
.noautoextend
= 1;
11727 else if (strcmp (name
, "push") == 0)
11729 struct mips_option_stack
*s
;
11731 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11732 s
->next
= mips_opts_stack
;
11733 s
->options
= mips_opts
;
11734 mips_opts_stack
= s
;
11736 else if (strcmp (name
, "pop") == 0)
11738 struct mips_option_stack
*s
;
11740 s
= mips_opts_stack
;
11742 as_bad (_(".set pop with no .set push"));
11745 /* If we're changing the reorder mode we need to handle
11746 delay slots correctly. */
11747 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11748 mips_emit_delays (TRUE
);
11749 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11751 if (prev_nop_frag
!= NULL
)
11753 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11754 * (mips_opts
.mips16
? 2 : 4));
11755 prev_nop_frag
= NULL
;
11759 mips_opts
= s
->options
;
11760 mips_opts_stack
= s
->next
;
11766 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11768 *input_line_pointer
= ch
;
11769 demand_empty_rest_of_line ();
11772 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11773 .option pic2. It means to generate SVR4 PIC calls. */
11776 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11778 mips_pic
= SVR4_PIC
;
11779 mips_abicalls
= TRUE
;
11781 if (g_switch_seen
&& g_switch_value
!= 0)
11782 as_warn (_("-G may not be used with SVR4 PIC code"));
11783 g_switch_value
= 0;
11785 bfd_set_gp_size (stdoutput
, 0);
11786 demand_empty_rest_of_line ();
11789 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11790 PIC code. It sets the $gp register for the function based on the
11791 function address, which is in the register named in the argument.
11792 This uses a relocation against _gp_disp, which is handled specially
11793 by the linker. The result is:
11794 lui $gp,%hi(_gp_disp)
11795 addiu $gp,$gp,%lo(_gp_disp)
11796 addu $gp,$gp,.cpload argument
11797 The .cpload argument is normally $25 == $t9.
11799 The -mno-shared option changes this to:
11801 addiu $gp,$gp,%lo(_gp)
11802 and the argument is ignored. This saves an instruction, but the
11803 resulting code is not position independent; it uses an absolute
11804 address for _gp. Thus code assembled with -mno-shared can go into
11805 an ordinary executable, but not into a shared library. */
11808 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11814 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11815 .cpload is ignored. */
11816 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11822 /* .cpload should be in a .set noreorder section. */
11823 if (mips_opts
.noreorder
== 0)
11824 as_warn (_(".cpload not in noreorder section"));
11826 reg
= tc_get_register (0);
11828 /* If we need to produce a 64-bit address, we are better off using
11829 the default instruction sequence. */
11830 in_shared
= mips_in_shared
|| HAVE_64BIT_ADDRESSES
;
11832 ex
.X_op
= O_symbol
;
11833 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" : "_gp");
11834 ex
.X_op_symbol
= NULL
;
11835 ex
.X_add_number
= 0;
11837 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11838 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11841 macro_build_lui (&ex
, mips_gp_register
);
11842 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11843 mips_gp_register
, BFD_RELOC_LO16
);
11845 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11846 mips_gp_register
, reg
);
11849 demand_empty_rest_of_line ();
11852 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11853 .cpsetup $reg1, offset|$reg2, label
11855 If offset is given, this results in:
11856 sd $gp, offset($sp)
11857 lui $gp, %hi(%neg(%gp_rel(label)))
11858 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11859 daddu $gp, $gp, $reg1
11861 If $reg2 is given, this results in:
11862 daddu $reg2, $gp, $0
11863 lui $gp, %hi(%neg(%gp_rel(label)))
11864 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11865 daddu $gp, $gp, $reg1
11866 $reg1 is normally $25 == $t9.
11868 The -mno-shared option replaces the last three instructions with
11870 addiu $gp,$gp,%lo(_gp)
11874 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11876 expressionS ex_off
;
11877 expressionS ex_sym
;
11880 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11881 We also need NewABI support. */
11882 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11888 reg1
= tc_get_register (0);
11889 SKIP_WHITESPACE ();
11890 if (*input_line_pointer
!= ',')
11892 as_bad (_("missing argument separator ',' for .cpsetup"));
11896 ++input_line_pointer
;
11897 SKIP_WHITESPACE ();
11898 if (*input_line_pointer
== '$')
11900 mips_cpreturn_register
= tc_get_register (0);
11901 mips_cpreturn_offset
= -1;
11905 mips_cpreturn_offset
= get_absolute_expression ();
11906 mips_cpreturn_register
= -1;
11908 SKIP_WHITESPACE ();
11909 if (*input_line_pointer
!= ',')
11911 as_bad (_("missing argument separator ',' for .cpsetup"));
11915 ++input_line_pointer
;
11916 SKIP_WHITESPACE ();
11917 expression (&ex_sym
);
11920 if (mips_cpreturn_register
== -1)
11922 ex_off
.X_op
= O_constant
;
11923 ex_off
.X_add_symbol
= NULL
;
11924 ex_off
.X_op_symbol
= NULL
;
11925 ex_off
.X_add_number
= mips_cpreturn_offset
;
11927 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11928 BFD_RELOC_LO16
, SP
);
11931 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11932 mips_gp_register
, 0);
11934 if (mips_in_shared
|| HAVE_64BIT_ADDRESSES
)
11936 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11937 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11940 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11941 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11942 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11944 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11945 mips_gp_register
, reg1
);
11951 ex
.X_op
= O_symbol
;
11952 ex
.X_add_symbol
= symbol_find_or_make ("_gp");
11953 ex
.X_op_symbol
= NULL
;
11954 ex
.X_add_number
= 0;
11956 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11957 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11959 macro_build_lui (&ex
, mips_gp_register
);
11960 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11961 mips_gp_register
, BFD_RELOC_LO16
);
11966 demand_empty_rest_of_line ();
11970 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11972 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11973 .cplocal is ignored. */
11974 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11980 mips_gp_register
= tc_get_register (0);
11981 demand_empty_rest_of_line ();
11984 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11985 offset from $sp. The offset is remembered, and after making a PIC
11986 call $gp is restored from that location. */
11989 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11993 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11994 .cprestore is ignored. */
11995 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12001 mips_cprestore_offset
= get_absolute_expression ();
12002 mips_cprestore_valid
= 1;
12004 ex
.X_op
= O_constant
;
12005 ex
.X_add_symbol
= NULL
;
12006 ex
.X_op_symbol
= NULL
;
12007 ex
.X_add_number
= mips_cprestore_offset
;
12010 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12011 SP
, HAVE_64BIT_ADDRESSES
);
12014 demand_empty_rest_of_line ();
12017 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12018 was given in the preceding .cpsetup, it results in:
12019 ld $gp, offset($sp)
12021 If a register $reg2 was given there, it results in:
12022 daddu $gp, $reg2, $0
12025 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12029 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12030 We also need NewABI support. */
12031 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12038 if (mips_cpreturn_register
== -1)
12040 ex
.X_op
= O_constant
;
12041 ex
.X_add_symbol
= NULL
;
12042 ex
.X_op_symbol
= NULL
;
12043 ex
.X_add_number
= mips_cpreturn_offset
;
12045 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12048 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12049 mips_cpreturn_register
, 0);
12052 demand_empty_rest_of_line ();
12055 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12056 code. It sets the offset to use in gp_rel relocations. */
12059 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12061 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12062 We also need NewABI support. */
12063 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12069 mips_gprel_offset
= get_absolute_expression ();
12071 demand_empty_rest_of_line ();
12074 /* Handle the .gpword pseudo-op. This is used when generating PIC
12075 code. It generates a 32 bit GP relative reloc. */
12078 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12084 /* When not generating PIC code, this is treated as .word. */
12085 if (mips_pic
!= SVR4_PIC
)
12091 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12092 mips_emit_delays (TRUE
);
12094 mips_align (2, 0, label
);
12095 mips_clear_insn_labels ();
12099 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12101 as_bad (_("Unsupported use of .gpword"));
12102 ignore_rest_of_line ();
12106 md_number_to_chars (p
, 0, 4);
12107 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12108 BFD_RELOC_GPREL32
);
12110 demand_empty_rest_of_line ();
12114 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12120 /* When not generating PIC code, this is treated as .dword. */
12121 if (mips_pic
!= SVR4_PIC
)
12127 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12128 mips_emit_delays (TRUE
);
12130 mips_align (3, 0, label
);
12131 mips_clear_insn_labels ();
12135 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12137 as_bad (_("Unsupported use of .gpdword"));
12138 ignore_rest_of_line ();
12142 md_number_to_chars (p
, 0, 8);
12143 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12144 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12146 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12147 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12148 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12150 demand_empty_rest_of_line ();
12153 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12154 tables in SVR4 PIC code. */
12157 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12161 /* This is ignored when not generating SVR4 PIC code. */
12162 if (mips_pic
!= SVR4_PIC
)
12168 /* Add $gp to the register named as an argument. */
12170 reg
= tc_get_register (0);
12171 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12174 demand_empty_rest_of_line ();
12177 /* Handle the .insn pseudo-op. This marks instruction labels in
12178 mips16 mode. This permits the linker to handle them specially,
12179 such as generating jalx instructions when needed. We also make
12180 them odd for the duration of the assembly, in order to generate the
12181 right sort of code. We will make them even in the adjust_symtab
12182 routine, while leaving them marked. This is convenient for the
12183 debugger and the disassembler. The linker knows to make them odd
12187 s_insn (int ignore ATTRIBUTE_UNUSED
)
12189 mips16_mark_labels ();
12191 demand_empty_rest_of_line ();
12194 /* Handle a .stabn directive. We need these in order to mark a label
12195 as being a mips16 text label correctly. Sometimes the compiler
12196 will emit a label, followed by a .stabn, and then switch sections.
12197 If the label and .stabn are in mips16 mode, then the label is
12198 really a mips16 text label. */
12201 s_mips_stab (int type
)
12204 mips16_mark_labels ();
12209 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12213 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12220 name
= input_line_pointer
;
12221 c
= get_symbol_end ();
12222 symbolP
= symbol_find_or_make (name
);
12223 S_SET_WEAK (symbolP
);
12224 *input_line_pointer
= c
;
12226 SKIP_WHITESPACE ();
12228 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12230 if (S_IS_DEFINED (symbolP
))
12232 as_bad ("ignoring attempt to redefine symbol %s",
12233 S_GET_NAME (symbolP
));
12234 ignore_rest_of_line ();
12238 if (*input_line_pointer
== ',')
12240 ++input_line_pointer
;
12241 SKIP_WHITESPACE ();
12245 if (exp
.X_op
!= O_symbol
)
12247 as_bad ("bad .weakext directive");
12248 ignore_rest_of_line ();
12251 symbol_set_value_expression (symbolP
, &exp
);
12254 demand_empty_rest_of_line ();
12257 /* Parse a register string into a number. Called from the ECOFF code
12258 to parse .frame. The argument is non-zero if this is the frame
12259 register, so that we can record it in mips_frame_reg. */
12262 tc_get_register (int frame
)
12266 SKIP_WHITESPACE ();
12267 if (*input_line_pointer
++ != '$')
12269 as_warn (_("expected `$'"));
12272 else if (ISDIGIT (*input_line_pointer
))
12274 reg
= get_absolute_expression ();
12275 if (reg
< 0 || reg
>= 32)
12277 as_warn (_("Bad register number"));
12283 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12286 input_line_pointer
+= 2;
12288 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12291 input_line_pointer
+= 2;
12293 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12296 input_line_pointer
+= 2;
12298 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12301 input_line_pointer
+= 2;
12303 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12306 input_line_pointer
+= 2;
12308 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12311 input_line_pointer
+= 3;
12313 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12316 input_line_pointer
+= 3;
12318 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12321 input_line_pointer
+= 4;
12325 as_warn (_("Unrecognized register name"));
12327 while (ISALNUM(*input_line_pointer
))
12328 input_line_pointer
++;
12333 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12334 mips_frame_reg_valid
= 1;
12335 mips_cprestore_valid
= 0;
12341 md_section_align (asection
*seg
, valueT addr
)
12343 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12346 /* We don't need to align ELF sections to the full alignment.
12347 However, Irix 5 may prefer that we align them at least to a 16
12348 byte boundary. We don't bother to align the sections if we are
12349 targeted for an embedded system. */
12350 if (strcmp (TARGET_OS
, "elf") == 0)
12356 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12359 /* Utility routine, called from above as well. If called while the
12360 input file is still being read, it's only an approximation. (For
12361 example, a symbol may later become defined which appeared to be
12362 undefined earlier.) */
12365 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12370 if (g_switch_value
> 0)
12372 const char *symname
;
12375 /* Find out whether this symbol can be referenced off the $gp
12376 register. It can be if it is smaller than the -G size or if
12377 it is in the .sdata or .sbss section. Certain symbols can
12378 not be referenced off the $gp, although it appears as though
12380 symname
= S_GET_NAME (sym
);
12381 if (symname
!= (const char *) NULL
12382 && (strcmp (symname
, "eprol") == 0
12383 || strcmp (symname
, "etext") == 0
12384 || strcmp (symname
, "_gp") == 0
12385 || strcmp (symname
, "edata") == 0
12386 || strcmp (symname
, "_fbss") == 0
12387 || strcmp (symname
, "_fdata") == 0
12388 || strcmp (symname
, "_ftext") == 0
12389 || strcmp (symname
, "end") == 0
12390 || strcmp (symname
, "_gp_disp") == 0))
12392 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12394 #ifndef NO_ECOFF_DEBUGGING
12395 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12396 && (symbol_get_obj (sym
)->ecoff_extern_size
12397 <= g_switch_value
))
12399 /* We must defer this decision until after the whole
12400 file has been read, since there might be a .extern
12401 after the first use of this symbol. */
12402 || (before_relaxing
12403 #ifndef NO_ECOFF_DEBUGGING
12404 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12406 && S_GET_VALUE (sym
) == 0)
12407 || (S_GET_VALUE (sym
) != 0
12408 && S_GET_VALUE (sym
) <= g_switch_value
)))
12412 const char *segname
;
12414 segname
= segment_name (S_GET_SEGMENT (sym
));
12415 assert (strcmp (segname
, ".lit8") != 0
12416 && strcmp (segname
, ".lit4") != 0);
12417 change
= (strcmp (segname
, ".sdata") != 0
12418 && strcmp (segname
, ".sbss") != 0
12419 && strncmp (segname
, ".sdata.", 7) != 0
12420 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12425 /* We are not optimizing for the $gp register. */
12430 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12433 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12436 bfd_boolean linkonce
;
12438 /* Handle the case of a symbol equated to another symbol. */
12439 while (symbol_equated_reloc_p (sym
))
12443 /* It's possible to get a loop here in a badly written
12445 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12451 symsec
= S_GET_SEGMENT (sym
);
12453 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12455 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12457 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12461 /* The GNU toolchain uses an extension for ELF: a section
12462 beginning with the magic string .gnu.linkonce is a linkonce
12464 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12465 sizeof ".gnu.linkonce" - 1) == 0)
12469 /* This must duplicate the test in adjust_reloc_syms. */
12470 return (symsec
!= &bfd_und_section
12471 && symsec
!= &bfd_abs_section
12472 && ! bfd_is_com_section (symsec
)
12475 /* A global or weak symbol is treated as external. */
12476 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12477 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12483 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12484 extended opcode. SEC is the section the frag is in. */
12487 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12490 register const struct mips16_immed_operand
*op
;
12492 int mintiny
, maxtiny
;
12496 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12498 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12501 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12502 op
= mips16_immed_operands
;
12503 while (op
->type
!= type
)
12506 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12511 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12514 maxtiny
= 1 << op
->nbits
;
12519 maxtiny
= (1 << op
->nbits
) - 1;
12524 mintiny
= - (1 << (op
->nbits
- 1));
12525 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12528 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12529 val
= S_GET_VALUE (fragp
->fr_symbol
);
12530 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12536 /* We won't have the section when we are called from
12537 mips_relax_frag. However, we will always have been called
12538 from md_estimate_size_before_relax first. If this is a
12539 branch to a different section, we mark it as such. If SEC is
12540 NULL, and the frag is not marked, then it must be a branch to
12541 the same section. */
12544 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12549 /* Must have been called from md_estimate_size_before_relax. */
12552 fragp
->fr_subtype
=
12553 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12555 /* FIXME: We should support this, and let the linker
12556 catch branches and loads that are out of range. */
12557 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12558 _("unsupported PC relative reference to different section"));
12562 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12563 /* Assume non-extended on the first relaxation pass.
12564 The address we have calculated will be bogus if this is
12565 a forward branch to another frag, as the forward frag
12566 will have fr_address == 0. */
12570 /* In this case, we know for sure that the symbol fragment is in
12571 the same section. If the relax_marker of the symbol fragment
12572 differs from the relax_marker of this fragment, we have not
12573 yet adjusted the symbol fragment fr_address. We want to add
12574 in STRETCH in order to get a better estimate of the address.
12575 This particularly matters because of the shift bits. */
12577 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12581 /* Adjust stretch for any alignment frag. Note that if have
12582 been expanding the earlier code, the symbol may be
12583 defined in what appears to be an earlier frag. FIXME:
12584 This doesn't handle the fr_subtype field, which specifies
12585 a maximum number of bytes to skip when doing an
12587 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12589 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12592 stretch
= - ((- stretch
)
12593 & ~ ((1 << (int) f
->fr_offset
) - 1));
12595 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12604 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12606 /* The base address rules are complicated. The base address of
12607 a branch is the following instruction. The base address of a
12608 PC relative load or add is the instruction itself, but if it
12609 is in a delay slot (in which case it can not be extended) use
12610 the address of the instruction whose delay slot it is in. */
12611 if (type
== 'p' || type
== 'q')
12615 /* If we are currently assuming that this frag should be
12616 extended, then, the current address is two bytes
12618 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12621 /* Ignore the low bit in the target, since it will be set
12622 for a text label. */
12623 if ((val
& 1) != 0)
12626 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12628 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12631 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12633 /* Branch offsets have an implicit 0 in the lowest bit. */
12634 if (type
== 'p' || type
== 'q')
12637 /* If any of the shifted bits are set, we must use an extended
12638 opcode. If the address depends on the size of this
12639 instruction, this can lead to a loop, so we arrange to always
12640 use an extended opcode. We only check this when we are in
12641 the main relaxation loop, when SEC is NULL. */
12642 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12644 fragp
->fr_subtype
=
12645 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12649 /* If we are about to mark a frag as extended because the value
12650 is precisely maxtiny + 1, then there is a chance of an
12651 infinite loop as in the following code:
12656 In this case when the la is extended, foo is 0x3fc bytes
12657 away, so the la can be shrunk, but then foo is 0x400 away, so
12658 the la must be extended. To avoid this loop, we mark the
12659 frag as extended if it was small, and is about to become
12660 extended with a value of maxtiny + 1. */
12661 if (val
== ((maxtiny
+ 1) << op
->shift
)
12662 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12665 fragp
->fr_subtype
=
12666 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12670 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12671 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12673 if ((val
& ((1 << op
->shift
) - 1)) != 0
12674 || val
< (mintiny
<< op
->shift
)
12675 || val
> (maxtiny
<< op
->shift
))
12681 /* Compute the length of a branch sequence, and adjust the
12682 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12683 worst-case length is computed, with UPDATE being used to indicate
12684 whether an unconditional (-1), branch-likely (+1) or regular (0)
12685 branch is to be computed. */
12687 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12689 bfd_boolean toofar
;
12693 && S_IS_DEFINED (fragp
->fr_symbol
)
12694 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12699 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12701 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12705 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12708 /* If the symbol is not defined or it's in a different segment,
12709 assume the user knows what's going on and emit a short
12715 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12717 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12718 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12719 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12725 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12728 if (mips_pic
!= NO_PIC
)
12730 /* Additional space for PIC loading of target address. */
12732 if (mips_opts
.isa
== ISA_MIPS1
)
12733 /* Additional space for $at-stabilizing nop. */
12737 /* If branch is conditional. */
12738 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12745 /* Estimate the size of a frag before relaxing. Unless this is the
12746 mips16, we are not really relaxing here, and the final size is
12747 encoded in the subtype information. For the mips16, we have to
12748 decide whether we are using an extended opcode or not. */
12751 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12755 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12758 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12760 return fragp
->fr_var
;
12763 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12764 /* We don't want to modify the EXTENDED bit here; it might get us
12765 into infinite loops. We change it only in mips_relax_frag(). */
12766 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12768 if (mips_pic
== NO_PIC
)
12769 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12770 else if (mips_pic
== SVR4_PIC
)
12771 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12777 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12778 return -RELAX_FIRST (fragp
->fr_subtype
);
12781 return -RELAX_SECOND (fragp
->fr_subtype
);
12784 /* This is called to see whether a reloc against a defined symbol
12785 should be converted into a reloc against a section. */
12788 mips_fix_adjustable (fixS
*fixp
)
12790 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12791 about the format of the offset in the .o file. */
12792 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12795 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12796 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12799 if (fixp
->fx_addsy
== NULL
)
12802 /* If symbol SYM is in a mergeable section, relocations of the form
12803 SYM + 0 can usually be made section-relative. The mergeable data
12804 is then identified by the section offset rather than by the symbol.
12806 However, if we're generating REL LO16 relocations, the offset is split
12807 between the LO16 and parterning high part relocation. The linker will
12808 need to recalculate the complete offset in order to correctly identify
12811 The linker has traditionally not looked for the parterning high part
12812 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12813 placed anywhere. Rather than break backwards compatibility by changing
12814 this, it seems better not to force the issue, and instead keep the
12815 original symbol. This will work with either linker behavior. */
12816 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12817 && HAVE_IN_PLACE_ADDENDS
12818 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12822 /* Don't adjust relocations against mips16 symbols, so that the linker
12823 can find them if it needs to set up a stub. */
12824 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12825 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12826 && fixp
->fx_subsy
== NULL
)
12833 /* Translate internal representation of relocation info to BFD target
12837 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12839 static arelent
*retval
[4];
12841 bfd_reloc_code_real_type code
;
12843 memset (retval
, 0, sizeof(retval
));
12844 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12845 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12846 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12847 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12849 assert (! fixp
->fx_pcrel
);
12850 reloc
->addend
= fixp
->fx_addnumber
;
12852 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12853 entry to be used in the relocation's section offset. */
12854 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12856 reloc
->address
= reloc
->addend
;
12860 code
= fixp
->fx_r_type
;
12862 /* To support a PC relative reloc, we used a Cygnus extension.
12863 We check for that here to make sure that we don't let such a
12864 reloc escape normally. (FIXME: This was formerly used by
12865 embedded-PIC support, but is now used by branch handling in
12866 general. That probably should be fixed.) */
12867 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12868 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12869 && code
== BFD_RELOC_16_PCREL_S2
)
12870 reloc
->howto
= NULL
;
12872 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12874 if (reloc
->howto
== NULL
)
12876 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12877 _("Can not represent %s relocation in this object file format"),
12878 bfd_get_reloc_code_name (code
));
12885 /* Relax a machine dependent frag. This returns the amount by which
12886 the current size of the frag should change. */
12889 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12891 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12893 offsetT old_var
= fragp
->fr_var
;
12895 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12897 return fragp
->fr_var
- old_var
;
12900 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12903 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12905 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12907 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12912 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12914 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12921 /* Convert a machine dependent frag. */
12924 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12926 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12929 unsigned long insn
;
12933 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12935 if (target_big_endian
)
12936 insn
= bfd_getb32 (buf
);
12938 insn
= bfd_getl32 (buf
);
12940 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12942 /* We generate a fixup instead of applying it right now
12943 because, if there are linker relaxations, we're going to
12944 need the relocations. */
12945 exp
.X_op
= O_symbol
;
12946 exp
.X_add_symbol
= fragp
->fr_symbol
;
12947 exp
.X_add_number
= fragp
->fr_offset
;
12949 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12951 BFD_RELOC_16_PCREL_S2
);
12952 fixp
->fx_file
= fragp
->fr_file
;
12953 fixp
->fx_line
= fragp
->fr_line
;
12955 md_number_to_chars (buf
, insn
, 4);
12962 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12963 _("relaxed out-of-range branch into a jump"));
12965 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12968 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12970 /* Reverse the branch. */
12971 switch ((insn
>> 28) & 0xf)
12974 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12975 have the condition reversed by tweaking a single
12976 bit, and their opcodes all have 0x4???????. */
12977 assert ((insn
& 0xf1000000) == 0x41000000);
12978 insn
^= 0x00010000;
12982 /* bltz 0x04000000 bgez 0x04010000
12983 bltzal 0x04100000 bgezal 0x04110000 */
12984 assert ((insn
& 0xfc0e0000) == 0x04000000);
12985 insn
^= 0x00010000;
12989 /* beq 0x10000000 bne 0x14000000
12990 blez 0x18000000 bgtz 0x1c000000 */
12991 insn
^= 0x04000000;
12999 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13001 /* Clear the and-link bit. */
13002 assert ((insn
& 0xfc1c0000) == 0x04100000);
13004 /* bltzal 0x04100000 bgezal 0x04110000
13005 bltzall 0x04120000 bgezall 0x04130000 */
13006 insn
&= ~0x00100000;
13009 /* Branch over the branch (if the branch was likely) or the
13010 full jump (not likely case). Compute the offset from the
13011 current instruction to branch to. */
13012 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13016 /* How many bytes in instructions we've already emitted? */
13017 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13018 /* How many bytes in instructions from here to the end? */
13019 i
= fragp
->fr_var
- i
;
13021 /* Convert to instruction count. */
13023 /* Branch counts from the next instruction. */
13026 /* Branch over the jump. */
13027 md_number_to_chars (buf
, insn
, 4);
13031 md_number_to_chars (buf
, 0, 4);
13034 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13036 /* beql $0, $0, 2f */
13038 /* Compute the PC offset from the current instruction to
13039 the end of the variable frag. */
13040 /* How many bytes in instructions we've already emitted? */
13041 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13042 /* How many bytes in instructions from here to the end? */
13043 i
= fragp
->fr_var
- i
;
13044 /* Convert to instruction count. */
13046 /* Don't decrement i, because we want to branch over the
13050 md_number_to_chars (buf
, insn
, 4);
13053 md_number_to_chars (buf
, 0, 4);
13058 if (mips_pic
== NO_PIC
)
13061 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13062 ? 0x0c000000 : 0x08000000);
13063 exp
.X_op
= O_symbol
;
13064 exp
.X_add_symbol
= fragp
->fr_symbol
;
13065 exp
.X_add_number
= fragp
->fr_offset
;
13067 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13068 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13069 fixp
->fx_file
= fragp
->fr_file
;
13070 fixp
->fx_line
= fragp
->fr_line
;
13072 md_number_to_chars (buf
, insn
, 4);
13077 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13078 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13079 exp
.X_op
= O_symbol
;
13080 exp
.X_add_symbol
= fragp
->fr_symbol
;
13081 exp
.X_add_number
= fragp
->fr_offset
;
13083 if (fragp
->fr_offset
)
13085 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13086 exp
.X_add_number
= 0;
13089 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13090 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13091 fixp
->fx_file
= fragp
->fr_file
;
13092 fixp
->fx_line
= fragp
->fr_line
;
13094 md_number_to_chars (buf
, insn
, 4);
13097 if (mips_opts
.isa
== ISA_MIPS1
)
13100 md_number_to_chars (buf
, 0, 4);
13104 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13105 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13107 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13108 4, &exp
, 0, BFD_RELOC_LO16
);
13109 fixp
->fx_file
= fragp
->fr_file
;
13110 fixp
->fx_line
= fragp
->fr_line
;
13112 md_number_to_chars (buf
, insn
, 4);
13116 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13121 md_number_to_chars (buf
, insn
, 4);
13126 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13127 + fragp
->fr_fix
+ fragp
->fr_var
);
13129 fragp
->fr_fix
+= fragp
->fr_var
;
13134 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13137 register const struct mips16_immed_operand
*op
;
13138 bfd_boolean small
, ext
;
13141 unsigned long insn
;
13142 bfd_boolean use_extend
;
13143 unsigned short extend
;
13145 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13146 op
= mips16_immed_operands
;
13147 while (op
->type
!= type
)
13150 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13161 resolve_symbol_value (fragp
->fr_symbol
);
13162 val
= S_GET_VALUE (fragp
->fr_symbol
);
13167 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13169 /* The rules for the base address of a PC relative reloc are
13170 complicated; see mips16_extended_frag. */
13171 if (type
== 'p' || type
== 'q')
13176 /* Ignore the low bit in the target, since it will be
13177 set for a text label. */
13178 if ((val
& 1) != 0)
13181 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13183 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13186 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13189 /* Make sure the section winds up with the alignment we have
13192 record_alignment (asec
, op
->shift
);
13196 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13197 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13198 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13199 _("extended instruction in delay slot"));
13201 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13203 if (target_big_endian
)
13204 insn
= bfd_getb16 (buf
);
13206 insn
= bfd_getl16 (buf
);
13208 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13209 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13210 small
, ext
, &insn
, &use_extend
, &extend
);
13214 md_number_to_chars (buf
, 0xf000 | extend
, 2);
13215 fragp
->fr_fix
+= 2;
13219 md_number_to_chars (buf
, insn
, 2);
13220 fragp
->fr_fix
+= 2;
13228 first
= RELAX_FIRST (fragp
->fr_subtype
);
13229 second
= RELAX_SECOND (fragp
->fr_subtype
);
13230 fixp
= (fixS
*) fragp
->fr_opcode
;
13232 /* Possibly emit a warning if we've chosen the longer option. */
13233 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13234 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13236 const char *msg
= macro_warning (fragp
->fr_subtype
);
13238 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13241 /* Go through all the fixups for the first sequence. Disable them
13242 (by marking them as done) if we're going to use the second
13243 sequence instead. */
13245 && fixp
->fx_frag
== fragp
13246 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13248 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13250 fixp
= fixp
->fx_next
;
13253 /* Go through the fixups for the second sequence. Disable them if
13254 we're going to use the first sequence, otherwise adjust their
13255 addresses to account for the relaxation. */
13256 while (fixp
&& fixp
->fx_frag
== fragp
)
13258 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13259 fixp
->fx_where
-= first
;
13262 fixp
= fixp
->fx_next
;
13265 /* Now modify the frag contents. */
13266 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13270 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13271 memmove (start
, start
+ first
, second
);
13272 fragp
->fr_fix
-= first
;
13275 fragp
->fr_fix
-= second
;
13281 /* This function is called after the relocs have been generated.
13282 We've been storing mips16 text labels as odd. Here we convert them
13283 back to even for the convenience of the debugger. */
13286 mips_frob_file_after_relocs (void)
13289 unsigned int count
, i
;
13291 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13294 syms
= bfd_get_outsymbols (stdoutput
);
13295 count
= bfd_get_symcount (stdoutput
);
13296 for (i
= 0; i
< count
; i
++, syms
++)
13298 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13299 && ((*syms
)->value
& 1) != 0)
13301 (*syms
)->value
&= ~1;
13302 /* If the symbol has an odd size, it was probably computed
13303 incorrectly, so adjust that as well. */
13304 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13305 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13312 /* This function is called whenever a label is defined. It is used
13313 when handling branch delays; if a branch has a label, we assume we
13314 can not move it. */
13317 mips_define_label (symbolS
*sym
)
13319 struct insn_label_list
*l
;
13321 if (free_insn_labels
== NULL
)
13322 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13325 l
= free_insn_labels
;
13326 free_insn_labels
= l
->next
;
13330 l
->next
= insn_labels
;
13334 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13336 /* Some special processing for a MIPS ELF file. */
13339 mips_elf_final_processing (void)
13341 /* Write out the register information. */
13342 if (mips_abi
!= N64_ABI
)
13346 s
.ri_gprmask
= mips_gprmask
;
13347 s
.ri_cprmask
[0] = mips_cprmask
[0];
13348 s
.ri_cprmask
[1] = mips_cprmask
[1];
13349 s
.ri_cprmask
[2] = mips_cprmask
[2];
13350 s
.ri_cprmask
[3] = mips_cprmask
[3];
13351 /* The gp_value field is set by the MIPS ELF backend. */
13353 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13354 ((Elf32_External_RegInfo
*)
13355 mips_regmask_frag
));
13359 Elf64_Internal_RegInfo s
;
13361 s
.ri_gprmask
= mips_gprmask
;
13363 s
.ri_cprmask
[0] = mips_cprmask
[0];
13364 s
.ri_cprmask
[1] = mips_cprmask
[1];
13365 s
.ri_cprmask
[2] = mips_cprmask
[2];
13366 s
.ri_cprmask
[3] = mips_cprmask
[3];
13367 /* The gp_value field is set by the MIPS ELF backend. */
13369 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13370 ((Elf64_External_RegInfo
*)
13371 mips_regmask_frag
));
13374 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13375 sort of BFD interface for this. */
13376 if (mips_any_noreorder
)
13377 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13378 if (mips_pic
!= NO_PIC
)
13380 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13381 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13384 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13386 /* Set MIPS ELF flags for ASEs. */
13387 if (file_ase_mips16
)
13388 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13389 #if 0 /* XXX FIXME */
13390 if (file_ase_mips3d
)
13391 elf_elfheader (stdoutput
)->e_flags
|= ???;
13394 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13396 /* Set the MIPS ELF ABI flags. */
13397 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13398 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13399 else if (mips_abi
== O64_ABI
)
13400 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13401 else if (mips_abi
== EABI_ABI
)
13403 if (!file_mips_gp32
)
13404 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13406 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13408 else if (mips_abi
== N32_ABI
)
13409 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13411 /* Nothing to do for N64_ABI. */
13413 if (mips_32bitmode
)
13414 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13417 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13419 typedef struct proc
{
13421 unsigned long reg_mask
;
13422 unsigned long reg_offset
;
13423 unsigned long fpreg_mask
;
13424 unsigned long fpreg_offset
;
13425 unsigned long frame_offset
;
13426 unsigned long frame_reg
;
13427 unsigned long pc_reg
;
13430 static procS cur_proc
;
13431 static procS
*cur_proc_ptr
;
13432 static int numprocs
;
13434 /* Fill in an rs_align_code fragment. */
13437 mips_handle_align (fragS
*fragp
)
13439 if (fragp
->fr_type
!= rs_align_code
)
13442 if (mips_opts
.mips16
)
13444 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13445 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13450 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13451 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13459 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13463 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13467 md_obj_begin (void)
13474 /* check for premature end, nesting errors, etc */
13476 as_warn (_("missing .end at end of assembly"));
13485 if (*input_line_pointer
== '-')
13487 ++input_line_pointer
;
13490 if (!ISDIGIT (*input_line_pointer
))
13491 as_bad (_("expected simple number"));
13492 if (input_line_pointer
[0] == '0')
13494 if (input_line_pointer
[1] == 'x')
13496 input_line_pointer
+= 2;
13497 while (ISXDIGIT (*input_line_pointer
))
13500 val
|= hex_value (*input_line_pointer
++);
13502 return negative
? -val
: val
;
13506 ++input_line_pointer
;
13507 while (ISDIGIT (*input_line_pointer
))
13510 val
|= *input_line_pointer
++ - '0';
13512 return negative
? -val
: val
;
13515 if (!ISDIGIT (*input_line_pointer
))
13517 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13518 *input_line_pointer
, *input_line_pointer
);
13519 as_warn (_("invalid number"));
13522 while (ISDIGIT (*input_line_pointer
))
13525 val
+= *input_line_pointer
++ - '0';
13527 return negative
? -val
: val
;
13530 /* The .file directive; just like the usual .file directive, but there
13531 is an initial number which is the ECOFF file index. In the non-ECOFF
13532 case .file implies DWARF-2. */
13535 s_mips_file (int x ATTRIBUTE_UNUSED
)
13537 static int first_file_directive
= 0;
13539 if (ECOFF_DEBUGGING
)
13548 filename
= dwarf2_directive_file (0);
13550 /* Versions of GCC up to 3.1 start files with a ".file"
13551 directive even for stabs output. Make sure that this
13552 ".file" is handled. Note that you need a version of GCC
13553 after 3.1 in order to support DWARF-2 on MIPS. */
13554 if (filename
!= NULL
&& ! first_file_directive
)
13556 (void) new_logical_line (filename
, -1);
13557 s_app_file_string (filename
, 0);
13559 first_file_directive
= 1;
13563 /* The .loc directive, implying DWARF-2. */
13566 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13568 if (!ECOFF_DEBUGGING
)
13569 dwarf2_directive_loc (0);
13572 /* The .end directive. */
13575 s_mips_end (int x ATTRIBUTE_UNUSED
)
13579 /* Following functions need their own .frame and .cprestore directives. */
13580 mips_frame_reg_valid
= 0;
13581 mips_cprestore_valid
= 0;
13583 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13586 demand_empty_rest_of_line ();
13591 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13592 as_warn (_(".end not in text section"));
13596 as_warn (_(".end directive without a preceding .ent directive."));
13597 demand_empty_rest_of_line ();
13603 assert (S_GET_NAME (p
));
13604 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
13605 as_warn (_(".end symbol does not match .ent symbol."));
13607 if (debug_type
== DEBUG_STABS
)
13608 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13612 as_warn (_(".end directive missing or unknown symbol"));
13615 /* Generate a .pdr section. */
13616 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13619 segT saved_seg
= now_seg
;
13620 subsegT saved_subseg
= now_subseg
;
13625 dot
= frag_now_fix ();
13627 #ifdef md_flush_pending_output
13628 md_flush_pending_output ();
13632 subseg_set (pdr_seg
, 0);
13634 /* Write the symbol. */
13635 exp
.X_op
= O_symbol
;
13636 exp
.X_add_symbol
= p
;
13637 exp
.X_add_number
= 0;
13638 emit_expr (&exp
, 4);
13640 fragp
= frag_more (7 * 4);
13642 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13643 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13644 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13645 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13646 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13647 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13648 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13650 subseg_set (saved_seg
, saved_subseg
);
13652 #endif /* OBJ_ELF */
13654 cur_proc_ptr
= NULL
;
13657 /* The .aent and .ent directives. */
13660 s_mips_ent (int aent
)
13664 symbolP
= get_symbol ();
13665 if (*input_line_pointer
== ',')
13666 ++input_line_pointer
;
13667 SKIP_WHITESPACE ();
13668 if (ISDIGIT (*input_line_pointer
)
13669 || *input_line_pointer
== '-')
13672 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13673 as_warn (_(".ent or .aent not in text section."));
13675 if (!aent
&& cur_proc_ptr
)
13676 as_warn (_("missing .end"));
13680 /* This function needs its own .frame and .cprestore directives. */
13681 mips_frame_reg_valid
= 0;
13682 mips_cprestore_valid
= 0;
13684 cur_proc_ptr
= &cur_proc
;
13685 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13687 cur_proc_ptr
->isym
= symbolP
;
13689 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13693 if (debug_type
== DEBUG_STABS
)
13694 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13695 S_GET_NAME (symbolP
));
13698 demand_empty_rest_of_line ();
13701 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13702 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13703 s_mips_frame is used so that we can set the PDR information correctly.
13704 We can't use the ecoff routines because they make reference to the ecoff
13705 symbol table (in the mdebug section). */
13708 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13711 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13715 if (cur_proc_ptr
== (procS
*) NULL
)
13717 as_warn (_(".frame outside of .ent"));
13718 demand_empty_rest_of_line ();
13722 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13724 SKIP_WHITESPACE ();
13725 if (*input_line_pointer
++ != ','
13726 || get_absolute_expression_and_terminator (&val
) != ',')
13728 as_warn (_("Bad .frame directive"));
13729 --input_line_pointer
;
13730 demand_empty_rest_of_line ();
13734 cur_proc_ptr
->frame_offset
= val
;
13735 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13737 demand_empty_rest_of_line ();
13740 #endif /* OBJ_ELF */
13744 /* The .fmask and .mask directives. If the mdebug section is present
13745 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13746 embedded targets, s_mips_mask is used so that we can set the PDR
13747 information correctly. We can't use the ecoff routines because they
13748 make reference to the ecoff symbol table (in the mdebug section). */
13751 s_mips_mask (int reg_type
)
13754 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13758 if (cur_proc_ptr
== (procS
*) NULL
)
13760 as_warn (_(".mask/.fmask outside of .ent"));
13761 demand_empty_rest_of_line ();
13765 if (get_absolute_expression_and_terminator (&mask
) != ',')
13767 as_warn (_("Bad .mask/.fmask directive"));
13768 --input_line_pointer
;
13769 demand_empty_rest_of_line ();
13773 off
= get_absolute_expression ();
13775 if (reg_type
== 'F')
13777 cur_proc_ptr
->fpreg_mask
= mask
;
13778 cur_proc_ptr
->fpreg_offset
= off
;
13782 cur_proc_ptr
->reg_mask
= mask
;
13783 cur_proc_ptr
->reg_offset
= off
;
13786 demand_empty_rest_of_line ();
13789 #endif /* OBJ_ELF */
13790 s_ignore (reg_type
);
13793 /* A table describing all the processors gas knows about. Names are
13794 matched in the order listed.
13796 To ease comparison, please keep this table in the same order as
13797 gcc's mips_cpu_info_table[]. */
13798 static const struct mips_cpu_info mips_cpu_info_table
[] =
13800 /* Entries for generic ISAs */
13801 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13802 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13803 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13804 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13805 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13806 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13807 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13808 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13809 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13812 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13813 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13814 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13817 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13820 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13821 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13822 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13823 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13824 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13825 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13826 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13827 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13828 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13829 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13830 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13831 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13834 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13835 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13836 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13837 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13838 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13839 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13840 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13841 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13842 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13843 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13844 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13845 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13846 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13849 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13850 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13851 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13854 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13855 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13857 /* Broadcom SB-1 CPU core */
13858 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13865 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13866 with a final "000" replaced by "k". Ignore case.
13868 Note: this function is shared between GCC and GAS. */
13871 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13873 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13874 given
++, canonical
++;
13876 return ((*given
== 0 && *canonical
== 0)
13877 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13881 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13882 CPU name. We've traditionally allowed a lot of variation here.
13884 Note: this function is shared between GCC and GAS. */
13887 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13889 /* First see if the name matches exactly, or with a final "000"
13890 turned into "k". */
13891 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13894 /* If not, try comparing based on numerical designation alone.
13895 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13896 if (TOLOWER (*given
) == 'r')
13898 if (!ISDIGIT (*given
))
13901 /* Skip over some well-known prefixes in the canonical name,
13902 hoping to find a number there too. */
13903 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13905 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13907 else if (TOLOWER (canonical
[0]) == 'r')
13910 return mips_strict_matching_cpu_name_p (canonical
, given
);
13914 /* Parse an option that takes the name of a processor as its argument.
13915 OPTION is the name of the option and CPU_STRING is the argument.
13916 Return the corresponding processor enumeration if the CPU_STRING is
13917 recognized, otherwise report an error and return null.
13919 A similar function exists in GCC. */
13921 static const struct mips_cpu_info
*
13922 mips_parse_cpu (const char *option
, const char *cpu_string
)
13924 const struct mips_cpu_info
*p
;
13926 /* 'from-abi' selects the most compatible architecture for the given
13927 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13928 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13929 version. Look first at the -mgp options, if given, otherwise base
13930 the choice on MIPS_DEFAULT_64BIT.
13932 Treat NO_ABI like the EABIs. One reason to do this is that the
13933 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13934 architecture. This code picks MIPS I for 'mips' and MIPS III for
13935 'mips64', just as we did in the days before 'from-abi'. */
13936 if (strcasecmp (cpu_string
, "from-abi") == 0)
13938 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13939 return mips_cpu_info_from_isa (ISA_MIPS1
);
13941 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13942 return mips_cpu_info_from_isa (ISA_MIPS3
);
13944 if (file_mips_gp32
>= 0)
13945 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13947 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13952 /* 'default' has traditionally been a no-op. Probably not very useful. */
13953 if (strcasecmp (cpu_string
, "default") == 0)
13956 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13957 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13960 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13964 /* Return the canonical processor information for ISA (a member of the
13965 ISA_MIPS* enumeration). */
13967 static const struct mips_cpu_info
*
13968 mips_cpu_info_from_isa (int isa
)
13972 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13973 if (mips_cpu_info_table
[i
].is_isa
13974 && isa
== mips_cpu_info_table
[i
].isa
)
13975 return (&mips_cpu_info_table
[i
]);
13980 static const struct mips_cpu_info
*
13981 mips_cpu_info_from_arch (int arch
)
13985 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13986 if (arch
== mips_cpu_info_table
[i
].cpu
)
13987 return (&mips_cpu_info_table
[i
]);
13993 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
13997 fprintf (stream
, "%24s", "");
14002 fprintf (stream
, ", ");
14006 if (*col_p
+ strlen (string
) > 72)
14008 fprintf (stream
, "\n%24s", "");
14012 fprintf (stream
, "%s", string
);
14013 *col_p
+= strlen (string
);
14019 md_show_usage (FILE *stream
)
14024 fprintf (stream
, _("\
14026 -EB generate big endian output\n\
14027 -EL generate little endian output\n\
14028 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14029 -G NUM allow referencing objects up to NUM bytes\n\
14030 implicitly with the gp register [default 8]\n"));
14031 fprintf (stream
, _("\
14032 -mips1 generate MIPS ISA I instructions\n\
14033 -mips2 generate MIPS ISA II instructions\n\
14034 -mips3 generate MIPS ISA III instructions\n\
14035 -mips4 generate MIPS ISA IV instructions\n\
14036 -mips5 generate MIPS ISA V instructions\n\
14037 -mips32 generate MIPS32 ISA instructions\n\
14038 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14039 -mips64 generate MIPS64 ISA instructions\n\
14040 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14041 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14045 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14046 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14047 show (stream
, "from-abi", &column
, &first
);
14048 fputc ('\n', stream
);
14050 fprintf (stream
, _("\
14051 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14052 -no-mCPU don't generate code specific to CPU.\n\
14053 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14057 show (stream
, "3900", &column
, &first
);
14058 show (stream
, "4010", &column
, &first
);
14059 show (stream
, "4100", &column
, &first
);
14060 show (stream
, "4650", &column
, &first
);
14061 fputc ('\n', stream
);
14063 fprintf (stream
, _("\
14064 -mips16 generate mips16 instructions\n\
14065 -no-mips16 do not generate mips16 instructions\n"));
14066 fprintf (stream
, _("\
14067 -mfix-vr4120 work around certain VR4120 errata\n\
14068 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14069 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14070 -O0 remove unneeded NOPs, do not swap branches\n\
14071 -O remove unneeded NOPs and swap branches\n\
14072 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14073 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14074 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14076 fprintf (stream
, _("\
14077 -KPIC, -call_shared generate SVR4 position independent code\n\
14078 -non_shared do not generate position independent code\n\
14079 -xgot assume a 32 bit GOT\n\
14080 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14081 -mabi=ABI create ABI conformant object file for:\n"));
14085 show (stream
, "32", &column
, &first
);
14086 show (stream
, "o64", &column
, &first
);
14087 show (stream
, "n32", &column
, &first
);
14088 show (stream
, "64", &column
, &first
);
14089 show (stream
, "eabi", &column
, &first
);
14091 fputc ('\n', stream
);
14093 fprintf (stream
, _("\
14094 -32 create o32 ABI object file (default)\n\
14095 -n32 create n32 ABI object file\n\
14096 -64 create 64 ABI object file\n"));
14101 mips_dwarf2_format (void)
14103 if (mips_abi
== N64_ABI
)
14106 return dwarf2_format_64bit_irix
;
14108 return dwarf2_format_64bit
;
14112 return dwarf2_format_32bit
;
14116 mips_dwarf2_addr_size (void)
14118 if (mips_abi
== N64_ABI
)