1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* The name of the readonly data section. */
106 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
108 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
110 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
112 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
116 /* The ABI to use. */
127 /* MIPS ABI we are using for this output file. */
128 static enum mips_abi_level file_mips_abi
= NO_ABI
;
130 /* This is the set of options which may be modified by the .set
131 pseudo-op. We use a struct so that .set push and .set pop are more
134 struct mips_set_options
136 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
137 if it has not been initialized. Changed by `.set mipsN', and the
138 -mipsN command line option, and the default CPU. */
140 /* Enabled Application Specific Extensions (ASEs). These are set to -1
141 if they have not been initialized. Changed by `.set <asename>', by
142 command line options, and based on the default architecture. */
144 /* Whether we are assembling for the mips16 processor. 0 if we are
145 not, 1 if we are, and -1 if the value has not been initialized.
146 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
147 -nomips16 command line options, and the default CPU. */
149 /* Non-zero if we should not reorder instructions. Changed by `.set
150 reorder' and `.set noreorder'. */
152 /* Non-zero if we should not permit the $at ($1) register to be used
153 in instructions. Changed by `.set at' and `.set noat'. */
155 /* Non-zero if we should warn when a macro instruction expands into
156 more than one machine instruction. Changed by `.set nomacro' and
158 int warn_about_macros
;
159 /* Non-zero if we should not move instructions. Changed by `.set
160 move', `.set volatile', `.set nomove', and `.set novolatile'. */
162 /* Non-zero if we should not optimize branches by moving the target
163 of the branch into the delay slot. Actually, we don't perform
164 this optimization anyhow. Changed by `.set bopt' and `.set
167 /* Non-zero if we should not autoextend mips16 instructions.
168 Changed by `.set autoextend' and `.set noautoextend'. */
170 /* Restrict general purpose registers and floating point registers
171 to 32 bit. This is initially determined when -mgp32 or -mfp32
172 is passed but can changed if the assembler code uses .set mipsN. */
175 /* The ABI currently in use. This is changed by .set mipsN to loosen
176 restrictions and doesn't affect the whole file. */
177 enum mips_abi_level abi
;
180 /* True if -mgp32 was passed. */
181 static int file_mips_gp32
= -1;
183 /* True if -mfp32 was passed. */
184 static int file_mips_fp32
= -1;
186 /* This is the struct we use to hold the current set of options. Note
187 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
188 -1 to indicate that they have not been initialized. */
190 static struct mips_set_options mips_opts
=
192 ISA_UNKNOWN
, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
195 /* These variables are filled in with the masks of registers used.
196 The object format code reads them and puts them in the appropriate
198 unsigned long mips_gprmask
;
199 unsigned long mips_cprmask
[4];
201 /* MIPS ISA we are using for this output file. */
202 static int file_mips_isa
= ISA_UNKNOWN
;
204 /* True if -mips3d was passed or implied by arguments passed on the
205 command line (e.g., by -march). */
206 static int file_ase_mips3d
;
208 /* The argument of the -mcpu= flag. Historical for code generation. */
209 static int mips_cpu
= CPU_UNKNOWN
;
211 /* The argument of the -march= flag. The architecture we are assembling. */
212 static int mips_arch
= CPU_UNKNOWN
;
214 /* The argument of the -mtune= flag. The architecture for which we
216 static int mips_tune
= CPU_UNKNOWN
;
218 /* Whether we should mark the file EABI64 or EABI32. */
219 static int mips_eabi64
= 0;
221 /* If they asked for mips1 or mips2 and a cpu that is
222 mips3 or greater, then mark the object file 32BITMODE. */
223 static int mips_32bitmode
= 0;
225 /* Some ISA's have delay slots for instructions which read or write
226 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
227 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
228 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
229 delay slot in this ISA. The uses of this macro assume that any
230 ISA that has delay slots for one of these, has them for all. They
231 also assume that ISAs which don't have delays for these insns, don't
232 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
233 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
235 || (ISA) == ISA_MIPS2 \
236 || (ISA) == ISA_MIPS3 \
239 /* Return true if ISA supports 64 bit gp register instructions. */
240 #define ISA_HAS_64BIT_REGS(ISA) ( \
242 || (ISA) == ISA_MIPS4 \
243 || (ISA) == ISA_MIPS5 \
244 || (ISA) == ISA_MIPS64 \
247 #define HAVE_32BIT_GPRS \
249 || mips_opts.abi == O32_ABI \
250 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
252 #define HAVE_32BIT_FPRS \
254 || mips_opts.abi == O32_ABI \
255 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
257 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
258 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
260 #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI)
262 #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI)
264 /* We can only have 64bit addresses if the object file format
266 #define HAVE_32BIT_ADDRESSES \
268 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
269 || ! HAVE_64BIT_OBJECTS) \
270 && mips_pic != EMBEDDED_PIC))
272 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
274 /* Return true if the given CPU supports the MIPS3D ASE. */
275 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
278 /* Whether the processor uses hardware interlocks to protect
279 reads from the HI and LO registers, and thus does not
280 require nops to be inserted. */
282 #define hilo_interlocks (mips_arch == CPU_R4010 \
283 || mips_arch == CPU_SB1 \
286 /* Whether the processor uses hardware interlocks to protect reads
287 from the GPRs, and thus does not require nops to be inserted. */
288 #define gpr_interlocks \
289 (mips_opts.isa != ISA_MIPS1 \
290 || mips_arch == CPU_R3900)
292 /* As with other "interlocks" this is used by hardware that has FP
293 (co-processor) interlocks. */
294 /* Itbl support may require additional care here. */
295 #define cop_interlocks (mips_arch == CPU_R4300 \
296 || mips_arch == CPU_SB1 \
299 /* Is this a mfhi or mflo instruction? */
300 #define MF_HILO_INSN(PINFO) \
301 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
303 /* MIPS PIC level. */
307 /* Do not generate PIC code. */
310 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
311 not sure what it is supposed to do. */
314 /* Generate PIC code as in the SVR4 MIPS ABI. */
317 /* Generate PIC code without using a global offset table: the data
318 segment has a maximum size of 64K, all data references are off
319 the $gp register, and all text references are PC relative. This
320 is used on some embedded systems. */
324 static enum mips_pic_level mips_pic
;
326 /* Warn about all NOPS that the assembler generates. */
327 static int warn_nops
= 0;
329 /* 1 if we should generate 32 bit offsets from the $gp register in
330 SVR4_PIC mode. Currently has no meaning in other modes. */
331 static int mips_big_got
= 0;
333 /* 1 if trap instructions should used for overflow rather than break
335 static int mips_trap
= 0;
337 /* 1 if double width floating point constants should not be constructed
338 by assembling two single width halves into two single width floating
339 point registers which just happen to alias the double width destination
340 register. On some architectures this aliasing can be disabled by a bit
341 in the status register, and the setting of this bit cannot be determined
342 automatically at assemble time. */
343 static int mips_disable_float_construction
;
345 /* Non-zero if any .set noreorder directives were used. */
347 static int mips_any_noreorder
;
349 /* Non-zero if nops should be inserted when the register referenced in
350 an mfhi/mflo instruction is read in the next two instructions. */
351 static int mips_7000_hilo_fix
;
353 /* The size of the small data section. */
354 static unsigned int g_switch_value
= 8;
355 /* Whether the -G option was used. */
356 static int g_switch_seen
= 0;
361 /* If we can determine in advance that GP optimization won't be
362 possible, we can skip the relaxation stuff that tries to produce
363 GP-relative references. This makes delay slot optimization work
366 This function can only provide a guess, but it seems to work for
367 gcc output. It needs to guess right for gcc, otherwise gcc
368 will put what it thinks is a GP-relative instruction in a branch
371 I don't know if a fix is needed for the SVR4_PIC mode. I've only
372 fixed it for the non-PIC mode. KR 95/04/07 */
373 static int nopic_need_relax
PARAMS ((symbolS
*, int));
375 /* handle of the OPCODE hash table */
376 static struct hash_control
*op_hash
= NULL
;
378 /* The opcode hash table we use for the mips16. */
379 static struct hash_control
*mips16_op_hash
= NULL
;
381 /* This array holds the chars that always start a comment. If the
382 pre-processor is disabled, these aren't very useful */
383 const char comment_chars
[] = "#";
385 /* This array holds the chars that only start a comment at the beginning of
386 a line. If the line seems to have the form '# 123 filename'
387 .line and .file directives will appear in the pre-processed output */
388 /* Note that input_file.c hand checks for '#' at the beginning of the
389 first line of the input file. This is because the compiler outputs
390 #NO_APP at the beginning of its output. */
391 /* Also note that C style comments are always supported. */
392 const char line_comment_chars
[] = "#";
394 /* This array holds machine specific line separator characters. */
395 const char line_separator_chars
[] = ";";
397 /* Chars that can be used to separate mant from exp in floating point nums */
398 const char EXP_CHARS
[] = "eE";
400 /* Chars that mean this number is a floating point constant */
403 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
405 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
406 changed in read.c . Ideally it shouldn't have to know about it at all,
407 but nothing is ideal around here.
410 static char *insn_error
;
412 static int auto_align
= 1;
414 /* When outputting SVR4 PIC code, the assembler needs to know the
415 offset in the stack frame from which to restore the $gp register.
416 This is set by the .cprestore pseudo-op, and saved in this
418 static offsetT mips_cprestore_offset
= -1;
420 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
421 more optimizations, it can use a register value instead of a memory-saved
422 offset and even an other register than $gp as global pointer. */
423 static offsetT mips_cpreturn_offset
= -1;
424 static int mips_cpreturn_register
= -1;
425 static int mips_gp_register
= GP
;
426 static int mips_gprel_offset
= 0;
428 /* Whether mips_cprestore_offset has been set in the current function
429 (or whether it has already been warned about, if not). */
430 static int mips_cprestore_valid
= 0;
432 /* This is the register which holds the stack frame, as set by the
433 .frame pseudo-op. This is needed to implement .cprestore. */
434 static int mips_frame_reg
= SP
;
436 /* Whether mips_frame_reg has been set in the current function
437 (or whether it has already been warned about, if not). */
438 static int mips_frame_reg_valid
= 0;
440 /* To output NOP instructions correctly, we need to keep information
441 about the previous two instructions. */
443 /* Whether we are optimizing. The default value of 2 means to remove
444 unneeded NOPs and swap branch instructions when possible. A value
445 of 1 means to not swap branches. A value of 0 means to always
447 static int mips_optimize
= 2;
449 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
450 equivalent to seeing no -g option at all. */
451 static int mips_debug
= 0;
453 /* The previous instruction. */
454 static struct mips_cl_insn prev_insn
;
456 /* The instruction before prev_insn. */
457 static struct mips_cl_insn prev_prev_insn
;
459 /* If we don't want information for prev_insn or prev_prev_insn, we
460 point the insn_mo field at this dummy integer. */
461 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
463 /* Non-zero if prev_insn is valid. */
464 static int prev_insn_valid
;
466 /* The frag for the previous instruction. */
467 static struct frag
*prev_insn_frag
;
469 /* The offset into prev_insn_frag for the previous instruction. */
470 static long prev_insn_where
;
472 /* The reloc type for the previous instruction, if any. */
473 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
475 /* The reloc for the previous instruction, if any. */
476 static fixS
*prev_insn_fixp
[3];
478 /* Non-zero if the previous instruction was in a delay slot. */
479 static int prev_insn_is_delay_slot
;
481 /* Non-zero if the previous instruction was in a .set noreorder. */
482 static int prev_insn_unreordered
;
484 /* Non-zero if the previous instruction uses an extend opcode (if
486 static int prev_insn_extended
;
488 /* Non-zero if the previous previous instruction was in a .set
490 static int prev_prev_insn_unreordered
;
492 /* If this is set, it points to a frag holding nop instructions which
493 were inserted before the start of a noreorder section. If those
494 nops turn out to be unnecessary, the size of the frag can be
496 static fragS
*prev_nop_frag
;
498 /* The number of nop instructions we created in prev_nop_frag. */
499 static int prev_nop_frag_holds
;
501 /* The number of nop instructions that we know we need in
503 static int prev_nop_frag_required
;
505 /* The number of instructions we've seen since prev_nop_frag. */
506 static int prev_nop_frag_since
;
508 /* For ECOFF and ELF, relocations against symbols are done in two
509 parts, with a HI relocation and a LO relocation. Each relocation
510 has only 16 bits of space to store an addend. This means that in
511 order for the linker to handle carries correctly, it must be able
512 to locate both the HI and the LO relocation. This means that the
513 relocations must appear in order in the relocation table.
515 In order to implement this, we keep track of each unmatched HI
516 relocation. We then sort them so that they immediately precede the
517 corresponding LO relocation. */
522 struct mips_hi_fixup
*next
;
525 /* The section this fixup is in. */
529 /* The list of unmatched HI relocs. */
531 static struct mips_hi_fixup
*mips_hi_fixup_list
;
533 /* Map normal MIPS register numbers to mips16 register numbers. */
535 #define X ILLEGAL_REG
536 static const int mips32_to_16_reg_map
[] =
538 X
, X
, 2, 3, 4, 5, 6, 7,
539 X
, X
, X
, X
, X
, X
, X
, X
,
540 0, 1, X
, X
, X
, X
, X
, X
,
541 X
, X
, X
, X
, X
, X
, X
, X
545 /* Map mips16 register numbers to normal MIPS register numbers. */
547 static const unsigned int mips16_to_32_reg_map
[] =
549 16, 17, 2, 3, 4, 5, 6, 7
552 /* Since the MIPS does not have multiple forms of PC relative
553 instructions, we do not have to do relaxing as is done on other
554 platforms. However, we do have to handle GP relative addressing
555 correctly, which turns out to be a similar problem.
557 Every macro that refers to a symbol can occur in (at least) two
558 forms, one with GP relative addressing and one without. For
559 example, loading a global variable into a register generally uses
560 a macro instruction like this:
562 If i can be addressed off the GP register (this is true if it is in
563 the .sbss or .sdata section, or if it is known to be smaller than
564 the -G argument) this will generate the following instruction:
566 This instruction will use a GPREL reloc. If i can not be addressed
567 off the GP register, the following instruction sequence will be used:
570 In this case the first instruction will have a HI16 reloc, and the
571 second reloc will have a LO16 reloc. Both relocs will be against
574 The issue here is that we may not know whether i is GP addressable
575 until after we see the instruction that uses it. Therefore, we
576 want to be able to choose the final instruction sequence only at
577 the end of the assembly. This is similar to the way other
578 platforms choose the size of a PC relative instruction only at the
581 When generating position independent code we do not use GP
582 addressing in quite the same way, but the issue still arises as
583 external symbols and local symbols must be handled differently.
585 We handle these issues by actually generating both possible
586 instruction sequences. The longer one is put in a frag_var with
587 type rs_machine_dependent. We encode what to do with the frag in
588 the subtype field. We encode (1) the number of existing bytes to
589 replace, (2) the number of new bytes to use, (3) the offset from
590 the start of the existing bytes to the first reloc we must generate
591 (that is, the offset is applied from the start of the existing
592 bytes after they are replaced by the new bytes, if any), (4) the
593 offset from the start of the existing bytes to the second reloc,
594 (5) whether a third reloc is needed (the third reloc is always four
595 bytes after the second reloc), and (6) whether to warn if this
596 variant is used (this is sometimes needed if .set nomacro or .set
597 noat is in effect). All these numbers are reasonably small.
599 Generating two instruction sequences must be handled carefully to
600 ensure that delay slots are handled correctly. Fortunately, there
601 are a limited number of cases. When the second instruction
602 sequence is generated, append_insn is directed to maintain the
603 existing delay slot information, so it continues to apply to any
604 code after the second instruction sequence. This means that the
605 second instruction sequence must not impose any requirements not
606 required by the first instruction sequence.
608 These variant frags are then handled in functions called by the
609 machine independent code. md_estimate_size_before_relax returns
610 the final size of the frag. md_convert_frag sets up the final form
611 of the frag. tc_gen_reloc adjust the first reloc and adds a second
613 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
617 | (((reloc1) + 64) << 9) \
618 | (((reloc2) + 64) << 2) \
619 | ((reloc3) ? (1 << 1) : 0) \
621 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
622 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
623 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
624 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
625 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
626 #define RELAX_WARN(i) ((i) & 1)
628 /* For mips16 code, we use an entirely different form of relaxation.
629 mips16 supports two versions of most instructions which take
630 immediate values: a small one which takes some small value, and a
631 larger one which takes a 16 bit value. Since branches also follow
632 this pattern, relaxing these values is required.
634 We can assemble both mips16 and normal MIPS code in a single
635 object. Therefore, we need to support this type of relaxation at
636 the same time that we support the relaxation described above. We
637 use the high bit of the subtype field to distinguish these cases.
639 The information we store for this type of relaxation is the
640 argument code found in the opcode file for this relocation, whether
641 the user explicitly requested a small or extended form, and whether
642 the relocation is in a jump or jal delay slot. That tells us the
643 size of the value, and how it should be stored. We also store
644 whether the fragment is considered to be extended or not. We also
645 store whether this is known to be a branch to a different section,
646 whether we have tried to relax this frag yet, and whether we have
647 ever extended a PC relative fragment because of a shift count. */
648 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
651 | ((small) ? 0x100 : 0) \
652 | ((ext) ? 0x200 : 0) \
653 | ((dslot) ? 0x400 : 0) \
654 | ((jal_dslot) ? 0x800 : 0))
655 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
656 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
657 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
658 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
659 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
660 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
661 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
662 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
663 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
664 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
665 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
666 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
668 /* Prototypes for static functions. */
671 #define internalError() \
672 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
674 #define internalError() as_fatal (_("MIPS internal Error"));
677 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
679 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
680 unsigned int reg
, enum mips_regclass
class));
681 static int reg_needs_delay
PARAMS ((unsigned int));
682 static void mips16_mark_labels
PARAMS ((void));
683 static void append_insn
PARAMS ((char *place
,
684 struct mips_cl_insn
* ip
,
686 bfd_reloc_code_real_type
*r
,
688 static void mips_no_prev_insn
PARAMS ((int));
689 static void mips_emit_delays
PARAMS ((boolean
));
691 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
692 const char *name
, const char *fmt
,
695 static void macro_build ();
697 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
698 const char *, const char *,
700 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
701 expressionS
* ep
, int regnum
));
702 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
703 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
705 static void load_register
PARAMS ((int *, int, expressionS
*, int));
706 static void load_address
PARAMS ((int *, int, expressionS
*, int *));
707 static void move_register
PARAMS ((int *, int, int));
708 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
709 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
710 #ifdef LOSING_COMPILER
711 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
713 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
714 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
715 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
716 boolean
, boolean
, unsigned long *,
717 boolean
*, unsigned short *));
718 static int my_getPercentOp
PARAMS ((char **, unsigned int *, int *));
719 static int my_getSmallParser
PARAMS ((char **, unsigned int *, int *));
720 static int my_getSmallExpression
PARAMS ((expressionS
*, char *));
721 static void my_getExpression
PARAMS ((expressionS
*, char *));
723 static int support_64bit_objects
PARAMS((void));
725 static symbolS
*get_symbol
PARAMS ((void));
726 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
727 static void s_align
PARAMS ((int));
728 static void s_change_sec
PARAMS ((int));
729 static void s_cons
PARAMS ((int));
730 static void s_float_cons
PARAMS ((int));
731 static void s_mips_globl
PARAMS ((int));
732 static void s_option
PARAMS ((int));
733 static void s_mipsset
PARAMS ((int));
734 static void s_abicalls
PARAMS ((int));
735 static void s_cpload
PARAMS ((int));
736 static void s_cpsetup
PARAMS ((int));
737 static void s_cplocal
PARAMS ((int));
738 static void s_cprestore
PARAMS ((int));
739 static void s_cpreturn
PARAMS ((int));
740 static void s_gpvalue
PARAMS ((int));
741 static void s_gpword
PARAMS ((int));
742 static void s_cpadd
PARAMS ((int));
743 static void s_insn
PARAMS ((int));
744 static void md_obj_begin
PARAMS ((void));
745 static void md_obj_end
PARAMS ((void));
746 static long get_number
PARAMS ((void));
747 static void s_mips_ent
PARAMS ((int));
748 static void s_mips_end
PARAMS ((int));
749 static void s_mips_frame
PARAMS ((int));
750 static void s_mips_mask
PARAMS ((int));
751 static void s_mips_stab
PARAMS ((int));
752 static void s_mips_weakext
PARAMS ((int));
753 static void s_file
PARAMS ((int));
754 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
755 static const char *mips_isa_to_str
PARAMS ((int));
756 static const char *mips_cpu_to_str
PARAMS ((int));
757 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
758 static void show
PARAMS ((FILE *, char *, int *, int *));
760 static int mips_need_elf_addend_fixup
PARAMS ((fixS
*));
763 /* Return values of my_getSmallExpression(). */
770 /* Direct relocation creation by %percent_op(). */
789 /* Table and functions used to map between CPU/ISA names, and
790 ISA levels, and CPU numbers. */
794 const char *name
; /* CPU or ISA name. */
795 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
796 int isa
; /* ISA level. */
797 int cpu
; /* CPU number (default CPU if ISA). */
800 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
801 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
802 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
806 The following pseudo-ops from the Kane and Heinrich MIPS book
807 should be defined here, but are currently unsupported: .alias,
808 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
810 The following pseudo-ops from the Kane and Heinrich MIPS book are
811 specific to the type of debugging information being generated, and
812 should be defined by the object format: .aent, .begin, .bend,
813 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
816 The following pseudo-ops from the Kane and Heinrich MIPS book are
817 not MIPS CPU specific, but are also not specific to the object file
818 format. This file is probably the best place to define them, but
819 they are not currently supported: .asm0, .endr, .lab, .repeat,
822 static const pseudo_typeS mips_pseudo_table
[] =
824 /* MIPS specific pseudo-ops. */
825 {"option", s_option
, 0},
826 {"set", s_mipsset
, 0},
827 {"rdata", s_change_sec
, 'r'},
828 {"sdata", s_change_sec
, 's'},
829 {"livereg", s_ignore
, 0},
830 {"abicalls", s_abicalls
, 0},
831 {"cpload", s_cpload
, 0},
832 {"cpsetup", s_cpsetup
, 0},
833 {"cplocal", s_cplocal
, 0},
834 {"cprestore", s_cprestore
, 0},
835 {"cpreturn", s_cpreturn
, 0},
836 {"gpvalue", s_gpvalue
, 0},
837 {"gpword", s_gpword
, 0},
838 {"cpadd", s_cpadd
, 0},
841 /* Relatively generic pseudo-ops that happen to be used on MIPS
843 {"asciiz", stringer
, 1},
844 {"bss", s_change_sec
, 'b'},
847 {"dword", s_cons
, 3},
848 {"weakext", s_mips_weakext
, 0},
850 /* These pseudo-ops are defined in read.c, but must be overridden
851 here for one reason or another. */
852 {"align", s_align
, 0},
854 {"data", s_change_sec
, 'd'},
855 {"double", s_float_cons
, 'd'},
856 {"float", s_float_cons
, 'f'},
857 {"globl", s_mips_globl
, 0},
858 {"global", s_mips_globl
, 0},
859 {"hword", s_cons
, 1},
864 {"short", s_cons
, 1},
865 {"single", s_float_cons
, 'f'},
866 {"stabn", s_mips_stab
, 'n'},
867 {"text", s_change_sec
, 't'},
870 #ifdef MIPS_STABS_ELF
871 { "extern", ecoff_directive_extern
, 0},
877 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
879 /* These pseudo-ops should be defined by the object file format.
880 However, a.out doesn't support them, so we have versions here. */
881 {"aent", s_mips_ent
, 1},
882 {"bgnb", s_ignore
, 0},
883 {"end", s_mips_end
, 0},
884 {"endb", s_ignore
, 0},
885 {"ent", s_mips_ent
, 0},
887 {"fmask", s_mips_mask
, 'F'},
888 {"frame", s_mips_frame
, 0},
889 {"loc", s_ignore
, 0},
890 {"mask", s_mips_mask
, 'R'},
891 {"verstamp", s_ignore
, 0},
895 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
900 pop_insert (mips_pseudo_table
);
901 if (! ECOFF_DEBUGGING
)
902 pop_insert (mips_nonecoff_pseudo_table
);
905 /* Symbols labelling the current insn. */
907 struct insn_label_list
909 struct insn_label_list
*next
;
913 static struct insn_label_list
*insn_labels
;
914 static struct insn_label_list
*free_insn_labels
;
916 static void mips_clear_insn_labels
PARAMS ((void));
919 mips_clear_insn_labels ()
921 register struct insn_label_list
**pl
;
923 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
929 static char *expr_end
;
931 /* Expressions which appear in instructions. These are set by
934 static expressionS imm_expr
;
935 static expressionS offset_expr
;
937 /* Relocs associated with imm_expr and offset_expr. */
939 static bfd_reloc_code_real_type imm_reloc
[3]
940 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
941 static bfd_reloc_code_real_type offset_reloc
[3]
942 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
944 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
946 static boolean imm_unmatched_hi
;
948 /* These are set by mips16_ip if an explicit extension is used. */
950 static boolean mips16_small
, mips16_ext
;
952 #ifdef MIPS_STABS_ELF
953 /* The pdr segment for per procedure frame/regmask info */
959 mips_isa_to_str (isa
)
962 const struct mips_cpu_info
*ci
;
965 ci
= mips_cpu_info_from_isa (isa
);
969 sprintf (s
, "ISA#%d", isa
);
974 mips_cpu_to_str (cpu
)
977 const struct mips_cpu_info
*ci
;
980 ci
= mips_cpu_info_from_cpu (cpu
);
984 sprintf (s
, "CPU#%d", cpu
);
988 /* The default target format to use. */
991 mips_target_format ()
993 switch (OUTPUT_FLAVOR
)
995 case bfd_target_aout_flavour
:
996 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
997 case bfd_target_ecoff_flavour
:
998 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
999 case bfd_target_coff_flavour
:
1001 case bfd_target_elf_flavour
:
1003 /* This is traditional mips */
1004 return (target_big_endian
1005 ? (HAVE_64BIT_OBJECTS
? "elf64-tradbigmips"
1006 : "elf32-tradbigmips")
1007 : (HAVE_64BIT_OBJECTS
? "elf64-tradlittlemips"
1008 : "elf32-tradlittlemips"));
1010 return (target_big_endian
1011 ? (HAVE_64BIT_OBJECTS
? "elf64-bigmips" : "elf32-bigmips")
1012 : (HAVE_64BIT_OBJECTS
? "elf64-littlemips"
1013 : "elf32-littlemips"));
1021 /* This function is called once, at assembler startup time. It should
1022 set up all the tables, etc. that the MD part of the assembler will need. */
1027 register const char *retval
= NULL
;
1032 int mips_isa_from_cpu
;
1033 int target_cpu_had_mips16
= 0;
1034 const struct mips_cpu_info
*ci
;
1036 /* GP relative stuff not working for PE */
1037 if (strncmp (TARGET_OS
, "pe", 2) == 0
1038 && g_switch_value
!= 0)
1041 as_bad (_("-G not supported in this configuration."));
1046 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
1048 a
= xmalloc (sizeof TARGET_CPU
);
1049 strcpy (a
, TARGET_CPU
);
1050 a
[(sizeof TARGET_CPU
) - 3] = '\0';
1054 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
1056 target_cpu_had_mips16
= 1;
1057 cpu
+= sizeof "mips16" - 1;
1060 if (mips_opts
.mips16
< 0)
1061 mips_opts
.mips16
= target_cpu_had_mips16
;
1063 /* Backward compatibility for historic -mcpu= option. Check for
1064 incompatible options, warn if -mcpu is used. */
1065 if (mips_cpu
!= CPU_UNKNOWN
1066 && mips_arch
!= CPU_UNKNOWN
1067 && mips_cpu
!= mips_arch
)
1069 as_fatal (_("The -mcpu option can't be used together with -march. "
1070 "Use -mtune instead of -mcpu."));
1073 if (mips_cpu
!= CPU_UNKNOWN
1074 && mips_tune
!= CPU_UNKNOWN
1075 && mips_cpu
!= mips_tune
)
1077 as_fatal (_("The -mcpu option can't be used together with -mtune. "
1078 "Use -march instead of -mcpu."));
1082 /* For backward compatibility, let -mipsN set various defaults. */
1083 /* This code should go away, to be replaced with something rather more
1084 draconian. Until GCC 3.1 has been released for some reasonable
1085 amount of time, however, we need to support this. */
1086 if (mips_opts
.isa
!= ISA_UNKNOWN
)
1088 /* Translate -mipsN to the appropriate settings of file_mips_gp32
1089 and file_mips_fp32. Tag binaries as using the mipsN ISA. */
1090 if (file_mips_gp32
< 0)
1092 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1097 if (file_mips_fp32
< 0)
1099 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1105 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1106 assert (ci
!= NULL
);
1107 /* -mipsN has higher priority than -mcpu but lower than -march. */
1108 if (mips_arch
== CPU_UNKNOWN
)
1109 mips_arch
= ci
->cpu
;
1111 /* Default mips_abi. */
1112 if (mips_opts
.abi
== NO_ABI
)
1114 if (mips_opts
.isa
== ISA_MIPS1
|| mips_opts
.isa
== ISA_MIPS2
)
1115 mips_opts
.abi
= O32_ABI
;
1116 else if (mips_opts
.isa
== ISA_MIPS3
|| mips_opts
.isa
== ISA_MIPS4
)
1117 mips_opts
.abi
= O64_ABI
;
1121 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1123 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1124 assert (ci
!= NULL
);
1125 mips_arch
= ci
->cpu
;
1126 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1127 "-mtune instead."));
1130 /* Set tune from -mcpu, not from -mipsN. */
1131 if (mips_tune
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1133 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1134 assert (ci
!= NULL
);
1135 mips_tune
= ci
->cpu
;
1138 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1139 specified on the command line, or some other value if one was.
1140 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1141 the command line, or will be set otherwise if one was. */
1143 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1144 /* Handled above. */;
1146 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1148 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1149 assert (ci
!= NULL
);
1150 mips_arch
= ci
->cpu
;
1151 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1152 "-mtune instead."));
1155 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1156 specified on the command line, or some other value if one was.
1157 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1158 the command line, or will be set otherwise if one was. */
1160 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1162 /* We have to check if the isa is the default isa of arch. Otherwise
1163 we'll get invalid object file headers. */
1164 ci
= mips_cpu_info_from_cpu (mips_arch
);
1165 assert (ci
!= NULL
);
1166 if (mips_opts
.isa
!= ci
->isa
)
1168 /* This really should be an error instead of a warning, but old
1169 compilers only have -mcpu which sets both arch and tune. For
1170 now, we discard arch and preserve tune. */
1171 as_warn (_("The -march option is incompatible to -mipsN and "
1172 "therefore ignored."));
1173 if (mips_tune
== CPU_UNKNOWN
)
1174 mips_tune
= mips_arch
;
1175 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1176 assert (ci
!= NULL
);
1177 mips_arch
= ci
->cpu
;
1181 else if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
1183 /* We have ARCH, we need ISA. */
1184 ci
= mips_cpu_info_from_cpu (mips_arch
);
1185 assert (ci
!= NULL
);
1186 mips_opts
.isa
= ci
->isa
;
1188 else if (mips_arch
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1190 /* We have ISA, we need default ARCH. */
1191 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1192 assert (ci
!= NULL
);
1193 mips_arch
= ci
->cpu
;
1197 /* We need to set both ISA and ARCH from target cpu. */
1198 ci
= mips_cpu_info_from_name (cpu
);
1200 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
1201 assert (ci
!= NULL
);
1202 mips_opts
.isa
= ci
->isa
;
1203 mips_arch
= ci
->cpu
;
1206 if (mips_tune
== CPU_UNKNOWN
)
1207 mips_tune
= mips_arch
;
1209 ci
= mips_cpu_info_from_cpu (mips_arch
);
1210 assert (ci
!= NULL
);
1211 mips_isa_from_cpu
= ci
->isa
;
1213 /* End of TARGET_CPU processing, get rid of malloced memory
1222 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
1223 as_bad (_("trap exception not supported at ISA 1"));
1225 /* Set the EABI kind based on the ISA before the user gets
1226 to change the ISA with directives. This isn't really
1227 the best, but then neither is basing the abi on the isa. */
1228 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1229 && mips_opts
.abi
== EABI_ABI
)
1232 /* If they asked for mips1 or mips2 and a cpu that is
1233 mips3 or greater, then mark the object file 32BITMODE. */
1234 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1235 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1236 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1239 /* If the selected architecture includes support for ASEs, enable
1240 generation of code for them. */
1241 if (mips_opts
.ase_mips3d
== -1 && CPU_HAS_MIPS3D (mips_arch
))
1242 mips_opts
.ase_mips3d
= 1;
1244 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1245 as_warn (_("Could not set architecture and machine"));
1247 if (file_mips_gp32
< 0)
1249 if (file_mips_fp32
< 0)
1252 file_mips_isa
= mips_opts
.isa
;
1253 file_mips_abi
= mips_opts
.abi
;
1254 file_ase_mips3d
= mips_opts
.ase_mips3d
;
1255 mips_opts
.gp32
= file_mips_gp32
;
1256 mips_opts
.fp32
= file_mips_fp32
;
1258 op_hash
= hash_new ();
1260 for (i
= 0; i
< NUMOPCODES
;)
1262 const char *name
= mips_opcodes
[i
].name
;
1264 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1267 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1268 mips_opcodes
[i
].name
, retval
);
1269 /* Probably a memory allocation problem? Give up now. */
1270 as_fatal (_("Broken assembler. No assembly attempted."));
1274 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1276 if (!validate_mips_insn (&mips_opcodes
[i
]))
1281 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1284 mips16_op_hash
= hash_new ();
1287 while (i
< bfd_mips16_num_opcodes
)
1289 const char *name
= mips16_opcodes
[i
].name
;
1291 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1293 as_fatal (_("internal: can't hash `%s': %s"),
1294 mips16_opcodes
[i
].name
, retval
);
1297 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1298 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1299 != mips16_opcodes
[i
].match
))
1301 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1302 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1307 while (i
< bfd_mips16_num_opcodes
1308 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1312 as_fatal (_("Broken assembler. No assembly attempted."));
1314 /* We add all the general register names to the symbol table. This
1315 helps us detect invalid uses of them. */
1316 for (i
= 0; i
< 32; i
++)
1320 sprintf (buf
, "$%d", i
);
1321 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1322 &zero_address_frag
));
1324 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1325 &zero_address_frag
));
1326 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1327 &zero_address_frag
));
1328 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1329 &zero_address_frag
));
1330 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1331 &zero_address_frag
));
1332 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1333 &zero_address_frag
));
1334 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1335 &zero_address_frag
));
1336 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1337 &zero_address_frag
));
1339 mips_no_prev_insn (false);
1342 mips_cprmask
[0] = 0;
1343 mips_cprmask
[1] = 0;
1344 mips_cprmask
[2] = 0;
1345 mips_cprmask
[3] = 0;
1347 /* set the default alignment for the text section (2**2) */
1348 record_alignment (text_section
, 2);
1350 if (USE_GLOBAL_POINTER_OPT
)
1351 bfd_set_gp_size (stdoutput
, g_switch_value
);
1353 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1355 /* On a native system, sections must be aligned to 16 byte
1356 boundaries. When configured for an embedded ELF target, we
1358 if (strcmp (TARGET_OS
, "elf") != 0)
1360 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1361 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1362 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1365 /* Create a .reginfo section for register masks and a .mdebug
1366 section for debugging information. */
1374 subseg
= now_subseg
;
1376 /* The ABI says this section should be loaded so that the
1377 running program can access it. However, we don't load it
1378 if we are configured for an embedded target */
1379 flags
= SEC_READONLY
| SEC_DATA
;
1380 if (strcmp (TARGET_OS
, "elf") != 0)
1381 flags
|= SEC_ALLOC
| SEC_LOAD
;
1383 if (file_mips_abi
!= N64_ABI
)
1385 sec
= subseg_new (".reginfo", (subsegT
) 0);
1387 bfd_set_section_flags (stdoutput
, sec
, flags
);
1388 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1391 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1396 /* The 64-bit ABI uses a .MIPS.options section rather than
1397 .reginfo section. */
1398 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1399 bfd_set_section_flags (stdoutput
, sec
, flags
);
1400 bfd_set_section_alignment (stdoutput
, sec
, 3);
1403 /* Set up the option header. */
1405 Elf_Internal_Options opthdr
;
1408 opthdr
.kind
= ODK_REGINFO
;
1409 opthdr
.size
= (sizeof (Elf_External_Options
)
1410 + sizeof (Elf64_External_RegInfo
));
1413 f
= frag_more (sizeof (Elf_External_Options
));
1414 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1415 (Elf_External_Options
*) f
);
1417 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1422 if (ECOFF_DEBUGGING
)
1424 sec
= subseg_new (".mdebug", (subsegT
) 0);
1425 (void) bfd_set_section_flags (stdoutput
, sec
,
1426 SEC_HAS_CONTENTS
| SEC_READONLY
);
1427 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1430 #ifdef MIPS_STABS_ELF
1431 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1432 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1433 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1434 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1437 subseg_set (seg
, subseg
);
1441 if (! ECOFF_DEBUGGING
)
1448 if (! ECOFF_DEBUGGING
)
1456 struct mips_cl_insn insn
;
1457 bfd_reloc_code_real_type unused_reloc
[3]
1458 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1460 imm_expr
.X_op
= O_absent
;
1461 imm_unmatched_hi
= false;
1462 offset_expr
.X_op
= O_absent
;
1463 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1464 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1465 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1466 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1467 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1468 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1470 if (mips_opts
.mips16
)
1471 mips16_ip (str
, &insn
);
1474 mips_ip (str
, &insn
);
1475 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1476 str
, insn
.insn_opcode
));
1481 as_bad ("%s `%s'", insn_error
, str
);
1485 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1487 if (mips_opts
.mips16
)
1488 mips16_macro (&insn
);
1494 if (imm_expr
.X_op
!= O_absent
)
1495 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
, imm_unmatched_hi
);
1496 else if (offset_expr
.X_op
!= O_absent
)
1497 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1499 append_insn (NULL
, &insn
, NULL
, unused_reloc
, false);
1503 /* See whether instruction IP reads register REG. CLASS is the type
1507 insn_uses_reg (ip
, reg
, class)
1508 struct mips_cl_insn
*ip
;
1510 enum mips_regclass
class;
1512 if (class == MIPS16_REG
)
1514 assert (mips_opts
.mips16
);
1515 reg
= mips16_to_32_reg_map
[reg
];
1516 class = MIPS_GR_REG
;
1519 /* Don't report on general register 0, since it never changes. */
1520 if (class == MIPS_GR_REG
&& reg
== 0)
1523 if (class == MIPS_FP_REG
)
1525 assert (! mips_opts
.mips16
);
1526 /* If we are called with either $f0 or $f1, we must check $f0.
1527 This is not optimal, because it will introduce an unnecessary
1528 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1529 need to distinguish reading both $f0 and $f1 or just one of
1530 them. Note that we don't have to check the other way,
1531 because there is no instruction that sets both $f0 and $f1
1532 and requires a delay. */
1533 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1534 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1535 == (reg
&~ (unsigned) 1)))
1537 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1538 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1539 == (reg
&~ (unsigned) 1)))
1542 else if (! mips_opts
.mips16
)
1544 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1545 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1547 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1548 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1553 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1554 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1555 & MIPS16OP_MASK_RX
)]
1558 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1559 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1560 & MIPS16OP_MASK_RY
)]
1563 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1564 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1565 & MIPS16OP_MASK_MOVE32Z
)]
1568 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1570 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1572 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1574 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1575 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1576 & MIPS16OP_MASK_REGR32
) == reg
)
1583 /* This function returns true if modifying a register requires a
1587 reg_needs_delay (reg
)
1590 unsigned long prev_pinfo
;
1592 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1593 if (! mips_opts
.noreorder
1594 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1595 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1596 || (! gpr_interlocks
1597 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1599 /* A load from a coprocessor or from memory. All load
1600 delays delay the use of general register rt for one
1601 instruction on the r3000. The r6000 and r4000 use
1603 /* Itbl support may require additional care here. */
1604 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1605 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1612 /* Mark instruction labels in mips16 mode. This permits the linker to
1613 handle them specially, such as generating jalx instructions when
1614 needed. We also make them odd for the duration of the assembly, in
1615 order to generate the right sort of code. We will make them even
1616 in the adjust_symtab routine, while leaving them marked. This is
1617 convenient for the debugger and the disassembler. The linker knows
1618 to make them odd again. */
1621 mips16_mark_labels ()
1623 if (mips_opts
.mips16
)
1625 struct insn_label_list
*l
;
1628 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1631 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1632 S_SET_OTHER (l
->label
, STO_MIPS16
);
1634 val
= S_GET_VALUE (l
->label
);
1636 S_SET_VALUE (l
->label
, val
+ 1);
1641 /* Output an instruction. PLACE is where to put the instruction; if
1642 it is NULL, this uses frag_more to get room. IP is the instruction
1643 information. ADDRESS_EXPR is an operand of the instruction to be
1644 used with RELOC_TYPE. */
1647 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1649 struct mips_cl_insn
*ip
;
1650 expressionS
*address_expr
;
1651 bfd_reloc_code_real_type
*reloc_type
;
1652 boolean unmatched_hi
;
1654 register unsigned long prev_pinfo
, pinfo
;
1659 /* Mark instruction labels in mips16 mode. */
1660 mips16_mark_labels ();
1662 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1663 pinfo
= ip
->insn_mo
->pinfo
;
1665 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1669 /* If the previous insn required any delay slots, see if we need
1670 to insert a NOP or two. There are eight kinds of possible
1671 hazards, of which an instruction can have at most one type.
1672 (1) a load from memory delay
1673 (2) a load from a coprocessor delay
1674 (3) an unconditional branch delay
1675 (4) a conditional branch delay
1676 (5) a move to coprocessor register delay
1677 (6) a load coprocessor register from memory delay
1678 (7) a coprocessor condition code delay
1679 (8) a HI/LO special register delay
1681 There are a lot of optimizations we could do that we don't.
1682 In particular, we do not, in general, reorder instructions.
1683 If you use gcc with optimization, it will reorder
1684 instructions and generally do much more optimization then we
1685 do here; repeating all that work in the assembler would only
1686 benefit hand written assembly code, and does not seem worth
1689 /* This is how a NOP is emitted. */
1690 #define emit_nop() \
1692 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1693 : md_number_to_chars (frag_more (4), 0, 4))
1695 /* The previous insn might require a delay slot, depending upon
1696 the contents of the current insn. */
1697 if (! mips_opts
.mips16
1698 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1699 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1700 && ! cop_interlocks
)
1701 || (! gpr_interlocks
1702 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1704 /* A load from a coprocessor or from memory. All load
1705 delays delay the use of general register rt for one
1706 instruction on the r3000. The r6000 and r4000 use
1708 /* Itbl support may require additional care here. */
1709 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1710 if (mips_optimize
== 0
1711 || insn_uses_reg (ip
,
1712 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1717 else if (! mips_opts
.mips16
1718 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1719 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1720 && ! cop_interlocks
)
1721 || (mips_opts
.isa
== ISA_MIPS1
1722 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1724 /* A generic coprocessor delay. The previous instruction
1725 modified a coprocessor general or control register. If
1726 it modified a control register, we need to avoid any
1727 coprocessor instruction (this is probably not always
1728 required, but it sometimes is). If it modified a general
1729 register, we avoid using that register.
1731 On the r6000 and r4000 loading a coprocessor register
1732 from memory is interlocked, and does not require a delay.
1734 This case is not handled very well. There is no special
1735 knowledge of CP0 handling, and the coprocessors other
1736 than the floating point unit are not distinguished at
1738 /* Itbl support may require additional care here. FIXME!
1739 Need to modify this to include knowledge about
1740 user specified delays! */
1741 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1743 if (mips_optimize
== 0
1744 || insn_uses_reg (ip
,
1745 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1750 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1752 if (mips_optimize
== 0
1753 || insn_uses_reg (ip
,
1754 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1761 /* We don't know exactly what the previous instruction
1762 does. If the current instruction uses a coprocessor
1763 register, we must insert a NOP. If previous
1764 instruction may set the condition codes, and the
1765 current instruction uses them, we must insert two
1767 /* Itbl support may require additional care here. */
1768 if (mips_optimize
== 0
1769 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1770 && (pinfo
& INSN_READ_COND_CODE
)))
1772 else if (pinfo
& INSN_COP
)
1776 else if (! mips_opts
.mips16
1777 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1778 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1779 && ! cop_interlocks
)
1781 /* The previous instruction sets the coprocessor condition
1782 codes, but does not require a general coprocessor delay
1783 (this means it is a floating point comparison
1784 instruction). If this instruction uses the condition
1785 codes, we need to insert a single NOP. */
1786 /* Itbl support may require additional care here. */
1787 if (mips_optimize
== 0
1788 || (pinfo
& INSN_READ_COND_CODE
))
1792 /* If we're fixing up mfhi/mflo for the r7000 and the
1793 previous insn was an mfhi/mflo and the current insn
1794 reads the register that the mfhi/mflo wrote to, then
1797 else if (mips_7000_hilo_fix
1798 && MF_HILO_INSN (prev_pinfo
)
1799 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1806 /* If we're fixing up mfhi/mflo for the r7000 and the
1807 2nd previous insn was an mfhi/mflo and the current insn
1808 reads the register that the mfhi/mflo wrote to, then
1811 else if (mips_7000_hilo_fix
1812 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1813 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1821 else if (prev_pinfo
& INSN_READ_LO
)
1823 /* The previous instruction reads the LO register; if the
1824 current instruction writes to the LO register, we must
1825 insert two NOPS. Some newer processors have interlocks.
1826 Also the tx39's multiply instructions can be exectuted
1827 immediatly after a read from HI/LO (without the delay),
1828 though the tx39's divide insns still do require the
1830 if (! (hilo_interlocks
1831 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1832 && (mips_optimize
== 0
1833 || (pinfo
& INSN_WRITE_LO
)))
1835 /* Most mips16 branch insns don't have a delay slot.
1836 If a read from LO is immediately followed by a branch
1837 to a write to LO we have a read followed by a write
1838 less than 2 insns away. We assume the target of
1839 a branch might be a write to LO, and insert a nop
1840 between a read and an immediately following branch. */
1841 else if (mips_opts
.mips16
1842 && (mips_optimize
== 0
1843 || (pinfo
& MIPS16_INSN_BRANCH
)))
1846 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1848 /* The previous instruction reads the HI register; if the
1849 current instruction writes to the HI register, we must
1850 insert a NOP. Some newer processors have interlocks.
1851 Also the note tx39's multiply above. */
1852 if (! (hilo_interlocks
1853 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1854 && (mips_optimize
== 0
1855 || (pinfo
& INSN_WRITE_HI
)))
1857 /* Most mips16 branch insns don't have a delay slot.
1858 If a read from HI is immediately followed by a branch
1859 to a write to HI we have a read followed by a write
1860 less than 2 insns away. We assume the target of
1861 a branch might be a write to HI, and insert a nop
1862 between a read and an immediately following branch. */
1863 else if (mips_opts
.mips16
1864 && (mips_optimize
== 0
1865 || (pinfo
& MIPS16_INSN_BRANCH
)))
1869 /* If the previous instruction was in a noreorder section, then
1870 we don't want to insert the nop after all. */
1871 /* Itbl support may require additional care here. */
1872 if (prev_insn_unreordered
)
1875 /* There are two cases which require two intervening
1876 instructions: 1) setting the condition codes using a move to
1877 coprocessor instruction which requires a general coprocessor
1878 delay and then reading the condition codes 2) reading the HI
1879 or LO register and then writing to it (except on processors
1880 which have interlocks). If we are not already emitting a NOP
1881 instruction, we must check for these cases compared to the
1882 instruction previous to the previous instruction. */
1883 if ((! mips_opts
.mips16
1884 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1885 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1886 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1887 && (pinfo
& INSN_READ_COND_CODE
)
1888 && ! cop_interlocks
)
1889 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1890 && (pinfo
& INSN_WRITE_LO
)
1891 && ! (hilo_interlocks
1892 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1893 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1894 && (pinfo
& INSN_WRITE_HI
)
1895 && ! (hilo_interlocks
1896 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1901 if (prev_prev_insn_unreordered
)
1904 if (prev_prev_nop
&& nops
== 0)
1907 /* If we are being given a nop instruction, don't bother with
1908 one of the nops we would otherwise output. This will only
1909 happen when a nop instruction is used with mips_optimize set
1912 && ! mips_opts
.noreorder
1913 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1916 /* Now emit the right number of NOP instructions. */
1917 if (nops
> 0 && ! mips_opts
.noreorder
)
1920 unsigned long old_frag_offset
;
1922 struct insn_label_list
*l
;
1924 old_frag
= frag_now
;
1925 old_frag_offset
= frag_now_fix ();
1927 for (i
= 0; i
< nops
; i
++)
1932 listing_prev_line ();
1933 /* We may be at the start of a variant frag. In case we
1934 are, make sure there is enough space for the frag
1935 after the frags created by listing_prev_line. The
1936 argument to frag_grow here must be at least as large
1937 as the argument to all other calls to frag_grow in
1938 this file. We don't have to worry about being in the
1939 middle of a variant frag, because the variants insert
1940 all needed nop instructions themselves. */
1944 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1948 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1949 symbol_set_frag (l
->label
, frag_now
);
1950 val
= (valueT
) frag_now_fix ();
1951 /* mips16 text labels are stored as odd. */
1952 if (mips_opts
.mips16
)
1954 S_SET_VALUE (l
->label
, val
);
1957 #ifndef NO_ECOFF_DEBUGGING
1958 if (ECOFF_DEBUGGING
)
1959 ecoff_fix_loc (old_frag
, old_frag_offset
);
1962 else if (prev_nop_frag
!= NULL
)
1964 /* We have a frag holding nops we may be able to remove. If
1965 we don't need any nops, we can decrease the size of
1966 prev_nop_frag by the size of one instruction. If we do
1967 need some nops, we count them in prev_nops_required. */
1968 if (prev_nop_frag_since
== 0)
1972 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1973 --prev_nop_frag_holds
;
1976 prev_nop_frag_required
+= nops
;
1980 if (prev_prev_nop
== 0)
1982 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1983 --prev_nop_frag_holds
;
1986 ++prev_nop_frag_required
;
1989 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1990 prev_nop_frag
= NULL
;
1992 ++prev_nop_frag_since
;
1994 /* Sanity check: by the time we reach the second instruction
1995 after prev_nop_frag, we should have used up all the nops
1996 one way or another. */
1997 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2001 if (*reloc_type
> BFD_RELOC_UNUSED
)
2003 /* We need to set up a variant frag. */
2004 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2005 f
= frag_var (rs_machine_dependent
, 4, 0,
2006 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2007 mips16_small
, mips16_ext
,
2009 & INSN_UNCOND_BRANCH_DELAY
),
2010 (*prev_insn_reloc_type
2011 == BFD_RELOC_MIPS16_JMP
)),
2012 make_expr_symbol (address_expr
), 0, NULL
);
2014 else if (place
!= NULL
)
2016 else if (mips_opts
.mips16
2018 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2020 /* Make sure there is enough room to swap this instruction with
2021 a following jump instruction. */
2027 if (mips_opts
.mips16
2028 && mips_opts
.noreorder
2029 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2030 as_warn (_("extended instruction in delay slot"));
2035 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2036 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2038 if (address_expr
->X_op
== O_constant
)
2042 switch (*reloc_type
)
2045 ip
->insn_opcode
|= address_expr
->X_add_number
;
2048 case BFD_RELOC_MIPS_HIGHEST
:
2049 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
2051 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2054 case BFD_RELOC_MIPS_HIGHER
:
2055 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2056 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2059 case BFD_RELOC_HI16_S
:
2060 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2064 case BFD_RELOC_HI16
:
2065 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2068 case BFD_RELOC_LO16
:
2069 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2072 case BFD_RELOC_MIPS_JMP
:
2073 if ((address_expr
->X_add_number
& 3) != 0)
2074 as_bad (_("jump to misaligned address (0x%lx)"),
2075 (unsigned long) address_expr
->X_add_number
);
2076 if (address_expr
->X_add_number
& ~0xfffffff
2077 || address_expr
->X_add_number
> 0x7fffffc)
2078 as_bad (_("jump address range overflow (0x%lx)"),
2079 (unsigned long) address_expr
->X_add_number
);
2080 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2083 case BFD_RELOC_MIPS16_JMP
:
2084 if ((address_expr
->X_add_number
& 3) != 0)
2085 as_bad (_("jump to misaligned address (0x%lx)"),
2086 (unsigned long) address_expr
->X_add_number
);
2087 if (address_expr
->X_add_number
& ~0xfffffff
2088 || address_expr
->X_add_number
> 0x7fffffc)
2089 as_bad (_("jump address range overflow (0x%lx)"),
2090 (unsigned long) address_expr
->X_add_number
);
2092 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2093 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2094 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2097 case BFD_RELOC_16_PCREL
:
2098 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2101 case BFD_RELOC_16_PCREL_S2
:
2111 /* Don't generate a reloc if we are writing into a variant frag. */
2114 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
2116 (*reloc_type
== BFD_RELOC_16_PCREL
2117 || *reloc_type
== BFD_RELOC_16_PCREL_S2
),
2120 /* These relocations can have an addend that won't fit in
2121 4 octets for 64bit assembly. */
2122 if (HAVE_64BIT_GPRS
&&
2123 (*reloc_type
== BFD_RELOC_16
2124 || *reloc_type
== BFD_RELOC_32
2125 || *reloc_type
== BFD_RELOC_MIPS_JMP
2126 || *reloc_type
== BFD_RELOC_HI16_S
2127 || *reloc_type
== BFD_RELOC_LO16
2128 || *reloc_type
== BFD_RELOC_GPREL16
2129 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2130 || *reloc_type
== BFD_RELOC_GPREL32
2131 || *reloc_type
== BFD_RELOC_64
2132 || *reloc_type
== BFD_RELOC_CTOR
2133 || *reloc_type
== BFD_RELOC_MIPS_SUB
2134 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2135 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2136 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2137 || *reloc_type
== BFD_RELOC_MIPS_REL16
2138 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2139 fixp
[0]->fx_no_overflow
= 1;
2143 struct mips_hi_fixup
*hi_fixup
;
2145 assert (*reloc_type
== BFD_RELOC_HI16_S
);
2146 hi_fixup
= ((struct mips_hi_fixup
*)
2147 xmalloc (sizeof (struct mips_hi_fixup
)));
2148 hi_fixup
->fixp
= fixp
[0];
2149 hi_fixup
->seg
= now_seg
;
2150 hi_fixup
->next
= mips_hi_fixup_list
;
2151 mips_hi_fixup_list
= hi_fixup
;
2154 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2156 /* FIXME: This symbol can be one of
2157 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2158 address_expr
->X_op
= O_absent
;
2159 address_expr
->X_add_symbol
= 0;
2160 address_expr
->X_add_number
= 0;
2162 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2163 4, address_expr
, false,
2166 /* These relocations can have an addend that won't fit in
2167 4 octets for 64bit assembly. */
2168 if (HAVE_64BIT_GPRS
&&
2169 (*reloc_type
== BFD_RELOC_16
2170 || *reloc_type
== BFD_RELOC_32
2171 || *reloc_type
== BFD_RELOC_MIPS_JMP
2172 || *reloc_type
== BFD_RELOC_HI16_S
2173 || *reloc_type
== BFD_RELOC_LO16
2174 || *reloc_type
== BFD_RELOC_GPREL16
2175 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2176 || *reloc_type
== BFD_RELOC_GPREL32
2177 || *reloc_type
== BFD_RELOC_64
2178 || *reloc_type
== BFD_RELOC_CTOR
2179 || *reloc_type
== BFD_RELOC_MIPS_SUB
2180 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2181 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2182 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2183 || *reloc_type
== BFD_RELOC_MIPS_REL16
2184 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2185 fixp
[1]->fx_no_overflow
= 1;
2187 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2189 address_expr
->X_op
= O_absent
;
2190 address_expr
->X_add_symbol
= 0;
2191 address_expr
->X_add_number
= 0;
2193 fixp
[2] = fix_new_exp (frag_now
,
2194 f
- frag_now
->fr_literal
, 4,
2195 address_expr
, false,
2198 /* These relocations can have an addend that won't fit in
2199 4 octets for 64bit assembly. */
2200 if (HAVE_64BIT_GPRS
&&
2201 (*reloc_type
== BFD_RELOC_16
2202 || *reloc_type
== BFD_RELOC_32
2203 || *reloc_type
== BFD_RELOC_MIPS_JMP
2204 || *reloc_type
== BFD_RELOC_HI16_S
2205 || *reloc_type
== BFD_RELOC_LO16
2206 || *reloc_type
== BFD_RELOC_GPREL16
2207 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2208 || *reloc_type
== BFD_RELOC_GPREL32
2209 || *reloc_type
== BFD_RELOC_64
2210 || *reloc_type
== BFD_RELOC_CTOR
2211 || *reloc_type
== BFD_RELOC_MIPS_SUB
2212 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2213 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2214 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2215 || *reloc_type
== BFD_RELOC_MIPS_REL16
2216 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2217 fixp
[2]->fx_no_overflow
= 1;
2224 if (! mips_opts
.mips16
)
2225 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2226 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2228 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2229 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2235 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2238 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2241 /* Update the register mask information. */
2242 if (! mips_opts
.mips16
)
2244 if (pinfo
& INSN_WRITE_GPR_D
)
2245 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2246 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2247 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2248 if (pinfo
& INSN_READ_GPR_S
)
2249 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2250 if (pinfo
& INSN_WRITE_GPR_31
)
2251 mips_gprmask
|= 1 << RA
;
2252 if (pinfo
& INSN_WRITE_FPR_D
)
2253 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2254 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2255 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2256 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2257 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2258 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2259 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2260 if (pinfo
& INSN_COP
)
2262 /* We don't keep enough information to sort these cases out.
2263 The itbl support does keep this information however, although
2264 we currently don't support itbl fprmats as part of the cop
2265 instruction. May want to add this support in the future. */
2267 /* Never set the bit for $0, which is always zero. */
2268 mips_gprmask
&= ~1 << 0;
2272 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2273 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2274 & MIPS16OP_MASK_RX
);
2275 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2276 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2277 & MIPS16OP_MASK_RY
);
2278 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2279 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2280 & MIPS16OP_MASK_RZ
);
2281 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2282 mips_gprmask
|= 1 << TREG
;
2283 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2284 mips_gprmask
|= 1 << SP
;
2285 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2286 mips_gprmask
|= 1 << RA
;
2287 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2288 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2289 if (pinfo
& MIPS16_INSN_READ_Z
)
2290 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2291 & MIPS16OP_MASK_MOVE32Z
);
2292 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2293 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2294 & MIPS16OP_MASK_REGR32
);
2297 if (place
== NULL
&& ! mips_opts
.noreorder
)
2299 /* Filling the branch delay slot is more complex. We try to
2300 switch the branch with the previous instruction, which we can
2301 do if the previous instruction does not set up a condition
2302 that the branch tests and if the branch is not itself the
2303 target of any branch. */
2304 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2305 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2307 if (mips_optimize
< 2
2308 /* If we have seen .set volatile or .set nomove, don't
2310 || mips_opts
.nomove
!= 0
2311 /* If we had to emit any NOP instructions, then we
2312 already know we can not swap. */
2314 /* If we don't even know the previous insn, we can not
2316 || ! prev_insn_valid
2317 /* If the previous insn is already in a branch delay
2318 slot, then we can not swap. */
2319 || prev_insn_is_delay_slot
2320 /* If the previous previous insn was in a .set
2321 noreorder, we can't swap. Actually, the MIPS
2322 assembler will swap in this situation. However, gcc
2323 configured -with-gnu-as will generate code like
2329 in which we can not swap the bne and INSN. If gcc is
2330 not configured -with-gnu-as, it does not output the
2331 .set pseudo-ops. We don't have to check
2332 prev_insn_unreordered, because prev_insn_valid will
2333 be 0 in that case. We don't want to use
2334 prev_prev_insn_valid, because we do want to be able
2335 to swap at the start of a function. */
2336 || prev_prev_insn_unreordered
2337 /* If the branch is itself the target of a branch, we
2338 can not swap. We cheat on this; all we check for is
2339 whether there is a label on this instruction. If
2340 there are any branches to anything other than a
2341 label, users must use .set noreorder. */
2342 || insn_labels
!= NULL
2343 /* If the previous instruction is in a variant frag, we
2344 can not do the swap. This does not apply to the
2345 mips16, which uses variant frags for different
2347 || (! mips_opts
.mips16
2348 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2349 /* If the branch reads the condition codes, we don't
2350 even try to swap, because in the sequence
2355 we can not swap, and I don't feel like handling that
2357 || (! mips_opts
.mips16
2358 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2359 && (pinfo
& INSN_READ_COND_CODE
))
2360 /* We can not swap with an instruction that requires a
2361 delay slot, becase the target of the branch might
2362 interfere with that instruction. */
2363 || (! mips_opts
.mips16
2364 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2366 /* Itbl support may require additional care here. */
2367 & (INSN_LOAD_COPROC_DELAY
2368 | INSN_COPROC_MOVE_DELAY
2369 | INSN_WRITE_COND_CODE
)))
2370 || (! (hilo_interlocks
2371 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2375 || (! mips_opts
.mips16
2377 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2378 || (! mips_opts
.mips16
2379 && mips_opts
.isa
== ISA_MIPS1
2380 /* Itbl support may require additional care here. */
2381 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2382 /* We can not swap with a branch instruction. */
2384 & (INSN_UNCOND_BRANCH_DELAY
2385 | INSN_COND_BRANCH_DELAY
2386 | INSN_COND_BRANCH_LIKELY
))
2387 /* We do not swap with a trap instruction, since it
2388 complicates trap handlers to have the trap
2389 instruction be in a delay slot. */
2390 || (prev_pinfo
& INSN_TRAP
)
2391 /* If the branch reads a register that the previous
2392 instruction sets, we can not swap. */
2393 || (! mips_opts
.mips16
2394 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2395 && insn_uses_reg (ip
,
2396 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2399 || (! mips_opts
.mips16
2400 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2401 && insn_uses_reg (ip
,
2402 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2405 || (mips_opts
.mips16
2406 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2407 && insn_uses_reg (ip
,
2408 ((prev_insn
.insn_opcode
2410 & MIPS16OP_MASK_RX
),
2412 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2413 && insn_uses_reg (ip
,
2414 ((prev_insn
.insn_opcode
2416 & MIPS16OP_MASK_RY
),
2418 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2419 && insn_uses_reg (ip
,
2420 ((prev_insn
.insn_opcode
2422 & MIPS16OP_MASK_RZ
),
2424 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2425 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2426 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2427 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2428 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2429 && insn_uses_reg (ip
,
2430 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2433 /* If the branch writes a register that the previous
2434 instruction sets, we can not swap (we know that
2435 branches write only to RD or to $31). */
2436 || (! mips_opts
.mips16
2437 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2438 && (((pinfo
& INSN_WRITE_GPR_D
)
2439 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2440 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2441 || ((pinfo
& INSN_WRITE_GPR_31
)
2442 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2445 || (! mips_opts
.mips16
2446 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2447 && (((pinfo
& INSN_WRITE_GPR_D
)
2448 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2449 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2450 || ((pinfo
& INSN_WRITE_GPR_31
)
2451 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2454 || (mips_opts
.mips16
2455 && (pinfo
& MIPS16_INSN_WRITE_31
)
2456 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2457 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2458 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2460 /* If the branch writes a register that the previous
2461 instruction reads, we can not swap (we know that
2462 branches only write to RD or to $31). */
2463 || (! mips_opts
.mips16
2464 && (pinfo
& INSN_WRITE_GPR_D
)
2465 && insn_uses_reg (&prev_insn
,
2466 ((ip
->insn_opcode
>> OP_SH_RD
)
2469 || (! mips_opts
.mips16
2470 && (pinfo
& INSN_WRITE_GPR_31
)
2471 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2472 || (mips_opts
.mips16
2473 && (pinfo
& MIPS16_INSN_WRITE_31
)
2474 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2475 /* If we are generating embedded PIC code, the branch
2476 might be expanded into a sequence which uses $at, so
2477 we can't swap with an instruction which reads it. */
2478 || (mips_pic
== EMBEDDED_PIC
2479 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2480 /* If the previous previous instruction has a load
2481 delay, and sets a register that the branch reads, we
2483 || (! mips_opts
.mips16
2484 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2485 /* Itbl support may require additional care here. */
2486 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2487 || (! gpr_interlocks
2488 && (prev_prev_insn
.insn_mo
->pinfo
2489 & INSN_LOAD_MEMORY_DELAY
)))
2490 && insn_uses_reg (ip
,
2491 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2494 /* If one instruction sets a condition code and the
2495 other one uses a condition code, we can not swap. */
2496 || ((pinfo
& INSN_READ_COND_CODE
)
2497 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2498 || ((pinfo
& INSN_WRITE_COND_CODE
)
2499 && (prev_pinfo
& INSN_READ_COND_CODE
))
2500 /* If the previous instruction uses the PC, we can not
2502 || (mips_opts
.mips16
2503 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2504 /* If the previous instruction was extended, we can not
2506 || (mips_opts
.mips16
&& prev_insn_extended
)
2507 /* If the previous instruction had a fixup in mips16
2508 mode, we can not swap. This normally means that the
2509 previous instruction was a 4 byte branch anyhow. */
2510 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2511 /* If the previous instruction is a sync, sync.l, or
2512 sync.p, we can not swap. */
2513 || (prev_pinfo
& INSN_SYNC
))
2515 /* We could do even better for unconditional branches to
2516 portions of this object file; we could pick up the
2517 instruction at the destination, put it in the delay
2518 slot, and bump the destination address. */
2520 /* Update the previous insn information. */
2521 prev_prev_insn
= *ip
;
2522 prev_insn
.insn_mo
= &dummy_opcode
;
2526 /* It looks like we can actually do the swap. */
2527 if (! mips_opts
.mips16
)
2532 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2533 memcpy (temp
, prev_f
, 4);
2534 memcpy (prev_f
, f
, 4);
2535 memcpy (f
, temp
, 4);
2536 if (prev_insn_fixp
[0])
2538 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2539 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2541 if (prev_insn_fixp
[1])
2543 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2544 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2546 if (prev_insn_fixp
[2])
2548 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2549 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2553 fixp
[0]->fx_frag
= prev_insn_frag
;
2554 fixp
[0]->fx_where
= prev_insn_where
;
2558 fixp
[1]->fx_frag
= prev_insn_frag
;
2559 fixp
[1]->fx_where
= prev_insn_where
;
2563 fixp
[2]->fx_frag
= prev_insn_frag
;
2564 fixp
[2]->fx_where
= prev_insn_where
;
2572 assert (prev_insn_fixp
[0] == NULL
);
2573 assert (prev_insn_fixp
[1] == NULL
);
2574 assert (prev_insn_fixp
[2] == NULL
);
2575 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2576 memcpy (temp
, prev_f
, 2);
2577 memcpy (prev_f
, f
, 2);
2578 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2580 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2581 memcpy (f
, temp
, 2);
2585 memcpy (f
, f
+ 2, 2);
2586 memcpy (f
+ 2, temp
, 2);
2590 fixp
[0]->fx_frag
= prev_insn_frag
;
2591 fixp
[0]->fx_where
= prev_insn_where
;
2595 fixp
[1]->fx_frag
= prev_insn_frag
;
2596 fixp
[1]->fx_where
= prev_insn_where
;
2600 fixp
[2]->fx_frag
= prev_insn_frag
;
2601 fixp
[2]->fx_where
= prev_insn_where
;
2605 /* Update the previous insn information; leave prev_insn
2607 prev_prev_insn
= *ip
;
2609 prev_insn_is_delay_slot
= 1;
2611 /* If that was an unconditional branch, forget the previous
2612 insn information. */
2613 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2615 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2616 prev_insn
.insn_mo
= &dummy_opcode
;
2619 prev_insn_fixp
[0] = NULL
;
2620 prev_insn_fixp
[1] = NULL
;
2621 prev_insn_fixp
[2] = NULL
;
2622 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2623 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2624 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2625 prev_insn_extended
= 0;
2627 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2629 /* We don't yet optimize a branch likely. What we should do
2630 is look at the target, copy the instruction found there
2631 into the delay slot, and increment the branch to jump to
2632 the next instruction. */
2634 /* Update the previous insn information. */
2635 prev_prev_insn
= *ip
;
2636 prev_insn
.insn_mo
= &dummy_opcode
;
2637 prev_insn_fixp
[0] = NULL
;
2638 prev_insn_fixp
[1] = NULL
;
2639 prev_insn_fixp
[2] = NULL
;
2640 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2641 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2642 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2643 prev_insn_extended
= 0;
2647 /* Update the previous insn information. */
2649 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2651 prev_prev_insn
= prev_insn
;
2654 /* Any time we see a branch, we always fill the delay slot
2655 immediately; since this insn is not a branch, we know it
2656 is not in a delay slot. */
2657 prev_insn_is_delay_slot
= 0;
2659 prev_insn_fixp
[0] = fixp
[0];
2660 prev_insn_fixp
[1] = fixp
[1];
2661 prev_insn_fixp
[2] = fixp
[2];
2662 prev_insn_reloc_type
[0] = reloc_type
[0];
2663 prev_insn_reloc_type
[1] = reloc_type
[1];
2664 prev_insn_reloc_type
[2] = reloc_type
[2];
2665 if (mips_opts
.mips16
)
2666 prev_insn_extended
= (ip
->use_extend
2667 || *reloc_type
> BFD_RELOC_UNUSED
);
2670 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2671 prev_insn_unreordered
= 0;
2672 prev_insn_frag
= frag_now
;
2673 prev_insn_where
= f
- frag_now
->fr_literal
;
2674 prev_insn_valid
= 1;
2676 else if (place
== NULL
)
2678 /* We need to record a bit of information even when we are not
2679 reordering, in order to determine the base address for mips16
2680 PC relative relocs. */
2681 prev_prev_insn
= prev_insn
;
2683 prev_insn_reloc_type
[0] = reloc_type
[0];
2684 prev_insn_reloc_type
[1] = reloc_type
[1];
2685 prev_insn_reloc_type
[2] = reloc_type
[2];
2686 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2687 prev_insn_unreordered
= 1;
2690 /* We just output an insn, so the next one doesn't have a label. */
2691 mips_clear_insn_labels ();
2693 /* We must ensure that a fixup associated with an unmatched %hi
2694 reloc does not become a variant frag. Otherwise, the
2695 rearrangement of %hi relocs in frob_file may confuse
2699 frag_wane (frag_now
);
2704 /* This function forgets that there was any previous instruction or
2705 label. If PRESERVE is non-zero, it remembers enough information to
2706 know whether nops are needed before a noreorder section. */
2709 mips_no_prev_insn (preserve
)
2714 prev_insn
.insn_mo
= &dummy_opcode
;
2715 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2716 prev_nop_frag
= NULL
;
2717 prev_nop_frag_holds
= 0;
2718 prev_nop_frag_required
= 0;
2719 prev_nop_frag_since
= 0;
2721 prev_insn_valid
= 0;
2722 prev_insn_is_delay_slot
= 0;
2723 prev_insn_unreordered
= 0;
2724 prev_insn_extended
= 0;
2725 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2726 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2727 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2728 prev_prev_insn_unreordered
= 0;
2729 mips_clear_insn_labels ();
2732 /* This function must be called whenever we turn on noreorder or emit
2733 something other than instructions. It inserts any NOPS which might
2734 be needed by the previous instruction, and clears the information
2735 kept for the previous instructions. The INSNS parameter is true if
2736 instructions are to follow. */
2739 mips_emit_delays (insns
)
2742 if (! mips_opts
.noreorder
)
2747 if ((! mips_opts
.mips16
2748 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2749 && (! cop_interlocks
2750 && (prev_insn
.insn_mo
->pinfo
2751 & (INSN_LOAD_COPROC_DELAY
2752 | INSN_COPROC_MOVE_DELAY
2753 | INSN_WRITE_COND_CODE
))))
2754 || (! hilo_interlocks
2755 && (prev_insn
.insn_mo
->pinfo
2758 || (! mips_opts
.mips16
2760 && (prev_insn
.insn_mo
->pinfo
2761 & INSN_LOAD_MEMORY_DELAY
))
2762 || (! mips_opts
.mips16
2763 && mips_opts
.isa
== ISA_MIPS1
2764 && (prev_insn
.insn_mo
->pinfo
2765 & INSN_COPROC_MEMORY_DELAY
)))
2767 /* Itbl support may require additional care here. */
2769 if ((! mips_opts
.mips16
2770 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2771 && (! cop_interlocks
2772 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2773 || (! hilo_interlocks
2774 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2775 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2778 if (prev_insn_unreordered
)
2781 else if ((! mips_opts
.mips16
2782 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2783 && (! cop_interlocks
2784 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2785 || (! hilo_interlocks
2786 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2787 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2789 /* Itbl support may require additional care here. */
2790 if (! prev_prev_insn_unreordered
)
2796 struct insn_label_list
*l
;
2800 /* Record the frag which holds the nop instructions, so
2801 that we can remove them if we don't need them. */
2802 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2803 prev_nop_frag
= frag_now
;
2804 prev_nop_frag_holds
= nops
;
2805 prev_nop_frag_required
= 0;
2806 prev_nop_frag_since
= 0;
2809 for (; nops
> 0; --nops
)
2814 /* Move on to a new frag, so that it is safe to simply
2815 decrease the size of prev_nop_frag. */
2816 frag_wane (frag_now
);
2820 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2824 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2825 symbol_set_frag (l
->label
, frag_now
);
2826 val
= (valueT
) frag_now_fix ();
2827 /* mips16 text labels are stored as odd. */
2828 if (mips_opts
.mips16
)
2830 S_SET_VALUE (l
->label
, val
);
2835 /* Mark instruction labels in mips16 mode. */
2837 mips16_mark_labels ();
2839 mips_no_prev_insn (insns
);
2842 /* Build an instruction created by a macro expansion. This is passed
2843 a pointer to the count of instructions created so far, an
2844 expression, the name of the instruction to build, an operand format
2845 string, and corresponding arguments. */
2849 macro_build (char *place
,
2857 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2866 struct mips_cl_insn insn
;
2867 bfd_reloc_code_real_type r
[3];
2871 va_start (args
, fmt
);
2877 * If the macro is about to expand into a second instruction,
2878 * print a warning if needed. We need to pass ip as a parameter
2879 * to generate a better warning message here...
2881 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2882 as_warn (_("Macro instruction expanded into multiple instructions"));
2885 * If the macro is about to expand into a second instruction,
2886 * and it is in a delay slot, print a warning.
2890 && mips_opts
.noreorder
2891 && (prev_prev_insn
.insn_mo
->pinfo
2892 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2893 | INSN_COND_BRANCH_LIKELY
)) != 0)
2894 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2897 ++*counter
; /* bump instruction counter */
2899 if (mips_opts
.mips16
)
2901 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2906 r
[0] = BFD_RELOC_UNUSED
;
2907 r
[1] = BFD_RELOC_UNUSED
;
2908 r
[2] = BFD_RELOC_UNUSED
;
2909 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2910 assert (insn
.insn_mo
);
2911 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2913 /* Search until we get a match for NAME. */
2916 /* It is assumed here that macros will never generate
2917 MIPS-3D instructions. */
2918 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2919 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2920 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_arch
)
2921 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2925 assert (insn
.insn_mo
->name
);
2926 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2929 insn
.insn_opcode
= insn
.insn_mo
->match
;
2945 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2949 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2954 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2959 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2964 int tmp
= va_arg (args
, int);
2966 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2967 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2973 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2980 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2984 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2988 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2992 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2996 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3003 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3009 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3010 assert (*r
== BFD_RELOC_GPREL16
3011 || *r
== BFD_RELOC_MIPS_LITERAL
3012 || *r
== BFD_RELOC_MIPS_HIGHER
3013 || *r
== BFD_RELOC_HI16_S
3014 || *r
== BFD_RELOC_LO16
3015 || *r
== BFD_RELOC_MIPS_GOT16
3016 || *r
== BFD_RELOC_MIPS_CALL16
3017 || *r
== BFD_RELOC_MIPS_GOT_LO16
3018 || *r
== BFD_RELOC_MIPS_CALL_LO16
3019 || (ep
->X_op
== O_subtract
3020 && *r
== BFD_RELOC_PCREL_LO16
));
3024 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3026 && (ep
->X_op
== O_constant
3027 || (ep
->X_op
== O_symbol
3028 && (*r
== BFD_RELOC_MIPS_HIGHEST
3029 || *r
== BFD_RELOC_HI16_S
3030 || *r
== BFD_RELOC_HI16
3031 || *r
== BFD_RELOC_GPREL16
3032 || *r
== BFD_RELOC_MIPS_GOT_HI16
3033 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3034 || (ep
->X_op
== O_subtract
3035 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3039 assert (ep
!= NULL
);
3041 * This allows macro() to pass an immediate expression for
3042 * creating short branches without creating a symbol.
3043 * Note that the expression still might come from the assembly
3044 * input, in which case the value is not checked for range nor
3045 * is a relocation entry generated (yuck).
3047 if (ep
->X_op
== O_constant
)
3049 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3053 if (mips_pic
== EMBEDDED_PIC
)
3054 *r
= BFD_RELOC_16_PCREL_S2
;
3056 *r
= BFD_RELOC_16_PCREL
;
3060 assert (ep
!= NULL
);
3061 *r
= BFD_RELOC_MIPS_JMP
;
3065 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3074 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3076 append_insn (place
, &insn
, ep
, r
, false);
3080 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
3082 int *counter ATTRIBUTE_UNUSED
;
3088 struct mips_cl_insn insn
;
3089 bfd_reloc_code_real_type r
[3]
3090 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3092 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3093 assert (insn
.insn_mo
);
3094 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3096 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3097 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3100 assert (insn
.insn_mo
->name
);
3101 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3104 insn
.insn_opcode
= insn
.insn_mo
->match
;
3105 insn
.use_extend
= false;
3124 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3129 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3133 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3137 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3147 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3154 regno
= va_arg (args
, int);
3155 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3156 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3177 assert (ep
!= NULL
);
3179 if (ep
->X_op
!= O_constant
)
3180 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3183 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, false, false,
3184 false, &insn
.insn_opcode
, &insn
.use_extend
,
3187 *r
= BFD_RELOC_UNUSED
;
3193 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3200 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3202 append_insn (place
, &insn
, ep
, r
, false);
3206 * Generate a "lui" instruction.
3209 macro_build_lui (place
, counter
, ep
, regnum
)
3215 expressionS high_expr
;
3216 struct mips_cl_insn insn
;
3217 bfd_reloc_code_real_type r
[3]
3218 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3219 CONST
char *name
= "lui";
3220 CONST
char *fmt
= "t,u";
3222 assert (! mips_opts
.mips16
);
3228 high_expr
.X_op
= O_constant
;
3229 high_expr
.X_add_number
= ep
->X_add_number
;
3232 if (high_expr
.X_op
== O_constant
)
3234 /* we can compute the instruction now without a relocation entry */
3235 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3237 *r
= BFD_RELOC_UNUSED
;
3239 else if (! HAVE_NEWABI
)
3241 assert (ep
->X_op
== O_symbol
);
3242 /* _gp_disp is a special case, used from s_cpload. */
3243 assert (mips_pic
== NO_PIC
3244 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
3245 *r
= BFD_RELOC_HI16_S
;
3249 * If the macro is about to expand into a second instruction,
3250 * print a warning if needed. We need to pass ip as a parameter
3251 * to generate a better warning message here...
3253 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3254 as_warn (_("Macro instruction expanded into multiple instructions"));
3257 ++*counter
; /* bump instruction counter */
3259 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3260 assert (insn
.insn_mo
);
3261 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3262 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3264 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3265 if (*r
== BFD_RELOC_UNUSED
)
3267 insn
.insn_opcode
|= high_expr
.X_add_number
;
3268 append_insn (place
, &insn
, NULL
, r
, false);
3271 append_insn (place
, &insn
, &high_expr
, r
, false);
3275 * Generates code to set the $at register to true (one)
3276 * if reg is less than the immediate expression.
3279 set_at (counter
, reg
, unsignedp
)
3284 if (imm_expr
.X_op
== O_constant
3285 && imm_expr
.X_add_number
>= -0x8000
3286 && imm_expr
.X_add_number
< 0x8000)
3287 macro_build ((char *) NULL
, counter
, &imm_expr
,
3288 unsignedp
? "sltiu" : "slti",
3289 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3292 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3293 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3294 unsignedp
? "sltu" : "slt",
3295 "d,v,t", AT
, reg
, AT
);
3299 /* Warn if an expression is not a constant. */
3302 check_absolute_expr (ip
, ex
)
3303 struct mips_cl_insn
*ip
;
3306 if (ex
->X_op
== O_big
)
3307 as_bad (_("unsupported large constant"));
3308 else if (ex
->X_op
!= O_constant
)
3309 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3312 /* Count the leading zeroes by performing a binary chop. This is a
3313 bulky bit of source, but performance is a LOT better for the
3314 majority of values than a simple loop to count the bits:
3315 for (lcnt = 0; (lcnt < 32); lcnt++)
3316 if ((v) & (1 << (31 - lcnt)))
3318 However it is not code size friendly, and the gain will drop a bit
3319 on certain cached systems.
3321 #define COUNT_TOP_ZEROES(v) \
3322 (((v) & ~0xffff) == 0 \
3323 ? ((v) & ~0xff) == 0 \
3324 ? ((v) & ~0xf) == 0 \
3325 ? ((v) & ~0x3) == 0 \
3326 ? ((v) & ~0x1) == 0 \
3331 : ((v) & ~0x7) == 0 \
3334 : ((v) & ~0x3f) == 0 \
3335 ? ((v) & ~0x1f) == 0 \
3338 : ((v) & ~0x7f) == 0 \
3341 : ((v) & ~0xfff) == 0 \
3342 ? ((v) & ~0x3ff) == 0 \
3343 ? ((v) & ~0x1ff) == 0 \
3346 : ((v) & ~0x7ff) == 0 \
3349 : ((v) & ~0x3fff) == 0 \
3350 ? ((v) & ~0x1fff) == 0 \
3353 : ((v) & ~0x7fff) == 0 \
3356 : ((v) & ~0xffffff) == 0 \
3357 ? ((v) & ~0xfffff) == 0 \
3358 ? ((v) & ~0x3ffff) == 0 \
3359 ? ((v) & ~0x1ffff) == 0 \
3362 : ((v) & ~0x7ffff) == 0 \
3365 : ((v) & ~0x3fffff) == 0 \
3366 ? ((v) & ~0x1fffff) == 0 \
3369 : ((v) & ~0x7fffff) == 0 \
3372 : ((v) & ~0xfffffff) == 0 \
3373 ? ((v) & ~0x3ffffff) == 0 \
3374 ? ((v) & ~0x1ffffff) == 0 \
3377 : ((v) & ~0x7ffffff) == 0 \
3380 : ((v) & ~0x3fffffff) == 0 \
3381 ? ((v) & ~0x1fffffff) == 0 \
3384 : ((v) & ~0x7fffffff) == 0 \
3388 /* Is the given value a sign-extended 32-bit value? */
3389 #define IS_SEXT_32BIT_NUM(x) \
3390 (((x) &~ (offsetT) 0x7fffffff) == 0 \
3391 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
3394 * This routine generates the least number of instructions neccessary to load
3395 * an absolute expression value into a register.
3398 load_register (counter
, reg
, ep
, dbl
)
3405 expressionS hi32
, lo32
;
3407 if (ep
->X_op
!= O_big
)
3409 assert (ep
->X_op
== O_constant
);
3410 if (ep
->X_add_number
< 0x8000
3411 && (ep
->X_add_number
>= 0
3412 || (ep
->X_add_number
>= -0x8000
3415 || sizeof (ep
->X_add_number
) > 4))))
3417 /* We can handle 16 bit signed values with an addiu to
3418 $zero. No need to ever use daddiu here, since $zero and
3419 the result are always correct in 32 bit mode. */
3420 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3421 (int) BFD_RELOC_LO16
);
3424 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3426 /* We can handle 16 bit unsigned values with an ori to
3428 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3429 (int) BFD_RELOC_LO16
);
3432 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)
3435 || sizeof (ep
->X_add_number
) > 4
3436 || (ep
->X_add_number
& 0x80000000) == 0))
3437 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3438 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3441 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3442 == ~ (offsetT
) 0xffffffff)))
3444 /* 32 bit values require an lui. */
3445 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3446 (int) BFD_RELOC_HI16
);
3447 if ((ep
->X_add_number
& 0xffff) != 0)
3448 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3449 (int) BFD_RELOC_LO16
);
3454 /* The value is larger than 32 bits. */
3456 if (HAVE_32BIT_GPRS
)
3458 as_bad (_("Number (0x%lx) larger than 32 bits"),
3459 (unsigned long) ep
->X_add_number
);
3460 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3461 (int) BFD_RELOC_LO16
);
3465 if (ep
->X_op
!= O_big
)
3468 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3469 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3470 hi32
.X_add_number
&= 0xffffffff;
3472 lo32
.X_add_number
&= 0xffffffff;
3476 assert (ep
->X_add_number
> 2);
3477 if (ep
->X_add_number
== 3)
3478 generic_bignum
[3] = 0;
3479 else if (ep
->X_add_number
> 4)
3480 as_bad (_("Number larger than 64 bits"));
3481 lo32
.X_op
= O_constant
;
3482 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3483 hi32
.X_op
= O_constant
;
3484 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3487 if (hi32
.X_add_number
== 0)
3492 unsigned long hi
, lo
;
3494 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3496 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3498 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3499 reg
, 0, (int) BFD_RELOC_LO16
);
3502 if (lo32
.X_add_number
& 0x80000000)
3504 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3505 (int) BFD_RELOC_HI16
);
3506 if (lo32
.X_add_number
& 0xffff)
3507 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3508 reg
, reg
, (int) BFD_RELOC_LO16
);
3513 /* Check for 16bit shifted constant. We know that hi32 is
3514 non-zero, so start the mask on the first bit of the hi32
3519 unsigned long himask
, lomask
;
3523 himask
= 0xffff >> (32 - shift
);
3524 lomask
= (0xffff << shift
) & 0xffffffff;
3528 himask
= 0xffff << (shift
- 32);
3531 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3532 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3536 tmp
.X_op
= O_constant
;
3538 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3539 | (lo32
.X_add_number
>> shift
));
3541 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3542 macro_build ((char *) NULL
, counter
, &tmp
,
3543 "ori", "t,r,i", reg
, 0,
3544 (int) BFD_RELOC_LO16
);
3545 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3546 (shift
>= 32) ? "dsll32" : "dsll",
3548 (shift
>= 32) ? shift
- 32 : shift
);
3553 while (shift
<= (64 - 16));
3555 /* Find the bit number of the lowest one bit, and store the
3556 shifted value in hi/lo. */
3557 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3558 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3562 while ((lo
& 1) == 0)
3567 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3573 while ((hi
& 1) == 0)
3582 /* Optimize if the shifted value is a (power of 2) - 1. */
3583 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3584 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3586 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3591 /* This instruction will set the register to be all
3593 tmp
.X_op
= O_constant
;
3594 tmp
.X_add_number
= (offsetT
) -1;
3595 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3596 reg
, 0, (int) BFD_RELOC_LO16
);
3600 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3601 (bit
>= 32) ? "dsll32" : "dsll",
3603 (bit
>= 32) ? bit
- 32 : bit
);
3605 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3606 (shift
>= 32) ? "dsrl32" : "dsrl",
3608 (shift
>= 32) ? shift
- 32 : shift
);
3613 /* Sign extend hi32 before calling load_register, because we can
3614 generally get better code when we load a sign extended value. */
3615 if ((hi32
.X_add_number
& 0x80000000) != 0)
3616 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3617 load_register (counter
, reg
, &hi32
, 0);
3620 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3624 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3625 "dsll32", "d,w,<", reg
, freg
, 0);
3633 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3635 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3636 (int) BFD_RELOC_HI16
);
3637 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3638 "dsrl32", "d,w,<", reg
, reg
, 0);
3644 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3645 "d,w,<", reg
, freg
, 16);
3649 mid16
.X_add_number
>>= 16;
3650 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3651 freg
, (int) BFD_RELOC_LO16
);
3652 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3653 "d,w,<", reg
, reg
, 16);
3656 if ((lo32
.X_add_number
& 0xffff) != 0)
3657 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3658 (int) BFD_RELOC_LO16
);
3661 /* Load an address into a register. */
3664 load_address (counter
, reg
, ep
, used_at
)
3672 if (ep
->X_op
!= O_constant
3673 && ep
->X_op
!= O_symbol
)
3675 as_bad (_("expression too complex"));
3676 ep
->X_op
= O_constant
;
3679 if (ep
->X_op
== O_constant
)
3681 load_register (counter
, reg
, ep
, HAVE_64BIT_ADDRESSES
);
3685 if (mips_pic
== NO_PIC
)
3687 /* If this is a reference to a GP relative symbol, we want
3688 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3690 lui $reg,<sym> (BFD_RELOC_HI16_S)
3691 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3692 If we have an addend, we always use the latter form.
3694 With 64bit address space and a usable $at we want
3695 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3696 lui $at,<sym> (BFD_RELOC_HI16_S)
3697 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3698 daddiu $at,<sym> (BFD_RELOC_LO16)
3702 If $at is already in use, we use an path which is suboptimal
3703 on superscalar processors.
3704 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3705 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3707 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3709 daddiu $reg,<sym> (BFD_RELOC_LO16)
3711 if (HAVE_64BIT_ADDRESSES
)
3713 /* We don't do GP optimization for now because RELAX_ENCODE can't
3714 hold the data for such large chunks. */
3718 macro_build (p
, counter
, ep
, "lui", "t,u",
3719 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3720 macro_build (p
, counter
, ep
, "lui", "t,u",
3721 AT
, (int) BFD_RELOC_HI16_S
);
3722 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3723 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3724 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3725 AT
, AT
, (int) BFD_RELOC_LO16
);
3726 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3727 "d,w,<", reg
, reg
, 0);
3728 macro_build (p
, counter
, (expressionS
*) NULL
, "dadd",
3729 "d,v,t", reg
, reg
, AT
);
3734 macro_build (p
, counter
, ep
, "lui", "t,u",
3735 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3736 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3737 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3738 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3739 "d,w,<", reg
, reg
, 16);
3740 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3741 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3742 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3743 "d,w,<", reg
, reg
, 16);
3744 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3745 reg
, reg
, (int) BFD_RELOC_LO16
);
3750 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3751 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3754 macro_build ((char *) NULL
, counter
, ep
,
3755 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3756 reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3757 p
= frag_var (rs_machine_dependent
, 8, 0,
3758 RELAX_ENCODE (4, 8, 0, 4, 0,
3759 mips_opts
.warn_about_macros
),
3760 ep
->X_add_symbol
, 0, NULL
);
3762 macro_build_lui (p
, counter
, ep
, reg
);
3765 macro_build (p
, counter
, ep
,
3766 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3767 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3770 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3774 /* If this is a reference to an external symbol, we want
3775 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3777 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3779 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3780 If there is a constant, it must be added in after. */
3781 ex
.X_add_number
= ep
->X_add_number
;
3782 ep
->X_add_number
= 0;
3784 macro_build ((char *) NULL
, counter
, ep
,
3785 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
3786 reg
, (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3787 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3788 p
= frag_var (rs_machine_dependent
, 4, 0,
3789 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3790 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3791 macro_build (p
, counter
, ep
,
3792 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3793 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3794 if (ex
.X_add_number
!= 0)
3796 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3797 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3798 ex
.X_op
= O_constant
;
3799 macro_build ((char *) NULL
, counter
, &ex
,
3800 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3801 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3804 else if (mips_pic
== SVR4_PIC
)
3809 /* This is the large GOT case. If this is a reference to an
3810 external symbol, we want
3811 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3813 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3814 Otherwise, for a reference to a local symbol, we want
3815 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3817 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3818 If there is a constant, it must be added in after. */
3819 ex
.X_add_number
= ep
->X_add_number
;
3820 ep
->X_add_number
= 0;
3821 if (reg_needs_delay (GP
))
3826 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3827 (int) BFD_RELOC_MIPS_GOT_HI16
);
3828 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3829 dbl
? "daddu" : "addu", "d,v,t", reg
, reg
, GP
);
3830 macro_build ((char *) NULL
, counter
, ep
, dbl
? "ld" : "lw",
3831 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3832 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3833 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3834 mips_opts
.warn_about_macros
),
3835 ep
->X_add_symbol
, 0, NULL
);
3838 /* We need a nop before loading from $gp. This special
3839 check is required because the lui which starts the main
3840 instruction stream does not refer to $gp, and so will not
3841 insert the nop which may be required. */
3842 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3845 macro_build (p
, counter
, ep
, dbl
? "ld" : "lw",
3846 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3848 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3850 macro_build (p
, counter
, ep
, dbl
? "daddiu" : "addiu",
3851 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3852 if (ex
.X_add_number
!= 0)
3854 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3855 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3856 ex
.X_op
= O_constant
;
3857 macro_build ((char *) NULL
, counter
, &ex
, dbl
? "daddiu" : "addiu",
3858 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3861 else if (mips_pic
== EMBEDDED_PIC
)
3864 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3866 macro_build ((char *) NULL
, counter
, ep
,
3867 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3868 "t,r,j", reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3874 /* Move the contents of register SOURCE into register DEST. */
3877 move_register (counter
, dest
, source
)
3882 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3883 HAVE_32BIT_GPRS
? "addu" : "daddu",
3884 "d,v,t", dest
, source
, 0);
3889 * This routine implements the seemingly endless macro or synthesized
3890 * instructions and addressing modes in the mips assembly language. Many
3891 * of these macros are simple and are similar to each other. These could
3892 * probably be handled by some kind of table or grammer aproach instead of
3893 * this verbose method. Others are not simple macros but are more like
3894 * optimizing code generation.
3895 * One interesting optimization is when several store macros appear
3896 * consecutivly that would load AT with the upper half of the same address.
3897 * The ensuing load upper instructions are ommited. This implies some kind
3898 * of global optimization. We currently only optimize within a single macro.
3899 * For many of the load and store macros if the address is specified as a
3900 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3901 * first load register 'at' with zero and use it as the base register. The
3902 * mips assembler simply uses register $zero. Just one tiny optimization
3907 struct mips_cl_insn
*ip
;
3909 register int treg
, sreg
, dreg
, breg
;
3925 bfd_reloc_code_real_type r
;
3926 int hold_mips_optimize
;
3928 assert (! mips_opts
.mips16
);
3930 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3931 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3932 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3933 mask
= ip
->insn_mo
->mask
;
3935 expr1
.X_op
= O_constant
;
3936 expr1
.X_op_symbol
= NULL
;
3937 expr1
.X_add_symbol
= NULL
;
3938 expr1
.X_add_number
= 1;
3950 mips_emit_delays (true);
3951 ++mips_opts
.noreorder
;
3952 mips_any_noreorder
= 1;
3954 expr1
.X_add_number
= 8;
3955 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3957 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
3960 move_register (&icnt
, dreg
, sreg
);
3961 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3962 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
3964 --mips_opts
.noreorder
;
3985 if (imm_expr
.X_op
== O_constant
3986 && imm_expr
.X_add_number
>= -0x8000
3987 && imm_expr
.X_add_number
< 0x8000)
3989 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3990 (int) BFD_RELOC_LO16
);
3993 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3994 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4014 if (imm_expr
.X_op
== O_constant
4015 && imm_expr
.X_add_number
>= 0
4016 && imm_expr
.X_add_number
< 0x10000)
4018 if (mask
!= M_NOR_I
)
4019 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
4020 sreg
, (int) BFD_RELOC_LO16
);
4023 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
4024 treg
, sreg
, (int) BFD_RELOC_LO16
);
4025 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
4026 "d,v,t", treg
, treg
, 0);
4031 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4032 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4050 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4052 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
4056 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4057 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
4065 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4066 likely
? "bgezl" : "bgez", "s,p", sreg
);
4071 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4072 likely
? "blezl" : "blez", "s,p", treg
);
4075 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4077 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4078 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4084 /* check for > max integer */
4085 maxnum
= 0x7fffffff;
4086 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4093 if (imm_expr
.X_op
== O_constant
4094 && imm_expr
.X_add_number
>= maxnum
4095 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4098 /* result is always false */
4102 as_warn (_("Branch %s is always false (nop)"),
4104 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4110 as_warn (_("Branch likely %s is always false"),
4112 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4117 if (imm_expr
.X_op
!= O_constant
)
4118 as_bad (_("Unsupported large constant"));
4119 ++imm_expr
.X_add_number
;
4123 if (mask
== M_BGEL_I
)
4125 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4127 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4128 likely
? "bgezl" : "bgez", "s,p", sreg
);
4131 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4133 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4134 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4137 maxnum
= 0x7fffffff;
4138 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4145 maxnum
= - maxnum
- 1;
4146 if (imm_expr
.X_op
== O_constant
4147 && imm_expr
.X_add_number
<= maxnum
4148 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4151 /* result is always true */
4152 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4153 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4156 set_at (&icnt
, sreg
, 0);
4157 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4158 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4168 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4169 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4172 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4173 "d,v,t", AT
, sreg
, treg
);
4174 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4175 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4183 && imm_expr
.X_op
== O_constant
4184 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4186 if (imm_expr
.X_op
!= O_constant
)
4187 as_bad (_("Unsupported large constant"));
4188 ++imm_expr
.X_add_number
;
4192 if (mask
== M_BGEUL_I
)
4194 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4196 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4198 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4199 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4202 set_at (&icnt
, sreg
, 1);
4203 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4204 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4212 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4213 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4218 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4219 likely
? "bltzl" : "bltz", "s,p", treg
);
4222 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4224 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4225 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4233 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4234 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4239 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4240 "d,v,t", AT
, treg
, sreg
);
4241 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4242 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4250 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4251 likely
? "blezl" : "blez", "s,p", sreg
);
4256 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4257 likely
? "bgezl" : "bgez", "s,p", treg
);
4260 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4262 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4263 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4269 maxnum
= 0x7fffffff;
4270 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4277 if (imm_expr
.X_op
== O_constant
4278 && imm_expr
.X_add_number
>= maxnum
4279 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4281 if (imm_expr
.X_op
!= O_constant
)
4282 as_bad (_("Unsupported large constant"));
4283 ++imm_expr
.X_add_number
;
4287 if (mask
== M_BLTL_I
)
4289 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4291 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4292 likely
? "bltzl" : "bltz", "s,p", sreg
);
4295 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4297 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4298 likely
? "blezl" : "blez", "s,p", sreg
);
4301 set_at (&icnt
, sreg
, 0);
4302 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4303 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4311 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4312 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4317 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4318 "d,v,t", AT
, treg
, sreg
);
4319 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4320 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4328 && imm_expr
.X_op
== O_constant
4329 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4331 if (imm_expr
.X_op
!= O_constant
)
4332 as_bad (_("Unsupported large constant"));
4333 ++imm_expr
.X_add_number
;
4337 if (mask
== M_BLTUL_I
)
4339 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4341 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4343 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4344 likely
? "beql" : "beq",
4348 set_at (&icnt
, sreg
, 1);
4349 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4350 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4358 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4359 likely
? "bltzl" : "bltz", "s,p", sreg
);
4364 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4365 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4368 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4370 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4371 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4381 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4382 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4385 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4388 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4389 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4404 as_warn (_("Divide by zero."));
4406 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4409 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4414 mips_emit_delays (true);
4415 ++mips_opts
.noreorder
;
4416 mips_any_noreorder
= 1;
4419 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4421 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4422 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4426 expr1
.X_add_number
= 8;
4427 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4429 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4430 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4433 expr1
.X_add_number
= -1;
4434 macro_build ((char *) NULL
, &icnt
, &expr1
,
4435 dbl
? "daddiu" : "addiu",
4436 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4437 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4438 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4441 expr1
.X_add_number
= 1;
4442 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4443 (int) BFD_RELOC_LO16
);
4444 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4445 "d,w,<", AT
, AT
, 31);
4449 expr1
.X_add_number
= 0x80000000;
4450 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4451 (int) BFD_RELOC_HI16
);
4455 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4457 /* We want to close the noreorder block as soon as possible, so
4458 that later insns are available for delay slot filling. */
4459 --mips_opts
.noreorder
;
4463 expr1
.X_add_number
= 8;
4464 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4465 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4468 /* We want to close the noreorder block as soon as possible, so
4469 that later insns are available for delay slot filling. */
4470 --mips_opts
.noreorder
;
4472 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4475 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4514 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4516 as_warn (_("Divide by zero."));
4518 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4521 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4525 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4527 if (strcmp (s2
, "mflo") == 0)
4528 move_register (&icnt
, dreg
, sreg
);
4530 move_register (&icnt
, dreg
, 0);
4533 if (imm_expr
.X_op
== O_constant
4534 && imm_expr
.X_add_number
== -1
4535 && s
[strlen (s
) - 1] != 'u')
4537 if (strcmp (s2
, "mflo") == 0)
4539 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4540 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4543 move_register (&icnt
, dreg
, 0);
4547 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4548 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4550 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4569 mips_emit_delays (true);
4570 ++mips_opts
.noreorder
;
4571 mips_any_noreorder
= 1;
4574 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4576 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4578 /* We want to close the noreorder block as soon as possible, so
4579 that later insns are available for delay slot filling. */
4580 --mips_opts
.noreorder
;
4584 expr1
.X_add_number
= 8;
4585 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4586 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4589 /* We want to close the noreorder block as soon as possible, so
4590 that later insns are available for delay slot filling. */
4591 --mips_opts
.noreorder
;
4592 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4595 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4601 /* Load the address of a symbol into a register. If breg is not
4602 zero, we then add a base register to it. */
4604 if (dbl
&& HAVE_32BIT_GPRS
)
4605 as_warn (_("dla used to load 32-bit register"));
4607 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4608 as_warn (_("la used to load 64-bit address"));
4621 /* When generating embedded PIC code, we permit expressions of
4624 la $treg,foo-bar($breg)
4625 where bar is an address in the current section. These are used
4626 when getting the addresses of functions. We don't permit
4627 X_add_number to be non-zero, because if the symbol is
4628 external the relaxing code needs to know that any addend is
4629 purely the offset to X_op_symbol. */
4630 if (mips_pic
== EMBEDDED_PIC
4631 && offset_expr
.X_op
== O_subtract
4632 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4633 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4634 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4636 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4639 && (offset_expr
.X_add_number
== 0
4640 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4646 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4647 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4651 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4652 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4653 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4654 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4655 "d,v,t", tempreg
, tempreg
, breg
);
4657 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4658 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4659 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4665 if (offset_expr
.X_op
!= O_symbol
4666 && offset_expr
.X_op
!= O_constant
)
4668 as_bad (_("expression too complex"));
4669 offset_expr
.X_op
= O_constant
;
4672 if (offset_expr
.X_op
== O_constant
)
4673 load_register (&icnt
, tempreg
, &offset_expr
,
4674 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4675 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4676 : HAVE_64BIT_ADDRESSES
));
4677 else if (mips_pic
== NO_PIC
)
4679 /* If this is a reference to a GP relative symbol, we want
4680 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4682 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4683 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4684 If we have a constant, we need two instructions anyhow,
4685 so we may as well always use the latter form.
4687 With 64bit address space and a usable $at we want
4688 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4689 lui $at,<sym> (BFD_RELOC_HI16_S)
4690 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4691 daddiu $at,<sym> (BFD_RELOC_LO16)
4693 dadd $tempreg,$tempreg,$at
4695 If $at is already in use, we use an path which is suboptimal
4696 on superscalar processors.
4697 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4698 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4700 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4702 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4705 if (HAVE_64BIT_ADDRESSES
)
4707 /* We don't do GP optimization for now because RELAX_ENCODE can't
4708 hold the data for such large chunks. */
4712 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4713 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4714 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4715 AT
, (int) BFD_RELOC_HI16_S
);
4716 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4717 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4718 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4719 AT
, AT
, (int) BFD_RELOC_LO16
);
4720 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4721 "d,w,<", tempreg
, tempreg
, 0);
4722 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dadd", "d,v,t",
4723 tempreg
, tempreg
, AT
);
4728 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4729 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4730 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4731 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4732 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4733 tempreg
, tempreg
, 16);
4734 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4735 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4736 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4737 tempreg
, tempreg
, 16);
4738 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4739 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4744 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4745 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4748 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "addiu",
4749 "t,r,j", tempreg
, mips_gp_register
,
4750 (int) BFD_RELOC_GPREL16
);
4751 p
= frag_var (rs_machine_dependent
, 8, 0,
4752 RELAX_ENCODE (4, 8, 0, 4, 0,
4753 mips_opts
.warn_about_macros
),
4754 offset_expr
.X_add_symbol
, 0, NULL
);
4756 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4759 macro_build (p
, &icnt
, &offset_expr
, "addiu",
4760 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4763 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4765 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4767 /* If this is a reference to an external symbol, and there
4768 is no constant, we want
4769 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4770 or if tempreg is PIC_CALL_REG
4771 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4772 For a local symbol, we want
4773 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4775 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4777 If we have a small constant, and this is a reference to
4778 an external symbol, we want
4779 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4781 addiu $tempreg,$tempreg,<constant>
4782 For a local symbol, we want the same instruction
4783 sequence, but we output a BFD_RELOC_LO16 reloc on the
4786 If we have a large constant, and this is a reference to
4787 an external symbol, we want
4788 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4789 lui $at,<hiconstant>
4790 addiu $at,$at,<loconstant>
4791 addu $tempreg,$tempreg,$at
4792 For a local symbol, we want the same instruction
4793 sequence, but we output a BFD_RELOC_LO16 reloc on the
4794 addiu instruction. */
4795 expr1
.X_add_number
= offset_expr
.X_add_number
;
4796 offset_expr
.X_add_number
= 0;
4798 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4799 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4800 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4801 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4802 "t,o(b)", tempreg
, lw_reloc_type
, mips_gp_register
);
4803 if (expr1
.X_add_number
== 0)
4812 /* We're going to put in an addu instruction using
4813 tempreg, so we may as well insert the nop right
4815 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4819 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4820 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4822 ? mips_opts
.warn_about_macros
4824 offset_expr
.X_add_symbol
, 0, NULL
);
4827 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4830 macro_build (p
, &icnt
, &expr1
,
4831 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4832 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4833 /* FIXME: If breg == 0, and the next instruction uses
4834 $tempreg, then if this variant case is used an extra
4835 nop will be generated. */
4837 else if (expr1
.X_add_number
>= -0x8000
4838 && expr1
.X_add_number
< 0x8000)
4840 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4842 macro_build ((char *) NULL
, &icnt
, &expr1
,
4843 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4844 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4845 frag_var (rs_machine_dependent
, 0, 0,
4846 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4847 offset_expr
.X_add_symbol
, 0, NULL
);
4853 /* If we are going to add in a base register, and the
4854 target register and the base register are the same,
4855 then we are using AT as a temporary register. Since
4856 we want to load the constant into AT, we add our
4857 current AT (from the global offset table) and the
4858 register into the register now, and pretend we were
4859 not using a base register. */
4864 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4866 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4867 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4868 "d,v,t", treg
, AT
, breg
);
4874 /* Set mips_optimize around the lui instruction to avoid
4875 inserting an unnecessary nop after the lw. */
4876 hold_mips_optimize
= mips_optimize
;
4878 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
4879 mips_optimize
= hold_mips_optimize
;
4881 macro_build ((char *) NULL
, &icnt
, &expr1
,
4882 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4883 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4884 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4885 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4886 "d,v,t", tempreg
, tempreg
, AT
);
4887 frag_var (rs_machine_dependent
, 0, 0,
4888 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4889 offset_expr
.X_add_symbol
, 0, NULL
);
4893 else if (mips_pic
== SVR4_PIC
)
4897 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4898 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4900 /* This is the large GOT case. If this is a reference to an
4901 external symbol, and there is no constant, we want
4902 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4903 addu $tempreg,$tempreg,$gp
4904 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4905 or if tempreg is PIC_CALL_REG
4906 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4907 addu $tempreg,$tempreg,$gp
4908 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4909 For a local symbol, we want
4910 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4912 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4914 If we have a small constant, and this is a reference to
4915 an external symbol, we want
4916 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4917 addu $tempreg,$tempreg,$gp
4918 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4920 addiu $tempreg,$tempreg,<constant>
4921 For a local symbol, we want
4922 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4924 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4926 If we have a large constant, and this is a reference to
4927 an external symbol, we want
4928 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4929 addu $tempreg,$tempreg,$gp
4930 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4931 lui $at,<hiconstant>
4932 addiu $at,$at,<loconstant>
4933 addu $tempreg,$tempreg,$at
4934 For a local symbol, we want
4935 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4936 lui $at,<hiconstant>
4937 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4938 addu $tempreg,$tempreg,$at
4940 expr1
.X_add_number
= offset_expr
.X_add_number
;
4941 offset_expr
.X_add_number
= 0;
4943 if (reg_needs_delay (GP
))
4947 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4949 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4950 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4952 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4953 tempreg
, lui_reloc_type
);
4954 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4955 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4956 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
4957 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4958 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4959 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4960 if (expr1
.X_add_number
== 0)
4968 /* We're going to put in an addu instruction using
4969 tempreg, so we may as well insert the nop right
4971 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4976 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4977 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4980 ? mips_opts
.warn_about_macros
4982 offset_expr
.X_add_symbol
, 0, NULL
);
4984 else if (expr1
.X_add_number
>= -0x8000
4985 && expr1
.X_add_number
< 0x8000)
4987 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4989 macro_build ((char *) NULL
, &icnt
, &expr1
,
4990 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4991 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4993 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4994 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4996 ? mips_opts
.warn_about_macros
4998 offset_expr
.X_add_symbol
, 0, NULL
);
5004 /* If we are going to add in a base register, and the
5005 target register and the base register are the same,
5006 then we are using AT as a temporary register. Since
5007 we want to load the constant into AT, we add our
5008 current AT (from the global offset table) and the
5009 register into the register now, and pretend we were
5010 not using a base register. */
5018 assert (tempreg
== AT
);
5019 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5021 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5022 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5023 "d,v,t", treg
, AT
, breg
);
5028 /* Set mips_optimize around the lui instruction to avoid
5029 inserting an unnecessary nop after the lw. */
5030 hold_mips_optimize
= mips_optimize
;
5032 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5033 mips_optimize
= hold_mips_optimize
;
5035 macro_build ((char *) NULL
, &icnt
, &expr1
,
5036 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5037 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5038 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5039 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5040 "d,v,t", dreg
, dreg
, AT
);
5042 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
5043 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
5046 ? mips_opts
.warn_about_macros
5048 offset_expr
.X_add_symbol
, 0, NULL
);
5055 /* This is needed because this instruction uses $gp, but
5056 the first instruction on the main stream does not. */
5057 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5060 macro_build (p
, &icnt
, &offset_expr
,
5061 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5062 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
5065 if (expr1
.X_add_number
>= -0x8000
5066 && expr1
.X_add_number
< 0x8000)
5068 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5070 macro_build (p
, &icnt
, &expr1
,
5071 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5072 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5073 /* FIXME: If add_number is 0, and there was no base
5074 register, the external symbol case ended with a load,
5075 so if the symbol turns out to not be external, and
5076 the next instruction uses tempreg, an unnecessary nop
5077 will be inserted. */
5083 /* We must add in the base register now, as in the
5084 external symbol case. */
5085 assert (tempreg
== AT
);
5086 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5088 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5089 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5090 "d,v,t", treg
, AT
, breg
);
5093 /* We set breg to 0 because we have arranged to add
5094 it in in both cases. */
5098 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5100 macro_build (p
, &icnt
, &expr1
,
5101 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5102 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5104 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5105 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5106 "d,v,t", tempreg
, tempreg
, AT
);
5110 else if (mips_pic
== EMBEDDED_PIC
)
5113 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5115 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5116 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
5117 tempreg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5126 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5127 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5129 s
= HAVE_64BIT_ADDRESSES
? "daddu" : "addu";
5131 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
5132 "d,v,t", treg
, tempreg
, breg
);
5141 /* The j instruction may not be used in PIC code, since it
5142 requires an absolute address. We convert it to a b
5144 if (mips_pic
== NO_PIC
)
5145 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5147 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5150 /* The jal instructions must be handled as macros because when
5151 generating PIC code they expand to multi-instruction
5152 sequences. Normally they are simple instructions. */
5157 if (mips_pic
== NO_PIC
5158 || mips_pic
== EMBEDDED_PIC
)
5159 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5161 else if (mips_pic
== SVR4_PIC
)
5163 if (sreg
!= PIC_CALL_REG
)
5164 as_warn (_("MIPS PIC call to register other than $25"));
5166 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5170 if (mips_cprestore_offset
< 0)
5171 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5174 if (! mips_frame_reg_valid
)
5176 as_warn (_("No .frame pseudo-op used in PIC code"));
5177 /* Quiet this warning. */
5178 mips_frame_reg_valid
= 1;
5180 if (! mips_cprestore_valid
)
5182 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5183 /* Quiet this warning. */
5184 mips_cprestore_valid
= 1;
5186 expr1
.X_add_number
= mips_cprestore_offset
;
5187 macro_build ((char *) NULL
, &icnt
, &expr1
,
5188 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5189 mips_gp_register
, (int) BFD_RELOC_LO16
,
5200 if (mips_pic
== NO_PIC
)
5201 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5202 else if (mips_pic
== SVR4_PIC
)
5206 /* If this is a reference to an external symbol, and we are
5207 using a small GOT, we want
5208 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5212 lw $gp,cprestore($sp)
5213 The cprestore value is set using the .cprestore
5214 pseudo-op. If we are using a big GOT, we want
5215 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5217 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5221 lw $gp,cprestore($sp)
5222 If the symbol is not external, we want
5223 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5225 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5228 lw $gp,cprestore($sp) */
5232 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5233 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5234 "t,o(b)", PIC_CALL_REG
,
5235 (int) BFD_RELOC_MIPS_CALL16
, GP
);
5236 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5238 p
= frag_var (rs_machine_dependent
, 4, 0,
5239 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5240 offset_expr
.X_add_symbol
, 0, NULL
);
5246 if (reg_needs_delay (GP
))
5250 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5251 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
5252 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5253 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5254 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
5255 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5256 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5257 "t,o(b)", PIC_CALL_REG
,
5258 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5259 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5261 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5262 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
5264 offset_expr
.X_add_symbol
, 0, NULL
);
5267 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5270 macro_build (p
, &icnt
, &offset_expr
,
5271 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5272 "t,o(b)", PIC_CALL_REG
,
5273 (int) BFD_RELOC_MIPS_GOT16
, GP
);
5275 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5278 macro_build (p
, &icnt
, &offset_expr
,
5279 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5280 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5281 (int) BFD_RELOC_LO16
);
5282 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5283 "jalr", "s", PIC_CALL_REG
);
5286 if (mips_cprestore_offset
< 0)
5287 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5290 if (! mips_frame_reg_valid
)
5292 as_warn (_("No .frame pseudo-op used in PIC code"));
5293 /* Quiet this warning. */
5294 mips_frame_reg_valid
= 1;
5296 if (! mips_cprestore_valid
)
5298 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5299 /* Quiet this warning. */
5300 mips_cprestore_valid
= 1;
5302 if (mips_opts
.noreorder
)
5303 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5305 expr1
.X_add_number
= mips_cprestore_offset
;
5306 macro_build ((char *) NULL
, &icnt
, &expr1
,
5307 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5308 mips_gp_register
, (int) BFD_RELOC_LO16
,
5313 else if (mips_pic
== EMBEDDED_PIC
)
5315 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5316 /* The linker may expand the call to a longer sequence which
5317 uses $at, so we must break rather than return. */
5342 /* Itbl support may require additional care here. */
5347 /* Itbl support may require additional care here. */
5352 /* Itbl support may require additional care here. */
5357 /* Itbl support may require additional care here. */
5369 if (mips_arch
== CPU_R4650
)
5371 as_bad (_("opcode not supported on this processor"));
5375 /* Itbl support may require additional care here. */
5380 /* Itbl support may require additional care here. */
5385 /* Itbl support may require additional care here. */
5405 if (breg
== treg
|| coproc
|| lr
)
5427 /* Itbl support may require additional care here. */
5432 /* Itbl support may require additional care here. */
5437 /* Itbl support may require additional care here. */
5442 /* Itbl support may require additional care here. */
5458 if (mips_arch
== CPU_R4650
)
5460 as_bad (_("opcode not supported on this processor"));
5465 /* Itbl support may require additional care here. */
5469 /* Itbl support may require additional care here. */
5474 /* Itbl support may require additional care here. */
5486 /* Itbl support may require additional care here. */
5487 if (mask
== M_LWC1_AB
5488 || mask
== M_SWC1_AB
5489 || mask
== M_LDC1_AB
5490 || mask
== M_SDC1_AB
5499 /* For embedded PIC, we allow loads where the offset is calculated
5500 by subtracting a symbol in the current segment from an unknown
5501 symbol, relative to a base register, e.g.:
5502 <op> $treg, <sym>-<localsym>($breg)
5503 This is used by the compiler for switch statements. */
5504 if (mips_pic
== EMBEDDED_PIC
5505 && offset_expr
.X_op
== O_subtract
5506 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5507 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5508 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5510 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5514 && (offset_expr
.X_add_number
== 0
5515 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5517 /* For this case, we output the instructions:
5518 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5519 addiu $tempreg,$tempreg,$breg
5520 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5521 If the relocation would fit entirely in 16 bits, it would be
5523 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5524 instead, but that seems quite difficult. */
5525 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5526 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5527 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5528 ((bfd_arch_bits_per_address (stdoutput
) == 32
5529 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5530 ? "addu" : "daddu"),
5531 "d,v,t", tempreg
, tempreg
, breg
);
5532 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5533 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5539 if (offset_expr
.X_op
!= O_constant
5540 && offset_expr
.X_op
!= O_symbol
)
5542 as_bad (_("expression too complex"));
5543 offset_expr
.X_op
= O_constant
;
5546 /* A constant expression in PIC code can be handled just as it
5547 is in non PIC code. */
5548 if (mips_pic
== NO_PIC
5549 || offset_expr
.X_op
== O_constant
)
5553 /* If this is a reference to a GP relative symbol, and there
5554 is no base register, we want
5555 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5556 Otherwise, if there is no base register, we want
5557 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5558 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5559 If we have a constant, we need two instructions anyhow,
5560 so we always use the latter form.
5562 If we have a base register, and this is a reference to a
5563 GP relative symbol, we want
5564 addu $tempreg,$breg,$gp
5565 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5567 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5568 addu $tempreg,$tempreg,$breg
5569 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5570 With a constant we always use the latter case.
5572 With 64bit address space and no base register and $at usable,
5574 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5575 lui $at,<sym> (BFD_RELOC_HI16_S)
5576 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5579 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5580 If we have a base register, we want
5581 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5582 lui $at,<sym> (BFD_RELOC_HI16_S)
5583 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5587 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5589 Without $at we can't generate the optimal path for superscalar
5590 processors here since this would require two temporary registers.
5591 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5592 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5594 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5596 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5597 If we have a base register, we want
5598 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5599 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5601 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5603 daddu $tempreg,$tempreg,$breg
5604 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5606 If we have 64-bit addresses, as an optimization, for
5607 addresses which are 32-bit constants (e.g. kseg0/kseg1
5608 addresses) we fall back to the 32-bit address generation
5609 mechanism since it is more efficient. This code should
5610 probably attempt to generate 64-bit constants more
5611 efficiently in general.
5613 if (HAVE_64BIT_ADDRESSES
5614 && !(offset_expr
.X_op
== O_constant
5615 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
)))
5619 /* We don't do GP optimization for now because RELAX_ENCODE can't
5620 hold the data for such large chunks. */
5624 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5625 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5626 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5627 AT
, (int) BFD_RELOC_HI16_S
);
5628 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5629 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5631 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5632 "d,v,t", AT
, AT
, breg
);
5633 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5634 "d,w,<", tempreg
, tempreg
, 0);
5635 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5636 "d,v,t", tempreg
, tempreg
, AT
);
5637 macro_build (p
, &icnt
, &offset_expr
, s
,
5638 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5643 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5644 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5645 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5646 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5647 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5648 "d,w,<", tempreg
, tempreg
, 16);
5649 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5650 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5651 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5652 "d,w,<", tempreg
, tempreg
, 16);
5654 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5655 "d,v,t", tempreg
, tempreg
, breg
);
5656 macro_build (p
, &icnt
, &offset_expr
, s
,
5657 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5665 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5666 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5671 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5672 treg
, (int) BFD_RELOC_GPREL16
,
5674 p
= frag_var (rs_machine_dependent
, 8, 0,
5675 RELAX_ENCODE (4, 8, 0, 4, 0,
5676 (mips_opts
.warn_about_macros
5678 && mips_opts
.noat
))),
5679 offset_expr
.X_add_symbol
, 0, NULL
);
5682 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5685 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5686 (int) BFD_RELOC_LO16
, tempreg
);
5690 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5691 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5696 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5697 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5698 "d,v,t", tempreg
, breg
, mips_gp_register
);
5699 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5700 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5701 p
= frag_var (rs_machine_dependent
, 12, 0,
5702 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5703 offset_expr
.X_add_symbol
, 0, NULL
);
5705 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5708 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5709 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5710 "d,v,t", tempreg
, tempreg
, breg
);
5713 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5714 (int) BFD_RELOC_LO16
, tempreg
);
5717 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5721 /* If this is a reference to an external symbol, we want
5722 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5724 <op> $treg,0($tempreg)
5726 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5728 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5729 <op> $treg,0($tempreg)
5730 If there is a base register, we add it to $tempreg before
5731 the <op>. If there is a constant, we stick it in the
5732 <op> instruction. We don't handle constants larger than
5733 16 bits, because we have no way to load the upper 16 bits
5734 (actually, we could handle them for the subset of cases
5735 in which we are not using $at). */
5736 assert (offset_expr
.X_op
== O_symbol
);
5737 expr1
.X_add_number
= offset_expr
.X_add_number
;
5738 offset_expr
.X_add_number
= 0;
5739 if (expr1
.X_add_number
< -0x8000
5740 || expr1
.X_add_number
>= 0x8000)
5741 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5743 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5744 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", tempreg
,
5745 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5746 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5747 p
= frag_var (rs_machine_dependent
, 4, 0,
5748 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5749 offset_expr
.X_add_symbol
, 0, NULL
);
5750 macro_build (p
, &icnt
, &offset_expr
,
5751 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5752 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5754 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5755 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5756 "d,v,t", tempreg
, tempreg
, breg
);
5757 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5758 (int) BFD_RELOC_LO16
, tempreg
);
5760 else if (mips_pic
== SVR4_PIC
)
5765 /* If this is a reference to an external symbol, we want
5766 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5767 addu $tempreg,$tempreg,$gp
5768 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5769 <op> $treg,0($tempreg)
5771 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5773 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5774 <op> $treg,0($tempreg)
5775 If there is a base register, we add it to $tempreg before
5776 the <op>. If there is a constant, we stick it in the
5777 <op> instruction. We don't handle constants larger than
5778 16 bits, because we have no way to load the upper 16 bits
5779 (actually, we could handle them for the subset of cases
5780 in which we are not using $at). */
5781 assert (offset_expr
.X_op
== O_symbol
);
5782 expr1
.X_add_number
= offset_expr
.X_add_number
;
5783 offset_expr
.X_add_number
= 0;
5784 if (expr1
.X_add_number
< -0x8000
5785 || expr1
.X_add_number
>= 0x8000)
5786 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5787 if (reg_needs_delay (GP
))
5792 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5793 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5794 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5795 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5796 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5797 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5798 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5799 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5801 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5802 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5803 offset_expr
.X_add_symbol
, 0, NULL
);
5806 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5809 macro_build (p
, &icnt
, &offset_expr
,
5810 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5811 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
5814 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5816 macro_build (p
, &icnt
, &offset_expr
,
5817 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5818 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5820 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5821 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5822 "d,v,t", tempreg
, tempreg
, breg
);
5823 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5824 (int) BFD_RELOC_LO16
, tempreg
);
5826 else if (mips_pic
== EMBEDDED_PIC
)
5828 /* If there is no base register, we want
5829 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5830 If there is a base register, we want
5831 addu $tempreg,$breg,$gp
5832 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5834 assert (offset_expr
.X_op
== O_symbol
);
5837 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5838 treg
, (int) BFD_RELOC_GPREL16
, mips_gp_register
);
5843 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5844 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5845 "d,v,t", tempreg
, breg
, mips_gp_register
);
5846 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5847 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5860 load_register (&icnt
, treg
, &imm_expr
, 0);
5864 load_register (&icnt
, treg
, &imm_expr
, 1);
5868 if (imm_expr
.X_op
== O_constant
)
5870 load_register (&icnt
, AT
, &imm_expr
, 0);
5871 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5872 "mtc1", "t,G", AT
, treg
);
5877 assert (offset_expr
.X_op
== O_symbol
5878 && strcmp (segment_name (S_GET_SEGMENT
5879 (offset_expr
.X_add_symbol
)),
5881 && offset_expr
.X_add_number
== 0);
5882 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5883 treg
, (int) BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
5888 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5889 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5890 order 32 bits of the value and the low order 32 bits are either
5891 zero or in OFFSET_EXPR. */
5892 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5894 if (HAVE_64BIT_GPRS
)
5895 load_register (&icnt
, treg
, &imm_expr
, 1);
5900 if (target_big_endian
)
5912 load_register (&icnt
, hreg
, &imm_expr
, 0);
5915 if (offset_expr
.X_op
== O_absent
)
5916 move_register (&icnt
, lreg
, 0);
5919 assert (offset_expr
.X_op
== O_constant
);
5920 load_register (&icnt
, lreg
, &offset_expr
, 0);
5927 /* We know that sym is in the .rdata section. First we get the
5928 upper 16 bits of the address. */
5929 if (mips_pic
== NO_PIC
)
5931 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
5933 else if (mips_pic
== SVR4_PIC
)
5935 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5936 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5937 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
5940 else if (mips_pic
== EMBEDDED_PIC
)
5942 /* For embedded PIC we pick up the entire address off $gp in
5943 a single instruction. */
5944 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5945 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j", AT
,
5946 mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5947 offset_expr
.X_op
= O_constant
;
5948 offset_expr
.X_add_number
= 0;
5953 /* Now we load the register(s). */
5954 if (HAVE_64BIT_GPRS
)
5955 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5956 treg
, (int) BFD_RELOC_LO16
, AT
);
5959 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5960 treg
, (int) BFD_RELOC_LO16
, AT
);
5963 /* FIXME: How in the world do we deal with the possible
5965 offset_expr
.X_add_number
+= 4;
5966 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5967 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5971 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5972 does not become a variant frag. */
5973 frag_wane (frag_now
);
5979 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5980 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5981 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5982 the value and the low order 32 bits are either zero or in
5984 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5986 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
5987 if (HAVE_64BIT_FPRS
)
5989 assert (HAVE_64BIT_GPRS
);
5990 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5991 "dmtc1", "t,S", AT
, treg
);
5995 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5996 "mtc1", "t,G", AT
, treg
+ 1);
5997 if (offset_expr
.X_op
== O_absent
)
5998 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5999 "mtc1", "t,G", 0, treg
);
6002 assert (offset_expr
.X_op
== O_constant
);
6003 load_register (&icnt
, AT
, &offset_expr
, 0);
6004 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6005 "mtc1", "t,G", AT
, treg
);
6011 assert (offset_expr
.X_op
== O_symbol
6012 && offset_expr
.X_add_number
== 0);
6013 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6014 if (strcmp (s
, ".lit8") == 0)
6016 if (mips_opts
.isa
!= ISA_MIPS1
)
6018 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6019 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
,
6023 breg
= mips_gp_register
;
6024 r
= BFD_RELOC_MIPS_LITERAL
;
6029 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6030 if (mips_pic
== SVR4_PIC
)
6031 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6032 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6033 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6037 /* FIXME: This won't work for a 64 bit address. */
6038 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6041 if (mips_opts
.isa
!= ISA_MIPS1
)
6043 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6044 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
6046 /* To avoid confusion in tc_gen_reloc, we must ensure
6047 that this does not become a variant frag. */
6048 frag_wane (frag_now
);
6059 if (mips_arch
== CPU_R4650
)
6061 as_bad (_("opcode not supported on this processor"));
6064 /* Even on a big endian machine $fn comes before $fn+1. We have
6065 to adjust when loading from memory. */
6068 assert (mips_opts
.isa
== ISA_MIPS1
);
6069 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6070 target_big_endian
? treg
+ 1 : treg
,
6072 /* FIXME: A possible overflow which I don't know how to deal
6074 offset_expr
.X_add_number
+= 4;
6075 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6076 target_big_endian
? treg
: treg
+ 1,
6079 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6080 does not become a variant frag. */
6081 frag_wane (frag_now
);
6090 * The MIPS assembler seems to check for X_add_number not
6091 * being double aligned and generating:
6094 * addiu at,at,%lo(foo+1)
6097 * But, the resulting address is the same after relocation so why
6098 * generate the extra instruction?
6100 if (mips_arch
== CPU_R4650
)
6102 as_bad (_("opcode not supported on this processor"));
6105 /* Itbl support may require additional care here. */
6107 if (mips_opts
.isa
!= ISA_MIPS1
)
6118 if (mips_arch
== CPU_R4650
)
6120 as_bad (_("opcode not supported on this processor"));
6124 if (mips_opts
.isa
!= ISA_MIPS1
)
6132 /* Itbl support may require additional care here. */
6137 if (HAVE_64BIT_GPRS
)
6148 if (HAVE_64BIT_GPRS
)
6158 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6159 loads for the case of doing a pair of loads to simulate an 'ld'.
6160 This is not currently done by the compiler, and assembly coders
6161 writing embedded-pic code can cope. */
6163 if (offset_expr
.X_op
!= O_symbol
6164 && offset_expr
.X_op
!= O_constant
)
6166 as_bad (_("expression too complex"));
6167 offset_expr
.X_op
= O_constant
;
6170 /* Even on a big endian machine $fn comes before $fn+1. We have
6171 to adjust when loading from memory. We set coproc if we must
6172 load $fn+1 first. */
6173 /* Itbl support may require additional care here. */
6174 if (! target_big_endian
)
6177 if (mips_pic
== NO_PIC
6178 || offset_expr
.X_op
== O_constant
)
6182 /* If this is a reference to a GP relative symbol, we want
6183 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6184 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6185 If we have a base register, we use this
6187 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6188 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6189 If this is not a GP relative symbol, we want
6190 lui $at,<sym> (BFD_RELOC_HI16_S)
6191 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6192 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6193 If there is a base register, we add it to $at after the
6194 lui instruction. If there is a constant, we always use
6196 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6197 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6209 tempreg
= mips_gp_register
;
6216 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6217 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6218 "d,v,t", AT
, breg
, mips_gp_register
);
6224 /* Itbl support may require additional care here. */
6225 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6226 coproc
? treg
+ 1 : treg
,
6227 (int) BFD_RELOC_GPREL16
, tempreg
);
6228 offset_expr
.X_add_number
+= 4;
6230 /* Set mips_optimize to 2 to avoid inserting an
6232 hold_mips_optimize
= mips_optimize
;
6234 /* Itbl support may require additional care here. */
6235 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6236 coproc
? treg
: treg
+ 1,
6237 (int) BFD_RELOC_GPREL16
, tempreg
);
6238 mips_optimize
= hold_mips_optimize
;
6240 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6241 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6242 used_at
&& mips_opts
.noat
),
6243 offset_expr
.X_add_symbol
, 0, NULL
);
6245 /* We just generated two relocs. When tc_gen_reloc
6246 handles this case, it will skip the first reloc and
6247 handle the second. The second reloc already has an
6248 extra addend of 4, which we added above. We must
6249 subtract it out, and then subtract another 4 to make
6250 the first reloc come out right. The second reloc
6251 will come out right because we are going to add 4 to
6252 offset_expr when we build its instruction below.
6254 If we have a symbol, then we don't want to include
6255 the offset, because it will wind up being included
6256 when we generate the reloc. */
6258 if (offset_expr
.X_op
== O_constant
)
6259 offset_expr
.X_add_number
-= 8;
6262 offset_expr
.X_add_number
= -4;
6263 offset_expr
.X_op
= O_constant
;
6266 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6271 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6272 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6273 "d,v,t", AT
, breg
, AT
);
6277 /* Itbl support may require additional care here. */
6278 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6279 coproc
? treg
+ 1 : treg
,
6280 (int) BFD_RELOC_LO16
, AT
);
6283 /* FIXME: How do we handle overflow here? */
6284 offset_expr
.X_add_number
+= 4;
6285 /* Itbl support may require additional care here. */
6286 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6287 coproc
? treg
: treg
+ 1,
6288 (int) BFD_RELOC_LO16
, AT
);
6290 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6294 /* If this is a reference to an external symbol, we want
6295 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6300 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6302 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6303 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6304 If there is a base register we add it to $at before the
6305 lwc1 instructions. If there is a constant we include it
6306 in the lwc1 instructions. */
6308 expr1
.X_add_number
= offset_expr
.X_add_number
;
6309 offset_expr
.X_add_number
= 0;
6310 if (expr1
.X_add_number
< -0x8000
6311 || expr1
.X_add_number
>= 0x8000 - 4)
6312 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6317 frag_grow (24 + off
);
6318 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6319 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", AT
,
6320 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6321 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6323 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6324 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6325 "d,v,t", AT
, breg
, AT
);
6326 /* Itbl support may require additional care here. */
6327 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6328 coproc
? treg
+ 1 : treg
,
6329 (int) BFD_RELOC_LO16
, AT
);
6330 expr1
.X_add_number
+= 4;
6332 /* Set mips_optimize to 2 to avoid inserting an undesired
6334 hold_mips_optimize
= mips_optimize
;
6336 /* Itbl support may require additional care here. */
6337 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6338 coproc
? treg
: treg
+ 1,
6339 (int) BFD_RELOC_LO16
, AT
);
6340 mips_optimize
= hold_mips_optimize
;
6342 (void) frag_var (rs_machine_dependent
, 0, 0,
6343 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6344 offset_expr
.X_add_symbol
, 0, NULL
);
6346 else if (mips_pic
== SVR4_PIC
)
6351 /* If this is a reference to an external symbol, we want
6352 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6354 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6359 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6361 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6362 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6363 If there is a base register we add it to $at before the
6364 lwc1 instructions. If there is a constant we include it
6365 in the lwc1 instructions. */
6367 expr1
.X_add_number
= offset_expr
.X_add_number
;
6368 offset_expr
.X_add_number
= 0;
6369 if (expr1
.X_add_number
< -0x8000
6370 || expr1
.X_add_number
>= 0x8000 - 4)
6371 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6372 if (reg_needs_delay (mips_gp_register
))
6381 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6382 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6383 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6384 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6385 "d,v,t", AT
, AT
, mips_gp_register
);
6386 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6387 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6388 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6389 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6391 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6392 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6393 "d,v,t", AT
, breg
, AT
);
6394 /* Itbl support may require additional care here. */
6395 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6396 coproc
? treg
+ 1 : treg
,
6397 (int) BFD_RELOC_LO16
, AT
);
6398 expr1
.X_add_number
+= 4;
6400 /* Set mips_optimize to 2 to avoid inserting an undesired
6402 hold_mips_optimize
= mips_optimize
;
6404 /* Itbl support may require additional care here. */
6405 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6406 coproc
? treg
: treg
+ 1,
6407 (int) BFD_RELOC_LO16
, AT
);
6408 mips_optimize
= hold_mips_optimize
;
6409 expr1
.X_add_number
-= 4;
6411 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6412 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6413 8 + gpdel
+ off
, 1, 0),
6414 offset_expr
.X_add_symbol
, 0, NULL
);
6417 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6420 macro_build (p
, &icnt
, &offset_expr
,
6421 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6422 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6425 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6429 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6430 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6431 "d,v,t", AT
, breg
, AT
);
6434 /* Itbl support may require additional care here. */
6435 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6436 coproc
? treg
+ 1 : treg
,
6437 (int) BFD_RELOC_LO16
, AT
);
6439 expr1
.X_add_number
+= 4;
6441 /* Set mips_optimize to 2 to avoid inserting an undesired
6443 hold_mips_optimize
= mips_optimize
;
6445 /* Itbl support may require additional care here. */
6446 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6447 coproc
? treg
: treg
+ 1,
6448 (int) BFD_RELOC_LO16
, AT
);
6449 mips_optimize
= hold_mips_optimize
;
6451 else if (mips_pic
== EMBEDDED_PIC
)
6453 /* If there is no base register, we use
6454 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6455 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6456 If we have a base register, we use
6458 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6459 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6463 tempreg
= mips_gp_register
;
6468 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6469 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6470 "d,v,t", AT
, breg
, mips_gp_register
);
6475 /* Itbl support may require additional care here. */
6476 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6477 coproc
? treg
+ 1 : treg
,
6478 (int) BFD_RELOC_GPREL16
, tempreg
);
6479 offset_expr
.X_add_number
+= 4;
6480 /* Itbl support may require additional care here. */
6481 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6482 coproc
? treg
: treg
+ 1,
6483 (int) BFD_RELOC_GPREL16
, tempreg
);
6499 assert (HAVE_32BIT_ADDRESSES
);
6500 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6501 (int) BFD_RELOC_LO16
, breg
);
6502 offset_expr
.X_add_number
+= 4;
6503 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6504 (int) BFD_RELOC_LO16
, breg
);
6507 /* New code added to support COPZ instructions.
6508 This code builds table entries out of the macros in mip_opcodes.
6509 R4000 uses interlocks to handle coproc delays.
6510 Other chips (like the R3000) require nops to be inserted for delays.
6512 FIXME: Currently, we require that the user handle delays.
6513 In order to fill delay slots for non-interlocked chips,
6514 we must have a way to specify delays based on the coprocessor.
6515 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6516 What are the side-effects of the cop instruction?
6517 What cache support might we have and what are its effects?
6518 Both coprocessor & memory require delays. how long???
6519 What registers are read/set/modified?
6521 If an itbl is provided to interpret cop instructions,
6522 this knowledge can be encoded in the itbl spec. */
6536 /* For now we just do C (same as Cz). The parameter will be
6537 stored in insn_opcode by mips_ip. */
6538 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6543 move_register (&icnt
, dreg
, sreg
);
6546 #ifdef LOSING_COMPILER
6548 /* Try and see if this is a new itbl instruction.
6549 This code builds table entries out of the macros in mip_opcodes.
6550 FIXME: For now we just assemble the expression and pass it's
6551 value along as a 32-bit immediate.
6552 We may want to have the assembler assemble this value,
6553 so that we gain the assembler's knowledge of delay slots,
6555 Would it be more efficient to use mask (id) here? */
6556 if (itbl_have_entries
6557 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6559 s
= ip
->insn_mo
->name
;
6561 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6562 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6569 as_warn (_("Macro used $at after \".set noat\""));
6574 struct mips_cl_insn
*ip
;
6576 register int treg
, sreg
, dreg
, breg
;
6592 bfd_reloc_code_real_type r
;
6595 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6596 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6597 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6598 mask
= ip
->insn_mo
->mask
;
6600 expr1
.X_op
= O_constant
;
6601 expr1
.X_op_symbol
= NULL
;
6602 expr1
.X_add_symbol
= NULL
;
6603 expr1
.X_add_number
= 1;
6607 #endif /* LOSING_COMPILER */
6612 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6613 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6614 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6621 /* The MIPS assembler some times generates shifts and adds. I'm
6622 not trying to be that fancy. GCC should do this for us
6624 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6625 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6626 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6627 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6641 mips_emit_delays (true);
6642 ++mips_opts
.noreorder
;
6643 mips_any_noreorder
= 1;
6645 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6646 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6647 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6648 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6650 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6651 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6652 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6655 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne", "s,t",
6659 expr1
.X_add_number
= 8;
6660 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
6662 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6664 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6667 --mips_opts
.noreorder
;
6668 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
6681 mips_emit_delays (true);
6682 ++mips_opts
.noreorder
;
6683 mips_any_noreorder
= 1;
6685 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6686 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6687 dbl
? "dmultu" : "multu",
6688 "s,t", sreg
, imm
? AT
: treg
);
6689 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6691 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6694 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne", "s,t",
6698 expr1
.X_add_number
= 8;
6699 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6700 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6702 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6705 --mips_opts
.noreorder
;
6709 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6710 "d,v,t", AT
, 0, treg
);
6711 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6712 "d,t,s", AT
, sreg
, AT
);
6713 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6714 "d,t,s", dreg
, sreg
, treg
);
6715 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6716 "d,v,t", dreg
, dreg
, AT
);
6720 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6721 "d,v,t", AT
, 0, treg
);
6722 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6723 "d,t,s", AT
, sreg
, AT
);
6724 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6725 "d,t,s", dreg
, sreg
, treg
);
6726 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6727 "d,v,t", dreg
, dreg
, AT
);
6735 if (imm_expr
.X_op
!= O_constant
)
6736 as_bad (_("rotate count too large"));
6737 rot
= imm_expr
.X_add_number
& 0x3f;
6740 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6741 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6743 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
6744 "d,w,<", AT
, sreg
, rot
);
6745 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
6746 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6747 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6748 "d,v,t", dreg
, dreg
, AT
);
6756 if (imm_expr
.X_op
!= O_constant
)
6757 as_bad (_("rotate count too large"));
6758 rot
= imm_expr
.X_add_number
& 0x1f;
6761 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
6762 "d,w,<", AT
, sreg
, rot
);
6763 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6764 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6765 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6766 "d,v,t", dreg
, dreg
, AT
);
6771 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6772 "d,v,t", AT
, 0, treg
);
6773 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6774 "d,t,s", AT
, sreg
, AT
);
6775 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6776 "d,t,s", dreg
, sreg
, treg
);
6777 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6778 "d,v,t", dreg
, dreg
, AT
);
6782 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6783 "d,v,t", AT
, 0, treg
);
6784 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6785 "d,t,s", AT
, sreg
, AT
);
6786 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6787 "d,t,s", dreg
, sreg
, treg
);
6788 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6789 "d,v,t", dreg
, dreg
, AT
);
6797 if (imm_expr
.X_op
!= O_constant
)
6798 as_bad (_("rotate count too large"));
6799 rot
= imm_expr
.X_add_number
& 0x3f;
6802 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6803 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6805 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
6806 "d,w,<", AT
, sreg
, rot
);
6807 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
6808 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6809 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6810 "d,v,t", dreg
, dreg
, AT
);
6818 if (imm_expr
.X_op
!= O_constant
)
6819 as_bad (_("rotate count too large"));
6820 rot
= imm_expr
.X_add_number
& 0x1f;
6823 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
6824 "d,w,<", AT
, sreg
, rot
);
6825 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
6826 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6827 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6828 "d,v,t", dreg
, dreg
, AT
);
6833 if (mips_arch
== CPU_R4650
)
6835 as_bad (_("opcode not supported on this processor"));
6838 assert (mips_opts
.isa
== ISA_MIPS1
);
6839 /* Even on a big endian machine $fn comes before $fn+1. We have
6840 to adjust when storing to memory. */
6841 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6842 target_big_endian
? treg
+ 1 : treg
,
6843 (int) BFD_RELOC_LO16
, breg
);
6844 offset_expr
.X_add_number
+= 4;
6845 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6846 target_big_endian
? treg
: treg
+ 1,
6847 (int) BFD_RELOC_LO16
, breg
);
6852 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6853 treg
, (int) BFD_RELOC_LO16
);
6855 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6856 sreg
, (int) BFD_RELOC_LO16
);
6859 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6860 "d,v,t", dreg
, sreg
, treg
);
6861 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6862 dreg
, (int) BFD_RELOC_LO16
);
6867 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6869 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6870 sreg
, (int) BFD_RELOC_LO16
);
6875 as_warn (_("Instruction %s: result is always false"),
6877 move_register (&icnt
, dreg
, 0);
6880 if (imm_expr
.X_op
== O_constant
6881 && imm_expr
.X_add_number
>= 0
6882 && imm_expr
.X_add_number
< 0x10000)
6884 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6885 sreg
, (int) BFD_RELOC_LO16
);
6888 else if (imm_expr
.X_op
== O_constant
6889 && imm_expr
.X_add_number
> -0x8000
6890 && imm_expr
.X_add_number
< 0)
6892 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6893 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6894 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6895 "t,r,j", dreg
, sreg
,
6896 (int) BFD_RELOC_LO16
);
6901 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6902 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6903 "d,v,t", dreg
, sreg
, AT
);
6906 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6907 (int) BFD_RELOC_LO16
);
6912 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6918 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6920 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6921 (int) BFD_RELOC_LO16
);
6924 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6926 if (imm_expr
.X_op
== O_constant
6927 && imm_expr
.X_add_number
>= -0x8000
6928 && imm_expr
.X_add_number
< 0x8000)
6930 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6931 mask
== M_SGE_I
? "slti" : "sltiu",
6932 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6937 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6938 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6939 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
6943 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6944 (int) BFD_RELOC_LO16
);
6949 case M_SGT
: /* sreg > treg <==> treg < sreg */
6955 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6959 case M_SGT_I
: /* sreg > I <==> I < sreg */
6965 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6966 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6970 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6976 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6978 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6979 (int) BFD_RELOC_LO16
);
6982 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6988 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6989 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6991 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6992 (int) BFD_RELOC_LO16
);
6996 if (imm_expr
.X_op
== O_constant
6997 && imm_expr
.X_add_number
>= -0x8000
6998 && imm_expr
.X_add_number
< 0x8000)
7000 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
7001 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7004 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7005 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
7010 if (imm_expr
.X_op
== O_constant
7011 && imm_expr
.X_add_number
>= -0x8000
7012 && imm_expr
.X_add_number
< 0x8000)
7014 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
7015 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7018 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7019 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7020 "d,v,t", dreg
, sreg
, AT
);
7025 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7026 "d,v,t", dreg
, 0, treg
);
7028 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7029 "d,v,t", dreg
, 0, sreg
);
7032 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7033 "d,v,t", dreg
, sreg
, treg
);
7034 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7035 "d,v,t", dreg
, 0, dreg
);
7040 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7042 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7043 "d,v,t", dreg
, 0, sreg
);
7048 as_warn (_("Instruction %s: result is always true"),
7050 macro_build ((char *) NULL
, &icnt
, &expr1
,
7051 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7052 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
7055 if (imm_expr
.X_op
== O_constant
7056 && imm_expr
.X_add_number
>= 0
7057 && imm_expr
.X_add_number
< 0x10000)
7059 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
7060 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7063 else if (imm_expr
.X_op
== O_constant
7064 && imm_expr
.X_add_number
> -0x8000
7065 && imm_expr
.X_add_number
< 0)
7067 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7068 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7069 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7070 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7075 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7076 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7077 "d,v,t", dreg
, sreg
, AT
);
7080 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7081 "d,v,t", dreg
, 0, dreg
);
7089 if (imm_expr
.X_op
== O_constant
7090 && imm_expr
.X_add_number
> -0x8000
7091 && imm_expr
.X_add_number
<= 0x8000)
7093 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7094 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7095 dbl
? "daddi" : "addi",
7096 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7099 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7100 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7101 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7107 if (imm_expr
.X_op
== O_constant
7108 && imm_expr
.X_add_number
> -0x8000
7109 && imm_expr
.X_add_number
<= 0x8000)
7111 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7112 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7113 dbl
? "daddiu" : "addiu",
7114 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7117 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7118 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7119 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7140 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7141 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
7147 assert (mips_opts
.isa
== ISA_MIPS1
);
7148 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7149 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7152 * Is the double cfc1 instruction a bug in the mips assembler;
7153 * or is there a reason for it?
7155 mips_emit_delays (true);
7156 ++mips_opts
.noreorder
;
7157 mips_any_noreorder
= 1;
7158 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7160 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7162 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7163 expr1
.X_add_number
= 3;
7164 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7165 (int) BFD_RELOC_LO16
);
7166 expr1
.X_add_number
= 2;
7167 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7168 (int) BFD_RELOC_LO16
);
7169 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7171 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7172 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7173 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
7174 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7176 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7177 --mips_opts
.noreorder
;
7186 if (offset_expr
.X_add_number
>= 0x7fff)
7187 as_bad (_("operand overflow"));
7188 /* avoid load delay */
7189 if (! target_big_endian
)
7190 ++offset_expr
.X_add_number
;
7191 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7192 (int) BFD_RELOC_LO16
, breg
);
7193 if (! target_big_endian
)
7194 --offset_expr
.X_add_number
;
7196 ++offset_expr
.X_add_number
;
7197 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
7198 (int) BFD_RELOC_LO16
, breg
);
7199 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7201 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7215 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7216 as_bad (_("operand overflow"));
7217 if (! target_big_endian
)
7218 offset_expr
.X_add_number
+= off
;
7219 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7220 (int) BFD_RELOC_LO16
, breg
);
7221 if (! target_big_endian
)
7222 offset_expr
.X_add_number
-= off
;
7224 offset_expr
.X_add_number
+= off
;
7225 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7226 (int) BFD_RELOC_LO16
, breg
);
7240 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7242 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7243 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7244 "d,v,t", AT
, AT
, breg
);
7245 if (! target_big_endian
)
7246 expr1
.X_add_number
= off
;
7248 expr1
.X_add_number
= 0;
7249 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7250 (int) BFD_RELOC_LO16
, AT
);
7251 if (! target_big_endian
)
7252 expr1
.X_add_number
= 0;
7254 expr1
.X_add_number
= off
;
7255 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7256 (int) BFD_RELOC_LO16
, AT
);
7262 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7264 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7265 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7266 "d,v,t", AT
, AT
, breg
);
7267 if (target_big_endian
)
7268 expr1
.X_add_number
= 0;
7269 macro_build ((char *) NULL
, &icnt
, &expr1
,
7270 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7271 (int) BFD_RELOC_LO16
, AT
);
7272 if (target_big_endian
)
7273 expr1
.X_add_number
= 1;
7275 expr1
.X_add_number
= 0;
7276 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7277 (int) BFD_RELOC_LO16
, AT
);
7278 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7280 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7285 if (offset_expr
.X_add_number
>= 0x7fff)
7286 as_bad (_("operand overflow"));
7287 if (target_big_endian
)
7288 ++offset_expr
.X_add_number
;
7289 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7290 (int) BFD_RELOC_LO16
, breg
);
7291 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7293 if (target_big_endian
)
7294 --offset_expr
.X_add_number
;
7296 ++offset_expr
.X_add_number
;
7297 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7298 (int) BFD_RELOC_LO16
, breg
);
7311 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7312 as_bad (_("operand overflow"));
7313 if (! target_big_endian
)
7314 offset_expr
.X_add_number
+= off
;
7315 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7316 (int) BFD_RELOC_LO16
, breg
);
7317 if (! target_big_endian
)
7318 offset_expr
.X_add_number
-= off
;
7320 offset_expr
.X_add_number
+= off
;
7321 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7322 (int) BFD_RELOC_LO16
, breg
);
7336 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7338 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7339 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7340 "d,v,t", AT
, AT
, breg
);
7341 if (! target_big_endian
)
7342 expr1
.X_add_number
= off
;
7344 expr1
.X_add_number
= 0;
7345 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7346 (int) BFD_RELOC_LO16
, AT
);
7347 if (! target_big_endian
)
7348 expr1
.X_add_number
= 0;
7350 expr1
.X_add_number
= off
;
7351 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7352 (int) BFD_RELOC_LO16
, AT
);
7357 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7359 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7360 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7361 "d,v,t", AT
, AT
, breg
);
7362 if (! target_big_endian
)
7363 expr1
.X_add_number
= 0;
7364 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7365 (int) BFD_RELOC_LO16
, AT
);
7366 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7368 if (! target_big_endian
)
7369 expr1
.X_add_number
= 1;
7371 expr1
.X_add_number
= 0;
7372 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7373 (int) BFD_RELOC_LO16
, AT
);
7374 if (! target_big_endian
)
7375 expr1
.X_add_number
= 0;
7377 expr1
.X_add_number
= 1;
7378 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7379 (int) BFD_RELOC_LO16
, AT
);
7380 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7382 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7387 /* FIXME: Check if this is one of the itbl macros, since they
7388 are added dynamically. */
7389 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7393 as_warn (_("Macro used $at after \".set noat\""));
7396 /* Implement macros in mips16 mode. */
7400 struct mips_cl_insn
*ip
;
7403 int xreg
, yreg
, zreg
, tmp
;
7407 const char *s
, *s2
, *s3
;
7409 mask
= ip
->insn_mo
->mask
;
7411 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7412 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7413 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7417 expr1
.X_op
= O_constant
;
7418 expr1
.X_op_symbol
= NULL
;
7419 expr1
.X_add_symbol
= NULL
;
7420 expr1
.X_add_number
= 1;
7439 mips_emit_delays (true);
7440 ++mips_opts
.noreorder
;
7441 mips_any_noreorder
= 1;
7442 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7443 dbl
? "ddiv" : "div",
7444 "0,x,y", xreg
, yreg
);
7445 expr1
.X_add_number
= 2;
7446 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7447 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
7450 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7451 since that causes an overflow. We should do that as well,
7452 but I don't see how to do the comparisons without a temporary
7454 --mips_opts
.noreorder
;
7455 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
7474 mips_emit_delays (true);
7475 ++mips_opts
.noreorder
;
7476 mips_any_noreorder
= 1;
7477 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
7479 expr1
.X_add_number
= 2;
7480 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7481 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7483 --mips_opts
.noreorder
;
7484 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
7490 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7491 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7492 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
7501 if (imm_expr
.X_op
!= O_constant
)
7502 as_bad (_("Unsupported large constant"));
7503 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7504 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7505 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7509 if (imm_expr
.X_op
!= O_constant
)
7510 as_bad (_("Unsupported large constant"));
7511 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7512 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7517 if (imm_expr
.X_op
!= O_constant
)
7518 as_bad (_("Unsupported large constant"));
7519 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7520 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7543 goto do_reverse_branch
;
7547 goto do_reverse_branch
;
7559 goto do_reverse_branch
;
7570 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7572 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7599 goto do_addone_branch_i
;
7604 goto do_addone_branch_i
;
7619 goto do_addone_branch_i
;
7626 if (imm_expr
.X_op
!= O_constant
)
7627 as_bad (_("Unsupported large constant"));
7628 ++imm_expr
.X_add_number
;
7631 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7632 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7636 expr1
.X_add_number
= 0;
7637 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7639 move_register (&icnt
, xreg
, yreg
);
7640 expr1
.X_add_number
= 2;
7641 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7642 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7643 "neg", "x,w", xreg
, xreg
);
7647 /* For consistency checking, verify that all bits are specified either
7648 by the match/mask part of the instruction definition, or by the
7651 validate_mips_insn (opc
)
7652 const struct mips_opcode
*opc
;
7654 const char *p
= opc
->args
;
7656 unsigned long used_bits
= opc
->mask
;
7658 if ((used_bits
& opc
->match
) != opc
->match
)
7660 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7661 opc
->name
, opc
->args
);
7664 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7671 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7672 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7674 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7675 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7676 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7677 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7679 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7680 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7682 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7684 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7685 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7686 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7687 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7688 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7689 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7690 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7691 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7692 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7693 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7694 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7696 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7697 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7698 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7699 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7701 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7702 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7703 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7704 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7705 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7706 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7707 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7708 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7709 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7712 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7713 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7714 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7716 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7717 c
, opc
->name
, opc
->args
);
7721 if (used_bits
!= 0xffffffff)
7723 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7724 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7730 /* This routine assembles an instruction into its binary format. As a
7731 side effect, it sets one of the global variables imm_reloc or
7732 offset_reloc to the type of relocation to do if one of the operands
7733 is an address expression. */
7738 struct mips_cl_insn
*ip
;
7743 struct mips_opcode
*insn
;
7746 unsigned int lastregno
= 0;
7752 /* If the instruction contains a '.', we first try to match an instruction
7753 including the '.'. Then we try again without the '.'. */
7755 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7758 /* If we stopped on whitespace, then replace the whitespace with null for
7759 the call to hash_find. Save the character we replaced just in case we
7760 have to re-parse the instruction. */
7767 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7769 /* If we didn't find the instruction in the opcode table, try again, but
7770 this time with just the instruction up to, but not including the
7774 /* Restore the character we overwrite above (if any). */
7778 /* Scan up to the first '.' or whitespace. */
7780 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7784 /* If we did not find a '.', then we can quit now. */
7787 insn_error
= "unrecognized opcode";
7791 /* Lookup the instruction in the hash table. */
7793 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7795 insn_error
= "unrecognized opcode";
7805 assert (strcmp (insn
->name
, str
) == 0);
7807 if (OPCODE_IS_MEMBER (insn
,
7809 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7815 if (insn
->pinfo
!= INSN_MACRO
)
7817 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7823 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7824 && strcmp (insn
->name
, insn
[1].name
) == 0)
7833 static char buf
[100];
7835 _("opcode not supported on this processor: %s (%s)"),
7836 mips_cpu_to_str (mips_arch
),
7837 mips_isa_to_str (mips_opts
.isa
));
7848 ip
->insn_opcode
= insn
->match
;
7850 for (args
= insn
->args
;; ++args
)
7852 s
+= strspn (s
, " \t");
7855 case '\0': /* end of args */
7868 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7872 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7876 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7880 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7886 /* Handle optional base register.
7887 Either the base register is omitted or
7888 we must have a left paren. */
7889 /* This is dependent on the next operand specifier
7890 is a base register specification. */
7891 assert (args
[1] == 'b' || args
[1] == '5'
7892 || args
[1] == '-' || args
[1] == '4');
7896 case ')': /* these must match exactly */
7901 case '<': /* must be at least one digit */
7903 * According to the manual, if the shift amount is greater
7904 * than 31 or less than 0, then the shift amount should be
7905 * mod 32. In reality the mips assembler issues an error.
7906 * We issue a warning and mask out all but the low 5 bits.
7908 my_getExpression (&imm_expr
, s
);
7909 check_absolute_expr (ip
, &imm_expr
);
7910 if ((unsigned long) imm_expr
.X_add_number
> 31)
7912 as_warn (_("Improper shift amount (%ld)"),
7913 (long) imm_expr
.X_add_number
);
7914 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
7916 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
7917 imm_expr
.X_op
= O_absent
;
7921 case '>': /* shift amount minus 32 */
7922 my_getExpression (&imm_expr
, s
);
7923 check_absolute_expr (ip
, &imm_expr
);
7924 if ((unsigned long) imm_expr
.X_add_number
< 32
7925 || (unsigned long) imm_expr
.X_add_number
> 63)
7927 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
7928 imm_expr
.X_op
= O_absent
;
7932 case 'k': /* cache code */
7933 case 'h': /* prefx code */
7934 my_getExpression (&imm_expr
, s
);
7935 check_absolute_expr (ip
, &imm_expr
);
7936 if ((unsigned long) imm_expr
.X_add_number
> 31)
7938 as_warn (_("Invalid value for `%s' (%lu)"),
7940 (unsigned long) imm_expr
.X_add_number
);
7941 imm_expr
.X_add_number
&= 0x1f;
7944 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7946 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7947 imm_expr
.X_op
= O_absent
;
7951 case 'c': /* break code */
7952 my_getExpression (&imm_expr
, s
);
7953 check_absolute_expr (ip
, &imm_expr
);
7954 if ((unsigned) imm_expr
.X_add_number
> 1023)
7956 as_warn (_("Illegal break code (%ld)"),
7957 (long) imm_expr
.X_add_number
);
7958 imm_expr
.X_add_number
&= OP_MASK_CODE
;
7960 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
7961 imm_expr
.X_op
= O_absent
;
7965 case 'q': /* lower break code */
7966 my_getExpression (&imm_expr
, s
);
7967 check_absolute_expr (ip
, &imm_expr
);
7968 if ((unsigned) imm_expr
.X_add_number
> 1023)
7970 as_warn (_("Illegal lower break code (%ld)"),
7971 (long) imm_expr
.X_add_number
);
7972 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
7974 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
7975 imm_expr
.X_op
= O_absent
;
7979 case 'B': /* 20-bit syscall/break code. */
7980 my_getExpression (&imm_expr
, s
);
7981 check_absolute_expr (ip
, &imm_expr
);
7982 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE20
)
7983 as_warn (_("Illegal 20-bit code (%ld)"),
7984 (long) imm_expr
.X_add_number
);
7985 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
7986 imm_expr
.X_op
= O_absent
;
7990 case 'C': /* Coprocessor code */
7991 my_getExpression (&imm_expr
, s
);
7992 check_absolute_expr (ip
, &imm_expr
);
7993 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
7995 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7996 (long) imm_expr
.X_add_number
);
7997 imm_expr
.X_add_number
&= ((1 << 25) - 1);
7999 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8000 imm_expr
.X_op
= O_absent
;
8004 case 'J': /* 19-bit wait code. */
8005 my_getExpression (&imm_expr
, s
);
8006 check_absolute_expr (ip
, &imm_expr
);
8007 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8008 as_warn (_("Illegal 19-bit code (%ld)"),
8009 (long) imm_expr
.X_add_number
);
8010 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8011 imm_expr
.X_op
= O_absent
;
8015 case 'P': /* Performance register */
8016 my_getExpression (&imm_expr
, s
);
8017 check_absolute_expr (ip
, &imm_expr
);
8018 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8020 as_warn (_("Invalid performance register (%ld)"),
8021 (long) imm_expr
.X_add_number
);
8022 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8024 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8025 imm_expr
.X_op
= O_absent
;
8029 case 'b': /* base register */
8030 case 'd': /* destination register */
8031 case 's': /* source register */
8032 case 't': /* target register */
8033 case 'r': /* both target and source */
8034 case 'v': /* both dest and source */
8035 case 'w': /* both dest and target */
8036 case 'E': /* coprocessor target register */
8037 case 'G': /* coprocessor destination register */
8038 case 'x': /* ignore register name */
8039 case 'z': /* must be zero register */
8040 case 'U': /* destination register (clo/clz). */
8055 while (ISDIGIT (*s
));
8057 as_bad (_("Invalid register number (%d)"), regno
);
8059 else if (*args
== 'E' || *args
== 'G')
8063 if (s
[1] == 'f' && s
[2] == 'p')
8068 else if (s
[1] == 's' && s
[2] == 'p')
8073 else if (s
[1] == 'g' && s
[2] == 'p')
8078 else if (s
[1] == 'a' && s
[2] == 't')
8083 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8088 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8093 else if (itbl_have_entries
)
8098 p
= s
+ 1; /* advance past '$' */
8099 n
= itbl_get_field (&p
); /* n is name */
8101 /* See if this is a register defined in an
8103 if (itbl_get_reg_val (n
, &r
))
8105 /* Get_field advances to the start of
8106 the next field, so we need to back
8107 rack to the end of the last field. */
8111 s
= strchr (s
, '\0');
8124 as_warn (_("Used $at without \".set noat\""));
8130 if (c
== 'r' || c
== 'v' || c
== 'w')
8137 /* 'z' only matches $0. */
8138 if (c
== 'z' && regno
!= 0)
8141 /* Now that we have assembled one operand, we use the args string
8142 * to figure out where it goes in the instruction. */
8149 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8153 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8156 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8157 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8162 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8165 /* This case exists because on the r3000 trunc
8166 expands into a macro which requires a gp
8167 register. On the r6000 or r4000 it is
8168 assembled into a single instruction which
8169 ignores the register. Thus the insn version
8170 is MIPS_ISA2 and uses 'x', and the macro
8171 version is MIPS_ISA1 and uses 't'. */
8174 /* This case is for the div instruction, which
8175 acts differently if the destination argument
8176 is $0. This only matches $0, and is checked
8177 outside the switch. */
8180 /* Itbl operand; not yet implemented. FIXME ?? */
8182 /* What about all other operands like 'i', which
8183 can be specified in the opcode table? */
8193 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8196 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8201 case 'D': /* floating point destination register */
8202 case 'S': /* floating point source register */
8203 case 'T': /* floating point target register */
8204 case 'R': /* floating point source register */
8208 if (s
[0] == '$' && s
[1] == 'f'
8219 while (ISDIGIT (*s
));
8222 as_bad (_("Invalid float register number (%d)"), regno
);
8224 if ((regno
& 1) != 0
8226 && ! (strcmp (str
, "mtc1") == 0
8227 || strcmp (str
, "mfc1") == 0
8228 || strcmp (str
, "lwc1") == 0
8229 || strcmp (str
, "swc1") == 0
8230 || strcmp (str
, "l.s") == 0
8231 || strcmp (str
, "s.s") == 0))
8232 as_warn (_("Float register should be even, was %d"),
8240 if (c
== 'V' || c
== 'W')
8250 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8254 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8258 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8261 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8271 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8274 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8280 my_getExpression (&imm_expr
, s
);
8281 if (imm_expr
.X_op
!= O_big
8282 && imm_expr
.X_op
!= O_constant
)
8283 insn_error
= _("absolute expression required");
8288 my_getExpression (&offset_expr
, s
);
8289 *imm_reloc
= BFD_RELOC_32
;
8302 unsigned char temp
[8];
8304 unsigned int length
;
8309 /* These only appear as the last operand in an
8310 instruction, and every instruction that accepts
8311 them in any variant accepts them in all variants.
8312 This means we don't have to worry about backing out
8313 any changes if the instruction does not match.
8315 The difference between them is the size of the
8316 floating point constant and where it goes. For 'F'
8317 and 'L' the constant is 64 bits; for 'f' and 'l' it
8318 is 32 bits. Where the constant is placed is based
8319 on how the MIPS assembler does things:
8322 f -- immediate value
8325 The .lit4 and .lit8 sections are only used if
8326 permitted by the -G argument.
8328 When generating embedded PIC code, we use the
8329 .lit8 section but not the .lit4 section (we can do
8330 .lit4 inline easily; we need to put .lit8
8331 somewhere in the data segment, and using .lit8
8332 permits the linker to eventually combine identical
8335 The code below needs to know whether the target register
8336 is 32 or 64 bits wide. It relies on the fact 'f' and
8337 'F' are used with GPR-based instructions and 'l' and
8338 'L' are used with FPR-based instructions. */
8340 f64
= *args
== 'F' || *args
== 'L';
8341 using_gprs
= *args
== 'F' || *args
== 'f';
8343 save_in
= input_line_pointer
;
8344 input_line_pointer
= s
;
8345 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8347 s
= input_line_pointer
;
8348 input_line_pointer
= save_in
;
8349 if (err
!= NULL
&& *err
!= '\0')
8351 as_bad (_("Bad floating point constant: %s"), err
);
8352 memset (temp
, '\0', sizeof temp
);
8353 length
= f64
? 8 : 4;
8356 assert (length
== (unsigned) (f64
? 8 : 4));
8360 && (! USE_GLOBAL_POINTER_OPT
8361 || mips_pic
== EMBEDDED_PIC
8362 || g_switch_value
< 4
8363 || (temp
[0] == 0 && temp
[1] == 0)
8364 || (temp
[2] == 0 && temp
[3] == 0))))
8366 imm_expr
.X_op
= O_constant
;
8367 if (! target_big_endian
)
8368 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8370 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8373 && ! mips_disable_float_construction
8374 /* Constants can only be constructed in GPRs and
8375 copied to FPRs if the GPRs are at least as wide
8376 as the FPRs. Force the constant into memory if
8377 we are using 64-bit FPRs but the GPRs are only
8380 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8381 && ((temp
[0] == 0 && temp
[1] == 0)
8382 || (temp
[2] == 0 && temp
[3] == 0))
8383 && ((temp
[4] == 0 && temp
[5] == 0)
8384 || (temp
[6] == 0 && temp
[7] == 0)))
8386 /* The value is simple enough to load with a couple of
8387 instructions. If using 32-bit registers, set
8388 imm_expr to the high order 32 bits and offset_expr to
8389 the low order 32 bits. Otherwise, set imm_expr to
8390 the entire 64 bit constant. */
8391 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8393 imm_expr
.X_op
= O_constant
;
8394 offset_expr
.X_op
= O_constant
;
8395 if (! target_big_endian
)
8397 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8398 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8402 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8403 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8405 if (offset_expr
.X_add_number
== 0)
8406 offset_expr
.X_op
= O_absent
;
8408 else if (sizeof (imm_expr
.X_add_number
) > 4)
8410 imm_expr
.X_op
= O_constant
;
8411 if (! target_big_endian
)
8412 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8414 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8418 imm_expr
.X_op
= O_big
;
8419 imm_expr
.X_add_number
= 4;
8420 if (! target_big_endian
)
8422 generic_bignum
[0] = bfd_getl16 (temp
);
8423 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8424 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8425 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8429 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8430 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8431 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8432 generic_bignum
[3] = bfd_getb16 (temp
);
8438 const char *newname
;
8441 /* Switch to the right section. */
8443 subseg
= now_subseg
;
8446 default: /* unused default case avoids warnings. */
8448 newname
= RDATA_SECTION_NAME
;
8449 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8450 || mips_pic
== EMBEDDED_PIC
)
8454 if (mips_pic
== EMBEDDED_PIC
)
8457 newname
= RDATA_SECTION_NAME
;
8460 assert (!USE_GLOBAL_POINTER_OPT
8461 || g_switch_value
>= 4);
8465 new_seg
= subseg_new (newname
, (subsegT
) 0);
8466 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8467 bfd_set_section_flags (stdoutput
, new_seg
,
8472 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8473 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8474 && strcmp (TARGET_OS
, "elf") != 0)
8475 record_alignment (new_seg
, 4);
8477 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8479 as_bad (_("Can't use floating point insn in this section"));
8481 /* Set the argument to the current address in the
8483 offset_expr
.X_op
= O_symbol
;
8484 offset_expr
.X_add_symbol
=
8485 symbol_new ("L0\001", now_seg
,
8486 (valueT
) frag_now_fix (), frag_now
);
8487 offset_expr
.X_add_number
= 0;
8489 /* Put the floating point number into the section. */
8490 p
= frag_more ((int) length
);
8491 memcpy (p
, temp
, length
);
8493 /* Switch back to the original section. */
8494 subseg_set (seg
, subseg
);
8499 case 'i': /* 16 bit unsigned immediate */
8500 case 'j': /* 16 bit signed immediate */
8501 *imm_reloc
= BFD_RELOC_LO16
;
8502 c
= my_getSmallExpression (&imm_expr
, s
);
8507 if (imm_expr
.X_op
== O_constant
)
8508 imm_expr
.X_add_number
=
8509 (imm_expr
.X_add_number
>> 16) & 0xffff;
8511 else if (c
== S_EX_HIGHEST
)
8512 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8513 else if (c
== S_EX_HIGHER
)
8514 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
8515 else if (c
== S_EX_GP_REL
)
8517 /* This occurs in NewABI only. */
8518 c
= my_getSmallExpression (&imm_expr
, s
);
8520 as_bad (_("bad composition of relocations"));
8523 c
= my_getSmallExpression (&imm_expr
, s
);
8525 as_bad (_("bad composition of relocations"));
8528 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8529 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8530 imm_reloc
[2] = BFD_RELOC_LO16
;
8535 else if (c
== S_EX_HI
)
8537 *imm_reloc
= BFD_RELOC_HI16_S
;
8538 imm_unmatched_hi
= true;
8541 *imm_reloc
= BFD_RELOC_HI16
;
8543 else if (imm_expr
.X_op
== O_constant
)
8544 imm_expr
.X_add_number
&= 0xffff;
8548 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8549 || ((imm_expr
.X_add_number
< 0
8550 || imm_expr
.X_add_number
>= 0x10000)
8551 && imm_expr
.X_op
== O_constant
))
8553 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8554 !strcmp (insn
->name
, insn
[1].name
))
8556 if (imm_expr
.X_op
== O_constant
8557 || imm_expr
.X_op
== O_big
)
8558 as_bad (_("16 bit expression not in range 0..65535"));
8566 /* The upper bound should be 0x8000, but
8567 unfortunately the MIPS assembler accepts numbers
8568 from 0x8000 to 0xffff and sign extends them, and
8569 we want to be compatible. We only permit this
8570 extended range for an instruction which does not
8571 provide any further alternates, since those
8572 alternates may handle other cases. People should
8573 use the numbers they mean, rather than relying on
8574 a mysterious sign extension. */
8575 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8576 strcmp (insn
->name
, insn
[1].name
) == 0);
8581 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8582 || ((imm_expr
.X_add_number
< -0x8000
8583 || imm_expr
.X_add_number
>= max
)
8584 && imm_expr
.X_op
== O_constant
)
8586 && imm_expr
.X_add_number
< 0
8588 && imm_expr
.X_unsigned
8589 && sizeof (imm_expr
.X_add_number
) <= 4))
8593 if (imm_expr
.X_op
== O_constant
8594 || imm_expr
.X_op
== O_big
)
8595 as_bad (_("16 bit expression not in range -32768..32767"));
8601 case 'o': /* 16 bit offset */
8602 c
= my_getSmallExpression (&offset_expr
, s
);
8604 /* If this value won't fit into a 16 bit offset, then go
8605 find a macro that will generate the 32 bit offset
8608 && (offset_expr
.X_op
!= O_constant
8609 || offset_expr
.X_add_number
>= 0x8000
8610 || offset_expr
.X_add_number
< -0x8000))
8615 if (offset_expr
.X_op
!= O_constant
)
8617 offset_expr
.X_add_number
=
8618 (offset_expr
.X_add_number
>> 16) & 0xffff;
8620 *offset_reloc
= BFD_RELOC_LO16
;
8624 case 'p': /* pc relative offset */
8625 if (mips_pic
== EMBEDDED_PIC
)
8626 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8628 *offset_reloc
= BFD_RELOC_16_PCREL
;
8629 my_getExpression (&offset_expr
, s
);
8633 case 'u': /* upper 16 bits */
8634 c
= my_getSmallExpression (&imm_expr
, s
);
8635 *imm_reloc
= BFD_RELOC_LO16
;
8640 if (imm_expr
.X_op
== O_constant
)
8641 imm_expr
.X_add_number
=
8642 (imm_expr
.X_add_number
>> 16) & 0xffff;
8643 else if (c
== S_EX_HI
)
8645 *imm_reloc
= BFD_RELOC_HI16_S
;
8646 imm_unmatched_hi
= true;
8649 else if (c
== S_EX_HIGHEST
)
8650 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8651 else if (c
== S_EX_GP_REL
)
8653 /* This occurs in NewABI only. */
8654 c
= my_getSmallExpression (&imm_expr
, s
);
8656 as_bad (_("bad composition of relocations"));
8659 c
= my_getSmallExpression (&imm_expr
, s
);
8661 as_bad (_("bad composition of relocations"));
8664 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8665 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8666 imm_reloc
[2] = BFD_RELOC_HI16_S
;
8672 *imm_reloc
= BFD_RELOC_HI16
;
8674 else if (imm_expr
.X_op
== O_constant
)
8675 imm_expr
.X_add_number
&= 0xffff;
8677 if (imm_expr
.X_op
== O_constant
8678 && (imm_expr
.X_add_number
< 0
8679 || imm_expr
.X_add_number
>= 0x10000))
8680 as_bad (_("lui expression not in range 0..65535"));
8684 case 'a': /* 26 bit address */
8685 my_getExpression (&offset_expr
, s
);
8687 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8690 case 'N': /* 3 bit branch condition code */
8691 case 'M': /* 3 bit compare condition code */
8692 if (strncmp (s
, "$fcc", 4) != 0)
8702 while (ISDIGIT (*s
));
8704 as_bad (_("invalid condition code register $fcc%d"), regno
);
8706 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8708 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8712 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8723 while (ISDIGIT (*s
));
8726 c
= 8; /* Invalid sel value. */
8729 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8730 ip
->insn_opcode
|= c
;
8734 as_bad (_("bad char = '%c'\n"), *args
);
8739 /* Args don't match. */
8740 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8741 !strcmp (insn
->name
, insn
[1].name
))
8745 insn_error
= _("illegal operands");
8750 insn_error
= _("illegal operands");
8755 /* This routine assembles an instruction into its binary format when
8756 assembling for the mips16. As a side effect, it sets one of the
8757 global variables imm_reloc or offset_reloc to the type of
8758 relocation to do if one of the operands is an address expression.
8759 It also sets mips16_small and mips16_ext if the user explicitly
8760 requested a small or extended instruction. */
8765 struct mips_cl_insn
*ip
;
8769 struct mips_opcode
*insn
;
8772 unsigned int lastregno
= 0;
8777 mips16_small
= false;
8780 for (s
= str
; ISLOWER (*s
); ++s
)
8792 if (s
[1] == 't' && s
[2] == ' ')
8795 mips16_small
= true;
8799 else if (s
[1] == 'e' && s
[2] == ' ')
8808 insn_error
= _("unknown opcode");
8812 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8813 mips16_small
= true;
8815 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8817 insn_error
= _("unrecognized opcode");
8824 assert (strcmp (insn
->name
, str
) == 0);
8827 ip
->insn_opcode
= insn
->match
;
8828 ip
->use_extend
= false;
8829 imm_expr
.X_op
= O_absent
;
8830 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8831 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8832 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8833 offset_expr
.X_op
= O_absent
;
8834 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8835 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8836 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8837 for (args
= insn
->args
; 1; ++args
)
8844 /* In this switch statement we call break if we did not find
8845 a match, continue if we did find a match, or return if we
8854 /* Stuff the immediate value in now, if we can. */
8855 if (imm_expr
.X_op
== O_constant
8856 && *imm_reloc
> BFD_RELOC_UNUSED
8857 && insn
->pinfo
!= INSN_MACRO
)
8859 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
8860 imm_expr
.X_add_number
, true, mips16_small
,
8861 mips16_ext
, &ip
->insn_opcode
,
8862 &ip
->use_extend
, &ip
->extend
);
8863 imm_expr
.X_op
= O_absent
;
8864 *imm_reloc
= BFD_RELOC_UNUSED
;
8878 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8881 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8897 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8899 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8926 while (ISDIGIT (*s
));
8929 as_bad (_("invalid register number (%d)"), regno
);
8935 if (s
[1] == 'f' && s
[2] == 'p')
8940 else if (s
[1] == 's' && s
[2] == 'p')
8945 else if (s
[1] == 'g' && s
[2] == 'p')
8950 else if (s
[1] == 'a' && s
[2] == 't')
8955 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8960 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8973 if (c
== 'v' || c
== 'w')
8975 regno
= mips16_to_32_reg_map
[lastregno
];
8989 regno
= mips32_to_16_reg_map
[regno
];
8994 regno
= ILLEGAL_REG
;
8999 regno
= ILLEGAL_REG
;
9004 regno
= ILLEGAL_REG
;
9009 if (regno
== AT
&& ! mips_opts
.noat
)
9010 as_warn (_("used $at without \".set noat\""));
9017 if (regno
== ILLEGAL_REG
)
9024 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9028 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9031 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9034 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9040 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9043 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9044 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9054 if (strncmp (s
, "$pc", 3) == 0)
9078 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9080 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9081 and generate the appropriate reloc. If the text
9082 inside %gprel is not a symbol name with an
9083 optional offset, then we generate a normal reloc
9084 and will probably fail later. */
9085 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9086 if (imm_expr
.X_op
== O_symbol
)
9089 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9091 ip
->use_extend
= true;
9098 /* Just pick up a normal expression. */
9099 my_getExpression (&imm_expr
, s
);
9102 if (imm_expr
.X_op
== O_register
)
9104 /* What we thought was an expression turned out to
9107 if (s
[0] == '(' && args
[1] == '(')
9109 /* It looks like the expression was omitted
9110 before a register indirection, which means
9111 that the expression is implicitly zero. We
9112 still set up imm_expr, so that we handle
9113 explicit extensions correctly. */
9114 imm_expr
.X_op
= O_constant
;
9115 imm_expr
.X_add_number
= 0;
9116 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9123 /* We need to relax this instruction. */
9124 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9133 /* We use offset_reloc rather than imm_reloc for the PC
9134 relative operands. This lets macros with both
9135 immediate and address operands work correctly. */
9136 my_getExpression (&offset_expr
, s
);
9138 if (offset_expr
.X_op
== O_register
)
9141 /* We need to relax this instruction. */
9142 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9146 case '6': /* break code */
9147 my_getExpression (&imm_expr
, s
);
9148 check_absolute_expr (ip
, &imm_expr
);
9149 if ((unsigned long) imm_expr
.X_add_number
> 63)
9151 as_warn (_("Invalid value for `%s' (%lu)"),
9153 (unsigned long) imm_expr
.X_add_number
);
9154 imm_expr
.X_add_number
&= 0x3f;
9156 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9157 imm_expr
.X_op
= O_absent
;
9161 case 'a': /* 26 bit address */
9162 my_getExpression (&offset_expr
, s
);
9164 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9165 ip
->insn_opcode
<<= 16;
9168 case 'l': /* register list for entry macro */
9169 case 'L': /* register list for exit macro */
9179 int freg
, reg1
, reg2
;
9181 while (*s
== ' ' || *s
== ',')
9185 as_bad (_("can't parse register list"));
9197 while (ISDIGIT (*s
))
9219 as_bad (_("invalid register list"));
9224 while (ISDIGIT (*s
))
9231 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9236 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9241 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9242 mask
|= (reg2
- 3) << 3;
9243 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9244 mask
|= (reg2
- 15) << 1;
9245 else if (reg1
== RA
&& reg2
== RA
)
9249 as_bad (_("invalid register list"));
9253 /* The mask is filled in in the opcode table for the
9254 benefit of the disassembler. We remove it before
9255 applying the actual mask. */
9256 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9257 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9261 case 'e': /* extend code */
9262 my_getExpression (&imm_expr
, s
);
9263 check_absolute_expr (ip
, &imm_expr
);
9264 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9266 as_warn (_("Invalid value for `%s' (%lu)"),
9268 (unsigned long) imm_expr
.X_add_number
);
9269 imm_expr
.X_add_number
&= 0x7ff;
9271 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9272 imm_expr
.X_op
= O_absent
;
9282 /* Args don't match. */
9283 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9284 strcmp (insn
->name
, insn
[1].name
) == 0)
9291 insn_error
= _("illegal operands");
9297 /* This structure holds information we know about a mips16 immediate
9300 struct mips16_immed_operand
9302 /* The type code used in the argument string in the opcode table. */
9304 /* The number of bits in the short form of the opcode. */
9306 /* The number of bits in the extended form of the opcode. */
9308 /* The amount by which the short form is shifted when it is used;
9309 for example, the sw instruction has a shift count of 2. */
9311 /* The amount by which the short form is shifted when it is stored
9312 into the instruction code. */
9314 /* Non-zero if the short form is unsigned. */
9316 /* Non-zero if the extended form is unsigned. */
9318 /* Non-zero if the value is PC relative. */
9322 /* The mips16 immediate operand types. */
9324 static const struct mips16_immed_operand mips16_immed_operands
[] =
9326 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9327 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9328 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9329 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9330 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9331 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9332 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9333 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9334 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9335 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9336 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9337 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9338 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9339 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9340 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9341 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9342 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9343 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9344 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9345 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9346 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9349 #define MIPS16_NUM_IMMED \
9350 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9352 /* Handle a mips16 instruction with an immediate value. This or's the
9353 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9354 whether an extended value is needed; if one is needed, it sets
9355 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9356 If SMALL is true, an unextended opcode was explicitly requested.
9357 If EXT is true, an extended opcode was explicitly requested. If
9358 WARN is true, warn if EXT does not match reality. */
9361 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9370 unsigned long *insn
;
9371 boolean
*use_extend
;
9372 unsigned short *extend
;
9374 register const struct mips16_immed_operand
*op
;
9375 int mintiny
, maxtiny
;
9378 op
= mips16_immed_operands
;
9379 while (op
->type
!= type
)
9382 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9387 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9390 maxtiny
= 1 << op
->nbits
;
9395 maxtiny
= (1 << op
->nbits
) - 1;
9400 mintiny
= - (1 << (op
->nbits
- 1));
9401 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9404 /* Branch offsets have an implicit 0 in the lowest bit. */
9405 if (type
== 'p' || type
== 'q')
9408 if ((val
& ((1 << op
->shift
) - 1)) != 0
9409 || val
< (mintiny
<< op
->shift
)
9410 || val
> (maxtiny
<< op
->shift
))
9415 if (warn
&& ext
&& ! needext
)
9416 as_warn_where (file
, line
,
9417 _("extended operand requested but not required"));
9418 if (small
&& needext
)
9419 as_bad_where (file
, line
, _("invalid unextended operand value"));
9421 if (small
|| (! ext
&& ! needext
))
9425 *use_extend
= false;
9426 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9427 insnval
<<= op
->op_shift
;
9432 long minext
, maxext
;
9438 maxext
= (1 << op
->extbits
) - 1;
9442 minext
= - (1 << (op
->extbits
- 1));
9443 maxext
= (1 << (op
->extbits
- 1)) - 1;
9445 if (val
< minext
|| val
> maxext
)
9446 as_bad_where (file
, line
,
9447 _("operand value out of range for instruction"));
9450 if (op
->extbits
== 16)
9452 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9455 else if (op
->extbits
== 15)
9457 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9462 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9466 *extend
= (unsigned short) extval
;
9471 static struct percent_op_match
9474 const enum small_ex_type type
;
9479 {"%call_hi", S_EX_CALL_HI
},
9480 {"%call_lo", S_EX_CALL_LO
},
9481 {"%call16", S_EX_CALL16
},
9482 {"%got_disp", S_EX_GOT_DISP
},
9483 {"%got_page", S_EX_GOT_PAGE
},
9484 {"%got_ofst", S_EX_GOT_OFST
},
9485 {"%got_hi", S_EX_GOT_HI
},
9486 {"%got_lo", S_EX_GOT_LO
},
9488 {"%gp_rel", S_EX_GP_REL
},
9489 {"%half", S_EX_HALF
},
9490 {"%highest", S_EX_HIGHEST
},
9491 {"%higher", S_EX_HIGHER
},
9497 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9498 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9499 can be nested, this is handled by blanking the innermost, parsing the
9500 rest by subsequent calls. */
9503 my_getSmallParser (str
, len
, nestlevel
)
9509 *str
+= strspn (*str
, " \t");
9510 /* Check for expression in parentheses. */
9513 char *b
= *str
+ 1 + strspn (*str
+ 1, " \t");
9516 /* Check for base register. */
9520 && (e
= b
+ strcspn (b
, ") \t"))
9521 && e
- b
> 1 && e
- b
< 4)
9524 && ((b
[1] == 'f' && b
[2] == 'p')
9525 || (b
[1] == 's' && b
[2] == 'p')
9526 || (b
[1] == 'g' && b
[2] == 'p')
9527 || (b
[1] == 'a' && b
[2] == 't')
9529 && ISDIGIT (b
[2]))))
9530 || (ISDIGIT (b
[1])))
9532 *len
= strcspn (*str
, ")") + 1;
9533 return S_EX_REGISTER
;
9537 /* Check for percent_op (in parentheses). */
9538 else if (b
[0] == '%')
9541 return my_getPercentOp (str
, len
, nestlevel
);
9544 /* Some other expression in the parentheses, which can contain
9545 parentheses itself. Attempt to find the matching one. */
9551 for (s
= *str
+ 1; *s
&& pcnt
; s
++, (*len
)++)
9560 /* Check for percent_op (outside of parentheses). */
9561 else if (*str
[0] == '%')
9562 return my_getPercentOp (str
, len
, nestlevel
);
9564 /* Any other expression. */
9569 my_getPercentOp (str
, len
, nestlevel
)
9574 char *tmp
= *str
+ 1;
9577 while (ISALPHA (*tmp
) || *tmp
== '_')
9579 *tmp
= TOLOWER (*tmp
);
9582 while (i
< (sizeof (percent_op
) / sizeof (struct percent_op_match
)))
9584 if (strncmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)))
9588 int type
= percent_op
[i
].type
;
9590 /* Only %hi and %lo are allowed for OldABI. */
9591 if (! HAVE_NEWABI
&& type
!= S_EX_HI
&& type
!= S_EX_LO
)
9594 *len
= strlen (percent_op
[i
].str
);
9603 my_getSmallExpression (ep
, str
)
9607 static char *oldstr
= NULL
;
9613 /* Don't update oldstr if the last call had nested percent_op's. We need
9614 it to parse the outer ones later. */
9621 c
= my_getSmallParser (&str
, &len
, &nestlevel
);
9622 if (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
)
9625 while (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
);
9629 /* A percent_op was encountered. Don't try to get an expression if
9630 it is already blanked out. */
9631 if (*(str
+ strspn (str
+ 1, " )")) != ')')
9635 /* Let my_getExpression() stop at the closing parenthesis. */
9636 save
= *(str
+ len
);
9637 *(str
+ len
) = '\0';
9638 my_getExpression (ep
, str
);
9639 *(str
+ len
) = save
;
9643 /* Blank out including the % sign and the proper matching
9646 char *s
= strrchr (oldstr
, '%');
9649 for (end
= strchr (s
, '(') + 1; *end
&& pcnt
; end
++)
9653 else if (*end
== ')')
9657 memset (s
, ' ', end
- s
);
9661 expr_end
= str
+ len
;
9665 else if (c
== S_EX_NONE
)
9667 my_getExpression (ep
, str
);
9669 else if (c
== S_EX_REGISTER
)
9671 ep
->X_op
= O_constant
;
9673 ep
->X_add_symbol
= NULL
;
9674 ep
->X_op_symbol
= NULL
;
9675 ep
->X_add_number
= 0;
9679 as_fatal (_("internal error"));
9683 /* All percent_op's have been handled. */
9690 my_getExpression (ep
, str
)
9697 save_in
= input_line_pointer
;
9698 input_line_pointer
= str
;
9700 expr_end
= input_line_pointer
;
9701 input_line_pointer
= save_in
;
9703 /* If we are in mips16 mode, and this is an expression based on `.',
9704 then we bump the value of the symbol by 1 since that is how other
9705 text symbols are handled. We don't bother to handle complex
9706 expressions, just `.' plus or minus a constant. */
9707 if (mips_opts
.mips16
9708 && ep
->X_op
== O_symbol
9709 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9710 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9711 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9712 && symbol_constant_p (ep
->X_add_symbol
)
9713 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9714 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9717 /* Turn a string in input_line_pointer into a floating point constant
9718 of type TYPE, and store the appropriate bytes in *LITP. The number
9719 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9720 returned, or NULL on OK. */
9723 md_atof (type
, litP
, sizeP
)
9729 LITTLENUM_TYPE words
[4];
9745 return _("bad call to md_atof");
9748 t
= atof_ieee (input_line_pointer
, type
, words
);
9750 input_line_pointer
= t
;
9754 if (! target_big_endian
)
9756 for (i
= prec
- 1; i
>= 0; i
--)
9758 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9764 for (i
= 0; i
< prec
; i
++)
9766 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9775 md_number_to_chars (buf
, val
, n
)
9780 if (target_big_endian
)
9781 number_to_chars_bigendian (buf
, val
, n
);
9783 number_to_chars_littleendian (buf
, val
, n
);
9787 static int support_64bit_objects(void)
9789 const char **list
, **l
;
9791 list
= bfd_target_list ();
9792 for (l
= list
; *l
!= NULL
; l
++)
9794 /* This is traditional mips */
9795 if (strcmp (*l
, "elf64-tradbigmips") == 0
9796 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9798 if (strcmp (*l
, "elf64-bigmips") == 0
9799 || strcmp (*l
, "elf64-littlemips") == 0)
9803 return (*l
!= NULL
);
9805 #endif /* OBJ_ELF */
9807 CONST
char *md_shortopts
= "nO::g::G:";
9809 struct option md_longopts
[] =
9811 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9812 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9813 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9814 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9815 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9816 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9817 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9818 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9819 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9820 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9821 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9822 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9823 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9824 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9825 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9826 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9827 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9828 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9829 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9830 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9831 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9832 {"break", no_argument
, NULL
, OPTION_BREAK
},
9833 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9834 #define OPTION_EB (OPTION_MD_BASE + 11)
9835 {"EB", no_argument
, NULL
, OPTION_EB
},
9836 #define OPTION_EL (OPTION_MD_BASE + 12)
9837 {"EL", no_argument
, NULL
, OPTION_EL
},
9838 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9839 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9840 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9841 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9842 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9843 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9844 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 16)
9845 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
9846 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9847 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9848 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9849 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9850 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9851 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
9852 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9853 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
9854 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9855 {"march", required_argument
, NULL
, OPTION_MARCH
},
9856 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9857 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9858 #define OPTION_MCPU (OPTION_MD_BASE + 23)
9859 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9860 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9861 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9862 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9863 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9864 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9865 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9866 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9867 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9868 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9869 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9870 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9871 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9872 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9873 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9874 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9875 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9876 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9877 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
9878 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
9879 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
9880 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
9881 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
9883 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
9884 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9885 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9886 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9887 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9888 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9889 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9890 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9891 #define OPTION_MABI (OPTION_ELF_BASE + 3)
9892 {"mabi", required_argument
, NULL
, OPTION_MABI
},
9893 #define OPTION_32 (OPTION_ELF_BASE + 4)
9894 {"32", no_argument
, NULL
, OPTION_32
},
9895 #define OPTION_N32 (OPTION_ELF_BASE + 5)
9896 {"n32", no_argument
, NULL
, OPTION_N32
},
9897 #define OPTION_64 (OPTION_ELF_BASE + 6)
9898 {"64", no_argument
, NULL
, OPTION_64
},
9899 #endif /* OBJ_ELF */
9900 {NULL
, no_argument
, NULL
, 0}
9902 size_t md_longopts_size
= sizeof (md_longopts
);
9905 md_parse_option (c
, arg
)
9911 case OPTION_CONSTRUCT_FLOATS
:
9912 mips_disable_float_construction
= 0;
9915 case OPTION_NO_CONSTRUCT_FLOATS
:
9916 mips_disable_float_construction
= 1;
9928 target_big_endian
= 1;
9932 target_big_endian
= 0;
9940 if (arg
&& arg
[1] == '0')
9950 mips_debug
= atoi (arg
);
9951 /* When the MIPS assembler sees -g or -g2, it does not do
9952 optimizations which limit full symbolic debugging. We take
9953 that to be equivalent to -O0. */
9954 if (mips_debug
== 2)
9959 mips_opts
.isa
= ISA_MIPS1
;
9963 mips_opts
.isa
= ISA_MIPS2
;
9967 mips_opts
.isa
= ISA_MIPS3
;
9971 mips_opts
.isa
= ISA_MIPS4
;
9975 mips_opts
.isa
= ISA_MIPS5
;
9979 mips_opts
.isa
= ISA_MIPS32
;
9983 mips_opts
.isa
= ISA_MIPS64
;
9990 int cpu
= CPU_UNKNOWN
;
9992 /* Identify the processor type. */
9993 if (strcasecmp (arg
, "default") != 0)
9995 const struct mips_cpu_info
*ci
;
9997 ci
= mips_cpu_info_from_name (arg
);
9998 if (ci
== NULL
|| ci
->is_isa
)
10003 as_fatal (_("invalid architecture -mtune=%s"), arg
);
10006 as_fatal (_("invalid architecture -march=%s"), arg
);
10009 as_fatal (_("invalid architecture -mcpu=%s"), arg
);
10020 if (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= cpu
)
10021 as_warn (_("A different -mtune= was already specified, is now "
10022 "-mtune=%s"), arg
);
10026 if (mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= cpu
)
10027 as_warn (_("A different -march= was already specified, is now "
10028 "-march=%s"), arg
);
10032 if (mips_cpu
!= CPU_UNKNOWN
&& mips_cpu
!= cpu
)
10033 as_warn (_("A different -mcpu= was already specified, is now "
10041 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4650
)
10042 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4650
))
10043 as_warn (_("A different -march= or -mtune= was already specified, "
10045 mips_arch
= CPU_R4650
;
10046 mips_tune
= CPU_R4650
;
10049 case OPTION_NO_M4650
:
10053 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4010
)
10054 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4010
))
10055 as_warn (_("A different -march= or -mtune= was already specified, "
10057 mips_arch
= CPU_R4010
;
10058 mips_tune
= CPU_R4010
;
10061 case OPTION_NO_M4010
:
10065 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_VR4100
)
10066 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_VR4100
))
10067 as_warn (_("A different -march= or -mtune= was already specified, "
10069 mips_arch
= CPU_VR4100
;
10070 mips_tune
= CPU_VR4100
;
10073 case OPTION_NO_M4100
:
10077 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R3900
)
10078 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R3900
))
10079 as_warn (_("A different -march= or -mtune= was already specified, "
10081 mips_arch
= CPU_R3900
;
10082 mips_tune
= CPU_R3900
;
10085 case OPTION_NO_M3900
:
10088 case OPTION_MIPS16
:
10089 mips_opts
.mips16
= 1;
10090 mips_no_prev_insn (false);
10093 case OPTION_NO_MIPS16
:
10094 mips_opts
.mips16
= 0;
10095 mips_no_prev_insn (false);
10098 case OPTION_MIPS3D
:
10099 mips_opts
.ase_mips3d
= 1;
10102 case OPTION_NO_MIPS3D
:
10103 mips_opts
.ase_mips3d
= 0;
10106 case OPTION_MEMBEDDED_PIC
:
10107 mips_pic
= EMBEDDED_PIC
;
10108 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10110 as_bad (_("-G may not be used with embedded PIC code"));
10113 g_switch_value
= 0x7fffffff;
10117 /* When generating ELF code, we permit -KPIC and -call_shared to
10118 select SVR4_PIC, and -non_shared to select no PIC. This is
10119 intended to be compatible with Irix 5. */
10120 case OPTION_CALL_SHARED
:
10121 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10123 as_bad (_("-call_shared is supported only for ELF format"));
10126 mips_pic
= SVR4_PIC
;
10127 if (g_switch_seen
&& g_switch_value
!= 0)
10129 as_bad (_("-G may not be used with SVR4 PIC code"));
10132 g_switch_value
= 0;
10135 case OPTION_NON_SHARED
:
10136 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10138 as_bad (_("-non_shared is supported only for ELF format"));
10144 /* The -xgot option tells the assembler to use 32 offsets when
10145 accessing the got in SVR4_PIC mode. It is for Irix
10150 #endif /* OBJ_ELF */
10153 if (! USE_GLOBAL_POINTER_OPT
)
10155 as_bad (_("-G is not supported for this configuration"));
10158 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10160 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10164 g_switch_value
= atoi (arg
);
10169 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10172 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10174 as_bad (_("-32 is supported for ELF format only"));
10177 mips_opts
.abi
= O32_ABI
;
10181 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10183 as_bad (_("-n32 is supported for ELF format only"));
10186 mips_opts
.abi
= N32_ABI
;
10190 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10192 as_bad (_("-64 is supported for ELF format only"));
10195 mips_opts
.abi
= N64_ABI
;
10196 if (! support_64bit_objects())
10197 as_fatal (_("No compiled in support for 64 bit object file format"));
10199 #endif /* OBJ_ELF */
10202 file_mips_gp32
= 1;
10203 if (mips_opts
.abi
!= O32_ABI
)
10204 mips_opts
.abi
= NO_ABI
;
10208 file_mips_gp32
= 0;
10209 if (mips_opts
.abi
== O32_ABI
)
10210 mips_opts
.abi
= NO_ABI
;
10214 file_mips_fp32
= 1;
10215 if (mips_opts
.abi
!= O32_ABI
)
10216 mips_opts
.abi
= NO_ABI
;
10221 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10223 as_bad (_("-mabi is supported for ELF format only"));
10226 if (strcmp (arg
, "32") == 0)
10227 mips_opts
.abi
= O32_ABI
;
10228 else if (strcmp (arg
, "o64") == 0)
10229 mips_opts
.abi
= O64_ABI
;
10230 else if (strcmp (arg
, "n32") == 0)
10231 mips_opts
.abi
= N32_ABI
;
10232 else if (strcmp (arg
, "64") == 0)
10234 mips_opts
.abi
= N64_ABI
;
10235 if (! support_64bit_objects())
10236 as_fatal (_("No compiled in support for 64 bit object file "
10239 else if (strcmp (arg
, "eabi") == 0)
10240 mips_opts
.abi
= EABI_ABI
;
10243 as_fatal (_("invalid abi -mabi=%s"), arg
);
10247 #endif /* OBJ_ELF */
10249 case OPTION_M7000_HILO_FIX
:
10250 mips_7000_hilo_fix
= true;
10253 case OPTION_NO_M7000_HILO_FIX
:
10254 mips_7000_hilo_fix
= false;
10265 show (stream
, string
, col_p
, first_p
)
10273 fprintf (stream
, "%24s", "");
10278 fprintf (stream
, ", ");
10282 if (*col_p
+ strlen (string
) > 72)
10284 fprintf (stream
, "\n%24s", "");
10288 fprintf (stream
, "%s", string
);
10289 *col_p
+= strlen (string
);
10295 md_show_usage (stream
)
10300 fprintf (stream
, _("\
10302 -membedded-pic generate embedded position independent code\n\
10303 -EB generate big endian output\n\
10304 -EL generate little endian output\n\
10305 -g, -g2 do not remove unneeded NOPs or swap branches\n\
10306 -G NUM allow referencing objects up to NUM bytes\n\
10307 implicitly with the gp register [default 8]\n"));
10308 fprintf (stream
, _("\
10309 -mips1 generate MIPS ISA I instructions\n\
10310 -mips2 generate MIPS ISA II instructions\n\
10311 -mips3 generate MIPS ISA III instructions\n\
10312 -mips4 generate MIPS ISA IV instructions\n\
10313 -mips5 generate MIPS ISA V instructions\n\
10314 -mips32 generate MIPS32 ISA instructions\n\
10315 -mips64 generate MIPS64 ISA instructions\n\
10316 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
10320 show (stream
, "2000", &column
, &first
);
10321 show (stream
, "3000", &column
, &first
);
10322 show (stream
, "3900", &column
, &first
);
10323 show (stream
, "4000", &column
, &first
);
10324 show (stream
, "4010", &column
, &first
);
10325 show (stream
, "4100", &column
, &first
);
10326 show (stream
, "4111", &column
, &first
);
10327 show (stream
, "4300", &column
, &first
);
10328 show (stream
, "4400", &column
, &first
);
10329 show (stream
, "4600", &column
, &first
);
10330 show (stream
, "4650", &column
, &first
);
10331 show (stream
, "5000", &column
, &first
);
10332 show (stream
, "5200", &column
, &first
);
10333 show (stream
, "5230", &column
, &first
);
10334 show (stream
, "5231", &column
, &first
);
10335 show (stream
, "5261", &column
, &first
);
10336 show (stream
, "5721", &column
, &first
);
10337 show (stream
, "6000", &column
, &first
);
10338 show (stream
, "8000", &column
, &first
);
10339 show (stream
, "10000", &column
, &first
);
10340 show (stream
, "12000", &column
, &first
);
10341 show (stream
, "sb1", &column
, &first
);
10342 fputc ('\n', stream
);
10344 fprintf (stream
, _("\
10345 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
10346 -no-mCPU don't generate code specific to CPU.\n\
10347 For -mCPU and -no-mCPU, CPU must be one of:\n"));
10351 show (stream
, "3900", &column
, &first
);
10352 show (stream
, "4010", &column
, &first
);
10353 show (stream
, "4100", &column
, &first
);
10354 show (stream
, "4650", &column
, &first
);
10355 fputc ('\n', stream
);
10357 fprintf (stream
, _("\
10358 -mips16 generate mips16 instructions\n\
10359 -no-mips16 do not generate mips16 instructions\n"));
10360 fprintf (stream
, _("\
10361 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
10362 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
10363 -O0 remove unneeded NOPs, do not swap branches\n\
10364 -O remove unneeded NOPs and swap branches\n\
10365 -n warn about NOPs generated from macros\n\
10366 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
10367 --trap, --no-break trap exception on div by 0 and mult overflow\n\
10368 --break, --no-trap break exception on div by 0 and mult overflow\n"));
10370 fprintf (stream
, _("\
10371 -KPIC, -call_shared generate SVR4 position independent code\n\
10372 -non_shared do not generate position independent code\n\
10373 -xgot assume a 32 bit GOT\n\
10374 -mabi=ABI create ABI conformant object file for:\n"));
10378 show (stream
, "32", &column
, &first
);
10379 show (stream
, "o64", &column
, &first
);
10380 show (stream
, "n32", &column
, &first
);
10381 show (stream
, "64", &column
, &first
);
10382 show (stream
, "eabi", &column
, &first
);
10384 fputc ('\n', stream
);
10386 fprintf (stream
, _("\
10387 -32 create o32 ABI object file (default)\n\
10388 -n32 create n32 ABI object file\n\
10389 -64 create 64 ABI object file\n"));
10394 mips_init_after_args ()
10396 /* initialize opcodes */
10397 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10398 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10402 md_pcrel_from (fixP
)
10405 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10406 && fixP
->fx_addsy
!= (symbolS
*) NULL
10407 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10409 /* This makes a branch to an undefined symbol be a branch to the
10410 current location. */
10411 if (mips_pic
== EMBEDDED_PIC
)
10417 /* Return the address of the delay slot. */
10418 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10421 /* This is called before the symbol table is processed. In order to
10422 work with gcc when using mips-tfile, we must keep all local labels.
10423 However, in other cases, we want to discard them. If we were
10424 called with -g, but we didn't see any debugging information, it may
10425 mean that gcc is smuggling debugging information through to
10426 mips-tfile, in which case we must generate all local labels. */
10429 mips_frob_file_before_adjust ()
10431 #ifndef NO_ECOFF_DEBUGGING
10432 if (ECOFF_DEBUGGING
10434 && ! ecoff_debugging_seen
)
10435 flag_keep_locals
= 1;
10439 /* Sort any unmatched HI16_S relocs so that they immediately precede
10440 the corresponding LO reloc. This is called before md_apply_fix3 and
10441 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10442 explicit use of the %hi modifier. */
10447 struct mips_hi_fixup
*l
;
10449 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10451 segment_info_type
*seginfo
;
10454 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10456 /* Check quickly whether the next fixup happens to be a matching
10458 if (l
->fixp
->fx_next
!= NULL
10459 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10460 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10461 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10464 /* Look through the fixups for this segment for a matching %lo.
10465 When we find one, move the %hi just in front of it. We do
10466 this in two passes. In the first pass, we try to find a
10467 unique %lo. In the second pass, we permit multiple %hi
10468 relocs for a single %lo (this is a GNU extension). */
10469 seginfo
= seg_info (l
->seg
);
10470 for (pass
= 0; pass
< 2; pass
++)
10475 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10477 /* Check whether this is a %lo fixup which matches l->fixp. */
10478 if (f
->fx_r_type
== BFD_RELOC_LO16
10479 && f
->fx_addsy
== l
->fixp
->fx_addsy
10480 && f
->fx_offset
== l
->fixp
->fx_offset
10483 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10484 || prev
->fx_addsy
!= f
->fx_addsy
10485 || prev
->fx_offset
!= f
->fx_offset
))
10489 /* Move l->fixp before f. */
10490 for (pf
= &seginfo
->fix_root
;
10492 pf
= &(*pf
)->fx_next
)
10493 assert (*pf
!= NULL
);
10495 *pf
= l
->fixp
->fx_next
;
10497 l
->fixp
->fx_next
= f
;
10499 seginfo
->fix_root
= l
->fixp
;
10501 prev
->fx_next
= l
->fixp
;
10512 #if 0 /* GCC code motion plus incomplete dead code elimination
10513 can leave a %hi without a %lo. */
10515 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10516 _("Unmatched %%hi reloc"));
10522 /* When generating embedded PIC code we need to use a special
10523 relocation to represent the difference of two symbols in the .text
10524 section (switch tables use a difference of this sort). See
10525 include/coff/mips.h for details. This macro checks whether this
10526 fixup requires the special reloc. */
10527 #define SWITCH_TABLE(fixp) \
10528 ((fixp)->fx_r_type == BFD_RELOC_32 \
10529 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10530 && (fixp)->fx_addsy != NULL \
10531 && (fixp)->fx_subsy != NULL \
10532 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10533 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10535 /* When generating embedded PIC code we must keep all PC relative
10536 relocations, in case the linker has to relax a call. We also need
10537 to keep relocations for switch table entries.
10539 We may have combined relocations without symbols in the N32/N64 ABI.
10540 We have to prevent gas from dropping them. */
10543 mips_force_relocation (fixp
)
10546 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10547 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10551 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10552 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10553 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10554 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10557 return (mips_pic
== EMBEDDED_PIC
10559 || SWITCH_TABLE (fixp
)
10560 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10561 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10566 mips_need_elf_addend_fixup (fixP
)
10569 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
10571 if (mips_pic
== EMBEDDED_PIC
10572 && S_IS_WEAK (fixP
->fx_addsy
))
10574 if (mips_pic
!= EMBEDDED_PIC
10575 && (S_IS_WEAK (fixP
->fx_addsy
)
10576 || S_IS_EXTERN (fixP
->fx_addsy
))
10577 && !S_IS_COMMON (fixP
->fx_addsy
))
10579 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
10580 && (((bfd_get_section_flags (stdoutput
,
10581 S_GET_SEGMENT (fixP
->fx_addsy
))
10582 & SEC_LINK_ONCE
) != 0)
10583 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
10585 sizeof (".gnu.linkonce") - 1)))
10591 /* Apply a fixup to the object file. */
10594 md_apply_fix3 (fixP
, valP
, seg
)
10597 segT seg ATTRIBUTE_UNUSED
;
10603 assert (fixP
->fx_size
== 4
10604 || fixP
->fx_r_type
== BFD_RELOC_16
10605 || fixP
->fx_r_type
== BFD_RELOC_32
10606 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
10607 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
10608 || fixP
->fx_r_type
== BFD_RELOC_LO16
10609 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
10610 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
10611 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
10612 || fixP
->fx_r_type
== BFD_RELOC_64
10613 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10614 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10615 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
10616 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
10617 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
10618 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
10619 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
10620 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10621 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10625 /* If we aren't adjusting this fixup to be against the section
10626 symbol, we need to adjust the value. */
10628 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10630 if (mips_need_elf_addend_fixup (fixP
))
10632 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
10635 if (value
!= 0 && ! fixP
->fx_pcrel
)
10637 /* In this case, the bfd_install_relocation routine will
10638 incorrectly add the symbol value back in. We just want
10639 the addend to appear in the object file. */
10642 /* Make sure the addend is still non-zero. If it became zero
10643 after the last operation, set it to a spurious value and
10644 subtract the same value from the object file's contents. */
10649 /* The in-place addends for LO16 relocations are signed;
10650 leave the matching HI16 in-place addends as zero. */
10651 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
10653 reloc_howto_type
*howto
;
10654 bfd_vma contents
, mask
, field
;
10656 howto
= bfd_reloc_type_lookup (stdoutput
,
10659 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
10662 target_big_endian
);
10664 /* MASK has bits set where the relocation should go.
10665 FIELD is -value, shifted into the appropriate place
10666 for this relocation. */
10667 mask
= 1 << (howto
->bitsize
- 1);
10668 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
10669 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
10671 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
10672 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10674 target_big_endian
);
10680 /* This code was generated using trial and error and so is
10681 fragile and not trustworthy. If you change it, you should
10682 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10683 they still pass. */
10684 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
10686 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10688 /* BFD's REL handling, for MIPS, is _very_ weird.
10689 This gives the right results, but it can't possibly
10690 be the way things are supposed to work. */
10691 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
10692 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
10693 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
10694 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10699 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc. */
10701 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
10704 switch (fixP
->fx_r_type
)
10706 case BFD_RELOC_MIPS_JMP
:
10707 case BFD_RELOC_MIPS_SHIFT5
:
10708 case BFD_RELOC_MIPS_SHIFT6
:
10709 case BFD_RELOC_MIPS_GOT_DISP
:
10710 case BFD_RELOC_MIPS_GOT_PAGE
:
10711 case BFD_RELOC_MIPS_GOT_OFST
:
10712 case BFD_RELOC_MIPS_SUB
:
10713 case BFD_RELOC_MIPS_INSERT_A
:
10714 case BFD_RELOC_MIPS_INSERT_B
:
10715 case BFD_RELOC_MIPS_DELETE
:
10716 case BFD_RELOC_MIPS_HIGHEST
:
10717 case BFD_RELOC_MIPS_HIGHER
:
10718 case BFD_RELOC_MIPS_SCN_DISP
:
10719 case BFD_RELOC_MIPS_REL16
:
10720 case BFD_RELOC_MIPS_RELGOT
:
10721 case BFD_RELOC_MIPS_JALR
:
10722 case BFD_RELOC_HI16
:
10723 case BFD_RELOC_HI16_S
:
10724 case BFD_RELOC_GPREL16
:
10725 case BFD_RELOC_MIPS_LITERAL
:
10726 case BFD_RELOC_MIPS_CALL16
:
10727 case BFD_RELOC_MIPS_GOT16
:
10728 case BFD_RELOC_GPREL32
:
10729 case BFD_RELOC_MIPS_GOT_HI16
:
10730 case BFD_RELOC_MIPS_GOT_LO16
:
10731 case BFD_RELOC_MIPS_CALL_HI16
:
10732 case BFD_RELOC_MIPS_CALL_LO16
:
10733 case BFD_RELOC_MIPS16_GPREL
:
10734 if (fixP
->fx_pcrel
)
10735 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10736 _("Invalid PC relative reloc"));
10737 /* Nothing needed to do. The value comes from the reloc entry */
10740 case BFD_RELOC_MIPS16_JMP
:
10741 /* We currently always generate a reloc against a symbol, which
10742 means that we don't want an addend even if the symbol is
10744 fixP
->fx_addnumber
= 0;
10747 case BFD_RELOC_PCREL_HI16_S
:
10748 /* The addend for this is tricky if it is internal, so we just
10749 do everything here rather than in bfd_install_relocation. */
10750 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10755 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10757 /* For an external symbol adjust by the address to make it
10758 pcrel_offset. We use the address of the RELLO reloc
10759 which follows this one. */
10760 value
+= (fixP
->fx_next
->fx_frag
->fr_address
10761 + fixP
->fx_next
->fx_where
);
10763 value
= ((value
+ 0x8000) >> 16) & 0xffff;
10764 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10765 if (target_big_endian
)
10767 md_number_to_chars ((char *) buf
, value
, 2);
10770 case BFD_RELOC_PCREL_LO16
:
10771 /* The addend for this is tricky if it is internal, so we just
10772 do everything here rather than in bfd_install_relocation. */
10773 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10778 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10779 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10780 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10781 if (target_big_endian
)
10783 md_number_to_chars ((char *) buf
, value
, 2);
10787 /* This is handled like BFD_RELOC_32, but we output a sign
10788 extended value if we are only 32 bits. */
10790 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10792 if (8 <= sizeof (valueT
))
10793 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10800 w1
= w2
= fixP
->fx_where
;
10801 if (target_big_endian
)
10805 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10806 if ((value
& 0x80000000) != 0)
10810 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10815 case BFD_RELOC_RVA
:
10817 /* If we are deleting this reloc entry, we must fill in the
10818 value now. This can happen if we have a .word which is not
10819 resolved when it appears but is later defined. We also need
10820 to fill in the value if this is an embedded PIC switch table
10823 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10824 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10829 /* If we are deleting this reloc entry, we must fill in the
10831 assert (fixP
->fx_size
== 2);
10833 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10837 case BFD_RELOC_LO16
:
10838 /* When handling an embedded PIC switch statement, we can wind
10839 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10842 if (value
+ 0x8000 > 0xffff)
10843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10844 _("relocation overflow"));
10845 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10846 if (target_big_endian
)
10848 md_number_to_chars ((char *) buf
, value
, 2);
10852 case BFD_RELOC_16_PCREL_S2
:
10853 if ((value
& 0x3) != 0)
10854 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10855 _("Branch to odd address (%lx)"), (long) value
);
10857 /* Fall through. */
10859 case BFD_RELOC_16_PCREL
:
10861 * We need to save the bits in the instruction since fixup_segment()
10862 * might be deleting the relocation entry (i.e., a branch within
10863 * the current segment).
10865 if (!fixP
->fx_done
&& value
!= 0)
10867 /* If 'value' is zero, the remaining reloc code won't actually
10868 do the store, so it must be done here. This is probably
10869 a bug somewhere. */
10871 && (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
10872 || fixP
->fx_addsy
== NULL
/* ??? */
10873 || ! S_IS_DEFINED (fixP
->fx_addsy
)))
10874 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10876 value
= (offsetT
) value
>> 2;
10878 /* update old instruction data */
10879 buf
= (bfd_byte
*) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
10880 if (target_big_endian
)
10881 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10883 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10885 if (value
+ 0x8000 <= 0xffff)
10886 insn
|= value
& 0xffff;
10889 /* The branch offset is too large. If this is an
10890 unconditional branch, and we are not generating PIC code,
10891 we can convert it to an absolute jump instruction. */
10892 if (mips_pic
== NO_PIC
10894 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10895 && (fixP
->fx_frag
->fr_address
10896 < text_section
->vma
+ text_section
->_raw_size
)
10897 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10898 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
10899 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
10901 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
10902 insn
= 0x0c000000; /* jal */
10904 insn
= 0x08000000; /* j */
10905 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
10907 fixP
->fx_addsy
= section_symbol (text_section
);
10908 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
10912 /* FIXME. It would be possible in principle to handle
10913 conditional branches which overflow. They could be
10914 transformed into a branch around a jump. This would
10915 require setting up variant frags for each different
10916 branch type. The native MIPS assembler attempts to
10917 handle these cases, but it appears to do it
10919 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10920 _("Branch out of range"));
10924 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
10927 case BFD_RELOC_VTABLE_INHERIT
:
10930 && !S_IS_DEFINED (fixP
->fx_addsy
)
10931 && !S_IS_WEAK (fixP
->fx_addsy
))
10932 S_SET_WEAK (fixP
->fx_addsy
);
10935 case BFD_RELOC_VTABLE_ENTRY
:
10949 const struct mips_opcode
*p
;
10950 int treg
, sreg
, dreg
, shamt
;
10955 for (i
= 0; i
< NUMOPCODES
; ++i
)
10957 p
= &mips_opcodes
[i
];
10958 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
10960 printf ("%08lx %s\t", oc
, p
->name
);
10961 treg
= (oc
>> 16) & 0x1f;
10962 sreg
= (oc
>> 21) & 0x1f;
10963 dreg
= (oc
>> 11) & 0x1f;
10964 shamt
= (oc
>> 6) & 0x1f;
10966 for (args
= p
->args
;; ++args
)
10977 printf ("%c", *args
);
10981 assert (treg
== sreg
);
10982 printf ("$%d,$%d", treg
, sreg
);
10987 printf ("$%d", dreg
);
10992 printf ("$%d", treg
);
10996 printf ("0x%x", treg
);
11001 printf ("$%d", sreg
);
11005 printf ("0x%08lx", oc
& 0x1ffffff);
11012 printf ("%d", imm
);
11017 printf ("$%d", shamt
);
11028 printf (_("%08lx UNDEFINED\n"), oc
);
11039 name
= input_line_pointer
;
11040 c
= get_symbol_end ();
11041 p
= (symbolS
*) symbol_find_or_make (name
);
11042 *input_line_pointer
= c
;
11046 /* Align the current frag to a given power of two. The MIPS assembler
11047 also automatically adjusts any preceding label. */
11050 mips_align (to
, fill
, label
)
11055 mips_emit_delays (false);
11056 frag_align (to
, fill
, 0);
11057 record_alignment (now_seg
, to
);
11060 assert (S_GET_SEGMENT (label
) == now_seg
);
11061 symbol_set_frag (label
, frag_now
);
11062 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11066 /* Align to a given power of two. .align 0 turns off the automatic
11067 alignment used by the data creating pseudo-ops. */
11071 int x ATTRIBUTE_UNUSED
;
11074 register long temp_fill
;
11075 long max_alignment
= 15;
11079 o Note that the assembler pulls down any immediately preceeding label
11080 to the aligned address.
11081 o It's not documented but auto alignment is reinstated by
11082 a .align pseudo instruction.
11083 o Note also that after auto alignment is turned off the mips assembler
11084 issues an error on attempt to assemble an improperly aligned data item.
11089 temp
= get_absolute_expression ();
11090 if (temp
> max_alignment
)
11091 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11094 as_warn (_("Alignment negative: 0 assumed."));
11097 if (*input_line_pointer
== ',')
11099 ++input_line_pointer
;
11100 temp_fill
= get_absolute_expression ();
11107 mips_align (temp
, (int) temp_fill
,
11108 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11115 demand_empty_rest_of_line ();
11119 mips_flush_pending_output ()
11121 mips_emit_delays (false);
11122 mips_clear_insn_labels ();
11131 /* When generating embedded PIC code, we only use the .text, .lit8,
11132 .sdata and .sbss sections. We change the .data and .rdata
11133 pseudo-ops to use .sdata. */
11134 if (mips_pic
== EMBEDDED_PIC
11135 && (sec
== 'd' || sec
== 'r'))
11139 /* The ELF backend needs to know that we are changing sections, so
11140 that .previous works correctly. We could do something like check
11141 for an obj_section_change_hook macro, but that might be confusing
11142 as it would not be appropriate to use it in the section changing
11143 functions in read.c, since obj-elf.c intercepts those. FIXME:
11144 This should be cleaner, somehow. */
11145 obj_elf_section_change_hook ();
11148 mips_emit_delays (false);
11158 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11159 demand_empty_rest_of_line ();
11163 if (USE_GLOBAL_POINTER_OPT
)
11165 seg
= subseg_new (RDATA_SECTION_NAME
,
11166 (subsegT
) get_absolute_expression ());
11167 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11169 bfd_set_section_flags (stdoutput
, seg
,
11175 if (strcmp (TARGET_OS
, "elf") != 0)
11176 record_alignment (seg
, 4);
11178 demand_empty_rest_of_line ();
11182 as_bad (_("No read only data section in this object file format"));
11183 demand_empty_rest_of_line ();
11189 if (USE_GLOBAL_POINTER_OPT
)
11191 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11192 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11194 bfd_set_section_flags (stdoutput
, seg
,
11195 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
11197 if (strcmp (TARGET_OS
, "elf") != 0)
11198 record_alignment (seg
, 4);
11200 demand_empty_rest_of_line ();
11205 as_bad (_("Global pointers not supported; recompile -G 0"));
11206 demand_empty_rest_of_line ();
11215 mips_enable_auto_align ()
11226 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11227 mips_emit_delays (false);
11228 if (log_size
> 0 && auto_align
)
11229 mips_align (log_size
, 0, label
);
11230 mips_clear_insn_labels ();
11231 cons (1 << log_size
);
11235 s_float_cons (type
)
11240 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11242 mips_emit_delays (false);
11247 mips_align (3, 0, label
);
11249 mips_align (2, 0, label
);
11252 mips_clear_insn_labels ();
11257 /* Handle .globl. We need to override it because on Irix 5 you are
11260 where foo is an undefined symbol, to mean that foo should be
11261 considered to be the address of a function. */
11265 int x ATTRIBUTE_UNUSED
;
11272 name
= input_line_pointer
;
11273 c
= get_symbol_end ();
11274 symbolP
= symbol_find_or_make (name
);
11275 *input_line_pointer
= c
;
11276 SKIP_WHITESPACE ();
11278 /* On Irix 5, every global symbol that is not explicitly labelled as
11279 being a function is apparently labelled as being an object. */
11282 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11287 secname
= input_line_pointer
;
11288 c
= get_symbol_end ();
11289 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11291 as_bad (_("%s: no such section"), secname
);
11292 *input_line_pointer
= c
;
11294 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11295 flag
= BSF_FUNCTION
;
11298 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11300 S_SET_EXTERNAL (symbolP
);
11301 demand_empty_rest_of_line ();
11306 int x ATTRIBUTE_UNUSED
;
11311 opt
= input_line_pointer
;
11312 c
= get_symbol_end ();
11316 /* FIXME: What does this mean? */
11318 else if (strncmp (opt
, "pic", 3) == 0)
11322 i
= atoi (opt
+ 3);
11326 mips_pic
= SVR4_PIC
;
11328 as_bad (_(".option pic%d not supported"), i
);
11330 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
11332 if (g_switch_seen
&& g_switch_value
!= 0)
11333 as_warn (_("-G may not be used with SVR4 PIC code"));
11334 g_switch_value
= 0;
11335 bfd_set_gp_size (stdoutput
, 0);
11339 as_warn (_("Unrecognized option \"%s\""), opt
);
11341 *input_line_pointer
= c
;
11342 demand_empty_rest_of_line ();
11345 /* This structure is used to hold a stack of .set values. */
11347 struct mips_option_stack
11349 struct mips_option_stack
*next
;
11350 struct mips_set_options options
;
11353 static struct mips_option_stack
*mips_opts_stack
;
11355 /* Handle the .set pseudo-op. */
11359 int x ATTRIBUTE_UNUSED
;
11361 char *name
= input_line_pointer
, ch
;
11363 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11364 ++input_line_pointer
;
11365 ch
= *input_line_pointer
;
11366 *input_line_pointer
= '\0';
11368 if (strcmp (name
, "reorder") == 0)
11370 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11372 /* If we still have pending nops, we can discard them. The
11373 usual nop handling will insert any that are still
11375 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11376 * (mips_opts
.mips16
? 2 : 4));
11377 prev_nop_frag
= NULL
;
11379 mips_opts
.noreorder
= 0;
11381 else if (strcmp (name
, "noreorder") == 0)
11383 mips_emit_delays (true);
11384 mips_opts
.noreorder
= 1;
11385 mips_any_noreorder
= 1;
11387 else if (strcmp (name
, "at") == 0)
11389 mips_opts
.noat
= 0;
11391 else if (strcmp (name
, "noat") == 0)
11393 mips_opts
.noat
= 1;
11395 else if (strcmp (name
, "macro") == 0)
11397 mips_opts
.warn_about_macros
= 0;
11399 else if (strcmp (name
, "nomacro") == 0)
11401 if (mips_opts
.noreorder
== 0)
11402 as_bad (_("`noreorder' must be set before `nomacro'"));
11403 mips_opts
.warn_about_macros
= 1;
11405 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11407 mips_opts
.nomove
= 0;
11409 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11411 mips_opts
.nomove
= 1;
11413 else if (strcmp (name
, "bopt") == 0)
11415 mips_opts
.nobopt
= 0;
11417 else if (strcmp (name
, "nobopt") == 0)
11419 mips_opts
.nobopt
= 1;
11421 else if (strcmp (name
, "mips16") == 0
11422 || strcmp (name
, "MIPS-16") == 0)
11423 mips_opts
.mips16
= 1;
11424 else if (strcmp (name
, "nomips16") == 0
11425 || strcmp (name
, "noMIPS-16") == 0)
11426 mips_opts
.mips16
= 0;
11427 else if (strcmp (name
, "mips3d") == 0)
11428 mips_opts
.ase_mips3d
= 1;
11429 else if (strcmp (name
, "nomips3d") == 0)
11430 mips_opts
.ase_mips3d
= 0;
11431 else if (strncmp (name
, "mips", 4) == 0)
11435 /* Permit the user to change the ISA on the fly. Needless to
11436 say, misuse can cause serious problems. */
11437 isa
= atoi (name
+ 4);
11441 mips_opts
.gp32
= file_mips_gp32
;
11442 mips_opts
.fp32
= file_mips_fp32
;
11443 mips_opts
.abi
= file_mips_abi
;
11448 mips_opts
.gp32
= 1;
11449 mips_opts
.fp32
= 1;
11455 /* Loosen ABI register width restriction. */
11456 if (mips_opts
.abi
== O32_ABI
)
11457 mips_opts
.abi
= NO_ABI
;
11458 mips_opts
.gp32
= 0;
11459 mips_opts
.fp32
= 0;
11462 as_bad (_("unknown ISA level %s"), name
+ 4);
11468 case 0: mips_opts
.isa
= file_mips_isa
; break;
11469 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
11470 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
11471 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
11472 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
11473 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
11474 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
11475 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
11476 default: as_bad (_("unknown ISA level %s"), name
+ 4); break;
11479 else if (strcmp (name
, "autoextend") == 0)
11480 mips_opts
.noautoextend
= 0;
11481 else if (strcmp (name
, "noautoextend") == 0)
11482 mips_opts
.noautoextend
= 1;
11483 else if (strcmp (name
, "push") == 0)
11485 struct mips_option_stack
*s
;
11487 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11488 s
->next
= mips_opts_stack
;
11489 s
->options
= mips_opts
;
11490 mips_opts_stack
= s
;
11492 else if (strcmp (name
, "pop") == 0)
11494 struct mips_option_stack
*s
;
11496 s
= mips_opts_stack
;
11498 as_bad (_(".set pop with no .set push"));
11501 /* If we're changing the reorder mode we need to handle
11502 delay slots correctly. */
11503 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11504 mips_emit_delays (true);
11505 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11507 if (prev_nop_frag
!= NULL
)
11509 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11510 * (mips_opts
.mips16
? 2 : 4));
11511 prev_nop_frag
= NULL
;
11515 mips_opts
= s
->options
;
11516 mips_opts_stack
= s
->next
;
11522 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11524 *input_line_pointer
= ch
;
11525 demand_empty_rest_of_line ();
11528 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11529 .option pic2. It means to generate SVR4 PIC calls. */
11532 s_abicalls (ignore
)
11533 int ignore ATTRIBUTE_UNUSED
;
11535 mips_pic
= SVR4_PIC
;
11536 if (USE_GLOBAL_POINTER_OPT
)
11538 if (g_switch_seen
&& g_switch_value
!= 0)
11539 as_warn (_("-G may not be used with SVR4 PIC code"));
11540 g_switch_value
= 0;
11542 bfd_set_gp_size (stdoutput
, 0);
11543 demand_empty_rest_of_line ();
11546 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11547 PIC code. It sets the $gp register for the function based on the
11548 function address, which is in the register named in the argument.
11549 This uses a relocation against _gp_disp, which is handled specially
11550 by the linker. The result is:
11551 lui $gp,%hi(_gp_disp)
11552 addiu $gp,$gp,%lo(_gp_disp)
11553 addu $gp,$gp,.cpload argument
11554 The .cpload argument is normally $25 == $t9. */
11558 int ignore ATTRIBUTE_UNUSED
;
11563 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11564 .cpload is ignored. */
11565 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11571 /* .cpload should be in a .set noreorder section. */
11572 if (mips_opts
.noreorder
== 0)
11573 as_warn (_(".cpload not in noreorder section"));
11575 ex
.X_op
= O_symbol
;
11576 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
11577 ex
.X_op_symbol
= NULL
;
11578 ex
.X_add_number
= 0;
11580 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11581 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11583 macro_build_lui (NULL
, &icnt
, &ex
, mips_gp_register
);
11584 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j",
11585 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_LO16
);
11587 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
11588 mips_gp_register
, mips_gp_register
, tc_get_register (0));
11590 demand_empty_rest_of_line ();
11593 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11594 .cpsetup $reg1, offset|$reg2, label
11596 If offset is given, this results in:
11597 sd $gp, offset($sp)
11598 lui $gp, %hi(%neg(%gp_rel(label)))
11599 daddiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11600 addu $gp, $gp, $reg1
11602 If $reg2 is given, this results in:
11603 daddu $reg2, $gp, $0
11604 lui $gp, %hi(%neg(%gp_rel(label)))
11605 daddiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11606 addu $gp, $gp, $reg1
11610 int ignore ATTRIBUTE_UNUSED
;
11612 expressionS ex_off
;
11613 expressionS ex_sym
;
11618 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11619 We also need NewABI support. */
11620 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11626 reg1
= tc_get_register (0);
11627 SKIP_WHITESPACE ();
11628 if (*input_line_pointer
!= ',')
11630 as_bad (_("missing argument separator ',' for .cpsetup"));
11634 input_line_pointer
++;
11635 SKIP_WHITESPACE ();
11636 if (*input_line_pointer
== '$')
11637 mips_cpreturn_register
= tc_get_register (0);
11639 mips_cpreturn_offset
= get_absolute_expression ();
11640 SKIP_WHITESPACE ();
11641 if (*input_line_pointer
!= ',')
11643 as_bad (_("missing argument separator ',' for .cpsetup"));
11647 ++input_line_pointer
;
11648 SKIP_WHITESPACE ();
11649 sym
= input_line_pointer
;
11650 while (ISALNUM (*input_line_pointer
))
11651 ++input_line_pointer
;
11652 *input_line_pointer
= 0;
11654 ex_sym
.X_op
= O_symbol
;
11655 ex_sym
.X_add_symbol
= symbol_find_or_make (sym
);
11656 ex_sym
.X_op_symbol
= NULL
;
11657 ex_sym
.X_add_number
= 0;
11659 if (mips_cpreturn_register
== -1)
11661 ex_off
.X_op
= O_constant
;
11662 ex_off
.X_add_symbol
= NULL
;
11663 ex_off
.X_op_symbol
= NULL
;
11664 ex_off
.X_add_number
= mips_cpreturn_offset
;
11666 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
11667 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11670 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11671 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
11673 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
11674 (int) BFD_RELOC_GPREL16
);
11675 fix_new (frag_now
, prev_insn_where
, 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11676 fix_new (frag_now
, prev_insn_where
, 0, NULL
, 0, 0, BFD_RELOC_HI16_S
);
11677 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
11678 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
11679 fix_new (frag_now
, prev_insn_where
, 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11680 fix_new (frag_now
, prev_insn_where
, 0, NULL
, 0, 0, BFD_RELOC_LO16
);
11681 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11682 HAVE_64BIT_ADDRESSES
? "daddu" : "addu", "d,v,t",
11683 mips_gp_register
, mips_gp_register
, reg1
);
11685 demand_empty_rest_of_line ();
11690 int ignore ATTRIBUTE_UNUSED
;
11692 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11693 .cplocal is ignored. */
11694 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11700 mips_gp_register
= tc_get_register (0);
11703 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11704 offset from $sp. The offset is remembered, and after making a PIC
11705 call $gp is restored from that location. */
11708 s_cprestore (ignore
)
11709 int ignore ATTRIBUTE_UNUSED
;
11714 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11715 .cprestore is ignored. */
11716 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11722 mips_cprestore_offset
= get_absolute_expression ();
11723 mips_cprestore_valid
= 1;
11725 ex
.X_op
= O_constant
;
11726 ex
.X_add_symbol
= NULL
;
11727 ex
.X_op_symbol
= NULL
;
11728 ex
.X_add_number
= mips_cprestore_offset
;
11730 macro_build ((char *) NULL
, &icnt
, &ex
, HAVE_32BIT_ADDRESSES
? "sw" : "sd",
11731 "t,o(b)", mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11733 demand_empty_rest_of_line ();
11736 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11737 was given in the preceeding .gpsetup, it results in:
11738 ld $gp, offset($sp)
11740 If a register $reg2 was given there, it results in:
11741 daddiu $gp, $gp, $reg2
11744 s_cpreturn (ignore
)
11745 int ignore ATTRIBUTE_UNUSED
;
11750 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11751 We also need NewABI support. */
11752 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11758 if (mips_cpreturn_register
== -1)
11760 ex
.X_op
= O_constant
;
11761 ex
.X_add_symbol
= NULL
;
11762 ex
.X_op_symbol
= NULL
;
11763 ex
.X_add_number
= mips_cpreturn_offset
;
11765 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
11766 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11769 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11770 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
11772 demand_empty_rest_of_line ();
11775 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11776 code. It sets the offset to use in gp_rel relocations. */
11780 int ignore ATTRIBUTE_UNUSED
;
11782 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11783 We also need NewABI support. */
11784 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11790 mips_gprel_offset
= get_absolute_expression ();
11792 demand_empty_rest_of_line ();
11795 /* Handle the .gpword pseudo-op. This is used when generating PIC
11796 code. It generates a 32 bit GP relative reloc. */
11800 int ignore ATTRIBUTE_UNUSED
;
11806 /* When not generating PIC code, this is treated as .word. */
11807 if (mips_pic
!= SVR4_PIC
)
11813 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11814 mips_emit_delays (true);
11816 mips_align (2, 0, label
);
11817 mips_clear_insn_labels ();
11821 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11823 as_bad (_("Unsupported use of .gpword"));
11824 ignore_rest_of_line ();
11828 md_number_to_chars (p
, (valueT
) 0, 4);
11829 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, false,
11830 BFD_RELOC_GPREL32
);
11832 demand_empty_rest_of_line ();
11835 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11836 tables in SVR4 PIC code. */
11840 int ignore ATTRIBUTE_UNUSED
;
11845 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
11847 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11853 /* Add $gp to the register named as an argument. */
11854 reg
= tc_get_register (0);
11855 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11856 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
11857 "d,v,t", reg
, reg
, mips_gp_register
);
11859 demand_empty_rest_of_line ();
11862 /* Handle the .insn pseudo-op. This marks instruction labels in
11863 mips16 mode. This permits the linker to handle them specially,
11864 such as generating jalx instructions when needed. We also make
11865 them odd for the duration of the assembly, in order to generate the
11866 right sort of code. We will make them even in the adjust_symtab
11867 routine, while leaving them marked. This is convenient for the
11868 debugger and the disassembler. The linker knows to make them odd
11873 int ignore ATTRIBUTE_UNUSED
;
11875 mips16_mark_labels ();
11877 demand_empty_rest_of_line ();
11880 /* Handle a .stabn directive. We need these in order to mark a label
11881 as being a mips16 text label correctly. Sometimes the compiler
11882 will emit a label, followed by a .stabn, and then switch sections.
11883 If the label and .stabn are in mips16 mode, then the label is
11884 really a mips16 text label. */
11891 mips16_mark_labels ();
11896 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
11900 s_mips_weakext (ignore
)
11901 int ignore ATTRIBUTE_UNUSED
;
11908 name
= input_line_pointer
;
11909 c
= get_symbol_end ();
11910 symbolP
= symbol_find_or_make (name
);
11911 S_SET_WEAK (symbolP
);
11912 *input_line_pointer
= c
;
11914 SKIP_WHITESPACE ();
11916 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11918 if (S_IS_DEFINED (symbolP
))
11920 as_bad ("ignoring attempt to redefine symbol %s",
11921 S_GET_NAME (symbolP
));
11922 ignore_rest_of_line ();
11926 if (*input_line_pointer
== ',')
11928 ++input_line_pointer
;
11929 SKIP_WHITESPACE ();
11933 if (exp
.X_op
!= O_symbol
)
11935 as_bad ("bad .weakext directive");
11936 ignore_rest_of_line ();
11939 symbol_set_value_expression (symbolP
, &exp
);
11942 demand_empty_rest_of_line ();
11945 /* Parse a register string into a number. Called from the ECOFF code
11946 to parse .frame. The argument is non-zero if this is the frame
11947 register, so that we can record it in mips_frame_reg. */
11950 tc_get_register (frame
)
11955 SKIP_WHITESPACE ();
11956 if (*input_line_pointer
++ != '$')
11958 as_warn (_("expected `$'"));
11961 else if (ISDIGIT (*input_line_pointer
))
11963 reg
= get_absolute_expression ();
11964 if (reg
< 0 || reg
>= 32)
11966 as_warn (_("Bad register number"));
11972 if (strncmp (input_line_pointer
, "fp", 2) == 0)
11974 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
11976 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
11978 else if (strncmp (input_line_pointer
, "at", 2) == 0)
11982 as_warn (_("Unrecognized register name"));
11985 input_line_pointer
+= 2;
11989 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
11990 mips_frame_reg_valid
= 1;
11991 mips_cprestore_valid
= 0;
11997 md_section_align (seg
, addr
)
12001 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12004 /* We don't need to align ELF sections to the full alignment.
12005 However, Irix 5 may prefer that we align them at least to a 16
12006 byte boundary. We don't bother to align the sections if we are
12007 targeted for an embedded system. */
12008 if (strcmp (TARGET_OS
, "elf") == 0)
12014 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12017 /* Utility routine, called from above as well. If called while the
12018 input file is still being read, it's only an approximation. (For
12019 example, a symbol may later become defined which appeared to be
12020 undefined earlier.) */
12023 nopic_need_relax (sym
, before_relaxing
)
12025 int before_relaxing
;
12030 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
12032 const char *symname
;
12035 /* Find out whether this symbol can be referenced off the $gp
12036 register. It can be if it is smaller than the -G size or if
12037 it is in the .sdata or .sbss section. Certain symbols can
12038 not be referenced off the $gp, although it appears as though
12040 symname
= S_GET_NAME (sym
);
12041 if (symname
!= (const char *) NULL
12042 && (strcmp (symname
, "eprol") == 0
12043 || strcmp (symname
, "etext") == 0
12044 || strcmp (symname
, "_gp") == 0
12045 || strcmp (symname
, "edata") == 0
12046 || strcmp (symname
, "_fbss") == 0
12047 || strcmp (symname
, "_fdata") == 0
12048 || strcmp (symname
, "_ftext") == 0
12049 || strcmp (symname
, "end") == 0
12050 || strcmp (symname
, "_gp_disp") == 0))
12052 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12054 #ifndef NO_ECOFF_DEBUGGING
12055 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12056 && (symbol_get_obj (sym
)->ecoff_extern_size
12057 <= g_switch_value
))
12059 /* We must defer this decision until after the whole
12060 file has been read, since there might be a .extern
12061 after the first use of this symbol. */
12062 || (before_relaxing
12063 #ifndef NO_ECOFF_DEBUGGING
12064 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12066 && S_GET_VALUE (sym
) == 0)
12067 || (S_GET_VALUE (sym
) != 0
12068 && S_GET_VALUE (sym
) <= g_switch_value
)))
12072 const char *segname
;
12074 segname
= segment_name (S_GET_SEGMENT (sym
));
12075 assert (strcmp (segname
, ".lit8") != 0
12076 && strcmp (segname
, ".lit4") != 0);
12077 change
= (strcmp (segname
, ".sdata") != 0
12078 && strcmp (segname
, ".sbss") != 0
12079 && strncmp (segname
, ".sdata.", 7) != 0
12080 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12085 /* We are not optimizing for the $gp register. */
12089 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12090 extended opcode. SEC is the section the frag is in. */
12093 mips16_extended_frag (fragp
, sec
, stretch
)
12099 register const struct mips16_immed_operand
*op
;
12101 int mintiny
, maxtiny
;
12105 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12107 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12110 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12111 op
= mips16_immed_operands
;
12112 while (op
->type
!= type
)
12115 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12120 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12123 maxtiny
= 1 << op
->nbits
;
12128 maxtiny
= (1 << op
->nbits
) - 1;
12133 mintiny
= - (1 << (op
->nbits
- 1));
12134 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12137 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12138 val
= S_GET_VALUE (fragp
->fr_symbol
);
12139 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12145 /* We won't have the section when we are called from
12146 mips_relax_frag. However, we will always have been called
12147 from md_estimate_size_before_relax first. If this is a
12148 branch to a different section, we mark it as such. If SEC is
12149 NULL, and the frag is not marked, then it must be a branch to
12150 the same section. */
12153 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12158 /* Must have been called from md_estimate_size_before_relax. */
12161 fragp
->fr_subtype
=
12162 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12164 /* FIXME: We should support this, and let the linker
12165 catch branches and loads that are out of range. */
12166 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12167 _("unsupported PC relative reference to different section"));
12171 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12172 /* Assume non-extended on the first relaxation pass.
12173 The address we have calculated will be bogus if this is
12174 a forward branch to another frag, as the forward frag
12175 will have fr_address == 0. */
12179 /* In this case, we know for sure that the symbol fragment is in
12180 the same section. If the relax_marker of the symbol fragment
12181 differs from the relax_marker of this fragment, we have not
12182 yet adjusted the symbol fragment fr_address. We want to add
12183 in STRETCH in order to get a better estimate of the address.
12184 This particularly matters because of the shift bits. */
12186 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12190 /* Adjust stretch for any alignment frag. Note that if have
12191 been expanding the earlier code, the symbol may be
12192 defined in what appears to be an earlier frag. FIXME:
12193 This doesn't handle the fr_subtype field, which specifies
12194 a maximum number of bytes to skip when doing an
12196 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12198 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12201 stretch
= - ((- stretch
)
12202 & ~ ((1 << (int) f
->fr_offset
) - 1));
12204 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12213 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12215 /* The base address rules are complicated. The base address of
12216 a branch is the following instruction. The base address of a
12217 PC relative load or add is the instruction itself, but if it
12218 is in a delay slot (in which case it can not be extended) use
12219 the address of the instruction whose delay slot it is in. */
12220 if (type
== 'p' || type
== 'q')
12224 /* If we are currently assuming that this frag should be
12225 extended, then, the current address is two bytes
12227 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12230 /* Ignore the low bit in the target, since it will be set
12231 for a text label. */
12232 if ((val
& 1) != 0)
12235 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12237 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12240 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12242 /* Branch offsets have an implicit 0 in the lowest bit. */
12243 if (type
== 'p' || type
== 'q')
12246 /* If any of the shifted bits are set, we must use an extended
12247 opcode. If the address depends on the size of this
12248 instruction, this can lead to a loop, so we arrange to always
12249 use an extended opcode. We only check this when we are in
12250 the main relaxation loop, when SEC is NULL. */
12251 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12253 fragp
->fr_subtype
=
12254 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12258 /* If we are about to mark a frag as extended because the value
12259 is precisely maxtiny + 1, then there is a chance of an
12260 infinite loop as in the following code:
12265 In this case when the la is extended, foo is 0x3fc bytes
12266 away, so the la can be shrunk, but then foo is 0x400 away, so
12267 the la must be extended. To avoid this loop, we mark the
12268 frag as extended if it was small, and is about to become
12269 extended with a value of maxtiny + 1. */
12270 if (val
== ((maxtiny
+ 1) << op
->shift
)
12271 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12274 fragp
->fr_subtype
=
12275 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12279 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12280 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12282 if ((val
& ((1 << op
->shift
) - 1)) != 0
12283 || val
< (mintiny
<< op
->shift
)
12284 || val
> (maxtiny
<< op
->shift
))
12290 /* Estimate the size of a frag before relaxing. Unless this is the
12291 mips16, we are not really relaxing here, and the final size is
12292 encoded in the subtype information. For the mips16, we have to
12293 decide whether we are using an extended opcode or not. */
12296 md_estimate_size_before_relax (fragp
, segtype
)
12301 boolean linkonce
= false;
12303 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12304 /* We don't want to modify the EXTENDED bit here; it might get us
12305 into infinite loops. We change it only in mips_relax_frag(). */
12306 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12308 if (mips_pic
== NO_PIC
)
12310 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12312 else if (mips_pic
== SVR4_PIC
)
12317 sym
= fragp
->fr_symbol
;
12319 /* Handle the case of a symbol equated to another symbol. */
12320 while (symbol_equated_reloc_p (sym
))
12324 /* It's possible to get a loop here in a badly written
12326 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12332 symsec
= S_GET_SEGMENT (sym
);
12334 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12335 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12337 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12341 /* The GNU toolchain uses an extension for ELF: a section
12342 beginning with the magic string .gnu.linkonce is a linkonce
12344 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12345 sizeof ".gnu.linkonce" - 1) == 0)
12349 /* This must duplicate the test in adjust_reloc_syms. */
12350 change
= (symsec
!= &bfd_und_section
12351 && symsec
!= &bfd_abs_section
12352 && ! bfd_is_com_section (symsec
)
12355 /* A global or weak symbol is treated as external. */
12356 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12357 || (! S_IS_WEAK (sym
)
12358 && (! S_IS_EXTERN (sym
) || mips_pic
== EMBEDDED_PIC
)))
12367 /* Record the offset to the first reloc in the fr_opcode field.
12368 This lets md_convert_frag and tc_gen_reloc know that the code
12369 must be expanded. */
12370 fragp
->fr_opcode
= (fragp
->fr_literal
12372 - RELAX_OLD (fragp
->fr_subtype
)
12373 + RELAX_RELOC1 (fragp
->fr_subtype
));
12374 /* FIXME: This really needs as_warn_where. */
12375 if (RELAX_WARN (fragp
->fr_subtype
))
12376 as_warn (_("AT used after \".set noat\" or macro used after "
12377 "\".set nomacro\""));
12379 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
12385 /* This is called to see whether a reloc against a defined symbol
12386 should be converted into a reloc against a section. Don't adjust
12387 MIPS16 jump relocations, so we don't have to worry about the format
12388 of the offset in the .o file. Don't adjust relocations against
12389 mips16 symbols, so that the linker can find them if it needs to set
12393 mips_fix_adjustable (fixp
)
12397 /* Prevent all adjustments to global symbols. */
12398 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12399 && mips_pic
!= EMBEDDED_PIC
12400 && (S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
)))
12403 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12405 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12406 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12408 if (fixp
->fx_addsy
== NULL
)
12411 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12412 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12413 && fixp
->fx_subsy
== NULL
)
12419 /* Translate internal representation of relocation info to BFD target
12423 tc_gen_reloc (section
, fixp
)
12424 asection
*section ATTRIBUTE_UNUSED
;
12427 static arelent
*retval
[4];
12429 bfd_reloc_code_real_type code
;
12431 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
12434 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12435 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12436 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12438 if (mips_pic
== EMBEDDED_PIC
12439 && SWITCH_TABLE (fixp
))
12441 /* For a switch table entry we use a special reloc. The addend
12442 is actually the difference between the reloc address and the
12444 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12445 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
12446 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12447 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
12449 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
12451 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12452 reloc
->addend
= fixp
->fx_addnumber
;
12455 /* We use a special addend for an internal RELLO reloc. */
12456 if (symbol_section_p (fixp
->fx_addsy
))
12457 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12459 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
12462 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
12464 assert (fixp
->fx_next
!= NULL
12465 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
12467 /* The reloc is relative to the RELLO; adjust the addend
12469 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12470 reloc
->addend
= fixp
->fx_next
->fx_addnumber
;
12473 /* We use a special addend for an internal RELHI reloc. */
12474 if (symbol_section_p (fixp
->fx_addsy
))
12475 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
12476 + fixp
->fx_next
->fx_where
12477 - S_GET_VALUE (fixp
->fx_subsy
));
12479 reloc
->addend
= (fixp
->fx_addnumber
12480 + fixp
->fx_next
->fx_frag
->fr_address
12481 + fixp
->fx_next
->fx_where
);
12484 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12485 reloc
->addend
= fixp
->fx_addnumber
;
12488 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
12489 /* A gruesome hack which is a result of the gruesome gas reloc
12491 reloc
->addend
= reloc
->address
;
12493 reloc
->addend
= -reloc
->address
;
12496 /* If this is a variant frag, we may need to adjust the existing
12497 reloc and generate a new one. */
12498 if (fixp
->fx_frag
->fr_opcode
!= NULL
12499 && (fixp
->fx_r_type
== BFD_RELOC_GPREL16
12500 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
12501 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
12502 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12503 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
12504 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12505 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
12510 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
12512 /* If this is not the last reloc in this frag, then we have two
12513 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12514 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12515 the second one handle all of them. */
12516 if (fixp
->fx_next
!= NULL
12517 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
12519 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
12520 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
12521 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12522 && (fixp
->fx_next
->fx_r_type
12523 == BFD_RELOC_MIPS_GOT_LO16
))
12524 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12525 && (fixp
->fx_next
->fx_r_type
12526 == BFD_RELOC_MIPS_CALL_LO16
)));
12531 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
12532 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12533 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
12535 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12536 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12537 reloc2
->address
= (reloc
->address
12538 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
12539 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
12540 reloc2
->addend
= fixp
->fx_addnumber
;
12541 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
12542 assert (reloc2
->howto
!= NULL
);
12544 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
12548 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
12551 reloc3
->address
+= 4;
12554 if (mips_pic
== NO_PIC
)
12556 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
12557 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
12559 else if (mips_pic
== SVR4_PIC
)
12561 switch (fixp
->fx_r_type
)
12565 case BFD_RELOC_MIPS_GOT16
:
12567 case BFD_RELOC_MIPS_CALL16
:
12568 case BFD_RELOC_MIPS_GOT_LO16
:
12569 case BFD_RELOC_MIPS_CALL_LO16
:
12570 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
12578 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
12579 to be used in the relocation's section offset. */
12580 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12582 reloc
->address
= reloc
->addend
;
12586 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12587 fixup_segment converted a non-PC relative reloc into a PC
12588 relative reloc. In such a case, we need to convert the reloc
12590 code
= fixp
->fx_r_type
;
12591 if (fixp
->fx_pcrel
)
12596 code
= BFD_RELOC_8_PCREL
;
12599 code
= BFD_RELOC_16_PCREL
;
12602 code
= BFD_RELOC_32_PCREL
;
12605 code
= BFD_RELOC_64_PCREL
;
12607 case BFD_RELOC_8_PCREL
:
12608 case BFD_RELOC_16_PCREL
:
12609 case BFD_RELOC_32_PCREL
:
12610 case BFD_RELOC_64_PCREL
:
12611 case BFD_RELOC_16_PCREL_S2
:
12612 case BFD_RELOC_PCREL_HI16_S
:
12613 case BFD_RELOC_PCREL_LO16
:
12616 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12617 _("Cannot make %s relocation PC relative"),
12618 bfd_get_reloc_code_name (code
));
12623 /* md_apply_fix3 has a double-subtraction hack to get
12624 bfd_install_relocation to behave nicely. GPREL relocations are
12625 handled correctly without this hack, so undo it here. We can't
12626 stop md_apply_fix3 from subtracting twice in the first place since
12627 the fake addend is required for variant frags above. */
12628 if (fixp
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
12629 && code
== BFD_RELOC_GPREL16
12630 && reloc
->addend
!= 0
12631 && mips_need_elf_addend_fixup (fixp
))
12632 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
12635 /* To support a PC relative reloc when generating embedded PIC code
12636 for ECOFF, we use a Cygnus extension. We check for that here to
12637 make sure that we don't let such a reloc escape normally. */
12638 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12639 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12640 && code
== BFD_RELOC_16_PCREL_S2
12641 && mips_pic
!= EMBEDDED_PIC
)
12642 reloc
->howto
= NULL
;
12644 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12646 if (reloc
->howto
== NULL
)
12648 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12649 _("Can not represent %s relocation in this object file format"),
12650 bfd_get_reloc_code_name (code
));
12657 /* Relax a machine dependent frag. This returns the amount by which
12658 the current size of the frag should change. */
12661 mips_relax_frag (fragp
, stretch
)
12665 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12668 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12670 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12672 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12677 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12679 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12686 /* Convert a machine dependent frag. */
12689 md_convert_frag (abfd
, asec
, fragp
)
12690 bfd
*abfd ATTRIBUTE_UNUSED
;
12697 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12700 register const struct mips16_immed_operand
*op
;
12701 boolean small
, ext
;
12704 unsigned long insn
;
12705 boolean use_extend
;
12706 unsigned short extend
;
12708 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12709 op
= mips16_immed_operands
;
12710 while (op
->type
!= type
)
12713 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12724 resolve_symbol_value (fragp
->fr_symbol
);
12725 val
= S_GET_VALUE (fragp
->fr_symbol
);
12730 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12732 /* The rules for the base address of a PC relative reloc are
12733 complicated; see mips16_extended_frag. */
12734 if (type
== 'p' || type
== 'q')
12739 /* Ignore the low bit in the target, since it will be
12740 set for a text label. */
12741 if ((val
& 1) != 0)
12744 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12746 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12749 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
12752 /* Make sure the section winds up with the alignment we have
12755 record_alignment (asec
, op
->shift
);
12759 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
12760 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
12761 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12762 _("extended instruction in delay slot"));
12764 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
12766 if (target_big_endian
)
12767 insn
= bfd_getb16 (buf
);
12769 insn
= bfd_getl16 (buf
);
12771 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
12772 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
12773 small
, ext
, &insn
, &use_extend
, &extend
);
12777 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
12778 fragp
->fr_fix
+= 2;
12782 md_number_to_chars ((char *) buf
, insn
, 2);
12783 fragp
->fr_fix
+= 2;
12788 if (fragp
->fr_opcode
== NULL
)
12791 old
= RELAX_OLD (fragp
->fr_subtype
);
12792 new = RELAX_NEW (fragp
->fr_subtype
);
12793 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
12796 memcpy (fixptr
- old
, fixptr
, new);
12798 fragp
->fr_fix
+= new - old
;
12804 /* This function is called after the relocs have been generated.
12805 We've been storing mips16 text labels as odd. Here we convert them
12806 back to even for the convenience of the debugger. */
12809 mips_frob_file_after_relocs ()
12812 unsigned int count
, i
;
12814 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12817 syms
= bfd_get_outsymbols (stdoutput
);
12818 count
= bfd_get_symcount (stdoutput
);
12819 for (i
= 0; i
< count
; i
++, syms
++)
12821 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
12822 && ((*syms
)->value
& 1) != 0)
12824 (*syms
)->value
&= ~1;
12825 /* If the symbol has an odd size, it was probably computed
12826 incorrectly, so adjust that as well. */
12827 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
12828 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
12835 /* This function is called whenever a label is defined. It is used
12836 when handling branch delays; if a branch has a label, we assume we
12837 can not move it. */
12840 mips_define_label (sym
)
12843 struct insn_label_list
*l
;
12845 if (free_insn_labels
== NULL
)
12846 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
12849 l
= free_insn_labels
;
12850 free_insn_labels
= l
->next
;
12854 l
->next
= insn_labels
;
12858 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12860 /* Some special processing for a MIPS ELF file. */
12863 mips_elf_final_processing ()
12865 /* Write out the register information. */
12866 if (file_mips_abi
!= N64_ABI
)
12870 s
.ri_gprmask
= mips_gprmask
;
12871 s
.ri_cprmask
[0] = mips_cprmask
[0];
12872 s
.ri_cprmask
[1] = mips_cprmask
[1];
12873 s
.ri_cprmask
[2] = mips_cprmask
[2];
12874 s
.ri_cprmask
[3] = mips_cprmask
[3];
12875 /* The gp_value field is set by the MIPS ELF backend. */
12877 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
12878 ((Elf32_External_RegInfo
*)
12879 mips_regmask_frag
));
12883 Elf64_Internal_RegInfo s
;
12885 s
.ri_gprmask
= mips_gprmask
;
12887 s
.ri_cprmask
[0] = mips_cprmask
[0];
12888 s
.ri_cprmask
[1] = mips_cprmask
[1];
12889 s
.ri_cprmask
[2] = mips_cprmask
[2];
12890 s
.ri_cprmask
[3] = mips_cprmask
[3];
12891 /* The gp_value field is set by the MIPS ELF backend. */
12893 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
12894 ((Elf64_External_RegInfo
*)
12895 mips_regmask_frag
));
12898 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
12899 sort of BFD interface for this. */
12900 if (mips_any_noreorder
)
12901 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
12902 if (mips_pic
!= NO_PIC
)
12903 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
12905 /* Set MIPS ELF flags for ASEs. */
12906 #if 0 /* XXX FIXME */
12907 if (file_ase_mips3d
)
12908 elf_elfheader (stdoutput
)->e_flags
|= ???;
12911 /* Set the MIPS ELF ABI flags. */
12912 if (file_mips_abi
== NO_ABI
)
12914 else if (file_mips_abi
== O32_ABI
)
12915 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
12916 else if (file_mips_abi
== O64_ABI
)
12917 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
12918 else if (file_mips_abi
== EABI_ABI
)
12921 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
12923 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
12925 else if (file_mips_abi
== N32_ABI
)
12926 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
12928 /* Nothing to do for N64_ABI. */
12930 if (mips_32bitmode
)
12931 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
12934 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
12936 typedef struct proc
{
12938 unsigned long reg_mask
;
12939 unsigned long reg_offset
;
12940 unsigned long fpreg_mask
;
12941 unsigned long fpreg_offset
;
12942 unsigned long frame_offset
;
12943 unsigned long frame_reg
;
12944 unsigned long pc_reg
;
12947 static procS cur_proc
;
12948 static procS
*cur_proc_ptr
;
12949 static int numprocs
;
12951 /* Fill in an rs_align_code fragment. */
12954 mips_handle_align (fragp
)
12957 if (fragp
->fr_type
!= rs_align_code
)
12960 if (mips_opts
.mips16
)
12962 static const unsigned char be_nop
[] = { 0x65, 0x00 };
12963 static const unsigned char le_nop
[] = { 0x00, 0x65 };
12968 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
12969 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
12977 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
12981 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
12992 /* check for premature end, nesting errors, etc */
12994 as_warn (_("missing .end at end of assembly"));
13003 if (*input_line_pointer
== '-')
13005 ++input_line_pointer
;
13008 if (!ISDIGIT (*input_line_pointer
))
13009 as_bad (_("expected simple number"));
13010 if (input_line_pointer
[0] == '0')
13012 if (input_line_pointer
[1] == 'x')
13014 input_line_pointer
+= 2;
13015 while (ISXDIGIT (*input_line_pointer
))
13018 val
|= hex_value (*input_line_pointer
++);
13020 return negative
? -val
: val
;
13024 ++input_line_pointer
;
13025 while (ISDIGIT (*input_line_pointer
))
13028 val
|= *input_line_pointer
++ - '0';
13030 return negative
? -val
: val
;
13033 if (!ISDIGIT (*input_line_pointer
))
13035 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13036 *input_line_pointer
, *input_line_pointer
);
13037 as_warn (_("invalid number"));
13040 while (ISDIGIT (*input_line_pointer
))
13043 val
+= *input_line_pointer
++ - '0';
13045 return negative
? -val
: val
;
13048 /* The .file directive; just like the usual .file directive, but there
13049 is an initial number which is the ECOFF file index. */
13053 int x ATTRIBUTE_UNUSED
;
13059 /* The .end directive. */
13063 int x ATTRIBUTE_UNUSED
;
13068 /* Following functions need their own .frame and .cprestore directives. */
13069 mips_frame_reg_valid
= 0;
13070 mips_cprestore_valid
= 0;
13072 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13075 demand_empty_rest_of_line ();
13080 #ifdef BFD_ASSEMBLER
13081 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13086 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
13093 as_warn (_(".end not in text section"));
13097 as_warn (_(".end directive without a preceding .ent directive."));
13098 demand_empty_rest_of_line ();
13104 assert (S_GET_NAME (p
));
13105 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
13106 as_warn (_(".end symbol does not match .ent symbol."));
13109 as_warn (_(".end directive missing or unknown symbol"));
13111 #ifdef MIPS_STABS_ELF
13113 segT saved_seg
= now_seg
;
13114 subsegT saved_subseg
= now_subseg
;
13119 dot
= frag_now_fix ();
13121 #ifdef md_flush_pending_output
13122 md_flush_pending_output ();
13126 subseg_set (pdr_seg
, 0);
13128 /* Write the symbol. */
13129 exp
.X_op
= O_symbol
;
13130 exp
.X_add_symbol
= p
;
13131 exp
.X_add_number
= 0;
13132 emit_expr (&exp
, 4);
13134 fragp
= frag_more (7 * 4);
13136 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
13137 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
13138 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
13139 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
13140 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
13141 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
13142 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
13144 subseg_set (saved_seg
, saved_subseg
);
13146 #endif /* MIPS_STABS_ELF */
13148 cur_proc_ptr
= NULL
;
13151 /* The .aent and .ent directives. */
13160 symbolP
= get_symbol ();
13161 if (*input_line_pointer
== ',')
13162 ++input_line_pointer
;
13163 SKIP_WHITESPACE ();
13164 if (ISDIGIT (*input_line_pointer
)
13165 || *input_line_pointer
== '-')
13168 #ifdef BFD_ASSEMBLER
13169 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13174 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
13181 as_warn (_(".ent or .aent not in text section."));
13183 if (!aent
&& cur_proc_ptr
)
13184 as_warn (_("missing .end"));
13188 /* This function needs its own .frame and .cprestore directives. */
13189 mips_frame_reg_valid
= 0;
13190 mips_cprestore_valid
= 0;
13192 cur_proc_ptr
= &cur_proc
;
13193 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13195 cur_proc_ptr
->isym
= symbolP
;
13197 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13202 demand_empty_rest_of_line ();
13205 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13206 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13207 s_mips_frame is used so that we can set the PDR information correctly.
13208 We can't use the ecoff routines because they make reference to the ecoff
13209 symbol table (in the mdebug section). */
13212 s_mips_frame (ignore
)
13213 int ignore ATTRIBUTE_UNUSED
;
13215 #ifdef MIPS_STABS_ELF
13219 if (cur_proc_ptr
== (procS
*) NULL
)
13221 as_warn (_(".frame outside of .ent"));
13222 demand_empty_rest_of_line ();
13226 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13228 SKIP_WHITESPACE ();
13229 if (*input_line_pointer
++ != ','
13230 || get_absolute_expression_and_terminator (&val
) != ',')
13232 as_warn (_("Bad .frame directive"));
13233 --input_line_pointer
;
13234 demand_empty_rest_of_line ();
13238 cur_proc_ptr
->frame_offset
= val
;
13239 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13241 demand_empty_rest_of_line ();
13244 #endif /* MIPS_STABS_ELF */
13247 /* The .fmask and .mask directives. If the mdebug section is present
13248 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13249 embedded targets, s_mips_mask is used so that we can set the PDR
13250 information correctly. We can't use the ecoff routines because they
13251 make reference to the ecoff symbol table (in the mdebug section). */
13254 s_mips_mask (reg_type
)
13257 #ifdef MIPS_STABS_ELF
13260 if (cur_proc_ptr
== (procS
*) NULL
)
13262 as_warn (_(".mask/.fmask outside of .ent"));
13263 demand_empty_rest_of_line ();
13267 if (get_absolute_expression_and_terminator (&mask
) != ',')
13269 as_warn (_("Bad .mask/.fmask directive"));
13270 --input_line_pointer
;
13271 demand_empty_rest_of_line ();
13275 off
= get_absolute_expression ();
13277 if (reg_type
== 'F')
13279 cur_proc_ptr
->fpreg_mask
= mask
;
13280 cur_proc_ptr
->fpreg_offset
= off
;
13284 cur_proc_ptr
->reg_mask
= mask
;
13285 cur_proc_ptr
->reg_offset
= off
;
13288 demand_empty_rest_of_line ();
13290 s_ignore (reg_type
);
13291 #endif /* MIPS_STABS_ELF */
13294 /* The .loc directive. */
13305 assert (now_seg
== text_section
);
13307 lineno
= get_number ();
13308 addroff
= frag_now_fix ();
13310 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
13311 S_SET_TYPE (symbolP
, N_SLINE
);
13312 S_SET_OTHER (symbolP
, 0);
13313 S_SET_DESC (symbolP
, lineno
);
13314 symbolP
->sy_segment
= now_seg
;
13318 /* CPU name/ISA/number mapping table.
13320 Entries are grouped by type. The first matching CPU or ISA entry
13321 gets chosen by CPU or ISA, so it should be the 'canonical' name
13322 for that type. Entries after that within the type are sorted
13325 Case is ignored in comparison, so put the canonical entry in the
13326 appropriate case but everything else in lower case to ease eye pain. */
13327 static const struct mips_cpu_info mips_cpu_info_table
[] =
13330 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
13331 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
13334 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
13337 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
13340 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
13343 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
13344 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
13347 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
13348 { "mipsisa32", 0, ISA_MIPS32
, CPU_MIPS32
, },
13349 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
13350 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
13351 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
, },
13352 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
, },
13354 /* For historical reasons. */
13355 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
, },
13358 { "mipsisa64", 1, ISA_MIPS64
, CPU_MIPS64
, },
13359 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
13360 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
13361 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
13364 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
13365 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
13366 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
13367 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
13370 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
13371 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
13372 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
13373 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
13376 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
13377 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
13378 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
13381 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
13382 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
13383 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
13384 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
13387 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
13388 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
13391 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
13392 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
13395 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
13396 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
13397 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
13398 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
13401 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
13402 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
13405 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
13406 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
13407 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
13408 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
13411 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
13412 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
13413 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
13414 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
13417 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
13418 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
13419 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
13420 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
13423 { "R12000", 0, ISA_MIPS4
, CPU_R12000
, },
13424 { "12000", 0, ISA_MIPS4
, CPU_R12000
, },
13425 { "12k", 0, ISA_MIPS4
, CPU_R12000
, },
13426 { "r12k", 0, ISA_MIPS4
, CPU_R12000
, },
13429 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13430 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13431 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13432 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13435 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
13436 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
13437 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
13438 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
13441 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
13442 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
13443 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
13444 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
13447 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
13448 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
13449 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
13450 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
13451 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
13452 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
13453 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
, },
13454 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
13455 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
, },
13456 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
13457 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
, },
13458 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
13459 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
, },
13460 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
13461 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
, },
13462 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
13463 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
13465 /* Broadcom SB-1 CPU */
13466 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
13467 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
13468 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
13469 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
13472 { NULL
, 0, 0, 0, },
13475 static const struct mips_cpu_info
*
13476 mips_cpu_info_from_name (name
)
13481 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13482 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
13483 return (&mips_cpu_info_table
[i
]);
13488 static const struct mips_cpu_info
*
13489 mips_cpu_info_from_isa (isa
)
13494 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13495 if (mips_cpu_info_table
[i
].is_isa
13496 && isa
== mips_cpu_info_table
[i
].isa
)
13497 return (&mips_cpu_info_table
[i
]);
13502 static const struct mips_cpu_info
*
13503 mips_cpu_info_from_cpu (cpu
)
13508 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13509 if (!mips_cpu_info_table
[i
].is_isa
13510 && cpu
== mips_cpu_info_table
[i
].cpu
)
13511 return (&mips_cpu_info_table
[i
]);