1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
55 /* Decide whether to do GP reference optimizations based on the object
65 /* These variables are filled in with the masks of registers used.
66 The object format code reads them and puts them in the appropriate
68 unsigned long mips_gprmask
;
69 unsigned long mips_cprmask
[4];
71 /* MIPS ISA (Instruction Set Architecture) level. */
72 static int mips_isa
= -1;
74 static int mips_warn_about_macros
;
75 static int mips_noreorder
;
76 static int mips_nomove
;
78 static int mips_nobopt
;
81 /* The size of the small data section. */
82 static int g_switch_value
= 8;
88 /* handle of the OPCODE hash table */
89 static struct hash_control
*op_hash
= NULL
;
91 /* This array holds the chars that always start a comment. If the
92 pre-processor is disabled, these aren't very useful */
93 const char comment_chars
[] = "#";
95 /* This array holds the chars that only start a comment at the beginning of
96 a line. If the line seems to have the form '# 123 filename'
97 .line and .file directives will appear in the pre-processed output */
98 /* Note that input_file.c hand checks for '#' at the beginning of the
99 first line of the input file. This is because the compiler outputs
100 #NO_APP at the beginning of its output. */
101 /* Also note that C style comments are always supported. */
102 const char line_comment_chars
[] = "#";
104 /* This array holds machine specific line separator characters. */
105 const char line_separator_chars
[] = "";
107 /* Chars that can be used to separate mant from exp in floating point nums */
108 const char EXP_CHARS
[] = "eE";
110 /* Chars that mean this number is a floating point constant */
113 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
115 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
116 changed in read.c . Ideally it shouldn't have to know about it at all,
117 but nothing is ideal around here.
120 static char *insn_error
;
122 static int byte_order
= BYTE_ORDER
;
124 static int auto_align
= 1;
126 /* Symbol labelling the current insn. */
127 static symbolS
*insn_label
;
129 /* To output NOP instructions correctly, we need to keep information
130 about the previous two instructions. */
132 /* Whether we are optimizing. The default value of 2 means to remove
133 unneeded NOPs and swap branch instructions when possible. A value
134 of 1 means to not swap branches. A value of 0 means to always
136 static int mips_optimize
= 2;
138 /* The previous instruction. */
139 static struct mips_cl_insn prev_insn
;
141 /* The instruction before prev_insn. */
142 static struct mips_cl_insn prev_prev_insn
;
144 /* If we don't want information for prev_insn or prev_prev_insn, we
145 point the insn_mo field at this dummy integer. */
146 static const struct mips_opcode dummy_opcode
= { 0 };
148 /* Non-zero if prev_insn is valid. */
149 static int prev_insn_valid
;
151 /* The frag for the previous instruction. */
152 static struct frag
*prev_insn_frag
;
154 /* The offset into prev_insn_frag for the previous instruction. */
155 static long prev_insn_where
;
157 /* The reloc for the previous instruction, if any. */
158 static fixS
*prev_insn_fixp
;
160 /* Non-zero if the previous instruction was in a delay slot. */
161 static int prev_insn_is_delay_slot
;
163 /* Non-zero if the previous instruction was in a .set noreorder. */
164 static int prev_insn_unreordered
;
166 /* Non-zero if the previous previous instruction was in a .set
168 static int prev_prev_insn_unreordered
;
170 /* Prototypes for static functions. */
173 #define internalError() \
174 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
176 #define internalError() as_fatal ("MIPS internal Error");
179 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
180 unsigned int reg
, int fpr
));
181 static void append_insn
PARAMS ((struct mips_cl_insn
* ip
,
183 bfd_reloc_code_real_type r
));
184 static void mips_no_prev_insn
PARAMS ((void));
185 static void mips_emit_delays
PARAMS ((void));
186 static int gp_reference
PARAMS ((expressionS
* ep
));
187 static void macro_build
PARAMS ((int *counter
, expressionS
* ep
,
188 const char *name
, const char *fmt
,
190 static void macro_build_lui
PARAMS ((int *counter
, expressionS
* ep
,
192 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
193 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
195 static void load_register
PARAMS ((int *counter
,
196 int reg
, expressionS
* ep
));
197 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
198 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
199 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
200 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
201 static symbolS
*get_symbol
PARAMS ((void));
202 static void mips_align
PARAMS ((int to
, int fill
));
203 static void s_align
PARAMS ((int));
204 static void s_stringer
PARAMS ((int));
205 static void s_change_sec
PARAMS ((int));
206 static void s_cons
PARAMS ((int));
207 static void s_err
PARAMS ((int));
208 static void s_extern
PARAMS ((int));
209 static void s_float_cons
PARAMS ((int));
210 static void s_option
PARAMS ((int));
211 static void s_mipsset
PARAMS ((int));
212 static void s_mips_space
PARAMS ((int));
214 static void md_obj_begin
PARAMS ((void));
215 static void md_obj_end
PARAMS ((void));
216 static long get_number
PARAMS ((void));
217 static void s_ent
PARAMS ((int));
218 static void s_mipsend
PARAMS ((int));
219 static void s_file
PARAMS ((int));
221 static void s_frame
PARAMS ((int));
222 static void s_loc
PARAMS ((int));
223 static void s_mask
PARAMS ((char));
229 The following pseudo-ops from the Kane and Heinrich MIPS book
230 should be defined here, but are currently unsupported: .alias,
231 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
233 The following pseudo-ops from the Kane and Heinrich MIPS book are
234 specific to the type of debugging information being generated, and
235 should be defined by the object format: .aent, .begin, .bend,
236 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
239 The following pseudo-ops from the Kane and Heinrich MIPS book are
240 not MIPS CPU specific, but are also not specific to the object file
241 format. This file is probably the best place to define them, but
242 they are not currently supported: .asm0, .endr, .lab, .repeat,
243 .struct, .weakext. */
245 const pseudo_typeS md_pseudo_table
[] =
247 /* MIPS specific pseudo-ops. */
248 {"option", s_option
, 0},
249 {"set", s_mipsset
, 0},
250 {"rdata", s_change_sec
, 'r'},
251 {"sdata", s_change_sec
, 's'},
252 {"livereg", s_ignore
, 0},
254 /* Relatively generic pseudo-ops that happen to be used on MIPS
256 {"asciiz", s_stringer
, 1},
257 {"bss", s_change_sec
, 'b'},
261 /* These pseudo-ops are defined in read.c, but must be overridden
262 here for one reason or another. */
263 {"align", s_align
, 0},
264 {"ascii", s_stringer
, 0},
265 {"asciz", s_stringer
, 1},
267 {"data", s_change_sec
, 'd'},
268 {"double", s_float_cons
, 'd'},
269 {"extern", s_extern
, 0},
270 {"float", s_float_cons
, 'f'},
271 {"space", s_mips_space
, 0},
272 {"text", s_change_sec
, 't'},
276 /* These pseudo-ops should be defined by the object file format.
277 However, ECOFF is the only format which currently defines them,
278 so we have versions here for a.out. */
280 {"end", s_mipsend
, 0},
283 {"fmask", s_ignore
, 'F'},
284 {"frame", s_ignore
, 0},
285 {"loc", s_ignore
, 0},
286 {"mask", s_ignore
, 'R'},
287 {"verstamp", s_ignore
, 0},
294 const relax_typeS md_relax_table
[] =
300 static char *expr_end
;
302 static expressionS imm_expr
;
303 static expressionS offset_expr
;
304 static bfd_reloc_code_real_type imm_reloc
;
305 static bfd_reloc_code_real_type offset_reloc
;
307 /* FIXME: This should be handled in a different way. */
308 extern int target_big_endian
;
311 * This function is called once, at assembler startup time. It should
312 * set up all the tables, etc. that the MD part of the assembler will need.
318 register const char *retval
= NULL
;
319 register unsigned int i
= 0;
323 if (strcmp (TARGET_CPU
, "mips") == 0)
325 else if (strcmp (TARGET_CPU
, "r6000") == 0
326 || strcmp (TARGET_CPU
, "mips2") == 0)
328 else if (strcmp (TARGET_CPU
, "mips64") == 0
329 || strcmp (TARGET_CPU
, "r4000") == 0
330 || strcmp (TARGET_CPU
, "mips3") == 0)
339 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
342 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
345 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
349 as_warn ("Could not set architecture and machine");
351 if ((op_hash
= hash_new ()) == NULL
)
353 as_fatal ("Virtual memory exhausted");
355 for (i
= 0; i
< NUMOPCODES
;)
357 const char *name
= mips_opcodes
[i
].name
;
359 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
362 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
363 mips_opcodes
[i
].name
, retval
);
364 as_fatal ("Broken assembler. No assembly attempted.");
368 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
369 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
370 != mips_opcodes
[i
].match
))
372 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
373 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
374 as_fatal ("Broken assembler. No assembly attempted.");
378 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
381 mips_no_prev_insn ();
389 /* set the default alignment for the text section (2**2) */
390 record_alignment (text_section
, 2);
392 /* FIXME: This should be handled in a different way. */
393 target_big_endian
= byte_order
== BIG_ENDIAN
;
396 bfd_set_gp_size (stdoutput
, g_switch_value
);
400 /* Create a .reginfo section for register masks. */
408 regsec
= subseg_new (".reginfo", (subsegT
) 0);
410 /* I don't know why this section should be loaded, but the ABI
411 says that SHF_ALLOC should be set. */
412 bfd_set_section_flags (stdoutput
, regsec
,
413 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
415 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
417 subseg_set (seg
, subseg
);
438 struct mips_cl_insn insn
;
440 imm_expr
.X_op
= O_absent
;
441 offset_expr
.X_op
= O_absent
;
443 mips_ip (str
, &insn
);
446 as_bad ("%s `%s'", insn_error
, str
);
449 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
455 if (imm_expr
.X_op
!= O_absent
)
456 append_insn (&insn
, &imm_expr
, imm_reloc
);
457 else if (offset_expr
.X_op
!= O_absent
)
458 append_insn (&insn
, &offset_expr
, offset_reloc
);
460 append_insn (&insn
, NULL
, BFD_RELOC_UNUSED
);
464 /* See whether instruction IP reads register REG. If FPR is non-zero,
465 REG is a floating point register. */
468 insn_uses_reg (ip
, reg
, fpr
)
469 struct mips_cl_insn
*ip
;
473 /* Don't report on general register 0, since it never changes. */
474 if (! fpr
&& reg
== 0)
479 /* If we are called with either $f0 or $f1, we must check $f0.
480 This is not optimal, because it will introduce an unnecessary
481 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
482 need to distinguish reading both $f0 and $f1 or just one of
483 them. Note that we don't have to check the other way,
484 because there is no instruction that sets both $f0 and $f1
485 and requires a delay. */
486 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
487 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
488 == (reg
&~ (unsigned) 1)))
490 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
491 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
492 == (reg
&~ (unsigned) 1)))
497 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
498 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
500 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
501 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
508 #define ALIGN_ERR "Attempt to assemble instruction onto non word boundary."
509 #define ALIGN_ERR2 "GAS doesn't do implicit alignment; use .align directive."
513 * Output an instruction.
516 append_insn (ip
, address_expr
, reloc_type
)
517 struct mips_cl_insn
*ip
;
518 expressionS
*address_expr
;
519 bfd_reloc_code_real_type reloc_type
;
521 register unsigned long prev_pinfo
, pinfo
;
526 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
527 pinfo
= ip
->insn_mo
->pinfo
;
529 if (! mips_noreorder
)
531 /* If the previous insn required any delay slots, see if we need
532 to insert a NOP or two. There are eight kinds of possible
533 hazards, of which an instruction can have at most one type.
534 (1) a load from memory delay
535 (2) a load from a coprocessor delay
536 (3) an unconditional branch delay
537 (4) a conditional branch delay
538 (5) a move to coprocessor register delay
539 (6) a load coprocessor register from memory delay
540 (7) a coprocessor condition code delay
541 (8) a HI/LO special register delay
543 There are a lot of optimizations we could do that we don't.
544 In particular, we do not, in general, reorder instructions.
545 If you use gcc with optimization, it will reorder
546 instructions and generally do much more optimization then we
547 do here; repeating all that work in the assembler would only
548 benefit hand written assembly code, and does not seem worth
551 /* This is how a NOP is emitted. */
552 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
554 /* The previous insn might require a delay slot, depending upon
555 the contents of the current insn. */
556 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
558 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
560 /* A load from a coprocessor or from memory. All load
561 delays delay the use of general register rt for one
562 instruction on the r3000. The r6000 and r4000 use
564 know (prev_pinfo
& INSN_WRITE_GPR_T
);
565 if (mips_optimize
== 0
566 || insn_uses_reg (ip
,
567 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
572 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
574 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
576 /* A generic coprocessor delay. The previous instruction
577 modified a coprocessor general or control register. If
578 it modified a control register, we need to avoid any
579 coprocessor instruction (this is probably not always
580 required, but it sometimes is). If it modified a general
581 register, we avoid using that register.
583 On the r6000 and r4000 loading a coprocessor register
584 from memory is interlocked, and does not require a delay.
586 This case is not handled very well. There is no special
587 knowledge of CP0 handling, and the coprocessors other
588 than the floating point unit are not distinguished at
590 if (prev_pinfo
& INSN_WRITE_FPR_T
)
592 if (mips_optimize
== 0
593 || insn_uses_reg (ip
,
594 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
599 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
601 if (mips_optimize
== 0
602 || insn_uses_reg (ip
,
603 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
610 /* We don't know exactly what the previous instruction
611 does. If the current instruction uses a coprocessor
612 register, we must insert a NOP. If previous
613 instruction may set the condition codes, and the
614 current instruction uses them, we must insert two
616 if (mips_optimize
== 0
617 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
618 && (pinfo
& INSN_READ_COND_CODE
)))
620 else if (pinfo
& INSN_COP
)
624 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
626 /* The previous instruction sets the coprocessor condition
627 codes, but does not require a general coprocessor delay
628 (this means it is a floating point comparison
629 instruction). If this instruction uses the condition
630 codes, we need to insert a single NOP. */
631 if (mips_optimize
== 0
632 || (pinfo
& INSN_READ_COND_CODE
))
635 else if (prev_pinfo
& INSN_READ_LO
)
637 /* The previous instruction reads the LO register; if the
638 current instruction writes to the LO register, we must
640 if (mips_optimize
== 0
641 || (pinfo
& INSN_WRITE_LO
))
644 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
646 /* The previous instruction reads the HI register; if the
647 current instruction writes to the HI register, we must
649 if (mips_optimize
== 0
650 || (pinfo
& INSN_WRITE_HI
))
654 /* There are two cases which require two intervening
655 instructions: 1) setting the condition codes using a move to
656 coprocessor instruction which requires a general coprocessor
657 delay and then reading the condition codes 2) reading the HI
658 or LO register and then writing to it. If we are not already
659 emitting a NOP instruction, we must check for these cases
660 compared to the instruction previous to the previous
663 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
664 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
665 && (pinfo
& INSN_READ_COND_CODE
))
666 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
667 && (pinfo
& INSN_WRITE_LO
))
668 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
669 && (pinfo
& INSN_WRITE_HI
))))
672 /* Now emit the right number of NOP instructions. */
678 if (insn_label
!= NULL
)
680 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
681 insn_label
->sy_frag
= frag_now
;
682 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
689 /* This is testing the address of the frag, not the alignment of
690 the instruction in the current section. */
698 if (address_expr
!= NULL
)
700 if (address_expr
->X_op
== O_constant
)
705 ip
->insn_opcode
|= address_expr
->X_add_number
;
709 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
712 case BFD_RELOC_MIPS_JMP
:
713 case BFD_RELOC_16_PCREL_S2
:
722 assert (reloc_type
!= BFD_RELOC_UNUSED
);
724 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
726 reloc_type
== BFD_RELOC_16_PCREL_S2
,
731 md_number_to_chars (f
, ip
->insn_opcode
, 4);
733 /* Update the register mask information. */
734 if (pinfo
& INSN_WRITE_GPR_D
)
735 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
736 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
737 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
738 if (pinfo
& INSN_READ_GPR_S
)
739 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
740 if (pinfo
& INSN_WRITE_GPR_31
)
741 mips_gprmask
|= 1 << 31;
742 if (pinfo
& INSN_WRITE_FPR_D
)
743 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
744 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
745 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
746 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
747 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
748 if (pinfo
& INSN_COP
)
750 /* We don't keep enough information to sort these cases out. */
752 /* Never set the bit for $0, which is always zero. */
753 mips_gprmask
&=~ 1 << 0;
755 if (! mips_noreorder
)
757 /* Filling the branch delay slot is more complex. We try to
758 switch the branch with the previous instruction, which we can
759 do if the previous instruction does not set up a condition
760 that the branch tests and if the branch is not itself the
761 target of any branch. */
762 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
763 || (pinfo
& INSN_COND_BRANCH_DELAY
))
765 if (mips_optimize
< 2
766 /* If we have seen .set nobopt, don't optimize. */
768 /* If we have seen .set volatile or .set nomove, don't
771 /* If we had to emit any NOP instructions, then we
772 already know we can not swap. */
774 /* If we don't even know the previous insn, we can not
777 /* If the previous insn is already in a branch delay
778 slot, then we can not swap. */
779 || prev_insn_is_delay_slot
780 /* If the previous previous insn was in a .set
781 noreorder, we can't swap. Actually, the MIPS
782 assembler will swap in this situation. However, gcc
783 configured -with-gnu-as will generate code like
789 in which we can not swap the bne and INSN. If gcc is
790 not configured -with-gnu-as, it does not output the
791 .set pseudo-ops. We don't have to check
792 prev_insn_unreordered, because prev_insn_valid will
793 be 0 in that case. We don't want to use
794 prev_prev_insn_valid, because we do want to be able
795 to swap at the start of a function. */
796 || prev_prev_insn_unreordered
797 /* If the branch is itself the target of a branch, we
798 can not swap. We cheat on this; all we check for is
799 whether there is a label on this instruction. If
800 there are any branches to anything other than a
801 label, users must use .set noreorder. */
802 || insn_label
!= NULL
803 /* If the branch reads the condition codes, we don't
804 even try to swap, because in the sequence
809 we can not swap, and I don't feel like handling that
811 || (pinfo
& INSN_READ_COND_CODE
)
812 /* We can not swap with an instruction that requires a
813 delay slot, becase the target of the branch might
814 interfere with that instruction. */
816 & (INSN_LOAD_COPROC_DELAY
817 | INSN_COPROC_MOVE_DELAY
818 | INSN_WRITE_COND_CODE
823 & (INSN_LOAD_MEMORY_DELAY
824 | INSN_COPROC_MEMORY_DELAY
)))
825 /* We can not swap with a branch instruction. */
827 & (INSN_UNCOND_BRANCH_DELAY
828 | INSN_COND_BRANCH_DELAY
829 | INSN_COND_BRANCH_LIKELY
))
830 /* We do not swap with a trap instruction, since it
831 complicates trap handlers to have the trap
832 instruction be in a delay slot. */
833 || (prev_pinfo
& INSN_TRAP
)
834 /* If the branch reads a register that the previous
835 instruction sets, we can not swap. */
836 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
837 && insn_uses_reg (ip
,
838 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
841 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
842 && insn_uses_reg (ip
,
843 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
846 /* If the branch writes a register that the previous
847 instruction sets, we can not swap (we know that
848 branches write only to RD or to $31). */
849 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
850 && (((pinfo
& INSN_WRITE_GPR_D
)
851 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
852 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
853 || ((pinfo
& INSN_WRITE_GPR_31
)
854 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
857 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
858 && (((pinfo
& INSN_WRITE_GPR_D
)
859 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
860 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
861 || ((pinfo
& INSN_WRITE_GPR_31
)
862 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
865 /* If the branch writes a register that the previous
866 instruction reads, we can not swap (we know that
867 branches only write to RD or to $31). */
868 || ((pinfo
& INSN_WRITE_GPR_D
)
869 && insn_uses_reg (&prev_insn
,
870 ((ip
->insn_opcode
>> OP_SH_RD
)
873 || ((pinfo
& INSN_WRITE_GPR_31
)
874 && insn_uses_reg (&prev_insn
, 31, 0))
875 /* If the previous previous instruction has a load
876 delay, and sets a register that the branch reads, we
878 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
880 && (prev_prev_insn
.insn_mo
->pinfo
881 & INSN_LOAD_MEMORY_DELAY
)))
882 && insn_uses_reg (ip
,
883 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
887 /* We could do even better for unconditional branches to
888 portions of this object file; we could pick up the
889 instruction at the destination, put it in the delay
890 slot, and bump the destination address. */
892 /* Update the previous insn information. */
893 prev_prev_insn
= *ip
;
894 prev_insn
.insn_mo
= &dummy_opcode
;
901 /* It looks like we can actually do the swap. */
902 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
903 memcpy (temp
, prev_f
, 4);
904 memcpy (prev_f
, f
, 4);
908 prev_insn_fixp
->fx_frag
= frag_now
;
909 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
913 fixp
->fx_frag
= prev_insn_frag
;
914 fixp
->fx_where
= prev_insn_where
;
916 /* Update the previous insn information; leave prev_insn
918 prev_prev_insn
= *ip
;
920 prev_insn_is_delay_slot
= 1;
922 /* If that was an unconditional branch, forget the previous
924 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
926 prev_prev_insn
.insn_mo
= &dummy_opcode
;
927 prev_insn
.insn_mo
= &dummy_opcode
;
930 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
932 /* We don't yet optimize a branch likely. What we should do
933 is look at the target, copy the instruction found there
934 into the delay slot, and increment the branch to jump to
935 the next instruction. */
937 /* Update the previous insn information. */
938 prev_prev_insn
= *ip
;
939 prev_insn
.insn_mo
= &dummy_opcode
;
943 /* Update the previous insn information. */
945 prev_prev_insn
.insn_mo
= &dummy_opcode
;
947 prev_prev_insn
= prev_insn
;
950 /* Any time we see a branch, we always fill the delay slot
951 immediately; since this insn is not a branch, we know it
952 is not in a delay slot. */
953 prev_insn_is_delay_slot
= 0;
956 prev_prev_insn_unreordered
= prev_insn_unreordered
;
957 prev_insn_unreordered
= 0;
958 prev_insn_frag
= frag_now
;
959 prev_insn_where
= f
- frag_now
->fr_literal
;
960 prev_insn_fixp
= fixp
;
964 /* We just output an insn, so the next one doesn't have a label. */
968 /* This function forgets that there was any previous instruction or
974 prev_insn
.insn_mo
= &dummy_opcode
;
975 prev_prev_insn
.insn_mo
= &dummy_opcode
;
977 prev_insn_is_delay_slot
= 0;
978 prev_insn_unreordered
= 0;
979 prev_prev_insn_unreordered
= 0;
983 /* This function must be called whenever we turn on noreorder or emit
984 something other than instructions. It inserts any NOPS which might
985 be needed by the previous instruction, and clears the information
986 kept for the previous instructions. */
991 if (! mips_noreorder
)
996 if ((prev_insn
.insn_mo
->pinfo
997 & (INSN_LOAD_COPROC_DELAY
998 | INSN_COPROC_MOVE_DELAY
999 | INSN_WRITE_COND_CODE
1003 && (prev_insn
.insn_mo
->pinfo
1004 & (INSN_LOAD_MEMORY_DELAY
1005 | INSN_COPROC_MEMORY_DELAY
))))
1008 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1009 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1010 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1013 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1014 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1015 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1020 if (insn_label
!= NULL
)
1022 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1023 insn_label
->sy_frag
= frag_now
;
1024 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1027 mips_no_prev_insn ();
1031 /* Return 1 if an expression can be accessed via the GP register. */
1039 const char *symname
;
1040 const char *segname
;
1042 sym
= ep
->X_add_symbol
;
1043 if (sym
== (symbolS
*) NULL
1044 || ep
->X_op_symbol
!= (symbolS
*) NULL
)
1047 /* Certain symbols can not be referenced off the GP, although it
1048 appears as though they can. */
1049 symname
= S_GET_NAME (sym
);
1050 if (symname
!= (const char *) NULL
1051 && (strcmp (symname
, "eprol") == 0
1052 || strcmp (symname
, "etext") == 0
1053 || strcmp (symname
, "_gp") == 0
1054 || strcmp (symname
, "edata") == 0
1055 || strcmp (symname
, "_fbss") == 0
1056 || strcmp (symname
, "_fdata") == 0
1057 || strcmp (symname
, "_ftext") == 0
1058 || strcmp (symname
, "end") == 0))
1060 if (! S_IS_DEFINED (sym
)
1061 && S_GET_VALUE (sym
) != 0
1062 && S_GET_VALUE (sym
) <= g_switch_value
)
1064 segname
= segment_name (S_GET_SEGMENT (ep
->X_add_symbol
));
1065 return (strcmp (segname
, ".sdata") == 0
1066 || strcmp (segname
, ".sbss") == 0
1067 || strcmp (segname
, ".lit8") == 0
1068 || strcmp (segname
, ".lit4") == 0);
1069 #else /* ! defined (GPOPT) */
1070 /* We are not optimizing for the GP register. */
1072 #endif /* ! defined (GPOPT) */
1075 /* Build an instruction created by a macro expansion. This is passed
1076 a pointer to the count of instructions created so far, an
1077 expression, the name of the instruction to build, an operand format
1078 string, and corresponding arguments. */
1082 macro_build (int *counter
,
1087 #else /* ! defined (NO_STDARG) */
1089 macro_build (counter
, ep
, name
, fmt
, va_alist
)
1095 #endif /* ! defined (NO_STDARG) */
1097 struct mips_cl_insn insn
;
1098 bfd_reloc_code_real_type r
;
1102 va_start (args
, fmt
);
1108 * If the macro is about to expand into a second instruction,
1109 * print a warning if needed. We need to pass ip as a parameter
1110 * to generate a better warning message here...
1112 if (mips_warn_about_macros
&& *counter
== 1)
1113 as_warn ("Macro instruction expanded into multiple instructions");
1115 *counter
+= 1; /* bump instruction counter */
1117 r
= BFD_RELOC_UNUSED
;
1118 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1119 assert (insn
.insn_mo
);
1120 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1122 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0)
1125 assert (insn
.insn_mo
->name
);
1126 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1128 assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
1129 insn
.insn_opcode
= insn
.insn_mo
->match
;
1145 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1151 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1156 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1161 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1168 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1172 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1176 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1183 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1193 assert (ep
!= NULL
&& ep
->X_op
== O_constant
);
1194 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1199 assert (ep
!= NULL
);
1201 * This allows macro() to pass an immediate expression for
1202 * creating short branches without creating a symbol.
1203 * Note that the expression still might come from the assembly
1204 * input, in which case the value is not checked for range nor
1205 * is a relocation entry generated (yuck).
1207 if (ep
->X_op
== O_constant
)
1209 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1213 r
= BFD_RELOC_16_PCREL_S2
;
1222 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1224 /* Use GP relative addressing if possible. */
1225 if (r
== BFD_RELOC_LO16
1226 && gp_reference (ep
))
1227 r
= BFD_RELOC_MIPS_GPREL
;
1229 append_insn (&insn
, ep
, r
);
1233 * Generate a "lui" instruction.
1236 macro_build_lui (counter
, ep
, regnum
)
1241 expressionS high_expr
;
1242 struct mips_cl_insn insn
;
1243 bfd_reloc_code_real_type r
;
1244 CONST
char *name
= "lui";
1245 CONST
char *fmt
= "t,u";
1249 if (high_expr
.X_op
== O_constant
)
1251 /* we can compute the instruction now without a relocation entry */
1252 if (high_expr
.X_add_number
& 0x8000)
1253 high_expr
.X_add_number
+= 0x10000;
1254 high_expr
.X_add_number
=
1255 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1256 r
= BFD_RELOC_UNUSED
;
1259 r
= BFD_RELOC_HI16_S
;
1262 * If the macro is about to expand into a second instruction,
1263 * print a warning if needed. We need to pass ip as a parameter
1264 * to generate a better warning message here...
1266 if (mips_warn_about_macros
&& *counter
== 1)
1267 as_warn ("Macro instruction expanded into multiple instructions");
1269 *counter
+= 1; /* bump instruction counter */
1271 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1272 assert (insn
.insn_mo
);
1273 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1274 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1276 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< 16);
1277 if (r
== BFD_RELOC_UNUSED
)
1279 insn
.insn_opcode
|= high_expr
.X_add_number
;
1280 append_insn (&insn
, NULL
, r
);
1283 append_insn (&insn
, &high_expr
, r
);
1287 * Generates code to set the $at register to true (one)
1288 * if reg is less than the immediate expression.
1291 set_at (counter
, reg
, unsignedp
)
1296 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1297 macro_build (counter
, &imm_expr
,
1298 unsignedp
? "sltiu" : "slti",
1302 load_register (counter
, AT
, &imm_expr
);
1303 macro_build (counter
, NULL
,
1304 unsignedp
? "sltu" : "slt",
1305 "d,v,t", AT
, reg
, AT
);
1309 /* Warn if an expression is not a constant. */
1312 check_absolute_expr (ip
, ex
)
1313 struct mips_cl_insn
*ip
;
1316 if (ex
->X_op
!= O_constant
)
1317 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1321 * This routine generates the least number of instructions neccessary to load
1322 * an absolute expression value into a register.
1325 load_register (counter
, reg
, ep
)
1330 assert (ep
->X_op
== O_constant
);
1331 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1332 macro_build (counter
, ep
,
1333 mips_isa
< 3 ? "addiu" : "daddiu",
1335 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1336 macro_build (counter
, ep
, "ori", "t,r,i", reg
, 0);
1337 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1338 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1339 == ~ (offsetT
) 0x7fffffff))
1341 macro_build (counter
, ep
, "lui", "t,u", reg
);
1342 if ((ep
->X_add_number
& 0xffff) != 0)
1343 macro_build (counter
, ep
, "ori", "t,r,i", reg
, reg
);
1345 else if (mips_isa
< 3)
1347 as_bad ("Number larger than 32 bits");
1348 macro_build (counter
, ep
, "addiu", "t,r,j", reg
, 0);
1353 expressionS hi32
, lo32
;
1357 hi32
.X_add_number
>>= shift
;
1358 hi32
.X_add_number
&= 0xffffffff;
1359 if ((hi32
.X_add_number
& 0x80000000) != 0)
1360 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1361 load_register (counter
, reg
, &hi32
);
1363 lo32
.X_add_number
&= 0xffffffff;
1364 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1365 macro_build (counter
, NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
1370 macro_build (counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
1372 mid16
.X_add_number
>>= 16;
1373 macro_build (counter
, &mid16
, "ori", "t,r,i", reg
, reg
);
1374 macro_build (counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
1376 if ((lo32
.X_add_number
& 0xffff) != 0)
1377 macro_build (counter
, &lo32
, "ori", "t,r,i", reg
, reg
);
1383 * This routine implements the seemingly endless macro or synthesized
1384 * instructions and addressing modes in the mips assembly language. Many
1385 * of these macros are simple and are similar to each other. These could
1386 * probably be handled by some kind of table or grammer aproach instead of
1387 * this verbose method. Others are not simple macros but are more like
1388 * optimizing code generation.
1389 * One interesting optimization is when several store macros appear
1390 * consecutivly that would load AT with the upper half of the same address.
1391 * The ensuing load upper instructions are ommited. This implies some kind
1392 * of global optimization. We currently only optimize within a single macro.
1393 * For many of the load and store macros if the address is specified as a
1394 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1395 * first load register 'at' with zero and use it as the base register. The
1396 * mips assembler simply uses register $zero. Just one tiny optimization
1401 struct mips_cl_insn
*ip
;
1403 register int treg
, sreg
, dreg
, breg
;
1417 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1418 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1419 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1420 mask
= ip
->insn_mo
->mask
;
1422 expr1
.X_op
= O_constant
;
1423 expr1
.X_op_symbol
= NULL
;
1424 expr1
.X_add_symbol
= NULL
;
1425 expr1
.X_add_number
= 1;
1437 mips_emit_delays ();
1440 expr1
.X_add_number
= 8;
1441 macro_build (&icnt
, &expr1
, "bgez", "s,p", sreg
);
1443 macro_build (&icnt
, NULL
, "nop", "", 0);
1445 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1446 macro_build (&icnt
, NULL
,
1447 dbl
? "dsub" : "sub",
1448 "d,v,t", dreg
, 0, sreg
);
1471 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1473 macro_build (&icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
);
1476 load_register (&icnt
, AT
, &imm_expr
);
1477 macro_build (&icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1496 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1498 if (mask
!= M_NOR_I
)
1499 macro_build (&icnt
, &imm_expr
, s
, "t,r,i", treg
, sreg
);
1502 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", treg
, sreg
);
1503 macro_build (&icnt
, &imm_expr
, "nor", "d,v,t", treg
, treg
, 0);
1508 load_register (&icnt
, AT
, &imm_expr
);
1509 macro_build (&icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1526 if (imm_expr
.X_add_number
== 0)
1528 macro_build (&icnt
, &offset_expr
, s
, "s,t,p", sreg
, 0);
1531 load_register (&icnt
, AT
, &imm_expr
);
1532 macro_build (&icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1540 macro_build (&icnt
, &offset_expr
,
1541 likely
? "bgezl" : "bgez",
1547 macro_build (&icnt
, &offset_expr
,
1548 likely
? "blezl" : "blez",
1552 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1553 macro_build (&icnt
, &offset_expr
,
1554 likely
? "beql" : "beq",
1561 /* check for > max integer */
1562 maxnum
= 0x7fffffff;
1570 if (imm_expr
.X_add_number
>= maxnum
)
1573 /* result is always false */
1576 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1577 macro_build (&icnt
, NULL
, "nop", "", 0);
1581 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1582 macro_build (&icnt
, &offset_expr
, "bnel", "s,t,p", 0, 0);
1586 imm_expr
.X_add_number
++;
1590 if (mask
== M_BGEL_I
)
1592 if (imm_expr
.X_add_number
== 0)
1594 macro_build (&icnt
, &offset_expr
,
1595 likely
? "bgezl" : "bgez",
1599 if (imm_expr
.X_add_number
== 1)
1601 macro_build (&icnt
, &offset_expr
,
1602 likely
? "bgtzl" : "bgtz",
1606 maxnum
= 0x7fffffff;
1614 maxnum
= - maxnum
- 1;
1615 if (imm_expr
.X_add_number
<= maxnum
)
1618 /* result is always true */
1619 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1620 macro_build (&icnt
, &offset_expr
, "b", "p");
1623 set_at (&icnt
, sreg
, 0);
1624 macro_build (&icnt
, &offset_expr
,
1625 likely
? "beql" : "beq",
1636 macro_build (&icnt
, &offset_expr
,
1637 likely
? "beql" : "beq",
1641 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1642 macro_build (&icnt
, &offset_expr
,
1643 likely
? "beql" : "beq",
1650 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1652 imm_expr
.X_add_number
++;
1656 if (mask
== M_BGEUL_I
)
1658 if (imm_expr
.X_add_number
== 0)
1660 if (imm_expr
.X_add_number
== 1)
1662 macro_build (&icnt
, &offset_expr
,
1663 likely
? "bnel" : "bne",
1667 set_at (&icnt
, sreg
, 1);
1668 macro_build (&icnt
, &offset_expr
,
1669 likely
? "beql" : "beq",
1678 macro_build (&icnt
, &offset_expr
,
1679 likely
? "bgtzl" : "bgtz",
1685 macro_build (&icnt
, &offset_expr
,
1686 likely
? "bltzl" : "bltz",
1690 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1691 macro_build (&icnt
, &offset_expr
,
1692 likely
? "bnel" : "bne",
1701 macro_build (&icnt
, &offset_expr
,
1702 likely
? "bnel" : "bne",
1708 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1709 macro_build (&icnt
, &offset_expr
,
1710 likely
? "bnel" : "bne",
1719 macro_build (&icnt
, &offset_expr
,
1720 likely
? "blezl" : "blez",
1726 macro_build (&icnt
, &offset_expr
,
1727 likely
? "bgezl" : "bgez",
1731 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1732 macro_build (&icnt
, &offset_expr
,
1733 likely
? "beql" : "beq",
1740 maxnum
= 0x7fffffff;
1748 if (imm_expr
.X_add_number
>= maxnum
)
1750 imm_expr
.X_add_number
++;
1754 if (mask
== M_BLTL_I
)
1756 if (imm_expr
.X_add_number
== 0)
1758 macro_build (&icnt
, &offset_expr
,
1759 likely
? "bltzl" : "bltz",
1763 if (imm_expr
.X_add_number
== 1)
1765 macro_build (&icnt
, &offset_expr
,
1766 likely
? "blezl" : "blez",
1770 set_at (&icnt
, sreg
, 0);
1771 macro_build (&icnt
, &offset_expr
,
1772 likely
? "bnel" : "bne",
1781 macro_build (&icnt
, &offset_expr
,
1782 likely
? "beql" : "beq",
1788 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1789 macro_build (&icnt
, &offset_expr
,
1790 likely
? "beql" : "beq",
1797 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1799 imm_expr
.X_add_number
++;
1803 if (mask
== M_BLTUL_I
)
1805 if (imm_expr
.X_add_number
== 0)
1807 if (imm_expr
.X_add_number
== 1)
1809 macro_build (&icnt
, &offset_expr
,
1810 likely
? "beql" : "beq",
1814 set_at (&icnt
, sreg
, 1);
1815 macro_build (&icnt
, &offset_expr
,
1816 likely
? "bnel" : "bne",
1825 macro_build (&icnt
, &offset_expr
,
1826 likely
? "bltzl" : "bltz",
1832 macro_build (&icnt
, &offset_expr
,
1833 likely
? "bgtzl" : "bgtz",
1837 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1838 macro_build (&icnt
, &offset_expr
,
1839 likely
? "bnel" : "bne",
1850 macro_build (&icnt
, &offset_expr
,
1851 likely
? "bnel" : "bne",
1855 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1856 macro_build (&icnt
, &offset_expr
,
1857 likely
? "bnel" : "bne",
1873 as_warn ("Divide by zero.");
1874 macro_build (&icnt
, NULL
, "break", "c", 7);
1878 mips_emit_delays ();
1880 macro_build (&icnt
, NULL
,
1881 dbl
? "ddiv" : "div",
1882 "z,s,t", sreg
, treg
);
1883 expr1
.X_add_number
= 8;
1884 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1885 macro_build (&icnt
, NULL
, "nop", "", 0);
1886 macro_build (&icnt
, NULL
, "break", "c", 7);
1887 expr1
.X_add_number
= -1;
1888 macro_build (&icnt
, &expr1
,
1889 dbl
? "daddiu" : "addiu",
1891 expr1
.X_add_number
= dbl
? 20 : 16;
1892 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
1895 expr1
.X_add_number
= 1;
1896 macro_build (&icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0);
1897 macro_build (&icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
1901 expr1
.X_add_number
= 0x80000000;
1902 macro_build (&icnt
, &expr1
, "lui", "t,u", AT
);
1904 expr1
.X_add_number
= 8;
1905 macro_build (&icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
1906 macro_build (&icnt
, NULL
, "nop", "", 0);
1907 macro_build (&icnt
, NULL
, "break", "c", 6);
1909 macro_build (&icnt
, NULL
, s
, "d", dreg
);
1948 if (imm_expr
.X_add_number
== 0)
1950 as_warn ("Divide by zero.");
1951 macro_build (&icnt
, NULL
, "break", "c", 7);
1954 if (imm_expr
.X_add_number
== 1)
1956 if (strcmp (s2
, "mflo") == 0)
1957 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
);
1959 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1962 if (imm_expr
.X_add_number
== -1
1963 && s
[strlen (s
) - 1] != 'u')
1965 if (strcmp (s2
, "mflo") == 0)
1968 macro_build (&icnt
, NULL
, "dneg", "d,w", dreg
, sreg
);
1970 macro_build (&icnt
, NULL
, "neg", "d,w", dreg
, sreg
);
1973 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1977 load_register (&icnt
, AT
, &imm_expr
);
1978 macro_build (&icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
1979 macro_build (&icnt
, NULL
, s2
, "d", dreg
);
1998 mips_emit_delays ();
2000 macro_build (&icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2001 expr1
.X_add_number
= 8;
2002 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2003 macro_build (&icnt
, NULL
, "nop", "", 0);
2004 macro_build (&icnt
, NULL
, "break", "c", 7);
2006 macro_build (&icnt
, NULL
, s2
, "d", dreg
);
2010 if (offset_expr
.X_op
== O_constant
)
2012 load_register (&icnt
, treg
, &offset_expr
);
2015 if (gp_reference (&offset_expr
))
2016 macro_build (&icnt
, &offset_expr
,
2017 mips_isa
< 3 ? "addiu" : "daddiu",
2021 /* FIXME: This won't work for a 64 bit address. */
2022 macro_build_lui (&icnt
, &offset_expr
, treg
);
2023 macro_build (&icnt
, &offset_expr
,
2024 mips_isa
< 3 ? "addiu" : "daddiu",
2025 "t,r,j", treg
, treg
);
2030 tempreg
= (breg
== treg
) ? AT
: treg
;
2031 if (offset_expr
.X_op
== O_constant
)
2032 load_register (&icnt
, tempreg
, &offset_expr
);
2033 else if (gp_reference (&offset_expr
))
2034 macro_build (&icnt
, &offset_expr
,
2035 mips_isa
< 3 ? "addiu" : "daddiu",
2036 "t,r,j", tempreg
, GP
);
2039 /* FIXME: This won't work for a 64 bit address. */
2040 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2041 macro_build (&icnt
, &offset_expr
,
2042 mips_isa
< 3 ? "addiu" : "daddiu",
2043 "t,r,j", tempreg
, tempreg
);
2046 macro_build (&icnt
, NULL
, "addu", "d,v,t", treg
, tempreg
, breg
);
2116 if (breg
== treg
|| coproc
)
2185 if (mask
== M_LWC1_AB
2186 || mask
== M_SWC1_AB
2188 || mask
== M_LDC1_AB
2189 || mask
== M_SDC1_AB
)
2195 if (gp_reference (&offset_expr
))
2199 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, GP
);
2202 macro_build (&icnt
, (expressionS
*) NULL
,
2203 mips_isa
< 3 ? "addu" : "daddu",
2204 "d,v,t", tempreg
, breg
, GP
);
2208 /* FIXME: This won't work for a 64 bit address. */
2209 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2211 macro_build (&icnt
, NULL
,
2212 mips_isa
< 3 ? "addu" : "daddu",
2213 "d,v,t", tempreg
, tempreg
, breg
);
2215 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, tempreg
);
2222 load_register (&icnt
, treg
, &imm_expr
);
2227 lw $v0,%lo(foo)($at)
2228 lw $v1,%lo(foo+4)($at)
2233 /* FIXME: This won't work for a 64 bit address. */
2234 macro_build_lui (&icnt
, &offset_expr
, AT
);
2236 macro_build (&icnt
, &offset_expr
, "ld", "t,o(b)", treg
, AT
);
2239 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
, AT
);
2240 offset_expr
.X_add_number
+= 4;
2241 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
+ 1, AT
);
2246 /* Load a floating point number from the .lit8 section. */
2249 macro_build (&icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
, GP
);
2255 /* Even on a big endian machine $fn comes before $fn+1. We have
2256 to adjust when loading from memory. */
2257 assert (mips_isa
< 2);
2258 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2259 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2261 offset_expr
.X_add_number
+= 4;
2262 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2263 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2269 * The MIPS assembler seems to check for X_add_number not
2270 * being double aligned and generating:
2273 * addiu at,at,%lo(foo+1)
2276 * But, the resulting address is the same after relocation so why
2277 * generate the extra instruction?
2279 if (gp_reference (&offset_expr
))
2285 macro_build (&icnt
, &offset_expr
,
2286 mips_isa
< 3 ? "addu" : "daddu",
2287 "d,v,t", AT
, breg
, GP
);
2293 /* FIXME: This won't work for a 64 bit address. */
2294 macro_build_lui (&icnt
, &offset_expr
, AT
);
2296 macro_build (&icnt
, NULL
,
2297 mips_isa
< 3 ? "addu" : "daddu",
2298 "d,v,t", AT
, AT
, breg
);
2302 macro_build (&icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
, tempreg
);
2305 /* Even on a big endian machine $fn comes before $fn+1. We
2306 have to adjust when loading from memory. */
2307 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2308 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2310 offset_expr
.X_add_number
+= 4;
2311 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2312 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2325 assert (mips_isa
< 3);
2326 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2327 offset_expr
.X_add_number
+= 4;
2328 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, breg
);
2351 if (gp_reference (&offset_expr
))
2359 macro_build (&icnt
, (expressionS
*) NULL
,
2360 mips_isa
< 3 ? "addu" : "daddu",
2361 "d,v,t", tempreg
, breg
, GP
);
2365 /* FIXME: This won't work for a 64 bit address. */
2366 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2368 macro_build (&icnt
, NULL
,
2369 mips_isa
< 3 ? "addu" : "daddu",
2370 "d,v,t", tempreg
, tempreg
, breg
);
2373 macro_build (&icnt
, &offset_expr
, s2
, "t,o(b)", treg
, tempreg
);
2376 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, tempreg
);
2377 offset_expr
.X_add_number
+= 4;
2378 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, tempreg
);
2387 macro_build (&icnt
, NULL
,
2388 dbl
? "dmultu" : "multu",
2390 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2396 /* The MIPS assembler some times generates shifts and adds. I'm
2397 not trying to be that fancy. GCC should do this for us
2399 load_register (&icnt
, AT
, &imm_expr
);
2400 macro_build (&icnt
, NULL
,
2401 dbl
? "dmult" : "mult",
2403 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2409 mips_emit_delays ();
2411 macro_build (&icnt
, NULL
,
2412 dbl
? "dmult" : "mult",
2414 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2415 macro_build (&icnt
, NULL
,
2416 dbl
? "dsra32" : "sra",
2417 "d,w,<", dreg
, dreg
, 31);
2418 macro_build (&icnt
, NULL
, "mfhi", "d", AT
);
2419 expr1
.X_add_number
= 8;
2420 macro_build (&icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
2421 macro_build (&icnt
, NULL
, "nop", "", 0);
2422 macro_build (&icnt
, NULL
, "break", "c", 6);
2424 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2430 mips_emit_delays ();
2432 macro_build (&icnt
, NULL
,
2433 dbl
? "dmultu" : "multu",
2435 macro_build (&icnt
, NULL
, "mfhi", "d", AT
);
2436 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2437 expr1
.X_add_number
= 8;
2438 macro_build (&icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
2439 macro_build (&icnt
, NULL
, "nop", "", 0);
2440 macro_build (&icnt
, NULL
, "break", "c", 6);
2445 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
2446 macro_build (&icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
2447 macro_build (&icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
2448 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2452 macro_build (&icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
2453 imm_expr
.X_add_number
& 0x1f);
2454 macro_build (&icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
2455 (0 - imm_expr
.X_add_number
) & 0x1f);
2456 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2460 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
2461 macro_build (&icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
2462 macro_build (&icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
2463 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2467 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
2468 imm_expr
.X_add_number
& 0x1f);
2469 macro_build (&icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
2470 (0 - imm_expr
.X_add_number
) & 0x1f);
2471 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2475 assert (mips_isa
< 2);
2476 /* Even on a big endian machine $fn comes before $fn+1. We have
2477 to adjust when storing to memory. */
2478 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2479 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2481 offset_expr
.X_add_number
+= 4;
2482 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2483 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2488 if (gp_reference (&offset_expr
))
2494 macro_build (&icnt
, (expressionS
*) NULL
,
2495 mips_isa
< 3 ? "addu" : "daddu",
2496 "d,v,t", AT
, breg
, GP
);
2502 /* FIXME: This won't work for a 64 bit address. */
2503 macro_build_lui (&icnt
, &offset_expr
, AT
);
2505 macro_build (&icnt
, NULL
,
2506 mips_isa
< 3 ? "addu" : "daddu",
2507 "d,v,t", AT
, AT
, breg
);
2511 macro_build (&icnt
, &offset_expr
, "sdc1", "T,o(b)", treg
, tempreg
);
2514 /* Even on a big endian machine $fn comes before $fn+1. We
2515 have to adjust when storing to memory. */
2516 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2517 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2519 offset_expr
.X_add_number
+= 4;
2520 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2521 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2530 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, treg
);
2532 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
2535 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2536 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2541 if (imm_expr
.X_add_number
== 0)
2543 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
2548 as_warn ("Instruction %s: result is always false",
2550 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
2553 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2555 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2558 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
2560 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2561 macro_build (&icnt
, &imm_expr
,
2562 mips_isa
< 3 ? "addiu" : "daddiu",
2563 "t,r,j", dreg
, sreg
);
2568 load_register (&icnt
, AT
, &imm_expr
);
2569 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2572 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2577 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
2583 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
2584 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2587 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
2589 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2591 macro_build (&icnt
, &expr1
,
2592 mask
== M_SGE_I
? "slti" : "sltiu",
2593 "t,r,j", dreg
, sreg
);
2598 load_register (&icnt
, AT
, &imm_expr
);
2599 macro_build (&icnt
, NULL
,
2600 mask
== M_SGE_I
? "slt" : "sltu",
2601 "d,v,t", dreg
, sreg
, AT
);
2604 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2609 case M_SGT
: /* sreg > treg <==> treg < sreg */
2615 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2618 case M_SGT_I
: /* sreg > I <==> I < sreg */
2624 load_register (&icnt
, AT
, &imm_expr
);
2625 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2628 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
2634 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2635 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2638 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
2644 load_register (&icnt
, AT
, &imm_expr
);
2645 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2646 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2650 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2652 macro_build (&icnt
, &imm_expr
, "slti", "t,r,j", dreg
, sreg
);
2655 load_register (&icnt
, AT
, &imm_expr
);
2656 macro_build (&icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
2660 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2662 macro_build (&icnt
, &imm_expr
, "sltiu", "t,r,j", dreg
, sreg
);
2665 load_register (&icnt
, AT
, &imm_expr
);
2666 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
2671 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
2673 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2676 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2677 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2682 if (imm_expr
.X_add_number
== 0)
2684 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2689 as_warn ("Instruction %s: result is always true",
2691 macro_build (&icnt
, &expr1
,
2692 mips_isa
< 3 ? "addiu" : "daddiu",
2696 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2698 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2701 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
2703 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2704 macro_build (&icnt
, &imm_expr
,
2705 mips_isa
< 3 ? "addiu" : "daddiu",
2706 "t,r,j", dreg
, sreg
);
2711 load_register (&icnt
, AT
, &imm_expr
);
2712 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2715 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2723 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
2725 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2726 macro_build (&icnt
, &imm_expr
,
2727 dbl
? "daddi" : "addi",
2728 "t,r,j", dreg
, sreg
);
2731 load_register (&icnt
, AT
, &imm_expr
);
2732 macro_build (&icnt
, NULL
,
2733 dbl
? "dsub" : "sub",
2734 "d,v,t", dreg
, sreg
, AT
);
2740 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
2742 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2743 macro_build (&icnt
, &imm_expr
,
2744 dbl
? "daddiu" : "addiu",
2745 "t,r,j", dreg
, sreg
);
2748 load_register (&icnt
, AT
, &imm_expr
);
2749 macro_build (&icnt
, NULL
,
2750 dbl
? "dsubu" : "subu",
2751 "d,v,t", dreg
, sreg
, AT
);
2772 load_register (&icnt
, AT
, &imm_expr
);
2773 macro_build (&icnt
, NULL
, s
, "s,t", sreg
, AT
);
2778 assert (mips_isa
< 2);
2779 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
2780 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
2783 * Is the double cfc1 instruction a bug in the mips assembler;
2784 * or is there a reason for it?
2786 mips_emit_delays ();
2788 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2789 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2790 macro_build (&icnt
, NULL
, "nop", "");
2791 expr1
.X_add_number
= 3;
2792 macro_build (&icnt
, &expr1
, "ori", "t,r,i", AT
, treg
);
2793 expr1
.X_add_number
= 2;
2794 macro_build (&icnt
, &expr1
, "xori", "t,r,i", AT
, AT
);
2795 macro_build (&icnt
, NULL
, "ctc1", "t,G", AT
, 31);
2796 macro_build (&icnt
, NULL
, "nop", "");
2797 macro_build (&icnt
, NULL
,
2798 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
2799 macro_build (&icnt
, NULL
, "ctc1", "t,G", treg
, 31);
2800 macro_build (&icnt
, NULL
, "nop", "");
2810 /* avoid load delay */
2811 offset_expr
.X_add_number
+= 1;
2812 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2813 offset_expr
.X_add_number
-= 1;
2814 macro_build (&icnt
, &offset_expr
, "lbu", "t,o(b)", AT
, breg
);
2815 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2816 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2820 /* does this work on a big endian machine? */
2821 offset_expr
.X_add_number
+= 3;
2822 macro_build (&icnt
, &offset_expr
, "lwl", "t,o(b)", treg
, breg
);
2823 offset_expr
.X_add_number
-= 3;
2824 macro_build (&icnt
, &offset_expr
, "lwr", "t,o(b)", treg
, breg
);
2830 if (offset_expr
.X_op
== O_constant
)
2831 load_register (&icnt
, AT
, &offset_expr
);
2832 else if (gp_reference (&offset_expr
))
2833 macro_build (&icnt
, &offset_expr
,
2834 mips_isa
< 3 ? "addiu" : "daddiu",
2838 /* FIXME: This won't work for a 64 bit address. */
2839 macro_build_lui (&icnt
, &offset_expr
, AT
);
2840 macro_build (&icnt
, &offset_expr
,
2841 mips_isa
< 3 ? "addiu" : "daddiu",
2844 if (mask
== M_ULW_A
)
2846 expr1
.X_add_number
= 3;
2847 macro_build (&icnt
, &expr1
, "lwl", "t,o(b)", treg
, AT
);
2848 imm_expr
.X_add_number
= 0;
2849 macro_build (&icnt
, &expr1
, "lwr", "t,o(b)", treg
, AT
);
2853 macro_build (&icnt
, &expr1
,
2854 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
, AT
);
2855 imm_expr
.X_add_number
= 0;
2856 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2857 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2858 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2863 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", treg
, breg
);
2864 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
2865 offset_expr
.X_add_number
+= 1;
2866 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", AT
, breg
);
2870 offset_expr
.X_add_number
+= 3;
2871 macro_build (&icnt
, &offset_expr
, "swl", "t,o(b)", treg
, breg
);
2872 offset_expr
.X_add_number
-= 3;
2873 macro_build (&icnt
, &offset_expr
, "swr", "t,o(b)", treg
, breg
);
2878 if (offset_expr
.X_op
== O_constant
)
2879 load_register (&icnt
, AT
, &offset_expr
);
2880 else if (gp_reference (&offset_expr
))
2881 macro_build (&icnt
, &offset_expr
,
2882 mips_isa
< 3 ? "addiu" : "daddiu",
2886 /* FIXME: This won't work for a 64 bit address. */
2887 macro_build_lui (&icnt
, &offset_expr
, AT
);
2888 macro_build (&icnt
, &offset_expr
,
2889 mips_isa
< 3 ? "addiu" : "daddiu",
2892 if (mask
== M_USW_A
)
2894 expr1
.X_add_number
= 3;
2895 macro_build (&icnt
, &expr1
, "swl", "t,o(b)", treg
, AT
);
2896 expr1
.X_add_number
= 0;
2897 macro_build (&icnt
, &expr1
, "swr", "t,o(b)", treg
, AT
);
2901 expr1
.X_add_number
= 0;
2902 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2903 macro_build (&icnt
, NULL
, "srl", "d,w,<", treg
, treg
, 8);
2904 expr1
.X_add_number
= 1;
2905 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2906 expr1
.X_add_number
= 0;
2907 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2908 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2909 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2914 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
2918 as_warn ("Macro used $at after \".set noat\"");
2923 This routine assembles an instruction into its binary format. As a side
2924 effect it sets one of the global variables imm_reloc or offset_reloc to the
2925 type of relocation to do if one of the operands is an address expression.
2930 struct mips_cl_insn
*ip
;
2935 struct mips_opcode
*insn
;
2938 unsigned int lastregno
= 0;
2943 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
2955 as_warn ("Unknown opcode: `%s'", str
);
2958 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
2960 as_warn ("`%s' not in hash table.", str
);
2961 insn_error
= "ERROR: Unrecognized opcode";
2969 assert (strcmp (insn
->name
, str
) == 0);
2971 if (insn
->pinfo
== INSN_MACRO
)
2972 insn_isa
= insn
->match
;
2973 else if (insn
->pinfo
& INSN_ISA2
)
2975 else if (insn
->pinfo
& INSN_ISA3
)
2980 if (insn_isa
> mips_isa
)
2982 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
2983 && strcmp (insn
->name
, insn
[1].name
) == 0)
2988 insn_error
= "ERROR: instruction not supported on this processor";
2993 ip
->insn_opcode
= insn
->match
;
2994 for (args
= insn
->args
;; ++args
)
3000 case '\0': /* end of args */
3013 ip
->insn_opcode
|= lastregno
<< 21;
3018 ip
->insn_opcode
|= lastregno
<< 16;
3022 ip
->insn_opcode
|= lastregno
<< 11;
3028 /* handle optional base register.
3029 Either the base register is omitted or
3030 we must have a left paren. */
3031 /* this is dependent on the next operand specifier
3032 is a 'b' for base register */
3033 assert (args
[1] == 'b');
3037 case ')': /* these must match exactly */
3042 case '<': /* must be at least one digit */
3044 * According to the manual, if the shift amount is greater
3045 * than 31 or less than 0 the the shift amount should be
3046 * mod 32. In reality the mips assembler issues an error.
3047 * We issue a warning and do the mod.
3049 my_getExpression (&imm_expr
, s
);
3050 check_absolute_expr (ip
, &imm_expr
);
3051 if ((unsigned long) imm_expr
.X_add_number
> 31)
3053 as_warn ("Improper shift amount (%ld)",
3054 (long) imm_expr
.X_add_number
);
3055 imm_expr
.X_add_number
= imm_expr
.X_add_number
% 32;
3057 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3058 imm_expr
.X_op
= O_absent
;
3062 case 'c': /* break code */
3063 my_getExpression (&imm_expr
, s
);
3064 check_absolute_expr (ip
, &imm_expr
);
3065 if ((unsigned) imm_expr
.X_add_number
> 1023)
3066 as_warn ("Illegal break code (%ld)",
3067 (long) imm_expr
.X_add_number
);
3068 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
3069 imm_expr
.X_op
= O_absent
;
3073 case 'B': /* syscall code */
3074 my_getExpression (&imm_expr
, s
);
3075 check_absolute_expr (ip
, &imm_expr
);
3076 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
3077 as_warn ("Illegal syscall code (%ld)",
3078 (long) imm_expr
.X_add_number
);
3079 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3080 imm_expr
.X_op
= O_absent
;
3084 case 'C': /* Coprocessor code */
3085 my_getExpression (&imm_expr
, s
);
3086 check_absolute_expr (ip
, &imm_expr
);
3087 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
3089 as_warn ("Coproccesor code > 25 bits (%ld)",
3090 (long) imm_expr
.X_add_number
);
3091 imm_expr
.X_add_number
&= ((1<<25) - 1);
3093 ip
->insn_opcode
|= imm_expr
.X_add_number
;
3094 imm_expr
.X_op
= O_absent
;
3098 case 'b': /* base register */
3099 case 'd': /* destination register */
3100 case 's': /* source register */
3101 case 't': /* target register */
3102 case 'r': /* both target and source */
3103 case 'v': /* both dest and source */
3104 case 'w': /* both dest and target */
3105 case 'E': /* coprocessor target register */
3106 case 'G': /* coprocessor destination register */
3107 case 'x': /* ignore register name */
3108 case 'z': /* must be zero register */
3122 while (isdigit (*s
));
3124 as_bad ("Invalid register number (%d)", regno
);
3126 else if (*args
!= 'E' && *args
!= 'G')
3128 if (s
[1] == 'f' && s
[2] == 'p')
3133 else if (s
[1] == 's' && s
[2] == 'p')
3138 else if (s
[1] == 'g' && s
[2] == 'p')
3143 else if (s
[1] == 'a' && s
[2] == 't')
3150 if (regno
== AT
&& ! mips_noat
)
3151 as_warn ("Used $at without \".set noat\"");
3158 if (c
== 'r' || c
== 'v' || c
== 'w')
3165 /* 'z' only matches $0. */
3166 if (c
== 'z' && regno
!= 0)
3174 ip
->insn_opcode
|= regno
<< 21;
3178 ip
->insn_opcode
|= regno
<< 11;
3183 ip
->insn_opcode
|= regno
<< 16;
3186 /* This case exists because on the r3000 trunc
3187 expands into a macro which requires a gp
3188 register. On the r6000 or r4000 it is
3189 assembled into a single instruction which
3190 ignores the register. Thus the insn version
3191 is MIPS_ISA2 and uses 'x', and the macro
3192 version is MIPS_ISA1 and uses 't'. */
3195 /* This case is for the div instruction, which
3196 acts differently if the destination argument
3197 is $0. This only matches $0, and is checked
3198 outside the switch. */
3209 ip
->insn_opcode
|= lastregno
<< 21;
3212 ip
->insn_opcode
|= lastregno
<< 16;
3217 case 'D': /* floating point destination register */
3218 case 'S': /* floating point source register */
3219 case 'T': /* floating point target register */
3223 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
3233 while (isdigit (*s
));
3236 as_bad ("Invalid float register number (%d)", regno
);
3239 !(strcmp (str
, "mtc1") == 0 ||
3240 strcmp (str
, "mfc1") == 0 ||
3241 strcmp (str
, "lwc1") == 0 ||
3242 strcmp (str
, "swc1") == 0))
3243 as_warn ("Float register should be even, was %d",
3251 if (c
== 'V' || c
== 'W')
3261 ip
->insn_opcode
|= regno
<< 6;
3265 ip
->insn_opcode
|= regno
<< 11;
3269 ip
->insn_opcode
|= regno
<< 16;
3277 ip
->insn_opcode
|= lastregno
<< 11;
3280 ip
->insn_opcode
|= lastregno
<< 16;
3286 my_getExpression (&imm_expr
, s
);
3287 check_absolute_expr (ip
, &imm_expr
);
3292 my_getExpression (&offset_expr
, s
);
3293 imm_reloc
= BFD_RELOC_32
;
3305 unsigned char temp
[8];
3307 unsigned int length
;
3312 /* These only appear as the last operand in an
3313 instruction, and every instruction that accepts
3314 them in any variant accepts them in all variants.
3315 This means we don't have to worry about backing out
3316 any changes if the instruction does not match.
3318 The difference between them is the size of the
3319 floating point constant and where it goes. For 'F'
3320 and 'L' the constant is 64 bits; for 'f' and 'l' it
3321 is 32 bits. Where the constant is placed is based
3322 on how the MIPS assembler does things:
3325 f -- immediate value
3329 f64
= *args
== 'F' || *args
== 'L';
3331 save_in
= input_line_pointer
;
3332 input_line_pointer
= s
;
3333 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
3335 s
= input_line_pointer
;
3336 input_line_pointer
= save_in
;
3337 if (err
!= NULL
&& *err
!= '\0')
3339 as_bad ("Bad floating point constant: %s", err
);
3340 memset (temp
, '\0', sizeof temp
);
3341 length
= f64
? 8 : 4;
3344 assert (length
== (f64
? 8 : 4));
3348 imm_expr
.X_op
= O_constant
;
3349 if (byte_order
== LITTLE_ENDIAN
)
3350 imm_expr
.X_add_number
=
3351 (((((((int) temp
[3] << 8)
3356 imm_expr
.X_add_number
=
3357 (((((((int) temp
[0] << 8)
3364 /* Switch to the right section. */
3366 subseg
= now_subseg
;
3370 subseg_new (".rdata", (subsegT
) 0);
3373 subseg_new (".lit8", (subsegT
) 0);
3376 subseg_new (".lit4", (subsegT
) 0);
3380 as_bad ("Can't use floating point insn in this section");
3382 /* Set the argument to the current address in the
3384 offset_expr
.X_op
= O_symbol
;
3385 offset_expr
.X_add_symbol
=
3386 symbol_new ("L0\001", now_seg
,
3387 (valueT
) frag_now_fix (), frag_now
);
3388 offset_expr
.X_add_number
= 0;
3390 /* Put the floating point number into the section. */
3391 p
= frag_more ((int) length
);
3392 memcpy (p
, temp
, length
);
3394 /* Switch back to the original section. */
3395 subseg_set (seg
, subseg
);
3400 case 'i': /* 16 bit unsigned immediate */
3401 case 'j': /* 16 bit signed immediate */
3402 imm_reloc
= BFD_RELOC_LO16
;
3403 c
= my_getSmallExpression (&imm_expr
, s
);
3408 if (imm_expr
.X_op
== O_constant
)
3409 imm_expr
.X_add_number
=
3410 (imm_expr
.X_add_number
>> 16) & 0xffff;
3412 imm_reloc
= BFD_RELOC_HI16_S
;
3414 imm_reloc
= BFD_RELOC_HI16
;
3418 check_absolute_expr (ip
, &imm_expr
);
3421 if (imm_expr
.X_add_number
< 0
3422 || imm_expr
.X_add_number
>= 0x10000)
3424 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3425 !strcmp (insn
->name
, insn
[1].name
))
3427 as_bad ("16 bit expression not in range 0..65535");
3432 if (imm_expr
.X_add_number
< -0x8000 ||
3433 imm_expr
.X_add_number
>= 0x8000)
3435 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3436 !strcmp (insn
->name
, insn
[1].name
))
3438 as_bad ("16 bit expression not in range -32768..32767");
3444 case 'o': /* 16 bit offset */
3445 c
= my_getSmallExpression (&offset_expr
, s
);
3447 * If this value won't fit into a 16 bit offset, then
3448 * go find a macro that will generate the 32 bit offset
3451 if (offset_expr
.X_op
!= O_constant
3452 || offset_expr
.X_add_number
>= 0x8000
3453 || offset_expr
.X_add_number
< -0x8000)
3456 offset_reloc
= BFD_RELOC_LO16
;
3457 if (c
== 'h' || c
== 'H')
3459 assert (offset_expr
.X_op
== O_constant
);
3460 offset_expr
.X_add_number
=
3461 (offset_expr
.X_add_number
>> 16) & 0xffff;
3466 case 'p': /* pc relative offset */
3467 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
3468 my_getExpression (&offset_expr
, s
);
3472 case 'u': /* upper 16 bits */
3473 c
= my_getSmallExpression (&imm_expr
, s
);
3474 if (imm_expr
.X_op
!= O_constant
3475 || imm_expr
.X_add_number
< 0
3476 || imm_expr
.X_add_number
>= 0x10000)
3477 as_bad ("lui expression not in range 0..65535");
3478 imm_reloc
= BFD_RELOC_LO16
;
3483 if (imm_expr
.X_op
== O_constant
)
3484 imm_expr
.X_add_number
=
3485 (imm_expr
.X_add_number
>> 16) & 0xffff;
3487 imm_reloc
= BFD_RELOC_HI16_S
;
3489 imm_reloc
= BFD_RELOC_HI16
;
3495 case 'a': /* 26 bit address */
3496 my_getExpression (&offset_expr
, s
);
3498 offset_reloc
= BFD_RELOC_MIPS_JMP
;
3502 fprintf (stderr
, "bad char = '%c'\n", *args
);
3507 /* Args don't match. */
3508 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3509 !strcmp (insn
->name
, insn
[1].name
))
3515 insn_error
= "ERROR: Illegal operands";
3524 my_getSmallExpression (ep
, str
)
3535 ((str
[1] == 'h' && str
[2] == 'i')
3536 || (str
[1] == 'H' && str
[2] == 'I')
3537 || (str
[1] == 'l' && str
[2] == 'o'))
3549 * A small expression may be followed by a base register.
3550 * Scan to the end of this operand, and then back over a possible
3551 * base register. Then scan the small expression up to that
3552 * point. (Based on code in sparc.c...)
3554 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
3556 if (sp
- 4 >= str
&& sp
[-1] == RP
)
3558 if (isdigit (sp
[-2]))
3560 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
3562 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
3568 else if (sp
- 5 >= str
3571 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
3572 || (sp
[-3] == 's' && sp
[-2] == 'p')
3573 || (sp
[-3] == 'g' && sp
[-2] == 'p')
3574 || (sp
[-3] == 'a' && sp
[-2] == 't')))
3580 /* no expression means zero offset */
3583 /* %xx(reg) is an error */
3584 ep
->X_op
= O_absent
;
3589 ep
->X_op
= O_absent
;
3592 ep
->X_add_symbol
= NULL
;
3593 ep
->X_op_symbol
= NULL
;
3594 ep
->X_add_number
= 0;
3599 my_getExpression (ep
, str
);
3606 my_getExpression (ep
, str
);
3607 return c
; /* => %hi or %lo encountered */
3611 my_getExpression (ep
, str
)
3617 save_in
= input_line_pointer
;
3618 input_line_pointer
= str
;
3620 expr_end
= input_line_pointer
;
3621 input_line_pointer
= save_in
;
3624 /* Turn a string in input_line_pointer into a floating point constant
3625 of type type, and store the appropriate bytes in *litP. The number
3626 of LITTLENUMS emitted is stored in *sizeP . An error message is
3627 returned, or NULL on OK. */
3630 md_atof (type
, litP
, sizeP
)
3636 LITTLENUM_TYPE words
[4];
3652 return "bad call to md_atof";
3655 t
= atof_ieee (input_line_pointer
, type
, words
);
3657 input_line_pointer
= t
;
3661 if (byte_order
== LITTLE_ENDIAN
)
3663 for (i
= prec
- 1; i
>= 0; i
--)
3665 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
3671 for (i
= 0; i
< prec
; i
++)
3673 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
3682 md_number_to_chars (buf
, val
, n
)
3730 md_number_to_chars (buf
, hi
, 4);
3755 md_parse_option (argP
, cntP
, vecP
)
3760 /* Accept -nocpp but ignore it. */
3761 if (strcmp (*argP
, "nocpp") == 0)
3767 if (strcmp (*argP
, "EL") == 0
3768 || strcmp (*argP
, "EB") == 0)
3770 /* FIXME: This breaks -L -EL. */
3778 if ((*argP
)[1] == '0')
3787 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
3792 if (strncmp (*argP
, "mips", 4) == 0)
3794 mips_isa
= atol (*argP
+ 4);
3797 else if (mips_isa
< 1 || mips_isa
> 3)
3799 as_bad ("-mips%d not supported", mips_isa
);
3806 if (strncmp (*argP
, "mcpu=", 5) == 0)
3810 /* Identify the processor type */
3812 if (strcmp (p
, "default") == 0
3813 || strcmp (p
, "DEFAULT") == 0)
3817 if (*p
== 'r' || *p
== 'R')
3824 if (strcmp (p
, "2000") == 0
3825 || strcmp (p
, "2k") == 0
3826 || strcmp (p
, "2K") == 0)
3831 if (strcmp (p
, "3000") == 0
3832 || strcmp (p
, "3k") == 0
3833 || strcmp (p
, "3K") == 0)
3838 if (strcmp (p
, "4000") == 0
3839 || strcmp (p
, "4k") == 0
3840 || strcmp (p
, "4K") == 0)
3845 if (strcmp (p
, "6000") == 0
3846 || strcmp (p
, "6k") == 0
3847 || strcmp (p
, "6K") == 0)
3854 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
3867 if ((*argP
)[1] != '\0')
3868 g_switch_value
= atoi (*argP
+ 1);
3871 **vecP
= (char *) NULL
;
3874 g_switch_value
= atoi (**vecP
);
3877 as_warn ("Number expected after -G");
3883 return 1; /* pretend you parsed the character */
3887 md_pcrel_from (fixP
)
3890 /* return the address of the delay slot */
3891 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3894 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3895 reloc for a cons. We could use the definition there, except that
3896 we want to handle 64 bit relocs specially. */
3899 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
3902 unsigned int nbytes
;
3905 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
3907 FIXME: There is no way to select anything but 32 bit mode right
3911 if (byte_order
== BIG_ENDIAN
)
3916 if (nbytes
!= 2 && nbytes
!= 4)
3917 as_bad ("Unsupported reloc size %d", nbytes
);
3919 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
3920 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
3924 md_apply_fix (fixP
, valueP
)
3931 assert (fixP
->fx_size
== 4);
3934 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
3936 switch (fixP
->fx_r_type
)
3939 case BFD_RELOC_MIPS_JMP
:
3940 case BFD_RELOC_HI16
:
3941 case BFD_RELOC_HI16_S
:
3942 case BFD_RELOC_LO16
:
3943 case BFD_RELOC_MIPS_GPREL
:
3944 /* Nothing needed to do. The value comes from the reloc entry */
3947 case BFD_RELOC_16_PCREL_S2
:
3949 * We need to save the bits in the instruction since fixup_segment()
3950 * might be deleting the relocation entry (i.e., a branch within
3951 * the current segment).
3954 as_warn ("Branch to odd address (%lx)", value
);
3956 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
3957 as_bad ("Relocation overflow");
3959 /* update old instruction data */
3960 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
3964 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
3968 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
3975 insn
|= value
& 0xFFFF;
3976 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
3990 const struct mips_opcode
*p
;
3991 int treg
, sreg
, dreg
, shamt
;
3996 for (i
= 0; i
< NUMOPCODES
; ++i
)
3998 p
= &mips_opcodes
[i
];
3999 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
4001 printf ("%08lx %s\t", oc
, p
->name
);
4002 treg
= (oc
>> 16) & 0x1f;
4003 sreg
= (oc
>> 21) & 0x1f;
4004 dreg
= (oc
>> 11) & 0x1f;
4005 shamt
= (oc
>> 6) & 0x1f;
4007 for (args
= p
->args
;; ++args
)
4018 printf ("%c", *args
);
4022 assert (treg
== sreg
);
4023 printf ("$%d,$%d", treg
, sreg
);
4028 printf ("$%d", dreg
);
4033 printf ("$%d", treg
);
4038 printf ("$%d", sreg
);
4042 printf ("0x%08lx", oc
& 0x1ffffff);
4053 printf ("$%d", shamt
);
4064 printf ("%08lx UNDEFINED\n", oc
);
4075 name
= input_line_pointer
;
4076 c
= get_symbol_end ();
4077 p
= (symbolS
*) symbol_find_or_make (name
);
4078 *input_line_pointer
= c
;
4082 /* Align the current frag to a given power of two. The MIPS assembler
4083 also automatically adjusts any preceding label. */
4086 mips_align (to
, fill
)
4090 mips_emit_delays ();
4091 frag_align (to
, fill
);
4092 record_alignment (now_seg
, to
);
4093 if (insn_label
!= NULL
)
4095 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
4096 insn_label
->sy_frag
= frag_now
;
4097 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
4102 /* Align to a given power of two. .align 0 turns off the automatic
4103 alignment used by the data creating pseudo-ops. */
4110 register long temp_fill
;
4111 long max_alignment
= 15;
4115 o Note that the assembler pulls down any immediately preceeding label
4116 to the aligned address.
4117 o It's not documented but auto alignment is reinstated by
4118 a .align pseudo instruction.
4119 o Note also that after auto alignment is turned off the mips assembler
4120 issues an error on attempt to assemble an improperly aligned data item.
4125 temp
= get_absolute_expression ();
4126 if (temp
> max_alignment
)
4127 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
4130 as_warn ("Alignment negative: 0 assumed.");
4133 if (*input_line_pointer
== ',')
4135 input_line_pointer
++;
4136 temp_fill
= get_absolute_expression ();
4143 mips_align (temp
, (int) temp_fill
);
4150 demand_empty_rest_of_line ();
4153 /* Handle .ascii and .asciiz. This just calls stringer and forgets
4154 that there was a previous instruction. */
4157 s_stringer (append_zero
)
4160 mips_emit_delays ();
4162 stringer (append_zero
);
4173 mips_emit_delays ();
4183 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
4184 demand_empty_rest_of_line ();
4189 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
4190 demand_empty_rest_of_line ();
4192 #else /* ! defined (OBJ_ECOFF) */
4194 seg
= subseg_new (".rodata", (subsegT
) get_absolute_expression ());
4195 bfd_set_section_flags (stdoutput
, seg
,
4201 demand_empty_rest_of_line ();
4203 #else /* ! defined (OBJ_ELF) */
4206 #endif /* ! defined (OBJ_ELF) */
4207 #endif /* ! defined (OBJ_ECOFF) */
4211 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
4213 bfd_set_section_flags (stdoutput
, seg
,
4214 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
4216 demand_empty_rest_of_line ();
4218 #else /* ! defined (GPOPT) */
4219 as_bad ("Global pointers not supported; recompile -G 0");
4220 demand_empty_rest_of_line ();
4222 #endif /* ! defined (GPOPT) */
4232 mips_emit_delays ();
4233 if (log_size
> 0 && auto_align
)
4234 mips_align (log_size
, 0);
4236 cons (1 << log_size
);
4243 as_fatal ("Encountered `.err', aborting assembly");
4253 symbolP
= get_symbol ();
4254 if (*input_line_pointer
== ',')
4255 input_line_pointer
++;
4256 size
= get_absolute_expression ();
4257 S_SET_VALUE (symbolP
, size
);
4258 S_SET_EXTERNAL (symbolP
);
4261 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
4262 so we use an additional ECOFF specific field. */
4263 symbolP
->ecoff_undefined
= 1;
4271 mips_emit_delays ();
4291 opt
= input_line_pointer
;
4292 c
= get_symbol_end ();
4294 /* FIXME: What do these options mean? */
4297 else if (strncmp (opt
, "pic", 3) == 0)
4300 as_warn ("Unrecognized option \"%s\"", opt
);
4302 *input_line_pointer
= c
;
4303 demand_empty_rest_of_line ();
4310 char *name
= input_line_pointer
, ch
;
4312 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4313 input_line_pointer
++;
4314 ch
= *input_line_pointer
;
4315 *input_line_pointer
= '\0';
4317 if (strcmp (name
, "reorder") == 0)
4321 prev_insn_unreordered
= 1;
4322 prev_prev_insn_unreordered
= 1;
4326 else if (strcmp (name
, "noreorder") == 0)
4328 mips_emit_delays ();
4331 else if (strcmp (name
, "at") == 0)
4335 else if (strcmp (name
, "noat") == 0)
4339 else if (strcmp (name
, "macro") == 0)
4341 mips_warn_about_macros
= 0;
4343 else if (strcmp (name
, "nomacro") == 0)
4345 if (mips_noreorder
== 0)
4346 as_bad ("`noreorder' must be set before `nomacro'");
4347 mips_warn_about_macros
= 1;
4349 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
4353 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
4357 else if (strcmp (name
, "bopt") == 0)
4361 else if (strcmp (name
, "nobopt") == 0)
4367 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
4369 *input_line_pointer
= ch
;
4370 demand_empty_rest_of_line ();
4373 /* The same as the usual .space directive, except that we have to
4374 forget about any previous instruction. */
4377 s_mips_space (param
)
4380 mips_emit_delays ();
4391 if (*input_line_pointer
++ != '$')
4393 as_warn ("expected `$'");
4396 if (isdigit ((unsigned char) *input_line_pointer
))
4398 reg
= get_absolute_expression ();
4399 if (reg
< 0 || reg
>= 32)
4401 as_warn ("Bad register number");
4407 if (strncmp (input_line_pointer
, "fp", 2) == 0)
4409 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
4411 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
4413 else if (strncmp (input_line_pointer
, "at", 2) == 0)
4417 as_warn ("Unrecognized register name");
4420 input_line_pointer
+= 2;
4426 * Translate internal representation of relocation info to BFD target format.
4429 tc_gen_reloc (section
, fixp
)
4435 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
4436 assert (reloc
!= 0);
4438 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
4439 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4440 if (fixp
->fx_pcrel
== 0)
4441 reloc
->addend
= fixp
->fx_addnumber
;
4446 reloc
->addend
= -reloc
->address
;
4448 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
4449 assert (reloc
->howto
!= 0);
4454 /* should never be called */
4456 md_section_align (seg
, addr
)
4460 int align
= bfd_get_section_alignment (stdoutput
, seg
);
4462 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
4466 md_estimate_size_before_relax (fragP
, segtype
)
4470 as_fatal ("md_estimate_size_before_relax");
4472 } /* md_estimate_size_before_relax() */
4474 /* This function is called whenever a label is defined. It is used
4475 when handling branch delays; if a branch has a label, we assume we
4479 mips_define_label (sym
)
4487 /* Write out the .reginfo section for a MIPS ELF file. */
4490 mips_elf_final_processing ()
4494 s
.ri_gprmask
= mips_gprmask
;
4495 s
.ri_cprmask
[0] = mips_cprmask
[0];
4496 s
.ri_cprmask
[1] = mips_cprmask
[1];
4497 s
.ri_cprmask
[2] = mips_cprmask
[2];
4498 s
.ri_cprmask
[3] = mips_cprmask
[3];
4499 /* The gp_value field is set by the MIPS ELF backend. */
4501 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
4502 ((Elf32_External_RegInfo
*)
4503 mips_regmask_frag
));
4506 #endif /* OBJ_ELF */
4510 /* These functions should really be defined by the object file format,
4511 since they are related to debugging information. However, this
4512 code has to work for the a.out format, which does not define them,
4513 so we provide simple versions here. These don't actually generate
4514 any debugging information, but they do simple checking and someday
4515 somebody may make them useful. */
4519 struct loc
*loc_next
;
4520 unsigned long loc_fileno
;
4521 unsigned long loc_lineno
;
4522 unsigned long loc_offset
;
4523 unsigned short loc_delta
;
4524 unsigned short loc_count
;
4533 struct proc
*proc_next
;
4534 struct symbol
*proc_isym
;
4535 struct symbol
*proc_end
;
4536 unsigned long proc_reg_mask
;
4537 unsigned long proc_reg_offset
;
4538 unsigned long proc_fpreg_mask
;
4539 unsigned long proc_fpreg_offset
;
4540 unsigned long proc_frameoffset
;
4541 unsigned long proc_framereg
;
4542 unsigned long proc_pcreg
;
4544 struct file
*proc_file
;
4551 struct file
*file_next
;
4552 unsigned long file_fileno
;
4553 struct symbol
*file_symbol
;
4554 struct symbol
*file_end
;
4555 struct proc
*file_proc
;
4560 static struct obstack proc_frags
;
4561 static procS
*proc_lastP
;
4562 static procS
*proc_rootP
;
4563 static int numprocs
;
4568 obstack_begin (&proc_frags
, 0x2000);
4574 /* check for premature end, nesting errors, etc */
4575 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
4576 as_warn ("missing `.end' at end of assembly");
4579 extern char hex_value
[];
4587 if (*input_line_pointer
== '-')
4589 ++input_line_pointer
;
4592 if (!isdigit (*input_line_pointer
))
4593 as_bad ("Expected simple number.");
4594 if (input_line_pointer
[0] == '0')
4596 if (input_line_pointer
[1] == 'x')
4598 input_line_pointer
+= 2;
4599 while (isxdigit (*input_line_pointer
))
4602 val
|= hex_value
[(int) *input_line_pointer
++];
4604 return negative
? -val
: val
;
4608 ++input_line_pointer
;
4609 while (isdigit (*input_line_pointer
))
4612 val
|= *input_line_pointer
++ - '0';
4614 return negative
? -val
: val
;
4617 if (!isdigit (*input_line_pointer
))
4619 printf (" *input_line_pointer == '%c' 0x%02x\n",
4620 *input_line_pointer
, *input_line_pointer
);
4621 as_warn ("Invalid number");
4624 while (isdigit (*input_line_pointer
))
4627 val
+= *input_line_pointer
++ - '0';
4629 return negative
? -val
: val
;
4632 /* The .file directive; just like the usual .file directive, but there
4633 is an initial number which is the ECOFF file index. */
4641 line
= get_number ();
4646 /* The .end directive. */
4654 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4657 demand_empty_rest_of_line ();
4661 if (now_seg
!= text_section
)
4662 as_warn (".end not in text section");
4665 as_warn (".end and no .ent seen yet.");
4671 assert (S_GET_NAME (p
));
4672 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
4673 as_warn (".end symbol does not match .ent symbol.");
4676 proc_lastP
->proc_end
= (symbolS
*) 1;
4679 /* The .aent and .ent directives. */
4689 symbolP
= get_symbol ();
4690 if (*input_line_pointer
== ',')
4691 input_line_pointer
++;
4693 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
4694 number
= get_number ();
4695 if (now_seg
!= text_section
)
4696 as_warn (".ent or .aent not in text section.");
4698 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
4699 as_warn ("missing `.end'");
4703 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
4704 procP
->proc_isym
= symbolP
;
4705 procP
->proc_reg_mask
= 0;
4706 procP
->proc_reg_offset
= 0;
4707 procP
->proc_fpreg_mask
= 0;
4708 procP
->proc_fpreg_offset
= 0;
4709 procP
->proc_frameoffset
= 0;
4710 procP
->proc_framereg
= 0;
4711 procP
->proc_pcreg
= 0;
4712 procP
->proc_end
= NULL
;
4713 procP
->proc_next
= NULL
;
4715 proc_lastP
->proc_next
= procP
;
4721 demand_empty_rest_of_line ();
4724 /* The .frame directive. */
4737 frame_reg
= tc_get_register ();
4738 if (*input_line_pointer
== ',')
4739 input_line_pointer
++;
4740 frame_off
= get_absolute_expression ();
4741 if (*input_line_pointer
== ',')
4742 input_line_pointer
++;
4743 pcreg
= tc_get_register ();
4746 assert (proc_rootP
);
4747 proc_rootP
->proc_framereg
= frame_reg
;
4748 proc_rootP
->proc_frameoffset
= frame_off
;
4749 proc_rootP
->proc_pcreg
= pcreg
;
4750 /* bob macho .frame */
4752 /* We don't have to write out a frame stab for unoptimized code. */
4753 if (!(frame_reg
== 30 && frame_off
== 0))
4756 as_warn ("No .ent for .frame to use.");
4757 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
4758 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
4759 S_SET_TYPE (symP
, N_RMASK
);
4760 S_SET_OTHER (symP
, 0);
4761 S_SET_DESC (symP
, 0);
4762 symP
->sy_forward
= proc_lastP
->proc_isym
;
4763 /* bob perhaps I should have used pseudo set */
4765 demand_empty_rest_of_line ();
4769 /* The .fmask and .mask directives. */
4776 char str
[100], *strP
;
4782 mask
= get_number ();
4783 if (*input_line_pointer
== ',')
4784 input_line_pointer
++;
4785 off
= get_absolute_expression ();
4787 /* bob only for coff */
4788 assert (proc_rootP
);
4789 if (reg_type
== 'F')
4791 proc_rootP
->proc_fpreg_mask
= mask
;
4792 proc_rootP
->proc_fpreg_offset
= off
;
4796 proc_rootP
->proc_reg_mask
= mask
;
4797 proc_rootP
->proc_reg_offset
= off
;
4800 /* bob macho .mask + .fmask */
4802 /* We don't have to write out a mask stab if no saved regs. */
4806 as_warn ("No .ent for .mask to use.");
4808 for (i
= 0; i
< 32; i
++)
4812 sprintf (strP
, "%c%d,", reg_type
, i
);
4813 strP
+= strlen (strP
);
4817 sprintf (strP
, ";%d,", off
);
4818 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
4819 S_SET_TYPE (symP
, N_RMASK
);
4820 S_SET_OTHER (symP
, 0);
4821 S_SET_DESC (symP
, 0);
4822 symP
->sy_forward
= proc_lastP
->proc_isym
;
4823 /* bob perhaps I should have used pseudo set */
4828 /* The .loc directive. */
4839 assert (now_seg
== text_section
);
4841 lineno
= get_number ();
4842 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
4844 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
4845 S_SET_TYPE (symbolP
, N_SLINE
);
4846 S_SET_OTHER (symbolP
, 0);
4847 S_SET_DESC (symbolP
, lineno
);
4848 symbolP
->sy_segment
= now_seg
;
4852 #endif /* ! defined (OBJ_ECOFF) */